Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 14
- Kernel Errors: 31
1 04:46:55.108393 lava-dispatcher, installed at version: 2023.10
2 04:46:55.108584 start: 0 validate
3 04:46:55.108708 Start time: 2024-02-04 04:46:55.108701+00:00 (UTC)
4 04:46:55.108825 Using caching service: 'http://localhost/cache/?uri=%s'
5 04:46:55.108954 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20231214.0%2Farm64%2Finitrd.cpio.gz exists
6 04:46:55.382908 Using caching service: 'http://localhost/cache/?uri=%s'
7 04:46:55.383657 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 04:46:55.645835 Using caching service: 'http://localhost/cache/?uri=%s'
9 04:46:55.646680 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 04:46:55.907171 Using caching service: 'http://localhost/cache/?uri=%s'
11 04:46:55.907917 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20231214.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 04:46:56.178125 Using caching service: 'http://localhost/cache/?uri=%s'
13 04:46:56.178946 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 04:46:56.455916 validate duration: 1.35
16 04:46:56.456173 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 04:46:56.456272 start: 1.1 download-retry (timeout 00:10:00) [common]
18 04:46:56.456361 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 04:46:56.456480 Not decompressing ramdisk as can be used compressed.
20 04:46:56.456564 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20231214.0/arm64/initrd.cpio.gz
21 04:46:56.456630 saving as /var/lib/lava/dispatcher/tmp/12699845/tftp-deploy-2p2y6t07/ramdisk/initrd.cpio.gz
22 04:46:56.456697 total size: 5628325 (5 MB)
23 04:46:56.457725 progress 0 % (0 MB)
24 04:46:56.459287 progress 5 % (0 MB)
25 04:46:56.460813 progress 10 % (0 MB)
26 04:46:56.462218 progress 15 % (0 MB)
27 04:46:56.463751 progress 20 % (1 MB)
28 04:46:56.465111 progress 25 % (1 MB)
29 04:46:56.466668 progress 30 % (1 MB)
30 04:46:56.468170 progress 35 % (1 MB)
31 04:46:56.469518 progress 40 % (2 MB)
32 04:46:56.471056 progress 45 % (2 MB)
33 04:46:56.472435 progress 50 % (2 MB)
34 04:46:56.473955 progress 55 % (2 MB)
35 04:46:56.475488 progress 60 % (3 MB)
36 04:46:56.476865 progress 65 % (3 MB)
37 04:46:56.478400 progress 70 % (3 MB)
38 04:46:56.479734 progress 75 % (4 MB)
39 04:46:56.481222 progress 80 % (4 MB)
40 04:46:56.482695 progress 85 % (4 MB)
41 04:46:56.484199 progress 90 % (4 MB)
42 04:46:56.485689 progress 95 % (5 MB)
43 04:46:56.487100 progress 100 % (5 MB)
44 04:46:56.487302 5 MB downloaded in 0.03 s (175.38 MB/s)
45 04:46:56.487449 end: 1.1.1 http-download (duration 00:00:00) [common]
47 04:46:56.487685 end: 1.1 download-retry (duration 00:00:00) [common]
48 04:46:56.487771 start: 1.2 download-retry (timeout 00:10:00) [common]
49 04:46:56.487855 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 04:46:56.487977 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 04:46:56.488048 saving as /var/lib/lava/dispatcher/tmp/12699845/tftp-deploy-2p2y6t07/kernel/Image
52 04:46:56.488110 total size: 51597824 (49 MB)
53 04:46:56.488171 No compression specified
54 04:46:56.489211 progress 0 % (0 MB)
55 04:46:56.502097 progress 5 % (2 MB)
56 04:46:56.514865 progress 10 % (4 MB)
57 04:46:56.527568 progress 15 % (7 MB)
58 04:46:56.540114 progress 20 % (9 MB)
59 04:46:56.552862 progress 25 % (12 MB)
60 04:46:56.565578 progress 30 % (14 MB)
61 04:46:56.578433 progress 35 % (17 MB)
62 04:46:56.591204 progress 40 % (19 MB)
63 04:46:56.604152 progress 45 % (22 MB)
64 04:46:56.617270 progress 50 % (24 MB)
65 04:46:56.630136 progress 55 % (27 MB)
66 04:46:56.642636 progress 60 % (29 MB)
67 04:46:56.655423 progress 65 % (32 MB)
68 04:46:56.668072 progress 70 % (34 MB)
69 04:46:56.680830 progress 75 % (36 MB)
70 04:46:56.693706 progress 80 % (39 MB)
71 04:46:56.706631 progress 85 % (41 MB)
72 04:46:56.719636 progress 90 % (44 MB)
73 04:46:56.732235 progress 95 % (46 MB)
74 04:46:56.744710 progress 100 % (49 MB)
75 04:46:56.744907 49 MB downloaded in 0.26 s (191.62 MB/s)
76 04:46:56.745058 end: 1.2.1 http-download (duration 00:00:00) [common]
78 04:46:56.745293 end: 1.2 download-retry (duration 00:00:00) [common]
79 04:46:56.745381 start: 1.3 download-retry (timeout 00:10:00) [common]
80 04:46:56.745468 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 04:46:56.745636 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 04:46:56.745711 saving as /var/lib/lava/dispatcher/tmp/12699845/tftp-deploy-2p2y6t07/dtb/mt8192-asurada-spherion-r0.dtb
83 04:46:56.745776 total size: 47278 (0 MB)
84 04:46:56.745839 No compression specified
85 04:46:56.746956 progress 69 % (0 MB)
86 04:46:56.747224 progress 100 % (0 MB)
87 04:46:56.747376 0 MB downloaded in 0.00 s (28.21 MB/s)
88 04:46:56.747499 end: 1.3.1 http-download (duration 00:00:00) [common]
90 04:46:56.747719 end: 1.3 download-retry (duration 00:00:00) [common]
91 04:46:56.747807 start: 1.4 download-retry (timeout 00:10:00) [common]
92 04:46:56.747889 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 04:46:56.747998 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20231214.0/arm64/full.rootfs.tar.xz
94 04:46:56.748066 saving as /var/lib/lava/dispatcher/tmp/12699845/tftp-deploy-2p2y6t07/nfsrootfs/full.rootfs.tar
95 04:46:56.748143 total size: 198084472 (188 MB)
96 04:46:56.748246 Using unxz to decompress xz
97 04:46:56.751801 progress 0 % (0 MB)
98 04:46:57.299574 progress 5 % (9 MB)
99 04:46:57.785977 progress 10 % (18 MB)
100 04:46:58.355210 progress 15 % (28 MB)
101 04:46:58.638575 progress 20 % (37 MB)
102 04:46:59.087093 progress 25 % (47 MB)
103 04:46:59.646296 progress 30 % (56 MB)
104 04:47:00.191664 progress 35 % (66 MB)
105 04:47:00.740848 progress 40 % (75 MB)
106 04:47:01.299676 progress 45 % (85 MB)
107 04:47:01.891995 progress 50 % (94 MB)
108 04:47:02.487245 progress 55 % (103 MB)
109 04:47:03.146319 progress 60 % (113 MB)
110 04:47:03.523283 progress 65 % (122 MB)
111 04:47:03.614329 progress 70 % (132 MB)
112 04:47:03.752777 progress 75 % (141 MB)
113 04:47:03.826827 progress 80 % (151 MB)
114 04:47:03.874597 progress 85 % (160 MB)
115 04:47:03.967426 progress 90 % (170 MB)
116 04:47:04.320586 progress 95 % (179 MB)
117 04:47:04.885378 progress 100 % (188 MB)
118 04:47:04.890147 188 MB downloaded in 8.14 s (23.20 MB/s)
119 04:47:04.890399 end: 1.4.1 http-download (duration 00:00:08) [common]
121 04:47:04.890697 end: 1.4 download-retry (duration 00:00:08) [common]
122 04:47:04.890799 start: 1.5 download-retry (timeout 00:09:52) [common]
123 04:47:04.890886 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 04:47:04.891086 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 04:47:04.891159 saving as /var/lib/lava/dispatcher/tmp/12699845/tftp-deploy-2p2y6t07/modules/modules.tar
126 04:47:04.891221 total size: 8633524 (8 MB)
127 04:47:04.891286 Using unxz to decompress xz
128 04:47:04.894844 progress 0 % (0 MB)
129 04:47:04.915938 progress 5 % (0 MB)
130 04:47:04.938760 progress 10 % (0 MB)
131 04:47:04.961625 progress 15 % (1 MB)
132 04:47:04.984285 progress 20 % (1 MB)
133 04:47:05.007710 progress 25 % (2 MB)
134 04:47:05.034046 progress 30 % (2 MB)
135 04:47:05.057372 progress 35 % (2 MB)
136 04:47:05.079970 progress 40 % (3 MB)
137 04:47:05.104127 progress 45 % (3 MB)
138 04:47:05.128528 progress 50 % (4 MB)
139 04:47:05.151659 progress 55 % (4 MB)
140 04:47:05.177155 progress 60 % (4 MB)
141 04:47:05.202056 progress 65 % (5 MB)
142 04:47:05.226232 progress 70 % (5 MB)
143 04:47:05.248713 progress 75 % (6 MB)
144 04:47:05.274653 progress 80 % (6 MB)
145 04:47:05.299666 progress 85 % (7 MB)
146 04:47:05.325674 progress 90 % (7 MB)
147 04:47:05.354654 progress 95 % (7 MB)
148 04:47:05.381117 progress 100 % (8 MB)
149 04:47:05.386525 8 MB downloaded in 0.50 s (16.62 MB/s)
150 04:47:05.386766 end: 1.5.1 http-download (duration 00:00:00) [common]
152 04:47:05.387025 end: 1.5 download-retry (duration 00:00:00) [common]
153 04:47:05.387117 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 04:47:05.387212 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 04:47:08.695927 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12699845/extract-nfsrootfs-6vzpzxd0
156 04:47:08.696135 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 04:47:08.696244 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 04:47:08.696409 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1
159 04:47:08.696536 makedir: /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/bin
160 04:47:08.696637 makedir: /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/tests
161 04:47:08.696734 makedir: /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/results
162 04:47:08.696836 Creating /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/bin/lava-add-keys
163 04:47:08.696977 Creating /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/bin/lava-add-sources
164 04:47:08.697102 Creating /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/bin/lava-background-process-start
165 04:47:08.697225 Creating /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/bin/lava-background-process-stop
166 04:47:08.697349 Creating /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/bin/lava-common-functions
167 04:47:08.697471 Creating /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/bin/lava-echo-ipv4
168 04:47:08.697591 Creating /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/bin/lava-install-packages
169 04:47:08.697711 Creating /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/bin/lava-installed-packages
170 04:47:08.697830 Creating /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/bin/lava-os-build
171 04:47:08.697952 Creating /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/bin/lava-probe-channel
172 04:47:08.698072 Creating /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/bin/lava-probe-ip
173 04:47:08.698190 Creating /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/bin/lava-target-ip
174 04:47:08.698309 Creating /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/bin/lava-target-mac
175 04:47:08.698429 Creating /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/bin/lava-target-storage
176 04:47:08.698551 Creating /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/bin/lava-test-case
177 04:47:08.698672 Creating /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/bin/lava-test-event
178 04:47:08.698792 Creating /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/bin/lava-test-feedback
179 04:47:08.698912 Creating /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/bin/lava-test-raise
180 04:47:08.699033 Creating /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/bin/lava-test-reference
181 04:47:08.699152 Creating /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/bin/lava-test-runner
182 04:47:08.699277 Creating /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/bin/lava-test-set
183 04:47:08.699398 Creating /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/bin/lava-test-shell
184 04:47:08.699521 Updating /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/bin/lava-add-keys (debian)
185 04:47:08.699670 Updating /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/bin/lava-add-sources (debian)
186 04:47:08.699808 Updating /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/bin/lava-install-packages (debian)
187 04:47:08.699942 Updating /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/bin/lava-installed-packages (debian)
188 04:47:08.700075 Updating /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/bin/lava-os-build (debian)
189 04:47:08.700192 Creating /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/environment
190 04:47:08.700287 LAVA metadata
191 04:47:08.700360 - LAVA_JOB_ID=12699845
192 04:47:08.700425 - LAVA_DISPATCHER_IP=192.168.201.1
193 04:47:08.700524 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 04:47:08.700593 skipped lava-vland-overlay
195 04:47:08.700669 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 04:47:08.700759 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 04:47:08.700822 skipped lava-multinode-overlay
198 04:47:08.700896 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 04:47:08.700979 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 04:47:08.701054 Loading test definitions
201 04:47:08.701141 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 04:47:08.701212 Using /lava-12699845 at stage 0
203 04:47:08.701485 uuid=12699845_1.6.2.3.1 testdef=None
204 04:47:08.701575 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 04:47:08.701661 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 04:47:08.702196 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 04:47:08.702421 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 04:47:08.702967 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 04:47:08.703197 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 04:47:08.703718 runner path: /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/0/tests/0_timesync-off test_uuid 12699845_1.6.2.3.1
213 04:47:08.703871 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 04:47:08.704099 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 04:47:08.704173 Using /lava-12699845 at stage 0
217 04:47:08.704269 Fetching tests from https://github.com/kernelci/test-definitions.git
218 04:47:08.704349 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/0/tests/1_kselftest-alsa'
219 04:47:14.364660 Running '/usr/bin/git checkout kernelci.org
220 04:47:14.505439 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 04:47:14.506180 uuid=12699845_1.6.2.3.5 testdef=None
222 04:47:14.506326 end: 1.6.2.3.5 git-repo-action (duration 00:00:06) [common]
224 04:47:14.506571 start: 1.6.2.3.6 test-overlay (timeout 00:09:42) [common]
225 04:47:14.507302 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 04:47:14.507536 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:42) [common]
228 04:47:14.508476 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 04:47:14.508710 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:42) [common]
231 04:47:14.509629 runner path: /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/0/tests/1_kselftest-alsa test_uuid 12699845_1.6.2.3.5
232 04:47:14.509722 BOARD='mt8192-asurada-spherion-r0'
233 04:47:14.509786 BRANCH='cip-gitlab'
234 04:47:14.509846 SKIPFILE='/dev/null'
235 04:47:14.509904 SKIP_INSTALL='True'
236 04:47:14.510023 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 04:47:14.510100 TST_CASENAME=''
238 04:47:14.510156 TST_CMDFILES='alsa'
239 04:47:14.510292 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 04:47:14.510504 Creating lava-test-runner.conf files
242 04:47:14.510570 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12699845/lava-overlay-yzs9izv1/lava-12699845/0 for stage 0
243 04:47:14.510670 - 0_timesync-off
244 04:47:14.510745 - 1_kselftest-alsa
245 04:47:14.510839 end: 1.6.2.3 test-definition (duration 00:00:06) [common]
246 04:47:14.510925 start: 1.6.2.4 compress-overlay (timeout 00:09:42) [common]
247 04:47:21.873005 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 04:47:21.873193 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:35) [common]
249 04:47:21.873284 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 04:47:21.873385 end: 1.6.2 lava-overlay (duration 00:00:13) [common]
251 04:47:21.873477 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:35) [common]
252 04:47:22.034931 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 04:47:22.035361 start: 1.6.4 extract-modules (timeout 00:09:34) [common]
254 04:47:22.035483 extracting modules file /var/lib/lava/dispatcher/tmp/12699845/tftp-deploy-2p2y6t07/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12699845/extract-nfsrootfs-6vzpzxd0
255 04:47:22.240039 extracting modules file /var/lib/lava/dispatcher/tmp/12699845/tftp-deploy-2p2y6t07/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12699845/extract-overlay-ramdisk-ctb2kie9/ramdisk
256 04:47:22.447829 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 04:47:22.448047 start: 1.6.5 apply-overlay-tftp (timeout 00:09:34) [common]
258 04:47:22.448150 [common] Applying overlay to NFS
259 04:47:22.448221 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12699845/compress-overlay-4fvxqjal/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12699845/extract-nfsrootfs-6vzpzxd0
260 04:47:23.343790 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 04:47:23.343977 start: 1.6.6 configure-preseed-file (timeout 00:09:33) [common]
262 04:47:23.344073 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 04:47:23.344158 start: 1.6.7 compress-ramdisk (timeout 00:09:33) [common]
264 04:47:23.344243 Building ramdisk /var/lib/lava/dispatcher/tmp/12699845/extract-overlay-ramdisk-ctb2kie9/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12699845/extract-overlay-ramdisk-ctb2kie9/ramdisk
265 04:47:23.626044 >> 130561 blocks
266 04:47:25.610587 rename /var/lib/lava/dispatcher/tmp/12699845/extract-overlay-ramdisk-ctb2kie9/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12699845/tftp-deploy-2p2y6t07/ramdisk/ramdisk.cpio.gz
267 04:47:25.611042 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 04:47:25.611187 start: 1.6.8 prepare-kernel (timeout 00:09:31) [common]
269 04:47:25.611314 start: 1.6.8.1 prepare-fit (timeout 00:09:31) [common]
270 04:47:25.611450 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12699845/tftp-deploy-2p2y6t07/kernel/Image'
271 04:47:37.683828 Returned 0 in 12 seconds
272 04:47:37.784601 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12699845/tftp-deploy-2p2y6t07/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12699845/tftp-deploy-2p2y6t07/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12699845/tftp-deploy-2p2y6t07/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12699845/tftp-deploy-2p2y6t07/kernel/image.itb
273 04:47:38.138239 output: FIT description: Kernel Image image with one or more FDT blobs
274 04:47:38.138600 output: Created: Sun Feb 4 04:47:38 2024
275 04:47:38.138684 output: Image 0 (kernel-1)
276 04:47:38.138750 output: Description:
277 04:47:38.138810 output: Created: Sun Feb 4 04:47:38 2024
278 04:47:38.138869 output: Type: Kernel Image
279 04:47:38.138924 output: Compression: lzma compressed
280 04:47:38.138979 output: Data Size: 12048508 Bytes = 11766.12 KiB = 11.49 MiB
281 04:47:38.139038 output: Architecture: AArch64
282 04:47:38.139093 output: OS: Linux
283 04:47:38.139146 output: Load Address: 0x00000000
284 04:47:38.139202 output: Entry Point: 0x00000000
285 04:47:38.139255 output: Hash algo: crc32
286 04:47:38.139308 output: Hash value: 3b31d50c
287 04:47:38.139362 output: Image 1 (fdt-1)
288 04:47:38.139419 output: Description: mt8192-asurada-spherion-r0
289 04:47:38.139472 output: Created: Sun Feb 4 04:47:38 2024
290 04:47:38.139525 output: Type: Flat Device Tree
291 04:47:38.139578 output: Compression: uncompressed
292 04:47:38.139630 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 04:47:38.139683 output: Architecture: AArch64
294 04:47:38.139735 output: Hash algo: crc32
295 04:47:38.139787 output: Hash value: cc4352de
296 04:47:38.139839 output: Image 2 (ramdisk-1)
297 04:47:38.139891 output: Description: unavailable
298 04:47:38.139943 output: Created: Sun Feb 4 04:47:38 2024
299 04:47:38.139996 output: Type: RAMDisk Image
300 04:47:38.140048 output: Compression: Unknown Compression
301 04:47:38.140100 output: Data Size: 18775269 Bytes = 18335.22 KiB = 17.91 MiB
302 04:47:38.140152 output: Architecture: AArch64
303 04:47:38.140204 output: OS: Linux
304 04:47:38.140256 output: Load Address: unavailable
305 04:47:38.140308 output: Entry Point: unavailable
306 04:47:38.140360 output: Hash algo: crc32
307 04:47:38.140412 output: Hash value: b9451c20
308 04:47:38.140464 output: Default Configuration: 'conf-1'
309 04:47:38.140516 output: Configuration 0 (conf-1)
310 04:47:38.140568 output: Description: mt8192-asurada-spherion-r0
311 04:47:38.140620 output: Kernel: kernel-1
312 04:47:38.140672 output: Init Ramdisk: ramdisk-1
313 04:47:38.140723 output: FDT: fdt-1
314 04:47:38.140775 output: Loadables: kernel-1
315 04:47:38.140827 output:
316 04:47:38.141016 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 04:47:38.141109 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 04:47:38.141208 end: 1.6 prepare-tftp-overlay (duration 00:00:33) [common]
319 04:47:38.141301 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:18) [common]
320 04:47:38.141378 No LXC device requested
321 04:47:38.141467 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 04:47:38.141585 start: 1.8 deploy-device-env (timeout 00:09:18) [common]
323 04:47:38.141670 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 04:47:38.141741 Checking files for TFTP limit of 4294967296 bytes.
325 04:47:38.142243 end: 1 tftp-deploy (duration 00:00:42) [common]
326 04:47:38.142348 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 04:47:38.142443 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 04:47:38.142566 substitutions:
329 04:47:38.142635 - {DTB}: 12699845/tftp-deploy-2p2y6t07/dtb/mt8192-asurada-spherion-r0.dtb
330 04:47:38.142700 - {INITRD}: 12699845/tftp-deploy-2p2y6t07/ramdisk/ramdisk.cpio.gz
331 04:47:38.142761 - {KERNEL}: 12699845/tftp-deploy-2p2y6t07/kernel/Image
332 04:47:38.142820 - {LAVA_MAC}: None
333 04:47:38.142876 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12699845/extract-nfsrootfs-6vzpzxd0
334 04:47:38.142932 - {NFS_SERVER_IP}: 192.168.201.1
335 04:47:38.142985 - {PRESEED_CONFIG}: None
336 04:47:38.143040 - {PRESEED_LOCAL}: None
337 04:47:38.143095 - {RAMDISK}: 12699845/tftp-deploy-2p2y6t07/ramdisk/ramdisk.cpio.gz
338 04:47:38.143148 - {ROOT_PART}: None
339 04:47:38.143202 - {ROOT}: None
340 04:47:38.143256 - {SERVER_IP}: 192.168.201.1
341 04:47:38.143310 - {TEE}: None
342 04:47:38.143363 Parsed boot commands:
343 04:47:38.143421 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 04:47:38.143639 Parsed boot commands: tftpboot 192.168.201.1 12699845/tftp-deploy-2p2y6t07/kernel/image.itb 12699845/tftp-deploy-2p2y6t07/kernel/cmdline
345 04:47:38.143725 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 04:47:38.143807 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 04:47:38.143895 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 04:47:38.143980 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 04:47:38.144047 Not connected, no need to disconnect.
350 04:47:38.144118 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 04:47:38.144197 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 04:47:38.144264 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
353 04:47:38.147563 Setting prompt string to ['lava-test: # ']
354 04:47:38.147883 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 04:47:38.147989 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 04:47:38.148100 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 04:47:38.148215 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 04:47:38.148443 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
359 04:47:43.288411 >> Command sent successfully.
360 04:47:43.293554 Returned 0 in 5 seconds
361 04:47:43.394269 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 04:47:43.396127 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 04:47:43.396825 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 04:47:43.397393 Setting prompt string to 'Starting depthcharge on Spherion...'
366 04:47:43.397869 Changing prompt to 'Starting depthcharge on Spherion...'
367 04:47:43.398417 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 04:47:43.400006 [Enter `^Ec?' for help]
369 04:47:43.567390
370 04:47:43.568063
371 04:47:43.568476 F0: 102B 0000
372 04:47:43.568867
373 04:47:43.569233 F3: 1001 0000 [0200]
374 04:47:43.569569
375 04:47:43.571250 F3: 1001 0000
376 04:47:43.571736
377 04:47:43.572119 F7: 102D 0000
378 04:47:43.572480
379 04:47:43.572825 F1: 0000 0000
380 04:47:43.573164
381 04:47:43.574984 V0: 0000 0000 [0001]
382 04:47:43.575513
383 04:47:43.575912 00: 0007 8000
384 04:47:43.576283
385 04:47:43.578563 01: 0000 0000
386 04:47:43.579055
387 04:47:43.579438 BP: 0C00 0209 [0000]
388 04:47:43.579796
389 04:47:43.580137 G0: 1182 0000
390 04:47:43.580472
391 04:47:43.582060 EC: 0000 0021 [4000]
392 04:47:43.582543
393 04:47:43.586109 S7: 0000 0000 [0000]
394 04:47:43.586589
395 04:47:43.586978 CC: 0000 0000 [0001]
396 04:47:43.587343
397 04:47:43.589436 T0: 0000 0040 [010F]
398 04:47:43.589918
399 04:47:43.590360 Jump to BL
400 04:47:43.590726
401 04:47:43.614470
402 04:47:43.615057
403 04:47:43.615447
404 04:47:43.621928 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 04:47:43.625212 ARM64: Exception handlers installed.
406 04:47:43.629227 ARM64: Testing exception
407 04:47:43.632771 ARM64: Done test exception
408 04:47:43.639876 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 04:47:43.646848 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 04:47:43.653833 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 04:47:43.664970 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 04:47:43.671117 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 04:47:43.681861 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 04:47:43.692243 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 04:47:43.699079 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 04:47:43.716948 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 04:47:43.720208 WDT: Last reset was cold boot
418 04:47:43.723288 SPI1(PAD0) initialized at 2873684 Hz
419 04:47:43.726783 SPI5(PAD0) initialized at 992727 Hz
420 04:47:43.730272 VBOOT: Loading verstage.
421 04:47:43.736995 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 04:47:43.740655 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 04:47:43.743492 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 04:47:43.746760 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 04:47:43.754693 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 04:47:43.761020 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 04:47:43.771948 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 04:47:43.772578
429 04:47:43.772968
430 04:47:43.781752 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 04:47:43.785219 ARM64: Exception handlers installed.
432 04:47:43.788315 ARM64: Testing exception
433 04:47:43.788809 ARM64: Done test exception
434 04:47:43.795400 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 04:47:43.798675 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 04:47:43.812956 Probing TPM: . done!
437 04:47:43.813550 TPM ready after 0 ms
438 04:47:43.819831 Connected to device vid:did:rid of 1ae0:0028:00
439 04:47:43.826552 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 04:47:43.883751 Initialized TPM device CR50 revision 0
441 04:47:43.895592 tlcl_send_startup: Startup return code is 0
442 04:47:43.896093 TPM: setup succeeded
443 04:47:43.906919 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 04:47:43.916194 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 04:47:43.926117 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 04:47:43.935609 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 04:47:43.938928 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 04:47:43.945497 in-header: 03 07 00 00 08 00 00 00
449 04:47:43.949285 in-data: aa e4 47 04 13 02 00 00
450 04:47:43.952557 Chrome EC: UHEPI supported
451 04:47:43.959921 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 04:47:43.964024 in-header: 03 ad 00 00 08 00 00 00
453 04:47:43.967215 in-data: 00 20 20 08 00 00 00 00
454 04:47:43.967797 Phase 1
455 04:47:43.970943 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 04:47:43.978109 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 04:47:43.981937 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 04:47:43.985628 Recovery requested (1009000e)
459 04:47:43.994605 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 04:47:44.000391 tlcl_extend: response is 0
461 04:47:44.010055 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 04:47:44.015596 tlcl_extend: response is 0
463 04:47:44.022487 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 04:47:44.042849 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 04:47:44.049754 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 04:47:44.050363
467 04:47:44.050754
468 04:47:44.060037 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 04:47:44.063742 ARM64: Exception handlers installed.
470 04:47:44.064335 ARM64: Testing exception
471 04:47:44.067223 ARM64: Done test exception
472 04:47:44.088136 pmic_efuse_setting: Set efuses in 11 msecs
473 04:47:44.091427 pmwrap_interface_init: Select PMIF_VLD_RDY
474 04:47:44.098422 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 04:47:44.102259 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 04:47:44.105733 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 04:47:44.112504 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 04:47:44.116765 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 04:47:44.119910 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 04:47:44.127861 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 04:47:44.131105 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 04:47:44.134956 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 04:47:44.138809 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 04:47:44.145539 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 04:47:44.148896 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 04:47:44.152095 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 04:47:44.159815 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 04:47:44.166510 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 04:47:44.173239 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 04:47:44.177133 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 04:47:44.184356 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 04:47:44.187866 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 04:47:44.194768 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 04:47:44.198134 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 04:47:44.205445 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 04:47:44.212184 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 04:47:44.215303 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 04:47:44.221888 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 04:47:44.229185 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 04:47:44.231827 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 04:47:44.235415 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 04:47:44.242315 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 04:47:44.245372 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 04:47:44.252496 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 04:47:44.255693 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 04:47:44.262106 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 04:47:44.265533 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 04:47:44.271942 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 04:47:44.275380 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 04:47:44.282326 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 04:47:44.285787 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 04:47:44.291890 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 04:47:44.295295 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 04:47:44.298447 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 04:47:44.305437 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 04:47:44.312151 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 04:47:44.312987 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 04:47:44.316294 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 04:47:44.322773 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 04:47:44.326591 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 04:47:44.329454 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 04:47:44.336597 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 04:47:44.339945 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 04:47:44.342644 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 04:47:44.349869 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 04:47:44.359520 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 04:47:44.362942 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 04:47:44.372941 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 04:47:44.379591 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 04:47:44.386458 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 04:47:44.389837 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 04:47:44.393156 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 04:47:44.400590 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x18
534 04:47:44.407616 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 04:47:44.410578 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 04:47:44.413824 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 04:47:44.425674 [RTC]rtc_get_frequency_meter,154: input=15, output=774
538 04:47:44.434839 [RTC]rtc_get_frequency_meter,154: input=23, output=956
539 04:47:44.444089 [RTC]rtc_get_frequency_meter,154: input=19, output=864
540 04:47:44.453639 [RTC]rtc_get_frequency_meter,154: input=17, output=818
541 04:47:44.463470 [RTC]rtc_get_frequency_meter,154: input=16, output=796
542 04:47:44.466830 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
543 04:47:44.473502 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
544 04:47:44.476757 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
545 04:47:44.480056 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
546 04:47:44.483310 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
547 04:47:44.486764 ADC[4]: Raw value=903245 ID=7
548 04:47:44.490296 ADC[3]: Raw value=213179 ID=1
549 04:47:44.491072 RAM Code: 0x71
550 04:47:44.496646 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
551 04:47:44.499693 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
552 04:47:44.510129 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
553 04:47:44.516832 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 04:47:44.520318 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
555 04:47:44.523568 in-header: 03 07 00 00 08 00 00 00
556 04:47:44.526723 in-data: aa e4 47 04 13 02 00 00
557 04:47:44.529830 Chrome EC: UHEPI supported
558 04:47:44.536881 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
559 04:47:44.540066 in-header: 03 ed 00 00 08 00 00 00
560 04:47:44.543717 in-data: 80 20 60 08 00 00 00 00
561 04:47:44.546559 MRC: failed to locate region type 0.
562 04:47:44.553148 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
563 04:47:44.556590 DRAM-K: Running full calibration
564 04:47:44.563314 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
565 04:47:44.563905 header.status = 0x0
566 04:47:44.566609 header.version = 0x6 (expected: 0x6)
567 04:47:44.570393 header.size = 0xd00 (expected: 0xd00)
568 04:47:44.573290 header.flags = 0x0
569 04:47:44.580150 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
570 04:47:44.595959 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
571 04:47:44.602782 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
572 04:47:44.606197 dram_init: ddr_geometry: 2
573 04:47:44.609638 [EMI] MDL number = 2
574 04:47:44.610271 [EMI] Get MDL freq = 0
575 04:47:44.612827 dram_init: ddr_type: 0
576 04:47:44.613421 is_discrete_lpddr4: 1
577 04:47:44.615918 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
578 04:47:44.616400
579 04:47:44.616778
580 04:47:44.619324 [Bian_co] ETT version 0.0.0.1
581 04:47:44.626021 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
582 04:47:44.626607
583 04:47:44.629668 dramc_set_vcore_voltage set vcore to 650000
584 04:47:44.630318 Read voltage for 800, 4
585 04:47:44.632945 Vio18 = 0
586 04:47:44.633650 Vcore = 650000
587 04:47:44.634260 Vdram = 0
588 04:47:44.635960 Vddq = 0
589 04:47:44.636520 Vmddr = 0
590 04:47:44.639440 dram_init: config_dvfs: 1
591 04:47:44.643240 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
592 04:47:44.649828 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
593 04:47:44.653080 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
594 04:47:44.656399 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
595 04:47:44.659710 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
596 04:47:44.663066 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
597 04:47:44.666708 MEM_TYPE=3, freq_sel=18
598 04:47:44.670521 sv_algorithm_assistance_LP4_1600
599 04:47:44.674024 ============ PULL DRAM RESETB DOWN ============
600 04:47:44.677917 ========== PULL DRAM RESETB DOWN end =========
601 04:47:44.682020 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
602 04:47:44.685753 ===================================
603 04:47:44.689811 LPDDR4 DRAM CONFIGURATION
604 04:47:44.692909 ===================================
605 04:47:44.693391 EX_ROW_EN[0] = 0x0
606 04:47:44.696815 EX_ROW_EN[1] = 0x0
607 04:47:44.697298 LP4Y_EN = 0x0
608 04:47:44.700875 WORK_FSP = 0x0
609 04:47:44.701706 WL = 0x2
610 04:47:44.702254 RL = 0x2
611 04:47:44.703981 BL = 0x2
612 04:47:44.704620 RPST = 0x0
613 04:47:44.707882 RD_PRE = 0x0
614 04:47:44.708374 WR_PRE = 0x1
615 04:47:44.712049 WR_PST = 0x0
616 04:47:44.712528 DBI_WR = 0x0
617 04:47:44.715857 DBI_RD = 0x0
618 04:47:44.716352 OTF = 0x1
619 04:47:44.719152 ===================================
620 04:47:44.722696 ===================================
621 04:47:44.723183 ANA top config
622 04:47:44.726845 ===================================
623 04:47:44.729897 DLL_ASYNC_EN = 0
624 04:47:44.733199 ALL_SLAVE_EN = 1
625 04:47:44.733710 NEW_RANK_MODE = 1
626 04:47:44.736780 DLL_IDLE_MODE = 1
627 04:47:44.739998 LP45_APHY_COMB_EN = 1
628 04:47:44.743271 TX_ODT_DIS = 1
629 04:47:44.746517 NEW_8X_MODE = 1
630 04:47:44.749860 ===================================
631 04:47:44.752933 ===================================
632 04:47:44.753423 data_rate = 1600
633 04:47:44.756678 CKR = 1
634 04:47:44.759981 DQ_P2S_RATIO = 8
635 04:47:44.763219 ===================================
636 04:47:44.766798 CA_P2S_RATIO = 8
637 04:47:44.770366 DQ_CA_OPEN = 0
638 04:47:44.773406 DQ_SEMI_OPEN = 0
639 04:47:44.773896 CA_SEMI_OPEN = 0
640 04:47:44.776725 CA_FULL_RATE = 0
641 04:47:44.780256 DQ_CKDIV4_EN = 1
642 04:47:44.783853 CA_CKDIV4_EN = 1
643 04:47:44.787254 CA_PREDIV_EN = 0
644 04:47:44.787861 PH8_DLY = 0
645 04:47:44.791139 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
646 04:47:44.794876 DQ_AAMCK_DIV = 4
647 04:47:44.798274 CA_AAMCK_DIV = 4
648 04:47:44.798766 CA_ADMCK_DIV = 4
649 04:47:44.801795 DQ_TRACK_CA_EN = 0
650 04:47:44.805225 CA_PICK = 800
651 04:47:44.809779 CA_MCKIO = 800
652 04:47:44.810446 MCKIO_SEMI = 0
653 04:47:44.813018 PLL_FREQ = 3068
654 04:47:44.816264 DQ_UI_PI_RATIO = 32
655 04:47:44.819801 CA_UI_PI_RATIO = 0
656 04:47:44.823371 ===================================
657 04:47:44.826042 ===================================
658 04:47:44.829700 memory_type:LPDDR4
659 04:47:44.830324 GP_NUM : 10
660 04:47:44.832991 SRAM_EN : 1
661 04:47:44.833575 MD32_EN : 0
662 04:47:44.836383 ===================================
663 04:47:44.839948 [ANA_INIT] >>>>>>>>>>>>>>
664 04:47:44.844385 <<<<<< [CONFIGURE PHASE]: ANA_TX
665 04:47:44.847895 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
666 04:47:44.852120 ===================================
667 04:47:44.852744 data_rate = 1600,PCW = 0X7600
668 04:47:44.854988 ===================================
669 04:47:44.858512 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
670 04:47:44.866636 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 04:47:44.870629 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
672 04:47:44.873712 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
673 04:47:44.877131 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
674 04:47:44.880932 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
675 04:47:44.884426 [ANA_INIT] flow start
676 04:47:44.887239 [ANA_INIT] PLL >>>>>>>>
677 04:47:44.887824 [ANA_INIT] PLL <<<<<<<<
678 04:47:44.890645 [ANA_INIT] MIDPI >>>>>>>>
679 04:47:44.894282 [ANA_INIT] MIDPI <<<<<<<<
680 04:47:44.894767 [ANA_INIT] DLL >>>>>>>>
681 04:47:44.897238 [ANA_INIT] flow end
682 04:47:44.900888 ============ LP4 DIFF to SE enter ============
683 04:47:44.904572 ============ LP4 DIFF to SE exit ============
684 04:47:44.907444 [ANA_INIT] <<<<<<<<<<<<<
685 04:47:44.910756 [Flow] Enable top DCM control >>>>>
686 04:47:44.913883 [Flow] Enable top DCM control <<<<<
687 04:47:44.917522 Enable DLL master slave shuffle
688 04:47:44.924357 ==============================================================
689 04:47:44.924946 Gating Mode config
690 04:47:44.930840 ==============================================================
691 04:47:44.931431 Config description:
692 04:47:44.940816 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
693 04:47:44.947313 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
694 04:47:44.954199 SELPH_MODE 0: By rank 1: By Phase
695 04:47:44.957394 ==============================================================
696 04:47:44.960603 GAT_TRACK_EN = 1
697 04:47:44.964315 RX_GATING_MODE = 2
698 04:47:44.967420 RX_GATING_TRACK_MODE = 2
699 04:47:44.970614 SELPH_MODE = 1
700 04:47:44.974026 PICG_EARLY_EN = 1
701 04:47:44.977917 VALID_LAT_VALUE = 1
702 04:47:44.981240 ==============================================================
703 04:47:44.984350 Enter into Gating configuration >>>>
704 04:47:44.988001 Exit from Gating configuration <<<<
705 04:47:44.990790 Enter into DVFS_PRE_config >>>>>
706 04:47:45.004400 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
707 04:47:45.007734 Exit from DVFS_PRE_config <<<<<
708 04:47:45.008320 Enter into PICG configuration >>>>
709 04:47:45.010797 Exit from PICG configuration <<<<
710 04:47:45.014146 [RX_INPUT] configuration >>>>>
711 04:47:45.017379 [RX_INPUT] configuration <<<<<
712 04:47:45.024350 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
713 04:47:45.027572 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
714 04:47:45.034398 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
715 04:47:45.041417 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
716 04:47:45.047672 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
717 04:47:45.054405 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
718 04:47:45.057535 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
719 04:47:45.060950 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
720 04:47:45.064093 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
721 04:47:45.067864 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
722 04:47:45.075063 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
723 04:47:45.078237 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
724 04:47:45.081751 ===================================
725 04:47:45.084911 LPDDR4 DRAM CONFIGURATION
726 04:47:45.088981 ===================================
727 04:47:45.089577 EX_ROW_EN[0] = 0x0
728 04:47:45.091691 EX_ROW_EN[1] = 0x0
729 04:47:45.092167 LP4Y_EN = 0x0
730 04:47:45.095119 WORK_FSP = 0x0
731 04:47:45.095642 WL = 0x2
732 04:47:45.098376 RL = 0x2
733 04:47:45.098854 BL = 0x2
734 04:47:45.101973 RPST = 0x0
735 04:47:45.102590 RD_PRE = 0x0
736 04:47:45.105176 WR_PRE = 0x1
737 04:47:45.105652 WR_PST = 0x0
738 04:47:45.108712 DBI_WR = 0x0
739 04:47:45.109321 DBI_RD = 0x0
740 04:47:45.111869 OTF = 0x1
741 04:47:45.115117 ===================================
742 04:47:45.118462 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
743 04:47:45.121495 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
744 04:47:45.128977 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
745 04:47:45.131884 ===================================
746 04:47:45.132481 LPDDR4 DRAM CONFIGURATION
747 04:47:45.135116 ===================================
748 04:47:45.138658 EX_ROW_EN[0] = 0x10
749 04:47:45.142153 EX_ROW_EN[1] = 0x0
750 04:47:45.142749 LP4Y_EN = 0x0
751 04:47:45.145478 WORK_FSP = 0x0
752 04:47:45.146105 WL = 0x2
753 04:47:45.148930 RL = 0x2
754 04:47:45.149524 BL = 0x2
755 04:47:45.152269 RPST = 0x0
756 04:47:45.152864 RD_PRE = 0x0
757 04:47:45.155000 WR_PRE = 0x1
758 04:47:45.155484 WR_PST = 0x0
759 04:47:45.158793 DBI_WR = 0x0
760 04:47:45.159387 DBI_RD = 0x0
761 04:47:45.162302 OTF = 0x1
762 04:47:45.165452 ===================================
763 04:47:45.171646 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
764 04:47:45.175221 nWR fixed to 40
765 04:47:45.175706 [ModeRegInit_LP4] CH0 RK0
766 04:47:45.178464 [ModeRegInit_LP4] CH0 RK1
767 04:47:45.181965 [ModeRegInit_LP4] CH1 RK0
768 04:47:45.182569 [ModeRegInit_LP4] CH1 RK1
769 04:47:45.185182 match AC timing 13
770 04:47:45.188796 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
771 04:47:45.192494 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
772 04:47:45.199402 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
773 04:47:45.203068 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
774 04:47:45.206950 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
775 04:47:45.210182 [EMI DOE] emi_dcm 0
776 04:47:45.214134 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
777 04:47:45.214724 ==
778 04:47:45.217836 Dram Type= 6, Freq= 0, CH_0, rank 0
779 04:47:45.221159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 04:47:45.221767 ==
781 04:47:45.228413 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 04:47:45.231664 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 04:47:45.242261 [CA 0] Center 37 (7~68) winsize 62
784 04:47:45.246425 [CA 1] Center 38 (7~69) winsize 63
785 04:47:45.249762 [CA 2] Center 35 (5~66) winsize 62
786 04:47:45.253089 [CA 3] Center 35 (5~66) winsize 62
787 04:47:45.257420 [CA 4] Center 35 (4~66) winsize 63
788 04:47:45.260834 [CA 5] Center 33 (3~64) winsize 62
789 04:47:45.261420
790 04:47:45.264780 [CmdBusTrainingLP45] Vref(ca) range 1: 32
791 04:47:45.265363
792 04:47:45.268384 [CATrainingPosCal] consider 1 rank data
793 04:47:45.268870 u2DelayCellTimex100 = 270/100 ps
794 04:47:45.272008 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
795 04:47:45.275355 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
796 04:47:45.279037 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
797 04:47:45.283114 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
798 04:47:45.286586 CA4 delay=35 (4~66),Diff = 2 PI (14 cell)
799 04:47:45.290510 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
800 04:47:45.290996
801 04:47:45.294057 CA PerBit enable=1, Macro0, CA PI delay=33
802 04:47:45.297404
803 04:47:45.297887 [CBTSetCACLKResult] CA Dly = 33
804 04:47:45.301460 CS Dly: 5 (0~36)
805 04:47:45.301983 ==
806 04:47:45.304880 Dram Type= 6, Freq= 0, CH_0, rank 1
807 04:47:45.308299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 04:47:45.308787 ==
809 04:47:45.312480 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
810 04:47:45.319082 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
811 04:47:45.329471 [CA 0] Center 38 (7~69) winsize 63
812 04:47:45.333076 [CA 1] Center 38 (8~69) winsize 62
813 04:47:45.337025 [CA 2] Center 36 (6~67) winsize 62
814 04:47:45.340757 [CA 3] Center 36 (5~67) winsize 63
815 04:47:45.344226 [CA 4] Center 35 (4~66) winsize 63
816 04:47:45.344759 [CA 5] Center 34 (4~65) winsize 62
817 04:47:45.345217
818 04:47:45.347918 [CmdBusTrainingLP45] Vref(ca) range 1: 34
819 04:47:45.348464
820 04:47:45.351442 [CATrainingPosCal] consider 2 rank data
821 04:47:45.355167 u2DelayCellTimex100 = 270/100 ps
822 04:47:45.359167 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
823 04:47:45.363127 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
824 04:47:45.366606 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
825 04:47:45.370453 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
826 04:47:45.373790 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
827 04:47:45.377668 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
828 04:47:45.378203
829 04:47:45.381711 CA PerBit enable=1, Macro0, CA PI delay=34
830 04:47:45.382242
831 04:47:45.384681 [CBTSetCACLKResult] CA Dly = 34
832 04:47:45.385155 CS Dly: 6 (0~38)
833 04:47:45.388874
834 04:47:45.389467 ----->DramcWriteLeveling(PI) begin...
835 04:47:45.389865 ==
836 04:47:45.392324 Dram Type= 6, Freq= 0, CH_0, rank 0
837 04:47:45.396100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
838 04:47:45.399667 ==
839 04:47:45.400149 Write leveling (Byte 0): 32 => 32
840 04:47:45.403527 Write leveling (Byte 1): 31 => 31
841 04:47:45.407043 DramcWriteLeveling(PI) end<-----
842 04:47:45.407539
843 04:47:45.407928 ==
844 04:47:45.411040 Dram Type= 6, Freq= 0, CH_0, rank 0
845 04:47:45.414695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
846 04:47:45.415195 ==
847 04:47:45.418615 [Gating] SW mode calibration
848 04:47:45.425630 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
849 04:47:45.429396 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
850 04:47:45.433441 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
851 04:47:45.440694 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
852 04:47:45.444272 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 04:47:45.447877 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 04:47:45.451207 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 04:47:45.455013 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 04:47:45.462142 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 04:47:45.466034 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 04:47:45.469684 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 04:47:45.473477 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 04:47:45.477127 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 04:47:45.484405 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 04:47:45.487782 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 04:47:45.492032 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 04:47:45.495536 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 04:47:45.499186 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 04:47:45.506025 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 04:47:45.510262 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
868 04:47:45.513905 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
869 04:47:45.516975 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 04:47:45.523881 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 04:47:45.527035 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 04:47:45.530637 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 04:47:45.537397 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 04:47:45.540930 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 04:47:45.544215 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
876 04:47:45.547363 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
877 04:47:45.553858 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
878 04:47:45.557471 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 04:47:45.560530 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 04:47:45.567522 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 04:47:45.570677 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 04:47:45.573639 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 04:47:45.580644 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
884 04:47:45.584083 0 10 8 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
885 04:47:45.587012 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
886 04:47:45.593878 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 04:47:45.597282 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 04:47:45.600962 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 04:47:45.607607 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 04:47:45.610754 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 04:47:45.613752 0 11 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
892 04:47:45.617432 0 11 8 | B1->B0 | 2929 4646 | 0 0 | (1 1) (0 0)
893 04:47:45.624080 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
894 04:47:45.627881 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 04:47:45.630636 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 04:47:45.637590 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 04:47:45.640964 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 04:47:45.644290 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 04:47:45.651088 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
900 04:47:45.654570 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
901 04:47:45.658064 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 04:47:45.664584 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 04:47:45.667788 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 04:47:45.671469 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 04:47:45.678035 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 04:47:45.681305 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 04:47:45.684555 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 04:47:45.690885 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 04:47:45.694395 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 04:47:45.697325 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 04:47:45.700782 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 04:47:45.707692 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 04:47:45.711191 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 04:47:45.714583 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 04:47:45.721287 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
916 04:47:45.724391 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
917 04:47:45.727910 Total UI for P1: 0, mck2ui 16
918 04:47:45.731480 best dqsien dly found for B0: ( 0, 14, 4)
919 04:47:45.734616 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
920 04:47:45.738141 Total UI for P1: 0, mck2ui 16
921 04:47:45.741438 best dqsien dly found for B1: ( 0, 14, 8)
922 04:47:45.744597 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
923 04:47:45.747879 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
924 04:47:45.748468
925 04:47:45.750778 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
926 04:47:45.757715 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
927 04:47:45.758337 [Gating] SW calibration Done
928 04:47:45.758723 ==
929 04:47:45.761179 Dram Type= 6, Freq= 0, CH_0, rank 0
930 04:47:45.767686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 04:47:45.768255 ==
932 04:47:45.768638 RX Vref Scan: 0
933 04:47:45.769087
934 04:47:45.771185 RX Vref 0 -> 0, step: 1
935 04:47:45.771762
936 04:47:45.774644 RX Delay -130 -> 252, step: 16
937 04:47:45.777893 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
938 04:47:45.781631 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
939 04:47:45.784629 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
940 04:47:45.791225 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
941 04:47:45.794675 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
942 04:47:45.798017 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
943 04:47:45.800744 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
944 04:47:45.804613 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
945 04:47:45.810801 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
946 04:47:45.814615 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
947 04:47:45.818103 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
948 04:47:45.821501 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
949 04:47:45.824784 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
950 04:47:45.831655 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
951 04:47:45.834710 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
952 04:47:45.838019 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
953 04:47:45.838607 ==
954 04:47:45.841530 Dram Type= 6, Freq= 0, CH_0, rank 0
955 04:47:45.844527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
956 04:47:45.845005 ==
957 04:47:45.848013 DQS Delay:
958 04:47:45.848596 DQS0 = 0, DQS1 = 0
959 04:47:45.851169 DQM Delay:
960 04:47:45.851644 DQM0 = 92, DQM1 = 80
961 04:47:45.852020 DQ Delay:
962 04:47:45.854548 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
963 04:47:45.857970 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
964 04:47:45.861681 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
965 04:47:45.865166 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
966 04:47:45.865753
967 04:47:45.866192
968 04:47:45.867732 ==
969 04:47:45.868205 Dram Type= 6, Freq= 0, CH_0, rank 0
970 04:47:45.874989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 04:47:45.875584 ==
972 04:47:45.875970
973 04:47:45.876322
974 04:47:45.876660 TX Vref Scan disable
975 04:47:45.878542 == TX Byte 0 ==
976 04:47:45.882093 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
977 04:47:45.888855 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
978 04:47:45.889439 == TX Byte 1 ==
979 04:47:45.892318 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
980 04:47:45.898350 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
981 04:47:45.898927 ==
982 04:47:45.901706 Dram Type= 6, Freq= 0, CH_0, rank 0
983 04:47:45.905263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
984 04:47:45.905743 ==
985 04:47:45.917656 TX Vref=22, minBit 6, minWin=27, winSum=439
986 04:47:45.920882 TX Vref=24, minBit 6, minWin=27, winSum=442
987 04:47:45.924362 TX Vref=26, minBit 10, minWin=27, winSum=448
988 04:47:45.927817 TX Vref=28, minBit 8, minWin=27, winSum=450
989 04:47:45.930882 TX Vref=30, minBit 8, minWin=27, winSum=456
990 04:47:45.937487 TX Vref=32, minBit 10, minWin=27, winSum=455
991 04:47:45.941152 [TxChooseVref] Worse bit 8, Min win 27, Win sum 456, Final Vref 30
992 04:47:45.941727
993 04:47:45.944387 Final TX Range 1 Vref 30
994 04:47:45.944899
995 04:47:45.945280 ==
996 04:47:45.947423 Dram Type= 6, Freq= 0, CH_0, rank 0
997 04:47:45.950851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
998 04:47:45.951354 ==
999 04:47:45.954291
1000 04:47:45.954763
1001 04:47:45.955137 TX Vref Scan disable
1002 04:47:45.957705 == TX Byte 0 ==
1003 04:47:45.961297 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1004 04:47:45.964638 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1005 04:47:45.968014 == TX Byte 1 ==
1006 04:47:45.971444 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1007 04:47:45.974514 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1008 04:47:45.975109
1009 04:47:45.977974 [DATLAT]
1010 04:47:45.978560 Freq=800, CH0 RK0
1011 04:47:45.978951
1012 04:47:45.981335 DATLAT Default: 0xa
1013 04:47:45.981911 0, 0xFFFF, sum = 0
1014 04:47:45.984814 1, 0xFFFF, sum = 0
1015 04:47:45.985417 2, 0xFFFF, sum = 0
1016 04:47:45.988212 3, 0xFFFF, sum = 0
1017 04:47:45.988823 4, 0xFFFF, sum = 0
1018 04:47:45.991736 5, 0xFFFF, sum = 0
1019 04:47:45.992319 6, 0xFFFF, sum = 0
1020 04:47:45.994875 7, 0xFFFF, sum = 0
1021 04:47:45.995461 8, 0xFFFF, sum = 0
1022 04:47:45.998355 9, 0x0, sum = 1
1023 04:47:45.999009 10, 0x0, sum = 2
1024 04:47:46.001149 11, 0x0, sum = 3
1025 04:47:46.001650 12, 0x0, sum = 4
1026 04:47:46.005244 best_step = 10
1027 04:47:46.005817
1028 04:47:46.006255 ==
1029 04:47:46.008163 Dram Type= 6, Freq= 0, CH_0, rank 0
1030 04:47:46.011664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1031 04:47:46.012243 ==
1032 04:47:46.014735 RX Vref Scan: 1
1033 04:47:46.015201
1034 04:47:46.015680 Set Vref Range= 32 -> 127
1035 04:47:46.016039
1036 04:47:46.018021 RX Vref 32 -> 127, step: 1
1037 04:47:46.018491
1038 04:47:46.021170 RX Delay -95 -> 252, step: 8
1039 04:47:46.021736
1040 04:47:46.024811 Set Vref, RX VrefLevel [Byte0]: 32
1041 04:47:46.028156 [Byte1]: 32
1042 04:47:46.028625
1043 04:47:46.031586 Set Vref, RX VrefLevel [Byte0]: 33
1044 04:47:46.035025 [Byte1]: 33
1045 04:47:46.038137
1046 04:47:46.038607 Set Vref, RX VrefLevel [Byte0]: 34
1047 04:47:46.041423 [Byte1]: 34
1048 04:47:46.045912
1049 04:47:46.046523 Set Vref, RX VrefLevel [Byte0]: 35
1050 04:47:46.048832 [Byte1]: 35
1051 04:47:46.053060
1052 04:47:46.053556 Set Vref, RX VrefLevel [Byte0]: 36
1053 04:47:46.056621 [Byte1]: 36
1054 04:47:46.061178
1055 04:47:46.061808 Set Vref, RX VrefLevel [Byte0]: 37
1056 04:47:46.064277 [Byte1]: 37
1057 04:47:46.069281
1058 04:47:46.069932 Set Vref, RX VrefLevel [Byte0]: 38
1059 04:47:46.072472 [Byte1]: 38
1060 04:47:46.076095
1061 04:47:46.076605 Set Vref, RX VrefLevel [Byte0]: 39
1062 04:47:46.079467 [Byte1]: 39
1063 04:47:46.083546
1064 04:47:46.084121 Set Vref, RX VrefLevel [Byte0]: 40
1065 04:47:46.086934 [Byte1]: 40
1066 04:47:46.091857
1067 04:47:46.092525 Set Vref, RX VrefLevel [Byte0]: 41
1068 04:47:46.094714 [Byte1]: 41
1069 04:47:46.098954
1070 04:47:46.099424 Set Vref, RX VrefLevel [Byte0]: 42
1071 04:47:46.101984 [Byte1]: 42
1072 04:47:46.106923
1073 04:47:46.107496 Set Vref, RX VrefLevel [Byte0]: 43
1074 04:47:46.109781 [Byte1]: 43
1075 04:47:46.114336
1076 04:47:46.114959 Set Vref, RX VrefLevel [Byte0]: 44
1077 04:47:46.117174 [Byte1]: 44
1078 04:47:46.121479
1079 04:47:46.122076 Set Vref, RX VrefLevel [Byte0]: 45
1080 04:47:46.125168 [Byte1]: 45
1081 04:47:46.129385
1082 04:47:46.129856 Set Vref, RX VrefLevel [Byte0]: 46
1083 04:47:46.132805 [Byte1]: 46
1084 04:47:46.136888
1085 04:47:46.137355 Set Vref, RX VrefLevel [Byte0]: 47
1086 04:47:46.140079 [Byte1]: 47
1087 04:47:46.144351
1088 04:47:46.144957 Set Vref, RX VrefLevel [Byte0]: 48
1089 04:47:46.147811 [Byte1]: 48
1090 04:47:46.152049
1091 04:47:46.152543 Set Vref, RX VrefLevel [Byte0]: 49
1092 04:47:46.155294 [Byte1]: 49
1093 04:47:46.159569
1094 04:47:46.160138 Set Vref, RX VrefLevel [Byte0]: 50
1095 04:47:46.162764 [Byte1]: 50
1096 04:47:46.167563
1097 04:47:46.168136 Set Vref, RX VrefLevel [Byte0]: 51
1098 04:47:46.170567 [Byte1]: 51
1099 04:47:46.175114
1100 04:47:46.175682 Set Vref, RX VrefLevel [Byte0]: 52
1101 04:47:46.178097 [Byte1]: 52
1102 04:47:46.182338
1103 04:47:46.182904 Set Vref, RX VrefLevel [Byte0]: 53
1104 04:47:46.185377 [Byte1]: 53
1105 04:47:46.189923
1106 04:47:46.190535 Set Vref, RX VrefLevel [Byte0]: 54
1107 04:47:46.193518 [Byte1]: 54
1108 04:47:46.197487
1109 04:47:46.198093 Set Vref, RX VrefLevel [Byte0]: 55
1110 04:47:46.200669 [Byte1]: 55
1111 04:47:46.205350
1112 04:47:46.205917 Set Vref, RX VrefLevel [Byte0]: 56
1113 04:47:46.208794 [Byte1]: 56
1114 04:47:46.212766
1115 04:47:46.213336 Set Vref, RX VrefLevel [Byte0]: 57
1116 04:47:46.216117 [Byte1]: 57
1117 04:47:46.220504
1118 04:47:46.221072 Set Vref, RX VrefLevel [Byte0]: 58
1119 04:47:46.223697 [Byte1]: 58
1120 04:47:46.227833
1121 04:47:46.228348 Set Vref, RX VrefLevel [Byte0]: 59
1122 04:47:46.231306 [Byte1]: 59
1123 04:47:46.235267
1124 04:47:46.235736 Set Vref, RX VrefLevel [Byte0]: 60
1125 04:47:46.239138 [Byte1]: 60
1126 04:47:46.243233
1127 04:47:46.243892 Set Vref, RX VrefLevel [Byte0]: 61
1128 04:47:46.246286 [Byte1]: 61
1129 04:47:46.250924
1130 04:47:46.251392 Set Vref, RX VrefLevel [Byte0]: 62
1131 04:47:46.254056 [Byte1]: 62
1132 04:47:46.258698
1133 04:47:46.259467 Set Vref, RX VrefLevel [Byte0]: 63
1134 04:47:46.261632 [Byte1]: 63
1135 04:47:46.265999
1136 04:47:46.266571 Set Vref, RX VrefLevel [Byte0]: 64
1137 04:47:46.269486 [Byte1]: 64
1138 04:47:46.273700
1139 04:47:46.274344 Set Vref, RX VrefLevel [Byte0]: 65
1140 04:47:46.276759 [Byte1]: 65
1141 04:47:46.281362
1142 04:47:46.281934 Set Vref, RX VrefLevel [Byte0]: 66
1143 04:47:46.284778 [Byte1]: 66
1144 04:47:46.288900
1145 04:47:46.289482 Set Vref, RX VrefLevel [Byte0]: 67
1146 04:47:46.291647 [Byte1]: 67
1147 04:47:46.296273
1148 04:47:46.296993 Set Vref, RX VrefLevel [Byte0]: 68
1149 04:47:46.299378 [Byte1]: 68
1150 04:47:46.303755
1151 04:47:46.304226 Set Vref, RX VrefLevel [Byte0]: 69
1152 04:47:46.307222 [Byte1]: 69
1153 04:47:46.311853
1154 04:47:46.312428 Set Vref, RX VrefLevel [Byte0]: 70
1155 04:47:46.314543 [Byte1]: 70
1156 04:47:46.319172
1157 04:47:46.319752 Set Vref, RX VrefLevel [Byte0]: 71
1158 04:47:46.322510 [Byte1]: 71
1159 04:47:46.326740
1160 04:47:46.327209 Set Vref, RX VrefLevel [Byte0]: 72
1161 04:47:46.329832 [Byte1]: 72
1162 04:47:46.334454
1163 04:47:46.335022 Set Vref, RX VrefLevel [Byte0]: 73
1164 04:47:46.337745 [Byte1]: 73
1165 04:47:46.342189
1166 04:47:46.342763 Set Vref, RX VrefLevel [Byte0]: 74
1167 04:47:46.345378 [Byte1]: 74
1168 04:47:46.349501
1169 04:47:46.350070 Set Vref, RX VrefLevel [Byte0]: 75
1170 04:47:46.352684 [Byte1]: 75
1171 04:47:46.356893
1172 04:47:46.357468 Set Vref, RX VrefLevel [Byte0]: 76
1173 04:47:46.360497 [Byte1]: 76
1174 04:47:46.364737
1175 04:47:46.365314 Set Vref, RX VrefLevel [Byte0]: 77
1176 04:47:46.368041 [Byte1]: 77
1177 04:47:46.372470
1178 04:47:46.373101 Set Vref, RX VrefLevel [Byte0]: 78
1179 04:47:46.375664 [Byte1]: 78
1180 04:47:46.379722
1181 04:47:46.380293 Final RX Vref Byte 0 = 63 to rank0
1182 04:47:46.383325 Final RX Vref Byte 1 = 58 to rank0
1183 04:47:46.386821 Final RX Vref Byte 0 = 63 to rank1
1184 04:47:46.390326 Final RX Vref Byte 1 = 58 to rank1==
1185 04:47:46.393608 Dram Type= 6, Freq= 0, CH_0, rank 0
1186 04:47:46.396972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1187 04:47:46.400080 ==
1188 04:47:46.400774 DQS Delay:
1189 04:47:46.401170 DQS0 = 0, DQS1 = 0
1190 04:47:46.403085 DQM Delay:
1191 04:47:46.403558 DQM0 = 93, DQM1 = 82
1192 04:47:46.406523 DQ Delay:
1193 04:47:46.406999 DQ0 =96, DQ1 =96, DQ2 =88, DQ3 =88
1194 04:47:46.410180 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1195 04:47:46.413685 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1196 04:47:46.417025 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =92
1197 04:47:46.420513
1198 04:47:46.421097
1199 04:47:46.426834 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c38, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1200 04:47:46.430294 CH0 RK0: MR19=606, MR18=3C38
1201 04:47:46.436681 CH0_RK0: MR19=0x606, MR18=0x3C38, DQSOSC=394, MR23=63, INC=95, DEC=63
1202 04:47:46.437271
1203 04:47:46.440236 ----->DramcWriteLeveling(PI) begin...
1204 04:47:46.440855 ==
1205 04:47:46.443710 Dram Type= 6, Freq= 0, CH_0, rank 1
1206 04:47:46.446681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1207 04:47:46.447159 ==
1208 04:47:46.450042 Write leveling (Byte 0): 33 => 33
1209 04:47:46.453136 Write leveling (Byte 1): 31 => 31
1210 04:47:46.457007 DramcWriteLeveling(PI) end<-----
1211 04:47:46.457614
1212 04:47:46.458031 ==
1213 04:47:46.460011 Dram Type= 6, Freq= 0, CH_0, rank 1
1214 04:47:46.463738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1215 04:47:46.464358 ==
1216 04:47:46.466593 [Gating] SW mode calibration
1217 04:47:46.473394 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1218 04:47:46.480302 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1219 04:47:46.483653 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1220 04:47:46.486847 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1221 04:47:46.493816 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1222 04:47:46.537907 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 04:47:46.538559 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 04:47:46.538948 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 04:47:46.539305 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 04:47:46.540009 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 04:47:46.540380 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 04:47:46.540721 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 04:47:46.541047 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 04:47:46.541369 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 04:47:46.541688 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 04:47:46.581505 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 04:47:46.582116 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 04:47:46.582880 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 04:47:46.583306 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1236 04:47:46.583689 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1237 04:47:46.584034 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 04:47:46.584369 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 04:47:46.584699 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 04:47:46.585023 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 04:47:46.585408 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 04:47:46.613505 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 04:47:46.614120 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 04:47:46.614498 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1245 04:47:46.615146 0 9 8 | B1->B0 | 2a2a 3131 | 1 0 | (0 0) (0 0)
1246 04:47:46.615553 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 04:47:46.615900 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 04:47:46.616238 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 04:47:46.617328 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 04:47:46.620781 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 04:47:46.624220 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 04:47:46.627231 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
1253 04:47:46.634207 0 10 8 | B1->B0 | 2d2d 2323 | 1 0 | (0 0) (0 0)
1254 04:47:46.637571 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 04:47:46.640792 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 04:47:46.647958 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 04:47:46.650787 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 04:47:46.654222 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 04:47:46.657725 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 04:47:46.664386 0 11 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
1261 04:47:46.667532 0 11 8 | B1->B0 | 3c3c 4444 | 0 0 | (0 0) (0 0)
1262 04:47:46.671264 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 04:47:46.678712 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 04:47:46.682704 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 04:47:46.686259 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 04:47:46.689800 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 04:47:46.693065 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 04:47:46.699982 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 04:47:46.703519 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 04:47:46.706777 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 04:47:46.710154 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 04:47:46.717055 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 04:47:46.720649 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 04:47:46.723720 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 04:47:46.730309 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 04:47:46.733860 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 04:47:46.737091 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 04:47:46.744047 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 04:47:46.747389 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 04:47:46.750061 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 04:47:46.757151 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 04:47:46.760832 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 04:47:46.763475 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 04:47:46.770805 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1285 04:47:46.773897 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1286 04:47:46.777067 Total UI for P1: 0, mck2ui 16
1287 04:47:46.780275 best dqsien dly found for B0: ( 0, 14, 4)
1288 04:47:46.783568 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1289 04:47:46.787046 Total UI for P1: 0, mck2ui 16
1290 04:47:46.790653 best dqsien dly found for B1: ( 0, 14, 8)
1291 04:47:46.793897 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1292 04:47:46.797410 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1293 04:47:46.798065
1294 04:47:46.800622 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1295 04:47:46.803658 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1296 04:47:46.807010 [Gating] SW calibration Done
1297 04:47:46.807479 ==
1298 04:47:46.810538 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 04:47:46.813907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 04:47:46.817332 ==
1301 04:47:46.817913 RX Vref Scan: 0
1302 04:47:46.818350
1303 04:47:46.820834 RX Vref 0 -> 0, step: 1
1304 04:47:46.821422
1305 04:47:46.823657 RX Delay -130 -> 252, step: 16
1306 04:47:46.827300 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1307 04:47:46.830487 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1308 04:47:46.834232 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1309 04:47:46.837203 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1310 04:47:46.844080 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1311 04:47:46.847395 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1312 04:47:46.850895 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1313 04:47:46.854152 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1314 04:47:46.857601 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1315 04:47:46.863845 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1316 04:47:46.867248 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1317 04:47:46.870542 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1318 04:47:46.873697 iDelay=206, Bit 12, Center 85 (-18 ~ 189) 208
1319 04:47:46.877131 iDelay=206, Bit 13, Center 85 (-18 ~ 189) 208
1320 04:47:46.883467 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1321 04:47:46.887068 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1322 04:47:46.887665 ==
1323 04:47:46.890891 Dram Type= 6, Freq= 0, CH_0, rank 1
1324 04:47:46.893636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1325 04:47:46.894143 ==
1326 04:47:46.896999 DQS Delay:
1327 04:47:46.897595 DQS0 = 0, DQS1 = 0
1328 04:47:46.898018 DQM Delay:
1329 04:47:46.900395 DQM0 = 87, DQM1 = 81
1330 04:47:46.900997 DQ Delay:
1331 04:47:46.903553 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1332 04:47:46.907027 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1333 04:47:46.910323 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1334 04:47:46.913558 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1335 04:47:46.914070
1336 04:47:46.914453
1337 04:47:46.914804 ==
1338 04:47:46.917285 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 04:47:46.923872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1340 04:47:46.924354 ==
1341 04:47:46.924735
1342 04:47:46.925090
1343 04:47:46.925431 TX Vref Scan disable
1344 04:47:46.927578 == TX Byte 0 ==
1345 04:47:46.930676 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1346 04:47:46.933642 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1347 04:47:46.937305 == TX Byte 1 ==
1348 04:47:46.940693 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1349 04:47:46.943993 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1350 04:47:46.947215 ==
1351 04:47:46.950876 Dram Type= 6, Freq= 0, CH_0, rank 1
1352 04:47:46.954242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1353 04:47:46.954821 ==
1354 04:47:46.966815 TX Vref=22, minBit 3, minWin=27, winSum=444
1355 04:47:46.969748 TX Vref=24, minBit 8, minWin=27, winSum=450
1356 04:47:46.973275 TX Vref=26, minBit 8, minWin=27, winSum=450
1357 04:47:46.976684 TX Vref=28, minBit 8, minWin=27, winSum=453
1358 04:47:46.979652 TX Vref=30, minBit 8, minWin=27, winSum=457
1359 04:47:46.986532 TX Vref=32, minBit 11, minWin=28, winSum=459
1360 04:47:46.989745 [TxChooseVref] Worse bit 11, Min win 28, Win sum 459, Final Vref 32
1361 04:47:46.990267
1362 04:47:46.992765 Final TX Range 1 Vref 32
1363 04:47:46.993225
1364 04:47:46.993583 ==
1365 04:47:46.996113 Dram Type= 6, Freq= 0, CH_0, rank 1
1366 04:47:46.999296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1367 04:47:46.999751 ==
1368 04:47:47.002687
1369 04:47:47.003145
1370 04:47:47.003507 TX Vref Scan disable
1371 04:47:47.006316 == TX Byte 0 ==
1372 04:47:47.009609 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1373 04:47:47.013184 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1374 04:47:47.016132 == TX Byte 1 ==
1375 04:47:47.019478 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1376 04:47:47.022846 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1377 04:47:47.026518
1378 04:47:47.026858 [DATLAT]
1379 04:47:47.027240 Freq=800, CH0 RK1
1380 04:47:47.027494
1381 04:47:47.029605 DATLAT Default: 0xa
1382 04:47:47.030065 0, 0xFFFF, sum = 0
1383 04:47:47.033103 1, 0xFFFF, sum = 0
1384 04:47:47.033535 2, 0xFFFF, sum = 0
1385 04:47:47.036666 3, 0xFFFF, sum = 0
1386 04:47:47.037100 4, 0xFFFF, sum = 0
1387 04:47:47.040085 5, 0xFFFF, sum = 0
1388 04:47:47.043135 6, 0xFFFF, sum = 0
1389 04:47:47.043468 7, 0xFFFF, sum = 0
1390 04:47:47.046622 8, 0xFFFF, sum = 0
1391 04:47:47.046950 9, 0x0, sum = 1
1392 04:47:47.047207 10, 0x0, sum = 2
1393 04:47:47.049661 11, 0x0, sum = 3
1394 04:47:47.050015 12, 0x0, sum = 4
1395 04:47:47.052939 best_step = 10
1396 04:47:47.053259
1397 04:47:47.053528 ==
1398 04:47:47.056601 Dram Type= 6, Freq= 0, CH_0, rank 1
1399 04:47:47.059746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1400 04:47:47.060067 ==
1401 04:47:47.063652 RX Vref Scan: 0
1402 04:47:47.064081
1403 04:47:47.064343 RX Vref 0 -> 0, step: 1
1404 04:47:47.064586
1405 04:47:47.066600 RX Delay -95 -> 252, step: 8
1406 04:47:47.073499 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1407 04:47:47.076529 iDelay=209, Bit 1, Center 96 (-15 ~ 208) 224
1408 04:47:47.079569 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1409 04:47:47.082935 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1410 04:47:47.086251 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1411 04:47:47.093377 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1412 04:47:47.096963 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1413 04:47:47.099723 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1414 04:47:47.103144 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1415 04:47:47.106221 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1416 04:47:47.113421 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1417 04:47:47.116384 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1418 04:47:47.119700 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1419 04:47:47.123026 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1420 04:47:47.126474 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1421 04:47:47.133004 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1422 04:47:47.133462 ==
1423 04:47:47.136549 Dram Type= 6, Freq= 0, CH_0, rank 1
1424 04:47:47.139826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1425 04:47:47.140389 ==
1426 04:47:47.140753 DQS Delay:
1427 04:47:47.143224 DQS0 = 0, DQS1 = 0
1428 04:47:47.143779 DQM Delay:
1429 04:47:47.146650 DQM0 = 91, DQM1 = 81
1430 04:47:47.147214 DQ Delay:
1431 04:47:47.150073 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =84
1432 04:47:47.153370 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1433 04:47:47.156781 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =80
1434 04:47:47.160071 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =92
1435 04:47:47.160533
1436 04:47:47.160892
1437 04:47:47.166822 [DQSOSCAuto] RK1, (LSB)MR18= 0x401a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
1438 04:47:47.170140 CH0 RK1: MR19=606, MR18=401A
1439 04:47:47.176683 CH0_RK1: MR19=0x606, MR18=0x401A, DQSOSC=393, MR23=63, INC=95, DEC=63
1440 04:47:47.180127 [RxdqsGatingPostProcess] freq 800
1441 04:47:47.186543 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1442 04:47:47.189907 Pre-setting of DQS Precalculation
1443 04:47:47.193106 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1444 04:47:47.193666 ==
1445 04:47:47.196700 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 04:47:47.200164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 04:47:47.200729 ==
1448 04:47:47.206406 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1449 04:47:47.213605 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1450 04:47:47.221825 [CA 0] Center 36 (6~67) winsize 62
1451 04:47:47.225237 [CA 1] Center 36 (6~67) winsize 62
1452 04:47:47.228332 [CA 2] Center 35 (5~65) winsize 61
1453 04:47:47.231515 [CA 3] Center 34 (3~65) winsize 63
1454 04:47:47.235156 [CA 4] Center 34 (4~65) winsize 62
1455 04:47:47.238385 [CA 5] Center 33 (3~64) winsize 62
1456 04:47:47.238861
1457 04:47:47.241823 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1458 04:47:47.242428
1459 04:47:47.245326 [CATrainingPosCal] consider 1 rank data
1460 04:47:47.248311 u2DelayCellTimex100 = 270/100 ps
1461 04:47:47.251918 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1462 04:47:47.255376 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1463 04:47:47.262246 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1464 04:47:47.264819 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1465 04:47:47.268508 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1466 04:47:47.271960 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1467 04:47:47.272541
1468 04:47:47.275183 CA PerBit enable=1, Macro0, CA PI delay=33
1469 04:47:47.275754
1470 04:47:47.278506 [CBTSetCACLKResult] CA Dly = 33
1471 04:47:47.279184 CS Dly: 5 (0~36)
1472 04:47:47.279564 ==
1473 04:47:47.281922 Dram Type= 6, Freq= 0, CH_1, rank 1
1474 04:47:47.288388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1475 04:47:47.288860 ==
1476 04:47:47.291841 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1477 04:47:47.298399 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1478 04:47:47.308112 [CA 0] Center 37 (7~68) winsize 62
1479 04:47:47.311038 [CA 1] Center 37 (6~68) winsize 63
1480 04:47:47.314351 [CA 2] Center 35 (5~66) winsize 62
1481 04:47:47.317933 [CA 3] Center 35 (5~65) winsize 61
1482 04:47:47.321419 [CA 4] Center 34 (4~65) winsize 62
1483 04:47:47.324727 [CA 5] Center 34 (4~65) winsize 62
1484 04:47:47.325303
1485 04:47:47.328153 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1486 04:47:47.328732
1487 04:47:47.331379 [CATrainingPosCal] consider 2 rank data
1488 04:47:47.334637 u2DelayCellTimex100 = 270/100 ps
1489 04:47:47.338264 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1490 04:47:47.341840 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1491 04:47:47.346012 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1492 04:47:47.349870 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1493 04:47:47.353254 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1494 04:47:47.357160 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1495 04:47:47.357737
1496 04:47:47.360817 CA PerBit enable=1, Macro0, CA PI delay=34
1497 04:47:47.361291
1498 04:47:47.364275 [CBTSetCACLKResult] CA Dly = 34
1499 04:47:47.364752 CS Dly: 6 (0~38)
1500 04:47:47.365128
1501 04:47:47.368421 ----->DramcWriteLeveling(PI) begin...
1502 04:47:47.369019 ==
1503 04:47:47.372139 Dram Type= 6, Freq= 0, CH_1, rank 0
1504 04:47:47.378537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1505 04:47:47.379099 ==
1506 04:47:47.381889 Write leveling (Byte 0): 25 => 25
1507 04:47:47.382488 Write leveling (Byte 1): 28 => 28
1508 04:47:47.385269 DramcWriteLeveling(PI) end<-----
1509 04:47:47.385844
1510 04:47:47.386266 ==
1511 04:47:47.388423 Dram Type= 6, Freq= 0, CH_1, rank 0
1512 04:47:47.395282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1513 04:47:47.395867 ==
1514 04:47:47.398499 [Gating] SW mode calibration
1515 04:47:47.405605 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1516 04:47:47.408764 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1517 04:47:47.415248 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1518 04:47:47.418493 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1519 04:47:47.422081 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 04:47:47.425254 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 04:47:47.432162 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 04:47:47.435609 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 04:47:47.438617 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 04:47:47.445272 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 04:47:47.448699 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 04:47:47.452035 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 04:47:47.458891 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 04:47:47.462174 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 04:47:47.465701 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 04:47:47.472490 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 04:47:47.475628 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 04:47:47.478826 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 04:47:47.485539 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 04:47:47.489146 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1535 04:47:47.492388 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 04:47:47.499168 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 04:47:47.502400 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 04:47:47.505471 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 04:47:47.508556 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 04:47:47.515792 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 04:47:47.518509 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 04:47:47.522201 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 04:47:47.528922 0 9 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1544 04:47:47.532000 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 04:47:47.535714 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 04:47:47.542454 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 04:47:47.545399 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 04:47:47.548624 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 04:47:47.555488 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1550 04:47:47.558987 0 10 4 | B1->B0 | 2f2f 2d2d | 0 0 | (0 0) (0 0)
1551 04:47:47.562360 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 04:47:47.569177 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 04:47:47.572504 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 04:47:47.576115 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 04:47:47.582097 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 04:47:47.586243 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 04:47:47.589105 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 04:47:47.592287 0 11 4 | B1->B0 | 3030 3535 | 0 0 | (0 0) (0 0)
1559 04:47:47.599252 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1560 04:47:47.602774 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 04:47:47.606119 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 04:47:47.612987 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 04:47:47.615715 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 04:47:47.618933 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 04:47:47.625763 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1566 04:47:47.629338 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1567 04:47:47.632610 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 04:47:47.639748 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 04:47:47.642653 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 04:47:47.646206 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 04:47:47.649221 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 04:47:47.656091 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 04:47:47.659682 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 04:47:47.662960 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 04:47:47.669688 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 04:47:47.672686 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 04:47:47.675910 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 04:47:47.682804 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 04:47:47.686117 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 04:47:47.689908 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 04:47:47.695878 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1582 04:47:47.699400 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1583 04:47:47.702873 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1584 04:47:47.706465 Total UI for P1: 0, mck2ui 16
1585 04:47:47.709770 best dqsien dly found for B0: ( 0, 14, 2)
1586 04:47:47.712938 Total UI for P1: 0, mck2ui 16
1587 04:47:47.716364 best dqsien dly found for B1: ( 0, 14, 4)
1588 04:47:47.719564 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1589 04:47:47.722729 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1590 04:47:47.723202
1591 04:47:47.726374 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1592 04:47:47.732979 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1593 04:47:47.733558 [Gating] SW calibration Done
1594 04:47:47.733970 ==
1595 04:47:47.736264 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 04:47:47.743135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 04:47:47.743712 ==
1598 04:47:47.744089 RX Vref Scan: 0
1599 04:47:47.744441
1600 04:47:47.746209 RX Vref 0 -> 0, step: 1
1601 04:47:47.746684
1602 04:47:47.749573 RX Delay -130 -> 252, step: 16
1603 04:47:47.752951 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1604 04:47:47.755896 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1605 04:47:47.759480 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1606 04:47:47.765780 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1607 04:47:47.769838 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1608 04:47:47.772444 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1609 04:47:47.776414 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1610 04:47:47.779378 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1611 04:47:47.786229 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1612 04:47:47.789380 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1613 04:47:47.792859 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1614 04:47:47.796472 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1615 04:47:47.799275 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1616 04:47:47.806224 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1617 04:47:47.809765 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1618 04:47:47.812936 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1619 04:47:47.813510 ==
1620 04:47:47.816266 Dram Type= 6, Freq= 0, CH_1, rank 0
1621 04:47:47.819500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1622 04:47:47.819976 ==
1623 04:47:47.823038 DQS Delay:
1624 04:47:47.823610 DQS0 = 0, DQS1 = 0
1625 04:47:47.823989 DQM Delay:
1626 04:47:47.826116 DQM0 = 91, DQM1 = 80
1627 04:47:47.826590 DQ Delay:
1628 04:47:47.829773 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1629 04:47:47.833348 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =93
1630 04:47:47.836658 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1631 04:47:47.839599 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1632 04:47:47.840077
1633 04:47:47.840449
1634 04:47:47.840799 ==
1635 04:47:47.843299 Dram Type= 6, Freq= 0, CH_1, rank 0
1636 04:47:47.849511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1637 04:47:47.850130 ==
1638 04:47:47.850513
1639 04:47:47.850864
1640 04:47:47.851199 TX Vref Scan disable
1641 04:47:47.853555 == TX Byte 0 ==
1642 04:47:47.856651 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1643 04:47:47.859954 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1644 04:47:47.863069 == TX Byte 1 ==
1645 04:47:47.866773 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1646 04:47:47.870195 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1647 04:47:47.873661 ==
1648 04:47:47.876713 Dram Type= 6, Freq= 0, CH_1, rank 0
1649 04:47:47.879879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1650 04:47:47.880362 ==
1651 04:47:47.892995 TX Vref=22, minBit 8, minWin=27, winSum=447
1652 04:47:47.896460 TX Vref=24, minBit 8, minWin=27, winSum=447
1653 04:47:47.899090 TX Vref=26, minBit 8, minWin=27, winSum=451
1654 04:47:47.902948 TX Vref=28, minBit 10, minWin=27, winSum=453
1655 04:47:47.905828 TX Vref=30, minBit 8, minWin=27, winSum=457
1656 04:47:47.909686 TX Vref=32, minBit 8, minWin=27, winSum=449
1657 04:47:47.916365 [TxChooseVref] Worse bit 8, Min win 27, Win sum 457, Final Vref 30
1658 04:47:47.916939
1659 04:47:47.919583 Final TX Range 1 Vref 30
1660 04:47:47.920058
1661 04:47:47.920431 ==
1662 04:47:47.923553 Dram Type= 6, Freq= 0, CH_1, rank 0
1663 04:47:47.926985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1664 04:47:47.927559 ==
1665 04:47:47.927940
1666 04:47:47.928293
1667 04:47:47.930124 TX Vref Scan disable
1668 04:47:47.933719 == TX Byte 0 ==
1669 04:47:47.936738 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1670 04:47:47.940024 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1671 04:47:47.943754 == TX Byte 1 ==
1672 04:47:47.946877 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1673 04:47:47.950259 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1674 04:47:47.950736
1675 04:47:47.953690 [DATLAT]
1676 04:47:47.954307 Freq=800, CH1 RK0
1677 04:47:47.954692
1678 04:47:47.956818 DATLAT Default: 0xa
1679 04:47:47.957288 0, 0xFFFF, sum = 0
1680 04:47:47.960356 1, 0xFFFF, sum = 0
1681 04:47:47.960898 2, 0xFFFF, sum = 0
1682 04:47:47.963279 3, 0xFFFF, sum = 0
1683 04:47:47.963771 4, 0xFFFF, sum = 0
1684 04:47:47.966921 5, 0xFFFF, sum = 0
1685 04:47:47.967559 6, 0xFFFF, sum = 0
1686 04:47:47.970095 7, 0xFFFF, sum = 0
1687 04:47:47.970673 8, 0xFFFF, sum = 0
1688 04:47:47.973439 9, 0x0, sum = 1
1689 04:47:47.973915 10, 0x0, sum = 2
1690 04:47:47.977087 11, 0x0, sum = 3
1691 04:47:47.977676 12, 0x0, sum = 4
1692 04:47:47.978101 best_step = 10
1693 04:47:47.980005
1694 04:47:47.980479 ==
1695 04:47:47.983686 Dram Type= 6, Freq= 0, CH_1, rank 0
1696 04:47:47.987137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1697 04:47:47.987620 ==
1698 04:47:47.988000 RX Vref Scan: 1
1699 04:47:47.988350
1700 04:47:47.990185 Set Vref Range= 32 -> 127
1701 04:47:47.990665
1702 04:47:47.993595 RX Vref 32 -> 127, step: 1
1703 04:47:47.994237
1704 04:47:47.997311 RX Delay -95 -> 252, step: 8
1705 04:47:47.997897
1706 04:47:48.000429 Set Vref, RX VrefLevel [Byte0]: 32
1707 04:47:48.003430 [Byte1]: 32
1708 04:47:48.004021
1709 04:47:48.007510 Set Vref, RX VrefLevel [Byte0]: 33
1710 04:47:48.009990 [Byte1]: 33
1711 04:47:48.010466
1712 04:47:48.013657 Set Vref, RX VrefLevel [Byte0]: 34
1713 04:47:48.017114 [Byte1]: 34
1714 04:47:48.020565
1715 04:47:48.021157 Set Vref, RX VrefLevel [Byte0]: 35
1716 04:47:48.024012 [Byte1]: 35
1717 04:47:48.028233
1718 04:47:48.028833 Set Vref, RX VrefLevel [Byte0]: 36
1719 04:47:48.031598 [Byte1]: 36
1720 04:47:48.035779
1721 04:47:48.036367 Set Vref, RX VrefLevel [Byte0]: 37
1722 04:47:48.039080 [Byte1]: 37
1723 04:47:48.043434
1724 04:47:48.044025 Set Vref, RX VrefLevel [Byte0]: 38
1725 04:47:48.046825 [Byte1]: 38
1726 04:47:48.051096
1727 04:47:48.051683 Set Vref, RX VrefLevel [Byte0]: 39
1728 04:47:48.054670 [Byte1]: 39
1729 04:47:48.058491
1730 04:47:48.059075 Set Vref, RX VrefLevel [Byte0]: 40
1731 04:47:48.061853 [Byte1]: 40
1732 04:47:48.066530
1733 04:47:48.067115 Set Vref, RX VrefLevel [Byte0]: 41
1734 04:47:48.069315 [Byte1]: 41
1735 04:47:48.073606
1736 04:47:48.074243 Set Vref, RX VrefLevel [Byte0]: 42
1737 04:47:48.077176 [Byte1]: 42
1738 04:47:48.081149
1739 04:47:48.081628 Set Vref, RX VrefLevel [Byte0]: 43
1740 04:47:48.084494 [Byte1]: 43
1741 04:47:48.088875
1742 04:47:48.089465 Set Vref, RX VrefLevel [Byte0]: 44
1743 04:47:48.092285 [Byte1]: 44
1744 04:47:48.096597
1745 04:47:48.097172 Set Vref, RX VrefLevel [Byte0]: 45
1746 04:47:48.099630 [Byte1]: 45
1747 04:47:48.104130
1748 04:47:48.104702 Set Vref, RX VrefLevel [Byte0]: 46
1749 04:47:48.107273 [Byte1]: 46
1750 04:47:48.111725
1751 04:47:48.112196 Set Vref, RX VrefLevel [Byte0]: 47
1752 04:47:48.114742 [Byte1]: 47
1753 04:47:48.119469
1754 04:47:48.120116 Set Vref, RX VrefLevel [Byte0]: 48
1755 04:47:48.122654 [Byte1]: 48
1756 04:47:48.126854
1757 04:47:48.127429 Set Vref, RX VrefLevel [Byte0]: 49
1758 04:47:48.129908 [Byte1]: 49
1759 04:47:48.134443
1760 04:47:48.135016 Set Vref, RX VrefLevel [Byte0]: 50
1761 04:47:48.137636 [Byte1]: 50
1762 04:47:48.142291
1763 04:47:48.142862 Set Vref, RX VrefLevel [Byte0]: 51
1764 04:47:48.145735 [Byte1]: 51
1765 04:47:48.149474
1766 04:47:48.150108 Set Vref, RX VrefLevel [Byte0]: 52
1767 04:47:48.153255 [Byte1]: 52
1768 04:47:48.157654
1769 04:47:48.158270 Set Vref, RX VrefLevel [Byte0]: 53
1770 04:47:48.160887 [Byte1]: 53
1771 04:47:48.164538
1772 04:47:48.165005 Set Vref, RX VrefLevel [Byte0]: 54
1773 04:47:48.171289 [Byte1]: 54
1774 04:47:48.171867
1775 04:47:48.174758 Set Vref, RX VrefLevel [Byte0]: 55
1776 04:47:48.178046 [Byte1]: 55
1777 04:47:48.178621
1778 04:47:48.181280 Set Vref, RX VrefLevel [Byte0]: 56
1779 04:47:48.184397 [Byte1]: 56
1780 04:47:48.184866
1781 04:47:48.188188 Set Vref, RX VrefLevel [Byte0]: 57
1782 04:47:48.191369 [Byte1]: 57
1783 04:47:48.195100
1784 04:47:48.195567 Set Vref, RX VrefLevel [Byte0]: 58
1785 04:47:48.198555 [Byte1]: 58
1786 04:47:48.202883
1787 04:47:48.203458 Set Vref, RX VrefLevel [Byte0]: 59
1788 04:47:48.206165 [Byte1]: 59
1789 04:47:48.210152
1790 04:47:48.210620 Set Vref, RX VrefLevel [Byte0]: 60
1791 04:47:48.213743 [Byte1]: 60
1792 04:47:48.217928
1793 04:47:48.218541 Set Vref, RX VrefLevel [Byte0]: 61
1794 04:47:48.221440 [Byte1]: 61
1795 04:47:48.225411
1796 04:47:48.226085 Set Vref, RX VrefLevel [Byte0]: 62
1797 04:47:48.229160 [Byte1]: 62
1798 04:47:48.233651
1799 04:47:48.234280 Set Vref, RX VrefLevel [Byte0]: 63
1800 04:47:48.236532 [Byte1]: 63
1801 04:47:48.240945
1802 04:47:48.241517 Set Vref, RX VrefLevel [Byte0]: 64
1803 04:47:48.244089 [Byte1]: 64
1804 04:47:48.248425
1805 04:47:48.248997 Set Vref, RX VrefLevel [Byte0]: 65
1806 04:47:48.251867 [Byte1]: 65
1807 04:47:48.256082
1808 04:47:48.256651 Set Vref, RX VrefLevel [Byte0]: 66
1809 04:47:48.259177 [Byte1]: 66
1810 04:47:48.263829
1811 04:47:48.264404 Set Vref, RX VrefLevel [Byte0]: 67
1812 04:47:48.266644 [Byte1]: 67
1813 04:47:48.271265
1814 04:47:48.271852 Set Vref, RX VrefLevel [Byte0]: 68
1815 04:47:48.274926 [Byte1]: 68
1816 04:47:48.278712
1817 04:47:48.279312 Set Vref, RX VrefLevel [Byte0]: 69
1818 04:47:48.281831 [Byte1]: 69
1819 04:47:48.286593
1820 04:47:48.287173 Set Vref, RX VrefLevel [Byte0]: 70
1821 04:47:48.289770 [Byte1]: 70
1822 04:47:48.293644
1823 04:47:48.294186 Set Vref, RX VrefLevel [Byte0]: 71
1824 04:47:48.297363 [Byte1]: 71
1825 04:47:48.301319
1826 04:47:48.301786 Set Vref, RX VrefLevel [Byte0]: 72
1827 04:47:48.304486 [Byte1]: 72
1828 04:47:48.308817
1829 04:47:48.309283 Set Vref, RX VrefLevel [Byte0]: 73
1830 04:47:48.312394 [Byte1]: 73
1831 04:47:48.317250
1832 04:47:48.317842 Set Vref, RX VrefLevel [Byte0]: 74
1833 04:47:48.319865 [Byte1]: 74
1834 04:47:48.324339
1835 04:47:48.324913 Final RX Vref Byte 0 = 51 to rank0
1836 04:47:48.327481 Final RX Vref Byte 1 = 63 to rank0
1837 04:47:48.330699 Final RX Vref Byte 0 = 51 to rank1
1838 04:47:48.334043 Final RX Vref Byte 1 = 63 to rank1==
1839 04:47:48.337641 Dram Type= 6, Freq= 0, CH_1, rank 0
1840 04:47:48.344473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1841 04:47:48.345055 ==
1842 04:47:48.345437 DQS Delay:
1843 04:47:48.345787 DQS0 = 0, DQS1 = 0
1844 04:47:48.347692 DQM Delay:
1845 04:47:48.348278 DQM0 = 93, DQM1 = 83
1846 04:47:48.350793 DQ Delay:
1847 04:47:48.354304 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1848 04:47:48.357715 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1849 04:47:48.358279 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =80
1850 04:47:48.364549 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1851 04:47:48.365128
1852 04:47:48.365507
1853 04:47:48.371587 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b48, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1854 04:47:48.374384 CH1 RK0: MR19=606, MR18=2B48
1855 04:47:48.381278 CH1_RK0: MR19=0x606, MR18=0x2B48, DQSOSC=391, MR23=63, INC=96, DEC=64
1856 04:47:48.381924
1857 04:47:48.384931 ----->DramcWriteLeveling(PI) begin...
1858 04:47:48.385513 ==
1859 04:47:48.387928 Dram Type= 6, Freq= 0, CH_1, rank 1
1860 04:47:48.391242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1861 04:47:48.391824 ==
1862 04:47:48.394573 Write leveling (Byte 0): 27 => 27
1863 04:47:48.397977 Write leveling (Byte 1): 32 => 32
1864 04:47:48.401126 DramcWriteLeveling(PI) end<-----
1865 04:47:48.401602
1866 04:47:48.402005 ==
1867 04:47:48.404526 Dram Type= 6, Freq= 0, CH_1, rank 1
1868 04:47:48.408165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1869 04:47:48.408748 ==
1870 04:47:48.411040 [Gating] SW mode calibration
1871 04:47:48.417883 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1872 04:47:48.424445 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1873 04:47:48.428253 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1874 04:47:48.431320 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1875 04:47:48.437891 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 04:47:48.441459 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 04:47:48.445026 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 04:47:48.451803 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 04:47:48.454684 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 04:47:48.458466 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 04:47:48.461238 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 04:47:48.468081 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 04:47:48.471857 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 04:47:48.475128 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 04:47:48.481555 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 04:47:48.485232 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 04:47:48.488574 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 04:47:48.495083 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 04:47:48.498292 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 04:47:48.501876 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1891 04:47:48.508502 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 04:47:48.511565 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 04:47:48.514600 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 04:47:48.521200 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 04:47:48.524811 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 04:47:48.528164 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 04:47:48.534920 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 04:47:48.538540 0 9 4 | B1->B0 | 2524 2323 | 1 0 | (0 0) (0 0)
1899 04:47:48.541411 0 9 8 | B1->B0 | 3333 3030 | 1 1 | (1 1) (1 1)
1900 04:47:48.544842 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 04:47:48.551371 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 04:47:48.554624 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 04:47:48.558459 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 04:47:48.565478 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 04:47:48.568402 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1906 04:47:48.572107 0 10 4 | B1->B0 | 2d2d 2f2f | 1 1 | (1 0) (1 0)
1907 04:47:48.578265 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1908 04:47:48.581633 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 04:47:48.585594 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 04:47:48.591899 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 04:47:48.595334 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 04:47:48.598505 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 04:47:48.605513 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 04:47:48.608872 0 11 4 | B1->B0 | 3535 2727 | 0 0 | (0 0) (0 0)
1915 04:47:48.611848 0 11 8 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
1916 04:47:48.615023 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 04:47:48.622182 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 04:47:48.625254 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 04:47:48.628453 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 04:47:48.635089 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 04:47:48.638356 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1922 04:47:48.641854 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1923 04:47:48.648625 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 04:47:48.651524 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 04:47:48.654801 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 04:47:48.661510 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 04:47:48.664818 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 04:47:48.668282 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 04:47:48.674959 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 04:47:48.678685 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 04:47:48.681662 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 04:47:48.685031 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 04:47:48.691684 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 04:47:48.695226 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 04:47:48.698610 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 04:47:48.705010 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 04:47:48.708412 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 04:47:48.711652 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1939 04:47:48.718626 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1940 04:47:48.721695 Total UI for P1: 0, mck2ui 16
1941 04:47:48.725472 best dqsien dly found for B0: ( 0, 14, 4)
1942 04:47:48.725722 Total UI for P1: 0, mck2ui 16
1943 04:47:48.731699 best dqsien dly found for B1: ( 0, 14, 4)
1944 04:47:48.735393 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1945 04:47:48.738824 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1946 04:47:48.739089
1947 04:47:48.741886 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1948 04:47:48.745680 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1949 04:47:48.748913 [Gating] SW calibration Done
1950 04:47:48.749341 ==
1951 04:47:48.752019 Dram Type= 6, Freq= 0, CH_1, rank 1
1952 04:47:48.755428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1953 04:47:48.755903 ==
1954 04:47:48.759136 RX Vref Scan: 0
1955 04:47:48.759703
1956 04:47:48.760080 RX Vref 0 -> 0, step: 1
1957 04:47:48.760428
1958 04:47:48.762431 RX Delay -130 -> 252, step: 16
1959 04:47:48.765770 iDelay=206, Bit 0, Center 101 (-2 ~ 205) 208
1960 04:47:48.772414 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1961 04:47:48.775735 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1962 04:47:48.779082 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1963 04:47:48.782333 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1964 04:47:48.785573 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1965 04:47:48.789114 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1966 04:47:48.795429 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1967 04:47:48.798837 iDelay=206, Bit 8, Center 69 (-34 ~ 173) 208
1968 04:47:48.802312 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1969 04:47:48.805543 iDelay=206, Bit 10, Center 93 (-18 ~ 205) 224
1970 04:47:48.808901 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1971 04:47:48.815926 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1972 04:47:48.818624 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1973 04:47:48.822190 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1974 04:47:48.825684 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1975 04:47:48.826256 ==
1976 04:47:48.828880 Dram Type= 6, Freq= 0, CH_1, rank 1
1977 04:47:48.835447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1978 04:47:48.836016 ==
1979 04:47:48.836398 DQS Delay:
1980 04:47:48.838877 DQS0 = 0, DQS1 = 0
1981 04:47:48.839353 DQM Delay:
1982 04:47:48.839732 DQM0 = 92, DQM1 = 86
1983 04:47:48.842291 DQ Delay:
1984 04:47:48.846172 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =93
1985 04:47:48.849229 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1986 04:47:48.852173 DQ8 =69, DQ9 =77, DQ10 =93, DQ11 =77
1987 04:47:48.855630 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1988 04:47:48.856216
1989 04:47:48.856594
1990 04:47:48.856947 ==
1991 04:47:48.858615 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 04:47:48.861980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 04:47:48.862461 ==
1994 04:47:48.862842
1995 04:47:48.863192
1996 04:47:48.865360 TX Vref Scan disable
1997 04:47:48.868961 == TX Byte 0 ==
1998 04:47:48.872197 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1999 04:47:48.875661 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2000 04:47:48.879165 == TX Byte 1 ==
2001 04:47:48.882343 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
2002 04:47:48.885664 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
2003 04:47:48.886345 ==
2004 04:47:48.889013 Dram Type= 6, Freq= 0, CH_1, rank 1
2005 04:47:48.892229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2006 04:47:48.892709 ==
2007 04:47:48.907210 TX Vref=22, minBit 13, minWin=27, winSum=453
2008 04:47:48.910665 TX Vref=24, minBit 13, minWin=27, winSum=455
2009 04:47:48.913655 TX Vref=26, minBit 13, minWin=27, winSum=454
2010 04:47:48.916856 TX Vref=28, minBit 1, minWin=28, winSum=460
2011 04:47:48.920460 TX Vref=30, minBit 8, minWin=28, winSum=463
2012 04:47:48.927012 TX Vref=32, minBit 8, minWin=28, winSum=460
2013 04:47:48.930304 [TxChooseVref] Worse bit 8, Min win 28, Win sum 463, Final Vref 30
2014 04:47:48.930878
2015 04:47:48.933545 Final TX Range 1 Vref 30
2016 04:47:48.934083
2017 04:47:48.934477 ==
2018 04:47:48.937043 Dram Type= 6, Freq= 0, CH_1, rank 1
2019 04:47:48.940620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2020 04:47:48.941203 ==
2021 04:47:48.941588
2022 04:47:48.943680
2023 04:47:48.944176 TX Vref Scan disable
2024 04:47:48.946998 == TX Byte 0 ==
2025 04:47:48.950383 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2026 04:47:48.954110 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2027 04:47:48.957095 == TX Byte 1 ==
2028 04:47:48.960169 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
2029 04:47:48.967314 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
2030 04:47:48.967890
2031 04:47:48.968269 [DATLAT]
2032 04:47:48.968622 Freq=800, CH1 RK1
2033 04:47:48.968963
2034 04:47:48.970185 DATLAT Default: 0xa
2035 04:47:48.970662 0, 0xFFFF, sum = 0
2036 04:47:48.973865 1, 0xFFFF, sum = 0
2037 04:47:48.974489 2, 0xFFFF, sum = 0
2038 04:47:48.977264 3, 0xFFFF, sum = 0
2039 04:47:48.977842 4, 0xFFFF, sum = 0
2040 04:47:48.980909 5, 0xFFFF, sum = 0
2041 04:47:48.983615 6, 0xFFFF, sum = 0
2042 04:47:48.984103 7, 0xFFFF, sum = 0
2043 04:47:48.987035 8, 0xFFFF, sum = 0
2044 04:47:48.987632 9, 0x0, sum = 1
2045 04:47:48.988023 10, 0x0, sum = 2
2046 04:47:48.990609 11, 0x0, sum = 3
2047 04:47:48.991192 12, 0x0, sum = 4
2048 04:47:48.993443 best_step = 10
2049 04:47:48.993916
2050 04:47:48.994385 ==
2051 04:47:48.996905 Dram Type= 6, Freq= 0, CH_1, rank 1
2052 04:47:49.000558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2053 04:47:49.001138 ==
2054 04:47:49.003815 RX Vref Scan: 0
2055 04:47:49.004393
2056 04:47:49.004770 RX Vref 0 -> 0, step: 1
2057 04:47:49.005124
2058 04:47:49.007044 RX Delay -79 -> 252, step: 8
2059 04:47:49.013470 iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200
2060 04:47:49.017082 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2061 04:47:49.020594 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2062 04:47:49.023588 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2063 04:47:49.026973 iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208
2064 04:47:49.033902 iDelay=209, Bit 5, Center 104 (1 ~ 208) 208
2065 04:47:49.037386 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2066 04:47:49.040264 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2067 04:47:49.043716 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2068 04:47:49.047116 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2069 04:47:49.050651 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2070 04:47:49.057359 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2071 04:47:49.060529 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2072 04:47:49.063715 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2073 04:47:49.067102 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2074 04:47:49.074131 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
2075 04:47:49.074711 ==
2076 04:47:49.077388 Dram Type= 6, Freq= 0, CH_1, rank 1
2077 04:47:49.080437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2078 04:47:49.081057 ==
2079 04:47:49.081444 DQS Delay:
2080 04:47:49.083576 DQS0 = 0, DQS1 = 0
2081 04:47:49.084050 DQM Delay:
2082 04:47:49.087284 DQM0 = 91, DQM1 = 84
2083 04:47:49.087890 DQ Delay:
2084 04:47:49.090816 DQ0 =92, DQ1 =84, DQ2 =80, DQ3 =88
2085 04:47:49.093742 DQ4 =96, DQ5 =104, DQ6 =96, DQ7 =88
2086 04:47:49.096786 DQ8 =68, DQ9 =76, DQ10 =88, DQ11 =80
2087 04:47:49.100933 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =92
2088 04:47:49.101510
2089 04:47:49.101886
2090 04:47:49.107241 [DQSOSCAuto] RK1, (LSB)MR18= 0x360b, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
2091 04:47:49.110360 CH1 RK1: MR19=606, MR18=360B
2092 04:47:49.117201 CH1_RK1: MR19=0x606, MR18=0x360B, DQSOSC=396, MR23=63, INC=94, DEC=62
2093 04:47:49.120713 [RxdqsGatingPostProcess] freq 800
2094 04:47:49.127444 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2095 04:47:49.128011 Pre-setting of DQS Precalculation
2096 04:47:49.134046 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2097 04:47:49.140875 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2098 04:47:49.147423 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2099 04:47:49.147998
2100 04:47:49.148375
2101 04:47:49.150761 [Calibration Summary] 1600 Mbps
2102 04:47:49.153898 CH 0, Rank 0
2103 04:47:49.154498 SW Impedance : PASS
2104 04:47:49.157389 DUTY Scan : NO K
2105 04:47:49.158009 ZQ Calibration : PASS
2106 04:47:49.160963 Jitter Meter : NO K
2107 04:47:49.163878 CBT Training : PASS
2108 04:47:49.164351 Write leveling : PASS
2109 04:47:49.167100 RX DQS gating : PASS
2110 04:47:49.170685 RX DQ/DQS(RDDQC) : PASS
2111 04:47:49.171260 TX DQ/DQS : PASS
2112 04:47:49.174145 RX DATLAT : PASS
2113 04:47:49.177201 RX DQ/DQS(Engine): PASS
2114 04:47:49.177774 TX OE : NO K
2115 04:47:49.180619 All Pass.
2116 04:47:49.181108
2117 04:47:49.181479 CH 0, Rank 1
2118 04:47:49.184061 SW Impedance : PASS
2119 04:47:49.184528 DUTY Scan : NO K
2120 04:47:49.187104 ZQ Calibration : PASS
2121 04:47:49.190520 Jitter Meter : NO K
2122 04:47:49.190994 CBT Training : PASS
2123 04:47:49.193991 Write leveling : PASS
2124 04:47:49.197582 RX DQS gating : PASS
2125 04:47:49.198212 RX DQ/DQS(RDDQC) : PASS
2126 04:47:49.200854 TX DQ/DQS : PASS
2127 04:47:49.201433 RX DATLAT : PASS
2128 04:47:49.204142 RX DQ/DQS(Engine): PASS
2129 04:47:49.207590 TX OE : NO K
2130 04:47:49.208172 All Pass.
2131 04:47:49.208549
2132 04:47:49.208895 CH 1, Rank 0
2133 04:47:49.210695 SW Impedance : PASS
2134 04:47:49.213860 DUTY Scan : NO K
2135 04:47:49.214510 ZQ Calibration : PASS
2136 04:47:49.217263 Jitter Meter : NO K
2137 04:47:49.220917 CBT Training : PASS
2138 04:47:49.221489 Write leveling : PASS
2139 04:47:49.223934 RX DQS gating : PASS
2140 04:47:49.227141 RX DQ/DQS(RDDQC) : PASS
2141 04:47:49.227611 TX DQ/DQS : PASS
2142 04:47:49.230349 RX DATLAT : PASS
2143 04:47:49.234507 RX DQ/DQS(Engine): PASS
2144 04:47:49.235081 TX OE : NO K
2145 04:47:49.235459 All Pass.
2146 04:47:49.237408
2147 04:47:49.238029 CH 1, Rank 1
2148 04:47:49.240789 SW Impedance : PASS
2149 04:47:49.241367 DUTY Scan : NO K
2150 04:47:49.243747 ZQ Calibration : PASS
2151 04:47:49.244220 Jitter Meter : NO K
2152 04:47:49.247408 CBT Training : PASS
2153 04:47:49.250833 Write leveling : PASS
2154 04:47:49.251418 RX DQS gating : PASS
2155 04:47:49.254103 RX DQ/DQS(RDDQC) : PASS
2156 04:47:49.257690 TX DQ/DQS : PASS
2157 04:47:49.258334 RX DATLAT : PASS
2158 04:47:49.260730 RX DQ/DQS(Engine): PASS
2159 04:47:49.264480 TX OE : NO K
2160 04:47:49.265073 All Pass.
2161 04:47:49.265454
2162 04:47:49.265805 DramC Write-DBI off
2163 04:47:49.267427 PER_BANK_REFRESH: Hybrid Mode
2164 04:47:49.270487 TX_TRACKING: ON
2165 04:47:49.274495 [GetDramInforAfterCalByMRR] Vendor 6.
2166 04:47:49.277440 [GetDramInforAfterCalByMRR] Revision 606.
2167 04:47:49.280778 [GetDramInforAfterCalByMRR] Revision 2 0.
2168 04:47:49.281384 MR0 0x3b3b
2169 04:47:49.283952 MR8 0x5151
2170 04:47:49.287426 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2171 04:47:49.287927
2172 04:47:49.288304 MR0 0x3b3b
2173 04:47:49.288656 MR8 0x5151
2174 04:47:49.294029 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2175 04:47:49.294629
2176 04:47:49.301048 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2177 04:47:49.303715 [FAST_K] Save calibration result to emmc
2178 04:47:49.307420 [FAST_K] Save calibration result to emmc
2179 04:47:49.310654 dram_init: config_dvfs: 1
2180 04:47:49.314157 dramc_set_vcore_voltage set vcore to 662500
2181 04:47:49.317307 Read voltage for 1200, 2
2182 04:47:49.317780 Vio18 = 0
2183 04:47:49.321116 Vcore = 662500
2184 04:47:49.321704 Vdram = 0
2185 04:47:49.322160 Vddq = 0
2186 04:47:49.322526 Vmddr = 0
2187 04:47:49.327393 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2188 04:47:49.334341 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2189 04:47:49.334925 MEM_TYPE=3, freq_sel=15
2190 04:47:49.337389 sv_algorithm_assistance_LP4_1600
2191 04:47:49.341123 ============ PULL DRAM RESETB DOWN ============
2192 04:47:49.347977 ========== PULL DRAM RESETB DOWN end =========
2193 04:47:49.350931 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2194 04:47:49.354328 ===================================
2195 04:47:49.357870 LPDDR4 DRAM CONFIGURATION
2196 04:47:49.361152 ===================================
2197 04:47:49.361738 EX_ROW_EN[0] = 0x0
2198 04:47:49.364525 EX_ROW_EN[1] = 0x0
2199 04:47:49.365109 LP4Y_EN = 0x0
2200 04:47:49.367984 WORK_FSP = 0x0
2201 04:47:49.368572 WL = 0x4
2202 04:47:49.371150 RL = 0x4
2203 04:47:49.371731 BL = 0x2
2204 04:47:49.374316 RPST = 0x0
2205 04:47:49.374792 RD_PRE = 0x0
2206 04:47:49.377569 WR_PRE = 0x1
2207 04:47:49.378192 WR_PST = 0x0
2208 04:47:49.381029 DBI_WR = 0x0
2209 04:47:49.381503 DBI_RD = 0x0
2210 04:47:49.384185 OTF = 0x1
2211 04:47:49.387978 ===================================
2212 04:47:49.391045 ===================================
2213 04:47:49.391630 ANA top config
2214 04:47:49.394156 ===================================
2215 04:47:49.398209 DLL_ASYNC_EN = 0
2216 04:47:49.401158 ALL_SLAVE_EN = 0
2217 04:47:49.404405 NEW_RANK_MODE = 1
2218 04:47:49.404993 DLL_IDLE_MODE = 1
2219 04:47:49.407601 LP45_APHY_COMB_EN = 1
2220 04:47:49.411105 TX_ODT_DIS = 1
2221 04:47:49.414261 NEW_8X_MODE = 1
2222 04:47:49.417546 ===================================
2223 04:47:49.421355 ===================================
2224 04:47:49.424615 data_rate = 2400
2225 04:47:49.425209 CKR = 1
2226 04:47:49.427776 DQ_P2S_RATIO = 8
2227 04:47:49.431151 ===================================
2228 04:47:49.434776 CA_P2S_RATIO = 8
2229 04:47:49.438000 DQ_CA_OPEN = 0
2230 04:47:49.440946 DQ_SEMI_OPEN = 0
2231 04:47:49.444618 CA_SEMI_OPEN = 0
2232 04:47:49.445205 CA_FULL_RATE = 0
2233 04:47:49.448090 DQ_CKDIV4_EN = 0
2234 04:47:49.451092 CA_CKDIV4_EN = 0
2235 04:47:49.454415 CA_PREDIV_EN = 0
2236 04:47:49.457812 PH8_DLY = 17
2237 04:47:49.461116 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2238 04:47:49.461707 DQ_AAMCK_DIV = 4
2239 04:47:49.464502 CA_AAMCK_DIV = 4
2240 04:47:49.468199 CA_ADMCK_DIV = 4
2241 04:47:49.471682 DQ_TRACK_CA_EN = 0
2242 04:47:49.474896 CA_PICK = 1200
2243 04:47:49.478236 CA_MCKIO = 1200
2244 04:47:49.478825 MCKIO_SEMI = 0
2245 04:47:49.481286 PLL_FREQ = 2366
2246 04:47:49.484497 DQ_UI_PI_RATIO = 32
2247 04:47:49.487739 CA_UI_PI_RATIO = 0
2248 04:47:49.491453 ===================================
2249 04:47:49.494727 ===================================
2250 04:47:49.498055 memory_type:LPDDR4
2251 04:47:49.498535 GP_NUM : 10
2252 04:47:49.501699 SRAM_EN : 1
2253 04:47:49.502338 MD32_EN : 0
2254 04:47:49.505007 ===================================
2255 04:47:49.508392 [ANA_INIT] >>>>>>>>>>>>>>
2256 04:47:49.511714 <<<<<< [CONFIGURE PHASE]: ANA_TX
2257 04:47:49.514837 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2258 04:47:49.517931 ===================================
2259 04:47:49.521728 data_rate = 2400,PCW = 0X5b00
2260 04:47:49.524968 ===================================
2261 04:47:49.528152 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2262 04:47:49.534920 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2263 04:47:49.538309 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2264 04:47:49.544904 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2265 04:47:49.548034 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2266 04:47:49.551881 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2267 04:47:49.552472 [ANA_INIT] flow start
2268 04:47:49.555265 [ANA_INIT] PLL >>>>>>>>
2269 04:47:49.558079 [ANA_INIT] PLL <<<<<<<<
2270 04:47:49.558669 [ANA_INIT] MIDPI >>>>>>>>
2271 04:47:49.561915 [ANA_INIT] MIDPI <<<<<<<<
2272 04:47:49.565101 [ANA_INIT] DLL >>>>>>>>
2273 04:47:49.565687 [ANA_INIT] DLL <<<<<<<<
2274 04:47:49.568544 [ANA_INIT] flow end
2275 04:47:49.571842 ============ LP4 DIFF to SE enter ============
2276 04:47:49.575230 ============ LP4 DIFF to SE exit ============
2277 04:47:49.578665 [ANA_INIT] <<<<<<<<<<<<<
2278 04:47:49.581567 [Flow] Enable top DCM control >>>>>
2279 04:47:49.585174 [Flow] Enable top DCM control <<<<<
2280 04:47:49.588246 Enable DLL master slave shuffle
2281 04:47:49.594590 ==============================================================
2282 04:47:49.595083 Gating Mode config
2283 04:47:49.601559 ==============================================================
2284 04:47:49.602181 Config description:
2285 04:47:49.611744 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2286 04:47:49.618075 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2287 04:47:49.624921 SELPH_MODE 0: By rank 1: By Phase
2288 04:47:49.628344 ==============================================================
2289 04:47:49.631540 GAT_TRACK_EN = 1
2290 04:47:49.635072 RX_GATING_MODE = 2
2291 04:47:49.638064 RX_GATING_TRACK_MODE = 2
2292 04:47:49.641639 SELPH_MODE = 1
2293 04:47:49.644970 PICG_EARLY_EN = 1
2294 04:47:49.648284 VALID_LAT_VALUE = 1
2295 04:47:49.652018 ==============================================================
2296 04:47:49.654864 Enter into Gating configuration >>>>
2297 04:47:49.658323 Exit from Gating configuration <<<<
2298 04:47:49.661637 Enter into DVFS_PRE_config >>>>>
2299 04:47:49.674921 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2300 04:47:49.678370 Exit from DVFS_PRE_config <<<<<
2301 04:47:49.682039 Enter into PICG configuration >>>>
2302 04:47:49.682615 Exit from PICG configuration <<<<
2303 04:47:49.684777 [RX_INPUT] configuration >>>>>
2304 04:47:49.688689 [RX_INPUT] configuration <<<<<
2305 04:47:49.694745 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2306 04:47:49.698371 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2307 04:47:49.704899 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2308 04:47:49.712027 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2309 04:47:49.718255 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2310 04:47:49.725174 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2311 04:47:49.728551 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2312 04:47:49.731412 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2313 04:47:49.734874 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2314 04:47:49.741257 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2315 04:47:49.744701 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2316 04:47:49.748473 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2317 04:47:49.751635 ===================================
2318 04:47:49.755466 LPDDR4 DRAM CONFIGURATION
2319 04:47:49.758717 ===================================
2320 04:47:49.759212 EX_ROW_EN[0] = 0x0
2321 04:47:49.761870 EX_ROW_EN[1] = 0x0
2322 04:47:49.765318 LP4Y_EN = 0x0
2323 04:47:49.765905 WORK_FSP = 0x0
2324 04:47:49.768233 WL = 0x4
2325 04:47:49.768719 RL = 0x4
2326 04:47:49.772133 BL = 0x2
2327 04:47:49.772727 RPST = 0x0
2328 04:47:49.775231 RD_PRE = 0x0
2329 04:47:49.775715 WR_PRE = 0x1
2330 04:47:49.778481 WR_PST = 0x0
2331 04:47:49.778986 DBI_WR = 0x0
2332 04:47:49.781995 DBI_RD = 0x0
2333 04:47:49.782577 OTF = 0x1
2334 04:47:49.785068 ===================================
2335 04:47:49.788542 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2336 04:47:49.795419 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2337 04:47:49.798599 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2338 04:47:49.801884 ===================================
2339 04:47:49.805241 LPDDR4 DRAM CONFIGURATION
2340 04:47:49.808519 ===================================
2341 04:47:49.809120 EX_ROW_EN[0] = 0x10
2342 04:47:49.812258 EX_ROW_EN[1] = 0x0
2343 04:47:49.812847 LP4Y_EN = 0x0
2344 04:47:49.815151 WORK_FSP = 0x0
2345 04:47:49.815640 WL = 0x4
2346 04:47:49.818613 RL = 0x4
2347 04:47:49.819151 BL = 0x2
2348 04:47:49.821519 RPST = 0x0
2349 04:47:49.825324 RD_PRE = 0x0
2350 04:47:49.825913 WR_PRE = 0x1
2351 04:47:49.828511 WR_PST = 0x0
2352 04:47:49.829099 DBI_WR = 0x0
2353 04:47:49.831636 DBI_RD = 0x0
2354 04:47:49.832188 OTF = 0x1
2355 04:47:49.835170 ===================================
2356 04:47:49.841823 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2357 04:47:49.842448 ==
2358 04:47:49.845503 Dram Type= 6, Freq= 0, CH_0, rank 0
2359 04:47:49.848713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2360 04:47:49.849327 ==
2361 04:47:49.851865 [Duty_Offset_Calibration]
2362 04:47:49.852439 B0:2 B1:0 CA:1
2363 04:47:49.852938
2364 04:47:49.855135 [DutyScan_Calibration_Flow] k_type=0
2365 04:47:49.865294
2366 04:47:49.865700 ==CLK 0==
2367 04:47:49.868547 Final CLK duty delay cell = -4
2368 04:47:49.871862 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2369 04:47:49.875135 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2370 04:47:49.878429 [-4] AVG Duty = 4953%(X100)
2371 04:47:49.878671
2372 04:47:49.881898 CH0 CLK Duty spec in!! Max-Min= 156%
2373 04:47:49.885068 [DutyScan_Calibration_Flow] ====Done====
2374 04:47:49.885237
2375 04:47:49.888407 [DutyScan_Calibration_Flow] k_type=1
2376 04:47:49.904112
2377 04:47:49.904688 ==DQS 0 ==
2378 04:47:49.907433 Final DQS duty delay cell = 0
2379 04:47:49.911512 [0] MAX Duty = 5187%(X100), DQS PI = 30
2380 04:47:49.914234 [0] MIN Duty = 4938%(X100), DQS PI = 0
2381 04:47:49.914726 [0] AVG Duty = 5062%(X100)
2382 04:47:49.917736
2383 04:47:49.918239 ==DQS 1 ==
2384 04:47:49.920931 Final DQS duty delay cell = -4
2385 04:47:49.924637 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2386 04:47:49.927974 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2387 04:47:49.930764 [-4] AVG Duty = 5015%(X100)
2388 04:47:49.931226
2389 04:47:49.934598 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2390 04:47:49.935173
2391 04:47:49.937846 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2392 04:47:49.940989 [DutyScan_Calibration_Flow] ====Done====
2393 04:47:49.941555
2394 04:47:49.944182 [DutyScan_Calibration_Flow] k_type=3
2395 04:47:49.961079
2396 04:47:49.961646 ==DQM 0 ==
2397 04:47:49.964164 Final DQM duty delay cell = 0
2398 04:47:49.968173 [0] MAX Duty = 5062%(X100), DQS PI = 24
2399 04:47:49.971003 [0] MIN Duty = 4844%(X100), DQS PI = 0
2400 04:47:49.971570 [0] AVG Duty = 4953%(X100)
2401 04:47:49.974806
2402 04:47:49.975364 ==DQM 1 ==
2403 04:47:49.977624 Final DQM duty delay cell = 0
2404 04:47:49.981388 [0] MAX Duty = 5187%(X100), DQS PI = 46
2405 04:47:49.984114 [0] MIN Duty = 5000%(X100), DQS PI = 12
2406 04:47:49.987640 [0] AVG Duty = 5093%(X100)
2407 04:47:49.988200
2408 04:47:49.990879 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2409 04:47:49.991343
2410 04:47:49.994326 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2411 04:47:49.997711 [DutyScan_Calibration_Flow] ====Done====
2412 04:47:49.998298
2413 04:47:50.001100 [DutyScan_Calibration_Flow] k_type=2
2414 04:47:50.017889
2415 04:47:50.018489 ==DQ 0 ==
2416 04:47:50.021033 Final DQ duty delay cell = -4
2417 04:47:50.024535 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2418 04:47:50.027662 [-4] MIN Duty = 4844%(X100), DQS PI = 16
2419 04:47:50.028129 [-4] AVG Duty = 4937%(X100)
2420 04:47:50.031263
2421 04:47:50.031824 ==DQ 1 ==
2422 04:47:50.034464 Final DQ duty delay cell = 4
2423 04:47:50.037813 [4] MAX Duty = 5093%(X100), DQS PI = 4
2424 04:47:50.041026 [4] MIN Duty = 5031%(X100), DQS PI = 16
2425 04:47:50.041510 [4] AVG Duty = 5062%(X100)
2426 04:47:50.042014
2427 04:47:50.044335 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2428 04:47:50.048212
2429 04:47:50.050910 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2430 04:47:50.054881 [DutyScan_Calibration_Flow] ====Done====
2431 04:47:50.055477 ==
2432 04:47:50.057739 Dram Type= 6, Freq= 0, CH_1, rank 0
2433 04:47:50.061587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2434 04:47:50.062231 ==
2435 04:47:50.064739 [Duty_Offset_Calibration]
2436 04:47:50.065229 B0:0 B1:-1 CA:2
2437 04:47:50.065714
2438 04:47:50.067697 [DutyScan_Calibration_Flow] k_type=0
2439 04:47:50.077969
2440 04:47:50.078562 ==CLK 0==
2441 04:47:50.081351 Final CLK duty delay cell = 0
2442 04:47:50.084457 [0] MAX Duty = 5156%(X100), DQS PI = 16
2443 04:47:50.088060 [0] MIN Duty = 4938%(X100), DQS PI = 44
2444 04:47:50.088658 [0] AVG Duty = 5047%(X100)
2445 04:47:50.091425
2446 04:47:50.092011 CH1 CLK Duty spec in!! Max-Min= 218%
2447 04:47:50.097890 [DutyScan_Calibration_Flow] ====Done====
2448 04:47:50.098511
2449 04:47:50.101371 [DutyScan_Calibration_Flow] k_type=1
2450 04:47:50.117511
2451 04:47:50.118135 ==DQS 0 ==
2452 04:47:50.120711 Final DQS duty delay cell = 0
2453 04:47:50.123741 [0] MAX Duty = 5093%(X100), DQS PI = 24
2454 04:47:50.127296 [0] MIN Duty = 4969%(X100), DQS PI = 0
2455 04:47:50.127873 [0] AVG Duty = 5031%(X100)
2456 04:47:50.130805
2457 04:47:50.131277 ==DQS 1 ==
2458 04:47:50.133912 Final DQS duty delay cell = 0
2459 04:47:50.137455 [0] MAX Duty = 5156%(X100), DQS PI = 0
2460 04:47:50.140791 [0] MIN Duty = 4844%(X100), DQS PI = 34
2461 04:47:50.141369 [0] AVG Duty = 5000%(X100)
2462 04:47:50.141811
2463 04:47:50.147424 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2464 04:47:50.148001
2465 04:47:50.150791 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2466 04:47:50.154192 [DutyScan_Calibration_Flow] ====Done====
2467 04:47:50.154803
2468 04:47:50.157344 [DutyScan_Calibration_Flow] k_type=3
2469 04:47:50.173602
2470 04:47:50.174221 ==DQM 0 ==
2471 04:47:50.176979 Final DQM duty delay cell = 4
2472 04:47:50.180452 [4] MAX Duty = 5093%(X100), DQS PI = 6
2473 04:47:50.183836 [4] MIN Duty = 4969%(X100), DQS PI = 28
2474 04:47:50.184413 [4] AVG Duty = 5031%(X100)
2475 04:47:50.187018
2476 04:47:50.187485 ==DQM 1 ==
2477 04:47:50.190638 Final DQM duty delay cell = -4
2478 04:47:50.193538 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2479 04:47:50.197329 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2480 04:47:50.200707 [-4] AVG Duty = 4875%(X100)
2481 04:47:50.201277
2482 04:47:50.203855 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2483 04:47:50.204432
2484 04:47:50.207295 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2485 04:47:50.210656 [DutyScan_Calibration_Flow] ====Done====
2486 04:47:50.211234
2487 04:47:50.213881 [DutyScan_Calibration_Flow] k_type=2
2488 04:47:50.230626
2489 04:47:50.231198 ==DQ 0 ==
2490 04:47:50.233760 Final DQ duty delay cell = 0
2491 04:47:50.237643 [0] MAX Duty = 5062%(X100), DQS PI = 20
2492 04:47:50.241069 [0] MIN Duty = 4938%(X100), DQS PI = 0
2493 04:47:50.241649 [0] AVG Duty = 5000%(X100)
2494 04:47:50.242079
2495 04:47:50.243831 ==DQ 1 ==
2496 04:47:50.244302 Final DQ duty delay cell = 0
2497 04:47:50.250784 [0] MAX Duty = 5031%(X100), DQS PI = 2
2498 04:47:50.254114 [0] MIN Duty = 4813%(X100), DQS PI = 36
2499 04:47:50.254684 [0] AVG Duty = 4922%(X100)
2500 04:47:50.255060
2501 04:47:50.257307 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2502 04:47:50.257884
2503 04:47:50.260608 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2504 04:47:50.267231 [DutyScan_Calibration_Flow] ====Done====
2505 04:47:50.270699 nWR fixed to 30
2506 04:47:50.271270 [ModeRegInit_LP4] CH0 RK0
2507 04:47:50.274067 [ModeRegInit_LP4] CH0 RK1
2508 04:47:50.277526 [ModeRegInit_LP4] CH1 RK0
2509 04:47:50.278146 [ModeRegInit_LP4] CH1 RK1
2510 04:47:50.280629 match AC timing 7
2511 04:47:50.284016 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2512 04:47:50.287246 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2513 04:47:50.294026 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2514 04:47:50.297457 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2515 04:47:50.303879 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2516 04:47:50.304465 ==
2517 04:47:50.307485 Dram Type= 6, Freq= 0, CH_0, rank 0
2518 04:47:50.310725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2519 04:47:50.311203 ==
2520 04:47:50.317337 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2521 04:47:50.320194 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2522 04:47:50.330079 [CA 0] Center 38 (7~69) winsize 63
2523 04:47:50.333712 [CA 1] Center 38 (8~69) winsize 62
2524 04:47:50.337015 [CA 2] Center 35 (5~66) winsize 62
2525 04:47:50.340637 [CA 3] Center 35 (4~66) winsize 63
2526 04:47:50.343503 [CA 4] Center 34 (4~65) winsize 62
2527 04:47:50.346865 [CA 5] Center 33 (3~63) winsize 61
2528 04:47:50.347360
2529 04:47:50.350232 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2530 04:47:50.350707
2531 04:47:50.353712 [CATrainingPosCal] consider 1 rank data
2532 04:47:50.356865 u2DelayCellTimex100 = 270/100 ps
2533 04:47:50.360265 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2534 04:47:50.363860 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2535 04:47:50.367029 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2536 04:47:50.373985 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2537 04:47:50.377392 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2538 04:47:50.380543 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2539 04:47:50.381149
2540 04:47:50.383812 CA PerBit enable=1, Macro0, CA PI delay=33
2541 04:47:50.384565
2542 04:47:50.386795 [CBTSetCACLKResult] CA Dly = 33
2543 04:47:50.387277 CS Dly: 6 (0~37)
2544 04:47:50.387654 ==
2545 04:47:50.390554 Dram Type= 6, Freq= 0, CH_0, rank 1
2546 04:47:50.397508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2547 04:47:50.398144 ==
2548 04:47:50.400317 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2549 04:47:50.407468 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2550 04:47:50.416046 [CA 0] Center 39 (8~70) winsize 63
2551 04:47:50.419377 [CA 1] Center 38 (8~69) winsize 62
2552 04:47:50.422398 [CA 2] Center 35 (5~66) winsize 62
2553 04:47:50.426099 [CA 3] Center 35 (5~66) winsize 62
2554 04:47:50.429169 [CA 4] Center 34 (4~65) winsize 62
2555 04:47:50.433059 [CA 5] Center 34 (4~64) winsize 61
2556 04:47:50.433659
2557 04:47:50.436365 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2558 04:47:50.436942
2559 04:47:50.439624 [CATrainingPosCal] consider 2 rank data
2560 04:47:50.442803 u2DelayCellTimex100 = 270/100 ps
2561 04:47:50.446105 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2562 04:47:50.449808 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2563 04:47:50.453182 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2564 04:47:50.459344 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2565 04:47:50.462967 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2566 04:47:50.465992 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2567 04:47:50.466568
2568 04:47:50.469681 CA PerBit enable=1, Macro0, CA PI delay=33
2569 04:47:50.470302
2570 04:47:50.472897 [CBTSetCACLKResult] CA Dly = 33
2571 04:47:50.473475 CS Dly: 7 (0~39)
2572 04:47:50.473853
2573 04:47:50.476100 ----->DramcWriteLeveling(PI) begin...
2574 04:47:50.476683 ==
2575 04:47:50.480018 Dram Type= 6, Freq= 0, CH_0, rank 0
2576 04:47:50.485915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2577 04:47:50.486527 ==
2578 04:47:50.489438 Write leveling (Byte 0): 32 => 32
2579 04:47:50.492876 Write leveling (Byte 1): 31 => 31
2580 04:47:50.493453 DramcWriteLeveling(PI) end<-----
2581 04:47:50.493834
2582 04:47:50.496067 ==
2583 04:47:50.499143 Dram Type= 6, Freq= 0, CH_0, rank 0
2584 04:47:50.502991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2585 04:47:50.503570 ==
2586 04:47:50.506320 [Gating] SW mode calibration
2587 04:47:50.512744 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2588 04:47:50.516117 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2589 04:47:50.522689 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2590 04:47:50.526119 0 15 4 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
2591 04:47:50.529686 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2592 04:47:50.536034 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 04:47:50.539089 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 04:47:50.542319 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2595 04:47:50.549597 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2596 04:47:50.552924 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
2597 04:47:50.555650 1 0 0 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
2598 04:47:50.562517 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 04:47:50.565746 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 04:47:50.569245 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 04:47:50.576322 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 04:47:50.579205 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 04:47:50.582705 1 0 24 | B1->B0 | 2323 3939 | 0 0 | (0 0) (1 1)
2604 04:47:50.589355 1 0 28 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
2605 04:47:50.592612 1 1 0 | B1->B0 | 2e2e 4646 | 1 0 | (0 0) (0 0)
2606 04:47:50.595607 1 1 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2607 04:47:50.602450 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 04:47:50.606066 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 04:47:50.609083 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 04:47:50.612469 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 04:47:50.619139 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 04:47:50.622446 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2613 04:47:50.626035 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2614 04:47:50.632839 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 04:47:50.635800 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 04:47:50.639087 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 04:47:50.646297 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 04:47:50.649181 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 04:47:50.652822 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 04:47:50.659206 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 04:47:50.663005 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 04:47:50.666062 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 04:47:50.672614 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 04:47:50.676073 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 04:47:50.679353 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 04:47:50.686496 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 04:47:50.689424 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2628 04:47:50.692553 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2629 04:47:50.696555 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2630 04:47:50.699597 Total UI for P1: 0, mck2ui 16
2631 04:47:50.702594 best dqsien dly found for B0: ( 1, 3, 26)
2632 04:47:50.709781 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2633 04:47:50.712602 Total UI for P1: 0, mck2ui 16
2634 04:47:50.715949 best dqsien dly found for B1: ( 1, 4, 0)
2635 04:47:50.719764 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2636 04:47:50.722660 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2637 04:47:50.723376
2638 04:47:50.725734 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2639 04:47:50.729558 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2640 04:47:50.732972 [Gating] SW calibration Done
2641 04:47:50.733566 ==
2642 04:47:50.736012 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 04:47:50.739364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2644 04:47:50.739845 ==
2645 04:47:50.742698 RX Vref Scan: 0
2646 04:47:50.743172
2647 04:47:50.743550 RX Vref 0 -> 0, step: 1
2648 04:47:50.743905
2649 04:47:50.745804 RX Delay -40 -> 252, step: 8
2650 04:47:50.749180 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
2651 04:47:50.755906 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2652 04:47:50.759260 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2653 04:47:50.762532 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2654 04:47:50.765992 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2655 04:47:50.769303 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2656 04:47:50.776071 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2657 04:47:50.779749 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2658 04:47:50.783074 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2659 04:47:50.786012 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2660 04:47:50.789918 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2661 04:47:50.793297 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2662 04:47:50.799719 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2663 04:47:50.803038 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2664 04:47:50.806490 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2665 04:47:50.810026 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2666 04:47:50.810614 ==
2667 04:47:50.812921 Dram Type= 6, Freq= 0, CH_0, rank 0
2668 04:47:50.819982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2669 04:47:50.820565 ==
2670 04:47:50.820949 DQS Delay:
2671 04:47:50.821302 DQS0 = 0, DQS1 = 0
2672 04:47:50.823246 DQM Delay:
2673 04:47:50.823783 DQM0 = 122, DQM1 = 110
2674 04:47:50.826053 DQ Delay:
2675 04:47:50.829613 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2676 04:47:50.833476 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2677 04:47:50.836419 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2678 04:47:50.839977 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2679 04:47:50.840547
2680 04:47:50.840920
2681 04:47:50.841266 ==
2682 04:47:50.843390 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 04:47:50.846431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 04:47:50.846903 ==
2685 04:47:50.847312
2686 04:47:50.849816
2687 04:47:50.850359 TX Vref Scan disable
2688 04:47:50.853237 == TX Byte 0 ==
2689 04:47:50.856856 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2690 04:47:50.859899 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2691 04:47:50.863337 == TX Byte 1 ==
2692 04:47:50.866680 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2693 04:47:50.869974 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2694 04:47:50.870556 ==
2695 04:47:50.873264 Dram Type= 6, Freq= 0, CH_0, rank 0
2696 04:47:50.879961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2697 04:47:50.880544 ==
2698 04:47:50.890388 TX Vref=22, minBit 4, minWin=24, winSum=413
2699 04:47:50.893618 TX Vref=24, minBit 0, minWin=25, winSum=414
2700 04:47:50.897049 TX Vref=26, minBit 0, minWin=25, winSum=414
2701 04:47:50.900078 TX Vref=28, minBit 6, minWin=25, winSum=421
2702 04:47:50.903761 TX Vref=30, minBit 7, minWin=25, winSum=428
2703 04:47:50.907028 TX Vref=32, minBit 1, minWin=25, winSum=422
2704 04:47:50.913827 [TxChooseVref] Worse bit 7, Min win 25, Win sum 428, Final Vref 30
2705 04:47:50.914463
2706 04:47:50.916729 Final TX Range 1 Vref 30
2707 04:47:50.917313
2708 04:47:50.917695 ==
2709 04:47:50.920026 Dram Type= 6, Freq= 0, CH_0, rank 0
2710 04:47:50.923466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2711 04:47:50.923977 ==
2712 04:47:50.924362
2713 04:47:50.926806
2714 04:47:50.927423 TX Vref Scan disable
2715 04:47:50.929936 == TX Byte 0 ==
2716 04:47:50.933656 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2717 04:47:50.936710 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2718 04:47:50.940027 == TX Byte 1 ==
2719 04:47:50.943631 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2720 04:47:50.946748 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2721 04:47:50.947227
2722 04:47:50.950040 [DATLAT]
2723 04:47:50.950517 Freq=1200, CH0 RK0
2724 04:47:50.950899
2725 04:47:50.953814 DATLAT Default: 0xd
2726 04:47:50.954459 0, 0xFFFF, sum = 0
2727 04:47:50.956498 1, 0xFFFF, sum = 0
2728 04:47:50.956979 2, 0xFFFF, sum = 0
2729 04:47:50.960518 3, 0xFFFF, sum = 0
2730 04:47:50.961121 4, 0xFFFF, sum = 0
2731 04:47:50.963711 5, 0xFFFF, sum = 0
2732 04:47:50.964302 6, 0xFFFF, sum = 0
2733 04:47:50.966683 7, 0xFFFF, sum = 0
2734 04:47:50.967169 8, 0xFFFF, sum = 0
2735 04:47:50.970407 9, 0xFFFF, sum = 0
2736 04:47:50.974013 10, 0xFFFF, sum = 0
2737 04:47:50.974606 11, 0xFFFF, sum = 0
2738 04:47:50.974989 12, 0x0, sum = 1
2739 04:47:50.976926 13, 0x0, sum = 2
2740 04:47:50.977518 14, 0x0, sum = 3
2741 04:47:50.980325 15, 0x0, sum = 4
2742 04:47:50.980913 best_step = 13
2743 04:47:50.981294
2744 04:47:50.981647 ==
2745 04:47:50.983625 Dram Type= 6, Freq= 0, CH_0, rank 0
2746 04:47:50.990399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2747 04:47:50.990993 ==
2748 04:47:50.991379 RX Vref Scan: 1
2749 04:47:50.991735
2750 04:47:50.993657 Set Vref Range= 32 -> 127
2751 04:47:50.994282
2752 04:47:50.996979 RX Vref 32 -> 127, step: 1
2753 04:47:50.997566
2754 04:47:51.000327 RX Delay -13 -> 252, step: 4
2755 04:47:51.000917
2756 04:47:51.001312 Set Vref, RX VrefLevel [Byte0]: 32
2757 04:47:51.003434 [Byte1]: 32
2758 04:47:51.008427
2759 04:47:51.011355 Set Vref, RX VrefLevel [Byte0]: 33
2760 04:47:51.011835 [Byte1]: 33
2761 04:47:51.016112
2762 04:47:51.016588 Set Vref, RX VrefLevel [Byte0]: 34
2763 04:47:51.019667 [Byte1]: 34
2764 04:47:51.024200
2765 04:47:51.024675 Set Vref, RX VrefLevel [Byte0]: 35
2766 04:47:51.027378 [Byte1]: 35
2767 04:47:51.032014
2768 04:47:51.032645 Set Vref, RX VrefLevel [Byte0]: 36
2769 04:47:51.035305 [Byte1]: 36
2770 04:47:51.039501
2771 04:47:51.039973 Set Vref, RX VrefLevel [Byte0]: 37
2772 04:47:51.043154 [Byte1]: 37
2773 04:47:51.047866
2774 04:47:51.048454 Set Vref, RX VrefLevel [Byte0]: 38
2775 04:47:51.051312 [Byte1]: 38
2776 04:47:51.055402
2777 04:47:51.055979 Set Vref, RX VrefLevel [Byte0]: 39
2778 04:47:51.058720 [Byte1]: 39
2779 04:47:51.063670
2780 04:47:51.064257 Set Vref, RX VrefLevel [Byte0]: 40
2781 04:47:51.066622 [Byte1]: 40
2782 04:47:51.071639
2783 04:47:51.072245 Set Vref, RX VrefLevel [Byte0]: 41
2784 04:47:51.074863 [Byte1]: 41
2785 04:47:51.079309
2786 04:47:51.079894 Set Vref, RX VrefLevel [Byte0]: 42
2787 04:47:51.082900 [Byte1]: 42
2788 04:47:51.087241
2789 04:47:51.087833 Set Vref, RX VrefLevel [Byte0]: 43
2790 04:47:51.090630 [Byte1]: 43
2791 04:47:51.095469
2792 04:47:51.096058 Set Vref, RX VrefLevel [Byte0]: 44
2793 04:47:51.098340 [Byte1]: 44
2794 04:47:51.103313
2795 04:47:51.103897 Set Vref, RX VrefLevel [Byte0]: 45
2796 04:47:51.106258 [Byte1]: 45
2797 04:47:51.110970
2798 04:47:51.111554 Set Vref, RX VrefLevel [Byte0]: 46
2799 04:47:51.114110 [Byte1]: 46
2800 04:47:51.118619
2801 04:47:51.119092 Set Vref, RX VrefLevel [Byte0]: 47
2802 04:47:51.122244 [Byte1]: 47
2803 04:47:51.126839
2804 04:47:51.127420 Set Vref, RX VrefLevel [Byte0]: 48
2805 04:47:51.130043 [Byte1]: 48
2806 04:47:51.134119
2807 04:47:51.134597 Set Vref, RX VrefLevel [Byte0]: 49
2808 04:47:51.137768 [Byte1]: 49
2809 04:47:51.142291
2810 04:47:51.142874 Set Vref, RX VrefLevel [Byte0]: 50
2811 04:47:51.145712 [Byte1]: 50
2812 04:47:51.150607
2813 04:47:51.151192 Set Vref, RX VrefLevel [Byte0]: 51
2814 04:47:51.153922 [Byte1]: 51
2815 04:47:51.158170
2816 04:47:51.158753 Set Vref, RX VrefLevel [Byte0]: 52
2817 04:47:51.161698 [Byte1]: 52
2818 04:47:51.166304
2819 04:47:51.166900 Set Vref, RX VrefLevel [Byte0]: 53
2820 04:47:51.169155 [Byte1]: 53
2821 04:47:51.174096
2822 04:47:51.174682 Set Vref, RX VrefLevel [Byte0]: 54
2823 04:47:51.177172 [Byte1]: 54
2824 04:47:51.182217
2825 04:47:51.182877 Set Vref, RX VrefLevel [Byte0]: 55
2826 04:47:51.185010 [Byte1]: 55
2827 04:47:51.189756
2828 04:47:51.190376 Set Vref, RX VrefLevel [Byte0]: 56
2829 04:47:51.192706 [Byte1]: 56
2830 04:47:51.197776
2831 04:47:51.198388 Set Vref, RX VrefLevel [Byte0]: 57
2832 04:47:51.201098 [Byte1]: 57
2833 04:47:51.205703
2834 04:47:51.206394 Set Vref, RX VrefLevel [Byte0]: 58
2835 04:47:51.208657 [Byte1]: 58
2836 04:47:51.213116
2837 04:47:51.213593 Set Vref, RX VrefLevel [Byte0]: 59
2838 04:47:51.216752 [Byte1]: 59
2839 04:47:51.221689
2840 04:47:51.222411 Set Vref, RX VrefLevel [Byte0]: 60
2841 04:47:51.224633 [Byte1]: 60
2842 04:47:51.229168
2843 04:47:51.229753 Set Vref, RX VrefLevel [Byte0]: 61
2844 04:47:51.232337 [Byte1]: 61
2845 04:47:51.236924
2846 04:47:51.237396 Set Vref, RX VrefLevel [Byte0]: 62
2847 04:47:51.240217 [Byte1]: 62
2848 04:47:51.245176
2849 04:47:51.245801 Set Vref, RX VrefLevel [Byte0]: 63
2850 04:47:51.248318 [Byte1]: 63
2851 04:47:51.253082
2852 04:47:51.253663 Set Vref, RX VrefLevel [Byte0]: 64
2853 04:47:51.256006 [Byte1]: 64
2854 04:47:51.260883
2855 04:47:51.261468 Set Vref, RX VrefLevel [Byte0]: 65
2856 04:47:51.264220 [Byte1]: 65
2857 04:47:51.268926
2858 04:47:51.269511 Set Vref, RX VrefLevel [Byte0]: 66
2859 04:47:51.272210 [Byte1]: 66
2860 04:47:51.276321
2861 04:47:51.276905 Set Vref, RX VrefLevel [Byte0]: 67
2862 04:47:51.279526 [Byte1]: 67
2863 04:47:51.284341
2864 04:47:51.284928 Set Vref, RX VrefLevel [Byte0]: 68
2865 04:47:51.287631 [Byte1]: 68
2866 04:47:51.292521
2867 04:47:51.293091 Set Vref, RX VrefLevel [Byte0]: 69
2868 04:47:51.295421 [Byte1]: 69
2869 04:47:51.300200
2870 04:47:51.300668 Set Vref, RX VrefLevel [Byte0]: 70
2871 04:47:51.303609 [Byte1]: 70
2872 04:47:51.308189
2873 04:47:51.308766 Final RX Vref Byte 0 = 58 to rank0
2874 04:47:51.311402 Final RX Vref Byte 1 = 48 to rank0
2875 04:47:51.315206 Final RX Vref Byte 0 = 58 to rank1
2876 04:47:51.318063 Final RX Vref Byte 1 = 48 to rank1==
2877 04:47:51.321614 Dram Type= 6, Freq= 0, CH_0, rank 0
2878 04:47:51.324599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2879 04:47:51.328282 ==
2880 04:47:51.328756 DQS Delay:
2881 04:47:51.329130 DQS0 = 0, DQS1 = 0
2882 04:47:51.331498 DQM Delay:
2883 04:47:51.331969 DQM0 = 123, DQM1 = 109
2884 04:47:51.334664 DQ Delay:
2885 04:47:51.338432 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2886 04:47:51.341732 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =130
2887 04:47:51.345266 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =106
2888 04:47:51.348095 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2889 04:47:51.348582
2890 04:47:51.348955
2891 04:47:51.355302 [DQSOSCAuto] RK0, (LSB)MR18= 0xa07, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 406 ps
2892 04:47:51.358345 CH0 RK0: MR19=404, MR18=A07
2893 04:47:51.365366 CH0_RK0: MR19=0x404, MR18=0xA07, DQSOSC=406, MR23=63, INC=39, DEC=26
2894 04:47:51.365976
2895 04:47:51.368626 ----->DramcWriteLeveling(PI) begin...
2896 04:47:51.369212 ==
2897 04:47:51.371456 Dram Type= 6, Freq= 0, CH_0, rank 1
2898 04:47:51.374968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2899 04:47:51.375561 ==
2900 04:47:51.378319 Write leveling (Byte 0): 33 => 33
2901 04:47:51.381410 Write leveling (Byte 1): 29 => 29
2902 04:47:51.384820 DramcWriteLeveling(PI) end<-----
2903 04:47:51.385395
2904 04:47:51.385767 ==
2905 04:47:51.388360 Dram Type= 6, Freq= 0, CH_0, rank 1
2906 04:47:51.392029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2907 04:47:51.395121 ==
2908 04:47:51.395592 [Gating] SW mode calibration
2909 04:47:51.401762 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2910 04:47:51.408497 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2911 04:47:51.411740 0 15 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
2912 04:47:51.418719 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2913 04:47:51.421881 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2914 04:47:51.425240 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2915 04:47:51.431847 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2916 04:47:51.435106 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2917 04:47:51.438902 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2918 04:47:51.444885 0 15 28 | B1->B0 | 3333 2f2f | 0 1 | (1 0) (1 0)
2919 04:47:51.448807 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2920 04:47:51.451660 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2921 04:47:51.455164 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2922 04:47:51.461910 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2923 04:47:51.465264 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2924 04:47:51.468619 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2925 04:47:51.475148 1 0 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2926 04:47:51.478548 1 0 28 | B1->B0 | 3b3b 4343 | 0 1 | (0 0) (0 0)
2927 04:47:51.482049 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2928 04:47:51.488497 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2929 04:47:51.492010 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2930 04:47:51.495117 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2931 04:47:51.502264 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2932 04:47:51.505475 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2933 04:47:51.508557 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2934 04:47:51.515520 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2935 04:47:51.518699 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2936 04:47:51.522244 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 04:47:51.525592 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 04:47:51.531962 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 04:47:51.535102 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 04:47:51.538397 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 04:47:51.545164 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 04:47:51.548787 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 04:47:51.552144 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 04:47:51.558627 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 04:47:51.562311 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 04:47:51.565552 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 04:47:51.572263 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 04:47:51.575769 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 04:47:51.578868 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 04:47:51.585459 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2951 04:47:51.588701 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2952 04:47:51.592226 Total UI for P1: 0, mck2ui 16
2953 04:47:51.595457 best dqsien dly found for B0: ( 1, 3, 28)
2954 04:47:51.598628 Total UI for P1: 0, mck2ui 16
2955 04:47:51.602269 best dqsien dly found for B1: ( 1, 3, 28)
2956 04:47:51.605601 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2957 04:47:51.608845 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2958 04:47:51.609362
2959 04:47:51.612329 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2960 04:47:51.616086 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2961 04:47:51.618949 [Gating] SW calibration Done
2962 04:47:51.619525 ==
2963 04:47:51.622364 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 04:47:51.625595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 04:47:51.626203 ==
2966 04:47:51.628797 RX Vref Scan: 0
2967 04:47:51.629416
2968 04:47:51.629802 RX Vref 0 -> 0, step: 1
2969 04:47:51.632200
2970 04:47:51.632675 RX Delay -40 -> 252, step: 8
2971 04:47:51.638832 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2972 04:47:51.642185 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2973 04:47:51.645652 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2974 04:47:51.649315 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2975 04:47:51.652593 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2976 04:47:51.658801 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2977 04:47:51.662430 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2978 04:47:51.665837 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2979 04:47:51.669053 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2980 04:47:51.672108 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2981 04:47:51.675837 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2982 04:47:51.682512 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2983 04:47:51.685862 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2984 04:47:51.689214 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2985 04:47:51.692448 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2986 04:47:51.695561 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2987 04:47:51.698974 ==
2988 04:47:51.702207 Dram Type= 6, Freq= 0, CH_0, rank 1
2989 04:47:51.705929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2990 04:47:51.706547 ==
2991 04:47:51.706932 DQS Delay:
2992 04:47:51.709288 DQS0 = 0, DQS1 = 0
2993 04:47:51.709882 DQM Delay:
2994 04:47:51.712682 DQM0 = 120, DQM1 = 108
2995 04:47:51.713269 DQ Delay:
2996 04:47:51.715981 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2997 04:47:51.719063 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2998 04:47:51.722802 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2999 04:47:51.726069 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
3000 04:47:51.726654
3001 04:47:51.727034
3002 04:47:51.727390 ==
3003 04:47:51.729001 Dram Type= 6, Freq= 0, CH_0, rank 1
3004 04:47:51.736336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3005 04:47:51.736935 ==
3006 04:47:51.737324
3007 04:47:51.737677
3008 04:47:51.738066 TX Vref Scan disable
3009 04:47:51.739005 == TX Byte 0 ==
3010 04:47:51.742763 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3011 04:47:51.745906 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3012 04:47:51.749383 == TX Byte 1 ==
3013 04:47:51.752778 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3014 04:47:51.756080 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3015 04:47:51.759146 ==
3016 04:47:51.759736 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 04:47:51.766033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 04:47:51.766627 ==
3019 04:47:51.777297 TX Vref=22, minBit 0, minWin=24, winSum=410
3020 04:47:51.780793 TX Vref=24, minBit 0, minWin=25, winSum=419
3021 04:47:51.784105 TX Vref=26, minBit 2, minWin=25, winSum=423
3022 04:47:51.787356 TX Vref=28, minBit 1, minWin=25, winSum=424
3023 04:47:51.790389 TX Vref=30, minBit 1, minWin=25, winSum=425
3024 04:47:51.793653 TX Vref=32, minBit 2, minWin=25, winSum=423
3025 04:47:51.800260 [TxChooseVref] Worse bit 1, Min win 25, Win sum 425, Final Vref 30
3026 04:47:51.800739
3027 04:47:51.803750 Final TX Range 1 Vref 30
3028 04:47:51.804232
3029 04:47:51.804614 ==
3030 04:47:51.807016 Dram Type= 6, Freq= 0, CH_0, rank 1
3031 04:47:51.810398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3032 04:47:51.810877 ==
3033 04:47:51.811257
3034 04:47:51.813911
3035 04:47:51.814412 TX Vref Scan disable
3036 04:47:51.817365 == TX Byte 0 ==
3037 04:47:51.820706 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3038 04:47:51.824136 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3039 04:47:51.827481 == TX Byte 1 ==
3040 04:47:51.830286 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3041 04:47:51.834171 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3042 04:47:51.834761
3043 04:47:51.837228 [DATLAT]
3044 04:47:51.837703 Freq=1200, CH0 RK1
3045 04:47:51.838133
3046 04:47:51.840651 DATLAT Default: 0xd
3047 04:47:51.841183 0, 0xFFFF, sum = 0
3048 04:47:51.843861 1, 0xFFFF, sum = 0
3049 04:47:51.844347 2, 0xFFFF, sum = 0
3050 04:47:51.847103 3, 0xFFFF, sum = 0
3051 04:47:51.847588 4, 0xFFFF, sum = 0
3052 04:47:51.850392 5, 0xFFFF, sum = 0
3053 04:47:51.850874 6, 0xFFFF, sum = 0
3054 04:47:51.853987 7, 0xFFFF, sum = 0
3055 04:47:51.854471 8, 0xFFFF, sum = 0
3056 04:47:51.857049 9, 0xFFFF, sum = 0
3057 04:47:51.857530 10, 0xFFFF, sum = 0
3058 04:47:51.860792 11, 0xFFFF, sum = 0
3059 04:47:51.861274 12, 0x0, sum = 1
3060 04:47:51.864099 13, 0x0, sum = 2
3061 04:47:51.864583 14, 0x0, sum = 3
3062 04:47:51.867459 15, 0x0, sum = 4
3063 04:47:51.867943 best_step = 13
3064 04:47:51.868321
3065 04:47:51.868675 ==
3066 04:47:51.870751 Dram Type= 6, Freq= 0, CH_0, rank 1
3067 04:47:51.877575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3068 04:47:51.878194 ==
3069 04:47:51.878579 RX Vref Scan: 0
3070 04:47:51.878930
3071 04:47:51.880859 RX Vref 0 -> 0, step: 1
3072 04:47:51.881335
3073 04:47:51.884420 RX Delay -21 -> 252, step: 4
3074 04:47:51.887549 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3075 04:47:51.890780 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3076 04:47:51.897739 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3077 04:47:51.901118 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3078 04:47:51.904121 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3079 04:47:51.907534 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3080 04:47:51.911080 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3081 04:47:51.917608 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3082 04:47:51.921009 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3083 04:47:51.924365 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3084 04:47:51.927354 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3085 04:47:51.930734 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3086 04:47:51.934443 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3087 04:47:51.941001 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3088 04:47:51.944494 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3089 04:47:51.947510 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3090 04:47:51.947989 ==
3091 04:47:51.951018 Dram Type= 6, Freq= 0, CH_0, rank 1
3092 04:47:51.954077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3093 04:47:51.957875 ==
3094 04:47:51.958517 DQS Delay:
3095 04:47:51.958903 DQS0 = 0, DQS1 = 0
3096 04:47:51.960597 DQM Delay:
3097 04:47:51.961075 DQM0 = 119, DQM1 = 107
3098 04:47:51.964728 DQ Delay:
3099 04:47:51.967695 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =112
3100 04:47:51.971109 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
3101 04:47:51.974326 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3102 04:47:51.977547 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3103 04:47:51.978055
3104 04:47:51.978434
3105 04:47:51.984177 [DQSOSCAuto] RK1, (LSB)MR18= 0xcf4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
3106 04:47:51.987267 CH0 RK1: MR19=403, MR18=CF4
3107 04:47:51.994107 CH0_RK1: MR19=0x403, MR18=0xCF4, DQSOSC=405, MR23=63, INC=39, DEC=26
3108 04:47:51.997598 [RxdqsGatingPostProcess] freq 1200
3109 04:47:52.000686 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3110 04:47:52.004332 best DQS0 dly(2T, 0.5T) = (0, 11)
3111 04:47:52.007597 best DQS1 dly(2T, 0.5T) = (0, 12)
3112 04:47:52.010851 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3113 04:47:52.014078 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3114 04:47:52.017835 best DQS0 dly(2T, 0.5T) = (0, 11)
3115 04:47:52.020826 best DQS1 dly(2T, 0.5T) = (0, 11)
3116 04:47:52.024154 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3117 04:47:52.027970 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3118 04:47:52.031039 Pre-setting of DQS Precalculation
3119 04:47:52.033913 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3120 04:47:52.034430 ==
3121 04:47:52.037614 Dram Type= 6, Freq= 0, CH_1, rank 0
3122 04:47:52.044506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3123 04:47:52.045106 ==
3124 04:47:52.047942 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3125 04:47:52.054473 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3126 04:47:52.062946 [CA 0] Center 37 (7~68) winsize 62
3127 04:47:52.066485 [CA 1] Center 37 (7~68) winsize 62
3128 04:47:52.070035 [CA 2] Center 35 (5~65) winsize 61
3129 04:47:52.072890 [CA 3] Center 34 (4~65) winsize 62
3130 04:47:52.076405 [CA 4] Center 34 (4~64) winsize 61
3131 04:47:52.079772 [CA 5] Center 33 (3~64) winsize 62
3132 04:47:52.080360
3133 04:47:52.083156 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3134 04:47:52.083747
3135 04:47:52.086392 [CATrainingPosCal] consider 1 rank data
3136 04:47:52.089863 u2DelayCellTimex100 = 270/100 ps
3137 04:47:52.093448 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3138 04:47:52.096573 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3139 04:47:52.103763 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3140 04:47:52.106400 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3141 04:47:52.109898 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3142 04:47:52.113058 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3143 04:47:52.113692
3144 04:47:52.117012 CA PerBit enable=1, Macro0, CA PI delay=33
3145 04:47:52.117604
3146 04:47:52.119986 [CBTSetCACLKResult] CA Dly = 33
3147 04:47:52.120466 CS Dly: 5 (0~36)
3148 04:47:52.120844 ==
3149 04:47:52.123653 Dram Type= 6, Freq= 0, CH_1, rank 1
3150 04:47:52.130280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3151 04:47:52.130905 ==
3152 04:47:52.133414 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3153 04:47:52.140139 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3154 04:47:52.148739 [CA 0] Center 38 (8~68) winsize 61
3155 04:47:52.152243 [CA 1] Center 38 (8~68) winsize 61
3156 04:47:52.155515 [CA 2] Center 35 (5~66) winsize 62
3157 04:47:52.158766 [CA 3] Center 34 (4~65) winsize 62
3158 04:47:52.161975 [CA 4] Center 35 (5~65) winsize 61
3159 04:47:52.165429 [CA 5] Center 34 (4~65) winsize 62
3160 04:47:52.166091
3161 04:47:52.168874 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3162 04:47:52.169351
3163 04:47:52.172352 [CATrainingPosCal] consider 2 rank data
3164 04:47:52.175526 u2DelayCellTimex100 = 270/100 ps
3165 04:47:52.178677 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3166 04:47:52.182254 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3167 04:47:52.188710 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3168 04:47:52.192125 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3169 04:47:52.195283 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
3170 04:47:52.198890 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3171 04:47:52.199469
3172 04:47:52.202061 CA PerBit enable=1, Macro0, CA PI delay=34
3173 04:47:52.202540
3174 04:47:52.205283 [CBTSetCACLKResult] CA Dly = 34
3175 04:47:52.205761 CS Dly: 6 (0~39)
3176 04:47:52.206180
3177 04:47:52.208555 ----->DramcWriteLeveling(PI) begin...
3178 04:47:52.212102 ==
3179 04:47:52.212678 Dram Type= 6, Freq= 0, CH_1, rank 0
3180 04:47:52.218951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3181 04:47:52.219514 ==
3182 04:47:52.222472 Write leveling (Byte 0): 25 => 25
3183 04:47:52.225529 Write leveling (Byte 1): 27 => 27
3184 04:47:52.228745 DramcWriteLeveling(PI) end<-----
3185 04:47:52.229224
3186 04:47:52.229671 ==
3187 04:47:52.232110 Dram Type= 6, Freq= 0, CH_1, rank 0
3188 04:47:52.235572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3189 04:47:52.236052 ==
3190 04:47:52.239173 [Gating] SW mode calibration
3191 04:47:52.245861 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3192 04:47:52.249136 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3193 04:47:52.255679 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3194 04:47:52.258941 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3195 04:47:52.262511 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3196 04:47:52.268863 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3197 04:47:52.272583 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3198 04:47:52.275446 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3199 04:47:52.282180 0 15 24 | B1->B0 | 3030 2929 | 1 1 | (1 0) (1 0)
3200 04:47:52.285663 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3201 04:47:52.289132 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3202 04:47:52.295504 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3203 04:47:52.298902 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3204 04:47:52.302521 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3205 04:47:52.309168 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3206 04:47:52.312121 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3207 04:47:52.315686 1 0 24 | B1->B0 | 4040 4242 | 0 0 | (0 0) (0 0)
3208 04:47:52.318957 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 04:47:52.325672 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 04:47:52.328839 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3211 04:47:52.332024 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 04:47:52.338980 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3213 04:47:52.342263 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3214 04:47:52.345603 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3215 04:47:52.352344 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3216 04:47:52.355828 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3217 04:47:52.359460 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 04:47:52.365707 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 04:47:52.369224 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 04:47:52.372657 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 04:47:52.378879 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 04:47:52.382467 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 04:47:52.385742 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 04:47:52.392556 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 04:47:52.395418 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 04:47:52.398919 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 04:47:52.402217 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 04:47:52.409437 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 04:47:52.412191 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 04:47:52.415907 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3231 04:47:52.422473 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3232 04:47:52.425821 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3233 04:47:52.429285 Total UI for P1: 0, mck2ui 16
3234 04:47:52.432575 best dqsien dly found for B0: ( 1, 3, 22)
3235 04:47:52.435990 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3236 04:47:52.439259 Total UI for P1: 0, mck2ui 16
3237 04:47:52.442663 best dqsien dly found for B1: ( 1, 3, 26)
3238 04:47:52.446336 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3239 04:47:52.449118 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3240 04:47:52.449700
3241 04:47:52.456452 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3242 04:47:52.459592 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3243 04:47:52.460177 [Gating] SW calibration Done
3244 04:47:52.462633 ==
3245 04:47:52.463267 Dram Type= 6, Freq= 0, CH_1, rank 0
3246 04:47:52.469530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3247 04:47:52.470155 ==
3248 04:47:52.470542 RX Vref Scan: 0
3249 04:47:52.470898
3250 04:47:52.472718 RX Vref 0 -> 0, step: 1
3251 04:47:52.473193
3252 04:47:52.476039 RX Delay -40 -> 252, step: 8
3253 04:47:52.479368 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3254 04:47:52.482590 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3255 04:47:52.485861 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3256 04:47:52.492492 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3257 04:47:52.495870 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3258 04:47:52.499072 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3259 04:47:52.502417 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3260 04:47:52.505771 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3261 04:47:52.509757 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3262 04:47:52.516141 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3263 04:47:52.519330 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3264 04:47:52.522830 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3265 04:47:52.526358 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3266 04:47:52.529798 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3267 04:47:52.536122 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3268 04:47:52.539384 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3269 04:47:52.539867 ==
3270 04:47:52.543132 Dram Type= 6, Freq= 0, CH_1, rank 0
3271 04:47:52.546451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3272 04:47:52.546931 ==
3273 04:47:52.549422 DQS Delay:
3274 04:47:52.549898 DQS0 = 0, DQS1 = 0
3275 04:47:52.550309 DQM Delay:
3276 04:47:52.552935 DQM0 = 120, DQM1 = 112
3277 04:47:52.553521 DQ Delay:
3278 04:47:52.556240 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3279 04:47:52.559312 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =123
3280 04:47:52.562999 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3281 04:47:52.569609 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3282 04:47:52.570427
3283 04:47:52.570832
3284 04:47:52.571185 ==
3285 04:47:52.572892 Dram Type= 6, Freq= 0, CH_1, rank 0
3286 04:47:52.576420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3287 04:47:52.577012 ==
3288 04:47:52.577398
3289 04:47:52.577749
3290 04:47:52.579470 TX Vref Scan disable
3291 04:47:52.579945 == TX Byte 0 ==
3292 04:47:52.586236 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3293 04:47:52.589648 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3294 04:47:52.590253 == TX Byte 1 ==
3295 04:47:52.596507 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3296 04:47:52.600168 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3297 04:47:52.600768 ==
3298 04:47:52.603310 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 04:47:52.606205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 04:47:52.606689 ==
3301 04:47:52.618806 TX Vref=22, minBit 10, minWin=24, winSum=405
3302 04:47:52.622579 TX Vref=24, minBit 15, minWin=24, winSum=409
3303 04:47:52.625185 TX Vref=26, minBit 8, minWin=25, winSum=417
3304 04:47:52.628833 TX Vref=28, minBit 10, minWin=25, winSum=421
3305 04:47:52.632264 TX Vref=30, minBit 8, minWin=25, winSum=422
3306 04:47:52.638699 TX Vref=32, minBit 14, minWin=25, winSum=423
3307 04:47:52.642023 [TxChooseVref] Worse bit 14, Min win 25, Win sum 423, Final Vref 32
3308 04:47:52.642504
3309 04:47:52.645477 Final TX Range 1 Vref 32
3310 04:47:52.646095
3311 04:47:52.646498 ==
3312 04:47:52.648775 Dram Type= 6, Freq= 0, CH_1, rank 0
3313 04:47:52.652239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3314 04:47:52.655316 ==
3315 04:47:52.655798
3316 04:47:52.656172
3317 04:47:52.656521 TX Vref Scan disable
3318 04:47:52.658622 == TX Byte 0 ==
3319 04:47:52.661926 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3320 04:47:52.665539 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3321 04:47:52.668824 == TX Byte 1 ==
3322 04:47:52.672471 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3323 04:47:52.675466 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3324 04:47:52.679012
3325 04:47:52.679583 [DATLAT]
3326 04:47:52.679962 Freq=1200, CH1 RK0
3327 04:47:52.680315
3328 04:47:52.682248 DATLAT Default: 0xd
3329 04:47:52.682726 0, 0xFFFF, sum = 0
3330 04:47:52.685448 1, 0xFFFF, sum = 0
3331 04:47:52.686075 2, 0xFFFF, sum = 0
3332 04:47:52.689109 3, 0xFFFF, sum = 0
3333 04:47:52.689708 4, 0xFFFF, sum = 0
3334 04:47:52.692101 5, 0xFFFF, sum = 0
3335 04:47:52.695217 6, 0xFFFF, sum = 0
3336 04:47:52.695701 7, 0xFFFF, sum = 0
3337 04:47:52.698562 8, 0xFFFF, sum = 0
3338 04:47:52.699045 9, 0xFFFF, sum = 0
3339 04:47:52.702317 10, 0xFFFF, sum = 0
3340 04:47:52.702906 11, 0xFFFF, sum = 0
3341 04:47:52.705673 12, 0x0, sum = 1
3342 04:47:52.706238 13, 0x0, sum = 2
3343 04:47:52.708658 14, 0x0, sum = 3
3344 04:47:52.709138 15, 0x0, sum = 4
3345 04:47:52.709526 best_step = 13
3346 04:47:52.709879
3347 04:47:52.712157 ==
3348 04:47:52.715506 Dram Type= 6, Freq= 0, CH_1, rank 0
3349 04:47:52.718930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3350 04:47:52.719414 ==
3351 04:47:52.719792 RX Vref Scan: 1
3352 04:47:52.720146
3353 04:47:52.722039 Set Vref Range= 32 -> 127
3354 04:47:52.722516
3355 04:47:52.725919 RX Vref 32 -> 127, step: 1
3356 04:47:52.726566
3357 04:47:52.728873 RX Delay -13 -> 252, step: 4
3358 04:47:52.729447
3359 04:47:52.731877 Set Vref, RX VrefLevel [Byte0]: 32
3360 04:47:52.735079 [Byte1]: 32
3361 04:47:52.735599
3362 04:47:52.738454 Set Vref, RX VrefLevel [Byte0]: 33
3363 04:47:52.742059 [Byte1]: 33
3364 04:47:52.742525
3365 04:47:52.745586 Set Vref, RX VrefLevel [Byte0]: 34
3366 04:47:52.748445 [Byte1]: 34
3367 04:47:52.752821
3368 04:47:52.753286 Set Vref, RX VrefLevel [Byte0]: 35
3369 04:47:52.756708 [Byte1]: 35
3370 04:47:52.761033
3371 04:47:52.761596 Set Vref, RX VrefLevel [Byte0]: 36
3372 04:47:52.764371 [Byte1]: 36
3373 04:47:52.768900
3374 04:47:52.769370 Set Vref, RX VrefLevel [Byte0]: 37
3375 04:47:52.772322 [Byte1]: 37
3376 04:47:52.776824
3377 04:47:52.777464 Set Vref, RX VrefLevel [Byte0]: 38
3378 04:47:52.780190 [Byte1]: 38
3379 04:47:52.784895
3380 04:47:52.785461 Set Vref, RX VrefLevel [Byte0]: 39
3381 04:47:52.787660 [Byte1]: 39
3382 04:47:52.792184
3383 04:47:52.795411 Set Vref, RX VrefLevel [Byte0]: 40
3384 04:47:52.795879 [Byte1]: 40
3385 04:47:52.799943
3386 04:47:52.800406 Set Vref, RX VrefLevel [Byte0]: 41
3387 04:47:52.803657 [Byte1]: 41
3388 04:47:52.808106
3389 04:47:52.808590 Set Vref, RX VrefLevel [Byte0]: 42
3390 04:47:52.811439 [Byte1]: 42
3391 04:47:52.816088
3392 04:47:52.816550 Set Vref, RX VrefLevel [Byte0]: 43
3393 04:47:52.819448 [Byte1]: 43
3394 04:47:52.823843
3395 04:47:52.824305 Set Vref, RX VrefLevel [Byte0]: 44
3396 04:47:52.827286 [Byte1]: 44
3397 04:47:52.831723
3398 04:47:52.832403 Set Vref, RX VrefLevel [Byte0]: 45
3399 04:47:52.834970 [Byte1]: 45
3400 04:47:52.839624
3401 04:47:52.840110 Set Vref, RX VrefLevel [Byte0]: 46
3402 04:47:52.843154 [Byte1]: 46
3403 04:47:52.847318
3404 04:47:52.847773 Set Vref, RX VrefLevel [Byte0]: 47
3405 04:47:52.850634 [Byte1]: 47
3406 04:47:52.855925
3407 04:47:52.856483 Set Vref, RX VrefLevel [Byte0]: 48
3408 04:47:52.858671 [Byte1]: 48
3409 04:47:52.863380
3410 04:47:52.863942 Set Vref, RX VrefLevel [Byte0]: 49
3411 04:47:52.866576 [Byte1]: 49
3412 04:47:52.871671
3413 04:47:52.872225 Set Vref, RX VrefLevel [Byte0]: 50
3414 04:47:52.874502 [Byte1]: 50
3415 04:47:52.879144
3416 04:47:52.879704 Set Vref, RX VrefLevel [Byte0]: 51
3417 04:47:52.882401 [Byte1]: 51
3418 04:47:52.887038
3419 04:47:52.887599 Set Vref, RX VrefLevel [Byte0]: 52
3420 04:47:52.890412 [Byte1]: 52
3421 04:47:52.895071
3422 04:47:52.895533 Set Vref, RX VrefLevel [Byte0]: 53
3423 04:47:52.898455 [Byte1]: 53
3424 04:47:52.903384
3425 04:47:52.903940 Set Vref, RX VrefLevel [Byte0]: 54
3426 04:47:52.906251 [Byte1]: 54
3427 04:47:52.910529
3428 04:47:52.910984 Set Vref, RX VrefLevel [Byte0]: 55
3429 04:47:52.914079 [Byte1]: 55
3430 04:47:52.918567
3431 04:47:52.919130 Set Vref, RX VrefLevel [Byte0]: 56
3432 04:47:52.921707 [Byte1]: 56
3433 04:47:52.926769
3434 04:47:52.927335 Set Vref, RX VrefLevel [Byte0]: 57
3435 04:47:52.930054 [Byte1]: 57
3436 04:47:52.934394
3437 04:47:52.934974 Set Vref, RX VrefLevel [Byte0]: 58
3438 04:47:52.937553 [Byte1]: 58
3439 04:47:52.942331
3440 04:47:52.942899 Set Vref, RX VrefLevel [Byte0]: 59
3441 04:47:52.945771 [Byte1]: 59
3442 04:47:52.950163
3443 04:47:52.950719 Set Vref, RX VrefLevel [Byte0]: 60
3444 04:47:52.953738 [Byte1]: 60
3445 04:47:52.958160
3446 04:47:52.958723 Set Vref, RX VrefLevel [Byte0]: 61
3447 04:47:52.961523 [Byte1]: 61
3448 04:47:52.966006
3449 04:47:52.966574 Set Vref, RX VrefLevel [Byte0]: 62
3450 04:47:52.969446 [Byte1]: 62
3451 04:47:52.974091
3452 04:47:52.974656 Set Vref, RX VrefLevel [Byte0]: 63
3453 04:47:52.977320 [Byte1]: 63
3454 04:47:52.981827
3455 04:47:52.982419 Set Vref, RX VrefLevel [Byte0]: 64
3456 04:47:52.985270 [Byte1]: 64
3457 04:47:52.990012
3458 04:47:52.990566 Set Vref, RX VrefLevel [Byte0]: 65
3459 04:47:52.992833 [Byte1]: 65
3460 04:47:52.997576
3461 04:47:52.998162 Set Vref, RX VrefLevel [Byte0]: 66
3462 04:47:53.001173 [Byte1]: 66
3463 04:47:53.005875
3464 04:47:53.006518 Set Vref, RX VrefLevel [Byte0]: 67
3465 04:47:53.008788 [Byte1]: 67
3466 04:47:53.013463
3467 04:47:53.013927 Final RX Vref Byte 0 = 50 to rank0
3468 04:47:53.016577 Final RX Vref Byte 1 = 52 to rank0
3469 04:47:53.020189 Final RX Vref Byte 0 = 50 to rank1
3470 04:47:53.023241 Final RX Vref Byte 1 = 52 to rank1==
3471 04:47:53.026702 Dram Type= 6, Freq= 0, CH_1, rank 0
3472 04:47:53.033549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3473 04:47:53.034171 ==
3474 04:47:53.034555 DQS Delay:
3475 04:47:53.034907 DQS0 = 0, DQS1 = 0
3476 04:47:53.036683 DQM Delay:
3477 04:47:53.037153 DQM0 = 119, DQM1 = 111
3478 04:47:53.039886 DQ Delay:
3479 04:47:53.043064 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =116
3480 04:47:53.046568 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =116
3481 04:47:53.049873 DQ8 =100, DQ9 =100, DQ10 =114, DQ11 =106
3482 04:47:53.053284 DQ12 =122, DQ13 =116, DQ14 =118, DQ15 =116
3483 04:47:53.053860
3484 04:47:53.054305
3485 04:47:53.062804 [DQSOSCAuto] RK0, (LSB)MR18= 0x418, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 408 ps
3486 04:47:53.063375 CH1 RK0: MR19=404, MR18=418
3487 04:47:53.069883 CH1_RK0: MR19=0x404, MR18=0x418, DQSOSC=400, MR23=63, INC=40, DEC=27
3488 04:47:53.070501
3489 04:47:53.073268 ----->DramcWriteLeveling(PI) begin...
3490 04:47:53.073844 ==
3491 04:47:53.076646 Dram Type= 6, Freq= 0, CH_1, rank 1
3492 04:47:53.080097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3493 04:47:53.083570 ==
3494 04:47:53.084145 Write leveling (Byte 0): 25 => 25
3495 04:47:53.086674 Write leveling (Byte 1): 29 => 29
3496 04:47:53.089911 DramcWriteLeveling(PI) end<-----
3497 04:47:53.090520
3498 04:47:53.090897 ==
3499 04:47:53.093385 Dram Type= 6, Freq= 0, CH_1, rank 1
3500 04:47:53.100274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3501 04:47:53.100849 ==
3502 04:47:53.101269 [Gating] SW mode calibration
3503 04:47:53.109904 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3504 04:47:53.113501 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3505 04:47:53.116786 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3506 04:47:53.123235 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3507 04:47:53.126537 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3508 04:47:53.130007 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3509 04:47:53.136548 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3510 04:47:53.140400 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3511 04:47:53.143275 0 15 24 | B1->B0 | 2929 3333 | 0 1 | (1 0) (1 0)
3512 04:47:53.150139 0 15 28 | B1->B0 | 2323 2e2e | 0 0 | (1 0) (0 0)
3513 04:47:53.153990 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3514 04:47:53.157216 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3515 04:47:53.163874 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3516 04:47:53.166956 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3517 04:47:53.170137 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3518 04:47:53.173760 1 0 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
3519 04:47:53.180358 1 0 24 | B1->B0 | 3f3f 2e2e | 0 1 | (1 1) (0 0)
3520 04:47:53.183817 1 0 28 | B1->B0 | 4646 3f3e | 0 1 | (0 0) (0 0)
3521 04:47:53.187056 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 04:47:53.193599 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3523 04:47:53.197032 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 04:47:53.200315 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 04:47:53.206918 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 04:47:53.210247 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 04:47:53.213871 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3528 04:47:53.220485 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3529 04:47:53.223661 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 04:47:53.227108 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 04:47:53.233560 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 04:47:53.236653 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 04:47:53.240223 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 04:47:53.246655 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 04:47:53.250067 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 04:47:53.253633 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 04:47:53.257187 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 04:47:53.263385 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 04:47:53.267206 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 04:47:53.270353 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 04:47:53.276964 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 04:47:53.280519 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 04:47:53.283948 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3544 04:47:53.290267 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3545 04:47:53.293432 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3546 04:47:53.296597 Total UI for P1: 0, mck2ui 16
3547 04:47:53.300356 best dqsien dly found for B0: ( 1, 3, 26)
3548 04:47:53.303315 Total UI for P1: 0, mck2ui 16
3549 04:47:53.307123 best dqsien dly found for B1: ( 1, 3, 26)
3550 04:47:53.310133 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3551 04:47:53.313754 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3552 04:47:53.314367
3553 04:47:53.316496 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3554 04:47:53.320456 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3555 04:47:53.323455 [Gating] SW calibration Done
3556 04:47:53.323925 ==
3557 04:47:53.327159 Dram Type= 6, Freq= 0, CH_1, rank 1
3558 04:47:53.333298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3559 04:47:53.333876 ==
3560 04:47:53.334306 RX Vref Scan: 0
3561 04:47:53.334661
3562 04:47:53.336599 RX Vref 0 -> 0, step: 1
3563 04:47:53.337068
3564 04:47:53.340097 RX Delay -40 -> 252, step: 8
3565 04:47:53.343340 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3566 04:47:53.346280 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3567 04:47:53.350046 iDelay=200, Bit 2, Center 107 (48 ~ 167) 120
3568 04:47:53.353520 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3569 04:47:53.359511 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3570 04:47:53.362842 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3571 04:47:53.366817 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3572 04:47:53.369924 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3573 04:47:53.372846 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3574 04:47:53.379827 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3575 04:47:53.383330 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3576 04:47:53.386670 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3577 04:47:53.390242 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3578 04:47:53.393310 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3579 04:47:53.400231 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3580 04:47:53.403064 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3581 04:47:53.403644 ==
3582 04:47:53.406516 Dram Type= 6, Freq= 0, CH_1, rank 1
3583 04:47:53.410031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3584 04:47:53.410640 ==
3585 04:47:53.413159 DQS Delay:
3586 04:47:53.413739 DQS0 = 0, DQS1 = 0
3587 04:47:53.414173 DQM Delay:
3588 04:47:53.416579 DQM0 = 119, DQM1 = 113
3589 04:47:53.417158 DQ Delay:
3590 04:47:53.419689 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3591 04:47:53.422868 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3592 04:47:53.429816 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3593 04:47:53.432779 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3594 04:47:53.433357
3595 04:47:53.433775
3596 04:47:53.434182 ==
3597 04:47:53.436275 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 04:47:53.439574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 04:47:53.440183 ==
3600 04:47:53.440615
3601 04:47:53.440967
3602 04:47:53.442688 TX Vref Scan disable
3603 04:47:53.443175 == TX Byte 0 ==
3604 04:47:53.449605 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3605 04:47:53.452725 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3606 04:47:53.453305 == TX Byte 1 ==
3607 04:47:53.459928 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3608 04:47:53.462560 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3609 04:47:53.463029 ==
3610 04:47:53.466489 Dram Type= 6, Freq= 0, CH_1, rank 1
3611 04:47:53.469888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3612 04:47:53.470506 ==
3613 04:47:53.482701 TX Vref=22, minBit 11, minWin=24, winSum=415
3614 04:47:53.485844 TX Vref=24, minBit 1, minWin=25, winSum=419
3615 04:47:53.489141 TX Vref=26, minBit 0, minWin=26, winSum=424
3616 04:47:53.492395 TX Vref=28, minBit 9, minWin=25, winSum=426
3617 04:47:53.495910 TX Vref=30, minBit 8, minWin=26, winSum=429
3618 04:47:53.502520 TX Vref=32, minBit 0, minWin=26, winSum=427
3619 04:47:53.505791 [TxChooseVref] Worse bit 8, Min win 26, Win sum 429, Final Vref 30
3620 04:47:53.506406
3621 04:47:53.509207 Final TX Range 1 Vref 30
3622 04:47:53.509783
3623 04:47:53.510242 ==
3624 04:47:53.512328 Dram Type= 6, Freq= 0, CH_1, rank 1
3625 04:47:53.515806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3626 04:47:53.518628 ==
3627 04:47:53.519199
3628 04:47:53.519569
3629 04:47:53.519914 TX Vref Scan disable
3630 04:47:53.522036 == TX Byte 0 ==
3631 04:47:53.525678 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3632 04:47:53.531967 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3633 04:47:53.532552 == TX Byte 1 ==
3634 04:47:53.535662 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3635 04:47:53.542177 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3636 04:47:53.542713
3637 04:47:53.543093 [DATLAT]
3638 04:47:53.543445 Freq=1200, CH1 RK1
3639 04:47:53.543789
3640 04:47:53.545492 DATLAT Default: 0xd
3641 04:47:53.546004 0, 0xFFFF, sum = 0
3642 04:47:53.548841 1, 0xFFFF, sum = 0
3643 04:47:53.549426 2, 0xFFFF, sum = 0
3644 04:47:53.552187 3, 0xFFFF, sum = 0
3645 04:47:53.555399 4, 0xFFFF, sum = 0
3646 04:47:53.555883 5, 0xFFFF, sum = 0
3647 04:47:53.558905 6, 0xFFFF, sum = 0
3648 04:47:53.559495 7, 0xFFFF, sum = 0
3649 04:47:53.562138 8, 0xFFFF, sum = 0
3650 04:47:53.562616 9, 0xFFFF, sum = 0
3651 04:47:53.565893 10, 0xFFFF, sum = 0
3652 04:47:53.566542 11, 0xFFFF, sum = 0
3653 04:47:53.568764 12, 0x0, sum = 1
3654 04:47:53.569354 13, 0x0, sum = 2
3655 04:47:53.571615 14, 0x0, sum = 3
3656 04:47:53.572098 15, 0x0, sum = 4
3657 04:47:53.575319 best_step = 13
3658 04:47:53.575902
3659 04:47:53.576301 ==
3660 04:47:53.578573 Dram Type= 6, Freq= 0, CH_1, rank 1
3661 04:47:53.582027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3662 04:47:53.582510 ==
3663 04:47:53.582888 RX Vref Scan: 0
3664 04:47:53.583237
3665 04:47:53.585464 RX Vref 0 -> 0, step: 1
3666 04:47:53.586111
3667 04:47:53.588827 RX Delay -13 -> 252, step: 4
3668 04:47:53.592255 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
3669 04:47:53.598722 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3670 04:47:53.602049 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3671 04:47:53.605351 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3672 04:47:53.608908 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3673 04:47:53.611680 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3674 04:47:53.618577 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3675 04:47:53.622124 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3676 04:47:53.625206 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3677 04:47:53.628781 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3678 04:47:53.632134 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3679 04:47:53.638347 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3680 04:47:53.642076 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3681 04:47:53.645047 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3682 04:47:53.648750 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3683 04:47:53.652419 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3684 04:47:53.655350 ==
3685 04:47:53.655824 Dram Type= 6, Freq= 0, CH_1, rank 1
3686 04:47:53.661932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3687 04:47:53.662546 ==
3688 04:47:53.662925 DQS Delay:
3689 04:47:53.665591 DQS0 = 0, DQS1 = 0
3690 04:47:53.666208 DQM Delay:
3691 04:47:53.668344 DQM0 = 119, DQM1 = 113
3692 04:47:53.668816 DQ Delay:
3693 04:47:53.671633 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3694 04:47:53.675026 DQ4 =120, DQ5 =130, DQ6 =126, DQ7 =116
3695 04:47:53.678521 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3696 04:47:53.682102 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3697 04:47:53.682683
3698 04:47:53.683060
3699 04:47:53.691552 [DQSOSCAuto] RK1, (LSB)MR18= 0x5ea, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 408 ps
3700 04:47:53.692134 CH1 RK1: MR19=403, MR18=5EA
3701 04:47:53.698477 CH1_RK1: MR19=0x403, MR18=0x5EA, DQSOSC=408, MR23=63, INC=39, DEC=26
3702 04:47:53.701889 [RxdqsGatingPostProcess] freq 1200
3703 04:47:53.708442 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3704 04:47:53.711705 best DQS0 dly(2T, 0.5T) = (0, 11)
3705 04:47:53.715162 best DQS1 dly(2T, 0.5T) = (0, 11)
3706 04:47:53.718657 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3707 04:47:53.721640 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3708 04:47:53.725162 best DQS0 dly(2T, 0.5T) = (0, 11)
3709 04:47:53.725750 best DQS1 dly(2T, 0.5T) = (0, 11)
3710 04:47:53.728641 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3711 04:47:53.731764 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3712 04:47:53.735103 Pre-setting of DQS Precalculation
3713 04:47:53.741431 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3714 04:47:53.748209 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3715 04:47:53.754837 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3716 04:47:53.755335
3717 04:47:53.755715
3718 04:47:53.758355 [Calibration Summary] 2400 Mbps
3719 04:47:53.761641 CH 0, Rank 0
3720 04:47:53.762207 SW Impedance : PASS
3721 04:47:53.764504 DUTY Scan : NO K
3722 04:47:53.764851 ZQ Calibration : PASS
3723 04:47:53.768098 Jitter Meter : NO K
3724 04:47:53.771084 CBT Training : PASS
3725 04:47:53.771330 Write leveling : PASS
3726 04:47:53.774474 RX DQS gating : PASS
3727 04:47:53.777687 RX DQ/DQS(RDDQC) : PASS
3728 04:47:53.777850 TX DQ/DQS : PASS
3729 04:47:53.780953 RX DATLAT : PASS
3730 04:47:53.784372 RX DQ/DQS(Engine): PASS
3731 04:47:53.784511 TX OE : NO K
3732 04:47:53.787631 All Pass.
3733 04:47:53.787752
3734 04:47:53.787848 CH 0, Rank 1
3735 04:47:53.790958 SW Impedance : PASS
3736 04:47:53.791079 DUTY Scan : NO K
3737 04:47:53.794103 ZQ Calibration : PASS
3738 04:47:53.797654 Jitter Meter : NO K
3739 04:47:53.797762 CBT Training : PASS
3740 04:47:53.801208 Write leveling : PASS
3741 04:47:53.804592 RX DQS gating : PASS
3742 04:47:53.804707 RX DQ/DQS(RDDQC) : PASS
3743 04:47:53.807530 TX DQ/DQS : PASS
3744 04:47:53.807652 RX DATLAT : PASS
3745 04:47:53.810930 RX DQ/DQS(Engine): PASS
3746 04:47:53.814385 TX OE : NO K
3747 04:47:53.814545 All Pass.
3748 04:47:53.814664
3749 04:47:53.814747 CH 1, Rank 0
3750 04:47:53.817615 SW Impedance : PASS
3751 04:47:53.821063 DUTY Scan : NO K
3752 04:47:53.821171 ZQ Calibration : PASS
3753 04:47:53.824458 Jitter Meter : NO K
3754 04:47:53.827477 CBT Training : PASS
3755 04:47:53.827584 Write leveling : PASS
3756 04:47:53.830999 RX DQS gating : PASS
3757 04:47:53.834616 RX DQ/DQS(RDDQC) : PASS
3758 04:47:53.835045 TX DQ/DQS : PASS
3759 04:47:53.837613 RX DATLAT : PASS
3760 04:47:53.840936 RX DQ/DQS(Engine): PASS
3761 04:47:53.841589 TX OE : NO K
3762 04:47:53.844908 All Pass.
3763 04:47:53.845338
3764 04:47:53.845678 CH 1, Rank 1
3765 04:47:53.847852 SW Impedance : PASS
3766 04:47:53.848279 DUTY Scan : NO K
3767 04:47:53.851409 ZQ Calibration : PASS
3768 04:47:53.854261 Jitter Meter : NO K
3769 04:47:53.854831 CBT Training : PASS
3770 04:47:53.857993 Write leveling : PASS
3771 04:47:53.858401 RX DQS gating : PASS
3772 04:47:53.861114 RX DQ/DQS(RDDQC) : PASS
3773 04:47:53.864321 TX DQ/DQS : PASS
3774 04:47:53.865014 RX DATLAT : PASS
3775 04:47:53.867651 RX DQ/DQS(Engine): PASS
3776 04:47:53.871024 TX OE : NO K
3777 04:47:53.871456 All Pass.
3778 04:47:53.871797
3779 04:47:53.874363 DramC Write-DBI off
3780 04:47:53.874791 PER_BANK_REFRESH: Hybrid Mode
3781 04:47:53.877587 TX_TRACKING: ON
3782 04:47:53.887451 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3783 04:47:53.890957 [FAST_K] Save calibration result to emmc
3784 04:47:53.894393 dramc_set_vcore_voltage set vcore to 650000
3785 04:47:53.894966 Read voltage for 600, 5
3786 04:47:53.897656 Vio18 = 0
3787 04:47:53.898162 Vcore = 650000
3788 04:47:53.898537 Vdram = 0
3789 04:47:53.901140 Vddq = 0
3790 04:47:53.901610 Vmddr = 0
3791 04:47:53.904406 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3792 04:47:53.910929 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3793 04:47:53.914055 MEM_TYPE=3, freq_sel=19
3794 04:47:53.917504 sv_algorithm_assistance_LP4_1600
3795 04:47:53.921213 ============ PULL DRAM RESETB DOWN ============
3796 04:47:53.924370 ========== PULL DRAM RESETB DOWN end =========
3797 04:47:53.931184 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3798 04:47:53.934121 ===================================
3799 04:47:53.934595 LPDDR4 DRAM CONFIGURATION
3800 04:47:53.937623 ===================================
3801 04:47:53.940836 EX_ROW_EN[0] = 0x0
3802 04:47:53.941307 EX_ROW_EN[1] = 0x0
3803 04:47:53.944212 LP4Y_EN = 0x0
3804 04:47:53.944701 WORK_FSP = 0x0
3805 04:47:53.947982 WL = 0x2
3806 04:47:53.948455 RL = 0x2
3807 04:47:53.951272 BL = 0x2
3808 04:47:53.951747 RPST = 0x0
3809 04:47:53.954608 RD_PRE = 0x0
3810 04:47:53.957657 WR_PRE = 0x1
3811 04:47:53.958286 WR_PST = 0x0
3812 04:47:53.961208 DBI_WR = 0x0
3813 04:47:53.961789 DBI_RD = 0x0
3814 04:47:53.964370 OTF = 0x1
3815 04:47:53.967438 ===================================
3816 04:47:53.970704 ===================================
3817 04:47:53.971184 ANA top config
3818 04:47:53.974233 ===================================
3819 04:47:53.977504 DLL_ASYNC_EN = 0
3820 04:47:53.981110 ALL_SLAVE_EN = 1
3821 04:47:53.981679 NEW_RANK_MODE = 1
3822 04:47:53.984263 DLL_IDLE_MODE = 1
3823 04:47:53.987759 LP45_APHY_COMB_EN = 1
3824 04:47:53.991152 TX_ODT_DIS = 1
3825 04:47:53.991731 NEW_8X_MODE = 1
3826 04:47:53.994389 ===================================
3827 04:47:53.997891 ===================================
3828 04:47:54.000915 data_rate = 1200
3829 04:47:54.004512 CKR = 1
3830 04:47:54.007755 DQ_P2S_RATIO = 8
3831 04:47:54.011125 ===================================
3832 04:47:54.014555 CA_P2S_RATIO = 8
3833 04:47:54.017308 DQ_CA_OPEN = 0
3834 04:47:54.017780 DQ_SEMI_OPEN = 0
3835 04:47:54.020695 CA_SEMI_OPEN = 0
3836 04:47:54.024400 CA_FULL_RATE = 0
3837 04:47:54.027414 DQ_CKDIV4_EN = 1
3838 04:47:54.031167 CA_CKDIV4_EN = 1
3839 04:47:54.034034 CA_PREDIV_EN = 0
3840 04:47:54.034603 PH8_DLY = 0
3841 04:47:54.037174 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3842 04:47:54.040760 DQ_AAMCK_DIV = 4
3843 04:47:54.044036 CA_AAMCK_DIV = 4
3844 04:47:54.047378 CA_ADMCK_DIV = 4
3845 04:47:54.050765 DQ_TRACK_CA_EN = 0
3846 04:47:54.051240 CA_PICK = 600
3847 04:47:54.054041 CA_MCKIO = 600
3848 04:47:54.057141 MCKIO_SEMI = 0
3849 04:47:54.061107 PLL_FREQ = 2288
3850 04:47:54.064364 DQ_UI_PI_RATIO = 32
3851 04:47:54.067537 CA_UI_PI_RATIO = 0
3852 04:47:54.070547 ===================================
3853 04:47:54.074302 ===================================
3854 04:47:54.074876 memory_type:LPDDR4
3855 04:47:54.077809 GP_NUM : 10
3856 04:47:54.080719 SRAM_EN : 1
3857 04:47:54.081291 MD32_EN : 0
3858 04:47:54.083702 ===================================
3859 04:47:54.087235 [ANA_INIT] >>>>>>>>>>>>>>
3860 04:47:54.090594 <<<<<< [CONFIGURE PHASE]: ANA_TX
3861 04:47:54.093956 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3862 04:47:54.097064 ===================================
3863 04:47:54.100533 data_rate = 1200,PCW = 0X5800
3864 04:47:54.103871 ===================================
3865 04:47:54.107186 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3866 04:47:54.110392 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3867 04:47:54.117101 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3868 04:47:54.120694 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3869 04:47:54.127486 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3870 04:47:54.130468 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3871 04:47:54.130945 [ANA_INIT] flow start
3872 04:47:54.133745 [ANA_INIT] PLL >>>>>>>>
3873 04:47:54.137058 [ANA_INIT] PLL <<<<<<<<
3874 04:47:54.137531 [ANA_INIT] MIDPI >>>>>>>>
3875 04:47:54.140710 [ANA_INIT] MIDPI <<<<<<<<
3876 04:47:54.143722 [ANA_INIT] DLL >>>>>>>>
3877 04:47:54.144206 [ANA_INIT] flow end
3878 04:47:54.147509 ============ LP4 DIFF to SE enter ============
3879 04:47:54.153786 ============ LP4 DIFF to SE exit ============
3880 04:47:54.154407 [ANA_INIT] <<<<<<<<<<<<<
3881 04:47:54.156995 [Flow] Enable top DCM control >>>>>
3882 04:47:54.160378 [Flow] Enable top DCM control <<<<<
3883 04:47:54.163681 Enable DLL master slave shuffle
3884 04:47:54.170196 ==============================================================
3885 04:47:54.170781 Gating Mode config
3886 04:47:54.177030 ==============================================================
3887 04:47:54.180615 Config description:
3888 04:47:54.190613 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3889 04:47:54.196593 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3890 04:47:54.199942 SELPH_MODE 0: By rank 1: By Phase
3891 04:47:54.206749 ==============================================================
3892 04:47:54.210094 GAT_TRACK_EN = 1
3893 04:47:54.213858 RX_GATING_MODE = 2
3894 04:47:54.214493 RX_GATING_TRACK_MODE = 2
3895 04:47:54.216579 SELPH_MODE = 1
3896 04:47:54.220284 PICG_EARLY_EN = 1
3897 04:47:54.223777 VALID_LAT_VALUE = 1
3898 04:47:54.230202 ==============================================================
3899 04:47:54.233659 Enter into Gating configuration >>>>
3900 04:47:54.236677 Exit from Gating configuration <<<<
3901 04:47:54.240222 Enter into DVFS_PRE_config >>>>>
3902 04:47:54.250263 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3903 04:47:54.253434 Exit from DVFS_PRE_config <<<<<
3904 04:47:54.256795 Enter into PICG configuration >>>>
3905 04:47:54.260237 Exit from PICG configuration <<<<
3906 04:47:54.263774 [RX_INPUT] configuration >>>>>
3907 04:47:54.266752 [RX_INPUT] configuration <<<<<
3908 04:47:54.269983 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3909 04:47:54.276855 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3910 04:47:54.283577 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3911 04:47:54.286545 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3912 04:47:54.293428 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3913 04:47:54.299777 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3914 04:47:54.303457 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3915 04:47:54.309901 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3916 04:47:54.313323 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3917 04:47:54.316314 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3918 04:47:54.320031 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3919 04:47:54.326596 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3920 04:47:54.329978 ===================================
3921 04:47:54.330564 LPDDR4 DRAM CONFIGURATION
3922 04:47:54.333300 ===================================
3923 04:47:54.336740 EX_ROW_EN[0] = 0x0
3924 04:47:54.339792 EX_ROW_EN[1] = 0x0
3925 04:47:54.340267 LP4Y_EN = 0x0
3926 04:47:54.342704 WORK_FSP = 0x0
3927 04:47:54.343176 WL = 0x2
3928 04:47:54.346113 RL = 0x2
3929 04:47:54.346579 BL = 0x2
3930 04:47:54.349494 RPST = 0x0
3931 04:47:54.349987 RD_PRE = 0x0
3932 04:47:54.353089 WR_PRE = 0x1
3933 04:47:54.353668 WR_PST = 0x0
3934 04:47:54.356246 DBI_WR = 0x0
3935 04:47:54.356869 DBI_RD = 0x0
3936 04:47:54.359917 OTF = 0x1
3937 04:47:54.363367 ===================================
3938 04:47:54.366186 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3939 04:47:54.369522 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3940 04:47:54.376397 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3941 04:47:54.379245 ===================================
3942 04:47:54.379726 LPDDR4 DRAM CONFIGURATION
3943 04:47:54.382891 ===================================
3944 04:47:54.386320 EX_ROW_EN[0] = 0x10
3945 04:47:54.389613 EX_ROW_EN[1] = 0x0
3946 04:47:54.390226 LP4Y_EN = 0x0
3947 04:47:54.392891 WORK_FSP = 0x0
3948 04:47:54.393480 WL = 0x2
3949 04:47:54.395899 RL = 0x2
3950 04:47:54.396374 BL = 0x2
3951 04:47:54.399590 RPST = 0x0
3952 04:47:54.400083 RD_PRE = 0x0
3953 04:47:54.402704 WR_PRE = 0x1
3954 04:47:54.403281 WR_PST = 0x0
3955 04:47:54.406318 DBI_WR = 0x0
3956 04:47:54.406889 DBI_RD = 0x0
3957 04:47:54.409488 OTF = 0x1
3958 04:47:54.412984 ===================================
3959 04:47:54.419323 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3960 04:47:54.422929 nWR fixed to 30
3961 04:47:54.423405 [ModeRegInit_LP4] CH0 RK0
3962 04:47:54.426138 [ModeRegInit_LP4] CH0 RK1
3963 04:47:54.429371 [ModeRegInit_LP4] CH1 RK0
3964 04:47:54.429843 [ModeRegInit_LP4] CH1 RK1
3965 04:47:54.433120 match AC timing 17
3966 04:47:54.435822 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3967 04:47:54.439341 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3968 04:47:54.445751 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3969 04:47:54.449387 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3970 04:47:54.456029 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3971 04:47:54.456590 ==
3972 04:47:54.459686 Dram Type= 6, Freq= 0, CH_0, rank 0
3973 04:47:54.462439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3974 04:47:54.462920 ==
3975 04:47:54.469267 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3976 04:47:54.475842 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3977 04:47:54.479166 [CA 0] Center 36 (5~67) winsize 63
3978 04:47:54.482654 [CA 1] Center 36 (6~67) winsize 62
3979 04:47:54.486018 [CA 2] Center 34 (4~65) winsize 62
3980 04:47:54.489128 [CA 3] Center 34 (3~65) winsize 63
3981 04:47:54.492445 [CA 4] Center 33 (3~64) winsize 62
3982 04:47:54.495671 [CA 5] Center 33 (2~64) winsize 63
3983 04:47:54.496146
3984 04:47:54.499176 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3985 04:47:54.499759
3986 04:47:54.502616 [CATrainingPosCal] consider 1 rank data
3987 04:47:54.506042 u2DelayCellTimex100 = 270/100 ps
3988 04:47:54.508973 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3989 04:47:54.512453 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3990 04:47:54.515758 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3991 04:47:54.519232 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3992 04:47:54.522830 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3993 04:47:54.525797 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3994 04:47:54.526415
3995 04:47:54.529114 CA PerBit enable=1, Macro0, CA PI delay=33
3996 04:47:54.529634
3997 04:47:54.532681 [CBTSetCACLKResult] CA Dly = 33
3998 04:47:54.536082 CS Dly: 5 (0~36)
3999 04:47:54.536685 ==
4000 04:47:54.538866 Dram Type= 6, Freq= 0, CH_0, rank 1
4001 04:47:54.542466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4002 04:47:54.542941 ==
4003 04:47:54.549327 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4004 04:47:54.556062 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4005 04:47:54.559118 [CA 0] Center 36 (6~67) winsize 62
4006 04:47:54.562469 [CA 1] Center 36 (6~67) winsize 62
4007 04:47:54.565980 [CA 2] Center 34 (4~65) winsize 62
4008 04:47:54.569089 [CA 3] Center 34 (4~65) winsize 62
4009 04:47:54.572347 [CA 4] Center 34 (3~65) winsize 63
4010 04:47:54.575675 [CA 5] Center 33 (3~64) winsize 62
4011 04:47:54.576257
4012 04:47:54.578809 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4013 04:47:54.579330
4014 04:47:54.582361 [CATrainingPosCal] consider 2 rank data
4015 04:47:54.585653 u2DelayCellTimex100 = 270/100 ps
4016 04:47:54.589061 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4017 04:47:54.591979 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4018 04:47:54.595773 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4019 04:47:54.598989 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4020 04:47:54.602500 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4021 04:47:54.605994 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4022 04:47:54.606581
4023 04:47:54.611806 CA PerBit enable=1, Macro0, CA PI delay=33
4024 04:47:54.612282
4025 04:47:54.612658 [CBTSetCACLKResult] CA Dly = 33
4026 04:47:54.615601 CS Dly: 5 (0~37)
4027 04:47:54.616071
4028 04:47:54.618634 ----->DramcWriteLeveling(PI) begin...
4029 04:47:54.619117 ==
4030 04:47:54.622542 Dram Type= 6, Freq= 0, CH_0, rank 0
4031 04:47:54.625111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4032 04:47:54.625592 ==
4033 04:47:54.628695 Write leveling (Byte 0): 33 => 33
4034 04:47:54.632380 Write leveling (Byte 1): 29 => 29
4035 04:47:54.635810 DramcWriteLeveling(PI) end<-----
4036 04:47:54.636387
4037 04:47:54.636771 ==
4038 04:47:54.638791 Dram Type= 6, Freq= 0, CH_0, rank 0
4039 04:47:54.642284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4040 04:47:54.645496 ==
4041 04:47:54.646000 [Gating] SW mode calibration
4042 04:47:54.652230 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4043 04:47:54.658708 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4044 04:47:54.662321 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4045 04:47:54.668454 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4046 04:47:54.672173 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4047 04:47:54.675229 0 9 12 | B1->B0 | 3333 2929 | 1 1 | (1 1) (1 0)
4048 04:47:54.682129 0 9 16 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
4049 04:47:54.685044 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 04:47:54.688961 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 04:47:54.695257 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 04:47:54.698470 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4053 04:47:54.702059 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4054 04:47:54.708387 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4055 04:47:54.711480 0 10 12 | B1->B0 | 2929 3a3a | 0 1 | (1 1) (0 0)
4056 04:47:54.715359 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4057 04:47:54.722129 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 04:47:54.725021 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 04:47:54.728494 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 04:47:54.731596 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 04:47:54.738711 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 04:47:54.741828 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 04:47:54.745094 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4064 04:47:54.751565 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4065 04:47:54.754686 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 04:47:54.758210 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 04:47:54.765028 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 04:47:54.768419 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 04:47:54.771755 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 04:47:54.778386 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 04:47:54.781415 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 04:47:54.784665 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 04:47:54.791553 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 04:47:54.794547 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 04:47:54.797989 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 04:47:54.804762 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 04:47:54.807796 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 04:47:54.811289 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 04:47:54.817820 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4080 04:47:54.818498 Total UI for P1: 0, mck2ui 16
4081 04:47:54.824812 best dqsien dly found for B0: ( 0, 13, 10)
4082 04:47:54.828343 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4083 04:47:54.831621 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4084 04:47:54.834695 Total UI for P1: 0, mck2ui 16
4085 04:47:54.838225 best dqsien dly found for B1: ( 0, 13, 18)
4086 04:47:54.841550 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4087 04:47:54.844699 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4088 04:47:54.845176
4089 04:47:54.848134 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4090 04:47:54.854516 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4091 04:47:54.855079 [Gating] SW calibration Done
4092 04:47:54.858069 ==
4093 04:47:54.858647 Dram Type= 6, Freq= 0, CH_0, rank 0
4094 04:47:54.864724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4095 04:47:54.865311 ==
4096 04:47:54.865693 RX Vref Scan: 0
4097 04:47:54.866101
4098 04:47:54.868080 RX Vref 0 -> 0, step: 1
4099 04:47:54.868654
4100 04:47:54.871555 RX Delay -230 -> 252, step: 16
4101 04:47:54.874383 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4102 04:47:54.877808 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4103 04:47:54.884136 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4104 04:47:54.887769 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4105 04:47:54.890982 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4106 04:47:54.894107 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4107 04:47:54.897871 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4108 04:47:54.904426 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4109 04:47:54.907649 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4110 04:47:54.911140 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4111 04:47:54.914105 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4112 04:47:54.921020 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4113 04:47:54.924799 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4114 04:47:54.927866 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4115 04:47:54.931433 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4116 04:47:54.937613 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4117 04:47:54.938329 ==
4118 04:47:54.941224 Dram Type= 6, Freq= 0, CH_0, rank 0
4119 04:47:54.944288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4120 04:47:54.944773 ==
4121 04:47:54.945152 DQS Delay:
4122 04:47:54.947545 DQS0 = 0, DQS1 = 0
4123 04:47:54.948019 DQM Delay:
4124 04:47:54.951312 DQM0 = 51, DQM1 = 41
4125 04:47:54.951885 DQ Delay:
4126 04:47:54.954265 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4127 04:47:54.957695 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4128 04:47:54.960997 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4129 04:47:54.964356 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =49
4130 04:47:54.964933
4131 04:47:54.965309
4132 04:47:54.965664 ==
4133 04:47:54.967358 Dram Type= 6, Freq= 0, CH_0, rank 0
4134 04:47:54.971070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 04:47:54.971488 ==
4136 04:47:54.971842
4137 04:47:54.972180
4138 04:47:54.974482 TX Vref Scan disable
4139 04:47:54.977766 == TX Byte 0 ==
4140 04:47:54.980681 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4141 04:47:54.984601 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4142 04:47:54.987576 == TX Byte 1 ==
4143 04:47:54.991130 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4144 04:47:54.994319 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4145 04:47:54.994798 ==
4146 04:47:54.997358 Dram Type= 6, Freq= 0, CH_0, rank 0
4147 04:47:55.004057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 04:47:55.004771 ==
4149 04:47:55.005259
4150 04:47:55.005623
4151 04:47:55.006005 TX Vref Scan disable
4152 04:47:55.008840 == TX Byte 0 ==
4153 04:47:55.012243 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4154 04:47:55.018961 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4155 04:47:55.019535 == TX Byte 1 ==
4156 04:47:55.021907 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4157 04:47:55.025325 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4158 04:47:55.028928
4159 04:47:55.029551 [DATLAT]
4160 04:47:55.029959 Freq=600, CH0 RK0
4161 04:47:55.030344
4162 04:47:55.032411 DATLAT Default: 0x9
4163 04:47:55.032982 0, 0xFFFF, sum = 0
4164 04:47:55.035036 1, 0xFFFF, sum = 0
4165 04:47:55.035520 2, 0xFFFF, sum = 0
4166 04:47:55.038230 3, 0xFFFF, sum = 0
4167 04:47:55.041864 4, 0xFFFF, sum = 0
4168 04:47:55.042376 5, 0xFFFF, sum = 0
4169 04:47:55.045155 6, 0xFFFF, sum = 0
4170 04:47:55.045640 7, 0xFFFF, sum = 0
4171 04:47:55.048547 8, 0x0, sum = 1
4172 04:47:55.049029 9, 0x0, sum = 2
4173 04:47:55.049414 10, 0x0, sum = 3
4174 04:47:55.052135 11, 0x0, sum = 4
4175 04:47:55.052719 best_step = 9
4176 04:47:55.053097
4177 04:47:55.053447 ==
4178 04:47:55.055145 Dram Type= 6, Freq= 0, CH_0, rank 0
4179 04:47:55.061994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4180 04:47:55.062577 ==
4181 04:47:55.062959 RX Vref Scan: 1
4182 04:47:55.063315
4183 04:47:55.065136 RX Vref 0 -> 0, step: 1
4184 04:47:55.065613
4185 04:47:55.068339 RX Delay -163 -> 252, step: 8
4186 04:47:55.068918
4187 04:47:55.072031 Set Vref, RX VrefLevel [Byte0]: 58
4188 04:47:55.074996 [Byte1]: 48
4189 04:47:55.075476
4190 04:47:55.078605 Final RX Vref Byte 0 = 58 to rank0
4191 04:47:55.082044 Final RX Vref Byte 1 = 48 to rank0
4192 04:47:55.085026 Final RX Vref Byte 0 = 58 to rank1
4193 04:47:55.088204 Final RX Vref Byte 1 = 48 to rank1==
4194 04:47:55.091671 Dram Type= 6, Freq= 0, CH_0, rank 0
4195 04:47:55.094941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4196 04:47:55.095517 ==
4197 04:47:55.098309 DQS Delay:
4198 04:47:55.098783 DQS0 = 0, DQS1 = 0
4199 04:47:55.099161 DQM Delay:
4200 04:47:55.101561 DQM0 = 49, DQM1 = 37
4201 04:47:55.102180 DQ Delay:
4202 04:47:55.104872 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44
4203 04:47:55.108298 DQ4 =52, DQ5 =40, DQ6 =56, DQ7 =56
4204 04:47:55.111760 DQ8 =32, DQ9 =20, DQ10 =36, DQ11 =32
4205 04:47:55.115266 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4206 04:47:55.115865
4207 04:47:55.116246
4208 04:47:55.124942 [DQSOSCAuto] RK0, (LSB)MR18= 0x5953, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4209 04:47:55.128212 CH0 RK0: MR19=808, MR18=5953
4210 04:47:55.131636 CH0_RK0: MR19=0x808, MR18=0x5953, DQSOSC=393, MR23=63, INC=169, DEC=113
4211 04:47:55.132238
4212 04:47:55.134846 ----->DramcWriteLeveling(PI) begin...
4213 04:47:55.138313 ==
4214 04:47:55.141558 Dram Type= 6, Freq= 0, CH_0, rank 1
4215 04:47:55.144741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4216 04:47:55.145223 ==
4217 04:47:55.147936 Write leveling (Byte 0): 33 => 33
4218 04:47:55.151432 Write leveling (Byte 1): 32 => 32
4219 04:47:55.154540 DramcWriteLeveling(PI) end<-----
4220 04:47:55.155019
4221 04:47:55.155394 ==
4222 04:47:55.158060 Dram Type= 6, Freq= 0, CH_0, rank 1
4223 04:47:55.161567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4224 04:47:55.162183 ==
4225 04:47:55.164641 [Gating] SW mode calibration
4226 04:47:55.171447 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4227 04:47:55.178478 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4228 04:47:55.181709 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4229 04:47:55.184927 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4230 04:47:55.191670 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4231 04:47:55.194810 0 9 12 | B1->B0 | 3131 3030 | 0 0 | (0 1) (0 1)
4232 04:47:55.197708 0 9 16 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (0 0)
4233 04:47:55.201458 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 04:47:55.208172 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 04:47:55.211408 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 04:47:55.214609 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 04:47:55.221184 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 04:47:55.224813 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 04:47:55.228276 0 10 12 | B1->B0 | 2e2e 3232 | 0 0 | (0 0) (0 0)
4240 04:47:55.234844 0 10 16 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
4241 04:47:55.238318 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 04:47:55.241447 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 04:47:55.247842 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 04:47:55.251385 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 04:47:55.254775 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 04:47:55.261253 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 04:47:55.264435 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4248 04:47:55.267586 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 04:47:55.274608 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 04:47:55.278086 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 04:47:55.281264 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 04:47:55.287557 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 04:47:55.291122 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 04:47:55.294119 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 04:47:55.300859 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 04:47:55.304639 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 04:47:55.307516 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 04:47:55.314037 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 04:47:55.317347 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 04:47:55.320987 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 04:47:55.327783 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 04:47:55.330865 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 04:47:55.334380 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4264 04:47:55.337396 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4265 04:47:55.340859 Total UI for P1: 0, mck2ui 16
4266 04:47:55.343902 best dqsien dly found for B0: ( 0, 13, 12)
4267 04:47:55.347374 Total UI for P1: 0, mck2ui 16
4268 04:47:55.350488 best dqsien dly found for B1: ( 0, 13, 14)
4269 04:47:55.357263 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4270 04:47:55.360951 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4271 04:47:55.361541
4272 04:47:55.364380 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4273 04:47:55.366973 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4274 04:47:55.370348 [Gating] SW calibration Done
4275 04:47:55.370932 ==
4276 04:47:55.373895 Dram Type= 6, Freq= 0, CH_0, rank 1
4277 04:47:55.377374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4278 04:47:55.378002 ==
4279 04:47:55.380537 RX Vref Scan: 0
4280 04:47:55.381127
4281 04:47:55.381612 RX Vref 0 -> 0, step: 1
4282 04:47:55.382190
4283 04:47:55.383613 RX Delay -230 -> 252, step: 16
4284 04:47:55.387075 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4285 04:47:55.393633 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4286 04:47:55.397619 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4287 04:47:55.400561 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4288 04:47:55.403933 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4289 04:47:55.410521 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4290 04:47:55.413739 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4291 04:47:55.417310 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4292 04:47:55.420159 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4293 04:47:55.423893 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4294 04:47:55.430238 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4295 04:47:55.434107 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4296 04:47:55.436614 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4297 04:47:55.439947 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4298 04:47:55.446715 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4299 04:47:55.449680 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4300 04:47:55.450230 ==
4301 04:47:55.453300 Dram Type= 6, Freq= 0, CH_0, rank 1
4302 04:47:55.457022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4303 04:47:55.457617 ==
4304 04:47:55.460035 DQS Delay:
4305 04:47:55.460520 DQS0 = 0, DQS1 = 0
4306 04:47:55.462985 DQM Delay:
4307 04:47:55.463566 DQM0 = 51, DQM1 = 43
4308 04:47:55.464056 DQ Delay:
4309 04:47:55.466290 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4310 04:47:55.469732 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =57
4311 04:47:55.473356 DQ8 =33, DQ9 =25, DQ10 =49, DQ11 =41
4312 04:47:55.476162 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4313 04:47:55.476652
4314 04:47:55.477131
4315 04:47:55.477577 ==
4316 04:47:55.480337 Dram Type= 6, Freq= 0, CH_0, rank 1
4317 04:47:55.486886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4318 04:47:55.487480 ==
4319 04:47:55.487971
4320 04:47:55.488420
4321 04:47:55.489536 TX Vref Scan disable
4322 04:47:55.490058 == TX Byte 0 ==
4323 04:47:55.493294 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4324 04:47:55.499365 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4325 04:47:55.499938 == TX Byte 1 ==
4326 04:47:55.502902 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4327 04:47:55.509759 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4328 04:47:55.510385 ==
4329 04:47:55.512699 Dram Type= 6, Freq= 0, CH_0, rank 1
4330 04:47:55.516531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4331 04:47:55.517121 ==
4332 04:47:55.517612
4333 04:47:55.518168
4334 04:47:55.519615 TX Vref Scan disable
4335 04:47:55.522705 == TX Byte 0 ==
4336 04:47:55.526387 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4337 04:47:55.529659 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4338 04:47:55.533217 == TX Byte 1 ==
4339 04:47:55.535959 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4340 04:47:55.539811 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4341 04:47:55.540403
4342 04:47:55.542614 [DATLAT]
4343 04:47:55.543099 Freq=600, CH0 RK1
4344 04:47:55.543580
4345 04:47:55.546360 DATLAT Default: 0x9
4346 04:47:55.546846 0, 0xFFFF, sum = 0
4347 04:47:55.549246 1, 0xFFFF, sum = 0
4348 04:47:55.549985 2, 0xFFFF, sum = 0
4349 04:47:55.552884 3, 0xFFFF, sum = 0
4350 04:47:55.553500 4, 0xFFFF, sum = 0
4351 04:47:55.555814 5, 0xFFFF, sum = 0
4352 04:47:55.556307 6, 0xFFFF, sum = 0
4353 04:47:55.559238 7, 0xFFFF, sum = 0
4354 04:47:55.559731 8, 0x0, sum = 1
4355 04:47:55.562439 9, 0x0, sum = 2
4356 04:47:55.562933 10, 0x0, sum = 3
4357 04:47:55.566219 11, 0x0, sum = 4
4358 04:47:55.566711 best_step = 9
4359 04:47:55.567185
4360 04:47:55.567750 ==
4361 04:47:55.569654 Dram Type= 6, Freq= 0, CH_0, rank 1
4362 04:47:55.573122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4363 04:47:55.573700 ==
4364 04:47:55.576047 RX Vref Scan: 0
4365 04:47:55.576606
4366 04:47:55.579105 RX Vref 0 -> 0, step: 1
4367 04:47:55.579495
4368 04:47:55.579840 RX Delay -179 -> 252, step: 8
4369 04:47:55.586917 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4370 04:47:55.590422 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4371 04:47:55.593601 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4372 04:47:55.597162 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4373 04:47:55.600710 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4374 04:47:55.607086 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4375 04:47:55.610410 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4376 04:47:55.613682 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4377 04:47:55.616758 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4378 04:47:55.620604 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4379 04:47:55.626762 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4380 04:47:55.630662 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4381 04:47:55.633536 iDelay=205, Bit 12, Center 44 (-99 ~ 188) 288
4382 04:47:55.636842 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4383 04:47:55.643966 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4384 04:47:55.647291 iDelay=205, Bit 15, Center 48 (-91 ~ 188) 280
4385 04:47:55.647715 ==
4386 04:47:55.649998 Dram Type= 6, Freq= 0, CH_0, rank 1
4387 04:47:55.653504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4388 04:47:55.653969 ==
4389 04:47:55.656775 DQS Delay:
4390 04:47:55.657232 DQS0 = 0, DQS1 = 0
4391 04:47:55.657600 DQM Delay:
4392 04:47:55.660589 DQM0 = 47, DQM1 = 41
4393 04:47:55.661152 DQ Delay:
4394 04:47:55.664150 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4395 04:47:55.667508 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =52
4396 04:47:55.670895 DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =36
4397 04:47:55.674084 DQ12 =44, DQ13 =44, DQ14 =52, DQ15 =48
4398 04:47:55.674640
4399 04:47:55.675004
4400 04:47:55.683882 [DQSOSCAuto] RK1, (LSB)MR18= 0x602e, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
4401 04:47:55.684450 CH0 RK1: MR19=808, MR18=602E
4402 04:47:55.690648 CH0_RK1: MR19=0x808, MR18=0x602E, DQSOSC=391, MR23=63, INC=171, DEC=114
4403 04:47:55.694062 [RxdqsGatingPostProcess] freq 600
4404 04:47:55.700521 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4405 04:47:55.703743 Pre-setting of DQS Precalculation
4406 04:47:55.707412 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4407 04:47:55.707974 ==
4408 04:47:55.710884 Dram Type= 6, Freq= 0, CH_1, rank 0
4409 04:47:55.717125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4410 04:47:55.717696 ==
4411 04:47:55.720438 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4412 04:47:55.726813 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4413 04:47:55.730500 [CA 0] Center 35 (5~66) winsize 62
4414 04:47:55.733465 [CA 1] Center 35 (5~66) winsize 62
4415 04:47:55.736783 [CA 2] Center 34 (3~65) winsize 63
4416 04:47:55.740521 [CA 3] Center 33 (3~64) winsize 62
4417 04:47:55.743685 [CA 4] Center 34 (3~65) winsize 63
4418 04:47:55.746705 [CA 5] Center 33 (3~64) winsize 62
4419 04:47:55.747191
4420 04:47:55.750248 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4421 04:47:55.750837
4422 04:47:55.753392 [CATrainingPosCal] consider 1 rank data
4423 04:47:55.757002 u2DelayCellTimex100 = 270/100 ps
4424 04:47:55.760422 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4425 04:47:55.764279 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4426 04:47:55.767211 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4427 04:47:55.773675 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4428 04:47:55.777107 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4429 04:47:55.780551 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4430 04:47:55.781132
4431 04:47:55.783734 CA PerBit enable=1, Macro0, CA PI delay=33
4432 04:47:55.784206
4433 04:47:55.786699 [CBTSetCACLKResult] CA Dly = 33
4434 04:47:55.787277 CS Dly: 4 (0~35)
4435 04:47:55.787653 ==
4436 04:47:55.790043 Dram Type= 6, Freq= 0, CH_1, rank 1
4437 04:47:55.796612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4438 04:47:55.797085 ==
4439 04:47:55.799991 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4440 04:47:55.806892 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4441 04:47:55.810268 [CA 0] Center 36 (6~66) winsize 61
4442 04:47:55.813594 [CA 1] Center 36 (5~67) winsize 63
4443 04:47:55.816955 [CA 2] Center 34 (4~65) winsize 62
4444 04:47:55.820206 [CA 3] Center 34 (4~65) winsize 62
4445 04:47:55.823668 [CA 4] Center 34 (4~65) winsize 62
4446 04:47:55.826784 [CA 5] Center 33 (3~64) winsize 62
4447 04:47:55.827256
4448 04:47:55.830385 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4449 04:47:55.830853
4450 04:47:55.833427 [CATrainingPosCal] consider 2 rank data
4451 04:47:55.837150 u2DelayCellTimex100 = 270/100 ps
4452 04:47:55.840101 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4453 04:47:55.843512 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4454 04:47:55.849859 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4455 04:47:55.853273 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4456 04:47:55.856916 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4457 04:47:55.859933 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4458 04:47:55.860530
4459 04:47:55.863157 CA PerBit enable=1, Macro0, CA PI delay=33
4460 04:47:55.863645
4461 04:47:55.866465 [CBTSetCACLKResult] CA Dly = 33
4462 04:47:55.866955 CS Dly: 4 (0~36)
4463 04:47:55.867433
4464 04:47:55.869736 ----->DramcWriteLeveling(PI) begin...
4465 04:47:55.873073 ==
4466 04:47:55.876454 Dram Type= 6, Freq= 0, CH_1, rank 0
4467 04:47:55.880006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4468 04:47:55.880625 ==
4469 04:47:55.882946 Write leveling (Byte 0): 28 => 28
4470 04:47:55.886801 Write leveling (Byte 1): 31 => 31
4471 04:47:55.889830 DramcWriteLeveling(PI) end<-----
4472 04:47:55.890369
4473 04:47:55.890846 ==
4474 04:47:55.893127 Dram Type= 6, Freq= 0, CH_1, rank 0
4475 04:47:55.897056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4476 04:47:55.897660 ==
4477 04:47:55.899466 [Gating] SW mode calibration
4478 04:47:55.906824 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4479 04:47:55.912951 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4480 04:47:55.916455 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4481 04:47:55.919434 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4482 04:47:55.922563 0 9 8 | B1->B0 | 3333 3434 | 1 0 | (1 0) (0 0)
4483 04:47:55.929820 0 9 12 | B1->B0 | 2f2f 2d2d | 1 1 | (1 1) (1 0)
4484 04:47:55.933163 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 04:47:55.936234 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 04:47:55.943225 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 04:47:55.946487 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4488 04:47:55.949382 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4489 04:47:55.956302 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4490 04:47:55.959851 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4491 04:47:55.963047 0 10 12 | B1->B0 | 3939 3d3d | 0 0 | (0 0) (0 0)
4492 04:47:55.969894 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 04:47:55.973011 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 04:47:55.975871 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 04:47:55.982914 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 04:47:55.986338 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 04:47:55.989765 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 04:47:55.996356 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4499 04:47:55.999217 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 04:47:56.002653 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 04:47:56.009628 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 04:47:56.013073 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 04:47:56.016408 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 04:47:56.022494 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 04:47:56.026105 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 04:47:56.029615 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 04:47:56.036532 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 04:47:56.039238 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 04:47:56.042873 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 04:47:56.049587 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 04:47:56.052374 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 04:47:56.055933 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 04:47:56.059770 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 04:47:56.066210 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4515 04:47:56.069697 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4516 04:47:56.072768 Total UI for P1: 0, mck2ui 16
4517 04:47:56.075739 best dqsien dly found for B0: ( 0, 13, 8)
4518 04:47:56.079483 Total UI for P1: 0, mck2ui 16
4519 04:47:56.082619 best dqsien dly found for B1: ( 0, 13, 8)
4520 04:47:56.086163 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4521 04:47:56.089540 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4522 04:47:56.090322
4523 04:47:56.092623 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4524 04:47:56.095625 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4525 04:47:56.098934 [Gating] SW calibration Done
4526 04:47:56.099444 ==
4527 04:47:56.102886 Dram Type= 6, Freq= 0, CH_1, rank 0
4528 04:47:56.105934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4529 04:47:56.109282 ==
4530 04:47:56.109866 RX Vref Scan: 0
4531 04:47:56.110291
4532 04:47:56.112806 RX Vref 0 -> 0, step: 1
4533 04:47:56.113396
4534 04:47:56.116105 RX Delay -230 -> 252, step: 16
4535 04:47:56.119583 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4536 04:47:56.122621 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4537 04:47:56.126148 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4538 04:47:56.129499 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4539 04:47:56.135978 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4540 04:47:56.139154 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4541 04:47:56.142186 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4542 04:47:56.146035 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4543 04:47:56.152470 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4544 04:47:56.155801 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4545 04:47:56.159554 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4546 04:47:56.162594 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4547 04:47:56.165633 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4548 04:47:56.172109 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4549 04:47:56.175941 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4550 04:47:56.179294 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4551 04:47:56.179767 ==
4552 04:47:56.182093 Dram Type= 6, Freq= 0, CH_1, rank 0
4553 04:47:56.189408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4554 04:47:56.190027 ==
4555 04:47:56.190413 DQS Delay:
4556 04:47:56.190765 DQS0 = 0, DQS1 = 0
4557 04:47:56.192437 DQM Delay:
4558 04:47:56.192910 DQM0 = 51, DQM1 = 40
4559 04:47:56.195602 DQ Delay:
4560 04:47:56.199155 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4561 04:47:56.202039 DQ4 =49, DQ5 =57, DQ6 =65, DQ7 =49
4562 04:47:56.202516 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4563 04:47:56.208942 DQ12 =57, DQ13 =41, DQ14 =41, DQ15 =41
4564 04:47:56.209533
4565 04:47:56.209912
4566 04:47:56.210299 ==
4567 04:47:56.212310 Dram Type= 6, Freq= 0, CH_1, rank 0
4568 04:47:56.215620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 04:47:56.216201 ==
4570 04:47:56.216576
4571 04:47:56.216920
4572 04:47:56.219414 TX Vref Scan disable
4573 04:47:56.219989 == TX Byte 0 ==
4574 04:47:56.226009 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4575 04:47:56.229234 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4576 04:47:56.229812 == TX Byte 1 ==
4577 04:47:56.235812 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4578 04:47:56.238630 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4579 04:47:56.239106 ==
4580 04:47:56.241872 Dram Type= 6, Freq= 0, CH_1, rank 0
4581 04:47:56.245773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4582 04:47:56.246391 ==
4583 04:47:56.246770
4584 04:47:56.247121
4585 04:47:56.248906 TX Vref Scan disable
4586 04:47:56.252304 == TX Byte 0 ==
4587 04:47:56.255675 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4588 04:47:56.259185 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4589 04:47:56.262152 == TX Byte 1 ==
4590 04:47:56.265604 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4591 04:47:56.268890 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4592 04:47:56.269468
4593 04:47:56.272448 [DATLAT]
4594 04:47:56.273021 Freq=600, CH1 RK0
4595 04:47:56.273403
4596 04:47:56.275432 DATLAT Default: 0x9
4597 04:47:56.275902 0, 0xFFFF, sum = 0
4598 04:47:56.278712 1, 0xFFFF, sum = 0
4599 04:47:56.279191 2, 0xFFFF, sum = 0
4600 04:47:56.282117 3, 0xFFFF, sum = 0
4601 04:47:56.282598 4, 0xFFFF, sum = 0
4602 04:47:56.285727 5, 0xFFFF, sum = 0
4603 04:47:56.286352 6, 0xFFFF, sum = 0
4604 04:47:56.288620 7, 0xFFFF, sum = 0
4605 04:47:56.289098 8, 0x0, sum = 1
4606 04:47:56.291861 9, 0x0, sum = 2
4607 04:47:56.292338 10, 0x0, sum = 3
4608 04:47:56.295383 11, 0x0, sum = 4
4609 04:47:56.295862 best_step = 9
4610 04:47:56.296237
4611 04:47:56.296587 ==
4612 04:47:56.298654 Dram Type= 6, Freq= 0, CH_1, rank 0
4613 04:47:56.305607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4614 04:47:56.306223 ==
4615 04:47:56.306605 RX Vref Scan: 1
4616 04:47:56.306957
4617 04:47:56.308931 RX Vref 0 -> 0, step: 1
4618 04:47:56.309506
4619 04:47:56.312061 RX Delay -179 -> 252, step: 8
4620 04:47:56.312536
4621 04:47:56.315724 Set Vref, RX VrefLevel [Byte0]: 50
4622 04:47:56.318718 [Byte1]: 52
4623 04:47:56.319290
4624 04:47:56.321826 Final RX Vref Byte 0 = 50 to rank0
4625 04:47:56.325523 Final RX Vref Byte 1 = 52 to rank0
4626 04:47:56.328669 Final RX Vref Byte 0 = 50 to rank1
4627 04:47:56.332370 Final RX Vref Byte 1 = 52 to rank1==
4628 04:47:56.335270 Dram Type= 6, Freq= 0, CH_1, rank 0
4629 04:47:56.338484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4630 04:47:56.338964 ==
4631 04:47:56.342088 DQS Delay:
4632 04:47:56.342659 DQS0 = 0, DQS1 = 0
4633 04:47:56.343039 DQM Delay:
4634 04:47:56.345521 DQM0 = 47, DQM1 = 40
4635 04:47:56.346131 DQ Delay:
4636 04:47:56.348976 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4637 04:47:56.351783 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =44
4638 04:47:56.355448 DQ8 =28, DQ9 =28, DQ10 =48, DQ11 =32
4639 04:47:56.358697 DQ12 =52, DQ13 =48, DQ14 =44, DQ15 =44
4640 04:47:56.359173
4641 04:47:56.359546
4642 04:47:56.368425 [DQSOSCAuto] RK0, (LSB)MR18= 0x486f, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4643 04:47:56.369028 CH1 RK0: MR19=808, MR18=486F
4644 04:47:56.375107 CH1_RK0: MR19=0x808, MR18=0x486F, DQSOSC=389, MR23=63, INC=173, DEC=115
4645 04:47:56.375666
4646 04:47:56.378204 ----->DramcWriteLeveling(PI) begin...
4647 04:47:56.381832 ==
4648 04:47:56.382438 Dram Type= 6, Freq= 0, CH_1, rank 1
4649 04:47:56.388690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4650 04:47:56.389271 ==
4651 04:47:56.391340 Write leveling (Byte 0): 29 => 29
4652 04:47:56.394894 Write leveling (Byte 1): 28 => 28
4653 04:47:56.398281 DramcWriteLeveling(PI) end<-----
4654 04:47:56.398756
4655 04:47:56.399128 ==
4656 04:47:56.401512 Dram Type= 6, Freq= 0, CH_1, rank 1
4657 04:47:56.404924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4658 04:47:56.405514 ==
4659 04:47:56.408470 [Gating] SW mode calibration
4660 04:47:56.415359 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4661 04:47:56.421387 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4662 04:47:56.424795 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4663 04:47:56.428100 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4664 04:47:56.434872 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
4665 04:47:56.438290 0 9 12 | B1->B0 | 2a2a 3434 | 0 0 | (0 0) (1 1)
4666 04:47:56.441596 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4667 04:47:56.444905 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4668 04:47:56.451055 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4669 04:47:56.454386 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4670 04:47:56.457803 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4671 04:47:56.464589 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4672 04:47:56.467741 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4673 04:47:56.471208 0 10 12 | B1->B0 | 3d3d 3434 | 0 0 | (0 0) (0 0)
4674 04:47:56.477688 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 04:47:56.481496 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 04:47:56.485035 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 04:47:56.490909 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 04:47:56.494388 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 04:47:56.497605 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4680 04:47:56.504018 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4681 04:47:56.507471 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4682 04:47:56.510750 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 04:47:56.517625 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 04:47:56.521090 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 04:47:56.524365 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 04:47:56.530679 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 04:47:56.534101 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 04:47:56.537370 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 04:47:56.543932 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 04:47:56.547001 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 04:47:56.550438 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 04:47:56.557193 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 04:47:56.560599 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 04:47:56.564071 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 04:47:56.570433 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 04:47:56.573645 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4697 04:47:56.577115 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4698 04:47:56.583645 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4699 04:47:56.584365 Total UI for P1: 0, mck2ui 16
4700 04:47:56.590574 best dqsien dly found for B0: ( 0, 13, 12)
4701 04:47:56.591169 Total UI for P1: 0, mck2ui 16
4702 04:47:56.593768 best dqsien dly found for B1: ( 0, 13, 10)
4703 04:47:56.600254 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4704 04:47:56.603890 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4705 04:47:56.604470
4706 04:47:56.606957 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4707 04:47:56.610643 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4708 04:47:56.613759 [Gating] SW calibration Done
4709 04:47:56.614375 ==
4710 04:47:56.617038 Dram Type= 6, Freq= 0, CH_1, rank 1
4711 04:47:56.620742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4712 04:47:56.621325 ==
4713 04:47:56.623843 RX Vref Scan: 0
4714 04:47:56.624315
4715 04:47:56.624685 RX Vref 0 -> 0, step: 1
4716 04:47:56.625032
4717 04:47:56.626747 RX Delay -230 -> 252, step: 16
4718 04:47:56.630142 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4719 04:47:56.637092 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4720 04:47:56.640586 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4721 04:47:56.643740 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4722 04:47:56.647351 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4723 04:47:56.650311 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4724 04:47:56.656862 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4725 04:47:56.660253 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4726 04:47:56.663979 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4727 04:47:56.666612 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4728 04:47:56.673514 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4729 04:47:56.677214 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4730 04:47:56.680608 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4731 04:47:56.683460 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4732 04:47:56.690635 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4733 04:47:56.693549 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4734 04:47:56.694089 ==
4735 04:47:56.696552 Dram Type= 6, Freq= 0, CH_1, rank 1
4736 04:47:56.700289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4737 04:47:56.700885 ==
4738 04:47:56.703794 DQS Delay:
4739 04:47:56.704374 DQS0 = 0, DQS1 = 0
4740 04:47:56.704750 DQM Delay:
4741 04:47:56.706599 DQM0 = 51, DQM1 = 45
4742 04:47:56.707068 DQ Delay:
4743 04:47:56.710626 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4744 04:47:56.713560 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4745 04:47:56.717107 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4746 04:47:56.720394 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4747 04:47:56.720973
4748 04:47:56.721343
4749 04:47:56.721690 ==
4750 04:47:56.723524 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 04:47:56.730354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 04:47:56.730935 ==
4753 04:47:56.731312
4754 04:47:56.731659
4755 04:47:56.731992 TX Vref Scan disable
4756 04:47:56.733522 == TX Byte 0 ==
4757 04:47:56.736977 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4758 04:47:56.743352 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4759 04:47:56.743827 == TX Byte 1 ==
4760 04:47:56.746637 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4761 04:47:56.753503 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4762 04:47:56.754292 ==
4763 04:47:56.756587 Dram Type= 6, Freq= 0, CH_1, rank 1
4764 04:47:56.760245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4765 04:47:56.760832 ==
4766 04:47:56.761214
4767 04:47:56.761564
4768 04:47:56.763481 TX Vref Scan disable
4769 04:47:56.763955 == TX Byte 0 ==
4770 04:47:56.770374 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4771 04:47:56.773530 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4772 04:47:56.774184 == TX Byte 1 ==
4773 04:47:56.780119 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4774 04:47:56.783569 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4775 04:47:56.784050
4776 04:47:56.784429 [DATLAT]
4777 04:47:56.786554 Freq=600, CH1 RK1
4778 04:47:56.787154
4779 04:47:56.787537 DATLAT Default: 0x9
4780 04:47:56.789996 0, 0xFFFF, sum = 0
4781 04:47:56.790479 1, 0xFFFF, sum = 0
4782 04:47:56.793357 2, 0xFFFF, sum = 0
4783 04:47:56.796760 3, 0xFFFF, sum = 0
4784 04:47:56.797239 4, 0xFFFF, sum = 0
4785 04:47:56.800024 5, 0xFFFF, sum = 0
4786 04:47:56.800504 6, 0xFFFF, sum = 0
4787 04:47:56.803380 7, 0xFFFF, sum = 0
4788 04:47:56.803973 8, 0x0, sum = 1
4789 04:47:56.806184 9, 0x0, sum = 2
4790 04:47:56.806670 10, 0x0, sum = 3
4791 04:47:56.807057 11, 0x0, sum = 4
4792 04:47:56.809707 best_step = 9
4793 04:47:56.810215
4794 04:47:56.810597 ==
4795 04:47:56.813027 Dram Type= 6, Freq= 0, CH_1, rank 1
4796 04:47:56.816331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4797 04:47:56.816907 ==
4798 04:47:56.819943 RX Vref Scan: 0
4799 04:47:56.820526
4800 04:47:56.820906 RX Vref 0 -> 0, step: 1
4801 04:47:56.821259
4802 04:47:56.822869 RX Delay -163 -> 252, step: 8
4803 04:47:56.830552 iDelay=205, Bit 0, Center 52 (-83 ~ 188) 272
4804 04:47:56.834187 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4805 04:47:56.837116 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4806 04:47:56.840729 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4807 04:47:56.843654 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4808 04:47:56.850160 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4809 04:47:56.853725 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4810 04:47:56.856944 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4811 04:47:56.860340 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4812 04:47:56.867100 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4813 04:47:56.870449 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4814 04:47:56.873496 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4815 04:47:56.877050 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4816 04:47:56.880338 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4817 04:47:56.886828 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4818 04:47:56.890579 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4819 04:47:56.891048 ==
4820 04:47:56.893926 Dram Type= 6, Freq= 0, CH_1, rank 1
4821 04:47:56.896992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4822 04:47:56.897584 ==
4823 04:47:56.900323 DQS Delay:
4824 04:47:56.900800 DQS0 = 0, DQS1 = 0
4825 04:47:56.901176 DQM Delay:
4826 04:47:56.903703 DQM0 = 48, DQM1 = 42
4827 04:47:56.904180 DQ Delay:
4828 04:47:56.906764 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =48
4829 04:47:56.910452 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4830 04:47:56.914011 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =40
4831 04:47:56.916906 DQ12 =48, DQ13 =48, DQ14 =44, DQ15 =52
4832 04:47:56.917495
4833 04:47:56.917908
4834 04:47:56.926782 [DQSOSCAuto] RK1, (LSB)MR18= 0x561c, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4835 04:47:56.927404 CH1 RK1: MR19=808, MR18=561C
4836 04:47:56.933127 CH1_RK1: MR19=0x808, MR18=0x561C, DQSOSC=393, MR23=63, INC=169, DEC=113
4837 04:47:56.936630 [RxdqsGatingPostProcess] freq 600
4838 04:47:56.943303 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4839 04:47:56.946374 Pre-setting of DQS Precalculation
4840 04:47:56.949617 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4841 04:47:56.960179 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4842 04:47:56.966136 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4843 04:47:56.966618
4844 04:47:56.966995
4845 04:47:56.969583 [Calibration Summary] 1200 Mbps
4846 04:47:56.970099 CH 0, Rank 0
4847 04:47:56.973114 SW Impedance : PASS
4848 04:47:56.973694 DUTY Scan : NO K
4849 04:47:56.976964 ZQ Calibration : PASS
4850 04:47:56.980145 Jitter Meter : NO K
4851 04:47:56.980722 CBT Training : PASS
4852 04:47:56.983470 Write leveling : PASS
4853 04:47:56.984051 RX DQS gating : PASS
4854 04:47:56.986317 RX DQ/DQS(RDDQC) : PASS
4855 04:47:56.989449 TX DQ/DQS : PASS
4856 04:47:56.989929 RX DATLAT : PASS
4857 04:47:56.993016 RX DQ/DQS(Engine): PASS
4858 04:47:56.995943 TX OE : NO K
4859 04:47:56.996424 All Pass.
4860 04:47:56.996802
4861 04:47:56.997153 CH 0, Rank 1
4862 04:47:56.999699 SW Impedance : PASS
4863 04:47:57.003012 DUTY Scan : NO K
4864 04:47:57.003487 ZQ Calibration : PASS
4865 04:47:57.006398 Jitter Meter : NO K
4866 04:47:57.009579 CBT Training : PASS
4867 04:47:57.010084 Write leveling : PASS
4868 04:47:57.013073 RX DQS gating : PASS
4869 04:47:57.016395 RX DQ/DQS(RDDQC) : PASS
4870 04:47:57.016979 TX DQ/DQS : PASS
4871 04:47:57.019980 RX DATLAT : PASS
4872 04:47:57.023158 RX DQ/DQS(Engine): PASS
4873 04:47:57.023732 TX OE : NO K
4874 04:47:57.025924 All Pass.
4875 04:47:57.026421
4876 04:47:57.026797 CH 1, Rank 0
4877 04:47:57.029684 SW Impedance : PASS
4878 04:47:57.030326 DUTY Scan : NO K
4879 04:47:57.033368 ZQ Calibration : PASS
4880 04:47:57.036112 Jitter Meter : NO K
4881 04:47:57.036809 CBT Training : PASS
4882 04:47:57.039753 Write leveling : PASS
4883 04:47:57.040276 RX DQS gating : PASS
4884 04:47:57.043017 RX DQ/DQS(RDDQC) : PASS
4885 04:47:57.046038 TX DQ/DQS : PASS
4886 04:47:57.046514 RX DATLAT : PASS
4887 04:47:57.049331 RX DQ/DQS(Engine): PASS
4888 04:47:57.053410 TX OE : NO K
4889 04:47:57.054027 All Pass.
4890 04:47:57.054410
4891 04:47:57.054758 CH 1, Rank 1
4892 04:47:57.056495 SW Impedance : PASS
4893 04:47:57.059780 DUTY Scan : NO K
4894 04:47:57.060372 ZQ Calibration : PASS
4895 04:47:57.062886 Jitter Meter : NO K
4896 04:47:57.066115 CBT Training : PASS
4897 04:47:57.066595 Write leveling : PASS
4898 04:47:57.069543 RX DQS gating : PASS
4899 04:47:57.073028 RX DQ/DQS(RDDQC) : PASS
4900 04:47:57.073623 TX DQ/DQS : PASS
4901 04:47:57.076496 RX DATLAT : PASS
4902 04:47:57.079618 RX DQ/DQS(Engine): PASS
4903 04:47:57.080207 TX OE : NO K
4904 04:47:57.080694 All Pass.
4905 04:47:57.082561
4906 04:47:57.083042 DramC Write-DBI off
4907 04:47:57.086124 PER_BANK_REFRESH: Hybrid Mode
4908 04:47:57.086730 TX_TRACKING: ON
4909 04:47:57.095982 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4910 04:47:57.099418 [FAST_K] Save calibration result to emmc
4911 04:47:57.102613 dramc_set_vcore_voltage set vcore to 662500
4912 04:47:57.105757 Read voltage for 933, 3
4913 04:47:57.106272 Vio18 = 0
4914 04:47:57.109832 Vcore = 662500
4915 04:47:57.110457 Vdram = 0
4916 04:47:57.110833 Vddq = 0
4917 04:47:57.111177 Vmddr = 0
4918 04:47:57.116065 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4919 04:47:57.122848 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4920 04:47:57.123444 MEM_TYPE=3, freq_sel=17
4921 04:47:57.125805 sv_algorithm_assistance_LP4_1600
4922 04:47:57.129240 ============ PULL DRAM RESETB DOWN ============
4923 04:47:57.136052 ========== PULL DRAM RESETB DOWN end =========
4924 04:47:57.139238 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4925 04:47:57.142398 ===================================
4926 04:47:57.145745 LPDDR4 DRAM CONFIGURATION
4927 04:47:57.149482 ===================================
4928 04:47:57.150111 EX_ROW_EN[0] = 0x0
4929 04:47:57.152346 EX_ROW_EN[1] = 0x0
4930 04:47:57.152818 LP4Y_EN = 0x0
4931 04:47:57.156002 WORK_FSP = 0x0
4932 04:47:57.156587 WL = 0x3
4933 04:47:57.158811 RL = 0x3
4934 04:47:57.159281 BL = 0x2
4935 04:47:57.162597 RPST = 0x0
4936 04:47:57.163185 RD_PRE = 0x0
4937 04:47:57.166005 WR_PRE = 0x1
4938 04:47:57.169317 WR_PST = 0x0
4939 04:47:57.169896 DBI_WR = 0x0
4940 04:47:57.172716 DBI_RD = 0x0
4941 04:47:57.173416 OTF = 0x1
4942 04:47:57.175655 ===================================
4943 04:47:57.178719 ===================================
4944 04:47:57.179216 ANA top config
4945 04:47:57.182106 ===================================
4946 04:47:57.186104 DLL_ASYNC_EN = 0
4947 04:47:57.189096 ALL_SLAVE_EN = 1
4948 04:47:57.192182 NEW_RANK_MODE = 1
4949 04:47:57.195659 DLL_IDLE_MODE = 1
4950 04:47:57.196135 LP45_APHY_COMB_EN = 1
4951 04:47:57.199152 TX_ODT_DIS = 1
4952 04:47:57.202516 NEW_8X_MODE = 1
4953 04:47:57.205851 ===================================
4954 04:47:57.209385 ===================================
4955 04:47:57.213036 data_rate = 1866
4956 04:47:57.215978 CKR = 1
4957 04:47:57.216563 DQ_P2S_RATIO = 8
4958 04:47:57.219119 ===================================
4959 04:47:57.222735 CA_P2S_RATIO = 8
4960 04:47:57.226025 DQ_CA_OPEN = 0
4961 04:47:57.229402 DQ_SEMI_OPEN = 0
4962 04:47:57.231997 CA_SEMI_OPEN = 0
4963 04:47:57.235872 CA_FULL_RATE = 0
4964 04:47:57.236452 DQ_CKDIV4_EN = 1
4965 04:47:57.239017 CA_CKDIV4_EN = 1
4966 04:47:57.242286 CA_PREDIV_EN = 0
4967 04:47:57.245928 PH8_DLY = 0
4968 04:47:57.248854 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4969 04:47:57.251993 DQ_AAMCK_DIV = 4
4970 04:47:57.252469 CA_AAMCK_DIV = 4
4971 04:47:57.255693 CA_ADMCK_DIV = 4
4972 04:47:57.258557 DQ_TRACK_CA_EN = 0
4973 04:47:57.262312 CA_PICK = 933
4974 04:47:57.265832 CA_MCKIO = 933
4975 04:47:57.268784 MCKIO_SEMI = 0
4976 04:47:57.272194 PLL_FREQ = 3732
4977 04:47:57.272784 DQ_UI_PI_RATIO = 32
4978 04:47:57.275293 CA_UI_PI_RATIO = 0
4979 04:47:57.278507 ===================================
4980 04:47:57.282298 ===================================
4981 04:47:57.285554 memory_type:LPDDR4
4982 04:47:57.288762 GP_NUM : 10
4983 04:47:57.289352 SRAM_EN : 1
4984 04:47:57.292157 MD32_EN : 0
4985 04:47:57.295327 ===================================
4986 04:47:57.295912 [ANA_INIT] >>>>>>>>>>>>>>
4987 04:47:57.298576 <<<<<< [CONFIGURE PHASE]: ANA_TX
4988 04:47:57.302062 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4989 04:47:57.305303 ===================================
4990 04:47:57.308535 data_rate = 1866,PCW = 0X8f00
4991 04:47:57.312207 ===================================
4992 04:47:57.315385 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4993 04:47:57.322163 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4994 04:47:57.325197 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4995 04:47:57.331799 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4996 04:47:57.335452 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4997 04:47:57.338677 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4998 04:47:57.342134 [ANA_INIT] flow start
4999 04:47:57.342718 [ANA_INIT] PLL >>>>>>>>
5000 04:47:57.345500 [ANA_INIT] PLL <<<<<<<<
5001 04:47:57.348742 [ANA_INIT] MIDPI >>>>>>>>
5002 04:47:57.349215 [ANA_INIT] MIDPI <<<<<<<<
5003 04:47:57.351738 [ANA_INIT] DLL >>>>>>>>
5004 04:47:57.355369 [ANA_INIT] flow end
5005 04:47:57.358595 ============ LP4 DIFF to SE enter ============
5006 04:47:57.361722 ============ LP4 DIFF to SE exit ============
5007 04:47:57.365096 [ANA_INIT] <<<<<<<<<<<<<
5008 04:47:57.368829 [Flow] Enable top DCM control >>>>>
5009 04:47:57.371974 [Flow] Enable top DCM control <<<<<
5010 04:47:57.375189 Enable DLL master slave shuffle
5011 04:47:57.378503 ==============================================================
5012 04:47:57.381860 Gating Mode config
5013 04:47:57.388741 ==============================================================
5014 04:47:57.389326 Config description:
5015 04:47:57.398716 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5016 04:47:57.405358 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5017 04:47:57.408908 SELPH_MODE 0: By rank 1: By Phase
5018 04:47:57.415331 ==============================================================
5019 04:47:57.418824 GAT_TRACK_EN = 1
5020 04:47:57.422376 RX_GATING_MODE = 2
5021 04:47:57.425385 RX_GATING_TRACK_MODE = 2
5022 04:47:57.428623 SELPH_MODE = 1
5023 04:47:57.431662 PICG_EARLY_EN = 1
5024 04:47:57.435461 VALID_LAT_VALUE = 1
5025 04:47:57.438813 ==============================================================
5026 04:47:57.442165 Enter into Gating configuration >>>>
5027 04:47:57.445225 Exit from Gating configuration <<<<
5028 04:47:57.448369 Enter into DVFS_PRE_config >>>>>
5029 04:47:57.458747 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5030 04:47:57.461978 Exit from DVFS_PRE_config <<<<<
5031 04:47:57.465478 Enter into PICG configuration >>>>
5032 04:47:57.468441 Exit from PICG configuration <<<<
5033 04:47:57.472087 [RX_INPUT] configuration >>>>>
5034 04:47:57.475643 [RX_INPUT] configuration <<<<<
5035 04:47:57.478480 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5036 04:47:57.485526 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5037 04:47:57.491865 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5038 04:47:57.498359 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5039 04:47:57.505335 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5040 04:47:57.511672 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5041 04:47:57.514539 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5042 04:47:57.518381 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5043 04:47:57.521788 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5044 04:47:57.528575 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5045 04:47:57.531587 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5046 04:47:57.534966 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5047 04:47:57.538094 ===================================
5048 04:47:57.541389 LPDDR4 DRAM CONFIGURATION
5049 04:47:57.544724 ===================================
5050 04:47:57.545208 EX_ROW_EN[0] = 0x0
5051 04:47:57.547971 EX_ROW_EN[1] = 0x0
5052 04:47:57.548450 LP4Y_EN = 0x0
5053 04:47:57.551358 WORK_FSP = 0x0
5054 04:47:57.554866 WL = 0x3
5055 04:47:57.555449 RL = 0x3
5056 04:47:57.558045 BL = 0x2
5057 04:47:57.558522 RPST = 0x0
5058 04:47:57.561347 RD_PRE = 0x0
5059 04:47:57.561821 WR_PRE = 0x1
5060 04:47:57.565003 WR_PST = 0x0
5061 04:47:57.565583 DBI_WR = 0x0
5062 04:47:57.567749 DBI_RD = 0x0
5063 04:47:57.568229 OTF = 0x1
5064 04:47:57.571041 ===================================
5065 04:47:57.574404 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5066 04:47:57.581684 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5067 04:47:57.584493 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5068 04:47:57.588075 ===================================
5069 04:47:57.591266 LPDDR4 DRAM CONFIGURATION
5070 04:47:57.594412 ===================================
5071 04:47:57.594894 EX_ROW_EN[0] = 0x10
5072 04:47:57.598080 EX_ROW_EN[1] = 0x0
5073 04:47:57.598653 LP4Y_EN = 0x0
5074 04:47:57.601482 WORK_FSP = 0x0
5075 04:47:57.602107 WL = 0x3
5076 04:47:57.604632 RL = 0x3
5077 04:47:57.605109 BL = 0x2
5078 04:47:57.607578 RPST = 0x0
5079 04:47:57.611539 RD_PRE = 0x0
5080 04:47:57.612119 WR_PRE = 0x1
5081 04:47:57.614669 WR_PST = 0x0
5082 04:47:57.615251 DBI_WR = 0x0
5083 04:47:57.617787 DBI_RD = 0x0
5084 04:47:57.618418 OTF = 0x1
5085 04:47:57.620981 ===================================
5086 04:47:57.627603 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5087 04:47:57.631329 nWR fixed to 30
5088 04:47:57.634571 [ModeRegInit_LP4] CH0 RK0
5089 04:47:57.635149 [ModeRegInit_LP4] CH0 RK1
5090 04:47:57.638233 [ModeRegInit_LP4] CH1 RK0
5091 04:47:57.641273 [ModeRegInit_LP4] CH1 RK1
5092 04:47:57.641846 match AC timing 9
5093 04:47:57.647756 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5094 04:47:57.651677 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5095 04:47:57.654606 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5096 04:47:57.660906 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5097 04:47:57.664576 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5098 04:47:57.665153 ==
5099 04:47:57.667879 Dram Type= 6, Freq= 0, CH_0, rank 0
5100 04:47:57.671277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5101 04:47:57.671859 ==
5102 04:47:57.677493 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5103 04:47:57.684490 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5104 04:47:57.687855 [CA 0] Center 38 (7~69) winsize 63
5105 04:47:57.690824 [CA 1] Center 38 (8~69) winsize 62
5106 04:47:57.694891 [CA 2] Center 35 (5~66) winsize 62
5107 04:47:57.697907 [CA 3] Center 34 (4~65) winsize 62
5108 04:47:57.700968 [CA 4] Center 34 (4~65) winsize 62
5109 04:47:57.704184 [CA 5] Center 33 (3~64) winsize 62
5110 04:47:57.704665
5111 04:47:57.707759 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5112 04:47:57.708340
5113 04:47:57.711038 [CATrainingPosCal] consider 1 rank data
5114 04:47:57.714624 u2DelayCellTimex100 = 270/100 ps
5115 04:47:57.717718 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5116 04:47:57.721071 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5117 04:47:57.724185 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5118 04:47:57.727901 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5119 04:47:57.730979 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5120 04:47:57.737467 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5121 04:47:57.738064
5122 04:47:57.740710 CA PerBit enable=1, Macro0, CA PI delay=33
5123 04:47:57.741183
5124 04:47:57.743855 [CBTSetCACLKResult] CA Dly = 33
5125 04:47:57.744327 CS Dly: 6 (0~37)
5126 04:47:57.744706 ==
5127 04:47:57.747382 Dram Type= 6, Freq= 0, CH_0, rank 1
5128 04:47:57.750880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5129 04:47:57.754051 ==
5130 04:47:57.757384 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5131 04:47:57.764414 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5132 04:47:57.767464 [CA 0] Center 38 (8~69) winsize 62
5133 04:47:57.770779 [CA 1] Center 38 (8~69) winsize 62
5134 04:47:57.774007 [CA 2] Center 36 (6~66) winsize 61
5135 04:47:57.777376 [CA 3] Center 35 (5~66) winsize 62
5136 04:47:57.780606 [CA 4] Center 34 (4~65) winsize 62
5137 04:47:57.783935 [CA 5] Center 34 (4~65) winsize 62
5138 04:47:57.784517
5139 04:47:57.787371 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5140 04:47:57.787845
5141 04:47:57.790628 [CATrainingPosCal] consider 2 rank data
5142 04:47:57.793909 u2DelayCellTimex100 = 270/100 ps
5143 04:47:57.797303 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5144 04:47:57.800792 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5145 04:47:57.803899 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5146 04:47:57.807122 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5147 04:47:57.814027 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5148 04:47:57.817383 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5149 04:47:57.817995
5150 04:47:57.820558 CA PerBit enable=1, Macro0, CA PI delay=34
5151 04:47:57.821034
5152 04:47:57.823729 [CBTSetCACLKResult] CA Dly = 34
5153 04:47:57.824332 CS Dly: 7 (0~39)
5154 04:47:57.824742
5155 04:47:57.827038 ----->DramcWriteLeveling(PI) begin...
5156 04:47:57.827519 ==
5157 04:47:57.830212 Dram Type= 6, Freq= 0, CH_0, rank 0
5158 04:47:57.837177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5159 04:47:57.837759 ==
5160 04:47:57.840118 Write leveling (Byte 0): 33 => 33
5161 04:47:57.843696 Write leveling (Byte 1): 30 => 30
5162 04:47:57.844171 DramcWriteLeveling(PI) end<-----
5163 04:47:57.844548
5164 04:47:57.847106 ==
5165 04:47:57.850501 Dram Type= 6, Freq= 0, CH_0, rank 0
5166 04:47:57.853426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5167 04:47:57.853903 ==
5168 04:47:57.857138 [Gating] SW mode calibration
5169 04:47:57.864094 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5170 04:47:57.866722 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5171 04:47:57.874019 0 14 0 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
5172 04:47:57.876971 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5173 04:47:57.880184 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5174 04:47:57.886895 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5175 04:47:57.890249 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5176 04:47:57.893832 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5177 04:47:57.900495 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5178 04:47:57.903299 0 14 28 | B1->B0 | 3030 2323 | 0 0 | (0 0) (1 0)
5179 04:47:57.906973 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5180 04:47:57.913368 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5181 04:47:57.916893 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5182 04:47:57.920112 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5183 04:47:57.927044 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5184 04:47:57.930073 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5185 04:47:57.933580 0 15 24 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
5186 04:47:57.936945 0 15 28 | B1->B0 | 2f2f 4545 | 0 0 | (0 0) (0 0)
5187 04:47:57.943587 1 0 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5188 04:47:57.946716 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 04:47:57.949998 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 04:47:57.956687 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 04:47:57.960362 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 04:47:57.963222 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 04:47:57.970221 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5194 04:47:57.973638 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5195 04:47:57.976730 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 04:47:57.983139 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 04:47:57.986678 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 04:47:57.990075 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 04:47:57.996598 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 04:47:57.999868 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 04:47:58.003395 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 04:47:58.010025 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 04:47:58.013628 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 04:47:58.016944 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 04:47:58.023766 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 04:47:58.027025 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 04:47:58.029851 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 04:47:58.036758 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 04:47:58.040253 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5210 04:47:58.043191 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5211 04:47:58.046703 Total UI for P1: 0, mck2ui 16
5212 04:47:58.050028 best dqsien dly found for B0: ( 1, 2, 24)
5213 04:47:58.052945 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5214 04:47:58.059919 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5215 04:47:58.063206 Total UI for P1: 0, mck2ui 16
5216 04:47:58.066614 best dqsien dly found for B1: ( 1, 2, 30)
5217 04:47:58.070068 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5218 04:47:58.073137 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5219 04:47:58.073714
5220 04:47:58.076427 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5221 04:47:58.079762 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5222 04:47:58.083419 [Gating] SW calibration Done
5223 04:47:58.083994 ==
5224 04:47:58.086330 Dram Type= 6, Freq= 0, CH_0, rank 0
5225 04:47:58.089912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5226 04:47:58.090536 ==
5227 04:47:58.093272 RX Vref Scan: 0
5228 04:47:58.093861
5229 04:47:58.096265 RX Vref 0 -> 0, step: 1
5230 04:47:58.096749
5231 04:47:58.097221 RX Delay -80 -> 252, step: 8
5232 04:47:58.102816 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5233 04:47:58.106226 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5234 04:47:58.110103 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5235 04:47:58.112867 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5236 04:47:58.116493 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5237 04:47:58.123163 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5238 04:47:58.125914 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5239 04:47:58.129632 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5240 04:47:58.132689 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5241 04:47:58.136198 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5242 04:47:58.139415 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5243 04:47:58.146147 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5244 04:47:58.149539 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5245 04:47:58.152656 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5246 04:47:58.155707 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5247 04:47:58.159324 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5248 04:47:58.159806 ==
5249 04:47:58.162489 Dram Type= 6, Freq= 0, CH_0, rank 0
5250 04:47:58.169166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5251 04:47:58.169756 ==
5252 04:47:58.170178 DQS Delay:
5253 04:47:58.172688 DQS0 = 0, DQS1 = 0
5254 04:47:58.173276 DQM Delay:
5255 04:47:58.173653 DQM0 = 105, DQM1 = 90
5256 04:47:58.176049 DQ Delay:
5257 04:47:58.179265 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =99
5258 04:47:58.182433 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5259 04:47:58.185806 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5260 04:47:58.189242 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5261 04:47:58.189826
5262 04:47:58.190261
5263 04:47:58.190618 ==
5264 04:47:58.192470 Dram Type= 6, Freq= 0, CH_0, rank 0
5265 04:47:58.196188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5266 04:47:58.196777 ==
5267 04:47:58.197156
5268 04:47:58.197506
5269 04:47:58.199336 TX Vref Scan disable
5270 04:47:58.202577 == TX Byte 0 ==
5271 04:47:58.205502 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5272 04:47:58.209197 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5273 04:47:58.212491 == TX Byte 1 ==
5274 04:47:58.216028 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5275 04:47:58.219119 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5276 04:47:58.219697 ==
5277 04:47:58.222246 Dram Type= 6, Freq= 0, CH_0, rank 0
5278 04:47:58.225974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 04:47:58.229096 ==
5280 04:47:58.229571
5281 04:47:58.229978
5282 04:47:58.230367 TX Vref Scan disable
5283 04:47:58.232423 == TX Byte 0 ==
5284 04:47:58.235719 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5285 04:47:58.242547 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5286 04:47:58.243132 == TX Byte 1 ==
5287 04:47:58.245794 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5288 04:47:58.252540 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5289 04:47:58.253013
5290 04:47:58.253388 [DATLAT]
5291 04:47:58.253804 Freq=933, CH0 RK0
5292 04:47:58.254191
5293 04:47:58.256126 DATLAT Default: 0xd
5294 04:47:58.256705 0, 0xFFFF, sum = 0
5295 04:47:58.259316 1, 0xFFFF, sum = 0
5296 04:47:58.259910 2, 0xFFFF, sum = 0
5297 04:47:58.262460 3, 0xFFFF, sum = 0
5298 04:47:58.263075 4, 0xFFFF, sum = 0
5299 04:47:58.265678 5, 0xFFFF, sum = 0
5300 04:47:58.269328 6, 0xFFFF, sum = 0
5301 04:47:58.269803 7, 0xFFFF, sum = 0
5302 04:47:58.272752 8, 0xFFFF, sum = 0
5303 04:47:58.273342 9, 0xFFFF, sum = 0
5304 04:47:58.275968 10, 0x0, sum = 1
5305 04:47:58.276578 11, 0x0, sum = 2
5306 04:47:58.276959 12, 0x0, sum = 3
5307 04:47:58.279226 13, 0x0, sum = 4
5308 04:47:58.279704 best_step = 11
5309 04:47:58.280076
5310 04:47:58.280424 ==
5311 04:47:58.282580 Dram Type= 6, Freq= 0, CH_0, rank 0
5312 04:47:58.289295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 04:47:58.289785 ==
5314 04:47:58.290220 RX Vref Scan: 1
5315 04:47:58.290573
5316 04:47:58.292674 RX Vref 0 -> 0, step: 1
5317 04:47:58.293139
5318 04:47:58.296389 RX Delay -53 -> 252, step: 4
5319 04:47:58.296962
5320 04:47:58.299067 Set Vref, RX VrefLevel [Byte0]: 58
5321 04:47:58.302678 [Byte1]: 48
5322 04:47:58.303255
5323 04:47:58.305611 Final RX Vref Byte 0 = 58 to rank0
5324 04:47:58.309636 Final RX Vref Byte 1 = 48 to rank0
5325 04:47:58.312720 Final RX Vref Byte 0 = 58 to rank1
5326 04:47:58.315799 Final RX Vref Byte 1 = 48 to rank1==
5327 04:47:58.319181 Dram Type= 6, Freq= 0, CH_0, rank 0
5328 04:47:58.322373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5329 04:47:58.322853 ==
5330 04:47:58.325525 DQS Delay:
5331 04:47:58.326028 DQS0 = 0, DQS1 = 0
5332 04:47:58.329125 DQM Delay:
5333 04:47:58.329706 DQM0 = 108, DQM1 = 91
5334 04:47:58.330127 DQ Delay:
5335 04:47:58.335783 DQ0 =108, DQ1 =108, DQ2 =104, DQ3 =106
5336 04:47:58.339407 DQ4 =108, DQ5 =98, DQ6 =116, DQ7 =116
5337 04:47:58.342153 DQ8 =86, DQ9 =76, DQ10 =92, DQ11 =90
5338 04:47:58.345856 DQ12 =94, DQ13 =94, DQ14 =102, DQ15 =100
5339 04:47:58.346472
5340 04:47:58.346869
5341 04:47:58.352316 [DQSOSCAuto] RK0, (LSB)MR18= 0x2420, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
5342 04:47:58.355832 CH0 RK0: MR19=505, MR18=2420
5343 04:47:58.362667 CH0_RK0: MR19=0x505, MR18=0x2420, DQSOSC=410, MR23=63, INC=64, DEC=42
5344 04:47:58.363255
5345 04:47:58.365464 ----->DramcWriteLeveling(PI) begin...
5346 04:47:58.365973 ==
5347 04:47:58.369153 Dram Type= 6, Freq= 0, CH_0, rank 1
5348 04:47:58.372682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5349 04:47:58.373401 ==
5350 04:47:58.375566 Write leveling (Byte 0): 32 => 32
5351 04:47:58.378649 Write leveling (Byte 1): 31 => 31
5352 04:47:58.382167 DramcWriteLeveling(PI) end<-----
5353 04:47:58.382739
5354 04:47:58.383117 ==
5355 04:47:58.385646 Dram Type= 6, Freq= 0, CH_0, rank 1
5356 04:47:58.388663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5357 04:47:58.389142 ==
5358 04:47:58.392258 [Gating] SW mode calibration
5359 04:47:58.398450 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5360 04:47:58.405115 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5361 04:47:58.408354 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 04:47:58.415255 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 04:47:58.418279 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 04:47:58.421857 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5365 04:47:58.428505 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5366 04:47:58.431602 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5367 04:47:58.435183 0 14 24 | B1->B0 | 3333 3232 | 1 1 | (1 1) (1 1)
5368 04:47:58.438581 0 14 28 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
5369 04:47:58.445229 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 04:47:58.448616 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 04:47:58.451872 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 04:47:58.458637 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 04:47:58.461455 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5374 04:47:58.464816 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5375 04:47:58.471651 0 15 24 | B1->B0 | 2727 2e2e | 0 1 | (0 0) (0 0)
5376 04:47:58.474792 0 15 28 | B1->B0 | 3939 4343 | 0 0 | (1 1) (0 0)
5377 04:47:58.478014 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 04:47:58.485126 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 04:47:58.488552 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 04:47:58.491707 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 04:47:58.498295 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 04:47:58.501427 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 04:47:58.504635 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5384 04:47:58.511425 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 04:47:58.514837 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 04:47:58.518449 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 04:47:58.525125 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 04:47:58.528456 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 04:47:58.531673 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 04:47:58.538014 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 04:47:58.541315 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 04:47:58.545044 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 04:47:58.551713 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 04:47:58.555171 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 04:47:58.557931 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 04:47:58.564837 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 04:47:58.567878 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 04:47:58.571444 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 04:47:58.574496 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5400 04:47:58.581291 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5401 04:47:58.585009 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5402 04:47:58.588049 Total UI for P1: 0, mck2ui 16
5403 04:47:58.591480 best dqsien dly found for B0: ( 1, 2, 28)
5404 04:47:58.595007 Total UI for P1: 0, mck2ui 16
5405 04:47:58.598308 best dqsien dly found for B1: ( 1, 2, 30)
5406 04:47:58.601646 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5407 04:47:58.605290 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5408 04:47:58.606110
5409 04:47:58.608704 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5410 04:47:58.611440 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5411 04:47:58.614799 [Gating] SW calibration Done
5412 04:47:58.615272 ==
5413 04:47:58.618282 Dram Type= 6, Freq= 0, CH_0, rank 1
5414 04:47:58.621564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5415 04:47:58.625277 ==
5416 04:47:58.625858 RX Vref Scan: 0
5417 04:47:58.626276
5418 04:47:58.628708 RX Vref 0 -> 0, step: 1
5419 04:47:58.629431
5420 04:47:58.631360 RX Delay -80 -> 252, step: 8
5421 04:47:58.634904 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5422 04:47:58.638455 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5423 04:47:58.641589 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5424 04:47:58.644794 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5425 04:47:58.647833 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5426 04:47:58.654810 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5427 04:47:58.658622 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5428 04:47:58.661801 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5429 04:47:58.664778 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5430 04:47:58.667770 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5431 04:47:58.674719 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5432 04:47:58.677795 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5433 04:47:58.681311 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5434 04:47:58.684800 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5435 04:47:58.687851 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5436 04:47:58.691204 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5437 04:47:58.694593 ==
5438 04:47:58.695173 Dram Type= 6, Freq= 0, CH_0, rank 1
5439 04:47:58.701180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5440 04:47:58.701839 ==
5441 04:47:58.702258 DQS Delay:
5442 04:47:58.704606 DQS0 = 0, DQS1 = 0
5443 04:47:58.705178 DQM Delay:
5444 04:47:58.707837 DQM0 = 105, DQM1 = 90
5445 04:47:58.708418 DQ Delay:
5446 04:47:58.710945 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5447 04:47:58.714451 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5448 04:47:58.717749 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =91
5449 04:47:58.720962 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5450 04:47:58.721451
5451 04:47:58.721829
5452 04:47:58.722235 ==
5453 04:47:58.723937 Dram Type= 6, Freq= 0, CH_0, rank 1
5454 04:47:58.727202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5455 04:47:58.727685 ==
5456 04:47:58.728139
5457 04:47:58.730564
5458 04:47:58.731039 TX Vref Scan disable
5459 04:47:58.734507 == TX Byte 0 ==
5460 04:47:58.737359 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5461 04:47:58.740780 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5462 04:47:58.744064 == TX Byte 1 ==
5463 04:47:58.747181 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5464 04:47:58.750571 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5465 04:47:58.751080 ==
5466 04:47:58.753787 Dram Type= 6, Freq= 0, CH_0, rank 1
5467 04:47:58.760250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5468 04:47:58.760700 ==
5469 04:47:58.761132
5470 04:47:58.761546
5471 04:47:58.761969 TX Vref Scan disable
5472 04:47:58.764704 == TX Byte 0 ==
5473 04:47:58.767945 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5474 04:47:58.774720 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5475 04:47:58.775162 == TX Byte 1 ==
5476 04:47:58.777838 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5477 04:47:58.784148 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5478 04:47:58.784585
5479 04:47:58.785011 [DATLAT]
5480 04:47:58.785417 Freq=933, CH0 RK1
5481 04:47:58.785812
5482 04:47:58.787447 DATLAT Default: 0xb
5483 04:47:58.787927 0, 0xFFFF, sum = 0
5484 04:47:58.791174 1, 0xFFFF, sum = 0
5485 04:47:58.791616 2, 0xFFFF, sum = 0
5486 04:47:58.794358 3, 0xFFFF, sum = 0
5487 04:47:58.797566 4, 0xFFFF, sum = 0
5488 04:47:58.798043 5, 0xFFFF, sum = 0
5489 04:47:58.801018 6, 0xFFFF, sum = 0
5490 04:47:58.801458 7, 0xFFFF, sum = 0
5491 04:47:58.804539 8, 0xFFFF, sum = 0
5492 04:47:58.805026 9, 0xFFFF, sum = 0
5493 04:47:58.807243 10, 0x0, sum = 1
5494 04:47:58.807685 11, 0x0, sum = 2
5495 04:47:58.811122 12, 0x0, sum = 3
5496 04:47:58.811588 13, 0x0, sum = 4
5497 04:47:58.812023 best_step = 11
5498 04:47:58.812422
5499 04:47:58.814418 ==
5500 04:47:58.817609 Dram Type= 6, Freq= 0, CH_0, rank 1
5501 04:47:58.820504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5502 04:47:58.820942 ==
5503 04:47:58.821490 RX Vref Scan: 0
5504 04:47:58.822039
5505 04:47:58.824038 RX Vref 0 -> 0, step: 1
5506 04:47:58.824238
5507 04:47:58.827050 RX Delay -53 -> 252, step: 4
5508 04:47:58.833724 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5509 04:47:58.837146 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5510 04:47:58.840511 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5511 04:47:58.843615 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5512 04:47:58.846976 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5513 04:47:58.850323 iDelay=199, Bit 5, Center 96 (11 ~ 182) 172
5514 04:47:58.856804 iDelay=199, Bit 6, Center 110 (23 ~ 198) 176
5515 04:47:58.860460 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5516 04:47:58.863912 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5517 04:47:58.867456 iDelay=199, Bit 9, Center 78 (-5 ~ 162) 168
5518 04:47:58.870785 iDelay=199, Bit 10, Center 92 (7 ~ 178) 172
5519 04:47:58.873553 iDelay=199, Bit 11, Center 90 (7 ~ 174) 168
5520 04:47:58.880201 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5521 04:47:58.883472 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5522 04:47:58.886843 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5523 04:47:58.890457 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5524 04:47:58.890542 ==
5525 04:47:58.893377 Dram Type= 6, Freq= 0, CH_0, rank 1
5526 04:47:58.900184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5527 04:47:58.900269 ==
5528 04:47:58.900337 DQS Delay:
5529 04:47:58.903639 DQS0 = 0, DQS1 = 0
5530 04:47:58.903724 DQM Delay:
5531 04:47:58.903792 DQM0 = 103, DQM1 = 91
5532 04:47:58.907039 DQ Delay:
5533 04:47:58.910300 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =98
5534 04:47:58.913649 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =112
5535 04:47:58.916938 DQ8 =84, DQ9 =78, DQ10 =92, DQ11 =90
5536 04:47:58.920157 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98
5537 04:47:58.920263
5538 04:47:58.920346
5539 04:47:58.926736 [DQSOSCAuto] RK1, (LSB)MR18= 0x2606, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 409 ps
5540 04:47:58.930388 CH0 RK1: MR19=505, MR18=2606
5541 04:47:58.936695 CH0_RK1: MR19=0x505, MR18=0x2606, DQSOSC=409, MR23=63, INC=64, DEC=43
5542 04:47:58.940235 [RxdqsGatingPostProcess] freq 933
5543 04:47:58.946847 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5544 04:47:58.947027 best DQS0 dly(2T, 0.5T) = (0, 10)
5545 04:47:58.950466 best DQS1 dly(2T, 0.5T) = (0, 10)
5546 04:47:58.953670 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5547 04:47:58.957385 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5548 04:47:58.960607 best DQS0 dly(2T, 0.5T) = (0, 10)
5549 04:47:58.963455 best DQS1 dly(2T, 0.5T) = (0, 10)
5550 04:47:58.966767 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5551 04:47:58.970172 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5552 04:47:58.973571 Pre-setting of DQS Precalculation
5553 04:47:58.980343 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5554 04:47:58.980779 ==
5555 04:47:58.983595 Dram Type= 6, Freq= 0, CH_1, rank 0
5556 04:47:58.987090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5557 04:47:58.987527 ==
5558 04:47:58.990223 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5559 04:47:58.996688 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5560 04:47:59.000320 [CA 0] Center 37 (7~68) winsize 62
5561 04:47:59.003929 [CA 1] Center 37 (7~68) winsize 62
5562 04:47:59.007309 [CA 2] Center 35 (5~65) winsize 61
5563 04:47:59.010689 [CA 3] Center 34 (4~65) winsize 62
5564 04:47:59.013976 [CA 4] Center 35 (4~66) winsize 63
5565 04:47:59.017329 [CA 5] Center 34 (4~65) winsize 62
5566 04:47:59.017779
5567 04:47:59.020667 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5568 04:47:59.021100
5569 04:47:59.023844 [CATrainingPosCal] consider 1 rank data
5570 04:47:59.027400 u2DelayCellTimex100 = 270/100 ps
5571 04:47:59.030444 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5572 04:47:59.034037 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5573 04:47:59.040377 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5574 04:47:59.043571 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5575 04:47:59.047115 CA4 delay=35 (4~66),Diff = 1 PI (6 cell)
5576 04:47:59.050370 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5577 04:47:59.050805
5578 04:47:59.053621 CA PerBit enable=1, Macro0, CA PI delay=34
5579 04:47:59.054087
5580 04:47:59.057042 [CBTSetCACLKResult] CA Dly = 34
5581 04:47:59.057480 CS Dly: 6 (0~37)
5582 04:47:59.057828 ==
5583 04:47:59.060487 Dram Type= 6, Freq= 0, CH_1, rank 1
5584 04:47:59.067088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5585 04:47:59.067528 ==
5586 04:47:59.070481 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5587 04:47:59.076830 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5588 04:47:59.080715 [CA 0] Center 37 (7~68) winsize 62
5589 04:47:59.083750 [CA 1] Center 38 (8~69) winsize 62
5590 04:47:59.087064 [CA 2] Center 36 (6~67) winsize 62
5591 04:47:59.090445 [CA 3] Center 35 (5~66) winsize 62
5592 04:47:59.093731 [CA 4] Center 35 (5~66) winsize 62
5593 04:47:59.097101 [CA 5] Center 34 (4~65) winsize 62
5594 04:47:59.097534
5595 04:47:59.100341 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5596 04:47:59.100774
5597 04:47:59.103712 [CATrainingPosCal] consider 2 rank data
5598 04:47:59.107356 u2DelayCellTimex100 = 270/100 ps
5599 04:47:59.110474 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5600 04:47:59.117314 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5601 04:47:59.120408 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5602 04:47:59.123767 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5603 04:47:59.127079 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5604 04:47:59.130322 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5605 04:47:59.130803
5606 04:47:59.133308 CA PerBit enable=1, Macro0, CA PI delay=34
5607 04:47:59.133739
5608 04:47:59.136862 [CBTSetCACLKResult] CA Dly = 34
5609 04:47:59.139974 CS Dly: 7 (0~39)
5610 04:47:59.140406
5611 04:47:59.143418 ----->DramcWriteLeveling(PI) begin...
5612 04:47:59.143967 ==
5613 04:47:59.146440 Dram Type= 6, Freq= 0, CH_1, rank 0
5614 04:47:59.150251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5615 04:47:59.150819 ==
5616 04:47:59.153512 Write leveling (Byte 0): 26 => 26
5617 04:47:59.156593 Write leveling (Byte 1): 29 => 29
5618 04:47:59.160062 DramcWriteLeveling(PI) end<-----
5619 04:47:59.160655
5620 04:47:59.161013 ==
5621 04:47:59.163320 Dram Type= 6, Freq= 0, CH_1, rank 0
5622 04:47:59.166837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5623 04:47:59.167315 ==
5624 04:47:59.169913 [Gating] SW mode calibration
5625 04:47:59.176670 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5626 04:47:59.183081 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5627 04:47:59.186338 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 04:47:59.190053 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5629 04:47:59.196706 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5630 04:47:59.199584 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5631 04:47:59.202863 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5632 04:47:59.209466 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5633 04:47:59.212855 0 14 24 | B1->B0 | 3131 3232 | 1 0 | (1 0) (1 1)
5634 04:47:59.216429 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5635 04:47:59.223141 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 04:47:59.226344 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 04:47:59.229721 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5638 04:47:59.236330 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5639 04:47:59.239733 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5640 04:47:59.243101 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5641 04:47:59.249340 0 15 24 | B1->B0 | 2828 3030 | 1 0 | (0 0) (1 1)
5642 04:47:59.252883 0 15 28 | B1->B0 | 3b3b 4444 | 0 0 | (0 0) (0 0)
5643 04:47:59.256008 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 04:47:59.259540 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 04:47:59.266211 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 04:47:59.269566 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5647 04:47:59.272870 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5648 04:47:59.279544 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 04:47:59.283099 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5650 04:47:59.286423 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5651 04:47:59.292964 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 04:47:59.296102 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 04:47:59.299465 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 04:47:59.305988 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 04:47:59.309181 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 04:47:59.312596 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 04:47:59.319190 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 04:47:59.322671 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 04:47:59.326206 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 04:47:59.332625 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 04:47:59.335900 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 04:47:59.339387 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 04:47:59.346255 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 04:47:59.349176 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5665 04:47:59.352798 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5666 04:47:59.359350 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5667 04:47:59.359786 Total UI for P1: 0, mck2ui 16
5668 04:47:59.365830 best dqsien dly found for B0: ( 1, 2, 22)
5669 04:47:59.366321 Total UI for P1: 0, mck2ui 16
5670 04:47:59.369194 best dqsien dly found for B1: ( 1, 2, 24)
5671 04:47:59.375949 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5672 04:47:59.379223 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5673 04:47:59.379659
5674 04:47:59.382651 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5675 04:47:59.385642 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5676 04:47:59.389032 [Gating] SW calibration Done
5677 04:47:59.389464 ==
5678 04:47:59.392394 Dram Type= 6, Freq= 0, CH_1, rank 0
5679 04:47:59.395747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5680 04:47:59.396185 ==
5681 04:47:59.399105 RX Vref Scan: 0
5682 04:47:59.399538
5683 04:47:59.400024 RX Vref 0 -> 0, step: 1
5684 04:47:59.400412
5685 04:47:59.402201 RX Delay -80 -> 252, step: 8
5686 04:47:59.405516 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5687 04:47:59.412019 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5688 04:47:59.415793 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5689 04:47:59.418818 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5690 04:47:59.422046 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5691 04:47:59.425635 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5692 04:47:59.429060 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5693 04:47:59.435804 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5694 04:47:59.439048 iDelay=208, Bit 8, Center 87 (-8 ~ 183) 192
5695 04:47:59.442154 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5696 04:47:59.445718 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5697 04:47:59.448961 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5698 04:47:59.452378 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5699 04:47:59.458920 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5700 04:47:59.462651 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5701 04:47:59.465657 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5702 04:47:59.466131 ==
5703 04:47:59.468902 Dram Type= 6, Freq= 0, CH_1, rank 0
5704 04:47:59.472515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5705 04:47:59.473011 ==
5706 04:47:59.475859 DQS Delay:
5707 04:47:59.476462 DQS0 = 0, DQS1 = 0
5708 04:47:59.477015 DQM Delay:
5709 04:47:59.479370 DQM0 = 103, DQM1 = 96
5710 04:47:59.480003 DQ Delay:
5711 04:47:59.482568 DQ0 =111, DQ1 =95, DQ2 =91, DQ3 =99
5712 04:47:59.485527 DQ4 =103, DQ5 =111, DQ6 =115, DQ7 =99
5713 04:47:59.488721 DQ8 =87, DQ9 =83, DQ10 =99, DQ11 =87
5714 04:47:59.492260 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5715 04:47:59.492850
5716 04:47:59.495594
5717 04:47:59.496205 ==
5718 04:47:59.499167 Dram Type= 6, Freq= 0, CH_1, rank 0
5719 04:47:59.502346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5720 04:47:59.502939 ==
5721 04:47:59.503468
5722 04:47:59.504013
5723 04:47:59.505521 TX Vref Scan disable
5724 04:47:59.506130 == TX Byte 0 ==
5725 04:47:59.512187 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5726 04:47:59.515569 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5727 04:47:59.516003 == TX Byte 1 ==
5728 04:47:59.522415 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5729 04:47:59.525633 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5730 04:47:59.526107 ==
5731 04:47:59.528871 Dram Type= 6, Freq= 0, CH_1, rank 0
5732 04:47:59.532111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 04:47:59.532550 ==
5734 04:47:59.532895
5735 04:47:59.533218
5736 04:47:59.535576 TX Vref Scan disable
5737 04:47:59.538783 == TX Byte 0 ==
5738 04:47:59.542304 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5739 04:47:59.545454 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5740 04:47:59.548742 == TX Byte 1 ==
5741 04:47:59.552255 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5742 04:47:59.555552 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5743 04:47:59.556076
5744 04:47:59.558836 [DATLAT]
5745 04:47:59.559270 Freq=933, CH1 RK0
5746 04:47:59.559617
5747 04:47:59.562441 DATLAT Default: 0xd
5748 04:47:59.562871 0, 0xFFFF, sum = 0
5749 04:47:59.565512 1, 0xFFFF, sum = 0
5750 04:47:59.566137 2, 0xFFFF, sum = 0
5751 04:47:59.568815 3, 0xFFFF, sum = 0
5752 04:47:59.569447 4, 0xFFFF, sum = 0
5753 04:47:59.572484 5, 0xFFFF, sum = 0
5754 04:47:59.573027 6, 0xFFFF, sum = 0
5755 04:47:59.575593 7, 0xFFFF, sum = 0
5756 04:47:59.576061 8, 0xFFFF, sum = 0
5757 04:47:59.578878 9, 0xFFFF, sum = 0
5758 04:47:59.579317 10, 0x0, sum = 1
5759 04:47:59.582282 11, 0x0, sum = 2
5760 04:47:59.582724 12, 0x0, sum = 3
5761 04:47:59.585652 13, 0x0, sum = 4
5762 04:47:59.586135 best_step = 11
5763 04:47:59.586569
5764 04:47:59.586973 ==
5765 04:47:59.588847 Dram Type= 6, Freq= 0, CH_1, rank 0
5766 04:47:59.592202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5767 04:47:59.595664 ==
5768 04:47:59.596100 RX Vref Scan: 1
5769 04:47:59.596527
5770 04:47:59.599076 RX Vref 0 -> 0, step: 1
5771 04:47:59.599510
5772 04:47:59.599940 RX Delay -53 -> 252, step: 4
5773 04:47:59.602356
5774 04:47:59.602791 Set Vref, RX VrefLevel [Byte0]: 50
5775 04:47:59.605748 [Byte1]: 52
5776 04:47:59.610417
5777 04:47:59.610852 Final RX Vref Byte 0 = 50 to rank0
5778 04:47:59.614006 Final RX Vref Byte 1 = 52 to rank0
5779 04:47:59.617055 Final RX Vref Byte 0 = 50 to rank1
5780 04:47:59.620152 Final RX Vref Byte 1 = 52 to rank1==
5781 04:47:59.624008 Dram Type= 6, Freq= 0, CH_1, rank 0
5782 04:47:59.630409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5783 04:47:59.630856 ==
5784 04:47:59.631200 DQS Delay:
5785 04:47:59.631524 DQS0 = 0, DQS1 = 0
5786 04:47:59.633751 DQM Delay:
5787 04:47:59.634584 DQM0 = 104, DQM1 = 97
5788 04:47:59.637056 DQ Delay:
5789 04:47:59.640444 DQ0 =106, DQ1 =98, DQ2 =96, DQ3 =104
5790 04:47:59.643716 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =100
5791 04:47:59.647083 DQ8 =88, DQ9 =86, DQ10 =100, DQ11 =90
5792 04:47:59.650234 DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =102
5793 04:47:59.650691
5794 04:47:59.651032
5795 04:47:59.657102 [DQSOSCAuto] RK0, (LSB)MR18= 0x172f, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5796 04:47:59.660382 CH1 RK0: MR19=505, MR18=172F
5797 04:47:59.667138 CH1_RK0: MR19=0x505, MR18=0x172F, DQSOSC=407, MR23=63, INC=65, DEC=43
5798 04:47:59.667566
5799 04:47:59.670222 ----->DramcWriteLeveling(PI) begin...
5800 04:47:59.670733 ==
5801 04:47:59.673815 Dram Type= 6, Freq= 0, CH_1, rank 1
5802 04:47:59.676817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5803 04:47:59.677244 ==
5804 04:47:59.680165 Write leveling (Byte 0): 29 => 29
5805 04:47:59.683661 Write leveling (Byte 1): 29 => 29
5806 04:47:59.686892 DramcWriteLeveling(PI) end<-----
5807 04:47:59.687430
5808 04:47:59.687775 ==
5809 04:47:59.689850 Dram Type= 6, Freq= 0, CH_1, rank 1
5810 04:47:59.696864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5811 04:47:59.697289 ==
5812 04:47:59.697632 [Gating] SW mode calibration
5813 04:47:59.706573 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5814 04:47:59.710454 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5815 04:47:59.713518 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5816 04:47:59.720202 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5817 04:47:59.723589 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5818 04:47:59.727021 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5819 04:47:59.733434 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5820 04:47:59.736954 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5821 04:47:59.739839 0 14 24 | B1->B0 | 3030 3333 | 0 0 | (0 1) (0 1)
5822 04:47:59.746677 0 14 28 | B1->B0 | 2525 2e2e | 0 0 | (1 1) (0 0)
5823 04:47:59.749869 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 04:47:59.753216 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5825 04:47:59.760144 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5826 04:47:59.763439 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5827 04:47:59.766791 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5828 04:47:59.773101 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5829 04:47:59.776509 0 15 24 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
5830 04:47:59.780139 0 15 28 | B1->B0 | 4141 3b3b | 0 0 | (0 0) (0 0)
5831 04:47:59.786456 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 04:47:59.789926 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 04:47:59.793253 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 04:47:59.799627 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5835 04:47:59.803162 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 04:47:59.806300 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 04:47:59.812996 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5838 04:47:59.816499 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5839 04:47:59.819829 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 04:47:59.822868 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 04:47:59.829456 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 04:47:59.832992 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 04:47:59.836392 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 04:47:59.842974 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 04:47:59.846213 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 04:47:59.849768 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 04:47:59.856264 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 04:47:59.859421 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 04:47:59.863337 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 04:47:59.869791 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 04:47:59.872793 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 04:47:59.876432 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 04:47:59.882827 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5854 04:47:59.886260 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5855 04:47:59.889347 Total UI for P1: 0, mck2ui 16
5856 04:47:59.892647 best dqsien dly found for B1: ( 1, 2, 24)
5857 04:47:59.896017 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5858 04:47:59.899298 Total UI for P1: 0, mck2ui 16
5859 04:47:59.902488 best dqsien dly found for B0: ( 1, 2, 26)
5860 04:47:59.906048 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5861 04:47:59.909425 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5862 04:47:59.909858
5863 04:47:59.915721 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5864 04:47:59.919213 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5865 04:47:59.922535 [Gating] SW calibration Done
5866 04:47:59.922962 ==
5867 04:47:59.925613 Dram Type= 6, Freq= 0, CH_1, rank 1
5868 04:47:59.928951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5869 04:47:59.929383 ==
5870 04:47:59.929723 RX Vref Scan: 0
5871 04:47:59.930072
5872 04:47:59.932840 RX Vref 0 -> 0, step: 1
5873 04:47:59.933268
5874 04:47:59.935663 RX Delay -80 -> 252, step: 8
5875 04:47:59.939154 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5876 04:47:59.942403 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5877 04:47:59.945641 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5878 04:47:59.952321 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5879 04:47:59.955661 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5880 04:47:59.958854 iDelay=200, Bit 5, Center 107 (16 ~ 199) 184
5881 04:47:59.962107 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5882 04:47:59.965653 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5883 04:47:59.972557 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5884 04:47:59.975570 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5885 04:47:59.978808 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5886 04:47:59.982338 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5887 04:47:59.985405 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5888 04:47:59.988600 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5889 04:47:59.995233 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5890 04:47:59.998586 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5891 04:47:59.999016 ==
5892 04:48:00.002039 Dram Type= 6, Freq= 0, CH_1, rank 1
5893 04:48:00.005097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5894 04:48:00.005576 ==
5895 04:48:00.008544 DQS Delay:
5896 04:48:00.009013 DQS0 = 0, DQS1 = 0
5897 04:48:00.009357 DQM Delay:
5898 04:48:00.011746 DQM0 = 101, DQM1 = 96
5899 04:48:00.012167 DQ Delay:
5900 04:48:00.015200 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5901 04:48:00.018628 DQ4 =103, DQ5 =107, DQ6 =107, DQ7 =99
5902 04:48:00.021928 DQ8 =83, DQ9 =87, DQ10 =99, DQ11 =91
5903 04:48:00.024950 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5904 04:48:00.025508
5905 04:48:00.026026
5906 04:48:00.028294 ==
5907 04:48:00.031655 Dram Type= 6, Freq= 0, CH_1, rank 1
5908 04:48:00.035233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5909 04:48:00.035919 ==
5910 04:48:00.036601
5911 04:48:00.037207
5912 04:48:00.038357 TX Vref Scan disable
5913 04:48:00.038987 == TX Byte 0 ==
5914 04:48:00.041308 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5915 04:48:00.047936 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5916 04:48:00.048523 == TX Byte 1 ==
5917 04:48:00.051404 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5918 04:48:00.057979 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5919 04:48:00.058412 ==
5920 04:48:00.061490 Dram Type= 6, Freq= 0, CH_1, rank 1
5921 04:48:00.064448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5922 04:48:00.064886 ==
5923 04:48:00.065234
5924 04:48:00.065558
5925 04:48:00.067806 TX Vref Scan disable
5926 04:48:00.071425 == TX Byte 0 ==
5927 04:48:00.074326 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5928 04:48:00.077718 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5929 04:48:00.081033 == TX Byte 1 ==
5930 04:48:00.084297 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5931 04:48:00.087960 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5932 04:48:00.088292
5933 04:48:00.090803 [DATLAT]
5934 04:48:00.091110 Freq=933, CH1 RK1
5935 04:48:00.091359
5936 04:48:00.094156 DATLAT Default: 0xb
5937 04:48:00.094464 0, 0xFFFF, sum = 0
5938 04:48:00.097734 1, 0xFFFF, sum = 0
5939 04:48:00.098145 2, 0xFFFF, sum = 0
5940 04:48:00.101015 3, 0xFFFF, sum = 0
5941 04:48:00.101329 4, 0xFFFF, sum = 0
5942 04:48:00.104107 5, 0xFFFF, sum = 0
5943 04:48:00.104422 6, 0xFFFF, sum = 0
5944 04:48:00.107554 7, 0xFFFF, sum = 0
5945 04:48:00.107866 8, 0xFFFF, sum = 0
5946 04:48:00.110974 9, 0xFFFF, sum = 0
5947 04:48:00.111306 10, 0x0, sum = 1
5948 04:48:00.114143 11, 0x0, sum = 2
5949 04:48:00.114465 12, 0x0, sum = 3
5950 04:48:00.117597 13, 0x0, sum = 4
5951 04:48:00.117911 best_step = 11
5952 04:48:00.118181
5953 04:48:00.118411 ==
5954 04:48:00.121036 Dram Type= 6, Freq= 0, CH_1, rank 1
5955 04:48:00.127567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5956 04:48:00.127879 ==
5957 04:48:00.128172 RX Vref Scan: 0
5958 04:48:00.128472
5959 04:48:00.130618 RX Vref 0 -> 0, step: 1
5960 04:48:00.131087
5961 04:48:00.134071 RX Delay -53 -> 252, step: 4
5962 04:48:00.137556 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5963 04:48:00.140952 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5964 04:48:00.147637 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5965 04:48:00.150819 iDelay=199, Bit 3, Center 102 (23 ~ 182) 160
5966 04:48:00.154002 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5967 04:48:00.156981 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5968 04:48:00.160670 iDelay=199, Bit 6, Center 114 (35 ~ 194) 160
5969 04:48:00.167017 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5970 04:48:00.170547 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5971 04:48:00.173818 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5972 04:48:00.177189 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5973 04:48:00.180405 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5974 04:48:00.187167 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5975 04:48:00.190524 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5976 04:48:00.193622 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5977 04:48:00.196919 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5978 04:48:00.197363 ==
5979 04:48:00.200165 Dram Type= 6, Freq= 0, CH_1, rank 1
5980 04:48:00.203518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5981 04:48:00.207003 ==
5982 04:48:00.207457 DQS Delay:
5983 04:48:00.207797 DQS0 = 0, DQS1 = 0
5984 04:48:00.210383 DQM Delay:
5985 04:48:00.210807 DQM0 = 104, DQM1 = 97
5986 04:48:00.213680 DQ Delay:
5987 04:48:00.217369 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =102
5988 04:48:00.220125 DQ4 =106, DQ5 =114, DQ6 =114, DQ7 =102
5989 04:48:00.223725 DQ8 =84, DQ9 =88, DQ10 =96, DQ11 =92
5990 04:48:00.227066 DQ12 =106, DQ13 =104, DQ14 =102, DQ15 =106
5991 04:48:00.227488
5992 04:48:00.227846
5993 04:48:00.233340 [DQSOSCAuto] RK1, (LSB)MR18= 0x22ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
5994 04:48:00.236836 CH1 RK1: MR19=504, MR18=22FF
5995 04:48:00.243757 CH1_RK1: MR19=0x504, MR18=0x22FF, DQSOSC=411, MR23=63, INC=64, DEC=42
5996 04:48:00.246887 [RxdqsGatingPostProcess] freq 933
5997 04:48:00.253485 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5998 04:48:00.253920 best DQS0 dly(2T, 0.5T) = (0, 10)
5999 04:48:00.256826 best DQS1 dly(2T, 0.5T) = (0, 10)
6000 04:48:00.260587 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6001 04:48:00.263798 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6002 04:48:00.267029 best DQS0 dly(2T, 0.5T) = (0, 10)
6003 04:48:00.270359 best DQS1 dly(2T, 0.5T) = (0, 10)
6004 04:48:00.273057 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6005 04:48:00.276107 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6006 04:48:00.279342 Pre-setting of DQS Precalculation
6007 04:48:00.286147 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6008 04:48:00.292790 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6009 04:48:00.299229 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6010 04:48:00.299311
6011 04:48:00.299377
6012 04:48:00.303055 [Calibration Summary] 1866 Mbps
6013 04:48:00.303139 CH 0, Rank 0
6014 04:48:00.306068 SW Impedance : PASS
6015 04:48:00.309394 DUTY Scan : NO K
6016 04:48:00.309501 ZQ Calibration : PASS
6017 04:48:00.312837 Jitter Meter : NO K
6018 04:48:00.312911 CBT Training : PASS
6019 04:48:00.316133 Write leveling : PASS
6020 04:48:00.319446 RX DQS gating : PASS
6021 04:48:00.319530 RX DQ/DQS(RDDQC) : PASS
6022 04:48:00.322515 TX DQ/DQS : PASS
6023 04:48:00.326080 RX DATLAT : PASS
6024 04:48:00.326156 RX DQ/DQS(Engine): PASS
6025 04:48:00.329370 TX OE : NO K
6026 04:48:00.329442 All Pass.
6027 04:48:00.329506
6028 04:48:00.332854 CH 0, Rank 1
6029 04:48:00.332924 SW Impedance : PASS
6030 04:48:00.336224 DUTY Scan : NO K
6031 04:48:00.339888 ZQ Calibration : PASS
6032 04:48:00.340460 Jitter Meter : NO K
6033 04:48:00.343194 CBT Training : PASS
6034 04:48:00.346362 Write leveling : PASS
6035 04:48:00.346827 RX DQS gating : PASS
6036 04:48:00.349565 RX DQ/DQS(RDDQC) : PASS
6037 04:48:00.352875 TX DQ/DQS : PASS
6038 04:48:00.353422 RX DATLAT : PASS
6039 04:48:00.356586 RX DQ/DQS(Engine): PASS
6040 04:48:00.357099 TX OE : NO K
6041 04:48:00.359412 All Pass.
6042 04:48:00.359976
6043 04:48:00.360504 CH 1, Rank 0
6044 04:48:00.363174 SW Impedance : PASS
6045 04:48:00.363684 DUTY Scan : NO K
6046 04:48:00.366056 ZQ Calibration : PASS
6047 04:48:00.369635 Jitter Meter : NO K
6048 04:48:00.370149 CBT Training : PASS
6049 04:48:00.372998 Write leveling : PASS
6050 04:48:00.375964 RX DQS gating : PASS
6051 04:48:00.376525 RX DQ/DQS(RDDQC) : PASS
6052 04:48:00.379509 TX DQ/DQS : PASS
6053 04:48:00.383041 RX DATLAT : PASS
6054 04:48:00.383468 RX DQ/DQS(Engine): PASS
6055 04:48:00.386448 TX OE : NO K
6056 04:48:00.386885 All Pass.
6057 04:48:00.387228
6058 04:48:00.389295 CH 1, Rank 1
6059 04:48:00.389721 SW Impedance : PASS
6060 04:48:00.393339 DUTY Scan : NO K
6061 04:48:00.396194 ZQ Calibration : PASS
6062 04:48:00.396668 Jitter Meter : NO K
6063 04:48:00.399482 CBT Training : PASS
6064 04:48:00.402816 Write leveling : PASS
6065 04:48:00.403243 RX DQS gating : PASS
6066 04:48:00.405875 RX DQ/DQS(RDDQC) : PASS
6067 04:48:00.409352 TX DQ/DQS : PASS
6068 04:48:00.409845 RX DATLAT : PASS
6069 04:48:00.412798 RX DQ/DQS(Engine): PASS
6070 04:48:00.413223 TX OE : NO K
6071 04:48:00.416236 All Pass.
6072 04:48:00.416671
6073 04:48:00.417016 DramC Write-DBI off
6074 04:48:00.419192 PER_BANK_REFRESH: Hybrid Mode
6075 04:48:00.422740 TX_TRACKING: ON
6076 04:48:00.429539 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6077 04:48:00.432600 [FAST_K] Save calibration result to emmc
6078 04:48:00.438984 dramc_set_vcore_voltage set vcore to 650000
6079 04:48:00.439420 Read voltage for 400, 6
6080 04:48:00.439770 Vio18 = 0
6081 04:48:00.442805 Vcore = 650000
6082 04:48:00.443240 Vdram = 0
6083 04:48:00.443587 Vddq = 0
6084 04:48:00.446295 Vmddr = 0
6085 04:48:00.449269 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6086 04:48:00.456088 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6087 04:48:00.456523 MEM_TYPE=3, freq_sel=20
6088 04:48:00.459612 sv_algorithm_assistance_LP4_800
6089 04:48:00.465967 ============ PULL DRAM RESETB DOWN ============
6090 04:48:00.469156 ========== PULL DRAM RESETB DOWN end =========
6091 04:48:00.472604 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6092 04:48:00.475765 ===================================
6093 04:48:00.479387 LPDDR4 DRAM CONFIGURATION
6094 04:48:00.482470 ===================================
6095 04:48:00.485896 EX_ROW_EN[0] = 0x0
6096 04:48:00.486487 EX_ROW_EN[1] = 0x0
6097 04:48:00.489045 LP4Y_EN = 0x0
6098 04:48:00.489884 WORK_FSP = 0x0
6099 04:48:00.492449 WL = 0x2
6100 04:48:00.492878 RL = 0x2
6101 04:48:00.495987 BL = 0x2
6102 04:48:00.496706 RPST = 0x0
6103 04:48:00.499020 RD_PRE = 0x0
6104 04:48:00.499408 WR_PRE = 0x1
6105 04:48:00.502260 WR_PST = 0x0
6106 04:48:00.502689 DBI_WR = 0x0
6107 04:48:00.505520 DBI_RD = 0x0
6108 04:48:00.506128 OTF = 0x1
6109 04:48:00.508891 ===================================
6110 04:48:00.512180 ===================================
6111 04:48:00.515526 ANA top config
6112 04:48:00.519104 ===================================
6113 04:48:00.522491 DLL_ASYNC_EN = 0
6114 04:48:00.522924 ALL_SLAVE_EN = 1
6115 04:48:00.525365 NEW_RANK_MODE = 1
6116 04:48:00.529023 DLL_IDLE_MODE = 1
6117 04:48:00.532482 LP45_APHY_COMB_EN = 1
6118 04:48:00.532912 TX_ODT_DIS = 1
6119 04:48:00.535424 NEW_8X_MODE = 1
6120 04:48:00.538874 ===================================
6121 04:48:00.542374 ===================================
6122 04:48:00.545822 data_rate = 800
6123 04:48:00.549206 CKR = 1
6124 04:48:00.551905 DQ_P2S_RATIO = 4
6125 04:48:00.555436 ===================================
6126 04:48:00.558586 CA_P2S_RATIO = 4
6127 04:48:00.559018 DQ_CA_OPEN = 0
6128 04:48:00.562081 DQ_SEMI_OPEN = 1
6129 04:48:00.565441 CA_SEMI_OPEN = 1
6130 04:48:00.568932 CA_FULL_RATE = 0
6131 04:48:00.572335 DQ_CKDIV4_EN = 0
6132 04:48:00.575170 CA_CKDIV4_EN = 1
6133 04:48:00.575719 CA_PREDIV_EN = 0
6134 04:48:00.578910 PH8_DLY = 0
6135 04:48:00.582312 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6136 04:48:00.585507 DQ_AAMCK_DIV = 0
6137 04:48:00.588535 CA_AAMCK_DIV = 0
6138 04:48:00.592029 CA_ADMCK_DIV = 4
6139 04:48:00.592459 DQ_TRACK_CA_EN = 0
6140 04:48:00.595815 CA_PICK = 800
6141 04:48:00.598840 CA_MCKIO = 400
6142 04:48:00.602132 MCKIO_SEMI = 400
6143 04:48:00.605235 PLL_FREQ = 3016
6144 04:48:00.608630 DQ_UI_PI_RATIO = 32
6145 04:48:00.611931 CA_UI_PI_RATIO = 32
6146 04:48:00.615507 ===================================
6147 04:48:00.618413 ===================================
6148 04:48:00.618886 memory_type:LPDDR4
6149 04:48:00.621782 GP_NUM : 10
6150 04:48:00.625203 SRAM_EN : 1
6151 04:48:00.625831 MD32_EN : 0
6152 04:48:00.628697 ===================================
6153 04:48:00.631987 [ANA_INIT] >>>>>>>>>>>>>>
6154 04:48:00.635164 <<<<<< [CONFIGURE PHASE]: ANA_TX
6155 04:48:00.639060 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6156 04:48:00.641984 ===================================
6157 04:48:00.642484 data_rate = 800,PCW = 0X7400
6158 04:48:00.645407 ===================================
6159 04:48:00.652415 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6160 04:48:00.655298 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6161 04:48:00.668702 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6162 04:48:00.672257 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6163 04:48:00.675447 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6164 04:48:00.678610 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6165 04:48:00.682026 [ANA_INIT] flow start
6166 04:48:00.682574 [ANA_INIT] PLL >>>>>>>>
6167 04:48:00.685405 [ANA_INIT] PLL <<<<<<<<
6168 04:48:00.688625 [ANA_INIT] MIDPI >>>>>>>>
6169 04:48:00.689101 [ANA_INIT] MIDPI <<<<<<<<
6170 04:48:00.692240 [ANA_INIT] DLL >>>>>>>>
6171 04:48:00.695224 [ANA_INIT] flow end
6172 04:48:00.698835 ============ LP4 DIFF to SE enter ============
6173 04:48:00.702001 ============ LP4 DIFF to SE exit ============
6174 04:48:00.705483 [ANA_INIT] <<<<<<<<<<<<<
6175 04:48:00.708713 [Flow] Enable top DCM control >>>>>
6176 04:48:00.711876 [Flow] Enable top DCM control <<<<<
6177 04:48:00.715173 Enable DLL master slave shuffle
6178 04:48:00.718721 ==============================================================
6179 04:48:00.721984 Gating Mode config
6180 04:48:00.728687 ==============================================================
6181 04:48:00.729124 Config description:
6182 04:48:00.738455 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6183 04:48:00.745507 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6184 04:48:00.748485 SELPH_MODE 0: By rank 1: By Phase
6185 04:48:00.755472 ==============================================================
6186 04:48:00.758776 GAT_TRACK_EN = 0
6187 04:48:00.761378 RX_GATING_MODE = 2
6188 04:48:00.764759 RX_GATING_TRACK_MODE = 2
6189 04:48:00.768236 SELPH_MODE = 1
6190 04:48:00.771411 PICG_EARLY_EN = 1
6191 04:48:00.774917 VALID_LAT_VALUE = 1
6192 04:48:00.777812 ==============================================================
6193 04:48:00.781387 Enter into Gating configuration >>>>
6194 04:48:00.784380 Exit from Gating configuration <<<<
6195 04:48:00.788183 Enter into DVFS_PRE_config >>>>>
6196 04:48:00.801275 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6197 04:48:00.804653 Exit from DVFS_PRE_config <<<<<
6198 04:48:00.808069 Enter into PICG configuration >>>>
6199 04:48:00.808154 Exit from PICG configuration <<<<
6200 04:48:00.811072 [RX_INPUT] configuration >>>>>
6201 04:48:00.814632 [RX_INPUT] configuration <<<<<
6202 04:48:00.821123 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6203 04:48:00.824344 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6204 04:48:00.831142 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6205 04:48:00.838148 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6206 04:48:00.844754 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6207 04:48:00.851036 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6208 04:48:00.854527 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6209 04:48:00.858013 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6210 04:48:00.861394 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6211 04:48:00.867731 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6212 04:48:00.871079 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6213 04:48:00.874477 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6214 04:48:00.877820 ===================================
6215 04:48:00.881154 LPDDR4 DRAM CONFIGURATION
6216 04:48:00.884556 ===================================
6217 04:48:00.887723 EX_ROW_EN[0] = 0x0
6218 04:48:00.888155 EX_ROW_EN[1] = 0x0
6219 04:48:00.891054 LP4Y_EN = 0x0
6220 04:48:00.891492 WORK_FSP = 0x0
6221 04:48:00.894390 WL = 0x2
6222 04:48:00.894825 RL = 0x2
6223 04:48:00.897658 BL = 0x2
6224 04:48:00.898127 RPST = 0x0
6225 04:48:00.901046 RD_PRE = 0x0
6226 04:48:00.901510 WR_PRE = 0x1
6227 04:48:00.904189 WR_PST = 0x0
6228 04:48:00.904620 DBI_WR = 0x0
6229 04:48:00.907503 DBI_RD = 0x0
6230 04:48:00.907937 OTF = 0x1
6231 04:48:00.911152 ===================================
6232 04:48:00.917474 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6233 04:48:00.920714 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6234 04:48:00.924298 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6235 04:48:00.927553 ===================================
6236 04:48:00.930883 LPDDR4 DRAM CONFIGURATION
6237 04:48:00.934223 ===================================
6238 04:48:00.937644 EX_ROW_EN[0] = 0x10
6239 04:48:00.938117 EX_ROW_EN[1] = 0x0
6240 04:48:00.940533 LP4Y_EN = 0x0
6241 04:48:00.940964 WORK_FSP = 0x0
6242 04:48:00.943906 WL = 0x2
6243 04:48:00.944339 RL = 0x2
6244 04:48:00.947162 BL = 0x2
6245 04:48:00.947595 RPST = 0x0
6246 04:48:00.951010 RD_PRE = 0x0
6247 04:48:00.951442 WR_PRE = 0x1
6248 04:48:00.954440 WR_PST = 0x0
6249 04:48:00.954934 DBI_WR = 0x0
6250 04:48:00.957150 DBI_RD = 0x0
6251 04:48:00.957579 OTF = 0x1
6252 04:48:00.960676 ===================================
6253 04:48:00.967460 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6254 04:48:00.971817 nWR fixed to 30
6255 04:48:00.975081 [ModeRegInit_LP4] CH0 RK0
6256 04:48:00.975519 [ModeRegInit_LP4] CH0 RK1
6257 04:48:00.978404 [ModeRegInit_LP4] CH1 RK0
6258 04:48:00.981869 [ModeRegInit_LP4] CH1 RK1
6259 04:48:00.982334 match AC timing 19
6260 04:48:00.988706 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6261 04:48:00.991835 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6262 04:48:00.995274 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6263 04:48:01.002013 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6264 04:48:01.005296 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6265 04:48:01.005730 ==
6266 04:48:01.008206 Dram Type= 6, Freq= 0, CH_0, rank 0
6267 04:48:01.011344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6268 04:48:01.011430 ==
6269 04:48:01.018081 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6270 04:48:01.024953 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6271 04:48:01.028512 [CA 0] Center 36 (8~64) winsize 57
6272 04:48:01.031323 [CA 1] Center 36 (8~64) winsize 57
6273 04:48:01.034790 [CA 2] Center 36 (8~64) winsize 57
6274 04:48:01.034908 [CA 3] Center 36 (8~64) winsize 57
6275 04:48:01.038089 [CA 4] Center 36 (8~64) winsize 57
6276 04:48:01.041323 [CA 5] Center 36 (8~64) winsize 57
6277 04:48:01.041410
6278 04:48:01.047816 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6279 04:48:01.047903
6280 04:48:01.051475 [CATrainingPosCal] consider 1 rank data
6281 04:48:01.054668 u2DelayCellTimex100 = 270/100 ps
6282 04:48:01.057671 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 04:48:01.061050 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 04:48:01.064508 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 04:48:01.067937 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 04:48:01.071015 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 04:48:01.074250 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 04:48:01.074398
6289 04:48:01.077724 CA PerBit enable=1, Macro0, CA PI delay=36
6290 04:48:01.077915
6291 04:48:01.081290 [CBTSetCACLKResult] CA Dly = 36
6292 04:48:01.084644 CS Dly: 1 (0~32)
6293 04:48:01.084827 ==
6294 04:48:01.088209 Dram Type= 6, Freq= 0, CH_0, rank 1
6295 04:48:01.091083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6296 04:48:01.091299 ==
6297 04:48:01.097696 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6298 04:48:01.101062 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6299 04:48:01.104435 [CA 0] Center 36 (8~64) winsize 57
6300 04:48:01.107971 [CA 1] Center 36 (8~64) winsize 57
6301 04:48:01.110945 [CA 2] Center 36 (8~64) winsize 57
6302 04:48:01.114760 [CA 3] Center 36 (8~64) winsize 57
6303 04:48:01.117875 [CA 4] Center 36 (8~64) winsize 57
6304 04:48:01.121380 [CA 5] Center 36 (8~64) winsize 57
6305 04:48:01.121823
6306 04:48:01.124412 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6307 04:48:01.124857
6308 04:48:01.127778 [CATrainingPosCal] consider 2 rank data
6309 04:48:01.131397 u2DelayCellTimex100 = 270/100 ps
6310 04:48:01.134620 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 04:48:01.138264 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 04:48:01.141057 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 04:48:01.147865 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 04:48:01.151264 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 04:48:01.154576 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 04:48:01.155001
6317 04:48:01.157669 CA PerBit enable=1, Macro0, CA PI delay=36
6318 04:48:01.158121
6319 04:48:01.161251 [CBTSetCACLKResult] CA Dly = 36
6320 04:48:01.161675 CS Dly: 1 (0~32)
6321 04:48:01.162036
6322 04:48:01.164703 ----->DramcWriteLeveling(PI) begin...
6323 04:48:01.165133 ==
6324 04:48:01.168042 Dram Type= 6, Freq= 0, CH_0, rank 0
6325 04:48:01.174741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 04:48:01.175184 ==
6327 04:48:01.177795 Write leveling (Byte 0): 40 => 8
6328 04:48:01.178267 Write leveling (Byte 1): 32 => 0
6329 04:48:01.181126 DramcWriteLeveling(PI) end<-----
6330 04:48:01.181555
6331 04:48:01.184550 ==
6332 04:48:01.187917 Dram Type= 6, Freq= 0, CH_0, rank 0
6333 04:48:01.191304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6334 04:48:01.191740 ==
6335 04:48:01.194224 [Gating] SW mode calibration
6336 04:48:01.201104 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6337 04:48:01.204218 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6338 04:48:01.211119 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6339 04:48:01.214432 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6340 04:48:01.217570 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6341 04:48:01.224264 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6342 04:48:01.227500 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6343 04:48:01.230766 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6344 04:48:01.237428 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6345 04:48:01.240765 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6346 04:48:01.244278 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6347 04:48:01.247273 Total UI for P1: 0, mck2ui 16
6348 04:48:01.250434 best dqsien dly found for B0: ( 0, 14, 24)
6349 04:48:01.253892 Total UI for P1: 0, mck2ui 16
6350 04:48:01.257399 best dqsien dly found for B1: ( 0, 14, 24)
6351 04:48:01.260606 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6352 04:48:01.263994 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6353 04:48:01.264636
6354 04:48:01.270774 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6355 04:48:01.273646 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6356 04:48:01.277190 [Gating] SW calibration Done
6357 04:48:01.277686 ==
6358 04:48:01.280210 Dram Type= 6, Freq= 0, CH_0, rank 0
6359 04:48:01.283285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6360 04:48:01.283716 ==
6361 04:48:01.284054 RX Vref Scan: 0
6362 04:48:01.286719
6363 04:48:01.287151 RX Vref 0 -> 0, step: 1
6364 04:48:01.287485
6365 04:48:01.290353 RX Delay -410 -> 252, step: 16
6366 04:48:01.293555 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6367 04:48:01.300196 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6368 04:48:01.303760 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6369 04:48:01.307068 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6370 04:48:01.310096 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6371 04:48:01.316743 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6372 04:48:01.319884 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6373 04:48:01.323519 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6374 04:48:01.326649 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6375 04:48:01.333132 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6376 04:48:01.336403 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6377 04:48:01.339921 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6378 04:48:01.343155 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6379 04:48:01.349764 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6380 04:48:01.353453 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6381 04:48:01.356531 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6382 04:48:01.356917 ==
6383 04:48:01.360007 Dram Type= 6, Freq= 0, CH_0, rank 0
6384 04:48:01.366796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6385 04:48:01.367223 ==
6386 04:48:01.367561 DQS Delay:
6387 04:48:01.369759 DQS0 = 27, DQS1 = 43
6388 04:48:01.370229 DQM Delay:
6389 04:48:01.370566 DQM0 = 12, DQM1 = 12
6390 04:48:01.373180 DQ Delay:
6391 04:48:01.376539 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6392 04:48:01.376963 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6393 04:48:01.379850 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6394 04:48:01.383569 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6395 04:48:01.384035
6396 04:48:01.384401
6397 04:48:01.386444 ==
6398 04:48:01.389978 Dram Type= 6, Freq= 0, CH_0, rank 0
6399 04:48:01.392885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6400 04:48:01.393428 ==
6401 04:48:01.393775
6402 04:48:01.394147
6403 04:48:01.396680 TX Vref Scan disable
6404 04:48:01.397098 == TX Byte 0 ==
6405 04:48:01.400002 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6406 04:48:01.406456 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6407 04:48:01.407002 == TX Byte 1 ==
6408 04:48:01.409636 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6409 04:48:01.416372 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6410 04:48:01.416903 ==
6411 04:48:01.419804 Dram Type= 6, Freq= 0, CH_0, rank 0
6412 04:48:01.423206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 04:48:01.423721 ==
6414 04:48:01.424062
6415 04:48:01.424409
6416 04:48:01.426560 TX Vref Scan disable
6417 04:48:01.426979 == TX Byte 0 ==
6418 04:48:01.429693 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6419 04:48:01.436228 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6420 04:48:01.436660 == TX Byte 1 ==
6421 04:48:01.439526 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6422 04:48:01.446210 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6423 04:48:01.446648
6424 04:48:01.446996 [DATLAT]
6425 04:48:01.447303 Freq=400, CH0 RK0
6426 04:48:01.449537
6427 04:48:01.450122 DATLAT Default: 0xf
6428 04:48:01.453087 0, 0xFFFF, sum = 0
6429 04:48:01.453566 1, 0xFFFF, sum = 0
6430 04:48:01.456510 2, 0xFFFF, sum = 0
6431 04:48:01.456889 3, 0xFFFF, sum = 0
6432 04:48:01.460063 4, 0xFFFF, sum = 0
6433 04:48:01.460417 5, 0xFFFF, sum = 0
6434 04:48:01.462931 6, 0xFFFF, sum = 0
6435 04:48:01.463566 7, 0xFFFF, sum = 0
6436 04:48:01.466231 8, 0xFFFF, sum = 0
6437 04:48:01.466651 9, 0xFFFF, sum = 0
6438 04:48:01.469479 10, 0xFFFF, sum = 0
6439 04:48:01.469902 11, 0xFFFF, sum = 0
6440 04:48:01.473114 12, 0xFFFF, sum = 0
6441 04:48:01.473531 13, 0x0, sum = 1
6442 04:48:01.476455 14, 0x0, sum = 2
6443 04:48:01.477055 15, 0x0, sum = 3
6444 04:48:01.479540 16, 0x0, sum = 4
6445 04:48:01.480104 best_step = 14
6446 04:48:01.480514
6447 04:48:01.480868 ==
6448 04:48:01.482760 Dram Type= 6, Freq= 0, CH_0, rank 0
6449 04:48:01.486246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 04:48:01.489616 ==
6451 04:48:01.490062 RX Vref Scan: 1
6452 04:48:01.490407
6453 04:48:01.493158 RX Vref 0 -> 0, step: 1
6454 04:48:01.493558
6455 04:48:01.496374 RX Delay -327 -> 252, step: 8
6456 04:48:01.496864
6457 04:48:01.499736 Set Vref, RX VrefLevel [Byte0]: 58
6458 04:48:01.502989 [Byte1]: 48
6459 04:48:01.503406
6460 04:48:01.506534 Final RX Vref Byte 0 = 58 to rank0
6461 04:48:01.509767 Final RX Vref Byte 1 = 48 to rank0
6462 04:48:01.513009 Final RX Vref Byte 0 = 58 to rank1
6463 04:48:01.516205 Final RX Vref Byte 1 = 48 to rank1==
6464 04:48:01.519245 Dram Type= 6, Freq= 0, CH_0, rank 0
6465 04:48:01.522815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6466 04:48:01.523265 ==
6467 04:48:01.526233 DQS Delay:
6468 04:48:01.526663 DQS0 = 28, DQS1 = 48
6469 04:48:01.529436 DQM Delay:
6470 04:48:01.529850 DQM0 = 11, DQM1 = 16
6471 04:48:01.530259 DQ Delay:
6472 04:48:01.532649 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6473 04:48:01.535897 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6474 04:48:01.539284 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6475 04:48:01.543110 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6476 04:48:01.543531
6477 04:48:01.543925
6478 04:48:01.552814 [DQSOSCAuto] RK0, (LSB)MR18= 0xa9a1, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6479 04:48:01.556135 CH0 RK0: MR19=C0C, MR18=A9A1
6480 04:48:01.559354 CH0_RK0: MR19=0xC0C, MR18=0xA9A1, DQSOSC=388, MR23=63, INC=392, DEC=261
6481 04:48:01.562769 ==
6482 04:48:01.566031 Dram Type= 6, Freq= 0, CH_0, rank 1
6483 04:48:01.569050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6484 04:48:01.569424 ==
6485 04:48:01.572794 [Gating] SW mode calibration
6486 04:48:01.579469 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6487 04:48:01.582493 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6488 04:48:01.589288 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6489 04:48:01.592722 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6490 04:48:01.595992 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6491 04:48:01.602677 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6492 04:48:01.606082 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6493 04:48:01.609435 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6494 04:48:01.615872 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6495 04:48:01.619227 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6496 04:48:01.622442 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6497 04:48:01.625704 Total UI for P1: 0, mck2ui 16
6498 04:48:01.629072 best dqsien dly found for B0: ( 0, 14, 24)
6499 04:48:01.632196 Total UI for P1: 0, mck2ui 16
6500 04:48:01.635553 best dqsien dly found for B1: ( 0, 14, 24)
6501 04:48:01.638964 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6502 04:48:01.642377 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6503 04:48:01.642800
6504 04:48:01.648846 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6505 04:48:01.652218 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6506 04:48:01.652771 [Gating] SW calibration Done
6507 04:48:01.655866 ==
6508 04:48:01.659041 Dram Type= 6, Freq= 0, CH_0, rank 1
6509 04:48:01.662245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6510 04:48:01.662679 ==
6511 04:48:01.663029 RX Vref Scan: 0
6512 04:48:01.663350
6513 04:48:01.665652 RX Vref 0 -> 0, step: 1
6514 04:48:01.666308
6515 04:48:01.668992 RX Delay -410 -> 252, step: 16
6516 04:48:01.671909 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6517 04:48:01.679126 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6518 04:48:01.682114 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6519 04:48:01.685481 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6520 04:48:01.688872 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6521 04:48:01.692357 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6522 04:48:01.698563 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6523 04:48:01.702148 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6524 04:48:01.705428 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6525 04:48:01.708919 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6526 04:48:01.715370 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6527 04:48:01.718896 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6528 04:48:01.722265 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6529 04:48:01.728936 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6530 04:48:01.731897 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6531 04:48:01.735229 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6532 04:48:01.735855 ==
6533 04:48:01.738682 Dram Type= 6, Freq= 0, CH_0, rank 1
6534 04:48:01.742440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6535 04:48:01.742884 ==
6536 04:48:01.745174 DQS Delay:
6537 04:48:01.745805 DQS0 = 27, DQS1 = 43
6538 04:48:01.749045 DQM Delay:
6539 04:48:01.749626 DQM0 = 9, DQM1 = 16
6540 04:48:01.750191 DQ Delay:
6541 04:48:01.752198 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6542 04:48:01.755359 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6543 04:48:01.758820 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6544 04:48:01.762203 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6545 04:48:01.762741
6546 04:48:01.763308
6547 04:48:01.763821 ==
6548 04:48:01.765390 Dram Type= 6, Freq= 0, CH_0, rank 1
6549 04:48:01.772384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6550 04:48:01.772902 ==
6551 04:48:01.773380
6552 04:48:01.773830
6553 04:48:01.774264 TX Vref Scan disable
6554 04:48:01.775705 == TX Byte 0 ==
6555 04:48:01.778565 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6556 04:48:01.782196 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6557 04:48:01.785165 == TX Byte 1 ==
6558 04:48:01.788653 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6559 04:48:01.792127 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6560 04:48:01.792529 ==
6561 04:48:01.795650 Dram Type= 6, Freq= 0, CH_0, rank 1
6562 04:48:01.802005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6563 04:48:01.802525 ==
6564 04:48:01.803044
6565 04:48:01.803480
6566 04:48:01.803809 TX Vref Scan disable
6567 04:48:01.805376 == TX Byte 0 ==
6568 04:48:01.808733 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6569 04:48:01.812180 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6570 04:48:01.815577 == TX Byte 1 ==
6571 04:48:01.818677 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6572 04:48:01.822033 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6573 04:48:01.822534
6574 04:48:01.824991 [DATLAT]
6575 04:48:01.825383 Freq=400, CH0 RK1
6576 04:48:01.825756
6577 04:48:01.828751 DATLAT Default: 0xe
6578 04:48:01.829223 0, 0xFFFF, sum = 0
6579 04:48:01.831781 1, 0xFFFF, sum = 0
6580 04:48:01.832289 2, 0xFFFF, sum = 0
6581 04:48:01.835060 3, 0xFFFF, sum = 0
6582 04:48:01.835543 4, 0xFFFF, sum = 0
6583 04:48:01.838373 5, 0xFFFF, sum = 0
6584 04:48:01.838860 6, 0xFFFF, sum = 0
6585 04:48:01.841730 7, 0xFFFF, sum = 0
6586 04:48:01.842275 8, 0xFFFF, sum = 0
6587 04:48:01.844982 9, 0xFFFF, sum = 0
6588 04:48:01.848463 10, 0xFFFF, sum = 0
6589 04:48:01.848895 11, 0xFFFF, sum = 0
6590 04:48:01.851891 12, 0xFFFF, sum = 0
6591 04:48:01.852419 13, 0x0, sum = 1
6592 04:48:01.854987 14, 0x0, sum = 2
6593 04:48:01.855425 15, 0x0, sum = 3
6594 04:48:01.855773 16, 0x0, sum = 4
6595 04:48:01.858007 best_step = 14
6596 04:48:01.858564
6597 04:48:01.858912 ==
6598 04:48:01.861729 Dram Type= 6, Freq= 0, CH_0, rank 1
6599 04:48:01.865085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6600 04:48:01.865558 ==
6601 04:48:01.868278 RX Vref Scan: 0
6602 04:48:01.868688
6603 04:48:01.869060 RX Vref 0 -> 0, step: 1
6604 04:48:01.871575
6605 04:48:01.872112 RX Delay -327 -> 252, step: 8
6606 04:48:01.879675 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6607 04:48:01.882950 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6608 04:48:01.886466 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6609 04:48:01.889988 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6610 04:48:01.896466 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6611 04:48:01.899828 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6612 04:48:01.903139 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6613 04:48:01.906060 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6614 04:48:01.912828 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6615 04:48:01.915875 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6616 04:48:01.919572 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6617 04:48:01.922584 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6618 04:48:01.929536 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6619 04:48:01.932856 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6620 04:48:01.935834 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6621 04:48:01.942614 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6622 04:48:01.942703 ==
6623 04:48:01.946117 Dram Type= 6, Freq= 0, CH_0, rank 1
6624 04:48:01.949060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6625 04:48:01.949156 ==
6626 04:48:01.949223 DQS Delay:
6627 04:48:01.952602 DQS0 = 28, DQS1 = 40
6628 04:48:01.952703 DQM Delay:
6629 04:48:01.956050 DQM0 = 11, DQM1 = 12
6630 04:48:01.956152 DQ Delay:
6631 04:48:01.959239 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6632 04:48:01.962671 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6633 04:48:01.965713 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6634 04:48:01.969323 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6635 04:48:01.969431
6636 04:48:01.969528
6637 04:48:01.975989 [DQSOSCAuto] RK1, (LSB)MR18= 0xb86b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 386 ps
6638 04:48:01.978826 CH0 RK1: MR19=C0C, MR18=B86B
6639 04:48:01.985668 CH0_RK1: MR19=0xC0C, MR18=0xB86B, DQSOSC=386, MR23=63, INC=396, DEC=264
6640 04:48:01.989169 [RxdqsGatingPostProcess] freq 400
6641 04:48:01.995685 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6642 04:48:01.999369 best DQS0 dly(2T, 0.5T) = (0, 10)
6643 04:48:01.999754 best DQS1 dly(2T, 0.5T) = (0, 10)
6644 04:48:02.002671 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6645 04:48:02.005641 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6646 04:48:02.009023 best DQS0 dly(2T, 0.5T) = (0, 10)
6647 04:48:02.012343 best DQS1 dly(2T, 0.5T) = (0, 10)
6648 04:48:02.015787 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6649 04:48:02.019150 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6650 04:48:02.022460 Pre-setting of DQS Precalculation
6651 04:48:02.029300 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6652 04:48:02.029737 ==
6653 04:48:02.032160 Dram Type= 6, Freq= 0, CH_1, rank 0
6654 04:48:02.035642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6655 04:48:02.036080 ==
6656 04:48:02.042595 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6657 04:48:02.045628 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6658 04:48:02.049173 [CA 0] Center 36 (8~64) winsize 57
6659 04:48:02.052804 [CA 1] Center 36 (8~64) winsize 57
6660 04:48:02.055739 [CA 2] Center 36 (8~64) winsize 57
6661 04:48:02.059200 [CA 3] Center 36 (8~64) winsize 57
6662 04:48:02.062304 [CA 4] Center 36 (8~64) winsize 57
6663 04:48:02.065754 [CA 5] Center 36 (8~64) winsize 57
6664 04:48:02.066236
6665 04:48:02.069455 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6666 04:48:02.069889
6667 04:48:02.072568 [CATrainingPosCal] consider 1 rank data
6668 04:48:02.076254 u2DelayCellTimex100 = 270/100 ps
6669 04:48:02.079526 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 04:48:02.082794 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 04:48:02.086344 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 04:48:02.089283 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 04:48:02.092675 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 04:48:02.099421 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 04:48:02.099850
6676 04:48:02.102929 CA PerBit enable=1, Macro0, CA PI delay=36
6677 04:48:02.103364
6678 04:48:02.105847 [CBTSetCACLKResult] CA Dly = 36
6679 04:48:02.106324 CS Dly: 1 (0~32)
6680 04:48:02.106672 ==
6681 04:48:02.109133 Dram Type= 6, Freq= 0, CH_1, rank 1
6682 04:48:02.112604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6683 04:48:02.116006 ==
6684 04:48:02.119497 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6685 04:48:02.126211 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6686 04:48:02.129433 [CA 0] Center 36 (8~64) winsize 57
6687 04:48:02.132555 [CA 1] Center 36 (8~64) winsize 57
6688 04:48:02.135895 [CA 2] Center 36 (8~64) winsize 57
6689 04:48:02.139222 [CA 3] Center 36 (8~64) winsize 57
6690 04:48:02.142462 [CA 4] Center 36 (8~64) winsize 57
6691 04:48:02.145923 [CA 5] Center 36 (8~64) winsize 57
6692 04:48:02.146612
6693 04:48:02.149174 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6694 04:48:02.149607
6695 04:48:02.152554 [CATrainingPosCal] consider 2 rank data
6696 04:48:02.155863 u2DelayCellTimex100 = 270/100 ps
6697 04:48:02.159059 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 04:48:02.162202 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 04:48:02.165707 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 04:48:02.169231 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 04:48:02.172270 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 04:48:02.175576 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 04:48:02.176013
6704 04:48:02.182489 CA PerBit enable=1, Macro0, CA PI delay=36
6705 04:48:02.182923
6706 04:48:02.183399 [CBTSetCACLKResult] CA Dly = 36
6707 04:48:02.185666 CS Dly: 1 (0~32)
6708 04:48:02.186139
6709 04:48:02.189185 ----->DramcWriteLeveling(PI) begin...
6710 04:48:02.189624 ==
6711 04:48:02.192177 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 04:48:02.195593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 04:48:02.196030 ==
6714 04:48:02.198999 Write leveling (Byte 0): 40 => 8
6715 04:48:02.202018 Write leveling (Byte 1): 32 => 0
6716 04:48:02.205604 DramcWriteLeveling(PI) end<-----
6717 04:48:02.206078
6718 04:48:02.206428 ==
6719 04:48:02.208601 Dram Type= 6, Freq= 0, CH_1, rank 0
6720 04:48:02.212073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6721 04:48:02.212510 ==
6722 04:48:02.215494 [Gating] SW mode calibration
6723 04:48:02.222402 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6724 04:48:02.228757 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6725 04:48:02.231913 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6726 04:48:02.238659 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6727 04:48:02.241987 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6728 04:48:02.245412 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6729 04:48:02.251876 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6730 04:48:02.255145 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6731 04:48:02.258436 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6732 04:48:02.265282 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6733 04:48:02.268363 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6734 04:48:02.271755 Total UI for P1: 0, mck2ui 16
6735 04:48:02.274921 best dqsien dly found for B0: ( 0, 14, 24)
6736 04:48:02.278289 Total UI for P1: 0, mck2ui 16
6737 04:48:02.281475 best dqsien dly found for B1: ( 0, 14, 24)
6738 04:48:02.284839 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6739 04:48:02.287971 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6740 04:48:02.288521
6741 04:48:02.291875 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6742 04:48:02.294735 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6743 04:48:02.298210 [Gating] SW calibration Done
6744 04:48:02.298645 ==
6745 04:48:02.301377 Dram Type= 6, Freq= 0, CH_1, rank 0
6746 04:48:02.304763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6747 04:48:02.308289 ==
6748 04:48:02.308722 RX Vref Scan: 0
6749 04:48:02.309072
6750 04:48:02.311555 RX Vref 0 -> 0, step: 1
6751 04:48:02.311989
6752 04:48:02.314615 RX Delay -410 -> 252, step: 16
6753 04:48:02.318044 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6754 04:48:02.321413 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6755 04:48:02.324843 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6756 04:48:02.331102 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6757 04:48:02.334508 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6758 04:48:02.337748 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6759 04:48:02.341651 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6760 04:48:02.347937 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6761 04:48:02.351362 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6762 04:48:02.354638 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6763 04:48:02.357656 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6764 04:48:02.364656 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6765 04:48:02.367785 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6766 04:48:02.371123 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6767 04:48:02.374566 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6768 04:48:02.381060 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6769 04:48:02.381500 ==
6770 04:48:02.384286 Dram Type= 6, Freq= 0, CH_1, rank 0
6771 04:48:02.387996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6772 04:48:02.388600 ==
6773 04:48:02.391038 DQS Delay:
6774 04:48:02.391472 DQS0 = 27, DQS1 = 43
6775 04:48:02.391817 DQM Delay:
6776 04:48:02.394416 DQM0 = 8, DQM1 = 17
6777 04:48:02.394918 DQ Delay:
6778 04:48:02.397926 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6779 04:48:02.400805 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6780 04:48:02.404287 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6781 04:48:02.407547 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6782 04:48:02.407995
6783 04:48:02.408338
6784 04:48:02.408659 ==
6785 04:48:02.410854 Dram Type= 6, Freq= 0, CH_1, rank 0
6786 04:48:02.414019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6787 04:48:02.414586 ==
6788 04:48:02.415140
6789 04:48:02.417378
6790 04:48:02.417971 TX Vref Scan disable
6791 04:48:02.420940 == TX Byte 0 ==
6792 04:48:02.424299 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6793 04:48:02.427209 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6794 04:48:02.430768 == TX Byte 1 ==
6795 04:48:02.434181 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6796 04:48:02.437567 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6797 04:48:02.438179 ==
6798 04:48:02.440836 Dram Type= 6, Freq= 0, CH_1, rank 0
6799 04:48:02.444146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 04:48:02.447233 ==
6801 04:48:02.447666
6802 04:48:02.448006
6803 04:48:02.448327 TX Vref Scan disable
6804 04:48:02.450581 == TX Byte 0 ==
6805 04:48:02.454030 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6806 04:48:02.457280 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6807 04:48:02.460400 == TX Byte 1 ==
6808 04:48:02.463757 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6809 04:48:02.467016 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6810 04:48:02.467453
6811 04:48:02.470440 [DATLAT]
6812 04:48:02.470873 Freq=400, CH1 RK0
6813 04:48:02.471221
6814 04:48:02.473791 DATLAT Default: 0xf
6815 04:48:02.474259 0, 0xFFFF, sum = 0
6816 04:48:02.477282 1, 0xFFFF, sum = 0
6817 04:48:02.477721 2, 0xFFFF, sum = 0
6818 04:48:02.480536 3, 0xFFFF, sum = 0
6819 04:48:02.480984 4, 0xFFFF, sum = 0
6820 04:48:02.483817 5, 0xFFFF, sum = 0
6821 04:48:02.484420 6, 0xFFFF, sum = 0
6822 04:48:02.487192 7, 0xFFFF, sum = 0
6823 04:48:02.487713 8, 0xFFFF, sum = 0
6824 04:48:02.490295 9, 0xFFFF, sum = 0
6825 04:48:02.490753 10, 0xFFFF, sum = 0
6826 04:48:02.493982 11, 0xFFFF, sum = 0
6827 04:48:02.497201 12, 0xFFFF, sum = 0
6828 04:48:02.497668 13, 0x0, sum = 1
6829 04:48:02.498169 14, 0x0, sum = 2
6830 04:48:02.500423 15, 0x0, sum = 3
6831 04:48:02.500863 16, 0x0, sum = 4
6832 04:48:02.503873 best_step = 14
6833 04:48:02.504304
6834 04:48:02.504646 ==
6835 04:48:02.506835 Dram Type= 6, Freq= 0, CH_1, rank 0
6836 04:48:02.510259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 04:48:02.510803 ==
6838 04:48:02.513498 RX Vref Scan: 1
6839 04:48:02.514089
6840 04:48:02.514506 RX Vref 0 -> 0, step: 1
6841 04:48:02.515101
6842 04:48:02.517050 RX Delay -327 -> 252, step: 8
6843 04:48:02.517556
6844 04:48:02.520076 Set Vref, RX VrefLevel [Byte0]: 50
6845 04:48:02.523580 [Byte1]: 52
6846 04:48:02.528656
6847 04:48:02.529098 Final RX Vref Byte 0 = 50 to rank0
6848 04:48:02.531618 Final RX Vref Byte 1 = 52 to rank0
6849 04:48:02.535403 Final RX Vref Byte 0 = 50 to rank1
6850 04:48:02.538770 Final RX Vref Byte 1 = 52 to rank1==
6851 04:48:02.542057 Dram Type= 6, Freq= 0, CH_1, rank 0
6852 04:48:02.548598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6853 04:48:02.549032 ==
6854 04:48:02.549383 DQS Delay:
6855 04:48:02.549707 DQS0 = 32, DQS1 = 40
6856 04:48:02.551557 DQM Delay:
6857 04:48:02.551990 DQM0 = 11, DQM1 = 12
6858 04:48:02.555437 DQ Delay:
6859 04:48:02.558340 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6860 04:48:02.558785 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =8
6861 04:48:02.561771 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6862 04:48:02.565197 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6863 04:48:02.565651
6864 04:48:02.566045
6865 04:48:02.574918 [DQSOSCAuto] RK0, (LSB)MR18= 0x8fc9, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6866 04:48:02.578322 CH1 RK0: MR19=C0C, MR18=8FC9
6867 04:48:02.585242 CH1_RK0: MR19=0xC0C, MR18=0x8FC9, DQSOSC=384, MR23=63, INC=400, DEC=267
6868 04:48:02.585675 ==
6869 04:48:02.588330 Dram Type= 6, Freq= 0, CH_1, rank 1
6870 04:48:02.591730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6871 04:48:02.592162 ==
6872 04:48:02.594990 [Gating] SW mode calibration
6873 04:48:02.601441 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6874 04:48:02.608026 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6875 04:48:02.611552 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6876 04:48:02.614851 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6877 04:48:02.618205 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6878 04:48:02.624823 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6879 04:48:02.628497 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6880 04:48:02.631322 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6881 04:48:02.638038 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6882 04:48:02.641416 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6883 04:48:02.644922 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6884 04:48:02.648184 Total UI for P1: 0, mck2ui 16
6885 04:48:02.651467 best dqsien dly found for B0: ( 0, 14, 24)
6886 04:48:02.654769 Total UI for P1: 0, mck2ui 16
6887 04:48:02.658327 best dqsien dly found for B1: ( 0, 14, 24)
6888 04:48:02.661540 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6889 04:48:02.664614 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6890 04:48:02.667974
6891 04:48:02.671333 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6892 04:48:02.674830 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6893 04:48:02.678241 [Gating] SW calibration Done
6894 04:48:02.678668 ==
6895 04:48:02.681078 Dram Type= 6, Freq= 0, CH_1, rank 1
6896 04:48:02.684597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6897 04:48:02.685031 ==
6898 04:48:02.685433 RX Vref Scan: 0
6899 04:48:02.687659
6900 04:48:02.688088 RX Vref 0 -> 0, step: 1
6901 04:48:02.688448
6902 04:48:02.691055 RX Delay -410 -> 252, step: 16
6903 04:48:02.694299 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6904 04:48:02.700791 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6905 04:48:02.704448 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6906 04:48:02.707554 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6907 04:48:02.710865 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6908 04:48:02.717423 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6909 04:48:02.720763 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6910 04:48:02.723997 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6911 04:48:02.727346 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6912 04:48:02.734065 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6913 04:48:02.737439 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6914 04:48:02.740992 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6915 04:48:02.743886 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6916 04:48:02.750393 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6917 04:48:02.754207 iDelay=230, Bit 14, Center -19 (-266 ~ 229) 496
6918 04:48:02.757072 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6919 04:48:02.757499 ==
6920 04:48:02.760369 Dram Type= 6, Freq= 0, CH_1, rank 1
6921 04:48:02.767233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6922 04:48:02.767661 ==
6923 04:48:02.768004 DQS Delay:
6924 04:48:02.770342 DQS0 = 35, DQS1 = 43
6925 04:48:02.770858 DQM Delay:
6926 04:48:02.773805 DQM0 = 17, DQM1 = 20
6927 04:48:02.774294 DQ Delay:
6928 04:48:02.777091 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6929 04:48:02.780536 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6930 04:48:02.783634 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6931 04:48:02.787377 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6932 04:48:02.787820
6933 04:48:02.788196
6934 04:48:02.788675 ==
6935 04:48:02.790398 Dram Type= 6, Freq= 0, CH_1, rank 1
6936 04:48:02.793827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6937 04:48:02.794293 ==
6938 04:48:02.794739
6939 04:48:02.795106
6940 04:48:02.796986 TX Vref Scan disable
6941 04:48:02.797426 == TX Byte 0 ==
6942 04:48:02.803582 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6943 04:48:02.806889 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6944 04:48:02.807313 == TX Byte 1 ==
6945 04:48:02.813754 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6946 04:48:02.816726 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6947 04:48:02.817154 ==
6948 04:48:02.820128 Dram Type= 6, Freq= 0, CH_1, rank 1
6949 04:48:02.823508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6950 04:48:02.823933 ==
6951 04:48:02.824273
6952 04:48:02.824589
6953 04:48:02.826983 TX Vref Scan disable
6954 04:48:02.827408 == TX Byte 0 ==
6955 04:48:02.833469 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6956 04:48:02.836942 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6957 04:48:02.837367 == TX Byte 1 ==
6958 04:48:02.840401 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6959 04:48:02.846878 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6960 04:48:02.847305
6961 04:48:02.847644 [DATLAT]
6962 04:48:02.850244 Freq=400, CH1 RK1
6963 04:48:02.850671
6964 04:48:02.851009 DATLAT Default: 0xe
6965 04:48:02.853636 0, 0xFFFF, sum = 0
6966 04:48:02.854105 1, 0xFFFF, sum = 0
6967 04:48:02.856927 2, 0xFFFF, sum = 0
6968 04:48:02.857358 3, 0xFFFF, sum = 0
6969 04:48:02.860227 4, 0xFFFF, sum = 0
6970 04:48:02.860654 5, 0xFFFF, sum = 0
6971 04:48:02.863774 6, 0xFFFF, sum = 0
6972 04:48:02.864205 7, 0xFFFF, sum = 0
6973 04:48:02.867091 8, 0xFFFF, sum = 0
6974 04:48:02.867518 9, 0xFFFF, sum = 0
6975 04:48:02.870552 10, 0xFFFF, sum = 0
6976 04:48:02.870979 11, 0xFFFF, sum = 0
6977 04:48:02.873579 12, 0xFFFF, sum = 0
6978 04:48:02.874049 13, 0x0, sum = 1
6979 04:48:02.876874 14, 0x0, sum = 2
6980 04:48:02.877305 15, 0x0, sum = 3
6981 04:48:02.880292 16, 0x0, sum = 4
6982 04:48:02.880721 best_step = 14
6983 04:48:02.881059
6984 04:48:02.881377 ==
6985 04:48:02.883323 Dram Type= 6, Freq= 0, CH_1, rank 1
6986 04:48:02.890054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6987 04:48:02.890516 ==
6988 04:48:02.890863 RX Vref Scan: 0
6989 04:48:02.891188
6990 04:48:02.893879 RX Vref 0 -> 0, step: 1
6991 04:48:02.894360
6992 04:48:02.896635 RX Delay -327 -> 252, step: 8
6993 04:48:02.903602 iDelay=217, Bit 0, Center -20 (-239 ~ 200) 440
6994 04:48:02.906817 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6995 04:48:02.910248 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6996 04:48:02.913482 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6997 04:48:02.920654 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6998 04:48:02.923323 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6999 04:48:02.926729 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
7000 04:48:02.929890 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
7001 04:48:02.936745 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7002 04:48:02.940057 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
7003 04:48:02.943307 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
7004 04:48:02.946750 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
7005 04:48:02.953409 iDelay=217, Bit 12, Center -16 (-239 ~ 208) 448
7006 04:48:02.956504 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
7007 04:48:02.960003 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
7008 04:48:02.963186 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7009 04:48:02.966707 ==
7010 04:48:02.969872 Dram Type= 6, Freq= 0, CH_1, rank 1
7011 04:48:02.973421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7012 04:48:02.973814 ==
7013 04:48:02.974290 DQS Delay:
7014 04:48:02.976479 DQS0 = 32, DQS1 = 36
7015 04:48:02.976913 DQM Delay:
7016 04:48:02.979809 DQM0 = 10, DQM1 = 12
7017 04:48:02.980220 DQ Delay:
7018 04:48:02.983066 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
7019 04:48:02.986620 DQ4 =16, DQ5 =20, DQ6 =16, DQ7 =8
7020 04:48:02.989730 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
7021 04:48:02.993030 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
7022 04:48:02.993489
7023 04:48:02.993830
7024 04:48:02.999904 [DQSOSCAuto] RK1, (LSB)MR18= 0xaa55, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
7025 04:48:03.003291 CH1 RK1: MR19=C0C, MR18=AA55
7026 04:48:03.009616 CH1_RK1: MR19=0xC0C, MR18=0xAA55, DQSOSC=388, MR23=63, INC=392, DEC=261
7027 04:48:03.013158 [RxdqsGatingPostProcess] freq 400
7028 04:48:03.016820 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7029 04:48:03.019985 best DQS0 dly(2T, 0.5T) = (0, 10)
7030 04:48:03.023037 best DQS1 dly(2T, 0.5T) = (0, 10)
7031 04:48:03.026322 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7032 04:48:03.029732 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7033 04:48:03.033242 best DQS0 dly(2T, 0.5T) = (0, 10)
7034 04:48:03.036451 best DQS1 dly(2T, 0.5T) = (0, 10)
7035 04:48:03.039675 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7036 04:48:03.043195 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7037 04:48:03.046230 Pre-setting of DQS Precalculation
7038 04:48:03.049463 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7039 04:48:03.059614 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7040 04:48:03.066539 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7041 04:48:03.067028
7042 04:48:03.067413
7043 04:48:03.069521 [Calibration Summary] 800 Mbps
7044 04:48:03.070138 CH 0, Rank 0
7045 04:48:03.072917 SW Impedance : PASS
7046 04:48:03.073579 DUTY Scan : NO K
7047 04:48:03.076272 ZQ Calibration : PASS
7048 04:48:03.079820 Jitter Meter : NO K
7049 04:48:03.080251 CBT Training : PASS
7050 04:48:03.082683 Write leveling : PASS
7051 04:48:03.086568 RX DQS gating : PASS
7052 04:48:03.087126 RX DQ/DQS(RDDQC) : PASS
7053 04:48:03.089280 TX DQ/DQS : PASS
7054 04:48:03.092745 RX DATLAT : PASS
7055 04:48:03.093375 RX DQ/DQS(Engine): PASS
7056 04:48:03.095996 TX OE : NO K
7057 04:48:03.096426 All Pass.
7058 04:48:03.096898
7059 04:48:03.099633 CH 0, Rank 1
7060 04:48:03.100172 SW Impedance : PASS
7061 04:48:03.102922 DUTY Scan : NO K
7062 04:48:03.103464 ZQ Calibration : PASS
7063 04:48:03.106250 Jitter Meter : NO K
7064 04:48:03.109470 CBT Training : PASS
7065 04:48:03.109896 Write leveling : NO K
7066 04:48:03.112802 RX DQS gating : PASS
7067 04:48:03.115961 RX DQ/DQS(RDDQC) : PASS
7068 04:48:03.116508 TX DQ/DQS : PASS
7069 04:48:03.119233 RX DATLAT : PASS
7070 04:48:03.122951 RX DQ/DQS(Engine): PASS
7071 04:48:03.123459 TX OE : NO K
7072 04:48:03.126077 All Pass.
7073 04:48:03.126586
7074 04:48:03.127124 CH 1, Rank 0
7075 04:48:03.129368 SW Impedance : PASS
7076 04:48:03.129928 DUTY Scan : NO K
7077 04:48:03.132558 ZQ Calibration : PASS
7078 04:48:03.135852 Jitter Meter : NO K
7079 04:48:03.136366 CBT Training : PASS
7080 04:48:03.139365 Write leveling : PASS
7081 04:48:03.142542 RX DQS gating : PASS
7082 04:48:03.142973 RX DQ/DQS(RDDQC) : PASS
7083 04:48:03.145742 TX DQ/DQS : PASS
7084 04:48:03.148905 RX DATLAT : PASS
7085 04:48:03.149438 RX DQ/DQS(Engine): PASS
7086 04:48:03.152543 TX OE : NO K
7087 04:48:03.153021 All Pass.
7088 04:48:03.153366
7089 04:48:03.155412 CH 1, Rank 1
7090 04:48:03.155905 SW Impedance : PASS
7091 04:48:03.158932 DUTY Scan : NO K
7092 04:48:03.159360 ZQ Calibration : PASS
7093 04:48:03.162440 Jitter Meter : NO K
7094 04:48:03.165910 CBT Training : PASS
7095 04:48:03.166502 Write leveling : NO K
7096 04:48:03.168845 RX DQS gating : PASS
7097 04:48:03.171951 RX DQ/DQS(RDDQC) : PASS
7098 04:48:03.172054 TX DQ/DQS : PASS
7099 04:48:03.175116 RX DATLAT : PASS
7100 04:48:03.178885 RX DQ/DQS(Engine): PASS
7101 04:48:03.179314 TX OE : NO K
7102 04:48:03.182440 All Pass.
7103 04:48:03.182864
7104 04:48:03.183200 DramC Write-DBI off
7105 04:48:03.185893 PER_BANK_REFRESH: Hybrid Mode
7106 04:48:03.186359 TX_TRACKING: ON
7107 04:48:03.195642 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7108 04:48:03.199120 [FAST_K] Save calibration result to emmc
7109 04:48:03.202427 dramc_set_vcore_voltage set vcore to 725000
7110 04:48:03.205566 Read voltage for 1600, 0
7111 04:48:03.206049 Vio18 = 0
7112 04:48:03.208945 Vcore = 725000
7113 04:48:03.209365 Vdram = 0
7114 04:48:03.209704 Vddq = 0
7115 04:48:03.212429 Vmddr = 0
7116 04:48:03.215587 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7117 04:48:03.222017 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7118 04:48:03.222448 MEM_TYPE=3, freq_sel=13
7119 04:48:03.225303 sv_algorithm_assistance_LP4_3733
7120 04:48:03.228993 ============ PULL DRAM RESETB DOWN ============
7121 04:48:03.235396 ========== PULL DRAM RESETB DOWN end =========
7122 04:48:03.238776 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7123 04:48:03.242262 ===================================
7124 04:48:03.245586 LPDDR4 DRAM CONFIGURATION
7125 04:48:03.248963 ===================================
7126 04:48:03.249452 EX_ROW_EN[0] = 0x0
7127 04:48:03.252322 EX_ROW_EN[1] = 0x0
7128 04:48:03.255746 LP4Y_EN = 0x0
7129 04:48:03.256169 WORK_FSP = 0x1
7130 04:48:03.258910 WL = 0x5
7131 04:48:03.259368 RL = 0x5
7132 04:48:03.262031 BL = 0x2
7133 04:48:03.262476 RPST = 0x0
7134 04:48:03.265148 RD_PRE = 0x0
7135 04:48:03.265574 WR_PRE = 0x1
7136 04:48:03.268454 WR_PST = 0x1
7137 04:48:03.268879 DBI_WR = 0x0
7138 04:48:03.272075 DBI_RD = 0x0
7139 04:48:03.272501 OTF = 0x1
7140 04:48:03.275128 ===================================
7141 04:48:03.278362 ===================================
7142 04:48:03.282015 ANA top config
7143 04:48:03.285452 ===================================
7144 04:48:03.285891 DLL_ASYNC_EN = 0
7145 04:48:03.288436 ALL_SLAVE_EN = 0
7146 04:48:03.292028 NEW_RANK_MODE = 1
7147 04:48:03.295252 DLL_IDLE_MODE = 1
7148 04:48:03.298407 LP45_APHY_COMB_EN = 1
7149 04:48:03.298831 TX_ODT_DIS = 0
7150 04:48:03.302062 NEW_8X_MODE = 1
7151 04:48:03.305386 ===================================
7152 04:48:03.308620 ===================================
7153 04:48:03.311731 data_rate = 3200
7154 04:48:03.315418 CKR = 1
7155 04:48:03.318546 DQ_P2S_RATIO = 8
7156 04:48:03.321824 ===================================
7157 04:48:03.322303 CA_P2S_RATIO = 8
7158 04:48:03.324998 DQ_CA_OPEN = 0
7159 04:48:03.328009 DQ_SEMI_OPEN = 0
7160 04:48:03.331174 CA_SEMI_OPEN = 0
7161 04:48:03.334928 CA_FULL_RATE = 0
7162 04:48:03.338236 DQ_CKDIV4_EN = 0
7163 04:48:03.338319 CA_CKDIV4_EN = 0
7164 04:48:03.341161 CA_PREDIV_EN = 0
7165 04:48:03.344488 PH8_DLY = 12
7166 04:48:03.347906 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7167 04:48:03.351070 DQ_AAMCK_DIV = 4
7168 04:48:03.354417 CA_AAMCK_DIV = 4
7169 04:48:03.354505 CA_ADMCK_DIV = 4
7170 04:48:03.357739 DQ_TRACK_CA_EN = 0
7171 04:48:03.361198 CA_PICK = 1600
7172 04:48:03.364548 CA_MCKIO = 1600
7173 04:48:03.367607 MCKIO_SEMI = 0
7174 04:48:03.371090 PLL_FREQ = 3068
7175 04:48:03.374674 DQ_UI_PI_RATIO = 32
7176 04:48:03.377863 CA_UI_PI_RATIO = 0
7177 04:48:03.381325 ===================================
7178 04:48:03.384508 ===================================
7179 04:48:03.384590 memory_type:LPDDR4
7180 04:48:03.387685 GP_NUM : 10
7181 04:48:03.390943 SRAM_EN : 1
7182 04:48:03.391026 MD32_EN : 0
7183 04:48:03.394289 ===================================
7184 04:48:03.397659 [ANA_INIT] >>>>>>>>>>>>>>
7185 04:48:03.400968 <<<<<< [CONFIGURE PHASE]: ANA_TX
7186 04:48:03.404754 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7187 04:48:03.407352 ===================================
7188 04:48:03.410850 data_rate = 3200,PCW = 0X7600
7189 04:48:03.414492 ===================================
7190 04:48:03.417568 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7191 04:48:03.420865 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7192 04:48:03.427897 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7193 04:48:03.430754 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7194 04:48:03.434133 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7195 04:48:03.437351 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7196 04:48:03.440965 [ANA_INIT] flow start
7197 04:48:03.444379 [ANA_INIT] PLL >>>>>>>>
7198 04:48:03.444462 [ANA_INIT] PLL <<<<<<<<
7199 04:48:03.447341 [ANA_INIT] MIDPI >>>>>>>>
7200 04:48:03.450862 [ANA_INIT] MIDPI <<<<<<<<
7201 04:48:03.450945 [ANA_INIT] DLL >>>>>>>>
7202 04:48:03.454113 [ANA_INIT] DLL <<<<<<<<
7203 04:48:03.457664 [ANA_INIT] flow end
7204 04:48:03.460710 ============ LP4 DIFF to SE enter ============
7205 04:48:03.464082 ============ LP4 DIFF to SE exit ============
7206 04:48:03.467516 [ANA_INIT] <<<<<<<<<<<<<
7207 04:48:03.470981 [Flow] Enable top DCM control >>>>>
7208 04:48:03.473933 [Flow] Enable top DCM control <<<<<
7209 04:48:03.477436 Enable DLL master slave shuffle
7210 04:48:03.480766 ==============================================================
7211 04:48:03.484006 Gating Mode config
7212 04:48:03.490938 ==============================================================
7213 04:48:03.491047 Config description:
7214 04:48:03.501031 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7215 04:48:03.507545 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7216 04:48:03.510690 SELPH_MODE 0: By rank 1: By Phase
7217 04:48:03.517388 ==============================================================
7218 04:48:03.521117 GAT_TRACK_EN = 1
7219 04:48:03.524493 RX_GATING_MODE = 2
7220 04:48:03.527697 RX_GATING_TRACK_MODE = 2
7221 04:48:03.530980 SELPH_MODE = 1
7222 04:48:03.534314 PICG_EARLY_EN = 1
7223 04:48:03.537596 VALID_LAT_VALUE = 1
7224 04:48:03.540860 ==============================================================
7225 04:48:03.544146 Enter into Gating configuration >>>>
7226 04:48:03.547497 Exit from Gating configuration <<<<
7227 04:48:03.550821 Enter into DVFS_PRE_config >>>>>
7228 04:48:03.560804 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7229 04:48:03.564083 Exit from DVFS_PRE_config <<<<<
7230 04:48:03.567472 Enter into PICG configuration >>>>
7231 04:48:03.570910 Exit from PICG configuration <<<<
7232 04:48:03.574428 [RX_INPUT] configuration >>>>>
7233 04:48:03.577325 [RX_INPUT] configuration <<<<<
7234 04:48:03.584170 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7235 04:48:03.587567 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7236 04:48:03.594142 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7237 04:48:03.600976 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7238 04:48:03.607506 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7239 04:48:03.614174 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7240 04:48:03.617545 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7241 04:48:03.620718 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7242 04:48:03.624192 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7243 04:48:03.630494 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7244 04:48:03.634105 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7245 04:48:03.637011 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7246 04:48:03.640845 ===================================
7247 04:48:03.643855 LPDDR4 DRAM CONFIGURATION
7248 04:48:03.647179 ===================================
7249 04:48:03.647606 EX_ROW_EN[0] = 0x0
7250 04:48:03.650800 EX_ROW_EN[1] = 0x0
7251 04:48:03.653607 LP4Y_EN = 0x0
7252 04:48:03.654075 WORK_FSP = 0x1
7253 04:48:03.657003 WL = 0x5
7254 04:48:03.657428 RL = 0x5
7255 04:48:03.660591 BL = 0x2
7256 04:48:03.661018 RPST = 0x0
7257 04:48:03.663702 RD_PRE = 0x0
7258 04:48:03.664125 WR_PRE = 0x1
7259 04:48:03.667204 WR_PST = 0x1
7260 04:48:03.667626 DBI_WR = 0x0
7261 04:48:03.670156 DBI_RD = 0x0
7262 04:48:03.670579 OTF = 0x1
7263 04:48:03.673574 ===================================
7264 04:48:03.676901 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7265 04:48:03.683842 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7266 04:48:03.687175 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7267 04:48:03.690215 ===================================
7268 04:48:03.693574 LPDDR4 DRAM CONFIGURATION
7269 04:48:03.696888 ===================================
7270 04:48:03.697310 EX_ROW_EN[0] = 0x10
7271 04:48:03.700275 EX_ROW_EN[1] = 0x0
7272 04:48:03.700700 LP4Y_EN = 0x0
7273 04:48:03.703631 WORK_FSP = 0x1
7274 04:48:03.704098 WL = 0x5
7275 04:48:03.707023 RL = 0x5
7276 04:48:03.710648 BL = 0x2
7277 04:48:03.711069 RPST = 0x0
7278 04:48:03.713511 RD_PRE = 0x0
7279 04:48:03.713932 WR_PRE = 0x1
7280 04:48:03.716769 WR_PST = 0x1
7281 04:48:03.717234 DBI_WR = 0x0
7282 04:48:03.720771 DBI_RD = 0x0
7283 04:48:03.721244 OTF = 0x1
7284 04:48:03.723933 ===================================
7285 04:48:03.730334 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7286 04:48:03.730761 ==
7287 04:48:03.733812 Dram Type= 6, Freq= 0, CH_0, rank 0
7288 04:48:03.737037 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7289 04:48:03.737566 ==
7290 04:48:03.740144 [Duty_Offset_Calibration]
7291 04:48:03.743548 B0:2 B1:0 CA:1
7292 04:48:03.744075
7293 04:48:03.746727 [DutyScan_Calibration_Flow] k_type=0
7294 04:48:03.754555
7295 04:48:03.754978 ==CLK 0==
7296 04:48:03.757420 Final CLK duty delay cell = -4
7297 04:48:03.760912 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7298 04:48:03.764176 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7299 04:48:03.767657 [-4] AVG Duty = 4937%(X100)
7300 04:48:03.768127
7301 04:48:03.770845 CH0 CLK Duty spec in!! Max-Min= 187%
7302 04:48:03.774266 [DutyScan_Calibration_Flow] ====Done====
7303 04:48:03.774734
7304 04:48:03.777702 [DutyScan_Calibration_Flow] k_type=1
7305 04:48:03.793996
7306 04:48:03.794475 ==DQS 0 ==
7307 04:48:03.796888 Final DQS duty delay cell = 0
7308 04:48:03.800236 [0] MAX Duty = 5249%(X100), DQS PI = 32
7309 04:48:03.803701 [0] MIN Duty = 4969%(X100), DQS PI = 0
7310 04:48:03.804129 [0] AVG Duty = 5109%(X100)
7311 04:48:03.807042
7312 04:48:03.807464 ==DQS 1 ==
7313 04:48:03.810439 Final DQS duty delay cell = -4
7314 04:48:03.813862 [-4] MAX Duty = 5125%(X100), DQS PI = 46
7315 04:48:03.817179 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7316 04:48:03.820441 [-4] AVG Duty = 5000%(X100)
7317 04:48:03.820867
7318 04:48:03.823802 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7319 04:48:03.824340
7320 04:48:03.827075 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7321 04:48:03.830276 [DutyScan_Calibration_Flow] ====Done====
7322 04:48:03.830703
7323 04:48:03.833377 [DutyScan_Calibration_Flow] k_type=3
7324 04:48:03.851213
7325 04:48:03.851773 ==DQM 0 ==
7326 04:48:03.854351 Final DQM duty delay cell = 0
7327 04:48:03.857708 [0] MAX Duty = 5093%(X100), DQS PI = 26
7328 04:48:03.861510 [0] MIN Duty = 4813%(X100), DQS PI = 50
7329 04:48:03.864526 [0] AVG Duty = 4953%(X100)
7330 04:48:03.864953
7331 04:48:03.865293 ==DQM 1 ==
7332 04:48:03.867844 Final DQM duty delay cell = 0
7333 04:48:03.871432 [0] MAX Duty = 5249%(X100), DQS PI = 28
7334 04:48:03.874552 [0] MIN Duty = 5031%(X100), DQS PI = 8
7335 04:48:03.877977 [0] AVG Duty = 5140%(X100)
7336 04:48:03.878454
7337 04:48:03.881019 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7338 04:48:03.881450
7339 04:48:03.884287 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7340 04:48:03.887538 [DutyScan_Calibration_Flow] ====Done====
7341 04:48:03.887622
7342 04:48:03.890860 [DutyScan_Calibration_Flow] k_type=2
7343 04:48:03.907812
7344 04:48:03.907896 ==DQ 0 ==
7345 04:48:03.911344 Final DQ duty delay cell = 0
7346 04:48:03.914863 [0] MAX Duty = 5124%(X100), DQS PI = 32
7347 04:48:03.918217 [0] MIN Duty = 5000%(X100), DQS PI = 0
7348 04:48:03.918301 [0] AVG Duty = 5062%(X100)
7349 04:48:03.918368
7350 04:48:03.921472 ==DQ 1 ==
7351 04:48:03.924700 Final DQ duty delay cell = 0
7352 04:48:03.928139 [0] MAX Duty = 4969%(X100), DQS PI = 44
7353 04:48:03.931437 [0] MIN Duty = 4875%(X100), DQS PI = 10
7354 04:48:03.931535 [0] AVG Duty = 4922%(X100)
7355 04:48:03.931612
7356 04:48:03.934630 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7357 04:48:03.937807
7358 04:48:03.941074 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7359 04:48:03.944343 [DutyScan_Calibration_Flow] ====Done====
7360 04:48:03.944465 ==
7361 04:48:03.948014 Dram Type= 6, Freq= 0, CH_1, rank 0
7362 04:48:03.951152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7363 04:48:03.951289 ==
7364 04:48:03.954413 [Duty_Offset_Calibration]
7365 04:48:03.954564 B0:0 B1:-1 CA:2
7366 04:48:03.954683
7367 04:48:03.957549 [DutyScan_Calibration_Flow] k_type=0
7368 04:48:03.968363
7369 04:48:03.968602 ==CLK 0==
7370 04:48:03.971531 Final CLK duty delay cell = 0
7371 04:48:03.975467 [0] MAX Duty = 5156%(X100), DQS PI = 10
7372 04:48:03.978429 [0] MIN Duty = 4906%(X100), DQS PI = 44
7373 04:48:03.978817 [0] AVG Duty = 5031%(X100)
7374 04:48:03.982029
7375 04:48:03.985480 CH1 CLK Duty spec in!! Max-Min= 250%
7376 04:48:03.988459 [DutyScan_Calibration_Flow] ====Done====
7377 04:48:03.988948
7378 04:48:03.991764 [DutyScan_Calibration_Flow] k_type=1
7379 04:48:04.008143
7380 04:48:04.008564 ==DQS 0 ==
7381 04:48:04.011636 Final DQS duty delay cell = 0
7382 04:48:04.014953 [0] MAX Duty = 5124%(X100), DQS PI = 24
7383 04:48:04.018231 [0] MIN Duty = 5000%(X100), DQS PI = 0
7384 04:48:04.018698 [0] AVG Duty = 5062%(X100)
7385 04:48:04.021712
7386 04:48:04.022247 ==DQS 1 ==
7387 04:48:04.025177 Final DQS duty delay cell = 0
7388 04:48:04.028525 [0] MAX Duty = 5156%(X100), DQS PI = 0
7389 04:48:04.031817 [0] MIN Duty = 4844%(X100), DQS PI = 34
7390 04:48:04.032247 [0] AVG Duty = 5000%(X100)
7391 04:48:04.032608
7392 04:48:04.034928 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7393 04:48:04.038676
7394 04:48:04.041927 CH1 DQS 1 Duty spec in!! Max-Min= 312%
7395 04:48:04.045089 [DutyScan_Calibration_Flow] ====Done====
7396 04:48:04.045555
7397 04:48:04.048579 [DutyScan_Calibration_Flow] k_type=3
7398 04:48:04.065543
7399 04:48:04.065997 ==DQM 0 ==
7400 04:48:04.069146 Final DQM duty delay cell = 4
7401 04:48:04.072582 [4] MAX Duty = 5125%(X100), DQS PI = 6
7402 04:48:04.076014 [4] MIN Duty = 4969%(X100), DQS PI = 44
7403 04:48:04.076446 [4] AVG Duty = 5047%(X100)
7404 04:48:04.079529
7405 04:48:04.079952 ==DQM 1 ==
7406 04:48:04.082364 Final DQM duty delay cell = 0
7407 04:48:04.085568 [0] MAX Duty = 5281%(X100), DQS PI = 58
7408 04:48:04.088976 [0] MIN Duty = 4844%(X100), DQS PI = 34
7409 04:48:04.089444 [0] AVG Duty = 5062%(X100)
7410 04:48:04.092553
7411 04:48:04.095852 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7412 04:48:04.096279
7413 04:48:04.099232 CH1 DQM 1 Duty spec in!! Max-Min= 437%
7414 04:48:04.102428 [DutyScan_Calibration_Flow] ====Done====
7415 04:48:04.102861
7416 04:48:04.105589 [DutyScan_Calibration_Flow] k_type=2
7417 04:48:04.122228
7418 04:48:04.122313 ==DQ 0 ==
7419 04:48:04.125631 Final DQ duty delay cell = 0
7420 04:48:04.129053 [0] MAX Duty = 5062%(X100), DQS PI = 22
7421 04:48:04.132331 [0] MIN Duty = 4969%(X100), DQS PI = 46
7422 04:48:04.132415 [0] AVG Duty = 5015%(X100)
7423 04:48:04.135842
7424 04:48:04.135926 ==DQ 1 ==
7425 04:48:04.139276 Final DQ duty delay cell = 0
7426 04:48:04.142332 [0] MAX Duty = 5062%(X100), DQS PI = 2
7427 04:48:04.145827 [0] MIN Duty = 4813%(X100), DQS PI = 36
7428 04:48:04.145960 [0] AVG Duty = 4937%(X100)
7429 04:48:04.146044
7430 04:48:04.149222 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7431 04:48:04.149307
7432 04:48:04.152276 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7433 04:48:04.158604 [DutyScan_Calibration_Flow] ====Done====
7434 04:48:04.161909 nWR fixed to 30
7435 04:48:04.162058 [ModeRegInit_LP4] CH0 RK0
7436 04:48:04.165580 [ModeRegInit_LP4] CH0 RK1
7437 04:48:04.169123 [ModeRegInit_LP4] CH1 RK0
7438 04:48:04.169208 [ModeRegInit_LP4] CH1 RK1
7439 04:48:04.172312 match AC timing 5
7440 04:48:04.175361 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7441 04:48:04.178715 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7442 04:48:04.185547 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7443 04:48:04.188731 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7444 04:48:04.195206 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7445 04:48:04.195305 [MiockJmeterHQA]
7446 04:48:04.195373
7447 04:48:04.198973 [DramcMiockJmeter] u1RxGatingPI = 0
7448 04:48:04.202006 0 : 4253, 4027
7449 04:48:04.202092 4 : 4252, 4026
7450 04:48:04.202162 8 : 4255, 4030
7451 04:48:04.205227 12 : 4365, 4142
7452 04:48:04.205314 16 : 4253, 4027
7453 04:48:04.208697 20 : 4255, 4029
7454 04:48:04.208783 24 : 4253, 4027
7455 04:48:04.212140 28 : 4363, 4137
7456 04:48:04.212226 32 : 4363, 4137
7457 04:48:04.212294 36 : 4253, 4027
7458 04:48:04.215578 40 : 4252, 4027
7459 04:48:04.215664 44 : 4250, 4026
7460 04:48:04.219021 48 : 4253, 4027
7461 04:48:04.219106 52 : 4253, 4029
7462 04:48:04.222031 56 : 4250, 4027
7463 04:48:04.222116 60 : 4250, 4027
7464 04:48:04.225435 64 : 4250, 4027
7465 04:48:04.225521 68 : 4250, 4027
7466 04:48:04.225589 72 : 4250, 4027
7467 04:48:04.228828 76 : 4250, 4027
7468 04:48:04.228920 80 : 4361, 4137
7469 04:48:04.232388 84 : 4361, 4137
7470 04:48:04.232480 88 : 4361, 3790
7471 04:48:04.235730 92 : 4249, 1
7472 04:48:04.235830 96 : 4250, 0
7473 04:48:04.235909 100 : 4250, 0
7474 04:48:04.238805 104 : 4363, 0
7475 04:48:04.238912 108 : 4250, 0
7476 04:48:04.238997 112 : 4249, 0
7477 04:48:04.242446 116 : 4250, 0
7478 04:48:04.242553 120 : 4253, 0
7479 04:48:04.245745 124 : 4250, 0
7480 04:48:04.245861 128 : 4250, 0
7481 04:48:04.245965 132 : 4255, 0
7482 04:48:04.249174 136 : 4361, 0
7483 04:48:04.249612 140 : 4360, 0
7484 04:48:04.252500 144 : 4363, 0
7485 04:48:04.252941 148 : 4249, 0
7486 04:48:04.253327 152 : 4250, 0
7487 04:48:04.255934 156 : 4366, 0
7488 04:48:04.256374 160 : 4250, 0
7489 04:48:04.256724 164 : 4250, 0
7490 04:48:04.259339 168 : 4250, 0
7491 04:48:04.259780 172 : 4252, 0
7492 04:48:04.262557 176 : 4250, 0
7493 04:48:04.262998 180 : 4250, 0
7494 04:48:04.263510 184 : 4252, 0
7495 04:48:04.265848 188 : 4361, 0
7496 04:48:04.266368 192 : 4250, 0
7497 04:48:04.268977 196 : 4363, 0
7498 04:48:04.269419 200 : 4257, 2
7499 04:48:04.269773 204 : 4250, 2037
7500 04:48:04.272575 208 : 4253, 4027
7501 04:48:04.273017 212 : 4253, 4029
7502 04:48:04.275980 216 : 4255, 4029
7503 04:48:04.276538 220 : 4361, 4137
7504 04:48:04.279120 224 : 4363, 4137
7505 04:48:04.279726 228 : 4250, 4026
7506 04:48:04.282554 232 : 4255, 4029
7507 04:48:04.283075 236 : 4250, 4026
7508 04:48:04.285735 240 : 4253, 4027
7509 04:48:04.286240 244 : 4250, 4027
7510 04:48:04.289118 248 : 4363, 4139
7511 04:48:04.289560 252 : 4250, 4026
7512 04:48:04.292497 256 : 4250, 4027
7513 04:48:04.292937 260 : 4361, 4138
7514 04:48:04.293287 264 : 4250, 4026
7515 04:48:04.295846 268 : 4250, 4027
7516 04:48:04.296288 272 : 4361, 4137
7517 04:48:04.299406 276 : 4363, 4137
7518 04:48:04.299846 280 : 4250, 4026
7519 04:48:04.302262 284 : 4255, 4029
7520 04:48:04.302701 288 : 4250, 4027
7521 04:48:04.305701 292 : 4250, 4027
7522 04:48:04.306197 296 : 4250, 4027
7523 04:48:04.309113 300 : 4363, 4139
7524 04:48:04.309550 304 : 4250, 4026
7525 04:48:04.312525 308 : 4250, 4027
7526 04:48:04.312963 312 : 4361, 4105
7527 04:48:04.315327 316 : 4250, 2129
7528 04:48:04.315768 320 : 4250, 3
7529 04:48:04.316120
7530 04:48:04.318963 MIOCK jitter meter ch=0
7531 04:48:04.319399
7532 04:48:04.321892 1T = (320-92) = 228 dly cells
7533 04:48:04.325189 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7534 04:48:04.325624 ==
7535 04:48:04.329001 Dram Type= 6, Freq= 0, CH_0, rank 0
7536 04:48:04.335547 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7537 04:48:04.335984 ==
7538 04:48:04.338818 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7539 04:48:04.341876 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7540 04:48:04.348808 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7541 04:48:04.355192 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7542 04:48:04.362547 [CA 0] Center 43 (13~73) winsize 61
7543 04:48:04.365919 [CA 1] Center 43 (13~73) winsize 61
7544 04:48:04.369417 [CA 2] Center 38 (8~68) winsize 61
7545 04:48:04.372851 [CA 3] Center 37 (8~67) winsize 60
7546 04:48:04.376003 [CA 4] Center 36 (6~66) winsize 61
7547 04:48:04.379155 [CA 5] Center 35 (5~65) winsize 61
7548 04:48:04.379588
7549 04:48:04.382496 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7550 04:48:04.382958
7551 04:48:04.386041 [CATrainingPosCal] consider 1 rank data
7552 04:48:04.389072 u2DelayCellTimex100 = 285/100 ps
7553 04:48:04.392518 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7554 04:48:04.399158 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7555 04:48:04.402142 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7556 04:48:04.405483 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7557 04:48:04.408904 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7558 04:48:04.412430 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7559 04:48:04.412515
7560 04:48:04.415496 CA PerBit enable=1, Macro0, CA PI delay=35
7561 04:48:04.415587
7562 04:48:04.418981 [CBTSetCACLKResult] CA Dly = 35
7563 04:48:04.422251 CS Dly: 9 (0~40)
7564 04:48:04.425343 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7565 04:48:04.429038 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7566 04:48:04.429123 ==
7567 04:48:04.432197 Dram Type= 6, Freq= 0, CH_0, rank 1
7568 04:48:04.435568 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7569 04:48:04.435654 ==
7570 04:48:04.442271 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7571 04:48:04.446006 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7572 04:48:04.452001 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7573 04:48:04.455218 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7574 04:48:04.465633 [CA 0] Center 43 (13~74) winsize 62
7575 04:48:04.469179 [CA 1] Center 43 (13~73) winsize 61
7576 04:48:04.472251 [CA 2] Center 38 (9~68) winsize 60
7577 04:48:04.475614 [CA 3] Center 38 (9~68) winsize 60
7578 04:48:04.478791 [CA 4] Center 37 (7~67) winsize 61
7579 04:48:04.482333 [CA 5] Center 36 (6~66) winsize 61
7580 04:48:04.482419
7581 04:48:04.485638 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7582 04:48:04.485723
7583 04:48:04.488861 [CATrainingPosCal] consider 2 rank data
7584 04:48:04.492241 u2DelayCellTimex100 = 285/100 ps
7585 04:48:04.495560 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7586 04:48:04.502184 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7587 04:48:04.505494 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7588 04:48:04.508913 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7589 04:48:04.512340 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7590 04:48:04.515479 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7591 04:48:04.515564
7592 04:48:04.518743 CA PerBit enable=1, Macro0, CA PI delay=35
7593 04:48:04.518828
7594 04:48:04.522204 [CBTSetCACLKResult] CA Dly = 35
7595 04:48:04.525432 CS Dly: 10 (0~43)
7596 04:48:04.528803 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7597 04:48:04.531994 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7598 04:48:04.532079
7599 04:48:04.535609 ----->DramcWriteLeveling(PI) begin...
7600 04:48:04.535694 ==
7601 04:48:04.538935 Dram Type= 6, Freq= 0, CH_0, rank 0
7602 04:48:04.545344 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7603 04:48:04.545430 ==
7604 04:48:04.549137 Write leveling (Byte 0): 36 => 36
7605 04:48:04.549227 Write leveling (Byte 1): 29 => 29
7606 04:48:04.552168 DramcWriteLeveling(PI) end<-----
7607 04:48:04.552252
7608 04:48:04.552327 ==
7609 04:48:04.555434 Dram Type= 6, Freq= 0, CH_0, rank 0
7610 04:48:04.561993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7611 04:48:04.562079 ==
7612 04:48:04.565728 [Gating] SW mode calibration
7613 04:48:04.572197 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7614 04:48:04.575124 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7615 04:48:04.581999 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7616 04:48:04.585185 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 04:48:04.588687 1 4 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 1)
7618 04:48:04.595575 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7619 04:48:04.598563 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7620 04:48:04.602056 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7621 04:48:04.605242 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7622 04:48:04.611869 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7623 04:48:04.615211 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7624 04:48:04.618648 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7625 04:48:04.625109 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
7626 04:48:04.628717 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7627 04:48:04.631955 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7628 04:48:04.639072 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
7629 04:48:04.642043 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7630 04:48:04.645612 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7631 04:48:04.652455 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7632 04:48:04.655472 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7633 04:48:04.658656 1 6 8 | B1->B0 | 2323 403f | 0 1 | (0 0) (0 0)
7634 04:48:04.665359 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7635 04:48:04.668731 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7636 04:48:04.672115 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7637 04:48:04.678716 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7638 04:48:04.682088 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7639 04:48:04.685156 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7640 04:48:04.691625 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7641 04:48:04.695393 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7642 04:48:04.698583 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7643 04:48:04.705495 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7644 04:48:04.708695 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7645 04:48:04.711988 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 04:48:04.718163 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 04:48:04.721656 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 04:48:04.725153 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 04:48:04.731814 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 04:48:04.735370 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 04:48:04.738211 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 04:48:04.744900 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 04:48:04.748399 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 04:48:04.751896 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 04:48:04.758016 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 04:48:04.761427 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 04:48:04.764655 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7658 04:48:04.771443 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7659 04:48:04.774922 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7660 04:48:04.778233 Total UI for P1: 0, mck2ui 16
7661 04:48:04.781077 best dqsien dly found for B0: ( 1, 9, 10)
7662 04:48:04.784923 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7663 04:48:04.787998 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7664 04:48:04.791254 Total UI for P1: 0, mck2ui 16
7665 04:48:04.794239 best dqsien dly found for B1: ( 1, 9, 20)
7666 04:48:04.797641 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7667 04:48:04.804680 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7668 04:48:04.805118
7669 04:48:04.807659 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7670 04:48:04.811063 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7671 04:48:04.814397 [Gating] SW calibration Done
7672 04:48:04.814916 ==
7673 04:48:04.817851 Dram Type= 6, Freq= 0, CH_0, rank 0
7674 04:48:04.821308 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7675 04:48:04.821743 ==
7676 04:48:04.824175 RX Vref Scan: 0
7677 04:48:04.824609
7678 04:48:04.824950 RX Vref 0 -> 0, step: 1
7679 04:48:04.825268
7680 04:48:04.827694 RX Delay 0 -> 252, step: 8
7681 04:48:04.831053 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7682 04:48:04.837733 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7683 04:48:04.841059 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7684 04:48:04.844460 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7685 04:48:04.847642 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7686 04:48:04.850660 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7687 04:48:04.853994 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7688 04:48:04.860833 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7689 04:48:04.864210 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7690 04:48:04.867583 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7691 04:48:04.870671 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7692 04:48:04.874238 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7693 04:48:04.880768 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7694 04:48:04.883748 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7695 04:48:04.887528 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7696 04:48:04.890786 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7697 04:48:04.891283 ==
7698 04:48:04.894049 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 04:48:04.900381 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 04:48:04.900871 ==
7701 04:48:04.901246 DQS Delay:
7702 04:48:04.903868 DQS0 = 0, DQS1 = 0
7703 04:48:04.904451 DQM Delay:
7704 04:48:04.904838 DQM0 = 138, DQM1 = 126
7705 04:48:04.907077 DQ Delay:
7706 04:48:04.910492 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7707 04:48:04.913684 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7708 04:48:04.917128 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7709 04:48:04.920595 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7710 04:48:04.921023
7711 04:48:04.921391
7712 04:48:04.921785 ==
7713 04:48:04.923923 Dram Type= 6, Freq= 0, CH_0, rank 0
7714 04:48:04.930411 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7715 04:48:04.931031 ==
7716 04:48:04.931552
7717 04:48:04.932006
7718 04:48:04.932327 TX Vref Scan disable
7719 04:48:04.933856 == TX Byte 0 ==
7720 04:48:04.937157 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7721 04:48:04.940118 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7722 04:48:04.943571 == TX Byte 1 ==
7723 04:48:04.946871 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7724 04:48:04.953648 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7725 04:48:04.954261 ==
7726 04:48:04.956999 Dram Type= 6, Freq= 0, CH_0, rank 0
7727 04:48:04.959989 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7728 04:48:04.960526 ==
7729 04:48:04.974165
7730 04:48:04.977410 TX Vref early break, caculate TX vref
7731 04:48:04.981063 TX Vref=16, minBit 7, minWin=22, winSum=376
7732 04:48:04.984215 TX Vref=18, minBit 1, minWin=23, winSum=385
7733 04:48:04.987453 TX Vref=20, minBit 12, minWin=23, winSum=393
7734 04:48:04.991047 TX Vref=22, minBit 0, minWin=24, winSum=405
7735 04:48:04.994291 TX Vref=24, minBit 1, minWin=25, winSum=414
7736 04:48:05.000578 TX Vref=26, minBit 12, minWin=25, winSum=425
7737 04:48:05.003792 TX Vref=28, minBit 0, minWin=26, winSum=427
7738 04:48:05.007243 TX Vref=30, minBit 7, minWin=25, winSum=426
7739 04:48:05.010877 TX Vref=32, minBit 0, minWin=25, winSum=417
7740 04:48:05.013749 TX Vref=34, minBit 2, minWin=24, winSum=408
7741 04:48:05.017121 TX Vref=36, minBit 2, minWin=24, winSum=395
7742 04:48:05.023644 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28
7743 04:48:05.024227
7744 04:48:05.027457 Final TX Range 0 Vref 28
7745 04:48:05.028033
7746 04:48:05.028517 ==
7747 04:48:05.030261 Dram Type= 6, Freq= 0, CH_0, rank 0
7748 04:48:05.033622 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7749 04:48:05.034221 ==
7750 04:48:05.034727
7751 04:48:05.036998
7752 04:48:05.037563 TX Vref Scan disable
7753 04:48:05.044102 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7754 04:48:05.044572 == TX Byte 0 ==
7755 04:48:05.047012 u2DelayCellOfst[0]=17 cells (5 PI)
7756 04:48:05.050551 u2DelayCellOfst[1]=20 cells (6 PI)
7757 04:48:05.054022 u2DelayCellOfst[2]=13 cells (4 PI)
7758 04:48:05.057167 u2DelayCellOfst[3]=13 cells (4 PI)
7759 04:48:05.060756 u2DelayCellOfst[4]=10 cells (3 PI)
7760 04:48:05.064084 u2DelayCellOfst[5]=0 cells (0 PI)
7761 04:48:05.067064 u2DelayCellOfst[6]=20 cells (6 PI)
7762 04:48:05.070454 u2DelayCellOfst[7]=17 cells (5 PI)
7763 04:48:05.074094 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7764 04:48:05.077184 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7765 04:48:05.080509 == TX Byte 1 ==
7766 04:48:05.084246 u2DelayCellOfst[8]=0 cells (0 PI)
7767 04:48:05.087058 u2DelayCellOfst[9]=0 cells (0 PI)
7768 04:48:05.087628 u2DelayCellOfst[10]=6 cells (2 PI)
7769 04:48:05.090515 u2DelayCellOfst[11]=3 cells (1 PI)
7770 04:48:05.093884 u2DelayCellOfst[12]=13 cells (4 PI)
7771 04:48:05.097440 u2DelayCellOfst[13]=13 cells (4 PI)
7772 04:48:05.100750 u2DelayCellOfst[14]=17 cells (5 PI)
7773 04:48:05.103948 u2DelayCellOfst[15]=10 cells (3 PI)
7774 04:48:05.110255 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7775 04:48:05.113988 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7776 04:48:05.114512 DramC Write-DBI on
7777 04:48:05.114979 ==
7778 04:48:05.117090 Dram Type= 6, Freq= 0, CH_0, rank 0
7779 04:48:05.123538 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7780 04:48:05.124122 ==
7781 04:48:05.124617
7782 04:48:05.125077
7783 04:48:05.125534 TX Vref Scan disable
7784 04:48:05.128018 == TX Byte 0 ==
7785 04:48:05.131127 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7786 04:48:05.134542 == TX Byte 1 ==
7787 04:48:05.137823 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7788 04:48:05.140924 DramC Write-DBI off
7789 04:48:05.141471
7790 04:48:05.142032 [DATLAT]
7791 04:48:05.142522 Freq=1600, CH0 RK0
7792 04:48:05.142975
7793 04:48:05.144731 DATLAT Default: 0xf
7794 04:48:05.145304 0, 0xFFFF, sum = 0
7795 04:48:05.148163 1, 0xFFFF, sum = 0
7796 04:48:05.148761 2, 0xFFFF, sum = 0
7797 04:48:05.151210 3, 0xFFFF, sum = 0
7798 04:48:05.151776 4, 0xFFFF, sum = 0
7799 04:48:05.154601 5, 0xFFFF, sum = 0
7800 04:48:05.157731 6, 0xFFFF, sum = 0
7801 04:48:05.158394 7, 0xFFFF, sum = 0
7802 04:48:05.161430 8, 0xFFFF, sum = 0
7803 04:48:05.162019 9, 0xFFFF, sum = 0
7804 04:48:05.164336 10, 0xFFFF, sum = 0
7805 04:48:05.164873 11, 0xFFFF, sum = 0
7806 04:48:05.167767 12, 0xFFFF, sum = 0
7807 04:48:05.168354 13, 0xFFFF, sum = 0
7808 04:48:05.171145 14, 0x0, sum = 1
7809 04:48:05.171682 15, 0x0, sum = 2
7810 04:48:05.174425 16, 0x0, sum = 3
7811 04:48:05.175047 17, 0x0, sum = 4
7812 04:48:05.177697 best_step = 15
7813 04:48:05.178404
7814 04:48:05.179043 ==
7815 04:48:05.180657 Dram Type= 6, Freq= 0, CH_0, rank 0
7816 04:48:05.184045 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7817 04:48:05.184618 ==
7818 04:48:05.185116 RX Vref Scan: 1
7819 04:48:05.187329
7820 04:48:05.187982 Set Vref Range= 24 -> 127
7821 04:48:05.188519
7822 04:48:05.191198 RX Vref 24 -> 127, step: 1
7823 04:48:05.191907
7824 04:48:05.194232 RX Delay 19 -> 252, step: 4
7825 04:48:05.194670
7826 04:48:05.197199 Set Vref, RX VrefLevel [Byte0]: 24
7827 04:48:05.200677 [Byte1]: 24
7828 04:48:05.201108
7829 04:48:05.204293 Set Vref, RX VrefLevel [Byte0]: 25
7830 04:48:05.207549 [Byte1]: 25
7831 04:48:05.207983
7832 04:48:05.210855 Set Vref, RX VrefLevel [Byte0]: 26
7833 04:48:05.214027 [Byte1]: 26
7834 04:48:05.218190
7835 04:48:05.218707 Set Vref, RX VrefLevel [Byte0]: 27
7836 04:48:05.221378 [Byte1]: 27
7837 04:48:05.225707
7838 04:48:05.226211 Set Vref, RX VrefLevel [Byte0]: 28
7839 04:48:05.229245 [Byte1]: 28
7840 04:48:05.233328
7841 04:48:05.233911 Set Vref, RX VrefLevel [Byte0]: 29
7842 04:48:05.236498 [Byte1]: 29
7843 04:48:05.240789
7844 04:48:05.241362 Set Vref, RX VrefLevel [Byte0]: 30
7845 04:48:05.243991 [Byte1]: 30
7846 04:48:05.248440
7847 04:48:05.248979 Set Vref, RX VrefLevel [Byte0]: 31
7848 04:48:05.251440 [Byte1]: 31
7849 04:48:05.255917
7850 04:48:05.256465 Set Vref, RX VrefLevel [Byte0]: 32
7851 04:48:05.259144 [Byte1]: 32
7852 04:48:05.263531
7853 04:48:05.263968 Set Vref, RX VrefLevel [Byte0]: 33
7854 04:48:05.266744 [Byte1]: 33
7855 04:48:05.271105
7856 04:48:05.271534 Set Vref, RX VrefLevel [Byte0]: 34
7857 04:48:05.274633 [Byte1]: 34
7858 04:48:05.278952
7859 04:48:05.279376 Set Vref, RX VrefLevel [Byte0]: 35
7860 04:48:05.281791 [Byte1]: 35
7861 04:48:05.286053
7862 04:48:05.286476 Set Vref, RX VrefLevel [Byte0]: 36
7863 04:48:05.289636 [Byte1]: 36
7864 04:48:05.293720
7865 04:48:05.294190 Set Vref, RX VrefLevel [Byte0]: 37
7866 04:48:05.297176 [Byte1]: 37
7867 04:48:05.301534
7868 04:48:05.301993 Set Vref, RX VrefLevel [Byte0]: 38
7869 04:48:05.304942 [Byte1]: 38
7870 04:48:05.308776
7871 04:48:05.309197 Set Vref, RX VrefLevel [Byte0]: 39
7872 04:48:05.312109 [Byte1]: 39
7873 04:48:05.316554
7874 04:48:05.316979 Set Vref, RX VrefLevel [Byte0]: 40
7875 04:48:05.319884 [Byte1]: 40
7876 04:48:05.324081
7877 04:48:05.324542 Set Vref, RX VrefLevel [Byte0]: 41
7878 04:48:05.327237 [Byte1]: 41
7879 04:48:05.331819
7880 04:48:05.332240 Set Vref, RX VrefLevel [Byte0]: 42
7881 04:48:05.335118 [Byte1]: 42
7882 04:48:05.339198
7883 04:48:05.339620 Set Vref, RX VrefLevel [Byte0]: 43
7884 04:48:05.342532 [Byte1]: 43
7885 04:48:05.346795
7886 04:48:05.347216 Set Vref, RX VrefLevel [Byte0]: 44
7887 04:48:05.350162 [Byte1]: 44
7888 04:48:05.354502
7889 04:48:05.354942 Set Vref, RX VrefLevel [Byte0]: 45
7890 04:48:05.358022 [Byte1]: 45
7891 04:48:05.361894
7892 04:48:05.362371 Set Vref, RX VrefLevel [Byte0]: 46
7893 04:48:05.365132 [Byte1]: 46
7894 04:48:05.369424
7895 04:48:05.369862 Set Vref, RX VrefLevel [Byte0]: 47
7896 04:48:05.372833 [Byte1]: 47
7897 04:48:05.377230
7898 04:48:05.377670 Set Vref, RX VrefLevel [Byte0]: 48
7899 04:48:05.380255 [Byte1]: 48
7900 04:48:05.384610
7901 04:48:05.385047 Set Vref, RX VrefLevel [Byte0]: 49
7902 04:48:05.388017 [Byte1]: 49
7903 04:48:05.392284
7904 04:48:05.392925 Set Vref, RX VrefLevel [Byte0]: 50
7905 04:48:05.395553 [Byte1]: 50
7906 04:48:05.399705
7907 04:48:05.400141 Set Vref, RX VrefLevel [Byte0]: 51
7908 04:48:05.402907 [Byte1]: 51
7909 04:48:05.407255
7910 04:48:05.407696 Set Vref, RX VrefLevel [Byte0]: 52
7911 04:48:05.410679 [Byte1]: 52
7912 04:48:05.414963
7913 04:48:05.415405 Set Vref, RX VrefLevel [Byte0]: 53
7914 04:48:05.418378 [Byte1]: 53
7915 04:48:05.422522
7916 04:48:05.422960 Set Vref, RX VrefLevel [Byte0]: 54
7917 04:48:05.425751 [Byte1]: 54
7918 04:48:05.430192
7919 04:48:05.430631 Set Vref, RX VrefLevel [Byte0]: 55
7920 04:48:05.433406 [Byte1]: 55
7921 04:48:05.437521
7922 04:48:05.438000 Set Vref, RX VrefLevel [Byte0]: 56
7923 04:48:05.440900 [Byte1]: 56
7924 04:48:05.445148
7925 04:48:05.445585 Set Vref, RX VrefLevel [Byte0]: 57
7926 04:48:05.448698 [Byte1]: 57
7927 04:48:05.452687
7928 04:48:05.453126 Set Vref, RX VrefLevel [Byte0]: 58
7929 04:48:05.455969 [Byte1]: 58
7930 04:48:05.460127
7931 04:48:05.460566 Set Vref, RX VrefLevel [Byte0]: 59
7932 04:48:05.463441 [Byte1]: 59
7933 04:48:05.467872
7934 04:48:05.468310 Set Vref, RX VrefLevel [Byte0]: 60
7935 04:48:05.471058 [Byte1]: 60
7936 04:48:05.475305
7937 04:48:05.475747 Set Vref, RX VrefLevel [Byte0]: 61
7938 04:48:05.478807 [Byte1]: 61
7939 04:48:05.483219
7940 04:48:05.483659 Set Vref, RX VrefLevel [Byte0]: 62
7941 04:48:05.486229 [Byte1]: 62
7942 04:48:05.490888
7943 04:48:05.491326 Set Vref, RX VrefLevel [Byte0]: 63
7944 04:48:05.493928 [Byte1]: 63
7945 04:48:05.498245
7946 04:48:05.498686 Set Vref, RX VrefLevel [Byte0]: 64
7947 04:48:05.501533 [Byte1]: 64
7948 04:48:05.505751
7949 04:48:05.506231 Set Vref, RX VrefLevel [Byte0]: 65
7950 04:48:05.509256 [Byte1]: 65
7951 04:48:05.513305
7952 04:48:05.513742 Set Vref, RX VrefLevel [Byte0]: 66
7953 04:48:05.516744 [Byte1]: 66
7954 04:48:05.520912
7955 04:48:05.521350 Set Vref, RX VrefLevel [Byte0]: 67
7956 04:48:05.524226 [Byte1]: 67
7957 04:48:05.528325
7958 04:48:05.528822 Set Vref, RX VrefLevel [Byte0]: 68
7959 04:48:05.531916 [Byte1]: 68
7960 04:48:05.535954
7961 04:48:05.536441 Set Vref, RX VrefLevel [Byte0]: 69
7962 04:48:05.539354 [Byte1]: 69
7963 04:48:05.543859
7964 04:48:05.544299 Set Vref, RX VrefLevel [Byte0]: 70
7965 04:48:05.547078 [Byte1]: 70
7966 04:48:05.551179
7967 04:48:05.551616 Set Vref, RX VrefLevel [Byte0]: 71
7968 04:48:05.554625 [Byte1]: 71
7969 04:48:05.558965
7970 04:48:05.559406 Set Vref, RX VrefLevel [Byte0]: 72
7971 04:48:05.561873 [Byte1]: 72
7972 04:48:05.566395
7973 04:48:05.566893 Set Vref, RX VrefLevel [Byte0]: 73
7974 04:48:05.569764 [Byte1]: 73
7975 04:48:05.573718
7976 04:48:05.577147 Set Vref, RX VrefLevel [Byte0]: 74
7977 04:48:05.577592 [Byte1]: 74
7978 04:48:05.581521
7979 04:48:05.582003 Set Vref, RX VrefLevel [Byte0]: 75
7980 04:48:05.584908 [Byte1]: 75
7981 04:48:05.589389
7982 04:48:05.589829 Set Vref, RX VrefLevel [Byte0]: 76
7983 04:48:05.592219 [Byte1]: 76
7984 04:48:05.596487
7985 04:48:05.596914 Final RX Vref Byte 0 = 62 to rank0
7986 04:48:05.599824 Final RX Vref Byte 1 = 63 to rank0
7987 04:48:05.603214 Final RX Vref Byte 0 = 62 to rank1
7988 04:48:05.606766 Final RX Vref Byte 1 = 63 to rank1==
7989 04:48:05.610087 Dram Type= 6, Freq= 0, CH_0, rank 0
7990 04:48:05.616864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7991 04:48:05.617331 ==
7992 04:48:05.617673 DQS Delay:
7993 04:48:05.618026 DQS0 = 0, DQS1 = 0
7994 04:48:05.620391 DQM Delay:
7995 04:48:05.620924 DQM0 = 135, DQM1 = 124
7996 04:48:05.623473 DQ Delay:
7997 04:48:05.626157 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
7998 04:48:05.629816 DQ4 =138, DQ5 =124, DQ6 =144, DQ7 =142
7999 04:48:05.632695 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =118
8000 04:48:05.636490 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =132
8001 04:48:05.636595
8002 04:48:05.636689
8003 04:48:05.636778
8004 04:48:05.639458 [DramC_TX_OE_Calibration] TA2
8005 04:48:05.643051 Original DQ_B0 (3 6) =30, OEN = 27
8006 04:48:05.646447 Original DQ_B1 (3 6) =30, OEN = 27
8007 04:48:05.649773 24, 0x0, End_B0=24 End_B1=24
8008 04:48:05.650432 25, 0x0, End_B0=25 End_B1=25
8009 04:48:05.652989 26, 0x0, End_B0=26 End_B1=26
8010 04:48:05.656681 27, 0x0, End_B0=27 End_B1=27
8011 04:48:05.660116 28, 0x0, End_B0=28 End_B1=28
8012 04:48:05.660692 29, 0x0, End_B0=29 End_B1=29
8013 04:48:05.663035 30, 0x0, End_B0=30 End_B1=30
8014 04:48:05.666487 31, 0x4141, End_B0=30 End_B1=30
8015 04:48:05.670005 Byte0 end_step=30 best_step=27
8016 04:48:05.673346 Byte1 end_step=30 best_step=27
8017 04:48:05.676294 Byte0 TX OE(2T, 0.5T) = (3, 3)
8018 04:48:05.676722 Byte1 TX OE(2T, 0.5T) = (3, 3)
8019 04:48:05.679705
8020 04:48:05.680128
8021 04:48:05.686424 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
8022 04:48:05.689799 CH0 RK0: MR19=303, MR18=1C1A
8023 04:48:05.696591 CH0_RK0: MR19=0x303, MR18=0x1C1A, DQSOSC=395, MR23=63, INC=23, DEC=15
8024 04:48:05.697089
8025 04:48:05.699975 ----->DramcWriteLeveling(PI) begin...
8026 04:48:05.700472 ==
8027 04:48:05.703108 Dram Type= 6, Freq= 0, CH_0, rank 1
8028 04:48:05.706141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8029 04:48:05.706592 ==
8030 04:48:05.709837 Write leveling (Byte 0): 38 => 38
8031 04:48:05.712907 Write leveling (Byte 1): 29 => 29
8032 04:48:05.716164 DramcWriteLeveling(PI) end<-----
8033 04:48:05.716599
8034 04:48:05.716945 ==
8035 04:48:05.719668 Dram Type= 6, Freq= 0, CH_0, rank 1
8036 04:48:05.723033 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8037 04:48:05.723484 ==
8038 04:48:05.726486 [Gating] SW mode calibration
8039 04:48:05.732890 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8040 04:48:05.739756 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8041 04:48:05.743002 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8042 04:48:05.746165 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8043 04:48:05.752911 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8044 04:48:05.756207 1 4 12 | B1->B0 | 2626 3131 | 0 1 | (0 0) (1 1)
8045 04:48:05.759514 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8046 04:48:05.766206 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8047 04:48:05.769773 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8048 04:48:05.772806 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8049 04:48:05.779596 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8050 04:48:05.782614 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8051 04:48:05.786019 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8052 04:48:05.792772 1 5 12 | B1->B0 | 3333 2828 | 0 1 | (0 0) (1 0)
8053 04:48:05.795830 1 5 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8054 04:48:05.799204 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 04:48:05.805915 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 04:48:05.809433 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8057 04:48:05.812628 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8058 04:48:05.819433 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8059 04:48:05.822495 1 6 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8060 04:48:05.825592 1 6 12 | B1->B0 | 2b2b 4545 | 0 1 | (1 1) (0 0)
8061 04:48:05.832637 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 04:48:05.836099 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8063 04:48:05.839178 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 04:48:05.846077 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8065 04:48:05.849111 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8066 04:48:05.852359 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8067 04:48:05.855831 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8068 04:48:05.862219 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8069 04:48:05.865683 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8070 04:48:05.869005 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8071 04:48:05.875481 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 04:48:05.878773 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 04:48:05.882336 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 04:48:05.888894 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 04:48:05.892119 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 04:48:05.895430 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 04:48:05.901914 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 04:48:05.905575 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 04:48:05.908485 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 04:48:05.915175 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 04:48:05.918680 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 04:48:05.922284 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 04:48:05.928543 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8084 04:48:05.931917 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8085 04:48:05.935114 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8086 04:48:05.938726 Total UI for P1: 0, mck2ui 16
8087 04:48:05.942150 best dqsien dly found for B0: ( 1, 9, 10)
8088 04:48:05.948967 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 04:48:05.949425 Total UI for P1: 0, mck2ui 16
8090 04:48:05.955337 best dqsien dly found for B1: ( 1, 9, 16)
8091 04:48:05.958473 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8092 04:48:05.962127 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8093 04:48:05.962562
8094 04:48:05.965420 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8095 04:48:05.968675 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8096 04:48:05.972014 [Gating] SW calibration Done
8097 04:48:05.972451 ==
8098 04:48:05.975607 Dram Type= 6, Freq= 0, CH_0, rank 1
8099 04:48:05.978486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8100 04:48:05.978922 ==
8101 04:48:05.981863 RX Vref Scan: 0
8102 04:48:05.982332
8103 04:48:05.982680 RX Vref 0 -> 0, step: 1
8104 04:48:05.983008
8105 04:48:05.985333 RX Delay 0 -> 252, step: 8
8106 04:48:05.988371 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8107 04:48:05.994972 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8108 04:48:05.998248 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8109 04:48:06.002122 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8110 04:48:06.005392 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8111 04:48:06.008493 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8112 04:48:06.014852 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8113 04:48:06.018331 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8114 04:48:06.021587 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8115 04:48:06.024957 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8116 04:48:06.028433 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8117 04:48:06.034930 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8118 04:48:06.038377 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8119 04:48:06.041575 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8120 04:48:06.045052 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8121 04:48:06.048364 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8122 04:48:06.051740 ==
8123 04:48:06.054866 Dram Type= 6, Freq= 0, CH_0, rank 1
8124 04:48:06.058081 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8125 04:48:06.058530 ==
8126 04:48:06.058981 DQS Delay:
8127 04:48:06.061791 DQS0 = 0, DQS1 = 0
8128 04:48:06.062315 DQM Delay:
8129 04:48:06.065110 DQM0 = 136, DQM1 = 125
8130 04:48:06.065542 DQ Delay:
8131 04:48:06.068587 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8132 04:48:06.071677 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8133 04:48:06.075070 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =123
8134 04:48:06.078056 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8135 04:48:06.078492
8136 04:48:06.078832
8137 04:48:06.079149 ==
8138 04:48:06.082037 Dram Type= 6, Freq= 0, CH_0, rank 1
8139 04:48:06.088318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8140 04:48:06.088756 ==
8141 04:48:06.089101
8142 04:48:06.089423
8143 04:48:06.089729 TX Vref Scan disable
8144 04:48:06.091765 == TX Byte 0 ==
8145 04:48:06.095302 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8146 04:48:06.101655 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8147 04:48:06.102143 == TX Byte 1 ==
8148 04:48:06.105026 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8149 04:48:06.111394 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8150 04:48:06.111947 ==
8151 04:48:06.114716 Dram Type= 6, Freq= 0, CH_0, rank 1
8152 04:48:06.118102 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8153 04:48:06.118626 ==
8154 04:48:06.131608
8155 04:48:06.134907 TX Vref early break, caculate TX vref
8156 04:48:06.138292 TX Vref=16, minBit 0, minWin=23, winSum=387
8157 04:48:06.141750 TX Vref=18, minBit 1, minWin=24, winSum=396
8158 04:48:06.145006 TX Vref=20, minBit 3, minWin=24, winSum=405
8159 04:48:06.148324 TX Vref=22, minBit 8, minWin=24, winSum=412
8160 04:48:06.151912 TX Vref=24, minBit 0, minWin=25, winSum=423
8161 04:48:06.158334 TX Vref=26, minBit 0, minWin=26, winSum=432
8162 04:48:06.161641 TX Vref=28, minBit 0, minWin=26, winSum=431
8163 04:48:06.165200 TX Vref=30, minBit 2, minWin=26, winSum=427
8164 04:48:06.168209 TX Vref=32, minBit 0, minWin=25, winSum=419
8165 04:48:06.171633 TX Vref=34, minBit 4, minWin=24, winSum=408
8166 04:48:06.178177 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 26
8167 04:48:06.178732
8168 04:48:06.181654 Final TX Range 0 Vref 26
8169 04:48:06.182308
8170 04:48:06.182733 ==
8171 04:48:06.185001 Dram Type= 6, Freq= 0, CH_0, rank 1
8172 04:48:06.188045 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8173 04:48:06.188617 ==
8174 04:48:06.189000
8175 04:48:06.189413
8176 04:48:06.191499 TX Vref Scan disable
8177 04:48:06.198453 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8178 04:48:06.198939 == TX Byte 0 ==
8179 04:48:06.201275 u2DelayCellOfst[0]=13 cells (4 PI)
8180 04:48:06.204697 u2DelayCellOfst[1]=20 cells (6 PI)
8181 04:48:06.207762 u2DelayCellOfst[2]=13 cells (4 PI)
8182 04:48:06.211224 u2DelayCellOfst[3]=13 cells (4 PI)
8183 04:48:06.214536 u2DelayCellOfst[4]=10 cells (3 PI)
8184 04:48:06.218111 u2DelayCellOfst[5]=0 cells (0 PI)
8185 04:48:06.221303 u2DelayCellOfst[6]=17 cells (5 PI)
8186 04:48:06.224453 u2DelayCellOfst[7]=20 cells (6 PI)
8187 04:48:06.228106 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8188 04:48:06.231393 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8189 04:48:06.234411 == TX Byte 1 ==
8190 04:48:06.237605 u2DelayCellOfst[8]=0 cells (0 PI)
8191 04:48:06.238093 u2DelayCellOfst[9]=0 cells (0 PI)
8192 04:48:06.241122 u2DelayCellOfst[10]=6 cells (2 PI)
8193 04:48:06.244309 u2DelayCellOfst[11]=3 cells (1 PI)
8194 04:48:06.248001 u2DelayCellOfst[12]=13 cells (4 PI)
8195 04:48:06.251248 u2DelayCellOfst[13]=10 cells (3 PI)
8196 04:48:06.254521 u2DelayCellOfst[14]=17 cells (5 PI)
8197 04:48:06.257827 u2DelayCellOfst[15]=10 cells (3 PI)
8198 04:48:06.261019 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8199 04:48:06.267718 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8200 04:48:06.268155 DramC Write-DBI on
8201 04:48:06.268549 ==
8202 04:48:06.271240 Dram Type= 6, Freq= 0, CH_0, rank 1
8203 04:48:06.274163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8204 04:48:06.277394 ==
8205 04:48:06.277817
8206 04:48:06.278203
8207 04:48:06.278559 TX Vref Scan disable
8208 04:48:06.281145 == TX Byte 0 ==
8209 04:48:06.285004 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8210 04:48:06.287791 == TX Byte 1 ==
8211 04:48:06.291240 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8212 04:48:06.294658 DramC Write-DBI off
8213 04:48:06.295082
8214 04:48:06.295416 [DATLAT]
8215 04:48:06.295732 Freq=1600, CH0 RK1
8216 04:48:06.296042
8217 04:48:06.298127 DATLAT Default: 0xf
8218 04:48:06.298592 0, 0xFFFF, sum = 0
8219 04:48:06.301406 1, 0xFFFF, sum = 0
8220 04:48:06.304489 2, 0xFFFF, sum = 0
8221 04:48:06.305007 3, 0xFFFF, sum = 0
8222 04:48:06.307701 4, 0xFFFF, sum = 0
8223 04:48:06.308247 5, 0xFFFF, sum = 0
8224 04:48:06.311671 6, 0xFFFF, sum = 0
8225 04:48:06.312104 7, 0xFFFF, sum = 0
8226 04:48:06.314796 8, 0xFFFF, sum = 0
8227 04:48:06.315444 9, 0xFFFF, sum = 0
8228 04:48:06.318181 10, 0xFFFF, sum = 0
8229 04:48:06.318722 11, 0xFFFF, sum = 0
8230 04:48:06.321419 12, 0xFFFF, sum = 0
8231 04:48:06.321874 13, 0xFFFF, sum = 0
8232 04:48:06.324500 14, 0x0, sum = 1
8233 04:48:06.324878 15, 0x0, sum = 2
8234 04:48:06.327907 16, 0x0, sum = 3
8235 04:48:06.328587 17, 0x0, sum = 4
8236 04:48:06.331214 best_step = 15
8237 04:48:06.331732
8238 04:48:06.332099 ==
8239 04:48:06.334637 Dram Type= 6, Freq= 0, CH_0, rank 1
8240 04:48:06.337668 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8241 04:48:06.338160 ==
8242 04:48:06.338535 RX Vref Scan: 0
8243 04:48:06.341189
8244 04:48:06.341698 RX Vref 0 -> 0, step: 1
8245 04:48:06.342085
8246 04:48:06.344419 RX Delay 11 -> 252, step: 4
8247 04:48:06.347927 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8248 04:48:06.354692 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8249 04:48:06.357770 iDelay=191, Bit 2, Center 130 (83 ~ 178) 96
8250 04:48:06.361444 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8251 04:48:06.364258 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8252 04:48:06.368126 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8253 04:48:06.371136 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8254 04:48:06.377584 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8255 04:48:06.380982 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8256 04:48:06.384418 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8257 04:48:06.387639 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8258 04:48:06.394439 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8259 04:48:06.397981 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8260 04:48:06.401478 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8261 04:48:06.404390 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8262 04:48:06.407878 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8263 04:48:06.408304 ==
8264 04:48:06.411238 Dram Type= 6, Freq= 0, CH_0, rank 1
8265 04:48:06.417664 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8266 04:48:06.418197 ==
8267 04:48:06.418537 DQS Delay:
8268 04:48:06.421045 DQS0 = 0, DQS1 = 0
8269 04:48:06.421470 DQM Delay:
8270 04:48:06.424188 DQM0 = 133, DQM1 = 123
8271 04:48:06.424611 DQ Delay:
8272 04:48:06.427474 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130
8273 04:48:06.430749 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8274 04:48:06.434219 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8275 04:48:06.437395 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8276 04:48:06.437821
8277 04:48:06.438224
8278 04:48:06.438549
8279 04:48:06.440980 [DramC_TX_OE_Calibration] TA2
8280 04:48:06.444128 Original DQ_B0 (3 6) =30, OEN = 27
8281 04:48:06.447852 Original DQ_B1 (3 6) =30, OEN = 27
8282 04:48:06.450955 24, 0x0, End_B0=24 End_B1=24
8283 04:48:06.454447 25, 0x0, End_B0=25 End_B1=25
8284 04:48:06.454877 26, 0x0, End_B0=26 End_B1=26
8285 04:48:06.457416 27, 0x0, End_B0=27 End_B1=27
8286 04:48:06.460692 28, 0x0, End_B0=28 End_B1=28
8287 04:48:06.464151 29, 0x0, End_B0=29 End_B1=29
8288 04:48:06.464583 30, 0x0, End_B0=30 End_B1=30
8289 04:48:06.467614 31, 0x4141, End_B0=30 End_B1=30
8290 04:48:06.470710 Byte0 end_step=30 best_step=27
8291 04:48:06.474197 Byte1 end_step=30 best_step=27
8292 04:48:06.477625 Byte0 TX OE(2T, 0.5T) = (3, 3)
8293 04:48:06.480839 Byte1 TX OE(2T, 0.5T) = (3, 3)
8294 04:48:06.481263
8295 04:48:06.481598
8296 04:48:06.487602 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f0c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 394 ps
8297 04:48:06.490834 CH0 RK1: MR19=303, MR18=1F0C
8298 04:48:06.497683 CH0_RK1: MR19=0x303, MR18=0x1F0C, DQSOSC=394, MR23=63, INC=23, DEC=15
8299 04:48:06.500355 [RxdqsGatingPostProcess] freq 1600
8300 04:48:06.504034 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8301 04:48:06.507226 best DQS0 dly(2T, 0.5T) = (1, 1)
8302 04:48:06.510603 best DQS1 dly(2T, 0.5T) = (1, 1)
8303 04:48:06.513909 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8304 04:48:06.517163 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8305 04:48:06.520816 best DQS0 dly(2T, 0.5T) = (1, 1)
8306 04:48:06.524247 best DQS1 dly(2T, 0.5T) = (1, 1)
8307 04:48:06.527201 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8308 04:48:06.530682 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8309 04:48:06.533823 Pre-setting of DQS Precalculation
8310 04:48:06.537350 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8311 04:48:06.537877 ==
8312 04:48:06.540254 Dram Type= 6, Freq= 0, CH_1, rank 0
8313 04:48:06.544021 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8314 04:48:06.546979 ==
8315 04:48:06.550551 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8316 04:48:06.553748 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8317 04:48:06.560660 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8318 04:48:06.567101 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8319 04:48:06.574351 [CA 0] Center 42 (12~72) winsize 61
8320 04:48:06.577584 [CA 1] Center 42 (12~72) winsize 61
8321 04:48:06.580760 [CA 2] Center 38 (9~68) winsize 60
8322 04:48:06.584006 [CA 3] Center 37 (8~67) winsize 60
8323 04:48:06.587225 [CA 4] Center 37 (8~67) winsize 60
8324 04:48:06.590619 [CA 5] Center 37 (7~67) winsize 61
8325 04:48:06.591225
8326 04:48:06.594066 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8327 04:48:06.594636
8328 04:48:06.597177 [CATrainingPosCal] consider 1 rank data
8329 04:48:06.600664 u2DelayCellTimex100 = 285/100 ps
8330 04:48:06.604120 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8331 04:48:06.611011 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8332 04:48:06.614016 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8333 04:48:06.617387 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8334 04:48:06.620775 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8335 04:48:06.623995 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8336 04:48:06.624570
8337 04:48:06.627513 CA PerBit enable=1, Macro0, CA PI delay=37
8338 04:48:06.628096
8339 04:48:06.631015 [CBTSetCACLKResult] CA Dly = 37
8340 04:48:06.631598 CS Dly: 8 (0~39)
8341 04:48:06.637803 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8342 04:48:06.641182 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8343 04:48:06.641632 ==
8344 04:48:06.644150 Dram Type= 6, Freq= 0, CH_1, rank 1
8345 04:48:06.647603 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8346 04:48:06.648202 ==
8347 04:48:06.654073 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8348 04:48:06.657652 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8349 04:48:06.664086 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8350 04:48:06.667486 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8351 04:48:06.677254 [CA 0] Center 41 (12~71) winsize 60
8352 04:48:06.680403 [CA 1] Center 41 (12~71) winsize 60
8353 04:48:06.683902 [CA 2] Center 38 (9~68) winsize 60
8354 04:48:06.687191 [CA 3] Center 37 (8~67) winsize 60
8355 04:48:06.690479 [CA 4] Center 37 (8~67) winsize 60
8356 04:48:06.694174 [CA 5] Center 37 (7~67) winsize 61
8357 04:48:06.694775
8358 04:48:06.697063 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8359 04:48:06.697672
8360 04:48:06.700305 [CATrainingPosCal] consider 2 rank data
8361 04:48:06.703682 u2DelayCellTimex100 = 285/100 ps
8362 04:48:06.707141 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8363 04:48:06.713888 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8364 04:48:06.717289 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8365 04:48:06.720228 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8366 04:48:06.724160 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8367 04:48:06.727387 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8368 04:48:06.727934
8369 04:48:06.730648 CA PerBit enable=1, Macro0, CA PI delay=37
8370 04:48:06.731155
8371 04:48:06.733629 [CBTSetCACLKResult] CA Dly = 37
8372 04:48:06.736889 CS Dly: 9 (0~41)
8373 04:48:06.740198 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8374 04:48:06.743686 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8375 04:48:06.744237
8376 04:48:06.747053 ----->DramcWriteLeveling(PI) begin...
8377 04:48:06.747650 ==
8378 04:48:06.750528 Dram Type= 6, Freq= 0, CH_1, rank 0
8379 04:48:06.753664 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8380 04:48:06.756778 ==
8381 04:48:06.757275 Write leveling (Byte 0): 25 => 25
8382 04:48:06.760494 Write leveling (Byte 1): 27 => 27
8383 04:48:06.763679 DramcWriteLeveling(PI) end<-----
8384 04:48:06.764271
8385 04:48:06.764759 ==
8386 04:48:06.766995 Dram Type= 6, Freq= 0, CH_1, rank 0
8387 04:48:06.773526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8388 04:48:06.774109 ==
8389 04:48:06.774561 [Gating] SW mode calibration
8390 04:48:06.783669 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8391 04:48:06.786890 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8392 04:48:06.793742 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 04:48:06.797075 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 04:48:06.800059 1 4 8 | B1->B0 | 2b2b 3333 | 1 1 | (0 0) (1 1)
8395 04:48:06.803479 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8396 04:48:06.810088 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8397 04:48:06.813567 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8398 04:48:06.817188 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8399 04:48:06.823526 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8400 04:48:06.826686 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8401 04:48:06.830260 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8402 04:48:06.836953 1 5 8 | B1->B0 | 3030 2d2d | 0 0 | (0 0) (1 0)
8403 04:48:06.839979 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8404 04:48:06.843489 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 04:48:06.850300 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 04:48:06.853225 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 04:48:06.856492 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 04:48:06.863298 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8409 04:48:06.866492 1 6 4 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
8410 04:48:06.870117 1 6 8 | B1->B0 | 3838 4040 | 0 0 | (0 0) (0 0)
8411 04:48:06.876556 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8412 04:48:06.879806 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 04:48:06.883041 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 04:48:06.889821 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8415 04:48:06.892939 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 04:48:06.896534 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8417 04:48:06.903363 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8418 04:48:06.906337 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8419 04:48:06.909558 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8420 04:48:06.916422 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 04:48:06.919838 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 04:48:06.923031 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 04:48:06.929669 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 04:48:06.933091 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 04:48:06.936372 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 04:48:06.939777 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 04:48:06.946431 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 04:48:06.949481 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 04:48:06.953344 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 04:48:06.959589 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 04:48:06.962982 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 04:48:06.966301 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 04:48:06.973046 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 04:48:06.976183 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8435 04:48:06.979586 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8436 04:48:06.982840 Total UI for P1: 0, mck2ui 16
8437 04:48:06.986390 best dqsien dly found for B0: ( 1, 9, 8)
8438 04:48:06.992757 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 04:48:06.993337 Total UI for P1: 0, mck2ui 16
8440 04:48:06.999821 best dqsien dly found for B1: ( 1, 9, 10)
8441 04:48:07.002958 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8442 04:48:07.006210 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8443 04:48:07.006726
8444 04:48:07.009787 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8445 04:48:07.012975 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8446 04:48:07.016185 [Gating] SW calibration Done
8447 04:48:07.016896 ==
8448 04:48:07.019653 Dram Type= 6, Freq= 0, CH_1, rank 0
8449 04:48:07.022953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8450 04:48:07.023615 ==
8451 04:48:07.026325 RX Vref Scan: 0
8452 04:48:07.026825
8453 04:48:07.027198 RX Vref 0 -> 0, step: 1
8454 04:48:07.027520
8455 04:48:07.029734 RX Delay 0 -> 252, step: 8
8456 04:48:07.032698 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8457 04:48:07.039568 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8458 04:48:07.042784 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8459 04:48:07.046123 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8460 04:48:07.049474 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8461 04:48:07.052480 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8462 04:48:07.059355 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8463 04:48:07.062838 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8464 04:48:07.065805 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8465 04:48:07.069520 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8466 04:48:07.072465 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8467 04:48:07.079167 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8468 04:48:07.082490 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8469 04:48:07.085586 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8470 04:48:07.089207 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8471 04:48:07.092578 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8472 04:48:07.095426 ==
8473 04:48:07.095984 Dram Type= 6, Freq= 0, CH_1, rank 0
8474 04:48:07.102199 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8475 04:48:07.102639 ==
8476 04:48:07.102985 DQS Delay:
8477 04:48:07.105856 DQS0 = 0, DQS1 = 0
8478 04:48:07.106341 DQM Delay:
8479 04:48:07.109186 DQM0 = 136, DQM1 = 130
8480 04:48:07.109617 DQ Delay:
8481 04:48:07.112566 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8482 04:48:07.115569 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8483 04:48:07.119426 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8484 04:48:07.122285 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =139
8485 04:48:07.122716
8486 04:48:07.123078
8487 04:48:07.123401 ==
8488 04:48:07.125743 Dram Type= 6, Freq= 0, CH_1, rank 0
8489 04:48:07.132127 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8490 04:48:07.132565 ==
8491 04:48:07.132915
8492 04:48:07.133237
8493 04:48:07.133548 TX Vref Scan disable
8494 04:48:07.135672 == TX Byte 0 ==
8495 04:48:07.138954 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8496 04:48:07.142521 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8497 04:48:07.145930 == TX Byte 1 ==
8498 04:48:07.149108 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8499 04:48:07.152577 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8500 04:48:07.155693 ==
8501 04:48:07.158996 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 04:48:07.162429 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 04:48:07.162862 ==
8504 04:48:07.175258
8505 04:48:07.178941 TX Vref early break, caculate TX vref
8506 04:48:07.182077 TX Vref=16, minBit 9, minWin=22, winSum=371
8507 04:48:07.185375 TX Vref=18, minBit 10, minWin=21, winSum=379
8508 04:48:07.188711 TX Vref=20, minBit 10, minWin=23, winSum=395
8509 04:48:07.191889 TX Vref=22, minBit 15, minWin=23, winSum=399
8510 04:48:07.195583 TX Vref=24, minBit 10, minWin=24, winSum=409
8511 04:48:07.202247 TX Vref=26, minBit 10, minWin=24, winSum=421
8512 04:48:07.205227 TX Vref=28, minBit 10, minWin=25, winSum=422
8513 04:48:07.208984 TX Vref=30, minBit 13, minWin=25, winSum=419
8514 04:48:07.212076 TX Vref=32, minBit 9, minWin=24, winSum=407
8515 04:48:07.215134 TX Vref=34, minBit 8, minWin=24, winSum=401
8516 04:48:07.221918 TX Vref=36, minBit 10, minWin=23, winSum=391
8517 04:48:07.225149 [TxChooseVref] Worse bit 10, Min win 25, Win sum 422, Final Vref 28
8518 04:48:07.225582
8519 04:48:07.228557 Final TX Range 0 Vref 28
8520 04:48:07.229109
8521 04:48:07.229491 ==
8522 04:48:07.232092 Dram Type= 6, Freq= 0, CH_1, rank 0
8523 04:48:07.235229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8524 04:48:07.238284 ==
8525 04:48:07.238785
8526 04:48:07.239123
8527 04:48:07.239462 TX Vref Scan disable
8528 04:48:07.245503 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8529 04:48:07.245977 == TX Byte 0 ==
8530 04:48:07.248787 u2DelayCellOfst[0]=13 cells (4 PI)
8531 04:48:07.252107 u2DelayCellOfst[1]=10 cells (3 PI)
8532 04:48:07.255346 u2DelayCellOfst[2]=0 cells (0 PI)
8533 04:48:07.258413 u2DelayCellOfst[3]=3 cells (1 PI)
8534 04:48:07.261810 u2DelayCellOfst[4]=6 cells (2 PI)
8535 04:48:07.265319 u2DelayCellOfst[5]=17 cells (5 PI)
8536 04:48:07.268737 u2DelayCellOfst[6]=17 cells (5 PI)
8537 04:48:07.272071 u2DelayCellOfst[7]=6 cells (2 PI)
8538 04:48:07.275326 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8539 04:48:07.278534 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8540 04:48:07.281901 == TX Byte 1 ==
8541 04:48:07.285004 u2DelayCellOfst[8]=0 cells (0 PI)
8542 04:48:07.288630 u2DelayCellOfst[9]=3 cells (1 PI)
8543 04:48:07.291917 u2DelayCellOfst[10]=10 cells (3 PI)
8544 04:48:07.292351 u2DelayCellOfst[11]=3 cells (1 PI)
8545 04:48:07.295133 u2DelayCellOfst[12]=13 cells (4 PI)
8546 04:48:07.298647 u2DelayCellOfst[13]=17 cells (5 PI)
8547 04:48:07.301978 u2DelayCellOfst[14]=17 cells (5 PI)
8548 04:48:07.305341 u2DelayCellOfst[15]=17 cells (5 PI)
8549 04:48:07.311777 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8550 04:48:07.315006 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8551 04:48:07.315435 DramC Write-DBI on
8552 04:48:07.315776 ==
8553 04:48:07.318434 Dram Type= 6, Freq= 0, CH_1, rank 0
8554 04:48:07.325257 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8555 04:48:07.325690 ==
8556 04:48:07.326069
8557 04:48:07.326475
8558 04:48:07.326790 TX Vref Scan disable
8559 04:48:07.329281 == TX Byte 0 ==
8560 04:48:07.332208 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8561 04:48:07.335441 == TX Byte 1 ==
8562 04:48:07.338934 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8563 04:48:07.342421 DramC Write-DBI off
8564 04:48:07.342518
8565 04:48:07.342595 [DATLAT]
8566 04:48:07.342667 Freq=1600, CH1 RK0
8567 04:48:07.342737
8568 04:48:07.345375 DATLAT Default: 0xf
8569 04:48:07.345472 0, 0xFFFF, sum = 0
8570 04:48:07.348681 1, 0xFFFF, sum = 0
8571 04:48:07.352089 2, 0xFFFF, sum = 0
8572 04:48:07.352192 3, 0xFFFF, sum = 0
8573 04:48:07.355793 4, 0xFFFF, sum = 0
8574 04:48:07.355880 5, 0xFFFF, sum = 0
8575 04:48:07.358932 6, 0xFFFF, sum = 0
8576 04:48:07.359029 7, 0xFFFF, sum = 0
8577 04:48:07.362227 8, 0xFFFF, sum = 0
8578 04:48:07.362314 9, 0xFFFF, sum = 0
8579 04:48:07.365200 10, 0xFFFF, sum = 0
8580 04:48:07.365286 11, 0xFFFF, sum = 0
8581 04:48:07.368624 12, 0xFFFF, sum = 0
8582 04:48:07.368724 13, 0xFFFF, sum = 0
8583 04:48:07.371990 14, 0x0, sum = 1
8584 04:48:07.372076 15, 0x0, sum = 2
8585 04:48:07.375424 16, 0x0, sum = 3
8586 04:48:07.375510 17, 0x0, sum = 4
8587 04:48:07.379052 best_step = 15
8588 04:48:07.379137
8589 04:48:07.379204 ==
8590 04:48:07.381898 Dram Type= 6, Freq= 0, CH_1, rank 0
8591 04:48:07.385738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8592 04:48:07.385823 ==
8593 04:48:07.385891 RX Vref Scan: 1
8594 04:48:07.389045
8595 04:48:07.389129 Set Vref Range= 24 -> 127
8596 04:48:07.389196
8597 04:48:07.392064 RX Vref 24 -> 127, step: 1
8598 04:48:07.392149
8599 04:48:07.395927 RX Delay 19 -> 252, step: 4
8600 04:48:07.396012
8601 04:48:07.398739 Set Vref, RX VrefLevel [Byte0]: 24
8602 04:48:07.402283 [Byte1]: 24
8603 04:48:07.402368
8604 04:48:07.405413 Set Vref, RX VrefLevel [Byte0]: 25
8605 04:48:07.408949 [Byte1]: 25
8606 04:48:07.409034
8607 04:48:07.412486 Set Vref, RX VrefLevel [Byte0]: 26
8608 04:48:07.415635 [Byte1]: 26
8609 04:48:07.419280
8610 04:48:07.419364 Set Vref, RX VrefLevel [Byte0]: 27
8611 04:48:07.422702 [Byte1]: 27
8612 04:48:07.426583
8613 04:48:07.426667 Set Vref, RX VrefLevel [Byte0]: 28
8614 04:48:07.430111 [Byte1]: 28
8615 04:48:07.434559
8616 04:48:07.434644 Set Vref, RX VrefLevel [Byte0]: 29
8617 04:48:07.437776 [Byte1]: 29
8618 04:48:07.442054
8619 04:48:07.442144 Set Vref, RX VrefLevel [Byte0]: 30
8620 04:48:07.445160 [Byte1]: 30
8621 04:48:07.449734
8622 04:48:07.450215 Set Vref, RX VrefLevel [Byte0]: 31
8623 04:48:07.453119 [Byte1]: 31
8624 04:48:07.457516
8625 04:48:07.457979 Set Vref, RX VrefLevel [Byte0]: 32
8626 04:48:07.460747 [Byte1]: 32
8627 04:48:07.465074
8628 04:48:07.465504 Set Vref, RX VrefLevel [Byte0]: 33
8629 04:48:07.468135 [Byte1]: 33
8630 04:48:07.472606
8631 04:48:07.473039 Set Vref, RX VrefLevel [Byte0]: 34
8632 04:48:07.475892 [Byte1]: 34
8633 04:48:07.480350
8634 04:48:07.480783 Set Vref, RX VrefLevel [Byte0]: 35
8635 04:48:07.483535 [Byte1]: 35
8636 04:48:07.487837
8637 04:48:07.488268 Set Vref, RX VrefLevel [Byte0]: 36
8638 04:48:07.490905 [Byte1]: 36
8639 04:48:07.495417
8640 04:48:07.495850 Set Vref, RX VrefLevel [Byte0]: 37
8641 04:48:07.498563 [Byte1]: 37
8642 04:48:07.503078
8643 04:48:07.503555 Set Vref, RX VrefLevel [Byte0]: 38
8644 04:48:07.505896 [Byte1]: 38
8645 04:48:07.510477
8646 04:48:07.510910 Set Vref, RX VrefLevel [Byte0]: 39
8647 04:48:07.513436 [Byte1]: 39
8648 04:48:07.517710
8649 04:48:07.517794 Set Vref, RX VrefLevel [Byte0]: 40
8650 04:48:07.520693 [Byte1]: 40
8651 04:48:07.525032
8652 04:48:07.525123 Set Vref, RX VrefLevel [Byte0]: 41
8653 04:48:07.528853 [Byte1]: 41
8654 04:48:07.532690
8655 04:48:07.532795 Set Vref, RX VrefLevel [Byte0]: 42
8656 04:48:07.535951 [Byte1]: 42
8657 04:48:07.540370
8658 04:48:07.540485 Set Vref, RX VrefLevel [Byte0]: 43
8659 04:48:07.543616 [Byte1]: 43
8660 04:48:07.548094
8661 04:48:07.548233 Set Vref, RX VrefLevel [Byte0]: 44
8662 04:48:07.551292 [Byte1]: 44
8663 04:48:07.555761
8664 04:48:07.555845 Set Vref, RX VrefLevel [Byte0]: 45
8665 04:48:07.558889 [Byte1]: 45
8666 04:48:07.563024
8667 04:48:07.563109 Set Vref, RX VrefLevel [Byte0]: 46
8668 04:48:07.566377 [Byte1]: 46
8669 04:48:07.570890
8670 04:48:07.570975 Set Vref, RX VrefLevel [Byte0]: 47
8671 04:48:07.574153 [Byte1]: 47
8672 04:48:07.578145
8673 04:48:07.578242 Set Vref, RX VrefLevel [Byte0]: 48
8674 04:48:07.581567 [Byte1]: 48
8675 04:48:07.585931
8676 04:48:07.586035 Set Vref, RX VrefLevel [Byte0]: 49
8677 04:48:07.589498 [Byte1]: 49
8678 04:48:07.593307
8679 04:48:07.593397 Set Vref, RX VrefLevel [Byte0]: 50
8680 04:48:07.596874 [Byte1]: 50
8681 04:48:07.600967
8682 04:48:07.601078 Set Vref, RX VrefLevel [Byte0]: 51
8683 04:48:07.604248 [Byte1]: 51
8684 04:48:07.608859
8685 04:48:07.608947 Set Vref, RX VrefLevel [Byte0]: 52
8686 04:48:07.612099 [Byte1]: 52
8687 04:48:07.615915
8688 04:48:07.616005 Set Vref, RX VrefLevel [Byte0]: 53
8689 04:48:07.619819 [Byte1]: 53
8690 04:48:07.623465
8691 04:48:07.623556 Set Vref, RX VrefLevel [Byte0]: 54
8692 04:48:07.626814 [Byte1]: 54
8693 04:48:07.631137
8694 04:48:07.631241 Set Vref, RX VrefLevel [Byte0]: 55
8695 04:48:07.634356 [Byte1]: 55
8696 04:48:07.639060
8697 04:48:07.639179 Set Vref, RX VrefLevel [Byte0]: 56
8698 04:48:07.642268 [Byte1]: 56
8699 04:48:07.646385
8700 04:48:07.646523 Set Vref, RX VrefLevel [Byte0]: 57
8701 04:48:07.649834 [Byte1]: 57
8702 04:48:07.653848
8703 04:48:07.654050 Set Vref, RX VrefLevel [Byte0]: 58
8704 04:48:07.657200 [Byte1]: 58
8705 04:48:07.661716
8706 04:48:07.662000 Set Vref, RX VrefLevel [Byte0]: 59
8707 04:48:07.664656 [Byte1]: 59
8708 04:48:07.669406
8709 04:48:07.669651 Set Vref, RX VrefLevel [Byte0]: 60
8710 04:48:07.672763 [Byte1]: 60
8711 04:48:07.676830
8712 04:48:07.677262 Set Vref, RX VrefLevel [Byte0]: 61
8713 04:48:07.680139 [Byte1]: 61
8714 04:48:07.684655
8715 04:48:07.685125 Set Vref, RX VrefLevel [Byte0]: 62
8716 04:48:07.687902 [Byte1]: 62
8717 04:48:07.692102
8718 04:48:07.692533 Set Vref, RX VrefLevel [Byte0]: 63
8719 04:48:07.695731 [Byte1]: 63
8720 04:48:07.699800
8721 04:48:07.700232 Set Vref, RX VrefLevel [Byte0]: 64
8722 04:48:07.702851 [Byte1]: 64
8723 04:48:07.707475
8724 04:48:07.707909 Set Vref, RX VrefLevel [Byte0]: 65
8725 04:48:07.710657 [Byte1]: 65
8726 04:48:07.715172
8727 04:48:07.715648 Set Vref, RX VrefLevel [Byte0]: 66
8728 04:48:07.718366 [Byte1]: 66
8729 04:48:07.722546
8730 04:48:07.722976 Set Vref, RX VrefLevel [Byte0]: 67
8731 04:48:07.725802 [Byte1]: 67
8732 04:48:07.730301
8733 04:48:07.730732 Set Vref, RX VrefLevel [Byte0]: 68
8734 04:48:07.733584 [Byte1]: 68
8735 04:48:07.737802
8736 04:48:07.738262 Set Vref, RX VrefLevel [Byte0]: 69
8737 04:48:07.740679 [Byte1]: 69
8738 04:48:07.745326
8739 04:48:07.745783 Set Vref, RX VrefLevel [Byte0]: 70
8740 04:48:07.748466 [Byte1]: 70
8741 04:48:07.752850
8742 04:48:07.753283 Set Vref, RX VrefLevel [Byte0]: 71
8743 04:48:07.756265 [Byte1]: 71
8744 04:48:07.760278
8745 04:48:07.760710 Set Vref, RX VrefLevel [Byte0]: 72
8746 04:48:07.763583 [Byte1]: 72
8747 04:48:07.767954
8748 04:48:07.768399 Set Vref, RX VrefLevel [Byte0]: 73
8749 04:48:07.771408 [Byte1]: 73
8750 04:48:07.775681
8751 04:48:07.776112 Set Vref, RX VrefLevel [Byte0]: 74
8752 04:48:07.778658 [Byte1]: 74
8753 04:48:07.783125
8754 04:48:07.783556 Final RX Vref Byte 0 = 58 to rank0
8755 04:48:07.786171 Final RX Vref Byte 1 = 61 to rank0
8756 04:48:07.789429 Final RX Vref Byte 0 = 58 to rank1
8757 04:48:07.792947 Final RX Vref Byte 1 = 61 to rank1==
8758 04:48:07.796452 Dram Type= 6, Freq= 0, CH_1, rank 0
8759 04:48:07.802895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8760 04:48:07.803408 ==
8761 04:48:07.803903 DQS Delay:
8762 04:48:07.804246 DQS0 = 0, DQS1 = 0
8763 04:48:07.806200 DQM Delay:
8764 04:48:07.806635 DQM0 = 134, DQM1 = 128
8765 04:48:07.809700 DQ Delay:
8766 04:48:07.812900 DQ0 =136, DQ1 =128, DQ2 =122, DQ3 =132
8767 04:48:07.816294 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =132
8768 04:48:07.819646 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =122
8769 04:48:07.822737 DQ12 =138, DQ13 =134, DQ14 =138, DQ15 =134
8770 04:48:07.823174
8771 04:48:07.823517
8772 04:48:07.823934
8773 04:48:07.826096 [DramC_TX_OE_Calibration] TA2
8774 04:48:07.829689 Original DQ_B0 (3 6) =30, OEN = 27
8775 04:48:07.832955 Original DQ_B1 (3 6) =30, OEN = 27
8776 04:48:07.836107 24, 0x0, End_B0=24 End_B1=24
8777 04:48:07.836746 25, 0x0, End_B0=25 End_B1=25
8778 04:48:07.839411 26, 0x0, End_B0=26 End_B1=26
8779 04:48:07.842779 27, 0x0, End_B0=27 End_B1=27
8780 04:48:07.846250 28, 0x0, End_B0=28 End_B1=28
8781 04:48:07.849125 29, 0x0, End_B0=29 End_B1=29
8782 04:48:07.849707 30, 0x0, End_B0=30 End_B1=30
8783 04:48:07.852745 31, 0x4545, End_B0=30 End_B1=30
8784 04:48:07.856153 Byte0 end_step=30 best_step=27
8785 04:48:07.859556 Byte1 end_step=30 best_step=27
8786 04:48:07.862964 Byte0 TX OE(2T, 0.5T) = (3, 3)
8787 04:48:07.865797 Byte1 TX OE(2T, 0.5T) = (3, 3)
8788 04:48:07.866350
8789 04:48:07.866700
8790 04:48:07.872453 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8791 04:48:07.875745 CH1 RK0: MR19=303, MR18=1826
8792 04:48:07.882302 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8793 04:48:07.882753
8794 04:48:07.886134 ----->DramcWriteLeveling(PI) begin...
8795 04:48:07.886623 ==
8796 04:48:07.889038 Dram Type= 6, Freq= 0, CH_1, rank 1
8797 04:48:07.892465 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8798 04:48:07.893047 ==
8799 04:48:07.895890 Write leveling (Byte 0): 24 => 24
8800 04:48:07.899359 Write leveling (Byte 1): 29 => 29
8801 04:48:07.902255 DramcWriteLeveling(PI) end<-----
8802 04:48:07.902848
8803 04:48:07.903295 ==
8804 04:48:07.905805 Dram Type= 6, Freq= 0, CH_1, rank 1
8805 04:48:07.909027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8806 04:48:07.909523 ==
8807 04:48:07.912497 [Gating] SW mode calibration
8808 04:48:07.918908 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8809 04:48:07.925482 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8810 04:48:07.928840 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 04:48:07.932112 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 04:48:07.938911 1 4 8 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
8813 04:48:07.942501 1 4 12 | B1->B0 | 3434 2625 | 1 1 | (1 1) (0 0)
8814 04:48:07.945808 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8815 04:48:07.952506 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8816 04:48:07.955401 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8817 04:48:07.959122 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8818 04:48:07.965440 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8819 04:48:07.968834 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8820 04:48:07.972287 1 5 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 0)
8821 04:48:07.978802 1 5 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 1)
8822 04:48:07.982057 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8823 04:48:07.985301 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8824 04:48:07.992158 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8825 04:48:07.995609 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 04:48:07.998575 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 04:48:08.005348 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8828 04:48:08.008673 1 6 8 | B1->B0 | 3f3f 2525 | 0 0 | (0 0) (0 0)
8829 04:48:08.012070 1 6 12 | B1->B0 | 4646 4444 | 0 1 | (0 0) (0 0)
8830 04:48:08.018793 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8831 04:48:08.022042 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8832 04:48:08.025317 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8833 04:48:08.031888 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 04:48:08.035218 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8835 04:48:08.038796 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8836 04:48:08.045444 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8837 04:48:08.048876 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 04:48:08.052170 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 04:48:08.055483 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 04:48:08.062061 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 04:48:08.065093 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 04:48:08.068545 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 04:48:08.075206 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 04:48:08.078711 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 04:48:08.082164 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 04:48:08.088503 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 04:48:08.091685 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 04:48:08.095348 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 04:48:08.101732 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 04:48:08.105041 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 04:48:08.108403 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 04:48:08.114873 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8853 04:48:08.118420 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8854 04:48:08.121675 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8855 04:48:08.124814 Total UI for P1: 0, mck2ui 16
8856 04:48:08.128500 best dqsien dly found for B0: ( 1, 9, 10)
8857 04:48:08.131628 Total UI for P1: 0, mck2ui 16
8858 04:48:08.134956 best dqsien dly found for B1: ( 1, 9, 10)
8859 04:48:08.138332 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8860 04:48:08.141448 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8861 04:48:08.141884
8862 04:48:08.148486 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8863 04:48:08.151770 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8864 04:48:08.154769 [Gating] SW calibration Done
8865 04:48:08.155279 ==
8866 04:48:08.158521 Dram Type= 6, Freq= 0, CH_1, rank 1
8867 04:48:08.161278 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8868 04:48:08.161713 ==
8869 04:48:08.162111 RX Vref Scan: 0
8870 04:48:08.162446
8871 04:48:08.164900 RX Vref 0 -> 0, step: 1
8872 04:48:08.165450
8873 04:48:08.168262 RX Delay 0 -> 252, step: 8
8874 04:48:08.171490 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8875 04:48:08.175183 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8876 04:48:08.177907 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8877 04:48:08.184687 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8878 04:48:08.188184 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8879 04:48:08.191265 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8880 04:48:08.194502 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8881 04:48:08.197910 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8882 04:48:08.204664 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8883 04:48:08.208085 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8884 04:48:08.211581 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8885 04:48:08.214935 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8886 04:48:08.217849 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8887 04:48:08.224805 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8888 04:48:08.227961 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8889 04:48:08.231384 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8890 04:48:08.232030 ==
8891 04:48:08.234962 Dram Type= 6, Freq= 0, CH_1, rank 1
8892 04:48:08.237917 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8893 04:48:08.241636 ==
8894 04:48:08.242203 DQS Delay:
8895 04:48:08.242551 DQS0 = 0, DQS1 = 0
8896 04:48:08.244701 DQM Delay:
8897 04:48:08.245115 DQM0 = 136, DQM1 = 132
8898 04:48:08.247941 DQ Delay:
8899 04:48:08.251281 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8900 04:48:08.254432 DQ4 =139, DQ5 =147, DQ6 =139, DQ7 =135
8901 04:48:08.257970 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8902 04:48:08.261375 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =143
8903 04:48:08.261804
8904 04:48:08.262190
8905 04:48:08.262617 ==
8906 04:48:08.264448 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 04:48:08.267843 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 04:48:08.268271 ==
8909 04:48:08.268609
8910 04:48:08.268925
8911 04:48:08.270948 TX Vref Scan disable
8912 04:48:08.274485 == TX Byte 0 ==
8913 04:48:08.277781 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8914 04:48:08.281163 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8915 04:48:08.284631 == TX Byte 1 ==
8916 04:48:08.287945 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8917 04:48:08.291021 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8918 04:48:08.291598 ==
8919 04:48:08.294357 Dram Type= 6, Freq= 0, CH_1, rank 1
8920 04:48:08.300889 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8921 04:48:08.301359 ==
8922 04:48:08.313859
8923 04:48:08.317283 TX Vref early break, caculate TX vref
8924 04:48:08.320628 TX Vref=16, minBit 9, minWin=21, winSum=378
8925 04:48:08.323731 TX Vref=18, minBit 8, minWin=23, winSum=388
8926 04:48:08.327228 TX Vref=20, minBit 8, minWin=23, winSum=393
8927 04:48:08.330414 TX Vref=22, minBit 9, minWin=23, winSum=403
8928 04:48:08.333894 TX Vref=24, minBit 10, minWin=24, winSum=410
8929 04:48:08.340345 TX Vref=26, minBit 9, minWin=24, winSum=416
8930 04:48:08.344139 TX Vref=28, minBit 8, minWin=24, winSum=417
8931 04:48:08.347062 TX Vref=30, minBit 9, minWin=24, winSum=410
8932 04:48:08.350707 TX Vref=32, minBit 8, minWin=24, winSum=403
8933 04:48:08.354036 TX Vref=34, minBit 9, minWin=23, winSum=402
8934 04:48:08.356948 TX Vref=36, minBit 8, minWin=23, winSum=388
8935 04:48:08.364036 [TxChooseVref] Worse bit 8, Min win 24, Win sum 417, Final Vref 28
8936 04:48:08.364468
8937 04:48:08.367341 Final TX Range 0 Vref 28
8938 04:48:08.367974
8939 04:48:08.368381 ==
8940 04:48:08.370896 Dram Type= 6, Freq= 0, CH_1, rank 1
8941 04:48:08.373626 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8942 04:48:08.374095 ==
8943 04:48:08.374446
8944 04:48:08.374765
8945 04:48:08.377299 TX Vref Scan disable
8946 04:48:08.383740 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8947 04:48:08.384171 == TX Byte 0 ==
8948 04:48:08.387199 u2DelayCellOfst[0]=17 cells (5 PI)
8949 04:48:08.390563 u2DelayCellOfst[1]=13 cells (4 PI)
8950 04:48:08.393535 u2DelayCellOfst[2]=0 cells (0 PI)
8951 04:48:08.396928 u2DelayCellOfst[3]=6 cells (2 PI)
8952 04:48:08.400451 u2DelayCellOfst[4]=10 cells (3 PI)
8953 04:48:08.403714 u2DelayCellOfst[5]=20 cells (6 PI)
8954 04:48:08.406738 u2DelayCellOfst[6]=20 cells (6 PI)
8955 04:48:08.410292 u2DelayCellOfst[7]=6 cells (2 PI)
8956 04:48:08.413793 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8957 04:48:08.416774 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8958 04:48:08.420237 == TX Byte 1 ==
8959 04:48:08.423779 u2DelayCellOfst[8]=0 cells (0 PI)
8960 04:48:08.424210 u2DelayCellOfst[9]=3 cells (1 PI)
8961 04:48:08.426629 u2DelayCellOfst[10]=10 cells (3 PI)
8962 04:48:08.430352 u2DelayCellOfst[11]=3 cells (1 PI)
8963 04:48:08.433561 u2DelayCellOfst[12]=10 cells (3 PI)
8964 04:48:08.436692 u2DelayCellOfst[13]=17 cells (5 PI)
8965 04:48:08.440279 u2DelayCellOfst[14]=17 cells (5 PI)
8966 04:48:08.443685 u2DelayCellOfst[15]=17 cells (5 PI)
8967 04:48:08.446461 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8968 04:48:08.453388 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8969 04:48:08.453822 DramC Write-DBI on
8970 04:48:08.454205 ==
8971 04:48:08.456805 Dram Type= 6, Freq= 0, CH_1, rank 1
8972 04:48:08.463397 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8973 04:48:08.463831 ==
8974 04:48:08.464171
8975 04:48:08.464484
8976 04:48:08.464941 TX Vref Scan disable
8977 04:48:08.467144 == TX Byte 0 ==
8978 04:48:08.470580 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8979 04:48:08.473503 == TX Byte 1 ==
8980 04:48:08.476896 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8981 04:48:08.480411 DramC Write-DBI off
8982 04:48:08.480840
8983 04:48:08.481178 [DATLAT]
8984 04:48:08.481495 Freq=1600, CH1 RK1
8985 04:48:08.481800
8986 04:48:08.483674 DATLAT Default: 0xf
8987 04:48:08.484101 0, 0xFFFF, sum = 0
8988 04:48:08.487088 1, 0xFFFF, sum = 0
8989 04:48:08.490445 2, 0xFFFF, sum = 0
8990 04:48:08.490879 3, 0xFFFF, sum = 0
8991 04:48:08.493552 4, 0xFFFF, sum = 0
8992 04:48:08.494025 5, 0xFFFF, sum = 0
8993 04:48:08.496821 6, 0xFFFF, sum = 0
8994 04:48:08.497255 7, 0xFFFF, sum = 0
8995 04:48:08.500365 8, 0xFFFF, sum = 0
8996 04:48:08.500844 9, 0xFFFF, sum = 0
8997 04:48:08.503805 10, 0xFFFF, sum = 0
8998 04:48:08.504244 11, 0xFFFF, sum = 0
8999 04:48:08.507053 12, 0xFFFF, sum = 0
9000 04:48:08.507581 13, 0xFFFF, sum = 0
9001 04:48:08.510387 14, 0x0, sum = 1
9002 04:48:08.510823 15, 0x0, sum = 2
9003 04:48:08.513325 16, 0x0, sum = 3
9004 04:48:08.513762 17, 0x0, sum = 4
9005 04:48:08.516638 best_step = 15
9006 04:48:08.517066
9007 04:48:08.517406 ==
9008 04:48:08.520206 Dram Type= 6, Freq= 0, CH_1, rank 1
9009 04:48:08.523501 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9010 04:48:08.523934 ==
9011 04:48:08.526749 RX Vref Scan: 0
9012 04:48:08.527272
9013 04:48:08.527806 RX Vref 0 -> 0, step: 1
9014 04:48:08.528366
9015 04:48:08.530425 RX Delay 19 -> 252, step: 4
9016 04:48:08.533637 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
9017 04:48:08.539867 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9018 04:48:08.543368 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
9019 04:48:08.546636 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
9020 04:48:08.550081 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9021 04:48:08.553315 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
9022 04:48:08.556647 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9023 04:48:08.563708 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
9024 04:48:08.566847 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9025 04:48:08.569883 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
9026 04:48:08.573247 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9027 04:48:08.576694 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9028 04:48:08.583439 iDelay=195, Bit 12, Center 140 (91 ~ 190) 100
9029 04:48:08.586639 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9030 04:48:08.590054 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9031 04:48:08.593466 iDelay=195, Bit 15, Center 142 (91 ~ 194) 104
9032 04:48:08.594057 ==
9033 04:48:08.596826 Dram Type= 6, Freq= 0, CH_1, rank 1
9034 04:48:08.603349 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9035 04:48:08.603784 ==
9036 04:48:08.604125 DQS Delay:
9037 04:48:08.606843 DQS0 = 0, DQS1 = 0
9038 04:48:08.607501 DQM Delay:
9039 04:48:08.608134 DQM0 = 133, DQM1 = 130
9040 04:48:08.610185 DQ Delay:
9041 04:48:08.613574 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
9042 04:48:08.616748 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =130
9043 04:48:08.620089 DQ8 =112, DQ9 =120, DQ10 =130, DQ11 =126
9044 04:48:08.623247 DQ12 =140, DQ13 =138, DQ14 =138, DQ15 =142
9045 04:48:08.623873
9046 04:48:08.624407
9047 04:48:08.624872
9048 04:48:08.626480 [DramC_TX_OE_Calibration] TA2
9049 04:48:08.629776 Original DQ_B0 (3 6) =30, OEN = 27
9050 04:48:08.633186 Original DQ_B1 (3 6) =30, OEN = 27
9051 04:48:08.636892 24, 0x0, End_B0=24 End_B1=24
9052 04:48:08.637503 25, 0x0, End_B0=25 End_B1=25
9053 04:48:08.639866 26, 0x0, End_B0=26 End_B1=26
9054 04:48:08.643469 27, 0x0, End_B0=27 End_B1=27
9055 04:48:08.646635 28, 0x0, End_B0=28 End_B1=28
9056 04:48:08.649845 29, 0x0, End_B0=29 End_B1=29
9057 04:48:08.650534 30, 0x0, End_B0=30 End_B1=30
9058 04:48:08.653139 31, 0x4141, End_B0=30 End_B1=30
9059 04:48:08.656470 Byte0 end_step=30 best_step=27
9060 04:48:08.659575 Byte1 end_step=30 best_step=27
9061 04:48:08.663224 Byte0 TX OE(2T, 0.5T) = (3, 3)
9062 04:48:08.666623 Byte1 TX OE(2T, 0.5T) = (3, 3)
9063 04:48:08.667195
9064 04:48:08.667746
9065 04:48:08.673177 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 395 ps
9066 04:48:08.676459 CH1 RK1: MR19=303, MR18=1D08
9067 04:48:08.683287 CH1_RK1: MR19=0x303, MR18=0x1D08, DQSOSC=395, MR23=63, INC=23, DEC=15
9068 04:48:08.686336 [RxdqsGatingPostProcess] freq 1600
9069 04:48:08.689742 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9070 04:48:08.693185 best DQS0 dly(2T, 0.5T) = (1, 1)
9071 04:48:08.696509 best DQS1 dly(2T, 0.5T) = (1, 1)
9072 04:48:08.699932 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9073 04:48:08.702771 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9074 04:48:08.706152 best DQS0 dly(2T, 0.5T) = (1, 1)
9075 04:48:08.709653 best DQS1 dly(2T, 0.5T) = (1, 1)
9076 04:48:08.712942 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9077 04:48:08.716283 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9078 04:48:08.719582 Pre-setting of DQS Precalculation
9079 04:48:08.723112 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9080 04:48:08.729630 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9081 04:48:08.736319 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9082 04:48:08.739795
9083 04:48:08.740356
9084 04:48:08.740873 [Calibration Summary] 3200 Mbps
9085 04:48:08.743191 CH 0, Rank 0
9086 04:48:08.743792 SW Impedance : PASS
9087 04:48:08.746409 DUTY Scan : NO K
9088 04:48:08.749449 ZQ Calibration : PASS
9089 04:48:08.750087 Jitter Meter : NO K
9090 04:48:08.752947 CBT Training : PASS
9091 04:48:08.756045 Write leveling : PASS
9092 04:48:08.756619 RX DQS gating : PASS
9093 04:48:08.759355 RX DQ/DQS(RDDQC) : PASS
9094 04:48:08.762871 TX DQ/DQS : PASS
9095 04:48:08.763331 RX DATLAT : PASS
9096 04:48:08.766361 RX DQ/DQS(Engine): PASS
9097 04:48:08.769489 TX OE : PASS
9098 04:48:08.769980 All Pass.
9099 04:48:08.770379
9100 04:48:08.770754 CH 0, Rank 1
9101 04:48:08.772717 SW Impedance : PASS
9102 04:48:08.775876 DUTY Scan : NO K
9103 04:48:08.776401 ZQ Calibration : PASS
9104 04:48:08.779496 Jitter Meter : NO K
9105 04:48:08.782738 CBT Training : PASS
9106 04:48:08.783116 Write leveling : PASS
9107 04:48:08.786200 RX DQS gating : PASS
9108 04:48:08.786622 RX DQ/DQS(RDDQC) : PASS
9109 04:48:08.789131 TX DQ/DQS : PASS
9110 04:48:08.792575 RX DATLAT : PASS
9111 04:48:08.792999 RX DQ/DQS(Engine): PASS
9112 04:48:08.795842 TX OE : PASS
9113 04:48:08.796269 All Pass.
9114 04:48:08.796605
9115 04:48:08.799246 CH 1, Rank 0
9116 04:48:08.799809 SW Impedance : PASS
9117 04:48:08.802649 DUTY Scan : NO K
9118 04:48:08.805534 ZQ Calibration : PASS
9119 04:48:08.806097 Jitter Meter : NO K
9120 04:48:08.809084 CBT Training : PASS
9121 04:48:08.812460 Write leveling : PASS
9122 04:48:08.812887 RX DQS gating : PASS
9123 04:48:08.816139 RX DQ/DQS(RDDQC) : PASS
9124 04:48:08.819086 TX DQ/DQS : PASS
9125 04:48:08.819514 RX DATLAT : PASS
9126 04:48:08.822425 RX DQ/DQS(Engine): PASS
9127 04:48:08.826097 TX OE : PASS
9128 04:48:08.826526 All Pass.
9129 04:48:08.826865
9130 04:48:08.827181 CH 1, Rank 1
9131 04:48:08.829135 SW Impedance : PASS
9132 04:48:08.832436 DUTY Scan : NO K
9133 04:48:08.832862 ZQ Calibration : PASS
9134 04:48:08.836021 Jitter Meter : NO K
9135 04:48:08.836449 CBT Training : PASS
9136 04:48:08.839412 Write leveling : PASS
9137 04:48:08.842939 RX DQS gating : PASS
9138 04:48:08.843365 RX DQ/DQS(RDDQC) : PASS
9139 04:48:08.845646 TX DQ/DQS : PASS
9140 04:48:08.849031 RX DATLAT : PASS
9141 04:48:08.849453 RX DQ/DQS(Engine): PASS
9142 04:48:08.852548 TX OE : PASS
9143 04:48:08.852986 All Pass.
9144 04:48:08.853330
9145 04:48:08.855897 DramC Write-DBI on
9146 04:48:08.858921 PER_BANK_REFRESH: Hybrid Mode
9147 04:48:08.859358 TX_TRACKING: ON
9148 04:48:08.868969 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9149 04:48:08.875685 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9150 04:48:08.882207 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9151 04:48:08.885650 [FAST_K] Save calibration result to emmc
9152 04:48:08.888896 sync common calibartion params.
9153 04:48:08.892382 sync cbt_mode0:1, 1:1
9154 04:48:08.895734 dram_init: ddr_geometry: 2
9155 04:48:08.896238 dram_init: ddr_geometry: 2
9156 04:48:08.899026 dram_init: ddr_geometry: 2
9157 04:48:08.901881 0:dram_rank_size:100000000
9158 04:48:08.905466 1:dram_rank_size:100000000
9159 04:48:08.908783 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9160 04:48:08.912294 DFS_SHUFFLE_HW_MODE: ON
9161 04:48:08.915286 dramc_set_vcore_voltage set vcore to 725000
9162 04:48:08.918945 Read voltage for 1600, 0
9163 04:48:08.919436 Vio18 = 0
9164 04:48:08.919801 Vcore = 725000
9165 04:48:08.922366 Vdram = 0
9166 04:48:08.922860 Vddq = 0
9167 04:48:08.923206 Vmddr = 0
9168 04:48:08.925291 switch to 3200 Mbps bootup
9169 04:48:08.928841 [DramcRunTimeConfig]
9170 04:48:08.929298 PHYPLL
9171 04:48:08.929644 DPM_CONTROL_AFTERK: ON
9172 04:48:08.932237 PER_BANK_REFRESH: ON
9173 04:48:08.935236 REFRESH_OVERHEAD_REDUCTION: ON
9174 04:48:08.935849 CMD_PICG_NEW_MODE: OFF
9175 04:48:08.938601 XRTWTW_NEW_MODE: ON
9176 04:48:08.941998 XRTRTR_NEW_MODE: ON
9177 04:48:08.942512 TX_TRACKING: ON
9178 04:48:08.945387 RDSEL_TRACKING: OFF
9179 04:48:08.946005 DQS Precalculation for DVFS: ON
9180 04:48:08.948282 RX_TRACKING: OFF
9181 04:48:08.948827 HW_GATING DBG: ON
9182 04:48:08.951661 ZQCS_ENABLE_LP4: ON
9183 04:48:08.955132 RX_PICG_NEW_MODE: ON
9184 04:48:08.955698 TX_PICG_NEW_MODE: ON
9185 04:48:08.958337 ENABLE_RX_DCM_DPHY: ON
9186 04:48:08.961672 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9187 04:48:08.962225 DUMMY_READ_FOR_TRACKING: OFF
9188 04:48:08.965133 !!! SPM_CONTROL_AFTERK: OFF
9189 04:48:08.968284 !!! SPM could not control APHY
9190 04:48:08.971641 IMPEDANCE_TRACKING: ON
9191 04:48:08.972207 TEMP_SENSOR: ON
9192 04:48:08.975316 HW_SAVE_FOR_SR: OFF
9193 04:48:08.975883 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9194 04:48:08.981651 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9195 04:48:08.982345 Read ODT Tracking: ON
9196 04:48:08.984903 Refresh Rate DeBounce: ON
9197 04:48:08.988174 DFS_NO_QUEUE_FLUSH: ON
9198 04:48:08.991777 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9199 04:48:08.992351 ENABLE_DFS_RUNTIME_MRW: OFF
9200 04:48:08.994693 DDR_RESERVE_NEW_MODE: ON
9201 04:48:08.998161 MR_CBT_SWITCH_FREQ: ON
9202 04:48:08.998589 =========================
9203 04:48:09.017826 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9204 04:48:09.021189 dram_init: ddr_geometry: 2
9205 04:48:09.039647 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9206 04:48:09.043173 dram_init: dram init end (result: 0)
9207 04:48:09.049436 DRAM-K: Full calibration passed in 24482 msecs
9208 04:48:09.052830 MRC: failed to locate region type 0.
9209 04:48:09.053414 DRAM rank0 size:0x100000000,
9210 04:48:09.056307 DRAM rank1 size=0x100000000
9211 04:48:09.066206 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9212 04:48:09.072587 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9213 04:48:09.079577 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9214 04:48:09.086231 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9215 04:48:09.089516 DRAM rank0 size:0x100000000,
9216 04:48:09.092616 DRAM rank1 size=0x100000000
9217 04:48:09.093091 CBMEM:
9218 04:48:09.096200 IMD: root @ 0xfffff000 254 entries.
9219 04:48:09.099499 IMD: root @ 0xffffec00 62 entries.
9220 04:48:09.102588 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9221 04:48:09.105838 WARNING: RO_VPD is uninitialized or empty.
9222 04:48:09.112750 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9223 04:48:09.119759 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9224 04:48:09.132454 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9225 04:48:09.143731 BS: romstage times (exec / console): total (unknown) / 23984 ms
9226 04:48:09.144292
9227 04:48:09.144798
9228 04:48:09.154005 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9229 04:48:09.157421 ARM64: Exception handlers installed.
9230 04:48:09.160791 ARM64: Testing exception
9231 04:48:09.163655 ARM64: Done test exception
9232 04:48:09.164276 Enumerating buses...
9233 04:48:09.167183 Show all devs... Before device enumeration.
9234 04:48:09.170389 Root Device: enabled 1
9235 04:48:09.173987 CPU_CLUSTER: 0: enabled 1
9236 04:48:09.174456 CPU: 00: enabled 1
9237 04:48:09.177230 Compare with tree...
9238 04:48:09.177857 Root Device: enabled 1
9239 04:48:09.180166 CPU_CLUSTER: 0: enabled 1
9240 04:48:09.183646 CPU: 00: enabled 1
9241 04:48:09.184372 Root Device scanning...
9242 04:48:09.187076 scan_static_bus for Root Device
9243 04:48:09.190163 CPU_CLUSTER: 0 enabled
9244 04:48:09.193547 scan_static_bus for Root Device done
9245 04:48:09.197108 scan_bus: bus Root Device finished in 8 msecs
9246 04:48:09.197702 done
9247 04:48:09.203548 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9248 04:48:09.206894 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9249 04:48:09.213553 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9250 04:48:09.217034 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9251 04:48:09.220434 Allocating resources...
9252 04:48:09.220912 Reading resources...
9253 04:48:09.226716 Root Device read_resources bus 0 link: 0
9254 04:48:09.227163 DRAM rank0 size:0x100000000,
9255 04:48:09.230170 DRAM rank1 size=0x100000000
9256 04:48:09.233615 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9257 04:48:09.236635 CPU: 00 missing read_resources
9258 04:48:09.240051 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9259 04:48:09.247000 Root Device read_resources bus 0 link: 0 done
9260 04:48:09.247437 Done reading resources.
9261 04:48:09.253335 Show resources in subtree (Root Device)...After reading.
9262 04:48:09.256687 Root Device child on link 0 CPU_CLUSTER: 0
9263 04:48:09.260053 CPU_CLUSTER: 0 child on link 0 CPU: 00
9264 04:48:09.269698 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9265 04:48:09.270254 CPU: 00
9266 04:48:09.273253 Root Device assign_resources, bus 0 link: 0
9267 04:48:09.276546 CPU_CLUSTER: 0 missing set_resources
9268 04:48:09.283272 Root Device assign_resources, bus 0 link: 0 done
9269 04:48:09.284099 Done setting resources.
9270 04:48:09.289764 Show resources in subtree (Root Device)...After assigning values.
9271 04:48:09.293244 Root Device child on link 0 CPU_CLUSTER: 0
9272 04:48:09.296321 CPU_CLUSTER: 0 child on link 0 CPU: 00
9273 04:48:09.306255 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9274 04:48:09.306730 CPU: 00
9275 04:48:09.309538 Done allocating resources.
9276 04:48:09.313186 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9277 04:48:09.316343 Enabling resources...
9278 04:48:09.316777 done.
9279 04:48:09.323227 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9280 04:48:09.323664 Initializing devices...
9281 04:48:09.326486 Root Device init
9282 04:48:09.326923 init hardware done!
9283 04:48:09.329807 0x00000018: ctrlr->caps
9284 04:48:09.332997 52.000 MHz: ctrlr->f_max
9285 04:48:09.333506 0.400 MHz: ctrlr->f_min
9286 04:48:09.336393 0x40ff8080: ctrlr->voltages
9287 04:48:09.336835 sclk: 390625
9288 04:48:09.339710 Bus Width = 1
9289 04:48:09.340142 sclk: 390625
9290 04:48:09.343108 Bus Width = 1
9291 04:48:09.343542 Early init status = 3
9292 04:48:09.349473 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9293 04:48:09.352938 in-header: 03 fc 00 00 01 00 00 00
9294 04:48:09.356379 in-data: 00
9295 04:48:09.359635 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9296 04:48:09.364123 in-header: 03 fd 00 00 00 00 00 00
9297 04:48:09.367495 in-data:
9298 04:48:09.370931 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9299 04:48:09.375700 in-header: 03 fc 00 00 01 00 00 00
9300 04:48:09.378475 in-data: 00
9301 04:48:09.381918 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9302 04:48:09.387147 in-header: 03 fd 00 00 00 00 00 00
9303 04:48:09.390588 in-data:
9304 04:48:09.394076 [SSUSB] Setting up USB HOST controller...
9305 04:48:09.397563 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9306 04:48:09.400833 [SSUSB] phy power-on done.
9307 04:48:09.404059 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9308 04:48:09.410411 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9309 04:48:09.413886 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9310 04:48:09.420437 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9311 04:48:09.427553 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9312 04:48:09.434087 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9313 04:48:09.440613 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9314 04:48:09.447342 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9315 04:48:09.450213 SPM: binary array size = 0x9dc
9316 04:48:09.453902 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9317 04:48:09.460331 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9318 04:48:09.467092 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9319 04:48:09.470481 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9320 04:48:09.476907 configure_display: Starting display init
9321 04:48:09.510680 anx7625_power_on_init: Init interface.
9322 04:48:09.514341 anx7625_disable_pd_protocol: Disabled PD feature.
9323 04:48:09.517142 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9324 04:48:09.545162 anx7625_start_dp_work: Secure OCM version=00
9325 04:48:09.548678 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9326 04:48:09.563459 sp_tx_get_edid_block: EDID Block = 1
9327 04:48:09.665706 Extracted contents:
9328 04:48:09.669104 header: 00 ff ff ff ff ff ff 00
9329 04:48:09.672501 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9330 04:48:09.675840 version: 01 04
9331 04:48:09.679278 basic params: 95 1f 11 78 0a
9332 04:48:09.682233 chroma info: 76 90 94 55 54 90 27 21 50 54
9333 04:48:09.685278 established: 00 00 00
9334 04:48:09.692038 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9335 04:48:09.698545 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9336 04:48:09.701519 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9337 04:48:09.708424 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9338 04:48:09.715018 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9339 04:48:09.718293 extensions: 00
9340 04:48:09.718379 checksum: fb
9341 04:48:09.718447
9342 04:48:09.721797 Manufacturer: IVO Model 57d Serial Number 0
9343 04:48:09.725287 Made week 0 of 2020
9344 04:48:09.725371 EDID version: 1.4
9345 04:48:09.728452 Digital display
9346 04:48:09.731818 6 bits per primary color channel
9347 04:48:09.731906 DisplayPort interface
9348 04:48:09.734808 Maximum image size: 31 cm x 17 cm
9349 04:48:09.738352 Gamma: 220%
9350 04:48:09.738437 Check DPMS levels
9351 04:48:09.741744 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9352 04:48:09.744994 First detailed timing is preferred timing
9353 04:48:09.748701 Established timings supported:
9354 04:48:09.751579 Standard timings supported:
9355 04:48:09.755252 Detailed timings
9356 04:48:09.758495 Hex of detail: 383680a07038204018303c0035ae10000019
9357 04:48:09.761875 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9358 04:48:09.768187 0780 0798 07c8 0820 hborder 0
9359 04:48:09.771975 0438 043b 0447 0458 vborder 0
9360 04:48:09.775136 -hsync -vsync
9361 04:48:09.775222 Did detailed timing
9362 04:48:09.778426 Hex of detail: 000000000000000000000000000000000000
9363 04:48:09.781867 Manufacturer-specified data, tag 0
9364 04:48:09.788299 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9365 04:48:09.788393 ASCII string: InfoVision
9366 04:48:09.795132 Hex of detail: 000000fe00523134304e574635205248200a
9367 04:48:09.798087 ASCII string: R140NWF5 RH
9368 04:48:09.798231 Checksum
9369 04:48:09.798320 Checksum: 0xfb (valid)
9370 04:48:09.804807 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9371 04:48:09.808363 DSI data_rate: 832800000 bps
9372 04:48:09.811692 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9373 04:48:09.818658 anx7625_parse_edid: pixelclock(138800).
9374 04:48:09.821666 hactive(1920), hsync(48), hfp(24), hbp(88)
9375 04:48:09.825293 vactive(1080), vsync(12), vfp(3), vbp(17)
9376 04:48:09.828368 anx7625_dsi_config: config dsi.
9377 04:48:09.834830 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9378 04:48:09.847719 anx7625_dsi_config: success to config DSI
9379 04:48:09.850879 anx7625_dp_start: MIPI phy setup OK.
9380 04:48:09.854348 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9381 04:48:09.857662 mtk_ddp_mode_set invalid vrefresh 60
9382 04:48:09.861197 main_disp_path_setup
9383 04:48:09.861618 ovl_layer_smi_id_en
9384 04:48:09.864515 ovl_layer_smi_id_en
9385 04:48:09.864937 ccorr_config
9386 04:48:09.865272 aal_config
9387 04:48:09.867853 gamma_config
9388 04:48:09.868276 postmask_config
9389 04:48:09.871052 dither_config
9390 04:48:09.874225 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9391 04:48:09.881070 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9392 04:48:09.884317 Root Device init finished in 555 msecs
9393 04:48:09.887788 CPU_CLUSTER: 0 init
9394 04:48:09.894460 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9395 04:48:09.897458 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9396 04:48:09.900811 APU_MBOX 0x190000b0 = 0x10001
9397 04:48:09.904382 APU_MBOX 0x190001b0 = 0x10001
9398 04:48:09.907279 APU_MBOX 0x190005b0 = 0x10001
9399 04:48:09.910819 APU_MBOX 0x190006b0 = 0x10001
9400 04:48:09.914487 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9401 04:48:09.926886 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9402 04:48:09.939119 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9403 04:48:09.946062 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9404 04:48:09.957487 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9405 04:48:09.966500 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9406 04:48:09.970001 CPU_CLUSTER: 0 init finished in 81 msecs
9407 04:48:09.973413 Devices initialized
9408 04:48:09.976735 Show all devs... After init.
9409 04:48:09.977195 Root Device: enabled 1
9410 04:48:09.980165 CPU_CLUSTER: 0: enabled 1
9411 04:48:09.983046 CPU: 00: enabled 1
9412 04:48:09.986389 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9413 04:48:09.989745 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9414 04:48:09.993181 ELOG: NV offset 0x57f000 size 0x1000
9415 04:48:10.000205 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9416 04:48:10.006595 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9417 04:48:10.009882 ELOG: Event(17) added with size 13 at 2024-02-04 04:47:32 UTC
9418 04:48:10.013180 out: cmd=0x121: 03 db 21 01 00 00 00 00
9419 04:48:10.016911 in-header: 03 43 00 00 2c 00 00 00
9420 04:48:10.030174 in-data: 1c 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9421 04:48:10.036667 ELOG: Event(A1) added with size 10 at 2024-02-04 04:47:32 UTC
9422 04:48:10.043576 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9423 04:48:10.050285 ELOG: Event(A0) added with size 9 at 2024-02-04 04:47:32 UTC
9424 04:48:10.053629 elog_add_boot_reason: Logged dev mode boot
9425 04:48:10.056878 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9426 04:48:10.060310 Finalize devices...
9427 04:48:10.060731 Devices finalized
9428 04:48:10.067104 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9429 04:48:10.070521 Writing coreboot table at 0xffe64000
9430 04:48:10.073368 0. 000000000010a000-0000000000113fff: RAMSTAGE
9431 04:48:10.076762 1. 0000000040000000-00000000400fffff: RAM
9432 04:48:10.080498 2. 0000000040100000-000000004032afff: RAMSTAGE
9433 04:48:10.086742 3. 000000004032b000-00000000545fffff: RAM
9434 04:48:10.089814 4. 0000000054600000-000000005465ffff: BL31
9435 04:48:10.093191 5. 0000000054660000-00000000ffe63fff: RAM
9436 04:48:10.096718 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9437 04:48:10.103108 7. 0000000100000000-000000023fffffff: RAM
9438 04:48:10.103191 Passing 5 GPIOs to payload:
9439 04:48:10.109808 NAME | PORT | POLARITY | VALUE
9440 04:48:10.113474 EC in RW | 0x000000aa | low | undefined
9441 04:48:10.120049 EC interrupt | 0x00000005 | low | undefined
9442 04:48:10.123359 TPM interrupt | 0x000000ab | high | undefined
9443 04:48:10.126801 SD card detect | 0x00000011 | high | undefined
9444 04:48:10.133052 speaker enable | 0x00000093 | high | undefined
9445 04:48:10.136240 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9446 04:48:10.139675 in-header: 03 f9 00 00 02 00 00 00
9447 04:48:10.139760 in-data: 02 00
9448 04:48:10.143225 ADC[4]: Raw value=901032 ID=7
9449 04:48:10.146596 ADC[3]: Raw value=212810 ID=1
9450 04:48:10.146694 RAM Code: 0x71
9451 04:48:10.149674 ADC[6]: Raw value=74502 ID=0
9452 04:48:10.153160 ADC[5]: Raw value=212441 ID=1
9453 04:48:10.153265 SKU Code: 0x1
9454 04:48:10.159830 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 3234
9455 04:48:10.163029 coreboot table: 964 bytes.
9456 04:48:10.166554 IMD ROOT 0. 0xfffff000 0x00001000
9457 04:48:10.169555 IMD SMALL 1. 0xffffe000 0x00001000
9458 04:48:10.173219 RO MCACHE 2. 0xffffc000 0x00001104
9459 04:48:10.176724 CONSOLE 3. 0xfff7c000 0x00080000
9460 04:48:10.179655 FMAP 4. 0xfff7b000 0x00000452
9461 04:48:10.183473 TIME STAMP 5. 0xfff7a000 0x00000910
9462 04:48:10.186332 VBOOT WORK 6. 0xfff66000 0x00014000
9463 04:48:10.189582 RAMOOPS 7. 0xffe66000 0x00100000
9464 04:48:10.193139 COREBOOT 8. 0xffe64000 0x00002000
9465 04:48:10.193448 IMD small region:
9466 04:48:10.196719 IMD ROOT 0. 0xffffec00 0x00000400
9467 04:48:10.200209 VPD 1. 0xffffeb80 0x0000006c
9468 04:48:10.203272 MMC STATUS 2. 0xffffeb60 0x00000004
9469 04:48:10.210026 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9470 04:48:10.210467 Probing TPM: done!
9471 04:48:10.216823 Connected to device vid:did:rid of 1ae0:0028:00
9472 04:48:10.223184 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9473 04:48:10.226589 Initialized TPM device CR50 revision 0
9474 04:48:10.231093 Checking cr50 for pending updates
9475 04:48:10.236196 Reading cr50 TPM mode
9476 04:48:10.245273 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9477 04:48:10.251274 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9478 04:48:10.291616 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9479 04:48:10.295155 Checking segment from ROM address 0x40100000
9480 04:48:10.298522 Checking segment from ROM address 0x4010001c
9481 04:48:10.304937 Loading segment from ROM address 0x40100000
9482 04:48:10.305373 code (compression=0)
9483 04:48:10.311508 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9484 04:48:10.321495 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9485 04:48:10.321935 it's not compressed!
9486 04:48:10.328387 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9487 04:48:10.332033 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9488 04:48:10.351743 Loading segment from ROM address 0x4010001c
9489 04:48:10.352182 Entry Point 0x80000000
9490 04:48:10.355402 Loaded segments
9491 04:48:10.358851 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9492 04:48:10.365000 Jumping to boot code at 0x80000000(0xffe64000)
9493 04:48:10.371785 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9494 04:48:10.378379 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9495 04:48:10.386109 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9496 04:48:10.389434 Checking segment from ROM address 0x40100000
9497 04:48:10.392930 Checking segment from ROM address 0x4010001c
9498 04:48:10.399405 Loading segment from ROM address 0x40100000
9499 04:48:10.399714 code (compression=1)
9500 04:48:10.406317 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9501 04:48:10.415946 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9502 04:48:10.416256 using LZMA
9503 04:48:10.424444 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9504 04:48:10.431469 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9505 04:48:10.434950 Loading segment from ROM address 0x4010001c
9506 04:48:10.435433 Entry Point 0x54601000
9507 04:48:10.437927 Loaded segments
9508 04:48:10.441337 NOTICE: MT8192 bl31_setup
9509 04:48:10.448310 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9510 04:48:10.451682 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9511 04:48:10.454931 WARNING: region 0:
9512 04:48:10.458391 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9513 04:48:10.458829 WARNING: region 1:
9514 04:48:10.465042 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9515 04:48:10.468527 WARNING: region 2:
9516 04:48:10.471566 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9517 04:48:10.475173 WARNING: region 3:
9518 04:48:10.478338 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9519 04:48:10.481525 WARNING: region 4:
9520 04:48:10.488438 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9521 04:48:10.488921 WARNING: region 5:
9522 04:48:10.491806 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9523 04:48:10.494997 WARNING: region 6:
9524 04:48:10.498339 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9525 04:48:10.501493 WARNING: region 7:
9526 04:48:10.504989 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9527 04:48:10.511664 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9528 04:48:10.514672 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9529 04:48:10.518559 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9530 04:48:10.525013 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9531 04:48:10.528039 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9532 04:48:10.531763 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9533 04:48:10.538587 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9534 04:48:10.541601 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9535 04:48:10.545322 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9536 04:48:10.551758 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9537 04:48:10.555181 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9538 04:48:10.561827 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9539 04:48:10.565404 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9540 04:48:10.568508 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9541 04:48:10.575144 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9542 04:48:10.578830 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9543 04:48:10.581998 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9544 04:48:10.588570 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9545 04:48:10.592100 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9546 04:48:10.595306 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9547 04:48:10.602281 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9548 04:48:10.605542 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9549 04:48:10.612155 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9550 04:48:10.615197 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9551 04:48:10.618505 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9552 04:48:10.625396 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9553 04:48:10.628667 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9554 04:48:10.635563 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9555 04:48:10.639084 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9556 04:48:10.642697 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9557 04:48:10.648954 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9558 04:48:10.652453 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9559 04:48:10.655480 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9560 04:48:10.662383 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9561 04:48:10.665752 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9562 04:48:10.669245 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9563 04:48:10.672280 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9564 04:48:10.678690 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9565 04:48:10.682504 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9566 04:48:10.685791 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9567 04:48:10.688858 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9568 04:48:10.692359 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9569 04:48:10.699246 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9570 04:48:10.702488 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9571 04:48:10.705791 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9572 04:48:10.712439 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9573 04:48:10.715846 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9574 04:48:10.719283 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9575 04:48:10.722520 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9576 04:48:10.729271 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9577 04:48:10.732700 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9578 04:48:10.739503 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9579 04:48:10.742645 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9580 04:48:10.749288 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9581 04:48:10.752638 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9582 04:48:10.755759 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9583 04:48:10.762294 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9584 04:48:10.765733 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9585 04:48:10.772594 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9586 04:48:10.775741 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9587 04:48:10.782552 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9588 04:48:10.786061 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9589 04:48:10.789478 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9590 04:48:10.796100 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9591 04:48:10.799382 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9592 04:48:10.806054 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9593 04:48:10.809182 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9594 04:48:10.816260 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9595 04:48:10.819336 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9596 04:48:10.822685 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9597 04:48:10.829440 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9598 04:48:10.832714 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9599 04:48:10.839655 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9600 04:48:10.842586 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9601 04:48:10.849427 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9602 04:48:10.853011 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9603 04:48:10.855987 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9604 04:48:10.862896 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9605 04:48:10.866263 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9606 04:48:10.872973 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9607 04:48:10.875891 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9608 04:48:10.882788 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9609 04:48:10.886014 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9610 04:48:10.889452 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9611 04:48:10.895434 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9612 04:48:10.898862 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9613 04:48:10.905552 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9614 04:48:10.909155 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9615 04:48:10.915872 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9616 04:48:10.918891 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9617 04:48:10.922188 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9618 04:48:10.929141 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9619 04:48:10.932282 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9620 04:48:10.939275 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9621 04:48:10.942717 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9622 04:48:10.949125 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9623 04:48:10.952392 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9624 04:48:10.955790 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9625 04:48:10.959164 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9626 04:48:10.965893 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9627 04:48:10.969094 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9628 04:48:10.972713 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9629 04:48:10.979243 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9630 04:48:10.982682 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9631 04:48:10.989710 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9632 04:48:10.993132 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9633 04:48:10.996396 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9634 04:48:11.003148 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9635 04:48:11.006121 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9636 04:48:11.009564 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9637 04:48:11.016259 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9638 04:48:11.019871 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9639 04:48:11.026248 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9640 04:48:11.029784 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9641 04:48:11.033226 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9642 04:48:11.039446 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9643 04:48:11.042859 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9644 04:48:11.046314 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9645 04:48:11.053006 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9646 04:48:11.056077 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9647 04:48:11.060127 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9648 04:48:11.062954 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9649 04:48:11.069636 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9650 04:48:11.073048 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9651 04:48:11.076262 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9652 04:48:11.082949 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9653 04:48:11.086381 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9654 04:48:11.089882 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9655 04:48:11.096304 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9656 04:48:11.099892 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9657 04:48:11.106452 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9658 04:48:11.109762 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9659 04:48:11.113259 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9660 04:48:11.119946 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9661 04:48:11.122893 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9662 04:48:11.129585 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9663 04:48:11.133106 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9664 04:48:11.136603 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9665 04:48:11.142807 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9666 04:48:11.146093 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9667 04:48:11.149825 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9668 04:48:11.156740 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9669 04:48:11.160079 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9670 04:48:11.166277 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9671 04:48:11.170055 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9672 04:48:11.173120 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9673 04:48:11.180021 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9674 04:48:11.183333 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9675 04:48:11.187000 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9676 04:48:11.193787 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9677 04:48:11.196783 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9678 04:48:11.203463 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9679 04:48:11.206486 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9680 04:48:11.210127 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9681 04:48:11.216796 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9682 04:48:11.220183 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9683 04:48:11.226642 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9684 04:48:11.230226 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9685 04:48:11.233319 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9686 04:48:11.240100 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9687 04:48:11.243534 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9688 04:48:11.246772 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9689 04:48:11.253878 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9690 04:48:11.256850 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9691 04:48:11.263755 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9692 04:48:11.266588 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9693 04:48:11.269920 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9694 04:48:11.276707 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9695 04:48:11.280114 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9696 04:48:11.286453 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9697 04:48:11.290434 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9698 04:48:11.292813 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9699 04:48:11.299548 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9700 04:48:11.302938 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9701 04:48:11.310011 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9702 04:48:11.313239 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9703 04:48:11.316498 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9704 04:48:11.323437 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9705 04:48:11.326246 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9706 04:48:11.329647 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9707 04:48:11.336409 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9708 04:48:11.339347 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9709 04:48:11.346592 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9710 04:48:11.349739 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9711 04:48:11.353056 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9712 04:48:11.360042 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9713 04:48:11.362806 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9714 04:48:11.369743 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9715 04:48:11.373190 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9716 04:48:11.376291 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9717 04:48:11.382755 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9718 04:48:11.386353 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9719 04:48:11.392833 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9720 04:48:11.395931 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9721 04:48:11.399319 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9722 04:48:11.406004 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9723 04:48:11.409284 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9724 04:48:11.415979 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9725 04:48:11.419331 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9726 04:48:11.426040 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9727 04:48:11.429850 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9728 04:48:11.432459 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9729 04:48:11.439522 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9730 04:48:11.442619 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9731 04:48:11.449375 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9732 04:48:11.452701 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9733 04:48:11.456271 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9734 04:48:11.462741 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9735 04:48:11.466067 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9736 04:48:11.473171 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9737 04:48:11.476637 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9738 04:48:11.479354 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9739 04:48:11.486403 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9740 04:48:11.490060 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9741 04:48:11.496734 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9742 04:48:11.499610 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9743 04:48:11.506304 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9744 04:48:11.509764 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9745 04:48:11.512905 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9746 04:48:11.519388 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9747 04:48:11.522890 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9748 04:48:11.529172 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9749 04:48:11.532506 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9750 04:48:11.535999 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9751 04:48:11.542649 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9752 04:48:11.545783 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9753 04:48:11.552488 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9754 04:48:11.556342 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9755 04:48:11.559108 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9756 04:48:11.566364 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9757 04:48:11.569277 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9758 04:48:11.572943 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9759 04:48:11.575676 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9760 04:48:11.582831 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9761 04:48:11.586285 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9762 04:48:11.589430 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9763 04:48:11.595779 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9764 04:48:11.599261 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9765 04:48:11.602277 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9766 04:48:11.609453 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9767 04:48:11.612582 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9768 04:48:11.619091 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9769 04:48:11.622481 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9770 04:48:11.625728 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9771 04:48:11.632635 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9772 04:48:11.636060 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9773 04:48:11.639577 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9774 04:48:11.645859 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9775 04:48:11.649126 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9776 04:48:11.652693 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9777 04:48:11.658799 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9778 04:48:11.662535 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9779 04:48:11.669539 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9780 04:48:11.672389 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9781 04:48:11.675639 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9782 04:48:11.682632 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9783 04:48:11.685639 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9784 04:48:11.692466 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9785 04:48:11.695249 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9786 04:48:11.698922 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9787 04:48:11.705411 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9788 04:48:11.708538 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9789 04:48:11.712182 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9790 04:48:11.718806 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9791 04:48:11.722256 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9792 04:48:11.725609 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9793 04:48:11.732234 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9794 04:48:11.735229 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9795 04:48:11.738452 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9796 04:48:11.745575 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9797 04:48:11.748938 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9798 04:48:11.751955 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9799 04:48:11.755653 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9800 04:48:11.758665 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9801 04:48:11.765096 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9802 04:48:11.768755 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9803 04:48:11.771900 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9804 04:48:11.775434 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9805 04:48:11.781882 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9806 04:48:11.785272 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9807 04:48:11.788649 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9808 04:48:11.795377 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9809 04:48:11.798587 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9810 04:48:11.801790 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9811 04:48:11.808664 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9812 04:48:11.811820 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9813 04:48:11.818501 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9814 04:48:11.821699 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9815 04:48:11.828426 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9816 04:48:11.831774 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9817 04:48:11.834972 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9818 04:48:11.841898 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9819 04:48:11.845585 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9820 04:48:11.848367 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9821 04:48:11.855139 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9822 04:48:11.858585 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9823 04:48:11.865275 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9824 04:48:11.868435 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9825 04:48:11.871382 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9826 04:48:11.878634 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9827 04:48:11.882150 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9828 04:48:11.888237 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9829 04:48:11.891568 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9830 04:48:11.898458 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9831 04:48:11.901505 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9832 04:48:11.904844 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9833 04:48:11.911384 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9834 04:48:11.914905 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9835 04:48:11.921437 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9836 04:48:11.925210 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9837 04:48:11.928538 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9838 04:48:11.934987 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9839 04:48:11.938275 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9840 04:48:11.944776 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9841 04:48:11.948065 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9842 04:48:11.951498 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9843 04:48:11.958539 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9844 04:48:11.961778 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9845 04:48:11.968010 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9846 04:48:11.971960 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9847 04:48:11.974702 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9848 04:48:11.982068 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9849 04:48:11.984717 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9850 04:48:11.991655 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9851 04:48:11.994919 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9852 04:48:11.998533 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9853 04:48:12.004853 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9854 04:48:12.008325 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9855 04:48:12.014585 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9856 04:48:12.018444 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9857 04:48:12.021395 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9858 04:48:12.028431 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9859 04:48:12.031452 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9860 04:48:12.037776 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9861 04:48:12.041712 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9862 04:48:12.048382 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9863 04:48:12.051606 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9864 04:48:12.054903 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9865 04:48:12.061532 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9866 04:48:12.064914 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9867 04:48:12.068283 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9868 04:48:12.074630 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9869 04:48:12.078180 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9870 04:48:12.084418 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9871 04:48:12.087926 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9872 04:48:12.091435 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9873 04:48:12.098056 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9874 04:48:12.101286 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9875 04:48:12.108035 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9876 04:48:12.111029 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9877 04:48:12.117837 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9878 04:48:12.120962 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9879 04:48:12.124599 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9880 04:48:12.130911 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9881 04:48:12.134195 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9882 04:48:12.141289 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9883 04:48:12.144446 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9884 04:48:12.151188 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9885 04:48:12.154406 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9886 04:48:12.157785 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9887 04:48:12.164686 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9888 04:48:12.168200 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9889 04:48:12.174384 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9890 04:48:12.177859 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9891 04:48:12.183894 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9892 04:48:12.187538 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9893 04:48:12.190910 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9894 04:48:12.197434 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9895 04:48:12.200533 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9896 04:48:12.207632 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9897 04:48:12.210834 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9898 04:48:12.217491 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9899 04:48:12.220519 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9900 04:48:12.227391 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9901 04:48:12.230378 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9902 04:48:12.234090 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9903 04:48:12.240809 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9904 04:48:12.244296 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9905 04:48:12.250507 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9906 04:48:12.254093 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9907 04:48:12.260775 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9908 04:48:12.264045 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9909 04:48:12.267052 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9910 04:48:12.273980 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9911 04:48:12.277327 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9912 04:48:12.284059 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9913 04:48:12.287099 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9914 04:48:12.294040 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9915 04:48:12.297265 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9916 04:48:12.300082 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9917 04:48:12.306954 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9918 04:48:12.310610 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9919 04:48:12.316729 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9920 04:48:12.320725 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9921 04:48:12.326506 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9922 04:48:12.330368 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9923 04:48:12.333279 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9924 04:48:12.340419 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9925 04:48:12.343384 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9926 04:48:12.350179 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9927 04:48:12.353476 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9928 04:48:12.360170 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9929 04:48:12.363381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9930 04:48:12.367155 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9931 04:48:12.373542 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9932 04:48:12.376635 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9933 04:48:12.383278 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9934 04:48:12.386747 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9935 04:48:12.393382 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9936 04:48:12.396791 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9937 04:48:12.403265 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9938 04:48:12.406443 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9939 04:48:12.413303 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9940 04:48:12.416553 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9941 04:48:12.422941 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9942 04:48:12.426291 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9943 04:48:12.433188 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9944 04:48:12.436268 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9945 04:48:12.443261 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9946 04:48:12.446219 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9947 04:48:12.453088 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9948 04:48:12.456515 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9949 04:48:12.462588 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9950 04:48:12.466041 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9951 04:48:12.472800 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9952 04:48:12.475977 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9953 04:48:12.482743 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9954 04:48:12.486199 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9955 04:48:12.492770 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9956 04:48:12.496056 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9957 04:48:12.502570 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9958 04:48:12.506379 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9959 04:48:12.512959 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9960 04:48:12.516234 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9961 04:48:12.519399 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9962 04:48:12.522545 INFO: [APUAPC] vio 0
9963 04:48:12.525869 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9964 04:48:12.532986 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9965 04:48:12.535933 INFO: [APUAPC] D0_APC_0: 0x400510
9966 04:48:12.539356 INFO: [APUAPC] D0_APC_1: 0x0
9967 04:48:12.542610 INFO: [APUAPC] D0_APC_2: 0x1540
9968 04:48:12.543080 INFO: [APUAPC] D0_APC_3: 0x0
9969 04:48:12.546271 INFO: [APUAPC] D1_APC_0: 0xffffffff
9970 04:48:12.549593 INFO: [APUAPC] D1_APC_1: 0xffffffff
9971 04:48:12.552881 INFO: [APUAPC] D1_APC_2: 0x3fffff
9972 04:48:12.556125 INFO: [APUAPC] D1_APC_3: 0x0
9973 04:48:12.559707 INFO: [APUAPC] D2_APC_0: 0xffffffff
9974 04:48:12.563097 INFO: [APUAPC] D2_APC_1: 0xffffffff
9975 04:48:12.566202 INFO: [APUAPC] D2_APC_2: 0x3fffff
9976 04:48:12.569448 INFO: [APUAPC] D2_APC_3: 0x0
9977 04:48:12.573082 INFO: [APUAPC] D3_APC_0: 0xffffffff
9978 04:48:12.575975 INFO: [APUAPC] D3_APC_1: 0xffffffff
9979 04:48:12.579409 INFO: [APUAPC] D3_APC_2: 0x3fffff
9980 04:48:12.583042 INFO: [APUAPC] D3_APC_3: 0x0
9981 04:48:12.586661 INFO: [APUAPC] D4_APC_0: 0xffffffff
9982 04:48:12.589473 INFO: [APUAPC] D4_APC_1: 0xffffffff
9983 04:48:12.592855 INFO: [APUAPC] D4_APC_2: 0x3fffff
9984 04:48:12.596313 INFO: [APUAPC] D4_APC_3: 0x0
9985 04:48:12.599509 INFO: [APUAPC] D5_APC_0: 0xffffffff
9986 04:48:12.602646 INFO: [APUAPC] D5_APC_1: 0xffffffff
9987 04:48:12.605802 INFO: [APUAPC] D5_APC_2: 0x3fffff
9988 04:48:12.609360 INFO: [APUAPC] D5_APC_3: 0x0
9989 04:48:12.612429 INFO: [APUAPC] D6_APC_0: 0xffffffff
9990 04:48:12.616212 INFO: [APUAPC] D6_APC_1: 0xffffffff
9991 04:48:12.619237 INFO: [APUAPC] D6_APC_2: 0x3fffff
9992 04:48:12.622764 INFO: [APUAPC] D6_APC_3: 0x0
9993 04:48:12.625830 INFO: [APUAPC] D7_APC_0: 0xffffffff
9994 04:48:12.629184 INFO: [APUAPC] D7_APC_1: 0xffffffff
9995 04:48:12.632712 INFO: [APUAPC] D7_APC_2: 0x3fffff
9996 04:48:12.636079 INFO: [APUAPC] D7_APC_3: 0x0
9997 04:48:12.639188 INFO: [APUAPC] D8_APC_0: 0xffffffff
9998 04:48:12.642516 INFO: [APUAPC] D8_APC_1: 0xffffffff
9999 04:48:12.646066 INFO: [APUAPC] D8_APC_2: 0x3fffff
10000 04:48:12.648782 INFO: [APUAPC] D8_APC_3: 0x0
10001 04:48:12.652827 INFO: [APUAPC] D9_APC_0: 0xffffffff
10002 04:48:12.655715 INFO: [APUAPC] D9_APC_1: 0xffffffff
10003 04:48:12.659259 INFO: [APUAPC] D9_APC_2: 0x3fffff
10004 04:48:12.662313 INFO: [APUAPC] D9_APC_3: 0x0
10005 04:48:12.665698 INFO: [APUAPC] D10_APC_0: 0xffffffff
10006 04:48:12.668848 INFO: [APUAPC] D10_APC_1: 0xffffffff
10007 04:48:12.671922 INFO: [APUAPC] D10_APC_2: 0x3fffff
10008 04:48:12.675572 INFO: [APUAPC] D10_APC_3: 0x0
10009 04:48:12.678805 INFO: [APUAPC] D11_APC_0: 0xffffffff
10010 04:48:12.682385 INFO: [APUAPC] D11_APC_1: 0xffffffff
10011 04:48:12.685754 INFO: [APUAPC] D11_APC_2: 0x3fffff
10012 04:48:12.688701 INFO: [APUAPC] D11_APC_3: 0x0
10013 04:48:12.692005 INFO: [APUAPC] D12_APC_0: 0xffffffff
10014 04:48:12.695441 INFO: [APUAPC] D12_APC_1: 0xffffffff
10015 04:48:12.698915 INFO: [APUAPC] D12_APC_2: 0x3fffff
10016 04:48:12.702033 INFO: [APUAPC] D12_APC_3: 0x0
10017 04:48:12.705262 INFO: [APUAPC] D13_APC_0: 0xffffffff
10018 04:48:12.708750 INFO: [APUAPC] D13_APC_1: 0xffffffff
10019 04:48:12.712161 INFO: [APUAPC] D13_APC_2: 0x3fffff
10020 04:48:12.715578 INFO: [APUAPC] D13_APC_3: 0x0
10021 04:48:12.718493 INFO: [APUAPC] D14_APC_0: 0xffffffff
10022 04:48:12.721919 INFO: [APUAPC] D14_APC_1: 0xffffffff
10023 04:48:12.725002 INFO: [APUAPC] D14_APC_2: 0x3fffff
10024 04:48:12.728513 INFO: [APUAPC] D14_APC_3: 0x0
10025 04:48:12.731742 INFO: [APUAPC] D15_APC_0: 0xffffffff
10026 04:48:12.734998 INFO: [APUAPC] D15_APC_1: 0xffffffff
10027 04:48:12.738436 INFO: [APUAPC] D15_APC_2: 0x3fffff
10028 04:48:12.741582 INFO: [APUAPC] D15_APC_3: 0x0
10029 04:48:12.745350 INFO: [APUAPC] APC_CON: 0x4
10030 04:48:12.748227 INFO: [NOCDAPC] D0_APC_0: 0x0
10031 04:48:12.751644 INFO: [NOCDAPC] D0_APC_1: 0x0
10032 04:48:12.752118 INFO: [NOCDAPC] D1_APC_0: 0x0
10033 04:48:12.754875 INFO: [NOCDAPC] D1_APC_1: 0xfff
10034 04:48:12.758138 INFO: [NOCDAPC] D2_APC_0: 0x0
10035 04:48:12.761370 INFO: [NOCDAPC] D2_APC_1: 0xfff
10036 04:48:12.765097 INFO: [NOCDAPC] D3_APC_0: 0x0
10037 04:48:12.768059 INFO: [NOCDAPC] D3_APC_1: 0xfff
10038 04:48:12.771515 INFO: [NOCDAPC] D4_APC_0: 0x0
10039 04:48:12.774301 INFO: [NOCDAPC] D4_APC_1: 0xfff
10040 04:48:12.777921 INFO: [NOCDAPC] D5_APC_0: 0x0
10041 04:48:12.781182 INFO: [NOCDAPC] D5_APC_1: 0xfff
10042 04:48:12.784685 INFO: [NOCDAPC] D6_APC_0: 0x0
10043 04:48:12.788057 INFO: [NOCDAPC] D6_APC_1: 0xfff
10044 04:48:12.788641 INFO: [NOCDAPC] D7_APC_0: 0x0
10045 04:48:12.791425 INFO: [NOCDAPC] D7_APC_1: 0xfff
10046 04:48:12.794123 INFO: [NOCDAPC] D8_APC_0: 0x0
10047 04:48:12.797836 INFO: [NOCDAPC] D8_APC_1: 0xfff
10048 04:48:12.800852 INFO: [NOCDAPC] D9_APC_0: 0x0
10049 04:48:12.804322 INFO: [NOCDAPC] D9_APC_1: 0xfff
10050 04:48:12.807285 INFO: [NOCDAPC] D10_APC_0: 0x0
10051 04:48:12.810683 INFO: [NOCDAPC] D10_APC_1: 0xfff
10052 04:48:12.814511 INFO: [NOCDAPC] D11_APC_0: 0x0
10053 04:48:12.817642 INFO: [NOCDAPC] D11_APC_1: 0xfff
10054 04:48:12.820924 INFO: [NOCDAPC] D12_APC_0: 0x0
10055 04:48:12.823854 INFO: [NOCDAPC] D12_APC_1: 0xfff
10056 04:48:12.827273 INFO: [NOCDAPC] D13_APC_0: 0x0
10057 04:48:12.830642 INFO: [NOCDAPC] D13_APC_1: 0xfff
10058 04:48:12.831114 INFO: [NOCDAPC] D14_APC_0: 0x0
10059 04:48:12.833836 INFO: [NOCDAPC] D14_APC_1: 0xfff
10060 04:48:12.837562 INFO: [NOCDAPC] D15_APC_0: 0x0
10061 04:48:12.840377 INFO: [NOCDAPC] D15_APC_1: 0xfff
10062 04:48:12.843914 INFO: [NOCDAPC] APC_CON: 0x4
10063 04:48:12.847291 INFO: [APUAPC] set_apusys_apc done
10064 04:48:12.850514 INFO: [DEVAPC] devapc_init done
10065 04:48:12.854135 INFO: GICv3 without legacy support detected.
10066 04:48:12.860651 INFO: ARM GICv3 driver initialized in EL3
10067 04:48:12.863637 INFO: Maximum SPI INTID supported: 639
10068 04:48:12.867028 INFO: BL31: Initializing runtime services
10069 04:48:12.873658 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10070 04:48:12.874370 INFO: SPM: enable CPC mode
10071 04:48:12.880671 INFO: mcdi ready for mcusys-off-idle and system suspend
10072 04:48:12.884036 INFO: BL31: Preparing for EL3 exit to normal world
10073 04:48:12.890471 INFO: Entry point address = 0x80000000
10074 04:48:12.891047 INFO: SPSR = 0x8
10075 04:48:12.896440
10076 04:48:12.897009
10077 04:48:12.897384
10078 04:48:12.899830 Starting depthcharge on Spherion...
10079 04:48:12.900401
10080 04:48:12.900778 Wipe memory regions:
10081 04:48:12.901126
10082 04:48:12.903632 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10083 04:48:12.904180 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10084 04:48:12.904642 Setting prompt string to ['asurada:']
10085 04:48:12.905089 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10086 04:48:12.905798 [0x00000040000000, 0x00000054600000)
10087 04:48:13.025695
10088 04:48:13.026469 [0x00000054660000, 0x00000080000000)
10089 04:48:13.286208
10090 04:48:13.286804 [0x000000821a7280, 0x000000ffe64000)
10091 04:48:14.031000
10092 04:48:14.031581 [0x00000100000000, 0x00000240000000)
10093 04:48:15.921060
10094 04:48:15.923788 Initializing XHCI USB controller at 0x11200000.
10095 04:48:16.962226
10096 04:48:16.964944 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10097 04:48:16.965383
10098 04:48:16.965725
10099 04:48:16.966070
10100 04:48:16.967016 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10102 04:48:17.068190 asurada: tftpboot 192.168.201.1 12699845/tftp-deploy-2p2y6t07/kernel/image.itb 12699845/tftp-deploy-2p2y6t07/kernel/cmdline
10103 04:48:17.068733 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10104 04:48:17.069147 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10105 04:48:17.073827 tftpboot 192.168.201.1 12699845/tftp-deploy-2p2y6t07/kernel/image.ittp-deploy-2p2y6t07/kernel/cmdline
10106 04:48:17.074312
10107 04:48:17.074655 Waiting for link
10108 04:48:17.234389
10109 04:48:17.234964 R8152: Initializing
10110 04:48:17.235389
10111 04:48:17.237686 Version 9 (ocp_data = 6010)
10112 04:48:17.238412
10113 04:48:17.241051 R8152: Done initializing
10114 04:48:17.241637
10115 04:48:17.242064 Adding net device
10116 04:48:19.183505
10117 04:48:19.184012 done.
10118 04:48:19.184361
10119 04:48:19.184680 MAC: 00:e0:4c:72:2d:d6
10120 04:48:19.184988
10121 04:48:19.186185 Sending DHCP discover... done.
10122 04:48:19.186617
10123 04:48:29.516049 Waiting for reply... R8152: Bulk read error 0xffffffbf
10124 04:48:29.516634
10125 04:48:29.519606 Receive failed.
10126 04:48:29.520085
10127 04:48:29.520801 done.
10128 04:48:29.521180
10129 04:48:29.522788 Sending DHCP request... done.
10130 04:48:29.523249
10131 04:48:29.526150 Waiting for reply... done.
10132 04:48:29.526661
10133 04:48:29.527193 My ip is 192.168.201.21
10134 04:48:29.527559
10135 04:48:29.529386 The DHCP server ip is 192.168.201.1
10136 04:48:29.529846
10137 04:48:29.536313 TFTP server IP predefined by user: 192.168.201.1
10138 04:48:29.536889
10139 04:48:29.542598 Bootfile predefined by user: 12699845/tftp-deploy-2p2y6t07/kernel/image.itb
10140 04:48:29.543066
10141 04:48:29.546274 Sending tftp read request... done.
10142 04:48:29.546840
10143 04:48:29.551109 Waiting for the transfer...
10144 04:48:29.551691
10145 04:48:29.841609 00000000 ################################################################
10146 04:48:29.841762
10147 04:48:30.121008 00080000 ################################################################
10148 04:48:30.121144
10149 04:48:30.404143 00100000 ################################################################
10150 04:48:30.404268
10151 04:48:30.665932 00180000 ################################################################
10152 04:48:30.666071
10153 04:48:30.914895 00200000 ################################################################
10154 04:48:30.915018
10155 04:48:31.163386 00280000 ################################################################
10156 04:48:31.163512
10157 04:48:31.411849 00300000 ################################################################
10158 04:48:31.411970
10159 04:48:31.661056 00380000 ################################################################
10160 04:48:31.661181
10161 04:48:31.909848 00400000 ################################################################
10162 04:48:31.910028
10163 04:48:32.159691 00480000 ################################################################
10164 04:48:32.159820
10165 04:48:32.408608 00500000 ################################################################
10166 04:48:32.408758
10167 04:48:32.657078 00580000 ################################################################
10168 04:48:32.657206
10169 04:48:32.906428 00600000 ################################################################
10170 04:48:32.906552
10171 04:48:33.155056 00680000 ################################################################
10172 04:48:33.155186
10173 04:48:33.406883 00700000 ################################################################
10174 04:48:33.407012
10175 04:48:33.656114 00780000 ################################################################
10176 04:48:33.656240
10177 04:48:33.905251 00800000 ################################################################
10178 04:48:33.905375
10179 04:48:34.161879 00880000 ################################################################
10180 04:48:34.162030
10181 04:48:34.411163 00900000 ################################################################
10182 04:48:34.411293
10183 04:48:34.659993 00980000 ################################################################
10184 04:48:34.660126
10185 04:48:34.908389 00a00000 ################################################################
10186 04:48:34.908523
10187 04:48:35.162875 00a80000 ################################################################
10188 04:48:35.163008
10189 04:48:35.411857 00b00000 ################################################################
10190 04:48:35.411984
10191 04:48:35.660620 00b80000 ################################################################
10192 04:48:35.660748
10193 04:48:35.916208 00c00000 ################################################################
10194 04:48:35.916338
10195 04:48:36.167481 00c80000 ################################################################
10196 04:48:36.167613
10197 04:48:36.421591 00d00000 ################################################################
10198 04:48:36.421719
10199 04:48:36.680403 00d80000 ################################################################
10200 04:48:36.680536
10201 04:48:36.929904 00e00000 ################################################################
10202 04:48:36.930072
10203 04:48:37.178312 00e80000 ################################################################
10204 04:48:37.178442
10205 04:48:37.427115 00f00000 ################################################################
10206 04:48:37.427249
10207 04:48:37.676187 00f80000 ################################################################
10208 04:48:37.676316
10209 04:48:37.925318 01000000 ################################################################
10210 04:48:37.925443
10211 04:48:38.179966 01080000 ################################################################
10212 04:48:38.180102
10213 04:48:38.463976 01100000 ################################################################
10214 04:48:38.464113
10215 04:48:38.745087 01180000 ################################################################
10216 04:48:38.745243
10217 04:48:39.025057 01200000 ################################################################
10218 04:48:39.025179
10219 04:48:39.300602 01280000 ################################################################
10220 04:48:39.300761
10221 04:48:39.566314 01300000 ################################################################
10222 04:48:39.566485
10223 04:48:39.842128 01380000 ################################################################
10224 04:48:39.842287
10225 04:48:40.100072 01400000 ################################################################
10226 04:48:40.100243
10227 04:48:40.352569 01480000 ################################################################
10228 04:48:40.352719
10229 04:48:40.633117 01500000 ################################################################
10230 04:48:40.633244
10231 04:48:40.924923 01580000 ################################################################
10232 04:48:40.925073
10233 04:48:41.214511 01600000 ################################################################
10234 04:48:41.214638
10235 04:48:41.492230 01680000 ################################################################
10236 04:48:41.492385
10237 04:48:41.741445 01700000 ################################################################
10238 04:48:41.741599
10239 04:48:41.990775 01780000 ################################################################
10240 04:48:41.990925
10241 04:48:42.239785 01800000 ################################################################
10242 04:48:42.239936
10243 04:48:42.488399 01880000 ################################################################
10244 04:48:42.488522
10245 04:48:42.737632 01900000 ################################################################
10246 04:48:42.737783
10247 04:48:42.986738 01980000 ################################################################
10248 04:48:42.986887
10249 04:48:43.235774 01a00000 ################################################################
10250 04:48:43.235928
10251 04:48:43.485195 01a80000 ################################################################
10252 04:48:43.485358
10253 04:48:43.739699 01b00000 ################################################################
10254 04:48:43.739849
10255 04:48:43.992922 01b80000 ################################################################
10256 04:48:43.993069
10257 04:48:44.257244 01c00000 ################################################################
10258 04:48:44.257371
10259 04:48:44.507691 01c80000 ################################################################
10260 04:48:44.507823
10261 04:48:44.725556 01d00000 ######################################################### done.
10262 04:48:44.728658
10263 04:48:44.728756 The bootfile was 30873090 bytes long.
10264 04:48:44.732325
10265 04:48:44.732430 Sending tftp read request... done.
10266 04:48:44.732508
10267 04:48:44.735558 Waiting for the transfer...
10268 04:48:44.735655
10269 04:48:44.738811 00000000 # done.
10270 04:48:44.738917
10271 04:48:44.745804 Command line loaded dynamically from TFTP file: 12699845/tftp-deploy-2p2y6t07/kernel/cmdline
10272 04:48:44.746003
10273 04:48:44.768855 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12699845/extract-nfsrootfs-6vzpzxd0,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10274 04:48:44.769149
10275 04:48:44.769313 Loading FIT.
10276 04:48:44.769465
10277 04:48:44.772379 Image ramdisk-1 has 18775269 bytes.
10278 04:48:44.772728
10279 04:48:44.775779 Image fdt-1 has 47278 bytes.
10280 04:48:44.776124
10281 04:48:44.778854 Image kernel-1 has 12048508 bytes.
10282 04:48:44.779269
10283 04:48:44.785662 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10284 04:48:44.786259
10285 04:48:44.805932 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10286 04:48:44.806505
10287 04:48:44.809387 Choosing best match conf-1 for compat google,spherion-rev2.
10288 04:48:44.814149
10289 04:48:44.819137 Connected to device vid:did:rid of 1ae0:0028:00
10290 04:48:44.827150
10291 04:48:44.830305 tpm_get_response: command 0x17b, return code 0x0
10292 04:48:44.830704
10293 04:48:44.833782 ec_init: CrosEC protocol v3 supported (256, 248)
10294 04:48:44.838731
10295 04:48:44.842381 tpm_cleanup: add release locality here.
10296 04:48:44.842903
10297 04:48:44.843222 Shutting down all USB controllers.
10298 04:48:44.845313
10299 04:48:44.845741 Removing current net device
10300 04:48:44.846192
10301 04:48:44.851935 Exiting depthcharge with code 4 at timestamp: 61234556
10302 04:48:44.852404
10303 04:48:44.855448 LZMA decompressing kernel-1 to 0x821a6718
10304 04:48:44.855936
10305 04:48:44.858542 LZMA decompressing kernel-1 to 0x40000000
10306 04:48:46.357775
10307 04:48:46.358395 jumping to kernel
10308 04:48:46.360626 end: 2.2.4 bootloader-commands (duration 00:00:33) [common]
10309 04:48:46.361200 start: 2.2.5 auto-login-action (timeout 00:03:52) [common]
10310 04:48:46.361623 Setting prompt string to ['Linux version [0-9]']
10311 04:48:46.362049 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10312 04:48:46.362445 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10313 04:48:46.439396
10314 04:48:46.442796 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10315 04:48:46.446401 start: 2.2.5.1 login-action (timeout 00:03:52) [common]
10316 04:48:46.446927 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10317 04:48:46.447349 Setting prompt string to []
10318 04:48:46.447812 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10319 04:48:46.448215 Using line separator: #'\n'#
10320 04:48:46.448561 No login prompt set.
10321 04:48:46.449006 Parsing kernel messages
10322 04:48:46.449375 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10323 04:48:46.450043 [login-action] Waiting for messages, (timeout 00:03:52)
10324 04:48:46.466373 [ 0.000000] Linux version 6.1.75-cip14-rt8 (KernelCI@build-j97480-arm64-gcc-10-defconfig-arm64-chromebook-6n26j) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Feb 4 04:24:19 UTC 2024
10325 04:48:46.469623 [ 0.000000] random: crng init done
10326 04:48:46.476343 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10327 04:48:46.479365 [ 0.000000] efi: UEFI not found.
10328 04:48:46.486031 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10329 04:48:46.492414 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10330 04:48:46.502458 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10331 04:48:46.512531 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10332 04:48:46.519189 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10333 04:48:46.525769 [ 0.000000] printk: bootconsole [mtk8250] enabled
10334 04:48:46.532133 [ 0.000000] NUMA: No NUMA configuration found
10335 04:48:46.539155 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10336 04:48:46.542420 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10337 04:48:46.545439 [ 0.000000] Zone ranges:
10338 04:48:46.552315 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10339 04:48:46.555487 [ 0.000000] DMA32 empty
10340 04:48:46.562133 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10341 04:48:46.565275 [ 0.000000] Movable zone start for each node
10342 04:48:46.568926 [ 0.000000] Early memory node ranges
10343 04:48:46.575589 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10344 04:48:46.582273 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10345 04:48:46.588763 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10346 04:48:46.595596 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10347 04:48:46.598818 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10348 04:48:46.608858 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10349 04:48:46.664151 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10350 04:48:46.671337 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10351 04:48:46.677976 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10352 04:48:46.681056 [ 0.000000] psci: probing for conduit method from DT.
10353 04:48:46.687484 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10354 04:48:46.690818 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10355 04:48:46.697207 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10356 04:48:46.701077 [ 0.000000] psci: SMC Calling Convention v1.2
10357 04:48:46.707451 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10358 04:48:46.710735 [ 0.000000] Detected VIPT I-cache on CPU0
10359 04:48:46.717545 [ 0.000000] CPU features: detected: GIC system register CPU interface
10360 04:48:46.724540 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10361 04:48:46.730535 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10362 04:48:46.737587 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10363 04:48:46.743950 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10364 04:48:46.753685 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10365 04:48:46.757304 [ 0.000000] alternatives: applying boot alternatives
10366 04:48:46.763718 [ 0.000000] Fallback order for Node 0: 0
10367 04:48:46.770615 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10368 04:48:46.773899 [ 0.000000] Policy zone: Normal
10369 04:48:46.797266 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12699845/extract-nfsrootfs-6vzpzxd0,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10370 04:48:46.806990 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10371 04:48:46.816760 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10372 04:48:46.826667 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10373 04:48:46.833528 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10374 04:48:46.836463 <6>[ 0.000000] software IO TLB: area num 8.
10375 04:48:46.892740 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10376 04:48:47.042202 <6>[ 0.000000] Memory: 7948856K/8385536K available (18048K kernel code, 4116K rwdata, 19608K rodata, 8448K init, 616K bss, 403912K reserved, 32768K cma-reserved)
10377 04:48:47.048413 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10378 04:48:47.055090 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10379 04:48:47.058760 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10380 04:48:47.065553 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10381 04:48:47.071815 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10382 04:48:47.075520 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10383 04:48:47.085691 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10384 04:48:47.092346 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10385 04:48:47.095714 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10386 04:48:47.103158 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10387 04:48:47.106369 <6>[ 0.000000] GICv3: 608 SPIs implemented
10388 04:48:47.113158 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10389 04:48:47.116111 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10390 04:48:47.119559 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10391 04:48:47.129580 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10392 04:48:47.139328 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10393 04:48:47.152673 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10394 04:48:47.159108 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10395 04:48:47.169042 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10396 04:48:47.182373 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10397 04:48:47.188550 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10398 04:48:47.195292 <6>[ 0.009235] Console: colour dummy device 80x25
10399 04:48:47.205421 <6>[ 0.013959] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10400 04:48:47.212382 <6>[ 0.024466] pid_max: default: 32768 minimum: 301
10401 04:48:47.215066 <6>[ 0.029367] LSM: Security Framework initializing
10402 04:48:47.222118 <6>[ 0.034307] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10403 04:48:47.232581 <6>[ 0.042122] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10404 04:48:47.238535 <6>[ 0.051534] cblist_init_generic: Setting adjustable number of callback queues.
10405 04:48:47.245031 <6>[ 0.059023] cblist_init_generic: Setting shift to 3 and lim to 1.
10406 04:48:47.254926 <6>[ 0.065364] cblist_init_generic: Setting adjustable number of callback queues.
10407 04:48:47.261578 <6>[ 0.072792] cblist_init_generic: Setting shift to 3 and lim to 1.
10408 04:48:47.264797 <6>[ 0.079262] rcu: Hierarchical SRCU implementation.
10409 04:48:47.271574 <6>[ 0.079264] rcu: Max phase no-delay instances is 1000.
10410 04:48:47.278555 <6>[ 0.079287] printk: bootconsole [mtk8250] printing thread started
10411 04:48:47.284940 <6>[ 0.097617] EFI services will not be available.
10412 04:48:47.288282 <6>[ 0.097815] smp: Bringing up secondary CPUs ...
10413 04:48:47.291531 <6>[ 0.098127] Detected VIPT I-cache on CPU1
10414 04:48:47.298275 <6>[ 0.098195] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10415 04:48:47.308011 <6>[ 0.098227] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10416 04:48:47.316802 <6>[ 0.126074] Detected VIPT I-cache on CPU2
10417 04:48:47.323474 <6>[ 0.126122] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10418 04:48:47.330375 <6>[ 0.126138] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10419 04:48:47.336943 <6>[ 0.126391] Detected VIPT I-cache on CPU3
10420 04:48:47.343573 <6>[ 0.126438] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10421 04:48:47.350214 <6>[ 0.126452] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10422 04:48:47.353571 <6>[ 0.126763] CPU features: detected: Spectre-v4
10423 04:48:47.359787 <6>[ 0.126770] CPU features: detected: Spectre-BHB
10424 04:48:47.363378 <6>[ 0.126775] Detected PIPT I-cache on CPU4
10425 04:48:47.370169 <6>[ 0.126835] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10426 04:48:47.376819 <6>[ 0.126852] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10427 04:48:47.383606 <6>[ 0.127141] Detected PIPT I-cache on CPU5
10428 04:48:47.390480 <6>[ 0.127201] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10429 04:48:47.396590 <6>[ 0.127218] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10430 04:48:47.400012 <6>[ 0.127490] Detected PIPT I-cache on CPU6
10431 04:48:47.406218 <6>[ 0.127552] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10432 04:48:47.413007 <6>[ 0.127568] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10433 04:48:47.421203 <6>[ 0.127857] Detected PIPT I-cache on CPU7
10434 04:48:47.427987 <6>[ 0.127921] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10435 04:48:47.434458 <6>[ 0.127937] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10436 04:48:47.437672 <6>[ 0.127982] smp: Brought up 1 node, 8 CPUs
10437 04:48:47.444267 <6>[ 0.127987] SMP: Total of 8 processors activated.
10438 04:48:47.447918 <6>[ 0.127989] CPU features: detected: 32-bit EL0 Support
10439 04:48:47.457579 <6>[ 0.127992] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10440 04:48:47.464185 <6>[ 0.127994] CPU features: detected: Common not Private translations
10441 04:48:47.470745 <6>[ 0.127996] CPU features: detected: CRC32 instructions
10442 04:48:47.477542 <6>[ 0.127999] CPU features: detected: RCpc load-acquire (LDAPR)
10443 04:48:47.480590 <6>[ 0.128000] CPU features: detected: LSE atomic instructions
10444 04:48:47.487483 <6>[ 0.128002] CPU features: detected: Privileged Access Never
10445 04:48:47.493828 <6>[ 0.128003] CPU features: detected: RAS Extension Support
10446 04:48:47.500642 <6>[ 0.128006] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10447 04:48:47.504280 <6>[ 0.128068] CPU: All CPU(s) started at EL2
10448 04:48:47.510348 <6>[ 0.128070] alternatives: applying system-wide alternatives
10449 04:48:47.513930 <6>[ 0.141170] devtmpfs: initialized
10450 04:48:47.523880 <6>[ 0.147382] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10451 04:48:47.530472 <6>[ 0.147397] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10452 04:48:47.563011 �⥕�郊�����Bzɑ����b���ª���ѕͱ�b����ɥ;R�<6>[ 0.37<4690] printk: console [ttyS0] printing thread started
10453 04:48:47.566299 6<6>[ 0.374725] printk: console [ttyS0] enabled
10454 04:48:47.576434 >[ 0.247541] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10455 04:48:47.582983 <6>[ 0.247620] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10456 04:48:47.589625 <6>[ 0.374728] printk: bootconsole [mtk8250] disabled
10457 04:48:47.596176 <6>[ 0.401784] printk: bootconsole [mtk8250] printing thread stopped
10458 04:48:47.599296 <6>[ 0.403155] SuperH (H)SCI(F) driver initialized
10459 04:48:47.606111 <6>[ 0.403663] msm_serial: driver initialized
10460 04:48:47.612945 <6>[ 0.408319] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10461 04:48:47.622604 <6>[ 0.408365] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10462 04:48:47.628876 <6>[ 0.408400] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10463 04:48:47.644558 <6>[ 0.408440] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10464 04:48:47.657732 <6>[ 0.408463] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10465 04:48:47.658374 <6>[ 0.408494] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10466 04:48:47.673601 <6>[ 0.408528] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10467 04:48:47.678907 <6>[ 0.408691] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10468 04:48:47.687478 <6>[ 0.408721] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10469 04:48:47.688074 <6>[ 0.418619] loop: module loaded
10470 04:48:47.697391 <6>[ 0.421141] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10471 04:48:47.700367 <4>[ 0.437982] mtk-pmic-keys: Failed to locate of_node [id: -1]
10472 04:48:47.700958 <6>[ 0.438874] megasas: 07.719.03.00-rc1
10473 04:48:47.707174 <6>[ 0.451007] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10474 04:48:47.714052 <6>[ 0.451194] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10475 04:48:47.720354 <6>[ 0.462973] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10476 04:48:47.730498 <6>[ 0.516088] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10477 04:48:48.257413 <6>[ 1.067941] Freeing initrd memory: 18332K
10478 04:48:48.263860 <6>[ 1.075157] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10479 04:48:48.267420 <6>[ 1.080006] tun: Universal TUN/TAP device driver, 1.6
10480 04:48:48.270959 <6>[ 1.080780] thunder_xcv, ver 1.0
10481 04:48:48.273614 <6>[ 1.080798] thunder_bgx, ver 1.0
10482 04:48:48.277202 <6>[ 1.080811] nicpf, ver 1.0
10483 04:48:48.287096 <6>[ 1.081874] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10484 04:48:48.290780 <6>[ 1.081877] hns3: Copyright (c) 2017 Huawei Corporation.
10485 04:48:48.294019 <6>[ 1.081903] hclge is initializing
10486 04:48:48.300692 <6>[ 1.081917] e1000: Intel(R) PRO/1000 Network Driver
10487 04:48:48.307522 <6>[ 1.081919] e1000: Copyright (c) 1999-2006 Intel Corporation.
10488 04:48:48.311511 <6>[ 1.081935] e1000e: Intel(R) PRO/1000 Network Driver
10489 04:48:48.318125 <6>[ 1.081937] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10490 04:48:48.322105 <6>[ 1.081954] igb: Intel(R) Gigabit Ethernet Network Driver
10491 04:48:48.329062 <6>[ 1.081956] igb: Copyright (c) 2007-2014 Intel Corporation.
10492 04:48:48.335526 <6>[ 1.081970] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10493 04:48:48.342306 <6>[ 1.081973] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10494 04:48:48.346054 <6>[ 1.082265] sky2: driver version 1.30
10495 04:48:48.349188 <6>[ 1.083335] VFIO - User Level meta-driver version: 0.3
10496 04:48:48.355980 <6>[ 1.086165] usbcore: registered new interface driver usb-storage
10497 04:48:48.362962 <6>[ 1.086346] usbcore: registered new device driver onboard-usb-hub
10498 04:48:48.369160 <6>[ 1.089195] mt6397-rtc mt6359-rtc: registered as rtc0
10499 04:48:48.376213 <6>[ 1.089353] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-04T04:48:11 UTC (1707022091)
10500 04:48:48.382965 <6>[ 1.089968] i2c_dev: i2c /dev entries driver
10501 04:48:48.389320 <6>[ 1.097157] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10502 04:48:48.396071 <6>[ 1.112150] cpu cpu0: EM: created perf domain
10503 04:48:48.399307 <6>[ 1.112492] cpu cpu4: EM: created perf domain
10504 04:48:48.406552 <6>[ 1.114133] sdhci: Secure Digital Host Controller Interface driver
10505 04:48:48.409903 <6>[ 1.114134] sdhci: Copyright(c) Pierre Ossman
10506 04:48:48.416194 <6>[ 1.114489] Synopsys Designware Multimedia Card Interface Driver
10507 04:48:48.422664 <6>[ 1.114860] sdhci-pltfm: SDHCI platform and OF driver helper
10508 04:48:48.426320 <6>[ 1.119403] mmc0: CQHCI version 5.10
10509 04:48:48.433063 <6>[ 1.125261] ledtrig-cpu: registered to indicate activity on CPUs
10510 04:48:48.439728 <6>[ 1.126181] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10511 04:48:48.445800 <6>[ 1.126467] usbcore: registered new interface driver usbhid
10512 04:48:48.449042 <6>[ 1.126468] usbhid: USB HID core driver
10513 04:48:48.455990 <6>[ 1.126583] spi_master spi0: will run message pump with realtime priority
10514 04:48:48.469563 <6>[ 1.159688] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10515 04:48:48.482558 <6>[ 1.162474] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10516 04:48:48.489544 <6>[ 1.163389] cros-ec-spi spi0.0: Chrome EC device registered
10517 04:48:48.496196 <6>[ 1.175621] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10518 04:48:48.502712 <6>[ 1.176562] NET: Registered PF_PACKET protocol family
10519 04:48:48.506158 <6>[ 1.176643] 9pnet: Installing 9P2000 support
10520 04:48:48.512698 <5>[ 1.176675] Key type dns_resolver registered
10521 04:48:48.516575 <6>[ 1.177069] registered taskstats version 1
10522 04:48:48.522764 <5>[ 1.177086] Loading compiled-in X.509 certificates
10523 04:48:48.532442 <4>[ 1.192233] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10524 04:48:48.542457 <4>[ 1.192407] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10525 04:48:48.549425 <3>[ 1.192425] debugfs: File 'uA_load' in directory '/' already present!
10526 04:48:48.556037 <3>[ 1.192437] debugfs: File 'min_uV' in directory '/' already present!
10527 04:48:48.562629 <3>[ 1.192442] debugfs: File 'max_uV' in directory '/' already present!
10528 04:48:48.569411 <3>[ 1.192446] debugfs: File 'constraint_flags' in directory '/' already present!
10529 04:48:48.579394 <3>[ 1.194634] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10530 04:48:48.582851 <6>[ 1.202148] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10531 04:48:48.589488 <6>[ 1.202705] xhci-mtk 11200000.usb: xHCI Host Controller
10532 04:48:48.598854 <6>[ 1.202726] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10533 04:48:48.605697 <6>[ 1.202942] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10534 04:48:48.612066 <6>[ 1.202988] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10535 04:48:48.618474 <6>[ 1.203077] xhci-mtk 11200000.usb: xHCI Host Controller
10536 04:48:48.625763 <6>[ 1.203084] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10537 04:48:48.631987 <6>[ 1.203096] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10538 04:48:48.639125 <6>[ 1.203531] hub 1-0:1.0: USB hub found
10539 04:48:48.641712 <6>[ 1.203556] hub 1-0:1.0: 1 port detected
10540 04:48:48.648727 <6>[ 1.203801] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10541 04:48:48.655165 <6>[ 1.204073] hub 2-0:1.0: USB hub found
10542 04:48:48.658379 <6>[ 1.204093] hub 2-0:1.0: 1 port detected
10543 04:48:48.662388 <6>[ 1.207159] mtk-msdc 11f70000.mmc: Got CD GPIO
10544 04:48:48.668502 <6>[ 1.213971] mmc0: Command Queue Engine enabled
10545 04:48:48.675419 <6>[ 1.213981] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10546 04:48:48.678704 <6>[ 1.214577] mmcblk0: mmc0:0001 DA4128 116 GiB
10547 04:48:48.685322 <6>[ 1.217881] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10548 04:48:48.688443 <6>[ 1.218843] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10549 04:48:48.694714 <6>[ 1.219559] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10550 04:48:48.701726 <6>[ 1.220374] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10551 04:48:48.708257 <6>[ 1.224256] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10552 04:48:48.718341 <6>[ 1.224262] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10553 04:48:48.724806 <4>[ 1.224413] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10554 04:48:48.734694 <6>[ 1.225042] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10555 04:48:48.741503 <6>[ 1.225045] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10556 04:48:48.750910 <6>[ 1.225164] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10557 04:48:48.757657 <6>[ 1.225175] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10558 04:48:48.764365 <6>[ 1.225179] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10559 04:48:48.774036 <6>[ 1.225185] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10560 04:48:48.784270 <6>[ 1.226621] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10561 04:48:48.791213 <6>[ 1.226639] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10562 04:48:48.800790 <6>[ 1.226646] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10563 04:48:48.807818 <6>[ 1.226653] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10564 04:48:48.817681 <6>[ 1.226659] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10565 04:48:48.824453 <6>[ 1.226666] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10566 04:48:48.834023 <6>[ 1.226672] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10567 04:48:48.841356 <6>[ 1.226679] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10568 04:48:48.850896 <6>[ 1.226685] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10569 04:48:48.857312 <6>[ 1.226692] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10570 04:48:48.867038 <6>[ 1.226699] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10571 04:48:48.873927 <6>[ 1.226705] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10572 04:48:48.883749 <6>[ 1.226711] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10573 04:48:48.890278 <6>[ 1.226718] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10574 04:48:48.900505 <6>[ 1.226724] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10575 04:48:48.907150 <6>[ 1.227219] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10576 04:48:48.913728 <6>[ 1.228127] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10577 04:48:48.920383 <6>[ 1.228688] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10578 04:48:48.926778 <6>[ 1.229305] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10579 04:48:48.933313 <6>[ 1.229945] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10580 04:48:48.943611 <6>[ 1.230137] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10581 04:48:48.949723 <6>[ 1.230152] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10582 04:48:48.960081 <6>[ 1.230158] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10583 04:48:48.969819 <6>[ 1.230164] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10584 04:48:48.980166 <6>[ 1.230170] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10585 04:48:48.989515 <6>[ 1.230176] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10586 04:48:48.996566 <6>[ 1.230181] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10587 04:48:49.006031 <6>[ 1.230186] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10588 04:48:49.016366 <6>[ 1.230191] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10589 04:48:49.026401 <6>[ 1.230197] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10590 04:48:49.036100 <6>[ 1.230202] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10591 04:48:49.046385 <6>[ 1.230674] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10592 04:48:49.049198 <6>[ 1.240084] Trying to probe devices needed for running init ...
10593 04:48:49.059021 <6>[ 1.627741] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10594 04:48:49.062583 <6>[ 1.791809] hub 1-1:1.0: USB hub found
10595 04:48:49.066130 <6>[ 1.792187] hub 1-1:1.0: 4 ports detected
10596 04:48:49.069361 <6>[ 1.795421] hub 1-1:1.0: USB hub found
10597 04:48:49.075521 <6>[ 1.795819] hub 1-1:1.0: 4 ports detected
10598 04:48:49.108536 <6>[ 1.916142] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10599 04:48:49.129087 <6>[ 1.941293] hub 2-1:1.0: USB hub found
10600 04:48:49.132343 <6>[ 1.941709] hub 2-1:1.0: 3 ports detected
10601 04:48:49.135833 <6>[ 1.944955] hub 2-1:1.0: USB hub found
10602 04:48:49.139052 <6>[ 1.945308] hub 2-1:1.0: 3 ports detected
10603 04:48:49.300777 <6>[ 2.107866] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10604 04:48:49.421523 <6>[ 2.234949] hub 1-1.4:1.0: USB hub found
10605 04:48:49.424907 <6>[ 2.235305] hub 1-1.4:1.0: 2 ports detected
10606 04:48:49.428224 <6>[ 2.238818] hub 1-1.4:1.0: USB hub found
10607 04:48:49.434365 <6>[ 2.239180] hub 1-1.4:1.0: 2 ports detected
10608 04:48:49.504437 <6>[ 2.311993] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10609 04:48:49.720593 <6>[ 2.527868] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10610 04:48:49.904447 <6>[ 2.711876] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10611 04:49:00.720796 <6>[ 13.536866] ALSA device list:
10612 04:49:00.727547 <6>[ 13.536885] No soundcards found.
10613 04:49:00.731107 <6>[ 13.540545] Freeing unused kernel memory: 8448K
10614 04:49:00.734277 <6>[ 13.540711] Run /init as init process
10615 04:49:00.737177 Loading, please wait...
10616 04:49:00.764682 Starting systemd-udevd version 252.19-1~deb12u1
10617 04:49:00.963654 <6>[ 13.775296] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10618 04:49:00.975508 <3>[ 13.785765] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10619 04:49:00.981931 <3>[ 13.785786] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10620 04:49:00.991684 <3>[ 13.785794] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10621 04:49:00.998244 <3>[ 13.788882] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10622 04:49:01.008682 <3>[ 13.788891] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10623 04:49:01.014598 <3>[ 13.788895] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10624 04:49:01.024731 <3>[ 13.788898] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10625 04:49:01.031157 <3>[ 13.788901] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10626 04:49:01.037722 <6>[ 13.788923] remoteproc remoteproc0: scp is available
10627 04:49:01.041330 <6>[ 13.788979] remoteproc remoteproc0: powering up scp
10628 04:49:01.051158 <6>[ 13.788983] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10629 04:49:01.054731 <6>[ 13.789000] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10630 04:49:01.064268 <3>[ 13.791680] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10631 04:49:01.072257 <3>[ 13.791713] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10632 04:49:01.081680 <3>[ 13.791716] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10633 04:49:01.088832 <3>[ 13.791719] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10634 04:49:01.095507 <3>[ 13.791749] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10635 04:49:01.105458 <3>[ 13.791752] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10636 04:49:01.112375 <3>[ 13.791754] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10637 04:49:01.121915 <3>[ 13.791757] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10638 04:49:01.128904 <3>[ 13.791759] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10639 04:49:01.135191 <3>[ 13.791772] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10640 04:49:01.145781 <6>[ 13.792118] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10641 04:49:01.152397 <6>[ 13.792142] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10642 04:49:01.162272 <6>[ 13.792154] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10643 04:49:01.168760 <4>[ 13.820310] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10644 04:49:01.172002 <6>[ 13.820402] mc: Linux media interface: v0.10
10645 04:49:01.182094 <4>[ 13.821617] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10646 04:49:01.188604 <6>[ 13.850250] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10647 04:49:01.194928 <6>[ 13.852863] videodev: Linux video capture interface: v2.00
10648 04:49:01.201556 <6>[ 13.857695] usbcore: registered new device driver r8152-cfgselector
10649 04:49:01.208126 <4>[ 13.877233] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10650 04:49:01.215150 <4>[ 13.877233] Fallback method does not support PEC.
10651 04:49:01.224853 <3>[ 13.894070] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10652 04:49:01.231212 <6>[ 13.916711] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10653 04:49:01.238137 <6>[ 13.916719] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10654 04:49:01.244508 <6>[ 13.916721] remoteproc remoteproc0: remote processor scp is now up
10655 04:49:01.254605 <3>[ 13.916738] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10656 04:49:01.261423 <6>[ 13.916978] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10657 04:49:01.267718 <6>[ 13.916984] pci_bus 0000:00: root bus resource [bus 00-ff]
10658 04:49:01.274356 <6>[ 13.916989] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10659 04:49:01.284231 <6>[ 13.916994] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10660 04:49:01.290807 <6>[ 13.917021] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10661 04:49:01.297581 <6>[ 13.917039] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10662 04:49:01.300979 <6>[ 13.917110] pci 0000:00:00.0: supports D1 D2
10663 04:49:01.307364 <6>[ 13.917114] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10664 04:49:01.317606 <6>[ 13.918568] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10665 04:49:01.323710 <6>[ 13.918673] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10666 04:49:01.330540 <6>[ 13.918703] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10667 04:49:01.337060 <6>[ 13.918722] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10668 04:49:01.347161 <6>[ 13.918740] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10669 04:49:01.350592 <6>[ 13.918852] pci 0000:01:00.0: supports D1 D2
10670 04:49:01.356856 <6>[ 13.918855] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10671 04:49:01.366703 <6>[ 13.927872] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10672 04:49:01.373750 <6>[ 13.931695] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10673 04:49:01.380227 <6>[ 13.931724] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10674 04:49:01.390092 <6>[ 13.931731] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10675 04:49:01.397021 <6>[ 13.931743] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10676 04:49:01.406557 Begin: Loading e<6>[ 13.931759] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10677 04:49:01.413202 <6>[ 13.931775] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10678 04:49:01.419812 <6>[ 13.931791] pci 0000:00:00.0: PCI bridge to [bus 01]
10679 04:49:01.426519 <6>[ 13.931798] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10680 04:49:01.432862 <6>[ 13.931909] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10681 04:49:01.439690 <6>[ 13.932777] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10682 04:49:01.446256 <6>[ 13.933111] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10683 04:49:01.453268 <6>[ 13.933969] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10684 04:49:01.463208 <6>[ 13.934822] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10685 04:49:01.470041 <6>[ 13.939969] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10686 04:49:01.479665 <6>[ 13.960395] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10687 04:49:01.489548 <6>[ 13.960840] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10688 04:49:01.499475 <4>[ 13.968693] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10689 04:49:01.506104 <4>[ 13.968699] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10690 04:49:01.515653 <5>[ 13.984628] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10691 04:49:01.519450 <6>[ 13.994700] Bluetooth: Core ver 2.22
10692 04:49:01.525868 <6>[ 13.994738] NET: Registered PF_BLUETOOTH protocol family
10693 04:49:01.532463 <6>[ 13.994739] Bluetooth: HCI device and connection manager initialized
10694 04:49:01.535899 <6>[ 13.994746] Bluetooth: HCI socket layer initialized
10695 04:49:01.542405 <6>[ 13.994749] Bluetooth: L2CAP socket layer initialized
10696 04:49:01.545804 <6>[ 13.994753] Bluetooth: SCO socket layer initialized
10697 04:49:01.552426 <5>[ 13.999326] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10698 04:49:01.562346 <5>[ 13.999842] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10699 04:49:01.572141 <4>[ 13.999912] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10700 04:49:01.575241 <6>[ 13.999920] cfg80211: failed to load regulatory.db
10701 04:49:01.581793 <6>[ 14.015507] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10702 04:49:01.595348 <6>[ 14.016609] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10703 04:49:01.602115 <6>[ 14.016690] usbcore: registered new interface driver uvcvideo
10704 04:49:01.605387 <6>[ 14.027748] r8152 2-1.3:1.0 eth0: v1.12.13
10705 04:49:01.611592 <6>[ 14.027811] usbcore: registered new interface driver r8152
10706 04:49:01.618489 <6>[ 14.059913] usbcore: registered new interface driver cdc_ether
10707 04:49:01.621550 <6>[ 14.060041] usbcore: registered new interface driver btusb
10708 04:49:01.628241 <6>[ 14.060087] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10709 04:49:01.641485 <4>[ 14.061256] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10710 04:49:01.645114 <3>[ 14.061261] Bluetooth: hci0: Failed to load firmware file (-2)
10711 04:49:01.651297 <3>[ 14.061262] Bluetooth: hci0: Failed to set up firmware (-2)
10712 04:49:01.661683 <4>[ 14.061264] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10713 04:49:01.668058 <6>[ 14.074862] usbcore: registered new interface driver r8153_ecm
10714 04:49:01.674462 <6>[ 14.082497] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10715 04:49:01.681045 <6>[ 14.095146] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10716 04:49:01.687906 <6>[ 14.095217] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10717 04:49:01.694620 <6>[ 14.111672] mt7921e 0000:01:00.0: ASIC revision: 79610010
10718 04:49:01.701142 <6>[ 14.201286] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10719 04:49:01.704091 <6>[ 14.201286]
10720 04:49:01.710812 <6>[ 14.460739] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10721 04:49:01.714527 ssential drivers ... done.
10722 04:49:01.720982 Begin: Running /scripts/init-premount ... done.
10723 04:49:01.727285 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10724 04:49:01.734405 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10725 04:49:01.737338 Device /sys/class/net/enx00e04c722dd6 found
10726 04:49:01.740653 done.
10727 04:49:01.747193 Begin: Waiting up to 180 secs for any network device to become available ... done.
10728 04:49:01.754287 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10729 04:49:02.527902 <6>[ 15.339717] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10730 04:49:02.773495 IP-Config: no response after 2 secs - giving up
10731 04:49:02.779867 <6>[ 15.592484] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10732 04:49:02.811987 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:7b mtu 1500 DHCP
10733 04:49:03.511705 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10734 04:49:03.518217 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10735 04:49:03.525492 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10736 04:49:03.531539 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10737 04:49:03.538363 host : mt8192-asurada-spherion-r0-cbg-1
10738 04:49:03.545026 domain : lava-rack
10739 04:49:03.548366 rootserver: 192.168.201.1 rootpath:
10740 04:49:03.551425 filename :
10741 04:49:03.661256 done.
10742 04:49:03.667932 Begin: Running /scripts/nfs-bottom ... done.
10743 04:49:03.682777 Begin: Running /scripts/init-bottom ... done.
10744 04:49:04.999128 <6>[ 17.814294] NET: Registered PF_INET6 protocol family
10745 04:49:05.002593 <6>[ 17.816424] Segment Routing with IPv6
10746 04:49:05.009075 <6>[ 17.816436] In-situ OAM (IOAM) with IPv6
10747 04:49:05.157913 <30>[ 17.947347] systemd[1]: systemd 252.19-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10748 04:49:05.164972 <30>[ 17.947386] systemd[1]: Detected architecture arm64.
10749 04:49:05.173507
10750 04:49:05.176674 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10751 04:49:05.177152
10752 04:49:05.203276 <30>[ 18.016852] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10753 04:49:06.246444 <30>[ 19.059397] systemd[1]: Queued start job for default target graphical.target.
10754 04:49:06.279772 [[0;32m OK [0m] Created slic<30>[ 19.088986] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10755 04:49:06.283281 e [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10756 04:49:06.308268 [[0;32m OK [0m] Created slic<30>[ 19.117644] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10757 04:49:06.311621 e [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10758 04:49:06.335997 [[0;32m OK [0m] Created slic<30>[ 19.145568] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10759 04:49:06.342562 e [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10760 04:49:06.360598 [[0;32m OK [0m] Created slic<30>[ 19.173277] systemd[1]: Created slice user.slice - User and Session Slice.
10761 04:49:06.367042 e [0;1;39muser.slice[0m - User and Session Slice.
10762 04:49:06.394067 [[0;32m OK [0m] Started [0;1;39msystemd-ask<30>[ 19.200175] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10763 04:49:06.397460 -passwo…quests to Console Directory Watch.
10764 04:49:06.421925 [[0;32m OK [0m] Started [0;1;39msystemd-ask<30>[ 19.228099] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10765 04:49:06.425131 -passwo… Requests to Wall Directory Watch.
10766 04:49:06.460470 [[0;32m OK [0m] Reached target [0;1;39mcryp<30>[ 19.256426] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10767 04:49:06.470246 tsetup.…get[0<30>[ 19.256723] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10768 04:49:06.470873 m - Local Encrypted Volumes.
10769 04:49:06.498525 [[0;32m OK [0m] Reached target [0;1;39minte<30>[ 19.304205] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10770 04:49:06.501388 grityse…Local Integrity Protected Volumes.
10771 04:49:06.522761 [[0;32m OK [0m] Reached target [0;1;39mpath<30>[ 19.331951] systemd[1]: Reached target paths.target - Path Units.
10772 04:49:06.523355 s.target[0m - Path Units.
10773 04:49:06.546854 [[0;32m OK [0m] Reached target [0;1;39mremo<30>[ 19.356264] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10774 04:49:06.549908 te-fs.target[0m - Remote File Systems.
10775 04:49:06.570517 [[0;32m OK [0m] Reached target [0;1;39mslic<30>[ 19.379862] systemd[1]: Reached target slices.target - Slice Units.
10776 04:49:06.573687 es.target[0m - Slice Units.
10777 04:49:06.594739 [[0;32m OK [0m] Reached target [0;1;39mswap<30>[ 19.404288] systemd[1]: Reached target swap.target - Swaps.
10778 04:49:06.595310 .target[0m - Swaps.
10779 04:49:06.619361 [[0;32m OK [0m] Reached target [0;1;39mveri<30>[ 19.428298] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10780 04:49:06.625462 tysetup… - Local Verity Protected Volumes.
10781 04:49:06.646595 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 19.456327] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10782 04:49:06.653443 d-initc… initctl Compatibility Named Pipe.
10783 04:49:06.673669 [[0;32m OK [<30>[ 19.486626] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10784 04:49:06.684083 0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10785 04:49:06.704707 [[0;32m OK [<30>[ 19.514212] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10786 04:49:06.710809 0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10787 04:49:06.731150 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 19.540508] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10788 04:49:06.734662 d-journald.socket[0m - Journal Socket.
10789 04:49:06.755965 [[0;32m OK [0m] Listening on<30>[ 19.565362] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10790 04:49:06.762275 [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10791 04:49:06.786495 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 19.595787] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10792 04:49:06.789981 d-udevd….socket[0m - udev Control Socket.
10793 04:49:06.810718 [[0;32m OK [0m] Listening on [0;1;39msystem<30>[ 19.620439] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10794 04:49:06.814475 d-udevd…l.socket[0m - udev Kernel Socket.
10795 04:49:06.870585 Mounting [0;1;39mdev-hugepages.mount[<30>[ 19.680171] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10796 04:49:06.873665 0m - Huge Pages File System...
10797 04:49:06.896336 Mounting [0;1;39mdev-m<30>[ 19.705936] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10798 04:49:06.899713 queue.mount…POSIX Message Queue File System...
10799 04:49:06.922239 Mountin<30>[ 19.735355] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10800 04:49:06.928943 g [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10801 04:49:06.964601 Startin<30>[ 19.764005] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10802 04:49:06.974755 g [0;1;39mkmod-<30>[ 19.767914] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10803 04:49:06.978234 static-nodes…ate List of Static Device Nodes...
10804 04:49:07.011844 Starting [0;1;39mmodpr<30>[ 19.821326] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10805 04:49:07.015061 obe@configfs…m - Load Kernel Module configfs...
10806 04:49:07.042008 Starting [0;1;39mmodprobe@dm_mod.s…[<30>[ 19.851790] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10807 04:49:07.045451 0m - Load Kernel Module dm_mod...
10808 04:49:07.076113 Starting [0;1;39mmodpr<30>[ 19.885802] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10809 04:49:07.079432 obe@drm.service[0m - Load Kernel Module drm...
10810 04:49:07.089249 <6>[ 19.899221] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10811 04:49:07.089989
10812 04:49:07.115263 Starting [0;1;39mmodprobe@efi_psto…-<30>[ 19.924698] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10813 04:49:07.118593 Load Kernel Module efi_pstore...
10814 04:49:07.151428 Starting [0;1;39mmodpr<30>[ 19.960812] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10815 04:49:07.154612 obe@fuse.ser…e[0m - Load Kernel Module fuse...
10816 04:49:07.182204 Starting [0;1;39mmodprobe@loop.ser…e<30>[ 19.991853] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10817 04:49:07.185514 [0m - Load Kernel Module loop...
10818 04:49:07.194855 <6>[ 20.011115] fuse: init (API version 7.37)
10819 04:49:07.215575 Starting [0;1;39msyste<30>[ 20.024841] systemd[1]: Starting systemd-journald.service - Journal Service...
10820 04:49:07.218660 md-journald.service[0m - Journal Service...
10821 04:49:07.241463 Startin<30>[ 20.054391] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10822 04:49:07.247906 g [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10823 04:49:07.278348 Starting [0;1;39msystemd-network-g… <30>[ 20.084629] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10824 04:49:07.281721 units from Kernel command line...
10825 04:49:07.307983 Starting [0;1;39msyste<30>[ 20.117463] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10826 04:49:07.314259 md-remount-f…nt Root and Kernel File Systems...
10827 04:49:07.340932 Startin<30>[ 20.150693] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10828 04:49:07.344025 g [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10829 04:49:07.371700 [[0;32m OK [0m] Mounted [0;<30>[ 20.181475] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10830 04:49:07.374958 1;39mdev-hugepages.mount[0m - Huge Pages File System.
10831 04:49:07.402740 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.<30>[ 20.212288] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10832 04:49:07.405534 mount[…- POSIX Message Queue File System.
10833 04:49:07.426634 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-<30>[ 20.236196] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10834 04:49:07.430005 debug.m…nt[0m - Kernel Debug File System.
10835 04:49:07.442054 <3>[ 20.253236] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10836 04:49:07.456093 [[0;32m OK [0m] Finished [0<30>[ 20.265335] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10837 04:49:07.466005 ;1;39mkmod-stati<3>[ 20.275315] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10838 04:49:07.469208 c-nodes…reate List of Static Device Nodes.
10839 04:49:07.493219 [[0;32m OK [<30>[ 20.305326] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10840 04:49:07.504103 0m] Finished [0<30>[ 20.306105] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10841 04:49:07.513701 ;1;39mmodprobe@c<3>[ 20.324044] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10842 04:49:07.517138 onfigfs…[0m - Load Kernel Module configfs.
10843 04:49:07.539423 [[0;32m OK [0m] Finished [0<30>[ 20.348591] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10844 04:49:07.545709 ;1;39mmodprobe@d<30>[ 20.349012] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10845 04:49:07.552569 m_mod.s…e[0m - Load Kernel Module dm_mod.
10846 04:49:07.566604 <3>[ 20.377587] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10847 04:49:07.577822 [[0;32m OK [<30>[ 20.390147] systemd[1]: modprobe@drm.service: Deactivated successfully.
10848 04:49:07.588750 0m] Finished [0<30>[ 20.390925] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10849 04:49:07.598469 ;1;39mmodprobe@d<3>[ 20.404437] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10850 04:49:07.601620 rm.service[0m - Load Kernel Module drm.
10851 04:49:07.624509 [[0;32m OK [0m] Finished [0<30>[ 20.433118] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10852 04:49:07.631128 ;1;39mmodprobe@e<30>[ 20.433678] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10853 04:49:07.644468 fi_psto…m - Lo<3>[ 20.434702] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10854 04:49:07.651651 ad Kernel Module<3>[ 20.454899] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10855 04:49:07.654885 efi_pstore.
10856 04:49:07.666552 <3>[ 20.476722] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10857 04:49:07.678529 [[0;32m OK [<30>[ 20.490126] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10858 04:49:07.688937 0m] Finished [0<30>[ 20.490724] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10859 04:49:07.695561 ;1;39mmodprobe@f<3>[ 20.497742] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10860 04:49:07.705639 use.service[0m <3>[ 20.519364] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10861 04:49:07.709505 - Load Kernel Module fuse.
10862 04:49:07.728452 [[0;32m OK [0m] Finished [0<30>[ 20.540777] systemd[1]: modprobe@loop.service: Deactivated successfully.
10863 04:49:07.738189 ;1;39mmodprobe@l<30>[ 20.541182] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10864 04:49:07.741258 oop.service[0m - Load Kernel Module loop.
10865 04:49:07.764252 [[0;32m OK [0m] Finished [0<30>[ 20.573326] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10866 04:49:07.777716 <4>[ 20.581111] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10867 04:49:07.784348 <3>[ 20.581116] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
10868 04:49:07.790931 ;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10869 04:49:07.815278 [[0;32m OK [0m] Started [0;<30>[ 20.624901] systemd[1]: Started systemd-journald.service - Journal Service.
10870 04:49:07.819108 1;39msystemd-journald.service[0m - Journal Service.
10871 04:49:07.838928 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10872 04:49:07.860394 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10873 04:49:07.879921 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10874 04:49:07.901712 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10875 04:49:07.947199 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10876 04:49:07.965572 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10877 04:49:07.985189 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10878 04:49:08.007638 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10879 04:49:08.038065 Starting [0;1;39msystemd-sysctl.se…c<46>[ 20.848445] systemd-journald[313]: Received client request to flush runtime journal.
10880 04:49:08.041514 e[0m - Apply Kernel Variables...
10881 04:49:08.086947 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10882 04:49:08.334610 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10883 04:49:08.350677 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10884 04:49:08.371779 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10885 04:49:08.795441 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10886 04:49:09.452195 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10887 04:49:09.495273 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10888 04:49:09.521292 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10889 04:49:09.596434 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10890 04:49:09.616019 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10891 04:49:09.635307 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10892 04:49:09.688154 Starting [0;1;39msystemd-binfmt.se…et Up Additional Binary Formats...
10893 04:49:09.709584 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10894 04:49:09.730685 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10895 04:49:09.759569 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-bi… Set Up Additional Binary Formats.
10896 04:49:09.774396 See 'systemctl status systemd-binfmt.service' for details.
10897 04:49:09.955198 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10898 04:49:10.014328 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10899 04:49:10.046143 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10900 04:49:10.209431 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10901 04:49:10.270096 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10902 04:49:10.342525 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10903 04:49:10.376856 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10904 04:49:10.394883 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10905 04:49:10.511254 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10906 04:49:10.533730 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10907 04:49:10.552076 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10908 04:49:10.623881 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10909 04:49:10.643355 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10910 04:49:10.663147 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10911 04:49:10.687201 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10912 04:49:10.712766 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10913 04:49:10.734968 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10914 04:49:10.741359 <46>[ 23.554848] systemd-journald[313]: Time jumped backwards, rotating.
10915 04:49:10.758673 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10916 04:49:10.782589 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10917 04:49:10.798210 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10918 04:49:11.516811 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10919 04:49:11.844348 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10920 04:49:11.862626 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10921 04:49:12.211229 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10922 04:49:12.233389 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10923 04:49:12.250189 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10924 04:49:12.268953 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10925 04:49:12.286126 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10926 04:49:12.302614 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10927 04:49:12.346958 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10928 04:49:12.427004 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10929 04:49:12.551709 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10930 04:49:12.568632 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10931 04:49:12.748841 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10932 04:49:12.791449 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10933 04:49:12.812013 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10934 04:49:12.834573 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10935 04:49:12.852595 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10936 04:49:12.888587 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10937 04:49:12.912492 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10938 04:49:12.944913 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10939 04:49:12.965034 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10940 04:49:13.025742 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
10941 04:49:13.049516 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10942 04:49:13.096112 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10943 04:49:13.129856 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
10944 04:49:13.205877
10945 04:49:13.206056
10946 04:49:13.209568 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10947 04:49:13.209697
10948 04:49:13.212509 debian-bookworm-arm64 login: root (automatic login)
10949 04:49:13.212595
10950 04:49:13.212662
10951 04:49:13.483774 Linux debian-bookworm-arm64 6.1.75-cip14-rt8 #1 SMP PREEMPT Sun Feb 4 04:24:19 UTC 2024 aarch64
10952 04:49:13.484305
10953 04:49:13.490669 The programs included with the Debian GNU/Linux system are free software;
10954 04:49:13.496857 the exact distribution terms for each program are described in the
10955 04:49:13.500408 individual files in /usr/share/doc/*/copyright.
10956 04:49:13.500846
10957 04:49:13.506872 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10958 04:49:13.510263 permitted by applicable law.
10959 04:49:14.497259 Matched prompt #10: / #
10961 04:49:14.497728 Setting prompt string to ['/ #']
10962 04:49:14.497898 end: 2.2.5.1 login-action (duration 00:00:28) [common]
10964 04:49:14.498274 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
10965 04:49:14.498441 start: 2.2.6 expect-shell-connection (timeout 00:03:24) [common]
10966 04:49:14.498577 Setting prompt string to ['/ #']
10967 04:49:14.498694 Forcing a shell prompt, looking for ['/ #']
10969 04:49:14.549116 / #
10970 04:49:14.549620 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10971 04:49:14.550145 Waiting using forced prompt support (timeout 00:02:30)
10972 04:49:14.555210
10973 04:49:14.555980 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10974 04:49:14.556471 start: 2.2.7 export-device-env (timeout 00:03:24) [common]
10976 04:49:14.657661 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12699845/extract-nfsrootfs-6vzpzxd0'
10977 04:49:14.664192 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12699845/extract-nfsrootfs-6vzpzxd0'
10979 04:49:14.765786 / # export NFS_SERVER_IP='192.168.201.1'
10980 04:49:14.771448 export NFS_SERVER_IP='192.168.201.1'
10981 04:49:14.772304 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10982 04:49:14.772828 end: 2.2 depthcharge-retry (duration 00:01:37) [common]
10983 04:49:14.773354 end: 2 depthcharge-action (duration 00:01:37) [common]
10984 04:49:14.773921 start: 3 lava-test-retry (timeout 00:07:42) [common]
10985 04:49:14.774476 start: 3.1 lava-test-shell (timeout 00:07:42) [common]
10986 04:49:14.774910 Using namespace: common
10988 04:49:14.876196 / # #
10989 04:49:14.876873 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10990 04:49:14.882329 #
10991 04:49:14.883220 Using /lava-12699845
10993 04:49:14.984443 / # export SHELL=/bin/bash
10994 04:49:14.991289 export SHELL=/bin/bash
10996 04:49:15.093078 / # . /lava-12699845/environment
10997 04:49:15.099874 . /lava-12699845/environment
10999 04:49:15.207190 / # /lava-12699845/bin/lava-test-runner /lava-12699845/0
11000 04:49:15.207864 Test shell timeout: 10s (minimum of the action and connection timeout)
11001 04:49:15.213201 /lava-12699845/bin/lava-test-runner /lava-12699845/0
11002 04:49:15.444013 + export TESTRUN_ID=0_timesync-off
11003 04:49:15.446909 + TESTRUN_ID=0_timesync-off
11004 04:49:15.450200 + cd /lava-12699845/0/tests/0_timesync-off
11005 04:49:15.453497 ++ cat uuid
11006 04:49:15.458093 + UUID=12699845_1.6.2.3.1
11007 04:49:15.458473 + set +x
11008 04:49:15.464871 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12699845_1.6.2.3.1>
11009 04:49:15.465535 Received signal: <STARTRUN> 0_timesync-off 12699845_1.6.2.3.1
11010 04:49:15.465923 Starting test lava.0_timesync-off (12699845_1.6.2.3.1)
11011 04:49:15.466425 Skipping test definition patterns.
11012 04:49:15.467789 + systemctl stop systemd-timesyncd
11013 04:49:15.523362 + set +x
11014 04:49:15.526476 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12699845_1.6.2.3.1>
11015 04:49:15.527246 Received signal: <ENDRUN> 0_timesync-off 12699845_1.6.2.3.1
11016 04:49:15.527730 Ending use of test pattern.
11017 04:49:15.528122 Ending test lava.0_timesync-off (12699845_1.6.2.3.1), duration 0.06
11019 04:49:15.594927 + export TESTRUN_ID=1_kselftest-alsa
11020 04:49:15.597929 + TESTRUN_ID=1_kselftest-alsa
11021 04:49:15.601272 + cd /lava-12699845/0/tests/1_kselftest-alsa
11022 04:49:15.604711 ++ cat uuid
11023 04:49:15.609093 + UUID=12699845_1.6.2.3.5
11024 04:49:15.609481 + set +x
11025 04:49:15.616056 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 12699845_1.6.2.3.5>
11026 04:49:15.616712 Received signal: <STARTRUN> 1_kselftest-alsa 12699845_1.6.2.3.5
11027 04:49:15.617085 Starting test lava.1_kselftest-alsa (12699845_1.6.2.3.5)
11028 04:49:15.617469 Skipping test definition patterns.
11029 04:49:15.619375 + cd ./automated/linux/kselftest/
11030 04:49:15.645689 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11031 04:49:15.682005 INFO: install_deps skipped
11032 04:49:16.192231 --2024-02-04 04:48:36-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11033 04:49:16.205044 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11034 04:49:16.337545 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11035 04:49:16.470040 HTTP request sent, awaiting response... 200 OK
11036 04:49:16.473722 Length: 2966368 (2.8M) [application/octet-stream]
11037 04:49:16.476538 Saving to: 'kselftest.tar.xz'
11038 04:49:16.477095
11039 04:49:16.477473
11040 04:49:16.735618 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11041 04:49:17.001583 kselftest.tar.xz 1%[ ] 47.81K 181KB/s
11042 04:49:17.313748 kselftest.tar.xz 7%[> ] 217.50K 411KB/s
11043 04:49:17.589598 kselftest.tar.xz 28%[====> ] 819.89K 973KB/s
11044 04:49:17.718339 kselftest.tar.xz 68%[============> ] 1.93M 1.72MB/s
11045 04:49:17.724638 kselftest.tar.xz 100%[===================>] 2.83M 2.27MB/s in 1.2s
11046 04:49:17.724731
11047 04:49:17.982264 2024-02-04 04:48:38 (2.27 MB/s) - 'kselftest.tar.xz' saved [2966368/2966368]
11048 04:49:17.982422
11049 04:49:23.366841 skiplist:
11050 04:49:23.369735 ========================================
11051 04:49:23.373160 ========================================
11052 04:49:23.419550 alsa:mixer-test
11053 04:49:23.438670 ============== Tests to run ===============
11054 04:49:23.439111 alsa:mixer-test
11055 04:49:23.442213 ===========End Tests to run ===============
11056 04:49:23.445714 shardfile-alsa pass
11057 04:49:23.549488 <12>[ 36.364986] kselftest: Running tests in alsa
11058 04:49:23.552394 TAP version 13
11059 04:49:23.566050 1..1
11060 04:49:23.579680 # selftests: alsa: mixer-test
11061 04:49:24.086305 # TAP version 13
11062 04:49:24.086483 # 1..0
11063 04:49:24.092973 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11064 04:49:24.096439 ok 1 selftests: alsa: mixer-test
11065 04:49:24.815461 alsa_mixer-test pass
11066 04:49:24.859762 + ../../utils/send-to-lava.sh ./output/result.txt
11067 04:49:24.936628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
11068 04:49:24.937495 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
11070 04:49:24.985471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11071 04:49:24.985988 + set +x
11072 04:49:24.986715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11074 04:49:24.992383 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 12699845_1.6.2.3.5>
11075 04:49:24.993262 Received signal: <ENDRUN> 1_kselftest-alsa 12699845_1.6.2.3.5
11076 04:49:24.993727 Ending use of test pattern.
11077 04:49:24.994284 Ending test lava.1_kselftest-alsa (12699845_1.6.2.3.5), duration 9.38
11079 04:49:24.995801 <LAVA_TEST_RUNNER EXIT>
11080 04:49:24.996496 ok: lava_test_shell seems to have completed
11081 04:49:24.997150 alsa_mixer-test: pass
shardfile-alsa: pass
11082 04:49:24.997676 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11083 04:49:24.998286 end: 3 lava-test-retry (duration 00:00:10) [common]
11084 04:49:24.998889 start: 4 finalize (timeout 00:07:31) [common]
11085 04:49:24.999494 start: 4.1 power-off (timeout 00:00:30) [common]
11086 04:49:25.000414 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11087 04:49:25.118230 >> Command sent successfully.
11088 04:49:25.122182 Returned 0 in 0 seconds
11089 04:49:25.223118 end: 4.1 power-off (duration 00:00:00) [common]
11091 04:49:25.224969 start: 4.2 read-feedback (timeout 00:07:31) [common]
11092 04:49:25.226380 Listened to connection for namespace 'common' for up to 1s
11093 04:49:26.226251 Finalising connection for namespace 'common'
11094 04:49:26.226960 Disconnecting from shell: Finalise
11095 04:49:26.227490 / #
11096 04:49:26.328597 end: 4.2 read-feedback (duration 00:00:01) [common]
11097 04:49:26.329368 end: 4 finalize (duration 00:00:01) [common]
11098 04:49:26.330118 Cleaning after the job
11099 04:49:26.330723 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699845/tftp-deploy-2p2y6t07/ramdisk
11100 04:49:26.342275 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699845/tftp-deploy-2p2y6t07/kernel
11101 04:49:26.373052 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699845/tftp-deploy-2p2y6t07/dtb
11102 04:49:26.373404 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699845/tftp-deploy-2p2y6t07/nfsrootfs
11103 04:49:26.452879 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699845/tftp-deploy-2p2y6t07/modules
11104 04:49:26.458301 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12699845
11105 04:49:26.998842 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12699845
11106 04:49:26.999016 Job finished correctly