Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 14
- Kernel Errors: 34
1 04:46:06.890186 lava-dispatcher, installed at version: 2023.10
2 04:46:06.890406 start: 0 validate
3 04:46:06.890552 Start time: 2024-02-04 04:46:06.890542+00:00 (UTC)
4 04:46:06.890670 Using caching service: 'http://localhost/cache/?uri=%s'
5 04:46:06.890808 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 04:46:07.157985 Using caching service: 'http://localhost/cache/?uri=%s'
7 04:46:07.158167 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 04:46:07.415424 Using caching service: 'http://localhost/cache/?uri=%s'
9 04:46:07.415591 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 04:46:07.681811 Using caching service: 'http://localhost/cache/?uri=%s'
11 04:46:07.681983 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 04:46:07.941606 Using caching service: 'http://localhost/cache/?uri=%s'
13 04:46:07.941794 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 04:46:08.209011 validate duration: 1.32
16 04:46:08.209271 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 04:46:08.209372 start: 1.1 download-retry (timeout 00:10:00) [common]
18 04:46:08.209463 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 04:46:08.209589 Not decompressing ramdisk as can be used compressed.
20 04:46:08.209674 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 04:46:08.209742 saving as /var/lib/lava/dispatcher/tmp/12699848/tftp-deploy-qzgrpv7l/ramdisk/initrd.cpio.gz
22 04:46:08.209808 total size: 4665395 (4 MB)
23 04:46:08.210922 progress 0 % (0 MB)
24 04:46:08.212395 progress 5 % (0 MB)
25 04:46:08.213711 progress 10 % (0 MB)
26 04:46:08.214976 progress 15 % (0 MB)
27 04:46:08.216222 progress 20 % (0 MB)
28 04:46:08.217512 progress 25 % (1 MB)
29 04:46:08.218767 progress 30 % (1 MB)
30 04:46:08.219994 progress 35 % (1 MB)
31 04:46:08.221270 progress 40 % (1 MB)
32 04:46:08.222663 progress 45 % (2 MB)
33 04:46:08.223897 progress 50 % (2 MB)
34 04:46:08.225189 progress 55 % (2 MB)
35 04:46:08.226417 progress 60 % (2 MB)
36 04:46:08.227645 progress 65 % (2 MB)
37 04:46:08.228915 progress 70 % (3 MB)
38 04:46:08.230148 progress 75 % (3 MB)
39 04:46:08.231375 progress 80 % (3 MB)
40 04:46:08.232828 progress 85 % (3 MB)
41 04:46:08.234091 progress 90 % (4 MB)
42 04:46:08.235318 progress 95 % (4 MB)
43 04:46:08.236563 progress 100 % (4 MB)
44 04:46:08.236727 4 MB downloaded in 0.03 s (165.28 MB/s)
45 04:46:08.236873 end: 1.1.1 http-download (duration 00:00:00) [common]
47 04:46:08.237110 end: 1.1 download-retry (duration 00:00:00) [common]
48 04:46:08.237210 start: 1.2 download-retry (timeout 00:10:00) [common]
49 04:46:08.237296 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 04:46:08.237426 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 04:46:08.237499 saving as /var/lib/lava/dispatcher/tmp/12699848/tftp-deploy-qzgrpv7l/kernel/Image
52 04:46:08.237561 total size: 51597824 (49 MB)
53 04:46:08.237622 No compression specified
54 04:46:08.238651 progress 0 % (0 MB)
55 04:46:08.252130 progress 5 % (2 MB)
56 04:46:08.265784 progress 10 % (4 MB)
57 04:46:08.279220 progress 15 % (7 MB)
58 04:46:08.292493 progress 20 % (9 MB)
59 04:46:08.306317 progress 25 % (12 MB)
60 04:46:08.319844 progress 30 % (14 MB)
61 04:46:08.333328 progress 35 % (17 MB)
62 04:46:08.346649 progress 40 % (19 MB)
63 04:46:08.360174 progress 45 % (22 MB)
64 04:46:08.373824 progress 50 % (24 MB)
65 04:46:08.387507 progress 55 % (27 MB)
66 04:46:08.401001 progress 60 % (29 MB)
67 04:46:08.414661 progress 65 % (32 MB)
68 04:46:08.428031 progress 70 % (34 MB)
69 04:46:08.441179 progress 75 % (36 MB)
70 04:46:08.454489 progress 80 % (39 MB)
71 04:46:08.467814 progress 85 % (41 MB)
72 04:46:08.481358 progress 90 % (44 MB)
73 04:46:08.494621 progress 95 % (46 MB)
74 04:46:08.508290 progress 100 % (49 MB)
75 04:46:08.508522 49 MB downloaded in 0.27 s (181.61 MB/s)
76 04:46:08.508675 end: 1.2.1 http-download (duration 00:00:00) [common]
78 04:46:08.508958 end: 1.2 download-retry (duration 00:00:00) [common]
79 04:46:08.509047 start: 1.3 download-retry (timeout 00:10:00) [common]
80 04:46:08.509137 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 04:46:08.509315 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 04:46:08.509393 saving as /var/lib/lava/dispatcher/tmp/12699848/tftp-deploy-qzgrpv7l/dtb/mt8192-asurada-spherion-r0.dtb
83 04:46:08.509455 total size: 47278 (0 MB)
84 04:46:08.509517 No compression specified
85 04:46:08.510625 progress 69 % (0 MB)
86 04:46:08.510936 progress 100 % (0 MB)
87 04:46:08.511098 0 MB downloaded in 0.00 s (27.49 MB/s)
88 04:46:08.511222 end: 1.3.1 http-download (duration 00:00:00) [common]
90 04:46:08.511446 end: 1.3 download-retry (duration 00:00:00) [common]
91 04:46:08.511534 start: 1.4 download-retry (timeout 00:10:00) [common]
92 04:46:08.511617 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 04:46:08.511733 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 04:46:08.511814 saving as /var/lib/lava/dispatcher/tmp/12699848/tftp-deploy-qzgrpv7l/nfsrootfs/full.rootfs.tar
95 04:46:08.511876 total size: 200813988 (191 MB)
96 04:46:08.511938 Using unxz to decompress xz
97 04:46:08.516209 progress 0 % (0 MB)
98 04:46:09.044371 progress 5 % (9 MB)
99 04:46:09.557745 progress 10 % (19 MB)
100 04:46:10.140594 progress 15 % (28 MB)
101 04:46:10.513058 progress 20 % (38 MB)
102 04:46:10.834582 progress 25 % (47 MB)
103 04:46:11.422966 progress 30 % (57 MB)
104 04:46:11.969418 progress 35 % (67 MB)
105 04:46:12.562609 progress 40 % (76 MB)
106 04:46:13.120886 progress 45 % (86 MB)
107 04:46:13.703971 progress 50 % (95 MB)
108 04:46:14.334720 progress 55 % (105 MB)
109 04:46:14.996564 progress 60 % (114 MB)
110 04:46:15.115430 progress 65 % (124 MB)
111 04:46:15.255945 progress 70 % (134 MB)
112 04:46:15.355117 progress 75 % (143 MB)
113 04:46:15.429030 progress 80 % (153 MB)
114 04:46:15.500373 progress 85 % (162 MB)
115 04:46:15.602580 progress 90 % (172 MB)
116 04:46:15.880927 progress 95 % (181 MB)
117 04:46:16.453755 progress 100 % (191 MB)
118 04:46:16.458933 191 MB downloaded in 7.95 s (24.10 MB/s)
119 04:46:16.459197 end: 1.4.1 http-download (duration 00:00:08) [common]
121 04:46:16.459460 end: 1.4 download-retry (duration 00:00:08) [common]
122 04:46:16.459550 start: 1.5 download-retry (timeout 00:09:52) [common]
123 04:46:16.459640 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 04:46:16.459799 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 04:46:16.459871 saving as /var/lib/lava/dispatcher/tmp/12699848/tftp-deploy-qzgrpv7l/modules/modules.tar
126 04:46:16.459932 total size: 8633524 (8 MB)
127 04:46:16.459994 Using unxz to decompress xz
128 04:46:16.464519 progress 0 % (0 MB)
129 04:46:16.485597 progress 5 % (0 MB)
130 04:46:16.509545 progress 10 % (0 MB)
131 04:46:16.533205 progress 15 % (1 MB)
132 04:46:16.556542 progress 20 % (1 MB)
133 04:46:16.580077 progress 25 % (2 MB)
134 04:46:16.607451 progress 30 % (2 MB)
135 04:46:16.631979 progress 35 % (2 MB)
136 04:46:16.655288 progress 40 % (3 MB)
137 04:46:16.679348 progress 45 % (3 MB)
138 04:46:16.705577 progress 50 % (4 MB)
139 04:46:16.730476 progress 55 % (4 MB)
140 04:46:16.757536 progress 60 % (4 MB)
141 04:46:16.783275 progress 65 % (5 MB)
142 04:46:16.808014 progress 70 % (5 MB)
143 04:46:16.831412 progress 75 % (6 MB)
144 04:46:16.858503 progress 80 % (6 MB)
145 04:46:16.883935 progress 85 % (7 MB)
146 04:46:16.910547 progress 90 % (7 MB)
147 04:46:16.940343 progress 95 % (7 MB)
148 04:46:16.968259 progress 100 % (8 MB)
149 04:46:16.973707 8 MB downloaded in 0.51 s (16.03 MB/s)
150 04:46:16.973971 end: 1.5.1 http-download (duration 00:00:01) [common]
152 04:46:16.974238 end: 1.5 download-retry (duration 00:00:01) [common]
153 04:46:16.974332 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 04:46:16.974425 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 04:46:20.501723 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12699848/extract-nfsrootfs-7j02hjaw
156 04:46:20.501927 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 04:46:20.502029 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 04:46:20.502204 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp
159 04:46:20.502338 makedir: /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/bin
160 04:46:20.502442 makedir: /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/tests
161 04:46:20.502543 makedir: /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/results
162 04:46:20.502646 Creating /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/bin/lava-add-keys
163 04:46:20.502793 Creating /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/bin/lava-add-sources
164 04:46:20.502929 Creating /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/bin/lava-background-process-start
165 04:46:20.503060 Creating /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/bin/lava-background-process-stop
166 04:46:20.503191 Creating /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/bin/lava-common-functions
167 04:46:20.503318 Creating /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/bin/lava-echo-ipv4
168 04:46:20.503449 Creating /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/bin/lava-install-packages
169 04:46:20.503576 Creating /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/bin/lava-installed-packages
170 04:46:20.503704 Creating /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/bin/lava-os-build
171 04:46:20.503833 Creating /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/bin/lava-probe-channel
172 04:46:20.503961 Creating /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/bin/lava-probe-ip
173 04:46:20.504088 Creating /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/bin/lava-target-ip
174 04:46:20.504216 Creating /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/bin/lava-target-mac
175 04:46:20.504344 Creating /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/bin/lava-target-storage
176 04:46:20.504475 Creating /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/bin/lava-test-case
177 04:46:20.504604 Creating /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/bin/lava-test-event
178 04:46:20.504759 Creating /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/bin/lava-test-feedback
179 04:46:20.504901 Creating /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/bin/lava-test-raise
180 04:46:20.505030 Creating /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/bin/lava-test-reference
181 04:46:20.505159 Creating /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/bin/lava-test-runner
182 04:46:20.505287 Creating /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/bin/lava-test-set
183 04:46:20.505416 Creating /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/bin/lava-test-shell
184 04:46:20.505546 Updating /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/bin/lava-add-keys (debian)
185 04:46:20.505700 Updating /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/bin/lava-add-sources (debian)
186 04:46:20.505843 Updating /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/bin/lava-install-packages (debian)
187 04:46:20.505985 Updating /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/bin/lava-installed-packages (debian)
188 04:46:20.506126 Updating /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/bin/lava-os-build (debian)
189 04:46:20.506249 Creating /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/environment
190 04:46:20.506346 LAVA metadata
191 04:46:20.506418 - LAVA_JOB_ID=12699848
192 04:46:20.506483 - LAVA_DISPATCHER_IP=192.168.201.1
193 04:46:20.506584 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 04:46:20.506652 skipped lava-vland-overlay
195 04:46:20.506726 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 04:46:20.506805 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 04:46:20.506867 skipped lava-multinode-overlay
198 04:46:20.506939 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 04:46:20.507018 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 04:46:20.507092 Loading test definitions
201 04:46:20.507182 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 04:46:20.507253 Using /lava-12699848 at stage 0
203 04:46:20.507541 uuid=12699848_1.6.2.3.1 testdef=None
204 04:46:20.507630 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 04:46:20.507716 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 04:46:20.508190 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 04:46:20.508412 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 04:46:20.509068 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 04:46:20.509300 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 04:46:20.509859 runner path: /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/0/tests/0_timesync-off test_uuid 12699848_1.6.2.3.1
213 04:46:20.510015 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 04:46:20.510243 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 04:46:20.510317 Using /lava-12699848 at stage 0
217 04:46:20.510414 Fetching tests from https://github.com/kernelci/test-definitions.git
218 04:46:20.510493 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/0/tests/1_kselftest-dt'
219 04:46:26.694136 Running '/usr/bin/git checkout kernelci.org
220 04:46:26.842560 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 04:46:26.843311 uuid=12699848_1.6.2.3.5 testdef=None
222 04:46:26.843466 end: 1.6.2.3.5 git-repo-action (duration 00:00:06) [common]
224 04:46:26.843716 start: 1.6.2.3.6 test-overlay (timeout 00:09:41) [common]
225 04:46:26.844468 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 04:46:26.844729 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:41) [common]
228 04:46:26.845731 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 04:46:26.845965 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:41) [common]
231 04:46:26.846924 runner path: /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/0/tests/1_kselftest-dt test_uuid 12699848_1.6.2.3.5
232 04:46:26.847014 BOARD='mt8192-asurada-spherion-r0'
233 04:46:26.847079 BRANCH='cip-gitlab'
234 04:46:26.847138 SKIPFILE='/dev/null'
235 04:46:26.847196 SKIP_INSTALL='True'
236 04:46:26.847251 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 04:46:26.847311 TST_CASENAME=''
238 04:46:26.847367 TST_CMDFILES='dt'
239 04:46:26.847508 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 04:46:26.847712 Creating lava-test-runner.conf files
242 04:46:26.847776 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12699848/lava-overlay-ak7l20gp/lava-12699848/0 for stage 0
243 04:46:26.847868 - 0_timesync-off
244 04:46:26.847938 - 1_kselftest-dt
245 04:46:26.848033 end: 1.6.2.3 test-definition (duration 00:00:06) [common]
246 04:46:26.848120 start: 1.6.2.4 compress-overlay (timeout 00:09:41) [common]
247 04:46:34.312289 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 04:46:34.312441 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:34) [common]
249 04:46:34.312556 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 04:46:34.312685 end: 1.6.2 lava-overlay (duration 00:00:14) [common]
251 04:46:34.312798 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
252 04:46:34.434249 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 04:46:34.434655 start: 1.6.4 extract-modules (timeout 00:09:34) [common]
254 04:46:34.434793 extracting modules file /var/lib/lava/dispatcher/tmp/12699848/tftp-deploy-qzgrpv7l/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12699848/extract-nfsrootfs-7j02hjaw
255 04:46:34.658214 extracting modules file /var/lib/lava/dispatcher/tmp/12699848/tftp-deploy-qzgrpv7l/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12699848/extract-overlay-ramdisk-0p4bjss_/ramdisk
256 04:46:34.897435 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 04:46:34.897604 start: 1.6.5 apply-overlay-tftp (timeout 00:09:33) [common]
258 04:46:34.897697 [common] Applying overlay to NFS
259 04:46:34.897768 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12699848/compress-overlay-p24s1_y2/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12699848/extract-nfsrootfs-7j02hjaw
260 04:46:35.891952 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 04:46:35.892120 start: 1.6.6 configure-preseed-file (timeout 00:09:32) [common]
262 04:46:35.892215 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 04:46:35.892307 start: 1.6.7 compress-ramdisk (timeout 00:09:32) [common]
264 04:46:35.892386 Building ramdisk /var/lib/lava/dispatcher/tmp/12699848/extract-overlay-ramdisk-0p4bjss_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12699848/extract-overlay-ramdisk-0p4bjss_/ramdisk
265 04:46:36.226985 >> 119436 blocks
266 04:46:38.135158 rename /var/lib/lava/dispatcher/tmp/12699848/extract-overlay-ramdisk-0p4bjss_/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12699848/tftp-deploy-qzgrpv7l/ramdisk/ramdisk.cpio.gz
267 04:46:38.135612 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 04:46:38.135734 start: 1.6.8 prepare-kernel (timeout 00:09:30) [common]
269 04:46:38.135832 start: 1.6.8.1 prepare-fit (timeout 00:09:30) [common]
270 04:46:38.135937 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12699848/tftp-deploy-qzgrpv7l/kernel/Image'
271 04:46:50.437826 Returned 0 in 12 seconds
272 04:46:50.538875 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12699848/tftp-deploy-qzgrpv7l/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12699848/tftp-deploy-qzgrpv7l/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12699848/tftp-deploy-qzgrpv7l/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12699848/tftp-deploy-qzgrpv7l/kernel/image.itb
273 04:46:50.919351 output: FIT description: Kernel Image image with one or more FDT blobs
274 04:46:50.919730 output: Created: Sun Feb 4 04:46:50 2024
275 04:46:50.919815 output: Image 0 (kernel-1)
276 04:46:50.919881 output: Description:
277 04:46:50.919941 output: Created: Sun Feb 4 04:46:50 2024
278 04:46:50.920000 output: Type: Kernel Image
279 04:46:50.920060 output: Compression: lzma compressed
280 04:46:50.920118 output: Data Size: 12048508 Bytes = 11766.12 KiB = 11.49 MiB
281 04:46:50.920177 output: Architecture: AArch64
282 04:46:50.920232 output: OS: Linux
283 04:46:50.920291 output: Load Address: 0x00000000
284 04:46:50.920347 output: Entry Point: 0x00000000
285 04:46:50.920401 output: Hash algo: crc32
286 04:46:50.920460 output: Hash value: 3b31d50c
287 04:46:50.920512 output: Image 1 (fdt-1)
288 04:46:50.920563 output: Description: mt8192-asurada-spherion-r0
289 04:46:50.920614 output: Created: Sun Feb 4 04:46:50 2024
290 04:46:50.920666 output: Type: Flat Device Tree
291 04:46:50.920748 output: Compression: uncompressed
292 04:46:50.920828 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 04:46:50.920880 output: Architecture: AArch64
294 04:46:50.920931 output: Hash algo: crc32
295 04:46:50.920983 output: Hash value: cc4352de
296 04:46:50.921034 output: Image 2 (ramdisk-1)
297 04:46:50.921085 output: Description: unavailable
298 04:46:50.921136 output: Created: Sun Feb 4 04:46:50 2024
299 04:46:50.921188 output: Type: RAMDisk Image
300 04:46:50.921240 output: Compression: Unknown Compression
301 04:46:50.921291 output: Data Size: 17800906 Bytes = 17383.70 KiB = 16.98 MiB
302 04:46:50.921342 output: Architecture: AArch64
303 04:46:50.921393 output: OS: Linux
304 04:46:50.921444 output: Load Address: unavailable
305 04:46:50.921495 output: Entry Point: unavailable
306 04:46:50.921546 output: Hash algo: crc32
307 04:46:50.921597 output: Hash value: 00424bc5
308 04:46:50.921648 output: Default Configuration: 'conf-1'
309 04:46:50.921700 output: Configuration 0 (conf-1)
310 04:46:50.921755 output: Description: mt8192-asurada-spherion-r0
311 04:46:50.921814 output: Kernel: kernel-1
312 04:46:50.921866 output: Init Ramdisk: ramdisk-1
313 04:46:50.921917 output: FDT: fdt-1
314 04:46:50.921968 output: Loadables: kernel-1
315 04:46:50.922019 output:
316 04:46:50.922221 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 04:46:50.922316 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 04:46:50.922423 end: 1.6 prepare-tftp-overlay (duration 00:00:34) [common]
319 04:46:50.922511 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:17) [common]
320 04:46:50.922587 No LXC device requested
321 04:46:50.922664 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 04:46:50.922744 start: 1.8 deploy-device-env (timeout 00:09:17) [common]
323 04:46:50.922820 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 04:46:50.922890 Checking files for TFTP limit of 4294967296 bytes.
325 04:46:50.923394 end: 1 tftp-deploy (duration 00:00:43) [common]
326 04:46:50.923496 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 04:46:50.923588 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 04:46:50.923731 substitutions:
329 04:46:50.923869 - {DTB}: 12699848/tftp-deploy-qzgrpv7l/dtb/mt8192-asurada-spherion-r0.dtb
330 04:46:50.923961 - {INITRD}: 12699848/tftp-deploy-qzgrpv7l/ramdisk/ramdisk.cpio.gz
331 04:46:50.924020 - {KERNEL}: 12699848/tftp-deploy-qzgrpv7l/kernel/Image
332 04:46:50.924076 - {LAVA_MAC}: None
333 04:46:50.924132 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12699848/extract-nfsrootfs-7j02hjaw
334 04:46:50.924187 - {NFS_SERVER_IP}: 192.168.201.1
335 04:46:50.924240 - {PRESEED_CONFIG}: None
336 04:46:50.924293 - {PRESEED_LOCAL}: None
337 04:46:50.924346 - {RAMDISK}: 12699848/tftp-deploy-qzgrpv7l/ramdisk/ramdisk.cpio.gz
338 04:46:50.924399 - {ROOT_PART}: None
339 04:46:50.924451 - {ROOT}: None
340 04:46:50.924504 - {SERVER_IP}: 192.168.201.1
341 04:46:50.924556 - {TEE}: None
342 04:46:50.924608 Parsed boot commands:
343 04:46:50.924661 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 04:46:50.924901 Parsed boot commands: tftpboot 192.168.201.1 12699848/tftp-deploy-qzgrpv7l/kernel/image.itb 12699848/tftp-deploy-qzgrpv7l/kernel/cmdline
345 04:46:50.924989 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 04:46:50.925074 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 04:46:50.925164 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 04:46:50.925248 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 04:46:50.925318 Not connected, no need to disconnect.
350 04:46:50.925390 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 04:46:50.925469 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 04:46:50.925547 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 04:46:50.929907 Setting prompt string to ['lava-test: # ']
354 04:46:50.930323 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 04:46:50.930425 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 04:46:50.930544 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 04:46:50.930665 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 04:46:50.930897 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
359 04:46:56.083834 >> Command sent successfully.
360 04:46:56.095496 Returned 0 in 5 seconds
361 04:46:56.196874 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 04:46:56.198400 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 04:46:56.199076 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 04:46:56.199891 Setting prompt string to 'Starting depthcharge on Spherion...'
366 04:46:56.200367 Changing prompt to 'Starting depthcharge on Spherion...'
367 04:46:56.200838 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 04:46:56.202191 [Enter `^Ec?' for help]
369 04:46:56.370144
370 04:46:56.370689
371 04:46:56.371075 F0: 102B 0000
372 04:46:56.371447
373 04:46:56.371794 F3: 1001 0000 [0200]
374 04:46:56.372126
375 04:46:56.373220 F3: 1001 0000
376 04:46:56.373688
377 04:46:56.374022 F7: 102D 0000
378 04:46:56.374335
379 04:46:56.377847 F1: 0000 0000
380 04:46:56.378275
381 04:46:56.378610 V0: 0000 0000 [0001]
382 04:46:56.378926
383 04:46:56.379224 00: 0007 8000
384 04:46:56.379539
385 04:46:56.380300 01: 0000 0000
386 04:46:56.380658
387 04:46:56.381014 BP: 0C00 0209 [0000]
388 04:46:56.381310
389 04:46:56.383692 G0: 1182 0000
390 04:46:56.384113
391 04:46:56.384448 EC: 0000 0021 [4000]
392 04:46:56.384800
393 04:46:56.389698 S7: 0000 0000 [0000]
394 04:46:56.390118
395 04:46:56.390452 CC: 0000 0000 [0001]
396 04:46:56.390763
397 04:46:56.391063 T0: 0000 0040 [010F]
398 04:46:56.391360
399 04:46:56.392022 Jump to BL
400 04:46:56.392360
401 04:46:56.416649
402 04:46:56.417275
403 04:46:56.417649
404 04:46:56.423481 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 04:46:56.428020 ARM64: Exception handlers installed.
406 04:46:56.430405 ARM64: Testing exception
407 04:46:56.434883 ARM64: Done test exception
408 04:46:56.440601 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 04:46:56.450120 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 04:46:56.457117 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 04:46:56.467341 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 04:46:56.474032 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 04:46:56.484116 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 04:46:56.495813 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 04:46:56.501936 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 04:46:56.519539 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 04:46:56.523329 WDT: Last reset was cold boot
418 04:46:56.526623 SPI1(PAD0) initialized at 2873684 Hz
419 04:46:56.529604 SPI5(PAD0) initialized at 992727 Hz
420 04:46:56.532817 VBOOT: Loading verstage.
421 04:46:56.539903 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 04:46:56.542910 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 04:46:56.546017 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 04:46:56.550044 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 04:46:56.556921 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 04:46:56.563899 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 04:46:56.574977 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 04:46:56.575542
429 04:46:56.575919
430 04:46:56.584403 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 04:46:56.588456 ARM64: Exception handlers installed.
432 04:46:56.591616 ARM64: Testing exception
433 04:46:56.592205 ARM64: Done test exception
434 04:46:56.597914 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 04:46:56.601770 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 04:46:56.615296 Probing TPM: . done!
437 04:46:56.615767 TPM ready after 0 ms
438 04:46:56.623083 Connected to device vid:did:rid of 1ae0:0028:00
439 04:46:56.629112 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
440 04:46:56.633620 Initialized TPM device CR50 revision 0
441 04:46:56.683829 tlcl_send_startup: Startup return code is 0
442 04:46:56.684395 TPM: setup succeeded
443 04:46:56.694804 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 04:46:56.703351 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 04:46:56.713316 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 04:46:56.722490 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 04:46:56.726366 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 04:46:56.729517 in-header: 03 07 00 00 08 00 00 00
449 04:46:56.732485 in-data: aa e4 47 04 13 02 00 00
450 04:46:56.736262 Chrome EC: UHEPI supported
451 04:46:56.743378 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 04:46:56.745483 in-header: 03 9d 00 00 08 00 00 00
453 04:46:56.748494 in-data: 10 20 20 08 00 00 00 00
454 04:46:56.749074 Phase 1
455 04:46:56.753652 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 04:46:56.758842 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 04:46:56.765692 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 04:46:56.769154 Recovery requested (1009000e)
459 04:46:56.775620 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 04:46:56.781658 tlcl_extend: response is 0
461 04:46:56.789170 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 04:46:56.794920 tlcl_extend: response is 0
463 04:46:56.801319 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 04:46:56.822260 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 04:46:56.828632 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 04:46:56.829343
467 04:46:56.829737
468 04:46:56.838707 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 04:46:56.841931 ARM64: Exception handlers installed.
470 04:46:56.845326 ARM64: Testing exception
471 04:46:56.845801 ARM64: Done test exception
472 04:46:56.867708 pmic_efuse_setting: Set efuses in 11 msecs
473 04:46:56.871328 pmwrap_interface_init: Select PMIF_VLD_RDY
474 04:46:56.877653 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 04:46:56.881366 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 04:46:56.884895 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 04:46:56.892141 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 04:46:56.897247 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 04:46:56.900304 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 04:46:56.906733 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 04:46:56.909831 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 04:46:56.916246 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 04:46:56.919619 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 04:46:56.928328 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 04:46:56.931192 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 04:46:56.932780 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 04:46:56.939720 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 04:46:56.945861 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 04:46:56.949298 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 04:46:56.956831 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 04:46:56.964370 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 04:46:56.967140 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 04:46:56.974288 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 04:46:56.980339 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 04:46:56.983838 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 04:46:56.990604 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 04:46:56.997155 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 04:46:57.000774 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 04:46:57.007337 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 04:46:57.011951 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 04:46:57.017445 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 04:46:57.020867 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 04:46:57.027491 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 04:46:57.030312 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 04:46:57.037370 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 04:46:57.040399 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 04:46:57.047272 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 04:46:57.051159 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 04:46:57.057035 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 04:46:57.061412 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 04:46:57.068053 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 04:46:57.070627 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 04:46:57.074167 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 04:46:57.080143 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 04:46:57.084463 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 04:46:57.087121 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 04:46:57.093941 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 04:46:57.097358 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 04:46:57.100797 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 04:46:57.107233 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 04:46:57.110437 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 04:46:57.113482 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 04:46:57.116986 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 04:46:57.123654 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 04:46:57.130491 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 04:46:57.141333 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 04:46:57.143954 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 04:46:57.150489 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 04:46:57.160461 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 04:46:57.163902 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 04:46:57.170221 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 04:46:57.173431 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 04:46:57.181062 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
534 04:46:57.187892 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 04:46:57.190611 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 04:46:57.193367 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 04:46:57.205161 [RTC]rtc_get_frequency_meter,154: input=15, output=764
538 04:46:57.214439 [RTC]rtc_get_frequency_meter,154: input=23, output=948
539 04:46:57.224577 [RTC]rtc_get_frequency_meter,154: input=19, output=857
540 04:46:57.233061 [RTC]rtc_get_frequency_meter,154: input=17, output=810
541 04:46:57.243200 [RTC]rtc_get_frequency_meter,154: input=16, output=787
542 04:46:57.252862 [RTC]rtc_get_frequency_meter,154: input=16, output=787
543 04:46:57.261788 [RTC]rtc_get_frequency_meter,154: input=17, output=811
544 04:46:57.265007 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 04:46:57.272502 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 04:46:57.275497 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 04:46:57.278834 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 04:46:57.285692 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 04:46:57.289426 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 04:46:57.293289 ADC[4]: Raw value=670063 ID=5
551 04:46:57.293828 ADC[3]: Raw value=212549 ID=1
552 04:46:57.295752 RAM Code: 0x51
553 04:46:57.298893 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 04:46:57.305347 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 04:46:57.312566 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
556 04:46:57.318744 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
557 04:46:57.321790 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 04:46:57.326770 in-header: 03 07 00 00 08 00 00 00
559 04:46:57.328757 in-data: aa e4 47 04 13 02 00 00
560 04:46:57.332009 Chrome EC: UHEPI supported
561 04:46:57.338688 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 04:46:57.341889 in-header: 03 d5 00 00 08 00 00 00
563 04:46:57.346175 in-data: 98 20 60 08 00 00 00 00
564 04:46:57.348321 MRC: failed to locate region type 0.
565 04:46:57.355293 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 04:46:57.358784 DRAM-K: Running full calibration
567 04:46:57.362089 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
568 04:46:57.365107 header.status = 0x0
569 04:46:57.368555 header.version = 0x6 (expected: 0x6)
570 04:46:57.372300 header.size = 0xd00 (expected: 0xd00)
571 04:46:57.375853 header.flags = 0x0
572 04:46:57.378485 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 04:46:57.397017 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 04:46:57.403626 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 04:46:57.406922 dram_init: ddr_geometry: 0
576 04:46:57.410427 [EMI] MDL number = 0
577 04:46:57.410930 [EMI] Get MDL freq = 0
578 04:46:57.413691 dram_init: ddr_type: 0
579 04:46:57.414135 is_discrete_lpddr4: 1
580 04:46:57.417661 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 04:46:57.418180
582 04:46:57.418561
583 04:46:57.420953 [Bian_co] ETT version 0.0.0.1
584 04:46:57.424439 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
585 04:46:57.427830
586 04:46:57.431257 dramc_set_vcore_voltage set vcore to 650000
587 04:46:57.431799 Read voltage for 800, 4
588 04:46:57.434198 Vio18 = 0
589 04:46:57.434739 Vcore = 650000
590 04:46:57.435187 Vdram = 0
591 04:46:57.438106 Vddq = 0
592 04:46:57.438534 Vmddr = 0
593 04:46:57.440966 dram_init: config_dvfs: 1
594 04:46:57.444344 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 04:46:57.451118 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 04:46:57.454211 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 04:46:57.457375 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 04:46:57.461450 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 04:46:57.464851 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 04:46:57.467292 MEM_TYPE=3, freq_sel=18
601 04:46:57.470852 sv_algorithm_assistance_LP4_1600
602 04:46:57.474460 ============ PULL DRAM RESETB DOWN ============
603 04:46:57.477865 ========== PULL DRAM RESETB DOWN end =========
604 04:46:57.484754 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 04:46:57.487891 ===================================
606 04:46:57.488322 LPDDR4 DRAM CONFIGURATION
607 04:46:57.491527 ===================================
608 04:46:57.495119 EX_ROW_EN[0] = 0x0
609 04:46:57.497541 EX_ROW_EN[1] = 0x0
610 04:46:57.497974 LP4Y_EN = 0x0
611 04:46:57.501075 WORK_FSP = 0x0
612 04:46:57.501504 WL = 0x2
613 04:46:57.504450 RL = 0x2
614 04:46:57.505037 BL = 0x2
615 04:46:57.507702 RPST = 0x0
616 04:46:57.508180 RD_PRE = 0x0
617 04:46:57.511165 WR_PRE = 0x1
618 04:46:57.511721 WR_PST = 0x0
619 04:46:57.514311 DBI_WR = 0x0
620 04:46:57.514784 DBI_RD = 0x0
621 04:46:57.518292 OTF = 0x1
622 04:46:57.520655 ===================================
623 04:46:57.524764 ===================================
624 04:46:57.525343 ANA top config
625 04:46:57.528414 ===================================
626 04:46:57.530959 DLL_ASYNC_EN = 0
627 04:46:57.534233 ALL_SLAVE_EN = 1
628 04:46:57.534803 NEW_RANK_MODE = 1
629 04:46:57.537792 DLL_IDLE_MODE = 1
630 04:46:57.540650 LP45_APHY_COMB_EN = 1
631 04:46:57.544082 TX_ODT_DIS = 1
632 04:46:57.547839 NEW_8X_MODE = 1
633 04:46:57.550991 ===================================
634 04:46:57.554271 ===================================
635 04:46:57.554748 data_rate = 1600
636 04:46:57.558186 CKR = 1
637 04:46:57.561291 DQ_P2S_RATIO = 8
638 04:46:57.564195 ===================================
639 04:46:57.567252 CA_P2S_RATIO = 8
640 04:46:57.571259 DQ_CA_OPEN = 0
641 04:46:57.574919 DQ_SEMI_OPEN = 0
642 04:46:57.575498 CA_SEMI_OPEN = 0
643 04:46:57.577636 CA_FULL_RATE = 0
644 04:46:57.582138 DQ_CKDIV4_EN = 1
645 04:46:57.584481 CA_CKDIV4_EN = 1
646 04:46:57.587848 CA_PREDIV_EN = 0
647 04:46:57.591340 PH8_DLY = 0
648 04:46:57.591815 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 04:46:57.594407 DQ_AAMCK_DIV = 4
650 04:46:57.597720 CA_AAMCK_DIV = 4
651 04:46:57.600860 CA_ADMCK_DIV = 4
652 04:46:57.604297 DQ_TRACK_CA_EN = 0
653 04:46:57.607571 CA_PICK = 800
654 04:46:57.608052 CA_MCKIO = 800
655 04:46:57.611006 MCKIO_SEMI = 0
656 04:46:57.614678 PLL_FREQ = 3068
657 04:46:57.618810 DQ_UI_PI_RATIO = 32
658 04:46:57.620681 CA_UI_PI_RATIO = 0
659 04:46:57.624880 ===================================
660 04:46:57.627556 ===================================
661 04:46:57.631273 memory_type:LPDDR4
662 04:46:57.631742 GP_NUM : 10
663 04:46:57.634913 SRAM_EN : 1
664 04:46:57.635482 MD32_EN : 0
665 04:46:57.637783 ===================================
666 04:46:57.640797 [ANA_INIT] >>>>>>>>>>>>>>
667 04:46:57.644474 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 04:46:57.647391 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 04:46:57.651258 ===================================
670 04:46:57.654180 data_rate = 1600,PCW = 0X7600
671 04:46:57.657638 ===================================
672 04:46:57.661080 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 04:46:57.664585 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 04:46:57.670813 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 04:46:57.674857 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 04:46:57.677425 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 04:46:57.684281 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 04:46:57.684797 [ANA_INIT] flow start
679 04:46:57.688176 [ANA_INIT] PLL >>>>>>>>
680 04:46:57.688823 [ANA_INIT] PLL <<<<<<<<
681 04:46:57.691644 [ANA_INIT] MIDPI >>>>>>>>
682 04:46:57.694920 [ANA_INIT] MIDPI <<<<<<<<
683 04:46:57.698158 [ANA_INIT] DLL >>>>>>>>
684 04:46:57.698798 [ANA_INIT] flow end
685 04:46:57.701193 ============ LP4 DIFF to SE enter ============
686 04:46:57.708054 ============ LP4 DIFF to SE exit ============
687 04:46:57.708666 [ANA_INIT] <<<<<<<<<<<<<
688 04:46:57.711156 [Flow] Enable top DCM control >>>>>
689 04:46:57.714957 [Flow] Enable top DCM control <<<<<
690 04:46:57.717287 Enable DLL master slave shuffle
691 04:46:57.724377 ==============================================================
692 04:46:57.724892 Gating Mode config
693 04:46:57.731196 ==============================================================
694 04:46:57.734831 Config description:
695 04:46:57.744824 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 04:46:57.750933 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 04:46:57.754323 SELPH_MODE 0: By rank 1: By Phase
698 04:46:57.761074 ==============================================================
699 04:46:57.764771 GAT_TRACK_EN = 1
700 04:46:57.765356 RX_GATING_MODE = 2
701 04:46:57.768459 RX_GATING_TRACK_MODE = 2
702 04:46:57.771471 SELPH_MODE = 1
703 04:46:57.774176 PICG_EARLY_EN = 1
704 04:46:57.777518 VALID_LAT_VALUE = 1
705 04:46:57.784464 ==============================================================
706 04:46:57.787861 Enter into Gating configuration >>>>
707 04:46:57.791361 Exit from Gating configuration <<<<
708 04:46:57.794008 Enter into DVFS_PRE_config >>>>>
709 04:46:57.804396 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 04:46:57.807362 Exit from DVFS_PRE_config <<<<<
711 04:46:57.810511 Enter into PICG configuration >>>>
712 04:46:57.814739 Exit from PICG configuration <<<<
713 04:46:57.818176 [RX_INPUT] configuration >>>>>
714 04:46:57.820555 [RX_INPUT] configuration <<<<<
715 04:46:57.824072 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 04:46:57.831864 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 04:46:57.837387 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 04:46:57.841328 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 04:46:57.847199 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 04:46:57.853462 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 04:46:57.857870 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 04:46:57.863414 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 04:46:57.867540 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 04:46:57.870415 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 04:46:57.874481 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 04:46:57.880951 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 04:46:57.883621 ===================================
728 04:46:57.884166 LPDDR4 DRAM CONFIGURATION
729 04:46:57.887182 ===================================
730 04:46:57.890566 EX_ROW_EN[0] = 0x0
731 04:46:57.894426 EX_ROW_EN[1] = 0x0
732 04:46:57.895004 LP4Y_EN = 0x0
733 04:46:57.897262 WORK_FSP = 0x0
734 04:46:57.897726 WL = 0x2
735 04:46:57.900414 RL = 0x2
736 04:46:57.900930 BL = 0x2
737 04:46:57.903987 RPST = 0x0
738 04:46:57.904598 RD_PRE = 0x0
739 04:46:57.907164 WR_PRE = 0x1
740 04:46:57.907627 WR_PST = 0x0
741 04:46:57.910859 DBI_WR = 0x0
742 04:46:57.911324 DBI_RD = 0x0
743 04:46:57.913654 OTF = 0x1
744 04:46:57.918669 ===================================
745 04:46:57.920568 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 04:46:57.924618 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 04:46:57.930896 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 04:46:57.933614 ===================================
749 04:46:57.934418 LPDDR4 DRAM CONFIGURATION
750 04:46:57.940526 ===================================
751 04:46:57.941233 EX_ROW_EN[0] = 0x10
752 04:46:57.941887 EX_ROW_EN[1] = 0x0
753 04:46:57.943765 LP4Y_EN = 0x0
754 04:46:57.944493 WORK_FSP = 0x0
755 04:46:57.947149 WL = 0x2
756 04:46:57.947714 RL = 0x2
757 04:46:57.951547 BL = 0x2
758 04:46:57.952136 RPST = 0x0
759 04:46:57.954684 RD_PRE = 0x0
760 04:46:57.957232 WR_PRE = 0x1
761 04:46:57.957796 WR_PST = 0x0
762 04:46:57.960458 DBI_WR = 0x0
763 04:46:57.960984 DBI_RD = 0x0
764 04:46:57.963783 OTF = 0x1
765 04:46:57.967075 ===================================
766 04:46:57.970737 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 04:46:57.976503 nWR fixed to 40
768 04:46:57.980151 [ModeRegInit_LP4] CH0 RK0
769 04:46:57.980827 [ModeRegInit_LP4] CH0 RK1
770 04:46:57.982876 [ModeRegInit_LP4] CH1 RK0
771 04:46:57.986602 [ModeRegInit_LP4] CH1 RK1
772 04:46:57.987108 match AC timing 12
773 04:46:57.992555 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
774 04:46:57.995481 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 04:46:57.999427 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 04:46:58.006052 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 04:46:58.008870 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 04:46:58.011893 [EMI DOE] emi_dcm 0
779 04:46:58.015380 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 04:46:58.015849 ==
781 04:46:58.019176 Dram Type= 6, Freq= 0, CH_0, rank 0
782 04:46:58.022077 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
783 04:46:58.022648 ==
784 04:46:58.028422 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 04:46:58.035411 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 04:46:58.043468 [CA 0] Center 37 (7~68) winsize 62
787 04:46:58.046488 [CA 1] Center 37 (7~68) winsize 62
788 04:46:58.049452 [CA 2] Center 35 (5~66) winsize 62
789 04:46:58.052939 [CA 3] Center 35 (5~66) winsize 62
790 04:46:58.056303 [CA 4] Center 34 (4~65) winsize 62
791 04:46:58.059664 [CA 5] Center 33 (3~64) winsize 62
792 04:46:58.060232
793 04:46:58.063275 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 04:46:58.063750
795 04:46:58.066661 [CATrainingPosCal] consider 1 rank data
796 04:46:58.069634 u2DelayCellTimex100 = 270/100 ps
797 04:46:58.072905 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 04:46:58.076448 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
799 04:46:58.083523 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
800 04:46:58.086274 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
801 04:46:58.089695 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
802 04:46:58.092761 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 04:46:58.093236
804 04:46:58.096364 CA PerBit enable=1, Macro0, CA PI delay=33
805 04:46:58.097030
806 04:46:58.099914 [CBTSetCACLKResult] CA Dly = 33
807 04:46:58.100481 CS Dly: 5 (0~36)
808 04:46:58.103164 ==
809 04:46:58.103735 Dram Type= 6, Freq= 0, CH_0, rank 1
810 04:46:58.109628 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
811 04:46:58.110237 ==
812 04:46:58.113225 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 04:46:58.119437 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 04:46:58.129136 [CA 0] Center 37 (6~68) winsize 63
815 04:46:58.133466 [CA 1] Center 37 (6~68) winsize 63
816 04:46:58.136246 [CA 2] Center 35 (4~66) winsize 63
817 04:46:58.139619 [CA 3] Center 34 (4~65) winsize 62
818 04:46:58.142576 [CA 4] Center 33 (3~64) winsize 62
819 04:46:58.145486 [CA 5] Center 33 (3~64) winsize 62
820 04:46:58.145976
821 04:46:58.149070 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 04:46:58.149541
823 04:46:58.152939 [CATrainingPosCal] consider 2 rank data
824 04:46:58.155659 u2DelayCellTimex100 = 270/100 ps
825 04:46:58.158914 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 04:46:58.162386 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 04:46:58.169416 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
828 04:46:58.172776 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
829 04:46:58.175638 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
830 04:46:58.178915 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 04:46:58.179487
832 04:46:58.182046 CA PerBit enable=1, Macro0, CA PI delay=33
833 04:46:58.182515
834 04:46:58.185924 [CBTSetCACLKResult] CA Dly = 33
835 04:46:58.186467 CS Dly: 6 (0~38)
836 04:46:58.189017
837 04:46:58.192796 ----->DramcWriteLeveling(PI) begin...
838 04:46:58.193356 ==
839 04:46:58.195743 Dram Type= 6, Freq= 0, CH_0, rank 0
840 04:46:58.199411 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
841 04:46:58.199960 ==
842 04:46:58.202617 Write leveling (Byte 0): 28 => 28
843 04:46:58.205461 Write leveling (Byte 1): 28 => 28
844 04:46:58.209064 DramcWriteLeveling(PI) end<-----
845 04:46:58.209612
846 04:46:58.210037 ==
847 04:46:58.212149 Dram Type= 6, Freq= 0, CH_0, rank 0
848 04:46:58.215238 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
849 04:46:58.215714 ==
850 04:46:58.219180 [Gating] SW mode calibration
851 04:46:58.225379 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 04:46:58.232100 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 04:46:58.235543 0 6 0 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
854 04:46:58.238952 0 6 4 | B1->B0 | 2929 2828 | 0 0 | (1 0) (0 0)
855 04:46:58.245078 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 04:46:58.248682 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 04:46:58.252027 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 04:46:58.258948 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 04:46:58.262418 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 04:46:58.266021 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 04:46:58.269275 0 7 0 | B1->B0 | 2626 2e2e | 0 1 | (0 0) (0 0)
862 04:46:58.275678 0 7 4 | B1->B0 | 3f3f 4040 | 1 1 | (0 0) (0 0)
863 04:46:58.278326 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 04:46:58.282010 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 04:46:58.288600 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 04:46:58.292426 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 04:46:58.295920 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 04:46:58.301788 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 04:46:58.305567 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
870 04:46:58.308908 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
871 04:46:58.315163 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 04:46:58.318692 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 04:46:58.322795 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 04:46:58.329470 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 04:46:58.331662 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 04:46:58.335619 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 04:46:58.342160 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 04:46:58.345264 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 04:46:58.349332 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 04:46:58.354917 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 04:46:58.359240 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 04:46:58.361670 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 04:46:58.365048 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 04:46:58.371591 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 04:46:58.376157 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
886 04:46:58.378936 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 04:46:58.381971 Total UI for P1: 0, mck2ui 16
888 04:46:58.385504 best dqsien dly found for B0: ( 0, 10, 2)
889 04:46:58.388258 Total UI for P1: 0, mck2ui 16
890 04:46:58.391891 best dqsien dly found for B1: ( 0, 10, 0)
891 04:46:58.395459 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
892 04:46:58.398701 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
893 04:46:58.399273
894 04:46:58.405899 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
895 04:46:58.409399 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
896 04:46:58.412239 [Gating] SW calibration Done
897 04:46:58.412912 ==
898 04:46:58.413485 Dram Type= 6, Freq= 0, CH_0, rank 0
899 04:46:58.419362 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 04:46:58.419839 ==
901 04:46:58.420208 RX Vref Scan: 0
902 04:46:58.420553
903 04:46:58.422669 RX Vref 0 -> 0, step: 1
904 04:46:58.423140
905 04:46:58.426799 RX Delay -130 -> 252, step: 16
906 04:46:58.429086 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
907 04:46:58.432587 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
908 04:46:58.435699 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
909 04:46:58.442290 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
910 04:46:58.445487 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
911 04:46:58.448777 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
912 04:46:58.453197 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
913 04:46:58.456105 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
914 04:46:58.462305 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
915 04:46:58.465528 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
916 04:46:58.469022 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
917 04:46:58.472428 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
918 04:46:58.475794 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
919 04:46:58.482914 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
920 04:46:58.486667 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
921 04:46:58.490248 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
922 04:46:58.490800 ==
923 04:46:58.493283 Dram Type= 6, Freq= 0, CH_0, rank 0
924 04:46:58.496532 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
925 04:46:58.497107 ==
926 04:46:58.499552 DQS Delay:
927 04:46:58.500117 DQS0 = 0, DQS1 = 0
928 04:46:58.502709 DQM Delay:
929 04:46:58.503278 DQM0 = 84, DQM1 = 74
930 04:46:58.503650 DQ Delay:
931 04:46:58.506093 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
932 04:46:58.509592 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
933 04:46:58.512342 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
934 04:46:58.515569 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
935 04:46:58.516139
936 04:46:58.516516
937 04:46:58.519149 ==
938 04:46:58.522449 Dram Type= 6, Freq= 0, CH_0, rank 0
939 04:46:58.526100 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
940 04:46:58.526572 ==
941 04:46:58.526942
942 04:46:58.527284
943 04:46:58.529489 TX Vref Scan disable
944 04:46:58.529952 == TX Byte 0 ==
945 04:46:58.532519 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
946 04:46:58.538999 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
947 04:46:58.539577 == TX Byte 1 ==
948 04:46:58.542769 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
949 04:46:58.548834 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
950 04:46:58.549304 ==
951 04:46:58.552359 Dram Type= 6, Freq= 0, CH_0, rank 0
952 04:46:58.555539 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
953 04:46:58.556108 ==
954 04:46:58.568598 TX Vref=22, minBit 0, minWin=27, winSum=442
955 04:46:58.571695 TX Vref=24, minBit 2, minWin=27, winSum=445
956 04:46:58.575458 TX Vref=26, minBit 0, minWin=28, winSum=450
957 04:46:58.579683 TX Vref=28, minBit 0, minWin=28, winSum=453
958 04:46:58.582620 TX Vref=30, minBit 1, minWin=28, winSum=455
959 04:46:58.585603 TX Vref=32, minBit 0, minWin=27, winSum=451
960 04:46:58.592066 [TxChooseVref] Worse bit 1, Min win 28, Win sum 455, Final Vref 30
961 04:46:58.592633
962 04:46:58.596242 Final TX Range 1 Vref 30
963 04:46:58.596856
964 04:46:58.597233 ==
965 04:46:58.598752 Dram Type= 6, Freq= 0, CH_0, rank 0
966 04:46:58.602566 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
967 04:46:58.603138 ==
968 04:46:58.603514
969 04:46:58.605117
970 04:46:58.605580 TX Vref Scan disable
971 04:46:58.608928 == TX Byte 0 ==
972 04:46:58.611836 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
973 04:46:58.618810 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
974 04:46:58.619390 == TX Byte 1 ==
975 04:46:58.621596 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
976 04:46:58.628600 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
977 04:46:58.629214
978 04:46:58.629614 [DATLAT]
979 04:46:58.629968 Freq=800, CH0 RK0
980 04:46:58.630303
981 04:46:58.632264 DATLAT Default: 0xa
982 04:46:58.632767 0, 0xFFFF, sum = 0
983 04:46:58.635727 1, 0xFFFF, sum = 0
984 04:46:58.636429 2, 0xFFFF, sum = 0
985 04:46:58.638751 3, 0xFFFF, sum = 0
986 04:46:58.639223 4, 0xFFFF, sum = 0
987 04:46:58.642043 5, 0xFFFF, sum = 0
988 04:46:58.645114 6, 0xFFFF, sum = 0
989 04:46:58.645603 7, 0xFFFF, sum = 0
990 04:46:58.645982 8, 0x0, sum = 1
991 04:46:58.648171 9, 0x0, sum = 2
992 04:46:58.648639 10, 0x0, sum = 3
993 04:46:58.651522 11, 0x0, sum = 4
994 04:46:58.652180 best_step = 9
995 04:46:58.652641
996 04:46:58.653052 ==
997 04:46:58.655208 Dram Type= 6, Freq= 0, CH_0, rank 0
998 04:46:58.661960 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
999 04:46:58.662515 ==
1000 04:46:58.662891 RX Vref Scan: 1
1001 04:46:58.663237
1002 04:46:58.664607 Set Vref Range= 32 -> 127
1003 04:46:58.665133
1004 04:46:58.668422 RX Vref 32 -> 127, step: 1
1005 04:46:58.668925
1006 04:46:58.671526 RX Delay -111 -> 252, step: 8
1007 04:46:58.672066
1008 04:46:58.675809 Set Vref, RX VrefLevel [Byte0]: 32
1009 04:46:58.676379 [Byte1]: 32
1010 04:46:58.679689
1011 04:46:58.680265 Set Vref, RX VrefLevel [Byte0]: 33
1012 04:46:58.682669 [Byte1]: 33
1013 04:46:58.687210
1014 04:46:58.687847 Set Vref, RX VrefLevel [Byte0]: 34
1015 04:46:58.691011 [Byte1]: 34
1016 04:46:58.695178
1017 04:46:58.695741 Set Vref, RX VrefLevel [Byte0]: 35
1018 04:46:58.698451 [Byte1]: 35
1019 04:46:58.702610
1020 04:46:58.703071 Set Vref, RX VrefLevel [Byte0]: 36
1021 04:46:58.706031 [Byte1]: 36
1022 04:46:58.710288
1023 04:46:58.710853 Set Vref, RX VrefLevel [Byte0]: 37
1024 04:46:58.714263 [Byte1]: 37
1025 04:46:58.717572
1026 04:46:58.718029 Set Vref, RX VrefLevel [Byte0]: 38
1027 04:46:58.721201 [Byte1]: 38
1028 04:46:58.725308
1029 04:46:58.725860 Set Vref, RX VrefLevel [Byte0]: 39
1030 04:46:58.728433 [Byte1]: 39
1031 04:46:58.732836
1032 04:46:58.733297 Set Vref, RX VrefLevel [Byte0]: 40
1033 04:46:58.736553 [Byte1]: 40
1034 04:46:58.740773
1035 04:46:58.741319 Set Vref, RX VrefLevel [Byte0]: 41
1036 04:46:58.744240 [Byte1]: 41
1037 04:46:58.748067
1038 04:46:58.748749 Set Vref, RX VrefLevel [Byte0]: 42
1039 04:46:58.751895 [Byte1]: 42
1040 04:46:58.756383
1041 04:46:58.756980 Set Vref, RX VrefLevel [Byte0]: 43
1042 04:46:58.759021 [Byte1]: 43
1043 04:46:58.763170
1044 04:46:58.763628 Set Vref, RX VrefLevel [Byte0]: 44
1045 04:46:58.767905 [Byte1]: 44
1046 04:46:58.770793
1047 04:46:58.771253 Set Vref, RX VrefLevel [Byte0]: 45
1048 04:46:58.774309 [Byte1]: 45
1049 04:46:58.779181
1050 04:46:58.779759 Set Vref, RX VrefLevel [Byte0]: 46
1051 04:46:58.782120 [Byte1]: 46
1052 04:46:58.786184
1053 04:46:58.786641 Set Vref, RX VrefLevel [Byte0]: 47
1054 04:46:58.789765 [Byte1]: 47
1055 04:46:58.794275
1056 04:46:58.794804 Set Vref, RX VrefLevel [Byte0]: 48
1057 04:46:58.797364 [Byte1]: 48
1058 04:46:58.802828
1059 04:46:58.803360 Set Vref, RX VrefLevel [Byte0]: 49
1060 04:46:58.805371 [Byte1]: 49
1061 04:46:58.809738
1062 04:46:58.810269 Set Vref, RX VrefLevel [Byte0]: 50
1063 04:46:58.812527 [Byte1]: 50
1064 04:46:58.817162
1065 04:46:58.817617 Set Vref, RX VrefLevel [Byte0]: 51
1066 04:46:58.820907 [Byte1]: 51
1067 04:46:58.825462
1068 04:46:58.826021 Set Vref, RX VrefLevel [Byte0]: 52
1069 04:46:58.828337 [Byte1]: 52
1070 04:46:58.832236
1071 04:46:58.832850 Set Vref, RX VrefLevel [Byte0]: 53
1072 04:46:58.836433 [Byte1]: 53
1073 04:46:58.840321
1074 04:46:58.840928 Set Vref, RX VrefLevel [Byte0]: 54
1075 04:46:58.843632 [Byte1]: 54
1076 04:46:58.847317
1077 04:46:58.847772 Set Vref, RX VrefLevel [Byte0]: 55
1078 04:46:58.851713 [Byte1]: 55
1079 04:46:58.855469
1080 04:46:58.856071 Set Vref, RX VrefLevel [Byte0]: 56
1081 04:46:58.858425 [Byte1]: 56
1082 04:46:58.862868
1083 04:46:58.863414 Set Vref, RX VrefLevel [Byte0]: 57
1084 04:46:58.865960 [Byte1]: 57
1085 04:46:58.870698
1086 04:46:58.871154 Set Vref, RX VrefLevel [Byte0]: 58
1087 04:46:58.873766 [Byte1]: 58
1088 04:46:58.878325
1089 04:46:58.878865 Set Vref, RX VrefLevel [Byte0]: 59
1090 04:46:58.881323 [Byte1]: 59
1091 04:46:58.886740
1092 04:46:58.887202 Set Vref, RX VrefLevel [Byte0]: 60
1093 04:46:58.889862 [Byte1]: 60
1094 04:46:58.893563
1095 04:46:58.894024 Set Vref, RX VrefLevel [Byte0]: 61
1096 04:46:58.897032 [Byte1]: 61
1097 04:46:58.901575
1098 04:46:58.902163 Set Vref, RX VrefLevel [Byte0]: 62
1099 04:46:58.904346 [Byte1]: 62
1100 04:46:58.909151
1101 04:46:58.909611 Set Vref, RX VrefLevel [Byte0]: 63
1102 04:46:58.912060 [Byte1]: 63
1103 04:46:58.916858
1104 04:46:58.917323 Set Vref, RX VrefLevel [Byte0]: 64
1105 04:46:58.919820 [Byte1]: 64
1106 04:46:58.924141
1107 04:46:58.924771 Set Vref, RX VrefLevel [Byte0]: 65
1108 04:46:58.927288 [Byte1]: 65
1109 04:46:58.932428
1110 04:46:58.932913 Set Vref, RX VrefLevel [Byte0]: 66
1111 04:46:58.934943 [Byte1]: 66
1112 04:46:58.940680
1113 04:46:58.941279 Set Vref, RX VrefLevel [Byte0]: 67
1114 04:46:58.942426 [Byte1]: 67
1115 04:46:58.946950
1116 04:46:58.947489 Set Vref, RX VrefLevel [Byte0]: 68
1117 04:46:58.955322 [Byte1]: 68
1118 04:46:58.955879
1119 04:46:58.957191 Set Vref, RX VrefLevel [Byte0]: 69
1120 04:46:58.960293 [Byte1]: 69
1121 04:46:58.961028
1122 04:46:58.963570 Set Vref, RX VrefLevel [Byte0]: 70
1123 04:46:58.966798 [Byte1]: 70
1124 04:46:58.967360
1125 04:46:58.970477 Set Vref, RX VrefLevel [Byte0]: 71
1126 04:46:58.973376 [Byte1]: 71
1127 04:46:58.977808
1128 04:46:58.978368 Set Vref, RX VrefLevel [Byte0]: 72
1129 04:46:58.981399 [Byte1]: 72
1130 04:46:58.985977
1131 04:46:58.986531 Set Vref, RX VrefLevel [Byte0]: 73
1132 04:46:58.988540 [Byte1]: 73
1133 04:46:58.992594
1134 04:46:58.993090 Set Vref, RX VrefLevel [Byte0]: 74
1135 04:46:58.996093 [Byte1]: 74
1136 04:46:59.001622
1137 04:46:59.002331 Set Vref, RX VrefLevel [Byte0]: 75
1138 04:46:59.003690 [Byte1]: 75
1139 04:46:59.008096
1140 04:46:59.008650 Final RX Vref Byte 0 = 52 to rank0
1141 04:46:59.011620 Final RX Vref Byte 1 = 56 to rank0
1142 04:46:59.015510 Final RX Vref Byte 0 = 52 to rank1
1143 04:46:59.018280 Final RX Vref Byte 1 = 56 to rank1==
1144 04:46:59.021386 Dram Type= 6, Freq= 0, CH_0, rank 0
1145 04:46:59.028527 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1146 04:46:59.029158 ==
1147 04:46:59.029533 DQS Delay:
1148 04:46:59.029872 DQS0 = 0, DQS1 = 0
1149 04:46:59.031746 DQM Delay:
1150 04:46:59.032200 DQM0 = 83, DQM1 = 74
1151 04:46:59.034886 DQ Delay:
1152 04:46:59.039210 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1153 04:46:59.039768 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1154 04:46:59.041277 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1155 04:46:59.048465 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1156 04:46:59.048994
1157 04:46:59.049365
1158 04:46:59.056040 [DQSOSCAuto] RK0, (LSB)MR18= 0x3737, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1159 04:46:59.058749 CH0 RK0: MR19=606, MR18=3737
1160 04:46:59.065257 CH0_RK0: MR19=0x606, MR18=0x3737, DQSOSC=395, MR23=63, INC=94, DEC=63
1161 04:46:59.065806
1162 04:46:59.068112 ----->DramcWriteLeveling(PI) begin...
1163 04:46:59.068770 ==
1164 04:46:59.072003 Dram Type= 6, Freq= 0, CH_0, rank 1
1165 04:46:59.074650 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1166 04:46:59.075112 ==
1167 04:46:59.078109 Write leveling (Byte 0): 28 => 28
1168 04:46:59.081169 Write leveling (Byte 1): 28 => 28
1169 04:46:59.084671 DramcWriteLeveling(PI) end<-----
1170 04:46:59.085155
1171 04:46:59.085520 ==
1172 04:46:59.087990 Dram Type= 6, Freq= 0, CH_0, rank 1
1173 04:46:59.091407 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1174 04:46:59.091873 ==
1175 04:46:59.094561 [Gating] SW mode calibration
1176 04:46:59.102485 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1177 04:46:59.108088 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1178 04:46:59.111952 0 6 0 | B1->B0 | 3434 3030 | 0 0 | (0 1) (0 0)
1179 04:46:59.115064 0 6 4 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
1180 04:46:59.122246 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 04:46:59.124916 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 04:46:59.127971 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 04:46:59.134785 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 04:46:59.139189 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 04:46:59.142301 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 04:46:59.147803 0 7 0 | B1->B0 | 2d2d 3333 | 1 0 | (0 0) (0 0)
1187 04:46:59.151586 0 7 4 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1188 04:46:59.154655 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 04:46:59.161498 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 04:46:59.164765 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 04:46:59.168829 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 04:46:59.171335 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 04:46:59.178110 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 04:46:59.181444 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 04:46:59.184401 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1196 04:46:59.191476 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 04:46:59.195490 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 04:46:59.197495 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 04:46:59.204801 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 04:46:59.208385 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 04:46:59.211216 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 04:46:59.217825 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 04:46:59.221348 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 04:46:59.224757 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 04:46:59.231515 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 04:46:59.235127 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 04:46:59.237747 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 04:46:59.244274 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 04:46:59.247601 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 04:46:59.251106 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 04:46:59.258853 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 04:46:59.259412 Total UI for P1: 0, mck2ui 16
1213 04:46:59.264524 best dqsien dly found for B0: ( 0, 10, 2)
1214 04:46:59.265038 Total UI for P1: 0, mck2ui 16
1215 04:46:59.267520 best dqsien dly found for B1: ( 0, 10, 2)
1216 04:46:59.274327 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1217 04:46:59.278391 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
1218 04:46:59.278952
1219 04:46:59.280840 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1220 04:46:59.284694 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
1221 04:46:59.287786 [Gating] SW calibration Done
1222 04:46:59.288244 ==
1223 04:46:59.291614 Dram Type= 6, Freq= 0, CH_0, rank 1
1224 04:46:59.294747 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1225 04:46:59.295305 ==
1226 04:46:59.339037 RX Vref Scan: 0
1227 04:46:59.339705
1228 04:46:59.340132 RX Vref 0 -> 0, step: 1
1229 04:46:59.340643
1230 04:46:59.341148 RX Delay -130 -> 252, step: 16
1231 04:46:59.341994 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1232 04:46:59.342475 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1233 04:46:59.342921 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1234 04:46:59.343269 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1235 04:46:59.343587 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1236 04:46:59.343963 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1237 04:46:59.344285 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1238 04:46:59.344593 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1239 04:46:59.345037 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1240 04:46:59.359045 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1241 04:46:59.359687 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1242 04:46:59.360060 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1243 04:46:59.360802 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1244 04:46:59.362237 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1245 04:46:59.362695 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1246 04:46:59.365490 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1247 04:46:59.365998 ==
1248 04:46:59.369074 Dram Type= 6, Freq= 0, CH_0, rank 1
1249 04:46:59.372073 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1250 04:46:59.372531 ==
1251 04:46:59.375651 DQS Delay:
1252 04:46:59.376204 DQS0 = 0, DQS1 = 0
1253 04:46:59.379439 DQM Delay:
1254 04:46:59.380061 DQM0 = 82, DQM1 = 73
1255 04:46:59.380431 DQ Delay:
1256 04:46:59.381632 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =69
1257 04:46:59.385464 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
1258 04:46:59.388657 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1259 04:46:59.393443 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1260 04:46:59.394002
1261 04:46:59.394363
1262 04:46:59.395241 ==
1263 04:46:59.395626 Dram Type= 6, Freq= 0, CH_0, rank 1
1264 04:46:59.402944 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1265 04:46:59.403512 ==
1266 04:46:59.403879
1267 04:46:59.404217
1268 04:46:59.405066 TX Vref Scan disable
1269 04:46:59.405443 == TX Byte 0 ==
1270 04:46:59.408602 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1271 04:46:59.415318 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1272 04:46:59.415880 == TX Byte 1 ==
1273 04:46:59.418384 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1274 04:46:59.425139 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1275 04:46:59.425759 ==
1276 04:46:59.428527 Dram Type= 6, Freq= 0, CH_0, rank 1
1277 04:46:59.431821 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1278 04:46:59.432283 ==
1279 04:46:59.445070 TX Vref=22, minBit 0, minWin=27, winSum=445
1280 04:46:59.448212 TX Vref=24, minBit 0, minWin=27, winSum=450
1281 04:46:59.452200 TX Vref=26, minBit 3, minWin=27, winSum=451
1282 04:46:59.454919 TX Vref=28, minBit 2, minWin=28, winSum=454
1283 04:46:59.459085 TX Vref=30, minBit 2, minWin=28, winSum=459
1284 04:46:59.463239 TX Vref=32, minBit 2, minWin=28, winSum=457
1285 04:46:59.468656 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 30
1286 04:46:59.469152
1287 04:46:59.471760 Final TX Range 1 Vref 30
1288 04:46:59.472222
1289 04:46:59.472604 ==
1290 04:46:59.475890 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 04:46:59.478260 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1292 04:46:59.478911 ==
1293 04:46:59.479304
1294 04:46:59.481725
1295 04:46:59.482179 TX Vref Scan disable
1296 04:46:59.484697 == TX Byte 0 ==
1297 04:46:59.488534 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1298 04:46:59.492105 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1299 04:46:59.494960 == TX Byte 1 ==
1300 04:46:59.498544 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1301 04:46:59.501538 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1302 04:46:59.505069
1303 04:46:59.505628 [DATLAT]
1304 04:46:59.505996 Freq=800, CH0 RK1
1305 04:46:59.506341
1306 04:46:59.508568 DATLAT Default: 0x9
1307 04:46:59.509161 0, 0xFFFF, sum = 0
1308 04:46:59.511820 1, 0xFFFF, sum = 0
1309 04:46:59.512382 2, 0xFFFF, sum = 0
1310 04:46:59.515045 3, 0xFFFF, sum = 0
1311 04:46:59.515609 4, 0xFFFF, sum = 0
1312 04:46:59.517883 5, 0xFFFF, sum = 0
1313 04:46:59.518530 6, 0xFFFF, sum = 0
1314 04:46:59.521782 7, 0xFFFF, sum = 0
1315 04:46:59.522250 8, 0x0, sum = 1
1316 04:46:59.525858 9, 0x0, sum = 2
1317 04:46:59.526330 10, 0x0, sum = 3
1318 04:46:59.528110 11, 0x0, sum = 4
1319 04:46:59.528576 best_step = 9
1320 04:46:59.528996
1321 04:46:59.529417 ==
1322 04:46:59.531225 Dram Type= 6, Freq= 0, CH_0, rank 1
1323 04:46:59.538388 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1324 04:46:59.538990 ==
1325 04:46:59.539376 RX Vref Scan: 0
1326 04:46:59.539814
1327 04:46:59.541874 RX Vref 0 -> 0, step: 1
1328 04:46:59.542496
1329 04:46:59.544807 RX Delay -111 -> 252, step: 8
1330 04:46:59.547975 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1331 04:46:59.552073 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1332 04:46:59.558926 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1333 04:46:59.561529 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1334 04:46:59.564969 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1335 04:46:59.568513 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1336 04:46:59.571494 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1337 04:46:59.574950 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1338 04:46:59.581662 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1339 04:46:59.584687 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1340 04:46:59.588565 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1341 04:46:59.591446 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1342 04:46:59.594683 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1343 04:46:59.601696 iDelay=217, Bit 13, Center 80 (-31 ~ 192) 224
1344 04:46:59.605031 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1345 04:46:59.608862 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1346 04:46:59.609415 ==
1347 04:46:59.611624 Dram Type= 6, Freq= 0, CH_0, rank 1
1348 04:46:59.615960 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1349 04:46:59.618260 ==
1350 04:46:59.618974 DQS Delay:
1351 04:46:59.619371 DQS0 = 0, DQS1 = 0
1352 04:46:59.621040 DQM Delay:
1353 04:46:59.621498 DQM0 = 86, DQM1 = 74
1354 04:46:59.625090 DQ Delay:
1355 04:46:59.628227 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1356 04:46:59.628828 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1357 04:46:59.631253 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1358 04:46:59.634374 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1359 04:46:59.637900
1360 04:46:59.638354
1361 04:46:59.644314 [DQSOSCAuto] RK1, (LSB)MR18= 0x4040, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1362 04:46:59.648053 CH0 RK1: MR19=606, MR18=4040
1363 04:46:59.654724 CH0_RK1: MR19=0x606, MR18=0x4040, DQSOSC=393, MR23=63, INC=95, DEC=63
1364 04:46:59.655183 [RxdqsGatingPostProcess] freq 800
1365 04:46:59.660996 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1366 04:46:59.664917 Pre-setting of DQS Precalculation
1367 04:46:59.667872 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1368 04:46:59.672157 ==
1369 04:46:59.674301 Dram Type= 6, Freq= 0, CH_1, rank 0
1370 04:46:59.677613 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1371 04:46:59.677835 ==
1372 04:46:59.680578 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1373 04:46:59.687229 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1374 04:46:59.697294 [CA 0] Center 36 (6~67) winsize 62
1375 04:46:59.701426 [CA 1] Center 36 (6~67) winsize 62
1376 04:46:59.703806 [CA 2] Center 34 (4~65) winsize 62
1377 04:46:59.708182 [CA 3] Center 34 (4~65) winsize 62
1378 04:46:59.710628 [CA 4] Center 33 (3~64) winsize 62
1379 04:46:59.714668 [CA 5] Center 33 (2~64) winsize 63
1380 04:46:59.715308
1381 04:46:59.717914 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1382 04:46:59.718524
1383 04:46:59.721084 [CATrainingPosCal] consider 1 rank data
1384 04:46:59.724422 u2DelayCellTimex100 = 270/100 ps
1385 04:46:59.727325 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1386 04:46:59.731147 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1387 04:46:59.737780 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1388 04:46:59.740849 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1389 04:46:59.744029 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1390 04:46:59.747756 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
1391 04:46:59.748327
1392 04:46:59.751186 CA PerBit enable=1, Macro0, CA PI delay=33
1393 04:46:59.751745
1394 04:46:59.754248 [CBTSetCACLKResult] CA Dly = 33
1395 04:46:59.754807 CS Dly: 4 (0~35)
1396 04:46:59.757247 ==
1397 04:46:59.757703 Dram Type= 6, Freq= 0, CH_1, rank 1
1398 04:46:59.764413 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1399 04:46:59.765032 ==
1400 04:46:59.767272 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1401 04:46:59.774075 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1402 04:46:59.783433 [CA 0] Center 36 (6~67) winsize 62
1403 04:46:59.786426 [CA 1] Center 36 (5~67) winsize 63
1404 04:46:59.790072 [CA 2] Center 34 (4~65) winsize 62
1405 04:46:59.793680 [CA 3] Center 33 (3~64) winsize 62
1406 04:46:59.796545 [CA 4] Center 33 (2~64) winsize 63
1407 04:46:59.799570 [CA 5] Center 33 (3~63) winsize 61
1408 04:46:59.800022
1409 04:46:59.803069 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1410 04:46:59.803628
1411 04:46:59.806661 [CATrainingPosCal] consider 2 rank data
1412 04:46:59.811472 u2DelayCellTimex100 = 270/100 ps
1413 04:46:59.813053 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1414 04:46:59.819376 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1415 04:46:59.822937 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1416 04:46:59.827122 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1417 04:46:59.829418 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1418 04:46:59.832991 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
1419 04:46:59.833552
1420 04:46:59.836232 CA PerBit enable=1, Macro0, CA PI delay=33
1421 04:46:59.836843
1422 04:46:59.840514 [CBTSetCACLKResult] CA Dly = 33
1423 04:46:59.841134 CS Dly: 4 (0~36)
1424 04:46:59.842878
1425 04:46:59.846560 ----->DramcWriteLeveling(PI) begin...
1426 04:46:59.847105 ==
1427 04:46:59.849346 Dram Type= 6, Freq= 0, CH_1, rank 0
1428 04:46:59.853286 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1429 04:46:59.853817 ==
1430 04:46:59.856077 Write leveling (Byte 0): 26 => 26
1431 04:46:59.859630 Write leveling (Byte 1): 27 => 27
1432 04:46:59.862768 DramcWriteLeveling(PI) end<-----
1433 04:46:59.863255
1434 04:46:59.863613 ==
1435 04:46:59.866882 Dram Type= 6, Freq= 0, CH_1, rank 0
1436 04:46:59.869475 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1437 04:46:59.869939 ==
1438 04:46:59.872862 [Gating] SW mode calibration
1439 04:46:59.879901 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1440 04:46:59.886008 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1441 04:46:59.890035 0 6 0 | B1->B0 | 2f2f 2626 | 1 0 | (1 0) (1 0)
1442 04:46:59.893087 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 04:46:59.895969 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 04:46:59.903501 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 04:46:59.906128 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 04:46:59.909536 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 04:46:59.916390 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 04:46:59.919423 0 6 28 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (0 0)
1449 04:46:59.922929 0 7 0 | B1->B0 | 2e2e 3c3c | 1 0 | (0 0) (0 0)
1450 04:46:59.930365 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1451 04:46:59.932771 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1452 04:46:59.936137 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1453 04:46:59.943379 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1454 04:46:59.946993 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1455 04:46:59.949419 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1456 04:46:59.956590 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1457 04:46:59.960279 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1458 04:46:59.963254 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1459 04:46:59.969323 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1460 04:46:59.972702 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1461 04:46:59.975971 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1462 04:46:59.982611 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1463 04:46:59.985979 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1464 04:46:59.990124 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1465 04:46:59.996458 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1466 04:47:00.000428 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1467 04:47:00.002623 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1468 04:47:00.005881 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1469 04:47:00.012490 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1470 04:47:00.015910 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1471 04:47:00.019212 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1472 04:47:00.025748 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1473 04:47:00.029181 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1474 04:47:00.032599 Total UI for P1: 0, mck2ui 16
1475 04:47:00.036252 best dqsien dly found for B0: ( 0, 9, 28)
1476 04:47:00.039739 Total UI for P1: 0, mck2ui 16
1477 04:47:00.042528 best dqsien dly found for B1: ( 0, 9, 28)
1478 04:47:00.045882 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1479 04:47:00.049154 best DQS1 dly(MCK, UI, PI) = (0, 9, 28)
1480 04:47:00.049611
1481 04:47:00.055000 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1482 04:47:00.058818 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 28)
1483 04:47:00.059280 [Gating] SW calibration Done
1484 04:47:00.059642 ==
1485 04:47:00.062621 Dram Type= 6, Freq= 0, CH_1, rank 0
1486 04:47:00.069111 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1487 04:47:00.069571 ==
1488 04:47:00.069930 RX Vref Scan: 0
1489 04:47:00.070260
1490 04:47:00.072259 RX Vref 0 -> 0, step: 1
1491 04:47:00.072775
1492 04:47:00.075549 RX Delay -130 -> 252, step: 16
1493 04:47:00.080385 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1494 04:47:00.082948 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1495 04:47:00.085448 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1496 04:47:00.092411 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1497 04:47:00.095652 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1498 04:47:00.099326 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1499 04:47:00.102748 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1500 04:47:00.105626 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1501 04:47:00.108696 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1502 04:47:00.116183 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1503 04:47:00.118804 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1504 04:47:00.123105 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1505 04:47:00.125541 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1506 04:47:00.132470 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1507 04:47:00.135704 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1508 04:47:00.139026 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1509 04:47:00.139582 ==
1510 04:47:00.142179 Dram Type= 6, Freq= 0, CH_1, rank 0
1511 04:47:00.146239 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1512 04:47:00.146854 ==
1513 04:47:00.148828 DQS Delay:
1514 04:47:00.149286 DQS0 = 0, DQS1 = 0
1515 04:47:00.153821 DQM Delay:
1516 04:47:00.154523 DQM0 = 81, DQM1 = 73
1517 04:47:00.154936 DQ Delay:
1518 04:47:00.155657 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1519 04:47:00.159587 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1520 04:47:00.164345 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1521 04:47:00.165585 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1522 04:47:00.166041
1523 04:47:00.166396
1524 04:47:00.166727 ==
1525 04:47:00.168863 Dram Type= 6, Freq= 0, CH_1, rank 0
1526 04:47:00.175857 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1527 04:47:00.176379 ==
1528 04:47:00.176769
1529 04:47:00.177114
1530 04:47:00.177437 TX Vref Scan disable
1531 04:47:00.179600 == TX Byte 0 ==
1532 04:47:00.183259 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1533 04:47:00.189676 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1534 04:47:00.190232 == TX Byte 1 ==
1535 04:47:00.192658 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1536 04:47:00.199495 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1537 04:47:00.200055 ==
1538 04:47:00.202972 Dram Type= 6, Freq= 0, CH_1, rank 0
1539 04:47:00.205502 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1540 04:47:00.205962 ==
1541 04:47:00.218610 TX Vref=22, minBit 8, minWin=27, winSum=445
1542 04:47:00.221477 TX Vref=24, minBit 8, minWin=27, winSum=447
1543 04:47:00.225678 TX Vref=26, minBit 8, minWin=27, winSum=447
1544 04:47:00.228179 TX Vref=28, minBit 0, minWin=28, winSum=451
1545 04:47:00.232120 TX Vref=30, minBit 2, minWin=28, winSum=455
1546 04:47:00.235291 TX Vref=32, minBit 8, minWin=27, winSum=450
1547 04:47:00.241407 [TxChooseVref] Worse bit 2, Min win 28, Win sum 455, Final Vref 30
1548 04:47:00.241867
1549 04:47:00.245216 Final TX Range 1 Vref 30
1550 04:47:00.245672
1551 04:47:00.246026 ==
1552 04:47:00.248637 Dram Type= 6, Freq= 0, CH_1, rank 0
1553 04:47:00.252523 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1554 04:47:00.253023 ==
1555 04:47:00.253388
1556 04:47:00.254958
1557 04:47:00.255409 TX Vref Scan disable
1558 04:47:00.258340 == TX Byte 0 ==
1559 04:47:00.261324 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1560 04:47:00.264770 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1561 04:47:00.268639 == TX Byte 1 ==
1562 04:47:00.271224 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1563 04:47:00.274769 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1564 04:47:00.275091
1565 04:47:00.278114 [DATLAT]
1566 04:47:00.278347 Freq=800, CH1 RK0
1567 04:47:00.278532
1568 04:47:00.282052 DATLAT Default: 0xa
1569 04:47:00.282238 0, 0xFFFF, sum = 0
1570 04:47:00.284701 1, 0xFFFF, sum = 0
1571 04:47:00.284870 2, 0xFFFF, sum = 0
1572 04:47:00.288580 3, 0xFFFF, sum = 0
1573 04:47:00.288749 4, 0xFFFF, sum = 0
1574 04:47:00.291785 5, 0xFFFF, sum = 0
1575 04:47:00.291919 6, 0xFFFF, sum = 0
1576 04:47:00.294898 7, 0xFFFF, sum = 0
1577 04:47:00.295015 8, 0x0, sum = 1
1578 04:47:00.297810 9, 0x0, sum = 2
1579 04:47:00.297927 10, 0x0, sum = 3
1580 04:47:00.301390 11, 0x0, sum = 4
1581 04:47:00.301507 best_step = 9
1582 04:47:00.301599
1583 04:47:00.301684 ==
1584 04:47:00.304457 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 04:47:00.308835 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1586 04:47:00.311577 ==
1587 04:47:00.311691 RX Vref Scan: 1
1588 04:47:00.311781
1589 04:47:00.314394 Set Vref Range= 32 -> 127
1590 04:47:00.314509
1591 04:47:00.318024 RX Vref 32 -> 127, step: 1
1592 04:47:00.318139
1593 04:47:00.318229 RX Delay -111 -> 252, step: 8
1594 04:47:00.318314
1595 04:47:00.321390 Set Vref, RX VrefLevel [Byte0]: 32
1596 04:47:00.324780 [Byte1]: 32
1597 04:47:00.329118
1598 04:47:00.329526 Set Vref, RX VrefLevel [Byte0]: 33
1599 04:47:00.332795 [Byte1]: 33
1600 04:47:00.336238
1601 04:47:00.336527 Set Vref, RX VrefLevel [Byte0]: 34
1602 04:47:00.339929 [Byte1]: 34
1603 04:47:00.344574
1604 04:47:00.344854 Set Vref, RX VrefLevel [Byte0]: 35
1605 04:47:00.350368 [Byte1]: 35
1606 04:47:00.350565
1607 04:47:00.354179 Set Vref, RX VrefLevel [Byte0]: 36
1608 04:47:00.357905 [Byte1]: 36
1609 04:47:00.358171
1610 04:47:00.360854 Set Vref, RX VrefLevel [Byte0]: 37
1611 04:47:00.364686 [Byte1]: 37
1612 04:47:00.364971
1613 04:47:00.367546 Set Vref, RX VrefLevel [Byte0]: 38
1614 04:47:00.370859 [Byte1]: 38
1615 04:47:00.375384
1616 04:47:00.375917 Set Vref, RX VrefLevel [Byte0]: 39
1617 04:47:00.377957 [Byte1]: 39
1618 04:47:00.382549
1619 04:47:00.383107 Set Vref, RX VrefLevel [Byte0]: 40
1620 04:47:00.386032 [Byte1]: 40
1621 04:47:00.390625
1622 04:47:00.391174 Set Vref, RX VrefLevel [Byte0]: 41
1623 04:47:00.393663 [Byte1]: 41
1624 04:47:00.397953
1625 04:47:00.398407 Set Vref, RX VrefLevel [Byte0]: 42
1626 04:47:00.401624 [Byte1]: 42
1627 04:47:00.405637
1628 04:47:00.406193 Set Vref, RX VrefLevel [Byte0]: 43
1629 04:47:00.409055 [Byte1]: 43
1630 04:47:00.413409
1631 04:47:00.413964 Set Vref, RX VrefLevel [Byte0]: 44
1632 04:47:00.417079 [Byte1]: 44
1633 04:47:00.421874
1634 04:47:00.422428 Set Vref, RX VrefLevel [Byte0]: 45
1635 04:47:00.424571 [Byte1]: 45
1636 04:47:00.428641
1637 04:47:00.429296 Set Vref, RX VrefLevel [Byte0]: 46
1638 04:47:00.431808 [Byte1]: 46
1639 04:47:00.436037
1640 04:47:00.436596 Set Vref, RX VrefLevel [Byte0]: 47
1641 04:47:00.439794 [Byte1]: 47
1642 04:47:00.444427
1643 04:47:00.445040 Set Vref, RX VrefLevel [Byte0]: 48
1644 04:47:00.447889 [Byte1]: 48
1645 04:47:00.451991
1646 04:47:00.452548 Set Vref, RX VrefLevel [Byte0]: 49
1647 04:47:00.454489 [Byte1]: 49
1648 04:47:00.459802
1649 04:47:00.460366 Set Vref, RX VrefLevel [Byte0]: 50
1650 04:47:00.462262 [Byte1]: 50
1651 04:47:00.467010
1652 04:47:00.467560 Set Vref, RX VrefLevel [Byte0]: 51
1653 04:47:00.469973 [Byte1]: 51
1654 04:47:00.474918
1655 04:47:00.475514 Set Vref, RX VrefLevel [Byte0]: 52
1656 04:47:00.477892 [Byte1]: 52
1657 04:47:00.482922
1658 04:47:00.483471 Set Vref, RX VrefLevel [Byte0]: 53
1659 04:47:00.485208 [Byte1]: 53
1660 04:47:00.489741
1661 04:47:00.490297 Set Vref, RX VrefLevel [Byte0]: 54
1662 04:47:00.492881 [Byte1]: 54
1663 04:47:00.497320
1664 04:47:00.497874 Set Vref, RX VrefLevel [Byte0]: 55
1665 04:47:00.501410 [Byte1]: 55
1666 04:47:00.505389
1667 04:47:00.505938 Set Vref, RX VrefLevel [Byte0]: 56
1668 04:47:00.508180 [Byte1]: 56
1669 04:47:00.512598
1670 04:47:00.515780 Set Vref, RX VrefLevel [Byte0]: 57
1671 04:47:00.519371 [Byte1]: 57
1672 04:47:00.519927
1673 04:47:00.522505 Set Vref, RX VrefLevel [Byte0]: 58
1674 04:47:00.525498 [Byte1]: 58
1675 04:47:00.525961
1676 04:47:00.528961 Set Vref, RX VrefLevel [Byte0]: 59
1677 04:47:00.532526 [Byte1]: 59
1678 04:47:00.536045
1679 04:47:00.536595 Set Vref, RX VrefLevel [Byte0]: 60
1680 04:47:00.539031 [Byte1]: 60
1681 04:47:00.543852
1682 04:47:00.544400 Set Vref, RX VrefLevel [Byte0]: 61
1683 04:47:00.546514 [Byte1]: 61
1684 04:47:00.550664
1685 04:47:00.551212 Set Vref, RX VrefLevel [Byte0]: 62
1686 04:47:00.554546 [Byte1]: 62
1687 04:47:00.558865
1688 04:47:00.559535 Set Vref, RX VrefLevel [Byte0]: 63
1689 04:47:00.561594 [Byte1]: 63
1690 04:47:00.566179
1691 04:47:00.566642 Set Vref, RX VrefLevel [Byte0]: 64
1692 04:47:00.569056 [Byte1]: 64
1693 04:47:00.573911
1694 04:47:00.574370 Set Vref, RX VrefLevel [Byte0]: 65
1695 04:47:00.577418 [Byte1]: 65
1696 04:47:00.581729
1697 04:47:00.582241 Set Vref, RX VrefLevel [Byte0]: 66
1698 04:47:00.585328 [Byte1]: 66
1699 04:47:00.589746
1700 04:47:00.590296 Set Vref, RX VrefLevel [Byte0]: 67
1701 04:47:00.592279 [Byte1]: 67
1702 04:47:00.597009
1703 04:47:00.597754 Set Vref, RX VrefLevel [Byte0]: 68
1704 04:47:00.600555 [Byte1]: 68
1705 04:47:00.604066
1706 04:47:00.604532 Set Vref, RX VrefLevel [Byte0]: 69
1707 04:47:00.607655 [Byte1]: 69
1708 04:47:00.612213
1709 04:47:00.612805 Set Vref, RX VrefLevel [Byte0]: 70
1710 04:47:00.615588 [Byte1]: 70
1711 04:47:00.619559
1712 04:47:00.620107 Set Vref, RX VrefLevel [Byte0]: 71
1713 04:47:00.622870 [Byte1]: 71
1714 04:47:00.626903
1715 04:47:00.627361 Set Vref, RX VrefLevel [Byte0]: 72
1716 04:47:00.630314 [Byte1]: 72
1717 04:47:00.635455
1718 04:47:00.636008 Set Vref, RX VrefLevel [Byte0]: 73
1719 04:47:00.638726 [Byte1]: 73
1720 04:47:00.642712
1721 04:47:00.643269 Set Vref, RX VrefLevel [Byte0]: 74
1722 04:47:00.646059 [Byte1]: 74
1723 04:47:00.650795
1724 04:47:00.651280 Set Vref, RX VrefLevel [Byte0]: 75
1725 04:47:00.653608 [Byte1]: 75
1726 04:47:00.658104
1727 04:47:00.658659 Final RX Vref Byte 0 = 59 to rank0
1728 04:47:00.661018 Final RX Vref Byte 1 = 52 to rank0
1729 04:47:00.664151 Final RX Vref Byte 0 = 59 to rank1
1730 04:47:00.667733 Final RX Vref Byte 1 = 52 to rank1==
1731 04:47:00.671076 Dram Type= 6, Freq= 0, CH_1, rank 0
1732 04:47:00.678076 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1733 04:47:00.678632 ==
1734 04:47:00.678991 DQS Delay:
1735 04:47:00.679327 DQS0 = 0, DQS1 = 0
1736 04:47:00.681006 DQM Delay:
1737 04:47:00.681458 DQM0 = 79, DQM1 = 72
1738 04:47:00.684669 DQ Delay:
1739 04:47:00.688038 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1740 04:47:00.690869 DQ4 =76, DQ5 =92, DQ6 =88, DQ7 =76
1741 04:47:00.694804 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1742 04:47:00.697767 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
1743 04:47:00.698321
1744 04:47:00.698685
1745 04:47:00.704869 [DQSOSCAuto] RK0, (LSB)MR18= 0x5656, (MSB)MR19= 0x606, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
1746 04:47:00.708261 CH1 RK0: MR19=606, MR18=5656
1747 04:47:00.714206 CH1_RK0: MR19=0x606, MR18=0x5656, DQSOSC=388, MR23=63, INC=98, DEC=65
1748 04:47:00.714762
1749 04:47:00.718139 ----->DramcWriteLeveling(PI) begin...
1750 04:47:00.718698 ==
1751 04:47:00.720849 Dram Type= 6, Freq= 0, CH_1, rank 1
1752 04:47:00.724197 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1753 04:47:00.724653 ==
1754 04:47:00.728063 Write leveling (Byte 0): 26 => 26
1755 04:47:00.731346 Write leveling (Byte 1): 26 => 26
1756 04:47:00.734715 DramcWriteLeveling(PI) end<-----
1757 04:47:00.735291
1758 04:47:00.735654 ==
1759 04:47:00.737564 Dram Type= 6, Freq= 0, CH_1, rank 1
1760 04:47:00.741137 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1761 04:47:00.741695 ==
1762 04:47:00.744272 [Gating] SW mode calibration
1763 04:47:00.750731 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1764 04:47:00.758095 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1765 04:47:00.761061 0 6 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
1766 04:47:00.764053 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1767 04:47:00.770630 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1768 04:47:00.774025 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1769 04:47:00.777264 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1770 04:47:00.784368 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1771 04:47:00.787267 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1772 04:47:00.791046 0 6 28 | B1->B0 | 2424 3131 | 1 0 | (0 0) (1 1)
1773 04:47:00.798841 0 7 0 | B1->B0 | 3838 4646 | 0 0 | (1 1) (0 0)
1774 04:47:00.801424 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1775 04:47:00.804188 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1776 04:47:00.811037 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1777 04:47:00.815011 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1778 04:47:00.817606 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1779 04:47:00.824219 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1780 04:47:00.827516 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1781 04:47:00.831674 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1782 04:47:00.838053 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1783 04:47:00.840544 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1784 04:47:00.844629 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1785 04:47:00.850875 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1786 04:47:00.853998 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1787 04:47:00.857245 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1788 04:47:00.861241 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1789 04:47:00.867927 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1790 04:47:00.870614 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1791 04:47:00.873890 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1792 04:47:00.880811 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1793 04:47:00.884491 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1794 04:47:00.887174 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1795 04:47:00.894575 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1796 04:47:00.897499 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1797 04:47:00.900759 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1798 04:47:00.904125 Total UI for P1: 0, mck2ui 16
1799 04:47:00.907645 best dqsien dly found for B0: ( 0, 9, 28)
1800 04:47:00.914088 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1801 04:47:00.914647 Total UI for P1: 0, mck2ui 16
1802 04:47:00.921355 best dqsien dly found for B1: ( 0, 9, 30)
1803 04:47:00.923894 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1804 04:47:00.927209 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1805 04:47:00.927671
1806 04:47:00.931676 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1807 04:47:00.934561 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1808 04:47:00.938090 [Gating] SW calibration Done
1809 04:47:00.938645 ==
1810 04:47:00.940093 Dram Type= 6, Freq= 0, CH_1, rank 1
1811 04:47:00.944436 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1812 04:47:00.945050 ==
1813 04:47:00.947334 RX Vref Scan: 0
1814 04:47:00.947889
1815 04:47:00.948251 RX Vref 0 -> 0, step: 1
1816 04:47:00.948590
1817 04:47:00.950417 RX Delay -130 -> 252, step: 16
1818 04:47:00.956883 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1819 04:47:00.961094 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1820 04:47:00.963823 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1821 04:47:00.967187 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1822 04:47:00.970298 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1823 04:47:00.976665 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1824 04:47:00.980355 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1825 04:47:00.984044 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1826 04:47:00.987127 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1827 04:47:00.990017 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1828 04:47:00.997922 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1829 04:47:01.000449 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1830 04:47:01.003647 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1831 04:47:01.007469 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1832 04:47:01.010132 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1833 04:47:01.017045 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1834 04:47:01.017589 ==
1835 04:47:01.020356 Dram Type= 6, Freq= 0, CH_1, rank 1
1836 04:47:01.023650 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1837 04:47:01.024373 ==
1838 04:47:01.024804 DQS Delay:
1839 04:47:01.026998 DQS0 = 0, DQS1 = 0
1840 04:47:01.027478 DQM Delay:
1841 04:47:01.030121 DQM0 = 81, DQM1 = 72
1842 04:47:01.030576 DQ Delay:
1843 04:47:01.033096 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1844 04:47:01.036881 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =77
1845 04:47:01.039860 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1846 04:47:01.043409 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =77
1847 04:47:01.043962
1848 04:47:01.044326
1849 04:47:01.044663 ==
1850 04:47:01.046936 Dram Type= 6, Freq= 0, CH_1, rank 1
1851 04:47:01.050373 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1852 04:47:01.050928 ==
1853 04:47:01.051403
1854 04:47:01.053050
1855 04:47:01.053504 TX Vref Scan disable
1856 04:47:01.057128 == TX Byte 0 ==
1857 04:47:01.060208 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1858 04:47:01.063239 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1859 04:47:01.066706 == TX Byte 1 ==
1860 04:47:01.069753 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1861 04:47:01.073699 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1862 04:47:01.074270 ==
1863 04:47:01.077232 Dram Type= 6, Freq= 0, CH_1, rank 1
1864 04:47:01.083120 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1865 04:47:01.083675 ==
1866 04:47:01.094916 TX Vref=22, minBit 10, minWin=27, winSum=448
1867 04:47:01.098411 TX Vref=24, minBit 8, minWin=27, winSum=451
1868 04:47:01.101461 TX Vref=26, minBit 1, minWin=28, winSum=454
1869 04:47:01.104582 TX Vref=28, minBit 0, minWin=28, winSum=455
1870 04:47:01.108233 TX Vref=30, minBit 8, minWin=28, winSum=457
1871 04:47:01.111751 TX Vref=32, minBit 9, minWin=26, winSum=454
1872 04:47:01.118085 [TxChooseVref] Worse bit 8, Min win 28, Win sum 457, Final Vref 30
1873 04:47:01.118642
1874 04:47:01.121480 Final TX Range 1 Vref 30
1875 04:47:01.122061
1876 04:47:01.122428 ==
1877 04:47:01.125198 Dram Type= 6, Freq= 0, CH_1, rank 1
1878 04:47:01.127791 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1879 04:47:01.128266 ==
1880 04:47:01.128633
1881 04:47:01.131836
1882 04:47:01.132600 TX Vref Scan disable
1883 04:47:01.134782 == TX Byte 0 ==
1884 04:47:01.137916 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1885 04:47:01.141156 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1886 04:47:01.145090 == TX Byte 1 ==
1887 04:47:01.148618 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1888 04:47:01.151493 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1889 04:47:01.155774
1890 04:47:01.156332 [DATLAT]
1891 04:47:01.156699 Freq=800, CH1 RK1
1892 04:47:01.157116
1893 04:47:01.157800 DATLAT Default: 0x9
1894 04:47:01.158158 0, 0xFFFF, sum = 0
1895 04:47:01.161791 1, 0xFFFF, sum = 0
1896 04:47:01.162350 2, 0xFFFF, sum = 0
1897 04:47:01.164871 3, 0xFFFF, sum = 0
1898 04:47:01.165339 4, 0xFFFF, sum = 0
1899 04:47:01.168122 5, 0xFFFF, sum = 0
1900 04:47:01.172308 6, 0xFFFF, sum = 0
1901 04:47:01.172979 7, 0xFFFF, sum = 0
1902 04:47:01.173367 8, 0x0, sum = 1
1903 04:47:01.174514 9, 0x0, sum = 2
1904 04:47:01.174983 10, 0x0, sum = 3
1905 04:47:01.177646 11, 0x0, sum = 4
1906 04:47:01.178115 best_step = 9
1907 04:47:01.178482
1908 04:47:01.178821 ==
1909 04:47:01.183026 Dram Type= 6, Freq= 0, CH_1, rank 1
1910 04:47:01.189426 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1911 04:47:01.190063 ==
1912 04:47:01.190444 RX Vref Scan: 0
1913 04:47:01.190788
1914 04:47:01.191534 RX Vref 0 -> 0, step: 1
1915 04:47:01.191986
1916 04:47:01.194615 RX Delay -111 -> 252, step: 8
1917 04:47:01.197910 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1918 04:47:01.201214 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1919 04:47:01.208329 iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240
1920 04:47:01.211604 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1921 04:47:01.214875 iDelay=217, Bit 4, Center 80 (-39 ~ 200) 240
1922 04:47:01.218304 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1923 04:47:01.221365 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1924 04:47:01.227735 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1925 04:47:01.231277 iDelay=217, Bit 8, Center 56 (-63 ~ 176) 240
1926 04:47:01.234603 iDelay=217, Bit 9, Center 64 (-55 ~ 184) 240
1927 04:47:01.237612 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1928 04:47:01.241130 iDelay=217, Bit 11, Center 64 (-55 ~ 184) 240
1929 04:47:01.247647 iDelay=217, Bit 12, Center 80 (-39 ~ 200) 240
1930 04:47:01.251281 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1931 04:47:01.254767 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1932 04:47:01.258006 iDelay=217, Bit 15, Center 80 (-39 ~ 200) 240
1933 04:47:01.258716 ==
1934 04:47:01.261524 Dram Type= 6, Freq= 0, CH_1, rank 1
1935 04:47:01.264415 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1936 04:47:01.267793 ==
1937 04:47:01.268248 DQS Delay:
1938 04:47:01.268810 DQS0 = 0, DQS1 = 0
1939 04:47:01.271715 DQM Delay:
1940 04:47:01.272277 DQM0 = 82, DQM1 = 72
1941 04:47:01.274611 DQ Delay:
1942 04:47:01.277779 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1943 04:47:01.278239 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1944 04:47:01.280820 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1945 04:47:01.285250 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =80
1946 04:47:01.287436
1947 04:47:01.287891
1948 04:47:01.294361 [DQSOSCAuto] RK1, (LSB)MR18= 0x3636, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1949 04:47:01.298261 CH1 RK1: MR19=606, MR18=3636
1950 04:47:01.305165 CH1_RK1: MR19=0x606, MR18=0x3636, DQSOSC=396, MR23=63, INC=94, DEC=62
1951 04:47:01.308322 [RxdqsGatingPostProcess] freq 800
1952 04:47:01.311239 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1953 04:47:01.314397 Pre-setting of DQS Precalculation
1954 04:47:01.321195 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1955 04:47:01.327727 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1956 04:47:01.334341 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1957 04:47:01.334817
1958 04:47:01.335176
1959 04:47:01.338341 [Calibration Summary] 1600 Mbps
1960 04:47:01.338911 CH 0, Rank 0
1961 04:47:01.341282 SW Impedance : PASS
1962 04:47:01.341740 DUTY Scan : NO K
1963 04:47:01.344477 ZQ Calibration : PASS
1964 04:47:01.349025 Jitter Meter : NO K
1965 04:47:01.349583 CBT Training : PASS
1966 04:47:01.350679 Write leveling : PASS
1967 04:47:01.354941 RX DQS gating : PASS
1968 04:47:01.355490 RX DQ/DQS(RDDQC) : PASS
1969 04:47:01.357559 TX DQ/DQS : PASS
1970 04:47:01.360796 RX DATLAT : PASS
1971 04:47:01.361269 RX DQ/DQS(Engine): PASS
1972 04:47:01.364676 TX OE : NO K
1973 04:47:01.365189 All Pass.
1974 04:47:01.365678
1975 04:47:01.367240 CH 0, Rank 1
1976 04:47:01.367715 SW Impedance : PASS
1977 04:47:01.370731 DUTY Scan : NO K
1978 04:47:01.374605 ZQ Calibration : PASS
1979 04:47:01.375079 Jitter Meter : NO K
1980 04:47:01.377301 CBT Training : PASS
1981 04:47:01.380615 Write leveling : PASS
1982 04:47:01.381228 RX DQS gating : PASS
1983 04:47:01.383905 RX DQ/DQS(RDDQC) : PASS
1984 04:47:01.388676 TX DQ/DQS : PASS
1985 04:47:01.389293 RX DATLAT : PASS
1986 04:47:01.390472 RX DQ/DQS(Engine): PASS
1987 04:47:01.394567 TX OE : NO K
1988 04:47:01.395132 All Pass.
1989 04:47:01.395523
1990 04:47:01.395934 CH 1, Rank 0
1991 04:47:01.397251 SW Impedance : PASS
1992 04:47:01.400871 DUTY Scan : NO K
1993 04:47:01.401436 ZQ Calibration : PASS
1994 04:47:01.403568 Jitter Meter : NO K
1995 04:47:01.404128 CBT Training : PASS
1996 04:47:01.407298 Write leveling : PASS
1997 04:47:01.411061 RX DQS gating : PASS
1998 04:47:01.411627 RX DQ/DQS(RDDQC) : PASS
1999 04:47:01.415246 TX DQ/DQS : PASS
2000 04:47:01.418226 RX DATLAT : PASS
2001 04:47:01.418839 RX DQ/DQS(Engine): PASS
2002 04:47:01.420174 TX OE : NO K
2003 04:47:01.420638 All Pass.
2004 04:47:01.421209
2005 04:47:01.423896 CH 1, Rank 1
2006 04:47:01.424459 SW Impedance : PASS
2007 04:47:01.427520 DUTY Scan : NO K
2008 04:47:01.430113 ZQ Calibration : PASS
2009 04:47:01.430575 Jitter Meter : NO K
2010 04:47:01.433660 CBT Training : PASS
2011 04:47:01.436904 Write leveling : PASS
2012 04:47:01.437364 RX DQS gating : PASS
2013 04:47:01.442058 RX DQ/DQS(RDDQC) : PASS
2014 04:47:01.443376 TX DQ/DQS : PASS
2015 04:47:01.443840 RX DATLAT : PASS
2016 04:47:01.446813 RX DQ/DQS(Engine): PASS
2017 04:47:01.450120 TX OE : NO K
2018 04:47:01.450583 All Pass.
2019 04:47:01.450950
2020 04:47:01.451289 DramC Write-DBI off
2021 04:47:01.453615 PER_BANK_REFRESH: Hybrid Mode
2022 04:47:01.457236 TX_TRACKING: ON
2023 04:47:01.460330 [GetDramInforAfterCalByMRR] Vendor 6.
2024 04:47:01.463538 [GetDramInforAfterCalByMRR] Revision 606.
2025 04:47:01.466711 [GetDramInforAfterCalByMRR] Revision 2 0.
2026 04:47:01.467177 MR0 0x3939
2027 04:47:01.471468 MR8 0x1111
2028 04:47:01.474675 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2029 04:47:01.475211
2030 04:47:01.475580 MR0 0x3939
2031 04:47:01.475965 MR8 0x1111
2032 04:47:01.476638 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2033 04:47:01.479681
2034 04:47:01.486774 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2035 04:47:01.489964 [FAST_K] Save calibration result to emmc
2036 04:47:01.493400 [FAST_K] Save calibration result to emmc
2037 04:47:01.496647 dram_init: config_dvfs: 1
2038 04:47:01.499894 dramc_set_vcore_voltage set vcore to 662500
2039 04:47:01.503102 Read voltage for 1200, 2
2040 04:47:01.503561 Vio18 = 0
2041 04:47:01.506750 Vcore = 662500
2042 04:47:01.507304 Vdram = 0
2043 04:47:01.507669 Vddq = 0
2044 04:47:01.508006 Vmddr = 0
2045 04:47:01.513330 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2046 04:47:01.520016 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2047 04:47:01.520480 MEM_TYPE=3, freq_sel=15
2048 04:47:01.523634 sv_algorithm_assistance_LP4_1600
2049 04:47:01.526615 ============ PULL DRAM RESETB DOWN ============
2050 04:47:01.533564 ========== PULL DRAM RESETB DOWN end =========
2051 04:47:01.537966 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2052 04:47:01.540652 ===================================
2053 04:47:01.543206 LPDDR4 DRAM CONFIGURATION
2054 04:47:01.547081 ===================================
2055 04:47:01.547650 EX_ROW_EN[0] = 0x0
2056 04:47:01.550110 EX_ROW_EN[1] = 0x0
2057 04:47:01.550570 LP4Y_EN = 0x0
2058 04:47:01.553519 WORK_FSP = 0x0
2059 04:47:01.553984 WL = 0x4
2060 04:47:01.557028 RL = 0x4
2061 04:47:01.557488 BL = 0x2
2062 04:47:01.560156 RPST = 0x0
2063 04:47:01.560616 RD_PRE = 0x0
2064 04:47:01.563693 WR_PRE = 0x1
2065 04:47:01.567315 WR_PST = 0x0
2066 04:47:01.567984 DBI_WR = 0x0
2067 04:47:01.569697 DBI_RD = 0x0
2068 04:47:01.570231 OTF = 0x1
2069 04:47:01.573044 ===================================
2070 04:47:01.576860 ===================================
2071 04:47:01.577327 ANA top config
2072 04:47:01.579704 ===================================
2073 04:47:01.585065 DLL_ASYNC_EN = 0
2074 04:47:01.586360 ALL_SLAVE_EN = 0
2075 04:47:01.589556 NEW_RANK_MODE = 1
2076 04:47:01.593203 DLL_IDLE_MODE = 1
2077 04:47:01.593667 LP45_APHY_COMB_EN = 1
2078 04:47:01.596301 TX_ODT_DIS = 1
2079 04:47:01.599667 NEW_8X_MODE = 1
2080 04:47:01.603207 ===================================
2081 04:47:01.606760 ===================================
2082 04:47:01.609845 data_rate = 2400
2083 04:47:01.612783 CKR = 1
2084 04:47:01.613250 DQ_P2S_RATIO = 8
2085 04:47:01.616444 ===================================
2086 04:47:01.620389 CA_P2S_RATIO = 8
2087 04:47:01.624600 DQ_CA_OPEN = 0
2088 04:47:01.626883 DQ_SEMI_OPEN = 0
2089 04:47:01.630150 CA_SEMI_OPEN = 0
2090 04:47:01.633364 CA_FULL_RATE = 0
2091 04:47:01.633824 DQ_CKDIV4_EN = 0
2092 04:47:01.636316 CA_CKDIV4_EN = 0
2093 04:47:01.639879 CA_PREDIV_EN = 0
2094 04:47:01.643813 PH8_DLY = 17
2095 04:47:01.646295 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2096 04:47:01.649561 DQ_AAMCK_DIV = 4
2097 04:47:01.650021 CA_AAMCK_DIV = 4
2098 04:47:01.653033 CA_ADMCK_DIV = 4
2099 04:47:01.657054 DQ_TRACK_CA_EN = 0
2100 04:47:01.659486 CA_PICK = 1200
2101 04:47:01.662720 CA_MCKIO = 1200
2102 04:47:01.666555 MCKIO_SEMI = 0
2103 04:47:01.669788 PLL_FREQ = 2366
2104 04:47:01.670267 DQ_UI_PI_RATIO = 32
2105 04:47:01.672671 CA_UI_PI_RATIO = 0
2106 04:47:01.675968 ===================================
2107 04:47:01.679132 ===================================
2108 04:47:01.683023 memory_type:LPDDR4
2109 04:47:01.686106 GP_NUM : 10
2110 04:47:01.686664 SRAM_EN : 1
2111 04:47:01.690341 MD32_EN : 0
2112 04:47:01.692580 ===================================
2113 04:47:01.696246 [ANA_INIT] >>>>>>>>>>>>>>
2114 04:47:01.696749 <<<<<< [CONFIGURE PHASE]: ANA_TX
2115 04:47:01.699926 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2116 04:47:01.702700 ===================================
2117 04:47:01.706530 data_rate = 2400,PCW = 0X5b00
2118 04:47:01.710579 ===================================
2119 04:47:01.713149 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2120 04:47:01.719563 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2121 04:47:01.726026 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2122 04:47:01.729748 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2123 04:47:01.732849 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2124 04:47:01.735893 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2125 04:47:01.739415 [ANA_INIT] flow start
2126 04:47:01.739880 [ANA_INIT] PLL >>>>>>>>
2127 04:47:01.742910 [ANA_INIT] PLL <<<<<<<<
2128 04:47:01.746270 [ANA_INIT] MIDPI >>>>>>>>
2129 04:47:01.746749 [ANA_INIT] MIDPI <<<<<<<<
2130 04:47:01.749615 [ANA_INIT] DLL >>>>>>>>
2131 04:47:01.752925 [ANA_INIT] DLL <<<<<<<<
2132 04:47:01.753391 [ANA_INIT] flow end
2133 04:47:01.759744 ============ LP4 DIFF to SE enter ============
2134 04:47:01.762753 ============ LP4 DIFF to SE exit ============
2135 04:47:01.766910 [ANA_INIT] <<<<<<<<<<<<<
2136 04:47:01.769991 [Flow] Enable top DCM control >>>>>
2137 04:47:01.773478 [Flow] Enable top DCM control <<<<<
2138 04:47:01.773942 Enable DLL master slave shuffle
2139 04:47:01.779717 ==============================================================
2140 04:47:01.783051 Gating Mode config
2141 04:47:01.786437 ==============================================================
2142 04:47:01.789385 Config description:
2143 04:47:01.799230 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2144 04:47:01.806667 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2145 04:47:01.809195 SELPH_MODE 0: By rank 1: By Phase
2146 04:47:01.816145 ==============================================================
2147 04:47:01.819923 GAT_TRACK_EN = 1
2148 04:47:01.822952 RX_GATING_MODE = 2
2149 04:47:01.825672 RX_GATING_TRACK_MODE = 2
2150 04:47:01.826141 SELPH_MODE = 1
2151 04:47:01.829360 PICG_EARLY_EN = 1
2152 04:47:01.832608 VALID_LAT_VALUE = 1
2153 04:47:01.839433 ==============================================================
2154 04:47:01.842968 Enter into Gating configuration >>>>
2155 04:47:01.845987 Exit from Gating configuration <<<<
2156 04:47:01.849820 Enter into DVFS_PRE_config >>>>>
2157 04:47:01.859088 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2158 04:47:01.862725 Exit from DVFS_PRE_config <<<<<
2159 04:47:01.865859 Enter into PICG configuration >>>>
2160 04:47:01.869831 Exit from PICG configuration <<<<
2161 04:47:01.873311 [RX_INPUT] configuration >>>>>
2162 04:47:01.876427 [RX_INPUT] configuration <<<<<
2163 04:47:01.879737 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2164 04:47:01.885639 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2165 04:47:01.892461 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2166 04:47:01.899114 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2167 04:47:01.902766 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2168 04:47:01.909649 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2169 04:47:01.912667 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2170 04:47:01.918841 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2171 04:47:01.923404 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2172 04:47:01.926530 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2173 04:47:01.928884 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2174 04:47:01.935486 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2175 04:47:01.939538 ===================================
2176 04:47:01.940100 LPDDR4 DRAM CONFIGURATION
2177 04:47:01.942690 ===================================
2178 04:47:01.946213 EX_ROW_EN[0] = 0x0
2179 04:47:01.949480 EX_ROW_EN[1] = 0x0
2180 04:47:01.950037 LP4Y_EN = 0x0
2181 04:47:01.952318 WORK_FSP = 0x0
2182 04:47:01.952808 WL = 0x4
2183 04:47:01.955736 RL = 0x4
2184 04:47:01.956293 BL = 0x2
2185 04:47:01.958888 RPST = 0x0
2186 04:47:01.959344 RD_PRE = 0x0
2187 04:47:01.962555 WR_PRE = 0x1
2188 04:47:01.963124 WR_PST = 0x0
2189 04:47:01.965975 DBI_WR = 0x0
2190 04:47:01.966429 DBI_RD = 0x0
2191 04:47:01.969334 OTF = 0x1
2192 04:47:01.972328 ===================================
2193 04:47:01.975810 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2194 04:47:01.979076 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2195 04:47:01.985686 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2196 04:47:01.989553 ===================================
2197 04:47:01.990303 LPDDR4 DRAM CONFIGURATION
2198 04:47:01.992368 ===================================
2199 04:47:01.995776 EX_ROW_EN[0] = 0x10
2200 04:47:01.996332 EX_ROW_EN[1] = 0x0
2201 04:47:01.999293 LP4Y_EN = 0x0
2202 04:47:02.003094 WORK_FSP = 0x0
2203 04:47:02.003656 WL = 0x4
2204 04:47:02.005900 RL = 0x4
2205 04:47:02.006355 BL = 0x2
2206 04:47:02.009559 RPST = 0x0
2207 04:47:02.010122 RD_PRE = 0x0
2208 04:47:02.012229 WR_PRE = 0x1
2209 04:47:02.012686 WR_PST = 0x0
2210 04:47:02.016902 DBI_WR = 0x0
2211 04:47:02.017464 DBI_RD = 0x0
2212 04:47:02.019324 OTF = 0x1
2213 04:47:02.023020 ===================================
2214 04:47:02.028953 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2215 04:47:02.029524 ==
2216 04:47:02.032986 Dram Type= 6, Freq= 0, CH_0, rank 0
2217 04:47:02.036174 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2218 04:47:02.036777 ==
2219 04:47:02.039374 [Duty_Offset_Calibration]
2220 04:47:02.039929 B0:0 B1:2 CA:1
2221 04:47:02.040296
2222 04:47:02.042907 [DutyScan_Calibration_Flow] k_type=0
2223 04:47:02.052500
2224 04:47:02.053091 ==CLK 0==
2225 04:47:02.055135 Final CLK duty delay cell = 0
2226 04:47:02.058701 [0] MAX Duty = 5093%(X100), DQS PI = 12
2227 04:47:02.061899 [0] MIN Duty = 4938%(X100), DQS PI = 52
2228 04:47:02.062359 [0] AVG Duty = 5015%(X100)
2229 04:47:02.065348
2230 04:47:02.065964 CH0 CLK Duty spec in!! Max-Min= 155%
2231 04:47:02.071995 [DutyScan_Calibration_Flow] ====Done====
2232 04:47:02.072451
2233 04:47:02.075363 [DutyScan_Calibration_Flow] k_type=1
2234 04:47:02.091930
2235 04:47:02.092484 ==DQS 0 ==
2236 04:47:02.094881 Final DQS duty delay cell = 0
2237 04:47:02.097863 [0] MAX Duty = 5125%(X100), DQS PI = 30
2238 04:47:02.101012 [0] MIN Duty = 5031%(X100), DQS PI = 6
2239 04:47:02.104794 [0] AVG Duty = 5078%(X100)
2240 04:47:02.105352
2241 04:47:02.105711 ==DQS 1 ==
2242 04:47:02.108875 Final DQS duty delay cell = 0
2243 04:47:02.111588 [0] MAX Duty = 5031%(X100), DQS PI = 50
2244 04:47:02.114707 [0] MIN Duty = 4906%(X100), DQS PI = 16
2245 04:47:02.117759 [0] AVG Duty = 4968%(X100)
2246 04:47:02.118315
2247 04:47:02.121349 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2248 04:47:02.121914
2249 04:47:02.125077 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2250 04:47:02.128797 [DutyScan_Calibration_Flow] ====Done====
2251 04:47:02.129354
2252 04:47:02.132173 [DutyScan_Calibration_Flow] k_type=3
2253 04:47:02.148415
2254 04:47:02.149009 ==DQM 0 ==
2255 04:47:02.151500 Final DQM duty delay cell = 0
2256 04:47:02.155555 [0] MAX Duty = 5187%(X100), DQS PI = 20
2257 04:47:02.157487 [0] MIN Duty = 5000%(X100), DQS PI = 40
2258 04:47:02.161276 [0] AVG Duty = 5093%(X100)
2259 04:47:02.161830
2260 04:47:02.162191 ==DQM 1 ==
2261 04:47:02.164600 Final DQM duty delay cell = 0
2262 04:47:02.168297 [0] MAX Duty = 5000%(X100), DQS PI = 56
2263 04:47:02.170948 [0] MIN Duty = 4844%(X100), DQS PI = 0
2264 04:47:02.171473 [0] AVG Duty = 4922%(X100)
2265 04:47:02.175093
2266 04:47:02.178256 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2267 04:47:02.178771
2268 04:47:02.181162 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2269 04:47:02.184878 [DutyScan_Calibration_Flow] ====Done====
2270 04:47:02.185438
2271 04:47:02.187863 [DutyScan_Calibration_Flow] k_type=2
2272 04:47:02.203211
2273 04:47:02.203764 ==DQ 0 ==
2274 04:47:02.206715 Final DQ duty delay cell = -4
2275 04:47:02.209381 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2276 04:47:02.212839 [-4] MIN Duty = 4813%(X100), DQS PI = 54
2277 04:47:02.216874 [-4] AVG Duty = 4937%(X100)
2278 04:47:02.217433
2279 04:47:02.217795 ==DQ 1 ==
2280 04:47:02.218894 Final DQ duty delay cell = -4
2281 04:47:02.222547 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2282 04:47:02.226488 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2283 04:47:02.229339 [-4] AVG Duty = 4969%(X100)
2284 04:47:02.229898
2285 04:47:02.233012 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2286 04:47:02.233575
2287 04:47:02.236154 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2288 04:47:02.240372 [DutyScan_Calibration_Flow] ====Done====
2289 04:47:02.240967 ==
2290 04:47:02.242546 Dram Type= 6, Freq= 0, CH_1, rank 0
2291 04:47:02.247047 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2292 04:47:02.247509 ==
2293 04:47:02.249798 [Duty_Offset_Calibration]
2294 04:47:02.250343 B0:0 B1:4 CA:-5
2295 04:47:02.250707
2296 04:47:02.252293 [DutyScan_Calibration_Flow] k_type=0
2297 04:47:02.263393
2298 04:47:02.263947 ==CLK 0==
2299 04:47:02.266736 Final CLK duty delay cell = 0
2300 04:47:02.270811 [0] MAX Duty = 5094%(X100), DQS PI = 24
2301 04:47:02.273178 [0] MIN Duty = 4875%(X100), DQS PI = 46
2302 04:47:02.273638 [0] AVG Duty = 4984%(X100)
2303 04:47:02.276941
2304 04:47:02.277393 CH1 CLK Duty spec in!! Max-Min= 219%
2305 04:47:02.283663 [DutyScan_Calibration_Flow] ====Done====
2306 04:47:02.284214
2307 04:47:02.286721 [DutyScan_Calibration_Flow] k_type=1
2308 04:47:02.301811
2309 04:47:02.302377 ==DQS 0 ==
2310 04:47:02.305386 Final DQS duty delay cell = 0
2311 04:47:02.308501 [0] MAX Duty = 5125%(X100), DQS PI = 14
2312 04:47:02.311973 [0] MIN Duty = 4875%(X100), DQS PI = 40
2313 04:47:02.312530 [0] AVG Duty = 5000%(X100)
2314 04:47:02.315389
2315 04:47:02.315959 ==DQS 1 ==
2316 04:47:02.320008 Final DQS duty delay cell = -4
2317 04:47:02.321790 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2318 04:47:02.325108 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2319 04:47:02.328637 [-4] AVG Duty = 4953%(X100)
2320 04:47:02.329245
2321 04:47:02.331958 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2322 04:47:02.332510
2323 04:47:02.335544 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2324 04:47:02.338535 [DutyScan_Calibration_Flow] ====Done====
2325 04:47:02.339099
2326 04:47:02.341412 [DutyScan_Calibration_Flow] k_type=3
2327 04:47:02.356669
2328 04:47:02.357259 ==DQM 0 ==
2329 04:47:02.360443 Final DQM duty delay cell = -4
2330 04:47:02.364357 [-4] MAX Duty = 5093%(X100), DQS PI = 32
2331 04:47:02.367121 [-4] MIN Duty = 4875%(X100), DQS PI = 38
2332 04:47:02.370637 [-4] AVG Duty = 4984%(X100)
2333 04:47:02.371093
2334 04:47:02.371449 ==DQM 1 ==
2335 04:47:02.373192 Final DQM duty delay cell = -4
2336 04:47:02.377463 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2337 04:47:02.380230 [-4] MIN Duty = 4875%(X100), DQS PI = 60
2338 04:47:02.383780 [-4] AVG Duty = 4968%(X100)
2339 04:47:02.384340
2340 04:47:02.387123 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2341 04:47:02.387687
2342 04:47:02.389926 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2343 04:47:02.393312 [DutyScan_Calibration_Flow] ====Done====
2344 04:47:02.393866
2345 04:47:02.396874 [DutyScan_Calibration_Flow] k_type=2
2346 04:47:02.413875
2347 04:47:02.414438 ==DQ 0 ==
2348 04:47:02.416830 Final DQ duty delay cell = 0
2349 04:47:02.420270 [0] MAX Duty = 5062%(X100), DQS PI = 0
2350 04:47:02.424537 [0] MIN Duty = 4938%(X100), DQS PI = 44
2351 04:47:02.425143 [0] AVG Duty = 5000%(X100)
2352 04:47:02.425505
2353 04:47:02.429459 ==DQ 1 ==
2354 04:47:02.431078 Final DQ duty delay cell = 0
2355 04:47:02.434181 [0] MAX Duty = 5031%(X100), DQS PI = 8
2356 04:47:02.437625 [0] MIN Duty = 4875%(X100), DQS PI = 0
2357 04:47:02.438109 [0] AVG Duty = 4953%(X100)
2358 04:47:02.438467
2359 04:47:02.440793 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2360 04:47:02.441250
2361 04:47:02.443580 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2362 04:47:02.450535 [DutyScan_Calibration_Flow] ====Done====
2363 04:47:02.453717 nWR fixed to 30
2364 04:47:02.454171 [ModeRegInit_LP4] CH0 RK0
2365 04:47:02.457063 [ModeRegInit_LP4] CH0 RK1
2366 04:47:02.460226 [ModeRegInit_LP4] CH1 RK0
2367 04:47:02.460674 [ModeRegInit_LP4] CH1 RK1
2368 04:47:02.464195 match AC timing 6
2369 04:47:02.468064 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2370 04:47:02.469880 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2371 04:47:02.476876 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2372 04:47:02.480373 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2373 04:47:02.487420 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2374 04:47:02.487839 ==
2375 04:47:02.491018 Dram Type= 6, Freq= 0, CH_0, rank 0
2376 04:47:02.493389 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2377 04:47:02.493840 ==
2378 04:47:02.500099 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2379 04:47:02.506986 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2380 04:47:02.513689 [CA 0] Center 39 (9~70) winsize 62
2381 04:47:02.517024 [CA 1] Center 39 (9~70) winsize 62
2382 04:47:02.520457 [CA 2] Center 36 (5~67) winsize 63
2383 04:47:02.523707 [CA 3] Center 35 (4~66) winsize 63
2384 04:47:02.526779 [CA 4] Center 34 (3~65) winsize 63
2385 04:47:02.530610 [CA 5] Center 33 (3~64) winsize 62
2386 04:47:02.531166
2387 04:47:02.533450 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2388 04:47:02.533909
2389 04:47:02.536791 [CATrainingPosCal] consider 1 rank data
2390 04:47:02.540431 u2DelayCellTimex100 = 270/100 ps
2391 04:47:02.544016 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2392 04:47:02.546967 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2393 04:47:02.553246 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2394 04:47:02.556846 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2395 04:47:02.560214 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2396 04:47:02.563167 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2397 04:47:02.563716
2398 04:47:02.566555 CA PerBit enable=1, Macro0, CA PI delay=33
2399 04:47:02.567120
2400 04:47:02.571368 [CBTSetCACLKResult] CA Dly = 33
2401 04:47:02.571930 CS Dly: 7 (0~38)
2402 04:47:02.572836 ==
2403 04:47:02.576383 Dram Type= 6, Freq= 0, CH_0, rank 1
2404 04:47:02.580131 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2405 04:47:02.580691 ==
2406 04:47:02.584675 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2407 04:47:02.589632 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2408 04:47:02.599516 [CA 0] Center 39 (8~70) winsize 63
2409 04:47:02.602360 [CA 1] Center 39 (8~70) winsize 63
2410 04:47:02.605789 [CA 2] Center 36 (5~67) winsize 63
2411 04:47:02.608986 [CA 3] Center 35 (4~66) winsize 63
2412 04:47:02.612821 [CA 4] Center 33 (3~64) winsize 62
2413 04:47:02.617236 [CA 5] Center 34 (3~65) winsize 63
2414 04:47:02.617786
2415 04:47:02.619701 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2416 04:47:02.620251
2417 04:47:02.623212 [CATrainingPosCal] consider 2 rank data
2418 04:47:02.625441 u2DelayCellTimex100 = 270/100 ps
2419 04:47:02.628947 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2420 04:47:02.632297 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2421 04:47:02.638693 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2422 04:47:02.642264 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2423 04:47:02.646019 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2424 04:47:02.649225 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2425 04:47:02.649902
2426 04:47:02.652526 CA PerBit enable=1, Macro0, CA PI delay=33
2427 04:47:02.653088
2428 04:47:02.656174 [CBTSetCACLKResult] CA Dly = 33
2429 04:47:02.656686 CS Dly: 7 (0~39)
2430 04:47:02.657118
2431 04:47:02.662509 ----->DramcWriteLeveling(PI) begin...
2432 04:47:02.663272 ==
2433 04:47:02.665392 Dram Type= 6, Freq= 0, CH_0, rank 0
2434 04:47:02.669207 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2435 04:47:02.669715 ==
2436 04:47:02.671975 Write leveling (Byte 0): 26 => 26
2437 04:47:02.676038 Write leveling (Byte 1): 26 => 26
2438 04:47:02.679199 DramcWriteLeveling(PI) end<-----
2439 04:47:02.679752
2440 04:47:02.680113 ==
2441 04:47:02.682600 Dram Type= 6, Freq= 0, CH_0, rank 0
2442 04:47:02.685492 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2443 04:47:02.685954 ==
2444 04:47:02.688875 [Gating] SW mode calibration
2445 04:47:02.695781 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2446 04:47:02.702976 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2447 04:47:02.705547 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2448 04:47:02.708495 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2449 04:47:02.715560 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2450 04:47:02.718604 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2451 04:47:02.721680 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2452 04:47:02.725231 0 11 20 | B1->B0 | 2e2e 2b2b | 1 0 | (1 0) (0 1)
2453 04:47:02.731784 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2454 04:47:02.735112 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2455 04:47:02.738389 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2456 04:47:02.745077 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2457 04:47:02.749088 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2458 04:47:02.752638 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2459 04:47:02.759270 0 12 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2460 04:47:02.761509 0 12 20 | B1->B0 | 3636 4343 | 0 0 | (0 0) (0 0)
2461 04:47:02.765540 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2462 04:47:02.771432 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2463 04:47:02.775217 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2464 04:47:02.778498 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2465 04:47:02.785489 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2466 04:47:02.788487 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2467 04:47:02.791507 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2468 04:47:02.798294 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2469 04:47:02.802179 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2470 04:47:02.805668 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2471 04:47:02.812039 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2472 04:47:02.815408 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2473 04:47:02.819389 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2474 04:47:02.825088 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2475 04:47:02.828296 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2476 04:47:02.832114 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2477 04:47:02.838111 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2478 04:47:02.842078 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2479 04:47:02.844912 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2480 04:47:02.851754 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2481 04:47:02.854791 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2482 04:47:02.858364 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2483 04:47:02.861416 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2484 04:47:02.868302 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2485 04:47:02.871987 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2486 04:47:02.875920 Total UI for P1: 0, mck2ui 16
2487 04:47:02.878159 best dqsien dly found for B0: ( 0, 15, 18)
2488 04:47:02.881872 Total UI for P1: 0, mck2ui 16
2489 04:47:02.885277 best dqsien dly found for B1: ( 0, 15, 20)
2490 04:47:02.888026 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2491 04:47:02.891495 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2492 04:47:02.892052
2493 04:47:02.895307 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2494 04:47:02.901686 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2495 04:47:02.902246 [Gating] SW calibration Done
2496 04:47:02.902608 ==
2497 04:47:02.904817 Dram Type= 6, Freq= 0, CH_0, rank 0
2498 04:47:02.911723 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2499 04:47:02.912288 ==
2500 04:47:02.912654 RX Vref Scan: 0
2501 04:47:02.913032
2502 04:47:02.915040 RX Vref 0 -> 0, step: 1
2503 04:47:02.915596
2504 04:47:02.919054 RX Delay -40 -> 252, step: 8
2505 04:47:02.921394 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2506 04:47:02.925664 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2507 04:47:02.928257 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2508 04:47:02.931530 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2509 04:47:02.938121 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2510 04:47:02.941153 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2511 04:47:02.944975 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2512 04:47:02.948453 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2513 04:47:02.951585 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2514 04:47:02.959012 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2515 04:47:02.961416 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2516 04:47:02.964832 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2517 04:47:02.968392 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2518 04:47:02.972887 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2519 04:47:02.977774 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2520 04:47:02.981063 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2521 04:47:02.981534 ==
2522 04:47:02.984299 Dram Type= 6, Freq= 0, CH_0, rank 0
2523 04:47:02.987623 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2524 04:47:02.988084 ==
2525 04:47:02.990874 DQS Delay:
2526 04:47:02.991330 DQS0 = 0, DQS1 = 0
2527 04:47:02.991694 DQM Delay:
2528 04:47:02.994958 DQM0 = 115, DQM1 = 105
2529 04:47:02.995418 DQ Delay:
2530 04:47:02.997364 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2531 04:47:03.001012 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2532 04:47:03.004867 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =99
2533 04:47:03.011105 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2534 04:47:03.011674
2535 04:47:03.012036
2536 04:47:03.012372 ==
2537 04:47:03.014586 Dram Type= 6, Freq= 0, CH_0, rank 0
2538 04:47:03.017690 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2539 04:47:03.018261 ==
2540 04:47:03.018629
2541 04:47:03.018964
2542 04:47:03.021088 TX Vref Scan disable
2543 04:47:03.021547 == TX Byte 0 ==
2544 04:47:03.028144 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2545 04:47:03.031158 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2546 04:47:03.031725 == TX Byte 1 ==
2547 04:47:03.038601 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2548 04:47:03.040828 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2549 04:47:03.041298 ==
2550 04:47:03.044617 Dram Type= 6, Freq= 0, CH_0, rank 0
2551 04:47:03.048036 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2552 04:47:03.048611 ==
2553 04:47:03.060300 TX Vref=22, minBit 5, minWin=25, winSum=412
2554 04:47:03.064217 TX Vref=24, minBit 10, minWin=25, winSum=421
2555 04:47:03.066433 TX Vref=26, minBit 4, minWin=26, winSum=427
2556 04:47:03.069832 TX Vref=28, minBit 10, minWin=25, winSum=426
2557 04:47:03.074055 TX Vref=30, minBit 5, minWin=26, winSum=427
2558 04:47:03.081518 TX Vref=32, minBit 1, minWin=26, winSum=428
2559 04:47:03.083880 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 32
2560 04:47:03.084346
2561 04:47:03.087929 Final TX Range 1 Vref 32
2562 04:47:03.088504
2563 04:47:03.088919 ==
2564 04:47:03.090124 Dram Type= 6, Freq= 0, CH_0, rank 0
2565 04:47:03.093548 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2566 04:47:03.094157 ==
2567 04:47:03.096732
2568 04:47:03.097302
2569 04:47:03.097736 TX Vref Scan disable
2570 04:47:03.100278 == TX Byte 0 ==
2571 04:47:03.103846 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2572 04:47:03.107428 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2573 04:47:03.109938 == TX Byte 1 ==
2574 04:47:03.113751 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2575 04:47:03.116788 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2576 04:47:03.120673
2577 04:47:03.121279 [DATLAT]
2578 04:47:03.121647 Freq=1200, CH0 RK0
2579 04:47:03.121988
2580 04:47:03.123847 DATLAT Default: 0xd
2581 04:47:03.124407 0, 0xFFFF, sum = 0
2582 04:47:03.127191 1, 0xFFFF, sum = 0
2583 04:47:03.127759 2, 0xFFFF, sum = 0
2584 04:47:03.130278 3, 0xFFFF, sum = 0
2585 04:47:03.130741 4, 0xFFFF, sum = 0
2586 04:47:03.134705 5, 0xFFFF, sum = 0
2587 04:47:03.137425 6, 0xFFFF, sum = 0
2588 04:47:03.137996 7, 0xFFFF, sum = 0
2589 04:47:03.140690 8, 0xFFFF, sum = 0
2590 04:47:03.141352 9, 0xFFFF, sum = 0
2591 04:47:03.143478 10, 0xFFFF, sum = 0
2592 04:47:03.144045 11, 0x0, sum = 1
2593 04:47:03.147471 12, 0x0, sum = 2
2594 04:47:03.148039 13, 0x0, sum = 3
2595 04:47:03.148413 14, 0x0, sum = 4
2596 04:47:03.149934 best_step = 12
2597 04:47:03.150391
2598 04:47:03.150747 ==
2599 04:47:03.153681 Dram Type= 6, Freq= 0, CH_0, rank 0
2600 04:47:03.156659 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2601 04:47:03.157167 ==
2602 04:47:03.159969 RX Vref Scan: 1
2603 04:47:03.160549
2604 04:47:03.163178 Set Vref Range= 32 -> 127
2605 04:47:03.163746
2606 04:47:03.164113 RX Vref 32 -> 127, step: 1
2607 04:47:03.164453
2608 04:47:03.166286 RX Delay -21 -> 252, step: 4
2609 04:47:03.166773
2610 04:47:03.169748 Set Vref, RX VrefLevel [Byte0]: 32
2611 04:47:03.172907 [Byte1]: 32
2612 04:47:03.176917
2613 04:47:03.177372 Set Vref, RX VrefLevel [Byte0]: 33
2614 04:47:03.180075 [Byte1]: 33
2615 04:47:03.185558
2616 04:47:03.186017 Set Vref, RX VrefLevel [Byte0]: 34
2617 04:47:03.188037 [Byte1]: 34
2618 04:47:03.192813
2619 04:47:03.193367 Set Vref, RX VrefLevel [Byte0]: 35
2620 04:47:03.196033 [Byte1]: 35
2621 04:47:03.200335
2622 04:47:03.200833 Set Vref, RX VrefLevel [Byte0]: 36
2623 04:47:03.203636 [Byte1]: 36
2624 04:47:03.208503
2625 04:47:03.209109 Set Vref, RX VrefLevel [Byte0]: 37
2626 04:47:03.211966 [Byte1]: 37
2627 04:47:03.216262
2628 04:47:03.216861 Set Vref, RX VrefLevel [Byte0]: 38
2629 04:47:03.219192 [Byte1]: 38
2630 04:47:03.224884
2631 04:47:03.225446 Set Vref, RX VrefLevel [Byte0]: 39
2632 04:47:03.227805 [Byte1]: 39
2633 04:47:03.232340
2634 04:47:03.232938 Set Vref, RX VrefLevel [Byte0]: 40
2635 04:47:03.235739 [Byte1]: 40
2636 04:47:03.240220
2637 04:47:03.240887 Set Vref, RX VrefLevel [Byte0]: 41
2638 04:47:03.243543 [Byte1]: 41
2639 04:47:03.247745
2640 04:47:03.248205 Set Vref, RX VrefLevel [Byte0]: 42
2641 04:47:03.251349 [Byte1]: 42
2642 04:47:03.256188
2643 04:47:03.256798 Set Vref, RX VrefLevel [Byte0]: 43
2644 04:47:03.259356 [Byte1]: 43
2645 04:47:03.264005
2646 04:47:03.264563 Set Vref, RX VrefLevel [Byte0]: 44
2647 04:47:03.267202 [Byte1]: 44
2648 04:47:03.271934
2649 04:47:03.272510 Set Vref, RX VrefLevel [Byte0]: 45
2650 04:47:03.274849 [Byte1]: 45
2651 04:47:03.280018
2652 04:47:03.280577 Set Vref, RX VrefLevel [Byte0]: 46
2653 04:47:03.282695 [Byte1]: 46
2654 04:47:03.287308
2655 04:47:03.287765 Set Vref, RX VrefLevel [Byte0]: 47
2656 04:47:03.291362 [Byte1]: 47
2657 04:47:03.296228
2658 04:47:03.296811 Set Vref, RX VrefLevel [Byte0]: 48
2659 04:47:03.299603 [Byte1]: 48
2660 04:47:03.303920
2661 04:47:03.304487 Set Vref, RX VrefLevel [Byte0]: 49
2662 04:47:03.306805 [Byte1]: 49
2663 04:47:03.311377
2664 04:47:03.311937 Set Vref, RX VrefLevel [Byte0]: 50
2665 04:47:03.314733 [Byte1]: 50
2666 04:47:03.319327
2667 04:47:03.322436 Set Vref, RX VrefLevel [Byte0]: 51
2668 04:47:03.326270 [Byte1]: 51
2669 04:47:03.326830
2670 04:47:03.329689 Set Vref, RX VrefLevel [Byte0]: 52
2671 04:47:03.332833 [Byte1]: 52
2672 04:47:03.333389
2673 04:47:03.336023 Set Vref, RX VrefLevel [Byte0]: 53
2674 04:47:03.338719 [Byte1]: 53
2675 04:47:03.343336
2676 04:47:03.343898 Set Vref, RX VrefLevel [Byte0]: 54
2677 04:47:03.346402 [Byte1]: 54
2678 04:47:03.351532
2679 04:47:03.352089 Set Vref, RX VrefLevel [Byte0]: 55
2680 04:47:03.355220 [Byte1]: 55
2681 04:47:03.359020
2682 04:47:03.359582 Set Vref, RX VrefLevel [Byte0]: 56
2683 04:47:03.362240 [Byte1]: 56
2684 04:47:03.367615
2685 04:47:03.368168 Set Vref, RX VrefLevel [Byte0]: 57
2686 04:47:03.371304 [Byte1]: 57
2687 04:47:03.375245
2688 04:47:03.375704 Set Vref, RX VrefLevel [Byte0]: 58
2689 04:47:03.378177 [Byte1]: 58
2690 04:47:03.383025
2691 04:47:03.383583 Set Vref, RX VrefLevel [Byte0]: 59
2692 04:47:03.386272 [Byte1]: 59
2693 04:47:03.390374
2694 04:47:03.390832 Set Vref, RX VrefLevel [Byte0]: 60
2695 04:47:03.393826 [Byte1]: 60
2696 04:47:03.398420
2697 04:47:03.398974 Set Vref, RX VrefLevel [Byte0]: 61
2698 04:47:03.402211 [Byte1]: 61
2699 04:47:03.407223
2700 04:47:03.407776 Set Vref, RX VrefLevel [Byte0]: 62
2701 04:47:03.410508 [Byte1]: 62
2702 04:47:03.414738
2703 04:47:03.415289 Set Vref, RX VrefLevel [Byte0]: 63
2704 04:47:03.417918 [Byte1]: 63
2705 04:47:03.422062
2706 04:47:03.422613 Set Vref, RX VrefLevel [Byte0]: 64
2707 04:47:03.425925 [Byte1]: 64
2708 04:47:03.430194
2709 04:47:03.430749 Set Vref, RX VrefLevel [Byte0]: 65
2710 04:47:03.433503 [Byte1]: 65
2711 04:47:03.438462
2712 04:47:03.439017 Set Vref, RX VrefLevel [Byte0]: 66
2713 04:47:03.441999 [Byte1]: 66
2714 04:47:03.446242
2715 04:47:03.446797 Final RX Vref Byte 0 = 45 to rank0
2716 04:47:03.449455 Final RX Vref Byte 1 = 52 to rank0
2717 04:47:03.453513 Final RX Vref Byte 0 = 45 to rank1
2718 04:47:03.455849 Final RX Vref Byte 1 = 52 to rank1==
2719 04:47:03.459647 Dram Type= 6, Freq= 0, CH_0, rank 0
2720 04:47:03.465827 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2721 04:47:03.466388 ==
2722 04:47:03.466754 DQS Delay:
2723 04:47:03.467097 DQS0 = 0, DQS1 = 0
2724 04:47:03.469713 DQM Delay:
2725 04:47:03.470169 DQM0 = 114, DQM1 = 106
2726 04:47:03.472533 DQ Delay:
2727 04:47:03.476096 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2728 04:47:03.479381 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2729 04:47:03.482496 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =100
2730 04:47:03.485844 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =118
2731 04:47:03.486329
2732 04:47:03.486694
2733 04:47:03.492574 [DQSOSCAuto] RK0, (LSB)MR18= 0x303, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
2734 04:47:03.497093 CH0 RK0: MR19=404, MR18=303
2735 04:47:03.502874 CH0_RK0: MR19=0x404, MR18=0x303, DQSOSC=408, MR23=63, INC=39, DEC=26
2736 04:47:03.503604
2737 04:47:03.505654 ----->DramcWriteLeveling(PI) begin...
2738 04:47:03.506127 ==
2739 04:47:03.509670 Dram Type= 6, Freq= 0, CH_0, rank 1
2740 04:47:03.513251 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2741 04:47:03.513821 ==
2742 04:47:03.516081 Write leveling (Byte 0): 26 => 26
2743 04:47:03.519304 Write leveling (Byte 1): 24 => 24
2744 04:47:03.522464 DramcWriteLeveling(PI) end<-----
2745 04:47:03.523047
2746 04:47:03.523422 ==
2747 04:47:03.525773 Dram Type= 6, Freq= 0, CH_0, rank 1
2748 04:47:03.532491 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2749 04:47:03.533098 ==
2750 04:47:03.533478 [Gating] SW mode calibration
2751 04:47:03.542348 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2752 04:47:03.545635 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2753 04:47:03.549237 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2754 04:47:03.556396 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2755 04:47:03.559090 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2756 04:47:03.562292 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2757 04:47:03.569128 0 11 16 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 1)
2758 04:47:03.572665 0 11 20 | B1->B0 | 2f2f 2727 | 1 0 | (1 0) (1 0)
2759 04:47:03.575973 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2760 04:47:03.582196 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2761 04:47:03.585858 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2762 04:47:03.588848 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2763 04:47:03.595621 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2764 04:47:03.599082 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2765 04:47:03.602553 0 12 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2766 04:47:03.609306 0 12 20 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
2767 04:47:03.612644 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2768 04:47:03.615458 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2769 04:47:03.622569 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2770 04:47:03.625910 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2771 04:47:03.628847 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2772 04:47:03.635812 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2773 04:47:03.638773 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2774 04:47:03.643058 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2775 04:47:03.649076 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2776 04:47:03.652576 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2777 04:47:03.656181 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2778 04:47:03.661666 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2779 04:47:03.665312 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2780 04:47:03.668796 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2781 04:47:03.675474 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2782 04:47:03.678203 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2783 04:47:03.681842 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2784 04:47:03.685288 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2785 04:47:03.691717 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2786 04:47:03.695235 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2787 04:47:03.699044 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2788 04:47:03.705200 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2789 04:47:03.708932 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2790 04:47:03.712421 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2791 04:47:03.716008 Total UI for P1: 0, mck2ui 16
2792 04:47:03.719730 best dqsien dly found for B0: ( 0, 15, 16)
2793 04:47:03.725613 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2794 04:47:03.726171 Total UI for P1: 0, mck2ui 16
2795 04:47:03.732435 best dqsien dly found for B1: ( 0, 15, 18)
2796 04:47:03.736193 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2797 04:47:03.738649 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2798 04:47:03.739110
2799 04:47:03.741873 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2800 04:47:03.746461 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2801 04:47:03.749414 [Gating] SW calibration Done
2802 04:47:03.749873 ==
2803 04:47:03.752084 Dram Type= 6, Freq= 0, CH_0, rank 1
2804 04:47:03.755525 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2805 04:47:03.756089 ==
2806 04:47:03.758638 RX Vref Scan: 0
2807 04:47:03.759100
2808 04:47:03.759463 RX Vref 0 -> 0, step: 1
2809 04:47:03.759803
2810 04:47:03.762090 RX Delay -40 -> 252, step: 8
2811 04:47:03.765497 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2812 04:47:03.772684 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2813 04:47:03.775541 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2814 04:47:03.779169 iDelay=200, Bit 3, Center 107 (40 ~ 175) 136
2815 04:47:03.781737 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2816 04:47:03.786062 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2817 04:47:03.792546 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2818 04:47:03.795342 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2819 04:47:03.798959 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2820 04:47:03.802809 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2821 04:47:03.805615 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2822 04:47:03.808983 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2823 04:47:03.815916 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2824 04:47:03.820041 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2825 04:47:03.822421 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2826 04:47:03.825541 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2827 04:47:03.826098 ==
2828 04:47:03.828780 Dram Type= 6, Freq= 0, CH_0, rank 1
2829 04:47:03.835427 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2830 04:47:03.835990 ==
2831 04:47:03.836359 DQS Delay:
2832 04:47:03.838920 DQS0 = 0, DQS1 = 0
2833 04:47:03.839481 DQM Delay:
2834 04:47:03.839850 DQM0 = 113, DQM1 = 107
2835 04:47:03.843073 DQ Delay:
2836 04:47:03.845114 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =107
2837 04:47:03.848489 DQ4 =115, DQ5 =107, DQ6 =119, DQ7 =123
2838 04:47:03.852648 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2839 04:47:03.855731 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =115
2840 04:47:03.856291
2841 04:47:03.856657
2842 04:47:03.857059 ==
2843 04:47:03.859298 Dram Type= 6, Freq= 0, CH_0, rank 1
2844 04:47:03.861924 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2845 04:47:03.862385 ==
2846 04:47:03.865273
2847 04:47:03.865728
2848 04:47:03.866089 TX Vref Scan disable
2849 04:47:03.869136 == TX Byte 0 ==
2850 04:47:03.871962 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2851 04:47:03.875816 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2852 04:47:03.879389 == TX Byte 1 ==
2853 04:47:03.882123 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2854 04:47:03.885276 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2855 04:47:03.885736 ==
2856 04:47:03.889773 Dram Type= 6, Freq= 0, CH_0, rank 1
2857 04:47:03.895079 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2858 04:47:03.895666 ==
2859 04:47:03.905754 TX Vref=22, minBit 1, minWin=25, winSum=416
2860 04:47:03.909008 TX Vref=24, minBit 8, minWin=25, winSum=421
2861 04:47:03.912223 TX Vref=26, minBit 8, minWin=25, winSum=422
2862 04:47:03.915774 TX Vref=28, minBit 8, minWin=25, winSum=428
2863 04:47:03.919200 TX Vref=30, minBit 1, minWin=26, winSum=431
2864 04:47:03.922795 TX Vref=32, minBit 8, minWin=26, winSum=431
2865 04:47:03.930183 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 30
2866 04:47:03.930742
2867 04:47:03.932980 Final TX Range 1 Vref 30
2868 04:47:03.933537
2869 04:47:03.933924 ==
2870 04:47:03.936459 Dram Type= 6, Freq= 0, CH_0, rank 1
2871 04:47:03.939865 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2872 04:47:03.940427 ==
2873 04:47:03.942821
2874 04:47:03.943409
2875 04:47:03.943900 TX Vref Scan disable
2876 04:47:03.946906 == TX Byte 0 ==
2877 04:47:03.949909 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2878 04:47:03.952535 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2879 04:47:03.956057 == TX Byte 1 ==
2880 04:47:03.959111 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2881 04:47:03.962646 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2882 04:47:03.965997
2883 04:47:03.966455 [DATLAT]
2884 04:47:03.966817 Freq=1200, CH0 RK1
2885 04:47:03.967158
2886 04:47:03.969421 DATLAT Default: 0xc
2887 04:47:03.969881 0, 0xFFFF, sum = 0
2888 04:47:03.973552 1, 0xFFFF, sum = 0
2889 04:47:03.974151 2, 0xFFFF, sum = 0
2890 04:47:03.975985 3, 0xFFFF, sum = 0
2891 04:47:03.976456 4, 0xFFFF, sum = 0
2892 04:47:03.980023 5, 0xFFFF, sum = 0
2893 04:47:03.980582 6, 0xFFFF, sum = 0
2894 04:47:03.983019 7, 0xFFFF, sum = 0
2895 04:47:03.986095 8, 0xFFFF, sum = 0
2896 04:47:03.986661 9, 0xFFFF, sum = 0
2897 04:47:03.989179 10, 0xFFFF, sum = 0
2898 04:47:03.989735 11, 0x0, sum = 1
2899 04:47:03.990111 12, 0x0, sum = 2
2900 04:47:03.992632 13, 0x0, sum = 3
2901 04:47:03.993145 14, 0x0, sum = 4
2902 04:47:03.996040 best_step = 12
2903 04:47:03.996501
2904 04:47:03.997002 ==
2905 04:47:03.999246 Dram Type= 6, Freq= 0, CH_0, rank 1
2906 04:47:04.003328 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2907 04:47:04.003888 ==
2908 04:47:04.005912 RX Vref Scan: 0
2909 04:47:04.006374
2910 04:47:04.006744 RX Vref 0 -> 0, step: 1
2911 04:47:04.009494
2912 04:47:04.010045 RX Delay -21 -> 252, step: 4
2913 04:47:04.016580 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2914 04:47:04.021117 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2915 04:47:04.022702 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
2916 04:47:04.026315 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2917 04:47:04.031702 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2918 04:47:04.036802 iDelay=195, Bit 5, Center 106 (35 ~ 178) 144
2919 04:47:04.039792 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
2920 04:47:04.043025 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
2921 04:47:04.047366 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
2922 04:47:04.050827 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128
2923 04:47:04.056967 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
2924 04:47:04.059728 iDelay=195, Bit 11, Center 98 (35 ~ 162) 128
2925 04:47:04.063507 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
2926 04:47:04.066322 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2927 04:47:04.069571 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
2928 04:47:04.076901 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
2929 04:47:04.077445 ==
2930 04:47:04.079695 Dram Type= 6, Freq= 0, CH_0, rank 1
2931 04:47:04.082600 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2932 04:47:04.083070 ==
2933 04:47:04.083434 DQS Delay:
2934 04:47:04.087054 DQS0 = 0, DQS1 = 0
2935 04:47:04.087611 DQM Delay:
2936 04:47:04.089178 DQM0 = 114, DQM1 = 106
2937 04:47:04.089784 DQ Delay:
2938 04:47:04.092757 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2939 04:47:04.096452 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =124
2940 04:47:04.099444 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =98
2941 04:47:04.102779 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =116
2942 04:47:04.103337
2943 04:47:04.103705
2944 04:47:04.112876 [DQSOSCAuto] RK1, (LSB)MR18= 0xc0c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
2945 04:47:04.116367 CH0 RK1: MR19=404, MR18=C0C
2946 04:47:04.119609 CH0_RK1: MR19=0x404, MR18=0xC0C, DQSOSC=405, MR23=63, INC=39, DEC=26
2947 04:47:04.123172 [RxdqsGatingPostProcess] freq 1200
2948 04:47:04.129968 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2949 04:47:04.132822 Pre-setting of DQS Precalculation
2950 04:47:04.136443 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2951 04:47:04.137038 ==
2952 04:47:04.139411 Dram Type= 6, Freq= 0, CH_1, rank 0
2953 04:47:04.145795 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2954 04:47:04.146566 ==
2955 04:47:04.150968 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2956 04:47:04.157467 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2957 04:47:04.164630 [CA 0] Center 37 (7~68) winsize 62
2958 04:47:04.168054 [CA 1] Center 37 (6~68) winsize 63
2959 04:47:04.171592 [CA 2] Center 34 (4~65) winsize 62
2960 04:47:04.174482 [CA 3] Center 33 (3~64) winsize 62
2961 04:47:04.177514 [CA 4] Center 32 (2~63) winsize 62
2962 04:47:04.181224 [CA 5] Center 32 (2~63) winsize 62
2963 04:47:04.181688
2964 04:47:04.184131 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2965 04:47:04.184594
2966 04:47:04.188178 [CATrainingPosCal] consider 1 rank data
2967 04:47:04.191163 u2DelayCellTimex100 = 270/100 ps
2968 04:47:04.194979 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2969 04:47:04.198493 CA1 delay=37 (6~68),Diff = 5 PI (24 cell)
2970 04:47:04.204931 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2971 04:47:04.208200 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2972 04:47:04.212872 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2973 04:47:04.213878 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2974 04:47:04.214292
2975 04:47:04.218468 CA PerBit enable=1, Macro0, CA PI delay=32
2976 04:47:04.219020
2977 04:47:04.221229 [CBTSetCACLKResult] CA Dly = 32
2978 04:47:04.221786 CS Dly: 6 (0~37)
2979 04:47:04.225717 ==
2980 04:47:04.226278 Dram Type= 6, Freq= 0, CH_1, rank 1
2981 04:47:04.231428 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2982 04:47:04.232180 ==
2983 04:47:04.234824 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2984 04:47:04.241667 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2985 04:47:04.249878 [CA 0] Center 37 (6~68) winsize 63
2986 04:47:04.253755 [CA 1] Center 37 (6~68) winsize 63
2987 04:47:04.256504 [CA 2] Center 34 (3~65) winsize 63
2988 04:47:04.260242 [CA 3] Center 33 (3~64) winsize 62
2989 04:47:04.264204 [CA 4] Center 32 (2~63) winsize 62
2990 04:47:04.267435 [CA 5] Center 32 (1~63) winsize 63
2991 04:47:04.268052
2992 04:47:04.269444 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2993 04:47:04.269922
2994 04:47:04.273295 [CATrainingPosCal] consider 2 rank data
2995 04:47:04.276567 u2DelayCellTimex100 = 270/100 ps
2996 04:47:04.280896 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2997 04:47:04.283081 CA1 delay=37 (6~68),Diff = 5 PI (24 cell)
2998 04:47:04.290095 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2999 04:47:04.293119 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
3000 04:47:04.296582 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3001 04:47:04.300006 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3002 04:47:04.300617
3003 04:47:04.303263 CA PerBit enable=1, Macro0, CA PI delay=32
3004 04:47:04.303722
3005 04:47:04.306525 [CBTSetCACLKResult] CA Dly = 32
3006 04:47:04.306981 CS Dly: 6 (0~38)
3007 04:47:04.307343
3008 04:47:04.309522 ----->DramcWriteLeveling(PI) begin...
3009 04:47:04.313439 ==
3010 04:47:04.316803 Dram Type= 6, Freq= 0, CH_1, rank 0
3011 04:47:04.319326 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3012 04:47:04.319789 ==
3013 04:47:04.323177 Write leveling (Byte 0): 22 => 22
3014 04:47:04.326485 Write leveling (Byte 1): 21 => 21
3015 04:47:04.329688 DramcWriteLeveling(PI) end<-----
3016 04:47:04.330248
3017 04:47:04.330607 ==
3018 04:47:04.333191 Dram Type= 6, Freq= 0, CH_1, rank 0
3019 04:47:04.336572 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3020 04:47:04.337178 ==
3021 04:47:04.339665 [Gating] SW mode calibration
3022 04:47:04.346556 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3023 04:47:04.352884 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3024 04:47:04.356455 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3025 04:47:04.359450 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3026 04:47:04.366234 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3027 04:47:04.369038 0 11 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3028 04:47:04.372685 0 11 16 | B1->B0 | 3434 2929 | 0 1 | (0 0) (1 0)
3029 04:47:04.379918 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3030 04:47:04.382198 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3031 04:47:04.386669 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3032 04:47:04.389380 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3033 04:47:04.396356 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3034 04:47:04.399450 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3035 04:47:04.402381 0 12 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
3036 04:47:04.409285 0 12 16 | B1->B0 | 3939 4545 | 0 0 | (1 1) (0 0)
3037 04:47:04.413024 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3038 04:47:04.415920 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3039 04:47:04.422919 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3040 04:47:04.426063 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3041 04:47:04.428880 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3042 04:47:04.436330 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3043 04:47:04.439780 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3044 04:47:04.443569 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3045 04:47:04.449012 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3046 04:47:04.455141 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3047 04:47:04.456058 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3048 04:47:04.463001 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3049 04:47:04.465581 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3050 04:47:04.469657 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3051 04:47:04.475814 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3052 04:47:04.480274 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3053 04:47:04.482356 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3054 04:47:04.489319 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3055 04:47:04.492677 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3056 04:47:04.496264 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3057 04:47:04.499014 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3058 04:47:04.505933 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3059 04:47:04.509176 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3060 04:47:04.512881 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3061 04:47:04.519242 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3062 04:47:04.522451 Total UI for P1: 0, mck2ui 16
3063 04:47:04.526779 best dqsien dly found for B0: ( 0, 15, 16)
3064 04:47:04.527338 Total UI for P1: 0, mck2ui 16
3065 04:47:04.534053 best dqsien dly found for B1: ( 0, 15, 16)
3066 04:47:04.535934 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3067 04:47:04.539706 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3068 04:47:04.540260
3069 04:47:04.543572 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3070 04:47:04.545500 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3071 04:47:04.548781 [Gating] SW calibration Done
3072 04:47:04.549243 ==
3073 04:47:04.552416 Dram Type= 6, Freq= 0, CH_1, rank 0
3074 04:47:04.556471 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3075 04:47:04.557113 ==
3076 04:47:04.559178 RX Vref Scan: 0
3077 04:47:04.559640
3078 04:47:04.560003 RX Vref 0 -> 0, step: 1
3079 04:47:04.563083
3080 04:47:04.563636 RX Delay -40 -> 252, step: 8
3081 04:47:04.568912 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3082 04:47:04.572257 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3083 04:47:04.576069 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3084 04:47:04.578594 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3085 04:47:04.583371 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3086 04:47:04.588503 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3087 04:47:04.592618 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3088 04:47:04.596777 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3089 04:47:04.598644 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3090 04:47:04.602038 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
3091 04:47:04.605291 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152
3092 04:47:04.612421 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3093 04:47:04.616091 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3094 04:47:04.620021 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3095 04:47:04.622485 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3096 04:47:04.629100 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3097 04:47:04.629656 ==
3098 04:47:04.631803 Dram Type= 6, Freq= 0, CH_1, rank 0
3099 04:47:04.635138 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3100 04:47:04.635603 ==
3101 04:47:04.635970 DQS Delay:
3102 04:47:04.638700 DQS0 = 0, DQS1 = 0
3103 04:47:04.639274 DQM Delay:
3104 04:47:04.641979 DQM0 = 116, DQM1 = 109
3105 04:47:04.642434 DQ Delay:
3106 04:47:04.645404 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3107 04:47:04.648694 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3108 04:47:04.652137 DQ8 =87, DQ9 =99, DQ10 =107, DQ11 =103
3109 04:47:04.655359 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3110 04:47:04.655915
3111 04:47:04.656279
3112 04:47:04.656616 ==
3113 04:47:04.658456 Dram Type= 6, Freq= 0, CH_1, rank 0
3114 04:47:04.666288 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3115 04:47:04.667044 ==
3116 04:47:04.667438
3117 04:47:04.667777
3118 04:47:04.668100 TX Vref Scan disable
3119 04:47:04.669319 == TX Byte 0 ==
3120 04:47:04.672611 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3121 04:47:04.679219 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3122 04:47:04.679771 == TX Byte 1 ==
3123 04:47:04.682639 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3124 04:47:04.689157 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3125 04:47:04.689714 ==
3126 04:47:04.692249 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 04:47:04.696283 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3128 04:47:04.696877 ==
3129 04:47:04.706993 TX Vref=22, minBit 9, minWin=25, winSum=418
3130 04:47:04.709821 TX Vref=24, minBit 8, minWin=25, winSum=417
3131 04:47:04.713646 TX Vref=26, minBit 0, minWin=26, winSum=430
3132 04:47:04.717106 TX Vref=28, minBit 9, minWin=25, winSum=431
3133 04:47:04.719977 TX Vref=30, minBit 9, minWin=26, winSum=433
3134 04:47:04.723462 TX Vref=32, minBit 9, minWin=26, winSum=432
3135 04:47:04.730535 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 30
3136 04:47:04.731098
3137 04:47:04.733649 Final TX Range 1 Vref 30
3138 04:47:04.734206
3139 04:47:04.734577 ==
3140 04:47:04.737026 Dram Type= 6, Freq= 0, CH_1, rank 0
3141 04:47:04.739733 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3142 04:47:04.740195 ==
3143 04:47:04.740558
3144 04:47:04.743470
3145 04:47:04.744019 TX Vref Scan disable
3146 04:47:04.746736 == TX Byte 0 ==
3147 04:47:04.750005 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3148 04:47:04.753139 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3149 04:47:04.756772 == TX Byte 1 ==
3150 04:47:04.760182 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3151 04:47:04.763160 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3152 04:47:04.763717
3153 04:47:04.767313 [DATLAT]
3154 04:47:04.767772 Freq=1200, CH1 RK0
3155 04:47:04.768134
3156 04:47:04.769934 DATLAT Default: 0xd
3157 04:47:04.770499 0, 0xFFFF, sum = 0
3158 04:47:04.773336 1, 0xFFFF, sum = 0
3159 04:47:04.773802 2, 0xFFFF, sum = 0
3160 04:47:04.776842 3, 0xFFFF, sum = 0
3161 04:47:04.777310 4, 0xFFFF, sum = 0
3162 04:47:04.780604 5, 0xFFFF, sum = 0
3163 04:47:04.781217 6, 0xFFFF, sum = 0
3164 04:47:04.784375 7, 0xFFFF, sum = 0
3165 04:47:04.786461 8, 0xFFFF, sum = 0
3166 04:47:04.786929 9, 0xFFFF, sum = 0
3167 04:47:04.790088 10, 0xFFFF, sum = 0
3168 04:47:04.790661 11, 0x0, sum = 1
3169 04:47:04.791039 12, 0x0, sum = 2
3170 04:47:04.793958 13, 0x0, sum = 3
3171 04:47:04.794534 14, 0x0, sum = 4
3172 04:47:04.796670 best_step = 12
3173 04:47:04.797166
3174 04:47:04.797528 ==
3175 04:47:04.800327 Dram Type= 6, Freq= 0, CH_1, rank 0
3176 04:47:04.803764 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3177 04:47:04.804333 ==
3178 04:47:04.807289 RX Vref Scan: 1
3179 04:47:04.807855
3180 04:47:04.810138 Set Vref Range= 32 -> 127
3181 04:47:04.810595
3182 04:47:04.810956 RX Vref 32 -> 127, step: 1
3183 04:47:04.811295
3184 04:47:04.813262 RX Delay -29 -> 252, step: 4
3185 04:47:04.813833
3186 04:47:04.816505 Set Vref, RX VrefLevel [Byte0]: 32
3187 04:47:04.819673 [Byte1]: 32
3188 04:47:04.823438
3189 04:47:04.823996 Set Vref, RX VrefLevel [Byte0]: 33
3190 04:47:04.826271 [Byte1]: 33
3191 04:47:04.831511
3192 04:47:04.832066 Set Vref, RX VrefLevel [Byte0]: 34
3193 04:47:04.834697 [Byte1]: 34
3194 04:47:04.839360
3195 04:47:04.839920 Set Vref, RX VrefLevel [Byte0]: 35
3196 04:47:04.842630 [Byte1]: 35
3197 04:47:04.847365
3198 04:47:04.847926 Set Vref, RX VrefLevel [Byte0]: 36
3199 04:47:04.850232 [Byte1]: 36
3200 04:47:04.855459
3201 04:47:04.856021 Set Vref, RX VrefLevel [Byte0]: 37
3202 04:47:04.857924 [Byte1]: 37
3203 04:47:04.862681
3204 04:47:04.863138 Set Vref, RX VrefLevel [Byte0]: 38
3205 04:47:04.866126 [Byte1]: 38
3206 04:47:04.870881
3207 04:47:04.871435 Set Vref, RX VrefLevel [Byte0]: 39
3208 04:47:04.875116 [Byte1]: 39
3209 04:47:04.878479
3210 04:47:04.878973 Set Vref, RX VrefLevel [Byte0]: 40
3211 04:47:04.882179 [Byte1]: 40
3212 04:47:04.887604
3213 04:47:04.888157 Set Vref, RX VrefLevel [Byte0]: 41
3214 04:47:04.889768 [Byte1]: 41
3215 04:47:04.895459
3216 04:47:04.896018 Set Vref, RX VrefLevel [Byte0]: 42
3217 04:47:04.898455 [Byte1]: 42
3218 04:47:04.903808
3219 04:47:04.904385 Set Vref, RX VrefLevel [Byte0]: 43
3220 04:47:04.905807 [Byte1]: 43
3221 04:47:04.911305
3222 04:47:04.911860 Set Vref, RX VrefLevel [Byte0]: 44
3223 04:47:04.914368 [Byte1]: 44
3224 04:47:04.918959
3225 04:47:04.919516 Set Vref, RX VrefLevel [Byte0]: 45
3226 04:47:04.922074 [Byte1]: 45
3227 04:47:04.926515
3228 04:47:04.927078 Set Vref, RX VrefLevel [Byte0]: 46
3229 04:47:04.931482 [Byte1]: 46
3230 04:47:04.934459
3231 04:47:04.935028 Set Vref, RX VrefLevel [Byte0]: 47
3232 04:47:04.937937 [Byte1]: 47
3233 04:47:04.942850
3234 04:47:04.943415 Set Vref, RX VrefLevel [Byte0]: 48
3235 04:47:04.946010 [Byte1]: 48
3236 04:47:04.950654
3237 04:47:04.951199 Set Vref, RX VrefLevel [Byte0]: 49
3238 04:47:04.954564 [Byte1]: 49
3239 04:47:04.958687
3240 04:47:04.959291 Set Vref, RX VrefLevel [Byte0]: 50
3241 04:47:04.961596 [Byte1]: 50
3242 04:47:04.966259
3243 04:47:04.966877 Set Vref, RX VrefLevel [Byte0]: 51
3244 04:47:04.969654 [Byte1]: 51
3245 04:47:04.973904
3246 04:47:04.974360 Set Vref, RX VrefLevel [Byte0]: 52
3247 04:47:04.977708 [Byte1]: 52
3248 04:47:04.982328
3249 04:47:04.982951 Set Vref, RX VrefLevel [Byte0]: 53
3250 04:47:04.985452 [Byte1]: 53
3251 04:47:04.990236
3252 04:47:04.990709 Set Vref, RX VrefLevel [Byte0]: 54
3253 04:47:04.993971 [Byte1]: 54
3254 04:47:04.998546
3255 04:47:04.999068 Set Vref, RX VrefLevel [Byte0]: 55
3256 04:47:05.001274 [Byte1]: 55
3257 04:47:05.006196
3258 04:47:05.006703 Set Vref, RX VrefLevel [Byte0]: 56
3259 04:47:05.009934 [Byte1]: 56
3260 04:47:05.013834
3261 04:47:05.014335 Set Vref, RX VrefLevel [Byte0]: 57
3262 04:47:05.017422 [Byte1]: 57
3263 04:47:05.022681
3264 04:47:05.023238 Set Vref, RX VrefLevel [Byte0]: 58
3265 04:47:05.025393 [Byte1]: 58
3266 04:47:05.029699
3267 04:47:05.030252 Set Vref, RX VrefLevel [Byte0]: 59
3268 04:47:05.035471 [Byte1]: 59
3269 04:47:05.038220
3270 04:47:05.038782 Set Vref, RX VrefLevel [Byte0]: 60
3271 04:47:05.041165 [Byte1]: 60
3272 04:47:05.045993
3273 04:47:05.046549 Set Vref, RX VrefLevel [Byte0]: 61
3274 04:47:05.049238 [Byte1]: 61
3275 04:47:05.054175
3276 04:47:05.054631 Set Vref, RX VrefLevel [Byte0]: 62
3277 04:47:05.058069 [Byte1]: 62
3278 04:47:05.061729
3279 04:47:05.062214 Set Vref, RX VrefLevel [Byte0]: 63
3280 04:47:05.064824 [Byte1]: 63
3281 04:47:05.069777
3282 04:47:05.070328 Set Vref, RX VrefLevel [Byte0]: 64
3283 04:47:05.072639 [Byte1]: 64
3284 04:47:05.077363
3285 04:47:05.077884 Set Vref, RX VrefLevel [Byte0]: 65
3286 04:47:05.081537 [Byte1]: 65
3287 04:47:05.085678
3288 04:47:05.086095 Set Vref, RX VrefLevel [Byte0]: 66
3289 04:47:05.088909 [Byte1]: 66
3290 04:47:05.094075
3291 04:47:05.094656 Final RX Vref Byte 0 = 57 to rank0
3292 04:47:05.097653 Final RX Vref Byte 1 = 50 to rank0
3293 04:47:05.100420 Final RX Vref Byte 0 = 57 to rank1
3294 04:47:05.103853 Final RX Vref Byte 1 = 50 to rank1==
3295 04:47:05.107201 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 04:47:05.113746 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3297 04:47:05.114321 ==
3298 04:47:05.114663 DQS Delay:
3299 04:47:05.114971 DQS0 = 0, DQS1 = 0
3300 04:47:05.116810 DQM Delay:
3301 04:47:05.117227 DQM0 = 115, DQM1 = 105
3302 04:47:05.120069 DQ Delay:
3303 04:47:05.124037 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3304 04:47:05.126442 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3305 04:47:05.130368 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3306 04:47:05.134170 DQ12 =112, DQ13 =116, DQ14 =116, DQ15 =114
3307 04:47:05.134587
3308 04:47:05.134916
3309 04:47:05.139803 [DQSOSCAuto] RK0, (LSB)MR18= 0x1414, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 402 ps
3310 04:47:05.144941 CH1 RK0: MR19=404, MR18=1414
3311 04:47:05.149771 CH1_RK0: MR19=0x404, MR18=0x1414, DQSOSC=402, MR23=63, INC=40, DEC=27
3312 04:47:05.150313
3313 04:47:05.154656 ----->DramcWriteLeveling(PI) begin...
3314 04:47:05.155170 ==
3315 04:47:05.156481 Dram Type= 6, Freq= 0, CH_1, rank 1
3316 04:47:05.159883 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3317 04:47:05.164040 ==
3318 04:47:05.164499 Write leveling (Byte 0): 22 => 22
3319 04:47:05.166815 Write leveling (Byte 1): 22 => 22
3320 04:47:05.170001 DramcWriteLeveling(PI) end<-----
3321 04:47:05.170517
3322 04:47:05.170891 ==
3323 04:47:05.173307 Dram Type= 6, Freq= 0, CH_1, rank 1
3324 04:47:05.179877 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3325 04:47:05.180297 ==
3326 04:47:05.180632 [Gating] SW mode calibration
3327 04:47:05.190388 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3328 04:47:05.193297 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3329 04:47:05.199896 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3330 04:47:05.203117 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3331 04:47:05.206243 0 11 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3332 04:47:05.210139 0 11 12 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 0)
3333 04:47:05.216804 0 11 16 | B1->B0 | 3030 2323 | 0 0 | (0 1) (1 0)
3334 04:47:05.219702 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3335 04:47:05.224074 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3336 04:47:05.230343 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3337 04:47:05.233558 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3338 04:47:05.236651 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3339 04:47:05.243427 0 12 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3340 04:47:05.247103 0 12 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
3341 04:47:05.250268 0 12 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
3342 04:47:05.256858 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3343 04:47:05.260227 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3344 04:47:05.263583 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3345 04:47:05.270058 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3346 04:47:05.273348 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3347 04:47:05.276907 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3348 04:47:05.283170 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3349 04:47:05.286687 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3350 04:47:05.289683 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3351 04:47:05.297279 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3352 04:47:05.300262 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3353 04:47:05.303559 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3354 04:47:05.306321 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3355 04:47:05.313623 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3356 04:47:05.316753 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3357 04:47:05.319912 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3358 04:47:05.326701 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3359 04:47:05.329754 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3360 04:47:05.333983 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3361 04:47:05.341157 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3362 04:47:05.342884 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3363 04:47:05.346966 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3364 04:47:05.353293 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3365 04:47:05.356588 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3366 04:47:05.359571 Total UI for P1: 0, mck2ui 16
3367 04:47:05.362968 best dqsien dly found for B0: ( 0, 15, 12)
3368 04:47:05.365897 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3369 04:47:05.369113 Total UI for P1: 0, mck2ui 16
3370 04:47:05.374046 best dqsien dly found for B1: ( 0, 15, 16)
3371 04:47:05.376140 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3372 04:47:05.379196 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3373 04:47:05.379744
3374 04:47:05.386990 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3375 04:47:05.389682 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3376 04:47:05.392866 [Gating] SW calibration Done
3377 04:47:05.393088 ==
3378 04:47:05.395891 Dram Type= 6, Freq= 0, CH_1, rank 1
3379 04:47:05.398932 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3380 04:47:05.399112 ==
3381 04:47:05.399253 RX Vref Scan: 0
3382 04:47:05.399383
3383 04:47:05.402260 RX Vref 0 -> 0, step: 1
3384 04:47:05.402437
3385 04:47:05.405798 RX Delay -40 -> 252, step: 8
3386 04:47:05.410312 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3387 04:47:05.412350 iDelay=208, Bit 1, Center 115 (40 ~ 191) 152
3388 04:47:05.418761 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3389 04:47:05.421947 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3390 04:47:05.425580 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3391 04:47:05.428718 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3392 04:47:05.432252 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3393 04:47:05.438954 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3394 04:47:05.442336 iDelay=208, Bit 8, Center 91 (16 ~ 167) 152
3395 04:47:05.445345 iDelay=208, Bit 9, Center 91 (16 ~ 167) 152
3396 04:47:05.448736 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152
3397 04:47:05.452118 iDelay=208, Bit 11, Center 99 (24 ~ 175) 152
3398 04:47:05.458816 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3399 04:47:05.461900 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3400 04:47:05.465024 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3401 04:47:05.468850 iDelay=208, Bit 15, Center 111 (40 ~ 183) 144
3402 04:47:05.469267 ==
3403 04:47:05.472382 Dram Type= 6, Freq= 0, CH_1, rank 1
3404 04:47:05.479365 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3405 04:47:05.479810 ==
3406 04:47:05.480146 DQS Delay:
3407 04:47:05.480453 DQS0 = 0, DQS1 = 0
3408 04:47:05.482303 DQM Delay:
3409 04:47:05.482746 DQM0 = 116, DQM1 = 106
3410 04:47:05.486107 DQ Delay:
3411 04:47:05.489002 DQ0 =119, DQ1 =115, DQ2 =103, DQ3 =115
3412 04:47:05.493260 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3413 04:47:05.495392 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
3414 04:47:05.499115 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =111
3415 04:47:05.499626
3416 04:47:05.499960
3417 04:47:05.500265 ==
3418 04:47:05.502765 Dram Type= 6, Freq= 0, CH_1, rank 1
3419 04:47:05.505812 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3420 04:47:05.506331 ==
3421 04:47:05.506667
3422 04:47:05.509073
3423 04:47:05.509486 TX Vref Scan disable
3424 04:47:05.512245 == TX Byte 0 ==
3425 04:47:05.515612 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3426 04:47:05.519666 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3427 04:47:05.522314 == TX Byte 1 ==
3428 04:47:05.525984 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3429 04:47:05.529244 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3430 04:47:05.529756 ==
3431 04:47:05.532304 Dram Type= 6, Freq= 0, CH_1, rank 1
3432 04:47:05.539135 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3433 04:47:05.539693 ==
3434 04:47:05.549640 TX Vref=22, minBit 1, minWin=26, winSum=424
3435 04:47:05.552839 TX Vref=24, minBit 9, minWin=25, winSum=424
3436 04:47:05.555971 TX Vref=26, minBit 0, minWin=26, winSum=428
3437 04:47:05.559143 TX Vref=28, minBit 9, minWin=25, winSum=430
3438 04:47:05.562870 TX Vref=30, minBit 9, minWin=26, winSum=435
3439 04:47:05.566099 TX Vref=32, minBit 0, minWin=26, winSum=431
3440 04:47:05.572328 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
3441 04:47:05.572898
3442 04:47:05.575621 Final TX Range 1 Vref 30
3443 04:47:05.576172
3444 04:47:05.576537 ==
3445 04:47:05.579305 Dram Type= 6, Freq= 0, CH_1, rank 1
3446 04:47:05.582583 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3447 04:47:05.583154 ==
3448 04:47:05.583529
3449 04:47:05.586089
3450 04:47:05.586545 TX Vref Scan disable
3451 04:47:05.588778 == TX Byte 0 ==
3452 04:47:05.593412 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3453 04:47:05.596029 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3454 04:47:05.599176 == TX Byte 1 ==
3455 04:47:05.601891 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3456 04:47:05.605496 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3457 04:47:05.605956
3458 04:47:05.609068 [DATLAT]
3459 04:47:05.609594 Freq=1200, CH1 RK1
3460 04:47:05.609934
3461 04:47:05.612465 DATLAT Default: 0xc
3462 04:47:05.613182 0, 0xFFFF, sum = 0
3463 04:47:05.615530 1, 0xFFFF, sum = 0
3464 04:47:05.616109 2, 0xFFFF, sum = 0
3465 04:47:05.619977 3, 0xFFFF, sum = 0
3466 04:47:05.620544 4, 0xFFFF, sum = 0
3467 04:47:05.622720 5, 0xFFFF, sum = 0
3468 04:47:05.623282 6, 0xFFFF, sum = 0
3469 04:47:05.625880 7, 0xFFFF, sum = 0
3470 04:47:05.628953 8, 0xFFFF, sum = 0
3471 04:47:05.629531 9, 0xFFFF, sum = 0
3472 04:47:05.632538 10, 0xFFFF, sum = 0
3473 04:47:05.633148 11, 0x0, sum = 1
3474 04:47:05.636246 12, 0x0, sum = 2
3475 04:47:05.636847 13, 0x0, sum = 3
3476 04:47:05.637229 14, 0x0, sum = 4
3477 04:47:05.639159 best_step = 12
3478 04:47:05.639707
3479 04:47:05.640078 ==
3480 04:47:05.642812 Dram Type= 6, Freq= 0, CH_1, rank 1
3481 04:47:05.645218 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3482 04:47:05.645688 ==
3483 04:47:05.649346 RX Vref Scan: 0
3484 04:47:05.649901
3485 04:47:05.650275 RX Vref 0 -> 0, step: 1
3486 04:47:05.652798
3487 04:47:05.653261 RX Delay -29 -> 252, step: 4
3488 04:47:05.659466 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3489 04:47:05.662508 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3490 04:47:05.666207 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3491 04:47:05.669311 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3492 04:47:05.672498 iDelay=195, Bit 4, Center 114 (43 ~ 186) 144
3493 04:47:05.679696 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3494 04:47:05.682300 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3495 04:47:05.686735 iDelay=195, Bit 7, Center 114 (43 ~ 186) 144
3496 04:47:05.689384 iDelay=195, Bit 8, Center 86 (19 ~ 154) 136
3497 04:47:05.692929 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3498 04:47:05.699460 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3499 04:47:05.702603 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3500 04:47:05.706018 iDelay=195, Bit 12, Center 112 (43 ~ 182) 140
3501 04:47:05.709307 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3502 04:47:05.712452 iDelay=195, Bit 14, Center 116 (47 ~ 186) 140
3503 04:47:05.719568 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3504 04:47:05.720142 ==
3505 04:47:05.723413 Dram Type= 6, Freq= 0, CH_1, rank 1
3506 04:47:05.726967 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3507 04:47:05.727522 ==
3508 04:47:05.727894 DQS Delay:
3509 04:47:05.729109 DQS0 = 0, DQS1 = 0
3510 04:47:05.729571 DQM Delay:
3511 04:47:05.732414 DQM0 = 114, DQM1 = 104
3512 04:47:05.733034 DQ Delay:
3513 04:47:05.736575 DQ0 =114, DQ1 =112, DQ2 =108, DQ3 =112
3514 04:47:05.739339 DQ4 =114, DQ5 =122, DQ6 =122, DQ7 =114
3515 04:47:05.743104 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3516 04:47:05.745981 DQ12 =112, DQ13 =112, DQ14 =116, DQ15 =110
3517 04:47:05.746538
3518 04:47:05.746909
3519 04:47:05.755564 [DQSOSCAuto] RK1, (LSB)MR18= 0x505, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
3520 04:47:05.759134 CH1 RK1: MR19=404, MR18=505
3521 04:47:05.763299 CH1_RK1: MR19=0x404, MR18=0x505, DQSOSC=408, MR23=63, INC=39, DEC=26
3522 04:47:05.765298 [RxdqsGatingPostProcess] freq 1200
3523 04:47:05.772572 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3524 04:47:05.775486 Pre-setting of DQS Precalculation
3525 04:47:05.778655 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3526 04:47:05.789681 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3527 04:47:05.795215 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3528 04:47:05.795886
3529 04:47:05.796280
3530 04:47:05.798877 [Calibration Summary] 2400 Mbps
3531 04:47:05.799431 CH 0, Rank 0
3532 04:47:05.802733 SW Impedance : PASS
3533 04:47:05.803290 DUTY Scan : NO K
3534 04:47:05.805493 ZQ Calibration : PASS
3535 04:47:05.808932 Jitter Meter : NO K
3536 04:47:05.809386 CBT Training : PASS
3537 04:47:05.812130 Write leveling : PASS
3538 04:47:05.815568 RX DQS gating : PASS
3539 04:47:05.816125 RX DQ/DQS(RDDQC) : PASS
3540 04:47:05.818946 TX DQ/DQS : PASS
3541 04:47:05.821993 RX DATLAT : PASS
3542 04:47:05.822546 RX DQ/DQS(Engine): PASS
3543 04:47:05.826040 TX OE : NO K
3544 04:47:05.826600 All Pass.
3545 04:47:05.826970
3546 04:47:05.828800 CH 0, Rank 1
3547 04:47:05.829357 SW Impedance : PASS
3548 04:47:05.832423 DUTY Scan : NO K
3549 04:47:05.835367 ZQ Calibration : PASS
3550 04:47:05.835925 Jitter Meter : NO K
3551 04:47:05.838572 CBT Training : PASS
3552 04:47:05.841280 Write leveling : PASS
3553 04:47:05.841751 RX DQS gating : PASS
3554 04:47:05.845632 RX DQ/DQS(RDDQC) : PASS
3555 04:47:05.848317 TX DQ/DQS : PASS
3556 04:47:05.848917 RX DATLAT : PASS
3557 04:47:05.852271 RX DQ/DQS(Engine): PASS
3558 04:47:05.852869 TX OE : NO K
3559 04:47:05.854850 All Pass.
3560 04:47:05.855500
3561 04:47:05.855873 CH 1, Rank 0
3562 04:47:05.858350 SW Impedance : PASS
3563 04:47:05.858943 DUTY Scan : NO K
3564 04:47:05.861614 ZQ Calibration : PASS
3565 04:47:05.865637 Jitter Meter : NO K
3566 04:47:05.866095 CBT Training : PASS
3567 04:47:05.868428 Write leveling : PASS
3568 04:47:05.871372 RX DQS gating : PASS
3569 04:47:05.871832 RX DQ/DQS(RDDQC) : PASS
3570 04:47:05.875356 TX DQ/DQS : PASS
3571 04:47:05.877992 RX DATLAT : PASS
3572 04:47:05.878454 RX DQ/DQS(Engine): PASS
3573 04:47:05.881852 TX OE : NO K
3574 04:47:05.882309 All Pass.
3575 04:47:05.882670
3576 04:47:05.885579 CH 1, Rank 1
3577 04:47:05.886090 SW Impedance : PASS
3578 04:47:05.888245 DUTY Scan : NO K
3579 04:47:05.892327 ZQ Calibration : PASS
3580 04:47:05.892934 Jitter Meter : NO K
3581 04:47:05.895354 CBT Training : PASS
3582 04:47:05.898864 Write leveling : PASS
3583 04:47:05.899418 RX DQS gating : PASS
3584 04:47:05.901803 RX DQ/DQS(RDDQC) : PASS
3585 04:47:05.902259 TX DQ/DQS : PASS
3586 04:47:05.904772 RX DATLAT : PASS
3587 04:47:05.908290 RX DQ/DQS(Engine): PASS
3588 04:47:05.908802 TX OE : NO K
3589 04:47:05.912140 All Pass.
3590 04:47:05.912596
3591 04:47:05.913018 DramC Write-DBI off
3592 04:47:05.915122 PER_BANK_REFRESH: Hybrid Mode
3593 04:47:05.918424 TX_TRACKING: ON
3594 04:47:05.924794 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3595 04:47:05.928473 [FAST_K] Save calibration result to emmc
3596 04:47:05.931477 dramc_set_vcore_voltage set vcore to 650000
3597 04:47:05.935334 Read voltage for 600, 5
3598 04:47:05.935848 Vio18 = 0
3599 04:47:05.938705 Vcore = 650000
3600 04:47:05.939165 Vdram = 0
3601 04:47:05.939532 Vddq = 0
3602 04:47:05.941286 Vmddr = 0
3603 04:47:05.944867 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3604 04:47:05.951480 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3605 04:47:05.952036 MEM_TYPE=3, freq_sel=19
3606 04:47:05.955364 sv_algorithm_assistance_LP4_1600
3607 04:47:05.962113 ============ PULL DRAM RESETB DOWN ============
3608 04:47:05.964968 ========== PULL DRAM RESETB DOWN end =========
3609 04:47:05.968590 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3610 04:47:05.971386 ===================================
3611 04:47:05.975152 LPDDR4 DRAM CONFIGURATION
3612 04:47:05.978106 ===================================
3613 04:47:05.978571 EX_ROW_EN[0] = 0x0
3614 04:47:05.981867 EX_ROW_EN[1] = 0x0
3615 04:47:05.985206 LP4Y_EN = 0x0
3616 04:47:05.985669 WORK_FSP = 0x0
3617 04:47:05.987829 WL = 0x2
3618 04:47:05.988291 RL = 0x2
3619 04:47:05.991559 BL = 0x2
3620 04:47:05.992108 RPST = 0x0
3621 04:47:05.994948 RD_PRE = 0x0
3622 04:47:05.995501 WR_PRE = 0x1
3623 04:47:05.998376 WR_PST = 0x0
3624 04:47:05.998935 DBI_WR = 0x0
3625 04:47:06.001214 DBI_RD = 0x0
3626 04:47:06.001678 OTF = 0x1
3627 04:47:06.005084 ===================================
3628 04:47:06.007913 ===================================
3629 04:47:06.011328 ANA top config
3630 04:47:06.015147 ===================================
3631 04:47:06.015701 DLL_ASYNC_EN = 0
3632 04:47:06.018303 ALL_SLAVE_EN = 1
3633 04:47:06.022228 NEW_RANK_MODE = 1
3634 04:47:06.024428 DLL_IDLE_MODE = 1
3635 04:47:06.028221 LP45_APHY_COMB_EN = 1
3636 04:47:06.028814 TX_ODT_DIS = 1
3637 04:47:06.031395 NEW_8X_MODE = 1
3638 04:47:06.034947 ===================================
3639 04:47:06.038483 ===================================
3640 04:47:06.041555 data_rate = 1200
3641 04:47:06.044850 CKR = 1
3642 04:47:06.047800 DQ_P2S_RATIO = 8
3643 04:47:06.051578 ===================================
3644 04:47:06.052348 CA_P2S_RATIO = 8
3645 04:47:06.054389 DQ_CA_OPEN = 0
3646 04:47:06.057461 DQ_SEMI_OPEN = 0
3647 04:47:06.061101 CA_SEMI_OPEN = 0
3648 04:47:06.064250 CA_FULL_RATE = 0
3649 04:47:06.067796 DQ_CKDIV4_EN = 1
3650 04:47:06.068355 CA_CKDIV4_EN = 1
3651 04:47:06.071138 CA_PREDIV_EN = 0
3652 04:47:06.074096 PH8_DLY = 0
3653 04:47:06.078226 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3654 04:47:06.081693 DQ_AAMCK_DIV = 4
3655 04:47:06.084632 CA_AAMCK_DIV = 4
3656 04:47:06.085184 CA_ADMCK_DIV = 4
3657 04:47:06.088402 DQ_TRACK_CA_EN = 0
3658 04:47:06.091151 CA_PICK = 600
3659 04:47:06.093990 CA_MCKIO = 600
3660 04:47:06.097696 MCKIO_SEMI = 0
3661 04:47:06.101522 PLL_FREQ = 2288
3662 04:47:06.104414 DQ_UI_PI_RATIO = 32
3663 04:47:06.105012 CA_UI_PI_RATIO = 0
3664 04:47:06.107753 ===================================
3665 04:47:06.110967 ===================================
3666 04:47:06.114360 memory_type:LPDDR4
3667 04:47:06.117858 GP_NUM : 10
3668 04:47:06.118327 SRAM_EN : 1
3669 04:47:06.120683 MD32_EN : 0
3670 04:47:06.123741 ===================================
3671 04:47:06.127687 [ANA_INIT] >>>>>>>>>>>>>>
3672 04:47:06.130896 <<<<<< [CONFIGURE PHASE]: ANA_TX
3673 04:47:06.134014 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3674 04:47:06.137294 ===================================
3675 04:47:06.140130 data_rate = 1200,PCW = 0X5800
3676 04:47:06.140592 ===================================
3677 04:47:06.147577 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3678 04:47:06.150982 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3679 04:47:06.156827 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3680 04:47:06.160682 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3681 04:47:06.163694 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3682 04:47:06.167429 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3683 04:47:06.170612 [ANA_INIT] flow start
3684 04:47:06.173637 [ANA_INIT] PLL >>>>>>>>
3685 04:47:06.174100 [ANA_INIT] PLL <<<<<<<<
3686 04:47:06.176786 [ANA_INIT] MIDPI >>>>>>>>
3687 04:47:06.179961 [ANA_INIT] MIDPI <<<<<<<<
3688 04:47:06.180440 [ANA_INIT] DLL >>>>>>>>
3689 04:47:06.184247 [ANA_INIT] flow end
3690 04:47:06.186737 ============ LP4 DIFF to SE enter ============
3691 04:47:06.194180 ============ LP4 DIFF to SE exit ============
3692 04:47:06.194739 [ANA_INIT] <<<<<<<<<<<<<
3693 04:47:06.196899 [Flow] Enable top DCM control >>>>>
3694 04:47:06.200792 [Flow] Enable top DCM control <<<<<
3695 04:47:06.204054 Enable DLL master slave shuffle
3696 04:47:06.211438 ==============================================================
3697 04:47:06.211996 Gating Mode config
3698 04:47:06.216836 ==============================================================
3699 04:47:06.220385 Config description:
3700 04:47:06.226867 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3701 04:47:06.233303 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3702 04:47:06.239888 SELPH_MODE 0: By rank 1: By Phase
3703 04:47:06.247017 ==============================================================
3704 04:47:06.247576 GAT_TRACK_EN = 1
3705 04:47:06.249802 RX_GATING_MODE = 2
3706 04:47:06.253587 RX_GATING_TRACK_MODE = 2
3707 04:47:06.257207 SELPH_MODE = 1
3708 04:47:06.260137 PICG_EARLY_EN = 1
3709 04:47:06.262856 VALID_LAT_VALUE = 1
3710 04:47:06.269525 ==============================================================
3711 04:47:06.273421 Enter into Gating configuration >>>>
3712 04:47:06.275954 Exit from Gating configuration <<<<
3713 04:47:06.279688 Enter into DVFS_PRE_config >>>>>
3714 04:47:06.289277 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3715 04:47:06.292759 Exit from DVFS_PRE_config <<<<<
3716 04:47:06.296086 Enter into PICG configuration >>>>
3717 04:47:06.300423 Exit from PICG configuration <<<<
3718 04:47:06.302942 [RX_INPUT] configuration >>>>>
3719 04:47:06.306020 [RX_INPUT] configuration <<<<<
3720 04:47:06.308937 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3721 04:47:06.316483 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3722 04:47:06.322895 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3723 04:47:06.326160 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3724 04:47:06.332374 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3725 04:47:06.339268 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3726 04:47:06.342516 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3727 04:47:06.349172 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3728 04:47:06.352770 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3729 04:47:06.355461 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3730 04:47:06.358852 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3731 04:47:06.366382 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3732 04:47:06.368433 ===================================
3733 04:47:06.368939 LPDDR4 DRAM CONFIGURATION
3734 04:47:06.372752 ===================================
3735 04:47:06.375748 EX_ROW_EN[0] = 0x0
3736 04:47:06.378732 EX_ROW_EN[1] = 0x0
3737 04:47:06.379194 LP4Y_EN = 0x0
3738 04:47:06.382025 WORK_FSP = 0x0
3739 04:47:06.382486 WL = 0x2
3740 04:47:06.385256 RL = 0x2
3741 04:47:06.385812 BL = 0x2
3742 04:47:06.389582 RPST = 0x0
3743 04:47:06.390044 RD_PRE = 0x0
3744 04:47:06.392210 WR_PRE = 0x1
3745 04:47:06.393044 WR_PST = 0x0
3746 04:47:06.395512 DBI_WR = 0x0
3747 04:47:06.395970 DBI_RD = 0x0
3748 04:47:06.399221 OTF = 0x1
3749 04:47:06.401967 ===================================
3750 04:47:06.405459 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3751 04:47:06.408972 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3752 04:47:06.415400 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3753 04:47:06.419100 ===================================
3754 04:47:06.419652 LPDDR4 DRAM CONFIGURATION
3755 04:47:06.421949 ===================================
3756 04:47:06.425420 EX_ROW_EN[0] = 0x10
3757 04:47:06.428571 EX_ROW_EN[1] = 0x0
3758 04:47:06.429174 LP4Y_EN = 0x0
3759 04:47:06.431833 WORK_FSP = 0x0
3760 04:47:06.432390 WL = 0x2
3761 04:47:06.435345 RL = 0x2
3762 04:47:06.435902 BL = 0x2
3763 04:47:06.439031 RPST = 0x0
3764 04:47:06.439589 RD_PRE = 0x0
3765 04:47:06.441326 WR_PRE = 0x1
3766 04:47:06.441788 WR_PST = 0x0
3767 04:47:06.445180 DBI_WR = 0x0
3768 04:47:06.445735 DBI_RD = 0x0
3769 04:47:06.448530 OTF = 0x1
3770 04:47:06.451885 ===================================
3771 04:47:06.458053 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3772 04:47:06.461901 nWR fixed to 30
3773 04:47:06.464246 [ModeRegInit_LP4] CH0 RK0
3774 04:47:06.464789 [ModeRegInit_LP4] CH0 RK1
3775 04:47:06.467809 [ModeRegInit_LP4] CH1 RK0
3776 04:47:06.471673 [ModeRegInit_LP4] CH1 RK1
3777 04:47:06.472229 match AC timing 16
3778 04:47:06.477609 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3779 04:47:06.480965 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3780 04:47:06.484489 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3781 04:47:06.491710 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3782 04:47:06.494608 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3783 04:47:06.495164 ==
3784 04:47:06.497746 Dram Type= 6, Freq= 0, CH_0, rank 0
3785 04:47:06.501260 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3786 04:47:06.501726 ==
3787 04:47:06.508314 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3788 04:47:06.514287 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3789 04:47:06.517898 [CA 0] Center 36 (6~66) winsize 61
3790 04:47:06.521090 [CA 1] Center 35 (5~66) winsize 62
3791 04:47:06.524234 [CA 2] Center 34 (4~65) winsize 62
3792 04:47:06.527566 [CA 3] Center 34 (4~65) winsize 62
3793 04:47:06.530697 [CA 4] Center 33 (3~64) winsize 62
3794 04:47:06.534310 [CA 5] Center 33 (3~64) winsize 62
3795 04:47:06.534868
3796 04:47:06.537768 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3797 04:47:06.538319
3798 04:47:06.540729 [CATrainingPosCal] consider 1 rank data
3799 04:47:06.544283 u2DelayCellTimex100 = 270/100 ps
3800 04:47:06.547350 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3801 04:47:06.550389 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3802 04:47:06.555050 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3803 04:47:06.557701 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3804 04:47:06.560462 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3805 04:47:06.567673 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3806 04:47:06.568229
3807 04:47:06.570558 CA PerBit enable=1, Macro0, CA PI delay=33
3808 04:47:06.571017
3809 04:47:06.574182 [CBTSetCACLKResult] CA Dly = 33
3810 04:47:06.574739 CS Dly: 5 (0~36)
3811 04:47:06.575106 ==
3812 04:47:06.576962 Dram Type= 6, Freq= 0, CH_0, rank 1
3813 04:47:06.580958 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3814 04:47:06.581476 ==
3815 04:47:06.587854 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3816 04:47:06.593963 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3817 04:47:06.597568 [CA 0] Center 36 (6~66) winsize 61
3818 04:47:06.600470 [CA 1] Center 35 (5~66) winsize 62
3819 04:47:06.603567 [CA 2] Center 34 (4~65) winsize 62
3820 04:47:06.606959 [CA 3] Center 34 (3~65) winsize 63
3821 04:47:06.609978 [CA 4] Center 33 (3~64) winsize 62
3822 04:47:06.613463 [CA 5] Center 33 (3~64) winsize 62
3823 04:47:06.614024
3824 04:47:06.617324 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3825 04:47:06.617880
3826 04:47:06.620783 [CATrainingPosCal] consider 2 rank data
3827 04:47:06.623252 u2DelayCellTimex100 = 270/100 ps
3828 04:47:06.626798 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3829 04:47:06.630510 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3830 04:47:06.633406 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3831 04:47:06.637599 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3832 04:47:06.644526 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3833 04:47:06.647439 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3834 04:47:06.647992
3835 04:47:06.650632 CA PerBit enable=1, Macro0, CA PI delay=33
3836 04:47:06.651189
3837 04:47:06.653129 [CBTSetCACLKResult] CA Dly = 33
3838 04:47:06.653588 CS Dly: 5 (0~36)
3839 04:47:06.653956
3840 04:47:06.656511 ----->DramcWriteLeveling(PI) begin...
3841 04:47:06.657122 ==
3842 04:47:06.659606 Dram Type= 6, Freq= 0, CH_0, rank 0
3843 04:47:06.666776 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3844 04:47:06.667333 ==
3845 04:47:06.670565 Write leveling (Byte 0): 31 => 31
3846 04:47:06.673260 Write leveling (Byte 1): 31 => 31
3847 04:47:06.673723 DramcWriteLeveling(PI) end<-----
3848 04:47:06.676934
3849 04:47:06.677486 ==
3850 04:47:06.679496 Dram Type= 6, Freq= 0, CH_0, rank 0
3851 04:47:06.682718 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3852 04:47:06.683180 ==
3853 04:47:06.687367 [Gating] SW mode calibration
3854 04:47:06.692928 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3855 04:47:06.696553 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3856 04:47:06.703439 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3857 04:47:06.706213 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3858 04:47:06.709864 0 5 8 | B1->B0 | 3333 3030 | 1 1 | (1 0) (0 0)
3859 04:47:06.716841 0 5 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3860 04:47:06.719633 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3861 04:47:06.723038 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3862 04:47:06.729986 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3863 04:47:06.733253 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3864 04:47:06.736084 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3865 04:47:06.742948 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3866 04:47:06.745745 0 6 8 | B1->B0 | 2b2b 3333 | 0 0 | (1 1) (0 0)
3867 04:47:06.750034 0 6 12 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
3868 04:47:06.756439 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3869 04:47:06.759167 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3870 04:47:06.762942 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3871 04:47:06.769205 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3872 04:47:06.772816 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3873 04:47:06.776433 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3874 04:47:06.781906 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3875 04:47:06.786771 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3876 04:47:06.788819 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3877 04:47:06.795755 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3878 04:47:06.800526 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3879 04:47:06.802486 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3880 04:47:06.809448 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3881 04:47:06.812207 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3882 04:47:06.815335 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3883 04:47:06.822064 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3884 04:47:06.825681 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3885 04:47:06.828459 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3886 04:47:06.835840 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3887 04:47:06.838660 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3888 04:47:06.841924 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3889 04:47:06.848814 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3890 04:47:06.851921 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3891 04:47:06.855241 Total UI for P1: 0, mck2ui 16
3892 04:47:06.858391 best dqsien dly found for B0: ( 0, 9, 6)
3893 04:47:06.862135 Total UI for P1: 0, mck2ui 16
3894 04:47:06.864983 best dqsien dly found for B1: ( 0, 9, 6)
3895 04:47:06.868863 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
3896 04:47:06.872145 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
3897 04:47:06.872662
3898 04:47:06.874755 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
3899 04:47:06.878091 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
3900 04:47:06.881476 [Gating] SW calibration Done
3901 04:47:06.881899 ==
3902 04:47:06.884578 Dram Type= 6, Freq= 0, CH_0, rank 0
3903 04:47:06.888326 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3904 04:47:06.888805 ==
3905 04:47:06.891789 RX Vref Scan: 0
3906 04:47:06.892299
3907 04:47:06.895580 RX Vref 0 -> 0, step: 1
3908 04:47:06.896106
3909 04:47:06.896445 RX Delay -230 -> 252, step: 16
3910 04:47:06.901859 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3911 04:47:06.905048 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3912 04:47:06.908147 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3913 04:47:06.911762 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3914 04:47:06.918382 iDelay=218, Bit 4, Center 41 (-134 ~ 217) 352
3915 04:47:06.921362 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
3916 04:47:06.925111 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3917 04:47:06.928064 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3918 04:47:06.935253 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3919 04:47:06.939516 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3920 04:47:06.941003 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3921 04:47:06.944827 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3922 04:47:06.948101 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3923 04:47:06.954651 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3924 04:47:06.958128 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3925 04:47:06.961010 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3926 04:47:06.961743 ==
3927 04:47:06.964691 Dram Type= 6, Freq= 0, CH_0, rank 0
3928 04:47:06.971439 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3929 04:47:06.971953 ==
3930 04:47:06.972289 DQS Delay:
3931 04:47:06.972598 DQS0 = 0, DQS1 = 0
3932 04:47:06.974411 DQM Delay:
3933 04:47:06.974923 DQM0 = 38, DQM1 = 33
3934 04:47:06.977925 DQ Delay:
3935 04:47:06.981417 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3936 04:47:06.984313 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
3937 04:47:06.987406 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3938 04:47:06.990931 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3939 04:47:06.991449
3940 04:47:06.991785
3941 04:47:06.992093 ==
3942 04:47:06.994583 Dram Type= 6, Freq= 0, CH_0, rank 0
3943 04:47:06.997308 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3944 04:47:06.997730 ==
3945 04:47:06.998092
3946 04:47:06.998440
3947 04:47:07.001104 TX Vref Scan disable
3948 04:47:07.001609 == TX Byte 0 ==
3949 04:47:07.007755 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3950 04:47:07.010350 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3951 04:47:07.010813 == TX Byte 1 ==
3952 04:47:07.019389 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
3953 04:47:07.020989 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
3954 04:47:07.021451 ==
3955 04:47:07.024067 Dram Type= 6, Freq= 0, CH_0, rank 0
3956 04:47:07.027965 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3957 04:47:07.028520 ==
3958 04:47:07.028936
3959 04:47:07.030870
3960 04:47:07.031418 TX Vref Scan disable
3961 04:47:07.034098 == TX Byte 0 ==
3962 04:47:07.037183 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3963 04:47:07.044223 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3964 04:47:07.044823 == TX Byte 1 ==
3965 04:47:07.047518 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
3966 04:47:07.053793 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
3967 04:47:07.054348
3968 04:47:07.054713 [DATLAT]
3969 04:47:07.055052 Freq=600, CH0 RK0
3970 04:47:07.055540
3971 04:47:07.056930 DATLAT Default: 0x9
3972 04:47:07.057390 0, 0xFFFF, sum = 0
3973 04:47:07.060481 1, 0xFFFF, sum = 0
3974 04:47:07.063701 2, 0xFFFF, sum = 0
3975 04:47:07.064169 3, 0xFFFF, sum = 0
3976 04:47:07.067112 4, 0xFFFF, sum = 0
3977 04:47:07.067576 5, 0xFFFF, sum = 0
3978 04:47:07.070434 6, 0xFFFF, sum = 0
3979 04:47:07.070952 7, 0x0, sum = 1
3980 04:47:07.071333 8, 0x0, sum = 2
3981 04:47:07.073381 9, 0x0, sum = 3
3982 04:47:07.073849 10, 0x0, sum = 4
3983 04:47:07.076861 best_step = 8
3984 04:47:07.077278
3985 04:47:07.077608 ==
3986 04:47:07.080222 Dram Type= 6, Freq= 0, CH_0, rank 0
3987 04:47:07.083463 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3988 04:47:07.083911 ==
3989 04:47:07.087218 RX Vref Scan: 1
3990 04:47:07.087731
3991 04:47:07.088065 RX Vref 0 -> 0, step: 1
3992 04:47:07.088376
3993 04:47:07.090434 RX Delay -195 -> 252, step: 8
3994 04:47:07.090945
3995 04:47:07.093494 Set Vref, RX VrefLevel [Byte0]: 45
3996 04:47:07.096966 [Byte1]: 52
3997 04:47:07.100851
3998 04:47:07.101360 Final RX Vref Byte 0 = 45 to rank0
3999 04:47:07.104201 Final RX Vref Byte 1 = 52 to rank0
4000 04:47:07.107569 Final RX Vref Byte 0 = 45 to rank1
4001 04:47:07.111119 Final RX Vref Byte 1 = 52 to rank1==
4002 04:47:07.114752 Dram Type= 6, Freq= 0, CH_0, rank 0
4003 04:47:07.120939 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4004 04:47:07.121456 ==
4005 04:47:07.121792 DQS Delay:
4006 04:47:07.124599 DQS0 = 0, DQS1 = 0
4007 04:47:07.125046 DQM Delay:
4008 04:47:07.125374 DQM0 = 41, DQM1 = 30
4009 04:47:07.129230 DQ Delay:
4010 04:47:07.130584 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =36
4011 04:47:07.134151 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4012 04:47:07.138032 DQ8 =20, DQ9 =12, DQ10 =32, DQ11 =20
4013 04:47:07.141682 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4014 04:47:07.142102
4015 04:47:07.142435
4016 04:47:07.147583 [DQSOSCAuto] RK0, (LSB)MR18= 0x5050, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
4017 04:47:07.151133 CH0 RK0: MR19=808, MR18=5050
4018 04:47:07.157612 CH0_RK0: MR19=0x808, MR18=0x5050, DQSOSC=394, MR23=63, INC=168, DEC=112
4019 04:47:07.158165
4020 04:47:07.160577 ----->DramcWriteLeveling(PI) begin...
4021 04:47:07.161184 ==
4022 04:47:07.163744 Dram Type= 6, Freq= 0, CH_0, rank 1
4023 04:47:07.167773 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4024 04:47:07.168232 ==
4025 04:47:07.170532 Write leveling (Byte 0): 31 => 31
4026 04:47:07.173979 Write leveling (Byte 1): 28 => 28
4027 04:47:07.177332 DramcWriteLeveling(PI) end<-----
4028 04:47:07.177884
4029 04:47:07.178251 ==
4030 04:47:07.180548 Dram Type= 6, Freq= 0, CH_0, rank 1
4031 04:47:07.183867 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4032 04:47:07.184337 ==
4033 04:47:07.187850 [Gating] SW mode calibration
4034 04:47:07.194133 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4035 04:47:07.201059 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4036 04:47:07.204367 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4037 04:47:07.210846 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4038 04:47:07.213689 0 5 8 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (0 0)
4039 04:47:07.217165 0 5 12 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
4040 04:47:07.223057 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 04:47:07.226742 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 04:47:07.229884 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 04:47:07.236584 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 04:47:07.240093 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 04:47:07.244123 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 04:47:07.250106 0 6 8 | B1->B0 | 2a2a 3434 | 1 0 | (0 0) (0 0)
4047 04:47:07.253933 0 6 12 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
4048 04:47:07.256388 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 04:47:07.262992 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 04:47:07.266173 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 04:47:07.269702 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 04:47:07.276084 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 04:47:07.280252 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 04:47:07.282401 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4055 04:47:07.289078 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 04:47:07.293436 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 04:47:07.295938 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 04:47:07.299136 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 04:47:07.305906 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 04:47:07.309352 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 04:47:07.312558 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 04:47:07.319623 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 04:47:07.322834 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 04:47:07.326420 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 04:47:07.332845 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 04:47:07.336483 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 04:47:07.339912 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 04:47:07.346589 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 04:47:07.349539 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 04:47:07.352492 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4071 04:47:07.359824 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 04:47:07.362359 Total UI for P1: 0, mck2ui 16
4073 04:47:07.365724 best dqsien dly found for B0: ( 0, 9, 8)
4074 04:47:07.369293 Total UI for P1: 0, mck2ui 16
4075 04:47:07.372949 best dqsien dly found for B1: ( 0, 9, 8)
4076 04:47:07.376227 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4077 04:47:07.379100 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4078 04:47:07.379673
4079 04:47:07.381840 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4080 04:47:07.385592 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4081 04:47:07.389110 [Gating] SW calibration Done
4082 04:47:07.389676 ==
4083 04:47:07.392205 Dram Type= 6, Freq= 0, CH_0, rank 1
4084 04:47:07.397083 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4085 04:47:07.397652 ==
4086 04:47:07.399000 RX Vref Scan: 0
4087 04:47:07.399460
4088 04:47:07.399821 RX Vref 0 -> 0, step: 1
4089 04:47:07.400167
4090 04:47:07.402276 RX Delay -230 -> 252, step: 16
4091 04:47:07.408798 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4092 04:47:07.411845 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4093 04:47:07.415640 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4094 04:47:07.418802 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4095 04:47:07.424946 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4096 04:47:07.428750 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4097 04:47:07.432254 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4098 04:47:07.435198 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4099 04:47:07.438681 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4100 04:47:07.445267 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4101 04:47:07.449358 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4102 04:47:07.451777 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4103 04:47:07.455607 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4104 04:47:07.461669 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4105 04:47:07.464811 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4106 04:47:07.468401 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4107 04:47:07.468894 ==
4108 04:47:07.471625 Dram Type= 6, Freq= 0, CH_0, rank 1
4109 04:47:07.475638 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4110 04:47:07.478135 ==
4111 04:47:07.478596 DQS Delay:
4112 04:47:07.478961 DQS0 = 0, DQS1 = 0
4113 04:47:07.481506 DQM Delay:
4114 04:47:07.481970 DQM0 = 42, DQM1 = 33
4115 04:47:07.484807 DQ Delay:
4116 04:47:07.488092 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =41
4117 04:47:07.488647 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4118 04:47:07.491476 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4119 04:47:07.495282 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4120 04:47:07.497933
4121 04:47:07.498486
4122 04:47:07.498853 ==
4123 04:47:07.501190 Dram Type= 6, Freq= 0, CH_0, rank 1
4124 04:47:07.505741 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4125 04:47:07.506300 ==
4126 04:47:07.506667
4127 04:47:07.507006
4128 04:47:07.508001 TX Vref Scan disable
4129 04:47:07.508525 == TX Byte 0 ==
4130 04:47:07.514425 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4131 04:47:07.518359 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4132 04:47:07.518824 == TX Byte 1 ==
4133 04:47:07.525247 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4134 04:47:07.527701 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4135 04:47:07.528257 ==
4136 04:47:07.530857 Dram Type= 6, Freq= 0, CH_0, rank 1
4137 04:47:07.534248 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4138 04:47:07.534803 ==
4139 04:47:07.535172
4140 04:47:07.535508
4141 04:47:07.537884 TX Vref Scan disable
4142 04:47:07.540865 == TX Byte 0 ==
4143 04:47:07.544285 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4144 04:47:07.550851 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4145 04:47:07.551405 == TX Byte 1 ==
4146 04:47:07.554701 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4147 04:47:07.561133 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4148 04:47:07.561686
4149 04:47:07.562054 [DATLAT]
4150 04:47:07.562397 Freq=600, CH0 RK1
4151 04:47:07.562729
4152 04:47:07.565762 DATLAT Default: 0x8
4153 04:47:07.566226 0, 0xFFFF, sum = 0
4154 04:47:07.568144 1, 0xFFFF, sum = 0
4155 04:47:07.571022 2, 0xFFFF, sum = 0
4156 04:47:07.571488 3, 0xFFFF, sum = 0
4157 04:47:07.574303 4, 0xFFFF, sum = 0
4158 04:47:07.574768 5, 0xFFFF, sum = 0
4159 04:47:07.577126 6, 0xFFFF, sum = 0
4160 04:47:07.577594 7, 0x0, sum = 1
4161 04:47:07.577964 8, 0x0, sum = 2
4162 04:47:07.581621 9, 0x0, sum = 3
4163 04:47:07.582092 10, 0x0, sum = 4
4164 04:47:07.583731 best_step = 8
4165 04:47:07.584188
4166 04:47:07.584609 ==
4167 04:47:07.587524 Dram Type= 6, Freq= 0, CH_0, rank 1
4168 04:47:07.590858 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4169 04:47:07.591320 ==
4170 04:47:07.594182 RX Vref Scan: 0
4171 04:47:07.594777
4172 04:47:07.595155 RX Vref 0 -> 0, step: 1
4173 04:47:07.595500
4174 04:47:07.597446 RX Delay -195 -> 252, step: 8
4175 04:47:07.604549 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4176 04:47:07.607897 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4177 04:47:07.611626 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4178 04:47:07.614426 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4179 04:47:07.620915 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4180 04:47:07.624398 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4181 04:47:07.628552 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4182 04:47:07.630944 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4183 04:47:07.637881 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4184 04:47:07.641051 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4185 04:47:07.644071 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4186 04:47:07.648086 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4187 04:47:07.654518 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4188 04:47:07.656990 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4189 04:47:07.660700 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4190 04:47:07.664100 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4191 04:47:07.664672 ==
4192 04:47:07.667066 Dram Type= 6, Freq= 0, CH_0, rank 1
4193 04:47:07.673522 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4194 04:47:07.674085 ==
4195 04:47:07.674456 DQS Delay:
4196 04:47:07.677205 DQS0 = 0, DQS1 = 0
4197 04:47:07.677687 DQM Delay:
4198 04:47:07.678094 DQM0 = 41, DQM1 = 32
4199 04:47:07.683205 DQ Delay:
4200 04:47:07.684020 DQ0 =36, DQ1 =44, DQ2 =40, DQ3 =36
4201 04:47:07.687158 DQ4 =44, DQ5 =32, DQ6 =44, DQ7 =52
4202 04:47:07.690742 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4203 04:47:07.694321 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4204 04:47:07.694878
4205 04:47:07.695243
4206 04:47:07.700085 [DQSOSCAuto] RK1, (LSB)MR18= 0x6666, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
4207 04:47:07.703975 CH0 RK1: MR19=808, MR18=6666
4208 04:47:07.710411 CH0_RK1: MR19=0x808, MR18=0x6666, DQSOSC=390, MR23=63, INC=172, DEC=114
4209 04:47:07.713353 [RxdqsGatingPostProcess] freq 600
4210 04:47:07.717785 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4211 04:47:07.720331 Pre-setting of DQS Precalculation
4212 04:47:07.727626 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4213 04:47:07.728189 ==
4214 04:47:07.730767 Dram Type= 6, Freq= 0, CH_1, rank 0
4215 04:47:07.734514 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4216 04:47:07.735071 ==
4217 04:47:07.740523 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4218 04:47:07.743487 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4219 04:47:07.748461 [CA 0] Center 35 (5~66) winsize 62
4220 04:47:07.752742 [CA 1] Center 35 (5~66) winsize 62
4221 04:47:07.754967 [CA 2] Center 33 (3~64) winsize 62
4222 04:47:07.758311 [CA 3] Center 33 (3~64) winsize 62
4223 04:47:07.761102 [CA 4] Center 33 (2~64) winsize 63
4224 04:47:07.764750 [CA 5] Center 33 (2~64) winsize 63
4225 04:47:07.765221
4226 04:47:07.767827 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4227 04:47:07.768290
4228 04:47:07.771363 [CATrainingPosCal] consider 1 rank data
4229 04:47:07.774321 u2DelayCellTimex100 = 270/100 ps
4230 04:47:07.777760 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4231 04:47:07.786370 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4232 04:47:07.787624 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4233 04:47:07.792111 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4234 04:47:07.794613 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4235 04:47:07.797641 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4236 04:47:07.798104
4237 04:47:07.800860 CA PerBit enable=1, Macro0, CA PI delay=33
4238 04:47:07.801324
4239 04:47:07.804201 [CBTSetCACLKResult] CA Dly = 33
4240 04:47:07.808037 CS Dly: 3 (0~34)
4241 04:47:07.808496 ==
4242 04:47:07.810993 Dram Type= 6, Freq= 0, CH_1, rank 1
4243 04:47:07.813855 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4244 04:47:07.814318 ==
4245 04:47:07.821465 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4246 04:47:07.824249 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4247 04:47:07.828679 [CA 0] Center 35 (4~66) winsize 63
4248 04:47:07.831755 [CA 1] Center 34 (4~65) winsize 62
4249 04:47:07.835118 [CA 2] Center 33 (3~64) winsize 62
4250 04:47:07.838674 [CA 3] Center 33 (3~64) winsize 62
4251 04:47:07.841533 [CA 4] Center 32 (2~63) winsize 62
4252 04:47:07.844768 [CA 5] Center 32 (2~63) winsize 62
4253 04:47:07.845328
4254 04:47:07.848389 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4255 04:47:07.848986
4256 04:47:07.851518 [CATrainingPosCal] consider 2 rank data
4257 04:47:07.855531 u2DelayCellTimex100 = 270/100 ps
4258 04:47:07.858034 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4259 04:47:07.864774 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4260 04:47:07.867919 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4261 04:47:07.871299 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4262 04:47:07.874553 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4263 04:47:07.877454 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4264 04:47:07.877917
4265 04:47:07.881058 CA PerBit enable=1, Macro0, CA PI delay=32
4266 04:47:07.881547
4267 04:47:07.884251 [CBTSetCACLKResult] CA Dly = 32
4268 04:47:07.887501 CS Dly: 4 (0~36)
4269 04:47:07.888096
4270 04:47:07.891355 ----->DramcWriteLeveling(PI) begin...
4271 04:47:07.891820 ==
4272 04:47:07.894905 Dram Type= 6, Freq= 0, CH_1, rank 0
4273 04:47:07.897463 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4274 04:47:07.897932 ==
4275 04:47:07.900573 Write leveling (Byte 0): 28 => 28
4276 04:47:07.904153 Write leveling (Byte 1): 28 => 28
4277 04:47:07.907684 DramcWriteLeveling(PI) end<-----
4278 04:47:07.908249
4279 04:47:07.908619 ==
4280 04:47:07.910570 Dram Type= 6, Freq= 0, CH_1, rank 0
4281 04:47:07.914630 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4282 04:47:07.915093 ==
4283 04:47:07.917214 [Gating] SW mode calibration
4284 04:47:07.924135 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4285 04:47:07.930839 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4286 04:47:07.934374 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4287 04:47:07.937524 0 5 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4288 04:47:07.943741 0 5 8 | B1->B0 | 2f2f 2828 | 0 0 | (1 1) (1 1)
4289 04:47:07.948971 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4290 04:47:07.950953 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4291 04:47:07.957633 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4292 04:47:07.960640 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4293 04:47:07.963659 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4294 04:47:07.971436 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4295 04:47:07.974104 0 6 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
4296 04:47:07.977828 0 6 8 | B1->B0 | 3535 4040 | 0 0 | (1 1) (0 0)
4297 04:47:07.983402 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4298 04:47:07.986717 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4299 04:47:07.991069 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4300 04:47:07.996808 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4301 04:47:07.999872 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4302 04:47:08.004302 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4303 04:47:08.010304 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4304 04:47:08.013468 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 04:47:08.017259 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 04:47:08.023951 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 04:47:08.027476 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 04:47:08.030437 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 04:47:08.033285 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 04:47:08.040127 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4311 04:47:08.043679 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4312 04:47:08.046279 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4313 04:47:08.053522 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4314 04:47:08.056430 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4315 04:47:08.059547 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4316 04:47:08.067102 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4317 04:47:08.071048 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4318 04:47:08.072839 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4319 04:47:08.079620 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4320 04:47:08.083079 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4321 04:47:08.086139 Total UI for P1: 0, mck2ui 16
4322 04:47:08.090012 best dqsien dly found for B0: ( 0, 9, 4)
4323 04:47:08.093701 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4324 04:47:08.099703 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4325 04:47:08.103360 Total UI for P1: 0, mck2ui 16
4326 04:47:08.105988 best dqsien dly found for B1: ( 0, 9, 8)
4327 04:47:08.109605 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4328 04:47:08.113295 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4329 04:47:08.113863
4330 04:47:08.116409 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4331 04:47:08.119871 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4332 04:47:08.123004 [Gating] SW calibration Done
4333 04:47:08.123466 ==
4334 04:47:08.126434 Dram Type= 6, Freq= 0, CH_1, rank 0
4335 04:47:08.129228 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4336 04:47:08.129802 ==
4337 04:47:08.132662 RX Vref Scan: 0
4338 04:47:08.133274
4339 04:47:08.133646 RX Vref 0 -> 0, step: 1
4340 04:47:08.133989
4341 04:47:08.135799 RX Delay -230 -> 252, step: 16
4342 04:47:08.142482 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4343 04:47:08.145803 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4344 04:47:08.149140 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4345 04:47:08.152480 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4346 04:47:08.159305 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4347 04:47:08.162357 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4348 04:47:08.165807 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4349 04:47:08.168582 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4350 04:47:08.172353 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4351 04:47:08.179340 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4352 04:47:08.182481 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4353 04:47:08.185580 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4354 04:47:08.188268 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4355 04:47:08.195007 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4356 04:47:08.198836 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4357 04:47:08.201463 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4358 04:47:08.201925 ==
4359 04:47:08.205055 Dram Type= 6, Freq= 0, CH_1, rank 0
4360 04:47:08.208409 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4361 04:47:08.211716 ==
4362 04:47:08.212169 DQS Delay:
4363 04:47:08.212531 DQS0 = 0, DQS1 = 0
4364 04:47:08.214988 DQM Delay:
4365 04:47:08.215440 DQM0 = 39, DQM1 = 33
4366 04:47:08.218278 DQ Delay:
4367 04:47:08.221527 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4368 04:47:08.221983 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4369 04:47:08.225396 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4370 04:47:08.228577 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =49
4371 04:47:08.232111
4372 04:47:08.232653
4373 04:47:08.233078 ==
4374 04:47:08.235231 Dram Type= 6, Freq= 0, CH_1, rank 0
4375 04:47:08.238889 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4376 04:47:08.239444 ==
4377 04:47:08.239806
4378 04:47:08.240140
4379 04:47:08.241680 TX Vref Scan disable
4380 04:47:08.242137 == TX Byte 0 ==
4381 04:47:08.248218 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4382 04:47:08.251908 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4383 04:47:08.252602 == TX Byte 1 ==
4384 04:47:08.258449 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4385 04:47:08.261278 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4386 04:47:08.261735 ==
4387 04:47:08.264602 Dram Type= 6, Freq= 0, CH_1, rank 0
4388 04:47:08.268086 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4389 04:47:08.268832 ==
4390 04:47:08.269336
4391 04:47:08.269688
4392 04:47:08.270942 TX Vref Scan disable
4393 04:47:08.274189 == TX Byte 0 ==
4394 04:47:08.277722 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4395 04:47:08.284568 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4396 04:47:08.285246 == TX Byte 1 ==
4397 04:47:08.288157 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4398 04:47:08.294606 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4399 04:47:08.295144
4400 04:47:08.295506 [DATLAT]
4401 04:47:08.295845 Freq=600, CH1 RK0
4402 04:47:08.296174
4403 04:47:08.297978 DATLAT Default: 0x9
4404 04:47:08.298525 0, 0xFFFF, sum = 0
4405 04:47:08.301218 1, 0xFFFF, sum = 0
4406 04:47:08.304897 2, 0xFFFF, sum = 0
4407 04:47:08.305450 3, 0xFFFF, sum = 0
4408 04:47:08.307492 4, 0xFFFF, sum = 0
4409 04:47:08.308053 5, 0xFFFF, sum = 0
4410 04:47:08.310756 6, 0xFFFF, sum = 0
4411 04:47:08.311221 7, 0x0, sum = 1
4412 04:47:08.314300 8, 0x0, sum = 2
4413 04:47:08.314863 9, 0x0, sum = 3
4414 04:47:08.315239 10, 0x0, sum = 4
4415 04:47:08.317203 best_step = 8
4416 04:47:08.317778
4417 04:47:08.318159 ==
4418 04:47:08.321214 Dram Type= 6, Freq= 0, CH_1, rank 0
4419 04:47:08.324281 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4420 04:47:08.324770 ==
4421 04:47:08.327717 RX Vref Scan: 1
4422 04:47:08.328290
4423 04:47:08.328922 RX Vref 0 -> 0, step: 1
4424 04:47:08.330699
4425 04:47:08.331269 RX Delay -195 -> 252, step: 8
4426 04:47:08.331781
4427 04:47:08.333800 Set Vref, RX VrefLevel [Byte0]: 57
4428 04:47:08.336919 [Byte1]: 50
4429 04:47:08.341915
4430 04:47:08.342466 Final RX Vref Byte 0 = 57 to rank0
4431 04:47:08.345455 Final RX Vref Byte 1 = 50 to rank0
4432 04:47:08.349123 Final RX Vref Byte 0 = 57 to rank1
4433 04:47:08.351609 Final RX Vref Byte 1 = 50 to rank1==
4434 04:47:08.355387 Dram Type= 6, Freq= 0, CH_1, rank 0
4435 04:47:08.361395 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4436 04:47:08.361857 ==
4437 04:47:08.362276 DQS Delay:
4438 04:47:08.362626 DQS0 = 0, DQS1 = 0
4439 04:47:08.365214 DQM Delay:
4440 04:47:08.365671 DQM0 = 37, DQM1 = 32
4441 04:47:08.368305 DQ Delay:
4442 04:47:08.371363 DQ0 =44, DQ1 =28, DQ2 =28, DQ3 =36
4443 04:47:08.374655 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4444 04:47:08.378629 DQ8 =16, DQ9 =20, DQ10 =36, DQ11 =24
4445 04:47:08.381212 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4446 04:47:08.381671
4447 04:47:08.382038
4448 04:47:08.388292 [DQSOSCAuto] RK0, (LSB)MR18= 0x6d6d, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4449 04:47:08.392148 CH1 RK0: MR19=808, MR18=6D6D
4450 04:47:08.398653 CH1_RK0: MR19=0x808, MR18=0x6D6D, DQSOSC=389, MR23=63, INC=173, DEC=115
4451 04:47:08.399212
4452 04:47:08.401834 ----->DramcWriteLeveling(PI) begin...
4453 04:47:08.402302 ==
4454 04:47:08.404994 Dram Type= 6, Freq= 0, CH_1, rank 1
4455 04:47:08.409011 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4456 04:47:08.409460 ==
4457 04:47:08.411735 Write leveling (Byte 0): 27 => 27
4458 04:47:08.414710 Write leveling (Byte 1): 27 => 27
4459 04:47:08.417844 DramcWriteLeveling(PI) end<-----
4460 04:47:08.418401
4461 04:47:08.418763 ==
4462 04:47:08.421554 Dram Type= 6, Freq= 0, CH_1, rank 1
4463 04:47:08.425143 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4464 04:47:08.425707 ==
4465 04:47:08.427787 [Gating] SW mode calibration
4466 04:47:08.434356 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4467 04:47:08.441340 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4468 04:47:08.444571 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4469 04:47:08.451020 0 5 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 1)
4470 04:47:08.454687 0 5 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4471 04:47:08.457411 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 04:47:08.464819 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 04:47:08.467742 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 04:47:08.470905 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 04:47:08.477481 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 04:47:08.480472 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 04:47:08.483872 0 6 4 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
4478 04:47:08.490788 0 6 8 | B1->B0 | 3838 4545 | 0 0 | (0 0) (0 0)
4479 04:47:08.494115 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 04:47:08.497447 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 04:47:08.500609 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 04:47:08.506912 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 04:47:08.510785 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 04:47:08.514737 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 04:47:08.520416 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4486 04:47:08.524214 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 04:47:08.527253 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 04:47:08.534110 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 04:47:08.537559 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 04:47:08.540431 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 04:47:08.547312 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 04:47:08.550742 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 04:47:08.553587 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 04:47:08.560759 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 04:47:08.563695 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 04:47:08.567228 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 04:47:08.575061 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 04:47:08.577237 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 04:47:08.580593 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 04:47:08.586859 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 04:47:08.589828 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 04:47:08.593454 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 04:47:08.596409 Total UI for P1: 0, mck2ui 16
4504 04:47:08.600239 best dqsien dly found for B0: ( 0, 9, 6)
4505 04:47:08.603188 Total UI for P1: 0, mck2ui 16
4506 04:47:08.606688 best dqsien dly found for B1: ( 0, 9, 6)
4507 04:47:08.610286 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4508 04:47:08.613420 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4509 04:47:08.613982
4510 04:47:08.619761 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4511 04:47:08.623613 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4512 04:47:08.626230 [Gating] SW calibration Done
4513 04:47:08.626698 ==
4514 04:47:08.629352 Dram Type= 6, Freq= 0, CH_1, rank 1
4515 04:47:08.633277 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4516 04:47:08.633842 ==
4517 04:47:08.634210 RX Vref Scan: 0
4518 04:47:08.634552
4519 04:47:08.636314 RX Vref 0 -> 0, step: 1
4520 04:47:08.636912
4521 04:47:08.640589 RX Delay -230 -> 252, step: 16
4522 04:47:08.642764 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4523 04:47:08.646259 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4524 04:47:08.653267 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4525 04:47:08.656683 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4526 04:47:08.659487 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4527 04:47:08.662928 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4528 04:47:08.669362 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4529 04:47:08.672606 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4530 04:47:08.677513 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4531 04:47:08.679233 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4532 04:47:08.687742 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4533 04:47:08.688897 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4534 04:47:08.692894 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4535 04:47:08.696045 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4536 04:47:08.702162 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4537 04:47:08.705451 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4538 04:47:08.706018 ==
4539 04:47:08.710211 Dram Type= 6, Freq= 0, CH_1, rank 1
4540 04:47:08.712773 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4541 04:47:08.713350 ==
4542 04:47:08.715304 DQS Delay:
4543 04:47:08.715765 DQS0 = 0, DQS1 = 0
4544 04:47:08.716127 DQM Delay:
4545 04:47:08.719224 DQM0 = 41, DQM1 = 34
4546 04:47:08.719795 DQ Delay:
4547 04:47:08.722726 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4548 04:47:08.726086 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4549 04:47:08.728819 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4550 04:47:08.731786 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4551 04:47:08.732350
4552 04:47:08.732769
4553 04:47:08.733255 ==
4554 04:47:08.735582 Dram Type= 6, Freq= 0, CH_1, rank 1
4555 04:47:08.742151 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4556 04:47:08.742716 ==
4557 04:47:08.743085
4558 04:47:08.743421
4559 04:47:08.743746 TX Vref Scan disable
4560 04:47:08.745293 == TX Byte 0 ==
4561 04:47:08.749150 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4562 04:47:08.756377 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4563 04:47:08.756996 == TX Byte 1 ==
4564 04:47:08.759748 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4565 04:47:08.766372 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4566 04:47:08.766943 ==
4567 04:47:08.768448 Dram Type= 6, Freq= 0, CH_1, rank 1
4568 04:47:08.772237 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4569 04:47:08.772999 ==
4570 04:47:08.773396
4571 04:47:08.773741
4572 04:47:08.775347 TX Vref Scan disable
4573 04:47:08.778375 == TX Byte 0 ==
4574 04:47:08.783225 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4575 04:47:08.785584 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4576 04:47:08.789287 == TX Byte 1 ==
4577 04:47:08.791675 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4578 04:47:08.794938 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4579 04:47:08.795406
4580 04:47:08.795773 [DATLAT]
4581 04:47:08.799096 Freq=600, CH1 RK1
4582 04:47:08.799667
4583 04:47:08.800038 DATLAT Default: 0x8
4584 04:47:08.802132 0, 0xFFFF, sum = 0
4585 04:47:08.805197 1, 0xFFFF, sum = 0
4586 04:47:08.805768 2, 0xFFFF, sum = 0
4587 04:47:08.808892 3, 0xFFFF, sum = 0
4588 04:47:08.809469 4, 0xFFFF, sum = 0
4589 04:47:08.811984 5, 0xFFFF, sum = 0
4590 04:47:08.812455 6, 0xFFFF, sum = 0
4591 04:47:08.814734 7, 0x0, sum = 1
4592 04:47:08.815204 8, 0x0, sum = 2
4593 04:47:08.815580 9, 0x0, sum = 3
4594 04:47:08.818224 10, 0x0, sum = 4
4595 04:47:08.818797 best_step = 8
4596 04:47:08.819172
4597 04:47:08.819515 ==
4598 04:47:08.821434 Dram Type= 6, Freq= 0, CH_1, rank 1
4599 04:47:08.828805 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4600 04:47:08.829425 ==
4601 04:47:08.829802 RX Vref Scan: 0
4602 04:47:08.830152
4603 04:47:08.831905 RX Vref 0 -> 0, step: 1
4604 04:47:08.832472
4605 04:47:08.835467 RX Delay -195 -> 252, step: 8
4606 04:47:08.841662 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4607 04:47:08.845068 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4608 04:47:08.848350 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4609 04:47:08.851572 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4610 04:47:08.854865 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4611 04:47:08.861956 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4612 04:47:08.865089 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4613 04:47:08.868165 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4614 04:47:08.871538 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4615 04:47:08.874773 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4616 04:47:08.881292 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4617 04:47:08.885309 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4618 04:47:08.887852 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4619 04:47:08.891267 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4620 04:47:08.898281 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4621 04:47:08.900947 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4622 04:47:08.901503 ==
4623 04:47:08.904534 Dram Type= 6, Freq= 0, CH_1, rank 1
4624 04:47:08.907861 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4625 04:47:08.908427 ==
4626 04:47:08.911669 DQS Delay:
4627 04:47:08.912237 DQS0 = 0, DQS1 = 0
4628 04:47:08.914989 DQM Delay:
4629 04:47:08.915555 DQM0 = 36, DQM1 = 29
4630 04:47:08.915932 DQ Delay:
4631 04:47:08.918672 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4632 04:47:08.921232 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4633 04:47:08.924527 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =20
4634 04:47:08.927590 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4635 04:47:08.928155
4636 04:47:08.928523
4637 04:47:08.938022 [DQSOSCAuto] RK1, (LSB)MR18= 0x5d5d, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
4638 04:47:08.940673 CH1 RK1: MR19=808, MR18=5D5D
4639 04:47:08.947176 CH1_RK1: MR19=0x808, MR18=0x5D5D, DQSOSC=392, MR23=63, INC=170, DEC=113
4640 04:47:08.947751 [RxdqsGatingPostProcess] freq 600
4641 04:47:08.953926 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4642 04:47:08.957490 Pre-setting of DQS Precalculation
4643 04:47:08.960426 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4644 04:47:08.970304 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4645 04:47:08.977544 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4646 04:47:08.978012
4647 04:47:08.978372
4648 04:47:08.979938 [Calibration Summary] 1200 Mbps
4649 04:47:08.980396 CH 0, Rank 0
4650 04:47:08.984123 SW Impedance : PASS
4651 04:47:08.987249 DUTY Scan : NO K
4652 04:47:08.987812 ZQ Calibration : PASS
4653 04:47:08.990338 Jitter Meter : NO K
4654 04:47:08.990817 CBT Training : PASS
4655 04:47:08.993804 Write leveling : PASS
4656 04:47:08.996923 RX DQS gating : PASS
4657 04:47:08.997500 RX DQ/DQS(RDDQC) : PASS
4658 04:47:09.001331 TX DQ/DQS : PASS
4659 04:47:09.003550 RX DATLAT : PASS
4660 04:47:09.004033 RX DQ/DQS(Engine): PASS
4661 04:47:09.007263 TX OE : NO K
4662 04:47:09.007848 All Pass.
4663 04:47:09.008342
4664 04:47:09.010246 CH 0, Rank 1
4665 04:47:09.010724 SW Impedance : PASS
4666 04:47:09.013166 DUTY Scan : NO K
4667 04:47:09.017365 ZQ Calibration : PASS
4668 04:47:09.017847 Jitter Meter : NO K
4669 04:47:09.020185 CBT Training : PASS
4670 04:47:09.023865 Write leveling : PASS
4671 04:47:09.024447 RX DQS gating : PASS
4672 04:47:09.026478 RX DQ/DQS(RDDQC) : PASS
4673 04:47:09.029534 TX DQ/DQS : PASS
4674 04:47:09.030094 RX DATLAT : PASS
4675 04:47:09.033089 RX DQ/DQS(Engine): PASS
4676 04:47:09.036368 TX OE : NO K
4677 04:47:09.036974 All Pass.
4678 04:47:09.037351
4679 04:47:09.037692 CH 1, Rank 0
4680 04:47:09.039667 SW Impedance : PASS
4681 04:47:09.043199 DUTY Scan : NO K
4682 04:47:09.043767 ZQ Calibration : PASS
4683 04:47:09.046057 Jitter Meter : NO K
4684 04:47:09.049229 CBT Training : PASS
4685 04:47:09.049690 Write leveling : PASS
4686 04:47:09.052823 RX DQS gating : PASS
4687 04:47:09.056270 RX DQ/DQS(RDDQC) : PASS
4688 04:47:09.056882 TX DQ/DQS : PASS
4689 04:47:09.059307 RX DATLAT : PASS
4690 04:47:09.062708 RX DQ/DQS(Engine): PASS
4691 04:47:09.063277 TX OE : NO K
4692 04:47:09.063652 All Pass.
4693 04:47:09.063998
4694 04:47:09.066291 CH 1, Rank 1
4695 04:47:09.066862 SW Impedance : PASS
4696 04:47:09.069200 DUTY Scan : NO K
4697 04:47:09.072535 ZQ Calibration : PASS
4698 04:47:09.073056 Jitter Meter : NO K
4699 04:47:09.075854 CBT Training : PASS
4700 04:47:09.079639 Write leveling : PASS
4701 04:47:09.080215 RX DQS gating : PASS
4702 04:47:09.082709 RX DQ/DQS(RDDQC) : PASS
4703 04:47:09.086054 TX DQ/DQS : PASS
4704 04:47:09.086523 RX DATLAT : PASS
4705 04:47:09.088825 RX DQ/DQS(Engine): PASS
4706 04:47:09.092279 TX OE : NO K
4707 04:47:09.092907 All Pass.
4708 04:47:09.093467
4709 04:47:09.096062 DramC Write-DBI off
4710 04:47:09.096528 PER_BANK_REFRESH: Hybrid Mode
4711 04:47:09.099197 TX_TRACKING: ON
4712 04:47:09.105930 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4713 04:47:09.112522 [FAST_K] Save calibration result to emmc
4714 04:47:09.115874 dramc_set_vcore_voltage set vcore to 662500
4715 04:47:09.116439 Read voltage for 933, 3
4716 04:47:09.119155 Vio18 = 0
4717 04:47:09.119719 Vcore = 662500
4718 04:47:09.120088 Vdram = 0
4719 04:47:09.122778 Vddq = 0
4720 04:47:09.123344 Vmddr = 0
4721 04:47:09.125927 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4722 04:47:09.132485 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4723 04:47:09.136141 MEM_TYPE=3, freq_sel=17
4724 04:47:09.139932 sv_algorithm_assistance_LP4_1600
4725 04:47:09.141959 ============ PULL DRAM RESETB DOWN ============
4726 04:47:09.145933 ========== PULL DRAM RESETB DOWN end =========
4727 04:47:09.151669 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4728 04:47:09.155456 ===================================
4729 04:47:09.156019 LPDDR4 DRAM CONFIGURATION
4730 04:47:09.159387 ===================================
4731 04:47:09.162149 EX_ROW_EN[0] = 0x0
4732 04:47:09.162706 EX_ROW_EN[1] = 0x0
4733 04:47:09.165225 LP4Y_EN = 0x0
4734 04:47:09.168801 WORK_FSP = 0x0
4735 04:47:09.169374 WL = 0x3
4736 04:47:09.172277 RL = 0x3
4737 04:47:09.172779 BL = 0x2
4738 04:47:09.175376 RPST = 0x0
4739 04:47:09.175834 RD_PRE = 0x0
4740 04:47:09.179075 WR_PRE = 0x1
4741 04:47:09.179655 WR_PST = 0x0
4742 04:47:09.181800 DBI_WR = 0x0
4743 04:47:09.182259 DBI_RD = 0x0
4744 04:47:09.185028 OTF = 0x1
4745 04:47:09.188264 ===================================
4746 04:47:09.191773 ===================================
4747 04:47:09.192234 ANA top config
4748 04:47:09.195837 ===================================
4749 04:47:09.199015 DLL_ASYNC_EN = 0
4750 04:47:09.201785 ALL_SLAVE_EN = 1
4751 04:47:09.202245 NEW_RANK_MODE = 1
4752 04:47:09.204424 DLL_IDLE_MODE = 1
4753 04:47:09.207828 LP45_APHY_COMB_EN = 1
4754 04:47:09.211311 TX_ODT_DIS = 1
4755 04:47:09.214615 NEW_8X_MODE = 1
4756 04:47:09.218238 ===================================
4757 04:47:09.222960 ===================================
4758 04:47:09.223525 data_rate = 1866
4759 04:47:09.224762 CKR = 1
4760 04:47:09.228312 DQ_P2S_RATIO = 8
4761 04:47:09.231061 ===================================
4762 04:47:09.235216 CA_P2S_RATIO = 8
4763 04:47:09.238962 DQ_CA_OPEN = 0
4764 04:47:09.241634 DQ_SEMI_OPEN = 0
4765 04:47:09.242197 CA_SEMI_OPEN = 0
4766 04:47:09.244512 CA_FULL_RATE = 0
4767 04:47:09.248122 DQ_CKDIV4_EN = 1
4768 04:47:09.251254 CA_CKDIV4_EN = 1
4769 04:47:09.255143 CA_PREDIV_EN = 0
4770 04:47:09.258075 PH8_DLY = 0
4771 04:47:09.258636 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4772 04:47:09.261161 DQ_AAMCK_DIV = 4
4773 04:47:09.264655 CA_AAMCK_DIV = 4
4774 04:47:09.268122 CA_ADMCK_DIV = 4
4775 04:47:09.270852 DQ_TRACK_CA_EN = 0
4776 04:47:09.273971 CA_PICK = 933
4777 04:47:09.277297 CA_MCKIO = 933
4778 04:47:09.277754 MCKIO_SEMI = 0
4779 04:47:09.281079 PLL_FREQ = 3732
4780 04:47:09.284640 DQ_UI_PI_RATIO = 32
4781 04:47:09.287453 CA_UI_PI_RATIO = 0
4782 04:47:09.290980 ===================================
4783 04:47:09.294600 ===================================
4784 04:47:09.297242 memory_type:LPDDR4
4785 04:47:09.297700 GP_NUM : 10
4786 04:47:09.301414 SRAM_EN : 1
4787 04:47:09.304951 MD32_EN : 0
4788 04:47:09.308127 ===================================
4789 04:47:09.308691 [ANA_INIT] >>>>>>>>>>>>>>
4790 04:47:09.311424 <<<<<< [CONFIGURE PHASE]: ANA_TX
4791 04:47:09.314289 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4792 04:47:09.317503 ===================================
4793 04:47:09.320948 data_rate = 1866,PCW = 0X8f00
4794 04:47:09.323886 ===================================
4795 04:47:09.327390 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4796 04:47:09.333584 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4797 04:47:09.337305 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4798 04:47:09.343332 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4799 04:47:09.347328 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4800 04:47:09.350402 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4801 04:47:09.353435 [ANA_INIT] flow start
4802 04:47:09.354000 [ANA_INIT] PLL >>>>>>>>
4803 04:47:09.357518 [ANA_INIT] PLL <<<<<<<<
4804 04:47:09.360296 [ANA_INIT] MIDPI >>>>>>>>
4805 04:47:09.360906 [ANA_INIT] MIDPI <<<<<<<<
4806 04:47:09.363670 [ANA_INIT] DLL >>>>>>>>
4807 04:47:09.366517 [ANA_INIT] flow end
4808 04:47:09.369684 ============ LP4 DIFF to SE enter ============
4809 04:47:09.372926 ============ LP4 DIFF to SE exit ============
4810 04:47:09.376890 [ANA_INIT] <<<<<<<<<<<<<
4811 04:47:09.380289 [Flow] Enable top DCM control >>>>>
4812 04:47:09.382883 [Flow] Enable top DCM control <<<<<
4813 04:47:09.386617 Enable DLL master slave shuffle
4814 04:47:09.390222 ==============================================================
4815 04:47:09.392883 Gating Mode config
4816 04:47:09.400806 ==============================================================
4817 04:47:09.401376 Config description:
4818 04:47:09.410067 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4819 04:47:09.416600 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4820 04:47:09.419861 SELPH_MODE 0: By rank 1: By Phase
4821 04:47:09.427039 ==============================================================
4822 04:47:09.429477 GAT_TRACK_EN = 1
4823 04:47:09.432912 RX_GATING_MODE = 2
4824 04:47:09.436039 RX_GATING_TRACK_MODE = 2
4825 04:47:09.440391 SELPH_MODE = 1
4826 04:47:09.443029 PICG_EARLY_EN = 1
4827 04:47:09.446140 VALID_LAT_VALUE = 1
4828 04:47:09.449409 ==============================================================
4829 04:47:09.452887 Enter into Gating configuration >>>>
4830 04:47:09.455772 Exit from Gating configuration <<<<
4831 04:47:09.459367 Enter into DVFS_PRE_config >>>>>
4832 04:47:09.472268 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4833 04:47:09.476024 Exit from DVFS_PRE_config <<<<<
4834 04:47:09.476778 Enter into PICG configuration >>>>
4835 04:47:09.479135 Exit from PICG configuration <<<<
4836 04:47:09.482406 [RX_INPUT] configuration >>>>>
4837 04:47:09.485499 [RX_INPUT] configuration <<<<<
4838 04:47:09.492365 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4839 04:47:09.495471 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4840 04:47:09.502443 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4841 04:47:09.509167 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4842 04:47:09.515620 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4843 04:47:09.522581 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4844 04:47:09.525639 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4845 04:47:09.528887 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4846 04:47:09.532607 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4847 04:47:09.539089 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4848 04:47:09.541821 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4849 04:47:09.545047 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4850 04:47:09.549027 ===================================
4851 04:47:09.551681 LPDDR4 DRAM CONFIGURATION
4852 04:47:09.555628 ===================================
4853 04:47:09.558836 EX_ROW_EN[0] = 0x0
4854 04:47:09.559295 EX_ROW_EN[1] = 0x0
4855 04:47:09.562046 LP4Y_EN = 0x0
4856 04:47:09.562604 WORK_FSP = 0x0
4857 04:47:09.565374 WL = 0x3
4858 04:47:09.565943 RL = 0x3
4859 04:47:09.568850 BL = 0x2
4860 04:47:09.569415 RPST = 0x0
4861 04:47:09.571942 RD_PRE = 0x0
4862 04:47:09.572400 WR_PRE = 0x1
4863 04:47:09.575601 WR_PST = 0x0
4864 04:47:09.576272 DBI_WR = 0x0
4865 04:47:09.578463 DBI_RD = 0x0
4866 04:47:09.579009 OTF = 0x1
4867 04:47:09.581727 ===================================
4868 04:47:09.588018 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4869 04:47:09.592153 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4870 04:47:09.595247 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4871 04:47:09.598292 ===================================
4872 04:47:09.601814 LPDDR4 DRAM CONFIGURATION
4873 04:47:09.604612 ===================================
4874 04:47:09.608105 EX_ROW_EN[0] = 0x10
4875 04:47:09.608666 EX_ROW_EN[1] = 0x0
4876 04:47:09.611596 LP4Y_EN = 0x0
4877 04:47:09.612185 WORK_FSP = 0x0
4878 04:47:09.614683 WL = 0x3
4879 04:47:09.615235 RL = 0x3
4880 04:47:09.618022 BL = 0x2
4881 04:47:09.618772 RPST = 0x0
4882 04:47:09.621056 RD_PRE = 0x0
4883 04:47:09.621509 WR_PRE = 0x1
4884 04:47:09.624643 WR_PST = 0x0
4885 04:47:09.625138 DBI_WR = 0x0
4886 04:47:09.628363 DBI_RD = 0x0
4887 04:47:09.628960 OTF = 0x1
4888 04:47:09.631490 ===================================
4889 04:47:09.637954 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4890 04:47:09.642980 nWR fixed to 30
4891 04:47:09.646143 [ModeRegInit_LP4] CH0 RK0
4892 04:47:09.646696 [ModeRegInit_LP4] CH0 RK1
4893 04:47:09.650999 [ModeRegInit_LP4] CH1 RK0
4894 04:47:09.652767 [ModeRegInit_LP4] CH1 RK1
4895 04:47:09.653230 match AC timing 8
4896 04:47:09.659331 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4897 04:47:09.663386 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4898 04:47:09.666384 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4899 04:47:09.672459 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4900 04:47:09.677225 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4901 04:47:09.677775 ==
4902 04:47:09.678847 Dram Type= 6, Freq= 0, CH_0, rank 0
4903 04:47:09.682501 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4904 04:47:09.683058 ==
4905 04:47:09.688772 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4906 04:47:09.695647 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4907 04:47:09.698727 [CA 0] Center 38 (8~69) winsize 62
4908 04:47:09.702594 [CA 1] Center 38 (7~69) winsize 63
4909 04:47:09.705479 [CA 2] Center 36 (5~67) winsize 63
4910 04:47:09.709185 [CA 3] Center 35 (5~66) winsize 62
4911 04:47:09.712749 [CA 4] Center 34 (4~65) winsize 62
4912 04:47:09.716236 [CA 5] Center 34 (4~65) winsize 62
4913 04:47:09.716855
4914 04:47:09.718799 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4915 04:47:09.719257
4916 04:47:09.722339 [CATrainingPosCal] consider 1 rank data
4917 04:47:09.725910 u2DelayCellTimex100 = 270/100 ps
4918 04:47:09.729475 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4919 04:47:09.732095 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
4920 04:47:09.735260 CA2 delay=36 (5~67),Diff = 2 PI (12 cell)
4921 04:47:09.738477 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4922 04:47:09.741745 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4923 04:47:09.748289 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4924 04:47:09.749000
4925 04:47:09.751814 CA PerBit enable=1, Macro0, CA PI delay=34
4926 04:47:09.752365
4927 04:47:09.755443 [CBTSetCACLKResult] CA Dly = 34
4928 04:47:09.756003 CS Dly: 7 (0~38)
4929 04:47:09.756376 ==
4930 04:47:09.758401 Dram Type= 6, Freq= 0, CH_0, rank 1
4931 04:47:09.762770 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4932 04:47:09.764893 ==
4933 04:47:09.768404 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4934 04:47:09.775214 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4935 04:47:09.778617 [CA 0] Center 38 (8~69) winsize 62
4936 04:47:09.781944 [CA 1] Center 38 (7~69) winsize 63
4937 04:47:09.784874 [CA 2] Center 36 (5~67) winsize 63
4938 04:47:09.788583 [CA 3] Center 35 (5~66) winsize 62
4939 04:47:09.791891 [CA 4] Center 34 (4~65) winsize 62
4940 04:47:09.794727 [CA 5] Center 34 (4~65) winsize 62
4941 04:47:09.795323
4942 04:47:09.797619 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4943 04:47:09.798078
4944 04:47:09.801625 [CATrainingPosCal] consider 2 rank data
4945 04:47:09.804559 u2DelayCellTimex100 = 270/100 ps
4946 04:47:09.808376 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4947 04:47:09.812069 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
4948 04:47:09.817669 CA2 delay=36 (5~67),Diff = 2 PI (12 cell)
4949 04:47:09.821961 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4950 04:47:09.824843 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4951 04:47:09.828114 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4952 04:47:09.828671
4953 04:47:09.831611 CA PerBit enable=1, Macro0, CA PI delay=34
4954 04:47:09.832167
4955 04:47:09.835249 [CBTSetCACLKResult] CA Dly = 34
4956 04:47:09.835800 CS Dly: 7 (0~39)
4957 04:47:09.836166
4958 04:47:09.838778 ----->DramcWriteLeveling(PI) begin...
4959 04:47:09.841088 ==
4960 04:47:09.844461 Dram Type= 6, Freq= 0, CH_0, rank 0
4961 04:47:09.848179 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4962 04:47:09.848785 ==
4963 04:47:09.850973 Write leveling (Byte 0): 29 => 29
4964 04:47:09.854349 Write leveling (Byte 1): 29 => 29
4965 04:47:09.857658 DramcWriteLeveling(PI) end<-----
4966 04:47:09.858210
4967 04:47:09.858574 ==
4968 04:47:09.860558 Dram Type= 6, Freq= 0, CH_0, rank 0
4969 04:47:09.864135 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4970 04:47:09.864695 ==
4971 04:47:09.867812 [Gating] SW mode calibration
4972 04:47:09.874019 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4973 04:47:09.880441 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4974 04:47:09.884417 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4975 04:47:09.887250 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4976 04:47:09.891698 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4977 04:47:09.897725 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4978 04:47:09.901027 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4979 04:47:09.904012 0 10 20 | B1->B0 | 3434 3131 | 1 0 | (1 0) (1 0)
4980 04:47:09.910751 0 10 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (1 0)
4981 04:47:09.914690 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4982 04:47:09.917496 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4983 04:47:09.924394 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4984 04:47:09.927856 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4985 04:47:09.931417 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4986 04:47:09.938153 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4987 04:47:09.940440 0 11 20 | B1->B0 | 2323 3232 | 0 0 | (0 0) (1 1)
4988 04:47:09.944295 0 11 24 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
4989 04:47:09.950655 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4990 04:47:09.953967 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4991 04:47:09.957173 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4992 04:47:09.963658 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4993 04:47:09.967053 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4994 04:47:09.970417 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4995 04:47:09.977021 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4996 04:47:09.979995 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4997 04:47:09.983346 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4998 04:47:09.989650 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4999 04:47:09.993486 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5000 04:47:09.996795 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5001 04:47:10.003902 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5002 04:47:10.007234 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5003 04:47:10.009970 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5004 04:47:10.016812 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5005 04:47:10.019713 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5006 04:47:10.023198 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5007 04:47:10.029677 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5008 04:47:10.032957 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5009 04:47:10.036199 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5010 04:47:10.043017 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5011 04:47:10.046241 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5012 04:47:10.049312 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5013 04:47:10.055860 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5014 04:47:10.059936 Total UI for P1: 0, mck2ui 16
5015 04:47:10.062534 best dqsien dly found for B0: ( 0, 14, 22)
5016 04:47:10.063102 Total UI for P1: 0, mck2ui 16
5017 04:47:10.069183 best dqsien dly found for B1: ( 0, 14, 20)
5018 04:47:10.072241 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5019 04:47:10.076216 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5020 04:47:10.076848
5021 04:47:10.079094 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5022 04:47:10.082897 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5023 04:47:10.085456 [Gating] SW calibration Done
5024 04:47:10.085924 ==
5025 04:47:10.089110 Dram Type= 6, Freq= 0, CH_0, rank 0
5026 04:47:10.092624 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5027 04:47:10.093287 ==
5028 04:47:10.095945 RX Vref Scan: 0
5029 04:47:10.096510
5030 04:47:10.099344 RX Vref 0 -> 0, step: 1
5031 04:47:10.099807
5032 04:47:10.100171 RX Delay -80 -> 252, step: 8
5033 04:47:10.105953 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5034 04:47:10.108777 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5035 04:47:10.112095 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5036 04:47:10.115389 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5037 04:47:10.119019 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5038 04:47:10.121747 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5039 04:47:10.128686 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5040 04:47:10.132066 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5041 04:47:10.135972 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5042 04:47:10.138447 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5043 04:47:10.142071 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5044 04:47:10.148363 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5045 04:47:10.151881 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5046 04:47:10.155235 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5047 04:47:10.158433 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5048 04:47:10.162268 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5049 04:47:10.164741 ==
5050 04:47:10.165380 Dram Type= 6, Freq= 0, CH_0, rank 0
5051 04:47:10.171878 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5052 04:47:10.172434 ==
5053 04:47:10.172837 DQS Delay:
5054 04:47:10.175113 DQS0 = 0, DQS1 = 0
5055 04:47:10.175575 DQM Delay:
5056 04:47:10.177865 DQM0 = 95, DQM1 = 83
5057 04:47:10.178328 DQ Delay:
5058 04:47:10.181443 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5059 04:47:10.185313 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5060 04:47:10.188823 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5061 04:47:10.191532 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5062 04:47:10.192097
5063 04:47:10.192466
5064 04:47:10.192887 ==
5065 04:47:10.195075 Dram Type= 6, Freq= 0, CH_0, rank 0
5066 04:47:10.197918 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5067 04:47:10.198510 ==
5068 04:47:10.198886
5069 04:47:10.199229
5070 04:47:10.201229 TX Vref Scan disable
5071 04:47:10.204525 == TX Byte 0 ==
5072 04:47:10.208157 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5073 04:47:10.212213 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5074 04:47:10.214754 == TX Byte 1 ==
5075 04:47:10.218450 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5076 04:47:10.222432 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5077 04:47:10.222997 ==
5078 04:47:10.224375 Dram Type= 6, Freq= 0, CH_0, rank 0
5079 04:47:10.231283 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5080 04:47:10.232050 ==
5081 04:47:10.232449
5082 04:47:10.232840
5083 04:47:10.233180 TX Vref Scan disable
5084 04:47:10.234854 == TX Byte 0 ==
5085 04:47:10.238835 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5086 04:47:10.245673 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5087 04:47:10.246240 == TX Byte 1 ==
5088 04:47:10.248597 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5089 04:47:10.255399 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5090 04:47:10.255966
5091 04:47:10.256332 [DATLAT]
5092 04:47:10.256671 Freq=933, CH0 RK0
5093 04:47:10.257050
5094 04:47:10.257872 DATLAT Default: 0xd
5095 04:47:10.258326 0, 0xFFFF, sum = 0
5096 04:47:10.262444 1, 0xFFFF, sum = 0
5097 04:47:10.263003 2, 0xFFFF, sum = 0
5098 04:47:10.265191 3, 0xFFFF, sum = 0
5099 04:47:10.268067 4, 0xFFFF, sum = 0
5100 04:47:10.268626 5, 0xFFFF, sum = 0
5101 04:47:10.271202 6, 0xFFFF, sum = 0
5102 04:47:10.271665 7, 0xFFFF, sum = 0
5103 04:47:10.274539 8, 0xFFFF, sum = 0
5104 04:47:10.275006 9, 0xFFFF, sum = 0
5105 04:47:10.277998 10, 0x0, sum = 1
5106 04:47:10.278462 11, 0x0, sum = 2
5107 04:47:10.281368 12, 0x0, sum = 3
5108 04:47:10.281832 13, 0x0, sum = 4
5109 04:47:10.282204 best_step = 11
5110 04:47:10.282540
5111 04:47:10.284730 ==
5112 04:47:10.288189 Dram Type= 6, Freq= 0, CH_0, rank 0
5113 04:47:10.291535 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5114 04:47:10.292088 ==
5115 04:47:10.292457 RX Vref Scan: 1
5116 04:47:10.292896
5117 04:47:10.294486 RX Vref 0 -> 0, step: 1
5118 04:47:10.294944
5119 04:47:10.298481 RX Delay -69 -> 252, step: 4
5120 04:47:10.299035
5121 04:47:10.301383 Set Vref, RX VrefLevel [Byte0]: 45
5122 04:47:10.305135 [Byte1]: 52
5123 04:47:10.305688
5124 04:47:10.308168 Final RX Vref Byte 0 = 45 to rank0
5125 04:47:10.311771 Final RX Vref Byte 1 = 52 to rank0
5126 04:47:10.314961 Final RX Vref Byte 0 = 45 to rank1
5127 04:47:10.317695 Final RX Vref Byte 1 = 52 to rank1==
5128 04:47:10.321327 Dram Type= 6, Freq= 0, CH_0, rank 0
5129 04:47:10.325111 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5130 04:47:10.327690 ==
5131 04:47:10.328249 DQS Delay:
5132 04:47:10.328619 DQS0 = 0, DQS1 = 0
5133 04:47:10.331072 DQM Delay:
5134 04:47:10.331621 DQM0 = 96, DQM1 = 87
5135 04:47:10.335031 DQ Delay:
5136 04:47:10.338420 DQ0 =92, DQ1 =98, DQ2 =94, DQ3 =92
5137 04:47:10.340855 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =104
5138 04:47:10.344242 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =78
5139 04:47:10.348335 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =96
5140 04:47:10.348985
5141 04:47:10.349366
5142 04:47:10.355284 [DQSOSCAuto] RK0, (LSB)MR18= 0x2525, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5143 04:47:10.357243 CH0 RK0: MR19=505, MR18=2525
5144 04:47:10.364440 CH0_RK0: MR19=0x505, MR18=0x2525, DQSOSC=410, MR23=63, INC=64, DEC=42
5145 04:47:10.365045
5146 04:47:10.368967 ----->DramcWriteLeveling(PI) begin...
5147 04:47:10.369521 ==
5148 04:47:10.370589 Dram Type= 6, Freq= 0, CH_0, rank 1
5149 04:47:10.373909 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5150 04:47:10.374371 ==
5151 04:47:10.378973 Write leveling (Byte 0): 32 => 32
5152 04:47:10.380899 Write leveling (Byte 1): 24 => 24
5153 04:47:10.384462 DramcWriteLeveling(PI) end<-----
5154 04:47:10.385081
5155 04:47:10.385455 ==
5156 04:47:10.387798 Dram Type= 6, Freq= 0, CH_0, rank 1
5157 04:47:10.390581 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5158 04:47:10.391046 ==
5159 04:47:10.393788 [Gating] SW mode calibration
5160 04:47:10.400967 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5161 04:47:10.407128 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5162 04:47:10.410766 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 04:47:10.417514 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 04:47:10.421440 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5165 04:47:10.425151 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5166 04:47:10.430498 0 10 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5167 04:47:10.433636 0 10 20 | B1->B0 | 3333 2d2d | 1 0 | (1 0) (0 0)
5168 04:47:10.437430 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 04:47:10.444538 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 04:47:10.446788 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 04:47:10.450269 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 04:47:10.457122 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5173 04:47:10.460097 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 04:47:10.463652 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 04:47:10.470402 0 11 20 | B1->B0 | 2b2a 3535 | 1 0 | (0 0) (0 0)
5176 04:47:10.472824 0 11 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5177 04:47:10.476801 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 04:47:10.482792 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 04:47:10.486327 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 04:47:10.489993 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 04:47:10.496350 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 04:47:10.499891 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 04:47:10.503888 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5184 04:47:10.509796 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5185 04:47:10.513382 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 04:47:10.515895 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 04:47:10.522632 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 04:47:10.526695 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 04:47:10.529571 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 04:47:10.536281 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 04:47:10.539107 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 04:47:10.542592 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 04:47:10.546175 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 04:47:10.552385 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 04:47:10.556672 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 04:47:10.560111 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 04:47:10.565599 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 04:47:10.569436 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5199 04:47:10.572470 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5200 04:47:10.579818 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 04:47:10.582287 Total UI for P1: 0, mck2ui 16
5202 04:47:10.585661 best dqsien dly found for B0: ( 0, 14, 20)
5203 04:47:10.590041 Total UI for P1: 0, mck2ui 16
5204 04:47:10.592762 best dqsien dly found for B1: ( 0, 14, 18)
5205 04:47:10.595540 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5206 04:47:10.598988 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5207 04:47:10.599452
5208 04:47:10.602529 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5209 04:47:10.605707 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5210 04:47:10.608439 [Gating] SW calibration Done
5211 04:47:10.609054 ==
5212 04:47:10.611964 Dram Type= 6, Freq= 0, CH_0, rank 1
5213 04:47:10.615476 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5214 04:47:10.615897 ==
5215 04:47:10.619328 RX Vref Scan: 0
5216 04:47:10.619848
5217 04:47:10.622701 RX Vref 0 -> 0, step: 1
5218 04:47:10.623221
5219 04:47:10.623564 RX Delay -80 -> 252, step: 8
5220 04:47:10.628569 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5221 04:47:10.631706 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5222 04:47:10.635380 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5223 04:47:10.638494 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5224 04:47:10.642020 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5225 04:47:10.645272 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5226 04:47:10.651879 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5227 04:47:10.654722 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5228 04:47:10.658364 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5229 04:47:10.662272 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5230 04:47:10.665560 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5231 04:47:10.671667 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5232 04:47:10.674807 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5233 04:47:10.678469 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5234 04:47:10.681319 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5235 04:47:10.684636 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5236 04:47:10.685120 ==
5237 04:47:10.689600 Dram Type= 6, Freq= 0, CH_0, rank 1
5238 04:47:10.694613 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5239 04:47:10.695039 ==
5240 04:47:10.695377 DQS Delay:
5241 04:47:10.698159 DQS0 = 0, DQS1 = 0
5242 04:47:10.698675 DQM Delay:
5243 04:47:10.699016 DQM0 = 96, DQM1 = 86
5244 04:47:10.701099 DQ Delay:
5245 04:47:10.705650 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =91
5246 04:47:10.708081 DQ4 =99, DQ5 =87, DQ6 =99, DQ7 =107
5247 04:47:10.711480 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =75
5248 04:47:10.714708 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5249 04:47:10.715226
5250 04:47:10.715614
5251 04:47:10.715941 ==
5252 04:47:10.718734 Dram Type= 6, Freq= 0, CH_0, rank 1
5253 04:47:10.721057 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5254 04:47:10.721573 ==
5255 04:47:10.721912
5256 04:47:10.722242
5257 04:47:10.724990 TX Vref Scan disable
5258 04:47:10.728000 == TX Byte 0 ==
5259 04:47:10.731077 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5260 04:47:10.735492 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5261 04:47:10.738969 == TX Byte 1 ==
5262 04:47:10.740821 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5263 04:47:10.744401 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5264 04:47:10.745078 ==
5265 04:47:10.747679 Dram Type= 6, Freq= 0, CH_0, rank 1
5266 04:47:10.750236 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5267 04:47:10.754239 ==
5268 04:47:10.754676
5269 04:47:10.755001
5270 04:47:10.755343 TX Vref Scan disable
5271 04:47:10.757482 == TX Byte 0 ==
5272 04:47:10.760985 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5273 04:47:10.767291 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5274 04:47:10.767534 == TX Byte 1 ==
5275 04:47:10.770500 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5276 04:47:10.777055 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5277 04:47:10.777233
5278 04:47:10.777367 [DATLAT]
5279 04:47:10.777492 Freq=933, CH0 RK1
5280 04:47:10.777617
5281 04:47:10.780262 DATLAT Default: 0xb
5282 04:47:10.784076 0, 0xFFFF, sum = 0
5283 04:47:10.784256 1, 0xFFFF, sum = 0
5284 04:47:10.786912 2, 0xFFFF, sum = 0
5285 04:47:10.787034 3, 0xFFFF, sum = 0
5286 04:47:10.790735 4, 0xFFFF, sum = 0
5287 04:47:10.790852 5, 0xFFFF, sum = 0
5288 04:47:10.794421 6, 0xFFFF, sum = 0
5289 04:47:10.794541 7, 0xFFFF, sum = 0
5290 04:47:10.796907 8, 0xFFFF, sum = 0
5291 04:47:10.797024 9, 0xFFFF, sum = 0
5292 04:47:10.800405 10, 0x0, sum = 1
5293 04:47:10.800549 11, 0x0, sum = 2
5294 04:47:10.804360 12, 0x0, sum = 3
5295 04:47:10.804484 13, 0x0, sum = 4
5296 04:47:10.804593 best_step = 11
5297 04:47:10.804693
5298 04:47:10.807576 ==
5299 04:47:10.810461 Dram Type= 6, Freq= 0, CH_0, rank 1
5300 04:47:10.813912 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5301 04:47:10.814077 ==
5302 04:47:10.814164 RX Vref Scan: 0
5303 04:47:10.814242
5304 04:47:10.817145 RX Vref 0 -> 0, step: 1
5305 04:47:10.817313
5306 04:47:10.822071 RX Delay -69 -> 252, step: 4
5307 04:47:10.823725 iDelay=199, Bit 0, Center 92 (3 ~ 182) 180
5308 04:47:10.830270 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5309 04:47:10.833747 iDelay=199, Bit 2, Center 94 (3 ~ 186) 184
5310 04:47:10.836675 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5311 04:47:10.840155 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5312 04:47:10.843762 iDelay=199, Bit 5, Center 92 (-1 ~ 186) 188
5313 04:47:10.846818 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5314 04:47:10.854054 iDelay=199, Bit 7, Center 108 (19 ~ 198) 180
5315 04:47:10.857251 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5316 04:47:10.860401 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5317 04:47:10.863947 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5318 04:47:10.867228 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5319 04:47:10.873446 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5320 04:47:10.877022 iDelay=199, Bit 13, Center 94 (3 ~ 186) 184
5321 04:47:10.880271 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5322 04:47:10.883567 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5323 04:47:10.884033 ==
5324 04:47:10.886952 Dram Type= 6, Freq= 0, CH_0, rank 1
5325 04:47:10.890623 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5326 04:47:10.893582 ==
5327 04:47:10.894059 DQS Delay:
5328 04:47:10.894547 DQS0 = 0, DQS1 = 0
5329 04:47:10.896672 DQM Delay:
5330 04:47:10.897204 DQM0 = 97, DQM1 = 86
5331 04:47:10.900181 DQ Delay:
5332 04:47:10.903409 DQ0 =92, DQ1 =98, DQ2 =94, DQ3 =92
5333 04:47:10.906929 DQ4 =102, DQ5 =92, DQ6 =104, DQ7 =108
5334 04:47:10.909995 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5335 04:47:10.913486 DQ12 =92, DQ13 =94, DQ14 =98, DQ15 =94
5336 04:47:10.914067
5337 04:47:10.914562
5338 04:47:10.919871 [DQSOSCAuto] RK1, (LSB)MR18= 0x2929, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5339 04:47:10.923260 CH0 RK1: MR19=505, MR18=2929
5340 04:47:10.930707 CH0_RK1: MR19=0x505, MR18=0x2929, DQSOSC=408, MR23=63, INC=65, DEC=43
5341 04:47:10.933239 [RxdqsGatingPostProcess] freq 933
5342 04:47:10.937035 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5343 04:47:10.940623 Pre-setting of DQS Precalculation
5344 04:47:10.946988 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5345 04:47:10.947575 ==
5346 04:47:10.950131 Dram Type= 6, Freq= 0, CH_1, rank 0
5347 04:47:10.952809 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5348 04:47:10.953291 ==
5349 04:47:10.960481 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5350 04:47:10.966830 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5351 04:47:10.969781 [CA 0] Center 37 (7~68) winsize 62
5352 04:47:10.973169 [CA 1] Center 37 (6~68) winsize 63
5353 04:47:10.976255 [CA 2] Center 34 (4~65) winsize 62
5354 04:47:10.979868 [CA 3] Center 34 (4~65) winsize 62
5355 04:47:10.983441 [CA 4] Center 33 (2~64) winsize 63
5356 04:47:10.984057 [CA 5] Center 33 (3~64) winsize 62
5357 04:47:10.986077
5358 04:47:10.989905 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5359 04:47:10.990386
5360 04:47:10.994188 [CATrainingPosCal] consider 1 rank data
5361 04:47:10.997483 u2DelayCellTimex100 = 270/100 ps
5362 04:47:10.999547 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5363 04:47:11.003303 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5364 04:47:11.006420 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5365 04:47:11.009195 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5366 04:47:11.012488 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5367 04:47:11.015363 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5368 04:47:11.015697
5369 04:47:11.019192 CA PerBit enable=1, Macro0, CA PI delay=33
5370 04:47:11.022495
5371 04:47:11.022759 [CBTSetCACLKResult] CA Dly = 33
5372 04:47:11.025840 CS Dly: 5 (0~36)
5373 04:47:11.026108 ==
5374 04:47:11.029257 Dram Type= 6, Freq= 0, CH_1, rank 1
5375 04:47:11.032003 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5376 04:47:11.032241 ==
5377 04:47:11.039311 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5378 04:47:11.046533 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5379 04:47:11.049213 [CA 0] Center 37 (6~68) winsize 63
5380 04:47:11.052898 [CA 1] Center 37 (6~68) winsize 63
5381 04:47:11.055766 [CA 2] Center 34 (4~65) winsize 62
5382 04:47:11.059369 [CA 3] Center 34 (4~64) winsize 61
5383 04:47:11.062296 [CA 4] Center 33 (2~64) winsize 63
5384 04:47:11.065670 [CA 5] Center 33 (2~64) winsize 63
5385 04:47:11.066188
5386 04:47:11.068864 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5387 04:47:11.069385
5388 04:47:11.072286 [CATrainingPosCal] consider 2 rank data
5389 04:47:11.075709 u2DelayCellTimex100 = 270/100 ps
5390 04:47:11.080048 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5391 04:47:11.083059 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5392 04:47:11.086143 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5393 04:47:11.088943 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5394 04:47:11.092245 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5395 04:47:11.095887 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5396 04:47:11.096439
5397 04:47:11.102108 CA PerBit enable=1, Macro0, CA PI delay=33
5398 04:47:11.102657
5399 04:47:11.103016 [CBTSetCACLKResult] CA Dly = 33
5400 04:47:11.105284 CS Dly: 5 (0~37)
5401 04:47:11.105729
5402 04:47:11.109122 ----->DramcWriteLeveling(PI) begin...
5403 04:47:11.109578 ==
5404 04:47:11.112327 Dram Type= 6, Freq= 0, CH_1, rank 0
5405 04:47:11.116078 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5406 04:47:11.116640 ==
5407 04:47:11.118929 Write leveling (Byte 0): 24 => 24
5408 04:47:11.121871 Write leveling (Byte 1): 25 => 25
5409 04:47:11.125109 DramcWriteLeveling(PI) end<-----
5410 04:47:11.125613
5411 04:47:11.125975 ==
5412 04:47:11.128614 Dram Type= 6, Freq= 0, CH_1, rank 0
5413 04:47:11.135455 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5414 04:47:11.136009 ==
5415 04:47:11.136369 [Gating] SW mode calibration
5416 04:47:11.145124 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5417 04:47:11.148217 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5418 04:47:11.152440 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5419 04:47:11.158292 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5420 04:47:11.163432 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5421 04:47:11.165282 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5422 04:47:11.171376 0 10 16 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
5423 04:47:11.175267 0 10 20 | B1->B0 | 3333 2626 | 1 0 | (1 0) (0 0)
5424 04:47:11.180111 0 10 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5425 04:47:11.185577 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5426 04:47:11.188059 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5427 04:47:11.191838 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5428 04:47:11.198816 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5429 04:47:11.201676 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5430 04:47:11.204777 0 11 16 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
5431 04:47:11.211483 0 11 20 | B1->B0 | 2b2b 4545 | 0 0 | (0 0) (0 0)
5432 04:47:11.214589 0 11 24 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
5433 04:47:11.217532 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5434 04:47:11.224891 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5435 04:47:11.227863 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5436 04:47:11.231194 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5437 04:47:11.238365 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5438 04:47:11.240894 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5439 04:47:11.244360 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5440 04:47:11.250986 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 04:47:11.254320 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 04:47:11.257761 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 04:47:11.264491 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 04:47:11.268212 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5445 04:47:11.270851 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5446 04:47:11.277194 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 04:47:11.280700 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 04:47:11.283876 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 04:47:11.290823 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5450 04:47:11.293597 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5451 04:47:11.297361 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5452 04:47:11.304026 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5453 04:47:11.306928 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5454 04:47:11.310530 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5455 04:47:11.316938 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5456 04:47:11.320058 Total UI for P1: 0, mck2ui 16
5457 04:47:11.323251 best dqsien dly found for B0: ( 0, 14, 16)
5458 04:47:11.327428 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5459 04:47:11.330682 Total UI for P1: 0, mck2ui 16
5460 04:47:11.333527 best dqsien dly found for B1: ( 0, 14, 18)
5461 04:47:11.336563 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5462 04:47:11.340892 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5463 04:47:11.341455
5464 04:47:11.343365 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5465 04:47:11.346667 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5466 04:47:11.349929 [Gating] SW calibration Done
5467 04:47:11.350390 ==
5468 04:47:11.354154 Dram Type= 6, Freq= 0, CH_1, rank 0
5469 04:47:11.359775 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5470 04:47:11.360338 ==
5471 04:47:11.360738 RX Vref Scan: 0
5472 04:47:11.361158
5473 04:47:11.363713 RX Vref 0 -> 0, step: 1
5474 04:47:11.364279
5475 04:47:11.366363 RX Delay -80 -> 252, step: 8
5476 04:47:11.369808 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5477 04:47:11.373367 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5478 04:47:11.376234 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5479 04:47:11.380089 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5480 04:47:11.386305 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5481 04:47:11.389373 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5482 04:47:11.393232 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5483 04:47:11.395993 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5484 04:47:11.399919 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5485 04:47:11.405881 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5486 04:47:11.409445 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5487 04:47:11.412689 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5488 04:47:11.415965 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5489 04:47:11.420887 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5490 04:47:11.426567 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5491 04:47:11.429641 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5492 04:47:11.430208 ==
5493 04:47:11.432354 Dram Type= 6, Freq= 0, CH_1, rank 0
5494 04:47:11.435413 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5495 04:47:11.435880 ==
5496 04:47:11.439539 DQS Delay:
5497 04:47:11.440112 DQS0 = 0, DQS1 = 0
5498 04:47:11.440487 DQM Delay:
5499 04:47:11.442448 DQM0 = 96, DQM1 = 89
5500 04:47:11.443013 DQ Delay:
5501 04:47:11.445702 DQ0 =103, DQ1 =91, DQ2 =83, DQ3 =91
5502 04:47:11.450120 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =95
5503 04:47:11.452100 DQ8 =71, DQ9 =79, DQ10 =87, DQ11 =79
5504 04:47:11.455933 DQ12 =99, DQ13 =103, DQ14 =91, DQ15 =103
5505 04:47:11.456503
5506 04:47:11.456937
5507 04:47:11.457287 ==
5508 04:47:11.458813 Dram Type= 6, Freq= 0, CH_1, rank 0
5509 04:47:11.465632 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5510 04:47:11.466197 ==
5511 04:47:11.466566
5512 04:47:11.466905
5513 04:47:11.469008 TX Vref Scan disable
5514 04:47:11.469575 == TX Byte 0 ==
5515 04:47:11.472514 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5516 04:47:11.479062 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5517 04:47:11.479632 == TX Byte 1 ==
5518 04:47:11.482319 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5519 04:47:11.488549 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5520 04:47:11.489142 ==
5521 04:47:11.492138 Dram Type= 6, Freq= 0, CH_1, rank 0
5522 04:47:11.495519 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5523 04:47:11.496088 ==
5524 04:47:11.496462
5525 04:47:11.496864
5526 04:47:11.499484 TX Vref Scan disable
5527 04:47:11.501927 == TX Byte 0 ==
5528 04:47:11.505518 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5529 04:47:11.508241 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5530 04:47:11.512274 == TX Byte 1 ==
5531 04:47:11.514937 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5532 04:47:11.519045 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5533 04:47:11.519616
5534 04:47:11.519986 [DATLAT]
5535 04:47:11.521538 Freq=933, CH1 RK0
5536 04:47:11.522001
5537 04:47:11.525482 DATLAT Default: 0xd
5538 04:47:11.526045 0, 0xFFFF, sum = 0
5539 04:47:11.528767 1, 0xFFFF, sum = 0
5540 04:47:11.529347 2, 0xFFFF, sum = 0
5541 04:47:11.531928 3, 0xFFFF, sum = 0
5542 04:47:11.532398 4, 0xFFFF, sum = 0
5543 04:47:11.534934 5, 0xFFFF, sum = 0
5544 04:47:11.535406 6, 0xFFFF, sum = 0
5545 04:47:11.538595 7, 0xFFFF, sum = 0
5546 04:47:11.539171 8, 0xFFFF, sum = 0
5547 04:47:11.541364 9, 0xFFFF, sum = 0
5548 04:47:11.541960 10, 0x0, sum = 1
5549 04:47:11.544893 11, 0x0, sum = 2
5550 04:47:11.545459 12, 0x0, sum = 3
5551 04:47:11.548466 13, 0x0, sum = 4
5552 04:47:11.549106 best_step = 11
5553 04:47:11.549756
5554 04:47:11.550256 ==
5555 04:47:11.552582 Dram Type= 6, Freq= 0, CH_1, rank 0
5556 04:47:11.555071 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5557 04:47:11.558635 ==
5558 04:47:11.559200 RX Vref Scan: 1
5559 04:47:11.559572
5560 04:47:11.561129 RX Vref 0 -> 0, step: 1
5561 04:47:11.561591
5562 04:47:11.564963 RX Delay -69 -> 252, step: 4
5563 04:47:11.565427
5564 04:47:11.568043 Set Vref, RX VrefLevel [Byte0]: 57
5565 04:47:11.571506 [Byte1]: 50
5566 04:47:11.572076
5567 04:47:11.574233 Final RX Vref Byte 0 = 57 to rank0
5568 04:47:11.577817 Final RX Vref Byte 1 = 50 to rank0
5569 04:47:11.580868 Final RX Vref Byte 0 = 57 to rank1
5570 04:47:11.584571 Final RX Vref Byte 1 = 50 to rank1==
5571 04:47:11.587751 Dram Type= 6, Freq= 0, CH_1, rank 0
5572 04:47:11.592648 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5573 04:47:11.593158 ==
5574 04:47:11.594752 DQS Delay:
5575 04:47:11.595216 DQS0 = 0, DQS1 = 0
5576 04:47:11.595586 DQM Delay:
5577 04:47:11.598448 DQM0 = 94, DQM1 = 88
5578 04:47:11.598910 DQ Delay:
5579 04:47:11.601029 DQ0 =98, DQ1 =88, DQ2 =84, DQ3 =92
5580 04:47:11.604092 DQ4 =94, DQ5 =104, DQ6 =100, DQ7 =94
5581 04:47:11.607702 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =80
5582 04:47:11.610808 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =98
5583 04:47:11.611372
5584 04:47:11.611739
5585 04:47:11.620847 [DQSOSCAuto] RK0, (LSB)MR18= 0x3939, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5586 04:47:11.624217 CH1 RK0: MR19=505, MR18=3939
5587 04:47:11.630702 CH1_RK0: MR19=0x505, MR18=0x3939, DQSOSC=404, MR23=63, INC=66, DEC=44
5588 04:47:11.631267
5589 04:47:11.634187 ----->DramcWriteLeveling(PI) begin...
5590 04:47:11.634760 ==
5591 04:47:11.637162 Dram Type= 6, Freq= 0, CH_1, rank 1
5592 04:47:11.641246 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5593 04:47:11.641709 ==
5594 04:47:11.643955 Write leveling (Byte 0): 26 => 26
5595 04:47:11.647357 Write leveling (Byte 1): 25 => 25
5596 04:47:11.650198 DramcWriteLeveling(PI) end<-----
5597 04:47:11.650946
5598 04:47:11.651370 ==
5599 04:47:11.653694 Dram Type= 6, Freq= 0, CH_1, rank 1
5600 04:47:11.657055 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5601 04:47:11.657517 ==
5602 04:47:11.660883 [Gating] SW mode calibration
5603 04:47:11.667091 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5604 04:47:11.673509 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5605 04:47:11.677250 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5606 04:47:11.680619 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5607 04:47:11.686594 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 04:47:11.689584 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 04:47:11.693040 0 10 16 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 1)
5610 04:47:11.700631 0 10 20 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
5611 04:47:11.703200 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5612 04:47:11.706683 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5613 04:47:11.713387 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5614 04:47:11.717498 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5615 04:47:11.720000 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 04:47:11.726262 0 11 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5617 04:47:11.729988 0 11 16 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
5618 04:47:11.733090 0 11 20 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
5619 04:47:11.740290 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5620 04:47:11.743796 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 04:47:11.746664 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 04:47:11.752686 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 04:47:11.756375 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 04:47:11.759401 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 04:47:11.766990 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5626 04:47:11.770008 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5627 04:47:11.773399 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 04:47:11.779166 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 04:47:11.782657 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 04:47:11.786072 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 04:47:11.792301 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 04:47:11.796255 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 04:47:11.800484 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 04:47:11.805657 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 04:47:11.809018 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 04:47:11.812461 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 04:47:11.819065 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 04:47:11.822275 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 04:47:11.825422 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 04:47:11.832108 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 04:47:11.835591 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5642 04:47:11.838673 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 04:47:11.842284 Total UI for P1: 0, mck2ui 16
5644 04:47:11.846276 best dqsien dly found for B0: ( 0, 14, 16)
5645 04:47:11.848764 Total UI for P1: 0, mck2ui 16
5646 04:47:11.852307 best dqsien dly found for B1: ( 0, 14, 18)
5647 04:47:11.856005 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5648 04:47:11.858421 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5649 04:47:11.859005
5650 04:47:11.865687 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5651 04:47:11.868796 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5652 04:47:11.869357 [Gating] SW calibration Done
5653 04:47:11.872401 ==
5654 04:47:11.875415 Dram Type= 6, Freq= 0, CH_1, rank 1
5655 04:47:11.878660 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5656 04:47:11.879130 ==
5657 04:47:11.879496 RX Vref Scan: 0
5658 04:47:11.879837
5659 04:47:11.882395 RX Vref 0 -> 0, step: 1
5660 04:47:11.882955
5661 04:47:11.885433 RX Delay -80 -> 252, step: 8
5662 04:47:11.888317 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5663 04:47:11.891483 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5664 04:47:11.895353 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5665 04:47:11.901515 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5666 04:47:11.904858 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5667 04:47:11.907779 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5668 04:47:11.911556 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5669 04:47:11.915367 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5670 04:47:11.921020 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5671 04:47:11.924883 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5672 04:47:11.927465 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5673 04:47:11.930886 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5674 04:47:11.934590 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5675 04:47:11.940856 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5676 04:47:11.944450 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5677 04:47:11.947366 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5678 04:47:11.947928 ==
5679 04:47:11.951504 Dram Type= 6, Freq= 0, CH_1, rank 1
5680 04:47:11.954296 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5681 04:47:11.954759 ==
5682 04:47:11.958654 DQS Delay:
5683 04:47:11.959219 DQS0 = 0, DQS1 = 0
5684 04:47:11.959587 DQM Delay:
5685 04:47:11.960772 DQM0 = 95, DQM1 = 87
5686 04:47:11.961241 DQ Delay:
5687 04:47:11.964155 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5688 04:47:11.968493 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =91
5689 04:47:11.970607 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5690 04:47:11.973812 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5691 04:47:11.974379
5692 04:47:11.974748
5693 04:47:11.975088 ==
5694 04:47:11.977370 Dram Type= 6, Freq= 0, CH_1, rank 1
5695 04:47:11.984160 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5696 04:47:11.984761 ==
5697 04:47:11.985145
5698 04:47:11.985488
5699 04:47:11.986927 TX Vref Scan disable
5700 04:47:11.987388 == TX Byte 0 ==
5701 04:47:11.991009 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5702 04:47:11.998104 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5703 04:47:11.998675 == TX Byte 1 ==
5704 04:47:12.000136 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5705 04:47:12.007498 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5706 04:47:12.008065 ==
5707 04:47:12.010191 Dram Type= 6, Freq= 0, CH_1, rank 1
5708 04:47:12.013409 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5709 04:47:12.013872 ==
5710 04:47:12.014236
5711 04:47:12.014568
5712 04:47:12.016764 TX Vref Scan disable
5713 04:47:12.021033 == TX Byte 0 ==
5714 04:47:12.025125 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5715 04:47:12.026872 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5716 04:47:12.030421 == TX Byte 1 ==
5717 04:47:12.033605 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5718 04:47:12.037047 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5719 04:47:12.037610
5720 04:47:12.040139 [DATLAT]
5721 04:47:12.040697 Freq=933, CH1 RK1
5722 04:47:12.041112
5723 04:47:12.043917 DATLAT Default: 0xb
5724 04:47:12.044479 0, 0xFFFF, sum = 0
5725 04:47:12.046957 1, 0xFFFF, sum = 0
5726 04:47:12.047524 2, 0xFFFF, sum = 0
5727 04:47:12.049839 3, 0xFFFF, sum = 0
5728 04:47:12.050305 4, 0xFFFF, sum = 0
5729 04:47:12.053055 5, 0xFFFF, sum = 0
5730 04:47:12.053520 6, 0xFFFF, sum = 0
5731 04:47:12.056619 7, 0xFFFF, sum = 0
5732 04:47:12.057239 8, 0xFFFF, sum = 0
5733 04:47:12.060156 9, 0xFFFF, sum = 0
5734 04:47:12.060775 10, 0x0, sum = 1
5735 04:47:12.063207 11, 0x0, sum = 2
5736 04:47:12.063810 12, 0x0, sum = 3
5737 04:47:12.066564 13, 0x0, sum = 4
5738 04:47:12.067315 best_step = 11
5739 04:47:12.067771
5740 04:47:12.068122 ==
5741 04:47:12.069582 Dram Type= 6, Freq= 0, CH_1, rank 1
5742 04:47:12.076263 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5743 04:47:12.076825 ==
5744 04:47:12.077209 RX Vref Scan: 0
5745 04:47:12.077577
5746 04:47:12.079777 RX Vref 0 -> 0, step: 1
5747 04:47:12.080235
5748 04:47:12.082932 RX Delay -69 -> 252, step: 4
5749 04:47:12.086126 iDelay=203, Bit 0, Center 96 (3 ~ 190) 188
5750 04:47:12.090112 iDelay=203, Bit 1, Center 92 (-1 ~ 186) 188
5751 04:47:12.096008 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5752 04:47:12.099629 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5753 04:47:12.103858 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5754 04:47:12.106158 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5755 04:47:12.109051 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5756 04:47:12.112959 iDelay=203, Bit 7, Center 94 (-1 ~ 190) 192
5757 04:47:12.120126 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5758 04:47:12.122999 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5759 04:47:12.126088 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5760 04:47:12.129446 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5761 04:47:12.132699 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5762 04:47:12.138961 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5763 04:47:12.142761 iDelay=203, Bit 14, Center 96 (-1 ~ 194) 196
5764 04:47:12.146737 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5765 04:47:12.147293 ==
5766 04:47:12.149389 Dram Type= 6, Freq= 0, CH_1, rank 1
5767 04:47:12.153345 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5768 04:47:12.153899 ==
5769 04:47:12.155486 DQS Delay:
5770 04:47:12.155944 DQS0 = 0, DQS1 = 0
5771 04:47:12.159596 DQM Delay:
5772 04:47:12.160150 DQM0 = 96, DQM1 = 87
5773 04:47:12.160515 DQ Delay:
5774 04:47:12.162427 DQ0 =96, DQ1 =92, DQ2 =88, DQ3 =92
5775 04:47:12.165511 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5776 04:47:12.169475 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5777 04:47:12.172070 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5778 04:47:12.175333
5779 04:47:12.176045
5780 04:47:12.181988 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5781 04:47:12.185252 CH1 RK1: MR19=505, MR18=1F1F
5782 04:47:12.191826 CH1_RK1: MR19=0x505, MR18=0x1F1F, DQSOSC=412, MR23=63, INC=63, DEC=42
5783 04:47:12.194876 [RxdqsGatingPostProcess] freq 933
5784 04:47:12.198178 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5785 04:47:12.202211 Pre-setting of DQS Precalculation
5786 04:47:12.208594 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5787 04:47:12.215266 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5788 04:47:12.222238 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5789 04:47:12.222802
5790 04:47:12.223166
5791 04:47:12.225039 [Calibration Summary] 1866 Mbps
5792 04:47:12.225602 CH 0, Rank 0
5793 04:47:12.228795 SW Impedance : PASS
5794 04:47:12.232169 DUTY Scan : NO K
5795 04:47:12.232768 ZQ Calibration : PASS
5796 04:47:12.234932 Jitter Meter : NO K
5797 04:47:12.239299 CBT Training : PASS
5798 04:47:12.239862 Write leveling : PASS
5799 04:47:12.242239 RX DQS gating : PASS
5800 04:47:12.244689 RX DQ/DQS(RDDQC) : PASS
5801 04:47:12.245293 TX DQ/DQS : PASS
5802 04:47:12.248308 RX DATLAT : PASS
5803 04:47:12.249066 RX DQ/DQS(Engine): PASS
5804 04:47:12.251389 TX OE : NO K
5805 04:47:12.251848 All Pass.
5806 04:47:12.252214
5807 04:47:12.254764 CH 0, Rank 1
5808 04:47:12.255221 SW Impedance : PASS
5809 04:47:12.258620 DUTY Scan : NO K
5810 04:47:12.261577 ZQ Calibration : PASS
5811 04:47:12.262135 Jitter Meter : NO K
5812 04:47:12.265218 CBT Training : PASS
5813 04:47:12.267881 Write leveling : PASS
5814 04:47:12.268437 RX DQS gating : PASS
5815 04:47:12.271026 RX DQ/DQS(RDDQC) : PASS
5816 04:47:12.275009 TX DQ/DQS : PASS
5817 04:47:12.275572 RX DATLAT : PASS
5818 04:47:12.278022 RX DQ/DQS(Engine): PASS
5819 04:47:12.281065 TX OE : NO K
5820 04:47:12.281626 All Pass.
5821 04:47:12.282012
5822 04:47:12.282351 CH 1, Rank 0
5823 04:47:12.284689 SW Impedance : PASS
5824 04:47:12.288074 DUTY Scan : NO K
5825 04:47:12.288634 ZQ Calibration : PASS
5826 04:47:12.290871 Jitter Meter : NO K
5827 04:47:12.293925 CBT Training : PASS
5828 04:47:12.294395 Write leveling : PASS
5829 04:47:12.297626 RX DQS gating : PASS
5830 04:47:12.301178 RX DQ/DQS(RDDQC) : PASS
5831 04:47:12.301734 TX DQ/DQS : PASS
5832 04:47:12.304310 RX DATLAT : PASS
5833 04:47:12.307685 RX DQ/DQS(Engine): PASS
5834 04:47:12.308249 TX OE : NO K
5835 04:47:12.308617 All Pass.
5836 04:47:12.310708
5837 04:47:12.311158 CH 1, Rank 1
5838 04:47:12.313899 SW Impedance : PASS
5839 04:47:12.314412 DUTY Scan : NO K
5840 04:47:12.317384 ZQ Calibration : PASS
5841 04:47:12.317836 Jitter Meter : NO K
5842 04:47:12.321258 CBT Training : PASS
5843 04:47:12.324526 Write leveling : PASS
5844 04:47:12.325141 RX DQS gating : PASS
5845 04:47:12.327853 RX DQ/DQS(RDDQC) : PASS
5846 04:47:12.331522 TX DQ/DQS : PASS
5847 04:47:12.332092 RX DATLAT : PASS
5848 04:47:12.334454 RX DQ/DQS(Engine): PASS
5849 04:47:12.337743 TX OE : NO K
5850 04:47:12.338208 All Pass.
5851 04:47:12.338572
5852 04:47:12.341330 DramC Write-DBI off
5853 04:47:12.341889 PER_BANK_REFRESH: Hybrid Mode
5854 04:47:12.343872 TX_TRACKING: ON
5855 04:47:12.354429 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5856 04:47:12.357122 [FAST_K] Save calibration result to emmc
5857 04:47:12.360923 dramc_set_vcore_voltage set vcore to 650000
5858 04:47:12.361486 Read voltage for 400, 6
5859 04:47:12.364626 Vio18 = 0
5860 04:47:12.365240 Vcore = 650000
5861 04:47:12.365609 Vdram = 0
5862 04:47:12.366629 Vddq = 0
5863 04:47:12.367086 Vmddr = 0
5864 04:47:12.373879 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5865 04:47:12.377589 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5866 04:47:12.380432 MEM_TYPE=3, freq_sel=20
5867 04:47:12.383396 sv_algorithm_assistance_LP4_800
5868 04:47:12.386976 ============ PULL DRAM RESETB DOWN ============
5869 04:47:12.390406 ========== PULL DRAM RESETB DOWN end =========
5870 04:47:12.397402 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5871 04:47:12.400139 ===================================
5872 04:47:12.400695 LPDDR4 DRAM CONFIGURATION
5873 04:47:12.403536 ===================================
5874 04:47:12.407249 EX_ROW_EN[0] = 0x0
5875 04:47:12.409480 EX_ROW_EN[1] = 0x0
5876 04:47:12.409942 LP4Y_EN = 0x0
5877 04:47:12.413664 WORK_FSP = 0x0
5878 04:47:12.414229 WL = 0x2
5879 04:47:12.416415 RL = 0x2
5880 04:47:12.416921 BL = 0x2
5881 04:47:12.419595 RPST = 0x0
5882 04:47:12.420161 RD_PRE = 0x0
5883 04:47:12.424382 WR_PRE = 0x1
5884 04:47:12.424988 WR_PST = 0x0
5885 04:47:12.426485 DBI_WR = 0x0
5886 04:47:12.426943 DBI_RD = 0x0
5887 04:47:12.429506 OTF = 0x1
5888 04:47:12.432768 ===================================
5889 04:47:12.436370 ===================================
5890 04:47:12.436981 ANA top config
5891 04:47:12.439350 ===================================
5892 04:47:12.442873 DLL_ASYNC_EN = 0
5893 04:47:12.446026 ALL_SLAVE_EN = 1
5894 04:47:12.450072 NEW_RANK_MODE = 1
5895 04:47:12.450641 DLL_IDLE_MODE = 1
5896 04:47:12.453631 LP45_APHY_COMB_EN = 1
5897 04:47:12.457438 TX_ODT_DIS = 1
5898 04:47:12.460242 NEW_8X_MODE = 1
5899 04:47:12.462669 ===================================
5900 04:47:12.465967 ===================================
5901 04:47:12.469115 data_rate = 800
5902 04:47:12.469683 CKR = 1
5903 04:47:12.472615 DQ_P2S_RATIO = 4
5904 04:47:12.475942 ===================================
5905 04:47:12.479276 CA_P2S_RATIO = 4
5906 04:47:12.483052 DQ_CA_OPEN = 0
5907 04:47:12.485852 DQ_SEMI_OPEN = 1
5908 04:47:12.489672 CA_SEMI_OPEN = 1
5909 04:47:12.490253 CA_FULL_RATE = 0
5910 04:47:12.492215 DQ_CKDIV4_EN = 0
5911 04:47:12.495659 CA_CKDIV4_EN = 1
5912 04:47:12.498699 CA_PREDIV_EN = 0
5913 04:47:12.502896 PH8_DLY = 0
5914 04:47:12.505403 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5915 04:47:12.505862 DQ_AAMCK_DIV = 0
5916 04:47:12.509321 CA_AAMCK_DIV = 0
5917 04:47:12.513446 CA_ADMCK_DIV = 4
5918 04:47:12.516426 DQ_TRACK_CA_EN = 0
5919 04:47:12.518686 CA_PICK = 800
5920 04:47:12.522002 CA_MCKIO = 400
5921 04:47:12.526038 MCKIO_SEMI = 400
5922 04:47:12.526603 PLL_FREQ = 3016
5923 04:47:12.531623 DQ_UI_PI_RATIO = 32
5924 04:47:12.532559 CA_UI_PI_RATIO = 32
5925 04:47:12.535976 ===================================
5926 04:47:12.538975 ===================================
5927 04:47:12.541756 memory_type:LPDDR4
5928 04:47:12.544918 GP_NUM : 10
5929 04:47:12.545485 SRAM_EN : 1
5930 04:47:12.549392 MD32_EN : 0
5931 04:47:12.552575 ===================================
5932 04:47:12.553176 [ANA_INIT] >>>>>>>>>>>>>>
5933 04:47:12.555770 <<<<<< [CONFIGURE PHASE]: ANA_TX
5934 04:47:12.558692 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5935 04:47:12.562437 ===================================
5936 04:47:12.565617 data_rate = 800,PCW = 0X7400
5937 04:47:12.568943 ===================================
5938 04:47:12.572151 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5939 04:47:12.578282 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5940 04:47:12.588599 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5941 04:47:12.595411 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5942 04:47:12.598377 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5943 04:47:12.601912 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5944 04:47:12.602475 [ANA_INIT] flow start
5945 04:47:12.605728 [ANA_INIT] PLL >>>>>>>>
5946 04:47:12.608520 [ANA_INIT] PLL <<<<<<<<
5947 04:47:12.611397 [ANA_INIT] MIDPI >>>>>>>>
5948 04:47:12.611858 [ANA_INIT] MIDPI <<<<<<<<
5949 04:47:12.614717 [ANA_INIT] DLL >>>>>>>>
5950 04:47:12.615299 [ANA_INIT] flow end
5951 04:47:12.621257 ============ LP4 DIFF to SE enter ============
5952 04:47:12.625537 ============ LP4 DIFF to SE exit ============
5953 04:47:12.628213 [ANA_INIT] <<<<<<<<<<<<<
5954 04:47:12.631539 [Flow] Enable top DCM control >>>>>
5955 04:47:12.634945 [Flow] Enable top DCM control <<<<<
5956 04:47:12.638102 Enable DLL master slave shuffle
5957 04:47:12.641666 ==============================================================
5958 04:47:12.644422 Gating Mode config
5959 04:47:12.651194 ==============================================================
5960 04:47:12.651752 Config description:
5961 04:47:12.660553 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5962 04:47:12.667755 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5963 04:47:12.670969 SELPH_MODE 0: By rank 1: By Phase
5964 04:47:12.678169 ==============================================================
5965 04:47:12.684211 GAT_TRACK_EN = 0
5966 04:47:12.685219 RX_GATING_MODE = 2
5967 04:47:12.686892 RX_GATING_TRACK_MODE = 2
5968 04:47:12.690650 SELPH_MODE = 1
5969 04:47:12.693912 PICG_EARLY_EN = 1
5970 04:47:12.697641 VALID_LAT_VALUE = 1
5971 04:47:12.700389 ==============================================================
5972 04:47:12.704286 Enter into Gating configuration >>>>
5973 04:47:12.707281 Exit from Gating configuration <<<<
5974 04:47:12.711623 Enter into DVFS_PRE_config >>>>>
5975 04:47:12.723549 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5976 04:47:12.726842 Exit from DVFS_PRE_config <<<<<
5977 04:47:12.727299 Enter into PICG configuration >>>>
5978 04:47:12.730908 Exit from PICG configuration <<<<
5979 04:47:12.733414 [RX_INPUT] configuration >>>>>
5980 04:47:12.737913 [RX_INPUT] configuration <<<<<
5981 04:47:12.744685 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5982 04:47:12.747278 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5983 04:47:12.753489 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5984 04:47:12.760100 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5985 04:47:12.766578 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5986 04:47:12.773614 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5987 04:47:12.776849 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5988 04:47:12.779681 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5989 04:47:12.783230 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5990 04:47:12.789515 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5991 04:47:12.795913 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5992 04:47:12.797041 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5993 04:47:12.800341 ===================================
5994 04:47:12.802916 LPDDR4 DRAM CONFIGURATION
5995 04:47:12.806446 ===================================
5996 04:47:12.810157 EX_ROW_EN[0] = 0x0
5997 04:47:12.810614 EX_ROW_EN[1] = 0x0
5998 04:47:12.813661 LP4Y_EN = 0x0
5999 04:47:12.814118 WORK_FSP = 0x0
6000 04:47:12.816341 WL = 0x2
6001 04:47:12.816830 RL = 0x2
6002 04:47:12.819682 BL = 0x2
6003 04:47:12.820241 RPST = 0x0
6004 04:47:12.822868 RD_PRE = 0x0
6005 04:47:12.823338 WR_PRE = 0x1
6006 04:47:12.826347 WR_PST = 0x0
6007 04:47:12.826804 DBI_WR = 0x0
6008 04:47:12.829930 DBI_RD = 0x0
6009 04:47:12.830486 OTF = 0x1
6010 04:47:12.833327 ===================================
6011 04:47:12.839310 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6012 04:47:12.843050 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6013 04:47:12.846920 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6014 04:47:12.850077 ===================================
6015 04:47:12.853139 LPDDR4 DRAM CONFIGURATION
6016 04:47:12.855635 ===================================
6017 04:47:12.859733 EX_ROW_EN[0] = 0x10
6018 04:47:12.860298 EX_ROW_EN[1] = 0x0
6019 04:47:12.863222 LP4Y_EN = 0x0
6020 04:47:12.863780 WORK_FSP = 0x0
6021 04:47:12.866123 WL = 0x2
6022 04:47:12.866578 RL = 0x2
6023 04:47:12.869081 BL = 0x2
6024 04:47:12.869638 RPST = 0x0
6025 04:47:12.872659 RD_PRE = 0x0
6026 04:47:12.873285 WR_PRE = 0x1
6027 04:47:12.876019 WR_PST = 0x0
6028 04:47:12.876574 DBI_WR = 0x0
6029 04:47:12.879237 DBI_RD = 0x0
6030 04:47:12.879690 OTF = 0x1
6031 04:47:12.882714 ===================================
6032 04:47:12.888905 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6033 04:47:12.893790 nWR fixed to 30
6034 04:47:12.896928 [ModeRegInit_LP4] CH0 RK0
6035 04:47:12.897395 [ModeRegInit_LP4] CH0 RK1
6036 04:47:12.900668 [ModeRegInit_LP4] CH1 RK0
6037 04:47:12.904237 [ModeRegInit_LP4] CH1 RK1
6038 04:47:12.904850 match AC timing 18
6039 04:47:12.910323 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6040 04:47:12.914441 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6041 04:47:12.917120 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6042 04:47:12.924057 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6043 04:47:12.926732 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6044 04:47:12.927191 ==
6045 04:47:12.930666 Dram Type= 6, Freq= 0, CH_0, rank 0
6046 04:47:12.933536 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6047 04:47:12.933997 ==
6048 04:47:12.940332 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6049 04:47:12.947002 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6050 04:47:12.950362 [CA 0] Center 36 (8~64) winsize 57
6051 04:47:12.953671 [CA 1] Center 36 (8~64) winsize 57
6052 04:47:12.956877 [CA 2] Center 36 (8~64) winsize 57
6053 04:47:12.960457 [CA 3] Center 36 (8~64) winsize 57
6054 04:47:12.961067 [CA 4] Center 36 (8~64) winsize 57
6055 04:47:12.964218 [CA 5] Center 36 (8~64) winsize 57
6056 04:47:12.964815
6057 04:47:12.970177 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6058 04:47:12.970732
6059 04:47:12.973630 [CATrainingPosCal] consider 1 rank data
6060 04:47:12.977006 u2DelayCellTimex100 = 270/100 ps
6061 04:47:12.979739 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6062 04:47:12.983494 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6063 04:47:12.988481 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6064 04:47:12.990041 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6065 04:47:12.992912 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6066 04:47:12.996179 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6067 04:47:12.996637
6068 04:47:13.000477 CA PerBit enable=1, Macro0, CA PI delay=36
6069 04:47:13.001107
6070 04:47:13.003366 [CBTSetCACLKResult] CA Dly = 36
6071 04:47:13.006532 CS Dly: 1 (0~32)
6072 04:47:13.006989 ==
6073 04:47:13.009830 Dram Type= 6, Freq= 0, CH_0, rank 1
6074 04:47:13.012696 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6075 04:47:13.013200 ==
6076 04:47:13.020292 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6077 04:47:13.026488 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6078 04:47:13.030007 [CA 0] Center 36 (8~64) winsize 57
6079 04:47:13.030595 [CA 1] Center 36 (8~64) winsize 57
6080 04:47:13.033122 [CA 2] Center 36 (8~64) winsize 57
6081 04:47:13.036537 [CA 3] Center 36 (8~64) winsize 57
6082 04:47:13.039892 [CA 4] Center 36 (8~64) winsize 57
6083 04:47:13.043337 [CA 5] Center 36 (8~64) winsize 57
6084 04:47:13.043891
6085 04:47:13.046122 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6086 04:47:13.046578
6087 04:47:13.049438 [CATrainingPosCal] consider 2 rank data
6088 04:47:13.052766 u2DelayCellTimex100 = 270/100 ps
6089 04:47:13.055831 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6090 04:47:13.063246 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6091 04:47:13.066719 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6092 04:47:13.069860 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6093 04:47:13.072443 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6094 04:47:13.075640 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6095 04:47:13.076100
6096 04:47:13.079366 CA PerBit enable=1, Macro0, CA PI delay=36
6097 04:47:13.079929
6098 04:47:13.082232 [CBTSetCACLKResult] CA Dly = 36
6099 04:47:13.085936 CS Dly: 1 (0~32)
6100 04:47:13.086492
6101 04:47:13.089457 ----->DramcWriteLeveling(PI) begin...
6102 04:47:13.090019 ==
6103 04:47:13.092951 Dram Type= 6, Freq= 0, CH_0, rank 0
6104 04:47:13.095388 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6105 04:47:13.096101 ==
6106 04:47:13.098909 Write leveling (Byte 0): 32 => 0
6107 04:47:13.102984 Write leveling (Byte 1): 32 => 0
6108 04:47:13.105632 DramcWriteLeveling(PI) end<-----
6109 04:47:13.106091
6110 04:47:13.106456 ==
6111 04:47:13.108854 Dram Type= 6, Freq= 0, CH_0, rank 0
6112 04:47:13.113331 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6113 04:47:13.113888 ==
6114 04:47:13.115711 [Gating] SW mode calibration
6115 04:47:13.122246 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6116 04:47:13.129710 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6117 04:47:13.132509 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6118 04:47:13.135583 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6119 04:47:13.141959 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6120 04:47:13.145254 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6121 04:47:13.148559 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6122 04:47:13.155214 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6123 04:47:13.158486 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6124 04:47:13.162019 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6125 04:47:13.168770 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6126 04:47:13.169336 Total UI for P1: 0, mck2ui 16
6127 04:47:13.175098 best dqsien dly found for B0: ( 0, 10, 16)
6128 04:47:13.175656 Total UI for P1: 0, mck2ui 16
6129 04:47:13.178931 best dqsien dly found for B1: ( 0, 10, 24)
6130 04:47:13.185298 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6131 04:47:13.189634 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6132 04:47:13.190187
6133 04:47:13.191662 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6134 04:47:13.194863 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6135 04:47:13.198275 [Gating] SW calibration Done
6136 04:47:13.198786 ==
6137 04:47:13.201646 Dram Type= 6, Freq= 0, CH_0, rank 0
6138 04:47:13.204888 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6139 04:47:13.205364 ==
6140 04:47:13.207909 RX Vref Scan: 0
6141 04:47:13.208360
6142 04:47:13.208759 RX Vref 0 -> 0, step: 1
6143 04:47:13.209116
6144 04:47:13.211678 RX Delay -410 -> 252, step: 16
6145 04:47:13.218060 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6146 04:47:13.221364 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6147 04:47:13.224767 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6148 04:47:13.228079 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6149 04:47:13.234928 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6150 04:47:13.238664 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6151 04:47:13.242073 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6152 04:47:13.244797 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6153 04:47:13.251530 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6154 04:47:13.254709 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6155 04:47:13.258358 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6156 04:47:13.260737 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6157 04:47:13.268277 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6158 04:47:13.271048 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6159 04:47:13.274161 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6160 04:47:13.281241 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6161 04:47:13.281764 ==
6162 04:47:13.284656 Dram Type= 6, Freq= 0, CH_0, rank 0
6163 04:47:13.288471 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6164 04:47:13.289073 ==
6165 04:47:13.289439 DQS Delay:
6166 04:47:13.290689 DQS0 = 51, DQS1 = 59
6167 04:47:13.291143 DQM Delay:
6168 04:47:13.293540 DQM0 = 12, DQM1 = 15
6169 04:47:13.294000 DQ Delay:
6170 04:47:13.297711 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6171 04:47:13.300609 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6172 04:47:13.304337 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6173 04:47:13.307513 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6174 04:47:13.308067
6175 04:47:13.308430
6176 04:47:13.308843 ==
6177 04:47:13.310258 Dram Type= 6, Freq= 0, CH_0, rank 0
6178 04:47:13.313647 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6179 04:47:13.314106 ==
6180 04:47:13.314465
6181 04:47:13.314797
6182 04:47:13.317493 TX Vref Scan disable
6183 04:47:13.321383 == TX Byte 0 ==
6184 04:47:13.324095 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6185 04:47:13.327016 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6186 04:47:13.330322 == TX Byte 1 ==
6187 04:47:13.334408 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6188 04:47:13.337058 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6189 04:47:13.337522 ==
6190 04:47:13.340418 Dram Type= 6, Freq= 0, CH_0, rank 0
6191 04:47:13.343660 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6192 04:47:13.347123 ==
6193 04:47:13.347683
6194 04:47:13.348047
6195 04:47:13.348384 TX Vref Scan disable
6196 04:47:13.349948 == TX Byte 0 ==
6197 04:47:13.353654 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6198 04:47:13.357546 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6199 04:47:13.361184 == TX Byte 1 ==
6200 04:47:13.363804 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6201 04:47:13.367293 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6202 04:47:13.367854
6203 04:47:13.370229 [DATLAT]
6204 04:47:13.370785 Freq=400, CH0 RK0
6205 04:47:13.371202
6206 04:47:13.373387 DATLAT Default: 0xf
6207 04:47:13.373847 0, 0xFFFF, sum = 0
6208 04:47:13.377235 1, 0xFFFF, sum = 0
6209 04:47:13.377818 2, 0xFFFF, sum = 0
6210 04:47:13.380570 3, 0xFFFF, sum = 0
6211 04:47:13.381158 4, 0xFFFF, sum = 0
6212 04:47:13.383373 5, 0xFFFF, sum = 0
6213 04:47:13.383940 6, 0xFFFF, sum = 0
6214 04:47:13.387375 7, 0xFFFF, sum = 0
6215 04:47:13.387941 8, 0xFFFF, sum = 0
6216 04:47:13.390342 9, 0xFFFF, sum = 0
6217 04:47:13.390807 10, 0xFFFF, sum = 0
6218 04:47:13.393286 11, 0xFFFF, sum = 0
6219 04:47:13.393868 12, 0x0, sum = 1
6220 04:47:13.396548 13, 0x0, sum = 2
6221 04:47:13.397110 14, 0x0, sum = 3
6222 04:47:13.399472 15, 0x0, sum = 4
6223 04:47:13.399935 best_step = 13
6224 04:47:13.400299
6225 04:47:13.400636 ==
6226 04:47:13.403066 Dram Type= 6, Freq= 0, CH_0, rank 0
6227 04:47:13.410078 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6228 04:47:13.410644 ==
6229 04:47:13.411013 RX Vref Scan: 1
6230 04:47:13.411355
6231 04:47:13.412603 RX Vref 0 -> 0, step: 1
6232 04:47:13.413120
6233 04:47:13.417033 RX Delay -359 -> 252, step: 8
6234 04:47:13.417598
6235 04:47:13.420067 Set Vref, RX VrefLevel [Byte0]: 45
6236 04:47:13.422580 [Byte1]: 52
6237 04:47:13.427471
6238 04:47:13.428032 Final RX Vref Byte 0 = 45 to rank0
6239 04:47:13.430307 Final RX Vref Byte 1 = 52 to rank0
6240 04:47:13.434387 Final RX Vref Byte 0 = 45 to rank1
6241 04:47:13.436731 Final RX Vref Byte 1 = 52 to rank1==
6242 04:47:13.439753 Dram Type= 6, Freq= 0, CH_0, rank 0
6243 04:47:13.446163 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6244 04:47:13.446729 ==
6245 04:47:13.447097 DQS Delay:
6246 04:47:13.449052 DQS0 = 52, DQS1 = 64
6247 04:47:13.449510 DQM Delay:
6248 04:47:13.449877 DQM0 = 8, DQM1 = 14
6249 04:47:13.453428 DQ Delay:
6250 04:47:13.456329 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6251 04:47:13.456821 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6252 04:47:13.459050 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6253 04:47:13.463115 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6254 04:47:13.463680
6255 04:47:13.466437
6256 04:47:13.472572 [DQSOSCAuto] RK0, (LSB)MR18= 0x9898, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
6257 04:47:13.475828 CH0 RK0: MR19=C0C, MR18=9898
6258 04:47:13.482192 CH0_RK0: MR19=0xC0C, MR18=0x9898, DQSOSC=390, MR23=63, INC=388, DEC=258
6259 04:47:13.482802 ==
6260 04:47:13.485896 Dram Type= 6, Freq= 0, CH_0, rank 1
6261 04:47:13.489611 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6262 04:47:13.490325 ==
6263 04:47:13.492161 [Gating] SW mode calibration
6264 04:47:13.499114 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6265 04:47:13.505602 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6266 04:47:13.509030 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6267 04:47:13.512056 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6268 04:47:13.519214 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6269 04:47:13.522044 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
6270 04:47:13.525645 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6271 04:47:13.531826 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6272 04:47:13.535627 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6273 04:47:13.539075 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6274 04:47:13.545159 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6275 04:47:13.545724 Total UI for P1: 0, mck2ui 16
6276 04:47:13.549932 best dqsien dly found for B0: ( 0, 10, 16)
6277 04:47:13.552283 Total UI for P1: 0, mck2ui 16
6278 04:47:13.554975 best dqsien dly found for B1: ( 0, 10, 24)
6279 04:47:13.561968 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6280 04:47:13.565252 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6281 04:47:13.565978
6282 04:47:13.568400 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6283 04:47:13.572447 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6284 04:47:13.575110 [Gating] SW calibration Done
6285 04:47:13.575669 ==
6286 04:47:13.578623 Dram Type= 6, Freq= 0, CH_0, rank 1
6287 04:47:13.581725 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6288 04:47:13.582268 ==
6289 04:47:13.585136 RX Vref Scan: 0
6290 04:47:13.585702
6291 04:47:13.586070 RX Vref 0 -> 0, step: 1
6292 04:47:13.586410
6293 04:47:13.588535 RX Delay -410 -> 252, step: 16
6294 04:47:13.594923 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6295 04:47:13.598396 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6296 04:47:13.601535 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6297 04:47:13.605187 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6298 04:47:13.608390 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6299 04:47:13.615636 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6300 04:47:13.618857 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6301 04:47:13.621475 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6302 04:47:13.628463 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6303 04:47:13.632086 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6304 04:47:13.635309 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6305 04:47:13.638697 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6306 04:47:13.645270 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6307 04:47:13.648186 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6308 04:47:13.651240 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6309 04:47:13.654916 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6310 04:47:13.657921 ==
6311 04:47:13.661420 Dram Type= 6, Freq= 0, CH_0, rank 1
6312 04:47:13.664749 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6313 04:47:13.665370 ==
6314 04:47:13.665748 DQS Delay:
6315 04:47:13.668572 DQS0 = 43, DQS1 = 59
6316 04:47:13.669201 DQM Delay:
6317 04:47:13.671067 DQM0 = 7, DQM1 = 14
6318 04:47:13.671617 DQ Delay:
6319 04:47:13.674383 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6320 04:47:13.678159 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6321 04:47:13.681337 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6322 04:47:13.684593 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6323 04:47:13.685194
6324 04:47:13.685566
6325 04:47:13.685903 ==
6326 04:47:13.687862 Dram Type= 6, Freq= 0, CH_0, rank 1
6327 04:47:13.691220 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6328 04:47:13.691780 ==
6329 04:47:13.692154
6330 04:47:13.692494
6331 04:47:13.693977 TX Vref Scan disable
6332 04:47:13.694437 == TX Byte 0 ==
6333 04:47:13.700822 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6334 04:47:13.704299 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6335 04:47:13.704923 == TX Byte 1 ==
6336 04:47:13.710947 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6337 04:47:13.714504 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6338 04:47:13.715061 ==
6339 04:47:13.717372 Dram Type= 6, Freq= 0, CH_0, rank 1
6340 04:47:13.720388 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6341 04:47:13.720882 ==
6342 04:47:13.721253
6343 04:47:13.721591
6344 04:47:13.724129 TX Vref Scan disable
6345 04:47:13.724680 == TX Byte 0 ==
6346 04:47:13.731284 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6347 04:47:13.734643 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6348 04:47:13.735248 == TX Byte 1 ==
6349 04:47:13.740875 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6350 04:47:13.743843 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6351 04:47:13.744397
6352 04:47:13.744830 [DATLAT]
6353 04:47:13.747559 Freq=400, CH0 RK1
6354 04:47:13.748150
6355 04:47:13.748521 DATLAT Default: 0xd
6356 04:47:13.750226 0, 0xFFFF, sum = 0
6357 04:47:13.750690 1, 0xFFFF, sum = 0
6358 04:47:13.754680 2, 0xFFFF, sum = 0
6359 04:47:13.755418 3, 0xFFFF, sum = 0
6360 04:47:13.757293 4, 0xFFFF, sum = 0
6361 04:47:13.757755 5, 0xFFFF, sum = 0
6362 04:47:13.759803 6, 0xFFFF, sum = 0
6363 04:47:13.760321 7, 0xFFFF, sum = 0
6364 04:47:13.763626 8, 0xFFFF, sum = 0
6365 04:47:13.767085 9, 0xFFFF, sum = 0
6366 04:47:13.767548 10, 0xFFFF, sum = 0
6367 04:47:13.770701 11, 0xFFFF, sum = 0
6368 04:47:13.771161 12, 0x0, sum = 1
6369 04:47:13.774066 13, 0x0, sum = 2
6370 04:47:13.774484 14, 0x0, sum = 3
6371 04:47:13.774815 15, 0x0, sum = 4
6372 04:47:13.776381 best_step = 13
6373 04:47:13.776825
6374 04:47:13.777156 ==
6375 04:47:13.780252 Dram Type= 6, Freq= 0, CH_0, rank 1
6376 04:47:13.783023 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6377 04:47:13.783452 ==
6378 04:47:13.786865 RX Vref Scan: 0
6379 04:47:13.787370
6380 04:47:13.789922 RX Vref 0 -> 0, step: 1
6381 04:47:13.790433
6382 04:47:13.790764 RX Delay -359 -> 252, step: 8
6383 04:47:13.798324 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6384 04:47:13.802670 iDelay=217, Bit 1, Center -36 (-287 ~ 216) 504
6385 04:47:13.804772 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6386 04:47:13.812114 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6387 04:47:13.815468 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6388 04:47:13.818065 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6389 04:47:13.822100 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6390 04:47:13.828633 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6391 04:47:13.831667 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6392 04:47:13.834979 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6393 04:47:13.839814 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6394 04:47:13.844529 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6395 04:47:13.848261 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6396 04:47:13.851470 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6397 04:47:13.854959 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6398 04:47:13.862020 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6399 04:47:13.862676 ==
6400 04:47:13.864624 Dram Type= 6, Freq= 0, CH_0, rank 1
6401 04:47:13.868439 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6402 04:47:13.869086 ==
6403 04:47:13.869433 DQS Delay:
6404 04:47:13.871246 DQS0 = 52, DQS1 = 64
6405 04:47:13.871751 DQM Delay:
6406 04:47:13.874824 DQM0 = 10, DQM1 = 14
6407 04:47:13.875240 DQ Delay:
6408 04:47:13.877375 DQ0 =4, DQ1 =16, DQ2 =8, DQ3 =4
6409 04:47:13.881510 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6410 04:47:13.884630 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6411 04:47:13.888084 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6412 04:47:13.888644
6413 04:47:13.889026
6414 04:47:13.895170 [DQSOSCAuto] RK1, (LSB)MR18= 0xc7c7, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 385 ps
6415 04:47:13.897783 CH0 RK1: MR19=C0C, MR18=C7C7
6416 04:47:13.903958 CH0_RK1: MR19=0xC0C, MR18=0xC7C7, DQSOSC=385, MR23=63, INC=398, DEC=265
6417 04:47:13.907851 [RxdqsGatingPostProcess] freq 400
6418 04:47:13.914096 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6419 04:47:13.919048 Pre-setting of DQS Precalculation
6420 04:47:13.920700 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6421 04:47:13.921237 ==
6422 04:47:13.923683 Dram Type= 6, Freq= 0, CH_1, rank 0
6423 04:47:13.927087 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6424 04:47:13.931021 ==
6425 04:47:13.933716 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6426 04:47:13.940933 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6427 04:47:13.944791 [CA 0] Center 36 (8~64) winsize 57
6428 04:47:13.947046 [CA 1] Center 36 (8~64) winsize 57
6429 04:47:13.951209 [CA 2] Center 36 (8~64) winsize 57
6430 04:47:13.954253 [CA 3] Center 36 (8~64) winsize 57
6431 04:47:13.957254 [CA 4] Center 36 (8~64) winsize 57
6432 04:47:13.960536 [CA 5] Center 36 (8~64) winsize 57
6433 04:47:13.961188
6434 04:47:13.964209 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6435 04:47:13.964833
6436 04:47:13.967548 [CATrainingPosCal] consider 1 rank data
6437 04:47:13.970883 u2DelayCellTimex100 = 270/100 ps
6438 04:47:13.974578 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6439 04:47:13.977322 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6440 04:47:13.980596 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6441 04:47:13.983479 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6442 04:47:13.987190 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6443 04:47:13.990512 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6444 04:47:13.991070
6445 04:47:13.994306 CA PerBit enable=1, Macro0, CA PI delay=36
6446 04:47:13.997051
6447 04:47:13.997512 [CBTSetCACLKResult] CA Dly = 36
6448 04:47:14.000269 CS Dly: 1 (0~32)
6449 04:47:14.000791 ==
6450 04:47:14.003705 Dram Type= 6, Freq= 0, CH_1, rank 1
6451 04:47:14.006987 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6452 04:47:14.007449 ==
6453 04:47:14.013669 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6454 04:47:14.020412 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6455 04:47:14.024281 [CA 0] Center 36 (8~64) winsize 57
6456 04:47:14.027085 [CA 1] Center 36 (8~64) winsize 57
6457 04:47:14.030439 [CA 2] Center 36 (8~64) winsize 57
6458 04:47:14.033135 [CA 3] Center 36 (8~64) winsize 57
6459 04:47:14.033692 [CA 4] Center 36 (8~64) winsize 57
6460 04:47:14.036376 [CA 5] Center 36 (8~64) winsize 57
6461 04:47:14.036966
6462 04:47:14.044146 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6463 04:47:14.044701
6464 04:47:14.046212 [CATrainingPosCal] consider 2 rank data
6465 04:47:14.049919 u2DelayCellTimex100 = 270/100 ps
6466 04:47:14.053296 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6467 04:47:14.057091 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6468 04:47:14.059536 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6469 04:47:14.063402 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6470 04:47:14.066435 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6471 04:47:14.070505 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6472 04:47:14.070967
6473 04:47:14.072796 CA PerBit enable=1, Macro0, CA PI delay=36
6474 04:47:14.073258
6475 04:47:14.076416 [CBTSetCACLKResult] CA Dly = 36
6476 04:47:14.079557 CS Dly: 1 (0~32)
6477 04:47:14.080017
6478 04:47:14.082559 ----->DramcWriteLeveling(PI) begin...
6479 04:47:14.083029 ==
6480 04:47:14.086090 Dram Type= 6, Freq= 0, CH_1, rank 0
6481 04:47:14.090093 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6482 04:47:14.090649 ==
6483 04:47:14.093089 Write leveling (Byte 0): 32 => 0
6484 04:47:14.096526 Write leveling (Byte 1): 32 => 0
6485 04:47:14.099375 DramcWriteLeveling(PI) end<-----
6486 04:47:14.099877
6487 04:47:14.100268 ==
6488 04:47:14.102521 Dram Type= 6, Freq= 0, CH_1, rank 0
6489 04:47:14.106195 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6490 04:47:14.106761 ==
6491 04:47:14.109579 [Gating] SW mode calibration
6492 04:47:14.116077 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6493 04:47:14.123117 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6494 04:47:14.125647 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6495 04:47:14.129308 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6496 04:47:14.136465 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6497 04:47:14.140140 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6498 04:47:14.142543 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6499 04:47:14.149310 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6500 04:47:14.152447 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6501 04:47:14.155828 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6502 04:47:14.162925 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6503 04:47:14.166221 Total UI for P1: 0, mck2ui 16
6504 04:47:14.170190 best dqsien dly found for B0: ( 0, 10, 16)
6505 04:47:14.170770 Total UI for P1: 0, mck2ui 16
6506 04:47:14.175595 best dqsien dly found for B1: ( 0, 10, 16)
6507 04:47:14.178986 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6508 04:47:14.182263 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6509 04:47:14.182780
6510 04:47:14.185633 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6511 04:47:14.189206 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6512 04:47:14.192320 [Gating] SW calibration Done
6513 04:47:14.192912 ==
6514 04:47:14.195717 Dram Type= 6, Freq= 0, CH_1, rank 0
6515 04:47:14.199613 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6516 04:47:14.200188 ==
6517 04:47:14.202009 RX Vref Scan: 0
6518 04:47:14.202488
6519 04:47:14.205324 RX Vref 0 -> 0, step: 1
6520 04:47:14.205802
6521 04:47:14.206289 RX Delay -410 -> 252, step: 16
6522 04:47:14.211887 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6523 04:47:14.214891 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6524 04:47:14.218753 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6525 04:47:14.225253 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6526 04:47:14.228890 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6527 04:47:14.232622 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6528 04:47:14.235191 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6529 04:47:14.241696 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6530 04:47:14.245523 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6531 04:47:14.249127 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6532 04:47:14.252013 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6533 04:47:14.258406 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6534 04:47:14.261340 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6535 04:47:14.264946 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6536 04:47:14.268245 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6537 04:47:14.274867 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6538 04:47:14.275443 ==
6539 04:47:14.277978 Dram Type= 6, Freq= 0, CH_1, rank 0
6540 04:47:14.281723 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6541 04:47:14.282305 ==
6542 04:47:14.282813 DQS Delay:
6543 04:47:14.284683 DQS0 = 43, DQS1 = 59
6544 04:47:14.285214 DQM Delay:
6545 04:47:14.288439 DQM0 = 6, DQM1 = 16
6546 04:47:14.289098 DQ Delay:
6547 04:47:14.291725 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6548 04:47:14.294945 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6549 04:47:14.298402 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6550 04:47:14.301412 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =32
6551 04:47:14.301991
6552 04:47:14.302359
6553 04:47:14.302710 ==
6554 04:47:14.304294 Dram Type= 6, Freq= 0, CH_1, rank 0
6555 04:47:14.307857 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6556 04:47:14.308420 ==
6557 04:47:14.308844
6558 04:47:14.312354
6559 04:47:14.312987 TX Vref Scan disable
6560 04:47:14.314516 == TX Byte 0 ==
6561 04:47:14.317613 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6562 04:47:14.320871 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6563 04:47:14.324162 == TX Byte 1 ==
6564 04:47:14.327855 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6565 04:47:14.331384 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6566 04:47:14.331938 ==
6567 04:47:14.337685 Dram Type= 6, Freq= 0, CH_1, rank 0
6568 04:47:14.339128 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6569 04:47:14.340898 ==
6570 04:47:14.341361
6571 04:47:14.341728
6572 04:47:14.342068 TX Vref Scan disable
6573 04:47:14.344200 == TX Byte 0 ==
6574 04:47:14.348101 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6575 04:47:14.351120 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6576 04:47:14.354257 == TX Byte 1 ==
6577 04:47:14.357476 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6578 04:47:14.360835 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6579 04:47:14.361301
6580 04:47:14.364080 [DATLAT]
6581 04:47:14.364636 Freq=400, CH1 RK0
6582 04:47:14.365048
6583 04:47:14.367388 DATLAT Default: 0xf
6584 04:47:14.367943 0, 0xFFFF, sum = 0
6585 04:47:14.371536 1, 0xFFFF, sum = 0
6586 04:47:14.372006 2, 0xFFFF, sum = 0
6587 04:47:14.373945 3, 0xFFFF, sum = 0
6588 04:47:14.374512 4, 0xFFFF, sum = 0
6589 04:47:14.377111 5, 0xFFFF, sum = 0
6590 04:47:14.377579 6, 0xFFFF, sum = 0
6591 04:47:14.380820 7, 0xFFFF, sum = 0
6592 04:47:14.383618 8, 0xFFFF, sum = 0
6593 04:47:14.384172 9, 0xFFFF, sum = 0
6594 04:47:14.387385 10, 0xFFFF, sum = 0
6595 04:47:14.387948 11, 0xFFFF, sum = 0
6596 04:47:14.390155 12, 0x0, sum = 1
6597 04:47:14.390622 13, 0x0, sum = 2
6598 04:47:14.394314 14, 0x0, sum = 3
6599 04:47:14.394784 15, 0x0, sum = 4
6600 04:47:14.395155 best_step = 13
6601 04:47:14.395496
6602 04:47:14.396898 ==
6603 04:47:14.401223 Dram Type= 6, Freq= 0, CH_1, rank 0
6604 04:47:14.403746 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6605 04:47:14.404231 ==
6606 04:47:14.404597 RX Vref Scan: 1
6607 04:47:14.404989
6608 04:47:14.407350 RX Vref 0 -> 0, step: 1
6609 04:47:14.407903
6610 04:47:14.410130 RX Delay -359 -> 252, step: 8
6611 04:47:14.410591
6612 04:47:14.413590 Set Vref, RX VrefLevel [Byte0]: 57
6613 04:47:14.417277 [Byte1]: 50
6614 04:47:14.420586
6615 04:47:14.421177 Final RX Vref Byte 0 = 57 to rank0
6616 04:47:14.423942 Final RX Vref Byte 1 = 50 to rank0
6617 04:47:14.426974 Final RX Vref Byte 0 = 57 to rank1
6618 04:47:14.430527 Final RX Vref Byte 1 = 50 to rank1==
6619 04:47:14.433790 Dram Type= 6, Freq= 0, CH_1, rank 0
6620 04:47:14.441216 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6621 04:47:14.441777 ==
6622 04:47:14.442144 DQS Delay:
6623 04:47:14.444814 DQS0 = 48, DQS1 = 64
6624 04:47:14.445369 DQM Delay:
6625 04:47:14.445740 DQM0 = 7, DQM1 = 16
6626 04:47:14.449585 DQ Delay:
6627 04:47:14.450645 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4
6628 04:47:14.451103 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6629 04:47:14.453664 DQ8 =0, DQ9 =8, DQ10 =20, DQ11 =8
6630 04:47:14.457409 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6631 04:47:14.457962
6632 04:47:14.458329
6633 04:47:14.467613 [DQSOSCAuto] RK0, (LSB)MR18= 0xdcdc, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 382 ps
6634 04:47:14.470746 CH1 RK0: MR19=C0C, MR18=DCDC
6635 04:47:14.477546 CH1_RK0: MR19=0xC0C, MR18=0xDCDC, DQSOSC=382, MR23=63, INC=404, DEC=269
6636 04:47:14.478133 ==
6637 04:47:14.480121 Dram Type= 6, Freq= 0, CH_1, rank 1
6638 04:47:14.483774 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6639 04:47:14.484244 ==
6640 04:47:14.487188 [Gating] SW mode calibration
6641 04:47:14.493549 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6642 04:47:14.496806 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6643 04:47:14.505311 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6644 04:47:14.506577 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6645 04:47:14.509896 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6646 04:47:14.517264 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6647 04:47:14.519779 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6648 04:47:14.523255 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6649 04:47:14.530384 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6650 04:47:14.533510 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6651 04:47:14.536693 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6652 04:47:14.540093 Total UI for P1: 0, mck2ui 16
6653 04:47:14.543201 best dqsien dly found for B0: ( 0, 10, 16)
6654 04:47:14.546896 Total UI for P1: 0, mck2ui 16
6655 04:47:14.549470 best dqsien dly found for B1: ( 0, 10, 16)
6656 04:47:14.553492 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6657 04:47:14.557117 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6658 04:47:14.559409
6659 04:47:14.563416 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6660 04:47:14.566887 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6661 04:47:14.569774 [Gating] SW calibration Done
6662 04:47:14.570351 ==
6663 04:47:14.572749 Dram Type= 6, Freq= 0, CH_1, rank 1
6664 04:47:14.576374 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6665 04:47:14.576970 ==
6666 04:47:14.579740 RX Vref Scan: 0
6667 04:47:14.580292
6668 04:47:14.580659 RX Vref 0 -> 0, step: 1
6669 04:47:14.581061
6670 04:47:14.582769 RX Delay -410 -> 252, step: 16
6671 04:47:14.586257 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6672 04:47:14.592828 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6673 04:47:14.596354 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6674 04:47:14.599333 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6675 04:47:14.602701 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6676 04:47:14.610027 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6677 04:47:14.612840 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6678 04:47:14.617780 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6679 04:47:14.620471 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6680 04:47:14.626472 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6681 04:47:14.629012 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6682 04:47:14.633349 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6683 04:47:14.639412 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6684 04:47:14.642585 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6685 04:47:14.645796 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6686 04:47:14.650006 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6687 04:47:14.650562 ==
6688 04:47:14.652422 Dram Type= 6, Freq= 0, CH_1, rank 1
6689 04:47:14.660201 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6690 04:47:14.660909 ==
6691 04:47:14.661296 DQS Delay:
6692 04:47:14.662783 DQS0 = 35, DQS1 = 59
6693 04:47:14.663244 DQM Delay:
6694 04:47:14.663614 DQM0 = 2, DQM1 = 17
6695 04:47:14.665394 DQ Delay:
6696 04:47:14.668482 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6697 04:47:14.668995 DQ4 =0, DQ5 =8, DQ6 =8, DQ7 =0
6698 04:47:14.673075 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6699 04:47:14.675617 DQ12 =32, DQ13 =24, DQ14 =32, DQ15 =24
6700 04:47:14.676168
6701 04:47:14.676536
6702 04:47:14.678922 ==
6703 04:47:14.682526 Dram Type= 6, Freq= 0, CH_1, rank 1
6704 04:47:14.685713 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6705 04:47:14.686181 ==
6706 04:47:14.686549
6707 04:47:14.686887
6708 04:47:14.689055 TX Vref Scan disable
6709 04:47:14.689614 == TX Byte 0 ==
6710 04:47:14.692007 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6711 04:47:14.698415 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6712 04:47:14.698883 == TX Byte 1 ==
6713 04:47:14.702576 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6714 04:47:14.708822 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6715 04:47:14.709382 ==
6716 04:47:14.712284 Dram Type= 6, Freq= 0, CH_1, rank 1
6717 04:47:14.715498 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6718 04:47:14.716056 ==
6719 04:47:14.716431
6720 04:47:14.716843
6721 04:47:14.719020 TX Vref Scan disable
6722 04:47:14.719572 == TX Byte 0 ==
6723 04:47:14.721690 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6724 04:47:14.728890 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6725 04:47:14.729445 == TX Byte 1 ==
6726 04:47:14.732513 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6727 04:47:14.739006 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6728 04:47:14.739562
6729 04:47:14.739930 [DATLAT]
6730 04:47:14.740402 Freq=400, CH1 RK1
6731 04:47:14.740968
6732 04:47:14.741726 DATLAT Default: 0xd
6733 04:47:14.745291 0, 0xFFFF, sum = 0
6734 04:47:14.745848 1, 0xFFFF, sum = 0
6735 04:47:14.749056 2, 0xFFFF, sum = 0
6736 04:47:14.749620 3, 0xFFFF, sum = 0
6737 04:47:14.751823 4, 0xFFFF, sum = 0
6738 04:47:14.752293 5, 0xFFFF, sum = 0
6739 04:47:14.755231 6, 0xFFFF, sum = 0
6740 04:47:14.755796 7, 0xFFFF, sum = 0
6741 04:47:14.758332 8, 0xFFFF, sum = 0
6742 04:47:14.758898 9, 0xFFFF, sum = 0
6743 04:47:14.761730 10, 0xFFFF, sum = 0
6744 04:47:14.762290 11, 0xFFFF, sum = 0
6745 04:47:14.765117 12, 0x0, sum = 1
6746 04:47:14.765729 13, 0x0, sum = 2
6747 04:47:14.768937 14, 0x0, sum = 3
6748 04:47:14.769510 15, 0x0, sum = 4
6749 04:47:14.772746 best_step = 13
6750 04:47:14.773349
6751 04:47:14.773721 ==
6752 04:47:14.775067 Dram Type= 6, Freq= 0, CH_1, rank 1
6753 04:47:14.779825 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6754 04:47:14.780382 ==
6755 04:47:14.781728 RX Vref Scan: 0
6756 04:47:14.782298
6757 04:47:14.782671 RX Vref 0 -> 0, step: 1
6758 04:47:14.783014
6759 04:47:14.784516 RX Delay -359 -> 252, step: 8
6760 04:47:14.793099 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6761 04:47:14.796500 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6762 04:47:14.798945 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6763 04:47:14.802602 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6764 04:47:14.809424 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6765 04:47:14.812844 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6766 04:47:14.815496 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6767 04:47:14.819530 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6768 04:47:14.825779 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6769 04:47:14.829280 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6770 04:47:14.833114 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6771 04:47:14.839554 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6772 04:47:14.842673 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6773 04:47:14.845846 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6774 04:47:14.848699 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6775 04:47:14.855681 iDelay=225, Bit 15, Center -44 (-287 ~ 200) 488
6776 04:47:14.856235 ==
6777 04:47:14.859163 Dram Type= 6, Freq= 0, CH_1, rank 1
6778 04:47:14.862748 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6779 04:47:14.863312 ==
6780 04:47:14.863679 DQS Delay:
6781 04:47:14.865409 DQS0 = 48, DQS1 = 64
6782 04:47:14.865869 DQM Delay:
6783 04:47:14.869414 DQM0 = 9, DQM1 = 15
6784 04:47:14.869970 DQ Delay:
6785 04:47:14.872063 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6786 04:47:14.875308 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6787 04:47:14.879434 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6788 04:47:14.882261 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =20
6789 04:47:14.882723
6790 04:47:14.883086
6791 04:47:14.889986 [DQSOSCAuto] RK1, (LSB)MR18= 0xb1b1, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6792 04:47:14.893614 CH1 RK1: MR19=C0C, MR18=B1B1
6793 04:47:14.899023 CH1_RK1: MR19=0xC0C, MR18=0xB1B1, DQSOSC=387, MR23=63, INC=394, DEC=262
6794 04:47:14.902126 [RxdqsGatingPostProcess] freq 400
6795 04:47:14.908631 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6796 04:47:14.909213 Pre-setting of DQS Precalculation
6797 04:47:14.915178 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6798 04:47:14.921449 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6799 04:47:14.928864 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6800 04:47:14.929424
6801 04:47:14.929791
6802 04:47:14.931933 [Calibration Summary] 800 Mbps
6803 04:47:14.935051 CH 0, Rank 0
6804 04:47:14.935609 SW Impedance : PASS
6805 04:47:14.938115 DUTY Scan : NO K
6806 04:47:14.941695 ZQ Calibration : PASS
6807 04:47:14.942110 Jitter Meter : NO K
6808 04:47:14.944686 CBT Training : PASS
6809 04:47:14.947589 Write leveling : PASS
6810 04:47:14.948003 RX DQS gating : PASS
6811 04:47:14.951962 RX DQ/DQS(RDDQC) : PASS
6812 04:47:14.955641 TX DQ/DQS : PASS
6813 04:47:14.956170 RX DATLAT : PASS
6814 04:47:14.957892 RX DQ/DQS(Engine): PASS
6815 04:47:14.961354 TX OE : NO K
6816 04:47:14.961888 All Pass.
6817 04:47:14.962224
6818 04:47:14.962530 CH 0, Rank 1
6819 04:47:14.964429 SW Impedance : PASS
6820 04:47:14.967721 DUTY Scan : NO K
6821 04:47:14.968442 ZQ Calibration : PASS
6822 04:47:14.971631 Jitter Meter : NO K
6823 04:47:14.972196 CBT Training : PASS
6824 04:47:14.974239 Write leveling : NO K
6825 04:47:14.977573 RX DQS gating : PASS
6826 04:47:14.977992 RX DQ/DQS(RDDQC) : PASS
6827 04:47:14.981106 TX DQ/DQS : PASS
6828 04:47:14.983932 RX DATLAT : PASS
6829 04:47:14.984350 RX DQ/DQS(Engine): PASS
6830 04:47:14.987730 TX OE : NO K
6831 04:47:14.988190 All Pass.
6832 04:47:14.988842
6833 04:47:14.990719 CH 1, Rank 0
6834 04:47:14.991133 SW Impedance : PASS
6835 04:47:14.994375 DUTY Scan : NO K
6836 04:47:14.997535 ZQ Calibration : PASS
6837 04:47:14.997954 Jitter Meter : NO K
6838 04:47:15.001293 CBT Training : PASS
6839 04:47:15.004413 Write leveling : PASS
6840 04:47:15.004892 RX DQS gating : PASS
6841 04:47:15.007617 RX DQ/DQS(RDDQC) : PASS
6842 04:47:15.010746 TX DQ/DQS : PASS
6843 04:47:15.011176 RX DATLAT : PASS
6844 04:47:15.014427 RX DQ/DQS(Engine): PASS
6845 04:47:15.017396 TX OE : NO K
6846 04:47:15.017812 All Pass.
6847 04:47:15.018141
6848 04:47:15.018446 CH 1, Rank 1
6849 04:47:15.020447 SW Impedance : PASS
6850 04:47:15.024201 DUTY Scan : NO K
6851 04:47:15.024614 ZQ Calibration : PASS
6852 04:47:15.027572 Jitter Meter : NO K
6853 04:47:15.031218 CBT Training : PASS
6854 04:47:15.031741 Write leveling : NO K
6855 04:47:15.033761 RX DQS gating : PASS
6856 04:47:15.036867 RX DQ/DQS(RDDQC) : PASS
6857 04:47:15.037280 TX DQ/DQS : PASS
6858 04:47:15.040492 RX DATLAT : PASS
6859 04:47:15.040968 RX DQ/DQS(Engine): PASS
6860 04:47:15.044054 TX OE : NO K
6861 04:47:15.044594 All Pass.
6862 04:47:15.045025
6863 04:47:15.046824 DramC Write-DBI off
6864 04:47:15.050847 PER_BANK_REFRESH: Hybrid Mode
6865 04:47:15.051370 TX_TRACKING: ON
6866 04:47:15.060806 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6867 04:47:15.063250 [FAST_K] Save calibration result to emmc
6868 04:47:15.067186 dramc_set_vcore_voltage set vcore to 725000
6869 04:47:15.070435 Read voltage for 1600, 0
6870 04:47:15.070956 Vio18 = 0
6871 04:47:15.073207 Vcore = 725000
6872 04:47:15.073624 Vdram = 0
6873 04:47:15.073992 Vddq = 0
6874 04:47:15.074321 Vmddr = 0
6875 04:47:15.080266 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6876 04:47:15.087704 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6877 04:47:15.088282 MEM_TYPE=3, freq_sel=13
6878 04:47:15.090713 sv_algorithm_assistance_LP4_3733
6879 04:47:15.093421 ============ PULL DRAM RESETB DOWN ============
6880 04:47:15.100372 ========== PULL DRAM RESETB DOWN end =========
6881 04:47:15.102902 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6882 04:47:15.107684 ===================================
6883 04:47:15.109699 LPDDR4 DRAM CONFIGURATION
6884 04:47:15.113737 ===================================
6885 04:47:15.114161 EX_ROW_EN[0] = 0x0
6886 04:47:15.116658 EX_ROW_EN[1] = 0x0
6887 04:47:15.117107 LP4Y_EN = 0x0
6888 04:47:15.120074 WORK_FSP = 0x1
6889 04:47:15.120601 WL = 0x5
6890 04:47:15.124068 RL = 0x5
6891 04:47:15.126167 BL = 0x2
6892 04:47:15.126587 RPST = 0x0
6893 04:47:15.130815 RD_PRE = 0x0
6894 04:47:15.131339 WR_PRE = 0x1
6895 04:47:15.133474 WR_PST = 0x1
6896 04:47:15.133899 DBI_WR = 0x0
6897 04:47:15.136288 DBI_RD = 0x0
6898 04:47:15.136735 OTF = 0x1
6899 04:47:15.140013 ===================================
6900 04:47:15.143100 ===================================
6901 04:47:15.147075 ANA top config
6902 04:47:15.149760 ===================================
6903 04:47:15.150308 DLL_ASYNC_EN = 0
6904 04:47:15.152992 ALL_SLAVE_EN = 0
6905 04:47:15.156447 NEW_RANK_MODE = 1
6906 04:47:15.160569 DLL_IDLE_MODE = 1
6907 04:47:15.161045 LP45_APHY_COMB_EN = 1
6908 04:47:15.163250 TX_ODT_DIS = 0
6909 04:47:15.166123 NEW_8X_MODE = 1
6910 04:47:15.169243 ===================================
6911 04:47:15.172761 ===================================
6912 04:47:15.175951 data_rate = 3200
6913 04:47:15.179331 CKR = 1
6914 04:47:15.182916 DQ_P2S_RATIO = 8
6915 04:47:15.185687 ===================================
6916 04:47:15.186184 CA_P2S_RATIO = 8
6917 04:47:15.188940 DQ_CA_OPEN = 0
6918 04:47:15.193588 DQ_SEMI_OPEN = 0
6919 04:47:15.195795 CA_SEMI_OPEN = 0
6920 04:47:15.200994 CA_FULL_RATE = 0
6921 04:47:15.202268 DQ_CKDIV4_EN = 0
6922 04:47:15.202705 CA_CKDIV4_EN = 0
6923 04:47:15.205601 CA_PREDIV_EN = 0
6924 04:47:15.209442 PH8_DLY = 12
6925 04:47:15.212465 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6926 04:47:15.215652 DQ_AAMCK_DIV = 4
6927 04:47:15.219378 CA_AAMCK_DIV = 4
6928 04:47:15.219906 CA_ADMCK_DIV = 4
6929 04:47:15.222890 DQ_TRACK_CA_EN = 0
6930 04:47:15.225848 CA_PICK = 1600
6931 04:47:15.229487 CA_MCKIO = 1600
6932 04:47:15.232932 MCKIO_SEMI = 0
6933 04:47:15.236411 PLL_FREQ = 3068
6934 04:47:15.240553 DQ_UI_PI_RATIO = 32
6935 04:47:15.241134 CA_UI_PI_RATIO = 0
6936 04:47:15.242640 ===================================
6937 04:47:15.245402 ===================================
6938 04:47:15.249085 memory_type:LPDDR4
6939 04:47:15.252873 GP_NUM : 10
6940 04:47:15.253407 SRAM_EN : 1
6941 04:47:15.255800 MD32_EN : 0
6942 04:47:15.259422 ===================================
6943 04:47:15.262368 [ANA_INIT] >>>>>>>>>>>>>>
6944 04:47:15.265542 <<<<<< [CONFIGURE PHASE]: ANA_TX
6945 04:47:15.269724 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6946 04:47:15.271996 ===================================
6947 04:47:15.272518 data_rate = 3200,PCW = 0X7600
6948 04:47:15.275675 ===================================
6949 04:47:15.283397 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6950 04:47:15.285823 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6951 04:47:15.292218 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6952 04:47:15.295769 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6953 04:47:15.299342 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6954 04:47:15.301990 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6955 04:47:15.305690 [ANA_INIT] flow start
6956 04:47:15.309695 [ANA_INIT] PLL >>>>>>>>
6957 04:47:15.310116 [ANA_INIT] PLL <<<<<<<<
6958 04:47:15.311619 [ANA_INIT] MIDPI >>>>>>>>
6959 04:47:15.315157 [ANA_INIT] MIDPI <<<<<<<<
6960 04:47:15.315578 [ANA_INIT] DLL >>>>>>>>
6961 04:47:15.319268 [ANA_INIT] DLL <<<<<<<<
6962 04:47:15.322120 [ANA_INIT] flow end
6963 04:47:15.325170 ============ LP4 DIFF to SE enter ============
6964 04:47:15.329476 ============ LP4 DIFF to SE exit ============
6965 04:47:15.331807 [ANA_INIT] <<<<<<<<<<<<<
6966 04:47:15.335646 [Flow] Enable top DCM control >>>>>
6967 04:47:15.338396 [Flow] Enable top DCM control <<<<<
6968 04:47:15.341946 Enable DLL master slave shuffle
6969 04:47:15.345104 ==============================================================
6970 04:47:15.348880 Gating Mode config
6971 04:47:15.355163 ==============================================================
6972 04:47:15.355691 Config description:
6973 04:47:15.365161 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6974 04:47:15.371326 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6975 04:47:15.378432 SELPH_MODE 0: By rank 1: By Phase
6976 04:47:15.381291 ==============================================================
6977 04:47:15.385253 GAT_TRACK_EN = 1
6978 04:47:15.388469 RX_GATING_MODE = 2
6979 04:47:15.392288 RX_GATING_TRACK_MODE = 2
6980 04:47:15.395720 SELPH_MODE = 1
6981 04:47:15.397933 PICG_EARLY_EN = 1
6982 04:47:15.400998 VALID_LAT_VALUE = 1
6983 04:47:15.404512 ==============================================================
6984 04:47:15.408096 Enter into Gating configuration >>>>
6985 04:47:15.411600 Exit from Gating configuration <<<<
6986 04:47:15.414161 Enter into DVFS_PRE_config >>>>>
6987 04:47:15.427703 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6988 04:47:15.431579 Exit from DVFS_PRE_config <<<<<
6989 04:47:15.435328 Enter into PICG configuration >>>>
6990 04:47:15.435888 Exit from PICG configuration <<<<
6991 04:47:15.437882 [RX_INPUT] configuration >>>>>
6992 04:47:15.442097 [RX_INPUT] configuration <<<<<
6993 04:47:15.447745 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6994 04:47:15.451175 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6995 04:47:15.457670 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6996 04:47:15.464285 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6997 04:47:15.470861 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6998 04:47:15.478038 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6999 04:47:15.480597 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7000 04:47:15.483946 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7001 04:47:15.490411 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7002 04:47:15.494742 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7003 04:47:15.497434 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7004 04:47:15.500512 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7005 04:47:15.504043 ===================================
7006 04:47:15.507421 LPDDR4 DRAM CONFIGURATION
7007 04:47:15.510070 ===================================
7008 04:47:15.513826 EX_ROW_EN[0] = 0x0
7009 04:47:15.514375 EX_ROW_EN[1] = 0x0
7010 04:47:15.517292 LP4Y_EN = 0x0
7011 04:47:15.517917 WORK_FSP = 0x1
7012 04:47:15.519871 WL = 0x5
7013 04:47:15.520281 RL = 0x5
7014 04:47:15.524009 BL = 0x2
7015 04:47:15.524433 RPST = 0x0
7016 04:47:15.526724 RD_PRE = 0x0
7017 04:47:15.530110 WR_PRE = 0x1
7018 04:47:15.530621 WR_PST = 0x1
7019 04:47:15.533692 DBI_WR = 0x0
7020 04:47:15.534111 DBI_RD = 0x0
7021 04:47:15.537164 OTF = 0x1
7022 04:47:15.540168 ===================================
7023 04:47:15.543698 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7024 04:47:15.546622 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7025 04:47:15.549845 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7026 04:47:15.554621 ===================================
7027 04:47:15.557127 LPDDR4 DRAM CONFIGURATION
7028 04:47:15.559888 ===================================
7029 04:47:15.563355 EX_ROW_EN[0] = 0x10
7030 04:47:15.563871 EX_ROW_EN[1] = 0x0
7031 04:47:15.566062 LP4Y_EN = 0x0
7032 04:47:15.566484 WORK_FSP = 0x1
7033 04:47:15.570353 WL = 0x5
7034 04:47:15.570914 RL = 0x5
7035 04:47:15.573281 BL = 0x2
7036 04:47:15.573798 RPST = 0x0
7037 04:47:15.576385 RD_PRE = 0x0
7038 04:47:15.580030 WR_PRE = 0x1
7039 04:47:15.580546 WR_PST = 0x1
7040 04:47:15.583154 DBI_WR = 0x0
7041 04:47:15.583666 DBI_RD = 0x0
7042 04:47:15.586272 OTF = 0x1
7043 04:47:15.590194 ===================================
7044 04:47:15.593061 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7045 04:47:15.596750 ==
7046 04:47:15.599156 Dram Type= 6, Freq= 0, CH_0, rank 0
7047 04:47:15.602807 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7048 04:47:15.603240 ==
7049 04:47:15.606312 [Duty_Offset_Calibration]
7050 04:47:15.606732 B0:0 B1:2 CA:1
7051 04:47:15.607066
7052 04:47:15.609071 [DutyScan_Calibration_Flow] k_type=0
7053 04:47:15.619537
7054 04:47:15.620105 ==CLK 0==
7055 04:47:15.623454 Final CLK duty delay cell = 0
7056 04:47:15.626134 [0] MAX Duty = 5156%(X100), DQS PI = 20
7057 04:47:15.630191 [0] MIN Duty = 4938%(X100), DQS PI = 54
7058 04:47:15.633149 [0] AVG Duty = 5047%(X100)
7059 04:47:15.633572
7060 04:47:15.635892 CH0 CLK Duty spec in!! Max-Min= 218%
7061 04:47:15.639189 [DutyScan_Calibration_Flow] ====Done====
7062 04:47:15.639703
7063 04:47:15.642575 [DutyScan_Calibration_Flow] k_type=1
7064 04:47:15.659598
7065 04:47:15.660150 ==DQS 0 ==
7066 04:47:15.663075 Final DQS duty delay cell = 0
7067 04:47:15.666309 [0] MAX Duty = 5125%(X100), DQS PI = 0
7068 04:47:15.669218 [0] MIN Duty = 5031%(X100), DQS PI = 8
7069 04:47:15.669777 [0] AVG Duty = 5078%(X100)
7070 04:47:15.672813
7071 04:47:15.673372 ==DQS 1 ==
7072 04:47:15.675999 Final DQS duty delay cell = 0
7073 04:47:15.679419 [0] MAX Duty = 5031%(X100), DQS PI = 4
7074 04:47:15.681952 [0] MIN Duty = 4876%(X100), DQS PI = 16
7075 04:47:15.686068 [0] AVG Duty = 4953%(X100)
7076 04:47:15.686660
7077 04:47:15.688785 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7078 04:47:15.689257
7079 04:47:15.692190 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7080 04:47:15.696569 [DutyScan_Calibration_Flow] ====Done====
7081 04:47:15.697086
7082 04:47:15.699028 [DutyScan_Calibration_Flow] k_type=3
7083 04:47:15.716984
7084 04:47:15.717530 ==DQM 0 ==
7085 04:47:15.719747 Final DQM duty delay cell = 0
7086 04:47:15.723475 [0] MAX Duty = 5187%(X100), DQS PI = 24
7087 04:47:15.726165 [0] MIN Duty = 4907%(X100), DQS PI = 56
7088 04:47:15.731122 [0] AVG Duty = 5047%(X100)
7089 04:47:15.731676
7090 04:47:15.732045 ==DQM 1 ==
7091 04:47:15.732805 Final DQM duty delay cell = 0
7092 04:47:15.737167 [0] MAX Duty = 5031%(X100), DQS PI = 52
7093 04:47:15.739625 [0] MIN Duty = 4782%(X100), DQS PI = 14
7094 04:47:15.742748 [0] AVG Duty = 4906%(X100)
7095 04:47:15.743213
7096 04:47:15.746132 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7097 04:47:15.746767
7098 04:47:15.749448 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7099 04:47:15.753357 [DutyScan_Calibration_Flow] ====Done====
7100 04:47:15.753916
7101 04:47:15.757241 [DutyScan_Calibration_Flow] k_type=2
7102 04:47:15.772979
7103 04:47:15.773531 ==DQ 0 ==
7104 04:47:15.776550 Final DQ duty delay cell = 0
7105 04:47:15.779499 [0] MAX Duty = 5218%(X100), DQS PI = 18
7106 04:47:15.782994 [0] MIN Duty = 4938%(X100), DQS PI = 56
7107 04:47:15.785660 [0] AVG Duty = 5078%(X100)
7108 04:47:15.786128
7109 04:47:15.786496 ==DQ 1 ==
7110 04:47:15.788783 Final DQ duty delay cell = -4
7111 04:47:15.793015 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7112 04:47:15.796199 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7113 04:47:15.799068 [-4] AVG Duty = 4953%(X100)
7114 04:47:15.799536
7115 04:47:15.802444 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7116 04:47:15.802913
7117 04:47:15.805610 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7118 04:47:15.809269 [DutyScan_Calibration_Flow] ====Done====
7119 04:47:15.809984 ==
7120 04:47:15.812354 Dram Type= 6, Freq= 0, CH_1, rank 0
7121 04:47:15.815187 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7122 04:47:15.815656 ==
7123 04:47:15.819489 [Duty_Offset_Calibration]
7124 04:47:15.820089 B0:0 B1:5 CA:-5
7125 04:47:15.820465
7126 04:47:15.822755 [DutyScan_Calibration_Flow] k_type=0
7127 04:47:15.833708
7128 04:47:15.834266 ==CLK 0==
7129 04:47:15.837116 Final CLK duty delay cell = 0
7130 04:47:15.841266 [0] MAX Duty = 5156%(X100), DQS PI = 20
7131 04:47:15.843975 [0] MIN Duty = 4906%(X100), DQS PI = 50
7132 04:47:15.844538 [0] AVG Duty = 5031%(X100)
7133 04:47:15.846839
7134 04:47:15.849572 CH1 CLK Duty spec in!! Max-Min= 250%
7135 04:47:15.853752 [DutyScan_Calibration_Flow] ====Done====
7136 04:47:15.854306
7137 04:47:15.856420 [DutyScan_Calibration_Flow] k_type=1
7138 04:47:15.872689
7139 04:47:15.873140 ==DQS 0 ==
7140 04:47:15.875468 Final DQS duty delay cell = 0
7141 04:47:15.879943 [0] MAX Duty = 5156%(X100), DQS PI = 18
7142 04:47:15.881911 [0] MIN Duty = 4844%(X100), DQS PI = 44
7143 04:47:15.885218 [0] AVG Duty = 5000%(X100)
7144 04:47:15.885640
7145 04:47:15.885972 ==DQS 1 ==
7146 04:47:15.888601 Final DQS duty delay cell = -4
7147 04:47:15.892686 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7148 04:47:15.895329 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7149 04:47:15.898528 [-4] AVG Duty = 4922%(X100)
7150 04:47:15.898993
7151 04:47:15.901621 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7152 04:47:15.902087
7153 04:47:15.905330 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7154 04:47:15.908425 [DutyScan_Calibration_Flow] ====Done====
7155 04:47:15.909058
7156 04:47:15.911622 [DutyScan_Calibration_Flow] k_type=3
7157 04:47:15.927701
7158 04:47:15.928284 ==DQM 0 ==
7159 04:47:15.932598 Final DQM duty delay cell = -4
7160 04:47:15.934780 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7161 04:47:15.938373 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7162 04:47:15.941114 [-4] AVG Duty = 4922%(X100)
7163 04:47:15.941671
7164 04:47:15.942039 ==DQM 1 ==
7165 04:47:15.944393 Final DQM duty delay cell = -4
7166 04:47:15.947909 [-4] MAX Duty = 5062%(X100), DQS PI = 14
7167 04:47:15.951857 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7168 04:47:15.954617 [-4] AVG Duty = 4984%(X100)
7169 04:47:15.955221
7170 04:47:15.957333 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7171 04:47:15.957797
7172 04:47:15.960916 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7173 04:47:15.964226 [DutyScan_Calibration_Flow] ====Done====
7174 04:47:15.964827
7175 04:47:15.968226 [DutyScan_Calibration_Flow] k_type=2
7176 04:47:15.985829
7177 04:47:15.986380 ==DQ 0 ==
7178 04:47:15.988446 Final DQ duty delay cell = 0
7179 04:47:15.992148 [0] MAX Duty = 5093%(X100), DQS PI = 18
7180 04:47:15.995581 [0] MIN Duty = 4938%(X100), DQS PI = 46
7181 04:47:15.996050 [0] AVG Duty = 5015%(X100)
7182 04:47:15.999125
7183 04:47:15.999556 ==DQ 1 ==
7184 04:47:16.002499 Final DQ duty delay cell = 0
7185 04:47:16.005265 [0] MAX Duty = 5031%(X100), DQS PI = 4
7186 04:47:16.008377 [0] MIN Duty = 4875%(X100), DQS PI = 28
7187 04:47:16.008874 [0] AVG Duty = 4953%(X100)
7188 04:47:16.009248
7189 04:47:16.015646 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7190 04:47:16.016219
7191 04:47:16.018343 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7192 04:47:16.021830 [DutyScan_Calibration_Flow] ====Done====
7193 04:47:16.026142 nWR fixed to 30
7194 04:47:16.026612 [ModeRegInit_LP4] CH0 RK0
7195 04:47:16.028302 [ModeRegInit_LP4] CH0 RK1
7196 04:47:16.032355 [ModeRegInit_LP4] CH1 RK0
7197 04:47:16.035232 [ModeRegInit_LP4] CH1 RK1
7198 04:47:16.035696 match AC timing 4
7199 04:47:16.041581 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7200 04:47:16.044825 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7201 04:47:16.048272 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7202 04:47:16.055346 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7203 04:47:16.059142 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7204 04:47:16.059698 [MiockJmeterHQA]
7205 04:47:16.060070
7206 04:47:16.062561 [DramcMiockJmeter] u1RxGatingPI = 0
7207 04:47:16.065342 0 : 4253, 4026
7208 04:47:16.065814 4 : 4253, 4026
7209 04:47:16.069351 8 : 4252, 4027
7210 04:47:16.069923 12 : 4363, 4137
7211 04:47:16.070305 16 : 4363, 4138
7212 04:47:16.071327 20 : 4252, 4027
7213 04:47:16.071813 24 : 4252, 4027
7214 04:47:16.074650 28 : 4253, 4026
7215 04:47:16.075241 32 : 4363, 4138
7216 04:47:16.078536 36 : 4252, 4027
7217 04:47:16.079131 40 : 4363, 4137
7218 04:47:16.081927 44 : 4253, 4027
7219 04:47:16.082517 48 : 4253, 4027
7220 04:47:16.083021 52 : 4250, 4027
7221 04:47:16.084483 56 : 4252, 4029
7222 04:47:16.085008 60 : 4360, 4138
7223 04:47:16.089112 64 : 4250, 4027
7224 04:47:16.089600 68 : 4361, 4137
7225 04:47:16.091477 72 : 4250, 4027
7226 04:47:16.092069 76 : 4250, 4026
7227 04:47:16.094433 80 : 4250, 4027
7228 04:47:16.094918 84 : 4361, 4138
7229 04:47:16.095411 88 : 4250, 4026
7230 04:47:16.097984 92 : 4360, 4138
7231 04:47:16.098471 96 : 4250, 4027
7232 04:47:16.101124 100 : 4250, 2149
7233 04:47:16.101718 104 : 4360, 0
7234 04:47:16.104343 108 : 4252, 0
7235 04:47:16.104888 112 : 4253, 0
7236 04:47:16.105386 116 : 4250, 0
7237 04:47:16.108100 120 : 4250, 0
7238 04:47:16.108589 124 : 4253, 0
7239 04:47:16.110746 128 : 4250, 0
7240 04:47:16.111466 132 : 4250, 0
7241 04:47:16.111972 136 : 4252, 0
7242 04:47:16.114439 140 : 4363, 0
7243 04:47:16.114928 144 : 4250, 0
7244 04:47:16.115419 148 : 4250, 0
7245 04:47:16.117344 152 : 4361, 0
7246 04:47:16.117830 156 : 4361, 0
7247 04:47:16.120825 160 : 4363, 0
7248 04:47:16.121315 164 : 4250, 0
7249 04:47:16.121802 168 : 4250, 0
7250 04:47:16.124291 172 : 4363, 0
7251 04:47:16.124762 176 : 4250, 0
7252 04:47:16.128181 180 : 4250, 0
7253 04:47:16.128763 184 : 4250, 0
7254 04:47:16.129225 188 : 4253, 0
7255 04:47:16.130703 192 : 4249, 0
7256 04:47:16.131146 196 : 4250, 0
7257 04:47:16.134322 200 : 4252, 0
7258 04:47:16.134874 204 : 4360, 0
7259 04:47:16.135336 208 : 4360, 0
7260 04:47:16.137325 212 : 4363, 0
7261 04:47:16.137747 216 : 4250, 0
7262 04:47:16.140658 220 : 4360, 731
7263 04:47:16.141271 224 : 4250, 4021
7264 04:47:16.144139 228 : 4360, 4137
7265 04:47:16.144818 232 : 4252, 4029
7266 04:47:16.145232 236 : 4250, 4027
7267 04:47:16.147239 240 : 4250, 4027
7268 04:47:16.147693 244 : 4252, 4029
7269 04:47:16.150453 248 : 4250, 4027
7270 04:47:16.150891 252 : 4250, 4027
7271 04:47:16.154556 256 : 4250, 4027
7272 04:47:16.155099 260 : 4252, 4029
7273 04:47:16.158270 264 : 4250, 4027
7274 04:47:16.158791 268 : 4360, 4138
7275 04:47:16.161154 272 : 4361, 4138
7276 04:47:16.161679 276 : 4250, 4027
7277 04:47:16.164921 280 : 4363, 4139
7278 04:47:16.165441 284 : 4360, 4138
7279 04:47:16.167749 288 : 4250, 4027
7280 04:47:16.168272 292 : 4249, 4027
7281 04:47:16.168617 296 : 4252, 4029
7282 04:47:16.171262 300 : 4250, 4027
7283 04:47:16.171689 304 : 4250, 4027
7284 04:47:16.174039 308 : 4250, 4027
7285 04:47:16.174466 312 : 4252, 4029
7286 04:47:16.177254 316 : 4250, 4026
7287 04:47:16.177679 320 : 4360, 4138
7288 04:47:16.181426 324 : 4361, 4138
7289 04:47:16.181879 328 : 4250, 4027
7290 04:47:16.183891 332 : 4363, 4140
7291 04:47:16.184632 336 : 4361, 3888
7292 04:47:16.187281 340 : 4250, 1849
7293 04:47:16.187704
7294 04:47:16.188036 MIOCK jitter meter ch=0
7295 04:47:16.188404
7296 04:47:16.190696 1T = (340-104) = 236 dly cells
7297 04:47:16.197882 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7298 04:47:16.198397 ==
7299 04:47:16.200367 Dram Type= 6, Freq= 0, CH_0, rank 0
7300 04:47:16.204223 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7301 04:47:16.204591 ==
7302 04:47:16.210565 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7303 04:47:16.213764 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7304 04:47:16.217209 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7305 04:47:16.224663 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7306 04:47:16.232345 [CA 0] Center 41 (11~72) winsize 62
7307 04:47:16.236270 [CA 1] Center 41 (11~72) winsize 62
7308 04:47:16.239943 [CA 2] Center 37 (7~67) winsize 61
7309 04:47:16.242830 [CA 3] Center 37 (7~67) winsize 61
7310 04:47:16.246812 [CA 4] Center 35 (5~66) winsize 62
7311 04:47:16.248846 [CA 5] Center 35 (5~65) winsize 61
7312 04:47:16.249310
7313 04:47:16.252583 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7314 04:47:16.253231
7315 04:47:16.255947 [CATrainingPosCal] consider 1 rank data
7316 04:47:16.259586 u2DelayCellTimex100 = 275/100 ps
7317 04:47:16.262400 CA0 delay=41 (11~72),Diff = 6 PI (21 cell)
7318 04:47:16.268918 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7319 04:47:16.272160 CA2 delay=37 (7~67),Diff = 2 PI (7 cell)
7320 04:47:16.275933 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7321 04:47:16.279219 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7322 04:47:16.282114 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7323 04:47:16.282583
7324 04:47:16.285730 CA PerBit enable=1, Macro0, CA PI delay=35
7325 04:47:16.286305
7326 04:47:16.289279 [CBTSetCACLKResult] CA Dly = 35
7327 04:47:16.292482 CS Dly: 11 (0~42)
7328 04:47:16.295526 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7329 04:47:16.299495 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7330 04:47:16.299963 ==
7331 04:47:16.302377 Dram Type= 6, Freq= 0, CH_0, rank 1
7332 04:47:16.305854 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7333 04:47:16.309171 ==
7334 04:47:16.311954 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7335 04:47:16.315351 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7336 04:47:16.322491 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7337 04:47:16.328525 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7338 04:47:16.336795 [CA 0] Center 42 (12~73) winsize 62
7339 04:47:16.339719 [CA 1] Center 41 (11~72) winsize 62
7340 04:47:16.341486 [CA 2] Center 38 (8~68) winsize 61
7341 04:47:16.346096 [CA 3] Center 37 (7~67) winsize 61
7342 04:47:16.348903 [CA 4] Center 35 (5~65) winsize 61
7343 04:47:16.351760 [CA 5] Center 35 (5~66) winsize 62
7344 04:47:16.352314
7345 04:47:16.354955 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7346 04:47:16.355508
7347 04:47:16.358519 [CATrainingPosCal] consider 2 rank data
7348 04:47:16.362349 u2DelayCellTimex100 = 275/100 ps
7349 04:47:16.368583 CA0 delay=42 (12~72),Diff = 7 PI (24 cell)
7350 04:47:16.372187 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7351 04:47:16.375707 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7352 04:47:16.378778 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7353 04:47:16.381613 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
7354 04:47:16.384972 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7355 04:47:16.385529
7356 04:47:16.388057 CA PerBit enable=1, Macro0, CA PI delay=35
7357 04:47:16.388520
7358 04:47:16.392294 [CBTSetCACLKResult] CA Dly = 35
7359 04:47:16.395435 CS Dly: 11 (0~43)
7360 04:47:16.399240 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7361 04:47:16.401250 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7362 04:47:16.401698
7363 04:47:16.404812 ----->DramcWriteLeveling(PI) begin...
7364 04:47:16.405280 ==
7365 04:47:16.408622 Dram Type= 6, Freq= 0, CH_0, rank 0
7366 04:47:16.414670 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7367 04:47:16.415161 ==
7368 04:47:16.417815 Write leveling (Byte 0): 29 => 29
7369 04:47:16.421102 Write leveling (Byte 1): 26 => 26
7370 04:47:16.421651 DramcWriteLeveling(PI) end<-----
7371 04:47:16.422015
7372 04:47:16.424821 ==
7373 04:47:16.427918 Dram Type= 6, Freq= 0, CH_0, rank 0
7374 04:47:16.430959 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7375 04:47:16.431413 ==
7376 04:47:16.434213 [Gating] SW mode calibration
7377 04:47:16.440801 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7378 04:47:16.443865 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7379 04:47:16.451317 0 12 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7380 04:47:16.454541 0 12 4 | B1->B0 | 2626 3434 | 0 0 | (0 0) (0 0)
7381 04:47:16.457866 0 12 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7382 04:47:16.464230 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7383 04:47:16.467498 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7384 04:47:16.470705 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7385 04:47:16.478372 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7386 04:47:16.480701 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7387 04:47:16.484318 0 13 0 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
7388 04:47:16.490707 0 13 4 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
7389 04:47:16.493639 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
7390 04:47:16.497723 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7391 04:47:16.503705 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7392 04:47:16.507604 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7393 04:47:16.510270 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7394 04:47:16.517047 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7395 04:47:16.520632 0 14 0 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7396 04:47:16.523831 0 14 4 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
7397 04:47:16.529787 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7398 04:47:16.533593 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7399 04:47:16.537709 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7400 04:47:16.543848 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7401 04:47:16.546727 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7402 04:47:16.550072 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7403 04:47:16.556749 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7404 04:47:16.560963 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7405 04:47:16.563069 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7406 04:47:16.570418 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7407 04:47:16.573468 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7408 04:47:16.576866 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7409 04:47:16.584371 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7410 04:47:16.586578 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7411 04:47:16.589711 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7412 04:47:16.596864 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7413 04:47:16.599760 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7414 04:47:16.603004 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7415 04:47:16.609331 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7416 04:47:16.613554 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7417 04:47:16.616372 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7418 04:47:16.622728 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7419 04:47:16.627311 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7420 04:47:16.629250 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7421 04:47:16.632686 Total UI for P1: 0, mck2ui 16
7422 04:47:16.636032 best dqsien dly found for B0: ( 1, 0, 30)
7423 04:47:16.639471 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7424 04:47:16.645992 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7425 04:47:16.649691 Total UI for P1: 0, mck2ui 16
7426 04:47:16.653205 best dqsien dly found for B1: ( 1, 1, 6)
7427 04:47:16.655929 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7428 04:47:16.659811 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7429 04:47:16.660388
7430 04:47:16.662556 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7431 04:47:16.666117 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7432 04:47:16.669007 [Gating] SW calibration Done
7433 04:47:16.669467 ==
7434 04:47:16.672847 Dram Type= 6, Freq= 0, CH_0, rank 0
7435 04:47:16.675964 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7436 04:47:16.676534 ==
7437 04:47:16.679827 RX Vref Scan: 0
7438 04:47:16.680387
7439 04:47:16.682550 RX Vref 0 -> 0, step: 1
7440 04:47:16.683114
7441 04:47:16.683482 RX Delay 0 -> 252, step: 8
7442 04:47:16.688859 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7443 04:47:16.692806 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7444 04:47:16.696010 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7445 04:47:16.699165 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7446 04:47:16.702813 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7447 04:47:16.705846 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
7448 04:47:16.712862 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7449 04:47:16.715494 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
7450 04:47:16.718947 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7451 04:47:16.722061 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7452 04:47:16.729663 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7453 04:47:16.731981 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7454 04:47:16.735439 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7455 04:47:16.738502 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7456 04:47:16.742257 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7457 04:47:16.748648 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7458 04:47:16.749246 ==
7459 04:47:16.753395 Dram Type= 6, Freq= 0, CH_0, rank 0
7460 04:47:16.754920 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7461 04:47:16.755389 ==
7462 04:47:16.755760 DQS Delay:
7463 04:47:16.758492 DQS0 = 0, DQS1 = 0
7464 04:47:16.759064 DQM Delay:
7465 04:47:16.761893 DQM0 = 129, DQM1 = 124
7466 04:47:16.762457 DQ Delay:
7467 04:47:16.765448 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7468 04:47:16.768580 DQ4 =135, DQ5 =115, DQ6 =139, DQ7 =135
7469 04:47:16.771258 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
7470 04:47:16.777957 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7471 04:47:16.778523
7472 04:47:16.778890
7473 04:47:16.779233 ==
7474 04:47:16.782072 Dram Type= 6, Freq= 0, CH_0, rank 0
7475 04:47:16.784820 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7476 04:47:16.785388 ==
7477 04:47:16.785756
7478 04:47:16.786091
7479 04:47:16.787835 TX Vref Scan disable
7480 04:47:16.788297 == TX Byte 0 ==
7481 04:47:16.794872 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7482 04:47:16.798802 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7483 04:47:16.799376 == TX Byte 1 ==
7484 04:47:16.804493 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7485 04:47:16.808426 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7486 04:47:16.809059 ==
7487 04:47:16.811287 Dram Type= 6, Freq= 0, CH_0, rank 0
7488 04:47:16.814536 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7489 04:47:16.815011 ==
7490 04:47:16.828766
7491 04:47:16.832005 TX Vref early break, caculate TX vref
7492 04:47:16.834903 TX Vref=16, minBit 8, minWin=22, winSum=374
7493 04:47:16.838061 TX Vref=18, minBit 8, minWin=22, winSum=381
7494 04:47:16.842025 TX Vref=20, minBit 8, minWin=23, winSum=390
7495 04:47:16.844858 TX Vref=22, minBit 7, minWin=24, winSum=397
7496 04:47:16.848226 TX Vref=24, minBit 11, minWin=23, winSum=400
7497 04:47:16.854860 TX Vref=26, minBit 7, minWin=25, winSum=411
7498 04:47:16.858265 TX Vref=28, minBit 8, minWin=24, winSum=415
7499 04:47:16.861541 TX Vref=30, minBit 0, minWin=25, winSum=409
7500 04:47:16.864588 TX Vref=32, minBit 6, minWin=24, winSum=398
7501 04:47:16.868823 TX Vref=34, minBit 3, minWin=23, winSum=391
7502 04:47:16.875086 [TxChooseVref] Worse bit 7, Min win 25, Win sum 411, Final Vref 26
7503 04:47:16.875673
7504 04:47:16.877822 Final TX Range 0 Vref 26
7505 04:47:16.878379
7506 04:47:16.878751 ==
7507 04:47:16.881277 Dram Type= 6, Freq= 0, CH_0, rank 0
7508 04:47:16.884377 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7509 04:47:16.884995 ==
7510 04:47:16.885545
7511 04:47:16.886012
7512 04:47:16.887618 TX Vref Scan disable
7513 04:47:16.894648 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7514 04:47:16.895218 == TX Byte 0 ==
7515 04:47:16.899603 u2DelayCellOfst[0]=10 cells (3 PI)
7516 04:47:16.900652 u2DelayCellOfst[1]=17 cells (5 PI)
7517 04:47:16.904574 u2DelayCellOfst[2]=14 cells (4 PI)
7518 04:47:16.907621 u2DelayCellOfst[3]=10 cells (3 PI)
7519 04:47:16.910901 u2DelayCellOfst[4]=7 cells (2 PI)
7520 04:47:16.914681 u2DelayCellOfst[5]=0 cells (0 PI)
7521 04:47:16.917488 u2DelayCellOfst[6]=17 cells (5 PI)
7522 04:47:16.921467 u2DelayCellOfst[7]=17 cells (5 PI)
7523 04:47:16.924863 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7524 04:47:16.928198 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7525 04:47:16.931273 == TX Byte 1 ==
7526 04:47:16.934551 u2DelayCellOfst[8]=3 cells (1 PI)
7527 04:47:16.935011 u2DelayCellOfst[9]=0 cells (0 PI)
7528 04:47:16.937224 u2DelayCellOfst[10]=10 cells (3 PI)
7529 04:47:16.940528 u2DelayCellOfst[11]=7 cells (2 PI)
7530 04:47:16.944581 u2DelayCellOfst[12]=17 cells (5 PI)
7531 04:47:16.947416 u2DelayCellOfst[13]=17 cells (5 PI)
7532 04:47:16.950377 u2DelayCellOfst[14]=17 cells (5 PI)
7533 04:47:16.953917 u2DelayCellOfst[15]=14 cells (4 PI)
7534 04:47:16.961118 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7535 04:47:16.963773 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7536 04:47:16.964327 DramC Write-DBI on
7537 04:47:16.964961 ==
7538 04:47:16.967496 Dram Type= 6, Freq= 0, CH_0, rank 0
7539 04:47:16.973624 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7540 04:47:16.974182 ==
7541 04:47:16.974551
7542 04:47:16.974885
7543 04:47:16.975206 TX Vref Scan disable
7544 04:47:16.978250 == TX Byte 0 ==
7545 04:47:16.980987 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7546 04:47:16.985378 == TX Byte 1 ==
7547 04:47:16.987815 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7548 04:47:16.991009 DramC Write-DBI off
7549 04:47:16.991469
7550 04:47:16.991832 [DATLAT]
7551 04:47:16.992170 Freq=1600, CH0 RK0
7552 04:47:16.992499
7553 04:47:16.994394 DATLAT Default: 0xf
7554 04:47:16.997503 0, 0xFFFF, sum = 0
7555 04:47:16.997973 1, 0xFFFF, sum = 0
7556 04:47:17.001625 2, 0xFFFF, sum = 0
7557 04:47:17.002107 3, 0xFFFF, sum = 0
7558 04:47:17.004170 4, 0xFFFF, sum = 0
7559 04:47:17.004787 5, 0xFFFF, sum = 0
7560 04:47:17.007845 6, 0xFFFF, sum = 0
7561 04:47:17.008308 7, 0xFFFF, sum = 0
7562 04:47:17.011345 8, 0xFFFF, sum = 0
7563 04:47:17.011907 9, 0xFFFF, sum = 0
7564 04:47:17.014612 10, 0xFFFF, sum = 0
7565 04:47:17.015178 11, 0xFFFF, sum = 0
7566 04:47:17.017694 12, 0xFFF, sum = 0
7567 04:47:17.018166 13, 0x0, sum = 1
7568 04:47:17.020898 14, 0x0, sum = 2
7569 04:47:17.021457 15, 0x0, sum = 3
7570 04:47:17.024545 16, 0x0, sum = 4
7571 04:47:17.025169 best_step = 14
7572 04:47:17.025537
7573 04:47:17.025928 ==
7574 04:47:17.027397 Dram Type= 6, Freq= 0, CH_0, rank 0
7575 04:47:17.030827 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7576 04:47:17.034391 ==
7577 04:47:17.034851 RX Vref Scan: 1
7578 04:47:17.035219
7579 04:47:17.037645 Set Vref Range= 24 -> 127
7580 04:47:17.038107
7581 04:47:17.040509 RX Vref 24 -> 127, step: 1
7582 04:47:17.041031
7583 04:47:17.041400 RX Delay 11 -> 252, step: 4
7584 04:47:17.041738
7585 04:47:17.043938 Set Vref, RX VrefLevel [Byte0]: 24
7586 04:47:17.047075 [Byte1]: 24
7587 04:47:17.051205
7588 04:47:17.051758 Set Vref, RX VrefLevel [Byte0]: 25
7589 04:47:17.055419 [Byte1]: 25
7590 04:47:17.059095
7591 04:47:17.059650 Set Vref, RX VrefLevel [Byte0]: 26
7592 04:47:17.062150 [Byte1]: 26
7593 04:47:17.066624
7594 04:47:17.067186 Set Vref, RX VrefLevel [Byte0]: 27
7595 04:47:17.070127 [Byte1]: 27
7596 04:47:17.073977
7597 04:47:17.074432 Set Vref, RX VrefLevel [Byte0]: 28
7598 04:47:17.077340 [Byte1]: 28
7599 04:47:17.081418
7600 04:47:17.081987 Set Vref, RX VrefLevel [Byte0]: 29
7601 04:47:17.084997 [Byte1]: 29
7602 04:47:17.089120
7603 04:47:17.089690 Set Vref, RX VrefLevel [Byte0]: 30
7604 04:47:17.092790 [Byte1]: 30
7605 04:47:17.096987
7606 04:47:17.097545 Set Vref, RX VrefLevel [Byte0]: 31
7607 04:47:17.100400 [Byte1]: 31
7608 04:47:17.105075
7609 04:47:17.105635 Set Vref, RX VrefLevel [Byte0]: 32
7610 04:47:17.107639 [Byte1]: 32
7611 04:47:17.112331
7612 04:47:17.112918 Set Vref, RX VrefLevel [Byte0]: 33
7613 04:47:17.115508 [Byte1]: 33
7614 04:47:17.119146
7615 04:47:17.119604 Set Vref, RX VrefLevel [Byte0]: 34
7616 04:47:17.122711 [Byte1]: 34
7617 04:47:17.127253
7618 04:47:17.127806 Set Vref, RX VrefLevel [Byte0]: 35
7619 04:47:17.130135 [Byte1]: 35
7620 04:47:17.134760
7621 04:47:17.135332 Set Vref, RX VrefLevel [Byte0]: 36
7622 04:47:17.137864 [Byte1]: 36
7623 04:47:17.143292
7624 04:47:17.143845 Set Vref, RX VrefLevel [Byte0]: 37
7625 04:47:17.146037 [Byte1]: 37
7626 04:47:17.150392
7627 04:47:17.154307 Set Vref, RX VrefLevel [Byte0]: 38
7628 04:47:17.154861 [Byte1]: 38
7629 04:47:17.157907
7630 04:47:17.158458 Set Vref, RX VrefLevel [Byte0]: 39
7631 04:47:17.160917 [Byte1]: 39
7632 04:47:17.165533
7633 04:47:17.166083 Set Vref, RX VrefLevel [Byte0]: 40
7634 04:47:17.168870 [Byte1]: 40
7635 04:47:17.173089
7636 04:47:17.173648 Set Vref, RX VrefLevel [Byte0]: 41
7637 04:47:17.176778 [Byte1]: 41
7638 04:47:17.180893
7639 04:47:17.181454 Set Vref, RX VrefLevel [Byte0]: 42
7640 04:47:17.183945 [Byte1]: 42
7641 04:47:17.188384
7642 04:47:17.188981 Set Vref, RX VrefLevel [Byte0]: 43
7643 04:47:17.192065 [Byte1]: 43
7644 04:47:17.195937
7645 04:47:17.196499 Set Vref, RX VrefLevel [Byte0]: 44
7646 04:47:17.198921 [Byte1]: 44
7647 04:47:17.203307
7648 04:47:17.203860 Set Vref, RX VrefLevel [Byte0]: 45
7649 04:47:17.207159 [Byte1]: 45
7650 04:47:17.210665
7651 04:47:17.211122 Set Vref, RX VrefLevel [Byte0]: 46
7652 04:47:17.214246 [Byte1]: 46
7653 04:47:17.218572
7654 04:47:17.219352 Set Vref, RX VrefLevel [Byte0]: 47
7655 04:47:17.222022 [Byte1]: 47
7656 04:47:17.226410
7657 04:47:17.226961 Set Vref, RX VrefLevel [Byte0]: 48
7658 04:47:17.229160 [Byte1]: 48
7659 04:47:17.233776
7660 04:47:17.234250 Set Vref, RX VrefLevel [Byte0]: 49
7661 04:47:17.237208 [Byte1]: 49
7662 04:47:17.241620
7663 04:47:17.242170 Set Vref, RX VrefLevel [Byte0]: 50
7664 04:47:17.244885 [Byte1]: 50
7665 04:47:17.249819
7666 04:47:17.250303 Set Vref, RX VrefLevel [Byte0]: 51
7667 04:47:17.252117 [Byte1]: 51
7668 04:47:17.256698
7669 04:47:17.257441 Set Vref, RX VrefLevel [Byte0]: 52
7670 04:47:17.260028 [Byte1]: 52
7671 04:47:17.264138
7672 04:47:17.264691 Set Vref, RX VrefLevel [Byte0]: 53
7673 04:47:17.268077 [Byte1]: 53
7674 04:47:17.271614
7675 04:47:17.272072 Set Vref, RX VrefLevel [Byte0]: 54
7676 04:47:17.275141 [Byte1]: 54
7677 04:47:17.280986
7678 04:47:17.281845 Set Vref, RX VrefLevel [Byte0]: 55
7679 04:47:17.282935 [Byte1]: 55
7680 04:47:17.287523
7681 04:47:17.288078 Set Vref, RX VrefLevel [Byte0]: 56
7682 04:47:17.291160 [Byte1]: 56
7683 04:47:17.294957
7684 04:47:17.295514 Set Vref, RX VrefLevel [Byte0]: 57
7685 04:47:17.298249 [Byte1]: 57
7686 04:47:17.301939
7687 04:47:17.302397 Set Vref, RX VrefLevel [Byte0]: 58
7688 04:47:17.305802 [Byte1]: 58
7689 04:47:17.309862
7690 04:47:17.310467 Set Vref, RX VrefLevel [Byte0]: 59
7691 04:47:17.313949 [Byte1]: 59
7692 04:47:17.318412
7693 04:47:17.318887 Set Vref, RX VrefLevel [Byte0]: 60
7694 04:47:17.320923 [Byte1]: 60
7695 04:47:17.324777
7696 04:47:17.325319 Set Vref, RX VrefLevel [Byte0]: 61
7697 04:47:17.328233 [Byte1]: 61
7698 04:47:17.332409
7699 04:47:17.333017 Set Vref, RX VrefLevel [Byte0]: 62
7700 04:47:17.336199 [Byte1]: 62
7701 04:47:17.341347
7702 04:47:17.341896 Set Vref, RX VrefLevel [Byte0]: 63
7703 04:47:17.344069 [Byte1]: 63
7704 04:47:17.348574
7705 04:47:17.351934 Set Vref, RX VrefLevel [Byte0]: 64
7706 04:47:17.354628 [Byte1]: 64
7707 04:47:17.355184
7708 04:47:17.358057 Set Vref, RX VrefLevel [Byte0]: 65
7709 04:47:17.361836 [Byte1]: 65
7710 04:47:17.362395
7711 04:47:17.364338 Set Vref, RX VrefLevel [Byte0]: 66
7712 04:47:17.368214 [Byte1]: 66
7713 04:47:17.368808
7714 04:47:17.371203 Set Vref, RX VrefLevel [Byte0]: 67
7715 04:47:17.374573 [Byte1]: 67
7716 04:47:17.378954
7717 04:47:17.379509 Set Vref, RX VrefLevel [Byte0]: 68
7718 04:47:17.382011 [Byte1]: 68
7719 04:47:17.387248
7720 04:47:17.387807 Set Vref, RX VrefLevel [Byte0]: 69
7721 04:47:17.389153 [Byte1]: 69
7722 04:47:17.393371
7723 04:47:17.393861 Set Vref, RX VrefLevel [Byte0]: 70
7724 04:47:17.397522 [Byte1]: 70
7725 04:47:17.401305
7726 04:47:17.401880 Final RX Vref Byte 0 = 54 to rank0
7727 04:47:17.404542 Final RX Vref Byte 1 = 56 to rank0
7728 04:47:17.407855 Final RX Vref Byte 0 = 54 to rank1
7729 04:47:17.410858 Final RX Vref Byte 1 = 56 to rank1==
7730 04:47:17.414873 Dram Type= 6, Freq= 0, CH_0, rank 0
7731 04:47:17.420529 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7732 04:47:17.421038 ==
7733 04:47:17.421408 DQS Delay:
7734 04:47:17.424224 DQS0 = 0, DQS1 = 0
7735 04:47:17.424686 DQM Delay:
7736 04:47:17.425120 DQM0 = 126, DQM1 = 120
7737 04:47:17.427697 DQ Delay:
7738 04:47:17.430878 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7739 04:47:17.434319 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7740 04:47:17.437631 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
7741 04:47:17.441040 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7742 04:47:17.441598
7743 04:47:17.441959
7744 04:47:17.442296
7745 04:47:17.444106 [DramC_TX_OE_Calibration] TA2
7746 04:47:17.447402 Original DQ_B0 (3 6) =30, OEN = 27
7747 04:47:17.450606 Original DQ_B1 (3 6) =30, OEN = 27
7748 04:47:17.454411 24, 0x0, End_B0=24 End_B1=24
7749 04:47:17.454976 25, 0x0, End_B0=25 End_B1=25
7750 04:47:17.457600 26, 0x0, End_B0=26 End_B1=26
7751 04:47:17.460598 27, 0x0, End_B0=27 End_B1=27
7752 04:47:17.464062 28, 0x0, End_B0=28 End_B1=28
7753 04:47:17.467473 29, 0x0, End_B0=29 End_B1=29
7754 04:47:17.468038 30, 0x0, End_B0=30 End_B1=30
7755 04:47:17.470848 31, 0x4141, End_B0=30 End_B1=30
7756 04:47:17.474314 Byte0 end_step=30 best_step=27
7757 04:47:17.476907 Byte1 end_step=30 best_step=27
7758 04:47:17.480482 Byte0 TX OE(2T, 0.5T) = (3, 3)
7759 04:47:17.484060 Byte1 TX OE(2T, 0.5T) = (3, 3)
7760 04:47:17.484617
7761 04:47:17.485024
7762 04:47:17.490918 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
7763 04:47:17.494022 CH0 RK0: MR19=303, MR18=1E1E
7764 04:47:17.500591 CH0_RK0: MR19=0x303, MR18=0x1E1E, DQSOSC=394, MR23=63, INC=23, DEC=15
7765 04:47:17.501164
7766 04:47:17.503457 ----->DramcWriteLeveling(PI) begin...
7767 04:47:17.503924 ==
7768 04:47:17.507300 Dram Type= 6, Freq= 0, CH_0, rank 1
7769 04:47:17.510205 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7770 04:47:17.510714 ==
7771 04:47:17.514024 Write leveling (Byte 0): 30 => 30
7772 04:47:17.517023 Write leveling (Byte 1): 26 => 26
7773 04:47:17.520109 DramcWriteLeveling(PI) end<-----
7774 04:47:17.520812
7775 04:47:17.521197 ==
7776 04:47:17.523779 Dram Type= 6, Freq= 0, CH_0, rank 1
7777 04:47:17.526661 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7778 04:47:17.527120 ==
7779 04:47:17.530359 [Gating] SW mode calibration
7780 04:47:17.536990 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7781 04:47:17.543223 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7782 04:47:17.546912 0 12 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
7783 04:47:17.553169 0 12 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
7784 04:47:17.557576 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7785 04:47:17.560573 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7786 04:47:17.566529 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7787 04:47:17.569592 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7788 04:47:17.573783 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7789 04:47:17.579682 0 12 28 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
7790 04:47:17.583165 0 13 0 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (1 0)
7791 04:47:17.586591 0 13 4 | B1->B0 | 3232 2323 | 0 0 | (0 1) (1 0)
7792 04:47:17.593821 0 13 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
7793 04:47:17.597138 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7794 04:47:17.599739 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7795 04:47:17.606338 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7796 04:47:17.609457 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7797 04:47:17.613200 0 13 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7798 04:47:17.619062 0 14 0 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7799 04:47:17.623109 0 14 4 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
7800 04:47:17.626421 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7801 04:47:17.633220 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7802 04:47:17.635742 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7803 04:47:17.639566 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7804 04:47:17.646456 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7805 04:47:17.649323 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7806 04:47:17.652485 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7807 04:47:17.659463 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7808 04:47:17.662473 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7809 04:47:17.665347 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7810 04:47:17.672134 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7811 04:47:17.676114 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7812 04:47:17.678682 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7813 04:47:17.685883 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7814 04:47:17.689176 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7815 04:47:17.692010 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7816 04:47:17.698784 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7817 04:47:17.701864 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7818 04:47:17.705616 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7819 04:47:17.712268 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7820 04:47:17.714832 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7821 04:47:17.718223 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7822 04:47:17.725101 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7823 04:47:17.728544 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7824 04:47:17.731641 Total UI for P1: 0, mck2ui 16
7825 04:47:17.735772 best dqsien dly found for B0: ( 1, 0, 28)
7826 04:47:17.738137 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7827 04:47:17.741838 Total UI for P1: 0, mck2ui 16
7828 04:47:17.745123 best dqsien dly found for B1: ( 1, 1, 2)
7829 04:47:17.749004 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
7830 04:47:17.751384 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7831 04:47:17.751938
7832 04:47:17.754937 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
7833 04:47:17.761450 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7834 04:47:17.762006 [Gating] SW calibration Done
7835 04:47:17.762377 ==
7836 04:47:17.764814 Dram Type= 6, Freq= 0, CH_0, rank 1
7837 04:47:17.771387 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7838 04:47:17.771945 ==
7839 04:47:17.772314 RX Vref Scan: 0
7840 04:47:17.772658
7841 04:47:17.774848 RX Vref 0 -> 0, step: 1
7842 04:47:17.775403
7843 04:47:17.778050 RX Delay 0 -> 252, step: 8
7844 04:47:17.781087 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7845 04:47:17.784794 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7846 04:47:17.788360 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7847 04:47:17.794870 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7848 04:47:17.797976 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7849 04:47:17.801158 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7850 04:47:17.804527 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7851 04:47:17.808462 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7852 04:47:17.810936 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7853 04:47:17.817803 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7854 04:47:17.821693 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7855 04:47:17.824543 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7856 04:47:17.827655 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7857 04:47:17.834324 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7858 04:47:17.837745 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
7859 04:47:17.840880 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7860 04:47:17.841444 ==
7861 04:47:17.844273 Dram Type= 6, Freq= 0, CH_0, rank 1
7862 04:47:17.848024 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7863 04:47:17.848582 ==
7864 04:47:17.850773 DQS Delay:
7865 04:47:17.851324 DQS0 = 0, DQS1 = 0
7866 04:47:17.854182 DQM Delay:
7867 04:47:17.854736 DQM0 = 130, DQM1 = 123
7868 04:47:17.857342 DQ Delay:
7869 04:47:17.861522 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =123
7870 04:47:17.864099 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7871 04:47:17.867394 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7872 04:47:17.870506 DQ12 =131, DQ13 =131, DQ14 =131, DQ15 =131
7873 04:47:17.871061
7874 04:47:17.871425
7875 04:47:17.871764 ==
7876 04:47:17.873904 Dram Type= 6, Freq= 0, CH_0, rank 1
7877 04:47:17.877260 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7878 04:47:17.877816 ==
7879 04:47:17.878186
7880 04:47:17.878524
7881 04:47:17.880329 TX Vref Scan disable
7882 04:47:17.883720 == TX Byte 0 ==
7883 04:47:17.887395 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7884 04:47:17.890258 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7885 04:47:17.894283 == TX Byte 1 ==
7886 04:47:17.897297 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7887 04:47:17.900407 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7888 04:47:17.900937 ==
7889 04:47:17.903612 Dram Type= 6, Freq= 0, CH_0, rank 1
7890 04:47:17.910136 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7891 04:47:17.910601 ==
7892 04:47:17.923408
7893 04:47:17.926274 TX Vref early break, caculate TX vref
7894 04:47:17.930569 TX Vref=16, minBit 1, minWin=22, winSum=374
7895 04:47:17.932833 TX Vref=18, minBit 1, minWin=23, winSum=387
7896 04:47:17.936465 TX Vref=20, minBit 9, minWin=22, winSum=392
7897 04:47:17.939552 TX Vref=22, minBit 1, minWin=24, winSum=399
7898 04:47:17.942742 TX Vref=24, minBit 8, minWin=24, winSum=405
7899 04:47:17.949607 TX Vref=26, minBit 1, minWin=24, winSum=408
7900 04:47:17.952685 TX Vref=28, minBit 1, minWin=25, winSum=414
7901 04:47:17.956629 TX Vref=30, minBit 8, minWin=24, winSum=405
7902 04:47:17.959680 TX Vref=32, minBit 7, minWin=24, winSum=397
7903 04:47:17.963306 TX Vref=34, minBit 8, minWin=22, winSum=393
7904 04:47:17.966121 TX Vref=36, minBit 8, minWin=22, winSum=383
7905 04:47:17.973566 [TxChooseVref] Worse bit 1, Min win 25, Win sum 414, Final Vref 28
7906 04:47:17.974123
7907 04:47:17.975649 Final TX Range 0 Vref 28
7908 04:47:17.976130
7909 04:47:17.976499 ==
7910 04:47:17.980002 Dram Type= 6, Freq= 0, CH_0, rank 1
7911 04:47:17.983225 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7912 04:47:17.983784 ==
7913 04:47:17.985972
7914 04:47:17.986521
7915 04:47:17.986886 TX Vref Scan disable
7916 04:47:17.992164 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7917 04:47:17.992835 == TX Byte 0 ==
7918 04:47:17.995498 u2DelayCellOfst[0]=14 cells (4 PI)
7919 04:47:17.999088 u2DelayCellOfst[1]=17 cells (5 PI)
7920 04:47:18.002456 u2DelayCellOfst[2]=10 cells (3 PI)
7921 04:47:18.005701 u2DelayCellOfst[3]=14 cells (4 PI)
7922 04:47:18.008779 u2DelayCellOfst[4]=10 cells (3 PI)
7923 04:47:18.012515 u2DelayCellOfst[5]=0 cells (0 PI)
7924 04:47:18.015697 u2DelayCellOfst[6]=21 cells (6 PI)
7925 04:47:18.019133 u2DelayCellOfst[7]=17 cells (5 PI)
7926 04:47:18.021790 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7927 04:47:18.026015 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7928 04:47:18.028821 == TX Byte 1 ==
7929 04:47:18.032442 u2DelayCellOfst[8]=0 cells (0 PI)
7930 04:47:18.035325 u2DelayCellOfst[9]=0 cells (0 PI)
7931 04:47:18.039024 u2DelayCellOfst[10]=7 cells (2 PI)
7932 04:47:18.042294 u2DelayCellOfst[11]=3 cells (1 PI)
7933 04:47:18.045380 u2DelayCellOfst[12]=14 cells (4 PI)
7934 04:47:18.045860 u2DelayCellOfst[13]=14 cells (4 PI)
7935 04:47:18.048889 u2DelayCellOfst[14]=17 cells (5 PI)
7936 04:47:18.052177 u2DelayCellOfst[15]=14 cells (4 PI)
7937 04:47:18.058941 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7938 04:47:18.061932 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7939 04:47:18.062502 DramC Write-DBI on
7940 04:47:18.064981 ==
7941 04:47:18.068834 Dram Type= 6, Freq= 0, CH_0, rank 1
7942 04:47:18.071931 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7943 04:47:18.072510 ==
7944 04:47:18.072931
7945 04:47:18.073275
7946 04:47:18.074656 TX Vref Scan disable
7947 04:47:18.075119 == TX Byte 0 ==
7948 04:47:18.082930 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7949 04:47:18.083500 == TX Byte 1 ==
7950 04:47:18.085052 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7951 04:47:18.088470 DramC Write-DBI off
7952 04:47:18.089069
7953 04:47:18.089439 [DATLAT]
7954 04:47:18.091695 Freq=1600, CH0 RK1
7955 04:47:18.092157
7956 04:47:18.092642 DATLAT Default: 0xe
7957 04:47:18.095009 0, 0xFFFF, sum = 0
7958 04:47:18.095586 1, 0xFFFF, sum = 0
7959 04:47:18.098687 2, 0xFFFF, sum = 0
7960 04:47:18.099346 3, 0xFFFF, sum = 0
7961 04:47:18.101670 4, 0xFFFF, sum = 0
7962 04:47:18.102141 5, 0xFFFF, sum = 0
7963 04:47:18.105607 6, 0xFFFF, sum = 0
7964 04:47:18.109401 7, 0xFFFF, sum = 0
7965 04:47:18.109871 8, 0xFFFF, sum = 0
7966 04:47:18.112988 9, 0xFFFF, sum = 0
7967 04:47:18.113461 10, 0xFFFF, sum = 0
7968 04:47:18.114904 11, 0xFFFF, sum = 0
7969 04:47:18.115374 12, 0x8FFF, sum = 0
7970 04:47:18.118469 13, 0x0, sum = 1
7971 04:47:18.118937 14, 0x0, sum = 2
7972 04:47:18.121105 15, 0x0, sum = 3
7973 04:47:18.121575 16, 0x0, sum = 4
7974 04:47:18.121948 best_step = 14
7975 04:47:18.125214
7976 04:47:18.125675 ==
7977 04:47:18.129037 Dram Type= 6, Freq= 0, CH_0, rank 1
7978 04:47:18.131402 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7979 04:47:18.131869 ==
7980 04:47:18.132319 RX Vref Scan: 0
7981 04:47:18.132672
7982 04:47:18.135147 RX Vref 0 -> 0, step: 1
7983 04:47:18.135711
7984 04:47:18.139897 RX Delay 11 -> 252, step: 4
7985 04:47:18.142122 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7986 04:47:18.149422 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
7987 04:47:18.152605 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7988 04:47:18.155674 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
7989 04:47:18.158306 iDelay=195, Bit 4, Center 132 (75 ~ 190) 116
7990 04:47:18.161673 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7991 04:47:18.167786 iDelay=195, Bit 6, Center 136 (79 ~ 194) 116
7992 04:47:18.171207 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7993 04:47:18.174761 iDelay=195, Bit 8, Center 106 (51 ~ 162) 112
7994 04:47:18.177797 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7995 04:47:18.181228 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7996 04:47:18.188144 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7997 04:47:18.190917 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7998 04:47:18.195502 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
7999 04:47:18.198312 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8000 04:47:18.200997 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8001 04:47:18.204218 ==
8002 04:47:18.208406 Dram Type= 6, Freq= 0, CH_0, rank 1
8003 04:47:18.210573 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8004 04:47:18.211042 ==
8005 04:47:18.211531 DQS Delay:
8006 04:47:18.214539 DQS0 = 0, DQS1 = 0
8007 04:47:18.215092 DQM Delay:
8008 04:47:18.217336 DQM0 = 128, DQM1 = 120
8009 04:47:18.217892 DQ Delay:
8010 04:47:18.220802 DQ0 =124, DQ1 =130, DQ2 =126, DQ3 =122
8011 04:47:18.224387 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
8012 04:47:18.227487 DQ8 =106, DQ9 =106, DQ10 =122, DQ11 =112
8013 04:47:18.231164 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
8014 04:47:18.231628
8015 04:47:18.231989
8016 04:47:18.232326
8017 04:47:18.234233 [DramC_TX_OE_Calibration] TA2
8018 04:47:18.237679 Original DQ_B0 (3 6) =30, OEN = 27
8019 04:47:18.241257 Original DQ_B1 (3 6) =30, OEN = 27
8020 04:47:18.243674 24, 0x0, End_B0=24 End_B1=24
8021 04:47:18.247775 25, 0x0, End_B0=25 End_B1=25
8022 04:47:18.248338 26, 0x0, End_B0=26 End_B1=26
8023 04:47:18.250827 27, 0x0, End_B0=27 End_B1=27
8024 04:47:18.255166 28, 0x0, End_B0=28 End_B1=28
8025 04:47:18.257578 29, 0x0, End_B0=29 End_B1=29
8026 04:47:18.261185 30, 0x0, End_B0=30 End_B1=30
8027 04:47:18.261748 31, 0x4141, End_B0=30 End_B1=30
8028 04:47:18.263782 Byte0 end_step=30 best_step=27
8029 04:47:18.266927 Byte1 end_step=30 best_step=27
8030 04:47:18.270299 Byte0 TX OE(2T, 0.5T) = (3, 3)
8031 04:47:18.274251 Byte1 TX OE(2T, 0.5T) = (3, 3)
8032 04:47:18.274800
8033 04:47:18.275165
8034 04:47:18.281201 [DQSOSCAuto] RK1, (LSB)MR18= 0x2121, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
8035 04:47:18.283963 CH0 RK1: MR19=303, MR18=2121
8036 04:47:18.290197 CH0_RK1: MR19=0x303, MR18=0x2121, DQSOSC=393, MR23=63, INC=23, DEC=15
8037 04:47:18.293727 [RxdqsGatingPostProcess] freq 1600
8038 04:47:18.300827 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8039 04:47:18.304010 Pre-setting of DQS Precalculation
8040 04:47:18.307820 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8041 04:47:18.308651 ==
8042 04:47:18.310185 Dram Type= 6, Freq= 0, CH_1, rank 0
8043 04:47:18.313660 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8044 04:47:18.314216 ==
8045 04:47:18.319603 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8046 04:47:18.323835 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8047 04:47:18.330030 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8048 04:47:18.333474 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8049 04:47:18.342601 [CA 0] Center 40 (10~70) winsize 61
8050 04:47:18.345333 [CA 1] Center 40 (10~70) winsize 61
8051 04:47:18.348832 [CA 2] Center 35 (6~65) winsize 60
8052 04:47:18.352669 [CA 3] Center 35 (5~65) winsize 61
8053 04:47:18.356340 [CA 4] Center 33 (3~63) winsize 61
8054 04:47:18.359094 [CA 5] Center 33 (3~63) winsize 61
8055 04:47:18.359667
8056 04:47:18.362920 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8057 04:47:18.363383
8058 04:47:18.369188 [CATrainingPosCal] consider 1 rank data
8059 04:47:18.369649 u2DelayCellTimex100 = 275/100 ps
8060 04:47:18.375917 CA0 delay=40 (10~70),Diff = 7 PI (24 cell)
8061 04:47:18.379968 CA1 delay=40 (10~70),Diff = 7 PI (24 cell)
8062 04:47:18.381716 CA2 delay=35 (6~65),Diff = 2 PI (7 cell)
8063 04:47:18.385633 CA3 delay=35 (5~65),Diff = 2 PI (7 cell)
8064 04:47:18.388806 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
8065 04:47:18.391851 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
8066 04:47:18.392405
8067 04:47:18.395290 CA PerBit enable=1, Macro0, CA PI delay=33
8068 04:47:18.395855
8069 04:47:18.398815 [CBTSetCACLKResult] CA Dly = 33
8070 04:47:18.402008 CS Dly: 8 (0~39)
8071 04:47:18.404889 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8072 04:47:18.408851 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8073 04:47:18.409489 ==
8074 04:47:18.411769 Dram Type= 6, Freq= 0, CH_1, rank 1
8075 04:47:18.418168 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8076 04:47:18.418708 ==
8077 04:47:18.421189 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8078 04:47:18.424535 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8079 04:47:18.431593 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8080 04:47:18.438360 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8081 04:47:18.444990 [CA 0] Center 41 (11~71) winsize 61
8082 04:47:18.448167 [CA 1] Center 40 (10~71) winsize 62
8083 04:47:18.451652 [CA 2] Center 36 (7~66) winsize 60
8084 04:47:18.454438 [CA 3] Center 36 (7~65) winsize 59
8085 04:47:18.457655 [CA 4] Center 34 (5~64) winsize 60
8086 04:47:18.461344 [CA 5] Center 33 (4~63) winsize 60
8087 04:47:18.461811
8088 04:47:18.465274 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8089 04:47:18.465842
8090 04:47:18.468256 [CATrainingPosCal] consider 2 rank data
8091 04:47:18.471284 u2DelayCellTimex100 = 275/100 ps
8092 04:47:18.474768 CA0 delay=40 (11~70),Diff = 7 PI (24 cell)
8093 04:47:18.481552 CA1 delay=40 (10~70),Diff = 7 PI (24 cell)
8094 04:47:18.484694 CA2 delay=36 (7~65),Diff = 3 PI (10 cell)
8095 04:47:18.488902 CA3 delay=36 (7~65),Diff = 3 PI (10 cell)
8096 04:47:18.491415 CA4 delay=34 (5~63),Diff = 1 PI (3 cell)
8097 04:47:18.494567 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8098 04:47:18.495037
8099 04:47:18.498160 CA PerBit enable=1, Macro0, CA PI delay=33
8100 04:47:18.498728
8101 04:47:18.502451 [CBTSetCACLKResult] CA Dly = 33
8102 04:47:18.504235 CS Dly: 9 (0~41)
8103 04:47:18.508038 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8104 04:47:18.511786 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8105 04:47:18.512343
8106 04:47:18.514961 ----->DramcWriteLeveling(PI) begin...
8107 04:47:18.515429 ==
8108 04:47:18.517404 Dram Type= 6, Freq= 0, CH_1, rank 0
8109 04:47:18.521297 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8110 04:47:18.524542 ==
8111 04:47:18.527414 Write leveling (Byte 0): 23 => 23
8112 04:47:18.527879 Write leveling (Byte 1): 22 => 22
8113 04:47:18.531128 DramcWriteLeveling(PI) end<-----
8114 04:47:18.531592
8115 04:47:18.531955 ==
8116 04:47:18.534079 Dram Type= 6, Freq= 0, CH_1, rank 0
8117 04:47:18.540890 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8118 04:47:18.541448 ==
8119 04:47:18.544567 [Gating] SW mode calibration
8120 04:47:18.550902 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8121 04:47:18.554331 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8122 04:47:18.561322 0 12 0 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
8123 04:47:18.564275 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8124 04:47:18.567960 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8125 04:47:18.574890 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8126 04:47:18.577632 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8127 04:47:18.581458 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8128 04:47:18.587584 0 12 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8129 04:47:18.590740 0 12 28 | B1->B0 | 3434 2424 | 1 1 | (1 1) (1 0)
8130 04:47:18.594703 0 13 0 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
8131 04:47:18.601184 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8132 04:47:18.604655 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8133 04:47:18.607896 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8134 04:47:18.614140 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8135 04:47:18.617466 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8136 04:47:18.620432 0 13 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8137 04:47:18.627020 0 13 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8138 04:47:18.630382 0 14 0 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
8139 04:47:18.633639 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8140 04:47:18.641047 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8141 04:47:18.643527 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8142 04:47:18.647031 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8143 04:47:18.650665 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8144 04:47:18.657096 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8145 04:47:18.661056 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8146 04:47:18.663877 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8147 04:47:18.670205 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8148 04:47:18.673284 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8149 04:47:18.676796 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8150 04:47:18.683077 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8151 04:47:18.687632 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8152 04:47:18.689584 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8153 04:47:18.697365 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8154 04:47:18.700341 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8155 04:47:18.702770 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8156 04:47:18.710668 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8157 04:47:18.713485 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8158 04:47:18.716858 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8159 04:47:18.722865 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8160 04:47:18.726243 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8161 04:47:18.730029 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8162 04:47:18.732999 Total UI for P1: 0, mck2ui 16
8163 04:47:18.735824 best dqsien dly found for B0: ( 1, 0, 24)
8164 04:47:18.742799 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8165 04:47:18.745982 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8166 04:47:18.749033 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8167 04:47:18.752365 Total UI for P1: 0, mck2ui 16
8168 04:47:18.756120 best dqsien dly found for B1: ( 1, 1, 0)
8169 04:47:18.759169 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8170 04:47:18.762729 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8171 04:47:18.765883
8172 04:47:18.769238 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8173 04:47:18.772666 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8174 04:47:18.776107 [Gating] SW calibration Done
8175 04:47:18.776664 ==
8176 04:47:18.779530 Dram Type= 6, Freq= 0, CH_1, rank 0
8177 04:47:18.782661 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8178 04:47:18.783215 ==
8179 04:47:18.783588 RX Vref Scan: 0
8180 04:47:18.786177
8181 04:47:18.786730 RX Vref 0 -> 0, step: 1
8182 04:47:18.787101
8183 04:47:18.789101 RX Delay 0 -> 252, step: 8
8184 04:47:18.792905 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8185 04:47:18.795902 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8186 04:47:18.802348 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8187 04:47:18.804914 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8188 04:47:18.808616 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8189 04:47:18.812207 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8190 04:47:18.815588 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8191 04:47:18.822064 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8192 04:47:18.825473 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8193 04:47:18.828418 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8194 04:47:18.832223 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8195 04:47:18.835303 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8196 04:47:18.842536 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8197 04:47:18.845121 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8198 04:47:18.849020 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8199 04:47:18.851834 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8200 04:47:18.852402 ==
8201 04:47:18.854790 Dram Type= 6, Freq= 0, CH_1, rank 0
8202 04:47:18.861607 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8203 04:47:18.862174 ==
8204 04:47:18.862543 DQS Delay:
8205 04:47:18.864401 DQS0 = 0, DQS1 = 0
8206 04:47:18.864894 DQM Delay:
8207 04:47:18.868312 DQM0 = 130, DQM1 = 126
8208 04:47:18.868924 DQ Delay:
8209 04:47:18.871238 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8210 04:47:18.874868 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8211 04:47:18.878172 DQ8 =107, DQ9 =119, DQ10 =127, DQ11 =115
8212 04:47:18.881714 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8213 04:47:18.882285
8214 04:47:18.882655
8215 04:47:18.882998 ==
8216 04:47:18.884847 Dram Type= 6, Freq= 0, CH_1, rank 0
8217 04:47:18.891567 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8218 04:47:18.892156 ==
8219 04:47:18.892530
8220 04:47:18.892913
8221 04:47:18.893247 TX Vref Scan disable
8222 04:47:18.895065 == TX Byte 0 ==
8223 04:47:18.897795 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8224 04:47:18.904699 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8225 04:47:18.905291 == TX Byte 1 ==
8226 04:47:18.908553 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8227 04:47:18.914615 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8228 04:47:18.915185 ==
8229 04:47:18.918877 Dram Type= 6, Freq= 0, CH_1, rank 0
8230 04:47:18.920926 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8231 04:47:18.921497 ==
8232 04:47:18.933085
8233 04:47:18.936515 TX Vref early break, caculate TX vref
8234 04:47:18.939519 TX Vref=16, minBit 3, minWin=21, winSum=365
8235 04:47:18.943265 TX Vref=18, minBit 0, minWin=22, winSum=376
8236 04:47:18.946345 TX Vref=20, minBit 1, minWin=23, winSum=384
8237 04:47:18.949708 TX Vref=22, minBit 0, minWin=24, winSum=395
8238 04:47:18.953686 TX Vref=24, minBit 3, minWin=23, winSum=399
8239 04:47:18.960021 TX Vref=26, minBit 3, minWin=24, winSum=410
8240 04:47:18.962838 TX Vref=28, minBit 0, minWin=25, winSum=415
8241 04:47:18.966302 TX Vref=30, minBit 3, minWin=24, winSum=408
8242 04:47:18.969404 TX Vref=32, minBit 0, minWin=24, winSum=398
8243 04:47:18.972799 TX Vref=34, minBit 1, minWin=23, winSum=387
8244 04:47:18.980166 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 28
8245 04:47:18.980784
8246 04:47:18.982678 Final TX Range 0 Vref 28
8247 04:47:18.983243
8248 04:47:18.983615 ==
8249 04:47:18.986287 Dram Type= 6, Freq= 0, CH_1, rank 0
8250 04:47:18.989440 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8251 04:47:18.990008 ==
8252 04:47:18.990380
8253 04:47:18.990718
8254 04:47:18.992397 TX Vref Scan disable
8255 04:47:18.999608 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8256 04:47:19.000184 == TX Byte 0 ==
8257 04:47:19.003494 u2DelayCellOfst[0]=17 cells (5 PI)
8258 04:47:19.006433 u2DelayCellOfst[1]=14 cells (4 PI)
8259 04:47:19.009192 u2DelayCellOfst[2]=0 cells (0 PI)
8260 04:47:19.012796 u2DelayCellOfst[3]=7 cells (2 PI)
8261 04:47:19.016874 u2DelayCellOfst[4]=10 cells (3 PI)
8262 04:47:19.019329 u2DelayCellOfst[5]=17 cells (5 PI)
8263 04:47:19.022438 u2DelayCellOfst[6]=21 cells (6 PI)
8264 04:47:19.022907 u2DelayCellOfst[7]=10 cells (3 PI)
8265 04:47:19.029413 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8266 04:47:19.033745 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8267 04:47:19.034311 == TX Byte 1 ==
8268 04:47:19.035969 u2DelayCellOfst[8]=0 cells (0 PI)
8269 04:47:19.039145 u2DelayCellOfst[9]=7 cells (2 PI)
8270 04:47:19.044359 u2DelayCellOfst[10]=10 cells (3 PI)
8271 04:47:19.046467 u2DelayCellOfst[11]=3 cells (1 PI)
8272 04:47:19.050548 u2DelayCellOfst[12]=17 cells (5 PI)
8273 04:47:19.053114 u2DelayCellOfst[13]=21 cells (6 PI)
8274 04:47:19.056651 u2DelayCellOfst[14]=17 cells (5 PI)
8275 04:47:19.059679 u2DelayCellOfst[15]=17 cells (5 PI)
8276 04:47:19.062676 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8277 04:47:19.069734 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8278 04:47:19.070300 DramC Write-DBI on
8279 04:47:19.070669 ==
8280 04:47:19.073566 Dram Type= 6, Freq= 0, CH_1, rank 0
8281 04:47:19.076317 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8282 04:47:19.076911 ==
8283 04:47:19.079129
8284 04:47:19.079696
8285 04:47:19.080067 TX Vref Scan disable
8286 04:47:19.083511 == TX Byte 0 ==
8287 04:47:19.086461 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8288 04:47:19.089213 == TX Byte 1 ==
8289 04:47:19.092412 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8290 04:47:19.093010 DramC Write-DBI off
8291 04:47:19.095616
8292 04:47:19.096075 [DATLAT]
8293 04:47:19.096444 Freq=1600, CH1 RK0
8294 04:47:19.096839
8295 04:47:19.099581 DATLAT Default: 0xf
8296 04:47:19.100059 0, 0xFFFF, sum = 0
8297 04:47:19.102099 1, 0xFFFF, sum = 0
8298 04:47:19.102583 2, 0xFFFF, sum = 0
8299 04:47:19.105674 3, 0xFFFF, sum = 0
8300 04:47:19.106160 4, 0xFFFF, sum = 0
8301 04:47:19.108957 5, 0xFFFF, sum = 0
8302 04:47:19.112200 6, 0xFFFF, sum = 0
8303 04:47:19.112670 7, 0xFFFF, sum = 0
8304 04:47:19.116168 8, 0xFFFF, sum = 0
8305 04:47:19.116776 9, 0xFFFF, sum = 0
8306 04:47:19.119048 10, 0xFFFF, sum = 0
8307 04:47:19.119516 11, 0xFFFF, sum = 0
8308 04:47:19.122205 12, 0xF7F, sum = 0
8309 04:47:19.122677 13, 0x0, sum = 1
8310 04:47:19.126657 14, 0x0, sum = 2
8311 04:47:19.127222 15, 0x0, sum = 3
8312 04:47:19.129065 16, 0x0, sum = 4
8313 04:47:19.129534 best_step = 14
8314 04:47:19.129899
8315 04:47:19.130239 ==
8316 04:47:19.131988 Dram Type= 6, Freq= 0, CH_1, rank 0
8317 04:47:19.135294 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8318 04:47:19.135760 ==
8319 04:47:19.138979 RX Vref Scan: 1
8320 04:47:19.139529
8321 04:47:19.142169 Set Vref Range= 24 -> 127
8322 04:47:19.142715
8323 04:47:19.143087 RX Vref 24 -> 127, step: 1
8324 04:47:19.145450
8325 04:47:19.145910 RX Delay 3 -> 252, step: 4
8326 04:47:19.146279
8327 04:47:19.148684 Set Vref, RX VrefLevel [Byte0]: 24
8328 04:47:19.153280 [Byte1]: 24
8329 04:47:19.156807
8330 04:47:19.157272 Set Vref, RX VrefLevel [Byte0]: 25
8331 04:47:19.158757 [Byte1]: 25
8332 04:47:19.163440
8333 04:47:19.163988 Set Vref, RX VrefLevel [Byte0]: 26
8334 04:47:19.166851 [Byte1]: 26
8335 04:47:19.171357
8336 04:47:19.171909 Set Vref, RX VrefLevel [Byte0]: 27
8337 04:47:19.175443 [Byte1]: 27
8338 04:47:19.178418
8339 04:47:19.178895 Set Vref, RX VrefLevel [Byte0]: 28
8340 04:47:19.181975 [Byte1]: 28
8341 04:47:19.186047
8342 04:47:19.186519 Set Vref, RX VrefLevel [Byte0]: 29
8343 04:47:19.189924 [Byte1]: 29
8344 04:47:19.193796
8345 04:47:19.194274 Set Vref, RX VrefLevel [Byte0]: 30
8346 04:47:19.197233 [Byte1]: 30
8347 04:47:19.202010
8348 04:47:19.202590 Set Vref, RX VrefLevel [Byte0]: 31
8349 04:47:19.204410 [Byte1]: 31
8350 04:47:19.209712
8351 04:47:19.210281 Set Vref, RX VrefLevel [Byte0]: 32
8352 04:47:19.212106 [Byte1]: 32
8353 04:47:19.216953
8354 04:47:19.217513 Set Vref, RX VrefLevel [Byte0]: 33
8355 04:47:19.220222 [Byte1]: 33
8356 04:47:19.224756
8357 04:47:19.225330 Set Vref, RX VrefLevel [Byte0]: 34
8358 04:47:19.228257 [Byte1]: 34
8359 04:47:19.232123
8360 04:47:19.232764 Set Vref, RX VrefLevel [Byte0]: 35
8361 04:47:19.234941 [Byte1]: 35
8362 04:47:19.239502
8363 04:47:19.240061 Set Vref, RX VrefLevel [Byte0]: 36
8364 04:47:19.243433 [Byte1]: 36
8365 04:47:19.246955
8366 04:47:19.247453 Set Vref, RX VrefLevel [Byte0]: 37
8367 04:47:19.250708 [Byte1]: 37
8368 04:47:19.254651
8369 04:47:19.255094 Set Vref, RX VrefLevel [Byte0]: 38
8370 04:47:19.258342 [Byte1]: 38
8371 04:47:19.262424
8372 04:47:19.265906 Set Vref, RX VrefLevel [Byte0]: 39
8373 04:47:19.268885 [Byte1]: 39
8374 04:47:19.269273
8375 04:47:19.272108 Set Vref, RX VrefLevel [Byte0]: 40
8376 04:47:19.275612 [Byte1]: 40
8377 04:47:19.276016
8378 04:47:19.278532 Set Vref, RX VrefLevel [Byte0]: 41
8379 04:47:19.282196 [Byte1]: 41
8380 04:47:19.285383
8381 04:47:19.285751 Set Vref, RX VrefLevel [Byte0]: 42
8382 04:47:19.288598 [Byte1]: 42
8383 04:47:19.292934
8384 04:47:19.293468 Set Vref, RX VrefLevel [Byte0]: 43
8385 04:47:19.296209 [Byte1]: 43
8386 04:47:19.300619
8387 04:47:19.301035 Set Vref, RX VrefLevel [Byte0]: 44
8388 04:47:19.304445 [Byte1]: 44
8389 04:47:19.310658
8390 04:47:19.311239 Set Vref, RX VrefLevel [Byte0]: 45
8391 04:47:19.312019 [Byte1]: 45
8392 04:47:19.316325
8393 04:47:19.316922 Set Vref, RX VrefLevel [Byte0]: 46
8394 04:47:19.320773 [Byte1]: 46
8395 04:47:19.324505
8396 04:47:19.325104 Set Vref, RX VrefLevel [Byte0]: 47
8397 04:47:19.327811 [Byte1]: 47
8398 04:47:19.331413
8399 04:47:19.331874 Set Vref, RX VrefLevel [Byte0]: 48
8400 04:47:19.334969 [Byte1]: 48
8401 04:47:19.339419
8402 04:47:19.339964 Set Vref, RX VrefLevel [Byte0]: 49
8403 04:47:19.342511 [Byte1]: 49
8404 04:47:19.346950
8405 04:47:19.347510 Set Vref, RX VrefLevel [Byte0]: 50
8406 04:47:19.350103 [Byte1]: 50
8407 04:47:19.354656
8408 04:47:19.355209 Set Vref, RX VrefLevel [Byte0]: 51
8409 04:47:19.358418 [Byte1]: 51
8410 04:47:19.362571
8411 04:47:19.363121 Set Vref, RX VrefLevel [Byte0]: 52
8412 04:47:19.365475 [Byte1]: 52
8413 04:47:19.370072
8414 04:47:19.370640 Set Vref, RX VrefLevel [Byte0]: 53
8415 04:47:19.372968 [Byte1]: 53
8416 04:47:19.377995
8417 04:47:19.378547 Set Vref, RX VrefLevel [Byte0]: 54
8418 04:47:19.380898 [Byte1]: 54
8419 04:47:19.385265
8420 04:47:19.385814 Set Vref, RX VrefLevel [Byte0]: 55
8421 04:47:19.388269 [Byte1]: 55
8422 04:47:19.392455
8423 04:47:19.393121 Set Vref, RX VrefLevel [Byte0]: 56
8424 04:47:19.396504 [Byte1]: 56
8425 04:47:19.401138
8426 04:47:19.401688 Set Vref, RX VrefLevel [Byte0]: 57
8427 04:47:19.403638 [Byte1]: 57
8428 04:47:19.407798
8429 04:47:19.408471 Set Vref, RX VrefLevel [Byte0]: 58
8430 04:47:19.411169 [Byte1]: 58
8431 04:47:19.415710
8432 04:47:19.416164 Set Vref, RX VrefLevel [Byte0]: 59
8433 04:47:19.419582 [Byte1]: 59
8434 04:47:19.423573
8435 04:47:19.424187 Set Vref, RX VrefLevel [Byte0]: 60
8436 04:47:19.426481 [Byte1]: 60
8437 04:47:19.430886
8438 04:47:19.431343 Set Vref, RX VrefLevel [Byte0]: 61
8439 04:47:19.434187 [Byte1]: 61
8440 04:47:19.439155
8441 04:47:19.439696 Set Vref, RX VrefLevel [Byte0]: 62
8442 04:47:19.442403 [Byte1]: 62
8443 04:47:19.447087
8444 04:47:19.447641 Set Vref, RX VrefLevel [Byte0]: 63
8445 04:47:19.449344 [Byte1]: 63
8446 04:47:19.454076
8447 04:47:19.454629 Set Vref, RX VrefLevel [Byte0]: 64
8448 04:47:19.457243 [Byte1]: 64
8449 04:47:19.461798
8450 04:47:19.462347 Set Vref, RX VrefLevel [Byte0]: 65
8451 04:47:19.464669 [Byte1]: 65
8452 04:47:19.469542
8453 04:47:19.470090 Set Vref, RX VrefLevel [Byte0]: 66
8454 04:47:19.472686 [Byte1]: 66
8455 04:47:19.477201
8456 04:47:19.477657 Set Vref, RX VrefLevel [Byte0]: 67
8457 04:47:19.480309 [Byte1]: 67
8458 04:47:19.485407
8459 04:47:19.485955 Set Vref, RX VrefLevel [Byte0]: 68
8460 04:47:19.487710 [Byte1]: 68
8461 04:47:19.492000
8462 04:47:19.492652 Set Vref, RX VrefLevel [Byte0]: 69
8463 04:47:19.495252 [Byte1]: 69
8464 04:47:19.500114
8465 04:47:19.500671 Set Vref, RX VrefLevel [Byte0]: 70
8466 04:47:19.503032 [Byte1]: 70
8467 04:47:19.507292
8468 04:47:19.507808 Set Vref, RX VrefLevel [Byte0]: 71
8469 04:47:19.510595 [Byte1]: 71
8470 04:47:19.514804
8471 04:47:19.515263 Set Vref, RX VrefLevel [Byte0]: 72
8472 04:47:19.518537 [Byte1]: 72
8473 04:47:19.522486
8474 04:47:19.522974 Set Vref, RX VrefLevel [Byte0]: 73
8475 04:47:19.526543 [Byte1]: 73
8476 04:47:19.530330
8477 04:47:19.530937 Final RX Vref Byte 0 = 60 to rank0
8478 04:47:19.533841 Final RX Vref Byte 1 = 56 to rank0
8479 04:47:19.537055 Final RX Vref Byte 0 = 60 to rank1
8480 04:47:19.540238 Final RX Vref Byte 1 = 56 to rank1==
8481 04:47:19.544210 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 04:47:19.550391 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8483 04:47:19.550969 ==
8484 04:47:19.551469 DQS Delay:
8485 04:47:19.553310 DQS0 = 0, DQS1 = 0
8486 04:47:19.553803 DQM Delay:
8487 04:47:19.554298 DQM0 = 128, DQM1 = 122
8488 04:47:19.556623 DQ Delay:
8489 04:47:19.561362 DQ0 =132, DQ1 =122, DQ2 =118, DQ3 =126
8490 04:47:19.563709 DQ4 =130, DQ5 =140, DQ6 =138, DQ7 =124
8491 04:47:19.566947 DQ8 =104, DQ9 =112, DQ10 =124, DQ11 =110
8492 04:47:19.570281 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =134
8493 04:47:19.570761
8494 04:47:19.571248
8495 04:47:19.571706
8496 04:47:19.573292 [DramC_TX_OE_Calibration] TA2
8497 04:47:19.576614 Original DQ_B0 (3 6) =30, OEN = 27
8498 04:47:19.579913 Original DQ_B1 (3 6) =30, OEN = 27
8499 04:47:19.583403 24, 0x0, End_B0=24 End_B1=24
8500 04:47:19.583986 25, 0x0, End_B0=25 End_B1=25
8501 04:47:19.586649 26, 0x0, End_B0=26 End_B1=26
8502 04:47:19.590513 27, 0x0, End_B0=27 End_B1=27
8503 04:47:19.593266 28, 0x0, End_B0=28 End_B1=28
8504 04:47:19.596546 29, 0x0, End_B0=29 End_B1=29
8505 04:47:19.597070 30, 0x0, End_B0=30 End_B1=30
8506 04:47:19.601118 31, 0x4141, End_B0=30 End_B1=30
8507 04:47:19.603655 Byte0 end_step=30 best_step=27
8508 04:47:19.606433 Byte1 end_step=30 best_step=27
8509 04:47:19.609784 Byte0 TX OE(2T, 0.5T) = (3, 3)
8510 04:47:19.613072 Byte1 TX OE(2T, 0.5T) = (3, 3)
8511 04:47:19.613633
8512 04:47:19.614124
8513 04:47:19.619610 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a2a, (MSB)MR19= 0x303, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
8514 04:47:19.622779 CH1 RK0: MR19=303, MR18=2A2A
8515 04:47:19.629553 CH1_RK0: MR19=0x303, MR18=0x2A2A, DQSOSC=388, MR23=63, INC=24, DEC=16
8516 04:47:19.630107
8517 04:47:19.632836 ----->DramcWriteLeveling(PI) begin...
8518 04:47:19.633322 ==
8519 04:47:19.636590 Dram Type= 6, Freq= 0, CH_1, rank 1
8520 04:47:19.639782 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8521 04:47:19.640356 ==
8522 04:47:19.642685 Write leveling (Byte 0): 22 => 22
8523 04:47:19.646213 Write leveling (Byte 1): 19 => 19
8524 04:47:19.649325 DramcWriteLeveling(PI) end<-----
8525 04:47:19.649892
8526 04:47:19.650393 ==
8527 04:47:19.652592 Dram Type= 6, Freq= 0, CH_1, rank 1
8528 04:47:19.655949 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8529 04:47:19.660510 ==
8530 04:47:19.661131 [Gating] SW mode calibration
8531 04:47:19.666269 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8532 04:47:19.672856 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8533 04:47:19.675953 0 12 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
8534 04:47:19.682675 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8535 04:47:19.685899 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8536 04:47:19.689206 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8537 04:47:19.695820 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8538 04:47:19.699307 0 12 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8539 04:47:19.702499 0 12 24 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
8540 04:47:19.708927 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8541 04:47:19.712499 0 13 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8542 04:47:19.715712 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8543 04:47:19.722453 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8544 04:47:19.725328 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8545 04:47:19.729203 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8546 04:47:19.735833 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8547 04:47:19.738928 0 13 24 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
8548 04:47:19.742065 0 13 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8549 04:47:19.748880 0 14 0 | B1->B0 | 4343 4646 | 0 0 | (1 1) (0 0)
8550 04:47:19.752418 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8551 04:47:19.755832 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8552 04:47:19.762771 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8553 04:47:19.765714 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8554 04:47:19.768882 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8555 04:47:19.775258 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8556 04:47:19.779120 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8557 04:47:19.782404 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8558 04:47:19.785668 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8559 04:47:19.792582 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8560 04:47:19.795036 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8561 04:47:19.799381 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8562 04:47:19.805178 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8563 04:47:19.808678 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8564 04:47:19.811874 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8565 04:47:19.819113 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8566 04:47:19.821964 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8567 04:47:19.824948 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8568 04:47:19.831349 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8569 04:47:19.834495 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8570 04:47:19.838552 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8571 04:47:19.844468 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8572 04:47:19.848123 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8573 04:47:19.851566 Total UI for P1: 0, mck2ui 16
8574 04:47:19.854444 best dqsien dly found for B0: ( 1, 0, 24)
8575 04:47:19.857655 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8576 04:47:19.864263 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8577 04:47:19.868534 Total UI for P1: 0, mck2ui 16
8578 04:47:19.871198 best dqsien dly found for B1: ( 1, 0, 30)
8579 04:47:19.874645 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8580 04:47:19.878262 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8581 04:47:19.878838
8582 04:47:19.880875 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8583 04:47:19.884591 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8584 04:47:19.887907 [Gating] SW calibration Done
8585 04:47:19.888481 ==
8586 04:47:19.891499 Dram Type= 6, Freq= 0, CH_1, rank 1
8587 04:47:19.895065 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8588 04:47:19.895642 ==
8589 04:47:19.898134 RX Vref Scan: 0
8590 04:47:19.898702
8591 04:47:19.899199 RX Vref 0 -> 0, step: 1
8592 04:47:19.901344
8593 04:47:19.901820 RX Delay 0 -> 252, step: 8
8594 04:47:19.904550 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8595 04:47:19.910944 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8596 04:47:19.914155 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8597 04:47:19.918015 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8598 04:47:19.922251 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8599 04:47:19.923804 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8600 04:47:19.930629 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8601 04:47:19.934064 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8602 04:47:19.937247 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8603 04:47:19.940884 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8604 04:47:19.943949 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8605 04:47:19.950671 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8606 04:47:19.954200 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8607 04:47:19.958002 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8608 04:47:19.961039 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8609 04:47:19.967221 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8610 04:47:19.967795 ==
8611 04:47:19.970466 Dram Type= 6, Freq= 0, CH_1, rank 1
8612 04:47:19.974080 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8613 04:47:19.974694 ==
8614 04:47:19.975188 DQS Delay:
8615 04:47:19.976962 DQS0 = 0, DQS1 = 0
8616 04:47:19.977441 DQM Delay:
8617 04:47:19.980837 DQM0 = 130, DQM1 = 124
8618 04:47:19.981315 DQ Delay:
8619 04:47:19.984006 DQ0 =135, DQ1 =127, DQ2 =115, DQ3 =131
8620 04:47:19.987353 DQ4 =127, DQ5 =143, DQ6 =139, DQ7 =127
8621 04:47:19.990484 DQ8 =107, DQ9 =111, DQ10 =123, DQ11 =115
8622 04:47:19.993717 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =131
8623 04:47:19.994190
8624 04:47:19.997581
8625 04:47:19.998132 ==
8626 04:47:20.000281 Dram Type= 6, Freq= 0, CH_1, rank 1
8627 04:47:20.004033 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8628 04:47:20.004597 ==
8629 04:47:20.005013
8630 04:47:20.005360
8631 04:47:20.007300 TX Vref Scan disable
8632 04:47:20.007762 == TX Byte 0 ==
8633 04:47:20.010564 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8634 04:47:20.017594 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8635 04:47:20.018150 == TX Byte 1 ==
8636 04:47:20.021680 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8637 04:47:20.026599 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8638 04:47:20.027145 ==
8639 04:47:20.030831 Dram Type= 6, Freq= 0, CH_1, rank 1
8640 04:47:20.033349 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8641 04:47:20.033816 ==
8642 04:47:20.047958
8643 04:47:20.051013 TX Vref early break, caculate TX vref
8644 04:47:20.054767 TX Vref=16, minBit 3, minWin=22, winSum=380
8645 04:47:20.057705 TX Vref=18, minBit 0, minWin=23, winSum=395
8646 04:47:20.061100 TX Vref=20, minBit 0, minWin=24, winSum=399
8647 04:47:20.063970 TX Vref=22, minBit 0, minWin=24, winSum=405
8648 04:47:20.067640 TX Vref=24, minBit 2, minWin=24, winSum=412
8649 04:47:20.074738 TX Vref=26, minBit 0, minWin=25, winSum=422
8650 04:47:20.077533 TX Vref=28, minBit 0, minWin=24, winSum=420
8651 04:47:20.080802 TX Vref=30, minBit 0, minWin=25, winSum=419
8652 04:47:20.083901 TX Vref=32, minBit 0, minWin=24, winSum=410
8653 04:47:20.087590 TX Vref=34, minBit 0, minWin=23, winSum=401
8654 04:47:20.090737 TX Vref=36, minBit 0, minWin=22, winSum=391
8655 04:47:20.097712 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 26
8656 04:47:20.098273
8657 04:47:20.100909 Final TX Range 0 Vref 26
8658 04:47:20.101540
8659 04:47:20.102021 ==
8660 04:47:20.104219 Dram Type= 6, Freq= 0, CH_1, rank 1
8661 04:47:20.107482 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8662 04:47:20.107984 ==
8663 04:47:20.108462
8664 04:47:20.108995
8665 04:47:20.110542 TX Vref Scan disable
8666 04:47:20.118292 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8667 04:47:20.118870 == TX Byte 0 ==
8668 04:47:20.121142 u2DelayCellOfst[0]=14 cells (4 PI)
8669 04:47:20.123851 u2DelayCellOfst[1]=7 cells (2 PI)
8670 04:47:20.127165 u2DelayCellOfst[2]=0 cells (0 PI)
8671 04:47:20.130922 u2DelayCellOfst[3]=3 cells (1 PI)
8672 04:47:20.134037 u2DelayCellOfst[4]=7 cells (2 PI)
8673 04:47:20.137440 u2DelayCellOfst[5]=14 cells (4 PI)
8674 04:47:20.140521 u2DelayCellOfst[6]=14 cells (4 PI)
8675 04:47:20.144903 u2DelayCellOfst[7]=3 cells (1 PI)
8676 04:47:20.147645 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8677 04:47:20.151141 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8678 04:47:20.153584 == TX Byte 1 ==
8679 04:47:20.157351 u2DelayCellOfst[8]=0 cells (0 PI)
8680 04:47:20.157906 u2DelayCellOfst[9]=7 cells (2 PI)
8681 04:47:20.160194 u2DelayCellOfst[10]=7 cells (2 PI)
8682 04:47:20.163595 u2DelayCellOfst[11]=7 cells (2 PI)
8683 04:47:20.167306 u2DelayCellOfst[12]=14 cells (4 PI)
8684 04:47:20.169987 u2DelayCellOfst[13]=17 cells (5 PI)
8685 04:47:20.173484 u2DelayCellOfst[14]=14 cells (4 PI)
8686 04:47:20.176849 u2DelayCellOfst[15]=17 cells (5 PI)
8687 04:47:20.180292 Update DQ dly =971 (3 ,6, 11) DQ OEN =(3 ,3)
8688 04:47:20.186594 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8689 04:47:20.187150 DramC Write-DBI on
8690 04:47:20.187522 ==
8691 04:47:20.190329 Dram Type= 6, Freq= 0, CH_1, rank 1
8692 04:47:20.196485 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8693 04:47:20.197248 ==
8694 04:47:20.197751
8695 04:47:20.198106
8696 04:47:20.198439 TX Vref Scan disable
8697 04:47:20.200830 == TX Byte 0 ==
8698 04:47:20.204132 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8699 04:47:20.206878 == TX Byte 1 ==
8700 04:47:20.210288 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8701 04:47:20.213610 DramC Write-DBI off
8702 04:47:20.214078
8703 04:47:20.214444 [DATLAT]
8704 04:47:20.214789 Freq=1600, CH1 RK1
8705 04:47:20.215125
8706 04:47:20.216764 DATLAT Default: 0xe
8707 04:47:20.220471 0, 0xFFFF, sum = 0
8708 04:47:20.221090 1, 0xFFFF, sum = 0
8709 04:47:20.223663 2, 0xFFFF, sum = 0
8710 04:47:20.224438 3, 0xFFFF, sum = 0
8711 04:47:20.227805 4, 0xFFFF, sum = 0
8712 04:47:20.228369 5, 0xFFFF, sum = 0
8713 04:47:20.230537 6, 0xFFFF, sum = 0
8714 04:47:20.231008 7, 0xFFFF, sum = 0
8715 04:47:20.233312 8, 0xFFFF, sum = 0
8716 04:47:20.233784 9, 0xFFFF, sum = 0
8717 04:47:20.237102 10, 0xFFFF, sum = 0
8718 04:47:20.237583 11, 0xFFFF, sum = 0
8719 04:47:20.239736 12, 0xF7F, sum = 0
8720 04:47:20.240217 13, 0x0, sum = 1
8721 04:47:20.243414 14, 0x0, sum = 2
8722 04:47:20.243895 15, 0x0, sum = 3
8723 04:47:20.246823 16, 0x0, sum = 4
8724 04:47:20.247365 best_step = 14
8725 04:47:20.247810
8726 04:47:20.248222 ==
8727 04:47:20.250902 Dram Type= 6, Freq= 0, CH_1, rank 1
8728 04:47:20.256526 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8729 04:47:20.257096 ==
8730 04:47:20.257541 RX Vref Scan: 0
8731 04:47:20.257954
8732 04:47:20.259696 RX Vref 0 -> 0, step: 1
8733 04:47:20.260120
8734 04:47:20.263157 RX Delay 3 -> 252, step: 4
8735 04:47:20.266599 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8736 04:47:20.269689 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8737 04:47:20.273465 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8738 04:47:20.279931 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8739 04:47:20.282905 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8740 04:47:20.286858 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8741 04:47:20.289872 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8742 04:47:20.293083 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8743 04:47:20.300104 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8744 04:47:20.302946 iDelay=195, Bit 9, Center 108 (55 ~ 162) 108
8745 04:47:20.306671 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8746 04:47:20.308907 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8747 04:47:20.316058 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8748 04:47:20.319379 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8749 04:47:20.322284 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8750 04:47:20.325660 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8751 04:47:20.326159 ==
8752 04:47:20.329411 Dram Type= 6, Freq= 0, CH_1, rank 1
8753 04:47:20.332499 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8754 04:47:20.335502 ==
8755 04:47:20.335931 DQS Delay:
8756 04:47:20.336375 DQS0 = 0, DQS1 = 0
8757 04:47:20.339351 DQM Delay:
8758 04:47:20.339854 DQM0 = 127, DQM1 = 122
8759 04:47:20.342977 DQ Delay:
8760 04:47:20.345650 DQ0 =128, DQ1 =122, DQ2 =116, DQ3 =124
8761 04:47:20.349705 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8762 04:47:20.352498 DQ8 =104, DQ9 =108, DQ10 =124, DQ11 =114
8763 04:47:20.355994 DQ12 =132, DQ13 =132, DQ14 =134, DQ15 =132
8764 04:47:20.356525
8765 04:47:20.357006
8766 04:47:20.357422
8767 04:47:20.361170 [DramC_TX_OE_Calibration] TA2
8768 04:47:20.362431 Original DQ_B0 (3 6) =30, OEN = 27
8769 04:47:20.365811 Original DQ_B1 (3 6) =30, OEN = 27
8770 04:47:20.369255 24, 0x0, End_B0=24 End_B1=24
8771 04:47:20.369795 25, 0x0, End_B0=25 End_B1=25
8772 04:47:20.372757 26, 0x0, End_B0=26 End_B1=26
8773 04:47:20.375974 27, 0x0, End_B0=27 End_B1=27
8774 04:47:20.379278 28, 0x0, End_B0=28 End_B1=28
8775 04:47:20.379803 29, 0x0, End_B0=29 End_B1=29
8776 04:47:20.382200 30, 0x0, End_B0=30 End_B1=30
8777 04:47:20.385412 31, 0x4141, End_B0=30 End_B1=30
8778 04:47:20.388793 Byte0 end_step=30 best_step=27
8779 04:47:20.392249 Byte1 end_step=30 best_step=27
8780 04:47:20.395752 Byte0 TX OE(2T, 0.5T) = (3, 3)
8781 04:47:20.398404 Byte1 TX OE(2T, 0.5T) = (3, 3)
8782 04:47:20.398867
8783 04:47:20.399229
8784 04:47:20.404933 [DQSOSCAuto] RK1, (LSB)MR18= 0x2020, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
8785 04:47:20.408735 CH1 RK1: MR19=303, MR18=2020
8786 04:47:20.415117 CH1_RK1: MR19=0x303, MR18=0x2020, DQSOSC=393, MR23=63, INC=23, DEC=15
8787 04:47:20.418991 [RxdqsGatingPostProcess] freq 1600
8788 04:47:20.422919 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8789 04:47:20.425277 Pre-setting of DQS Precalculation
8790 04:47:20.431916 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8791 04:47:20.437999 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8792 04:47:20.445444 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8793 04:47:20.446003
8794 04:47:20.446367
8795 04:47:20.449107 [Calibration Summary] 3200 Mbps
8796 04:47:20.449569 CH 0, Rank 0
8797 04:47:20.451931 SW Impedance : PASS
8798 04:47:20.455179 DUTY Scan : NO K
8799 04:47:20.455736 ZQ Calibration : PASS
8800 04:47:20.458264 Jitter Meter : NO K
8801 04:47:20.461255 CBT Training : PASS
8802 04:47:20.461715 Write leveling : PASS
8803 04:47:20.464561 RX DQS gating : PASS
8804 04:47:20.468485 RX DQ/DQS(RDDQC) : PASS
8805 04:47:20.469082 TX DQ/DQS : PASS
8806 04:47:20.471034 RX DATLAT : PASS
8807 04:47:20.475485 RX DQ/DQS(Engine): PASS
8808 04:47:20.476047 TX OE : PASS
8809 04:47:20.477890 All Pass.
8810 04:47:20.478440
8811 04:47:20.478801 CH 0, Rank 1
8812 04:47:20.481257 SW Impedance : PASS
8813 04:47:20.481719 DUTY Scan : NO K
8814 04:47:20.485856 ZQ Calibration : PASS
8815 04:47:20.488169 Jitter Meter : NO K
8816 04:47:20.488767 CBT Training : PASS
8817 04:47:20.491811 Write leveling : PASS
8818 04:47:20.494315 RX DQS gating : PASS
8819 04:47:20.494773 RX DQ/DQS(RDDQC) : PASS
8820 04:47:20.497595 TX DQ/DQS : PASS
8821 04:47:20.500343 RX DATLAT : PASS
8822 04:47:20.500426 RX DQ/DQS(Engine): PASS
8823 04:47:20.504502 TX OE : PASS
8824 04:47:20.504665 All Pass.
8825 04:47:20.504800
8826 04:47:20.507188 CH 1, Rank 0
8827 04:47:20.507307 SW Impedance : PASS
8828 04:47:20.510746 DUTY Scan : NO K
8829 04:47:20.510916 ZQ Calibration : PASS
8830 04:47:20.513668 Jitter Meter : NO K
8831 04:47:20.517847 CBT Training : PASS
8832 04:47:20.518022 Write leveling : PASS
8833 04:47:20.520758 RX DQS gating : PASS
8834 04:47:20.524150 RX DQ/DQS(RDDQC) : PASS
8835 04:47:20.524330 TX DQ/DQS : PASS
8836 04:47:20.527034 RX DATLAT : PASS
8837 04:47:20.530592 RX DQ/DQS(Engine): PASS
8838 04:47:20.530713 TX OE : PASS
8839 04:47:20.533602 All Pass.
8840 04:47:20.533723
8841 04:47:20.533818 CH 1, Rank 1
8842 04:47:20.536815 SW Impedance : PASS
8843 04:47:20.536993 DUTY Scan : NO K
8844 04:47:20.540352 ZQ Calibration : PASS
8845 04:47:20.543742 Jitter Meter : NO K
8846 04:47:20.543982 CBT Training : PASS
8847 04:47:20.547293 Write leveling : PASS
8848 04:47:20.551222 RX DQS gating : PASS
8849 04:47:20.551513 RX DQ/DQS(RDDQC) : PASS
8850 04:47:20.554011 TX DQ/DQS : PASS
8851 04:47:20.557363 RX DATLAT : PASS
8852 04:47:20.557720 RX DQ/DQS(Engine): PASS
8853 04:47:20.560418 TX OE : PASS
8854 04:47:20.560746 All Pass.
8855 04:47:20.560991
8856 04:47:20.563853 DramC Write-DBI on
8857 04:47:20.567495 PER_BANK_REFRESH: Hybrid Mode
8858 04:47:20.567984 TX_TRACKING: ON
8859 04:47:20.577510 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8860 04:47:20.584320 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8861 04:47:20.590871 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8862 04:47:20.594200 [FAST_K] Save calibration result to emmc
8863 04:47:20.597241 sync common calibartion params.
8864 04:47:20.600649 sync cbt_mode0:0, 1:0
8865 04:47:20.605192 dram_init: ddr_geometry: 0
8866 04:47:20.605772 dram_init: ddr_geometry: 0
8867 04:47:20.607671 dram_init: ddr_geometry: 0
8868 04:47:20.610929 0:dram_rank_size:80000000
8869 04:47:20.611502 1:dram_rank_size:80000000
8870 04:47:20.618073 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8871 04:47:20.621065 DFS_SHUFFLE_HW_MODE: ON
8872 04:47:20.623627 dramc_set_vcore_voltage set vcore to 725000
8873 04:47:20.626549 Read voltage for 1600, 0
8874 04:47:20.627022 Vio18 = 0
8875 04:47:20.627494 Vcore = 725000
8876 04:47:20.630466 Vdram = 0
8877 04:47:20.630938 Vddq = 0
8878 04:47:20.631415 Vmddr = 0
8879 04:47:20.633632 switch to 3200 Mbps bootup
8880 04:47:20.634107 [DramcRunTimeConfig]
8881 04:47:20.636980 PHYPLL
8882 04:47:20.637557 DPM_CONTROL_AFTERK: ON
8883 04:47:20.640418 PER_BANK_REFRESH: ON
8884 04:47:20.643553 REFRESH_OVERHEAD_REDUCTION: ON
8885 04:47:20.644139 CMD_PICG_NEW_MODE: OFF
8886 04:47:20.646398 XRTWTW_NEW_MODE: ON
8887 04:47:20.646857 XRTRTR_NEW_MODE: ON
8888 04:47:20.649860 TX_TRACKING: ON
8889 04:47:20.650421 RDSEL_TRACKING: OFF
8890 04:47:20.653634 DQS Precalculation for DVFS: ON
8891 04:47:20.656453 RX_TRACKING: OFF
8892 04:47:20.657052 HW_GATING DBG: ON
8893 04:47:20.659934 ZQCS_ENABLE_LP4: ON
8894 04:47:20.660392 RX_PICG_NEW_MODE: ON
8895 04:47:20.663839 TX_PICG_NEW_MODE: ON
8896 04:47:20.664402 ENABLE_RX_DCM_DPHY: ON
8897 04:47:20.666440 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8898 04:47:20.669556 DUMMY_READ_FOR_TRACKING: OFF
8899 04:47:20.672894 !!! SPM_CONTROL_AFTERK: OFF
8900 04:47:20.676761 !!! SPM could not control APHY
8901 04:47:20.677407 IMPEDANCE_TRACKING: ON
8902 04:47:20.679981 TEMP_SENSOR: ON
8903 04:47:20.680559 HW_SAVE_FOR_SR: OFF
8904 04:47:20.683365 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8905 04:47:20.686722 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8906 04:47:20.689928 Read ODT Tracking: ON
8907 04:47:20.693250 Refresh Rate DeBounce: ON
8908 04:47:20.693811 DFS_NO_QUEUE_FLUSH: ON
8909 04:47:20.696924 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8910 04:47:20.699376 ENABLE_DFS_RUNTIME_MRW: OFF
8911 04:47:20.702820 DDR_RESERVE_NEW_MODE: ON
8912 04:47:20.703389 MR_CBT_SWITCH_FREQ: ON
8913 04:47:20.706065 =========================
8914 04:47:20.725841 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8915 04:47:20.727865 dram_init: ddr_geometry: 0
8916 04:47:20.746689 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8917 04:47:20.749927 dram_init: dram init end (result: 0)
8918 04:47:20.756131 DRAM-K: Full calibration passed in 23387 msecs
8919 04:47:20.759792 MRC: failed to locate region type 0.
8920 04:47:20.760353 DRAM rank0 size:0x80000000,
8921 04:47:20.762535 DRAM rank1 size=0x80000000
8922 04:47:20.772983 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8923 04:47:20.779633 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8924 04:47:20.786858 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8925 04:47:20.793156 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8926 04:47:20.796808 DRAM rank0 size:0x80000000,
8927 04:47:20.799364 DRAM rank1 size=0x80000000
8928 04:47:20.799827 CBMEM:
8929 04:47:20.803242 IMD: root @ 0xfffff000 254 entries.
8930 04:47:20.806629 IMD: root @ 0xffffec00 62 entries.
8931 04:47:20.808871 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8932 04:47:20.813332 WARNING: RO_VPD is uninitialized or empty.
8933 04:47:20.819835 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8934 04:47:20.826214 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8935 04:47:20.838373 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8936 04:47:20.850995 BS: romstage times (exec / console): total (unknown) / 22930 ms
8937 04:47:20.851566
8938 04:47:20.851935
8939 04:47:20.860607 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8940 04:47:20.863906 ARM64: Exception handlers installed.
8941 04:47:20.866743 ARM64: Testing exception
8942 04:47:20.870581 ARM64: Done test exception
8943 04:47:20.871219 Enumerating buses...
8944 04:47:20.873196 Show all devs... Before device enumeration.
8945 04:47:20.877190 Root Device: enabled 1
8946 04:47:20.880213 CPU_CLUSTER: 0: enabled 1
8947 04:47:20.880824 CPU: 00: enabled 1
8948 04:47:20.883062 Compare with tree...
8949 04:47:20.883642 Root Device: enabled 1
8950 04:47:20.886706 CPU_CLUSTER: 0: enabled 1
8951 04:47:20.890227 CPU: 00: enabled 1
8952 04:47:20.890787 Root Device scanning...
8953 04:47:20.893036 scan_static_bus for Root Device
8954 04:47:20.896147 CPU_CLUSTER: 0 enabled
8955 04:47:20.899675 scan_static_bus for Root Device done
8956 04:47:20.903532 scan_bus: bus Root Device finished in 8 msecs
8957 04:47:20.904096 done
8958 04:47:20.909640 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8959 04:47:20.912990 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8960 04:47:20.919884 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8961 04:47:20.923620 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8962 04:47:20.926239 Allocating resources...
8963 04:47:20.929971 Reading resources...
8964 04:47:20.932928 Root Device read_resources bus 0 link: 0
8965 04:47:20.933391 DRAM rank0 size:0x80000000,
8966 04:47:20.935707 DRAM rank1 size=0x80000000
8967 04:47:20.939590 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8968 04:47:20.942499 CPU: 00 missing read_resources
8969 04:47:20.949543 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8970 04:47:20.953636 Root Device read_resources bus 0 link: 0 done
8971 04:47:20.954198 Done reading resources.
8972 04:47:20.959613 Show resources in subtree (Root Device)...After reading.
8973 04:47:20.963935 Root Device child on link 0 CPU_CLUSTER: 0
8974 04:47:20.967356 CPU_CLUSTER: 0 child on link 0 CPU: 00
8975 04:47:20.975759 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8976 04:47:20.976332 CPU: 00
8977 04:47:20.978796 Root Device assign_resources, bus 0 link: 0
8978 04:47:20.982384 CPU_CLUSTER: 0 missing set_resources
8979 04:47:20.988881 Root Device assign_resources, bus 0 link: 0 done
8980 04:47:20.989348 Done setting resources.
8981 04:47:20.995278 Show resources in subtree (Root Device)...After assigning values.
8982 04:47:20.998801 Root Device child on link 0 CPU_CLUSTER: 0
8983 04:47:21.003301 CPU_CLUSTER: 0 child on link 0 CPU: 00
8984 04:47:21.012013 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8985 04:47:21.012580 CPU: 00
8986 04:47:21.015482 Done allocating resources.
8987 04:47:21.022753 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8988 04:47:21.023366 Enabling resources...
8989 04:47:21.023743 done.
8990 04:47:21.029709 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8991 04:47:21.030271 Initializing devices...
8992 04:47:21.032082 Root Device init
8993 04:47:21.032645 init hardware done!
8994 04:47:21.035918 0x00000018: ctrlr->caps
8995 04:47:21.038716 52.000 MHz: ctrlr->f_max
8996 04:47:21.039202 0.400 MHz: ctrlr->f_min
8997 04:47:21.042032 0x40ff8080: ctrlr->voltages
8998 04:47:21.045070 sclk: 390625
8999 04:47:21.045527 Bus Width = 1
9000 04:47:21.045886 sclk: 390625
9001 04:47:21.048654 Bus Width = 1
9002 04:47:21.049271 Early init status = 3
9003 04:47:21.055201 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9004 04:47:21.058842 in-header: 03 fc 00 00 01 00 00 00
9005 04:47:21.062033 in-data: 00
9006 04:47:21.065418 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9007 04:47:21.068856 in-header: 03 fd 00 00 00 00 00 00
9008 04:47:21.072016 in-data:
9009 04:47:21.076647 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9010 04:47:21.079681 in-header: 03 fc 00 00 01 00 00 00
9011 04:47:21.081876 in-data: 00
9012 04:47:21.085261 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9013 04:47:21.090313 in-header: 03 fd 00 00 00 00 00 00
9014 04:47:21.092966 in-data:
9015 04:47:21.096533 [SSUSB] Setting up USB HOST controller...
9016 04:47:21.099734 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9017 04:47:21.103426 [SSUSB] phy power-on done.
9018 04:47:21.107224 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9019 04:47:21.113433 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9020 04:47:21.116790 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9021 04:47:21.123178 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9022 04:47:21.130892 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9023 04:47:21.136173 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9024 04:47:21.143819 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9025 04:47:21.150610 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9026 04:47:21.153114 SPM: binary array size = 0x9dc
9027 04:47:21.156506 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9028 04:47:21.162718 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9029 04:47:21.169440 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9030 04:47:21.176810 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9031 04:47:21.179128 configure_display: Starting display init
9032 04:47:21.213064 anx7625_power_on_init: Init interface.
9033 04:47:21.216777 anx7625_disable_pd_protocol: Disabled PD feature.
9034 04:47:21.219975 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9035 04:47:21.248290 anx7625_start_dp_work: Secure OCM version=00
9036 04:47:21.251651 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9037 04:47:21.266045 sp_tx_get_edid_block: EDID Block = 1
9038 04:47:21.368763 Extracted contents:
9039 04:47:21.372161 header: 00 ff ff ff ff ff ff 00
9040 04:47:21.375339 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9041 04:47:21.378646 version: 01 04
9042 04:47:21.381644 basic params: 95 1f 11 78 0a
9043 04:47:21.384894 chroma info: 76 90 94 55 54 90 27 21 50 54
9044 04:47:21.388060 established: 00 00 00
9045 04:47:21.394710 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9046 04:47:21.398048 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9047 04:47:21.404450 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9048 04:47:21.411752 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9049 04:47:21.417731 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9050 04:47:21.421292 extensions: 00
9051 04:47:21.421746 checksum: fb
9052 04:47:21.422101
9053 04:47:21.424221 Manufacturer: IVO Model 57d Serial Number 0
9054 04:47:21.427793 Made week 0 of 2020
9055 04:47:21.428248 EDID version: 1.4
9056 04:47:21.431450 Digital display
9057 04:47:21.434303 6 bits per primary color channel
9058 04:47:21.434766 DisplayPort interface
9059 04:47:21.437797 Maximum image size: 31 cm x 17 cm
9060 04:47:21.440659 Gamma: 220%
9061 04:47:21.441162 Check DPMS levels
9062 04:47:21.443837 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9063 04:47:21.450805 First detailed timing is preferred timing
9064 04:47:21.451372 Established timings supported:
9065 04:47:21.454142 Standard timings supported:
9066 04:47:21.457554 Detailed timings
9067 04:47:21.460457 Hex of detail: 383680a07038204018303c0035ae10000019
9068 04:47:21.467545 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9069 04:47:21.470908 0780 0798 07c8 0820 hborder 0
9070 04:47:21.473770 0438 043b 0447 0458 vborder 0
9071 04:47:21.477112 -hsync -vsync
9072 04:47:21.477569 Did detailed timing
9073 04:47:21.484262 Hex of detail: 000000000000000000000000000000000000
9074 04:47:21.487277 Manufacturer-specified data, tag 0
9075 04:47:21.490715 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9076 04:47:21.493920 ASCII string: InfoVision
9077 04:47:21.497260 Hex of detail: 000000fe00523134304e574635205248200a
9078 04:47:21.500571 ASCII string: R140NWF5 RH
9079 04:47:21.501199 Checksum
9080 04:47:21.503917 Checksum: 0xfb (valid)
9081 04:47:21.507199 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9082 04:47:21.510282 DSI data_rate: 832800000 bps
9083 04:47:21.517268 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9084 04:47:21.520174 anx7625_parse_edid: pixelclock(138800).
9085 04:47:21.523337 hactive(1920), hsync(48), hfp(24), hbp(88)
9086 04:47:21.526821 vactive(1080), vsync(12), vfp(3), vbp(17)
9087 04:47:21.529660 anx7625_dsi_config: config dsi.
9088 04:47:21.536913 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9089 04:47:21.550467 anx7625_dsi_config: success to config DSI
9090 04:47:21.553577 anx7625_dp_start: MIPI phy setup OK.
9091 04:47:21.556953 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9092 04:47:21.560285 mtk_ddp_mode_set invalid vrefresh 60
9093 04:47:21.564101 main_disp_path_setup
9094 04:47:21.564765 ovl_layer_smi_id_en
9095 04:47:21.567189 ovl_layer_smi_id_en
9096 04:47:21.567764 ccorr_config
9097 04:47:21.568132 aal_config
9098 04:47:21.570048 gamma_config
9099 04:47:21.570507 postmask_config
9100 04:47:21.572898 dither_config
9101 04:47:21.576829 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9102 04:47:21.582990 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9103 04:47:21.587241 Root Device init finished in 551 msecs
9104 04:47:21.589941 CPU_CLUSTER: 0 init
9105 04:47:21.596422 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9106 04:47:21.603067 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9107 04:47:21.603539 APU_MBOX 0x190000b0 = 0x10001
9108 04:47:21.606760 APU_MBOX 0x190001b0 = 0x10001
9109 04:47:21.609873 APU_MBOX 0x190005b0 = 0x10001
9110 04:47:21.613104 APU_MBOX 0x190006b0 = 0x10001
9111 04:47:21.619517 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9112 04:47:21.629766 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9113 04:47:21.642522 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9114 04:47:21.648808 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9115 04:47:21.660072 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9116 04:47:21.669123 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9117 04:47:21.672855 CPU_CLUSTER: 0 init finished in 81 msecs
9118 04:47:21.675926 Devices initialized
9119 04:47:21.678991 Show all devs... After init.
9120 04:47:21.679563 Root Device: enabled 1
9121 04:47:21.682614 CPU_CLUSTER: 0: enabled 1
9122 04:47:21.685930 CPU: 00: enabled 1
9123 04:47:21.688968 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9124 04:47:21.692585 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9125 04:47:21.695727 ELOG: NV offset 0x57f000 size 0x1000
9126 04:47:21.701918 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9127 04:47:21.708784 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9128 04:47:21.711824 ELOG: Event(17) added with size 13 at 2024-02-04 04:47:21 UTC
9129 04:47:21.718405 out: cmd=0x121: 03 db 21 01 00 00 00 00
9130 04:47:21.721832 in-header: 03 21 00 00 2c 00 00 00
9131 04:47:21.731507 in-data: 42 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9132 04:47:21.737873 ELOG: Event(A1) added with size 10 at 2024-02-04 04:47:21 UTC
9133 04:47:21.744789 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9134 04:47:21.751561 ELOG: Event(A0) added with size 9 at 2024-02-04 04:47:21 UTC
9135 04:47:21.755207 elog_add_boot_reason: Logged dev mode boot
9136 04:47:21.761564 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9137 04:47:21.762135 Finalize devices...
9138 04:47:21.764873 Devices finalized
9139 04:47:21.768535 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9140 04:47:21.771178 Writing coreboot table at 0xffe64000
9141 04:47:21.775026 0. 000000000010a000-0000000000113fff: RAMSTAGE
9142 04:47:21.780970 1. 0000000040000000-00000000400fffff: RAM
9143 04:47:21.784692 2. 0000000040100000-000000004032afff: RAMSTAGE
9144 04:47:21.787869 3. 000000004032b000-00000000545fffff: RAM
9145 04:47:21.790914 4. 0000000054600000-000000005465ffff: BL31
9146 04:47:21.794347 5. 0000000054660000-00000000ffe63fff: RAM
9147 04:47:21.800907 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9148 04:47:21.804848 7. 0000000100000000-000000013fffffff: RAM
9149 04:47:21.807789 Passing 5 GPIOs to payload:
9150 04:47:21.810458 NAME | PORT | POLARITY | VALUE
9151 04:47:21.817672 EC in RW | 0x000000aa | low | undefined
9152 04:47:21.820703 EC interrupt | 0x00000005 | low | undefined
9153 04:47:21.824300 TPM interrupt | 0x000000ab | high | undefined
9154 04:47:21.830762 SD card detect | 0x00000011 | high | undefined
9155 04:47:21.834321 speaker enable | 0x00000093 | high | undefined
9156 04:47:21.837124 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9157 04:47:21.840524 in-header: 03 f8 00 00 02 00 00 00
9158 04:47:21.844271 in-data: 03 00
9159 04:47:21.847025 ADC[4]: Raw value=669327 ID=5
9160 04:47:21.850887 ADC[3]: Raw value=212549 ID=1
9161 04:47:21.851457 RAM Code: 0x51
9162 04:47:21.854081 ADC[6]: Raw value=74778 ID=0
9163 04:47:21.856998 ADC[5]: Raw value=212180 ID=1
9164 04:47:21.857464 SKU Code: 0x1
9165 04:47:21.865049 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum d55
9166 04:47:21.865624 coreboot table: 964 bytes.
9167 04:47:21.867598 IMD ROOT 0. 0xfffff000 0x00001000
9168 04:47:21.870821 IMD SMALL 1. 0xffffe000 0x00001000
9169 04:47:21.874197 RO MCACHE 2. 0xffffc000 0x00001104
9170 04:47:21.876944 CONSOLE 3. 0xfff7c000 0x00080000
9171 04:47:21.880302 FMAP 4. 0xfff7b000 0x00000452
9172 04:47:21.884204 TIME STAMP 5. 0xfff7a000 0x00000910
9173 04:47:21.886774 VBOOT WORK 6. 0xfff66000 0x00014000
9174 04:47:21.890077 RAMOOPS 7. 0xffe66000 0x00100000
9175 04:47:21.893655 COREBOOT 8. 0xffe64000 0x00002000
9176 04:47:21.897921 IMD small region:
9177 04:47:21.900082 IMD ROOT 0. 0xffffec00 0x00000400
9178 04:47:21.903147 VPD 1. 0xffffeb80 0x0000006c
9179 04:47:21.907269 MMC STATUS 2. 0xffffeb60 0x00000004
9180 04:47:21.910000 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9181 04:47:21.913401 Probing TPM: done!
9182 04:47:21.917017 Connected to device vid:did:rid of 1ae0:0028:00
9183 04:47:21.928214 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9184 04:47:21.931541 Initialized TPM device CR50 revision 0
9185 04:47:21.935661 Checking cr50 for pending updates
9186 04:47:21.938165 Reading cr50 TPM mode
9187 04:47:21.947565 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9188 04:47:21.953476 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9189 04:47:21.993741 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9190 04:47:21.997276 Checking segment from ROM address 0x40100000
9191 04:47:22.000361 Checking segment from ROM address 0x4010001c
9192 04:47:22.007758 Loading segment from ROM address 0x40100000
9193 04:47:22.008335 code (compression=0)
9194 04:47:22.017465 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9195 04:47:22.023963 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9196 04:47:22.024545 it's not compressed!
9197 04:47:22.031322 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9198 04:47:22.033584 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9199 04:47:22.054357 Loading segment from ROM address 0x4010001c
9200 04:47:22.054925 Entry Point 0x80000000
9201 04:47:22.057905 Loaded segments
9202 04:47:22.060998 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9203 04:47:22.068501 Jumping to boot code at 0x80000000(0xffe64000)
9204 04:47:22.074323 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9205 04:47:22.080808 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9206 04:47:22.088824 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9207 04:47:22.092361 Checking segment from ROM address 0x40100000
9208 04:47:22.095423 Checking segment from ROM address 0x4010001c
9209 04:47:22.102216 Loading segment from ROM address 0x40100000
9210 04:47:22.102772 code (compression=1)
9211 04:47:22.108888 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9212 04:47:22.118743 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9213 04:47:22.119212 using LZMA
9214 04:47:22.126926 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9215 04:47:22.133673 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9216 04:47:22.137386 Loading segment from ROM address 0x4010001c
9217 04:47:22.137952 Entry Point 0x54601000
9218 04:47:22.140000 Loaded segments
9219 04:47:22.143737 NOTICE: MT8192 bl31_setup
9220 04:47:22.150593 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9221 04:47:22.153659 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9222 04:47:22.157172 WARNING: region 0:
9223 04:47:22.161492 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9224 04:47:22.162063 WARNING: region 1:
9225 04:47:22.167927 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9226 04:47:22.171031 WARNING: region 2:
9227 04:47:22.173291 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9228 04:47:22.176889 WARNING: region 3:
9229 04:47:22.180375 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9230 04:47:22.184110 WARNING: region 4:
9231 04:47:22.190934 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9232 04:47:22.191504 WARNING: region 5:
9233 04:47:22.193690 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9234 04:47:22.196781 WARNING: region 6:
9235 04:47:22.200950 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9236 04:47:22.203960 WARNING: region 7:
9237 04:47:22.207330 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9238 04:47:22.213669 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9239 04:47:22.217204 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9240 04:47:22.220046 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9241 04:47:22.227847 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9242 04:47:22.230467 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9243 04:47:22.233802 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9244 04:47:22.240307 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9245 04:47:22.243958 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9246 04:47:22.250407 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9247 04:47:22.253309 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9248 04:47:22.256998 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9249 04:47:22.263843 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9250 04:47:22.267733 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9251 04:47:22.269976 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9252 04:47:22.277088 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9253 04:47:22.280865 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9254 04:47:22.286869 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9255 04:47:22.290560 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9256 04:47:22.293652 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9257 04:47:22.300971 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9258 04:47:22.304122 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9259 04:47:22.307205 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9260 04:47:22.313402 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9261 04:47:22.317166 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9262 04:47:22.323282 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9263 04:47:22.327015 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9264 04:47:22.333658 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9265 04:47:22.337241 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9266 04:47:22.340407 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9267 04:47:22.346576 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9268 04:47:22.351031 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9269 04:47:22.354274 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9270 04:47:22.360616 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9271 04:47:22.363270 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9272 04:47:22.366732 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9273 04:47:22.370255 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9274 04:47:22.376800 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9275 04:47:22.380184 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9276 04:47:22.383385 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9277 04:47:22.387243 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9278 04:47:22.393634 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9279 04:47:22.396795 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9280 04:47:22.400148 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9281 04:47:22.404053 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9282 04:47:22.410053 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9283 04:47:22.413714 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9284 04:47:22.417054 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9285 04:47:22.420118 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9286 04:47:22.427167 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9287 04:47:22.429772 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9288 04:47:22.436647 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9289 04:47:22.440515 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9290 04:47:22.446430 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9291 04:47:22.450077 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9292 04:47:22.453163 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9293 04:47:22.460233 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9294 04:47:22.463375 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9295 04:47:22.470316 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9296 04:47:22.474809 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9297 04:47:22.480047 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9298 04:47:22.483961 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9299 04:47:22.490132 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9300 04:47:22.493632 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9301 04:47:22.496532 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9302 04:47:22.503732 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9303 04:47:22.506643 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9304 04:47:22.513073 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9305 04:47:22.516915 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9306 04:47:22.524808 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9307 04:47:22.526104 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9308 04:47:22.529795 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9309 04:47:22.536690 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9310 04:47:22.539875 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9311 04:47:22.546233 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9312 04:47:22.549668 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9313 04:47:22.556579 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9314 04:47:22.560280 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9315 04:47:22.566347 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9316 04:47:22.570267 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9317 04:47:22.572858 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9318 04:47:22.579628 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9319 04:47:22.582627 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9320 04:47:22.589326 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9321 04:47:22.592916 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9322 04:47:22.599684 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9323 04:47:22.602380 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9324 04:47:22.606300 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9325 04:47:22.612531 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9326 04:47:22.616384 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9327 04:47:22.622505 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9328 04:47:22.625783 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9329 04:47:22.633112 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9330 04:47:22.637187 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9331 04:47:22.643294 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9332 04:47:22.646069 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9333 04:47:22.648744 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9334 04:47:22.655457 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9335 04:47:22.658782 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9336 04:47:22.662308 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9337 04:47:22.665606 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9338 04:47:22.672268 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9339 04:47:22.675508 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9340 04:47:22.682100 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9341 04:47:22.685293 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9342 04:47:22.689302 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9343 04:47:22.695256 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9344 04:47:22.698594 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9345 04:47:22.705876 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9346 04:47:22.709133 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9347 04:47:22.712588 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9348 04:47:22.719794 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9349 04:47:22.722483 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9350 04:47:22.729224 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9351 04:47:22.732599 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9352 04:47:22.737236 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9353 04:47:22.741982 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9354 04:47:22.745580 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9355 04:47:22.748582 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9356 04:47:22.755584 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9357 04:47:22.758907 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9358 04:47:22.762395 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9359 04:47:22.766529 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9360 04:47:22.771607 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9361 04:47:22.776056 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9362 04:47:22.778978 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9363 04:47:22.785125 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9364 04:47:22.789414 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9365 04:47:22.791960 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9366 04:47:22.798902 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9367 04:47:22.801796 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9368 04:47:22.809013 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9369 04:47:22.811944 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9370 04:47:22.815166 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9371 04:47:22.821497 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9372 04:47:22.825247 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9373 04:47:22.831693 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9374 04:47:22.835710 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9375 04:47:22.838927 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9376 04:47:22.845113 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9377 04:47:22.848601 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9378 04:47:22.852650 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9379 04:47:22.859671 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9380 04:47:22.862458 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9381 04:47:22.868643 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9382 04:47:22.871953 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9383 04:47:22.875270 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9384 04:47:22.881589 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9385 04:47:22.885101 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9386 04:47:22.891610 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9387 04:47:22.895192 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9388 04:47:22.898383 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9389 04:47:22.905382 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9390 04:47:22.909048 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9391 04:47:22.912040 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9392 04:47:22.918276 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9393 04:47:22.921502 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9394 04:47:22.928736 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9395 04:47:22.931648 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9396 04:47:22.935050 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9397 04:47:22.941413 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9398 04:47:22.944652 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9399 04:47:22.951551 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9400 04:47:22.954411 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9401 04:47:22.958397 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9402 04:47:22.964647 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9403 04:47:22.968304 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9404 04:47:22.975199 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9405 04:47:22.978452 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9406 04:47:22.981084 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9407 04:47:22.987961 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9408 04:47:22.990988 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9409 04:47:22.998698 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9410 04:47:23.000994 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9411 04:47:23.004194 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9412 04:47:23.011226 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9413 04:47:23.014074 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9414 04:47:23.021038 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9415 04:47:23.024658 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9416 04:47:23.027722 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9417 04:47:23.034039 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9418 04:47:23.037429 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9419 04:47:23.045553 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9420 04:47:23.047332 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9421 04:47:23.051208 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9422 04:47:23.057100 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9423 04:47:23.061185 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9424 04:47:23.065450 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9425 04:47:23.071978 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9426 04:47:23.074297 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9427 04:47:23.081319 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9428 04:47:23.083646 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9429 04:47:23.090050 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9430 04:47:23.093697 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9431 04:47:23.096922 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9432 04:47:23.104010 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9433 04:47:23.107578 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9434 04:47:23.113397 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9435 04:47:23.116815 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9436 04:47:23.123490 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9437 04:47:23.126675 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9438 04:47:23.130178 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9439 04:47:23.136750 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9440 04:47:23.140219 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9441 04:47:23.146975 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9442 04:47:23.149964 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9443 04:47:23.156408 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9444 04:47:23.160129 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9445 04:47:23.163539 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9446 04:47:23.170037 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9447 04:47:23.173543 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9448 04:47:23.180477 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9449 04:47:23.183452 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9450 04:47:23.187249 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9451 04:47:23.193480 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9452 04:47:23.197584 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9453 04:47:23.203314 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9454 04:47:23.206365 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9455 04:47:23.213342 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9456 04:47:23.216146 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9457 04:47:23.219287 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9458 04:47:23.226274 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9459 04:47:23.229192 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9460 04:47:23.235774 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9461 04:47:23.240318 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9462 04:47:23.242830 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9463 04:47:23.249670 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9464 04:47:23.253129 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9465 04:47:23.259580 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9466 04:47:23.262469 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9467 04:47:23.265820 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9468 04:47:23.272669 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9469 04:47:23.275790 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9470 04:47:23.279063 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9471 04:47:23.283413 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9472 04:47:23.289833 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9473 04:47:23.293112 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9474 04:47:23.295836 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9475 04:47:23.302317 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9476 04:47:23.306568 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9477 04:47:23.312290 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9478 04:47:23.316591 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9479 04:47:23.319691 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9480 04:47:23.327383 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9481 04:47:23.328559 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9482 04:47:23.332186 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9483 04:47:23.338443 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9484 04:47:23.341602 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9485 04:47:23.348494 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9486 04:47:23.351621 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9487 04:47:23.355114 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9488 04:47:23.362087 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9489 04:47:23.364809 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9490 04:47:23.368034 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9491 04:47:23.375324 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9492 04:47:23.379131 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9493 04:47:23.385327 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9494 04:47:23.387769 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9495 04:47:23.391235 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9496 04:47:23.397994 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9497 04:47:23.401027 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9498 04:47:23.404439 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9499 04:47:23.411991 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9500 04:47:23.414432 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9501 04:47:23.417408 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9502 04:47:23.424230 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9503 04:47:23.427550 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9504 04:47:23.433992 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9505 04:47:23.437365 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9506 04:47:23.440691 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9507 04:47:23.448425 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9508 04:47:23.450524 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9509 04:47:23.454377 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9510 04:47:23.457635 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9511 04:47:23.460746 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9512 04:47:23.467648 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9513 04:47:23.470945 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9514 04:47:23.474299 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9515 04:47:23.476940 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9516 04:47:23.484201 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9517 04:47:23.487445 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9518 04:47:23.491147 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9519 04:47:23.497450 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9520 04:47:23.500342 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9521 04:47:23.504658 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9522 04:47:23.510441 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9523 04:47:23.513666 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9524 04:47:23.520103 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9525 04:47:23.524005 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9526 04:47:23.530852 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9527 04:47:23.533364 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9528 04:47:23.536771 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9529 04:47:23.543761 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9530 04:47:23.546441 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9531 04:47:23.553575 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9532 04:47:23.556826 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9533 04:47:23.564009 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9534 04:47:23.566417 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9535 04:47:23.569363 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9536 04:47:23.576984 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9537 04:47:23.580349 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9538 04:47:23.587054 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9539 04:47:23.589193 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9540 04:47:23.593392 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9541 04:47:23.599321 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9542 04:47:23.602574 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9543 04:47:23.609819 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9544 04:47:23.612638 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9545 04:47:23.615954 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9546 04:47:23.622430 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9547 04:47:23.625863 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9548 04:47:23.632907 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9549 04:47:23.635556 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9550 04:47:23.642194 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9551 04:47:23.645720 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9552 04:47:23.648738 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9553 04:47:23.656144 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9554 04:47:23.658795 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9555 04:47:23.665930 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9556 04:47:23.668200 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9557 04:47:23.676009 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9558 04:47:23.678702 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9559 04:47:23.681842 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9560 04:47:23.689445 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9561 04:47:23.692932 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9562 04:47:23.698327 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9563 04:47:23.701797 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9564 04:47:23.705266 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9565 04:47:23.712373 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9566 04:47:23.715186 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9567 04:47:23.721244 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9568 04:47:23.724638 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9569 04:47:23.727936 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9570 04:47:23.735123 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9571 04:47:23.739911 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9572 04:47:23.745009 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9573 04:47:23.748649 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9574 04:47:23.754155 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9575 04:47:23.757359 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9576 04:47:23.760879 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9577 04:47:23.767333 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9578 04:47:23.770867 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9579 04:47:23.777470 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9580 04:47:23.780789 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9581 04:47:23.787940 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9582 04:47:23.790745 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9583 04:47:23.793928 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9584 04:47:23.800387 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9585 04:47:23.804236 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9586 04:47:23.810880 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9587 04:47:23.814796 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9588 04:47:23.817398 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9589 04:47:23.823530 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9590 04:47:23.826856 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9591 04:47:23.833748 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9592 04:47:23.837452 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9593 04:47:23.840263 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9594 04:47:23.846682 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9595 04:47:23.850016 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9596 04:47:23.856393 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9597 04:47:23.859652 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9598 04:47:23.866921 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9599 04:47:23.869708 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9600 04:47:23.876610 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9601 04:47:23.880238 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9602 04:47:23.883417 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9603 04:47:23.889559 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9604 04:47:23.894511 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9605 04:47:23.899805 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9606 04:47:23.903394 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9607 04:47:23.909949 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9608 04:47:23.913346 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9609 04:47:23.919687 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9610 04:47:23.923202 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9611 04:47:23.927192 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9612 04:47:23.932972 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9613 04:47:23.936060 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9614 04:47:23.943427 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9615 04:47:23.946427 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9616 04:47:23.952382 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9617 04:47:23.956113 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9618 04:47:23.963139 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9619 04:47:23.966235 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9620 04:47:23.969218 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9621 04:47:23.975714 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9622 04:47:23.979093 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9623 04:47:23.985752 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9624 04:47:23.988946 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9625 04:47:23.995740 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9626 04:47:23.998713 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9627 04:47:24.005453 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9628 04:47:24.008610 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9629 04:47:24.012845 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9630 04:47:24.018835 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9631 04:47:24.021840 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9632 04:47:24.028997 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9633 04:47:24.032001 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9634 04:47:24.039014 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9635 04:47:24.041429 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9636 04:47:24.045082 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9637 04:47:24.052296 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9638 04:47:24.055596 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9639 04:47:24.061564 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9640 04:47:24.065914 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9641 04:47:24.069311 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9642 04:47:24.074907 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9643 04:47:24.078737 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9644 04:47:24.084661 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9645 04:47:24.088206 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9646 04:47:24.094950 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9647 04:47:24.098047 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9648 04:47:24.104513 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9649 04:47:24.107958 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9650 04:47:24.114655 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9651 04:47:24.117734 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9652 04:47:24.124432 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9653 04:47:24.127844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9654 04:47:24.135255 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9655 04:47:24.137763 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9656 04:47:24.145792 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9657 04:47:24.147640 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9658 04:47:24.155298 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9659 04:47:24.158846 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9660 04:47:24.164472 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9661 04:47:24.167666 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9662 04:47:24.174265 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9663 04:47:24.177543 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9664 04:47:24.184337 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9665 04:47:24.187990 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9666 04:47:24.194944 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9667 04:47:24.197664 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9668 04:47:24.204312 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9669 04:47:24.207646 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9670 04:47:24.214339 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9671 04:47:24.217194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9672 04:47:24.220825 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9673 04:47:24.224582 INFO: [APUAPC] vio 0
9674 04:47:24.230915 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9675 04:47:24.234118 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9676 04:47:24.237114 INFO: [APUAPC] D0_APC_0: 0x400510
9677 04:47:24.240439 INFO: [APUAPC] D0_APC_1: 0x0
9678 04:47:24.244294 INFO: [APUAPC] D0_APC_2: 0x1540
9679 04:47:24.247493 INFO: [APUAPC] D0_APC_3: 0x0
9680 04:47:24.250711 INFO: [APUAPC] D1_APC_0: 0xffffffff
9681 04:47:24.253645 INFO: [APUAPC] D1_APC_1: 0xffffffff
9682 04:47:24.256793 INFO: [APUAPC] D1_APC_2: 0x3fffff
9683 04:47:24.260469 INFO: [APUAPC] D1_APC_3: 0x0
9684 04:47:24.264196 INFO: [APUAPC] D2_APC_0: 0xffffffff
9685 04:47:24.267215 INFO: [APUAPC] D2_APC_1: 0xffffffff
9686 04:47:24.270918 INFO: [APUAPC] D2_APC_2: 0x3fffff
9687 04:47:24.274413 INFO: [APUAPC] D2_APC_3: 0x0
9688 04:47:24.277192 INFO: [APUAPC] D3_APC_0: 0xffffffff
9689 04:47:24.280563 INFO: [APUAPC] D3_APC_1: 0xffffffff
9690 04:47:24.284314 INFO: [APUAPC] D3_APC_2: 0x3fffff
9691 04:47:24.284915 INFO: [APUAPC] D3_APC_3: 0x0
9692 04:47:24.290387 INFO: [APUAPC] D4_APC_0: 0xffffffff
9693 04:47:24.293997 INFO: [APUAPC] D4_APC_1: 0xffffffff
9694 04:47:24.297195 INFO: [APUAPC] D4_APC_2: 0x3fffff
9695 04:47:24.297902 INFO: [APUAPC] D4_APC_3: 0x0
9696 04:47:24.300079 INFO: [APUAPC] D5_APC_0: 0xffffffff
9697 04:47:24.307290 INFO: [APUAPC] D5_APC_1: 0xffffffff
9698 04:47:24.310541 INFO: [APUAPC] D5_APC_2: 0x3fffff
9699 04:47:24.311142 INFO: [APUAPC] D5_APC_3: 0x0
9700 04:47:24.313534 INFO: [APUAPC] D6_APC_0: 0xffffffff
9701 04:47:24.316414 INFO: [APUAPC] D6_APC_1: 0xffffffff
9702 04:47:24.319869 INFO: [APUAPC] D6_APC_2: 0x3fffff
9703 04:47:24.323109 INFO: [APUAPC] D6_APC_3: 0x0
9704 04:47:24.326484 INFO: [APUAPC] D7_APC_0: 0xffffffff
9705 04:47:24.330316 INFO: [APUAPC] D7_APC_1: 0xffffffff
9706 04:47:24.333673 INFO: [APUAPC] D7_APC_2: 0x3fffff
9707 04:47:24.337093 INFO: [APUAPC] D7_APC_3: 0x0
9708 04:47:24.340017 INFO: [APUAPC] D8_APC_0: 0xffffffff
9709 04:47:24.343783 INFO: [APUAPC] D8_APC_1: 0xffffffff
9710 04:47:24.346399 INFO: [APUAPC] D8_APC_2: 0x3fffff
9711 04:47:24.349460 INFO: [APUAPC] D8_APC_3: 0x0
9712 04:47:24.353031 INFO: [APUAPC] D9_APC_0: 0xffffffff
9713 04:47:24.356301 INFO: [APUAPC] D9_APC_1: 0xffffffff
9714 04:47:24.359767 INFO: [APUAPC] D9_APC_2: 0x3fffff
9715 04:47:24.363097 INFO: [APUAPC] D9_APC_3: 0x0
9716 04:47:24.366058 INFO: [APUAPC] D10_APC_0: 0xffffffff
9717 04:47:24.370540 INFO: [APUAPC] D10_APC_1: 0xffffffff
9718 04:47:24.372754 INFO: [APUAPC] D10_APC_2: 0x3fffff
9719 04:47:24.376203 INFO: [APUAPC] D10_APC_3: 0x0
9720 04:47:24.379833 INFO: [APUAPC] D11_APC_0: 0xffffffff
9721 04:47:24.383437 INFO: [APUAPC] D11_APC_1: 0xffffffff
9722 04:47:24.386500 INFO: [APUAPC] D11_APC_2: 0x3fffff
9723 04:47:24.389799 INFO: [APUAPC] D11_APC_3: 0x0
9724 04:47:24.393206 INFO: [APUAPC] D12_APC_0: 0xffffffff
9725 04:47:24.396606 INFO: [APUAPC] D12_APC_1: 0xffffffff
9726 04:47:24.400353 INFO: [APUAPC] D12_APC_2: 0x3fffff
9727 04:47:24.403081 INFO: [APUAPC] D12_APC_3: 0x0
9728 04:47:24.405915 INFO: [APUAPC] D13_APC_0: 0xffffffff
9729 04:47:24.408995 INFO: [APUAPC] D13_APC_1: 0xffffffff
9730 04:47:24.413055 INFO: [APUAPC] D13_APC_2: 0x3fffff
9731 04:47:24.416110 INFO: [APUAPC] D13_APC_3: 0x0
9732 04:47:24.419491 INFO: [APUAPC] D14_APC_0: 0xffffffff
9733 04:47:24.422803 INFO: [APUAPC] D14_APC_1: 0xffffffff
9734 04:47:24.426884 INFO: [APUAPC] D14_APC_2: 0x3fffff
9735 04:47:24.429021 INFO: [APUAPC] D14_APC_3: 0x0
9736 04:47:24.432825 INFO: [APUAPC] D15_APC_0: 0xffffffff
9737 04:47:24.435996 INFO: [APUAPC] D15_APC_1: 0xffffffff
9738 04:47:24.439177 INFO: [APUAPC] D15_APC_2: 0x3fffff
9739 04:47:24.442474 INFO: [APUAPC] D15_APC_3: 0x0
9740 04:47:24.445767 INFO: [APUAPC] APC_CON: 0x4
9741 04:47:24.449388 INFO: [NOCDAPC] D0_APC_0: 0x0
9742 04:47:24.452529 INFO: [NOCDAPC] D0_APC_1: 0x0
9743 04:47:24.455822 INFO: [NOCDAPC] D1_APC_0: 0x0
9744 04:47:24.459425 INFO: [NOCDAPC] D1_APC_1: 0xfff
9745 04:47:24.462067 INFO: [NOCDAPC] D2_APC_0: 0x0
9746 04:47:24.465785 INFO: [NOCDAPC] D2_APC_1: 0xfff
9747 04:47:24.466250 INFO: [NOCDAPC] D3_APC_0: 0x0
9748 04:47:24.469208 INFO: [NOCDAPC] D3_APC_1: 0xfff
9749 04:47:24.472237 INFO: [NOCDAPC] D4_APC_0: 0x0
9750 04:47:24.476062 INFO: [NOCDAPC] D4_APC_1: 0xfff
9751 04:47:24.478995 INFO: [NOCDAPC] D5_APC_0: 0x0
9752 04:47:24.482442 INFO: [NOCDAPC] D5_APC_1: 0xfff
9753 04:47:24.485436 INFO: [NOCDAPC] D6_APC_0: 0x0
9754 04:47:24.488871 INFO: [NOCDAPC] D6_APC_1: 0xfff
9755 04:47:24.492790 INFO: [NOCDAPC] D7_APC_0: 0x0
9756 04:47:24.495116 INFO: [NOCDAPC] D7_APC_1: 0xfff
9757 04:47:24.498848 INFO: [NOCDAPC] D8_APC_0: 0x0
9758 04:47:24.502305 INFO: [NOCDAPC] D8_APC_1: 0xfff
9759 04:47:24.502873 INFO: [NOCDAPC] D9_APC_0: 0x0
9760 04:47:24.504975 INFO: [NOCDAPC] D9_APC_1: 0xfff
9761 04:47:24.508557 INFO: [NOCDAPC] D10_APC_0: 0x0
9762 04:47:24.512169 INFO: [NOCDAPC] D10_APC_1: 0xfff
9763 04:47:24.514893 INFO: [NOCDAPC] D11_APC_0: 0x0
9764 04:47:24.519368 INFO: [NOCDAPC] D11_APC_1: 0xfff
9765 04:47:24.521688 INFO: [NOCDAPC] D12_APC_0: 0x0
9766 04:47:24.525295 INFO: [NOCDAPC] D12_APC_1: 0xfff
9767 04:47:24.528477 INFO: [NOCDAPC] D13_APC_0: 0x0
9768 04:47:24.531870 INFO: [NOCDAPC] D13_APC_1: 0xfff
9769 04:47:24.535088 INFO: [NOCDAPC] D14_APC_0: 0x0
9770 04:47:24.538855 INFO: [NOCDAPC] D14_APC_1: 0xfff
9771 04:47:24.541972 INFO: [NOCDAPC] D15_APC_0: 0x0
9772 04:47:24.544824 INFO: [NOCDAPC] D15_APC_1: 0xfff
9773 04:47:24.545290 INFO: [NOCDAPC] APC_CON: 0x4
9774 04:47:24.548633 INFO: [APUAPC] set_apusys_apc done
9775 04:47:24.551430 INFO: [DEVAPC] devapc_init done
9776 04:47:24.558353 INFO: GICv3 without legacy support detected.
9777 04:47:24.561350 INFO: ARM GICv3 driver initialized in EL3
9778 04:47:24.564828 INFO: Maximum SPI INTID supported: 639
9779 04:47:24.568451 INFO: BL31: Initializing runtime services
9780 04:47:24.575056 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9781 04:47:24.578232 INFO: SPM: enable CPC mode
9782 04:47:24.581360 INFO: mcdi ready for mcusys-off-idle and system suspend
9783 04:47:24.588024 INFO: BL31: Preparing for EL3 exit to normal world
9784 04:47:24.591473 INFO: Entry point address = 0x80000000
9785 04:47:24.592039 INFO: SPSR = 0x8
9786 04:47:24.598676
9787 04:47:24.599262
9788 04:47:24.599632
9789 04:47:24.601875 Starting depthcharge on Spherion...
9790 04:47:24.602439
9791 04:47:24.602836 Wipe memory regions:
9792 04:47:24.603188
9793 04:47:24.606083 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9794 04:47:24.606654 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9795 04:47:24.607114 Setting prompt string to ['asurada:']
9796 04:47:24.607564 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9797 04:47:24.608426 [0x00000040000000, 0x00000054600000)
9798 04:47:24.728059
9799 04:47:24.728619 [0x00000054660000, 0x00000080000000)
9800 04:47:24.988388
9801 04:47:24.989012 [0x000000821a7280, 0x000000ffe64000)
9802 04:47:25.733127
9803 04:47:25.733696 [0x00000100000000, 0x00000140000000)
9804 04:47:26.113942
9805 04:47:26.117267 Initializing XHCI USB controller at 0x11200000.
9806 04:47:27.156430
9807 04:47:27.158169 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9808 04:47:27.158633
9809 04:47:27.158997
9810 04:47:27.159339
9811 04:47:27.160166 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9813 04:47:27.261508 asurada: tftpboot 192.168.201.1 12699848/tftp-deploy-qzgrpv7l/kernel/image.itb 12699848/tftp-deploy-qzgrpv7l/kernel/cmdline
9814 04:47:27.262178 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9815 04:47:27.262645 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9816 04:47:27.267386 tftpboot 192.168.201.1 12699848/tftp-deploy-qzgrpv7l/kernel/image.itp-deploy-qzgrpv7l/kernel/cmdline
9817 04:47:27.267959
9818 04:47:27.268333 Waiting for link
9819 04:47:27.427863
9820 04:47:27.428455 R8152: Initializing
9821 04:47:27.428892
9822 04:47:27.430836 Version 9 (ocp_data = 6010)
9823 04:47:27.431299
9824 04:47:27.434657 R8152: Done initializing
9825 04:47:27.435229
9826 04:47:27.435602 Adding net device
9827 04:47:29.317268
9828 04:47:29.317829 done.
9829 04:47:29.318202
9830 04:47:29.318543 MAC: 00:e0:4c:68:03:bd
9831 04:47:29.318879
9832 04:47:29.320270 Sending DHCP discover... done.
9833 04:47:29.320776
9834 04:47:39.729652 Waiting for reply... R8152: Bulk read error 0xffffffbf
9835 04:47:39.730224
9836 04:47:39.732891 Receive failed.
9837 04:47:39.733350
9838 04:47:39.733711 done.
9839 04:47:39.734051
9840 04:47:39.736167 Sending DHCP request... done.
9841 04:47:39.736772
9842 04:47:39.739363 Waiting for reply... done.
9843 04:47:39.739928
9844 04:47:39.742395 My ip is 192.168.201.16
9845 04:47:39.743185
9846 04:47:39.746344 The DHCP server ip is 192.168.201.1
9847 04:47:39.746912
9848 04:47:39.749111 TFTP server IP predefined by user: 192.168.201.1
9849 04:47:39.749775
9850 04:47:39.755894 Bootfile predefined by user: 12699848/tftp-deploy-qzgrpv7l/kernel/image.itb
9851 04:47:39.756394
9852 04:47:39.758805 Sending tftp read request... done.
9853 04:47:39.759265
9854 04:47:39.767386 Waiting for the transfer...
9855 04:47:39.767948
9856 04:47:40.094147 00000000 ################################################################
9857 04:47:40.094294
9858 04:47:40.375030 00080000 ################################################################
9859 04:47:40.375167
9860 04:47:40.656209 00100000 ################################################################
9861 04:47:40.656350
9862 04:47:40.936444 00180000 ################################################################
9863 04:47:40.936605
9864 04:47:41.199486 00200000 ################################################################
9865 04:47:41.199655
9866 04:47:41.450027 00280000 ################################################################
9867 04:47:41.450170
9868 04:47:41.701271 00300000 ################################################################
9869 04:47:41.701412
9870 04:47:41.952373 00380000 ################################################################
9871 04:47:41.952525
9872 04:47:42.206787 00400000 ################################################################
9873 04:47:42.206947
9874 04:47:42.479285 00480000 ################################################################
9875 04:47:42.479416
9876 04:47:42.734260 00500000 ################################################################
9877 04:47:42.734393
9878 04:47:43.016227 00580000 ################################################################
9879 04:47:43.016386
9880 04:47:43.271821 00600000 ################################################################
9881 04:47:43.271989
9882 04:47:43.524281 00680000 ################################################################
9883 04:47:43.524415
9884 04:47:43.776283 00700000 ################################################################
9885 04:47:43.776432
9886 04:47:44.027362 00780000 ################################################################
9887 04:47:44.027500
9888 04:47:44.282083 00800000 ################################################################
9889 04:47:44.282219
9890 04:47:44.536098 00880000 ################################################################
9891 04:47:44.536223
9892 04:47:44.810906 00900000 ################################################################
9893 04:47:44.811075
9894 04:47:45.061728 00980000 ################################################################
9895 04:47:45.061872
9896 04:47:45.320395 00a00000 ################################################################
9897 04:47:45.320560
9898 04:47:45.574972 00a80000 ################################################################
9899 04:47:45.575131
9900 04:47:45.825144 00b00000 ################################################################
9901 04:47:45.825282
9902 04:47:46.080312 00b80000 ################################################################
9903 04:47:46.080471
9904 04:47:46.331704 00c00000 ################################################################
9905 04:47:46.331845
9906 04:47:46.586073 00c80000 ################################################################
9907 04:47:46.586207
9908 04:47:46.838762 00d00000 ################################################################
9909 04:47:46.838917
9910 04:47:47.090671 00d80000 ################################################################
9911 04:47:47.090835
9912 04:47:47.340627 00e00000 ################################################################
9913 04:47:47.340791
9914 04:47:47.593111 00e80000 ################################################################
9915 04:47:47.593255
9916 04:47:47.844430 00f00000 ################################################################
9917 04:47:47.844587
9918 04:47:48.095339 00f80000 ################################################################
9919 04:47:48.095492
9920 04:47:48.346930 01000000 ################################################################
9921 04:47:48.347086
9922 04:47:48.597611 01080000 ################################################################
9923 04:47:48.597748
9924 04:47:48.851737 01100000 ################################################################
9925 04:47:48.851888
9926 04:47:49.122197 01180000 ################################################################
9927 04:47:49.122336
9928 04:47:49.402115 01200000 ################################################################
9929 04:47:49.402261
9930 04:47:49.686771 01280000 ################################################################
9931 04:47:49.686924
9932 04:47:49.974035 01300000 ################################################################
9933 04:47:49.974177
9934 04:47:50.252927 01380000 ################################################################
9935 04:47:50.253068
9936 04:47:50.538349 01400000 ################################################################
9937 04:47:50.538475
9938 04:47:50.817259 01480000 ################################################################
9939 04:47:50.817386
9940 04:47:51.097048 01500000 ################################################################
9941 04:47:51.097174
9942 04:47:51.378502 01580000 ################################################################
9943 04:47:51.378627
9944 04:47:51.658960 01600000 ################################################################
9945 04:47:51.659087
9946 04:47:51.940997 01680000 ################################################################
9947 04:47:51.941129
9948 04:47:52.222699 01700000 ################################################################
9949 04:47:52.222864
9950 04:47:52.505681 01780000 ################################################################
9951 04:47:52.505825
9952 04:47:52.785282 01800000 ################################################################
9953 04:47:52.785417
9954 04:47:53.063719 01880000 ################################################################
9955 04:47:53.063873
9956 04:47:53.343105 01900000 ################################################################
9957 04:47:53.343281
9958 04:47:53.621297 01980000 ################################################################
9959 04:47:53.621434
9960 04:47:53.899788 01a00000 ################################################################
9961 04:47:53.899942
9962 04:47:54.186244 01a80000 ################################################################
9963 04:47:54.186382
9964 04:47:54.464317 01b00000 ################################################################
9965 04:47:54.464470
9966 04:47:54.743451 01b80000 ################################################################
9967 04:47:54.743604
9968 04:47:55.024882 01c00000 ################################################################
9969 04:47:55.025012
9970 04:47:55.033898 01c80000 ## done.
9971 04:47:55.034316
9972 04:47:55.037693 The bootfile was 29898726 bytes long.
9973 04:47:55.038109
9974 04:47:55.041150 Sending tftp read request... done.
9975 04:47:55.041567
9976 04:47:55.043668 Waiting for the transfer...
9977 04:47:55.044081
9978 04:47:55.044406 00000000 # done.
9979 04:47:55.044768
9980 04:47:55.050565 Command line loaded dynamically from TFTP file: 12699848/tftp-deploy-qzgrpv7l/kernel/cmdline
9981 04:47:55.050985
9982 04:47:55.073234 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12699848/extract-nfsrootfs-7j02hjaw,tcp,hard ip=dhcp tftpserverip=192.168.201.1
9983 04:47:55.073753
9984 04:47:55.074137 Loading FIT.
9985 04:47:55.077166
9986 04:47:55.077580 Image ramdisk-1 has 17800906 bytes.
9987 04:47:55.077911
9988 04:47:55.079951 Image fdt-1 has 47278 bytes.
9989 04:47:55.080350
9990 04:47:55.083755 Image kernel-1 has 12048508 bytes.
9991 04:47:55.084172
9992 04:47:55.094107 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
9993 04:47:55.094678
9994 04:47:55.109954 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
9995 04:47:55.110455
9996 04:47:55.117551 Choosing best match conf-1 for compat google,spherion-rev3.
9997 04:47:55.118054
9998 04:47:55.124831 Connected to device vid:did:rid of 1ae0:0028:00
9999 04:47:55.131961
10000 04:47:55.136162 tpm_get_response: command 0x17b, return code 0x0
10001 04:47:55.136690
10002 04:47:55.138413 ec_init: CrosEC protocol v3 supported (256, 248)
10003 04:47:55.142892
10004 04:47:55.146077 tpm_cleanup: add release locality here.
10005 04:47:55.146493
10006 04:47:55.146819 Shutting down all USB controllers.
10007 04:47:55.149256
10008 04:47:55.149671 Removing current net device
10009 04:47:55.149999
10010 04:47:55.156875 Exiting depthcharge with code 4 at timestamp: 58735498
10011 04:47:55.157393
10012 04:47:55.159246 LZMA decompressing kernel-1 to 0x821a6718
10013 04:47:55.159654
10014 04:47:55.162965 LZMA decompressing kernel-1 to 0x40000000
10015 04:47:56.660156
10016 04:47:56.660756 jumping to kernel
10017 04:47:56.662968 end: 2.2.4 bootloader-commands (duration 00:00:32) [common]
10018 04:47:56.663500 start: 2.2.5 auto-login-action (timeout 00:03:54) [common]
10019 04:47:56.663910 Setting prompt string to ['Linux version [0-9]']
10020 04:47:56.664295 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10021 04:47:56.664672 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10022 04:47:56.710506
10023 04:47:56.713639 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10024 04:47:56.717728 start: 2.2.5.1 login-action (timeout 00:03:54) [common]
10025 04:47:56.718308 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10026 04:47:56.718709 Setting prompt string to []
10027 04:47:56.719340 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10028 04:47:56.719758 Using line separator: #'\n'#
10029 04:47:56.720155 No login prompt set.
10030 04:47:56.720528 Parsing kernel messages
10031 04:47:56.720892 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10032 04:47:56.721463 [login-action] Waiting for messages, (timeout 00:03:54)
10033 04:47:56.736933 [ 0.000000] Linux version 6.1.75-cip14-rt8 (KernelCI@build-j97480-arm64-gcc-10-defconfig-arm64-chromebook-6n26j) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Feb 4 04:24:19 UTC 2024
10034 04:47:56.739866 [ 0.000000] random: crng init done
10035 04:47:56.746232 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10036 04:47:56.749382 [ 0.000000] efi: UEFI not found.
10037 04:47:56.756406 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10038 04:47:56.766066 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10039 04:47:56.775903 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10040 04:47:56.782403 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10041 04:47:56.789215 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10042 04:47:56.795659 [ 0.000000] printk: bootconsole [mtk8250] enabled
10043 04:47:56.802522 [ 0.000000] NUMA: No NUMA configuration found
10044 04:47:56.809470 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10045 04:47:56.815606 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10046 04:47:56.816169 [ 0.000000] Zone ranges:
10047 04:47:56.823190 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10048 04:47:56.826052 [ 0.000000] DMA32 empty
10049 04:47:56.832369 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10050 04:47:56.835292 [ 0.000000] Movable zone start for each node
10051 04:47:56.839073 [ 0.000000] Early memory node ranges
10052 04:47:56.844952 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10053 04:47:56.852180 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10054 04:47:56.858518 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10055 04:47:56.865336 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10056 04:47:56.872543 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10057 04:47:56.878645 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10058 04:47:56.908551 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10059 04:47:56.915283 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10060 04:47:56.921682 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10061 04:47:56.925175 [ 0.000000] psci: probing for conduit method from DT.
10062 04:47:56.932131 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10063 04:47:56.935386 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10064 04:47:56.941712 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10065 04:47:56.944743 [ 0.000000] psci: SMC Calling Convention v1.2
10066 04:47:56.951655 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10067 04:47:56.955280 [ 0.000000] Detected VIPT I-cache on CPU0
10068 04:47:56.961743 [ 0.000000] CPU features: detected: GIC system register CPU interface
10069 04:47:56.968408 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10070 04:47:56.974244 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10071 04:47:56.981069 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10072 04:47:56.991694 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10073 04:47:56.997851 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10074 04:47:57.001335 [ 0.000000] alternatives: applying boot alternatives
10075 04:47:57.007443 [ 0.000000] Fallback order for Node 0: 0
10076 04:47:57.014163 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10077 04:47:57.017530 [ 0.000000] Policy zone: Normal
10078 04:47:57.040595 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12699848/extract-nfsrootfs-7j02hjaw,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10079 04:47:57.050604 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10080 04:47:57.060792 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10081 04:47:57.067317 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10082 04:47:57.073878 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10083 04:47:57.080053 <6>[ 0.000000] software IO TLB: area num 8.
10084 04:47:57.135824 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10085 04:47:57.215967 <6>[ 0.000000] Memory: 3835396K/4191232K available (18048K kernel code, 4116K rwdata, 19608K rodata, 8448K init, 616K bss, 323068K reserved, 32768K cma-reserved)
10086 04:47:57.222366 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10087 04:47:57.228930 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10088 04:47:57.232089 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10089 04:47:57.238769 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10090 04:47:57.245054 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10091 04:47:57.249137 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10092 04:47:57.259834 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10093 04:47:57.265986 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10094 04:47:57.271942 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10095 04:47:57.278556 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10096 04:47:57.281817 <6>[ 0.000000] GICv3: 608 SPIs implemented
10097 04:47:57.284546 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10098 04:47:57.291912 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10099 04:47:57.294502 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10100 04:47:57.301055 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10101 04:47:57.314307 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10102 04:47:57.328532 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10103 04:47:57.334327 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10104 04:47:57.342757 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10105 04:47:57.355915 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10106 04:47:57.362282 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10107 04:47:57.369418 <6>[ 0.009176] Console: colour dummy device 80x25
10108 04:47:57.378608 <6>[ 0.013924] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10109 04:47:57.385625 <6>[ 0.024366] pid_max: default: 32768 minimum: 301
10110 04:47:57.388552 <6>[ 0.029237] LSM: Security Framework initializing
10111 04:47:57.394981 <6>[ 0.034179] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10112 04:47:57.405452 <6>[ 0.041785] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10113 04:47:57.411836 <6>[ 0.051005] cblist_init_generic: Setting adjustable number of callback queues.
10114 04:47:57.418156 <6>[ 0.058448] cblist_init_generic: Setting shift to 3 and lim to 1.
10115 04:47:57.428218 <6>[ 0.064786] cblist_init_generic: Setting adjustable number of callback queues.
10116 04:47:57.432628 <6>[ 0.072213] cblist_init_generic: Setting shift to 3 and lim to 1.
10117 04:47:57.438408 <6>[ 0.078652] rcu: Hierarchical SRCU implementation.
10118 04:47:57.445042 <6>[ 0.078654] rcu: Max phase no-delay instances is 1000.
10119 04:47:57.451538 <6>[ 0.078678] printk: bootconsole [mtk8250] printing thread started
10120 04:47:57.458746 <6>[ 0.097029] EFI services will not be available.
10121 04:47:57.461921 <6>[ 0.097231] smp: Bringing up secondary CPUs ...
10122 04:47:57.465054 <6>[ 0.097542] Detected VIPT I-cache on CPU1
10123 04:47:57.474335 <6>[ 0.097609] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10124 04:47:57.482959 <6>[ 0.097638] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10125 04:47:57.490405 <6>[ 0.125512] Detected VIPT I-cache on CPU2
10126 04:47:57.496654 <6>[ 0.125557] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10127 04:47:57.503905 <6>[ 0.125573] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10128 04:47:57.510128 <6>[ 0.125827] Detected VIPT I-cache on CPU3
10129 04:47:57.516179 <6>[ 0.125872] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10130 04:47:57.523025 <6>[ 0.125886] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10131 04:47:57.526209 <6>[ 0.126193] CPU features: detected: Spectre-v4
10132 04:47:57.532891 <6>[ 0.126200] CPU features: detected: Spectre-BHB
10133 04:47:57.536404 <6>[ 0.126204] Detected PIPT I-cache on CPU4
10134 04:47:57.543249 <6>[ 0.126263] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10135 04:47:57.549817 <6>[ 0.126279] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10136 04:47:57.552903 <6>[ 0.126569] Detected PIPT I-cache on CPU5
10137 04:47:57.562617 <6>[ 0.126628] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10138 04:47:57.569494 <6>[ 0.126644] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10139 04:47:57.575627 <6>[ 0.126917] Detected PIPT I-cache on CPU6
10140 04:47:57.582382 <6>[ 0.126979] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10141 04:47:57.588847 <6>[ 0.126995] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10142 04:47:57.592586 <6>[ 0.127289] Detected PIPT I-cache on CPU7
10143 04:47:57.599978 <6>[ 0.127353] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10144 04:47:57.605579 <6>[ 0.127369] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10145 04:47:57.613252 <6>[ 0.127415] smp: Brought up 1 node, 8 CPUs
10146 04:47:57.615101 <6>[ 0.127420] SMP: Total of 8 processors activated.
10147 04:47:57.621820 <6>[ 0.127423] CPU features: detected: 32-bit EL0 Support
10148 04:47:57.628777 <6>[ 0.127425] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10149 04:47:57.635863 <6>[ 0.127428] CPU features: detected: Common not Private translations
10150 04:47:57.642035 <6>[ 0.127429] CPU features: detected: CRC32 instructions
10151 04:47:57.648195 <6>[ 0.127432] CPU features: detected: RCpc load-acquire (LDAPR)
10152 04:47:57.655710 <6>[ 0.127433] CPU features: detected: LSE atomic instructions
10153 04:47:57.657822 <6>[ 0.127435] CPU features: detected: Privileged Access Never
10154 04:47:57.665043 <6>[ 0.127437] CPU features: detected: RAS Extension Support
10155 04:47:57.671123 <6>[ 0.127439] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10156 04:47:57.697873 x6>[ 0.127502] CPU: All CPU(s) started at EL2
10157 04:47:57.704250 <6>[ 0.342160] prin<tk: console [ttyS0] printing thread started
10158 04:47:57.707038 6>[ <6>[ 0.342174] printk: console [ttyS0] enabled
10159 04:47:57.714053 0.127503] alternatives: applying system-wide alternatives
10160 04:47:57.720657 <6>[ 0.342177] printk: bootconsole [mtk8250] disabled
10161 04:47:57.727628 <6>[ 0.358266] printk: bootconsole [mtk8250] printing thread stopped
10162 04:47:57.730403 <6>[ 0.359312] SuperH (H)SCI(F) driver initialized
10163 04:47:57.733436 <6>[ 0.359790] msm_serial: driver initialized
10164 04:47:57.743685 <6>[ 0.364344] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10165 04:47:57.753446 <6>[ 0.364372] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10166 04:47:57.760238 <6>[ 0.364401] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10167 04:47:57.775457 <6>[ 0.364430] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10168 04:47:57.779535 <6>[ 0.364451] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10169 04:47:57.803476 <6>[ 0.364478] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10170 04:47:57.804774 <6>[ 0.364506] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10171 04:47:57.810115 <6>[ 0.364627] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10172 04:47:57.817379 <6>[ 0.364657] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10173 04:47:57.817939 <6>[ 0.374925] loop: module loaded
10174 04:47:57.823169 <6>[ 0.377495] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10175 04:47:57.826154 <4>[ 0.394279] mtk-pmic-keys: Failed to locate of_node [id: -1]
10176 04:47:57.833212 <6>[ 0.395055] megasas: 07.719.03.00-rc1
10177 04:47:57.839850 <6>[ 0.407439] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10178 04:47:57.843067 <6>[ 0.407501] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10179 04:47:57.849357 <6>[ 0.419328] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10180 04:47:57.859593 <6>[ 0.471567] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10181 04:47:58.319498 <6>[ 0.959739] Freeing initrd memory: 17380K
10182 04:47:58.327999 <6>[ 0.965971] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10183 04:47:58.334621 <6>[ 0.970549] tun: Universal TUN/TAP device driver, 1.6
10184 04:47:58.337528 <6>[ 0.971291] thunder_xcv, ver 1.0
10185 04:47:58.340929 <6>[ 0.971308] thunder_bgx, ver 1.0
10186 04:47:58.344632 <6>[ 0.971323] nicpf, ver 1.0
10187 04:47:58.351027 <6>[ 0.972387] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10188 04:47:58.357559 <6>[ 0.972390] hns3: Copyright (c) 2017 Huawei Corporation.
10189 04:47:58.361193 <6>[ 0.972416] hclge is initializing
10190 04:47:58.368024 <6>[ 0.972433] e1000: Intel(R) PRO/1000 Network Driver
10191 04:47:58.371053 <6>[ 0.972435] e1000: Copyright (c) 1999-2006 Intel Corporation.
10192 04:47:58.377958 <6>[ 0.972451] e1000e: Intel(R) PRO/1000 Network Driver
10193 04:47:58.384471 <6>[ 0.972452] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10194 04:47:58.387734 <6>[ 0.972467] igb: Intel(R) Gigabit Ethernet Network Driver
10195 04:47:58.394933 <6>[ 0.972469] igb: Copyright (c) 2007-2014 Intel Corporation.
10196 04:47:58.401438 <6>[ 0.972483] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10197 04:47:58.408240 <6>[ 0.972485] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10198 04:47:58.411907 <6>[ 0.972793] sky2: driver version 1.30
10199 04:47:58.415471 <6>[ 0.973854] VFIO - User Level meta-driver version: 0.3
10200 04:47:58.421811 <6>[ 0.976634] usbcore: registered new interface driver usb-storage
10201 04:47:58.429168 <6>[ 0.976812] usbcore: registered new device driver onboard-usb-hub
10202 04:47:58.435639 <6>[ 0.979573] mt6397-rtc mt6359-rtc: registered as rtc0
10203 04:47:58.441811 <6>[ 0.979726] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-04T04:47:58 UTC (1707022078)
10204 04:47:58.448804 <6>[ 0.980342] i2c_dev: i2c /dev entries driver
10205 04:47:58.455498 <6>[ 0.987362] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10206 04:47:58.462295 <6>[ 1.002334] cpu cpu0: EM: created perf domain
10207 04:47:58.465297 <6>[ 1.002622] cpu cpu4: EM: created perf domain
10208 04:47:58.472230 <6>[ 1.006243] sdhci: Secure Digital Host Controller Interface driver
10209 04:47:58.474871 <6>[ 1.006245] sdhci: Copyright(c) Pierre Ossman
10210 04:47:58.481788 <6>[ 1.006562] Synopsys Designware Multimedia Card Interface Driver
10211 04:47:58.488432 <6>[ 1.006891] sdhci-pltfm: SDHCI platform and OF driver helper
10212 04:47:58.491506 <6>[ 1.011522] mmc0: CQHCI version 5.10
10213 04:47:58.498204 <6>[ 1.017427] ledtrig-cpu: registered to indicate activity on CPUs
10214 04:47:58.504247 <6>[ 1.018175] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10215 04:47:58.512382 <6>[ 1.018421] usbcore: registered new interface driver usbhid
10216 04:47:58.514442 <6>[ 1.018422] usbhid: USB HID core driver
10217 04:47:58.521411 <6>[ 1.018550] spi_master spi0: will run message pump with realtime priority
10218 04:47:58.534679 <6>[ 1.046275] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10219 04:47:58.547909 <6>[ 1.048634] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10220 04:47:58.555206 <6>[ 1.049773] cros-ec-spi spi0.0: Chrome EC device registered
10221 04:47:58.564279 <6>[ 1.061484] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10222 04:47:58.567922 <6>[ 1.062332] NET: Registered PF_PACKET protocol family
10223 04:47:58.575056 <6>[ 1.062412] 9pnet: Installing 9P2000 support
10224 04:47:58.577939 <5>[ 1.062444] Key type dns_resolver registered
10225 04:47:58.580627 <6>[ 1.062769] registered taskstats version 1
10226 04:47:58.587899 <5>[ 1.062784] Loading compiled-in X.509 certificates
10227 04:47:58.597769 <4>[ 1.077485] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10228 04:47:58.607198 <4>[ 1.077666] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10229 04:47:58.614233 <3>[ 1.077680] debugfs: File 'uA_load' in directory '/' already present!
10230 04:47:58.620575 <3>[ 1.077689] debugfs: File 'min_uV' in directory '/' already present!
10231 04:47:58.627412 <3>[ 1.077694] debugfs: File 'max_uV' in directory '/' already present!
10232 04:47:58.633310 <3>[ 1.077699] debugfs: File 'constraint_flags' in directory '/' already present!
10233 04:47:58.643661 <3>[ 1.079554] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10234 04:47:58.649882 <6>[ 1.086551] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10235 04:47:58.656991 <6>[ 1.087214] xhci-mtk 11200000.usb: xHCI Host Controller
10236 04:47:58.664213 <6>[ 1.087230] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10237 04:47:58.673670 <6>[ 1.087442] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10238 04:47:58.679600 <6>[ 1.087482] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10239 04:47:58.682982 <6>[ 1.087583] xhci-mtk 11200000.usb: xHCI Host Controller
10240 04:47:58.692827 <6>[ 1.087590] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10241 04:47:58.699922 <6>[ 1.087597] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10242 04:47:58.703411 <6>[ 1.088081] hub 1-0:1.0: USB hub found
10243 04:47:58.706401 <6>[ 1.088124] hub 1-0:1.0: 1 port detected
10244 04:47:58.716362 <6>[ 1.088480] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10245 04:47:58.719944 <6>[ 1.088910] hub 2-0:1.0: USB hub found
10246 04:47:58.723070 <6>[ 1.088935] hub 2-0:1.0: 1 port detected
10247 04:47:58.730133 <6>[ 1.091595] mtk-msdc 11f70000.mmc: Got CD GPIO
10248 04:47:58.733166 <6>[ 1.106053] mmc0: Command Queue Engine enabled
10249 04:47:58.739751 <6>[ 1.106066] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10250 04:47:58.746067 <6>[ 1.106550] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10251 04:47:58.756543 <6>[ 1.106559] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10252 04:47:58.759911 <6>[ 1.106642] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10253 04:47:58.769861 <4>[ 1.106730] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10254 04:47:58.776339 <6>[ 1.107361] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10255 04:47:58.786160 <6>[ 1.107364] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10256 04:47:58.792410 <6>[ 1.107524] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10257 04:47:58.799210 <6>[ 1.107540] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10258 04:47:58.809229 <6>[ 1.107545] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10259 04:47:58.819522 <6>[ 1.107551] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10260 04:47:58.825634 <6>[ 1.109650] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10261 04:47:58.835663 <6>[ 1.109669] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10262 04:47:58.842217 <6>[ 1.109676] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10263 04:47:58.852171 <6>[ 1.109683] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10264 04:47:58.859113 <6>[ 1.109689] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10265 04:47:58.868599 <6>[ 1.109698] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10266 04:47:58.874838 <6>[ 1.109705] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10267 04:47:58.885014 <6>[ 1.109711] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10268 04:47:58.891682 <6>[ 1.109718] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10269 04:47:58.902149 <6>[ 1.109725] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10270 04:47:58.908792 <6>[ 1.109731] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10271 04:47:58.918038 <6>[ 1.109738] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10272 04:47:58.924602 <6>[ 1.109745] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10273 04:47:58.934695 <6>[ 1.109751] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10274 04:47:58.941395 <6>[ 1.109757] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10275 04:47:58.947702 <6>[ 1.109942] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10276 04:47:58.954374 <6>[ 1.110384] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10277 04:47:58.961179 <6>[ 1.111122] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10278 04:47:58.967611 <6>[ 1.111390] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10279 04:47:58.971287 <6>[ 1.111790] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10280 04:47:58.977991 <6>[ 1.112588] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10281 04:47:58.984045 <6>[ 1.112684] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10282 04:47:58.990731 <6>[ 1.113261] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10283 04:47:58.997462 <6>[ 1.113903] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10284 04:47:59.007139 <6>[ 1.114090] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10285 04:47:59.017956 <6>[ 1.114109] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10286 04:47:59.027105 <6>[ 1.114120] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10287 04:47:59.037227 <6>[ 1.114127] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10288 04:47:59.043525 <6>[ 1.114133] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10289 04:47:59.053504 <6>[ 1.114139] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10290 04:47:59.063975 <6>[ 1.114146] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10291 04:47:59.073253 <6>[ 1.114151] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10292 04:47:59.082988 <6>[ 1.114157] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10293 04:47:59.093468 <6>[ 1.114168] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10294 04:47:59.102765 <6>[ 1.114174] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10295 04:47:59.110283 <6>[ 1.114796] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10296 04:47:59.117086 <6>[ 1.127401] Trying to probe devices needed for running init ...
10297 04:47:59.122352 <6>[ 1.512082] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10298 04:47:59.126130 <6>[ 1.664708] hub 1-1:1.0: USB hub found
10299 04:47:59.133619 <6>[ 1.665100] hub 1-1:1.0: 4 ports detected
10300 04:47:59.136285 <6>[ 1.669363] hub 1-1:1.0: USB hub found
10301 04:47:59.139675 <6>[ 1.669752] hub 1-1:1.0: 4 ports detected
10302 04:47:59.158702 <6>[ 1.792400] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10303 04:47:59.179671 <6>[ 1.818082] hub 2-1:1.0: USB hub found
10304 04:47:59.182820 <6>[ 1.818543] hub 2-1:1.0: 3 ports detected
10305 04:47:59.185832 <6>[ 1.822162] hub 2-1:1.0: USB hub found
10306 04:47:59.189332 <6>[ 1.822556] hub 2-1:1.0: 3 ports detected
10307 04:47:59.347356 <6>[ 1.980306] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10308 04:47:59.467772 <6>[ 2.107864] hub 1-1.4:1.0: USB hub found
10309 04:47:59.471044 <6>[ 2.108291] hub 1-1.4:1.0: 2 ports detected
10310 04:47:59.474554 <6>[ 2.110968] hub 1-1.4:1.0: USB hub found
10311 04:47:59.481290 <6>[ 2.111296] hub 1-1.4:1.0: 2 ports detected
10312 04:47:59.550981 <6>[ 2.184460] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10313 04:47:59.766975 <6>[ 2.400285] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10314 04:47:59.950851 <6>[ 2.584291] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10315 04:48:10.767182 <6>[ 13.409352] ALSA device list:
10316 04:48:10.774046 <6>[ 13.409374] No soundcards found.
10317 04:48:10.777462 <6>[ 13.413707] Freeing unused kernel memory: 8448K
10318 04:48:10.780791 <6>[ 13.413874] Run /init as init process
10319 04:48:10.783416 Loading, please wait...
10320 04:48:10.803686 Starting version 247.3-7+deb11u2
10321 04:48:10.989732 <6>[ 13.626310] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10322 04:48:11.005307 <6>[ 13.641638] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10323 04:48:11.012584 <6>[ 13.641713] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10324 04:48:11.021893 <6>[ 13.641724] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10325 04:48:11.028944 <6>[ 13.653065] remoteproc remoteproc0: scp is available
10326 04:48:11.032073 <6>[ 13.653189] remoteproc remoteproc0: powering up scp
10327 04:48:11.042699 <6>[ 13.653197] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10328 04:48:11.049670 <6>[ 13.653230] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10329 04:48:11.056407 <3>[ 13.675281] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10330 04:48:11.065571 <3>[ 13.675293] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10331 04:48:11.072394 <3>[ 13.675296] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10332 04:48:11.079097 <4>[ 13.681636] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10333 04:48:11.089464 <4>[ 13.702273] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10334 04:48:11.095285 <3>[ 13.702598] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10335 04:48:11.102091 <3>[ 13.702607] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10336 04:48:11.112691 <3>[ 13.702611] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10337 04:48:11.119380 <3>[ 13.702615] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10338 04:48:11.126270 <3>[ 13.702617] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10339 04:48:11.136644 <3>[ 13.703736] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10340 04:48:11.143794 <3>[ 13.712168] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10341 04:48:11.153286 <3>[ 13.712209] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10342 04:48:11.159999 <3>[ 13.712218] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10343 04:48:11.169379 <3>[ 13.713106] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10344 04:48:11.176225 <3>[ 13.713134] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10345 04:48:11.183051 <3>[ 13.713142] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10346 04:48:11.193045 <3>[ 13.713153] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10347 04:48:11.199383 <3>[ 13.713164] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10348 04:48:11.208901 <3>[ 13.714084] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10349 04:48:11.216209 <6>[ 13.717081] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10350 04:48:11.222450 <6>[ 13.717281] mc: Linux media interface: v0.10
10351 04:48:11.225995 <6>[ 13.727651] usbcore: registered new device driver r8152-cfgselector
10352 04:48:11.235816 <4>[ 13.741505] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10353 04:48:11.242227 <4>[ 13.741505] Fallback method does not support PEC.
10354 04:48:11.250124 <3>[ 13.756982] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10355 04:48:11.257252 <6>[ 13.761369] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10356 04:48:11.262399 <6>[ 13.761376] pci_bus 0000:00: root bus resource [bus 00-ff]
10357 04:48:11.269550 <6>[ 13.761380] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10358 04:48:11.278783 <6>[ 13.761382] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10359 04:48:11.285004 <6>[ 13.761403] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10360 04:48:11.292043 <6>[ 13.761415] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10361 04:48:11.298894 <6>[ 13.761476] pci 0000:00:00.0: supports D1 D2
10362 04:48:11.305453 <6>[ 13.761477] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10363 04:48:11.311918 <6>[ 13.762511] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10364 04:48:11.318625 <6>[ 13.762611] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10365 04:48:11.324823 <6>[ 13.762636] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10366 04:48:11.334971 <6>[ 13.762650] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10367 04:48:11.341510 <6>[ 13.762665] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10368 04:48:11.345050 <6>[ 13.762768] pci 0000:01:00.0: supports D1 D2
10369 04:48:11.351605 <6>[ 13.762769] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10370 04:48:11.361005 <6>[ 13.776073] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10371 04:48:11.368326 <6>[ 13.776111] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10372 04:48:11.374421 <6>[ 13.776114] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10373 04:48:11.384835 <6>[ 13.776123] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10374 04:48:11.391507 <6>[ 13.776135] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10375 04:48:11.401675 <6>[ 13.776147] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10376 04:48:11.404602 <6>[ 13.776159] pci 0000:00:00.0: PCI bridge to [bus 01]
10377 04:48:11.414437 <6>[ 13.776164] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10378 04:48:11.420635 <6>[ 13.776353] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10379 04:48:11.424391 <6>[ 13.776880] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10380 04:48:11.430656 <6>[ 13.777141] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10381 04:48:11.440235 <3>[ 13.777468] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10382 04:48:11.447136 <6>[ 13.778444] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10383 04:48:11.457813 <6>[ 13.782898] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10384 04:48:11.460572 <6>[ 13.782910] remoteproc remoteproc0: remote processor scp is now up
10385 04:48:11.470006 <6>[ 13.808543] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10386 04:48:11.481795 <6>[ 13.812484] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10387 04:48:11.491598 <6>[ 13.821128] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10388 04:48:11.500903 <6>[ 13.821458] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10389 04:48:11.506484 <4>[ 13.832002] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10390 04:48:11.516386 <4>[ 13.832013] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10391 04:48:11.523316 <6>[ 13.840895] videodev: Linux video capture interface: v2.00
10392 04:48:11.529742 <6>[ 13.843112] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10393 04:48:11.536466 <5>[ 13.843248] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10394 04:48:11.546402 <6>[ 13.844176] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10395 04:48:11.552953 <5>[ 13.861327] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10396 04:48:11.562759 <5>[ 13.861532] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10397 04:48:11.569417 <4>[ 13.861589] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10398 04:48:11.575687 <6>[ 13.861594] cfg80211: failed to load regulatory.db
10399 04:48:11.579021 <6>[ 13.863888] Bluetooth: Core ver 2.22
10400 04:48:11.585944 <6>[ 13.864142] NET: Registered PF_BLUETOOTH protocol family
10401 04:48:11.592524 <6>[ 13.864153] Bluetooth: HCI device and connection manager initialized
10402 04:48:11.596177 <6>[ 13.864227] Bluetooth: HCI socket layer initialized
10403 04:48:11.602580 <6>[ 13.864256] Bluetooth: L2CAP socket layer initialized
10404 04:48:11.606614 <6>[ 13.864300] Bluetooth: SCO socket layer initialized
10405 04:48:11.613859 <6>[ 13.884095] r8152 2-1.3:1.0 eth0: v1.12.13
10406 04:48:11.618272 <6>[ 13.884179] usbcore: registered new interface driver r8152
10407 04:48:11.621790 <6>[ 13.905205] usbcore: registered new interface driver cdc_ether
10408 04:48:11.628507 <6>[ 13.917166] usbcore: registered new interface driver r8153_ecm
10409 04:48:11.635107 <6>[ 13.918871] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10410 04:48:11.648996 <6>[ 13.920085] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10411 04:48:11.655483 <6>[ 13.920294] usbcore: registered new interface driver uvcvideo
10412 04:48:11.662091 <6>[ 13.932814] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10413 04:48:11.664660 <6>[ 13.933778] usbcore: registered new interface driver btusb
10414 04:48:11.675540 <4>[ 13.934807] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10415 04:48:11.681486 <3>[ 13.934814] Bluetooth: hci0: Failed to load firmware file (-2)
10416 04:48:11.687959 <3>[ 13.934817] Bluetooth: hci0: Failed to set up firmware (-2)
10417 04:48:11.698248 <4>[ 13.934819] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10418 04:48:11.705133 <6>[ 13.960874] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10419 04:48:11.711070 <6>[ 13.972515] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10420 04:48:11.718555 <6>[ 13.972607] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10421 04:48:11.724609 <6>[ 13.992150] mt7921e 0000:01:00.0: ASIC revision: 79610010
10422 04:48:11.735889 <6>[ 14.090758] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10423 04:48:11.736419 <6>[ 14.090758]
10424 04:48:11.744612 <6>[ 14.350835] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10425 04:48:11.748055 Begin: Loading essential drivers ... done.
10426 04:48:11.752050 Begin: Running /scripts/init-premount ... done.
10427 04:48:11.757747 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10428 04:48:11.767716 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10429 04:48:11.770847 Device /sys/class/net/enx00e04c6803bd found
10430 04:48:11.771373 done.
10431 04:48:11.857403 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10432 04:48:12.549656 <6>[ 15.187971] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10433 04:48:12.917505 <6>[ 15.556771] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10434 04:48:13.837656 IP-Config: no response after 2 secs - giving up
10435 04:48:13.874202 IP-Config: wlp1s0 hardware address 74:4c:a1:92:35:3b mtu 1500 DHCP
10436 04:48:14.596913 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10437 04:48:14.603865 IP-Config: enx00e04c6803bd complete (dhcp from 192.168.201.1):
10438 04:48:14.610261 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10439 04:48:14.617273 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10440 04:48:14.623320 host : mt8192-asurada-spherion-r0-cbg-4
10441 04:48:14.629851 domain : lava-rack
10442 04:48:14.633579 rootserver: 192.168.201.1 rootpath:
10443 04:48:14.634115 filename :
10444 04:48:14.718470 done.
10445 04:48:14.726072 Begin: Running /scripts/nfs-bottom ... done.
10446 04:48:14.744828 Begin: Running /scripts/init-bottom ... done.
10447 04:48:15.966602 <6>[ 18.605283] NET: Registered PF_INET6 protocol family
10448 04:48:15.970107 <6>[ 18.607454] Segment Routing with IPv6
10449 04:48:15.976201 <6>[ 18.607483] In-situ OAM (IOAM) with IPv6
10450 04:48:16.093779 <30>[ 18.715010] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10451 04:48:16.096863 <30>[ 18.716064] systemd[1]: Detected architecture arm64.
10452 04:48:16.097339
10453 04:48:16.103354 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10454 04:48:16.103921
10455 04:48:16.122171 <30>[ 18.763192] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10456 04:48:17.040998 <30>[ 19.679332] systemd[1]: Queued start job for default target Graphical Interface.
10457 04:48:17.072211 [[0;32m OK [<30>[ 19.710850] systemd[1]: Created slice system-getty.slice.
10458 04:48:17.075539 0m] Created slice [0;1;39msystem-getty.slice[0m.
10459 04:48:17.094285 [[0;32m OK [0m] Created slic<30>[ 19.733787] systemd[1]: Created slice system-modprobe.slice.
10460 04:48:17.098051 e [0;1;39msystem-modprobe.slice[0m.
10461 04:48:17.118771 [[0;32m OK [0m] Created slic<30>[ 19.757675] systemd[1]: Created slice system-serial\x2dgetty.slice.
10462 04:48:17.124527 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10463 04:48:17.143456 [[0;32m OK [0m] Created slic<30>[ 19.782175] systemd[1]: Created slice User and Session Slice.
10464 04:48:17.146560 e [0;1;39mUser and Session Slice[0m.
10465 04:48:17.170057 [[0;32m OK [0m] Started [0;<30>[ 19.805140] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10466 04:48:17.173236 1;39mDispatch Password …ts to Console Directory Watch[0m.
10467 04:48:17.197883 [[0;32m OK [0m] Started [0;<30>[ 19.833112] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10468 04:48:17.200355 1;39mForward Password R…uests to Wall Directory Watch[0m.
10469 04:48:17.228625 [[0;32m OK [0m] Reached targ<30>[ 19.860876] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10470 04:48:17.236503 <30>[ 19.861181] systemd[1]: Reached target Local Encrypted Volumes.
10471 04:48:17.238431 et [0;1;39mLocal Encrypted Volumes[0m.
10472 04:48:17.257372 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 19.896473] systemd[1]: Reached target Paths.
10473 04:48:17.257931 s[0m.
10474 04:48:17.280540 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 19.916310] systemd[1]: Reached target Remote File Systems.
10475 04:48:17.281275 te File Systems[0m.
10476 04:48:17.301627 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 19.940569] systemd[1]: Reached target Slices.
10477 04:48:17.302193 es[0m.
10478 04:48:17.321640 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 19.960339] systemd[1]: Reached target Swap.
10479 04:48:17.322214 [0m.
10480 04:48:17.344631 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 19.980858] systemd[1]: Listening on initctl Compatibility Named Pipe.
10481 04:48:17.347914 l Compatibility Named Pipe[0m.
10482 04:48:17.358839 [[0;32m OK [0m] Listening on<30>[ 19.997281] systemd[1]: Listening on Journal Audit Socket.
10483 04:48:17.361030 [0;1;39mJournal Audit Socket[0m.
10484 04:48:17.383787 [[0;32m OK [0m] Listening on<30>[ 20.021967] systemd[1]: Listening on Journal Socket (/dev/log).
10485 04:48:17.385735 [0;1;39mJournal Socket (/dev/log)[0m.
10486 04:48:17.406954 [[0;32m OK [0m] Listening on<30>[ 20.045636] systemd[1]: Listening on Journal Socket.
10487 04:48:17.409500 [0;1;39mJournal Socket[0m.
10488 04:48:17.427356 [[0;32m OK [0m] Listening on<30>[ 20.066216] systemd[1]: Listening on Network Service Netlink Socket.
10489 04:48:17.433905 [0;1;39mNetwork Service Netlink Socket[0m.
10490 04:48:17.453719 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 20.092677] systemd[1]: Listening on udev Control Socket.
10491 04:48:17.457540 ontrol Socket[0m.
10492 04:48:17.477647 [[0;32m OK [0m] Listening on [0;1;39mudev K<30>[ 20.116911] systemd[1]: Listening on udev Kernel Socket.
10493 04:48:17.480883 ernel Socket[0m.
10494 04:48:17.528223 Mounting [0;1;39mHuge Pages File Syste<30>[ 20.164417] systemd[1]: Mounting Huge Pages File System...
10495 04:48:17.528812 m[0m...
10496 04:48:17.545885 <30>[ 20.187818] systemd[1]: Mounting POSIX Message Queue File System...
10497 04:48:17.551577 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10498 04:48:17.578413 Mounting [0;1;39mKerne<30>[ 20.217904] systemd[1]: Mounting Kernel Debug File System...
10499 04:48:17.581915 l Debug File System[0m...
10500 04:48:17.604680 <30>[ 20.241293] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10501 04:48:17.697219 Starting [0;1;39mCreate list of st…o<30>[ 20.332825] systemd[1]: Starting Create list of static device nodes for the current kernel...
10502 04:48:17.700352 des for the current kernel[0m...
10503 04:48:17.730339 Starting [0;1;39mLoad <30>[ 20.369425] systemd[1]: Starting Load Kernel Module configfs...
10504 04:48:17.733512 Kernel Module configfs[0m...
10505 04:48:17.758548 Starting [0;1;39mLoad <30>[ 20.397396] systemd[1]: Starting Load Kernel Module drm...
10506 04:48:17.761458 Kernel Module drm[0m...
10507 04:48:17.784673 Starting [0;1;39mLoad Kernel Module fu<30>[ 20.420554] systemd[1]: Starting Load Kernel Module fuse...
10508 04:48:17.785281 se[0m...
10509 04:48:17.809138 <30>[ 20.445859] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10510 04:48:17.829319 <6>[ 20.470153] fuse: init (API version 7.37)
10511 04:48:17.859412 Starting [0;1;39mJourn<30>[ 20.497234] systemd[1]: Starting Journal Service...
10512 04:48:17.859984 al Service[0m...
10513 04:48:17.889909 Starting [0;1;39mLoad Kernel Modules[<30>[ 20.529115] systemd[1]: Starting Load Kernel Modules...
10514 04:48:17.893180 0m...
10515 04:48:17.918382 Starting [0;1;39mRemou<30>[ 20.557659] systemd[1]: Starting Remount Root and Kernel File Systems...
10516 04:48:17.925137 nt Root and Kernel File Systems[0m...
10517 04:48:17.981946 Starting [0;1;39mColdp<30>[ 20.621238] systemd[1]: Starting Coldplug All udev Devices...
10518 04:48:17.985677 lug All udev Devices[0m...
10519 04:48:18.000856 <3>[ 20.639042] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10520 04:48:18.018171 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages <30>[ 20.656696] systemd[1]: Mounted Huge Pages File System.
10521 04:48:18.027690 File System[0m.<3>[ 20.666227] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10522 04:48:18.028167
10523 04:48:18.054634 [[0;32m OK [0m] Mounted [0;<30>[ 20.693579] systemd[1]: Mounted POSIX Message Queue File System.
10524 04:48:18.065518 1;39mPOSIX Messa<3>[ 20.695170] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10525 04:48:18.068600 ge Queue File System[0m.
10526 04:48:18.078523 <3>[ 20.715285] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10527 04:48:18.086371 [[0;32m OK [0m] Mounted [0;<30>[ 20.725616] systemd[1]: Mounted Kernel Debug File System.
10528 04:48:18.095736 1;39mKernel Debu<3>[ 20.734054] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10529 04:48:18.099164 g File System[0m.
10530 04:48:18.117350 <3>[ 20.755397] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10531 04:48:18.127077 <30>[ 20.758908] systemd[1]: Finished Create list of static device nodes for the current kernel.
10532 04:48:18.137505 [[0;32m OK [0m] Finished [0<3>[ 20.775405] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10533 04:48:18.143605 ;1;39mCreate list of st… nodes for the current kernel[0m.
10534 04:48:18.160301 <3>[ 20.796704] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10535 04:48:18.172981 [[0;32m OK [<30>[ 20.810158] systemd[1]: modprobe@configfs.service: Succeeded.
10536 04:48:18.175111 <30>[ 20.810830] systemd[1]: Finished Load Kernel Module configfs.
10537 04:48:18.185291 <3>[ 20.817358] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10538 04:48:18.191392 0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10539 04:48:18.204652 <3>[ 20.840896] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10540 04:48:18.213570 <30>[ 20.855049] systemd[1]: modprobe@drm.service: Succeeded.
10541 04:48:18.221462 <30>[ 20.856679] systemd[1]: Finished Load Kernel Module drm.
10542 04:48:18.226886 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10543 04:48:18.248386 [[0;32m OK [<30>[ 20.885648] systemd[1]: modprobe@fuse.service: Succeeded.
10544 04:48:18.251598 <30>[ 20.887045] systemd[1]: Finished Load Kernel Module fuse.
10545 04:48:18.257982 0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10546 04:48:18.281796 [[0;32m OK [0m] Started [0;1;39mJournal Ser<30>[ 20.920907] systemd[1]: Started Journal Service.
10547 04:48:18.284684 vice[0m.
10548 04:48:18.301832 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10549 04:48:18.323477 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10550 04:48:18.390049 Mounting [0;1;39mFUSE Control File System[0m...
10551 04:48:18.410106 Mounting [0;1;39mKernel Configuration File System[0m...
10552 04:48:18.440694 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10553 04:48:18.496171 <46>[ 21.135827] systemd-journald[306]: Received client request to flush runtime journal.
10554 04:48:18.503359 Starting [0;1;39mLoad/Save Random Seed[0m...
10555 04:48:18.521025 Starting [0;1;39mApply Kernel Variables[0m...
10556 04:48:18.537270 <4>[ 21.166009] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10557 04:48:18.543876 <3>[ 21.166022] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10558 04:48:18.646071 Starting [0;1;39mCreate System Users[0m...
10559 04:48:18.671527 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10560 04:48:18.684693 See 'systemctl status systemd-udev-trigger.service' for details.
10561 04:48:18.702017 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10562 04:48:18.717770 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10563 04:48:19.257605 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10564 04:48:19.620680 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10565 04:48:19.947220 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10566 04:48:19.978770 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10567 04:48:20.031111 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10568 04:48:20.116460 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10569 04:48:20.130094 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10570 04:48:20.146176 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10571 04:48:20.194623 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10572 04:48:20.223217 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10573 04:48:20.420914 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10574 04:48:20.475569 Starting [0;1;39mNetwork Service[0m...
10575 04:48:20.583702 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10576 04:48:20.701616 Starting [0;1;39mNetwork Time Synchronization[0m...
10577 04:48:20.724025 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10578 04:48:20.834195 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10579 04:48:20.862396 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10580 04:48:20.923843 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10581 04:48:21.136493 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10582 04:48:21.157009 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10583 04:48:21.173677 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10584 04:48:21.208069 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10585 04:48:21.254205 Starting [0;1;39mNetwork Name Resolution[0m...
10586 04:48:21.273923 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10587 04:48:21.295182 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10588 04:48:21.309702 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10589 04:48:21.325567 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10590 04:48:21.345965 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10591 04:48:21.365702 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10592 04:48:21.377940 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10593 04:48:21.397908 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10594 04:48:21.446383 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10595 04:48:21.500512 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10596 04:48:21.522961 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10597 04:48:21.544162 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10598 04:48:21.557832 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10599 04:48:21.580949 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10600 04:48:21.593667 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10601 04:48:21.614132 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10602 04:48:21.668334 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10603 04:48:21.789098 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10604 04:48:21.908462 Starting [0;1;39mUser Login Management[0m...
10605 04:48:22.123786 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10606 04:48:22.139186 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10607 04:48:22.158922 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10608 04:48:22.201458 Starting [0;1;39mPermit User Sessions[0m...
10609 04:48:22.224781 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10610 04:48:22.270339 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10611 04:48:22.315702 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10612 04:48:22.377350 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10613 04:48:22.383826 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10614 04:48:22.398025 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10615 04:48:22.414127 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10616 04:48:22.429523 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10617 04:48:22.471735 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10618 04:48:22.528162 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10619 04:48:22.607503
10620 04:48:22.607673
10621 04:48:22.611234 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10622 04:48:22.611414
10623 04:48:22.613865 debian-bullseye-arm64 login: root (automatic login)
10624 04:48:22.613998
10625 04:48:22.614099
10626 04:48:22.991633 Linux debian-bullseye-arm64 6.1.75-cip14-rt8 #1 SMP PREEMPT Sun Feb 4 04:24:19 UTC 2024 aarch64
10627 04:48:22.992121
10628 04:48:22.998577 The programs included with the Debian GNU/Linux system are free software;
10629 04:48:23.004926 the exact distribution terms for each program are described in the
10630 04:48:23.008109 individual files in /usr/share/doc/*/copyright.
10631 04:48:23.008526
10632 04:48:23.014294 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10633 04:48:23.017727 permitted by applicable law.
10634 04:48:23.865428 Matched prompt #10: / #
10636 04:48:23.866787 Setting prompt string to ['/ #']
10637 04:48:23.867311 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10639 04:48:23.868411 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10640 04:48:23.868947 start: 2.2.6 expect-shell-connection (timeout 00:03:27) [common]
10641 04:48:23.869328 Setting prompt string to ['/ #']
10642 04:48:23.869711 Forcing a shell prompt, looking for ['/ #']
10644 04:48:23.920686 / #
10645 04:48:23.921325 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10646 04:48:23.921735 Waiting using forced prompt support (timeout 00:02:30)
10647 04:48:23.927126
10648 04:48:23.927977 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10649 04:48:23.928787 start: 2.2.7 export-device-env (timeout 00:03:27) [common]
10651 04:48:24.030267 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12699848/extract-nfsrootfs-7j02hjaw'
10652 04:48:24.037124 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12699848/extract-nfsrootfs-7j02hjaw'
10654 04:48:24.138600 / # export NFS_SERVER_IP='192.168.201.1'
10655 04:48:24.145802 export NFS_SERVER_IP='192.168.201.1'
10656 04:48:24.146748 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10657 04:48:24.147303 end: 2.2 depthcharge-retry (duration 00:01:33) [common]
10658 04:48:24.147821 end: 2 depthcharge-action (duration 00:01:33) [common]
10659 04:48:24.148348 start: 3 lava-test-retry (timeout 00:07:44) [common]
10660 04:48:24.148893 start: 3.1 lava-test-shell (timeout 00:07:44) [common]
10661 04:48:24.149320 Using namespace: common
10663 04:48:24.250689 / # #
10664 04:48:24.251346 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10665 04:48:24.258149 #
10666 04:48:24.259092 Using /lava-12699848
10668 04:48:24.360510 / # export SHELL=/bin/bash
10669 04:48:24.367828 export SHELL=/bin/bash
10671 04:48:24.469503 / # . /lava-12699848/environment
10672 04:48:24.475044 . /lava-12699848/environment
10674 04:48:24.581720 / # /lava-12699848/bin/lava-test-runner /lava-12699848/0
10675 04:48:24.582326 Test shell timeout: 10s (minimum of the action and connection timeout)
10676 04:48:24.588456 /lava-12699848/bin/lava-test-runner /lava-12699848/0
10677 04:48:24.874163 + export TESTRUN_ID=0_timesync-off
10678 04:48:24.876260 + TESTRUN_ID=0_timesync-off
10679 04:48:24.879193 + cd /lava-12699848/0/tests/0_timesync-off
10680 04:48:24.882890 ++ cat uuid
10681 04:48:24.886051 + UUID=12699848_1.6.2.3.1
10682 04:48:24.886591 + set +x
10683 04:48:24.892081 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12699848_1.6.2.3.1>
10684 04:48:24.892793 Received signal: <STARTRUN> 0_timesync-off 12699848_1.6.2.3.1
10685 04:48:24.893187 Starting test lava.0_timesync-off (12699848_1.6.2.3.1)
10686 04:48:24.893761 Skipping test definition patterns.
10687 04:48:24.895513 + systemctl stop systemd-timesyncd
10688 04:48:24.958385 + set +x
10689 04:48:24.961960 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12699848_1.6.2.3.1>
10690 04:48:24.962654 Received signal: <ENDRUN> 0_timesync-off 12699848_1.6.2.3.1
10691 04:48:24.963090 Ending use of test pattern.
10692 04:48:24.963415 Ending test lava.0_timesync-off (12699848_1.6.2.3.1), duration 0.07
10694 04:48:25.031064 + export TESTRUN_ID=1_kselftest-dt
10695 04:48:25.035636 + TESTRUN_ID=1_kselftest-dt
10696 04:48:25.037599 + cd /lava-12699848/0/tests/1_kselftest-dt
10697 04:48:25.040964 ++ cat uuid
10698 04:48:25.041074 + UUID=12699848_1.6.2.3.5
10699 04:48:25.044008 + set +x
10700 04:48:25.047656 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 12699848_1.6.2.3.5>
10701 04:48:25.047941 Received signal: <STARTRUN> 1_kselftest-dt 12699848_1.6.2.3.5
10702 04:48:25.048039 Starting test lava.1_kselftest-dt (12699848_1.6.2.3.5)
10703 04:48:25.048153 Skipping test definition patterns.
10704 04:48:25.050541 + cd ./automated/linux/kselftest/
10705 04:48:25.080247 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10706 04:48:25.106882 INFO: install_deps skipped
10707 04:48:25.226236 --2024-02-04 04:48:25-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10708 04:48:25.233826 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10709 04:48:25.362333 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10710 04:48:25.491505 HTTP request sent, awaiting response... 200 OK
10711 04:48:25.494374 Length: 2966368 (2.8M) [application/octet-stream]
10712 04:48:25.498020 Saving to: 'kselftest.tar.xz'
10713 04:48:25.498389
10714 04:48:25.498626
10715 04:48:25.750645 kselftest.tar.xz 0%[ ] 0 --.-KB/s
10716 04:48:26.009227 kselftest.tar.xz 1%[ ] 47.81K 188KB/s
10717 04:48:26.315895 kselftest.tar.xz 7%[> ] 217.50K 427KB/s
10718 04:48:26.583326 kselftest.tar.xz 28%[====> ] 815.64K 1004KB/s
10719 04:48:26.785906 kselftest.tar.xz 66%[============> ] 1.88M 1.75MB/s
10720 04:48:26.792899 kselftest.tar.xz 99%[==================> ] 2.82M 2.21MB/s
10721 04:48:26.798477 kselftest.tar.xz 100%[===================>] 2.83M 2.21MB/s in 1.3s
10722 04:48:26.798558
10723 04:48:27.057652 2024-02-04 04:48:27 (2.21 MB/s) - 'kselftest.tar.xz' saved [2966368/2966368]
10724 04:48:27.057807
10725 04:48:33.022399 skiplist:
10726 04:48:33.025183 ========================================
10727 04:48:33.028750 ========================================
10728 04:48:33.099778 ============== Tests to run ===============
10729 04:48:33.103518 ===========End Tests to run ===============
10730 04:48:33.109295 shardfile-dt fail
10731 04:48:33.135064 ./kselftest.sh: 131: cannot open /lava-12699848/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
10732 04:48:33.138974 + ../../utils/send-to-lava.sh ./output/result.txt
10733 04:48:33.211823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
10734 04:48:33.212549 + set +x
10735 04:48:33.213366 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
10737 04:48:33.218569 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 12699848_1.6.2.3.5>
10738 04:48:33.219256 Received signal: <ENDRUN> 1_kselftest-dt 12699848_1.6.2.3.5
10739 04:48:33.219627 Ending use of test pattern.
10740 04:48:33.219987 Ending test lava.1_kselftest-dt (12699848_1.6.2.3.5), duration 8.17
10742 04:48:33.221275 ok: lava_test_shell seems to have completed
10743 04:48:33.221798 shardfile-dt: fail
10744 04:48:33.222284 end: 3.1 lava-test-shell (duration 00:00:09) [common]
10745 04:48:33.222744 end: 3 lava-test-retry (duration 00:00:09) [common]
10746 04:48:33.223225 start: 4 finalize (timeout 00:07:35) [common]
10747 04:48:33.223729 start: 4.1 power-off (timeout 00:00:30) [common]
10748 04:48:33.224537 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
10749 04:48:33.352872 >> Command sent successfully.
10750 04:48:33.364957 Returned 0 in 0 seconds
10751 04:48:33.466367 end: 4.1 power-off (duration 00:00:00) [common]
10753 04:48:33.467930 start: 4.2 read-feedback (timeout 00:07:35) [common]
10755 04:48:33.470358 Listened to connection for namespace 'common' for up to 1s
10756 04:48:34.468962 Finalising connection for namespace 'common'
10757 04:48:34.469776 Disconnecting from shell: Finalise
10758 04:48:34.470275 / #
10759 04:48:34.571323 end: 4.2 read-feedback (duration 00:00:01) [common]
10760 04:48:34.572064 end: 4 finalize (duration 00:00:01) [common]
10761 04:48:34.572687 Cleaning after the job
10762 04:48:34.573306 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699848/tftp-deploy-qzgrpv7l/ramdisk
10763 04:48:34.588128 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699848/tftp-deploy-qzgrpv7l/kernel
10764 04:48:34.623271 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699848/tftp-deploy-qzgrpv7l/dtb
10765 04:48:34.623551 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699848/tftp-deploy-qzgrpv7l/nfsrootfs
10766 04:48:34.717902 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699848/tftp-deploy-qzgrpv7l/modules
10767 04:48:34.725242 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12699848
10768 04:48:35.361317 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12699848
10769 04:48:35.361505 Job finished correctly