Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 1
- Kernel Warnings: 15
- Kernel Errors: 27
1 04:49:57.636160 lava-dispatcher, installed at version: 2023.10
2 04:49:57.636507 start: 0 validate
3 04:49:57.636696 Start time: 2024-02-04 04:49:57.636687+00:00 (UTC)
4 04:49:57.636852 Using caching service: 'http://localhost/cache/?uri=%s'
5 04:49:57.637032 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 04:49:57.895670 Using caching service: 'http://localhost/cache/?uri=%s'
7 04:49:57.895872 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 04:49:58.161181 Using caching service: 'http://localhost/cache/?uri=%s'
9 04:49:58.161351 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 04:49:58.426017 Using caching service: 'http://localhost/cache/?uri=%s'
11 04:49:58.426197 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-132-g6e54756fbd6c2%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 04:49:58.693299 validate duration: 1.06
14 04:49:58.693581 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 04:49:58.693677 start: 1.1 download-retry (timeout 00:10:00) [common]
16 04:49:58.693767 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 04:49:58.693890 Not decompressing ramdisk as can be used compressed.
18 04:49:58.694004 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 04:49:58.694091 saving as /var/lib/lava/dispatcher/tmp/12699854/tftp-deploy-u2wxkg8_/ramdisk/rootfs.cpio.gz
20 04:49:58.694161 total size: 26246609 (25 MB)
21 04:49:58.695247 progress 0 % (0 MB)
22 04:49:58.702687 progress 5 % (1 MB)
23 04:49:58.709879 progress 10 % (2 MB)
24 04:49:58.716868 progress 15 % (3 MB)
25 04:49:58.723819 progress 20 % (5 MB)
26 04:49:58.730875 progress 25 % (6 MB)
27 04:49:58.737860 progress 30 % (7 MB)
28 04:49:58.744818 progress 35 % (8 MB)
29 04:49:58.751881 progress 40 % (10 MB)
30 04:49:58.759136 progress 45 % (11 MB)
31 04:49:58.766413 progress 50 % (12 MB)
32 04:49:58.773630 progress 55 % (13 MB)
33 04:49:58.780938 progress 60 % (15 MB)
34 04:49:58.787853 progress 65 % (16 MB)
35 04:49:58.794853 progress 70 % (17 MB)
36 04:49:58.801985 progress 75 % (18 MB)
37 04:49:58.808995 progress 80 % (20 MB)
38 04:49:58.815889 progress 85 % (21 MB)
39 04:49:58.822680 progress 90 % (22 MB)
40 04:49:58.829463 progress 95 % (23 MB)
41 04:49:58.836257 progress 100 % (25 MB)
42 04:49:58.836570 25 MB downloaded in 0.14 s (175.76 MB/s)
43 04:49:58.836729 end: 1.1.1 http-download (duration 00:00:00) [common]
45 04:49:58.836981 end: 1.1 download-retry (duration 00:00:00) [common]
46 04:49:58.837067 start: 1.2 download-retry (timeout 00:10:00) [common]
47 04:49:58.837151 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 04:49:58.837289 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 04:49:58.837363 saving as /var/lib/lava/dispatcher/tmp/12699854/tftp-deploy-u2wxkg8_/kernel/Image
50 04:49:58.837424 total size: 51597824 (49 MB)
51 04:49:58.837485 No compression specified
52 04:49:58.838610 progress 0 % (0 MB)
53 04:49:58.852061 progress 5 % (2 MB)
54 04:49:58.866075 progress 10 % (4 MB)
55 04:49:58.879863 progress 15 % (7 MB)
56 04:49:58.893798 progress 20 % (9 MB)
57 04:49:58.907626 progress 25 % (12 MB)
58 04:49:58.921463 progress 30 % (14 MB)
59 04:49:58.939591 progress 35 % (17 MB)
60 04:49:58.956537 progress 40 % (19 MB)
61 04:49:58.970128 progress 45 % (22 MB)
62 04:49:58.983802 progress 50 % (24 MB)
63 04:49:58.997408 progress 55 % (27 MB)
64 04:49:59.010908 progress 60 % (29 MB)
65 04:49:59.024706 progress 65 % (32 MB)
66 04:49:59.038396 progress 70 % (34 MB)
67 04:49:59.052396 progress 75 % (36 MB)
68 04:49:59.066668 progress 80 % (39 MB)
69 04:49:59.080688 progress 85 % (41 MB)
70 04:49:59.094316 progress 90 % (44 MB)
71 04:49:59.107553 progress 95 % (46 MB)
72 04:49:59.120898 progress 100 % (49 MB)
73 04:49:59.121114 49 MB downloaded in 0.28 s (173.46 MB/s)
74 04:49:59.121266 end: 1.2.1 http-download (duration 00:00:00) [common]
76 04:49:59.121518 end: 1.2 download-retry (duration 00:00:00) [common]
77 04:49:59.121626 start: 1.3 download-retry (timeout 00:10:00) [common]
78 04:49:59.121714 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 04:49:59.121855 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 04:49:59.121925 saving as /var/lib/lava/dispatcher/tmp/12699854/tftp-deploy-u2wxkg8_/dtb/mt8192-asurada-spherion-r0.dtb
81 04:49:59.121986 total size: 47278 (0 MB)
82 04:49:59.122048 No compression specified
83 04:49:59.123226 progress 69 % (0 MB)
84 04:49:59.123516 progress 100 % (0 MB)
85 04:49:59.123692 0 MB downloaded in 0.00 s (26.49 MB/s)
86 04:49:59.123836 end: 1.3.1 http-download (duration 00:00:00) [common]
88 04:49:59.124059 end: 1.3 download-retry (duration 00:00:00) [common]
89 04:49:59.124143 start: 1.4 download-retry (timeout 00:10:00) [common]
90 04:49:59.124224 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 04:49:59.124381 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-132-g6e54756fbd6c2/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 04:49:59.124454 saving as /var/lib/lava/dispatcher/tmp/12699854/tftp-deploy-u2wxkg8_/modules/modules.tar
93 04:49:59.124516 total size: 8633524 (8 MB)
94 04:49:59.124578 Using unxz to decompress xz
95 04:49:59.128763 progress 0 % (0 MB)
96 04:49:59.150836 progress 5 % (0 MB)
97 04:49:59.177231 progress 10 % (0 MB)
98 04:49:59.203727 progress 15 % (1 MB)
99 04:49:59.230746 progress 20 % (1 MB)
100 04:49:59.256906 progress 25 % (2 MB)
101 04:49:59.286835 progress 30 % (2 MB)
102 04:49:59.313176 progress 35 % (2 MB)
103 04:49:59.338752 progress 40 % (3 MB)
104 04:49:59.365078 progress 45 % (3 MB)
105 04:49:59.392339 progress 50 % (4 MB)
106 04:49:59.418263 progress 55 % (4 MB)
107 04:49:59.446319 progress 60 % (4 MB)
108 04:49:59.473800 progress 65 % (5 MB)
109 04:49:59.500966 progress 70 % (5 MB)
110 04:49:59.525026 progress 75 % (6 MB)
111 04:49:59.554018 progress 80 % (6 MB)
112 04:49:59.583007 progress 85 % (7 MB)
113 04:49:59.611994 progress 90 % (7 MB)
114 04:49:59.643937 progress 95 % (7 MB)
115 04:49:59.674986 progress 100 % (8 MB)
116 04:49:59.681145 8 MB downloaded in 0.56 s (14.79 MB/s)
117 04:49:59.681413 end: 1.4.1 http-download (duration 00:00:01) [common]
119 04:49:59.681688 end: 1.4 download-retry (duration 00:00:01) [common]
120 04:49:59.681781 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 04:49:59.681874 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 04:49:59.681956 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 04:49:59.682047 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 04:49:59.682268 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh
125 04:49:59.682408 makedir: /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh/lava-12699854/bin
126 04:49:59.682515 makedir: /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh/lava-12699854/tests
127 04:49:59.682616 makedir: /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh/lava-12699854/results
128 04:49:59.682734 Creating /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh/lava-12699854/bin/lava-add-keys
129 04:49:59.682885 Creating /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh/lava-12699854/bin/lava-add-sources
130 04:49:59.683019 Creating /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh/lava-12699854/bin/lava-background-process-start
131 04:49:59.683150 Creating /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh/lava-12699854/bin/lava-background-process-stop
132 04:49:59.683316 Creating /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh/lava-12699854/bin/lava-common-functions
133 04:49:59.683443 Creating /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh/lava-12699854/bin/lava-echo-ipv4
134 04:49:59.683572 Creating /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh/lava-12699854/bin/lava-install-packages
135 04:49:59.683698 Creating /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh/lava-12699854/bin/lava-installed-packages
136 04:49:59.683825 Creating /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh/lava-12699854/bin/lava-os-build
137 04:49:59.683952 Creating /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh/lava-12699854/bin/lava-probe-channel
138 04:49:59.684078 Creating /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh/lava-12699854/bin/lava-probe-ip
139 04:49:59.684207 Creating /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh/lava-12699854/bin/lava-target-ip
140 04:49:59.684410 Creating /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh/lava-12699854/bin/lava-target-mac
141 04:49:59.684565 Creating /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh/lava-12699854/bin/lava-target-storage
142 04:49:59.684702 Creating /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh/lava-12699854/bin/lava-test-case
143 04:49:59.684833 Creating /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh/lava-12699854/bin/lava-test-event
144 04:49:59.684962 Creating /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh/lava-12699854/bin/lava-test-feedback
145 04:49:59.685091 Creating /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh/lava-12699854/bin/lava-test-raise
146 04:49:59.685221 Creating /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh/lava-12699854/bin/lava-test-reference
147 04:49:59.685350 Creating /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh/lava-12699854/bin/lava-test-runner
148 04:49:59.685478 Creating /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh/lava-12699854/bin/lava-test-set
149 04:49:59.685609 Creating /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh/lava-12699854/bin/lava-test-shell
150 04:49:59.685740 Updating /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh/lava-12699854/bin/lava-install-packages (oe)
151 04:49:59.685897 Updating /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh/lava-12699854/bin/lava-installed-packages (oe)
152 04:49:59.686022 Creating /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh/lava-12699854/environment
153 04:49:59.686123 LAVA metadata
154 04:49:59.686198 - LAVA_JOB_ID=12699854
155 04:49:59.686263 - LAVA_DISPATCHER_IP=192.168.201.1
156 04:49:59.686367 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 04:49:59.686433 skipped lava-vland-overlay
158 04:49:59.686506 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 04:49:59.686585 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 04:49:59.686650 skipped lava-multinode-overlay
161 04:49:59.686723 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 04:49:59.686815 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 04:49:59.686895 Loading test definitions
164 04:49:59.686986 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 04:49:59.687062 Using /lava-12699854 at stage 0
166 04:49:59.687374 uuid=12699854_1.5.2.3.1 testdef=None
167 04:49:59.687471 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 04:49:59.687556 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 04:49:59.688084 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 04:49:59.688338 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 04:49:59.689022 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 04:49:59.689255 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 04:49:59.689854 runner path: /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh/lava-12699854/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 12699854_1.5.2.3.1
176 04:49:59.690014 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 04:49:59.690222 Creating lava-test-runner.conf files
179 04:49:59.690285 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12699854/lava-overlay-w01w6ulh/lava-12699854/0 for stage 0
180 04:49:59.690377 - 0_v4l2-compliance-mtk-vcodec-enc
181 04:49:59.690477 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 04:49:59.690568 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 04:49:59.697421 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 04:49:59.697527 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 04:49:59.697617 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 04:49:59.697707 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 04:49:59.697796 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 04:50:00.452209 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 04:50:00.452636 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 04:50:00.452756 extracting modules file /var/lib/lava/dispatcher/tmp/12699854/tftp-deploy-u2wxkg8_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12699854/extract-overlay-ramdisk-7zrhysua/ramdisk
191 04:50:00.728182 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 04:50:00.728431 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 04:50:00.728534 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12699854/compress-overlay-wob3_5cm/overlay-1.5.2.4.tar.gz to ramdisk
194 04:50:00.728628 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12699854/compress-overlay-wob3_5cm/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12699854/extract-overlay-ramdisk-7zrhysua/ramdisk
195 04:50:00.735180 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 04:50:00.735292 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 04:50:00.735384 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 04:50:00.735474 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 04:50:00.735554 Building ramdisk /var/lib/lava/dispatcher/tmp/12699854/extract-overlay-ramdisk-7zrhysua/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12699854/extract-overlay-ramdisk-7zrhysua/ramdisk
200 04:50:01.372108 >> 228465 blocks
201 04:50:05.331946 rename /var/lib/lava/dispatcher/tmp/12699854/extract-overlay-ramdisk-7zrhysua/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12699854/tftp-deploy-u2wxkg8_/ramdisk/ramdisk.cpio.gz
202 04:50:05.332387 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 04:50:05.332511 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 04:50:05.332641 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 04:50:05.332765 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12699854/tftp-deploy-u2wxkg8_/kernel/Image'
206 04:50:18.194698 Returned 0 in 12 seconds
207 04:50:18.295402 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12699854/tftp-deploy-u2wxkg8_/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12699854/tftp-deploy-u2wxkg8_/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12699854/tftp-deploy-u2wxkg8_/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12699854/tftp-deploy-u2wxkg8_/kernel/image.itb
208 04:50:18.935666 output: FIT description: Kernel Image image with one or more FDT blobs
209 04:50:18.936079 output: Created: Sun Feb 4 04:50:18 2024
210 04:50:18.936192 output: Image 0 (kernel-1)
211 04:50:18.936322 output: Description:
212 04:50:18.936437 output: Created: Sun Feb 4 04:50:18 2024
213 04:50:18.936548 output: Type: Kernel Image
214 04:50:18.936652 output: Compression: lzma compressed
215 04:50:18.936751 output: Data Size: 12048508 Bytes = 11766.12 KiB = 11.49 MiB
216 04:50:18.936850 output: Architecture: AArch64
217 04:50:18.936929 output: OS: Linux
218 04:50:18.937025 output: Load Address: 0x00000000
219 04:50:18.937118 output: Entry Point: 0x00000000
220 04:50:18.937213 output: Hash algo: crc32
221 04:50:18.937307 output: Hash value: 3b31d50c
222 04:50:18.937401 output: Image 1 (fdt-1)
223 04:50:18.937494 output: Description: mt8192-asurada-spherion-r0
224 04:50:18.937586 output: Created: Sun Feb 4 04:50:18 2024
225 04:50:18.937678 output: Type: Flat Device Tree
226 04:50:18.937773 output: Compression: uncompressed
227 04:50:18.937864 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 04:50:18.937955 output: Architecture: AArch64
229 04:50:18.938085 output: Hash algo: crc32
230 04:50:18.938175 output: Hash value: cc4352de
231 04:50:18.938266 output: Image 2 (ramdisk-1)
232 04:50:18.938356 output: Description: unavailable
233 04:50:18.938446 output: Created: Sun Feb 4 04:50:18 2024
234 04:50:18.938576 output: Type: RAMDisk Image
235 04:50:18.938666 output: Compression: Unknown Compression
236 04:50:18.938755 output: Data Size: 39360925 Bytes = 38438.40 KiB = 37.54 MiB
237 04:50:18.938846 output: Architecture: AArch64
238 04:50:18.938936 output: OS: Linux
239 04:50:18.939026 output: Load Address: unavailable
240 04:50:18.939116 output: Entry Point: unavailable
241 04:50:18.939231 output: Hash algo: crc32
242 04:50:18.939334 output: Hash value: 31beb4ce
243 04:50:18.939424 output: Default Configuration: 'conf-1'
244 04:50:18.939513 output: Configuration 0 (conf-1)
245 04:50:18.939619 output: Description: mt8192-asurada-spherion-r0
246 04:50:18.939723 output: Kernel: kernel-1
247 04:50:18.939813 output: Init Ramdisk: ramdisk-1
248 04:50:18.939903 output: FDT: fdt-1
249 04:50:18.939992 output: Loadables: kernel-1
250 04:50:18.940082 output:
251 04:50:18.940371 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 04:50:18.940512 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 04:50:18.940661 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 04:50:18.940800 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
255 04:50:18.940911 No LXC device requested
256 04:50:18.941033 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 04:50:18.941158 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
258 04:50:18.941273 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 04:50:18.941377 Checking files for TFTP limit of 4294967296 bytes.
260 04:50:18.942035 end: 1 tftp-deploy (duration 00:00:20) [common]
261 04:50:18.942176 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 04:50:18.942303 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 04:50:18.942480 substitutions:
264 04:50:18.942579 - {DTB}: 12699854/tftp-deploy-u2wxkg8_/dtb/mt8192-asurada-spherion-r0.dtb
265 04:50:18.942683 - {INITRD}: 12699854/tftp-deploy-u2wxkg8_/ramdisk/ramdisk.cpio.gz
266 04:50:18.942780 - {KERNEL}: 12699854/tftp-deploy-u2wxkg8_/kernel/Image
267 04:50:18.942876 - {LAVA_MAC}: None
268 04:50:18.942971 - {PRESEED_CONFIG}: None
269 04:50:18.943065 - {PRESEED_LOCAL}: None
270 04:50:18.943158 - {RAMDISK}: 12699854/tftp-deploy-u2wxkg8_/ramdisk/ramdisk.cpio.gz
271 04:50:18.943252 - {ROOT_PART}: None
272 04:50:18.943346 - {ROOT}: None
273 04:50:18.943439 - {SERVER_IP}: 192.168.201.1
274 04:50:18.943531 - {TEE}: None
275 04:50:18.943624 Parsed boot commands:
276 04:50:18.943716 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 04:50:18.943950 Parsed boot commands: tftpboot 192.168.201.1 12699854/tftp-deploy-u2wxkg8_/kernel/image.itb 12699854/tftp-deploy-u2wxkg8_/kernel/cmdline
278 04:50:18.944078 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 04:50:18.944207 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 04:50:18.944383 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 04:50:18.944510 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 04:50:18.944619 Not connected, no need to disconnect.
283 04:50:18.944735 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 04:50:18.944856 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 04:50:18.944956 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 04:50:18.949388 Setting prompt string to ['lava-test: # ']
287 04:50:18.949799 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 04:50:18.949925 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 04:50:18.950091 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 04:50:18.950275 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 04:50:18.950607 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 04:50:24.087372 >> Command sent successfully.
293 04:50:24.090441 Returned 0 in 5 seconds
294 04:50:24.190814 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 04:50:24.191167 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 04:50:24.191283 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 04:50:24.191411 Setting prompt string to 'Starting depthcharge on Spherion...'
299 04:50:24.191487 Changing prompt to 'Starting depthcharge on Spherion...'
300 04:50:24.191577 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 04:50:24.191962 [Enter `^Ec?' for help]
302 04:50:24.362406
303 04:50:24.362644
304 04:50:24.362800 F0: 102B 0000
305 04:50:24.362948
306 04:50:24.363090 F3: 1001 0000 [0200]
307 04:50:24.363235
308 04:50:24.366426 F3: 1001 0000
309 04:50:24.366590
310 04:50:24.366736 F7: 102D 0000
311 04:50:24.366874
312 04:50:24.367014 F1: 0000 0000
313 04:50:24.369905
314 04:50:24.370063 V0: 0000 0000 [0001]
315 04:50:24.370212
316 04:50:24.370353 00: 0007 8000
317 04:50:24.370502
318 04:50:24.374023 01: 0000 0000
319 04:50:24.374188
320 04:50:24.374336 BP: 0C00 0209 [0000]
321 04:50:24.374480
322 04:50:24.377556 G0: 1182 0000
323 04:50:24.377716
324 04:50:24.377862 EC: 0000 0021 [4000]
325 04:50:24.378004
326 04:50:24.380955 S7: 0000 0000 [0000]
327 04:50:24.381113
328 04:50:24.381257 CC: 0000 0000 [0001]
329 04:50:24.381398
330 04:50:24.384339 T0: 0000 0040 [010F]
331 04:50:24.384505
332 04:50:24.384655 Jump to BL
333 04:50:24.384798
334 04:50:24.409061
335 04:50:24.409286
336 04:50:24.409440
337 04:50:24.416825 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 04:50:24.420792 ARM64: Exception handlers installed.
339 04:50:24.424496 ARM64: Testing exception
340 04:50:24.428362 ARM64: Done test exception
341 04:50:24.431785 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 04:50:24.442967 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 04:50:24.449894 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 04:50:24.460385 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 04:50:24.466517 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 04:50:24.476568 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 04:50:24.487947 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 04:50:24.494310 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 04:50:24.511877 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 04:50:24.515430 WDT: Last reset was cold boot
351 04:50:24.519099 SPI1(PAD0) initialized at 2873684 Hz
352 04:50:24.521980 SPI5(PAD0) initialized at 992727 Hz
353 04:50:24.525454 VBOOT: Loading verstage.
354 04:50:24.531900 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 04:50:24.536491 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 04:50:24.539832 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 04:50:24.543403 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 04:50:24.549814 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 04:50:24.556453 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 04:50:24.566943 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 04:50:24.567129
362 04:50:24.567279
363 04:50:24.577679 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 04:50:24.580791 ARM64: Exception handlers installed.
365 04:50:24.584015 ARM64: Testing exception
366 04:50:24.584129 ARM64: Done test exception
367 04:50:24.590461 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 04:50:24.594195 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 04:50:24.608453 Probing TPM: . done!
370 04:50:24.608590 TPM ready after 0 ms
371 04:50:24.615000 Connected to device vid:did:rid of 1ae0:0028:00
372 04:50:24.622027 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 04:50:24.681279 Initialized TPM device CR50 revision 0
374 04:50:24.692745 tlcl_send_startup: Startup return code is 0
375 04:50:24.692956 TPM: setup succeeded
376 04:50:24.704119 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 04:50:24.713222 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 04:50:24.727477 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 04:50:24.734324 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 04:50:24.737769 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 04:50:24.742015 in-header: 03 07 00 00 08 00 00 00
382 04:50:24.745496 in-data: aa e4 47 04 13 02 00 00
383 04:50:24.748877 Chrome EC: UHEPI supported
384 04:50:24.756443 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 04:50:24.759610 in-header: 03 95 00 00 08 00 00 00
386 04:50:24.763577 in-data: 18 20 20 08 00 00 00 00
387 04:50:24.763747 Phase 1
388 04:50:24.766943 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 04:50:24.774046 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 04:50:24.778043 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 04:50:24.781931 Recovery requested (1009000e)
392 04:50:24.790853 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 04:50:24.795725 tlcl_extend: response is 0
394 04:50:24.805609 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 04:50:24.810930 tlcl_extend: response is 0
396 04:50:24.817840 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 04:50:24.837440 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 04:50:24.844352 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 04:50:24.844527
400 04:50:24.844673
401 04:50:24.854066 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 04:50:24.857397 ARM64: Exception handlers installed.
403 04:50:24.860745 ARM64: Testing exception
404 04:50:24.860895 ARM64: Done test exception
405 04:50:24.883145 pmic_efuse_setting: Set efuses in 11 msecs
406 04:50:24.886853 pmwrap_interface_init: Select PMIF_VLD_RDY
407 04:50:24.893213 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 04:50:24.896606 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 04:50:24.903935 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 04:50:24.907832 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 04:50:24.911173 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 04:50:24.914990 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 04:50:24.922437 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 04:50:24.926727 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 04:50:24.930178 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 04:50:24.934287 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 04:50:24.941730 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 04:50:24.945032 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 04:50:24.948495 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 04:50:24.956483 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 04:50:24.959785 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 04:50:24.967423 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 04:50:24.970876 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 04:50:24.978356 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 04:50:24.985778 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 04:50:24.989597 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 04:50:24.993237 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 04:50:25.000774 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 04:50:25.008069 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 04:50:25.012150 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 04:50:25.015447 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 04:50:25.022752 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 04:50:25.026758 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 04:50:25.034304 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 04:50:25.037782 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 04:50:25.041181 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 04:50:25.048665 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 04:50:25.052134 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 04:50:25.056159 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 04:50:25.063402 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 04:50:25.067283 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 04:50:25.070690 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 04:50:25.078339 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 04:50:25.081786 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 04:50:25.085970 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 04:50:25.092511 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 04:50:25.096206 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 04:50:25.100164 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 04:50:25.104187 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 04:50:25.107860 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 04:50:25.111525 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 04:50:25.119297 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 04:50:25.123326 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 04:50:25.126780 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 04:50:25.130116 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 04:50:25.134046 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 04:50:25.137921 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 04:50:25.144780 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 04:50:25.156155 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 04:50:25.159474 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 04:50:25.167085 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 04:50:25.174344 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 04:50:25.181331 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 04:50:25.185633 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 04:50:25.188352 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 04:50:25.196677 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x34
467 04:50:25.200594 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 04:50:25.208638 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 04:50:25.211696 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 04:50:25.220902 [RTC]rtc_get_frequency_meter,154: input=15, output=759
471 04:50:25.230584 [RTC]rtc_get_frequency_meter,154: input=23, output=942
472 04:50:25.239889 [RTC]rtc_get_frequency_meter,154: input=19, output=850
473 04:50:25.249762 [RTC]rtc_get_frequency_meter,154: input=17, output=805
474 04:50:25.259474 [RTC]rtc_get_frequency_meter,154: input=16, output=781
475 04:50:25.268460 [RTC]rtc_get_frequency_meter,154: input=16, output=781
476 04:50:25.278634 [RTC]rtc_get_frequency_meter,154: input=17, output=805
477 04:50:25.282109 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 04:50:25.285439 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 04:50:25.292602 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 04:50:25.296141 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 04:50:25.300210 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 04:50:25.303816 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 04:50:25.307977 ADC[4]: Raw value=906573 ID=7
484 04:50:25.308096 ADC[3]: Raw value=213810 ID=1
485 04:50:25.311265 RAM Code: 0x71
486 04:50:25.314744 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 04:50:25.322066 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 04:50:25.329783 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 04:50:25.337087 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 04:50:25.341077 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 04:50:25.344455 in-header: 03 07 00 00 08 00 00 00
492 04:50:25.344562 in-data: aa e4 47 04 13 02 00 00
493 04:50:25.348405 Chrome EC: UHEPI supported
494 04:50:25.355651 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 04:50:25.359305 in-header: 03 95 00 00 08 00 00 00
496 04:50:25.363097 in-data: 18 20 20 08 00 00 00 00
497 04:50:25.366476 MRC: failed to locate region type 0.
498 04:50:25.370603 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 04:50:25.374134 DRAM-K: Running full calibration
500 04:50:25.381749 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 04:50:25.381913 header.status = 0x0
502 04:50:25.385231 header.version = 0x6 (expected: 0x6)
503 04:50:25.389339 header.size = 0xd00 (expected: 0xd00)
504 04:50:25.392878 header.flags = 0x0
505 04:50:25.396048 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 04:50:25.415244 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 04:50:25.423347 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 04:50:25.423475 dram_init: ddr_geometry: 2
509 04:50:25.427449 [EMI] MDL number = 2
510 04:50:25.427561 [EMI] Get MDL freq = 0
511 04:50:25.430878 dram_init: ddr_type: 0
512 04:50:25.430956 is_discrete_lpddr4: 1
513 04:50:25.434775 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 04:50:25.434874
515 04:50:25.434942
516 04:50:25.438528 [Bian_co] ETT version 0.0.0.1
517 04:50:25.442275 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 04:50:25.442361
519 04:50:25.450027 dramc_set_vcore_voltage set vcore to 650000
520 04:50:25.450114 Read voltage for 800, 4
521 04:50:25.450182 Vio18 = 0
522 04:50:25.453491 Vcore = 650000
523 04:50:25.453585 Vdram = 0
524 04:50:25.453653 Vddq = 0
525 04:50:25.453717 Vmddr = 0
526 04:50:25.456890 dram_init: config_dvfs: 1
527 04:50:25.460941 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 04:50:25.468160 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 04:50:25.472025 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 04:50:25.475750 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 04:50:25.479109 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 04:50:25.482955 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 04:50:25.486480 MEM_TYPE=3, freq_sel=18
534 04:50:25.489082 sv_algorithm_assistance_LP4_1600
535 04:50:25.492470 ============ PULL DRAM RESETB DOWN ============
536 04:50:25.496005 ========== PULL DRAM RESETB DOWN end =========
537 04:50:25.500163 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 04:50:25.503365 ===================================
539 04:50:25.507395 LPDDR4 DRAM CONFIGURATION
540 04:50:25.510852 ===================================
541 04:50:25.510945 EX_ROW_EN[0] = 0x0
542 04:50:25.514396 EX_ROW_EN[1] = 0x0
543 04:50:25.514513 LP4Y_EN = 0x0
544 04:50:25.517856 WORK_FSP = 0x0
545 04:50:25.517959 WL = 0x2
546 04:50:25.521355 RL = 0x2
547 04:50:25.521468 BL = 0x2
548 04:50:25.524676 RPST = 0x0
549 04:50:25.524788 RD_PRE = 0x0
550 04:50:25.528126 WR_PRE = 0x1
551 04:50:25.528234 WR_PST = 0x0
552 04:50:25.531363 DBI_WR = 0x0
553 04:50:25.531475 DBI_RD = 0x0
554 04:50:25.534790 OTF = 0x1
555 04:50:25.538208 ===================================
556 04:50:25.541673 ===================================
557 04:50:25.541800 ANA top config
558 04:50:25.545032 ===================================
559 04:50:25.549486 DLL_ASYNC_EN = 0
560 04:50:25.549571 ALL_SLAVE_EN = 1
561 04:50:25.553068 NEW_RANK_MODE = 1
562 04:50:25.556393 DLL_IDLE_MODE = 1
563 04:50:25.559479 LP45_APHY_COMB_EN = 1
564 04:50:25.562583 TX_ODT_DIS = 1
565 04:50:25.562695 NEW_8X_MODE = 1
566 04:50:25.566483 ===================================
567 04:50:25.570023 ===================================
568 04:50:25.573431 data_rate = 1600
569 04:50:25.576876 CKR = 1
570 04:50:25.579997 DQ_P2S_RATIO = 8
571 04:50:25.583266 ===================================
572 04:50:25.583378 CA_P2S_RATIO = 8
573 04:50:25.587178 DQ_CA_OPEN = 0
574 04:50:25.590269 DQ_SEMI_OPEN = 0
575 04:50:25.593337 CA_SEMI_OPEN = 0
576 04:50:25.597248 CA_FULL_RATE = 0
577 04:50:25.599925 DQ_CKDIV4_EN = 1
578 04:50:25.600060 CA_CKDIV4_EN = 1
579 04:50:25.603589 CA_PREDIV_EN = 0
580 04:50:25.606994 PH8_DLY = 0
581 04:50:25.610387 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 04:50:25.613437 DQ_AAMCK_DIV = 4
583 04:50:25.616799 CA_AAMCK_DIV = 4
584 04:50:25.616898 CA_ADMCK_DIV = 4
585 04:50:25.620191 DQ_TRACK_CA_EN = 0
586 04:50:25.623688 CA_PICK = 800
587 04:50:25.627137 CA_MCKIO = 800
588 04:50:25.630275 MCKIO_SEMI = 0
589 04:50:25.634387 PLL_FREQ = 3068
590 04:50:25.634508 DQ_UI_PI_RATIO = 32
591 04:50:25.637920 CA_UI_PI_RATIO = 0
592 04:50:25.641913 ===================================
593 04:50:25.646265 ===================================
594 04:50:25.646378 memory_type:LPDDR4
595 04:50:25.649868 GP_NUM : 10
596 04:50:25.649980 SRAM_EN : 1
597 04:50:25.654742 MD32_EN : 0
598 04:50:25.657756 ===================================
599 04:50:25.657874 [ANA_INIT] >>>>>>>>>>>>>>
600 04:50:25.660922 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 04:50:25.665389 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 04:50:25.668560 ===================================
603 04:50:25.671779 data_rate = 1600,PCW = 0X7600
604 04:50:25.675021 ===================================
605 04:50:25.678380 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 04:50:25.681832 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 04:50:25.688681 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 04:50:25.692211 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 04:50:25.698308 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 04:50:25.702123 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 04:50:25.702231 [ANA_INIT] flow start
612 04:50:25.705292 [ANA_INIT] PLL >>>>>>>>
613 04:50:25.705404 [ANA_INIT] PLL <<<<<<<<
614 04:50:25.708733 [ANA_INIT] MIDPI >>>>>>>>
615 04:50:25.712144 [ANA_INIT] MIDPI <<<<<<<<
616 04:50:25.715708 [ANA_INIT] DLL >>>>>>>>
617 04:50:25.715793 [ANA_INIT] flow end
618 04:50:25.718410 ============ LP4 DIFF to SE enter ============
619 04:50:25.725258 ============ LP4 DIFF to SE exit ============
620 04:50:25.725385 [ANA_INIT] <<<<<<<<<<<<<
621 04:50:25.728824 [Flow] Enable top DCM control >>>>>
622 04:50:25.731675 [Flow] Enable top DCM control <<<<<
623 04:50:25.735009 Enable DLL master slave shuffle
624 04:50:25.741945 ==============================================================
625 04:50:25.742057 Gating Mode config
626 04:50:25.748455 ==============================================================
627 04:50:25.751983 Config description:
628 04:50:25.758806 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 04:50:25.765388 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 04:50:25.772502 SELPH_MODE 0: By rank 1: By Phase
631 04:50:25.778660 ==============================================================
632 04:50:25.778774 GAT_TRACK_EN = 1
633 04:50:25.782409 RX_GATING_MODE = 2
634 04:50:25.785599 RX_GATING_TRACK_MODE = 2
635 04:50:25.788959 SELPH_MODE = 1
636 04:50:25.792198 PICG_EARLY_EN = 1
637 04:50:25.795611 VALID_LAT_VALUE = 1
638 04:50:25.801889 ==============================================================
639 04:50:25.805279 Enter into Gating configuration >>>>
640 04:50:25.808797 Exit from Gating configuration <<<<
641 04:50:25.812293 Enter into DVFS_PRE_config >>>>>
642 04:50:25.822205 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 04:50:25.825230 Exit from DVFS_PRE_config <<<<<
644 04:50:25.828719 Enter into PICG configuration >>>>
645 04:50:25.832077 Exit from PICG configuration <<<<
646 04:50:25.835599 [RX_INPUT] configuration >>>>>
647 04:50:25.835707 [RX_INPUT] configuration <<<<<
648 04:50:25.842368 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 04:50:25.848742 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 04:50:25.851928 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 04:50:25.858797 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 04:50:25.865744 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 04:50:25.871936 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 04:50:25.875427 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 04:50:25.878949 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 04:50:25.885756 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 04:50:25.888978 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 04:50:25.892191 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 04:50:25.895604 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 04:50:25.899452 ===================================
661 04:50:25.902356 LPDDR4 DRAM CONFIGURATION
662 04:50:25.906128 ===================================
663 04:50:25.909502 EX_ROW_EN[0] = 0x0
664 04:50:25.909614 EX_ROW_EN[1] = 0x0
665 04:50:25.912931 LP4Y_EN = 0x0
666 04:50:25.913046 WORK_FSP = 0x0
667 04:50:25.915725 WL = 0x2
668 04:50:25.915839 RL = 0x2
669 04:50:25.919098 BL = 0x2
670 04:50:25.919213 RPST = 0x0
671 04:50:25.922501 RD_PRE = 0x0
672 04:50:25.922616 WR_PRE = 0x1
673 04:50:25.925984 WR_PST = 0x0
674 04:50:25.926093 DBI_WR = 0x0
675 04:50:25.928866 DBI_RD = 0x0
676 04:50:25.928972 OTF = 0x1
677 04:50:25.932259 ===================================
678 04:50:25.936198 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 04:50:25.942324 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 04:50:25.945845 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 04:50:25.949405 ===================================
682 04:50:25.952790 LPDDR4 DRAM CONFIGURATION
683 04:50:25.956059 ===================================
684 04:50:25.956168 EX_ROW_EN[0] = 0x10
685 04:50:25.959444 EX_ROW_EN[1] = 0x0
686 04:50:25.962758 LP4Y_EN = 0x0
687 04:50:25.962867 WORK_FSP = 0x0
688 04:50:25.966310 WL = 0x2
689 04:50:25.966421 RL = 0x2
690 04:50:25.969158 BL = 0x2
691 04:50:25.969269 RPST = 0x0
692 04:50:25.972451 RD_PRE = 0x0
693 04:50:25.972562 WR_PRE = 0x1
694 04:50:25.975948 WR_PST = 0x0
695 04:50:25.976048 DBI_WR = 0x0
696 04:50:25.979430 DBI_RD = 0x0
697 04:50:25.979556 OTF = 0x1
698 04:50:25.983004 ===================================
699 04:50:25.989089 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 04:50:25.993609 nWR fixed to 40
701 04:50:25.996640 [ModeRegInit_LP4] CH0 RK0
702 04:50:25.996725 [ModeRegInit_LP4] CH0 RK1
703 04:50:25.999714 [ModeRegInit_LP4] CH1 RK0
704 04:50:26.003173 [ModeRegInit_LP4] CH1 RK1
705 04:50:26.003292 match AC timing 13
706 04:50:26.009864 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 04:50:26.013051 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 04:50:26.016752 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 04:50:26.023421 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 04:50:26.026870 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 04:50:26.026954 [EMI DOE] emi_dcm 0
712 04:50:26.033072 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 04:50:26.033155 ==
714 04:50:26.036561 Dram Type= 6, Freq= 0, CH_0, rank 0
715 04:50:26.039470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 04:50:26.039600 ==
717 04:50:26.046563 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 04:50:26.053280 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 04:50:26.061001 [CA 0] Center 36 (6~67) winsize 62
720 04:50:26.064039 [CA 1] Center 36 (6~67) winsize 62
721 04:50:26.067350 [CA 2] Center 34 (4~65) winsize 62
722 04:50:26.070592 [CA 3] Center 34 (4~64) winsize 61
723 04:50:26.073926 [CA 4] Center 33 (3~64) winsize 62
724 04:50:26.077473 [CA 5] Center 32 (3~62) winsize 60
725 04:50:26.077556
726 04:50:26.080790 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 04:50:26.080899
728 04:50:26.083945 [CATrainingPosCal] consider 1 rank data
729 04:50:26.087704 u2DelayCellTimex100 = 270/100 ps
730 04:50:26.090541 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 04:50:26.094218 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 04:50:26.100644 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 04:50:26.104214 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
734 04:50:26.107365 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
735 04:50:26.110510 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
736 04:50:26.110652
737 04:50:26.114289 CA PerBit enable=1, Macro0, CA PI delay=32
738 04:50:26.114404
739 04:50:26.117318 [CBTSetCACLKResult] CA Dly = 32
740 04:50:26.117422 CS Dly: 4 (0~35)
741 04:50:26.117515 ==
742 04:50:26.120724 Dram Type= 6, Freq= 0, CH_0, rank 1
743 04:50:26.127592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 04:50:26.127704 ==
745 04:50:26.131119 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 04:50:26.137175 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 04:50:26.146959 [CA 0] Center 36 (6~67) winsize 62
748 04:50:26.150614 [CA 1] Center 36 (6~67) winsize 62
749 04:50:26.153995 [CA 2] Center 34 (3~65) winsize 63
750 04:50:26.157036 [CA 3] Center 34 (4~64) winsize 61
751 04:50:26.160416 [CA 4] Center 32 (2~63) winsize 62
752 04:50:26.163750 [CA 5] Center 32 (2~63) winsize 62
753 04:50:26.163851
754 04:50:26.166793 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 04:50:26.166877
756 04:50:26.170231 [CATrainingPosCal] consider 2 rank data
757 04:50:26.173462 u2DelayCellTimex100 = 270/100 ps
758 04:50:26.176853 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 04:50:26.183398 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 04:50:26.186666 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 04:50:26.189762 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
762 04:50:26.193702 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
763 04:50:26.196908 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
764 04:50:26.196994
765 04:50:26.200505 CA PerBit enable=1, Macro0, CA PI delay=32
766 04:50:26.200615
767 04:50:26.203256 [CBTSetCACLKResult] CA Dly = 32
768 04:50:26.203365 CS Dly: 4 (0~36)
769 04:50:26.206887
770 04:50:26.211153 ----->DramcWriteLeveling(PI) begin...
771 04:50:26.211284 ==
772 04:50:26.211380 Dram Type= 6, Freq= 0, CH_0, rank 0
773 04:50:26.218462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 04:50:26.218574 ==
775 04:50:26.218671 Write leveling (Byte 0): 35 => 35
776 04:50:26.221932 Write leveling (Byte 1): 29 => 29
777 04:50:26.225734 DramcWriteLeveling(PI) end<-----
778 04:50:26.225825
779 04:50:26.225904 ==
780 04:50:26.229287 Dram Type= 6, Freq= 0, CH_0, rank 0
781 04:50:26.231980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 04:50:26.232070 ==
783 04:50:26.235609 [Gating] SW mode calibration
784 04:50:26.243535 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 04:50:26.249554 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 04:50:26.253092 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 04:50:26.256605 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 04:50:26.263334 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 04:50:26.266206 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 04:50:26.269883 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 04:50:26.276850 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 04:50:26.280245 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 04:50:26.283340 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 04:50:26.286700 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 04:50:26.292957 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 04:50:26.296419 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 04:50:26.300192 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 04:50:26.306586 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 04:50:26.309856 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 04:50:26.313256 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 04:50:26.319996 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 04:50:26.323466 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 04:50:26.326919 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 04:50:26.333623 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
805 04:50:26.337015 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 04:50:26.340398 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 04:50:26.346535 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 04:50:26.350131 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 04:50:26.353447 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 04:50:26.356957 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 04:50:26.363546 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 04:50:26.366890 0 9 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
813 04:50:26.370273 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 04:50:26.376446 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 04:50:26.379887 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 04:50:26.383328 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 04:50:26.389859 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 04:50:26.393400 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 04:50:26.397235 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
820 04:50:26.403769 0 10 8 | B1->B0 | 2f2f 2626 | 1 0 | (1 1) (0 0)
821 04:50:26.406717 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 04:50:26.410341 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 04:50:26.416820 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 04:50:26.420364 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 04:50:26.423777 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 04:50:26.430380 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 04:50:26.433614 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
828 04:50:26.436975 0 11 8 | B1->B0 | 2b2b 3d3d | 0 0 | (0 0) (0 0)
829 04:50:26.443547 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
830 04:50:26.446986 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 04:50:26.450453 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 04:50:26.453771 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 04:50:26.460626 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 04:50:26.463976 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 04:50:26.467378 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 04:50:26.473614 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 04:50:26.477159 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 04:50:26.480987 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 04:50:26.487058 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 04:50:26.490514 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 04:50:26.493958 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 04:50:26.497244 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 04:50:26.504273 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 04:50:26.507578 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 04:50:26.510914 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 04:50:26.517478 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 04:50:26.520732 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 04:50:26.524142 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 04:50:26.531131 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 04:50:26.534455 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 04:50:26.537250 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 04:50:26.544567 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 04:50:26.544655 Total UI for P1: 0, mck2ui 16
854 04:50:26.550818 best dqsien dly found for B0: ( 0, 14, 4)
855 04:50:26.554366 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
856 04:50:26.557631 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 04:50:26.561661 Total UI for P1: 0, mck2ui 16
858 04:50:26.565093 best dqsien dly found for B1: ( 0, 14, 10)
859 04:50:26.568479 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
860 04:50:26.571388 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
861 04:50:26.571474
862 04:50:26.574816 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
863 04:50:26.578233 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
864 04:50:26.581747 [Gating] SW calibration Done
865 04:50:26.581832 ==
866 04:50:26.584830 Dram Type= 6, Freq= 0, CH_0, rank 0
867 04:50:26.588639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 04:50:26.591622 ==
869 04:50:26.591710 RX Vref Scan: 0
870 04:50:26.591798
871 04:50:26.595135 RX Vref 0 -> 0, step: 1
872 04:50:26.595313
873 04:50:26.598215 RX Delay -130 -> 252, step: 16
874 04:50:26.601716 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
875 04:50:26.604973 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
876 04:50:26.608867 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
877 04:50:26.612097 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
878 04:50:26.614988 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
879 04:50:26.622084 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
880 04:50:26.625251 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
881 04:50:26.628868 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
882 04:50:26.631902 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
883 04:50:26.635626 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
884 04:50:26.641699 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
885 04:50:26.645159 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
886 04:50:26.648404 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
887 04:50:26.651893 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
888 04:50:26.655273 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
889 04:50:26.661992 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
890 04:50:26.662078 ==
891 04:50:26.665354 Dram Type= 6, Freq= 0, CH_0, rank 0
892 04:50:26.668733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 04:50:26.668820 ==
894 04:50:26.668907 DQS Delay:
895 04:50:26.672070 DQS0 = 0, DQS1 = 0
896 04:50:26.672157 DQM Delay:
897 04:50:26.675529 DQM0 = 89, DQM1 = 80
898 04:50:26.675615 DQ Delay:
899 04:50:26.678904 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
900 04:50:26.682406 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
901 04:50:26.685747 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
902 04:50:26.689139 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
903 04:50:26.689224
904 04:50:26.689312
905 04:50:26.689394 ==
906 04:50:26.692635 Dram Type= 6, Freq= 0, CH_0, rank 0
907 04:50:26.695399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 04:50:26.695489 ==
909 04:50:26.695576
910 04:50:26.695657
911 04:50:26.698881 TX Vref Scan disable
912 04:50:26.702186 == TX Byte 0 ==
913 04:50:26.705433 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
914 04:50:26.709378 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
915 04:50:26.712527 == TX Byte 1 ==
916 04:50:26.715424 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
917 04:50:26.718965 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
918 04:50:26.719050 ==
919 04:50:26.722476 Dram Type= 6, Freq= 0, CH_0, rank 0
920 04:50:26.725651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 04:50:26.728565 ==
922 04:50:26.740914 TX Vref=22, minBit 8, minWin=27, winSum=446
923 04:50:26.744020 TX Vref=24, minBit 9, minWin=27, winSum=451
924 04:50:26.747538 TX Vref=26, minBit 0, minWin=28, winSum=455
925 04:50:26.750747 TX Vref=28, minBit 7, minWin=28, winSum=456
926 04:50:26.754112 TX Vref=30, minBit 5, minWin=28, winSum=456
927 04:50:26.757776 TX Vref=32, minBit 5, minWin=28, winSum=453
928 04:50:26.764422 [TxChooseVref] Worse bit 7, Min win 28, Win sum 456, Final Vref 28
929 04:50:26.764509
930 04:50:26.767549 Final TX Range 1 Vref 28
931 04:50:26.767657
932 04:50:26.767743 ==
933 04:50:26.771002 Dram Type= 6, Freq= 0, CH_0, rank 0
934 04:50:26.774423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 04:50:26.774509 ==
936 04:50:26.774596
937 04:50:26.774698
938 04:50:26.777938 TX Vref Scan disable
939 04:50:26.781485 == TX Byte 0 ==
940 04:50:26.784218 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
941 04:50:26.787660 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
942 04:50:26.791293 == TX Byte 1 ==
943 04:50:26.794638 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
944 04:50:26.798015 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
945 04:50:26.798101
946 04:50:26.801507 [DATLAT]
947 04:50:26.801595 Freq=800, CH0 RK0
948 04:50:26.801663
949 04:50:26.804279 DATLAT Default: 0xa
950 04:50:26.804401 0, 0xFFFF, sum = 0
951 04:50:26.807849 1, 0xFFFF, sum = 0
952 04:50:26.807937 2, 0xFFFF, sum = 0
953 04:50:26.811017 3, 0xFFFF, sum = 0
954 04:50:26.811102 4, 0xFFFF, sum = 0
955 04:50:26.814395 5, 0xFFFF, sum = 0
956 04:50:26.814478 6, 0xFFFF, sum = 0
957 04:50:26.817937 7, 0xFFFF, sum = 0
958 04:50:26.818021 8, 0xFFFF, sum = 0
959 04:50:26.821313 9, 0x0, sum = 1
960 04:50:26.821397 10, 0x0, sum = 2
961 04:50:26.824662 11, 0x0, sum = 3
962 04:50:26.824746 12, 0x0, sum = 4
963 04:50:26.828100 best_step = 10
964 04:50:26.828182
965 04:50:26.828247 ==
966 04:50:26.831361 Dram Type= 6, Freq= 0, CH_0, rank 0
967 04:50:26.834612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 04:50:26.834695 ==
969 04:50:26.838303 RX Vref Scan: 1
970 04:50:26.838386
971 04:50:26.838452 Set Vref Range= 32 -> 127
972 04:50:26.838513
973 04:50:26.841178 RX Vref 32 -> 127, step: 1
974 04:50:26.841261
975 04:50:26.844498 RX Delay -95 -> 252, step: 8
976 04:50:26.844581
977 04:50:26.848019 Set Vref, RX VrefLevel [Byte0]: 32
978 04:50:26.851591 [Byte1]: 32
979 04:50:26.851674
980 04:50:26.854468 Set Vref, RX VrefLevel [Byte0]: 33
981 04:50:26.857996 [Byte1]: 33
982 04:50:26.861581
983 04:50:26.861695 Set Vref, RX VrefLevel [Byte0]: 34
984 04:50:26.864568 [Byte1]: 34
985 04:50:26.868985
986 04:50:26.869067 Set Vref, RX VrefLevel [Byte0]: 35
987 04:50:26.872504 [Byte1]: 35
988 04:50:26.877105
989 04:50:26.877214 Set Vref, RX VrefLevel [Byte0]: 36
990 04:50:26.880100 [Byte1]: 36
991 04:50:26.884610
992 04:50:26.884717 Set Vref, RX VrefLevel [Byte0]: 37
993 04:50:26.887974 [Byte1]: 37
994 04:50:26.892192
995 04:50:26.892325 Set Vref, RX VrefLevel [Byte0]: 38
996 04:50:26.895570 [Byte1]: 38
997 04:50:26.899720
998 04:50:26.899805 Set Vref, RX VrefLevel [Byte0]: 39
999 04:50:26.903103 [Byte1]: 39
1000 04:50:26.907197
1001 04:50:26.907302 Set Vref, RX VrefLevel [Byte0]: 40
1002 04:50:26.910710 [Byte1]: 40
1003 04:50:26.914555
1004 04:50:26.914637 Set Vref, RX VrefLevel [Byte0]: 41
1005 04:50:26.918099 [Byte1]: 41
1006 04:50:26.922143
1007 04:50:26.922226 Set Vref, RX VrefLevel [Byte0]: 42
1008 04:50:26.925652 [Byte1]: 42
1009 04:50:26.929809
1010 04:50:26.929892 Set Vref, RX VrefLevel [Byte0]: 43
1011 04:50:26.933135 [Byte1]: 43
1012 04:50:26.937300
1013 04:50:26.937383 Set Vref, RX VrefLevel [Byte0]: 44
1014 04:50:26.940708 [Byte1]: 44
1015 04:50:26.945008
1016 04:50:26.945090 Set Vref, RX VrefLevel [Byte0]: 45
1017 04:50:26.948477 [Byte1]: 45
1018 04:50:26.952939
1019 04:50:26.953022 Set Vref, RX VrefLevel [Byte0]: 46
1020 04:50:26.956078 [Byte1]: 46
1021 04:50:26.960194
1022 04:50:26.960350 Set Vref, RX VrefLevel [Byte0]: 47
1023 04:50:26.963297 [Byte1]: 47
1024 04:50:26.967877
1025 04:50:26.967963 Set Vref, RX VrefLevel [Byte0]: 48
1026 04:50:26.970934 [Byte1]: 48
1027 04:50:26.975112
1028 04:50:26.975193 Set Vref, RX VrefLevel [Byte0]: 49
1029 04:50:26.978674 [Byte1]: 49
1030 04:50:26.983227
1031 04:50:26.983308 Set Vref, RX VrefLevel [Byte0]: 50
1032 04:50:26.986461 [Byte1]: 50
1033 04:50:26.990878
1034 04:50:26.990959 Set Vref, RX VrefLevel [Byte0]: 51
1035 04:50:26.994085 [Byte1]: 51
1036 04:50:26.998205
1037 04:50:26.998286 Set Vref, RX VrefLevel [Byte0]: 52
1038 04:50:27.001727 [Byte1]: 52
1039 04:50:27.005624
1040 04:50:27.005705 Set Vref, RX VrefLevel [Byte0]: 53
1041 04:50:27.008865 [Byte1]: 53
1042 04:50:27.013682
1043 04:50:27.013763 Set Vref, RX VrefLevel [Byte0]: 54
1044 04:50:27.016399 [Byte1]: 54
1045 04:50:27.021200
1046 04:50:27.021281 Set Vref, RX VrefLevel [Byte0]: 55
1047 04:50:27.023962 [Byte1]: 55
1048 04:50:27.028773
1049 04:50:27.028854 Set Vref, RX VrefLevel [Byte0]: 56
1050 04:50:27.031485 [Byte1]: 56
1051 04:50:27.036261
1052 04:50:27.036354 Set Vref, RX VrefLevel [Byte0]: 57
1053 04:50:27.039797 [Byte1]: 57
1054 04:50:27.044108
1055 04:50:27.044215 Set Vref, RX VrefLevel [Byte0]: 58
1056 04:50:27.047358 [Byte1]: 58
1057 04:50:27.051488
1058 04:50:27.051569 Set Vref, RX VrefLevel [Byte0]: 59
1059 04:50:27.054962 [Byte1]: 59
1060 04:50:27.059029
1061 04:50:27.059110 Set Vref, RX VrefLevel [Byte0]: 60
1062 04:50:27.062305 [Byte1]: 60
1063 04:50:27.066740
1064 04:50:27.066821 Set Vref, RX VrefLevel [Byte0]: 61
1065 04:50:27.069811 [Byte1]: 61
1066 04:50:27.074356
1067 04:50:27.074437 Set Vref, RX VrefLevel [Byte0]: 62
1068 04:50:27.077087 [Byte1]: 62
1069 04:50:27.081603
1070 04:50:27.081684 Set Vref, RX VrefLevel [Byte0]: 63
1071 04:50:27.084803 [Byte1]: 63
1072 04:50:27.089437
1073 04:50:27.089518 Set Vref, RX VrefLevel [Byte0]: 64
1074 04:50:27.092421 [Byte1]: 64
1075 04:50:27.096593
1076 04:50:27.096675 Set Vref, RX VrefLevel [Byte0]: 65
1077 04:50:27.100526 [Byte1]: 65
1078 04:50:27.104713
1079 04:50:27.104794 Set Vref, RX VrefLevel [Byte0]: 66
1080 04:50:27.108110 [Byte1]: 66
1081 04:50:27.112162
1082 04:50:27.112268 Set Vref, RX VrefLevel [Byte0]: 67
1083 04:50:27.115189 [Byte1]: 67
1084 04:50:27.120187
1085 04:50:27.120330 Set Vref, RX VrefLevel [Byte0]: 68
1086 04:50:27.122745 [Byte1]: 68
1087 04:50:27.127652
1088 04:50:27.127733 Set Vref, RX VrefLevel [Byte0]: 69
1089 04:50:27.130409 [Byte1]: 69
1090 04:50:27.135064
1091 04:50:27.135145 Set Vref, RX VrefLevel [Byte0]: 70
1092 04:50:27.138255 [Byte1]: 70
1093 04:50:27.142387
1094 04:50:27.142468 Set Vref, RX VrefLevel [Byte0]: 71
1095 04:50:27.145946 [Byte1]: 71
1096 04:50:27.149930
1097 04:50:27.150011 Set Vref, RX VrefLevel [Byte0]: 72
1098 04:50:27.153482 [Byte1]: 72
1099 04:50:27.157610
1100 04:50:27.157691 Set Vref, RX VrefLevel [Byte0]: 73
1101 04:50:27.161236 [Byte1]: 73
1102 04:50:27.165244
1103 04:50:27.165325 Set Vref, RX VrefLevel [Byte0]: 74
1104 04:50:27.168492 [Byte1]: 74
1105 04:50:27.173203
1106 04:50:27.173285 Set Vref, RX VrefLevel [Byte0]: 75
1107 04:50:27.176483 [Byte1]: 75
1108 04:50:27.180290
1109 04:50:27.180373 Set Vref, RX VrefLevel [Byte0]: 76
1110 04:50:27.183579 [Byte1]: 76
1111 04:50:27.188202
1112 04:50:27.188343 Set Vref, RX VrefLevel [Byte0]: 77
1113 04:50:27.191571 [Byte1]: 77
1114 04:50:27.195690
1115 04:50:27.195771 Final RX Vref Byte 0 = 60 to rank0
1116 04:50:27.198976 Final RX Vref Byte 1 = 60 to rank0
1117 04:50:27.202444 Final RX Vref Byte 0 = 60 to rank1
1118 04:50:27.205584 Final RX Vref Byte 1 = 60 to rank1==
1119 04:50:27.208865 Dram Type= 6, Freq= 0, CH_0, rank 0
1120 04:50:27.215776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1121 04:50:27.215876 ==
1122 04:50:27.215956 DQS Delay:
1123 04:50:27.216016 DQS0 = 0, DQS1 = 0
1124 04:50:27.218677 DQM Delay:
1125 04:50:27.218758 DQM0 = 91, DQM1 = 85
1126 04:50:27.221988 DQ Delay:
1127 04:50:27.225370 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1128 04:50:27.228834 DQ4 =96, DQ5 =80, DQ6 =96, DQ7 =100
1129 04:50:27.228916 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1130 04:50:27.235684 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1131 04:50:27.235765
1132 04:50:27.235880
1133 04:50:27.242096 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b41, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1134 04:50:27.245699 CH0 RK0: MR19=606, MR18=4B41
1135 04:50:27.252482 CH0_RK0: MR19=0x606, MR18=0x4B41, DQSOSC=391, MR23=63, INC=96, DEC=64
1136 04:50:27.252565
1137 04:50:27.255354 ----->DramcWriteLeveling(PI) begin...
1138 04:50:27.255436 ==
1139 04:50:27.259249 Dram Type= 6, Freq= 0, CH_0, rank 1
1140 04:50:27.262633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1141 04:50:27.262715 ==
1142 04:50:27.265532 Write leveling (Byte 0): 33 => 33
1143 04:50:27.269047 Write leveling (Byte 1): 32 => 32
1144 04:50:27.272420 DramcWriteLeveling(PI) end<-----
1145 04:50:27.272503
1146 04:50:27.272567 ==
1147 04:50:27.275923 Dram Type= 6, Freq= 0, CH_0, rank 1
1148 04:50:27.279311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1149 04:50:27.279393 ==
1150 04:50:27.282669 [Gating] SW mode calibration
1151 04:50:27.327127 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1152 04:50:27.327226 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1153 04:50:27.327478 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1154 04:50:27.327560 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1155 04:50:27.327646 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1156 04:50:27.328464 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 04:50:27.328545 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 04:50:27.328795 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 04:50:27.328881 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 04:50:27.370806 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 04:50:27.371126 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 04:50:27.371209 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 04:50:27.371277 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 04:50:27.371337 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 04:50:27.371408 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 04:50:27.371469 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 04:50:27.371525 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 04:50:27.371594 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 04:50:27.371838 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 04:50:27.414139 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1171 04:50:27.414931 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1172 04:50:27.415017 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 04:50:27.415266 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 04:50:27.415333 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 04:50:27.415404 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 04:50:27.415465 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 04:50:27.415523 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 04:50:27.415589 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 04:50:27.416256 0 9 8 | B1->B0 | 2c2c 2a2a | 0 0 | (0 0) (0 0)
1180 04:50:27.418866 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 04:50:27.422146 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 04:50:27.425558 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 04:50:27.432471 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 04:50:27.435850 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 04:50:27.439154 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 04:50:27.442573 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1187 04:50:27.449475 0 10 8 | B1->B0 | 2828 2b2b | 1 0 | (1 1) (0 0)
1188 04:50:27.452920 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 04:50:27.456988 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 04:50:27.460281 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 04:50:27.467946 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 04:50:27.471180 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 04:50:27.474470 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 04:50:27.478291 0 11 4 | B1->B0 | 2828 2828 | 1 0 | (0 0) (0 0)
1195 04:50:27.485284 0 11 8 | B1->B0 | 3e3e 3b3b | 0 1 | (0 0) (1 1)
1196 04:50:27.488917 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 04:50:27.491888 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 04:50:27.495318 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 04:50:27.502164 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 04:50:27.505570 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 04:50:27.509077 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 04:50:27.515301 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1203 04:50:27.519088 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1204 04:50:27.522210 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 04:50:27.528914 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 04:50:27.532510 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 04:50:27.535574 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 04:50:27.542295 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 04:50:27.545733 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 04:50:27.549166 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 04:50:27.552505 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 04:50:27.559361 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 04:50:27.562769 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 04:50:27.566099 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 04:50:27.572793 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 04:50:27.576283 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 04:50:27.579651 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 04:50:27.585887 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1219 04:50:27.589258 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1220 04:50:27.592502 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1221 04:50:27.596378 Total UI for P1: 0, mck2ui 16
1222 04:50:27.599614 best dqsien dly found for B1: ( 0, 14, 8)
1223 04:50:27.602795 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1224 04:50:27.605892 Total UI for P1: 0, mck2ui 16
1225 04:50:27.609457 best dqsien dly found for B0: ( 0, 14, 8)
1226 04:50:27.612903 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1227 04:50:27.616168 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1228 04:50:27.619549
1229 04:50:27.622980 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1230 04:50:27.626357 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1231 04:50:27.629746 [Gating] SW calibration Done
1232 04:50:27.629823 ==
1233 04:50:27.633193 Dram Type= 6, Freq= 0, CH_0, rank 1
1234 04:50:27.636465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1235 04:50:27.636564 ==
1236 04:50:27.636628 RX Vref Scan: 0
1237 04:50:27.636686
1238 04:50:27.639559 RX Vref 0 -> 0, step: 1
1239 04:50:27.639640
1240 04:50:27.642825 RX Delay -130 -> 252, step: 16
1241 04:50:27.646183 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1242 04:50:27.649972 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1243 04:50:27.656398 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1244 04:50:27.659957 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1245 04:50:27.662784 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1246 04:50:27.666269 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1247 04:50:27.669940 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1248 04:50:27.673171 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1249 04:50:27.679970 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1250 04:50:27.683196 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1251 04:50:27.686620 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1252 04:50:27.689381 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1253 04:50:27.696248 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1254 04:50:27.699760 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1255 04:50:27.703156 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1256 04:50:27.706682 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1257 04:50:27.706763 ==
1258 04:50:27.710236 Dram Type= 6, Freq= 0, CH_0, rank 1
1259 04:50:27.712905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1260 04:50:27.716209 ==
1261 04:50:27.716314 DQS Delay:
1262 04:50:27.716394 DQS0 = 0, DQS1 = 0
1263 04:50:27.720247 DQM Delay:
1264 04:50:27.720366 DQM0 = 93, DQM1 = 86
1265 04:50:27.723224 DQ Delay:
1266 04:50:27.723305 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1267 04:50:27.726240 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1268 04:50:27.729677 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1269 04:50:27.732864 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1270 04:50:27.736243
1271 04:50:27.736381
1272 04:50:27.736449 ==
1273 04:50:27.739502 Dram Type= 6, Freq= 0, CH_0, rank 1
1274 04:50:27.743417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1275 04:50:27.743517 ==
1276 04:50:27.743611
1277 04:50:27.743697
1278 04:50:27.746620 TX Vref Scan disable
1279 04:50:27.746690 == TX Byte 0 ==
1280 04:50:27.753262 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1281 04:50:27.756603 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1282 04:50:27.756684 == TX Byte 1 ==
1283 04:50:27.763049 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1284 04:50:27.766554 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1285 04:50:27.766681 ==
1286 04:50:27.769664 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 04:50:27.772850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 04:50:27.772924 ==
1289 04:50:27.786673 TX Vref=22, minBit 8, minWin=27, winSum=447
1290 04:50:27.790228 TX Vref=24, minBit 8, minWin=27, winSum=450
1291 04:50:27.793522 TX Vref=26, minBit 1, minWin=28, winSum=455
1292 04:50:27.796418 TX Vref=28, minBit 5, minWin=28, winSum=456
1293 04:50:27.799797 TX Vref=30, minBit 4, minWin=28, winSum=454
1294 04:50:27.803274 TX Vref=32, minBit 8, minWin=27, winSum=448
1295 04:50:27.810131 [TxChooseVref] Worse bit 5, Min win 28, Win sum 456, Final Vref 28
1296 04:50:27.810214
1297 04:50:27.813557 Final TX Range 1 Vref 28
1298 04:50:27.813638
1299 04:50:27.813701 ==
1300 04:50:27.816933 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 04:50:27.820409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 04:50:27.820489 ==
1303 04:50:27.820552
1304 04:50:27.823126
1305 04:50:27.823209 TX Vref Scan disable
1306 04:50:27.826616 == TX Byte 0 ==
1307 04:50:27.830114 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1308 04:50:27.833583 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1309 04:50:27.836919 == TX Byte 1 ==
1310 04:50:27.840123 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1311 04:50:27.843429 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1312 04:50:27.843509
1313 04:50:27.847087 [DATLAT]
1314 04:50:27.847193 Freq=800, CH0 RK1
1315 04:50:27.847308
1316 04:50:27.850080 DATLAT Default: 0xa
1317 04:50:27.850160 0, 0xFFFF, sum = 0
1318 04:50:27.853404 1, 0xFFFF, sum = 0
1319 04:50:27.853485 2, 0xFFFF, sum = 0
1320 04:50:27.856722 3, 0xFFFF, sum = 0
1321 04:50:27.856804 4, 0xFFFF, sum = 0
1322 04:50:27.860096 5, 0xFFFF, sum = 0
1323 04:50:27.860178 6, 0xFFFF, sum = 0
1324 04:50:27.863477 7, 0xFFFF, sum = 0
1325 04:50:27.863558 8, 0xFFFF, sum = 0
1326 04:50:27.866964 9, 0x0, sum = 1
1327 04:50:27.867045 10, 0x0, sum = 2
1328 04:50:27.869707 11, 0x0, sum = 3
1329 04:50:27.869788 12, 0x0, sum = 4
1330 04:50:27.873566 best_step = 10
1331 04:50:27.873646
1332 04:50:27.873709 ==
1333 04:50:27.876785 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 04:50:27.879818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 04:50:27.879898 ==
1336 04:50:27.883583 RX Vref Scan: 0
1337 04:50:27.883663
1338 04:50:27.883726 RX Vref 0 -> 0, step: 1
1339 04:50:27.883786
1340 04:50:27.886591 RX Delay -79 -> 252, step: 8
1341 04:50:27.893552 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1342 04:50:27.896627 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1343 04:50:27.900465 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1344 04:50:27.903177 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1345 04:50:27.906585 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1346 04:50:27.913301 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1347 04:50:27.916726 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1348 04:50:27.920243 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1349 04:50:27.923777 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1350 04:50:27.926385 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1351 04:50:27.929976 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1352 04:50:27.936862 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1353 04:50:27.940248 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1354 04:50:27.943614 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1355 04:50:27.946914 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1356 04:50:27.953203 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1357 04:50:27.953283 ==
1358 04:50:27.956590 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 04:50:27.960136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 04:50:27.960216 ==
1361 04:50:27.960280 DQS Delay:
1362 04:50:27.963365 DQS0 = 0, DQS1 = 0
1363 04:50:27.963445 DQM Delay:
1364 04:50:27.967286 DQM0 = 93, DQM1 = 82
1365 04:50:27.967366 DQ Delay:
1366 04:50:27.970387 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1367 04:50:27.973614 DQ4 =92, DQ5 =88, DQ6 =100, DQ7 =100
1368 04:50:27.976569 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1369 04:50:27.980020 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1370 04:50:27.980101
1371 04:50:27.980164
1372 04:50:27.986625 [DQSOSCAuto] RK1, (LSB)MR18= 0x4415, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1373 04:50:27.990102 CH0 RK1: MR19=606, MR18=4415
1374 04:50:27.997048 CH0_RK1: MR19=0x606, MR18=0x4415, DQSOSC=392, MR23=63, INC=96, DEC=64
1375 04:50:27.999971 [RxdqsGatingPostProcess] freq 800
1376 04:50:28.007265 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1377 04:50:28.007399 Pre-setting of DQS Precalculation
1378 04:50:28.013598 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1379 04:50:28.013734 ==
1380 04:50:28.016871 Dram Type= 6, Freq= 0, CH_1, rank 0
1381 04:50:28.020052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 04:50:28.020175 ==
1383 04:50:28.026522 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1384 04:50:28.033071 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1385 04:50:28.041320 [CA 0] Center 36 (6~67) winsize 62
1386 04:50:28.044766 [CA 1] Center 36 (6~67) winsize 62
1387 04:50:28.048197 [CA 2] Center 35 (5~66) winsize 62
1388 04:50:28.051789 [CA 3] Center 34 (4~65) winsize 62
1389 04:50:28.055255 [CA 4] Center 34 (4~65) winsize 62
1390 04:50:28.057949 [CA 5] Center 34 (4~64) winsize 61
1391 04:50:28.058019
1392 04:50:28.061542 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1393 04:50:28.061609
1394 04:50:28.064899 [CATrainingPosCal] consider 1 rank data
1395 04:50:28.068163 u2DelayCellTimex100 = 270/100 ps
1396 04:50:28.071650 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1397 04:50:28.075308 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1398 04:50:28.078595 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1399 04:50:28.084821 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1400 04:50:28.088087 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1401 04:50:28.091987 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1402 04:50:28.092093
1403 04:50:28.095297 CA PerBit enable=1, Macro0, CA PI delay=34
1404 04:50:28.095406
1405 04:50:28.098811 [CBTSetCACLKResult] CA Dly = 34
1406 04:50:28.098912 CS Dly: 6 (0~37)
1407 04:50:28.099036 ==
1408 04:50:28.101376 Dram Type= 6, Freq= 0, CH_1, rank 1
1409 04:50:28.108487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1410 04:50:28.108572 ==
1411 04:50:28.111876 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1412 04:50:28.118143 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1413 04:50:28.128016 [CA 0] Center 36 (6~67) winsize 62
1414 04:50:28.131895 [CA 1] Center 36 (6~67) winsize 62
1415 04:50:28.135764 [CA 2] Center 35 (5~66) winsize 62
1416 04:50:28.139374 [CA 3] Center 34 (4~65) winsize 62
1417 04:50:28.143166 [CA 4] Center 34 (4~65) winsize 62
1418 04:50:28.143288 [CA 5] Center 34 (4~65) winsize 62
1419 04:50:28.143414
1420 04:50:28.146987 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1421 04:50:28.151212
1422 04:50:28.151330 [CATrainingPosCal] consider 2 rank data
1423 04:50:28.154628 u2DelayCellTimex100 = 270/100 ps
1424 04:50:28.157929 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1425 04:50:28.160849 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1426 04:50:28.168001 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1427 04:50:28.170791 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1428 04:50:28.174236 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1429 04:50:28.177614 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1430 04:50:28.177691
1431 04:50:28.180997 CA PerBit enable=1, Macro0, CA PI delay=34
1432 04:50:28.181067
1433 04:50:28.184540 [CBTSetCACLKResult] CA Dly = 34
1434 04:50:28.184606 CS Dly: 6 (0~38)
1435 04:50:28.184666
1436 04:50:28.188012 ----->DramcWriteLeveling(PI) begin...
1437 04:50:28.188078 ==
1438 04:50:28.191306 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 04:50:28.198098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 04:50:28.198167 ==
1441 04:50:28.201325 Write leveling (Byte 0): 28 => 28
1442 04:50:28.204442 Write leveling (Byte 1): 28 => 28
1443 04:50:28.204523 DramcWriteLeveling(PI) end<-----
1444 04:50:28.207859
1445 04:50:28.207940 ==
1446 04:50:28.211450 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 04:50:28.214661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 04:50:28.214742 ==
1449 04:50:28.217896 [Gating] SW mode calibration
1450 04:50:28.224534 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1451 04:50:28.228065 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1452 04:50:28.234356 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1453 04:50:28.237765 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1454 04:50:28.241679 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 04:50:28.247924 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 04:50:28.251332 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 04:50:28.254577 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 04:50:28.261126 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 04:50:28.264755 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 04:50:28.267708 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 04:50:28.274362 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 04:50:28.277603 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 04:50:28.281014 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 04:50:28.287872 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 04:50:28.291287 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 04:50:28.294682 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 04:50:28.297937 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 04:50:28.304682 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1469 04:50:28.307940 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1470 04:50:28.311031 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 04:50:28.318195 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 04:50:28.321545 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 04:50:28.324970 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 04:50:28.331523 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 04:50:28.335079 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 04:50:28.337834 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 04:50:28.344586 0 9 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
1478 04:50:28.347830 0 9 8 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1479 04:50:28.351182 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 04:50:28.357864 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 04:50:28.361243 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 04:50:28.364635 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 04:50:28.367979 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 04:50:28.374961 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1485 04:50:28.378335 0 10 4 | B1->B0 | 3232 2f2f | 0 0 | (1 1) (0 1)
1486 04:50:28.381617 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1487 04:50:28.388140 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 04:50:28.391414 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 04:50:28.394622 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 04:50:28.401780 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 04:50:28.405246 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 04:50:28.407931 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 04:50:28.414803 0 11 4 | B1->B0 | 2525 3333 | 0 0 | (0 0) (0 0)
1494 04:50:28.418243 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1495 04:50:28.421444 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 04:50:28.428618 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 04:50:28.431816 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 04:50:28.435275 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 04:50:28.441709 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 04:50:28.445227 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 04:50:28.448508 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1502 04:50:28.451970 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 04:50:28.458161 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 04:50:28.461531 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 04:50:28.464927 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 04:50:28.471829 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 04:50:28.475351 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 04:50:28.478539 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 04:50:28.485307 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 04:50:28.488764 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 04:50:28.491604 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 04:50:28.498559 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 04:50:28.501871 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 04:50:28.505512 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 04:50:28.512077 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 04:50:28.514981 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 04:50:28.518741 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1518 04:50:28.521663 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 04:50:28.525215 Total UI for P1: 0, mck2ui 16
1520 04:50:28.528297 best dqsien dly found for B0: ( 0, 14, 6)
1521 04:50:28.532241 Total UI for P1: 0, mck2ui 16
1522 04:50:28.535109 best dqsien dly found for B1: ( 0, 14, 4)
1523 04:50:28.538755 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1524 04:50:28.541851 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1525 04:50:28.545102
1526 04:50:28.548665 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1527 04:50:28.551639 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1528 04:50:28.555458 [Gating] SW calibration Done
1529 04:50:28.555539 ==
1530 04:50:28.558243 Dram Type= 6, Freq= 0, CH_1, rank 0
1531 04:50:28.561667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1532 04:50:28.561749 ==
1533 04:50:28.561813 RX Vref Scan: 0
1534 04:50:28.561874
1535 04:50:28.564988 RX Vref 0 -> 0, step: 1
1536 04:50:28.565069
1537 04:50:28.568399 RX Delay -130 -> 252, step: 16
1538 04:50:28.571962 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1539 04:50:28.575333 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1540 04:50:28.582096 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1541 04:50:28.585437 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1542 04:50:28.588894 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1543 04:50:28.591663 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1544 04:50:28.595102 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1545 04:50:28.598439 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1546 04:50:28.605377 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1547 04:50:28.608789 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1548 04:50:28.612064 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1549 04:50:28.615430 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1550 04:50:28.622091 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1551 04:50:28.625415 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1552 04:50:28.628280 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1553 04:50:28.631509 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1554 04:50:28.631611 ==
1555 04:50:28.635019 Dram Type= 6, Freq= 0, CH_1, rank 0
1556 04:50:28.638497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1557 04:50:28.641648 ==
1558 04:50:28.641742 DQS Delay:
1559 04:50:28.641808 DQS0 = 0, DQS1 = 0
1560 04:50:28.645255 DQM Delay:
1561 04:50:28.645353 DQM0 = 93, DQM1 = 89
1562 04:50:28.648248 DQ Delay:
1563 04:50:28.648391 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1564 04:50:28.651648 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1565 04:50:28.655269 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1566 04:50:28.662284 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101
1567 04:50:28.662389
1568 04:50:28.662480
1569 04:50:28.662567 ==
1570 04:50:28.665426 Dram Type= 6, Freq= 0, CH_1, rank 0
1571 04:50:28.669126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1572 04:50:28.669199 ==
1573 04:50:28.669259
1574 04:50:28.669337
1575 04:50:28.671782 TX Vref Scan disable
1576 04:50:28.671855 == TX Byte 0 ==
1577 04:50:28.678560 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1578 04:50:28.682491 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1579 04:50:28.682572 == TX Byte 1 ==
1580 04:50:28.688692 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1581 04:50:28.692155 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1582 04:50:28.692235 ==
1583 04:50:28.695604 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 04:50:28.698916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 04:50:28.699020 ==
1586 04:50:28.712056 TX Vref=22, minBit 3, minWin=26, winSum=435
1587 04:50:28.715463 TX Vref=24, minBit 3, minWin=26, winSum=438
1588 04:50:28.718892 TX Vref=26, minBit 0, minWin=27, winSum=446
1589 04:50:28.722364 TX Vref=28, minBit 1, minWin=27, winSum=445
1590 04:50:28.725744 TX Vref=30, minBit 0, minWin=27, winSum=448
1591 04:50:28.729107 TX Vref=32, minBit 0, minWin=27, winSum=448
1592 04:50:28.735246 [TxChooseVref] Worse bit 0, Min win 27, Win sum 448, Final Vref 30
1593 04:50:28.735351
1594 04:50:28.738741 Final TX Range 1 Vref 30
1595 04:50:28.738814
1596 04:50:28.738875 ==
1597 04:50:28.742227 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 04:50:28.745599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 04:50:28.745680 ==
1600 04:50:28.745743
1601 04:50:28.749007
1602 04:50:28.749087 TX Vref Scan disable
1603 04:50:28.752245 == TX Byte 0 ==
1604 04:50:28.755862 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1605 04:50:28.758963 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1606 04:50:28.762548 == TX Byte 1 ==
1607 04:50:28.765568 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1608 04:50:28.768970 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1609 04:50:28.772267
1610 04:50:28.772395 [DATLAT]
1611 04:50:28.772487 Freq=800, CH1 RK0
1612 04:50:28.772577
1613 04:50:28.775829 DATLAT Default: 0xa
1614 04:50:28.775927 0, 0xFFFF, sum = 0
1615 04:50:28.779004 1, 0xFFFF, sum = 0
1616 04:50:28.779075 2, 0xFFFF, sum = 0
1617 04:50:28.782259 3, 0xFFFF, sum = 0
1618 04:50:28.782331 4, 0xFFFF, sum = 0
1619 04:50:28.785407 5, 0xFFFF, sum = 0
1620 04:50:28.785478 6, 0xFFFF, sum = 0
1621 04:50:28.789202 7, 0xFFFF, sum = 0
1622 04:50:28.789271 8, 0xFFFF, sum = 0
1623 04:50:28.792254 9, 0x0, sum = 1
1624 04:50:28.792357 10, 0x0, sum = 2
1625 04:50:28.795776 11, 0x0, sum = 3
1626 04:50:28.795860 12, 0x0, sum = 4
1627 04:50:28.799097 best_step = 10
1628 04:50:28.799171
1629 04:50:28.799232 ==
1630 04:50:28.802410 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 04:50:28.806078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 04:50:28.806160 ==
1633 04:50:28.809237 RX Vref Scan: 1
1634 04:50:28.809307
1635 04:50:28.809368 Set Vref Range= 32 -> 127
1636 04:50:28.809425
1637 04:50:28.812522 RX Vref 32 -> 127, step: 1
1638 04:50:28.812589
1639 04:50:28.815925 RX Delay -79 -> 252, step: 8
1640 04:50:28.815992
1641 04:50:28.819343 Set Vref, RX VrefLevel [Byte0]: 32
1642 04:50:28.822698 [Byte1]: 32
1643 04:50:28.822805
1644 04:50:28.826085 Set Vref, RX VrefLevel [Byte0]: 33
1645 04:50:28.829611 [Byte1]: 33
1646 04:50:28.829686
1647 04:50:28.832245 Set Vref, RX VrefLevel [Byte0]: 34
1648 04:50:28.835694 [Byte1]: 34
1649 04:50:28.839650
1650 04:50:28.839723 Set Vref, RX VrefLevel [Byte0]: 35
1651 04:50:28.843032 [Byte1]: 35
1652 04:50:28.847260
1653 04:50:28.847328 Set Vref, RX VrefLevel [Byte0]: 36
1654 04:50:28.850698 [Byte1]: 36
1655 04:50:28.854879
1656 04:50:28.854953 Set Vref, RX VrefLevel [Byte0]: 37
1657 04:50:28.858301 [Byte1]: 37
1658 04:50:28.862894
1659 04:50:28.862961 Set Vref, RX VrefLevel [Byte0]: 38
1660 04:50:28.865546 [Byte1]: 38
1661 04:50:28.870243
1662 04:50:28.870315 Set Vref, RX VrefLevel [Byte0]: 39
1663 04:50:28.873610 [Byte1]: 39
1664 04:50:28.877665
1665 04:50:28.877745 Set Vref, RX VrefLevel [Byte0]: 40
1666 04:50:28.880783 [Byte1]: 40
1667 04:50:28.885118
1668 04:50:28.885199 Set Vref, RX VrefLevel [Byte0]: 41
1669 04:50:28.888537 [Byte1]: 41
1670 04:50:28.892576
1671 04:50:28.892661 Set Vref, RX VrefLevel [Byte0]: 42
1672 04:50:28.895862 [Byte1]: 42
1673 04:50:28.900497
1674 04:50:28.900579 Set Vref, RX VrefLevel [Byte0]: 43
1675 04:50:28.903744 [Byte1]: 43
1676 04:50:28.907787
1677 04:50:28.907867 Set Vref, RX VrefLevel [Byte0]: 44
1678 04:50:28.910941 [Byte1]: 44
1679 04:50:28.915632
1680 04:50:28.915712 Set Vref, RX VrefLevel [Byte0]: 45
1681 04:50:28.918406 [Byte1]: 45
1682 04:50:28.922862
1683 04:50:28.922943 Set Vref, RX VrefLevel [Byte0]: 46
1684 04:50:28.926566 [Byte1]: 46
1685 04:50:28.930325
1686 04:50:28.933388 Set Vref, RX VrefLevel [Byte0]: 47
1687 04:50:28.933470 [Byte1]: 47
1688 04:50:28.938275
1689 04:50:28.938359 Set Vref, RX VrefLevel [Byte0]: 48
1690 04:50:28.941604 [Byte1]: 48
1691 04:50:28.945722
1692 04:50:28.945801 Set Vref, RX VrefLevel [Byte0]: 49
1693 04:50:28.949100 [Byte1]: 49
1694 04:50:28.953302
1695 04:50:28.953388 Set Vref, RX VrefLevel [Byte0]: 50
1696 04:50:28.956704 [Byte1]: 50
1697 04:50:28.960917
1698 04:50:28.960997 Set Vref, RX VrefLevel [Byte0]: 51
1699 04:50:28.963647 [Byte1]: 51
1700 04:50:28.968580
1701 04:50:28.968660 Set Vref, RX VrefLevel [Byte0]: 52
1702 04:50:28.971168 [Byte1]: 52
1703 04:50:28.975691
1704 04:50:28.975770 Set Vref, RX VrefLevel [Byte0]: 53
1705 04:50:28.979263 [Byte1]: 53
1706 04:50:28.983315
1707 04:50:28.983400 Set Vref, RX VrefLevel [Byte0]: 54
1708 04:50:28.986706 [Byte1]: 54
1709 04:50:28.990838
1710 04:50:28.990910 Set Vref, RX VrefLevel [Byte0]: 55
1711 04:50:28.994226 [Byte1]: 55
1712 04:50:28.998077
1713 04:50:28.998148 Set Vref, RX VrefLevel [Byte0]: 56
1714 04:50:29.001693 [Byte1]: 56
1715 04:50:29.005984
1716 04:50:29.006057 Set Vref, RX VrefLevel [Byte0]: 57
1717 04:50:29.009318 [Byte1]: 57
1718 04:50:29.013680
1719 04:50:29.013780 Set Vref, RX VrefLevel [Byte0]: 58
1720 04:50:29.016892 [Byte1]: 58
1721 04:50:29.021118
1722 04:50:29.021198 Set Vref, RX VrefLevel [Byte0]: 59
1723 04:50:29.024276 [Byte1]: 59
1724 04:50:29.028500
1725 04:50:29.028580 Set Vref, RX VrefLevel [Byte0]: 60
1726 04:50:29.032103 [Byte1]: 60
1727 04:50:29.035814
1728 04:50:29.035915 Set Vref, RX VrefLevel [Byte0]: 61
1729 04:50:29.039561 [Byte1]: 61
1730 04:50:29.043973
1731 04:50:29.044053 Set Vref, RX VrefLevel [Byte0]: 62
1732 04:50:29.047107 [Byte1]: 62
1733 04:50:29.051080
1734 04:50:29.051184 Set Vref, RX VrefLevel [Byte0]: 63
1735 04:50:29.054599 [Byte1]: 63
1736 04:50:29.058565
1737 04:50:29.058664 Set Vref, RX VrefLevel [Byte0]: 64
1738 04:50:29.062081 [Byte1]: 64
1739 04:50:29.066203
1740 04:50:29.066302 Set Vref, RX VrefLevel [Byte0]: 65
1741 04:50:29.069681 [Byte1]: 65
1742 04:50:29.073737
1743 04:50:29.073808 Set Vref, RX VrefLevel [Byte0]: 66
1744 04:50:29.077116 [Byte1]: 66
1745 04:50:29.081647
1746 04:50:29.081717 Set Vref, RX VrefLevel [Byte0]: 67
1747 04:50:29.084368 [Byte1]: 67
1748 04:50:29.089300
1749 04:50:29.089376 Set Vref, RX VrefLevel [Byte0]: 68
1750 04:50:29.091993 [Byte1]: 68
1751 04:50:29.096720
1752 04:50:29.096820 Set Vref, RX VrefLevel [Byte0]: 69
1753 04:50:29.099400 [Byte1]: 69
1754 04:50:29.103765
1755 04:50:29.103839 Set Vref, RX VrefLevel [Byte0]: 70
1756 04:50:29.107191 [Byte1]: 70
1757 04:50:29.111423
1758 04:50:29.111519 Set Vref, RX VrefLevel [Byte0]: 71
1759 04:50:29.114784 [Byte1]: 71
1760 04:50:29.119277
1761 04:50:29.119348 Final RX Vref Byte 0 = 56 to rank0
1762 04:50:29.122347 Final RX Vref Byte 1 = 56 to rank0
1763 04:50:29.126143 Final RX Vref Byte 0 = 56 to rank1
1764 04:50:29.128896 Final RX Vref Byte 1 = 56 to rank1==
1765 04:50:29.132458 Dram Type= 6, Freq= 0, CH_1, rank 0
1766 04:50:29.138996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1767 04:50:29.139078 ==
1768 04:50:29.139142 DQS Delay:
1769 04:50:29.139202 DQS0 = 0, DQS1 = 0
1770 04:50:29.142453 DQM Delay:
1771 04:50:29.142549 DQM0 = 96, DQM1 = 90
1772 04:50:29.145871 DQ Delay:
1773 04:50:29.149535 DQ0 =96, DQ1 =88, DQ2 =88, DQ3 =92
1774 04:50:29.152219 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1775 04:50:29.155633 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1776 04:50:29.159021 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =100
1777 04:50:29.159095
1778 04:50:29.159155
1779 04:50:29.165854 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a46, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
1780 04:50:29.169479 CH1 RK0: MR19=606, MR18=2A46
1781 04:50:29.175927 CH1_RK0: MR19=0x606, MR18=0x2A46, DQSOSC=392, MR23=63, INC=96, DEC=64
1782 04:50:29.176028
1783 04:50:29.179225 ----->DramcWriteLeveling(PI) begin...
1784 04:50:29.179305 ==
1785 04:50:29.182582 Dram Type= 6, Freq= 0, CH_1, rank 1
1786 04:50:29.185927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1787 04:50:29.185999 ==
1788 04:50:29.189150 Write leveling (Byte 0): 24 => 24
1789 04:50:29.192652 Write leveling (Byte 1): 26 => 26
1790 04:50:29.196153 DramcWriteLeveling(PI) end<-----
1791 04:50:29.196227
1792 04:50:29.196297 ==
1793 04:50:29.199555 Dram Type= 6, Freq= 0, CH_1, rank 1
1794 04:50:29.202997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1795 04:50:29.203074 ==
1796 04:50:29.205694 [Gating] SW mode calibration
1797 04:50:29.212694 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1798 04:50:29.219457 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1799 04:50:29.223001 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1800 04:50:29.225670 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1801 04:50:29.232781 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 04:50:29.236177 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 04:50:29.239675 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 04:50:29.246025 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 04:50:29.249346 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 04:50:29.252467 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 04:50:29.259333 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 04:50:29.263101 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 04:50:29.266378 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 04:50:29.269485 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 04:50:29.276438 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 04:50:29.279548 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 04:50:29.282693 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 04:50:29.289486 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 04:50:29.293070 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1816 04:50:29.296013 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1817 04:50:29.303078 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 04:50:29.306522 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 04:50:29.309982 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 04:50:29.316577 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 04:50:29.319404 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 04:50:29.322952 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 04:50:29.329709 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 04:50:29.333307 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 04:50:29.335944 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1826 04:50:29.342599 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 04:50:29.346114 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 04:50:29.349396 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 04:50:29.352894 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 04:50:29.359551 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 04:50:29.362913 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1832 04:50:29.366324 0 10 4 | B1->B0 | 2d2d 3232 | 0 0 | (0 0) (0 1)
1833 04:50:29.373245 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 04:50:29.376475 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 04:50:29.379817 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 04:50:29.386328 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 04:50:29.389855 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 04:50:29.393198 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 04:50:29.399889 0 11 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1840 04:50:29.403012 0 11 4 | B1->B0 | 3535 2a2a | 0 1 | (1 1) (0 0)
1841 04:50:29.406386 0 11 8 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
1842 04:50:29.413404 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 04:50:29.416153 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 04:50:29.419787 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 04:50:29.423131 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 04:50:29.430134 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 04:50:29.432949 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 04:50:29.436314 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1849 04:50:29.443215 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 04:50:29.446268 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 04:50:29.449664 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 04:50:29.456436 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 04:50:29.459937 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 04:50:29.463229 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 04:50:29.469771 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 04:50:29.473098 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 04:50:29.476272 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 04:50:29.482832 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 04:50:29.486823 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 04:50:29.489546 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 04:50:29.496667 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 04:50:29.499683 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 04:50:29.502887 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1864 04:50:29.510176 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1865 04:50:29.512910 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 04:50:29.516426 Total UI for P1: 0, mck2ui 16
1867 04:50:29.519929 best dqsien dly found for B0: ( 0, 14, 2)
1868 04:50:29.523425 Total UI for P1: 0, mck2ui 16
1869 04:50:29.526554 best dqsien dly found for B1: ( 0, 14, 4)
1870 04:50:29.529905 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1871 04:50:29.533443 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1872 04:50:29.533550
1873 04:50:29.536680 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1874 04:50:29.540044 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1875 04:50:29.543489 [Gating] SW calibration Done
1876 04:50:29.543588 ==
1877 04:50:29.546876 Dram Type= 6, Freq= 0, CH_1, rank 1
1878 04:50:29.550177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1879 04:50:29.550285 ==
1880 04:50:29.553484 RX Vref Scan: 0
1881 04:50:29.553590
1882 04:50:29.553683 RX Vref 0 -> 0, step: 1
1883 04:50:29.553772
1884 04:50:29.556852 RX Delay -130 -> 252, step: 16
1885 04:50:29.560178 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1886 04:50:29.566474 iDelay=222, Bit 1, Center 93 (-2 ~ 189) 192
1887 04:50:29.569811 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1888 04:50:29.573198 iDelay=222, Bit 3, Center 93 (-2 ~ 189) 192
1889 04:50:29.576626 iDelay=222, Bit 4, Center 93 (-2 ~ 189) 192
1890 04:50:29.580138 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1891 04:50:29.586608 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1892 04:50:29.589932 iDelay=222, Bit 7, Center 101 (-2 ~ 205) 208
1893 04:50:29.593716 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1894 04:50:29.597058 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1895 04:50:29.600265 iDelay=222, Bit 10, Center 93 (-2 ~ 189) 192
1896 04:50:29.603358 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1897 04:50:29.609907 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1898 04:50:29.613752 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1899 04:50:29.616931 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1900 04:50:29.620339 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1901 04:50:29.620421 ==
1902 04:50:29.623232 Dram Type= 6, Freq= 0, CH_1, rank 1
1903 04:50:29.629995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1904 04:50:29.630084 ==
1905 04:50:29.630150 DQS Delay:
1906 04:50:29.633564 DQS0 = 0, DQS1 = 0
1907 04:50:29.633645 DQM Delay:
1908 04:50:29.633708 DQM0 = 97, DQM1 = 94
1909 04:50:29.636914 DQ Delay:
1910 04:50:29.640172 DQ0 =101, DQ1 =93, DQ2 =85, DQ3 =93
1911 04:50:29.643318 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =101
1912 04:50:29.646996 DQ8 =85, DQ9 =85, DQ10 =93, DQ11 =85
1913 04:50:29.650201 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1914 04:50:29.650281
1915 04:50:29.650345
1916 04:50:29.650404 ==
1917 04:50:29.653407 Dram Type= 6, Freq= 0, CH_1, rank 1
1918 04:50:29.656707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1919 04:50:29.656788 ==
1920 04:50:29.656852
1921 04:50:29.656911
1922 04:50:29.659791 TX Vref Scan disable
1923 04:50:29.663198 == TX Byte 0 ==
1924 04:50:29.666563 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1925 04:50:29.670148 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1926 04:50:29.673435 == TX Byte 1 ==
1927 04:50:29.676866 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1928 04:50:29.680091 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1929 04:50:29.680186 ==
1930 04:50:29.683507 Dram Type= 6, Freq= 0, CH_1, rank 1
1931 04:50:29.689970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1932 04:50:29.690051 ==
1933 04:50:29.701213 TX Vref=22, minBit 1, minWin=26, winSum=437
1934 04:50:29.705209 TX Vref=24, minBit 1, minWin=26, winSum=439
1935 04:50:29.708449 TX Vref=26, minBit 1, minWin=26, winSum=441
1936 04:50:29.711714 TX Vref=28, minBit 1, minWin=26, winSum=444
1937 04:50:29.714830 TX Vref=30, minBit 3, minWin=26, winSum=443
1938 04:50:29.718014 TX Vref=32, minBit 0, minWin=26, winSum=440
1939 04:50:29.724440 [TxChooseVref] Worse bit 1, Min win 26, Win sum 444, Final Vref 28
1940 04:50:29.724522
1941 04:50:29.728139 Final TX Range 1 Vref 28
1942 04:50:29.728235
1943 04:50:29.728357 ==
1944 04:50:29.731515 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 04:50:29.734957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 04:50:29.735051 ==
1947 04:50:29.738342
1948 04:50:29.738411
1949 04:50:29.738470 TX Vref Scan disable
1950 04:50:29.741134 == TX Byte 0 ==
1951 04:50:29.744589 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1952 04:50:29.747876 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1953 04:50:29.751220 == TX Byte 1 ==
1954 04:50:29.754672 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1955 04:50:29.757832 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1956 04:50:29.761770
1957 04:50:29.761855 [DATLAT]
1958 04:50:29.761921 Freq=800, CH1 RK1
1959 04:50:29.761981
1960 04:50:29.764970 DATLAT Default: 0xa
1961 04:50:29.765050 0, 0xFFFF, sum = 0
1962 04:50:29.768265 1, 0xFFFF, sum = 0
1963 04:50:29.768384 2, 0xFFFF, sum = 0
1964 04:50:29.771162 3, 0xFFFF, sum = 0
1965 04:50:29.771244 4, 0xFFFF, sum = 0
1966 04:50:29.774814 5, 0xFFFF, sum = 0
1967 04:50:29.774897 6, 0xFFFF, sum = 0
1968 04:50:29.778272 7, 0xFFFF, sum = 0
1969 04:50:29.781569 8, 0xFFFF, sum = 0
1970 04:50:29.781652 9, 0x0, sum = 1
1971 04:50:29.781717 10, 0x0, sum = 2
1972 04:50:29.784893 11, 0x0, sum = 3
1973 04:50:29.784975 12, 0x0, sum = 4
1974 04:50:29.788335 best_step = 10
1975 04:50:29.788415
1976 04:50:29.788479 ==
1977 04:50:29.791828 Dram Type= 6, Freq= 0, CH_1, rank 1
1978 04:50:29.795210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1979 04:50:29.795291 ==
1980 04:50:29.798358 RX Vref Scan: 0
1981 04:50:29.798438
1982 04:50:29.798502 RX Vref 0 -> 0, step: 1
1983 04:50:29.798561
1984 04:50:29.801311 RX Delay -63 -> 252, step: 8
1985 04:50:29.808586 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1986 04:50:29.811813 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1987 04:50:29.815093 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1988 04:50:29.818316 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1989 04:50:29.821666 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1990 04:50:29.825003 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1991 04:50:29.831347 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1992 04:50:29.835144 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1993 04:50:29.838571 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1994 04:50:29.841359 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1995 04:50:29.844784 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
1996 04:50:29.851728 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
1997 04:50:29.854961 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
1998 04:50:29.858319 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
1999 04:50:29.861802 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2000 04:50:29.865267 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2001 04:50:29.865348 ==
2002 04:50:29.868048 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 04:50:29.875007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 04:50:29.875088 ==
2005 04:50:29.875151 DQS Delay:
2006 04:50:29.878170 DQS0 = 0, DQS1 = 0
2007 04:50:29.878250 DQM Delay:
2008 04:50:29.878313 DQM0 = 97, DQM1 = 91
2009 04:50:29.881418 DQ Delay:
2010 04:50:29.884643 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2011 04:50:29.888114 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2012 04:50:29.891415 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =88
2013 04:50:29.894818 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2014 04:50:29.894897
2015 04:50:29.894974
2016 04:50:29.901868 [DQSOSCAuto] RK1, (LSB)MR18= 0x440d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2017 04:50:29.905152 CH1 RK1: MR19=606, MR18=440D
2018 04:50:29.911334 CH1_RK1: MR19=0x606, MR18=0x440D, DQSOSC=392, MR23=63, INC=96, DEC=64
2019 04:50:29.914667 [RxdqsGatingPostProcess] freq 800
2020 04:50:29.918624 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2021 04:50:29.921807 Pre-setting of DQS Precalculation
2022 04:50:29.928190 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2023 04:50:29.934949 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2024 04:50:29.941401 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2025 04:50:29.941483
2026 04:50:29.941547
2027 04:50:29.945012 [Calibration Summary] 1600 Mbps
2028 04:50:29.945092 CH 0, Rank 0
2029 04:50:29.948186 SW Impedance : PASS
2030 04:50:29.951640 DUTY Scan : NO K
2031 04:50:29.951720 ZQ Calibration : PASS
2032 04:50:29.955039 Jitter Meter : NO K
2033 04:50:29.958456 CBT Training : PASS
2034 04:50:29.958537 Write leveling : PASS
2035 04:50:29.961870 RX DQS gating : PASS
2036 04:50:29.965292 RX DQ/DQS(RDDQC) : PASS
2037 04:50:29.965372 TX DQ/DQS : PASS
2038 04:50:29.968647 RX DATLAT : PASS
2039 04:50:29.968727 RX DQ/DQS(Engine): PASS
2040 04:50:29.972079 TX OE : NO K
2041 04:50:29.972160 All Pass.
2042 04:50:29.972223
2043 04:50:29.975585 CH 0, Rank 1
2044 04:50:29.975664 SW Impedance : PASS
2045 04:50:29.978389 DUTY Scan : NO K
2046 04:50:29.981805 ZQ Calibration : PASS
2047 04:50:29.981886 Jitter Meter : NO K
2048 04:50:29.985323 CBT Training : PASS
2049 04:50:29.988049 Write leveling : PASS
2050 04:50:29.988129 RX DQS gating : PASS
2051 04:50:29.991427 RX DQ/DQS(RDDQC) : PASS
2052 04:50:29.994736 TX DQ/DQS : PASS
2053 04:50:29.994817 RX DATLAT : PASS
2054 04:50:29.998630 RX DQ/DQS(Engine): PASS
2055 04:50:30.001727 TX OE : NO K
2056 04:50:30.001824 All Pass.
2057 04:50:30.001889
2058 04:50:30.001948 CH 1, Rank 0
2059 04:50:30.004979 SW Impedance : PASS
2060 04:50:30.008424 DUTY Scan : NO K
2061 04:50:30.008505 ZQ Calibration : PASS
2062 04:50:30.011688 Jitter Meter : NO K
2063 04:50:30.014655 CBT Training : PASS
2064 04:50:30.014735 Write leveling : PASS
2065 04:50:30.018168 RX DQS gating : PASS
2066 04:50:30.021277 RX DQ/DQS(RDDQC) : PASS
2067 04:50:30.021358 TX DQ/DQS : PASS
2068 04:50:30.024847 RX DATLAT : PASS
2069 04:50:30.024928 RX DQ/DQS(Engine): PASS
2070 04:50:30.028031 TX OE : NO K
2071 04:50:30.028111 All Pass.
2072 04:50:30.028175
2073 04:50:30.031233 CH 1, Rank 1
2074 04:50:30.031314 SW Impedance : PASS
2075 04:50:30.034968 DUTY Scan : NO K
2076 04:50:30.038275 ZQ Calibration : PASS
2077 04:50:30.038356 Jitter Meter : NO K
2078 04:50:30.041581 CBT Training : PASS
2079 04:50:30.045074 Write leveling : PASS
2080 04:50:30.045154 RX DQS gating : PASS
2081 04:50:30.048521 RX DQ/DQS(RDDQC) : PASS
2082 04:50:30.051257 TX DQ/DQS : PASS
2083 04:50:30.051330 RX DATLAT : PASS
2084 04:50:30.055200 RX DQ/DQS(Engine): PASS
2085 04:50:30.057991 TX OE : NO K
2086 04:50:30.058100 All Pass.
2087 04:50:30.058193
2088 04:50:30.058281 DramC Write-DBI off
2089 04:50:30.061774 PER_BANK_REFRESH: Hybrid Mode
2090 04:50:30.065138 TX_TRACKING: ON
2091 04:50:30.068510 [GetDramInforAfterCalByMRR] Vendor 6.
2092 04:50:30.072008 [GetDramInforAfterCalByMRR] Revision 606.
2093 04:50:30.074665 [GetDramInforAfterCalByMRR] Revision 2 0.
2094 04:50:30.074745 MR0 0x3b3b
2095 04:50:30.078038 MR8 0x5151
2096 04:50:30.081606 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2097 04:50:30.081686
2098 04:50:30.081749 MR0 0x3b3b
2099 04:50:30.081808 MR8 0x5151
2100 04:50:30.084958 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2101 04:50:30.085038
2102 04:50:30.094668 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2103 04:50:30.098210 [FAST_K] Save calibration result to emmc
2104 04:50:30.101440 [FAST_K] Save calibration result to emmc
2105 04:50:30.104761 dram_init: config_dvfs: 1
2106 04:50:30.108137 dramc_set_vcore_voltage set vcore to 662500
2107 04:50:30.111528 Read voltage for 1200, 2
2108 04:50:30.111608 Vio18 = 0
2109 04:50:30.114861 Vcore = 662500
2110 04:50:30.114941 Vdram = 0
2111 04:50:30.115004 Vddq = 0
2112 04:50:30.115062 Vmddr = 0
2113 04:50:30.121192 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2114 04:50:30.128277 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2115 04:50:30.128397 MEM_TYPE=3, freq_sel=15
2116 04:50:30.131537 sv_algorithm_assistance_LP4_1600
2117 04:50:30.134885 ============ PULL DRAM RESETB DOWN ============
2118 04:50:30.141353 ========== PULL DRAM RESETB DOWN end =========
2119 04:50:30.144441 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2120 04:50:30.147972 ===================================
2121 04:50:30.151502 LPDDR4 DRAM CONFIGURATION
2122 04:50:30.154883 ===================================
2123 04:50:30.154964 EX_ROW_EN[0] = 0x0
2124 04:50:30.158424 EX_ROW_EN[1] = 0x0
2125 04:50:30.158512 LP4Y_EN = 0x0
2126 04:50:30.161158 WORK_FSP = 0x0
2127 04:50:30.161238 WL = 0x4
2128 04:50:30.165003 RL = 0x4
2129 04:50:30.165082 BL = 0x2
2130 04:50:30.168193 RPST = 0x0
2131 04:50:30.168272 RD_PRE = 0x0
2132 04:50:30.171326 WR_PRE = 0x1
2133 04:50:30.171405 WR_PST = 0x0
2134 04:50:30.174537 DBI_WR = 0x0
2135 04:50:30.178313 DBI_RD = 0x0
2136 04:50:30.178393 OTF = 0x1
2137 04:50:30.181540 ===================================
2138 04:50:30.184937 ===================================
2139 04:50:30.185017 ANA top config
2140 04:50:30.188404 ===================================
2141 04:50:30.191146 DLL_ASYNC_EN = 0
2142 04:50:30.194576 ALL_SLAVE_EN = 0
2143 04:50:30.198081 NEW_RANK_MODE = 1
2144 04:50:30.198166 DLL_IDLE_MODE = 1
2145 04:50:30.201508 LP45_APHY_COMB_EN = 1
2146 04:50:30.204964 TX_ODT_DIS = 1
2147 04:50:30.208277 NEW_8X_MODE = 1
2148 04:50:30.211029 ===================================
2149 04:50:30.215029 ===================================
2150 04:50:30.218418 data_rate = 2400
2151 04:50:30.221185 CKR = 1
2152 04:50:30.221266 DQ_P2S_RATIO = 8
2153 04:50:30.224515 ===================================
2154 04:50:30.228038 CA_P2S_RATIO = 8
2155 04:50:30.231357 DQ_CA_OPEN = 0
2156 04:50:30.234675 DQ_SEMI_OPEN = 0
2157 04:50:30.237886 CA_SEMI_OPEN = 0
2158 04:50:30.237983 CA_FULL_RATE = 0
2159 04:50:30.241149 DQ_CKDIV4_EN = 0
2160 04:50:30.244650 CA_CKDIV4_EN = 0
2161 04:50:30.247994 CA_PREDIV_EN = 0
2162 04:50:30.251364 PH8_DLY = 17
2163 04:50:30.254750 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2164 04:50:30.254830 DQ_AAMCK_DIV = 4
2165 04:50:30.257930 CA_AAMCK_DIV = 4
2166 04:50:30.261657 CA_ADMCK_DIV = 4
2167 04:50:30.264699 DQ_TRACK_CA_EN = 0
2168 04:50:30.267923 CA_PICK = 1200
2169 04:50:30.271389 CA_MCKIO = 1200
2170 04:50:30.274781 MCKIO_SEMI = 0
2171 04:50:30.274864 PLL_FREQ = 2366
2172 04:50:30.277866 DQ_UI_PI_RATIO = 32
2173 04:50:30.281783 CA_UI_PI_RATIO = 0
2174 04:50:30.284958 ===================================
2175 04:50:30.288151 ===================================
2176 04:50:30.291464 memory_type:LPDDR4
2177 04:50:30.291537 GP_NUM : 10
2178 04:50:30.295012 SRAM_EN : 1
2179 04:50:30.298467 MD32_EN : 0
2180 04:50:30.301743 ===================================
2181 04:50:30.301841 [ANA_INIT] >>>>>>>>>>>>>>
2182 04:50:30.305240 <<<<<< [CONFIGURE PHASE]: ANA_TX
2183 04:50:30.308580 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2184 04:50:30.311985 ===================================
2185 04:50:30.314587 data_rate = 2400,PCW = 0X5b00
2186 04:50:30.317983 ===================================
2187 04:50:30.321279 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2188 04:50:30.327949 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2189 04:50:30.331388 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2190 04:50:30.338475 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2191 04:50:30.341943 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2192 04:50:30.345217 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2193 04:50:30.345298 [ANA_INIT] flow start
2194 04:50:30.348616 [ANA_INIT] PLL >>>>>>>>
2195 04:50:30.351875 [ANA_INIT] PLL <<<<<<<<
2196 04:50:30.351974 [ANA_INIT] MIDPI >>>>>>>>
2197 04:50:30.355347 [ANA_INIT] MIDPI <<<<<<<<
2198 04:50:30.358815 [ANA_INIT] DLL >>>>>>>>
2199 04:50:30.358889 [ANA_INIT] DLL <<<<<<<<
2200 04:50:30.362219 [ANA_INIT] flow end
2201 04:50:30.365486 ============ LP4 DIFF to SE enter ============
2202 04:50:30.369041 ============ LP4 DIFF to SE exit ============
2203 04:50:30.372131 [ANA_INIT] <<<<<<<<<<<<<
2204 04:50:30.375234 [Flow] Enable top DCM control >>>>>
2205 04:50:30.378856 [Flow] Enable top DCM control <<<<<
2206 04:50:30.382160 Enable DLL master slave shuffle
2207 04:50:30.388784 ==============================================================
2208 04:50:30.388866 Gating Mode config
2209 04:50:30.395653 ==============================================================
2210 04:50:30.395735 Config description:
2211 04:50:30.405452 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2212 04:50:30.412105 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2213 04:50:30.418836 SELPH_MODE 0: By rank 1: By Phase
2214 04:50:30.422305 ==============================================================
2215 04:50:30.425670 GAT_TRACK_EN = 1
2216 04:50:30.428483 RX_GATING_MODE = 2
2217 04:50:30.431801 RX_GATING_TRACK_MODE = 2
2218 04:50:30.435093 SELPH_MODE = 1
2219 04:50:30.438495 PICG_EARLY_EN = 1
2220 04:50:30.441793 VALID_LAT_VALUE = 1
2221 04:50:30.448264 ==============================================================
2222 04:50:30.452205 Enter into Gating configuration >>>>
2223 04:50:30.452353 Exit from Gating configuration <<<<
2224 04:50:30.455495 Enter into DVFS_PRE_config >>>>>
2225 04:50:30.468457 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2226 04:50:30.471910 Exit from DVFS_PRE_config <<<<<
2227 04:50:30.475356 Enter into PICG configuration >>>>
2228 04:50:30.478739 Exit from PICG configuration <<<<
2229 04:50:30.478820 [RX_INPUT] configuration >>>>>
2230 04:50:30.482163 [RX_INPUT] configuration <<<<<
2231 04:50:30.488664 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2232 04:50:30.492220 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2233 04:50:30.498780 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2234 04:50:30.505509 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2235 04:50:30.512223 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2236 04:50:30.518754 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2237 04:50:30.522122 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2238 04:50:30.525532 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2239 04:50:30.528745 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2240 04:50:30.535594 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2241 04:50:30.538962 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2242 04:50:30.542380 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2243 04:50:30.545260 ===================================
2244 04:50:30.548681 LPDDR4 DRAM CONFIGURATION
2245 04:50:30.552195 ===================================
2246 04:50:30.555380 EX_ROW_EN[0] = 0x0
2247 04:50:30.555461 EX_ROW_EN[1] = 0x0
2248 04:50:30.558750 LP4Y_EN = 0x0
2249 04:50:30.558822 WORK_FSP = 0x0
2250 04:50:30.562079 WL = 0x4
2251 04:50:30.562161 RL = 0x4
2252 04:50:30.565391 BL = 0x2
2253 04:50:30.565471 RPST = 0x0
2254 04:50:30.568767 RD_PRE = 0x0
2255 04:50:30.568847 WR_PRE = 0x1
2256 04:50:30.571942 WR_PST = 0x0
2257 04:50:30.572023 DBI_WR = 0x0
2258 04:50:30.575305 DBI_RD = 0x0
2259 04:50:30.575386 OTF = 0x1
2260 04:50:30.578722 ===================================
2261 04:50:30.582265 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2262 04:50:30.589110 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2263 04:50:30.591903 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2264 04:50:30.595330 ===================================
2265 04:50:30.598662 LPDDR4 DRAM CONFIGURATION
2266 04:50:30.601817 ===================================
2267 04:50:30.601900 EX_ROW_EN[0] = 0x10
2268 04:50:30.605625 EX_ROW_EN[1] = 0x0
2269 04:50:30.608707 LP4Y_EN = 0x0
2270 04:50:30.608782 WORK_FSP = 0x0
2271 04:50:30.611870 WL = 0x4
2272 04:50:30.611940 RL = 0x4
2273 04:50:30.615599 BL = 0x2
2274 04:50:30.615674 RPST = 0x0
2275 04:50:30.618780 RD_PRE = 0x0
2276 04:50:30.618889 WR_PRE = 0x1
2277 04:50:30.622254 WR_PST = 0x0
2278 04:50:30.622324 DBI_WR = 0x0
2279 04:50:30.625698 DBI_RD = 0x0
2280 04:50:30.625765 OTF = 0x1
2281 04:50:30.628975 ===================================
2282 04:50:30.635668 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2283 04:50:30.635746 ==
2284 04:50:30.638850 Dram Type= 6, Freq= 0, CH_0, rank 0
2285 04:50:30.641909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2286 04:50:30.641980 ==
2287 04:50:30.645329 [Duty_Offset_Calibration]
2288 04:50:30.648860 B0:2 B1:1 CA:1
2289 04:50:30.648939
2290 04:50:30.651714 [DutyScan_Calibration_Flow] k_type=0
2291 04:50:30.660022
2292 04:50:30.660097 ==CLK 0==
2293 04:50:30.663274 Final CLK duty delay cell = 0
2294 04:50:30.666937 [0] MAX Duty = 5187%(X100), DQS PI = 24
2295 04:50:30.670263 [0] MIN Duty = 4844%(X100), DQS PI = 48
2296 04:50:30.670343 [0] AVG Duty = 5015%(X100)
2297 04:50:30.670411
2298 04:50:30.673484 CH0 CLK Duty spec in!! Max-Min= 343%
2299 04:50:30.680553 [DutyScan_Calibration_Flow] ====Done====
2300 04:50:30.680633
2301 04:50:30.683320 [DutyScan_Calibration_Flow] k_type=1
2302 04:50:30.698562
2303 04:50:30.698641 ==DQS 0 ==
2304 04:50:30.702011 Final DQS duty delay cell = -4
2305 04:50:30.705583 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2306 04:50:30.708992 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2307 04:50:30.711756 [-4] AVG Duty = 4937%(X100)
2308 04:50:30.711835
2309 04:50:30.711897 ==DQS 1 ==
2310 04:50:30.715581 Final DQS duty delay cell = 0
2311 04:50:30.718781 [0] MAX Duty = 5187%(X100), DQS PI = 62
2312 04:50:30.721917 [0] MIN Duty = 5000%(X100), DQS PI = 36
2313 04:50:30.725574 [0] AVG Duty = 5093%(X100)
2314 04:50:30.725647
2315 04:50:30.728472 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2316 04:50:30.728544
2317 04:50:30.732062 CH0 DQS 1 Duty spec in!! Max-Min= 187%
2318 04:50:30.735365 [DutyScan_Calibration_Flow] ====Done====
2319 04:50:30.735464
2320 04:50:30.738871 [DutyScan_Calibration_Flow] k_type=3
2321 04:50:30.755542
2322 04:50:30.755618 ==DQM 0 ==
2323 04:50:30.759161 Final DQM duty delay cell = 0
2324 04:50:30.762132 [0] MAX Duty = 5156%(X100), DQS PI = 30
2325 04:50:30.765282 [0] MIN Duty = 4906%(X100), DQS PI = 58
2326 04:50:30.765357 [0] AVG Duty = 5031%(X100)
2327 04:50:30.768821
2328 04:50:30.768889 ==DQM 1 ==
2329 04:50:30.772452 Final DQM duty delay cell = 0
2330 04:50:30.775815 [0] MAX Duty = 5125%(X100), DQS PI = 60
2331 04:50:30.778857 [0] MIN Duty = 5031%(X100), DQS PI = 36
2332 04:50:30.778956 [0] AVG Duty = 5078%(X100)
2333 04:50:30.779049
2334 04:50:30.785579 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2335 04:50:30.785661
2336 04:50:30.789362 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2337 04:50:30.792635 [DutyScan_Calibration_Flow] ====Done====
2338 04:50:30.792739
2339 04:50:30.795956 [DutyScan_Calibration_Flow] k_type=2
2340 04:50:30.811862
2341 04:50:30.811941 ==DQ 0 ==
2342 04:50:30.815231 Final DQ duty delay cell = 0
2343 04:50:30.818637 [0] MAX Duty = 5031%(X100), DQS PI = 24
2344 04:50:30.822199 [0] MIN Duty = 4875%(X100), DQS PI = 62
2345 04:50:30.822278 [0] AVG Duty = 4953%(X100)
2346 04:50:30.822341
2347 04:50:30.825455 ==DQ 1 ==
2348 04:50:30.829007 Final DQ duty delay cell = 0
2349 04:50:30.832275 [0] MAX Duty = 5093%(X100), DQS PI = 24
2350 04:50:30.835315 [0] MIN Duty = 4938%(X100), DQS PI = 36
2351 04:50:30.835394 [0] AVG Duty = 5015%(X100)
2352 04:50:30.835456
2353 04:50:30.838880 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2354 04:50:30.838960
2355 04:50:30.842356 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2356 04:50:30.849263 [DutyScan_Calibration_Flow] ====Done====
2357 04:50:30.849343 ==
2358 04:50:30.852009 Dram Type= 6, Freq= 0, CH_1, rank 0
2359 04:50:30.855392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2360 04:50:30.855472 ==
2361 04:50:30.858777 [Duty_Offset_Calibration]
2362 04:50:30.858856 B0:1 B1:0 CA:0
2363 04:50:30.858918
2364 04:50:30.862279 [DutyScan_Calibration_Flow] k_type=0
2365 04:50:30.871405
2366 04:50:30.871487 ==CLK 0==
2367 04:50:30.874651 Final CLK duty delay cell = -4
2368 04:50:30.877936 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2369 04:50:30.881179 [-4] MIN Duty = 4907%(X100), DQS PI = 50
2370 04:50:30.884491 [-4] AVG Duty = 4969%(X100)
2371 04:50:30.884570
2372 04:50:30.887808 CH1 CLK Duty spec in!! Max-Min= 124%
2373 04:50:30.891567 [DutyScan_Calibration_Flow] ====Done====
2374 04:50:30.891647
2375 04:50:30.894542 [DutyScan_Calibration_Flow] k_type=1
2376 04:50:30.911147
2377 04:50:30.911227 ==DQS 0 ==
2378 04:50:30.914545 Final DQS duty delay cell = 0
2379 04:50:30.918153 [0] MAX Duty = 5094%(X100), DQS PI = 26
2380 04:50:30.921403 [0] MIN Duty = 4875%(X100), DQS PI = 0
2381 04:50:30.921483 [0] AVG Duty = 4984%(X100)
2382 04:50:30.924129
2383 04:50:30.924209 ==DQS 1 ==
2384 04:50:30.927486 Final DQS duty delay cell = 0
2385 04:50:30.930937 [0] MAX Duty = 5187%(X100), DQS PI = 18
2386 04:50:30.934379 [0] MIN Duty = 4969%(X100), DQS PI = 10
2387 04:50:30.934463 [0] AVG Duty = 5078%(X100)
2388 04:50:30.937945
2389 04:50:30.941369 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2390 04:50:30.941449
2391 04:50:30.944667 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2392 04:50:30.947829 [DutyScan_Calibration_Flow] ====Done====
2393 04:50:30.947904
2394 04:50:30.950976 [DutyScan_Calibration_Flow] k_type=3
2395 04:50:30.967936
2396 04:50:30.968021 ==DQM 0 ==
2397 04:50:30.971341 Final DQM duty delay cell = 0
2398 04:50:30.974493 [0] MAX Duty = 5156%(X100), DQS PI = 6
2399 04:50:30.977896 [0] MIN Duty = 5031%(X100), DQS PI = 0
2400 04:50:30.977967 [0] AVG Duty = 5093%(X100)
2401 04:50:30.978027
2402 04:50:30.981278 ==DQM 1 ==
2403 04:50:30.984832 Final DQM duty delay cell = 0
2404 04:50:30.988043 [0] MAX Duty = 5031%(X100), DQS PI = 16
2405 04:50:30.991370 [0] MIN Duty = 4907%(X100), DQS PI = 36
2406 04:50:30.991451 [0] AVG Duty = 4969%(X100)
2407 04:50:30.991516
2408 04:50:30.997523 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2409 04:50:30.997603
2410 04:50:31.000991 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2411 04:50:31.004328 [DutyScan_Calibration_Flow] ====Done====
2412 04:50:31.004421
2413 04:50:31.007639 [DutyScan_Calibration_Flow] k_type=2
2414 04:50:31.023223
2415 04:50:31.023303 ==DQ 0 ==
2416 04:50:31.026679 Final DQ duty delay cell = -4
2417 04:50:31.030159 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2418 04:50:31.033513 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2419 04:50:31.036723 [-4] AVG Duty = 4984%(X100)
2420 04:50:31.036810
2421 04:50:31.036880 ==DQ 1 ==
2422 04:50:31.040417 Final DQ duty delay cell = 0
2423 04:50:31.042985 [0] MAX Duty = 5125%(X100), DQS PI = 20
2424 04:50:31.046441 [0] MIN Duty = 4969%(X100), DQS PI = 12
2425 04:50:31.046522 [0] AVG Duty = 5047%(X100)
2426 04:50:31.049986
2427 04:50:31.053458 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2428 04:50:31.053538
2429 04:50:31.056874 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2430 04:50:31.060157 [DutyScan_Calibration_Flow] ====Done====
2431 04:50:31.063382 nWR fixed to 30
2432 04:50:31.063465 [ModeRegInit_LP4] CH0 RK0
2433 04:50:31.066681 [ModeRegInit_LP4] CH0 RK1
2434 04:50:31.069856 [ModeRegInit_LP4] CH1 RK0
2435 04:50:31.073044 [ModeRegInit_LP4] CH1 RK1
2436 04:50:31.073124 match AC timing 7
2437 04:50:31.076632 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2438 04:50:31.083265 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2439 04:50:31.086752 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2440 04:50:31.089787 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2441 04:50:31.096890 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2442 04:50:31.096965 ==
2443 04:50:31.100060 Dram Type= 6, Freq= 0, CH_0, rank 0
2444 04:50:31.103420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2445 04:50:31.103495 ==
2446 04:50:31.110339 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2447 04:50:31.116445 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2448 04:50:31.123588 [CA 0] Center 39 (8~70) winsize 63
2449 04:50:31.126765 [CA 1] Center 39 (8~70) winsize 63
2450 04:50:31.130527 [CA 2] Center 35 (5~66) winsize 62
2451 04:50:31.133792 [CA 3] Center 34 (4~65) winsize 62
2452 04:50:31.136801 [CA 4] Center 33 (3~64) winsize 62
2453 04:50:31.140607 [CA 5] Center 32 (3~62) winsize 60
2454 04:50:31.140686
2455 04:50:31.143958 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2456 04:50:31.144038
2457 04:50:31.146703 [CATrainingPosCal] consider 1 rank data
2458 04:50:31.150136 u2DelayCellTimex100 = 270/100 ps
2459 04:50:31.153597 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2460 04:50:31.157116 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2461 04:50:31.163879 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2462 04:50:31.167249 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2463 04:50:31.170468 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2464 04:50:31.173917 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2465 04:50:31.173997
2466 04:50:31.177340 CA PerBit enable=1, Macro0, CA PI delay=32
2467 04:50:31.177420
2468 04:50:31.180082 [CBTSetCACLKResult] CA Dly = 32
2469 04:50:31.180160 CS Dly: 6 (0~37)
2470 04:50:31.180223 ==
2471 04:50:31.183393 Dram Type= 6, Freq= 0, CH_0, rank 1
2472 04:50:31.190118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2473 04:50:31.190199 ==
2474 04:50:31.193421 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2475 04:50:31.200252 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2476 04:50:31.209661 [CA 0] Center 38 (8~69) winsize 62
2477 04:50:31.212911 [CA 1] Center 38 (8~69) winsize 62
2478 04:50:31.216175 [CA 2] Center 35 (4~66) winsize 63
2479 04:50:31.219375 [CA 3] Center 34 (4~65) winsize 62
2480 04:50:31.222767 [CA 4] Center 33 (3~64) winsize 62
2481 04:50:31.226266 [CA 5] Center 32 (3~62) winsize 60
2482 04:50:31.226368
2483 04:50:31.229609 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2484 04:50:31.229704
2485 04:50:31.232881 [CATrainingPosCal] consider 2 rank data
2486 04:50:31.236493 u2DelayCellTimex100 = 270/100 ps
2487 04:50:31.239119 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2488 04:50:31.242703 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2489 04:50:31.249772 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2490 04:50:31.252761 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2491 04:50:31.256302 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2492 04:50:31.259047 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2493 04:50:31.259149
2494 04:50:31.262513 CA PerBit enable=1, Macro0, CA PI delay=32
2495 04:50:31.262610
2496 04:50:31.266038 [CBTSetCACLKResult] CA Dly = 32
2497 04:50:31.266118 CS Dly: 6 (0~38)
2498 04:50:31.266182
2499 04:50:31.269423 ----->DramcWriteLeveling(PI) begin...
2500 04:50:31.269508 ==
2501 04:50:31.272739 Dram Type= 6, Freq= 0, CH_0, rank 0
2502 04:50:31.279650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2503 04:50:31.279731 ==
2504 04:50:31.283034 Write leveling (Byte 0): 34 => 34
2505 04:50:31.286476 Write leveling (Byte 1): 32 => 32
2506 04:50:31.286556 DramcWriteLeveling(PI) end<-----
2507 04:50:31.289406
2508 04:50:31.289486 ==
2509 04:50:31.293290 Dram Type= 6, Freq= 0, CH_0, rank 0
2510 04:50:31.296375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2511 04:50:31.296463 ==
2512 04:50:31.299556 [Gating] SW mode calibration
2513 04:50:31.306298 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2514 04:50:31.310006 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2515 04:50:31.316498 0 15 0 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
2516 04:50:31.319580 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2517 04:50:31.322857 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2518 04:50:31.329982 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2519 04:50:31.333305 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2520 04:50:31.336484 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 04:50:31.343366 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2522 04:50:31.346632 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 0) (1 0)
2523 04:50:31.350123 1 0 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
2524 04:50:31.353503 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 04:50:31.360175 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 04:50:31.363107 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 04:50:31.366727 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 04:50:31.373411 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 04:50:31.376801 1 0 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2530 04:50:31.380160 1 0 28 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
2531 04:50:31.386333 1 1 0 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
2532 04:50:31.389880 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 04:50:31.393257 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 04:50:31.400103 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 04:50:31.403541 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 04:50:31.406787 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 04:50:31.413051 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 04:50:31.416790 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2539 04:50:31.419544 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2540 04:50:31.426917 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 04:50:31.430284 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 04:50:31.432985 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 04:50:31.437276 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 04:50:31.443528 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 04:50:31.446440 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 04:50:31.449959 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 04:50:31.456587 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 04:50:31.460042 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 04:50:31.463381 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 04:50:31.470318 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 04:50:31.473499 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 04:50:31.476751 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 04:50:31.483343 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 04:50:31.486537 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2555 04:50:31.489967 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2556 04:50:31.493441 Total UI for P1: 0, mck2ui 16
2557 04:50:31.496739 best dqsien dly found for B0: ( 1, 3, 28)
2558 04:50:31.503730 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 04:50:31.503811 Total UI for P1: 0, mck2ui 16
2560 04:50:31.506381 best dqsien dly found for B1: ( 1, 4, 0)
2561 04:50:31.513303 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2562 04:50:31.516516 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2563 04:50:31.516597
2564 04:50:31.520143 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2565 04:50:31.523168 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2566 04:50:31.526859 [Gating] SW calibration Done
2567 04:50:31.526940 ==
2568 04:50:31.530292 Dram Type= 6, Freq= 0, CH_0, rank 0
2569 04:50:31.533492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2570 04:50:31.533574 ==
2571 04:50:31.536804 RX Vref Scan: 0
2572 04:50:31.536887
2573 04:50:31.536951 RX Vref 0 -> 0, step: 1
2574 04:50:31.537011
2575 04:50:31.540443 RX Delay -40 -> 252, step: 8
2576 04:50:31.543690 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2577 04:50:31.546448 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2578 04:50:31.553396 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2579 04:50:31.556714 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2580 04:50:31.559880 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2581 04:50:31.563704 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2582 04:50:31.566883 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2583 04:50:31.573204 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2584 04:50:31.576645 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2585 04:50:31.580082 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2586 04:50:31.583342 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2587 04:50:31.587335 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2588 04:50:31.593473 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2589 04:50:31.596975 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2590 04:50:31.600411 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2591 04:50:31.603643 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2592 04:50:31.603715 ==
2593 04:50:31.607194 Dram Type= 6, Freq= 0, CH_0, rank 0
2594 04:50:31.610578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2595 04:50:31.613908 ==
2596 04:50:31.613989 DQS Delay:
2597 04:50:31.614054 DQS0 = 0, DQS1 = 0
2598 04:50:31.617339 DQM Delay:
2599 04:50:31.617420 DQM0 = 121, DQM1 = 113
2600 04:50:31.620328 DQ Delay:
2601 04:50:31.623607 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2602 04:50:31.626845 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2603 04:50:31.630472 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2604 04:50:31.634137 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2605 04:50:31.634218
2606 04:50:31.634282
2607 04:50:31.634342 ==
2608 04:50:31.637243 Dram Type= 6, Freq= 0, CH_0, rank 0
2609 04:50:31.640554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2610 04:50:31.640636 ==
2611 04:50:31.640700
2612 04:50:31.640761
2613 04:50:31.643846 TX Vref Scan disable
2614 04:50:31.647064 == TX Byte 0 ==
2615 04:50:31.650546 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2616 04:50:31.653817 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2617 04:50:31.657384 == TX Byte 1 ==
2618 04:50:31.660759 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2619 04:50:31.664076 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2620 04:50:31.664156 ==
2621 04:50:31.667308 Dram Type= 6, Freq= 0, CH_0, rank 0
2622 04:50:31.670521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2623 04:50:31.673743 ==
2624 04:50:31.683769 TX Vref=22, minBit 11, minWin=24, winSum=403
2625 04:50:31.687261 TX Vref=24, minBit 11, minWin=24, winSum=407
2626 04:50:31.690729 TX Vref=26, minBit 4, minWin=25, winSum=413
2627 04:50:31.694108 TX Vref=28, minBit 0, minWin=26, winSum=420
2628 04:50:31.696923 TX Vref=30, minBit 0, minWin=26, winSum=419
2629 04:50:31.703721 TX Vref=32, minBit 0, minWin=26, winSum=417
2630 04:50:31.707744 [TxChooseVref] Worse bit 0, Min win 26, Win sum 420, Final Vref 28
2631 04:50:31.707825
2632 04:50:31.710763 Final TX Range 1 Vref 28
2633 04:50:31.710845
2634 04:50:31.710908 ==
2635 04:50:31.713813 Dram Type= 6, Freq= 0, CH_0, rank 0
2636 04:50:31.717110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2637 04:50:31.717192 ==
2638 04:50:31.720730
2639 04:50:31.720810
2640 04:50:31.720874 TX Vref Scan disable
2641 04:50:31.723698 == TX Byte 0 ==
2642 04:50:31.726875 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2643 04:50:31.730437 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2644 04:50:31.733845 == TX Byte 1 ==
2645 04:50:31.737091 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2646 04:50:31.740467 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2647 04:50:31.740552
2648 04:50:31.744099 [DATLAT]
2649 04:50:31.744180 Freq=1200, CH0 RK0
2650 04:50:31.744245
2651 04:50:31.747177 DATLAT Default: 0xd
2652 04:50:31.747257 0, 0xFFFF, sum = 0
2653 04:50:31.750419 1, 0xFFFF, sum = 0
2654 04:50:31.750517 2, 0xFFFF, sum = 0
2655 04:50:31.754371 3, 0xFFFF, sum = 0
2656 04:50:31.754454 4, 0xFFFF, sum = 0
2657 04:50:31.757487 5, 0xFFFF, sum = 0
2658 04:50:31.757569 6, 0xFFFF, sum = 0
2659 04:50:31.760682 7, 0xFFFF, sum = 0
2660 04:50:31.760764 8, 0xFFFF, sum = 0
2661 04:50:31.763920 9, 0xFFFF, sum = 0
2662 04:50:31.767400 10, 0xFFFF, sum = 0
2663 04:50:31.767482 11, 0xFFFF, sum = 0
2664 04:50:31.770846 12, 0x0, sum = 1
2665 04:50:31.770928 13, 0x0, sum = 2
2666 04:50:31.770993 14, 0x0, sum = 3
2667 04:50:31.774293 15, 0x0, sum = 4
2668 04:50:31.774376 best_step = 13
2669 04:50:31.774439
2670 04:50:31.774499 ==
2671 04:50:31.777682 Dram Type= 6, Freq= 0, CH_0, rank 0
2672 04:50:31.783858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2673 04:50:31.783940 ==
2674 04:50:31.784004 RX Vref Scan: 1
2675 04:50:31.784065
2676 04:50:31.787416 Set Vref Range= 32 -> 127
2677 04:50:31.787498
2678 04:50:31.790728 RX Vref 32 -> 127, step: 1
2679 04:50:31.790809
2680 04:50:31.794167 RX Delay -13 -> 252, step: 4
2681 04:50:31.794248
2682 04:50:31.797599 Set Vref, RX VrefLevel [Byte0]: 32
2683 04:50:31.801074 [Byte1]: 32
2684 04:50:31.801156
2685 04:50:31.803804 Set Vref, RX VrefLevel [Byte0]: 33
2686 04:50:31.807236 [Byte1]: 33
2687 04:50:31.807317
2688 04:50:31.810548 Set Vref, RX VrefLevel [Byte0]: 34
2689 04:50:31.813984 [Byte1]: 34
2690 04:50:31.818324
2691 04:50:31.818404 Set Vref, RX VrefLevel [Byte0]: 35
2692 04:50:31.821646 [Byte1]: 35
2693 04:50:31.826249
2694 04:50:31.826330 Set Vref, RX VrefLevel [Byte0]: 36
2695 04:50:31.829487 [Byte1]: 36
2696 04:50:31.833963
2697 04:50:31.834044 Set Vref, RX VrefLevel [Byte0]: 37
2698 04:50:31.837023 [Byte1]: 37
2699 04:50:31.841621
2700 04:50:31.841701 Set Vref, RX VrefLevel [Byte0]: 38
2701 04:50:31.845243 [Byte1]: 38
2702 04:50:31.849479
2703 04:50:31.849559 Set Vref, RX VrefLevel [Byte0]: 39
2704 04:50:31.853138 [Byte1]: 39
2705 04:50:31.857309
2706 04:50:31.857390 Set Vref, RX VrefLevel [Byte0]: 40
2707 04:50:31.861227 [Byte1]: 40
2708 04:50:31.865503
2709 04:50:31.865583 Set Vref, RX VrefLevel [Byte0]: 41
2710 04:50:31.868639 [Byte1]: 41
2711 04:50:31.873094
2712 04:50:31.873174 Set Vref, RX VrefLevel [Byte0]: 42
2713 04:50:31.877003 [Byte1]: 42
2714 04:50:31.880924
2715 04:50:31.881005 Set Vref, RX VrefLevel [Byte0]: 43
2716 04:50:31.884242 [Byte1]: 43
2717 04:50:31.888901
2718 04:50:31.888982 Set Vref, RX VrefLevel [Byte0]: 44
2719 04:50:31.892214 [Byte1]: 44
2720 04:50:31.896966
2721 04:50:31.897054 Set Vref, RX VrefLevel [Byte0]: 45
2722 04:50:31.900439 [Byte1]: 45
2723 04:50:31.904456
2724 04:50:31.904539 Set Vref, RX VrefLevel [Byte0]: 46
2725 04:50:31.907834 [Byte1]: 46
2726 04:50:31.912625
2727 04:50:31.912698 Set Vref, RX VrefLevel [Byte0]: 47
2728 04:50:31.916127 [Byte1]: 47
2729 04:50:31.920906
2730 04:50:31.920982 Set Vref, RX VrefLevel [Byte0]: 48
2731 04:50:31.923730 [Byte1]: 48
2732 04:50:31.928282
2733 04:50:31.928387 Set Vref, RX VrefLevel [Byte0]: 49
2734 04:50:31.931750 [Byte1]: 49
2735 04:50:31.936669
2736 04:50:31.936744 Set Vref, RX VrefLevel [Byte0]: 50
2737 04:50:31.939443 [Byte1]: 50
2738 04:50:31.944024
2739 04:50:31.944098 Set Vref, RX VrefLevel [Byte0]: 51
2740 04:50:31.947243 [Byte1]: 51
2741 04:50:31.952214
2742 04:50:31.952337 Set Vref, RX VrefLevel [Byte0]: 52
2743 04:50:31.955590 [Byte1]: 52
2744 04:50:31.960054
2745 04:50:31.960156 Set Vref, RX VrefLevel [Byte0]: 53
2746 04:50:31.963713 [Byte1]: 53
2747 04:50:31.967799
2748 04:50:31.967905 Set Vref, RX VrefLevel [Byte0]: 54
2749 04:50:31.970984 [Byte1]: 54
2750 04:50:31.975688
2751 04:50:31.975767 Set Vref, RX VrefLevel [Byte0]: 55
2752 04:50:31.979170 [Byte1]: 55
2753 04:50:31.983957
2754 04:50:31.984035 Set Vref, RX VrefLevel [Byte0]: 56
2755 04:50:31.987266 [Byte1]: 56
2756 04:50:31.991453
2757 04:50:31.991532 Set Vref, RX VrefLevel [Byte0]: 57
2758 04:50:31.994828 [Byte1]: 57
2759 04:50:31.999238
2760 04:50:31.999317 Set Vref, RX VrefLevel [Byte0]: 58
2761 04:50:32.002803 [Byte1]: 58
2762 04:50:32.007120
2763 04:50:32.007225 Set Vref, RX VrefLevel [Byte0]: 59
2764 04:50:32.010650 [Byte1]: 59
2765 04:50:32.015442
2766 04:50:32.015521 Set Vref, RX VrefLevel [Byte0]: 60
2767 04:50:32.018888 [Byte1]: 60
2768 04:50:32.023619
2769 04:50:32.023697 Set Vref, RX VrefLevel [Byte0]: 61
2770 04:50:32.026376 [Byte1]: 61
2771 04:50:32.031117
2772 04:50:32.031195 Set Vref, RX VrefLevel [Byte0]: 62
2773 04:50:32.034709 [Byte1]: 62
2774 04:50:32.038829
2775 04:50:32.038934 Set Vref, RX VrefLevel [Byte0]: 63
2776 04:50:32.042261 [Byte1]: 63
2777 04:50:32.047085
2778 04:50:32.047164 Set Vref, RX VrefLevel [Byte0]: 64
2779 04:50:32.050362 [Byte1]: 64
2780 04:50:32.055051
2781 04:50:32.055131 Set Vref, RX VrefLevel [Byte0]: 65
2782 04:50:32.058280 [Byte1]: 65
2783 04:50:32.062452
2784 04:50:32.062530 Set Vref, RX VrefLevel [Byte0]: 66
2785 04:50:32.065796 [Byte1]: 66
2786 04:50:32.070430
2787 04:50:32.070512 Set Vref, RX VrefLevel [Byte0]: 67
2788 04:50:32.073696 [Byte1]: 67
2789 04:50:32.078269
2790 04:50:32.078357 Set Vref, RX VrefLevel [Byte0]: 68
2791 04:50:32.081743 [Byte1]: 68
2792 04:50:32.086522
2793 04:50:32.086605 Final RX Vref Byte 0 = 56 to rank0
2794 04:50:32.089625 Final RX Vref Byte 1 = 46 to rank0
2795 04:50:32.092926 Final RX Vref Byte 0 = 56 to rank1
2796 04:50:32.096404 Final RX Vref Byte 1 = 46 to rank1==
2797 04:50:32.099735 Dram Type= 6, Freq= 0, CH_0, rank 0
2798 04:50:32.105804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2799 04:50:32.105886 ==
2800 04:50:32.105951 DQS Delay:
2801 04:50:32.106011 DQS0 = 0, DQS1 = 0
2802 04:50:32.109499 DQM Delay:
2803 04:50:32.109580 DQM0 = 120, DQM1 = 110
2804 04:50:32.113511 DQ Delay:
2805 04:50:32.116647 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2806 04:50:32.119716 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2807 04:50:32.122704 DQ8 =96, DQ9 =98, DQ10 =112, DQ11 =104
2808 04:50:32.125935 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118
2809 04:50:32.126016
2810 04:50:32.126080
2811 04:50:32.132735 [DQSOSCAuto] RK0, (LSB)MR18= 0x130c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2812 04:50:32.136120 CH0 RK0: MR19=404, MR18=130C
2813 04:50:32.143049 CH0_RK0: MR19=0x404, MR18=0x130C, DQSOSC=402, MR23=63, INC=40, DEC=27
2814 04:50:32.143131
2815 04:50:32.146571 ----->DramcWriteLeveling(PI) begin...
2816 04:50:32.146654 ==
2817 04:50:32.149346 Dram Type= 6, Freq= 0, CH_0, rank 1
2818 04:50:32.153283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2819 04:50:32.156584 ==
2820 04:50:32.156695 Write leveling (Byte 0): 34 => 34
2821 04:50:32.160016 Write leveling (Byte 1): 30 => 30
2822 04:50:32.163243 DramcWriteLeveling(PI) end<-----
2823 04:50:32.163324
2824 04:50:32.163390 ==
2825 04:50:32.166665 Dram Type= 6, Freq= 0, CH_0, rank 1
2826 04:50:32.172886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2827 04:50:32.172968 ==
2828 04:50:32.173032 [Gating] SW mode calibration
2829 04:50:32.183364 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2830 04:50:32.186116 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2831 04:50:32.189420 0 15 0 | B1->B0 | 3434 2d2d | 0 0 | (0 0) (0 0)
2832 04:50:32.196133 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2833 04:50:32.199869 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2834 04:50:32.203107 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2835 04:50:32.210018 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2836 04:50:32.213401 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2837 04:50:32.216073 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
2838 04:50:32.223047 0 15 28 | B1->B0 | 2f2f 2d2d | 1 0 | (1 0) (0 0)
2839 04:50:32.226242 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2840 04:50:32.229787 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2841 04:50:32.236739 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2842 04:50:32.239800 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2843 04:50:32.242713 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2844 04:50:32.249598 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 04:50:32.252873 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2846 04:50:32.256223 1 0 28 | B1->B0 | 3737 3838 | 0 0 | (0 0) (0 0)
2847 04:50:32.262988 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2848 04:50:32.266235 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2849 04:50:32.269644 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2850 04:50:32.273033 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2851 04:50:32.279927 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 04:50:32.283316 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 04:50:32.286213 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 04:50:32.293256 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2855 04:50:32.296458 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2856 04:50:32.299866 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2857 04:50:32.306356 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 04:50:32.309639 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 04:50:32.312983 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 04:50:32.319176 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 04:50:32.322679 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 04:50:32.326014 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 04:50:32.332759 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 04:50:32.335951 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 04:50:32.339291 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 04:50:32.345918 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 04:50:32.349341 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 04:50:32.352540 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 04:50:32.359496 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 04:50:32.362961 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2871 04:50:32.366237 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2872 04:50:32.369538 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 04:50:32.373356 Total UI for P1: 0, mck2ui 16
2874 04:50:32.376547 best dqsien dly found for B0: ( 1, 3, 30)
2875 04:50:32.379832 Total UI for P1: 0, mck2ui 16
2876 04:50:32.383488 best dqsien dly found for B1: ( 1, 3, 30)
2877 04:50:32.386274 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2878 04:50:32.389797 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2879 04:50:32.393201
2880 04:50:32.396673 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2881 04:50:32.399825 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2882 04:50:32.402938 [Gating] SW calibration Done
2883 04:50:32.403019 ==
2884 04:50:32.406193 Dram Type= 6, Freq= 0, CH_0, rank 1
2885 04:50:32.409344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2886 04:50:32.409426 ==
2887 04:50:32.409491 RX Vref Scan: 0
2888 04:50:32.409551
2889 04:50:32.413224 RX Vref 0 -> 0, step: 1
2890 04:50:32.413305
2891 04:50:32.416418 RX Delay -40 -> 252, step: 8
2892 04:50:32.419588 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2893 04:50:32.423099 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2894 04:50:32.430091 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2895 04:50:32.432741 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2896 04:50:32.436101 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2897 04:50:32.439343 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2898 04:50:32.442704 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2899 04:50:32.446431 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2900 04:50:32.452748 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2901 04:50:32.456211 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2902 04:50:32.459375 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2903 04:50:32.462711 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2904 04:50:32.469615 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2905 04:50:32.473003 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2906 04:50:32.476340 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2907 04:50:32.479665 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2908 04:50:32.479745 ==
2909 04:50:32.482964 Dram Type= 6, Freq= 0, CH_0, rank 1
2910 04:50:32.486229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2911 04:50:32.489741 ==
2912 04:50:32.489810 DQS Delay:
2913 04:50:32.489869 DQS0 = 0, DQS1 = 0
2914 04:50:32.493090 DQM Delay:
2915 04:50:32.493158 DQM0 = 121, DQM1 = 112
2916 04:50:32.496435 DQ Delay:
2917 04:50:32.499913 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2918 04:50:32.503346 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2919 04:50:32.506658 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2920 04:50:32.509961 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2921 04:50:32.510046
2922 04:50:32.510109
2923 04:50:32.510167 ==
2924 04:50:32.513275 Dram Type= 6, Freq= 0, CH_0, rank 1
2925 04:50:32.516651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2926 04:50:32.516732 ==
2927 04:50:32.516796
2928 04:50:32.516860
2929 04:50:32.519824 TX Vref Scan disable
2930 04:50:32.523156 == TX Byte 0 ==
2931 04:50:32.526615 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2932 04:50:32.529703 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2933 04:50:32.533069 == TX Byte 1 ==
2934 04:50:32.536610 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2935 04:50:32.539999 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2936 04:50:38.597519 ==
2937 04:50:38.597876 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 04:50:38.597953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 04:50:38.598023 ==
2940 04:50:38.598089 TX Vref=22, minBit 1, minWin=25, winSum=411
2941 04:50:38.598155 TX Vref=24, minBit 12, minWin=25, winSum=415
2942 04:50:38.598211 TX Vref=26, minBit 10, minWin=25, winSum=422
2943 04:50:38.598265 TX Vref=28, minBit 10, minWin=25, winSum=420
2944 04:50:38.598320 TX Vref=30, minBit 12, minWin=25, winSum=422
2945 04:50:38.598372 TX Vref=32, minBit 10, minWin=25, winSum=423
2946 04:50:38.598426 [TxChooseVref] Worse bit 10, Min win 25, Win sum 423, Final Vref 32
2947 04:50:38.598479
2948 04:50:38.598544 Final TX Range 1 Vref 32
2949 04:50:38.598673
2950 04:50:38.598729 ==
2951 04:50:38.598782 Dram Type= 6, Freq= 0, CH_0, rank 1
2952 04:50:38.598835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2953 04:50:38.598895 ==
2954 04:50:38.598948
2955 04:50:38.598999
2956 04:50:38.599050 TX Vref Scan disable
2957 04:50:38.599102 == TX Byte 0 ==
2958 04:50:38.599159 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2959 04:50:38.599259 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2960 04:50:38.599342 == TX Byte 1 ==
2961 04:50:38.599428 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2962 04:50:38.599484 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2963 04:50:38.599537
2964 04:50:38.599588 [DATLAT]
2965 04:50:38.599640 Freq=1200, CH0 RK1
2966 04:50:38.599692
2967 04:50:38.599752 DATLAT Default: 0xd
2968 04:50:38.599805 0, 0xFFFF, sum = 0
2969 04:50:38.599859 1, 0xFFFF, sum = 0
2970 04:50:38.599912 2, 0xFFFF, sum = 0
2971 04:50:38.599970 3, 0xFFFF, sum = 0
2972 04:50:38.600032 4, 0xFFFF, sum = 0
2973 04:50:38.600086 5, 0xFFFF, sum = 0
2974 04:50:38.600153 6, 0xFFFF, sum = 0
2975 04:50:38.600246 7, 0xFFFF, sum = 0
2976 04:50:38.600358 8, 0xFFFF, sum = 0
2977 04:50:38.600413 9, 0xFFFF, sum = 0
2978 04:50:38.600466 10, 0xFFFF, sum = 0
2979 04:50:38.600529 11, 0xFFFF, sum = 0
2980 04:50:38.600583 12, 0x0, sum = 1
2981 04:50:38.600636 13, 0x0, sum = 2
2982 04:50:38.600696 14, 0x0, sum = 3
2983 04:50:38.600750 15, 0x0, sum = 4
2984 04:50:38.600802 best_step = 13
2985 04:50:38.600863
2986 04:50:38.600961 ==
2987 04:50:38.601020 Dram Type= 6, Freq= 0, CH_0, rank 1
2988 04:50:38.601072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2989 04:50:38.601124 ==
2990 04:50:38.601175 RX Vref Scan: 0
2991 04:50:38.601227
2992 04:50:38.601278 RX Vref 0 -> 0, step: 1
2993 04:50:38.601329
2994 04:50:38.601380 RX Delay -13 -> 252, step: 4
2995 04:50:38.601431 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
2996 04:50:38.601483 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
2997 04:50:38.601535 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
2998 04:50:38.601594 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
2999 04:50:38.601647 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3000 04:50:38.601699 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3001 04:50:38.601751 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3002 04:50:38.601802 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3003 04:50:38.601853 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3004 04:50:38.601911 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3005 04:50:38.601965 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3006 04:50:38.602016 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3007 04:50:38.602067 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3008 04:50:38.602119 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3009 04:50:38.602170 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3010 04:50:38.602221 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3011 04:50:38.602273 ==
3012 04:50:38.602332 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 04:50:38.602390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 04:50:38.602443 ==
3015 04:50:38.602495 DQS Delay:
3016 04:50:38.602546 DQS0 = 0, DQS1 = 0
3017 04:50:38.602597 DQM Delay:
3018 04:50:38.602648 DQM0 = 120, DQM1 = 109
3019 04:50:38.602707 DQ Delay:
3020 04:50:38.602759 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3021 04:50:38.602818 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3022 04:50:38.602870 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =100
3023 04:50:38.602921 DQ12 =114, DQ13 =114, DQ14 =122, DQ15 =118
3024 04:50:38.602978
3025 04:50:38.603030
3026 04:50:38.603081 [DQSOSCAuto] RK1, (LSB)MR18= 0xcee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3027 04:50:38.603134 CH0 RK1: MR19=403, MR18=CEE
3028 04:50:38.603194 CH0_RK1: MR19=0x403, MR18=0xCEE, DQSOSC=405, MR23=63, INC=39, DEC=26
3029 04:50:38.603246 [RxdqsGatingPostProcess] freq 1200
3030 04:50:38.603304 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3031 04:50:38.603365 best DQS0 dly(2T, 0.5T) = (0, 11)
3032 04:50:38.603417 best DQS1 dly(2T, 0.5T) = (0, 12)
3033 04:50:38.603473 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3034 04:50:38.603555 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3035 04:50:38.603610 best DQS0 dly(2T, 0.5T) = (0, 11)
3036 04:50:38.603663 best DQS1 dly(2T, 0.5T) = (0, 11)
3037 04:50:38.603723 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3038 04:50:38.603776 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3039 04:50:38.603828 Pre-setting of DQS Precalculation
3040 04:50:38.603881 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3041 04:50:38.603934 ==
3042 04:50:38.603995 Dram Type= 6, Freq= 0, CH_1, rank 0
3043 04:50:38.604047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3044 04:50:38.604100 ==
3045 04:50:38.604152 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3046 04:50:38.604219 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3047 04:50:38.604274 [CA 0] Center 37 (7~67) winsize 61
3048 04:50:38.604370 [CA 1] Center 37 (7~68) winsize 62
3049 04:50:38.604422 [CA 2] Center 35 (5~65) winsize 61
3050 04:50:38.604475 [CA 3] Center 34 (4~64) winsize 61
3051 04:50:38.604527 [CA 4] Center 34 (4~64) winsize 61
3052 04:50:38.604593 [CA 5] Center 33 (3~63) winsize 61
3053 04:50:38.604646
3054 04:50:38.604697 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3055 04:50:38.604750
3056 04:50:38.604810 [CATrainingPosCal] consider 1 rank data
3057 04:50:38.604863 u2DelayCellTimex100 = 270/100 ps
3058 04:50:38.604916 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3059 04:50:38.604968 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3060 04:50:38.605020 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3061 04:50:38.605072 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3062 04:50:38.605131 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3063 04:50:38.605184 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3064 04:50:38.605236
3065 04:50:38.605287 CA PerBit enable=1, Macro0, CA PI delay=33
3066 04:50:38.605339
3067 04:50:38.605397 [CBTSetCACLKResult] CA Dly = 33
3068 04:50:38.605453 CS Dly: 8 (0~39)
3069 04:50:38.605513 ==
3070 04:50:38.605574 Dram Type= 6, Freq= 0, CH_1, rank 1
3071 04:50:38.605838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3072 04:50:38.605941 ==
3073 04:50:38.606053 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3074 04:50:38.606146 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3075 04:50:38.606256 [CA 0] Center 37 (7~68) winsize 62
3076 04:50:38.606371 [CA 1] Center 37 (7~68) winsize 62
3077 04:50:38.606476 [CA 2] Center 35 (5~66) winsize 62
3078 04:50:38.606588 [CA 3] Center 34 (4~65) winsize 62
3079 04:50:38.606700 [CA 4] Center 35 (5~65) winsize 61
3080 04:50:38.606816 [CA 5] Center 33 (3~64) winsize 62
3081 04:50:38.606915
3082 04:50:38.607005 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3083 04:50:38.607087
3084 04:50:38.607168 [CATrainingPosCal] consider 2 rank data
3085 04:50:38.607250 u2DelayCellTimex100 = 270/100 ps
3086 04:50:38.607346 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3087 04:50:38.607429 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3088 04:50:38.607523 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3089 04:50:38.607622 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3090 04:50:38.607725 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3091 04:50:38.607831 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3092 04:50:38.607922
3093 04:50:38.608006 CA PerBit enable=1, Macro0, CA PI delay=33
3094 04:50:38.608088
3095 04:50:38.608169 [CBTSetCACLKResult] CA Dly = 33
3096 04:50:38.608258 CS Dly: 9 (0~41)
3097 04:50:38.608384
3098 04:50:38.608466 ----->DramcWriteLeveling(PI) begin...
3099 04:50:38.608558 ==
3100 04:50:38.608640 Dram Type= 6, Freq= 0, CH_1, rank 0
3101 04:50:38.608730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3102 04:50:38.608812 ==
3103 04:50:38.608894 Write leveling (Byte 0): 27 => 27
3104 04:50:38.608976 Write leveling (Byte 1): 28 => 28
3105 04:50:38.609057 DramcWriteLeveling(PI) end<-----
3106 04:50:38.609156
3107 04:50:38.609242 ==
3108 04:50:38.609323 Dram Type= 6, Freq= 0, CH_1, rank 0
3109 04:50:38.609405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3110 04:50:38.609487 ==
3111 04:50:38.609568 [Gating] SW mode calibration
3112 04:50:38.609658 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3113 04:50:38.609742 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3114 04:50:38.609823 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3115 04:50:38.609905 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3116 04:50:38.609987 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3117 04:50:38.610069 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3118 04:50:38.610149 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 04:50:38.610211 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 04:50:38.610264 0 15 24 | B1->B0 | 3131 2f2f | 0 0 | (0 1) (0 0)
3121 04:50:38.610316 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3122 04:50:38.610368 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3123 04:50:38.610421 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3124 04:50:38.610472 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 04:50:38.610524 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 04:50:38.610576 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 04:50:38.610629 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 04:50:38.610681 1 0 24 | B1->B0 | 2d2d 3737 | 1 1 | (0 0) (1 1)
3129 04:50:38.610733 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3130 04:50:38.610794 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3131 04:50:38.610854 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3132 04:50:38.610906 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 04:50:38.610958 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 04:50:38.611010 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 04:50:38.611098 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 04:50:38.611150 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3137 04:50:38.611202 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3138 04:50:38.611254 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3139 04:50:38.611306 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 04:50:38.611358 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 04:50:38.611410 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 04:50:38.611468 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 04:50:38.611528 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 04:50:38.611581 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 04:50:38.611642 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 04:50:38.611696 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 04:50:38.611757 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 04:50:38.611817 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 04:50:38.611907 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 04:50:38.611960 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 04:50:38.612012 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 04:50:38.612064 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3153 04:50:38.612115 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3154 04:50:38.612174 Total UI for P1: 0, mck2ui 16
3155 04:50:38.612229 best dqsien dly found for B1: ( 1, 3, 24)
3156 04:50:38.612282 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 04:50:38.612375 Total UI for P1: 0, mck2ui 16
3158 04:50:38.612428 best dqsien dly found for B0: ( 1, 3, 26)
3159 04:50:38.612481 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3160 04:50:38.612533 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3161 04:50:38.612585
3162 04:50:38.612636 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3163 04:50:38.612689 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3164 04:50:38.612750 [Gating] SW calibration Done
3165 04:50:38.612802 ==
3166 04:50:38.612871 Dram Type= 6, Freq= 0, CH_1, rank 0
3167 04:50:38.612925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3168 04:50:38.612978 ==
3169 04:50:38.613030 RX Vref Scan: 0
3170 04:50:38.613083
3171 04:50:38.613135 RX Vref 0 -> 0, step: 1
3172 04:50:38.613187
3173 04:50:38.613239 RX Delay -40 -> 252, step: 8
3174 04:50:38.613297 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3175 04:50:38.613359 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3176 04:50:38.613622 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3177 04:50:38.613682 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3178 04:50:38.613736 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3179 04:50:38.613798 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3180 04:50:38.613858 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3181 04:50:38.613954 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3182 04:50:38.614024 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3183 04:50:38.614131 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3184 04:50:38.614225 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3185 04:50:38.614308 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3186 04:50:38.614390 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3187 04:50:38.614472 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3188 04:50:38.614554 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3189 04:50:38.614644 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3190 04:50:38.614726 ==
3191 04:50:38.614808 Dram Type= 6, Freq= 0, CH_1, rank 0
3192 04:50:38.614889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3193 04:50:38.614971 ==
3194 04:50:38.615052 DQS Delay:
3195 04:50:38.615141 DQS0 = 0, DQS1 = 0
3196 04:50:38.615223 DQM Delay:
3197 04:50:38.615303 DQM0 = 120, DQM1 = 116
3198 04:50:38.615384 DQ Delay:
3199 04:50:38.615465 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3200 04:50:38.615547 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =119
3201 04:50:38.615628 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3202 04:50:38.615710 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3203 04:50:38.615790
3204 04:50:38.615870
3205 04:50:38.615950 ==
3206 04:50:38.616032 Dram Type= 6, Freq= 0, CH_1, rank 0
3207 04:50:38.616114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3208 04:50:38.616195 ==
3209 04:50:38.616275
3210 04:50:38.616374
3211 04:50:38.616427 TX Vref Scan disable
3212 04:50:38.616480 == TX Byte 0 ==
3213 04:50:38.616531 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3214 04:50:38.616594 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3215 04:50:38.616647 == TX Byte 1 ==
3216 04:50:38.616706 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3217 04:50:38.616761 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3218 04:50:38.616848 ==
3219 04:50:38.616929 Dram Type= 6, Freq= 0, CH_1, rank 0
3220 04:50:38.617018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3221 04:50:38.617101 ==
3222 04:50:38.617183 TX Vref=22, minBit 9, minWin=24, winSum=414
3223 04:50:38.617265 TX Vref=24, minBit 0, minWin=25, winSum=416
3224 04:50:38.617347 TX Vref=26, minBit 10, minWin=25, winSum=421
3225 04:50:38.617429 TX Vref=28, minBit 11, minWin=25, winSum=431
3226 04:50:38.617511 TX Vref=30, minBit 9, minWin=26, winSum=433
3227 04:50:38.617600 TX Vref=32, minBit 10, minWin=25, winSum=430
3228 04:50:38.617683 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 30
3229 04:50:38.617764
3230 04:50:38.617845 Final TX Range 1 Vref 30
3231 04:50:38.617928
3232 04:50:38.617996 ==
3233 04:50:38.618058 Dram Type= 6, Freq= 0, CH_1, rank 0
3234 04:50:38.618111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3235 04:50:38.618164 ==
3236 04:50:38.618216
3237 04:50:38.618268
3238 04:50:38.618320 TX Vref Scan disable
3239 04:50:38.618371 == TX Byte 0 ==
3240 04:50:38.618422 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3241 04:50:38.618474 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3242 04:50:38.618526 == TX Byte 1 ==
3243 04:50:38.618578 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3244 04:50:38.618630 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3245 04:50:38.618681
3246 04:50:38.618733 [DATLAT]
3247 04:50:38.618785 Freq=1200, CH1 RK0
3248 04:50:38.618837
3249 04:50:38.618888 DATLAT Default: 0xd
3250 04:50:38.618940 0, 0xFFFF, sum = 0
3251 04:50:38.618993 1, 0xFFFF, sum = 0
3252 04:50:38.619046 2, 0xFFFF, sum = 0
3253 04:50:38.619098 3, 0xFFFF, sum = 0
3254 04:50:38.619150 4, 0xFFFF, sum = 0
3255 04:50:38.619212 5, 0xFFFF, sum = 0
3256 04:50:38.619266 6, 0xFFFF, sum = 0
3257 04:50:38.619318 7, 0xFFFF, sum = 0
3258 04:50:38.619371 8, 0xFFFF, sum = 0
3259 04:50:38.619423 9, 0xFFFF, sum = 0
3260 04:50:38.619476 10, 0xFFFF, sum = 0
3261 04:50:38.619529 11, 0xFFFF, sum = 0
3262 04:50:38.619581 12, 0x0, sum = 1
3263 04:50:38.619634 13, 0x0, sum = 2
3264 04:50:38.619687 14, 0x0, sum = 3
3265 04:50:38.619747 15, 0x0, sum = 4
3266 04:50:38.619800 best_step = 13
3267 04:50:38.619851
3268 04:50:38.619902 ==
3269 04:50:38.619956 Dram Type= 6, Freq= 0, CH_1, rank 0
3270 04:50:38.620009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3271 04:50:38.620061 ==
3272 04:50:38.620114 RX Vref Scan: 1
3273 04:50:38.620204
3274 04:50:38.620307 Set Vref Range= 32 -> 127
3275 04:50:38.620386
3276 04:50:38.620439 RX Vref 32 -> 127, step: 1
3277 04:50:38.620492
3278 04:50:38.620544 RX Delay -5 -> 252, step: 4
3279 04:50:38.620596
3280 04:50:38.620648 Set Vref, RX VrefLevel [Byte0]: 32
3281 04:50:38.620700 [Byte1]: 32
3282 04:50:38.620752
3283 04:50:38.620804 Set Vref, RX VrefLevel [Byte0]: 33
3284 04:50:38.620856 [Byte1]: 33
3285 04:50:38.620908
3286 04:50:38.620959 Set Vref, RX VrefLevel [Byte0]: 34
3287 04:50:38.621011 [Byte1]: 34
3288 04:50:38.621062
3289 04:50:38.621114 Set Vref, RX VrefLevel [Byte0]: 35
3290 04:50:38.621165 [Byte1]: 35
3291 04:50:38.621227
3292 04:50:38.621279 Set Vref, RX VrefLevel [Byte0]: 36
3293 04:50:38.621331 [Byte1]: 36
3294 04:50:38.621383
3295 04:50:38.621433 Set Vref, RX VrefLevel [Byte0]: 37
3296 04:50:38.621485 [Byte1]: 37
3297 04:50:38.621536
3298 04:50:38.621587 Set Vref, RX VrefLevel [Byte0]: 38
3299 04:50:38.621638 [Byte1]: 38
3300 04:50:38.621688
3301 04:50:38.621754 Set Vref, RX VrefLevel [Byte0]: 39
3302 04:50:38.621807 [Byte1]: 39
3303 04:50:38.621858
3304 04:50:38.621909 Set Vref, RX VrefLevel [Byte0]: 40
3305 04:50:38.621968 [Byte1]: 40
3306 04:50:38.622021
3307 04:50:38.622072 Set Vref, RX VrefLevel [Byte0]: 41
3308 04:50:38.622123 [Byte1]: 41
3309 04:50:38.622174
3310 04:50:38.622225 Set Vref, RX VrefLevel [Byte0]: 42
3311 04:50:38.622276 [Byte1]: 42
3312 04:50:38.622327
3313 04:50:38.622377 Set Vref, RX VrefLevel [Byte0]: 43
3314 04:50:38.622429 [Byte1]: 43
3315 04:50:38.622479
3316 04:50:38.622530 Set Vref, RX VrefLevel [Byte0]: 44
3317 04:50:38.622581 [Byte1]: 44
3318 04:50:38.622632
3319 04:50:38.622682 Set Vref, RX VrefLevel [Byte0]: 45
3320 04:50:38.622733 [Byte1]: 45
3321 04:50:38.622784
3322 04:50:38.622834 Set Vref, RX VrefLevel [Byte0]: 46
3323 04:50:38.622886 [Byte1]: 46
3324 04:50:38.622937
3325 04:50:38.622988 Set Vref, RX VrefLevel [Byte0]: 47
3326 04:50:38.623038 [Byte1]: 47
3327 04:50:38.623089
3328 04:50:38.623147 Set Vref, RX VrefLevel [Byte0]: 48
3329 04:50:38.623200 [Byte1]: 48
3330 04:50:38.623251
3331 04:50:38.623302 Set Vref, RX VrefLevel [Byte0]: 49
3332 04:50:38.623370 [Byte1]: 49
3333 04:50:38.623633
3334 04:50:38.623733 Set Vref, RX VrefLevel [Byte0]: 50
3335 04:50:38.623856 [Byte1]: 50
3336 04:50:38.624000
3337 04:50:38.624104 Set Vref, RX VrefLevel [Byte0]: 51
3338 04:50:38.624207 [Byte1]: 51
3339 04:50:38.624361
3340 04:50:38.624467 Set Vref, RX VrefLevel [Byte0]: 52
3341 04:50:38.624570 [Byte1]: 52
3342 04:50:38.624673
3343 04:50:38.624775 Set Vref, RX VrefLevel [Byte0]: 53
3344 04:50:38.624869 [Byte1]: 53
3345 04:50:38.624958
3346 04:50:38.625049 Set Vref, RX VrefLevel [Byte0]: 54
3347 04:50:38.625131 [Byte1]: 54
3348 04:50:38.625211
3349 04:50:38.625292 Set Vref, RX VrefLevel [Byte0]: 55
3350 04:50:38.625373 [Byte1]: 55
3351 04:50:38.625453
3352 04:50:38.625533 Set Vref, RX VrefLevel [Byte0]: 56
3353 04:50:38.625614 [Byte1]: 56
3354 04:50:38.625693
3355 04:50:38.625757 Set Vref, RX VrefLevel [Byte0]: 57
3356 04:50:38.625821 [Byte1]: 57
3357 04:50:38.625874
3358 04:50:38.625925 Set Vref, RX VrefLevel [Byte0]: 58
3359 04:50:38.625977 [Byte1]: 58
3360 04:50:38.626029
3361 04:50:38.626080 Set Vref, RX VrefLevel [Byte0]: 59
3362 04:50:38.626132 [Byte1]: 59
3363 04:50:38.626183
3364 04:50:38.626234 Set Vref, RX VrefLevel [Byte0]: 60
3365 04:50:38.626285 [Byte1]: 60
3366 04:50:38.626337
3367 04:50:38.626388 Set Vref, RX VrefLevel [Byte0]: 61
3368 04:50:38.626440 [Byte1]: 61
3369 04:50:38.626491
3370 04:50:38.626542 Set Vref, RX VrefLevel [Byte0]: 62
3371 04:50:38.626601 [Byte1]: 62
3372 04:50:38.626657
3373 04:50:38.626709 Set Vref, RX VrefLevel [Byte0]: 63
3374 04:50:38.626760 [Byte1]: 63
3375 04:50:38.626811
3376 04:50:38.626863 Set Vref, RX VrefLevel [Byte0]: 64
3377 04:50:38.626914 [Byte1]: 64
3378 04:50:38.626967
3379 04:50:38.627018 Set Vref, RX VrefLevel [Byte0]: 65
3380 04:50:38.627083 [Byte1]: 65
3381 04:50:38.627135
3382 04:50:38.627193 Set Vref, RX VrefLevel [Byte0]: 66
3383 04:50:38.627245 [Byte1]: 66
3384 04:50:38.627297
3385 04:50:38.627348 Set Vref, RX VrefLevel [Byte0]: 67
3386 04:50:38.627400 [Byte1]: 67
3387 04:50:38.627451
3388 04:50:38.627510 Final RX Vref Byte 0 = 55 to rank0
3389 04:50:38.627565 Final RX Vref Byte 1 = 48 to rank0
3390 04:50:38.627616 Final RX Vref Byte 0 = 55 to rank1
3391 04:50:38.627668 Final RX Vref Byte 1 = 48 to rank1==
3392 04:50:38.627725 Dram Type= 6, Freq= 0, CH_1, rank 0
3393 04:50:38.627785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3394 04:50:38.627838 ==
3395 04:50:38.627889 DQS Delay:
3396 04:50:38.627940 DQS0 = 0, DQS1 = 0
3397 04:50:38.627992 DQM Delay:
3398 04:50:38.628053 DQM0 = 120, DQM1 = 116
3399 04:50:38.628105 DQ Delay:
3400 04:50:38.628157 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3401 04:50:38.628209 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3402 04:50:38.628260 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3403 04:50:38.628344 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3404 04:50:38.628410
3405 04:50:38.628461
3406 04:50:38.628513 [DQSOSCAuto] RK0, (LSB)MR18= 0x315, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3407 04:50:38.628566 CH1 RK0: MR19=404, MR18=315
3408 04:50:38.628627 CH1_RK0: MR19=0x404, MR18=0x315, DQSOSC=401, MR23=63, INC=40, DEC=27
3409 04:50:38.628680
3410 04:50:38.628732 ----->DramcWriteLeveling(PI) begin...
3411 04:50:38.628785 ==
3412 04:50:38.628837 Dram Type= 6, Freq= 0, CH_1, rank 1
3413 04:50:38.628889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3414 04:50:38.628941 ==
3415 04:50:38.629000 Write leveling (Byte 0): 26 => 26
3416 04:50:38.629052 Write leveling (Byte 1): 27 => 27
3417 04:50:38.629104 DramcWriteLeveling(PI) end<-----
3418 04:50:38.629155
3419 04:50:38.629207 ==
3420 04:50:38.629259 Dram Type= 6, Freq= 0, CH_1, rank 1
3421 04:50:38.629310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3422 04:50:38.629362 ==
3423 04:50:38.629413 [Gating] SW mode calibration
3424 04:50:38.629465 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3425 04:50:38.629517 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3426 04:50:38.629569 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3427 04:50:38.629622 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3428 04:50:38.629674 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3429 04:50:38.629784 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3430 04:50:38.629882 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3431 04:50:38.629938 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3432 04:50:38.629990 0 15 24 | B1->B0 | 2c2c 3434 | 0 1 | (0 1) (1 1)
3433 04:50:38.630041 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3434 04:50:38.630092 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3435 04:50:38.630153 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3436 04:50:38.630205 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3437 04:50:38.630257 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3438 04:50:38.630308 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3439 04:50:38.630360 1 0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3440 04:50:38.630411 1 0 24 | B1->B0 | 3e3e 2727 | 0 0 | (0 0) (0 0)
3441 04:50:38.630463 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3442 04:50:38.630514 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3443 04:50:38.630565 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3444 04:50:38.630616 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3445 04:50:38.630676 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3446 04:50:38.630728 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3447 04:50:38.630779 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3448 04:50:38.630831 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3449 04:50:38.630882 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3450 04:50:38.630933 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 04:50:38.630984 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3452 04:50:38.631035 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 04:50:38.631086 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 04:50:38.631138 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 04:50:38.631198 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 04:50:38.631458 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 04:50:38.631547 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 04:50:38.631630 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 04:50:38.631723 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 04:50:38.631820 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 04:50:38.631919 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 04:50:38.632017 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 04:50:38.632100 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3464 04:50:38.632181 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3465 04:50:38.632273 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3466 04:50:38.632395 Total UI for P1: 0, mck2ui 16
3467 04:50:38.632478 best dqsien dly found for B1: ( 1, 3, 22)
3468 04:50:38.632560 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 04:50:38.632641 Total UI for P1: 0, mck2ui 16
3470 04:50:38.632730 best dqsien dly found for B0: ( 1, 3, 28)
3471 04:50:38.632813 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3472 04:50:38.632895 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3473 04:50:38.632975
3474 04:50:38.633056 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3475 04:50:38.633111 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3476 04:50:38.633164 [Gating] SW calibration Done
3477 04:50:38.633216 ==
3478 04:50:38.633268 Dram Type= 6, Freq= 0, CH_1, rank 1
3479 04:50:38.633320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3480 04:50:38.633381 ==
3481 04:50:38.633434 RX Vref Scan: 0
3482 04:50:38.633486
3483 04:50:38.633537 RX Vref 0 -> 0, step: 1
3484 04:50:38.633588
3485 04:50:38.633640 RX Delay -40 -> 252, step: 8
3486 04:50:38.633692 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3487 04:50:38.633745 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3488 04:50:38.633796 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3489 04:50:38.633847 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3490 04:50:38.633907 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3491 04:50:38.633961 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3492 04:50:38.634013 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3493 04:50:38.634065 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3494 04:50:38.634117 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3495 04:50:38.634168 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3496 04:50:38.634220 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3497 04:50:38.634271 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3498 04:50:38.634323 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3499 04:50:38.634375 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3500 04:50:38.634426 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3501 04:50:38.634478 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3502 04:50:38.634528 ==
3503 04:50:38.634579 Dram Type= 6, Freq= 0, CH_1, rank 1
3504 04:50:38.634640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3505 04:50:38.634692 ==
3506 04:50:38.634744 DQS Delay:
3507 04:50:38.634795 DQS0 = 0, DQS1 = 0
3508 04:50:38.634846 DQM Delay:
3509 04:50:38.634896 DQM0 = 121, DQM1 = 118
3510 04:50:38.634969 DQ Delay:
3511 04:50:38.635062 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3512 04:50:38.635122 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3513 04:50:38.635175 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =115
3514 04:50:38.635227 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3515 04:50:38.635279
3516 04:50:38.635329
3517 04:50:38.635380 ==
3518 04:50:38.635431 Dram Type= 6, Freq= 0, CH_1, rank 1
3519 04:50:38.635482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3520 04:50:38.635535 ==
3521 04:50:38.635585
3522 04:50:38.635636
3523 04:50:38.635687 TX Vref Scan disable
3524 04:50:38.635738 == TX Byte 0 ==
3525 04:50:38.635810 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3526 04:50:38.635864 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3527 04:50:38.635916 == TX Byte 1 ==
3528 04:50:38.635967 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3529 04:50:38.636019 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3530 04:50:38.636071 ==
3531 04:50:38.636123 Dram Type= 6, Freq= 0, CH_1, rank 1
3532 04:50:38.636175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3533 04:50:38.636227 ==
3534 04:50:38.636277 TX Vref=22, minBit 9, minWin=25, winSum=415
3535 04:50:38.636371 TX Vref=24, minBit 1, minWin=26, winSum=424
3536 04:50:38.636454 TX Vref=26, minBit 2, minWin=26, winSum=427
3537 04:50:38.636525 TX Vref=28, minBit 10, minWin=25, winSum=432
3538 04:50:38.636589 TX Vref=30, minBit 9, minWin=26, winSum=434
3539 04:50:38.636642 TX Vref=32, minBit 1, minWin=26, winSum=434
3540 04:50:38.636695 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3541 04:50:38.636748
3542 04:50:38.636799 Final TX Range 1 Vref 30
3543 04:50:38.636851
3544 04:50:38.636903 ==
3545 04:50:38.636955 Dram Type= 6, Freq= 0, CH_1, rank 1
3546 04:50:38.637006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3547 04:50:38.637057 ==
3548 04:50:38.637109
3549 04:50:38.637169
3550 04:50:38.637223 TX Vref Scan disable
3551 04:50:38.637274 == TX Byte 0 ==
3552 04:50:38.637326 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3553 04:50:38.637377 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3554 04:50:38.637429 == TX Byte 1 ==
3555 04:50:38.637479 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3556 04:50:38.637531 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3557 04:50:38.637583
3558 04:50:38.637635 [DATLAT]
3559 04:50:38.637686 Freq=1200, CH1 RK1
3560 04:50:38.637751
3561 04:50:38.637825 DATLAT Default: 0xd
3562 04:50:38.637879 0, 0xFFFF, sum = 0
3563 04:50:38.637933 1, 0xFFFF, sum = 0
3564 04:50:38.637985 2, 0xFFFF, sum = 0
3565 04:50:38.638038 3, 0xFFFF, sum = 0
3566 04:50:38.638091 4, 0xFFFF, sum = 0
3567 04:50:38.638143 5, 0xFFFF, sum = 0
3568 04:50:38.638195 6, 0xFFFF, sum = 0
3569 04:50:38.638247 7, 0xFFFF, sum = 0
3570 04:50:38.638300 8, 0xFFFF, sum = 0
3571 04:50:38.638351 9, 0xFFFF, sum = 0
3572 04:50:38.638403 10, 0xFFFF, sum = 0
3573 04:50:38.638464 11, 0xFFFF, sum = 0
3574 04:50:38.638517 12, 0x0, sum = 1
3575 04:50:38.638569 13, 0x0, sum = 2
3576 04:50:38.638621 14, 0x0, sum = 3
3577 04:50:38.638673 15, 0x0, sum = 4
3578 04:50:38.638724 best_step = 13
3579 04:50:38.638775
3580 04:50:38.638826 ==
3581 04:50:38.638878 Dram Type= 6, Freq= 0, CH_1, rank 1
3582 04:50:38.638929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3583 04:50:38.638980 ==
3584 04:50:38.639031 RX Vref Scan: 0
3585 04:50:38.639082
3586 04:50:38.639133 RX Vref 0 -> 0, step: 1
3587 04:50:38.639185
3588 04:50:38.639235 RX Delay -5 -> 252, step: 4
3589 04:50:38.639287 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3590 04:50:38.639339 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3591 04:50:38.639390 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3592 04:50:38.639448 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3593 04:50:38.639711 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3594 04:50:38.639777 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3595 04:50:38.639914 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3596 04:50:38.640051 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3597 04:50:38.640149 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3598 04:50:38.640231 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3599 04:50:38.640347 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3600 04:50:38.640403 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3601 04:50:38.640456 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3602 04:50:38.640507 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3603 04:50:38.640562 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3604 04:50:38.640614 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3605 04:50:38.640665 ==
3606 04:50:38.640717 Dram Type= 6, Freq= 0, CH_1, rank 1
3607 04:50:38.640769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3608 04:50:38.640821 ==
3609 04:50:38.640872 DQS Delay:
3610 04:50:38.640924 DQS0 = 0, DQS1 = 0
3611 04:50:38.640975 DQM Delay:
3612 04:50:38.641027 DQM0 = 120, DQM1 = 116
3613 04:50:38.641078 DQ Delay:
3614 04:50:38.641130 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3615 04:50:38.641184 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3616 04:50:38.641236 DQ8 =106, DQ9 =106, DQ10 =116, DQ11 =110
3617 04:50:38.641287 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =124
3618 04:50:38.641339
3619 04:50:38.641389
3620 04:50:38.641441 [DQSOSCAuto] RK1, (LSB)MR18= 0xfeb, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 404 ps
3621 04:50:38.641494 CH1 RK1: MR19=403, MR18=FEB
3622 04:50:38.641545 CH1_RK1: MR19=0x403, MR18=0xFEB, DQSOSC=404, MR23=63, INC=40, DEC=26
3623 04:50:38.641597 [RxdqsGatingPostProcess] freq 1200
3624 04:50:38.641648 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3625 04:50:38.641700 best DQS0 dly(2T, 0.5T) = (0, 11)
3626 04:50:38.641752 best DQS1 dly(2T, 0.5T) = (0, 11)
3627 04:50:38.641812 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3628 04:50:38.641865 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3629 04:50:38.641917 best DQS0 dly(2T, 0.5T) = (0, 11)
3630 04:50:38.641968 best DQS1 dly(2T, 0.5T) = (0, 11)
3631 04:50:38.642020 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3632 04:50:38.642071 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3633 04:50:38.642122 Pre-setting of DQS Precalculation
3634 04:50:38.642173 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3635 04:50:38.642225 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3636 04:50:38.642277 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3637 04:50:38.642329
3638 04:50:38.642379
3639 04:50:38.642430 [Calibration Summary] 2400 Mbps
3640 04:50:38.642482 CH 0, Rank 0
3641 04:50:38.642540 SW Impedance : PASS
3642 04:50:38.642594 DUTY Scan : NO K
3643 04:50:38.642655 ZQ Calibration : PASS
3644 04:50:38.642709 Jitter Meter : NO K
3645 04:50:38.642760 CBT Training : PASS
3646 04:50:38.642812 Write leveling : PASS
3647 04:50:38.642864 RX DQS gating : PASS
3648 04:50:38.642915 RX DQ/DQS(RDDQC) : PASS
3649 04:50:38.642966 TX DQ/DQS : PASS
3650 04:50:38.643017 RX DATLAT : PASS
3651 04:50:38.643068 RX DQ/DQS(Engine): PASS
3652 04:50:38.643119 TX OE : NO K
3653 04:50:38.643172 All Pass.
3654 04:50:38.643223
3655 04:50:38.643274 CH 0, Rank 1
3656 04:50:38.643325 SW Impedance : PASS
3657 04:50:38.643376 DUTY Scan : NO K
3658 04:50:38.643427 ZQ Calibration : PASS
3659 04:50:38.643478 Jitter Meter : NO K
3660 04:50:38.643530 CBT Training : PASS
3661 04:50:38.643581 Write leveling : PASS
3662 04:50:38.643632 RX DQS gating : PASS
3663 04:50:38.643683 RX DQ/DQS(RDDQC) : PASS
3664 04:50:38.643747 TX DQ/DQS : PASS
3665 04:50:38.643831 RX DATLAT : PASS
3666 04:50:38.643897 RX DQ/DQS(Engine): PASS
3667 04:50:38.643948 TX OE : NO K
3668 04:50:38.644000 All Pass.
3669 04:50:38.644051
3670 04:50:38.644102 CH 1, Rank 0
3671 04:50:38.644153 SW Impedance : PASS
3672 04:50:38.644205 DUTY Scan : NO K
3673 04:50:38.644256 ZQ Calibration : PASS
3674 04:50:38.644361 Jitter Meter : NO K
3675 04:50:38.644414 CBT Training : PASS
3676 04:50:38.644466 Write leveling : PASS
3677 04:50:38.644518 RX DQS gating : PASS
3678 04:50:38.644569 RX DQ/DQS(RDDQC) : PASS
3679 04:50:38.644620 TX DQ/DQS : PASS
3680 04:50:38.644671 RX DATLAT : PASS
3681 04:50:38.644722 RX DQ/DQS(Engine): PASS
3682 04:50:38.644774 TX OE : NO K
3683 04:50:38.644846 All Pass.
3684 04:50:38.644939
3685 04:50:38.644996 CH 1, Rank 1
3686 04:50:38.645049 SW Impedance : PASS
3687 04:50:38.645101 DUTY Scan : NO K
3688 04:50:38.645152 ZQ Calibration : PASS
3689 04:50:38.645204 Jitter Meter : NO K
3690 04:50:38.645255 CBT Training : PASS
3691 04:50:38.645307 Write leveling : PASS
3692 04:50:38.645358 RX DQS gating : PASS
3693 04:50:38.645420 RX DQ/DQS(RDDQC) : PASS
3694 04:50:38.645472 TX DQ/DQS : PASS
3695 04:50:38.645524 RX DATLAT : PASS
3696 04:50:38.645581 RX DQ/DQS(Engine): PASS
3697 04:50:38.645676 TX OE : NO K
3698 04:50:38.645753 All Pass.
3699 04:50:38.645807
3700 04:50:38.645859 DramC Write-DBI off
3701 04:50:38.645911 PER_BANK_REFRESH: Hybrid Mode
3702 04:50:38.645963 TX_TRACKING: ON
3703 04:50:38.646032 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3704 04:50:38.646086 [FAST_K] Save calibration result to emmc
3705 04:50:38.646139 dramc_set_vcore_voltage set vcore to 650000
3706 04:50:38.646191 Read voltage for 600, 5
3707 04:50:38.646242 Vio18 = 0
3708 04:50:38.646294 Vcore = 650000
3709 04:50:38.646346 Vdram = 0
3710 04:50:38.646397 Vddq = 0
3711 04:50:38.646448 Vmddr = 0
3712 04:50:38.646500 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3713 04:50:38.646551 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3714 04:50:38.646603 MEM_TYPE=3, freq_sel=19
3715 04:50:38.646654 sv_algorithm_assistance_LP4_1600
3716 04:50:38.646706 ============ PULL DRAM RESETB DOWN ============
3717 04:50:38.646758 ========== PULL DRAM RESETB DOWN end =========
3718 04:50:38.646818 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3719 04:50:38.646871 ===================================
3720 04:50:38.646923 LPDDR4 DRAM CONFIGURATION
3721 04:50:38.646974 ===================================
3722 04:50:38.647025 EX_ROW_EN[0] = 0x0
3723 04:50:38.647077 EX_ROW_EN[1] = 0x0
3724 04:50:38.647128 LP4Y_EN = 0x0
3725 04:50:38.647179 WORK_FSP = 0x0
3726 04:50:38.647231 WL = 0x2
3727 04:50:38.647282 RL = 0x2
3728 04:50:38.647333 BL = 0x2
3729 04:50:38.647384 RPST = 0x0
3730 04:50:38.647435 RD_PRE = 0x0
3731 04:50:38.647486 WR_PRE = 0x1
3732 04:50:38.647537 WR_PST = 0x0
3733 04:50:38.647588 DBI_WR = 0x0
3734 04:50:38.647859 DBI_RD = 0x0
3735 04:50:38.647945 OTF = 0x1
3736 04:50:38.648011 ===================================
3737 04:50:38.648072 ===================================
3738 04:50:38.648131 ANA top config
3739 04:50:38.648190 ===================================
3740 04:50:38.648265 DLL_ASYNC_EN = 0
3741 04:50:38.648347 ALL_SLAVE_EN = 1
3742 04:50:38.648403 NEW_RANK_MODE = 1
3743 04:50:38.648458 DLL_IDLE_MODE = 1
3744 04:50:38.648511 LP45_APHY_COMB_EN = 1
3745 04:50:38.648564 TX_ODT_DIS = 1
3746 04:50:38.648618 NEW_8X_MODE = 1
3747 04:50:38.648672 ===================================
3748 04:50:38.648729 ===================================
3749 04:50:38.648784 data_rate = 1200
3750 04:50:38.648838 CKR = 1
3751 04:50:38.648891 DQ_P2S_RATIO = 8
3752 04:50:38.648944 ===================================
3753 04:50:38.648997 CA_P2S_RATIO = 8
3754 04:50:38.649050 DQ_CA_OPEN = 0
3755 04:50:38.649102 DQ_SEMI_OPEN = 0
3756 04:50:38.649156 CA_SEMI_OPEN = 0
3757 04:50:38.649208 CA_FULL_RATE = 0
3758 04:50:38.649261 DQ_CKDIV4_EN = 1
3759 04:50:38.649313 CA_CKDIV4_EN = 1
3760 04:50:38.649367 CA_PREDIV_EN = 0
3761 04:50:38.649419 PH8_DLY = 0
3762 04:50:38.649475 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3763 04:50:38.649530 DQ_AAMCK_DIV = 4
3764 04:50:38.649582 CA_AAMCK_DIV = 4
3765 04:50:38.649635 CA_ADMCK_DIV = 4
3766 04:50:38.649688 DQ_TRACK_CA_EN = 0
3767 04:50:38.649741 CA_PICK = 600
3768 04:50:38.649828 CA_MCKIO = 600
3769 04:50:38.649881 MCKIO_SEMI = 0
3770 04:50:38.649934 PLL_FREQ = 2288
3771 04:50:38.649986 DQ_UI_PI_RATIO = 32
3772 04:50:38.650039 CA_UI_PI_RATIO = 0
3773 04:50:38.650092 ===================================
3774 04:50:38.650145 ===================================
3775 04:50:38.650198 memory_type:LPDDR4
3776 04:50:38.650250 GP_NUM : 10
3777 04:50:38.650302 SRAM_EN : 1
3778 04:50:38.650355 MD32_EN : 0
3779 04:50:38.650408 ===================================
3780 04:50:38.650461 [ANA_INIT] >>>>>>>>>>>>>>
3781 04:50:38.650513 <<<<<< [CONFIGURE PHASE]: ANA_TX
3782 04:50:38.650566 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3783 04:50:38.650619 ===================================
3784 04:50:38.650671 data_rate = 1200,PCW = 0X5800
3785 04:50:38.650724 ===================================
3786 04:50:38.650777 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3787 04:50:38.650831 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3788 04:50:38.650884 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3789 04:50:38.650937 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3790 04:50:38.650990 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3791 04:50:38.651042 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3792 04:50:38.651095 [ANA_INIT] flow start
3793 04:50:38.651147 [ANA_INIT] PLL >>>>>>>>
3794 04:50:38.651199 [ANA_INIT] PLL <<<<<<<<
3795 04:50:38.651251 [ANA_INIT] MIDPI >>>>>>>>
3796 04:50:38.651304 [ANA_INIT] MIDPI <<<<<<<<
3797 04:50:38.651355 [ANA_INIT] DLL >>>>>>>>
3798 04:50:38.651408 [ANA_INIT] flow end
3799 04:50:38.651459 ============ LP4 DIFF to SE enter ============
3800 04:50:38.651516 ============ LP4 DIFF to SE exit ============
3801 04:50:38.651571 [ANA_INIT] <<<<<<<<<<<<<
3802 04:50:38.651623 [Flow] Enable top DCM control >>>>>
3803 04:50:38.651676 [Flow] Enable top DCM control <<<<<
3804 04:50:38.651728 Enable DLL master slave shuffle
3805 04:50:38.651781 ==============================================================
3806 04:50:38.651846 Gating Mode config
3807 04:50:38.651900 ==============================================================
3808 04:50:38.651954 Config description:
3809 04:50:38.652007 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3810 04:50:38.652061 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3811 04:50:38.652115 SELPH_MODE 0: By rank 1: By Phase
3812 04:50:38.652172 ==============================================================
3813 04:50:38.652227 GAT_TRACK_EN = 1
3814 04:50:38.652281 RX_GATING_MODE = 2
3815 04:50:38.652378 RX_GATING_TRACK_MODE = 2
3816 04:50:38.652431 SELPH_MODE = 1
3817 04:50:38.652484 PICG_EARLY_EN = 1
3818 04:50:38.652536 VALID_LAT_VALUE = 1
3819 04:50:38.652589 ==============================================================
3820 04:50:38.652642 Enter into Gating configuration >>>>
3821 04:50:38.652695 Exit from Gating configuration <<<<
3822 04:50:38.652748 Enter into DVFS_PRE_config >>>>>
3823 04:50:38.652801 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3824 04:50:38.652855 Exit from DVFS_PRE_config <<<<<
3825 04:50:38.652908 Enter into PICG configuration >>>>
3826 04:50:38.652961 Exit from PICG configuration <<<<
3827 04:50:38.653017 [RX_INPUT] configuration >>>>>
3828 04:50:38.653071 [RX_INPUT] configuration <<<<<
3829 04:50:38.653124 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3830 04:50:38.653177 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3831 04:50:38.653230 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3832 04:50:38.653283 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3833 04:50:38.653336 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3834 04:50:38.653389 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3835 04:50:38.653441 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3836 04:50:38.653495 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3837 04:50:38.653547 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3838 04:50:38.653807 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3839 04:50:38.653945 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3840 04:50:38.654080 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3841 04:50:38.654210 ===================================
3842 04:50:38.654340 LPDDR4 DRAM CONFIGURATION
3843 04:50:38.654468 ===================================
3844 04:50:38.654595 EX_ROW_EN[0] = 0x0
3845 04:50:38.654728 EX_ROW_EN[1] = 0x0
3846 04:50:38.654858 LP4Y_EN = 0x0
3847 04:50:38.654969 WORK_FSP = 0x0
3848 04:50:38.655026 WL = 0x2
3849 04:50:38.655082 RL = 0x2
3850 04:50:38.655136 BL = 0x2
3851 04:50:38.655189 RPST = 0x0
3852 04:50:38.655241 RD_PRE = 0x0
3853 04:50:38.655298 WR_PRE = 0x1
3854 04:50:38.655352 WR_PST = 0x0
3855 04:50:38.655405 DBI_WR = 0x0
3856 04:50:38.655458 DBI_RD = 0x0
3857 04:50:38.655510 OTF = 0x1
3858 04:50:38.655563 ===================================
3859 04:50:38.655617 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3860 04:50:38.655670 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3861 04:50:38.655723 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3862 04:50:38.655847 ===================================
3863 04:50:38.655906 LPDDR4 DRAM CONFIGURATION
3864 04:50:38.655961 ===================================
3865 04:50:38.656014 EX_ROW_EN[0] = 0x10
3866 04:50:38.656067 EX_ROW_EN[1] = 0x0
3867 04:50:38.656120 LP4Y_EN = 0x0
3868 04:50:38.656172 WORK_FSP = 0x0
3869 04:50:38.656224 WL = 0x2
3870 04:50:38.656277 RL = 0x2
3871 04:50:38.656373 BL = 0x2
3872 04:50:38.656426 RPST = 0x0
3873 04:50:38.656478 RD_PRE = 0x0
3874 04:50:38.656534 WR_PRE = 0x1
3875 04:50:38.656589 WR_PST = 0x0
3876 04:50:38.656641 DBI_WR = 0x0
3877 04:50:38.656693 DBI_RD = 0x0
3878 04:50:38.656745 OTF = 0x1
3879 04:50:38.656798 ===================================
3880 04:50:38.656851 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3881 04:50:38.656904 nWR fixed to 30
3882 04:50:38.656957 [ModeRegInit_LP4] CH0 RK0
3883 04:50:38.657010 [ModeRegInit_LP4] CH0 RK1
3884 04:50:38.657063 [ModeRegInit_LP4] CH1 RK0
3885 04:50:38.657119 [ModeRegInit_LP4] CH1 RK1
3886 04:50:38.657173 match AC timing 17
3887 04:50:38.657225 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3888 04:50:38.657278 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3889 04:50:38.657331 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3890 04:50:38.657385 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3891 04:50:38.657438 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3892 04:50:38.657491 ==
3893 04:50:38.657544 Dram Type= 6, Freq= 0, CH_0, rank 0
3894 04:50:38.657597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3895 04:50:38.657668 ==
3896 04:50:38.657722 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3897 04:50:38.657775 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3898 04:50:38.657829 [CA 0] Center 36 (5~67) winsize 63
3899 04:50:38.657881 [CA 1] Center 36 (5~67) winsize 63
3900 04:50:38.657934 [CA 2] Center 33 (3~64) winsize 62
3901 04:50:38.657991 [CA 3] Center 33 (2~64) winsize 63
3902 04:50:38.658045 [CA 4] Center 33 (2~64) winsize 63
3903 04:50:38.658098 [CA 5] Center 32 (2~63) winsize 62
3904 04:50:38.658151
3905 04:50:38.658203 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3906 04:50:38.658257
3907 04:50:38.658312 [CATrainingPosCal] consider 1 rank data
3908 04:50:38.658367 u2DelayCellTimex100 = 270/100 ps
3909 04:50:38.658419 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3910 04:50:38.658473 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3911 04:50:38.658525 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3912 04:50:38.658578 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3913 04:50:38.658631 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3914 04:50:38.658687 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3915 04:50:38.658741
3916 04:50:38.658810 CA PerBit enable=1, Macro0, CA PI delay=32
3917 04:50:38.658889
3918 04:50:38.658954 [CBTSetCACLKResult] CA Dly = 32
3919 04:50:38.659023 CS Dly: 5 (0~36)
3920 04:50:38.659102 ==
3921 04:50:38.659165 Dram Type= 6, Freq= 0, CH_0, rank 1
3922 04:50:38.659240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3923 04:50:38.659299 ==
3924 04:50:38.659356 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3925 04:50:38.659434 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3926 04:50:38.659497 [CA 0] Center 35 (5~66) winsize 62
3927 04:50:38.659553 [CA 1] Center 35 (5~66) winsize 62
3928 04:50:39.071562 [CA 2] Center 34 (3~65) winsize 63
3929 04:50:39.071707 [CA 3] Center 33 (3~64) winsize 62
3930 04:50:39.071775 [CA 4] Center 33 (2~64) winsize 63
3931 04:50:39.071836 [CA 5] Center 32 (2~63) winsize 62
3932 04:50:39.071895
3933 04:50:39.071952 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3934 04:50:39.072009
3935 04:50:39.072064 [CATrainingPosCal] consider 2 rank data
3936 04:50:39.072119 u2DelayCellTimex100 = 270/100 ps
3937 04:50:39.072175 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3938 04:50:39.072229 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3939 04:50:39.072283 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3940 04:50:39.072387 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3941 04:50:39.072442 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3942 04:50:39.072495 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3943 04:50:39.072548
3944 04:50:39.072601 CA PerBit enable=1, Macro0, CA PI delay=32
3945 04:50:39.072655
3946 04:50:39.072708 [CBTSetCACLKResult] CA Dly = 32
3947 04:50:39.072764 CS Dly: 5 (0~36)
3948 04:50:39.072818
3949 04:50:39.072872 ----->DramcWriteLeveling(PI) begin...
3950 04:50:39.072928 ==
3951 04:50:39.072981 Dram Type= 6, Freq= 0, CH_0, rank 0
3952 04:50:39.073034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3953 04:50:39.073088 ==
3954 04:50:39.073141 Write leveling (Byte 0): 33 => 33
3955 04:50:39.073195 Write leveling (Byte 1): 30 => 30
3956 04:50:39.073248 DramcWriteLeveling(PI) end<-----
3957 04:50:39.073301
3958 04:50:39.073353 ==
3959 04:50:39.073406 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 04:50:39.073460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 04:50:39.073513 ==
3962 04:50:39.073566 [Gating] SW mode calibration
3963 04:50:39.073619 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3964 04:50:39.073673 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3965 04:50:39.073727 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3966 04:50:39.073784 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3967 04:50:39.074054 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3968 04:50:39.074116 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (0 1)
3969 04:50:39.074171 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (0 0)
3970 04:50:39.074225 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3971 04:50:39.074279 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3972 04:50:39.074335 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3973 04:50:39.074391 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3974 04:50:39.074445 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 04:50:39.074498 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3976 04:50:39.074642 0 10 12 | B1->B0 | 2323 4040 | 0 1 | (0 0) (0 0)
3977 04:50:39.074714 0 10 16 | B1->B0 | 3434 4646 | 0 0 | (1 1) (0 0)
3978 04:50:39.074807 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3979 04:50:39.074894 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3980 04:50:39.074949 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3981 04:50:39.075002 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3982 04:50:39.075055 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 04:50:39.075109 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 04:50:39.075162 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3985 04:50:39.075219 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3986 04:50:39.075274 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 04:50:39.075327 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 04:50:39.075380 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 04:50:39.075433 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 04:50:39.075485 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 04:50:39.075539 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 04:50:39.075591 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 04:50:39.075644 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 04:50:39.075701 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 04:50:39.075756 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 04:50:39.075808 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 04:50:39.075861 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 04:50:39.075914 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 04:50:39.075967 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 04:50:39.076020 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4001 04:50:39.076073 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 04:50:39.076126 Total UI for P1: 0, mck2ui 16
4003 04:50:39.076180 best dqsien dly found for B0: ( 0, 13, 12)
4004 04:50:39.076233 Total UI for P1: 0, mck2ui 16
4005 04:50:39.076293 best dqsien dly found for B1: ( 0, 13, 14)
4006 04:50:39.076389 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4007 04:50:39.076443 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4008 04:50:39.076496
4009 04:50:39.076615 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4010 04:50:39.076742 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4011 04:50:39.076819 [Gating] SW calibration Done
4012 04:50:39.076875 ==
4013 04:50:39.076929 Dram Type= 6, Freq= 0, CH_0, rank 0
4014 04:50:39.076983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4015 04:50:39.077036 ==
4016 04:50:39.077090 RX Vref Scan: 0
4017 04:50:39.077142
4018 04:50:39.077194 RX Vref 0 -> 0, step: 1
4019 04:50:39.077247
4020 04:50:39.077299 RX Delay -230 -> 252, step: 16
4021 04:50:39.077352 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4022 04:50:39.077405 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4023 04:50:39.077458 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4024 04:50:39.077511 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4025 04:50:39.077563 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4026 04:50:39.077616 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4027 04:50:39.077669 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4028 04:50:39.077722 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4029 04:50:39.077774 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4030 04:50:39.077826 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4031 04:50:39.077879 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4032 04:50:39.077935 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4033 04:50:39.077988 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4034 04:50:39.078043 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4035 04:50:39.078096 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4036 04:50:39.078149 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4037 04:50:39.078202 ==
4038 04:50:39.078256 Dram Type= 6, Freq= 0, CH_0, rank 0
4039 04:50:39.078309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4040 04:50:39.078363 ==
4041 04:50:39.078416 DQS Delay:
4042 04:50:39.078469 DQS0 = 0, DQS1 = 0
4043 04:50:39.078522 DQM Delay:
4044 04:50:39.078575 DQM0 = 51, DQM1 = 45
4045 04:50:39.078628 DQ Delay:
4046 04:50:39.078685 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4047 04:50:39.078741 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4048 04:50:39.078794 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4049 04:50:39.078848 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4050 04:50:39.078901
4051 04:50:39.078954
4052 04:50:39.079007 ==
4053 04:50:39.079060 Dram Type= 6, Freq= 0, CH_0, rank 0
4054 04:50:39.079114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4055 04:50:39.079170 ==
4056 04:50:39.079225
4057 04:50:39.079278
4058 04:50:39.079331 TX Vref Scan disable
4059 04:50:39.079384 == TX Byte 0 ==
4060 04:50:39.079437 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4061 04:50:39.079490 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4062 04:50:39.079543 == TX Byte 1 ==
4063 04:50:39.079596 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4064 04:50:39.079649 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4065 04:50:39.079702 ==
4066 04:50:39.079759 Dram Type= 6, Freq= 0, CH_0, rank 0
4067 04:50:39.079814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4068 04:50:39.079868 ==
4069 04:50:39.079921
4070 04:50:39.079974
4071 04:50:39.080026 TX Vref Scan disable
4072 04:50:39.080080 == TX Byte 0 ==
4073 04:50:39.080132 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4074 04:50:39.080189 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4075 04:50:39.080243 == TX Byte 1 ==
4076 04:50:39.080345 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4077 04:50:39.080401 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4078 04:50:39.080455
4079 04:50:39.080508 [DATLAT]
4080 04:50:39.080561 Freq=600, CH0 RK0
4081 04:50:39.080824
4082 04:50:39.080963 DATLAT Default: 0x9
4083 04:50:39.081092 0, 0xFFFF, sum = 0
4084 04:50:39.081225 1, 0xFFFF, sum = 0
4085 04:50:39.081356 2, 0xFFFF, sum = 0
4086 04:50:39.081488 3, 0xFFFF, sum = 0
4087 04:50:39.081627 4, 0xFFFF, sum = 0
4088 04:50:39.081817 5, 0xFFFF, sum = 0
4089 04:50:39.081981 6, 0xFFFF, sum = 0
4090 04:50:39.082100 7, 0xFFFF, sum = 0
4091 04:50:39.082161 8, 0x0, sum = 1
4092 04:50:39.082218 9, 0x0, sum = 2
4093 04:50:39.082273 10, 0x0, sum = 3
4094 04:50:39.082329 11, 0x0, sum = 4
4095 04:50:39.082383 best_step = 9
4096 04:50:39.082437
4097 04:50:39.082491 ==
4098 04:50:39.082545 Dram Type= 6, Freq= 0, CH_0, rank 0
4099 04:50:39.082599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4100 04:50:39.082653 ==
4101 04:50:39.082710 RX Vref Scan: 1
4102 04:50:39.082766
4103 04:50:39.082819 RX Vref 0 -> 0, step: 1
4104 04:50:39.082873
4105 04:50:39.082925 RX Delay -163 -> 252, step: 8
4106 04:50:39.082978
4107 04:50:39.083032 Set Vref, RX VrefLevel [Byte0]: 56
4108 04:50:39.083089 [Byte1]: 46
4109 04:50:39.083143
4110 04:50:39.083197 Final RX Vref Byte 0 = 56 to rank0
4111 04:50:39.083251 Final RX Vref Byte 1 = 46 to rank0
4112 04:50:39.083304 Final RX Vref Byte 0 = 56 to rank1
4113 04:50:39.083358 Final RX Vref Byte 1 = 46 to rank1==
4114 04:50:39.083412 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 04:50:39.083465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 04:50:39.083519 ==
4117 04:50:39.083572 DQS Delay:
4118 04:50:39.083626 DQS0 = 0, DQS1 = 0
4119 04:50:39.083679 DQM Delay:
4120 04:50:39.083732 DQM0 = 53, DQM1 = 45
4121 04:50:39.083786 DQ Delay:
4122 04:50:39.083839 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4123 04:50:39.083892 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4124 04:50:39.083945 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4125 04:50:39.083998 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4126 04:50:39.084051
4127 04:50:39.084104
4128 04:50:39.084157 [DQSOSCAuto] RK0, (LSB)MR18= 0x6f63, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4129 04:50:39.084212 CH0 RK0: MR19=808, MR18=6F63
4130 04:50:39.084266 CH0_RK0: MR19=0x808, MR18=0x6F63, DQSOSC=389, MR23=63, INC=173, DEC=115
4131 04:50:39.084368
4132 04:50:39.084423 ----->DramcWriteLeveling(PI) begin...
4133 04:50:39.084478 ==
4134 04:50:39.084531 Dram Type= 6, Freq= 0, CH_0, rank 1
4135 04:50:39.084584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 04:50:39.084638 ==
4137 04:50:39.084692 Write leveling (Byte 0): 34 => 34
4138 04:50:39.084745 Write leveling (Byte 1): 33 => 33
4139 04:50:39.084799 DramcWriteLeveling(PI) end<-----
4140 04:50:39.084852
4141 04:50:39.084904 ==
4142 04:50:39.084958 Dram Type= 6, Freq= 0, CH_0, rank 1
4143 04:50:39.085011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4144 04:50:39.085065 ==
4145 04:50:39.085118 [Gating] SW mode calibration
4146 04:50:39.085172 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4147 04:50:39.085227 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4148 04:50:39.085280 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4149 04:50:39.085334 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4150 04:50:39.085387 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4151 04:50:39.085440 0 9 12 | B1->B0 | 3434 3232 | 0 1 | (0 1) (1 1)
4152 04:50:39.085493 0 9 16 | B1->B0 | 2f2f 2828 | 0 0 | (1 1) (0 0)
4153 04:50:39.085547 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4154 04:50:39.085599 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4155 04:50:39.085653 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4156 04:50:39.085706 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4157 04:50:39.085759 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4158 04:50:39.085812 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4159 04:50:39.085865 0 10 12 | B1->B0 | 2a2a 2d2d | 0 1 | (0 0) (0 0)
4160 04:50:39.085918 0 10 16 | B1->B0 | 3c3c 4040 | 0 1 | (0 0) (0 0)
4161 04:50:39.085971 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4162 04:50:39.086024 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4163 04:50:39.086077 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4164 04:50:39.086130 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4165 04:50:39.086183 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4166 04:50:39.086236 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4167 04:50:39.086289 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4168 04:50:39.086342 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4169 04:50:39.086396 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 04:50:39.086448 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 04:50:39.086501 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 04:50:39.086554 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 04:50:39.086607 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 04:50:39.086659 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 04:50:39.086712 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 04:50:39.086766 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 04:50:39.086819 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 04:50:39.086872 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 04:50:39.086925 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 04:50:39.086978 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 04:50:39.087031 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 04:50:39.087084 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 04:50:39.087137 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4184 04:50:39.087190 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4185 04:50:39.087243 Total UI for P1: 0, mck2ui 16
4186 04:50:39.087297 best dqsien dly found for B0: ( 0, 13, 12)
4187 04:50:39.087349 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 04:50:39.087403 Total UI for P1: 0, mck2ui 16
4189 04:50:39.087456 best dqsien dly found for B1: ( 0, 13, 16)
4190 04:50:39.087510 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4191 04:50:39.087563 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4192 04:50:39.087616
4193 04:50:39.087669 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4194 04:50:39.087723 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4195 04:50:39.087776 [Gating] SW calibration Done
4196 04:50:39.087829 ==
4197 04:50:39.087883 Dram Type= 6, Freq= 0, CH_0, rank 1
4198 04:50:39.087936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4199 04:50:39.088005 ==
4200 04:50:39.088072 RX Vref Scan: 0
4201 04:50:39.088125
4202 04:50:39.088389 RX Vref 0 -> 0, step: 1
4203 04:50:39.088453
4204 04:50:39.088509 RX Delay -230 -> 252, step: 16
4205 04:50:39.088564 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4206 04:50:39.088619 iDelay=218, Bit 1, Center 57 (-86 ~ 201) 288
4207 04:50:39.088672 iDelay=218, Bit 2, Center 57 (-86 ~ 201) 288
4208 04:50:39.088726 iDelay=218, Bit 3, Center 57 (-86 ~ 201) 288
4209 04:50:39.088779 iDelay=218, Bit 4, Center 65 (-86 ~ 217) 304
4210 04:50:39.088833 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4211 04:50:39.088886 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4212 04:50:39.088939 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4213 04:50:39.088992 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4214 04:50:39.089045 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4215 04:50:39.089098 iDelay=218, Bit 10, Center 57 (-86 ~ 201) 288
4216 04:50:39.089151 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4217 04:50:39.089204 iDelay=218, Bit 12, Center 57 (-86 ~ 201) 288
4218 04:50:39.089258 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4219 04:50:39.089311 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4220 04:50:39.089364 iDelay=218, Bit 15, Center 57 (-86 ~ 201) 288
4221 04:50:39.089417 ==
4222 04:50:39.089470 Dram Type= 6, Freq= 0, CH_0, rank 1
4223 04:50:39.089523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4224 04:50:39.089577 ==
4225 04:50:39.089630 DQS Delay:
4226 04:50:39.089683 DQS0 = 0, DQS1 = 0
4227 04:50:39.089736 DQM Delay:
4228 04:50:39.089789 DQM0 = 58, DQM1 = 48
4229 04:50:39.089841 DQ Delay:
4230 04:50:39.089895 DQ0 =57, DQ1 =57, DQ2 =57, DQ3 =57
4231 04:50:39.089948 DQ4 =65, DQ5 =41, DQ6 =65, DQ7 =65
4232 04:50:39.090001 DQ8 =33, DQ9 =33, DQ10 =57, DQ11 =33
4233 04:50:39.090054 DQ12 =57, DQ13 =57, DQ14 =57, DQ15 =57
4234 04:50:39.090107
4235 04:50:39.090160
4236 04:50:39.090213 ==
4237 04:50:39.090266 Dram Type= 6, Freq= 0, CH_0, rank 1
4238 04:50:39.090319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4239 04:50:39.090372 ==
4240 04:50:39.090426
4241 04:50:39.090496
4242 04:50:39.090550 TX Vref Scan disable
4243 04:50:39.090647 == TX Byte 0 ==
4244 04:50:39.090714 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4245 04:50:39.090770 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4246 04:50:39.090824 == TX Byte 1 ==
4247 04:50:39.090879 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4248 04:50:39.090933 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4249 04:50:39.090987 ==
4250 04:50:39.091055 Dram Type= 6, Freq= 0, CH_0, rank 1
4251 04:50:39.091108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4252 04:50:39.091161 ==
4253 04:50:39.091214
4254 04:50:39.091267
4255 04:50:39.091319 TX Vref Scan disable
4256 04:50:39.091372 == TX Byte 0 ==
4257 04:50:39.091440 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4258 04:50:39.091508 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4259 04:50:39.091561 == TX Byte 1 ==
4260 04:50:39.091615 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4261 04:50:39.091668 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4262 04:50:39.091721
4263 04:50:39.091773 [DATLAT]
4264 04:50:39.091826 Freq=600, CH0 RK1
4265 04:50:39.091879
4266 04:50:39.091932 DATLAT Default: 0x9
4267 04:50:39.091984 0, 0xFFFF, sum = 0
4268 04:50:39.092038 1, 0xFFFF, sum = 0
4269 04:50:39.092093 2, 0xFFFF, sum = 0
4270 04:50:39.092146 3, 0xFFFF, sum = 0
4271 04:50:39.092201 4, 0xFFFF, sum = 0
4272 04:50:39.092254 5, 0xFFFF, sum = 0
4273 04:50:39.092356 6, 0xFFFF, sum = 0
4274 04:50:39.092412 7, 0xFFFF, sum = 0
4275 04:50:39.092482 8, 0x0, sum = 1
4276 04:50:39.092613 9, 0x0, sum = 2
4277 04:50:39.092700 10, 0x0, sum = 3
4278 04:50:39.092816 11, 0x0, sum = 4
4279 04:50:39.092916 best_step = 9
4280 04:50:39.092987
4281 04:50:39.093041 ==
4282 04:50:39.093096 Dram Type= 6, Freq= 0, CH_0, rank 1
4283 04:50:39.093150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4284 04:50:39.093204 ==
4285 04:50:39.093257 RX Vref Scan: 0
4286 04:50:39.093311
4287 04:50:39.093364 RX Vref 0 -> 0, step: 1
4288 04:50:39.093417
4289 04:50:39.093469 RX Delay -163 -> 252, step: 8
4290 04:50:39.093523 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4291 04:50:39.093576 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4292 04:50:39.093629 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4293 04:50:39.093682 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4294 04:50:39.093735 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4295 04:50:39.093788 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4296 04:50:39.093841 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4297 04:50:39.093893 iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280
4298 04:50:39.093946 iDelay=205, Bit 8, Center 40 (-99 ~ 180) 280
4299 04:50:39.093998 iDelay=205, Bit 9, Center 32 (-107 ~ 172) 280
4300 04:50:39.094051 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4301 04:50:39.094104 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4302 04:50:39.094156 iDelay=205, Bit 12, Center 52 (-83 ~ 188) 272
4303 04:50:39.094208 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4304 04:50:39.094260 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4305 04:50:39.094312 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4306 04:50:39.094365 ==
4307 04:50:39.094417 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 04:50:39.094470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 04:50:39.094538 ==
4310 04:50:39.094592 DQS Delay:
4311 04:50:39.094645 DQS0 = 0, DQS1 = 0
4312 04:50:39.094698 DQM Delay:
4313 04:50:39.094750 DQM0 = 54, DQM1 = 46
4314 04:50:39.094802 DQ Delay:
4315 04:50:39.094857 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4316 04:50:39.094911 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =64
4317 04:50:39.094964 DQ8 =40, DQ9 =32, DQ10 =48, DQ11 =40
4318 04:50:39.095017 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4319 04:50:39.095069
4320 04:50:39.095122
4321 04:50:39.095174 [DQSOSCAuto] RK1, (LSB)MR18= 0x6223, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4322 04:50:39.095228 CH0 RK1: MR19=808, MR18=6223
4323 04:50:39.095281 CH0_RK1: MR19=0x808, MR18=0x6223, DQSOSC=391, MR23=63, INC=171, DEC=114
4324 04:50:39.095334 [RxdqsGatingPostProcess] freq 600
4325 04:50:39.095386 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4326 04:50:39.095439 Pre-setting of DQS Precalculation
4327 04:50:39.095492 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4328 04:50:39.095545 ==
4329 04:50:39.095597 Dram Type= 6, Freq= 0, CH_1, rank 0
4330 04:50:39.095650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4331 04:50:39.095703 ==
4332 04:50:39.095757 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4333 04:50:39.095810 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4334 04:50:39.095863 [CA 0] Center 35 (5~66) winsize 62
4335 04:50:39.095916 [CA 1] Center 35 (5~66) winsize 62
4336 04:50:39.095969 [CA 2] Center 34 (4~65) winsize 62
4337 04:50:39.096231 [CA 3] Center 34 (4~65) winsize 62
4338 04:50:39.096431 [CA 4] Center 34 (4~65) winsize 62
4339 04:50:39.096578 [CA 5] Center 33 (3~64) winsize 62
4340 04:50:39.096722
4341 04:50:39.096847 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4342 04:50:39.096990
4343 04:50:39.097129 [CATrainingPosCal] consider 1 rank data
4344 04:50:39.097257 u2DelayCellTimex100 = 270/100 ps
4345 04:50:39.097414 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4346 04:50:39.097541 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4347 04:50:39.097637 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4348 04:50:39.097693 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4349 04:50:39.097748 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4350 04:50:39.097801 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4351 04:50:39.097902
4352 04:50:39.097969 CA PerBit enable=1, Macro0, CA PI delay=33
4353 04:50:39.098022
4354 04:50:39.098074 [CBTSetCACLKResult] CA Dly = 33
4355 04:50:39.098128 CS Dly: 5 (0~36)
4356 04:50:39.098180 ==
4357 04:50:39.098249 Dram Type= 6, Freq= 0, CH_1, rank 1
4358 04:50:39.098316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4359 04:50:39.098398 ==
4360 04:50:39.098451 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4361 04:50:39.098504 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4362 04:50:39.098557 [CA 0] Center 36 (6~67) winsize 62
4363 04:50:39.098610 [CA 1] Center 36 (5~67) winsize 63
4364 04:50:39.098662 [CA 2] Center 34 (4~65) winsize 62
4365 04:50:39.098715 [CA 3] Center 34 (4~65) winsize 62
4366 04:50:39.098796 [CA 4] Center 34 (4~65) winsize 62
4367 04:50:39.098848 [CA 5] Center 34 (3~65) winsize 63
4368 04:50:39.098903
4369 04:50:39.098956 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4370 04:50:39.099008
4371 04:50:39.099091 [CATrainingPosCal] consider 2 rank data
4372 04:50:39.099171 u2DelayCellTimex100 = 270/100 ps
4373 04:50:39.099224 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4374 04:50:39.099277 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4375 04:50:39.099345 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4376 04:50:39.099411 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4377 04:50:39.099464 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4378 04:50:39.099516 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4379 04:50:39.099569
4380 04:50:39.099621 CA PerBit enable=1, Macro0, CA PI delay=33
4381 04:50:39.099717
4382 04:50:39.099771 [CBTSetCACLKResult] CA Dly = 33
4383 04:50:39.099825 CS Dly: 6 (0~38)
4384 04:50:39.099879
4385 04:50:39.099932 ----->DramcWriteLeveling(PI) begin...
4386 04:50:39.099987 ==
4387 04:50:39.100068 Dram Type= 6, Freq= 0, CH_1, rank 0
4388 04:50:39.100123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4389 04:50:39.100177 ==
4390 04:50:39.100231 Write leveling (Byte 0): 31 => 31
4391 04:50:39.100291 Write leveling (Byte 1): 31 => 31
4392 04:50:39.100366 DramcWriteLeveling(PI) end<-----
4393 04:50:39.100418
4394 04:50:39.100471 ==
4395 04:50:39.100524 Dram Type= 6, Freq= 0, CH_1, rank 0
4396 04:50:39.100577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 04:50:39.100630 ==
4398 04:50:39.100683 [Gating] SW mode calibration
4399 04:50:39.100736 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4400 04:50:39.100789 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4401 04:50:39.100842 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4402 04:50:39.100895 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4403 04:50:39.100947 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4404 04:50:39.101000 0 9 12 | B1->B0 | 3030 2f2f | 1 0 | (0 1) (0 1)
4405 04:50:39.101053 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4406 04:50:39.101105 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 04:50:39.101157 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 04:50:39.101210 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4409 04:50:39.101291 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 04:50:39.101359 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 04:50:39.101426 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4412 04:50:39.101479 0 10 12 | B1->B0 | 3434 4040 | 0 0 | (0 0) (0 0)
4413 04:50:39.101531 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 04:50:39.101583 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 04:50:39.101636 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 04:50:39.101688 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 04:50:39.101741 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 04:50:39.101794 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 04:50:39.101846 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4420 04:50:39.101899 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4421 04:50:39.101951 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 04:50:39.102004 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 04:50:39.102056 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 04:50:39.102108 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 04:50:39.102160 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 04:50:39.102213 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 04:50:39.102265 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 04:50:39.102317 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 04:50:39.102370 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 04:50:39.102423 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 04:50:39.102475 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 04:50:39.102527 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 04:50:39.102580 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 04:50:39.102632 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 04:50:39.102684 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 04:50:39.102737 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4437 04:50:39.102790 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 04:50:39.102842 Total UI for P1: 0, mck2ui 16
4439 04:50:39.102896 best dqsien dly found for B0: ( 0, 13, 12)
4440 04:50:39.102948 Total UI for P1: 0, mck2ui 16
4441 04:50:39.103001 best dqsien dly found for B1: ( 0, 13, 12)
4442 04:50:39.103053 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4443 04:50:39.103315 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4444 04:50:39.103404
4445 04:50:39.103488 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4446 04:50:39.103571 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4447 04:50:39.103662 [Gating] SW calibration Done
4448 04:50:39.103750 ==
4449 04:50:39.103805 Dram Type= 6, Freq= 0, CH_1, rank 0
4450 04:50:39.103859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4451 04:50:39.103912 ==
4452 04:50:39.103966 RX Vref Scan: 0
4453 04:50:39.104019
4454 04:50:39.104071 RX Vref 0 -> 0, step: 1
4455 04:50:39.104124
4456 04:50:39.104177 RX Delay -230 -> 252, step: 16
4457 04:50:39.104230 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4458 04:50:39.104283 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4459 04:50:39.104385 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4460 04:50:39.104439 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4461 04:50:39.104491 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4462 04:50:39.104545 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4463 04:50:39.104598 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4464 04:50:39.104650 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4465 04:50:39.104702 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4466 04:50:39.104755 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4467 04:50:39.104808 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4468 04:50:39.104860 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4469 04:50:39.104912 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4470 04:50:39.104965 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4471 04:50:39.105018 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4472 04:50:39.105070 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4473 04:50:39.105122 ==
4474 04:50:39.105189 Dram Type= 6, Freq= 0, CH_1, rank 0
4475 04:50:39.105243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4476 04:50:39.105296 ==
4477 04:50:39.105350 DQS Delay:
4478 04:50:39.105402 DQS0 = 0, DQS1 = 0
4479 04:50:39.105454 DQM Delay:
4480 04:50:39.105507 DQM0 = 50, DQM1 = 46
4481 04:50:39.105560 DQ Delay:
4482 04:50:39.105612 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4483 04:50:39.105666 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4484 04:50:39.105719 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4485 04:50:39.105771 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4486 04:50:39.105824
4487 04:50:39.105877
4488 04:50:39.105929 ==
4489 04:50:39.105981 Dram Type= 6, Freq= 0, CH_1, rank 0
4490 04:50:39.106033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4491 04:50:39.106086 ==
4492 04:50:39.106139
4493 04:50:39.106191
4494 04:50:39.106243 TX Vref Scan disable
4495 04:50:39.106295 == TX Byte 0 ==
4496 04:50:39.106347 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4497 04:50:39.106400 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4498 04:50:39.106453 == TX Byte 1 ==
4499 04:50:39.106505 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4500 04:50:39.106558 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4501 04:50:39.106610 ==
4502 04:50:39.106663 Dram Type= 6, Freq= 0, CH_1, rank 0
4503 04:50:39.106723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4504 04:50:39.106778 ==
4505 04:50:39.106831
4506 04:50:39.106883
4507 04:50:39.106935 TX Vref Scan disable
4508 04:50:39.106987 == TX Byte 0 ==
4509 04:50:39.107039 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4510 04:50:39.107093 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4511 04:50:39.107145 == TX Byte 1 ==
4512 04:50:39.107197 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4513 04:50:39.107250 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4514 04:50:39.107302
4515 04:50:39.107354 [DATLAT]
4516 04:50:39.107406 Freq=600, CH1 RK0
4517 04:50:39.107459
4518 04:50:39.107511 DATLAT Default: 0x9
4519 04:50:39.107564 0, 0xFFFF, sum = 0
4520 04:50:39.107618 1, 0xFFFF, sum = 0
4521 04:50:39.107672 2, 0xFFFF, sum = 0
4522 04:50:39.107726 3, 0xFFFF, sum = 0
4523 04:50:39.107780 4, 0xFFFF, sum = 0
4524 04:50:39.107854 5, 0xFFFF, sum = 0
4525 04:50:39.107911 6, 0xFFFF, sum = 0
4526 04:50:39.107967 7, 0xFFFF, sum = 0
4527 04:50:39.108021 8, 0x0, sum = 1
4528 04:50:39.108074 9, 0x0, sum = 2
4529 04:50:39.108128 10, 0x0, sum = 3
4530 04:50:39.108182 11, 0x0, sum = 4
4531 04:50:39.108235 best_step = 9
4532 04:50:39.108313
4533 04:50:39.108382 ==
4534 04:50:39.108435 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 04:50:39.108489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 04:50:39.108542 ==
4537 04:50:39.108595 RX Vref Scan: 1
4538 04:50:39.108647
4539 04:50:39.108700 RX Vref 0 -> 0, step: 1
4540 04:50:39.108752
4541 04:50:39.108841 RX Delay -163 -> 252, step: 8
4542 04:50:39.108944
4543 04:50:39.109044 Set Vref, RX VrefLevel [Byte0]: 55
4544 04:50:39.109109 [Byte1]: 48
4545 04:50:39.109171
4546 04:50:39.109225 Final RX Vref Byte 0 = 55 to rank0
4547 04:50:39.109287 Final RX Vref Byte 1 = 48 to rank0
4548 04:50:39.109341 Final RX Vref Byte 0 = 55 to rank1
4549 04:50:39.109395 Final RX Vref Byte 1 = 48 to rank1==
4550 04:50:39.109448 Dram Type= 6, Freq= 0, CH_1, rank 0
4551 04:50:39.109501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4552 04:50:39.109554 ==
4553 04:50:39.109608 DQS Delay:
4554 04:50:39.109661 DQS0 = 0, DQS1 = 0
4555 04:50:39.109713 DQM Delay:
4556 04:50:39.109766 DQM0 = 48, DQM1 = 46
4557 04:50:39.109819 DQ Delay:
4558 04:50:39.109871 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =48
4559 04:50:39.109923 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4560 04:50:39.109975 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4561 04:50:39.110028 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =60
4562 04:50:39.110080
4563 04:50:39.110132
4564 04:50:39.110184 [DQSOSCAuto] RK0, (LSB)MR18= 0x4268, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
4565 04:50:39.110240 CH1 RK0: MR19=808, MR18=4268
4566 04:50:39.110294 CH1_RK0: MR19=0x808, MR18=0x4268, DQSOSC=390, MR23=63, INC=172, DEC=114
4567 04:50:39.110347
4568 04:50:39.110400 ----->DramcWriteLeveling(PI) begin...
4569 04:50:39.110454 ==
4570 04:50:39.110508 Dram Type= 6, Freq= 0, CH_1, rank 1
4571 04:50:39.110560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 04:50:39.110613 ==
4573 04:50:39.110665 Write leveling (Byte 0): 31 => 31
4574 04:50:39.110718 Write leveling (Byte 1): 31 => 31
4575 04:50:39.110771 DramcWriteLeveling(PI) end<-----
4576 04:50:39.110824
4577 04:50:39.110876 ==
4578 04:50:39.110928 Dram Type= 6, Freq= 0, CH_1, rank 1
4579 04:50:39.110980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 04:50:39.111033 ==
4581 04:50:39.111086 [Gating] SW mode calibration
4582 04:50:39.111138 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4583 04:50:39.111191 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4584 04:50:39.111244 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4585 04:50:39.111296 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4586 04:50:39.111349 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4587 04:50:39.111402 0 9 12 | B1->B0 | 2e2e 2e2e | 1 1 | (1 0) (1 1)
4588 04:50:39.111454 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4589 04:50:39.111715 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4590 04:50:39.111908 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4591 04:50:39.112037 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4592 04:50:39.112165 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4593 04:50:39.112334 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4594 04:50:39.112483 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4595 04:50:39.112613 0 10 12 | B1->B0 | 3636 3535 | 0 0 | (0 0) (0 0)
4596 04:50:39.112689 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4597 04:50:39.112747 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4598 04:50:39.112803 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4599 04:50:39.112858 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4600 04:50:39.112914 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4601 04:50:39.112969 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4602 04:50:39.113023 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4603 04:50:39.113077 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4604 04:50:39.113131 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 04:50:39.113185 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 04:50:39.113239 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 04:50:39.113293 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 04:50:39.113347 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 04:50:39.113401 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 04:50:39.113455 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 04:50:39.113509 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 04:50:39.113562 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 04:50:39.113616 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 04:50:39.113670 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 04:50:39.113724 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 04:50:39.113778 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 04:50:39.113832 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 04:50:39.113886 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 04:50:39.113940 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4620 04:50:39.113994 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 04:50:39.114048 Total UI for P1: 0, mck2ui 16
4622 04:50:39.114102 best dqsien dly found for B0: ( 0, 13, 14)
4623 04:50:39.114156 Total UI for P1: 0, mck2ui 16
4624 04:50:39.114211 best dqsien dly found for B1: ( 0, 13, 12)
4625 04:50:39.114264 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4626 04:50:39.114319 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4627 04:50:39.114372
4628 04:50:39.114426 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4629 04:50:39.114480 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4630 04:50:39.114580 [Gating] SW calibration Done
4631 04:50:39.114637 ==
4632 04:50:39.114692 Dram Type= 6, Freq= 0, CH_1, rank 1
4633 04:50:39.114746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4634 04:50:39.114817 ==
4635 04:50:39.114870 RX Vref Scan: 0
4636 04:50:39.114923
4637 04:50:39.114976 RX Vref 0 -> 0, step: 1
4638 04:50:39.115029
4639 04:50:39.115081 RX Delay -230 -> 252, step: 16
4640 04:50:39.115134 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4641 04:50:39.115187 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4642 04:50:39.115241 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4643 04:50:39.115294 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4644 04:50:39.115347 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4645 04:50:39.115400 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4646 04:50:39.115453 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4647 04:50:39.115506 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4648 04:50:39.115558 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4649 04:50:39.115611 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4650 04:50:39.115664 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4651 04:50:39.115716 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4652 04:50:39.115787 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4653 04:50:39.115853 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4654 04:50:39.115905 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4655 04:50:39.115958 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4656 04:50:39.116011 ==
4657 04:50:39.116092 Dram Type= 6, Freq= 0, CH_1, rank 1
4658 04:50:39.116174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4659 04:50:39.116243 ==
4660 04:50:39.116321 DQS Delay:
4661 04:50:39.116376 DQS0 = 0, DQS1 = 0
4662 04:50:39.116429 DQM Delay:
4663 04:50:39.116482 DQM0 = 50, DQM1 = 47
4664 04:50:39.116534 DQ Delay:
4665 04:50:39.116605 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4666 04:50:39.116661 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4667 04:50:39.116714 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4668 04:50:39.116791 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4669 04:50:39.116871
4670 04:50:39.116936
4671 04:50:39.117001 ==
4672 04:50:39.117055 Dram Type= 6, Freq= 0, CH_1, rank 1
4673 04:50:39.117109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4674 04:50:39.117162 ==
4675 04:50:39.117215
4676 04:50:39.117268
4677 04:50:39.117320 TX Vref Scan disable
4678 04:50:39.117373 == TX Byte 0 ==
4679 04:50:39.117426 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4680 04:50:39.117480 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4681 04:50:39.117533 == TX Byte 1 ==
4682 04:50:39.117587 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4683 04:50:39.117655 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4684 04:50:39.117713 ==
4685 04:50:39.117767 Dram Type= 6, Freq= 0, CH_1, rank 1
4686 04:50:39.117820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4687 04:50:39.117873 ==
4688 04:50:39.117926
4689 04:50:39.118004
4690 04:50:39.118097 TX Vref Scan disable
4691 04:50:39.118155 == TX Byte 0 ==
4692 04:50:39.118208 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4693 04:50:39.118262 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4694 04:50:39.118316 == TX Byte 1 ==
4695 04:50:39.118369 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4696 04:50:39.118423 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4697 04:50:39.118476
4698 04:50:39.118528 [DATLAT]
4699 04:50:39.118580 Freq=600, CH1 RK1
4700 04:50:39.118634
4701 04:50:39.118686 DATLAT Default: 0x9
4702 04:50:39.118739 0, 0xFFFF, sum = 0
4703 04:50:39.118794 1, 0xFFFF, sum = 0
4704 04:50:39.118847 2, 0xFFFF, sum = 0
4705 04:50:39.118900 3, 0xFFFF, sum = 0
4706 04:50:39.118954 4, 0xFFFF, sum = 0
4707 04:50:39.119215 5, 0xFFFF, sum = 0
4708 04:50:39.119277 6, 0xFFFF, sum = 0
4709 04:50:39.119343 7, 0xFFFF, sum = 0
4710 04:50:39.119398 8, 0x0, sum = 1
4711 04:50:39.119452 9, 0x0, sum = 2
4712 04:50:39.119516 10, 0x0, sum = 3
4713 04:50:39.119585 11, 0x0, sum = 4
4714 04:50:39.119661 best_step = 9
4715 04:50:39.119725
4716 04:50:39.119781 ==
4717 04:50:39.119844 Dram Type= 6, Freq= 0, CH_1, rank 1
4718 04:50:39.119906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4719 04:50:39.119962 ==
4720 04:50:39.120022 RX Vref Scan: 0
4721 04:50:39.120084
4722 04:50:39.120144 RX Vref 0 -> 0, step: 1
4723 04:50:39.120205
4724 04:50:39.120264 RX Delay -163 -> 252, step: 8
4725 04:50:39.120381 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4726 04:50:39.120439 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4727 04:50:39.120501 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4728 04:50:39.120554 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4729 04:50:39.120613 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4730 04:50:39.120668 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4731 04:50:39.120728 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4732 04:50:39.120782 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4733 04:50:39.120834 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4734 04:50:39.120887 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4735 04:50:39.120940 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4736 04:50:39.120993 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4737 04:50:39.121046 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4738 04:50:39.121098 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4739 04:50:39.121151 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4740 04:50:39.121204 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4741 04:50:39.121257 ==
4742 04:50:39.121310 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 04:50:39.121374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 04:50:39.121430 ==
4745 04:50:39.121483 DQS Delay:
4746 04:50:39.121536 DQS0 = 0, DQS1 = 0
4747 04:50:39.121589 DQM Delay:
4748 04:50:39.121641 DQM0 = 48, DQM1 = 45
4749 04:50:39.121694 DQ Delay:
4750 04:50:39.121746 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4751 04:50:39.121799 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4752 04:50:39.121852 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4753 04:50:39.121904 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4754 04:50:39.121956
4755 04:50:39.122009
4756 04:50:39.122061 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4757 04:50:39.122116 CH1 RK1: MR19=808, MR18=6A21
4758 04:50:39.122168 CH1_RK1: MR19=0x808, MR18=0x6A21, DQSOSC=389, MR23=63, INC=173, DEC=115
4759 04:50:39.122221 [RxdqsGatingPostProcess] freq 600
4760 04:50:39.122274 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4761 04:50:39.122327 Pre-setting of DQS Precalculation
4762 04:50:39.122380 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4763 04:50:39.122433 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4764 04:50:39.122487 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4765 04:50:39.122540
4766 04:50:39.122592
4767 04:50:39.122644 [Calibration Summary] 1200 Mbps
4768 04:50:39.122697 CH 0, Rank 0
4769 04:50:39.122749 SW Impedance : PASS
4770 04:50:39.122802 DUTY Scan : NO K
4771 04:50:39.122854 ZQ Calibration : PASS
4772 04:50:39.122907 Jitter Meter : NO K
4773 04:50:39.122959 CBT Training : PASS
4774 04:50:39.123012 Write leveling : PASS
4775 04:50:39.123064 RX DQS gating : PASS
4776 04:50:39.123117 RX DQ/DQS(RDDQC) : PASS
4777 04:50:39.123232 TX DQ/DQS : PASS
4778 04:50:39.123290 RX DATLAT : PASS
4779 04:50:39.123343 RX DQ/DQS(Engine): PASS
4780 04:50:39.123396 TX OE : NO K
4781 04:50:39.123449 All Pass.
4782 04:50:39.123502
4783 04:50:39.123555 CH 0, Rank 1
4784 04:50:39.123607 SW Impedance : PASS
4785 04:50:39.123660 DUTY Scan : NO K
4786 04:50:39.123713 ZQ Calibration : PASS
4787 04:50:39.123766 Jitter Meter : NO K
4788 04:50:39.123818 CBT Training : PASS
4789 04:50:39.123871 Write leveling : PASS
4790 04:50:39.123925 RX DQS gating : PASS
4791 04:50:39.123978 RX DQ/DQS(RDDQC) : PASS
4792 04:50:39.124030 TX DQ/DQS : PASS
4793 04:50:39.124098 RX DATLAT : PASS
4794 04:50:39.124152 RX DQ/DQS(Engine): PASS
4795 04:50:39.124205 TX OE : NO K
4796 04:50:39.124260 All Pass.
4797 04:50:39.124354
4798 04:50:39.124411 CH 1, Rank 0
4799 04:50:39.124464 SW Impedance : PASS
4800 04:50:39.124518 DUTY Scan : NO K
4801 04:50:39.124570 ZQ Calibration : PASS
4802 04:50:39.124622 Jitter Meter : NO K
4803 04:50:39.124675 CBT Training : PASS
4804 04:50:39.124728 Write leveling : PASS
4805 04:50:39.124781 RX DQS gating : PASS
4806 04:50:39.124834 RX DQ/DQS(RDDQC) : PASS
4807 04:50:39.124888 TX DQ/DQS : PASS
4808 04:50:39.124940 RX DATLAT : PASS
4809 04:50:39.124992 RX DQ/DQS(Engine): PASS
4810 04:50:39.125045 TX OE : NO K
4811 04:50:39.125098 All Pass.
4812 04:50:39.125150
4813 04:50:39.125202 CH 1, Rank 1
4814 04:50:39.125255 SW Impedance : PASS
4815 04:50:39.125307 DUTY Scan : NO K
4816 04:50:39.125360 ZQ Calibration : PASS
4817 04:50:39.125412 Jitter Meter : NO K
4818 04:50:39.125465 CBT Training : PASS
4819 04:50:39.125516 Write leveling : PASS
4820 04:50:39.125569 RX DQS gating : PASS
4821 04:50:39.125622 RX DQ/DQS(RDDQC) : PASS
4822 04:50:39.125674 TX DQ/DQS : PASS
4823 04:50:39.125727 RX DATLAT : PASS
4824 04:50:39.125779 RX DQ/DQS(Engine): PASS
4825 04:50:39.125831 TX OE : NO K
4826 04:50:39.125884 All Pass.
4827 04:50:39.125936
4828 04:50:39.125988 DramC Write-DBI off
4829 04:50:39.126040 PER_BANK_REFRESH: Hybrid Mode
4830 04:50:39.126093 TX_TRACKING: ON
4831 04:50:39.126145 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4832 04:50:39.126200 [FAST_K] Save calibration result to emmc
4833 04:50:39.126252 dramc_set_vcore_voltage set vcore to 662500
4834 04:50:39.126305 Read voltage for 933, 3
4835 04:50:39.126357 Vio18 = 0
4836 04:50:39.126410 Vcore = 662500
4837 04:50:39.126461 Vdram = 0
4838 04:50:39.126513 Vddq = 0
4839 04:50:39.126565 Vmddr = 0
4840 04:50:39.126618 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4841 04:50:39.126671 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4842 04:50:39.126724 MEM_TYPE=3, freq_sel=17
4843 04:50:39.126776 sv_algorithm_assistance_LP4_1600
4844 04:50:39.126829 ============ PULL DRAM RESETB DOWN ============
4845 04:50:39.126882 ========== PULL DRAM RESETB DOWN end =========
4846 04:50:39.126935 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4847 04:50:39.126989 ===================================
4848 04:50:39.127041 LPDDR4 DRAM CONFIGURATION
4849 04:50:39.127094 ===================================
4850 04:50:39.127146 EX_ROW_EN[0] = 0x0
4851 04:50:39.127413 EX_ROW_EN[1] = 0x0
4852 04:50:39.127474 LP4Y_EN = 0x0
4853 04:50:39.127528 WORK_FSP = 0x0
4854 04:50:39.127582 WL = 0x3
4855 04:50:39.127635 RL = 0x3
4856 04:50:39.127688 BL = 0x2
4857 04:50:39.127743 RPST = 0x0
4858 04:50:39.127796 RD_PRE = 0x0
4859 04:50:39.127848 WR_PRE = 0x1
4860 04:50:39.127901 WR_PST = 0x0
4861 04:50:39.127953 DBI_WR = 0x0
4862 04:50:39.128005 DBI_RD = 0x0
4863 04:50:39.128057 OTF = 0x1
4864 04:50:39.128110 ===================================
4865 04:50:39.128163 ===================================
4866 04:50:39.128216 ANA top config
4867 04:50:39.128269 ===================================
4868 04:50:39.128368 DLL_ASYNC_EN = 0
4869 04:50:39.128421 ALL_SLAVE_EN = 1
4870 04:50:39.128474 NEW_RANK_MODE = 1
4871 04:50:39.128528 DLL_IDLE_MODE = 1
4872 04:50:39.128580 LP45_APHY_COMB_EN = 1
4873 04:50:39.128632 TX_ODT_DIS = 1
4874 04:50:39.128685 NEW_8X_MODE = 1
4875 04:50:39.128738 ===================================
4876 04:50:39.128790 ===================================
4877 04:50:39.128846 data_rate = 1866
4878 04:50:39.128899 CKR = 1
4879 04:50:39.128951 DQ_P2S_RATIO = 8
4880 04:50:39.129004 ===================================
4881 04:50:39.129057 CA_P2S_RATIO = 8
4882 04:50:39.129110 DQ_CA_OPEN = 0
4883 04:50:39.129163 DQ_SEMI_OPEN = 0
4884 04:50:39.129215 CA_SEMI_OPEN = 0
4885 04:50:39.129267 CA_FULL_RATE = 0
4886 04:50:39.129320 DQ_CKDIV4_EN = 1
4887 04:50:39.129373 CA_CKDIV4_EN = 1
4888 04:50:39.129436 CA_PREDIV_EN = 0
4889 04:50:39.129498 PH8_DLY = 0
4890 04:50:39.129552 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4891 04:50:39.129611 DQ_AAMCK_DIV = 4
4892 04:50:39.129670 CA_AAMCK_DIV = 4
4893 04:50:39.129723 CA_ADMCK_DIV = 4
4894 04:50:39.129782 DQ_TRACK_CA_EN = 0
4895 04:50:39.129842 CA_PICK = 933
4896 04:50:39.129902 CA_MCKIO = 933
4897 04:50:39.129955 MCKIO_SEMI = 0
4898 04:50:39.130015 PLL_FREQ = 3732
4899 04:50:39.130076 DQ_UI_PI_RATIO = 32
4900 04:50:39.130136 CA_UI_PI_RATIO = 0
4901 04:50:39.130189 ===================================
4902 04:50:39.130248 ===================================
4903 04:50:39.130303 memory_type:LPDDR4
4904 04:50:39.130356 GP_NUM : 10
4905 04:50:39.130408 SRAM_EN : 1
4906 04:50:39.130461 MD32_EN : 0
4907 04:50:39.130513 ===================================
4908 04:50:39.130566 [ANA_INIT] >>>>>>>>>>>>>>
4909 04:50:39.130619 <<<<<< [CONFIGURE PHASE]: ANA_TX
4910 04:50:39.130672 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4911 04:50:39.130725 ===================================
4912 04:50:39.130777 data_rate = 1866,PCW = 0X8f00
4913 04:50:39.130829 ===================================
4914 04:50:39.130882 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4915 04:50:39.130935 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4916 04:50:39.130988 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4917 04:50:39.131042 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4918 04:50:39.131094 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4919 04:50:39.131147 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4920 04:50:39.131199 [ANA_INIT] flow start
4921 04:50:39.131252 [ANA_INIT] PLL >>>>>>>>
4922 04:50:39.131303 [ANA_INIT] PLL <<<<<<<<
4923 04:50:39.131356 [ANA_INIT] MIDPI >>>>>>>>
4924 04:50:39.131409 [ANA_INIT] MIDPI <<<<<<<<
4925 04:50:39.131461 [ANA_INIT] DLL >>>>>>>>
4926 04:50:39.131513 [ANA_INIT] flow end
4927 04:50:39.489317 ============ LP4 DIFF to SE enter ============
4928 04:50:39.489460 ============ LP4 DIFF to SE exit ============
4929 04:50:39.489559 [ANA_INIT] <<<<<<<<<<<<<
4930 04:50:39.489620 [Flow] Enable top DCM control >>>>>
4931 04:50:39.489679 [Flow] Enable top DCM control <<<<<
4932 04:50:39.489736 Enable DLL master slave shuffle
4933 04:50:39.489808 ==============================================================
4934 04:50:39.489914 Gating Mode config
4935 04:50:39.490001 ==============================================================
4936 04:50:39.490057 Config description:
4937 04:50:39.490113 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4938 04:50:39.490170 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4939 04:50:39.490225 SELPH_MODE 0: By rank 1: By Phase
4940 04:50:39.490280 ==============================================================
4941 04:50:39.490335 GAT_TRACK_EN = 1
4942 04:50:39.490389 RX_GATING_MODE = 2
4943 04:50:39.490442 RX_GATING_TRACK_MODE = 2
4944 04:50:39.490496 SELPH_MODE = 1
4945 04:50:39.490549 PICG_EARLY_EN = 1
4946 04:50:39.490603 VALID_LAT_VALUE = 1
4947 04:50:39.490656 ==============================================================
4948 04:50:39.490710 Enter into Gating configuration >>>>
4949 04:50:39.490763 Exit from Gating configuration <<<<
4950 04:50:39.490816 Enter into DVFS_PRE_config >>>>>
4951 04:50:39.490870 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4952 04:50:39.490924 Exit from DVFS_PRE_config <<<<<
4953 04:50:39.490977 Enter into PICG configuration >>>>
4954 04:50:39.491030 Exit from PICG configuration <<<<
4955 04:50:39.491093 [RX_INPUT] configuration >>>>>
4956 04:50:39.491153 [RX_INPUT] configuration <<<<<
4957 04:50:39.491207 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4958 04:50:39.491261 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4959 04:50:39.491314 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4960 04:50:39.491367 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4961 04:50:39.491421 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4962 04:50:39.491680 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4963 04:50:39.491740 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4964 04:50:39.491795 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4965 04:50:39.491848 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4966 04:50:39.491901 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4967 04:50:39.491982 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4968 04:50:39.492036 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4969 04:50:39.492089 ===================================
4970 04:50:39.492142 LPDDR4 DRAM CONFIGURATION
4971 04:50:39.492194 ===================================
4972 04:50:39.492247 EX_ROW_EN[0] = 0x0
4973 04:50:39.492342 EX_ROW_EN[1] = 0x0
4974 04:50:39.492397 LP4Y_EN = 0x0
4975 04:50:39.492451 WORK_FSP = 0x0
4976 04:50:39.492504 WL = 0x3
4977 04:50:39.492557 RL = 0x3
4978 04:50:39.492609 BL = 0x2
4979 04:50:39.492662 RPST = 0x0
4980 04:50:39.492715 RD_PRE = 0x0
4981 04:50:39.492768 WR_PRE = 0x1
4982 04:50:39.492821 WR_PST = 0x0
4983 04:50:39.492873 DBI_WR = 0x0
4984 04:50:39.492925 DBI_RD = 0x0
4985 04:50:39.492978 OTF = 0x1
4986 04:50:39.493032 ===================================
4987 04:50:39.493085 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4988 04:50:39.493171 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4989 04:50:39.493227 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4990 04:50:39.493281 ===================================
4991 04:50:39.493334 LPDDR4 DRAM CONFIGURATION
4992 04:50:39.493387 ===================================
4993 04:50:39.493440 EX_ROW_EN[0] = 0x10
4994 04:50:39.493502 EX_ROW_EN[1] = 0x0
4995 04:50:39.493565 LP4Y_EN = 0x0
4996 04:50:39.493618 WORK_FSP = 0x0
4997 04:50:39.493671 WL = 0x3
4998 04:50:39.493724 RL = 0x3
4999 04:50:39.493777 BL = 0x2
5000 04:50:39.493830 RPST = 0x0
5001 04:50:39.493882 RD_PRE = 0x0
5002 04:50:39.493935 WR_PRE = 0x1
5003 04:50:39.493988 WR_PST = 0x0
5004 04:50:39.494040 DBI_WR = 0x0
5005 04:50:39.494092 DBI_RD = 0x0
5006 04:50:39.494145 OTF = 0x1
5007 04:50:39.494198 ===================================
5008 04:50:39.494251 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5009 04:50:39.494305 nWR fixed to 30
5010 04:50:39.494359 [ModeRegInit_LP4] CH0 RK0
5011 04:50:39.494412 [ModeRegInit_LP4] CH0 RK1
5012 04:50:39.494465 [ModeRegInit_LP4] CH1 RK0
5013 04:50:39.494517 [ModeRegInit_LP4] CH1 RK1
5014 04:50:39.494569 match AC timing 9
5015 04:50:39.494621 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5016 04:50:39.494675 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5017 04:50:39.494728 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5018 04:50:39.494781 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5019 04:50:39.494834 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5020 04:50:39.494887 ==
5021 04:50:39.494940 Dram Type= 6, Freq= 0, CH_0, rank 0
5022 04:50:39.494993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5023 04:50:39.495047 ==
5024 04:50:39.495100 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5025 04:50:39.495153 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5026 04:50:39.495206 [CA 0] Center 37 (6~68) winsize 63
5027 04:50:39.495259 [CA 1] Center 37 (7~68) winsize 62
5028 04:50:39.495312 [CA 2] Center 34 (4~65) winsize 62
5029 04:50:39.495365 [CA 3] Center 34 (3~65) winsize 63
5030 04:50:39.495419 [CA 4] Center 33 (3~64) winsize 62
5031 04:50:39.495472 [CA 5] Center 32 (2~62) winsize 61
5032 04:50:39.495525
5033 04:50:39.495578 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5034 04:50:39.495631
5035 04:50:39.495683 [CATrainingPosCal] consider 1 rank data
5036 04:50:39.495737 u2DelayCellTimex100 = 270/100 ps
5037 04:50:39.495790 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5038 04:50:39.495844 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5039 04:50:39.495897 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5040 04:50:39.495951 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5041 04:50:39.496004 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5042 04:50:39.496057 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5043 04:50:39.496110
5044 04:50:39.496162 CA PerBit enable=1, Macro0, CA PI delay=32
5045 04:50:39.496216
5046 04:50:39.496269 [CBTSetCACLKResult] CA Dly = 32
5047 04:50:39.496372 CS Dly: 5 (0~36)
5048 04:50:39.496427 ==
5049 04:50:39.496481 Dram Type= 6, Freq= 0, CH_0, rank 1
5050 04:50:39.496536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5051 04:50:39.496619 ==
5052 04:50:39.496676 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5053 04:50:39.496731 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5054 04:50:39.496786 [CA 0] Center 37 (7~68) winsize 62
5055 04:50:39.496840 [CA 1] Center 37 (7~68) winsize 62
5056 04:50:39.496893 [CA 2] Center 34 (4~65) winsize 62
5057 04:50:39.496947 [CA 3] Center 34 (3~65) winsize 63
5058 04:50:39.497000 [CA 4] Center 33 (3~63) winsize 61
5059 04:50:39.497053 [CA 5] Center 32 (2~62) winsize 61
5060 04:50:39.497106
5061 04:50:39.497159 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5062 04:50:39.497213
5063 04:50:39.497266 [CATrainingPosCal] consider 2 rank data
5064 04:50:39.497319 u2DelayCellTimex100 = 270/100 ps
5065 04:50:39.497372 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5066 04:50:39.497429 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5067 04:50:39.497498 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5068 04:50:39.497553 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5069 04:50:39.497606 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5070 04:50:39.497660 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5071 04:50:39.497713
5072 04:50:39.497765 CA PerBit enable=1, Macro0, CA PI delay=32
5073 04:50:39.497819
5074 04:50:39.497871 [CBTSetCACLKResult] CA Dly = 32
5075 04:50:39.497925 CS Dly: 5 (0~37)
5076 04:50:39.497978
5077 04:50:39.498031 ----->DramcWriteLeveling(PI) begin...
5078 04:50:39.498086 ==
5079 04:50:39.498139 Dram Type= 6, Freq= 0, CH_0, rank 0
5080 04:50:39.498193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5081 04:50:39.498247 ==
5082 04:50:39.498300 Write leveling (Byte 0): 32 => 32
5083 04:50:39.498353 Write leveling (Byte 1): 30 => 30
5084 04:50:39.498407 DramcWriteLeveling(PI) end<-----
5085 04:50:39.498460
5086 04:50:39.498512 ==
5087 04:50:39.498565 Dram Type= 6, Freq= 0, CH_0, rank 0
5088 04:50:39.498619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5089 04:50:39.498673 ==
5090 04:50:39.498726 [Gating] SW mode calibration
5091 04:50:39.498981 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5092 04:50:39.499041 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5093 04:50:39.499097 0 14 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
5094 04:50:39.499152 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5095 04:50:39.499206 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5096 04:50:39.499260 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5097 04:50:39.499314 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5098 04:50:39.499367 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5099 04:50:39.499420 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5100 04:50:39.499474 0 14 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
5101 04:50:39.499527 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5102 04:50:39.499580 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5103 04:50:39.499633 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5104 04:50:39.499686 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 04:50:39.499739 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5106 04:50:39.499792 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5107 04:50:39.499868 0 15 24 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
5108 04:50:39.499929 0 15 28 | B1->B0 | 2626 3b3b | 0 0 | (0 0) (0 0)
5109 04:50:39.499983 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5110 04:50:39.500037 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5111 04:50:39.500091 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5112 04:50:39.500144 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 04:50:39.500198 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 04:50:39.500251 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5115 04:50:39.500335 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5116 04:50:39.500405 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5117 04:50:39.500459 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5118 04:50:39.500512 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 04:50:39.500566 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 04:50:39.500619 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 04:50:39.500673 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 04:50:39.500726 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 04:50:39.500779 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 04:50:39.500833 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 04:50:39.500886 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 04:50:39.500940 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 04:50:39.500994 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 04:50:39.501047 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 04:50:39.501101 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 04:50:39.501154 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 04:50:39.501207 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5132 04:50:39.501260 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5133 04:50:39.501313 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 04:50:39.501366 Total UI for P1: 0, mck2ui 16
5135 04:50:39.501420 best dqsien dly found for B0: ( 1, 2, 26)
5136 04:50:39.501473 Total UI for P1: 0, mck2ui 16
5137 04:50:39.501527 best dqsien dly found for B1: ( 1, 2, 30)
5138 04:50:39.501581 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5139 04:50:39.501634 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5140 04:50:39.501687
5141 04:50:39.501740 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5142 04:50:39.501795 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5143 04:50:39.501848 [Gating] SW calibration Done
5144 04:50:39.501901 ==
5145 04:50:39.501955 Dram Type= 6, Freq= 0, CH_0, rank 0
5146 04:50:39.502009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5147 04:50:39.502064 ==
5148 04:50:39.502117 RX Vref Scan: 0
5149 04:50:39.502170
5150 04:50:39.502223 RX Vref 0 -> 0, step: 1
5151 04:50:39.502277
5152 04:50:39.502329 RX Delay -80 -> 252, step: 8
5153 04:50:39.502383 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5154 04:50:39.502437 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5155 04:50:39.502491 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5156 04:50:39.502545 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5157 04:50:39.502598 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5158 04:50:39.502651 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5159 04:50:39.502704 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5160 04:50:39.502758 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5161 04:50:39.502811 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5162 04:50:39.502865 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5163 04:50:39.502918 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5164 04:50:39.502972 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5165 04:50:39.503025 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5166 04:50:39.503079 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5167 04:50:39.503133 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5168 04:50:39.503186 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5169 04:50:39.503266 ==
5170 04:50:39.503325 Dram Type= 6, Freq= 0, CH_0, rank 0
5171 04:50:39.503379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5172 04:50:39.503433 ==
5173 04:50:39.503487 DQS Delay:
5174 04:50:39.503540 DQS0 = 0, DQS1 = 0
5175 04:50:39.503594 DQM Delay:
5176 04:50:39.503648 DQM0 = 103, DQM1 = 95
5177 04:50:39.503701 DQ Delay:
5178 04:50:39.503754 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5179 04:50:39.503808 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =111
5180 04:50:39.503861 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =91
5181 04:50:39.503915 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5182 04:50:39.503968
5183 04:50:39.504021
5184 04:50:39.504074 ==
5185 04:50:39.504127 Dram Type= 6, Freq= 0, CH_0, rank 0
5186 04:50:39.504180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5187 04:50:39.504246 ==
5188 04:50:39.504367
5189 04:50:39.504423
5190 04:50:39.504475 TX Vref Scan disable
5191 04:50:39.504529 == TX Byte 0 ==
5192 04:50:39.504582 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5193 04:50:39.504636 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5194 04:50:39.504689 == TX Byte 1 ==
5195 04:50:39.504742 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5196 04:50:39.504997 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5197 04:50:39.505057 ==
5198 04:50:39.505112 Dram Type= 6, Freq= 0, CH_0, rank 0
5199 04:50:39.505166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5200 04:50:39.505221 ==
5201 04:50:39.505274
5202 04:50:39.505326
5203 04:50:39.505379 TX Vref Scan disable
5204 04:50:39.505433 == TX Byte 0 ==
5205 04:50:39.505486 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5206 04:50:39.505540 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5207 04:50:39.505593 == TX Byte 1 ==
5208 04:50:39.505646 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5209 04:50:39.505709 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5210 04:50:39.505765
5211 04:50:39.505818 [DATLAT]
5212 04:50:39.505871 Freq=933, CH0 RK0
5213 04:50:39.505925
5214 04:50:39.505978 DATLAT Default: 0xd
5215 04:50:39.506031 0, 0xFFFF, sum = 0
5216 04:50:39.506087 1, 0xFFFF, sum = 0
5217 04:50:39.506141 2, 0xFFFF, sum = 0
5218 04:50:39.506196 3, 0xFFFF, sum = 0
5219 04:50:39.506250 4, 0xFFFF, sum = 0
5220 04:50:39.506305 5, 0xFFFF, sum = 0
5221 04:50:39.506359 6, 0xFFFF, sum = 0
5222 04:50:39.506413 7, 0xFFFF, sum = 0
5223 04:50:39.506466 8, 0xFFFF, sum = 0
5224 04:50:39.506520 9, 0xFFFF, sum = 0
5225 04:50:39.506574 10, 0x0, sum = 1
5226 04:50:39.506628 11, 0x0, sum = 2
5227 04:50:39.506692 12, 0x0, sum = 3
5228 04:50:39.506764 13, 0x0, sum = 4
5229 04:50:39.506820 best_step = 11
5230 04:50:39.506873
5231 04:50:39.506927 ==
5232 04:50:39.506980 Dram Type= 6, Freq= 0, CH_0, rank 0
5233 04:50:39.507034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5234 04:50:39.507089 ==
5235 04:50:39.507143 RX Vref Scan: 1
5236 04:50:39.507197
5237 04:50:39.507250 RX Vref 0 -> 0, step: 1
5238 04:50:39.507303
5239 04:50:39.507356 RX Delay -53 -> 252, step: 4
5240 04:50:39.507409
5241 04:50:39.507462 Set Vref, RX VrefLevel [Byte0]: 56
5242 04:50:39.507516 [Byte1]: 46
5243 04:50:39.507569
5244 04:50:39.507621 Final RX Vref Byte 0 = 56 to rank0
5245 04:50:39.507675 Final RX Vref Byte 1 = 46 to rank0
5246 04:50:39.507728 Final RX Vref Byte 0 = 56 to rank1
5247 04:50:39.507782 Final RX Vref Byte 1 = 46 to rank1==
5248 04:50:39.507835 Dram Type= 6, Freq= 0, CH_0, rank 0
5249 04:50:39.507889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5250 04:50:39.507942 ==
5251 04:50:39.507996 DQS Delay:
5252 04:50:39.508048 DQS0 = 0, DQS1 = 0
5253 04:50:39.508101 DQM Delay:
5254 04:50:39.508154 DQM0 = 104, DQM1 = 94
5255 04:50:39.508208 DQ Delay:
5256 04:50:39.508261 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5257 04:50:39.508374 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =110
5258 04:50:39.508461 DQ8 =84, DQ9 =84, DQ10 =96, DQ11 =88
5259 04:50:39.508530 DQ12 =100, DQ13 =98, DQ14 =104, DQ15 =102
5260 04:50:39.508586
5261 04:50:39.508640
5262 04:50:39.508694 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f27, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 407 ps
5263 04:50:39.508749 CH0 RK0: MR19=505, MR18=2F27
5264 04:50:39.508803 CH0_RK0: MR19=0x505, MR18=0x2F27, DQSOSC=407, MR23=63, INC=65, DEC=43
5265 04:50:39.508856
5266 04:50:39.508910 ----->DramcWriteLeveling(PI) begin...
5267 04:50:39.508965 ==
5268 04:50:39.509019 Dram Type= 6, Freq= 0, CH_0, rank 1
5269 04:50:39.509072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5270 04:50:39.509126 ==
5271 04:50:39.509179 Write leveling (Byte 0): 30 => 30
5272 04:50:39.509232 Write leveling (Byte 1): 29 => 29
5273 04:50:39.509286 DramcWriteLeveling(PI) end<-----
5274 04:50:39.509338
5275 04:50:39.509391 ==
5276 04:50:39.509444 Dram Type= 6, Freq= 0, CH_0, rank 1
5277 04:50:39.509498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 04:50:39.509551 ==
5279 04:50:39.509604 [Gating] SW mode calibration
5280 04:50:39.509658 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5281 04:50:39.509713 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5282 04:50:39.509767 0 14 0 | B1->B0 | 3434 3232 | 0 0 | (0 0) (1 1)
5283 04:50:39.509820 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5284 04:50:39.509874 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5285 04:50:39.509977 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5286 04:50:39.510040 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5287 04:50:39.510094 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5288 04:50:39.510148 0 14 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5289 04:50:39.510201 0 14 28 | B1->B0 | 2727 2c2c | 0 0 | (0 0) (0 0)
5290 04:50:39.510254 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 0)
5291 04:50:39.510307 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5292 04:50:39.510360 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5293 04:50:39.510413 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5294 04:50:39.510466 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5295 04:50:39.510519 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5296 04:50:39.510572 0 15 24 | B1->B0 | 2727 2626 | 0 0 | (0 0) (0 0)
5297 04:50:39.510625 0 15 28 | B1->B0 | 3d3d 3535 | 0 0 | (1 1) (1 1)
5298 04:50:39.510677 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5299 04:50:39.510729 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5300 04:50:39.510781 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5301 04:50:39.510834 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5302 04:50:39.510887 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5303 04:50:39.510939 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5304 04:50:39.510991 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5305 04:50:39.511044 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5306 04:50:39.511097 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5307 04:50:39.511149 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 04:50:39.511202 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 04:50:39.511254 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 04:50:39.511307 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 04:50:39.511359 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 04:50:39.511412 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 04:50:39.511464 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 04:50:39.511517 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 04:50:39.511569 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 04:50:39.511621 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 04:50:39.511674 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 04:50:39.511727 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 04:50:39.511779 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 04:50:39.512029 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 04:50:39.512093 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5322 04:50:39.512148 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 04:50:39.512201 Total UI for P1: 0, mck2ui 16
5324 04:50:39.512255 best dqsien dly found for B0: ( 1, 2, 28)
5325 04:50:39.512351 Total UI for P1: 0, mck2ui 16
5326 04:50:39.512406 best dqsien dly found for B1: ( 1, 2, 30)
5327 04:50:39.512458 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5328 04:50:39.512512 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5329 04:50:39.512565
5330 04:50:39.512618 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5331 04:50:39.512671 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5332 04:50:39.512724 [Gating] SW calibration Done
5333 04:50:39.512777 ==
5334 04:50:39.512829 Dram Type= 6, Freq= 0, CH_0, rank 1
5335 04:50:39.512882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5336 04:50:39.512935 ==
5337 04:50:39.512988 RX Vref Scan: 0
5338 04:50:39.513040
5339 04:50:39.513093 RX Vref 0 -> 0, step: 1
5340 04:50:39.513146
5341 04:50:39.513256 RX Delay -80 -> 252, step: 8
5342 04:50:39.513308 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5343 04:50:39.513396 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5344 04:50:39.513452 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5345 04:50:39.513506 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5346 04:50:39.513559 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5347 04:50:39.513613 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5348 04:50:39.513666 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5349 04:50:39.513719 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5350 04:50:39.513772 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5351 04:50:39.513824 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5352 04:50:39.513877 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5353 04:50:39.513929 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5354 04:50:39.513982 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5355 04:50:39.514035 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5356 04:50:39.514088 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5357 04:50:39.514141 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5358 04:50:39.514194 ==
5359 04:50:39.514247 Dram Type= 6, Freq= 0, CH_0, rank 1
5360 04:50:39.514300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5361 04:50:39.514353 ==
5362 04:50:39.514406 DQS Delay:
5363 04:50:39.514459 DQS0 = 0, DQS1 = 0
5364 04:50:39.514512 DQM Delay:
5365 04:50:39.514564 DQM0 = 105, DQM1 = 94
5366 04:50:39.514617 DQ Delay:
5367 04:50:39.514670 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =99
5368 04:50:39.514724 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5369 04:50:39.514777 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5370 04:50:39.514830 DQ12 =95, DQ13 =103, DQ14 =103, DQ15 =99
5371 04:50:39.514883
5372 04:50:39.514935
5373 04:50:39.514987 ==
5374 04:50:39.515040 Dram Type= 6, Freq= 0, CH_0, rank 1
5375 04:50:39.515093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5376 04:50:39.515146 ==
5377 04:50:39.515199
5378 04:50:39.515251
5379 04:50:39.515321 TX Vref Scan disable
5380 04:50:39.516798 == TX Byte 0 ==
5381 04:50:39.520058 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5382 04:50:39.523161 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5383 04:50:39.526700 == TX Byte 1 ==
5384 04:50:39.530024 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5385 04:50:39.533271 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5386 04:50:39.533360 ==
5387 04:50:39.536626 Dram Type= 6, Freq= 0, CH_0, rank 1
5388 04:50:39.543016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5389 04:50:39.543119 ==
5390 04:50:39.543186
5391 04:50:39.543246
5392 04:50:39.543303 TX Vref Scan disable
5393 04:50:39.547037 == TX Byte 0 ==
5394 04:50:39.550337 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5395 04:50:39.554181 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5396 04:50:39.557174 == TX Byte 1 ==
5397 04:50:39.560764 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5398 04:50:39.563852 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5399 04:50:39.567556
5400 04:50:39.567649 [DATLAT]
5401 04:50:39.567713 Freq=933, CH0 RK1
5402 04:50:39.567773
5403 04:50:39.570331 DATLAT Default: 0xb
5404 04:50:39.570413 0, 0xFFFF, sum = 0
5405 04:50:39.573805 1, 0xFFFF, sum = 0
5406 04:50:39.573891 2, 0xFFFF, sum = 0
5407 04:50:39.577036 3, 0xFFFF, sum = 0
5408 04:50:39.577130 4, 0xFFFF, sum = 0
5409 04:50:39.580183 5, 0xFFFF, sum = 0
5410 04:50:39.583559 6, 0xFFFF, sum = 0
5411 04:50:39.583644 7, 0xFFFF, sum = 0
5412 04:50:39.587436 8, 0xFFFF, sum = 0
5413 04:50:39.587511 9, 0xFFFF, sum = 0
5414 04:50:39.590150 10, 0x0, sum = 1
5415 04:50:39.590235 11, 0x0, sum = 2
5416 04:50:39.590298 12, 0x0, sum = 3
5417 04:50:39.593520 13, 0x0, sum = 4
5418 04:50:39.593607 best_step = 11
5419 04:50:39.593679
5420 04:50:39.596802 ==
5421 04:50:39.596886 Dram Type= 6, Freq= 0, CH_0, rank 1
5422 04:50:39.603836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5423 04:50:39.603944 ==
5424 04:50:39.604010 RX Vref Scan: 0
5425 04:50:39.604085
5426 04:50:39.607148 RX Vref 0 -> 0, step: 1
5427 04:50:39.607231
5428 04:50:39.610615 RX Delay -45 -> 252, step: 4
5429 04:50:39.614000 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5430 04:50:39.620614 iDelay=199, Bit 1, Center 106 (23 ~ 190) 168
5431 04:50:39.624115 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5432 04:50:39.627467 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5433 04:50:39.630755 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5434 04:50:39.634155 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5435 04:50:39.637167 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5436 04:50:39.643713 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5437 04:50:39.646908 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5438 04:50:39.650187 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5439 04:50:39.653467 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5440 04:50:39.657087 iDelay=199, Bit 11, Center 86 (3 ~ 170) 168
5441 04:50:39.663704 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5442 04:50:39.666765 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5443 04:50:39.670567 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5444 04:50:39.673792 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5445 04:50:39.673884 ==
5446 04:50:39.677145 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 04:50:39.680252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 04:50:39.684067 ==
5449 04:50:39.684153 DQS Delay:
5450 04:50:39.684218 DQS0 = 0, DQS1 = 0
5451 04:50:39.687043 DQM Delay:
5452 04:50:39.687128 DQM0 = 104, DQM1 = 93
5453 04:50:39.690488 DQ Delay:
5454 04:50:39.694117 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102
5455 04:50:39.697402 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5456 04:50:39.700456 DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =86
5457 04:50:39.703889 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102
5458 04:50:39.703976
5459 04:50:39.704041
5460 04:50:39.710447 [DQSOSCAuto] RK1, (LSB)MR18= 0x2700, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 409 ps
5461 04:50:39.713763 CH0 RK1: MR19=505, MR18=2700
5462 04:50:39.720530 CH0_RK1: MR19=0x505, MR18=0x2700, DQSOSC=409, MR23=63, INC=64, DEC=43
5463 04:50:39.723904 [RxdqsGatingPostProcess] freq 933
5464 04:50:39.729953 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5465 04:50:39.730091 best DQS0 dly(2T, 0.5T) = (0, 10)
5466 04:50:39.733403 best DQS1 dly(2T, 0.5T) = (0, 10)
5467 04:50:39.736855 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5468 04:50:39.740077 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5469 04:50:39.743507 best DQS0 dly(2T, 0.5T) = (0, 10)
5470 04:50:39.746803 best DQS1 dly(2T, 0.5T) = (0, 10)
5471 04:50:39.750254 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5472 04:50:39.753430 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5473 04:50:39.756661 Pre-setting of DQS Precalculation
5474 04:50:39.760307 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5475 04:50:39.763508 ==
5476 04:50:39.766808 Dram Type= 6, Freq= 0, CH_1, rank 0
5477 04:50:39.770089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5478 04:50:39.770189 ==
5479 04:50:39.773376 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5480 04:50:39.779846 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5481 04:50:39.783714 [CA 0] Center 36 (6~67) winsize 62
5482 04:50:39.786965 [CA 1] Center 36 (6~67) winsize 62
5483 04:50:39.790595 [CA 2] Center 34 (4~65) winsize 62
5484 04:50:39.793365 [CA 3] Center 34 (4~64) winsize 61
5485 04:50:39.797113 [CA 4] Center 34 (4~64) winsize 61
5486 04:50:39.800219 [CA 5] Center 33 (3~64) winsize 62
5487 04:50:39.800355
5488 04:50:39.803429 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5489 04:50:39.803513
5490 04:50:39.806938 [CATrainingPosCal] consider 1 rank data
5491 04:50:39.810110 u2DelayCellTimex100 = 270/100 ps
5492 04:50:39.813798 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5493 04:50:39.816754 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5494 04:50:39.823937 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5495 04:50:39.826684 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5496 04:50:39.830128 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5497 04:50:39.833417 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5498 04:50:39.833511
5499 04:50:39.836908 CA PerBit enable=1, Macro0, CA PI delay=33
5500 04:50:39.836994
5501 04:50:39.840217 [CBTSetCACLKResult] CA Dly = 33
5502 04:50:39.840361 CS Dly: 7 (0~38)
5503 04:50:39.843586 ==
5504 04:50:39.846940 Dram Type= 6, Freq= 0, CH_1, rank 1
5505 04:50:39.850343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5506 04:50:39.850439 ==
5507 04:50:39.853753 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5508 04:50:39.859930 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5509 04:50:39.863943 [CA 0] Center 36 (6~67) winsize 62
5510 04:50:39.867464 [CA 1] Center 37 (6~68) winsize 63
5511 04:50:39.870720 [CA 2] Center 35 (5~65) winsize 61
5512 04:50:39.873935 [CA 3] Center 34 (4~65) winsize 62
5513 04:50:39.877076 [CA 4] Center 34 (4~65) winsize 62
5514 04:50:39.880231 [CA 5] Center 33 (3~64) winsize 62
5515 04:50:39.880375
5516 04:50:39.883654 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5517 04:50:39.883739
5518 04:50:39.886831 [CATrainingPosCal] consider 2 rank data
5519 04:50:39.890437 u2DelayCellTimex100 = 270/100 ps
5520 04:50:39.893533 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5521 04:50:39.896637 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5522 04:50:39.903479 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5523 04:50:39.906634 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5524 04:50:39.910208 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5525 04:50:39.913527 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5526 04:50:39.913621
5527 04:50:39.916571 CA PerBit enable=1, Macro0, CA PI delay=33
5528 04:50:39.916657
5529 04:50:39.920069 [CBTSetCACLKResult] CA Dly = 33
5530 04:50:39.920155 CS Dly: 7 (0~39)
5531 04:50:39.923387
5532 04:50:39.926446 ----->DramcWriteLeveling(PI) begin...
5533 04:50:39.926539 ==
5534 04:50:39.929747 Dram Type= 6, Freq= 0, CH_1, rank 0
5535 04:50:39.933298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5536 04:50:39.933390 ==
5537 04:50:39.936165 Write leveling (Byte 0): 27 => 27
5538 04:50:39.939509 Write leveling (Byte 1): 29 => 29
5539 04:50:39.943144 DramcWriteLeveling(PI) end<-----
5540 04:50:39.943251
5541 04:50:39.943321 ==
5542 04:50:39.946564 Dram Type= 6, Freq= 0, CH_1, rank 0
5543 04:50:39.949866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5544 04:50:39.949956 ==
5545 04:50:39.953127 [Gating] SW mode calibration
5546 04:50:39.959961 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5547 04:50:39.966595 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5548 04:50:39.970021 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5549 04:50:39.973548 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5550 04:50:39.979589 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5551 04:50:39.983426 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5552 04:50:39.986573 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5553 04:50:39.993450 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5554 04:50:39.996685 0 14 24 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (0 1)
5555 04:50:39.999725 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (1 1) (0 0)
5556 04:50:40.003439 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5557 04:50:40.010133 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5558 04:50:40.013391 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 04:50:40.016493 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 04:50:40.023231 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5561 04:50:40.026509 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5562 04:50:40.030091 0 15 24 | B1->B0 | 2828 3333 | 0 0 | (0 0) (0 0)
5563 04:50:40.036129 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5564 04:50:40.039990 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5565 04:50:40.043522 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 04:50:40.049863 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 04:50:40.052954 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 04:50:40.056324 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 04:50:40.063257 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 04:50:40.066667 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5571 04:50:40.070062 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 04:50:40.076214 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 04:50:40.079588 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 04:50:40.082980 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 04:50:40.089614 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 04:50:40.092711 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 04:50:40.096038 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 04:50:40.103250 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 04:50:40.106336 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 04:50:40.109367 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 04:50:40.112567 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 04:50:40.119254 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 04:50:40.122562 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 04:50:40.125849 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 04:50:40.132941 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 04:50:40.136121 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5587 04:50:40.139276 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5588 04:50:40.146249 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 04:50:40.149347 Total UI for P1: 0, mck2ui 16
5590 04:50:40.153092 best dqsien dly found for B0: ( 1, 2, 26)
5591 04:50:40.156214 Total UI for P1: 0, mck2ui 16
5592 04:50:40.159680 best dqsien dly found for B1: ( 1, 2, 26)
5593 04:50:40.162418 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5594 04:50:40.166152 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5595 04:50:40.166246
5596 04:50:40.169486 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5597 04:50:40.172251 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5598 04:50:40.175804 [Gating] SW calibration Done
5599 04:50:40.175891 ==
5600 04:50:40.179413 Dram Type= 6, Freq= 0, CH_1, rank 0
5601 04:50:40.182816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5602 04:50:40.182904 ==
5603 04:50:40.186251 RX Vref Scan: 0
5604 04:50:40.186335
5605 04:50:40.186399 RX Vref 0 -> 0, step: 1
5606 04:50:40.189588
5607 04:50:40.189672 RX Delay -80 -> 252, step: 8
5608 04:50:40.195804 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5609 04:50:40.198993 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5610 04:50:40.202347 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5611 04:50:40.205647 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5612 04:50:40.209064 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5613 04:50:40.212493 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5614 04:50:40.218872 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5615 04:50:40.222696 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5616 04:50:40.225771 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5617 04:50:40.229221 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5618 04:50:40.232490 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5619 04:50:40.235808 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5620 04:50:40.242547 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5621 04:50:40.245803 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5622 04:50:40.248545 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5623 04:50:40.252529 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5624 04:50:40.252623 ==
5625 04:50:40.255147 Dram Type= 6, Freq= 0, CH_1, rank 0
5626 04:50:40.262031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5627 04:50:40.262155 ==
5628 04:50:40.262226 DQS Delay:
5629 04:50:40.262290 DQS0 = 0, DQS1 = 0
5630 04:50:40.265244 DQM Delay:
5631 04:50:40.265334 DQM0 = 102, DQM1 = 98
5632 04:50:40.268761 DQ Delay:
5633 04:50:40.272060 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5634 04:50:40.275510 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5635 04:50:40.278786 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5636 04:50:40.282070 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5637 04:50:40.282162
5638 04:50:40.282228
5639 04:50:40.282288 ==
5640 04:50:40.285054 Dram Type= 6, Freq= 0, CH_1, rank 0
5641 04:50:40.288343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5642 04:50:40.288430 ==
5643 04:50:40.288497
5644 04:50:40.288557
5645 04:50:40.291935 TX Vref Scan disable
5646 04:50:40.295473 == TX Byte 0 ==
5647 04:50:40.298709 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5648 04:50:40.302077 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5649 04:50:40.305267 == TX Byte 1 ==
5650 04:50:40.308430 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5651 04:50:40.311831 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5652 04:50:40.311924 ==
5653 04:50:40.315137 Dram Type= 6, Freq= 0, CH_1, rank 0
5654 04:50:40.318464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5655 04:50:40.321818 ==
5656 04:50:40.321906
5657 04:50:40.321972
5658 04:50:40.322032 TX Vref Scan disable
5659 04:50:40.325627 == TX Byte 0 ==
5660 04:50:40.328723 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5661 04:50:40.335392 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5662 04:50:40.335501 == TX Byte 1 ==
5663 04:50:40.338891 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5664 04:50:40.345417 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5665 04:50:40.345524
5666 04:50:40.345601 [DATLAT]
5667 04:50:40.345670 Freq=933, CH1 RK0
5668 04:50:40.345730
5669 04:50:40.348633 DATLAT Default: 0xd
5670 04:50:40.348772 0, 0xFFFF, sum = 0
5671 04:50:40.351856 1, 0xFFFF, sum = 0
5672 04:50:40.351943 2, 0xFFFF, sum = 0
5673 04:50:40.355745 3, 0xFFFF, sum = 0
5674 04:50:40.358374 4, 0xFFFF, sum = 0
5675 04:50:40.358461 5, 0xFFFF, sum = 0
5676 04:50:40.361778 6, 0xFFFF, sum = 0
5677 04:50:40.361863 7, 0xFFFF, sum = 0
5678 04:50:40.365063 8, 0xFFFF, sum = 0
5679 04:50:40.365154 9, 0xFFFF, sum = 0
5680 04:50:40.368881 10, 0x0, sum = 1
5681 04:50:40.369003 11, 0x0, sum = 2
5682 04:50:40.372150 12, 0x0, sum = 3
5683 04:50:40.372271 13, 0x0, sum = 4
5684 04:50:40.372385 best_step = 11
5685 04:50:40.372448
5686 04:50:40.375091 ==
5687 04:50:40.378327 Dram Type= 6, Freq= 0, CH_1, rank 0
5688 04:50:40.381973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5689 04:50:40.382072 ==
5690 04:50:40.382140 RX Vref Scan: 1
5691 04:50:40.382202
5692 04:50:40.385100 RX Vref 0 -> 0, step: 1
5693 04:50:40.385188
5694 04:50:40.388541 RX Delay -45 -> 252, step: 4
5695 04:50:40.388628
5696 04:50:40.391728 Set Vref, RX VrefLevel [Byte0]: 55
5697 04:50:40.395138 [Byte1]: 48
5698 04:50:40.395245
5699 04:50:40.398467 Final RX Vref Byte 0 = 55 to rank0
5700 04:50:40.401917 Final RX Vref Byte 1 = 48 to rank0
5701 04:50:40.405212 Final RX Vref Byte 0 = 55 to rank1
5702 04:50:40.408151 Final RX Vref Byte 1 = 48 to rank1==
5703 04:50:40.411639 Dram Type= 6, Freq= 0, CH_1, rank 0
5704 04:50:40.415086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5705 04:50:40.418344 ==
5706 04:50:40.418442 DQS Delay:
5707 04:50:40.418510 DQS0 = 0, DQS1 = 0
5708 04:50:40.421866 DQM Delay:
5709 04:50:40.421955 DQM0 = 103, DQM1 = 98
5710 04:50:40.424732 DQ Delay:
5711 04:50:40.428585 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =100
5712 04:50:40.428686 DQ4 =102, DQ5 =112, DQ6 =114, DQ7 =104
5713 04:50:40.431812 DQ8 =86, DQ9 =90, DQ10 =98, DQ11 =94
5714 04:50:40.438384 DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =108
5715 04:50:40.438504
5716 04:50:40.438576
5717 04:50:40.445068 [DQSOSCAuto] RK0, (LSB)MR18= 0x162e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5718 04:50:40.448211 CH1 RK0: MR19=505, MR18=162E
5719 04:50:40.455418 CH1_RK0: MR19=0x505, MR18=0x162E, DQSOSC=407, MR23=63, INC=65, DEC=43
5720 04:50:40.455554
5721 04:50:40.458520 ----->DramcWriteLeveling(PI) begin...
5722 04:50:40.458611 ==
5723 04:50:40.461868 Dram Type= 6, Freq= 0, CH_1, rank 1
5724 04:50:40.465137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 04:50:40.465231 ==
5726 04:50:40.468552 Write leveling (Byte 0): 28 => 28
5727 04:50:40.471804 Write leveling (Byte 1): 29 => 29
5728 04:50:40.475114 DramcWriteLeveling(PI) end<-----
5729 04:50:40.475210
5730 04:50:40.475278 ==
5731 04:50:40.478324 Dram Type= 6, Freq= 0, CH_1, rank 1
5732 04:50:40.481725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 04:50:40.481818 ==
5734 04:50:40.485023 [Gating] SW mode calibration
5735 04:50:40.491530 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5736 04:50:40.498407 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5737 04:50:40.501831 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5738 04:50:40.508454 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5739 04:50:40.511971 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5740 04:50:40.515317 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5741 04:50:40.521814 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5742 04:50:40.525159 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5743 04:50:40.528190 0 14 24 | B1->B0 | 2828 3232 | 0 1 | (0 0) (1 1)
5744 04:50:40.531958 0 14 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 0)
5745 04:50:40.538092 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5746 04:50:40.541597 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5747 04:50:40.544671 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5748 04:50:40.551718 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5749 04:50:40.555030 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5750 04:50:40.558027 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5751 04:50:40.564864 0 15 24 | B1->B0 | 3737 2d2c | 0 1 | (0 0) (0 0)
5752 04:50:40.568145 0 15 28 | B1->B0 | 4646 3b3b | 0 0 | (0 0) (0 0)
5753 04:50:40.571147 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5754 04:50:40.577759 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5755 04:50:40.581708 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5756 04:50:40.585026 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5757 04:50:40.591743 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5758 04:50:40.594506 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5759 04:50:40.597836 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5760 04:50:40.604712 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5761 04:50:40.607590 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 04:50:40.610897 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 04:50:40.617927 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 04:50:40.621190 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 04:50:40.624491 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 04:50:40.631292 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 04:50:40.634661 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 04:50:40.637934 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 04:50:40.643989 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 04:50:40.647223 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 04:50:40.650731 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 04:50:40.657653 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 04:50:40.660741 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 04:50:40.664257 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 04:50:40.670838 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5776 04:50:40.674203 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 04:50:40.677624 Total UI for P1: 0, mck2ui 16
5778 04:50:40.680888 best dqsien dly found for B0: ( 1, 2, 24)
5779 04:50:40.684262 Total UI for P1: 0, mck2ui 16
5780 04:50:40.687448 best dqsien dly found for B1: ( 1, 2, 24)
5781 04:50:40.691009 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5782 04:50:40.693958 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5783 04:50:40.694055
5784 04:50:40.697321 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5785 04:50:40.701035 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5786 04:50:40.704128 [Gating] SW calibration Done
5787 04:50:40.704220 ==
5788 04:50:40.707680 Dram Type= 6, Freq= 0, CH_1, rank 1
5789 04:50:40.711001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5790 04:50:40.711102 ==
5791 04:50:40.714181 RX Vref Scan: 0
5792 04:50:40.714298
5793 04:50:40.714389 RX Vref 0 -> 0, step: 1
5794 04:50:40.717888
5795 04:50:40.717976 RX Delay -80 -> 252, step: 8
5796 04:50:40.724240 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5797 04:50:40.727724 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5798 04:50:40.731005 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5799 04:50:40.734351 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5800 04:50:40.737180 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5801 04:50:40.740631 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5802 04:50:40.747419 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5803 04:50:40.750793 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5804 04:50:40.754154 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5805 04:50:40.757460 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5806 04:50:40.760663 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5807 04:50:40.764017 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5808 04:50:40.770818 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5809 04:50:40.774281 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5810 04:50:40.777468 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5811 04:50:40.780691 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5812 04:50:40.780790 ==
5813 04:50:40.783935 Dram Type= 6, Freq= 0, CH_1, rank 1
5814 04:50:40.790399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5815 04:50:40.790515 ==
5816 04:50:40.790586 DQS Delay:
5817 04:50:40.790647 DQS0 = 0, DQS1 = 0
5818 04:50:40.793634 DQM Delay:
5819 04:50:40.793738 DQM0 = 102, DQM1 = 98
5820 04:50:40.796896 DQ Delay:
5821 04:50:40.800113 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5822 04:50:40.804116 DQ4 =95, DQ5 =119, DQ6 =107, DQ7 =99
5823 04:50:40.807007 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5824 04:50:40.810158 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5825 04:50:40.810299
5826 04:50:40.810394
5827 04:50:40.810508 ==
5828 04:50:40.813566 Dram Type= 6, Freq= 0, CH_1, rank 1
5829 04:50:40.816669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5830 04:50:40.816767 ==
5831 04:50:40.816833
5832 04:50:40.816892
5833 04:50:40.820058 TX Vref Scan disable
5834 04:50:40.823462 == TX Byte 0 ==
5835 04:50:40.826780 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5836 04:50:40.830365 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5837 04:50:40.833684 == TX Byte 1 ==
5838 04:50:40.836939 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5839 04:50:40.840106 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5840 04:50:40.840240 ==
5841 04:50:40.843629 Dram Type= 6, Freq= 0, CH_1, rank 1
5842 04:50:40.846927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5843 04:50:40.847012 ==
5844 04:50:40.850361
5845 04:50:40.850453
5846 04:50:40.850518 TX Vref Scan disable
5847 04:50:40.853691 == TX Byte 0 ==
5848 04:50:40.857107 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5849 04:50:40.863748 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5850 04:50:40.863864 == TX Byte 1 ==
5851 04:50:40.867097 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5852 04:50:40.873553 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5853 04:50:40.873672
5854 04:50:40.873740 [DATLAT]
5855 04:50:40.873803 Freq=933, CH1 RK1
5856 04:50:40.873863
5857 04:50:40.876909 DATLAT Default: 0xb
5858 04:50:40.876994 0, 0xFFFF, sum = 0
5859 04:50:40.880141 1, 0xFFFF, sum = 0
5860 04:50:40.883487 2, 0xFFFF, sum = 0
5861 04:50:40.883603 3, 0xFFFF, sum = 0
5862 04:50:40.886745 4, 0xFFFF, sum = 0
5863 04:50:40.886835 5, 0xFFFF, sum = 0
5864 04:50:40.890014 6, 0xFFFF, sum = 0
5865 04:50:40.890100 7, 0xFFFF, sum = 0
5866 04:50:40.893201 8, 0xFFFF, sum = 0
5867 04:50:40.893295 9, 0xFFFF, sum = 0
5868 04:50:40.897114 10, 0x0, sum = 1
5869 04:50:40.897231 11, 0x0, sum = 2
5870 04:50:40.899832 12, 0x0, sum = 3
5871 04:50:40.899920 13, 0x0, sum = 4
5872 04:50:40.899988 best_step = 11
5873 04:50:40.900049
5874 04:50:40.903148 ==
5875 04:50:40.906454 Dram Type= 6, Freq= 0, CH_1, rank 1
5876 04:50:40.909833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5877 04:50:40.909931 ==
5878 04:50:40.909998 RX Vref Scan: 0
5879 04:50:40.910061
5880 04:50:40.913215 RX Vref 0 -> 0, step: 1
5881 04:50:40.913303
5882 04:50:40.916553 RX Delay -45 -> 252, step: 4
5883 04:50:40.923404 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5884 04:50:40.926357 iDelay=203, Bit 1, Center 100 (15 ~ 186) 172
5885 04:50:40.929659 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5886 04:50:40.932994 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5887 04:50:40.936267 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5888 04:50:40.939938 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5889 04:50:40.946188 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5890 04:50:40.950034 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5891 04:50:40.953277 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5892 04:50:40.956647 iDelay=203, Bit 9, Center 90 (7 ~ 174) 168
5893 04:50:40.959863 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5894 04:50:40.966660 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5895 04:50:40.970048 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5896 04:50:40.973234 iDelay=203, Bit 13, Center 104 (19 ~ 190) 172
5897 04:50:40.976276 iDelay=203, Bit 14, Center 106 (27 ~ 186) 160
5898 04:50:40.979626 iDelay=203, Bit 15, Center 110 (27 ~ 194) 168
5899 04:50:40.982996 ==
5900 04:50:40.983095 Dram Type= 6, Freq= 0, CH_1, rank 1
5901 04:50:40.989755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5902 04:50:40.989871 ==
5903 04:50:40.989957 DQS Delay:
5904 04:50:40.992770 DQS0 = 0, DQS1 = 0
5905 04:50:40.992860 DQM Delay:
5906 04:50:40.995904 DQM0 = 105, DQM1 = 100
5907 04:50:40.995993 DQ Delay:
5908 04:50:40.999934 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5909 04:50:41.003253 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5910 04:50:41.006646 DQ8 =90, DQ9 =90, DQ10 =100, DQ11 =94
5911 04:50:41.009664 DQ12 =108, DQ13 =104, DQ14 =106, DQ15 =110
5912 04:50:41.009760
5913 04:50:41.009827
5914 04:50:41.019908 [DQSOSCAuto] RK1, (LSB)MR18= 0x2afd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 408 ps
5915 04:50:41.020044 CH1 RK1: MR19=504, MR18=2AFD
5916 04:50:41.025940 CH1_RK1: MR19=0x504, MR18=0x2AFD, DQSOSC=408, MR23=63, INC=65, DEC=43
5917 04:50:41.029819 [RxdqsGatingPostProcess] freq 933
5918 04:50:41.035928 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5919 04:50:41.039589 best DQS0 dly(2T, 0.5T) = (0, 10)
5920 04:50:41.042850 best DQS1 dly(2T, 0.5T) = (0, 10)
5921 04:50:41.046087 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5922 04:50:41.049167 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5923 04:50:41.052514 best DQS0 dly(2T, 0.5T) = (0, 10)
5924 04:50:41.052612 best DQS1 dly(2T, 0.5T) = (0, 10)
5925 04:50:41.055880 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5926 04:50:41.059359 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5927 04:50:41.062695 Pre-setting of DQS Precalculation
5928 04:50:41.069674 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5929 04:50:41.075710 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5930 04:50:41.082634 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5931 04:50:41.082751
5932 04:50:41.082818
5933 04:50:41.085856 [Calibration Summary] 1866 Mbps
5934 04:50:41.089277 CH 0, Rank 0
5935 04:50:41.089366 SW Impedance : PASS
5936 04:50:41.092466 DUTY Scan : NO K
5937 04:50:41.092552 ZQ Calibration : PASS
5938 04:50:41.095580 Jitter Meter : NO K
5939 04:50:41.099363 CBT Training : PASS
5940 04:50:41.099456 Write leveling : PASS
5941 04:50:41.102572 RX DQS gating : PASS
5942 04:50:41.105599 RX DQ/DQS(RDDQC) : PASS
5943 04:50:41.105686 TX DQ/DQS : PASS
5944 04:50:41.108778 RX DATLAT : PASS
5945 04:50:41.112728 RX DQ/DQS(Engine): PASS
5946 04:50:41.112820 TX OE : NO K
5947 04:50:41.115562 All Pass.
5948 04:50:41.115647
5949 04:50:41.115712 CH 0, Rank 1
5950 04:50:41.118855 SW Impedance : PASS
5951 04:50:41.118939 DUTY Scan : NO K
5952 04:50:41.122175 ZQ Calibration : PASS
5953 04:50:41.125555 Jitter Meter : NO K
5954 04:50:41.125643 CBT Training : PASS
5955 04:50:41.128810 Write leveling : PASS
5956 04:50:41.132207 RX DQS gating : PASS
5957 04:50:41.132330 RX DQ/DQS(RDDQC) : PASS
5958 04:50:41.135661 TX DQ/DQS : PASS
5959 04:50:41.138768 RX DATLAT : PASS
5960 04:50:41.138855 RX DQ/DQS(Engine): PASS
5961 04:50:41.141977 TX OE : NO K
5962 04:50:41.142063 All Pass.
5963 04:50:41.142129
5964 04:50:41.145556 CH 1, Rank 0
5965 04:50:41.145641 SW Impedance : PASS
5966 04:50:41.149150 DUTY Scan : NO K
5967 04:50:41.149238 ZQ Calibration : PASS
5968 04:50:41.152225 Jitter Meter : NO K
5969 04:50:41.155343 CBT Training : PASS
5970 04:50:41.155456 Write leveling : PASS
5971 04:50:41.158637 RX DQS gating : PASS
5972 04:50:41.162073 RX DQ/DQS(RDDQC) : PASS
5973 04:50:41.162163 TX DQ/DQS : PASS
5974 04:50:41.165359 RX DATLAT : PASS
5975 04:50:41.168721 RX DQ/DQS(Engine): PASS
5976 04:50:41.168807 TX OE : NO K
5977 04:50:41.172022 All Pass.
5978 04:50:41.172105
5979 04:50:41.172171 CH 1, Rank 1
5980 04:50:41.175371 SW Impedance : PASS
5981 04:50:41.175455 DUTY Scan : NO K
5982 04:50:41.178749 ZQ Calibration : PASS
5983 04:50:41.182104 Jitter Meter : NO K
5984 04:50:41.182191 CBT Training : PASS
5985 04:50:41.185303 Write leveling : PASS
5986 04:50:41.188344 RX DQS gating : PASS
5987 04:50:41.188430 RX DQ/DQS(RDDQC) : PASS
5988 04:50:41.192110 TX DQ/DQS : PASS
5989 04:50:41.194935 RX DATLAT : PASS
5990 04:50:41.195020 RX DQ/DQS(Engine): PASS
5991 04:50:41.198502 TX OE : NO K
5992 04:50:41.198590 All Pass.
5993 04:50:41.198656
5994 04:50:41.201917 DramC Write-DBI off
5995 04:50:41.204924 PER_BANK_REFRESH: Hybrid Mode
5996 04:50:41.205010 TX_TRACKING: ON
5997 04:50:41.215075 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5998 04:50:41.218662 [FAST_K] Save calibration result to emmc
5999 04:50:41.222224 dramc_set_vcore_voltage set vcore to 650000
6000 04:50:41.225385 Read voltage for 400, 6
6001 04:50:41.225478 Vio18 = 0
6002 04:50:41.225545 Vcore = 650000
6003 04:50:41.225606 Vdram = 0
6004 04:50:41.228546 Vddq = 0
6005 04:50:41.228657 Vmddr = 0
6006 04:50:41.235541 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6007 04:50:41.238263 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6008 04:50:41.241590 MEM_TYPE=3, freq_sel=20
6009 04:50:41.245049 sv_algorithm_assistance_LP4_800
6010 04:50:41.248394 ============ PULL DRAM RESETB DOWN ============
6011 04:50:41.251865 ========== PULL DRAM RESETB DOWN end =========
6012 04:50:41.258322 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6013 04:50:41.261951 ===================================
6014 04:50:41.262052 LPDDR4 DRAM CONFIGURATION
6015 04:50:41.265472 ===================================
6016 04:50:41.268742 EX_ROW_EN[0] = 0x0
6017 04:50:41.268836 EX_ROW_EN[1] = 0x0
6018 04:50:41.272162 LP4Y_EN = 0x0
6019 04:50:41.272274 WORK_FSP = 0x0
6020 04:50:41.274899 WL = 0x2
6021 04:50:41.278329 RL = 0x2
6022 04:50:41.278418 BL = 0x2
6023 04:50:41.281653 RPST = 0x0
6024 04:50:41.281740 RD_PRE = 0x0
6025 04:50:41.285147 WR_PRE = 0x1
6026 04:50:41.285235 WR_PST = 0x0
6027 04:50:41.288592 DBI_WR = 0x0
6028 04:50:41.288679 DBI_RD = 0x0
6029 04:50:41.291863 OTF = 0x1
6030 04:50:41.295324 ===================================
6031 04:50:41.298527 ===================================
6032 04:50:41.298619 ANA top config
6033 04:50:41.301707 ===================================
6034 04:50:41.304868 DLL_ASYNC_EN = 0
6035 04:50:41.308210 ALL_SLAVE_EN = 1
6036 04:50:41.308366 NEW_RANK_MODE = 1
6037 04:50:41.311647 DLL_IDLE_MODE = 1
6038 04:50:41.314846 LP45_APHY_COMB_EN = 1
6039 04:50:41.317917 TX_ODT_DIS = 1
6040 04:50:41.321423 NEW_8X_MODE = 1
6041 04:50:41.324655 ===================================
6042 04:50:41.327828 ===================================
6043 04:50:41.327921 data_rate = 800
6044 04:50:41.331505 CKR = 1
6045 04:50:41.334527 DQ_P2S_RATIO = 4
6046 04:50:41.338157 ===================================
6047 04:50:41.341654 CA_P2S_RATIO = 4
6048 04:50:41.344332 DQ_CA_OPEN = 0
6049 04:50:41.347873 DQ_SEMI_OPEN = 1
6050 04:50:41.348015 CA_SEMI_OPEN = 1
6051 04:50:41.351163 CA_FULL_RATE = 0
6052 04:50:41.354474 DQ_CKDIV4_EN = 0
6053 04:50:41.357878 CA_CKDIV4_EN = 1
6054 04:50:41.360849 CA_PREDIV_EN = 0
6055 04:50:41.364634 PH8_DLY = 0
6056 04:50:41.364742 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6057 04:50:41.367758 DQ_AAMCK_DIV = 0
6058 04:50:41.370923 CA_AAMCK_DIV = 0
6059 04:50:41.374661 CA_ADMCK_DIV = 4
6060 04:50:41.377761 DQ_TRACK_CA_EN = 0
6061 04:50:41.381105 CA_PICK = 800
6062 04:50:41.384312 CA_MCKIO = 400
6063 04:50:41.384419 MCKIO_SEMI = 400
6064 04:50:41.387745 PLL_FREQ = 3016
6065 04:50:41.391124 DQ_UI_PI_RATIO = 32
6066 04:50:41.394454 CA_UI_PI_RATIO = 32
6067 04:50:41.397816 ===================================
6068 04:50:41.401095 ===================================
6069 04:50:41.404209 memory_type:LPDDR4
6070 04:50:41.404363 GP_NUM : 10
6071 04:50:41.407917 SRAM_EN : 1
6072 04:50:41.411164 MD32_EN : 0
6073 04:50:41.414626 ===================================
6074 04:50:41.414720 [ANA_INIT] >>>>>>>>>>>>>>
6075 04:50:41.417377 <<<<<< [CONFIGURE PHASE]: ANA_TX
6076 04:50:41.420789 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6077 04:50:41.423923 ===================================
6078 04:50:41.427726 data_rate = 800,PCW = 0X7400
6079 04:50:41.430812 ===================================
6080 04:50:41.434435 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6081 04:50:41.440461 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6082 04:50:41.450503 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6083 04:50:41.453851 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6084 04:50:41.460794 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6085 04:50:41.464240 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6086 04:50:41.464375 [ANA_INIT] flow start
6087 04:50:41.467137 [ANA_INIT] PLL >>>>>>>>
6088 04:50:41.470630 [ANA_INIT] PLL <<<<<<<<
6089 04:50:41.470721 [ANA_INIT] MIDPI >>>>>>>>
6090 04:50:41.474331 [ANA_INIT] MIDPI <<<<<<<<
6091 04:50:41.477535 [ANA_INIT] DLL >>>>>>>>
6092 04:50:41.477624 [ANA_INIT] flow end
6093 04:50:41.480508 ============ LP4 DIFF to SE enter ============
6094 04:50:41.487027 ============ LP4 DIFF to SE exit ============
6095 04:50:41.487129 [ANA_INIT] <<<<<<<<<<<<<
6096 04:50:41.490257 [Flow] Enable top DCM control >>>>>
6097 04:50:41.494202 [Flow] Enable top DCM control <<<<<
6098 04:50:41.497282 Enable DLL master slave shuffle
6099 04:50:41.504222 ==============================================================
6100 04:50:41.504398 Gating Mode config
6101 04:50:41.510296 ==============================================================
6102 04:50:41.514042 Config description:
6103 04:50:41.523988 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6104 04:50:41.530647 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6105 04:50:41.533911 SELPH_MODE 0: By rank 1: By Phase
6106 04:50:41.540430 ==============================================================
6107 04:50:41.543486 GAT_TRACK_EN = 0
6108 04:50:41.547099 RX_GATING_MODE = 2
6109 04:50:41.547197 RX_GATING_TRACK_MODE = 2
6110 04:50:41.550295 SELPH_MODE = 1
6111 04:50:41.553701 PICG_EARLY_EN = 1
6112 04:50:41.556878 VALID_LAT_VALUE = 1
6113 04:50:41.563624 ==============================================================
6114 04:50:41.566954 Enter into Gating configuration >>>>
6115 04:50:41.570201 Exit from Gating configuration <<<<
6116 04:50:41.573988 Enter into DVFS_PRE_config >>>>>
6117 04:50:41.583659 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6118 04:50:41.586827 Exit from DVFS_PRE_config <<<<<
6119 04:50:41.590201 Enter into PICG configuration >>>>
6120 04:50:41.593880 Exit from PICG configuration <<<<
6121 04:50:41.596968 [RX_INPUT] configuration >>>>>
6122 04:50:41.600093 [RX_INPUT] configuration <<<<<
6123 04:50:41.603779 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6124 04:50:41.610428 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6125 04:50:41.616876 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6126 04:50:41.619977 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6127 04:50:41.626552 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6128 04:50:41.633239 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6129 04:50:41.636587 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6130 04:50:41.643426 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6131 04:50:41.646837 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6132 04:50:41.650042 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6133 04:50:41.653797 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6134 04:50:41.660252 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6135 04:50:41.663328 ===================================
6136 04:50:41.663424 LPDDR4 DRAM CONFIGURATION
6137 04:50:41.666654 ===================================
6138 04:50:41.669929 EX_ROW_EN[0] = 0x0
6139 04:50:41.673124 EX_ROW_EN[1] = 0x0
6140 04:50:41.673210 LP4Y_EN = 0x0
6141 04:50:41.676515 WORK_FSP = 0x0
6142 04:50:41.676621 WL = 0x2
6143 04:50:41.680299 RL = 0x2
6144 04:50:41.680440 BL = 0x2
6145 04:50:41.683332 RPST = 0x0
6146 04:50:41.683415 RD_PRE = 0x0
6147 04:50:41.686582 WR_PRE = 0x1
6148 04:50:41.686666 WR_PST = 0x0
6149 04:50:41.689833 DBI_WR = 0x0
6150 04:50:41.689917 DBI_RD = 0x0
6151 04:50:41.693216 OTF = 0x1
6152 04:50:41.696478 ===================================
6153 04:50:41.699751 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6154 04:50:41.703463 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6155 04:50:41.710201 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6156 04:50:41.713602 ===================================
6157 04:50:41.713696 LPDDR4 DRAM CONFIGURATION
6158 04:50:41.716970 ===================================
6159 04:50:41.720271 EX_ROW_EN[0] = 0x10
6160 04:50:41.720407 EX_ROW_EN[1] = 0x0
6161 04:50:41.723506 LP4Y_EN = 0x0
6162 04:50:41.723589 WORK_FSP = 0x0
6163 04:50:41.726564 WL = 0x2
6164 04:50:41.726649 RL = 0x2
6165 04:50:41.730119 BL = 0x2
6166 04:50:41.733567 RPST = 0x0
6167 04:50:41.733691 RD_PRE = 0x0
6168 04:50:41.736774 WR_PRE = 0x1
6169 04:50:41.736857 WR_PST = 0x0
6170 04:50:41.740180 DBI_WR = 0x0
6171 04:50:41.740263 DBI_RD = 0x0
6172 04:50:41.743352 OTF = 0x1
6173 04:50:41.746729 ===================================
6174 04:50:41.753111 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6175 04:50:41.756599 nWR fixed to 30
6176 04:50:41.756695 [ModeRegInit_LP4] CH0 RK0
6177 04:50:41.759906 [ModeRegInit_LP4] CH0 RK1
6178 04:50:41.763116 [ModeRegInit_LP4] CH1 RK0
6179 04:50:41.763198 [ModeRegInit_LP4] CH1 RK1
6180 04:50:41.766273 match AC timing 19
6181 04:50:41.769500 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6182 04:50:41.773134 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6183 04:50:41.779560 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6184 04:50:41.782897 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6185 04:50:41.789912 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6186 04:50:41.789998 ==
6187 04:50:41.792914 Dram Type= 6, Freq= 0, CH_0, rank 0
6188 04:50:41.795934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6189 04:50:41.796015 ==
6190 04:50:41.803173 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6191 04:50:41.806261 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6192 04:50:41.809484 [CA 0] Center 36 (8~64) winsize 57
6193 04:50:41.812778 [CA 1] Center 36 (8~64) winsize 57
6194 04:50:41.816032 [CA 2] Center 36 (8~64) winsize 57
6195 04:50:41.819298 [CA 3] Center 36 (8~64) winsize 57
6196 04:50:41.822720 [CA 4] Center 36 (8~64) winsize 57
6197 04:50:41.825982 [CA 5] Center 36 (8~64) winsize 57
6198 04:50:41.826059
6199 04:50:41.829426 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6200 04:50:41.829499
6201 04:50:41.832795 [CATrainingPosCal] consider 1 rank data
6202 04:50:41.836213 u2DelayCellTimex100 = 270/100 ps
6203 04:50:41.839429 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6204 04:50:41.842857 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6205 04:50:41.848964 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6206 04:50:41.852429 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6207 04:50:41.855829 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6208 04:50:41.859231 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6209 04:50:41.859312
6210 04:50:41.862309 CA PerBit enable=1, Macro0, CA PI delay=36
6211 04:50:41.862390
6212 04:50:41.866193 [CBTSetCACLKResult] CA Dly = 36
6213 04:50:41.866274 CS Dly: 1 (0~32)
6214 04:50:41.869277 ==
6215 04:50:41.869358 Dram Type= 6, Freq= 0, CH_0, rank 1
6216 04:50:41.875464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6217 04:50:41.875546 ==
6218 04:50:41.879350 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6219 04:50:41.885583 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6220 04:50:41.889132 [CA 0] Center 36 (8~64) winsize 57
6221 04:50:41.892448 [CA 1] Center 36 (8~64) winsize 57
6222 04:50:41.895678 [CA 2] Center 36 (8~64) winsize 57
6223 04:50:41.898879 [CA 3] Center 36 (8~64) winsize 57
6224 04:50:41.902526 [CA 4] Center 36 (8~64) winsize 57
6225 04:50:41.905660 [CA 5] Center 36 (8~64) winsize 57
6226 04:50:41.905740
6227 04:50:41.908846 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6228 04:50:41.908927
6229 04:50:41.912109 [CATrainingPosCal] consider 2 rank data
6230 04:50:41.915801 u2DelayCellTimex100 = 270/100 ps
6231 04:50:41.919159 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 04:50:41.922491 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 04:50:41.925238 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 04:50:41.928556 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 04:50:41.931879 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 04:50:41.938849 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 04:50:41.938931
6238 04:50:41.941982 CA PerBit enable=1, Macro0, CA PI delay=36
6239 04:50:41.942064
6240 04:50:41.945298 [CBTSetCACLKResult] CA Dly = 36
6241 04:50:41.945380 CS Dly: 1 (0~32)
6242 04:50:41.945445
6243 04:50:41.948692 ----->DramcWriteLeveling(PI) begin...
6244 04:50:41.948775 ==
6245 04:50:41.951997 Dram Type= 6, Freq= 0, CH_0, rank 0
6246 04:50:41.958490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6247 04:50:41.958575 ==
6248 04:50:41.961676 Write leveling (Byte 0): 40 => 8
6249 04:50:41.961790 Write leveling (Byte 1): 40 => 8
6250 04:50:41.964983 DramcWriteLeveling(PI) end<-----
6251 04:50:41.965083
6252 04:50:41.965147 ==
6253 04:50:41.968838 Dram Type= 6, Freq= 0, CH_0, rank 0
6254 04:50:41.975440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6255 04:50:41.975524 ==
6256 04:50:41.978725 [Gating] SW mode calibration
6257 04:50:41.985243 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6258 04:50:41.988500 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6259 04:50:41.995189 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6260 04:50:41.998626 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6261 04:50:42.001799 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6262 04:50:42.008598 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6263 04:50:42.012113 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6264 04:50:42.015328 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6265 04:50:42.021425 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6266 04:50:42.024982 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6267 04:50:42.027991 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6268 04:50:42.031483 Total UI for P1: 0, mck2ui 16
6269 04:50:42.034830 best dqsien dly found for B0: ( 0, 14, 24)
6270 04:50:42.038209 Total UI for P1: 0, mck2ui 16
6271 04:50:42.041518 best dqsien dly found for B1: ( 0, 14, 24)
6272 04:50:42.044890 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6273 04:50:42.048257 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6274 04:50:42.048380
6275 04:50:42.051541 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6276 04:50:42.058266 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6277 04:50:42.058350 [Gating] SW calibration Done
6278 04:50:42.058416 ==
6279 04:50:42.061580 Dram Type= 6, Freq= 0, CH_0, rank 0
6280 04:50:42.068184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6281 04:50:42.068300 ==
6282 04:50:42.068401 RX Vref Scan: 0
6283 04:50:42.068465
6284 04:50:42.071094 RX Vref 0 -> 0, step: 1
6285 04:50:42.071176
6286 04:50:42.074589 RX Delay -410 -> 252, step: 16
6287 04:50:42.077977 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6288 04:50:42.081288 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6289 04:50:42.088089 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6290 04:50:42.091489 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6291 04:50:42.094840 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6292 04:50:42.098113 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6293 04:50:42.104703 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6294 04:50:42.107839 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6295 04:50:42.111523 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6296 04:50:42.114919 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6297 04:50:42.121282 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6298 04:50:42.124791 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6299 04:50:42.127861 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6300 04:50:42.131510 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6301 04:50:42.138311 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6302 04:50:42.141406 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6303 04:50:42.141490 ==
6304 04:50:42.145067 Dram Type= 6, Freq= 0, CH_0, rank 0
6305 04:50:42.148340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6306 04:50:42.148422 ==
6307 04:50:42.151196 DQS Delay:
6308 04:50:42.151276 DQS0 = 27, DQS1 = 35
6309 04:50:42.151339 DQM Delay:
6310 04:50:42.154503 DQM0 = 10, DQM1 = 11
6311 04:50:42.154585 DQ Delay:
6312 04:50:42.158419 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6313 04:50:42.161143 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6314 04:50:42.165076 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6315 04:50:42.167821 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6316 04:50:42.167901
6317 04:50:42.167965
6318 04:50:42.168023 ==
6319 04:50:42.171726 Dram Type= 6, Freq= 0, CH_0, rank 0
6320 04:50:42.174926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6321 04:50:42.175007 ==
6322 04:50:42.178115
6323 04:50:42.178195
6324 04:50:42.178258 TX Vref Scan disable
6325 04:50:42.181390 == TX Byte 0 ==
6326 04:50:42.184796 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6327 04:50:42.188263 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6328 04:50:42.191564 == TX Byte 1 ==
6329 04:50:42.194970 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6330 04:50:42.198355 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6331 04:50:42.198436 ==
6332 04:50:42.201701 Dram Type= 6, Freq= 0, CH_0, rank 0
6333 04:50:42.204927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6334 04:50:42.208047 ==
6335 04:50:42.208126
6336 04:50:42.208190
6337 04:50:42.208249 TX Vref Scan disable
6338 04:50:42.211387 == TX Byte 0 ==
6339 04:50:42.214721 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6340 04:50:42.218153 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6341 04:50:42.221249 == TX Byte 1 ==
6342 04:50:42.224411 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6343 04:50:42.227380 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6344 04:50:42.227461
6345 04:50:42.231153 [DATLAT]
6346 04:50:42.231234 Freq=400, CH0 RK0
6347 04:50:42.231298
6348 04:50:42.234402 DATLAT Default: 0xf
6349 04:50:42.234482 0, 0xFFFF, sum = 0
6350 04:50:42.237467 1, 0xFFFF, sum = 0
6351 04:50:42.237549 2, 0xFFFF, sum = 0
6352 04:50:42.240647 3, 0xFFFF, sum = 0
6353 04:50:42.240729 4, 0xFFFF, sum = 0
6354 04:50:42.244028 5, 0xFFFF, sum = 0
6355 04:50:42.244110 6, 0xFFFF, sum = 0
6356 04:50:42.247235 7, 0xFFFF, sum = 0
6357 04:50:42.247317 8, 0xFFFF, sum = 0
6358 04:50:42.250478 9, 0xFFFF, sum = 0
6359 04:50:42.250560 10, 0xFFFF, sum = 0
6360 04:50:42.254323 11, 0xFFFF, sum = 0
6361 04:50:42.257293 12, 0xFFFF, sum = 0
6362 04:50:42.257375 13, 0x0, sum = 1
6363 04:50:42.257440 14, 0x0, sum = 2
6364 04:50:42.260849 15, 0x0, sum = 3
6365 04:50:42.260931 16, 0x0, sum = 4
6366 04:50:42.263847 best_step = 14
6367 04:50:42.263926
6368 04:50:42.263989 ==
6369 04:50:42.267483 Dram Type= 6, Freq= 0, CH_0, rank 0
6370 04:50:42.270996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6371 04:50:42.271094 ==
6372 04:50:42.273950 RX Vref Scan: 1
6373 04:50:42.274031
6374 04:50:42.274095 RX Vref 0 -> 0, step: 1
6375 04:50:42.274154
6376 04:50:42.277349 RX Delay -311 -> 252, step: 8
6377 04:50:42.277430
6378 04:50:42.280750 Set Vref, RX VrefLevel [Byte0]: 56
6379 04:50:42.283716 [Byte1]: 46
6380 04:50:42.288464
6381 04:50:42.288544 Final RX Vref Byte 0 = 56 to rank0
6382 04:50:42.291849 Final RX Vref Byte 1 = 46 to rank0
6383 04:50:42.295231 Final RX Vref Byte 0 = 56 to rank1
6384 04:50:42.298560 Final RX Vref Byte 1 = 46 to rank1==
6385 04:50:42.301928 Dram Type= 6, Freq= 0, CH_0, rank 0
6386 04:50:42.308575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6387 04:50:42.308658 ==
6388 04:50:42.308722 DQS Delay:
6389 04:50:42.312280 DQS0 = 28, DQS1 = 36
6390 04:50:42.312371 DQM Delay:
6391 04:50:42.312436 DQM0 = 11, DQM1 = 13
6392 04:50:42.315556 DQ Delay:
6393 04:50:42.318909 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6394 04:50:42.318990 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6395 04:50:42.322330 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6396 04:50:42.325072 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6397 04:50:42.325154
6398 04:50:42.325230
6399 04:50:42.335426 [DQSOSCAuto] RK0, (LSB)MR18= 0xc6b3, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6400 04:50:42.338106 CH0 RK0: MR19=C0C, MR18=C6B3
6401 04:50:42.345509 CH0_RK0: MR19=0xC0C, MR18=0xC6B3, DQSOSC=385, MR23=63, INC=398, DEC=265
6402 04:50:42.345602 ==
6403 04:50:42.348416 Dram Type= 6, Freq= 0, CH_0, rank 1
6404 04:50:42.351433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 04:50:42.351516 ==
6406 04:50:42.354953 [Gating] SW mode calibration
6407 04:50:42.361560 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6408 04:50:42.368833 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6409 04:50:42.371514 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6410 04:50:42.375394 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6411 04:50:42.378496 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6412 04:50:42.385150 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6413 04:50:42.388268 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6414 04:50:42.391892 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6415 04:50:42.398022 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6416 04:50:42.401250 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6417 04:50:42.405009 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6418 04:50:42.408251 Total UI for P1: 0, mck2ui 16
6419 04:50:42.411613 best dqsien dly found for B0: ( 0, 14, 24)
6420 04:50:42.414845 Total UI for P1: 0, mck2ui 16
6421 04:50:42.418180 best dqsien dly found for B1: ( 0, 14, 24)
6422 04:50:42.421246 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6423 04:50:42.427888 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6424 04:50:42.427973
6425 04:50:42.431364 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6426 04:50:42.434644 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6427 04:50:42.437921 [Gating] SW calibration Done
6428 04:50:42.438005 ==
6429 04:50:42.441615 Dram Type= 6, Freq= 0, CH_0, rank 1
6430 04:50:42.444967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6431 04:50:42.445051 ==
6432 04:50:42.445117 RX Vref Scan: 0
6433 04:50:42.448350
6434 04:50:42.448433 RX Vref 0 -> 0, step: 1
6435 04:50:42.448499
6436 04:50:42.451841 RX Delay -410 -> 252, step: 16
6437 04:50:42.455036 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6438 04:50:42.461256 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6439 04:50:42.464965 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6440 04:50:42.468001 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6441 04:50:42.471847 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6442 04:50:42.478008 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6443 04:50:42.481241 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6444 04:50:42.485015 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6445 04:50:42.487819 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6446 04:50:42.495138 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6447 04:50:42.497773 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6448 04:50:42.501694 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6449 04:50:42.504359 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6450 04:50:42.511374 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6451 04:50:42.514498 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6452 04:50:42.517868 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6453 04:50:42.517951 ==
6454 04:50:42.521280 Dram Type= 6, Freq= 0, CH_0, rank 1
6455 04:50:42.524235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6456 04:50:42.527893 ==
6457 04:50:42.527978 DQS Delay:
6458 04:50:42.528043 DQS0 = 27, DQS1 = 35
6459 04:50:42.531194 DQM Delay:
6460 04:50:42.531278 DQM0 = 12, DQM1 = 12
6461 04:50:42.534569 DQ Delay:
6462 04:50:42.534652 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6463 04:50:42.537930 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6464 04:50:42.541368 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6465 04:50:42.544712 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6466 04:50:42.544795
6467 04:50:42.544860
6468 04:50:42.544920 ==
6469 04:50:42.547649 Dram Type= 6, Freq= 0, CH_0, rank 1
6470 04:50:42.554537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6471 04:50:42.554630 ==
6472 04:50:42.554697
6473 04:50:42.554757
6474 04:50:42.557968 TX Vref Scan disable
6475 04:50:42.558051 == TX Byte 0 ==
6476 04:50:42.561362 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6477 04:50:42.564621 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6478 04:50:42.567924 == TX Byte 1 ==
6479 04:50:42.571098 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6480 04:50:42.574342 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6481 04:50:42.577502 ==
6482 04:50:42.577587 Dram Type= 6, Freq= 0, CH_0, rank 1
6483 04:50:42.584509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6484 04:50:42.584599 ==
6485 04:50:42.584665
6486 04:50:42.584726
6487 04:50:42.587535 TX Vref Scan disable
6488 04:50:42.587651 == TX Byte 0 ==
6489 04:50:42.590810 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6490 04:50:42.594402 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6491 04:50:42.597830 == TX Byte 1 ==
6492 04:50:42.601203 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6493 04:50:42.604505 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6494 04:50:42.604589
6495 04:50:42.607814 [DATLAT]
6496 04:50:42.607897 Freq=400, CH0 RK1
6497 04:50:42.607963
6498 04:50:42.611249 DATLAT Default: 0xe
6499 04:50:42.611331 0, 0xFFFF, sum = 0
6500 04:50:42.614647 1, 0xFFFF, sum = 0
6501 04:50:42.614731 2, 0xFFFF, sum = 0
6502 04:50:42.617383 3, 0xFFFF, sum = 0
6503 04:50:42.617466 4, 0xFFFF, sum = 0
6504 04:50:42.620713 5, 0xFFFF, sum = 0
6505 04:50:42.620796 6, 0xFFFF, sum = 0
6506 04:50:42.623936 7, 0xFFFF, sum = 0
6507 04:50:42.627643 8, 0xFFFF, sum = 0
6508 04:50:42.627732 9, 0xFFFF, sum = 0
6509 04:50:42.631102 10, 0xFFFF, sum = 0
6510 04:50:42.631192 11, 0xFFFF, sum = 0
6511 04:50:42.634347 12, 0xFFFF, sum = 0
6512 04:50:42.634438 13, 0x0, sum = 1
6513 04:50:42.637367 14, 0x0, sum = 2
6514 04:50:42.637456 15, 0x0, sum = 3
6515 04:50:42.640802 16, 0x0, sum = 4
6516 04:50:42.640890 best_step = 14
6517 04:50:42.640957
6518 04:50:42.641018 ==
6519 04:50:42.644109 Dram Type= 6, Freq= 0, CH_0, rank 1
6520 04:50:42.647528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6521 04:50:42.647622 ==
6522 04:50:42.650704 RX Vref Scan: 0
6523 04:50:42.650790
6524 04:50:42.653763 RX Vref 0 -> 0, step: 1
6525 04:50:42.653859
6526 04:50:42.653926 RX Delay -311 -> 252, step: 8
6527 04:50:42.662576 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6528 04:50:42.665903 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6529 04:50:42.669255 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6530 04:50:42.675635 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6531 04:50:42.678872 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6532 04:50:42.682546 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6533 04:50:42.685728 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6534 04:50:42.688953 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6535 04:50:42.695436 iDelay=217, Bit 8, Center -32 (-247 ~ 184) 432
6536 04:50:42.698781 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6537 04:50:42.701980 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6538 04:50:42.708738 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6539 04:50:42.712257 iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432
6540 04:50:42.715352 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6541 04:50:42.718735 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6542 04:50:42.725404 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6543 04:50:42.725490 ==
6544 04:50:42.728755 Dram Type= 6, Freq= 0, CH_0, rank 1
6545 04:50:42.732128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6546 04:50:42.732211 ==
6547 04:50:42.732277 DQS Delay:
6548 04:50:42.735319 DQS0 = 24, DQS1 = 36
6549 04:50:42.735401 DQM Delay:
6550 04:50:42.739036 DQM0 = 8, DQM1 = 13
6551 04:50:42.739120 DQ Delay:
6552 04:50:42.742181 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6553 04:50:42.745542 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6554 04:50:42.748900 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6555 04:50:42.752132 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6556 04:50:42.752216
6557 04:50:42.752281
6558 04:50:42.758804 [DQSOSCAuto] RK1, (LSB)MR18= 0xba5a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6559 04:50:42.762290 CH0 RK1: MR19=C0C, MR18=BA5A
6560 04:50:42.768421 CH0_RK1: MR19=0xC0C, MR18=0xBA5A, DQSOSC=386, MR23=63, INC=396, DEC=264
6561 04:50:42.771850 [RxdqsGatingPostProcess] freq 400
6562 04:50:42.778199 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6563 04:50:42.782087 best DQS0 dly(2T, 0.5T) = (0, 10)
6564 04:50:42.782174 best DQS1 dly(2T, 0.5T) = (0, 10)
6565 04:50:42.785504 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6566 04:50:42.788556 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6567 04:50:42.791585 best DQS0 dly(2T, 0.5T) = (0, 10)
6568 04:50:42.794863 best DQS1 dly(2T, 0.5T) = (0, 10)
6569 04:50:42.798153 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6570 04:50:42.801427 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6571 04:50:42.804736 Pre-setting of DQS Precalculation
6572 04:50:42.811423 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6573 04:50:42.811512 ==
6574 04:50:42.814667 Dram Type= 6, Freq= 0, CH_1, rank 0
6575 04:50:42.818527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6576 04:50:42.818611 ==
6577 04:50:42.824812 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6578 04:50:42.827883 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6579 04:50:42.831358 [CA 0] Center 36 (8~64) winsize 57
6580 04:50:42.834782 [CA 1] Center 36 (8~64) winsize 57
6581 04:50:42.838171 [CA 2] Center 36 (8~64) winsize 57
6582 04:50:42.841391 [CA 3] Center 36 (8~64) winsize 57
6583 04:50:42.844661 [CA 4] Center 36 (8~64) winsize 57
6584 04:50:42.848198 [CA 5] Center 36 (8~64) winsize 57
6585 04:50:42.848292
6586 04:50:42.851404 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6587 04:50:42.851512
6588 04:50:42.854767 [CATrainingPosCal] consider 1 rank data
6589 04:50:42.858302 u2DelayCellTimex100 = 270/100 ps
6590 04:50:42.861696 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6591 04:50:42.865201 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6592 04:50:42.867891 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6593 04:50:42.874493 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6594 04:50:42.877793 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6595 04:50:42.881272 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6596 04:50:42.881356
6597 04:50:42.884697 CA PerBit enable=1, Macro0, CA PI delay=36
6598 04:50:42.884779
6599 04:50:42.887937 [CBTSetCACLKResult] CA Dly = 36
6600 04:50:42.888020 CS Dly: 1 (0~32)
6601 04:50:42.888086 ==
6602 04:50:42.891049 Dram Type= 6, Freq= 0, CH_1, rank 1
6603 04:50:42.897850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6604 04:50:42.897937 ==
6605 04:50:42.901658 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6606 04:50:42.908207 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6607 04:50:42.911622 [CA 0] Center 36 (8~64) winsize 57
6608 04:50:42.914559 [CA 1] Center 36 (8~64) winsize 57
6609 04:50:42.918279 [CA 2] Center 36 (8~64) winsize 57
6610 04:50:42.921402 [CA 3] Center 36 (8~64) winsize 57
6611 04:50:42.924683 [CA 4] Center 36 (8~64) winsize 57
6612 04:50:42.927922 [CA 5] Center 36 (8~64) winsize 57
6613 04:50:42.928003
6614 04:50:42.931266 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6615 04:50:42.931349
6616 04:50:42.934346 [CATrainingPosCal] consider 2 rank data
6617 04:50:42.938193 u2DelayCellTimex100 = 270/100 ps
6618 04:50:42.941635 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 04:50:42.944340 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 04:50:42.947704 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 04:50:42.951123 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 04:50:42.954202 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 04:50:42.957907 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 04:50:42.957991
6625 04:50:42.964704 CA PerBit enable=1, Macro0, CA PI delay=36
6626 04:50:42.964787
6627 04:50:42.968102 [CBTSetCACLKResult] CA Dly = 36
6628 04:50:42.968183 CS Dly: 1 (0~32)
6629 04:50:42.968247
6630 04:50:42.971505 ----->DramcWriteLeveling(PI) begin...
6631 04:50:42.971588 ==
6632 04:50:42.974883 Dram Type= 6, Freq= 0, CH_1, rank 0
6633 04:50:42.977577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6634 04:50:42.977658 ==
6635 04:50:42.980968 Write leveling (Byte 0): 40 => 8
6636 04:50:42.984275 Write leveling (Byte 1): 40 => 8
6637 04:50:42.987708 DramcWriteLeveling(PI) end<-----
6638 04:50:42.987789
6639 04:50:42.987852 ==
6640 04:50:42.990936 Dram Type= 6, Freq= 0, CH_1, rank 0
6641 04:50:42.994268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6642 04:50:42.997518 ==
6643 04:50:42.997600 [Gating] SW mode calibration
6644 04:50:43.004546 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6645 04:50:43.011332 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6646 04:50:43.014739 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6647 04:50:43.021237 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6648 04:50:43.024538 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6649 04:50:43.027846 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6650 04:50:43.034843 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6651 04:50:43.038051 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6652 04:50:43.041329 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6653 04:50:43.044246 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6654 04:50:43.051088 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6655 04:50:43.054369 Total UI for P1: 0, mck2ui 16
6656 04:50:43.057919 best dqsien dly found for B0: ( 0, 14, 24)
6657 04:50:43.061022 Total UI for P1: 0, mck2ui 16
6658 04:50:43.064559 best dqsien dly found for B1: ( 0, 14, 24)
6659 04:50:43.067680 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6660 04:50:43.071132 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6661 04:50:43.071215
6662 04:50:43.074326 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6663 04:50:43.077666 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6664 04:50:43.080941 [Gating] SW calibration Done
6665 04:50:43.081025 ==
6666 04:50:43.084228 Dram Type= 6, Freq= 0, CH_1, rank 0
6667 04:50:43.087616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6668 04:50:43.087699 ==
6669 04:50:43.090962 RX Vref Scan: 0
6670 04:50:43.091044
6671 04:50:43.094254 RX Vref 0 -> 0, step: 1
6672 04:50:43.094336
6673 04:50:43.094402 RX Delay -410 -> 252, step: 16
6674 04:50:43.101176 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6675 04:50:43.104314 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6676 04:50:43.107663 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6677 04:50:43.111662 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6678 04:50:43.117852 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6679 04:50:43.121271 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6680 04:50:43.124570 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6681 04:50:43.127872 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6682 04:50:43.134597 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6683 04:50:43.137919 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6684 04:50:43.141236 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6685 04:50:43.144272 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6686 04:50:43.151146 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6687 04:50:43.154386 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6688 04:50:43.157676 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6689 04:50:43.164605 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6690 04:50:43.164695 ==
6691 04:50:43.167907 Dram Type= 6, Freq= 0, CH_1, rank 0
6692 04:50:43.170842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6693 04:50:43.170926 ==
6694 04:50:43.170992 DQS Delay:
6695 04:50:43.174277 DQS0 = 35, DQS1 = 35
6696 04:50:43.174361 DQM Delay:
6697 04:50:43.177328 DQM0 = 17, DQM1 = 13
6698 04:50:43.177410 DQ Delay:
6699 04:50:43.181047 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6700 04:50:43.184614 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6701 04:50:43.187705 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6702 04:50:43.191009 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6703 04:50:43.191091
6704 04:50:43.191155
6705 04:50:43.191214 ==
6706 04:50:43.194130 Dram Type= 6, Freq= 0, CH_1, rank 0
6707 04:50:43.197542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6708 04:50:43.197624 ==
6709 04:50:43.197688
6710 04:50:43.197748
6711 04:50:43.200894 TX Vref Scan disable
6712 04:50:43.200974 == TX Byte 0 ==
6713 04:50:43.207601 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6714 04:50:43.210728 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6715 04:50:43.210810 == TX Byte 1 ==
6716 04:50:43.217498 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6717 04:50:43.220698 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6718 04:50:43.220781 ==
6719 04:50:43.223974 Dram Type= 6, Freq= 0, CH_1, rank 0
6720 04:50:43.227229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6721 04:50:43.227310 ==
6722 04:50:43.227374
6723 04:50:43.227435
6724 04:50:43.230601 TX Vref Scan disable
6725 04:50:43.233913 == TX Byte 0 ==
6726 04:50:43.237299 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6727 04:50:43.242795 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6728 04:50:43.242879 == TX Byte 1 ==
6729 04:50:43.247122 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6730 04:50:43.250392 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6731 04:50:43.250474
6732 04:50:43.250546 [DATLAT]
6733 04:50:43.254161 Freq=400, CH1 RK0
6734 04:50:43.254243
6735 04:50:43.254308 DATLAT Default: 0xf
6736 04:50:43.257524 0, 0xFFFF, sum = 0
6737 04:50:43.257608 1, 0xFFFF, sum = 0
6738 04:50:43.260857 2, 0xFFFF, sum = 0
6739 04:50:43.260941 3, 0xFFFF, sum = 0
6740 04:50:43.264263 4, 0xFFFF, sum = 0
6741 04:50:43.264385 5, 0xFFFF, sum = 0
6742 04:50:43.267583 6, 0xFFFF, sum = 0
6743 04:50:43.270718 7, 0xFFFF, sum = 0
6744 04:50:43.270802 8, 0xFFFF, sum = 0
6745 04:50:43.274239 9, 0xFFFF, sum = 0
6746 04:50:43.274322 10, 0xFFFF, sum = 0
6747 04:50:43.277537 11, 0xFFFF, sum = 0
6748 04:50:43.277619 12, 0xFFFF, sum = 0
6749 04:50:43.280731 13, 0x0, sum = 1
6750 04:50:43.280815 14, 0x0, sum = 2
6751 04:50:43.284126 15, 0x0, sum = 3
6752 04:50:43.284209 16, 0x0, sum = 4
6753 04:50:43.284275 best_step = 14
6754 04:50:43.287281
6755 04:50:43.287362 ==
6756 04:50:43.290365 Dram Type= 6, Freq= 0, CH_1, rank 0
6757 04:50:43.294098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6758 04:50:43.294181 ==
6759 04:50:43.294246 RX Vref Scan: 1
6760 04:50:43.294307
6761 04:50:43.296942 RX Vref 0 -> 0, step: 1
6762 04:50:43.297023
6763 04:50:43.300339 RX Delay -311 -> 252, step: 8
6764 04:50:43.300421
6765 04:50:43.303617 Set Vref, RX VrefLevel [Byte0]: 55
6766 04:50:43.306841 [Byte1]: 48
6767 04:50:43.311053
6768 04:50:43.311134 Final RX Vref Byte 0 = 55 to rank0
6769 04:50:43.313893 Final RX Vref Byte 1 = 48 to rank0
6770 04:50:43.317611 Final RX Vref Byte 0 = 55 to rank1
6771 04:50:43.320654 Final RX Vref Byte 1 = 48 to rank1==
6772 04:50:43.323832 Dram Type= 6, Freq= 0, CH_1, rank 0
6773 04:50:43.330591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6774 04:50:43.330675 ==
6775 04:50:43.330740 DQS Delay:
6776 04:50:43.334198 DQS0 = 28, DQS1 = 32
6777 04:50:43.334281 DQM Delay:
6778 04:50:43.334345 DQM0 = 10, DQM1 = 11
6779 04:50:43.337292 DQ Delay:
6780 04:50:43.340565 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6781 04:50:43.340648 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6782 04:50:43.343903 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6783 04:50:43.347169 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =24
6784 04:50:43.347251
6785 04:50:43.347315
6786 04:50:43.357300 [DQSOSCAuto] RK0, (LSB)MR18= 0x8cc4, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6787 04:50:43.360448 CH1 RK0: MR19=C0C, MR18=8CC4
6788 04:50:43.366870 CH1_RK0: MR19=0xC0C, MR18=0x8CC4, DQSOSC=385, MR23=63, INC=398, DEC=265
6789 04:50:43.366954 ==
6790 04:50:43.370203 Dram Type= 6, Freq= 0, CH_1, rank 1
6791 04:50:43.373432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 04:50:43.373513 ==
6793 04:50:43.376645 [Gating] SW mode calibration
6794 04:50:43.383765 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6795 04:50:43.390506 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6796 04:50:43.393923 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6797 04:50:43.397204 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6798 04:50:43.400616 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6799 04:50:43.407432 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6800 04:50:43.410738 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6801 04:50:43.413924 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6802 04:50:43.420222 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6803 04:50:43.423993 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6804 04:50:43.427051 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6805 04:50:43.430150 Total UI for P1: 0, mck2ui 16
6806 04:50:43.433978 best dqsien dly found for B0: ( 0, 14, 24)
6807 04:50:43.437080 Total UI for P1: 0, mck2ui 16
6808 04:50:43.440196 best dqsien dly found for B1: ( 0, 14, 24)
6809 04:50:43.444002 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6810 04:50:43.446813 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6811 04:50:43.450342
6812 04:50:43.453569 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6813 04:50:43.456666 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6814 04:50:43.460163 [Gating] SW calibration Done
6815 04:50:43.460245 ==
6816 04:50:43.463362 Dram Type= 6, Freq= 0, CH_1, rank 1
6817 04:50:43.466682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6818 04:50:43.466764 ==
6819 04:50:43.466829 RX Vref Scan: 0
6820 04:50:43.466889
6821 04:50:43.470401 RX Vref 0 -> 0, step: 1
6822 04:50:43.470482
6823 04:50:43.473557 RX Delay -410 -> 252, step: 16
6824 04:50:43.476926 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6825 04:50:43.483453 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6826 04:50:43.486602 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6827 04:50:43.489910 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6828 04:50:43.493138 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6829 04:50:43.497151 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6830 04:50:43.503294 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6831 04:50:43.506712 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6832 04:50:43.510069 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6833 04:50:43.513398 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6834 04:50:43.519943 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6835 04:50:43.523333 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6836 04:50:43.526548 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6837 04:50:43.533384 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6838 04:50:43.536557 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6839 04:50:43.539944 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6840 04:50:43.540028 ==
6841 04:50:43.543264 Dram Type= 6, Freq= 0, CH_1, rank 1
6842 04:50:43.546606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6843 04:50:43.546690 ==
6844 04:50:43.550310 DQS Delay:
6845 04:50:43.550393 DQS0 = 35, DQS1 = 35
6846 04:50:43.553594 DQM Delay:
6847 04:50:43.553677 DQM0 = 19, DQM1 = 13
6848 04:50:43.556946 DQ Delay:
6849 04:50:43.557031 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6850 04:50:43.560399 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6851 04:50:43.563446 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6852 04:50:43.566555 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6853 04:50:43.566638
6854 04:50:43.566703
6855 04:50:43.570276 ==
6856 04:50:43.570358 Dram Type= 6, Freq= 0, CH_1, rank 1
6857 04:50:43.577053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6858 04:50:43.577138 ==
6859 04:50:43.577204
6860 04:50:43.577265
6861 04:50:43.577323 TX Vref Scan disable
6862 04:50:43.579872 == TX Byte 0 ==
6863 04:50:43.583448 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6864 04:50:43.586761 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6865 04:50:43.590051 == TX Byte 1 ==
6866 04:50:43.593159 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6867 04:50:43.596816 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6868 04:50:43.600200 ==
6869 04:50:43.600347 Dram Type= 6, Freq= 0, CH_1, rank 1
6870 04:50:43.607017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6871 04:50:43.607104 ==
6872 04:50:43.607208
6873 04:50:43.607269
6874 04:50:43.610350 TX Vref Scan disable
6875 04:50:43.610433 == TX Byte 0 ==
6876 04:50:43.613120 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6877 04:50:43.619841 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6878 04:50:43.619925 == TX Byte 1 ==
6879 04:50:43.623260 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6880 04:50:43.626508 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6881 04:50:43.626591
6882 04:50:43.629744 [DATLAT]
6883 04:50:43.629827 Freq=400, CH1 RK1
6884 04:50:43.629893
6885 04:50:43.632851 DATLAT Default: 0xe
6886 04:50:43.632934 0, 0xFFFF, sum = 0
6887 04:50:43.636547 1, 0xFFFF, sum = 0
6888 04:50:43.636658 2, 0xFFFF, sum = 0
6889 04:50:43.639747 3, 0xFFFF, sum = 0
6890 04:50:43.639831 4, 0xFFFF, sum = 0
6891 04:50:43.643031 5, 0xFFFF, sum = 0
6892 04:50:43.643115 6, 0xFFFF, sum = 0
6893 04:50:43.646249 7, 0xFFFF, sum = 0
6894 04:50:43.649580 8, 0xFFFF, sum = 0
6895 04:50:43.649664 9, 0xFFFF, sum = 0
6896 04:50:43.652938 10, 0xFFFF, sum = 0
6897 04:50:43.653036 11, 0xFFFF, sum = 0
6898 04:50:43.656768 12, 0xFFFF, sum = 0
6899 04:50:43.656858 13, 0x0, sum = 1
6900 04:50:43.660014 14, 0x0, sum = 2
6901 04:50:43.660124 15, 0x0, sum = 3
6902 04:50:43.663300 16, 0x0, sum = 4
6903 04:50:43.663384 best_step = 14
6904 04:50:43.663450
6905 04:50:43.663511 ==
6906 04:50:43.666422 Dram Type= 6, Freq= 0, CH_1, rank 1
6907 04:50:43.669735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6908 04:50:43.669819 ==
6909 04:50:43.673164 RX Vref Scan: 0
6910 04:50:43.673247
6911 04:50:43.676484 RX Vref 0 -> 0, step: 1
6912 04:50:43.676567
6913 04:50:43.676633 RX Delay -311 -> 252, step: 8
6914 04:50:43.684733 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6915 04:50:43.688518 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6916 04:50:43.691600 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6917 04:50:43.695166 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6918 04:50:43.701392 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6919 04:50:43.705014 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6920 04:50:43.707925 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6921 04:50:43.711231 iDelay=217, Bit 7, Center -20 (-247 ~ 208) 456
6922 04:50:43.717881 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6923 04:50:43.721701 iDelay=217, Bit 9, Center -28 (-247 ~ 192) 440
6924 04:50:43.724890 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6925 04:50:43.728211 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6926 04:50:43.734862 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6927 04:50:43.738024 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6928 04:50:43.741119 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6929 04:50:43.748142 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6930 04:50:43.748232 ==
6931 04:50:43.751489 Dram Type= 6, Freq= 0, CH_1, rank 1
6932 04:50:43.754856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6933 04:50:43.754943 ==
6934 04:50:43.755007 DQS Delay:
6935 04:50:43.758129 DQS0 = 28, DQS1 = 36
6936 04:50:43.758211 DQM Delay:
6937 04:50:43.761299 DQM0 = 10, DQM1 = 15
6938 04:50:43.761380 DQ Delay:
6939 04:50:43.764718 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6940 04:50:43.768142 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6941 04:50:43.771401 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =12
6942 04:50:43.774406 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6943 04:50:43.774488
6944 04:50:43.774552
6945 04:50:43.781579 [DQSOSCAuto] RK1, (LSB)MR18= 0xc153, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
6946 04:50:43.784997 CH1 RK1: MR19=C0C, MR18=C153
6947 04:50:43.791019 CH1_RK1: MR19=0xC0C, MR18=0xC153, DQSOSC=385, MR23=63, INC=398, DEC=265
6948 04:50:43.794390 [RxdqsGatingPostProcess] freq 400
6949 04:50:43.801105 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6950 04:50:43.801195 best DQS0 dly(2T, 0.5T) = (0, 10)
6951 04:50:43.804537 best DQS1 dly(2T, 0.5T) = (0, 10)
6952 04:50:43.807910 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6953 04:50:43.811117 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6954 04:50:43.814305 best DQS0 dly(2T, 0.5T) = (0, 10)
6955 04:50:43.817571 best DQS1 dly(2T, 0.5T) = (0, 10)
6956 04:50:43.821362 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6957 04:50:43.824688 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6958 04:50:43.827946 Pre-setting of DQS Precalculation
6959 04:50:43.831366 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6960 04:50:43.841224 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6961 04:50:43.847895 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6962 04:50:43.847989
6963 04:50:43.848054
6964 04:50:43.851295 [Calibration Summary] 800 Mbps
6965 04:50:43.851380 CH 0, Rank 0
6966 04:50:43.854576 SW Impedance : PASS
6967 04:50:43.854660 DUTY Scan : NO K
6968 04:50:43.858129 ZQ Calibration : PASS
6969 04:50:43.861434 Jitter Meter : NO K
6970 04:50:43.861519 CBT Training : PASS
6971 04:50:43.864730 Write leveling : PASS
6972 04:50:43.867628 RX DQS gating : PASS
6973 04:50:43.867712 RX DQ/DQS(RDDQC) : PASS
6974 04:50:43.871136 TX DQ/DQS : PASS
6975 04:50:43.874571 RX DATLAT : PASS
6976 04:50:43.874656 RX DQ/DQS(Engine): PASS
6977 04:50:43.878095 TX OE : NO K
6978 04:50:43.878179 All Pass.
6979 04:50:43.878244
6980 04:50:43.878305 CH 0, Rank 1
6981 04:50:43.881257 SW Impedance : PASS
6982 04:50:43.884334 DUTY Scan : NO K
6983 04:50:43.884503 ZQ Calibration : PASS
6984 04:50:43.887544 Jitter Meter : NO K
6985 04:50:43.891029 CBT Training : PASS
6986 04:50:43.891113 Write leveling : NO K
6987 04:50:43.894376 RX DQS gating : PASS
6988 04:50:43.897777 RX DQ/DQS(RDDQC) : PASS
6989 04:50:43.897862 TX DQ/DQS : PASS
6990 04:50:43.901203 RX DATLAT : PASS
6991 04:50:43.904407 RX DQ/DQS(Engine): PASS
6992 04:50:43.904490 TX OE : NO K
6993 04:50:43.907867 All Pass.
6994 04:50:43.907950
6995 04:50:43.908015 CH 1, Rank 0
6996 04:50:43.911251 SW Impedance : PASS
6997 04:50:43.911334 DUTY Scan : NO K
6998 04:50:43.914516 ZQ Calibration : PASS
6999 04:50:43.917888 Jitter Meter : NO K
7000 04:50:43.917972 CBT Training : PASS
7001 04:50:43.921128 Write leveling : PASS
7002 04:50:43.924524 RX DQS gating : PASS
7003 04:50:43.924609 RX DQ/DQS(RDDQC) : PASS
7004 04:50:43.927941 TX DQ/DQS : PASS
7005 04:50:43.928025 RX DATLAT : PASS
7006 04:50:43.931326 RX DQ/DQS(Engine): PASS
7007 04:50:43.934509 TX OE : NO K
7008 04:50:43.934594 All Pass.
7009 04:50:43.934659
7010 04:50:43.934720 CH 1, Rank 1
7011 04:50:43.937602 SW Impedance : PASS
7012 04:50:43.941192 DUTY Scan : NO K
7013 04:50:43.941276 ZQ Calibration : PASS
7014 04:50:43.944596 Jitter Meter : NO K
7015 04:50:43.947806 CBT Training : PASS
7016 04:50:43.947889 Write leveling : NO K
7017 04:50:43.950846 RX DQS gating : PASS
7018 04:50:43.954452 RX DQ/DQS(RDDQC) : PASS
7019 04:50:43.954535 TX DQ/DQS : PASS
7020 04:50:43.957441 RX DATLAT : PASS
7021 04:50:43.961018 RX DQ/DQS(Engine): PASS
7022 04:50:43.961105 TX OE : NO K
7023 04:50:43.964268 All Pass.
7024 04:50:43.964389
7025 04:50:43.964455 DramC Write-DBI off
7026 04:50:43.967825 PER_BANK_REFRESH: Hybrid Mode
7027 04:50:43.967908 TX_TRACKING: ON
7028 04:50:43.977518 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7029 04:50:43.980902 [FAST_K] Save calibration result to emmc
7030 04:50:43.983901 dramc_set_vcore_voltage set vcore to 725000
7031 04:50:43.987257 Read voltage for 1600, 0
7032 04:50:43.987340 Vio18 = 0
7033 04:50:43.990737 Vcore = 725000
7034 04:50:43.990820 Vdram = 0
7035 04:50:43.990885 Vddq = 0
7036 04:50:43.993873 Vmddr = 0
7037 04:50:43.997014 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7038 04:50:44.004240 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7039 04:50:44.004359 MEM_TYPE=3, freq_sel=13
7040 04:50:44.007027 sv_algorithm_assistance_LP4_3733
7041 04:50:44.013762 ============ PULL DRAM RESETB DOWN ============
7042 04:50:44.017202 ========== PULL DRAM RESETB DOWN end =========
7043 04:50:44.020568 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7044 04:50:44.023726 ===================================
7045 04:50:44.027003 LPDDR4 DRAM CONFIGURATION
7046 04:50:44.030395 ===================================
7047 04:50:44.030479 EX_ROW_EN[0] = 0x0
7048 04:50:44.033878 EX_ROW_EN[1] = 0x0
7049 04:50:44.037207 LP4Y_EN = 0x0
7050 04:50:44.037289 WORK_FSP = 0x1
7051 04:50:44.040607 WL = 0x5
7052 04:50:44.040689 RL = 0x5
7053 04:50:44.043750 BL = 0x2
7054 04:50:44.043830 RPST = 0x0
7055 04:50:44.046783 RD_PRE = 0x0
7056 04:50:44.046865 WR_PRE = 0x1
7057 04:50:44.050414 WR_PST = 0x1
7058 04:50:44.050494 DBI_WR = 0x0
7059 04:50:44.053648 DBI_RD = 0x0
7060 04:50:44.053730 OTF = 0x1
7061 04:50:44.056966 ===================================
7062 04:50:44.060194 ===================================
7063 04:50:44.063419 ANA top config
7064 04:50:44.066668 ===================================
7065 04:50:44.066752 DLL_ASYNC_EN = 0
7066 04:50:44.069881 ALL_SLAVE_EN = 0
7067 04:50:44.073431 NEW_RANK_MODE = 1
7068 04:50:44.076785 DLL_IDLE_MODE = 1
7069 04:50:44.080168 LP45_APHY_COMB_EN = 1
7070 04:50:44.080251 TX_ODT_DIS = 0
7071 04:50:44.083363 NEW_8X_MODE = 1
7072 04:50:44.086663 ===================================
7073 04:50:44.090301 ===================================
7074 04:50:44.093125 data_rate = 3200
7075 04:50:44.096328 CKR = 1
7076 04:50:44.100158 DQ_P2S_RATIO = 8
7077 04:50:44.103256 ===================================
7078 04:50:44.106746 CA_P2S_RATIO = 8
7079 04:50:44.106832 DQ_CA_OPEN = 0
7080 04:50:44.109949 DQ_SEMI_OPEN = 0
7081 04:50:44.113144 CA_SEMI_OPEN = 0
7082 04:50:44.116470 CA_FULL_RATE = 0
7083 04:50:44.119784 DQ_CKDIV4_EN = 0
7084 04:50:44.123224 CA_CKDIV4_EN = 0
7085 04:50:44.123308 CA_PREDIV_EN = 0
7086 04:50:44.126489 PH8_DLY = 12
7087 04:50:44.129652 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7088 04:50:44.133000 DQ_AAMCK_DIV = 4
7089 04:50:44.136326 CA_AAMCK_DIV = 4
7090 04:50:44.136424 CA_ADMCK_DIV = 4
7091 04:50:44.139783 DQ_TRACK_CA_EN = 0
7092 04:50:44.143089 CA_PICK = 1600
7093 04:50:44.146424 CA_MCKIO = 1600
7094 04:50:44.149846 MCKIO_SEMI = 0
7095 04:50:44.153096 PLL_FREQ = 3068
7096 04:50:44.156260 DQ_UI_PI_RATIO = 32
7097 04:50:44.159925 CA_UI_PI_RATIO = 0
7098 04:50:44.163009 ===================================
7099 04:50:44.166223 ===================================
7100 04:50:44.166306 memory_type:LPDDR4
7101 04:50:44.169445 GP_NUM : 10
7102 04:50:44.172615 SRAM_EN : 1
7103 04:50:44.172713 MD32_EN : 0
7104 04:50:44.176502 ===================================
7105 04:50:44.179269 [ANA_INIT] >>>>>>>>>>>>>>
7106 04:50:44.182584 <<<<<< [CONFIGURE PHASE]: ANA_TX
7107 04:50:44.185955 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7108 04:50:44.189386 ===================================
7109 04:50:44.192788 data_rate = 3200,PCW = 0X7600
7110 04:50:44.196044 ===================================
7111 04:50:44.199368 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7112 04:50:44.202619 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7113 04:50:44.209818 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7114 04:50:44.212959 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7115 04:50:44.215989 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7116 04:50:44.219474 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7117 04:50:44.222639 [ANA_INIT] flow start
7118 04:50:44.226149 [ANA_INIT] PLL >>>>>>>>
7119 04:50:44.226231 [ANA_INIT] PLL <<<<<<<<
7120 04:50:44.229291 [ANA_INIT] MIDPI >>>>>>>>
7121 04:50:44.232488 [ANA_INIT] MIDPI <<<<<<<<
7122 04:50:44.232573 [ANA_INIT] DLL >>>>>>>>
7123 04:50:44.236275 [ANA_INIT] DLL <<<<<<<<
7124 04:50:44.239683 [ANA_INIT] flow end
7125 04:50:44.242438 ============ LP4 DIFF to SE enter ============
7126 04:50:44.245663 ============ LP4 DIFF to SE exit ============
7127 04:50:44.249351 [ANA_INIT] <<<<<<<<<<<<<
7128 04:50:44.252714 [Flow] Enable top DCM control >>>>>
7129 04:50:44.256079 [Flow] Enable top DCM control <<<<<
7130 04:50:44.259433 Enable DLL master slave shuffle
7131 04:50:44.262589 ==============================================================
7132 04:50:44.265814 Gating Mode config
7133 04:50:44.272610 ==============================================================
7134 04:50:44.272701 Config description:
7135 04:50:44.282249 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7136 04:50:44.288907 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7137 04:50:44.295683 SELPH_MODE 0: By rank 1: By Phase
7138 04:50:44.298997 ==============================================================
7139 04:50:44.302372 GAT_TRACK_EN = 1
7140 04:50:44.305745 RX_GATING_MODE = 2
7141 04:50:44.308913 RX_GATING_TRACK_MODE = 2
7142 04:50:44.312115 SELPH_MODE = 1
7143 04:50:44.315460 PICG_EARLY_EN = 1
7144 04:50:44.318807 VALID_LAT_VALUE = 1
7145 04:50:44.322067 ==============================================================
7146 04:50:44.325174 Enter into Gating configuration >>>>
7147 04:50:44.329042 Exit from Gating configuration <<<<
7148 04:50:44.331708 Enter into DVFS_PRE_config >>>>>
7149 04:50:44.345374 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7150 04:50:44.348834 Exit from DVFS_PRE_config <<<<<
7151 04:50:44.351826 Enter into PICG configuration >>>>
7152 04:50:44.351943 Exit from PICG configuration <<<<
7153 04:50:44.355066 [RX_INPUT] configuration >>>>>
7154 04:50:44.358394 [RX_INPUT] configuration <<<<<
7155 04:50:44.365412 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7156 04:50:44.368513 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7157 04:50:44.375479 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7158 04:50:44.382297 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7159 04:50:44.389007 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7160 04:50:44.395275 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7161 04:50:44.398565 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7162 04:50:44.401994 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7163 04:50:44.405375 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7164 04:50:44.412020 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7165 04:50:44.415226 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7166 04:50:44.418490 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7167 04:50:44.421899 ===================================
7168 04:50:44.425258 LPDDR4 DRAM CONFIGURATION
7169 04:50:44.428606 ===================================
7170 04:50:44.431702 EX_ROW_EN[0] = 0x0
7171 04:50:44.431785 EX_ROW_EN[1] = 0x0
7172 04:50:44.434977 LP4Y_EN = 0x0
7173 04:50:44.435062 WORK_FSP = 0x1
7174 04:50:44.438273 WL = 0x5
7175 04:50:44.438357 RL = 0x5
7176 04:50:44.441530 BL = 0x2
7177 04:50:44.441613 RPST = 0x0
7178 04:50:44.445055 RD_PRE = 0x0
7179 04:50:44.445138 WR_PRE = 0x1
7180 04:50:44.448166 WR_PST = 0x1
7181 04:50:44.448251 DBI_WR = 0x0
7182 04:50:44.451593 DBI_RD = 0x0
7183 04:50:44.451675 OTF = 0x1
7184 04:50:44.455017 ===================================
7185 04:50:44.461668 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7186 04:50:44.465023 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7187 04:50:44.468421 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7188 04:50:44.472171 ===================================
7189 04:50:44.475344 LPDDR4 DRAM CONFIGURATION
7190 04:50:44.478207 ===================================
7191 04:50:44.478293 EX_ROW_EN[0] = 0x10
7192 04:50:44.482029 EX_ROW_EN[1] = 0x0
7193 04:50:44.484879 LP4Y_EN = 0x0
7194 04:50:44.484963 WORK_FSP = 0x1
7195 04:50:44.488233 WL = 0x5
7196 04:50:44.488370 RL = 0x5
7197 04:50:44.491639 BL = 0x2
7198 04:50:44.491721 RPST = 0x0
7199 04:50:44.494762 RD_PRE = 0x0
7200 04:50:44.494846 WR_PRE = 0x1
7201 04:50:44.498116 WR_PST = 0x1
7202 04:50:44.498199 DBI_WR = 0x0
7203 04:50:44.501412 DBI_RD = 0x0
7204 04:50:44.501495 OTF = 0x1
7205 04:50:44.504911 ===================================
7206 04:50:44.511570 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7207 04:50:44.511663 ==
7208 04:50:44.515390 Dram Type= 6, Freq= 0, CH_0, rank 0
7209 04:50:44.517938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7210 04:50:44.521790 ==
7211 04:50:44.521876 [Duty_Offset_Calibration]
7212 04:50:44.525131 B0:2 B1:1 CA:1
7213 04:50:44.525215
7214 04:50:44.527778 [DutyScan_Calibration_Flow] k_type=0
7215 04:50:44.536732
7216 04:50:44.536831 ==CLK 0==
7217 04:50:44.539981 Final CLK duty delay cell = 0
7218 04:50:44.543273 [0] MAX Duty = 5156%(X100), DQS PI = 22
7219 04:50:44.547132 [0] MIN Duty = 4907%(X100), DQS PI = 0
7220 04:50:44.547218 [0] AVG Duty = 5031%(X100)
7221 04:50:44.550431
7222 04:50:44.553757 CH0 CLK Duty spec in!! Max-Min= 249%
7223 04:50:44.557247 [DutyScan_Calibration_Flow] ====Done====
7224 04:50:44.557337
7225 04:50:44.559953 [DutyScan_Calibration_Flow] k_type=1
7226 04:50:44.575977
7227 04:50:44.576101 ==DQS 0 ==
7228 04:50:44.579359 Final DQS duty delay cell = -4
7229 04:50:44.582611 [-4] MAX Duty = 5156%(X100), DQS PI = 26
7230 04:50:44.585722 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7231 04:50:44.589110 [-4] AVG Duty = 4906%(X100)
7232 04:50:44.589198
7233 04:50:44.589263 ==DQS 1 ==
7234 04:50:44.592454 Final DQS duty delay cell = 0
7235 04:50:44.595834 [0] MAX Duty = 5218%(X100), DQS PI = 22
7236 04:50:44.599082 [0] MIN Duty = 5062%(X100), DQS PI = 30
7237 04:50:44.602446 [0] AVG Duty = 5140%(X100)
7238 04:50:44.602533
7239 04:50:44.605770 CH0 DQS 0 Duty spec in!! Max-Min= 499%
7240 04:50:44.605857
7241 04:50:44.608907 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7242 04:50:44.612779 [DutyScan_Calibration_Flow] ====Done====
7243 04:50:44.612865
7244 04:50:44.615693 [DutyScan_Calibration_Flow] k_type=3
7245 04:50:44.632856
7246 04:50:44.632998 ==DQM 0 ==
7247 04:50:44.636176 Final DQM duty delay cell = 0
7248 04:50:44.639426 [0] MAX Duty = 5187%(X100), DQS PI = 26
7249 04:50:44.642889 [0] MIN Duty = 4875%(X100), DQS PI = 60
7250 04:50:44.645934 [0] AVG Duty = 5031%(X100)
7251 04:50:44.646019
7252 04:50:44.646083 ==DQM 1 ==
7253 04:50:44.648985 Final DQM duty delay cell = -4
7254 04:50:44.652204 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7255 04:50:44.656028 [-4] MIN Duty = 4813%(X100), DQS PI = 34
7256 04:50:44.658900 [-4] AVG Duty = 4906%(X100)
7257 04:50:44.658993
7258 04:50:44.662346 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7259 04:50:44.662465
7260 04:50:44.665911 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7261 04:50:44.669439 [DutyScan_Calibration_Flow] ====Done====
7262 04:50:44.669524
7263 04:50:44.672113 [DutyScan_Calibration_Flow] k_type=2
7264 04:50:44.690141
7265 04:50:44.690256 ==DQ 0 ==
7266 04:50:44.693461 Final DQ duty delay cell = 0
7267 04:50:44.696799 [0] MAX Duty = 5062%(X100), DQS PI = 24
7268 04:50:44.700219 [0] MIN Duty = 4907%(X100), DQS PI = 0
7269 04:50:44.700309 [0] AVG Duty = 4984%(X100)
7270 04:50:44.703613
7271 04:50:44.703695 ==DQ 1 ==
7272 04:50:44.706749 Final DQ duty delay cell = 0
7273 04:50:44.710230 [0] MAX Duty = 5125%(X100), DQS PI = 6
7274 04:50:44.713509 [0] MIN Duty = 4907%(X100), DQS PI = 34
7275 04:50:44.713593 [0] AVG Duty = 5016%(X100)
7276 04:50:44.713659
7277 04:50:44.716849 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7278 04:50:44.720166
7279 04:50:44.723574 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7280 04:50:44.726850 [DutyScan_Calibration_Flow] ====Done====
7281 04:50:44.726933 ==
7282 04:50:44.730087 Dram Type= 6, Freq= 0, CH_1, rank 0
7283 04:50:44.733167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7284 04:50:44.733251 ==
7285 04:50:44.736353 [Duty_Offset_Calibration]
7286 04:50:44.736436 B0:1 B1:0 CA:0
7287 04:50:44.736502
7288 04:50:44.739532 [DutyScan_Calibration_Flow] k_type=0
7289 04:50:44.749655
7290 04:50:44.749746 ==CLK 0==
7291 04:50:44.752988 Final CLK duty delay cell = -4
7292 04:50:44.756467 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7293 04:50:44.759286 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7294 04:50:44.763011 [-4] AVG Duty = 4922%(X100)
7295 04:50:44.763097
7296 04:50:44.766056 CH1 CLK Duty spec in!! Max-Min= 156%
7297 04:50:44.769625 [DutyScan_Calibration_Flow] ====Done====
7298 04:50:44.769709
7299 04:50:44.772987 [DutyScan_Calibration_Flow] k_type=1
7300 04:50:44.790045
7301 04:50:44.790157 ==DQS 0 ==
7302 04:50:44.793251 Final DQS duty delay cell = 0
7303 04:50:44.796419 [0] MAX Duty = 5094%(X100), DQS PI = 30
7304 04:50:44.799853 [0] MIN Duty = 4844%(X100), DQS PI = 50
7305 04:50:44.799935 [0] AVG Duty = 4969%(X100)
7306 04:50:44.802590
7307 04:50:44.802671 ==DQS 1 ==
7308 04:50:44.806527 Final DQS duty delay cell = 0
7309 04:50:44.809628 [0] MAX Duty = 5249%(X100), DQS PI = 16
7310 04:50:44.812984 [0] MIN Duty = 4969%(X100), DQS PI = 8
7311 04:50:44.813065 [0] AVG Duty = 5109%(X100)
7312 04:50:44.816381
7313 04:50:44.819552 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7314 04:50:44.819626
7315 04:50:44.823169 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7316 04:50:44.826419 [DutyScan_Calibration_Flow] ====Done====
7317 04:50:44.826500
7318 04:50:44.829792 [DutyScan_Calibration_Flow] k_type=3
7319 04:50:44.846192
7320 04:50:44.846323 ==DQM 0 ==
7321 04:50:44.849463 Final DQM duty delay cell = 0
7322 04:50:44.853305 [0] MAX Duty = 5218%(X100), DQS PI = 20
7323 04:50:44.856465 [0] MIN Duty = 4969%(X100), DQS PI = 48
7324 04:50:44.859471 [0] AVG Duty = 5093%(X100)
7325 04:50:44.859549
7326 04:50:44.859611 ==DQM 1 ==
7327 04:50:44.863083 Final DQM duty delay cell = 0
7328 04:50:44.866063 [0] MAX Duty = 5093%(X100), DQS PI = 40
7329 04:50:44.869793 [0] MIN Duty = 4907%(X100), DQS PI = 34
7330 04:50:44.872890 [0] AVG Duty = 5000%(X100)
7331 04:50:44.872965
7332 04:50:44.876260 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7333 04:50:44.876384
7334 04:50:44.879560 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7335 04:50:44.882815 [DutyScan_Calibration_Flow] ====Done====
7336 04:50:44.882899
7337 04:50:44.886127 [DutyScan_Calibration_Flow] k_type=2
7338 04:50:44.902462
7339 04:50:44.902582 ==DQ 0 ==
7340 04:50:44.906122 Final DQ duty delay cell = -4
7341 04:50:44.909290 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7342 04:50:44.912730 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7343 04:50:44.915795 [-4] AVG Duty = 4968%(X100)
7344 04:50:44.915877
7345 04:50:44.915941 ==DQ 1 ==
7346 04:50:44.919220 Final DQ duty delay cell = 0
7347 04:50:44.922437 [0] MAX Duty = 5125%(X100), DQS PI = 18
7348 04:50:44.925838 [0] MIN Duty = 4938%(X100), DQS PI = 8
7349 04:50:44.929169 [0] AVG Duty = 5031%(X100)
7350 04:50:44.929251
7351 04:50:44.932498 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7352 04:50:44.932580
7353 04:50:44.935915 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7354 04:50:44.939324 [DutyScan_Calibration_Flow] ====Done====
7355 04:50:44.942673 nWR fixed to 30
7356 04:50:44.942755 [ModeRegInit_LP4] CH0 RK0
7357 04:50:44.945954 [ModeRegInit_LP4] CH0 RK1
7358 04:50:44.949118 [ModeRegInit_LP4] CH1 RK0
7359 04:50:44.952450 [ModeRegInit_LP4] CH1 RK1
7360 04:50:44.952532 match AC timing 5
7361 04:50:44.959349 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7362 04:50:44.962657 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7363 04:50:44.966127 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7364 04:50:44.972160 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7365 04:50:44.975733 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7366 04:50:44.975819 [MiockJmeterHQA]
7367 04:50:44.975884
7368 04:50:44.978913 [DramcMiockJmeter] u1RxGatingPI = 0
7369 04:50:44.982508 0 : 4252, 4027
7370 04:50:44.982593 4 : 4253, 4027
7371 04:50:44.985733 8 : 4257, 4029
7372 04:50:44.985817 12 : 4253, 4027
7373 04:50:44.985884 16 : 4363, 4137
7374 04:50:44.989032 20 : 4363, 4138
7375 04:50:44.989115 24 : 4253, 4026
7376 04:50:44.992271 28 : 4252, 4027
7377 04:50:44.992360 32 : 4253, 4027
7378 04:50:44.995770 36 : 4363, 4137
7379 04:50:44.995853 40 : 4252, 4027
7380 04:50:44.995918 44 : 4253, 4027
7381 04:50:44.999198 48 : 4255, 4029
7382 04:50:44.999281 52 : 4252, 4027
7383 04:50:45.002572 56 : 4252, 4027
7384 04:50:45.002654 60 : 4253, 4027
7385 04:50:45.005920 64 : 4253, 4027
7386 04:50:45.006003 68 : 4253, 4027
7387 04:50:45.009303 72 : 4365, 4140
7388 04:50:45.009386 76 : 4250, 4026
7389 04:50:45.009451 80 : 4255, 4030
7390 04:50:45.012511 84 : 4252, 4030
7391 04:50:45.012593 88 : 4363, 138
7392 04:50:45.015364 92 : 4360, 0
7393 04:50:45.015446 96 : 4250, 0
7394 04:50:45.015511 100 : 4361, 0
7395 04:50:45.018934 104 : 4252, 0
7396 04:50:45.019048 108 : 4363, 0
7397 04:50:45.022004 112 : 4250, 0
7398 04:50:45.022087 116 : 4250, 0
7399 04:50:45.022152 120 : 4250, 0
7400 04:50:45.025603 124 : 4250, 0
7401 04:50:45.025685 128 : 4253, 0
7402 04:50:45.028920 132 : 4250, 0
7403 04:50:45.029002 136 : 4250, 0
7404 04:50:45.029067 140 : 4250, 0
7405 04:50:45.032061 144 : 4250, 0
7406 04:50:45.032143 148 : 4360, 0
7407 04:50:45.032208 152 : 4361, 0
7408 04:50:45.035541 156 : 4252, 0
7409 04:50:45.035623 160 : 4249, 0
7410 04:50:45.038895 164 : 4250, 0
7411 04:50:45.038986 168 : 4250, 0
7412 04:50:45.039084 172 : 4249, 0
7413 04:50:45.042235 176 : 4250, 0
7414 04:50:45.042334 180 : 4253, 0
7415 04:50:45.045491 184 : 4250, 0
7416 04:50:45.045597 188 : 4363, 0
7417 04:50:45.045690 192 : 4250, 0
7418 04:50:45.048861 196 : 4360, 0
7419 04:50:45.048960 200 : 4360, 0
7420 04:50:45.052077 204 : 4250, 1246
7421 04:50:45.052176 208 : 4363, 4111
7422 04:50:45.055287 212 : 4250, 4027
7423 04:50:45.055369 216 : 4250, 4026
7424 04:50:45.055433 220 : 4250, 4026
7425 04:50:45.058650 224 : 4250, 4026
7426 04:50:45.058731 228 : 4254, 4030
7427 04:50:45.062003 232 : 4360, 4137
7428 04:50:45.062084 236 : 4250, 4026
7429 04:50:45.065380 240 : 4250, 4027
7430 04:50:45.065461 244 : 4250, 4026
7431 04:50:45.068879 248 : 4249, 4027
7432 04:50:45.068960 252 : 4361, 4137
7433 04:50:45.072181 256 : 4250, 4027
7434 04:50:45.072296 260 : 4363, 4140
7435 04:50:45.075497 264 : 4249, 4027
7436 04:50:45.075578 268 : 4250, 4026
7437 04:50:45.078709 272 : 4250, 4027
7438 04:50:45.078790 276 : 4250, 4027
7439 04:50:45.081916 280 : 4250, 4026
7440 04:50:45.081998 284 : 4360, 4137
7441 04:50:45.082062 288 : 4250, 4026
7442 04:50:45.085119 292 : 4250, 4027
7443 04:50:45.085200 296 : 4250, 4026
7444 04:50:45.088890 300 : 4250, 4027
7445 04:50:45.088975 304 : 4361, 4137
7446 04:50:45.092183 308 : 4250, 3983
7447 04:50:45.092298 312 : 4363, 2250
7448 04:50:45.095021 316 : 4250, 4
7449 04:50:45.095133
7450 04:50:45.095196 MIOCK jitter meter ch=0
7451 04:50:45.095255
7452 04:50:45.098920 1T = (316-88) = 228 dly cells
7453 04:50:45.105626 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7454 04:50:45.105707 ==
7455 04:50:45.108215 Dram Type= 6, Freq= 0, CH_0, rank 0
7456 04:50:45.111620 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7457 04:50:45.111701 ==
7458 04:50:45.118522 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7459 04:50:45.121777 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7460 04:50:45.125444 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7461 04:50:45.131428 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7462 04:50:45.141763 [CA 0] Center 42 (12~73) winsize 62
7463 04:50:45.144974 [CA 1] Center 42 (12~73) winsize 62
7464 04:50:45.148270 [CA 2] Center 37 (8~67) winsize 60
7465 04:50:45.151561 [CA 3] Center 37 (8~67) winsize 60
7466 04:50:45.154695 [CA 4] Center 36 (6~66) winsize 61
7467 04:50:45.158190 [CA 5] Center 35 (6~64) winsize 59
7468 04:50:45.158275
7469 04:50:45.161531 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7470 04:50:45.161612
7471 04:50:45.164700 [CATrainingPosCal] consider 1 rank data
7472 04:50:45.168167 u2DelayCellTimex100 = 285/100 ps
7473 04:50:45.171516 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7474 04:50:45.178326 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7475 04:50:45.181541 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7476 04:50:45.184758 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7477 04:50:45.187973 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7478 04:50:45.191272 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7479 04:50:45.191354
7480 04:50:45.194493 CA PerBit enable=1, Macro0, CA PI delay=35
7481 04:50:45.194575
7482 04:50:45.197825 [CBTSetCACLKResult] CA Dly = 35
7483 04:50:45.201179 CS Dly: 9 (0~40)
7484 04:50:45.204596 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7485 04:50:45.207918 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7486 04:50:45.207999 ==
7487 04:50:45.211107 Dram Type= 6, Freq= 0, CH_0, rank 1
7488 04:50:45.214475 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7489 04:50:45.217861 ==
7490 04:50:45.221292 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7491 04:50:45.224218 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7492 04:50:45.231319 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7493 04:50:45.234473 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7494 04:50:45.244773 [CA 0] Center 42 (12~73) winsize 62
7495 04:50:45.247763 [CA 1] Center 42 (12~73) winsize 62
7496 04:50:45.251136 [CA 2] Center 38 (8~68) winsize 61
7497 04:50:45.254479 [CA 3] Center 37 (7~67) winsize 61
7498 04:50:45.257826 [CA 4] Center 36 (6~66) winsize 61
7499 04:50:45.261281 [CA 5] Center 35 (5~65) winsize 61
7500 04:50:45.261363
7501 04:50:45.264707 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7502 04:50:45.264790
7503 04:50:45.268148 [CATrainingPosCal] consider 2 rank data
7504 04:50:45.271296 u2DelayCellTimex100 = 285/100 ps
7505 04:50:45.277884 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7506 04:50:45.281291 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7507 04:50:45.284405 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7508 04:50:45.287605 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7509 04:50:45.290935 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7510 04:50:45.294073 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7511 04:50:45.294156
7512 04:50:45.297744 CA PerBit enable=1, Macro0, CA PI delay=35
7513 04:50:45.297826
7514 04:50:45.300812 [CBTSetCACLKResult] CA Dly = 35
7515 04:50:45.304450 CS Dly: 10 (0~42)
7516 04:50:45.307275 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7517 04:50:45.310554 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7518 04:50:45.310637
7519 04:50:45.314347 ----->DramcWriteLeveling(PI) begin...
7520 04:50:45.314431 ==
7521 04:50:45.317539 Dram Type= 6, Freq= 0, CH_0, rank 0
7522 04:50:45.323931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7523 04:50:45.324015 ==
7524 04:50:45.327312 Write leveling (Byte 0): 35 => 35
7525 04:50:45.330660 Write leveling (Byte 1): 27 => 27
7526 04:50:45.330742 DramcWriteLeveling(PI) end<-----
7527 04:50:45.330808
7528 04:50:45.334036 ==
7529 04:50:45.337394 Dram Type= 6, Freq= 0, CH_0, rank 0
7530 04:50:45.340494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7531 04:50:45.340577 ==
7532 04:50:45.344160 [Gating] SW mode calibration
7533 04:50:45.350434 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7534 04:50:45.353994 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7535 04:50:45.360323 1 4 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7536 04:50:45.363730 1 4 4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7537 04:50:45.367129 1 4 8 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (1 1)
7538 04:50:45.373841 1 4 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
7539 04:50:45.377232 1 4 16 | B1->B0 | 2424 3a39 | 0 1 | (0 0) (1 1)
7540 04:50:45.380587 1 4 20 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7541 04:50:45.387240 1 4 24 | B1->B0 | 3434 3837 | 1 1 | (1 1) (0 0)
7542 04:50:45.390295 1 4 28 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7543 04:50:45.393651 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
7544 04:50:45.399993 1 5 4 | B1->B0 | 3434 3939 | 1 1 | (1 1) (1 1)
7545 04:50:45.403603 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
7546 04:50:45.407030 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
7547 04:50:45.413642 1 5 16 | B1->B0 | 3333 2827 | 0 1 | (0 0) (0 0)
7548 04:50:45.417091 1 5 20 | B1->B0 | 2424 2828 | 0 0 | (1 0) (0 0)
7549 04:50:45.420347 1 5 24 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (1 1)
7550 04:50:45.426814 1 5 28 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7551 04:50:45.430533 1 6 0 | B1->B0 | 2323 302f | 0 1 | (0 0) (1 1)
7552 04:50:45.433305 1 6 4 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
7553 04:50:45.436791 1 6 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
7554 04:50:45.443232 1 6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)
7555 04:50:45.447152 1 6 16 | B1->B0 | 2626 4646 | 0 1 | (0 0) (1 1)
7556 04:50:45.450403 1 6 20 | B1->B0 | 4545 4645 | 0 1 | (0 0) (0 0)
7557 04:50:45.456588 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7558 04:50:45.459925 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7559 04:50:45.463503 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7560 04:50:45.469953 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7561 04:50:45.473381 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7562 04:50:45.476697 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7563 04:50:45.483389 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7564 04:50:45.486767 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7565 04:50:45.490126 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7566 04:50:45.496825 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7567 04:50:45.499630 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7568 04:50:45.503456 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7569 04:50:45.509983 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 04:50:45.513318 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 04:50:45.516669 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 04:50:45.523138 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 04:50:45.526261 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 04:50:45.529788 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 04:50:45.536183 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 04:50:45.539727 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 04:50:45.543237 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7578 04:50:45.549895 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7579 04:50:45.553227 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7580 04:50:45.556185 Total UI for P1: 0, mck2ui 16
7581 04:50:45.559795 best dqsien dly found for B0: ( 1, 9, 10)
7582 04:50:45.563022 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7583 04:50:45.566298 Total UI for P1: 0, mck2ui 16
7584 04:50:45.569450 best dqsien dly found for B1: ( 1, 9, 16)
7585 04:50:45.572816 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7586 04:50:45.576022 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
7587 04:50:45.576105
7588 04:50:45.583227 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7589 04:50:45.586523 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
7590 04:50:45.586606 [Gating] SW calibration Done
7591 04:50:45.589832 ==
7592 04:50:45.593240 Dram Type= 6, Freq= 0, CH_0, rank 0
7593 04:50:45.595923 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7594 04:50:45.596006 ==
7595 04:50:45.596070 RX Vref Scan: 0
7596 04:50:45.596131
7597 04:50:45.599253 RX Vref 0 -> 0, step: 1
7598 04:50:45.599334
7599 04:50:45.602739 RX Delay 0 -> 252, step: 8
7600 04:50:45.606081 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7601 04:50:45.609601 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7602 04:50:45.612726 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7603 04:50:45.619590 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7604 04:50:45.622937 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7605 04:50:45.625683 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7606 04:50:45.629085 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7607 04:50:45.632398 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7608 04:50:45.638995 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7609 04:50:45.642881 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7610 04:50:45.645929 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7611 04:50:45.649410 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7612 04:50:45.652614 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7613 04:50:45.658876 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7614 04:50:45.662219 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7615 04:50:45.665510 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7616 04:50:45.665593 ==
7617 04:50:45.668726 Dram Type= 6, Freq= 0, CH_0, rank 0
7618 04:50:45.672354 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7619 04:50:45.672437 ==
7620 04:50:45.675881 DQS Delay:
7621 04:50:45.675963 DQS0 = 0, DQS1 = 0
7622 04:50:45.679103 DQM Delay:
7623 04:50:45.679184 DQM0 = 136, DQM1 = 130
7624 04:50:45.679249 DQ Delay:
7625 04:50:45.685542 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7626 04:50:45.688793 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7627 04:50:45.692259 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7628 04:50:45.695446 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
7629 04:50:45.695527
7630 04:50:45.695592
7631 04:50:45.695652 ==
7632 04:50:45.698764 Dram Type= 6, Freq= 0, CH_0, rank 0
7633 04:50:45.702223 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7634 04:50:45.702305 ==
7635 04:50:45.702369
7636 04:50:45.702429
7637 04:50:45.705679 TX Vref Scan disable
7638 04:50:45.709106 == TX Byte 0 ==
7639 04:50:45.711858 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7640 04:50:45.715148 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7641 04:50:45.719089 == TX Byte 1 ==
7642 04:50:45.722321 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7643 04:50:45.725834 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7644 04:50:45.725916 ==
7645 04:50:45.728800 Dram Type= 6, Freq= 0, CH_0, rank 0
7646 04:50:45.732096 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7647 04:50:45.735384 ==
7648 04:50:45.747530
7649 04:50:45.750882 TX Vref early break, caculate TX vref
7650 04:50:45.754241 TX Vref=16, minBit 0, minWin=23, winSum=379
7651 04:50:45.757159 TX Vref=18, minBit 4, minWin=23, winSum=385
7652 04:50:45.760831 TX Vref=20, minBit 0, minWin=24, winSum=401
7653 04:50:45.763910 TX Vref=22, minBit 1, minWin=24, winSum=406
7654 04:50:45.767288 TX Vref=24, minBit 7, minWin=24, winSum=416
7655 04:50:45.773832 TX Vref=26, minBit 2, minWin=24, winSum=421
7656 04:50:45.777172 TX Vref=28, minBit 1, minWin=25, winSum=424
7657 04:50:45.780548 TX Vref=30, minBit 6, minWin=24, winSum=417
7658 04:50:45.783882 TX Vref=32, minBit 1, minWin=24, winSum=409
7659 04:50:45.787242 TX Vref=34, minBit 6, minWin=23, winSum=395
7660 04:50:45.793658 [TxChooseVref] Worse bit 1, Min win 25, Win sum 424, Final Vref 28
7661 04:50:45.793741
7662 04:50:45.796952 Final TX Range 0 Vref 28
7663 04:50:45.797036
7664 04:50:45.797100 ==
7665 04:50:45.800492 Dram Type= 6, Freq= 0, CH_0, rank 0
7666 04:50:45.803864 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7667 04:50:45.803947 ==
7668 04:50:45.804012
7669 04:50:45.804072
7670 04:50:45.807171 TX Vref Scan disable
7671 04:50:45.813401 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7672 04:50:45.813484 == TX Byte 0 ==
7673 04:50:45.817006 u2DelayCellOfst[0]=10 cells (3 PI)
7674 04:50:45.820300 u2DelayCellOfst[1]=17 cells (5 PI)
7675 04:50:45.823612 u2DelayCellOfst[2]=13 cells (4 PI)
7676 04:50:45.826685 u2DelayCellOfst[3]=10 cells (3 PI)
7677 04:50:45.830468 u2DelayCellOfst[4]=6 cells (2 PI)
7678 04:50:45.833836 u2DelayCellOfst[5]=0 cells (0 PI)
7679 04:50:45.837231 u2DelayCellOfst[6]=17 cells (5 PI)
7680 04:50:45.840458 u2DelayCellOfst[7]=17 cells (5 PI)
7681 04:50:45.843771 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7682 04:50:45.847240 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7683 04:50:45.849981 == TX Byte 1 ==
7684 04:50:45.850064 u2DelayCellOfst[8]=0 cells (0 PI)
7685 04:50:45.853320 u2DelayCellOfst[9]=3 cells (1 PI)
7686 04:50:45.856683 u2DelayCellOfst[10]=10 cells (3 PI)
7687 04:50:45.860060 u2DelayCellOfst[11]=3 cells (1 PI)
7688 04:50:45.863472 u2DelayCellOfst[12]=13 cells (4 PI)
7689 04:50:45.866892 u2DelayCellOfst[13]=10 cells (3 PI)
7690 04:50:45.870284 u2DelayCellOfst[14]=17 cells (5 PI)
7691 04:50:45.873412 u2DelayCellOfst[15]=10 cells (3 PI)
7692 04:50:45.876652 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7693 04:50:45.883229 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7694 04:50:45.883314 DramC Write-DBI on
7695 04:50:45.883380 ==
7696 04:50:45.886377 Dram Type= 6, Freq= 0, CH_0, rank 0
7697 04:50:45.893085 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7698 04:50:45.893168 ==
7699 04:50:45.893234
7700 04:50:45.893294
7701 04:50:45.893352 TX Vref Scan disable
7702 04:50:45.896824 == TX Byte 0 ==
7703 04:50:45.900038 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7704 04:50:45.903329 == TX Byte 1 ==
7705 04:50:45.907136 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7706 04:50:45.910507 DramC Write-DBI off
7707 04:50:45.910591
7708 04:50:45.910655 [DATLAT]
7709 04:50:45.910716 Freq=1600, CH0 RK0
7710 04:50:45.910775
7711 04:50:45.913909 DATLAT Default: 0xf
7712 04:50:45.913991 0, 0xFFFF, sum = 0
7713 04:50:45.916566 1, 0xFFFF, sum = 0
7714 04:50:45.919934 2, 0xFFFF, sum = 0
7715 04:50:45.920049 3, 0xFFFF, sum = 0
7716 04:50:45.923133 4, 0xFFFF, sum = 0
7717 04:50:45.923250 5, 0xFFFF, sum = 0
7718 04:50:45.926504 6, 0xFFFF, sum = 0
7719 04:50:45.926604 7, 0xFFFF, sum = 0
7720 04:50:45.929741 8, 0xFFFF, sum = 0
7721 04:50:45.929861 9, 0xFFFF, sum = 0
7722 04:50:45.933531 10, 0xFFFF, sum = 0
7723 04:50:45.933615 11, 0xFFFF, sum = 0
7724 04:50:45.936622 12, 0xFFFF, sum = 0
7725 04:50:45.936706 13, 0xFFFF, sum = 0
7726 04:50:45.940144 14, 0x0, sum = 1
7727 04:50:45.940255 15, 0x0, sum = 2
7728 04:50:45.943572 16, 0x0, sum = 3
7729 04:50:45.943655 17, 0x0, sum = 4
7730 04:50:45.946635 best_step = 15
7731 04:50:45.946717
7732 04:50:45.946782 ==
7733 04:50:45.950063 Dram Type= 6, Freq= 0, CH_0, rank 0
7734 04:50:45.953067 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7735 04:50:45.953149 ==
7736 04:50:45.956790 RX Vref Scan: 1
7737 04:50:45.956872
7738 04:50:45.956937 Set Vref Range= 24 -> 127
7739 04:50:45.956997
7740 04:50:45.960164 RX Vref 24 -> 127, step: 1
7741 04:50:45.960247
7742 04:50:45.963554 RX Delay 19 -> 252, step: 4
7743 04:50:45.963635
7744 04:50:45.966807 Set Vref, RX VrefLevel [Byte0]: 24
7745 04:50:45.970096 [Byte1]: 24
7746 04:50:45.970178
7747 04:50:45.973487 Set Vref, RX VrefLevel [Byte0]: 25
7748 04:50:45.976805 [Byte1]: 25
7749 04:50:45.976887
7750 04:50:45.980196 Set Vref, RX VrefLevel [Byte0]: 26
7751 04:50:45.983500 [Byte1]: 26
7752 04:50:45.987318
7753 04:50:45.987399 Set Vref, RX VrefLevel [Byte0]: 27
7754 04:50:45.990400 [Byte1]: 27
7755 04:50:45.994578
7756 04:50:45.994660 Set Vref, RX VrefLevel [Byte0]: 28
7757 04:50:45.998220 [Byte1]: 28
7758 04:50:46.002632
7759 04:50:46.002709 Set Vref, RX VrefLevel [Byte0]: 29
7760 04:50:46.005789 [Byte1]: 29
7761 04:50:46.010234
7762 04:50:46.010320 Set Vref, RX VrefLevel [Byte0]: 30
7763 04:50:46.013341 [Byte1]: 30
7764 04:50:46.017428
7765 04:50:46.017502 Set Vref, RX VrefLevel [Byte0]: 31
7766 04:50:46.020819 [Byte1]: 31
7767 04:50:46.025422
7768 04:50:46.025503 Set Vref, RX VrefLevel [Byte0]: 32
7769 04:50:46.028607 [Byte1]: 32
7770 04:50:46.032644
7771 04:50:46.032725 Set Vref, RX VrefLevel [Byte0]: 33
7772 04:50:46.035925 [Byte1]: 33
7773 04:50:46.040491
7774 04:50:46.040572 Set Vref, RX VrefLevel [Byte0]: 34
7775 04:50:46.043766 [Byte1]: 34
7776 04:50:46.048158
7777 04:50:46.048239 Set Vref, RX VrefLevel [Byte0]: 35
7778 04:50:46.050908 [Byte1]: 35
7779 04:50:46.055702
7780 04:50:46.055783 Set Vref, RX VrefLevel [Byte0]: 36
7781 04:50:46.058897 [Byte1]: 36
7782 04:50:46.062825
7783 04:50:46.062907 Set Vref, RX VrefLevel [Byte0]: 37
7784 04:50:46.066024 [Byte1]: 37
7785 04:50:46.070781
7786 04:50:46.070862 Set Vref, RX VrefLevel [Byte0]: 38
7787 04:50:46.074188 [Byte1]: 38
7788 04:50:46.077971
7789 04:50:46.078053 Set Vref, RX VrefLevel [Byte0]: 39
7790 04:50:46.081711 [Byte1]: 39
7791 04:50:46.085761
7792 04:50:46.085842 Set Vref, RX VrefLevel [Byte0]: 40
7793 04:50:46.089165 [Byte1]: 40
7794 04:50:46.093237
7795 04:50:46.093318 Set Vref, RX VrefLevel [Byte0]: 41
7796 04:50:46.096405 [Byte1]: 41
7797 04:50:46.100721
7798 04:50:46.100803 Set Vref, RX VrefLevel [Byte0]: 42
7799 04:50:46.104461 [Byte1]: 42
7800 04:50:46.108406
7801 04:50:46.108514 Set Vref, RX VrefLevel [Byte0]: 43
7802 04:50:46.111692 [Byte1]: 43
7803 04:50:46.115909
7804 04:50:46.115990 Set Vref, RX VrefLevel [Byte0]: 44
7805 04:50:46.119202 [Byte1]: 44
7806 04:50:46.123877
7807 04:50:46.123961 Set Vref, RX VrefLevel [Byte0]: 45
7808 04:50:46.127200 [Byte1]: 45
7809 04:50:46.131066
7810 04:50:46.131148 Set Vref, RX VrefLevel [Byte0]: 46
7811 04:50:46.134571 [Byte1]: 46
7812 04:50:46.139233
7813 04:50:46.139313 Set Vref, RX VrefLevel [Byte0]: 47
7814 04:50:46.141773 [Byte1]: 47
7815 04:50:46.146530
7816 04:50:46.146610 Set Vref, RX VrefLevel [Byte0]: 48
7817 04:50:46.149943 [Byte1]: 48
7818 04:50:46.153944
7819 04:50:46.154024 Set Vref, RX VrefLevel [Byte0]: 49
7820 04:50:46.157000 [Byte1]: 49
7821 04:50:46.161418
7822 04:50:46.161512 Set Vref, RX VrefLevel [Byte0]: 50
7823 04:50:46.164895 [Byte1]: 50
7824 04:50:46.169057
7825 04:50:46.169138 Set Vref, RX VrefLevel [Byte0]: 51
7826 04:50:46.172117 [Byte1]: 51
7827 04:50:46.176732
7828 04:50:46.176813 Set Vref, RX VrefLevel [Byte0]: 52
7829 04:50:46.179610 [Byte1]: 52
7830 04:50:46.184344
7831 04:50:46.184425 Set Vref, RX VrefLevel [Byte0]: 53
7832 04:50:46.187551 [Byte1]: 53
7833 04:50:46.192211
7834 04:50:46.192357 Set Vref, RX VrefLevel [Byte0]: 54
7835 04:50:46.194874 [Byte1]: 54
7836 04:50:46.199516
7837 04:50:46.199597 Set Vref, RX VrefLevel [Byte0]: 55
7838 04:50:46.202866 [Byte1]: 55
7839 04:50:46.206706
7840 04:50:46.206788 Set Vref, RX VrefLevel [Byte0]: 56
7841 04:50:46.210394 [Byte1]: 56
7842 04:50:46.214204
7843 04:50:46.214289 Set Vref, RX VrefLevel [Byte0]: 57
7844 04:50:46.217589 [Byte1]: 57
7845 04:50:46.222249
7846 04:50:46.222338 Set Vref, RX VrefLevel [Byte0]: 58
7847 04:50:46.225324 [Byte1]: 58
7848 04:50:46.229671
7849 04:50:46.229805 Set Vref, RX VrefLevel [Byte0]: 59
7850 04:50:46.232695 [Byte1]: 59
7851 04:50:46.237287
7852 04:50:46.237396 Set Vref, RX VrefLevel [Byte0]: 60
7853 04:50:46.240127 [Byte1]: 60
7854 04:50:46.245114
7855 04:50:46.245197 Set Vref, RX VrefLevel [Byte0]: 61
7856 04:50:46.248229 [Byte1]: 61
7857 04:50:46.252165
7858 04:50:46.252268 Set Vref, RX VrefLevel [Byte0]: 62
7859 04:50:46.255586 [Byte1]: 62
7860 04:50:46.260225
7861 04:50:46.260362 Set Vref, RX VrefLevel [Byte0]: 63
7862 04:50:46.263030 [Byte1]: 63
7863 04:50:46.267251
7864 04:50:46.267332 Set Vref, RX VrefLevel [Byte0]: 64
7865 04:50:46.270511 [Byte1]: 64
7866 04:50:46.275234
7867 04:50:46.275315 Set Vref, RX VrefLevel [Byte0]: 65
7868 04:50:46.278589 [Byte1]: 65
7869 04:50:46.282544
7870 04:50:46.282625 Set Vref, RX VrefLevel [Byte0]: 66
7871 04:50:46.285890 [Byte1]: 66
7872 04:50:46.289937
7873 04:50:46.290019 Set Vref, RX VrefLevel [Byte0]: 67
7874 04:50:46.293291 [Byte1]: 67
7875 04:50:46.297897
7876 04:50:46.297977 Set Vref, RX VrefLevel [Byte0]: 68
7877 04:50:46.301392 [Byte1]: 68
7878 04:50:46.305790
7879 04:50:46.305871 Set Vref, RX VrefLevel [Byte0]: 69
7880 04:50:46.309081 [Byte1]: 69
7881 04:50:46.312935
7882 04:50:46.313017 Set Vref, RX VrefLevel [Byte0]: 70
7883 04:50:46.316074 [Byte1]: 70
7884 04:50:46.320699
7885 04:50:46.320780 Set Vref, RX VrefLevel [Byte0]: 71
7886 04:50:46.323816 [Byte1]: 71
7887 04:50:46.327787
7888 04:50:46.327869 Set Vref, RX VrefLevel [Byte0]: 72
7889 04:50:46.331445 [Byte1]: 72
7890 04:50:46.335438
7891 04:50:46.335542 Set Vref, RX VrefLevel [Byte0]: 73
7892 04:50:46.339104 [Byte1]: 73
7893 04:50:46.342941
7894 04:50:46.343022 Set Vref, RX VrefLevel [Byte0]: 74
7895 04:50:46.346249 [Byte1]: 74
7896 04:50:46.350701
7897 04:50:46.350782 Set Vref, RX VrefLevel [Byte0]: 75
7898 04:50:46.353840 [Byte1]: 75
7899 04:50:46.358497
7900 04:50:46.358579 Set Vref, RX VrefLevel [Byte0]: 76
7901 04:50:46.361983 [Byte1]: 76
7902 04:50:46.366050
7903 04:50:46.366143 Final RX Vref Byte 0 = 60 to rank0
7904 04:50:46.369380 Final RX Vref Byte 1 = 59 to rank0
7905 04:50:46.372487 Final RX Vref Byte 0 = 60 to rank1
7906 04:50:46.375694 Final RX Vref Byte 1 = 59 to rank1==
7907 04:50:46.379000 Dram Type= 6, Freq= 0, CH_0, rank 0
7908 04:50:46.385644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7909 04:50:46.385723 ==
7910 04:50:46.385788 DQS Delay:
7911 04:50:46.385848 DQS0 = 0, DQS1 = 0
7912 04:50:46.389034 DQM Delay:
7913 04:50:46.389111 DQM0 = 134, DQM1 = 127
7914 04:50:46.392299 DQ Delay:
7915 04:50:46.395738 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7916 04:50:46.399097 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7917 04:50:46.402407 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7918 04:50:46.405749 DQ12 =130, DQ13 =132, DQ14 =138, DQ15 =134
7919 04:50:46.405822
7920 04:50:46.405883
7921 04:50:46.405940
7922 04:50:46.409125 [DramC_TX_OE_Calibration] TA2
7923 04:50:46.412515 Original DQ_B0 (3 6) =30, OEN = 27
7924 04:50:46.415908 Original DQ_B1 (3 6) =30, OEN = 27
7925 04:50:46.419247 24, 0x0, End_B0=24 End_B1=24
7926 04:50:46.419330 25, 0x0, End_B0=25 End_B1=25
7927 04:50:46.422563 26, 0x0, End_B0=26 End_B1=26
7928 04:50:46.425942 27, 0x0, End_B0=27 End_B1=27
7929 04:50:46.429248 28, 0x0, End_B0=28 End_B1=28
7930 04:50:46.432276 29, 0x0, End_B0=29 End_B1=29
7931 04:50:46.432419 30, 0x0, End_B0=30 End_B1=30
7932 04:50:46.435338 31, 0x4141, End_B0=30 End_B1=30
7933 04:50:46.439112 Byte0 end_step=30 best_step=27
7934 04:50:46.442195 Byte1 end_step=30 best_step=27
7935 04:50:46.445730 Byte0 TX OE(2T, 0.5T) = (3, 3)
7936 04:50:46.448960 Byte1 TX OE(2T, 0.5T) = (3, 3)
7937 04:50:46.449041
7938 04:50:46.449105
7939 04:50:46.455634 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
7940 04:50:46.458886 CH0 RK0: MR19=303, MR18=2622
7941 04:50:46.465809 CH0_RK0: MR19=0x303, MR18=0x2622, DQSOSC=390, MR23=63, INC=24, DEC=16
7942 04:50:46.465895
7943 04:50:46.468590 ----->DramcWriteLeveling(PI) begin...
7944 04:50:46.468673 ==
7945 04:50:46.472379 Dram Type= 6, Freq= 0, CH_0, rank 1
7946 04:50:46.475188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7947 04:50:46.475271 ==
7948 04:50:46.478851 Write leveling (Byte 0): 36 => 36
7949 04:50:46.482089 Write leveling (Byte 1): 29 => 29
7950 04:50:46.485086 DramcWriteLeveling(PI) end<-----
7951 04:50:46.485167
7952 04:50:46.485231 ==
7953 04:50:46.488756 Dram Type= 6, Freq= 0, CH_0, rank 1
7954 04:50:46.492091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7955 04:50:46.492173 ==
7956 04:50:46.495198 [Gating] SW mode calibration
7957 04:50:46.502048 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7958 04:50:46.508948 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7959 04:50:46.512119 1 4 0 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
7960 04:50:46.515589 1 4 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7961 04:50:46.521685 1 4 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7962 04:50:46.524966 1 4 12 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7963 04:50:46.528407 1 4 16 | B1->B0 | 2d2d 3938 | 1 1 | (1 1) (0 0)
7964 04:50:46.535029 1 4 20 | B1->B0 | 3434 3838 | 1 1 | (1 1) (0 0)
7965 04:50:46.538604 1 4 24 | B1->B0 | 3434 3939 | 1 1 | (1 1) (0 0)
7966 04:50:46.541807 1 4 28 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7967 04:50:46.548785 1 5 0 | B1->B0 | 3434 3838 | 1 1 | (1 1) (1 1)
7968 04:50:46.552180 1 5 4 | B1->B0 | 3434 3838 | 1 1 | (1 1) (1 1)
7969 04:50:46.554834 1 5 8 | B1->B0 | 3434 3939 | 1 1 | (1 1) (1 1)
7970 04:50:46.561583 1 5 12 | B1->B0 | 3434 2f2e | 1 1 | (1 0) (0 0)
7971 04:50:46.564740 1 5 16 | B1->B0 | 2d2d 2e2d | 1 1 | (1 0) (1 0)
7972 04:50:46.568108 1 5 20 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7973 04:50:46.575110 1 5 24 | B1->B0 | 2323 2726 | 0 1 | (0 0) (1 1)
7974 04:50:46.578066 1 5 28 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7975 04:50:46.581855 1 6 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7976 04:50:46.588184 1 6 4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7977 04:50:46.591812 1 6 8 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7978 04:50:46.594945 1 6 12 | B1->B0 | 2727 3c3c | 0 1 | (0 0) (0 0)
7979 04:50:46.601877 1 6 16 | B1->B0 | 3c3c 4645 | 0 1 | (0 0) (0 0)
7980 04:50:46.605062 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7981 04:50:46.608241 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7982 04:50:46.614448 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7983 04:50:46.618074 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7984 04:50:46.621308 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7985 04:50:46.628099 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7986 04:50:46.631460 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7987 04:50:46.634888 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7988 04:50:46.641661 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 04:50:46.645103 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 04:50:46.648393 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 04:50:46.654968 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 04:50:46.658366 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 04:50:46.661672 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 04:50:46.664283 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 04:50:46.671565 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 04:50:46.674927 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 04:50:46.678153 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 04:50:46.684456 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 04:50:46.687856 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 04:50:46.691247 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 04:50:46.697973 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 04:50:46.701183 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8003 04:50:46.704574 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8004 04:50:46.707615 Total UI for P1: 0, mck2ui 16
8005 04:50:46.711160 best dqsien dly found for B0: ( 1, 9, 12)
8006 04:50:46.714546 Total UI for P1: 0, mck2ui 16
8007 04:50:46.717776 best dqsien dly found for B1: ( 1, 9, 12)
8008 04:50:46.721062 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8009 04:50:46.724480 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8010 04:50:46.724567
8011 04:50:46.731348 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8012 04:50:46.734085 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8013 04:50:46.737509 [Gating] SW calibration Done
8014 04:50:46.737591 ==
8015 04:50:46.741051 Dram Type= 6, Freq= 0, CH_0, rank 1
8016 04:50:46.744393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8017 04:50:46.744474 ==
8018 04:50:46.744538 RX Vref Scan: 0
8019 04:50:46.744598
8020 04:50:46.747417 RX Vref 0 -> 0, step: 1
8021 04:50:46.747498
8022 04:50:46.751430 RX Delay 0 -> 252, step: 8
8023 04:50:46.754070 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8024 04:50:46.757636 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8025 04:50:46.764421 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8026 04:50:46.767660 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8027 04:50:46.770979 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8028 04:50:46.774253 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8029 04:50:46.777484 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8030 04:50:46.780784 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8031 04:50:46.787305 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8032 04:50:46.791101 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8033 04:50:46.794376 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8034 04:50:46.797725 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8035 04:50:46.804216 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8036 04:50:46.807630 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8037 04:50:46.811065 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8038 04:50:46.813727 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8039 04:50:46.813809 ==
8040 04:50:46.817416 Dram Type= 6, Freq= 0, CH_0, rank 1
8041 04:50:46.824217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8042 04:50:46.824373 ==
8043 04:50:46.824467 DQS Delay:
8044 04:50:46.824555 DQS0 = 0, DQS1 = 0
8045 04:50:46.827380 DQM Delay:
8046 04:50:46.827464 DQM0 = 137, DQM1 = 129
8047 04:50:46.830888 DQ Delay:
8048 04:50:46.834116 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8049 04:50:46.837344 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8050 04:50:46.840630 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8051 04:50:46.843947 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8052 04:50:46.844030
8053 04:50:46.844117
8054 04:50:46.844215 ==
8055 04:50:46.847101 Dram Type= 6, Freq= 0, CH_0, rank 1
8056 04:50:46.850820 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8057 04:50:46.850904 ==
8058 04:50:46.854247
8059 04:50:46.854330
8060 04:50:46.854414 TX Vref Scan disable
8061 04:50:46.857002 == TX Byte 0 ==
8062 04:50:46.860451 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8063 04:50:46.863708 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8064 04:50:46.867332 == TX Byte 1 ==
8065 04:50:46.870747 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8066 04:50:46.873999 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8067 04:50:46.874084 ==
8068 04:50:46.877124 Dram Type= 6, Freq= 0, CH_0, rank 1
8069 04:50:46.883994 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8070 04:50:46.884081 ==
8071 04:50:46.896436
8072 04:50:46.899590 TX Vref early break, caculate TX vref
8073 04:50:46.902949 TX Vref=16, minBit 1, minWin=21, winSum=388
8074 04:50:46.906317 TX Vref=18, minBit 1, minWin=23, winSum=395
8075 04:50:46.909737 TX Vref=20, minBit 0, minWin=24, winSum=406
8076 04:50:46.913093 TX Vref=22, minBit 3, minWin=24, winSum=411
8077 04:50:46.916472 TX Vref=24, minBit 1, minWin=25, winSum=418
8078 04:50:46.923176 TX Vref=26, minBit 1, minWin=25, winSum=430
8079 04:50:46.926400 TX Vref=28, minBit 4, minWin=24, winSum=423
8080 04:50:46.929770 TX Vref=30, minBit 1, minWin=25, winSum=420
8081 04:50:46.932798 TX Vref=32, minBit 0, minWin=25, winSum=410
8082 04:50:46.936638 TX Vref=34, minBit 0, minWin=24, winSum=396
8083 04:50:46.943129 [TxChooseVref] Worse bit 1, Min win 25, Win sum 430, Final Vref 26
8084 04:50:46.943213
8085 04:50:46.946198 Final TX Range 0 Vref 26
8086 04:50:46.946300
8087 04:50:46.946388 ==
8088 04:50:46.949422 Dram Type= 6, Freq= 0, CH_0, rank 1
8089 04:50:46.952872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8090 04:50:46.952955 ==
8091 04:50:46.953019
8092 04:50:46.953079
8093 04:50:46.956198 TX Vref Scan disable
8094 04:50:46.962710 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8095 04:50:46.962799 == TX Byte 0 ==
8096 04:50:46.965799 u2DelayCellOfst[0]=13 cells (4 PI)
8097 04:50:46.969398 u2DelayCellOfst[1]=17 cells (5 PI)
8098 04:50:46.972851 u2DelayCellOfst[2]=10 cells (3 PI)
8099 04:50:46.975931 u2DelayCellOfst[3]=13 cells (4 PI)
8100 04:50:46.979513 u2DelayCellOfst[4]=10 cells (3 PI)
8101 04:50:46.982949 u2DelayCellOfst[5]=0 cells (0 PI)
8102 04:50:46.986025 u2DelayCellOfst[6]=20 cells (6 PI)
8103 04:50:46.989439 u2DelayCellOfst[7]=17 cells (5 PI)
8104 04:50:46.992838 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8105 04:50:46.996311 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8106 04:50:46.999264 == TX Byte 1 ==
8107 04:50:46.999347 u2DelayCellOfst[8]=0 cells (0 PI)
8108 04:50:47.002437 u2DelayCellOfst[9]=0 cells (0 PI)
8109 04:50:47.006096 u2DelayCellOfst[10]=6 cells (2 PI)
8110 04:50:47.009151 u2DelayCellOfst[11]=6 cells (2 PI)
8111 04:50:47.012572 u2DelayCellOfst[12]=13 cells (4 PI)
8112 04:50:47.015919 u2DelayCellOfst[13]=10 cells (3 PI)
8113 04:50:47.019217 u2DelayCellOfst[14]=13 cells (4 PI)
8114 04:50:47.022588 u2DelayCellOfst[15]=10 cells (3 PI)
8115 04:50:47.025933 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8116 04:50:47.032473 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8117 04:50:47.032557 DramC Write-DBI on
8118 04:50:47.032623 ==
8119 04:50:47.035790 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 04:50:47.042256 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 04:50:47.042335 ==
8122 04:50:47.042399
8123 04:50:47.042458
8124 04:50:47.042516 TX Vref Scan disable
8125 04:50:47.045893 == TX Byte 0 ==
8126 04:50:47.049609 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8127 04:50:47.052575 == TX Byte 1 ==
8128 04:50:47.055710 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8129 04:50:47.059558 DramC Write-DBI off
8130 04:50:47.059640
8131 04:50:47.059705 [DATLAT]
8132 04:50:47.059766 Freq=1600, CH0 RK1
8133 04:50:47.059825
8134 04:50:47.062865 DATLAT Default: 0xf
8135 04:50:47.062943 0, 0xFFFF, sum = 0
8136 04:50:47.065647 1, 0xFFFF, sum = 0
8137 04:50:47.068955 2, 0xFFFF, sum = 0
8138 04:50:47.069038 3, 0xFFFF, sum = 0
8139 04:50:47.072942 4, 0xFFFF, sum = 0
8140 04:50:47.073025 5, 0xFFFF, sum = 0
8141 04:50:47.075884 6, 0xFFFF, sum = 0
8142 04:50:47.075968 7, 0xFFFF, sum = 0
8143 04:50:47.079385 8, 0xFFFF, sum = 0
8144 04:50:47.079469 9, 0xFFFF, sum = 0
8145 04:50:47.082485 10, 0xFFFF, sum = 0
8146 04:50:47.082570 11, 0xFFFF, sum = 0
8147 04:50:47.085753 12, 0xFFFF, sum = 0
8148 04:50:47.085837 13, 0xFFFF, sum = 0
8149 04:50:47.089004 14, 0x0, sum = 1
8150 04:50:47.089088 15, 0x0, sum = 2
8151 04:50:47.092306 16, 0x0, sum = 3
8152 04:50:47.092422 17, 0x0, sum = 4
8153 04:50:47.095586 best_step = 15
8154 04:50:47.095668
8155 04:50:47.095732 ==
8156 04:50:47.098797 Dram Type= 6, Freq= 0, CH_0, rank 1
8157 04:50:47.102338 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8158 04:50:47.102449 ==
8159 04:50:47.105625 RX Vref Scan: 0
8160 04:50:47.105711
8161 04:50:47.105778 RX Vref 0 -> 0, step: 1
8162 04:50:47.105840
8163 04:50:47.109349 RX Delay 19 -> 252, step: 4
8164 04:50:47.112246 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8165 04:50:47.119313 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8166 04:50:47.122284 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8167 04:50:47.125870 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8168 04:50:47.129122 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8169 04:50:47.132605 iDelay=191, Bit 5, Center 126 (75 ~ 178) 104
8170 04:50:47.139242 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8171 04:50:47.142601 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8172 04:50:47.145866 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8173 04:50:47.149276 iDelay=191, Bit 9, Center 116 (63 ~ 170) 108
8174 04:50:47.151942 iDelay=191, Bit 10, Center 130 (79 ~ 182) 104
8175 04:50:47.158689 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8176 04:50:47.161836 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8177 04:50:47.165247 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8178 04:50:47.168708 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8179 04:50:47.171772 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8180 04:50:47.175194 ==
8181 04:50:47.178614 Dram Type= 6, Freq= 0, CH_0, rank 1
8182 04:50:47.181935 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8183 04:50:47.182019 ==
8184 04:50:47.182084 DQS Delay:
8185 04:50:47.185134 DQS0 = 0, DQS1 = 0
8186 04:50:47.185217 DQM Delay:
8187 04:50:47.188702 DQM0 = 134, DQM1 = 127
8188 04:50:47.188785 DQ Delay:
8189 04:50:47.192208 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8190 04:50:47.195264 DQ4 =136, DQ5 =126, DQ6 =140, DQ7 =140
8191 04:50:47.198740 DQ8 =118, DQ9 =116, DQ10 =130, DQ11 =118
8192 04:50:47.201954 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8193 04:50:47.202036
8194 04:50:47.202101
8195 04:50:47.202161
8196 04:50:47.205323 [DramC_TX_OE_Calibration] TA2
8197 04:50:47.208394 Original DQ_B0 (3 6) =30, OEN = 27
8198 04:50:47.211713 Original DQ_B1 (3 6) =30, OEN = 27
8199 04:50:47.215626 24, 0x0, End_B0=24 End_B1=24
8200 04:50:47.218316 25, 0x0, End_B0=25 End_B1=25
8201 04:50:47.218401 26, 0x0, End_B0=26 End_B1=26
8202 04:50:47.222261 27, 0x0, End_B0=27 End_B1=27
8203 04:50:47.224953 28, 0x0, End_B0=28 End_B1=28
8204 04:50:47.228784 29, 0x0, End_B0=29 End_B1=29
8205 04:50:47.231864 30, 0x0, End_B0=30 End_B1=30
8206 04:50:47.231947 31, 0x4141, End_B0=30 End_B1=30
8207 04:50:47.235381 Byte0 end_step=30 best_step=27
8208 04:50:47.238331 Byte1 end_step=30 best_step=27
8209 04:50:47.242064 Byte0 TX OE(2T, 0.5T) = (3, 3)
8210 04:50:47.245480 Byte1 TX OE(2T, 0.5T) = (3, 3)
8211 04:50:47.245563
8212 04:50:47.245628
8213 04:50:47.251531 [DQSOSCAuto] RK1, (LSB)MR18= 0x220a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8214 04:50:47.254949 CH0 RK1: MR19=303, MR18=220A
8215 04:50:47.261656 CH0_RK1: MR19=0x303, MR18=0x220A, DQSOSC=392, MR23=63, INC=24, DEC=16
8216 04:50:47.265154 [RxdqsGatingPostProcess] freq 1600
8217 04:50:47.272045 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8218 04:50:47.272133 best DQS0 dly(2T, 0.5T) = (1, 1)
8219 04:50:47.275265 best DQS1 dly(2T, 0.5T) = (1, 1)
8220 04:50:47.278450 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8221 04:50:47.281961 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8222 04:50:47.284935 best DQS0 dly(2T, 0.5T) = (1, 1)
8223 04:50:47.288183 best DQS1 dly(2T, 0.5T) = (1, 1)
8224 04:50:47.291539 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8225 04:50:47.294819 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8226 04:50:47.298031 Pre-setting of DQS Precalculation
8227 04:50:47.301553 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8228 04:50:47.301636 ==
8229 04:50:47.305102 Dram Type= 6, Freq= 0, CH_1, rank 0
8230 04:50:47.311595 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8231 04:50:47.311679 ==
8232 04:50:47.314646 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8233 04:50:47.321837 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8234 04:50:47.325121 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8235 04:50:47.331175 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8236 04:50:47.339118 [CA 0] Center 42 (12~72) winsize 61
8237 04:50:47.342425 [CA 1] Center 42 (13~72) winsize 60
8238 04:50:47.346047 [CA 2] Center 39 (10~69) winsize 60
8239 04:50:47.348809 [CA 3] Center 38 (9~67) winsize 59
8240 04:50:47.352461 [CA 4] Center 38 (9~68) winsize 60
8241 04:50:47.355402 [CA 5] Center 37 (8~67) winsize 60
8242 04:50:47.355482
8243 04:50:47.358883 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8244 04:50:47.358980
8245 04:50:47.362211 [CATrainingPosCal] consider 1 rank data
8246 04:50:47.365728 u2DelayCellTimex100 = 285/100 ps
8247 04:50:47.369141 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8248 04:50:47.375585 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8249 04:50:47.379029 CA2 delay=39 (10~69),Diff = 2 PI (6 cell)
8250 04:50:47.382342 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8251 04:50:47.385553 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8252 04:50:47.388621 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8253 04:50:47.388703
8254 04:50:47.392305 CA PerBit enable=1, Macro0, CA PI delay=37
8255 04:50:47.392388
8256 04:50:47.395412 [CBTSetCACLKResult] CA Dly = 37
8257 04:50:47.398790 CS Dly: 11 (0~42)
8258 04:50:47.402474 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8259 04:50:47.405895 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8260 04:50:47.405976 ==
8261 04:50:47.408871 Dram Type= 6, Freq= 0, CH_1, rank 1
8262 04:50:47.412505 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8263 04:50:47.412591 ==
8264 04:50:47.418761 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8265 04:50:47.422058 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8266 04:50:47.428820 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8267 04:50:47.431888 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8268 04:50:47.442683 [CA 0] Center 42 (12~72) winsize 61
8269 04:50:47.445383 [CA 1] Center 42 (12~72) winsize 61
8270 04:50:47.448623 [CA 2] Center 38 (9~68) winsize 60
8271 04:50:47.451954 [CA 3] Center 38 (8~68) winsize 61
8272 04:50:47.455227 [CA 4] Center 38 (8~68) winsize 61
8273 04:50:47.459097 [CA 5] Center 36 (7~66) winsize 60
8274 04:50:47.459206
8275 04:50:47.462287 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8276 04:50:47.462370
8277 04:50:47.465834 [CATrainingPosCal] consider 2 rank data
8278 04:50:47.469106 u2DelayCellTimex100 = 285/100 ps
8279 04:50:47.472525 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8280 04:50:47.478973 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8281 04:50:47.482373 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8282 04:50:47.485631 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8283 04:50:47.488467 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8284 04:50:47.491873 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8285 04:50:47.491955
8286 04:50:47.495075 CA PerBit enable=1, Macro0, CA PI delay=37
8287 04:50:47.495158
8288 04:50:47.498426 [CBTSetCACLKResult] CA Dly = 37
8289 04:50:47.501762 CS Dly: 12 (0~44)
8290 04:50:47.505021 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8291 04:50:47.508766 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8292 04:50:47.508847
8293 04:50:47.511706 ----->DramcWriteLeveling(PI) begin...
8294 04:50:47.511789 ==
8295 04:50:47.515039 Dram Type= 6, Freq= 0, CH_1, rank 0
8296 04:50:47.521476 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8297 04:50:47.521584 ==
8298 04:50:47.524994 Write leveling (Byte 0): 24 => 24
8299 04:50:47.528232 Write leveling (Byte 1): 26 => 26
8300 04:50:47.528355 DramcWriteLeveling(PI) end<-----
8301 04:50:47.528421
8302 04:50:47.531416 ==
8303 04:50:47.535131 Dram Type= 6, Freq= 0, CH_1, rank 0
8304 04:50:47.538102 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8305 04:50:47.538212 ==
8306 04:50:47.541871 [Gating] SW mode calibration
8307 04:50:47.548652 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8308 04:50:47.551447 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8309 04:50:47.558144 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8310 04:50:47.562102 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8311 04:50:47.564718 1 4 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8312 04:50:47.571407 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8313 04:50:47.574556 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8314 04:50:47.578130 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8315 04:50:47.585276 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8316 04:50:47.588280 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8317 04:50:47.591519 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8318 04:50:47.598197 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8319 04:50:47.601497 1 5 8 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (0 0)
8320 04:50:47.604815 1 5 12 | B1->B0 | 2929 2323 | 0 0 | (0 1) (1 0)
8321 04:50:47.611679 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8322 04:50:47.614987 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 04:50:47.618263 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8324 04:50:47.624468 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8325 04:50:47.628193 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8326 04:50:47.631101 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8327 04:50:47.637625 1 6 8 | B1->B0 | 2424 3434 | 0 1 | (0 0) (0 0)
8328 04:50:47.641180 1 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8329 04:50:47.644523 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8330 04:50:47.647856 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8331 04:50:47.654305 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8332 04:50:47.658011 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8333 04:50:47.661303 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8334 04:50:47.667962 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8335 04:50:47.671178 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8336 04:50:47.674595 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8337 04:50:47.681198 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8338 04:50:47.684422 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8339 04:50:47.687729 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 04:50:47.694183 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 04:50:47.697785 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 04:50:47.700729 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 04:50:47.707909 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 04:50:47.711182 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 04:50:47.714591 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 04:50:47.721379 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 04:50:47.724183 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 04:50:47.727484 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 04:50:47.733975 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 04:50:47.738128 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 04:50:47.741278 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8352 04:50:47.748205 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8353 04:50:47.751657 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8354 04:50:47.754641 Total UI for P1: 0, mck2ui 16
8355 04:50:47.757513 best dqsien dly found for B0: ( 1, 9, 10)
8356 04:50:47.761234 Total UI for P1: 0, mck2ui 16
8357 04:50:47.764033 best dqsien dly found for B1: ( 1, 9, 10)
8358 04:50:47.767761 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8359 04:50:47.770763 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8360 04:50:47.771235
8361 04:50:47.774135 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8362 04:50:47.777643 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8363 04:50:47.780561 [Gating] SW calibration Done
8364 04:50:47.780643 ==
8365 04:50:47.783625 Dram Type= 6, Freq= 0, CH_1, rank 0
8366 04:50:47.787818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8367 04:50:47.791264 ==
8368 04:50:47.791681 RX Vref Scan: 0
8369 04:50:47.791959
8370 04:50:47.794577 RX Vref 0 -> 0, step: 1
8371 04:50:47.794901
8372 04:50:47.795161 RX Delay 0 -> 252, step: 8
8373 04:50:47.801153 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8374 04:50:47.804378 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8375 04:50:47.807560 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8376 04:50:47.810497 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8377 04:50:47.814170 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8378 04:50:47.820645 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8379 04:50:47.823981 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8380 04:50:47.827319 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8381 04:50:47.830618 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8382 04:50:47.833884 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8383 04:50:47.840344 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8384 04:50:47.843520 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8385 04:50:47.846688 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8386 04:50:47.849955 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8387 04:50:47.856593 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8388 04:50:47.859867 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8389 04:50:47.859972 ==
8390 04:50:47.863334 Dram Type= 6, Freq= 0, CH_1, rank 0
8391 04:50:47.866656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8392 04:50:47.866757 ==
8393 04:50:47.866824 DQS Delay:
8394 04:50:47.870083 DQS0 = 0, DQS1 = 0
8395 04:50:47.870172 DQM Delay:
8396 04:50:47.873317 DQM0 = 136, DQM1 = 132
8397 04:50:47.873407 DQ Delay:
8398 04:50:47.876578 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8399 04:50:47.879909 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8400 04:50:47.883678 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8401 04:50:47.889708 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8402 04:50:47.889837
8403 04:50:47.889910
8404 04:50:47.889971 ==
8405 04:50:47.893115 Dram Type= 6, Freq= 0, CH_1, rank 0
8406 04:50:47.896795 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8407 04:50:47.896894 ==
8408 04:50:47.896962
8409 04:50:47.897023
8410 04:50:47.900043 TX Vref Scan disable
8411 04:50:47.900129 == TX Byte 0 ==
8412 04:50:47.906652 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8413 04:50:47.910108 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8414 04:50:47.910199 == TX Byte 1 ==
8415 04:50:47.916751 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8416 04:50:47.920126 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8417 04:50:47.920224 ==
8418 04:50:47.923554 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 04:50:47.926665 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8420 04:50:47.926753 ==
8421 04:50:47.939509
8422 04:50:47.943115 TX Vref early break, caculate TX vref
8423 04:50:47.946412 TX Vref=16, minBit 9, minWin=22, winSum=381
8424 04:50:47.949736 TX Vref=18, minBit 0, minWin=23, winSum=386
8425 04:50:47.952958 TX Vref=20, minBit 1, minWin=24, winSum=403
8426 04:50:47.956169 TX Vref=22, minBit 0, minWin=25, winSum=410
8427 04:50:47.959359 TX Vref=24, minBit 0, minWin=25, winSum=422
8428 04:50:47.966129 TX Vref=26, minBit 1, minWin=25, winSum=427
8429 04:50:47.969510 TX Vref=28, minBit 0, minWin=25, winSum=429
8430 04:50:47.972916 TX Vref=30, minBit 0, minWin=25, winSum=421
8431 04:50:47.976136 TX Vref=32, minBit 0, minWin=24, winSum=413
8432 04:50:47.979711 TX Vref=34, minBit 0, minWin=24, winSum=406
8433 04:50:47.986210 [TxChooseVref] Worse bit 0, Min win 25, Win sum 429, Final Vref 28
8434 04:50:47.986349
8435 04:50:47.989433 Final TX Range 0 Vref 28
8436 04:50:47.989556
8437 04:50:47.989652 ==
8438 04:50:47.992917 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 04:50:47.996156 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 04:50:47.996280 ==
8441 04:50:47.996392
8442 04:50:47.996455
8443 04:50:47.999402 TX Vref Scan disable
8444 04:50:48.006383 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8445 04:50:48.006519 == TX Byte 0 ==
8446 04:50:48.009471 u2DelayCellOfst[0]=17 cells (5 PI)
8447 04:50:48.012437 u2DelayCellOfst[1]=10 cells (3 PI)
8448 04:50:48.015892 u2DelayCellOfst[2]=0 cells (0 PI)
8449 04:50:48.019392 u2DelayCellOfst[3]=6 cells (2 PI)
8450 04:50:48.022396 u2DelayCellOfst[4]=10 cells (3 PI)
8451 04:50:48.025699 u2DelayCellOfst[5]=17 cells (5 PI)
8452 04:50:48.029153 u2DelayCellOfst[6]=17 cells (5 PI)
8453 04:50:48.032398 u2DelayCellOfst[7]=6 cells (2 PI)
8454 04:50:48.035865 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8455 04:50:48.039162 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8456 04:50:48.042476 == TX Byte 1 ==
8457 04:50:48.042559 u2DelayCellOfst[8]=0 cells (0 PI)
8458 04:50:48.045823 u2DelayCellOfst[9]=3 cells (1 PI)
8459 04:50:48.048995 u2DelayCellOfst[10]=13 cells (4 PI)
8460 04:50:48.052499 u2DelayCellOfst[11]=3 cells (1 PI)
8461 04:50:48.056121 u2DelayCellOfst[12]=17 cells (5 PI)
8462 04:50:48.059161 u2DelayCellOfst[13]=17 cells (5 PI)
8463 04:50:48.062556 u2DelayCellOfst[14]=20 cells (6 PI)
8464 04:50:48.065790 u2DelayCellOfst[15]=17 cells (5 PI)
8465 04:50:48.069355 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8466 04:50:48.075833 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8467 04:50:48.075928 DramC Write-DBI on
8468 04:50:48.076010 ==
8469 04:50:48.079038 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 04:50:48.082543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 04:50:48.085832 ==
8472 04:50:48.085914
8473 04:50:48.085979
8474 04:50:48.086039 TX Vref Scan disable
8475 04:50:48.089077 == TX Byte 0 ==
8476 04:50:48.092887 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8477 04:50:48.095622 == TX Byte 1 ==
8478 04:50:48.098947 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8479 04:50:48.102347 DramC Write-DBI off
8480 04:50:48.102429
8481 04:50:48.102494 [DATLAT]
8482 04:50:48.102553 Freq=1600, CH1 RK0
8483 04:50:48.102612
8484 04:50:48.105992 DATLAT Default: 0xf
8485 04:50:48.106074 0, 0xFFFF, sum = 0
8486 04:50:48.109423 1, 0xFFFF, sum = 0
8487 04:50:48.112212 2, 0xFFFF, sum = 0
8488 04:50:48.112322 3, 0xFFFF, sum = 0
8489 04:50:48.115600 4, 0xFFFF, sum = 0
8490 04:50:48.115684 5, 0xFFFF, sum = 0
8491 04:50:48.118969 6, 0xFFFF, sum = 0
8492 04:50:48.119053 7, 0xFFFF, sum = 0
8493 04:50:48.122124 8, 0xFFFF, sum = 0
8494 04:50:48.122207 9, 0xFFFF, sum = 0
8495 04:50:48.125776 10, 0xFFFF, sum = 0
8496 04:50:48.125859 11, 0xFFFF, sum = 0
8497 04:50:48.129463 12, 0xFFFF, sum = 0
8498 04:50:48.129547 13, 0xFFFF, sum = 0
8499 04:50:48.132404 14, 0x0, sum = 1
8500 04:50:48.132488 15, 0x0, sum = 2
8501 04:50:48.135800 16, 0x0, sum = 3
8502 04:50:48.135883 17, 0x0, sum = 4
8503 04:50:48.139214 best_step = 15
8504 04:50:48.139296
8505 04:50:48.139361 ==
8506 04:50:48.142485 Dram Type= 6, Freq= 0, CH_1, rank 0
8507 04:50:48.145943 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8508 04:50:48.146025 ==
8509 04:50:48.146090 RX Vref Scan: 1
8510 04:50:48.146152
8511 04:50:48.149117 Set Vref Range= 24 -> 127
8512 04:50:48.149198
8513 04:50:48.152456 RX Vref 24 -> 127, step: 1
8514 04:50:48.152539
8515 04:50:48.155691 RX Delay 27 -> 252, step: 4
8516 04:50:48.155773
8517 04:50:48.159161 Set Vref, RX VrefLevel [Byte0]: 24
8518 04:50:48.162433 [Byte1]: 24
8519 04:50:48.162515
8520 04:50:48.165676 Set Vref, RX VrefLevel [Byte0]: 25
8521 04:50:48.169448 [Byte1]: 25
8522 04:50:48.169530
8523 04:50:48.172432 Set Vref, RX VrefLevel [Byte0]: 26
8524 04:50:48.175394 [Byte1]: 26
8525 04:50:48.179138
8526 04:50:48.179220 Set Vref, RX VrefLevel [Byte0]: 27
8527 04:50:48.182522 [Byte1]: 27
8528 04:50:48.186850
8529 04:50:48.186932 Set Vref, RX VrefLevel [Byte0]: 28
8530 04:50:48.190120 [Byte1]: 28
8531 04:50:48.194217
8532 04:50:48.194298 Set Vref, RX VrefLevel [Byte0]: 29
8533 04:50:48.197637 [Byte1]: 29
8534 04:50:48.202006
8535 04:50:48.202088 Set Vref, RX VrefLevel [Byte0]: 30
8536 04:50:48.205221 [Byte1]: 30
8537 04:50:48.209740
8538 04:50:48.209822 Set Vref, RX VrefLevel [Byte0]: 31
8539 04:50:48.212448 [Byte1]: 31
8540 04:50:48.217102
8541 04:50:48.217185 Set Vref, RX VrefLevel [Byte0]: 32
8542 04:50:48.220320 [Byte1]: 32
8543 04:50:48.224473
8544 04:50:48.224554 Set Vref, RX VrefLevel [Byte0]: 33
8545 04:50:48.227807 [Byte1]: 33
8546 04:50:48.232205
8547 04:50:48.232293 Set Vref, RX VrefLevel [Byte0]: 34
8548 04:50:48.235377 [Byte1]: 34
8549 04:50:48.239703
8550 04:50:48.239785 Set Vref, RX VrefLevel [Byte0]: 35
8551 04:50:48.242787 [Byte1]: 35
8552 04:50:48.246949
8553 04:50:48.247031 Set Vref, RX VrefLevel [Byte0]: 36
8554 04:50:48.250453 [Byte1]: 36
8555 04:50:48.254908
8556 04:50:48.254990 Set Vref, RX VrefLevel [Byte0]: 37
8557 04:50:48.258414 [Byte1]: 37
8558 04:50:48.262237
8559 04:50:48.262319 Set Vref, RX VrefLevel [Byte0]: 38
8560 04:50:48.265592 [Byte1]: 38
8561 04:50:48.269677
8562 04:50:48.269760 Set Vref, RX VrefLevel [Byte0]: 39
8563 04:50:48.273013 [Byte1]: 39
8564 04:50:48.277452
8565 04:50:48.277533 Set Vref, RX VrefLevel [Byte0]: 40
8566 04:50:48.280641 [Byte1]: 40
8567 04:50:48.284739
8568 04:50:48.284820 Set Vref, RX VrefLevel [Byte0]: 41
8569 04:50:48.287838 [Byte1]: 41
8570 04:50:48.292235
8571 04:50:48.292374 Set Vref, RX VrefLevel [Byte0]: 42
8572 04:50:48.295429 [Byte1]: 42
8573 04:50:48.299881
8574 04:50:48.299966 Set Vref, RX VrefLevel [Byte0]: 43
8575 04:50:48.303135 [Byte1]: 43
8576 04:50:48.307461
8577 04:50:48.307543 Set Vref, RX VrefLevel [Byte0]: 44
8578 04:50:48.310792 [Byte1]: 44
8579 04:50:48.315045
8580 04:50:48.315126 Set Vref, RX VrefLevel [Byte0]: 45
8581 04:50:48.317955 [Byte1]: 45
8582 04:50:48.322321
8583 04:50:48.322404 Set Vref, RX VrefLevel [Byte0]: 46
8584 04:50:48.325641 [Byte1]: 46
8585 04:50:48.329646
8586 04:50:48.329728 Set Vref, RX VrefLevel [Byte0]: 47
8587 04:50:48.333153 [Byte1]: 47
8588 04:50:48.337737
8589 04:50:48.337819 Set Vref, RX VrefLevel [Byte0]: 48
8590 04:50:48.341092 [Byte1]: 48
8591 04:50:48.345063
8592 04:50:48.345144 Set Vref, RX VrefLevel [Byte0]: 49
8593 04:50:48.348202 [Byte1]: 49
8594 04:50:48.352805
8595 04:50:48.352887 Set Vref, RX VrefLevel [Byte0]: 50
8596 04:50:48.356238 [Byte1]: 50
8597 04:50:48.359931
8598 04:50:48.360013 Set Vref, RX VrefLevel [Byte0]: 51
8599 04:50:48.363665 [Byte1]: 51
8600 04:50:48.367651
8601 04:50:48.367733 Set Vref, RX VrefLevel [Byte0]: 52
8602 04:50:48.370975 [Byte1]: 52
8603 04:50:48.375029
8604 04:50:48.375112 Set Vref, RX VrefLevel [Byte0]: 53
8605 04:50:48.378357 [Byte1]: 53
8606 04:50:48.382939
8607 04:50:48.383021 Set Vref, RX VrefLevel [Byte0]: 54
8608 04:50:48.386259 [Byte1]: 54
8609 04:50:48.390006
8610 04:50:48.390088 Set Vref, RX VrefLevel [Byte0]: 55
8611 04:50:48.393381 [Byte1]: 55
8612 04:50:48.397843
8613 04:50:48.397925 Set Vref, RX VrefLevel [Byte0]: 56
8614 04:50:48.401215 [Byte1]: 56
8615 04:50:48.405732
8616 04:50:48.405814 Set Vref, RX VrefLevel [Byte0]: 57
8617 04:50:48.408473 [Byte1]: 57
8618 04:50:48.413182
8619 04:50:48.413264 Set Vref, RX VrefLevel [Byte0]: 58
8620 04:50:48.415920 [Byte1]: 58
8621 04:50:48.420585
8622 04:50:48.420667 Set Vref, RX VrefLevel [Byte0]: 59
8623 04:50:48.423774 [Byte1]: 59
8624 04:50:48.428179
8625 04:50:48.428260 Set Vref, RX VrefLevel [Byte0]: 60
8626 04:50:48.431157 [Byte1]: 60
8627 04:50:48.435455
8628 04:50:48.435536 Set Vref, RX VrefLevel [Byte0]: 61
8629 04:50:48.438559 [Byte1]: 61
8630 04:50:48.443118
8631 04:50:48.443200 Set Vref, RX VrefLevel [Byte0]: 62
8632 04:50:48.446000 [Byte1]: 62
8633 04:50:48.450560
8634 04:50:48.450641 Set Vref, RX VrefLevel [Byte0]: 63
8635 04:50:48.453762 [Byte1]: 63
8636 04:50:48.458258
8637 04:50:48.458344 Set Vref, RX VrefLevel [Byte0]: 64
8638 04:50:48.461671 [Byte1]: 64
8639 04:50:48.465526
8640 04:50:48.465609 Set Vref, RX VrefLevel [Byte0]: 65
8641 04:50:48.469146 [Byte1]: 65
8642 04:50:48.472937
8643 04:50:48.473019 Set Vref, RX VrefLevel [Byte0]: 66
8644 04:50:48.476233 [Byte1]: 66
8645 04:50:48.480933
8646 04:50:48.481015 Set Vref, RX VrefLevel [Byte0]: 67
8647 04:50:48.484197 [Byte1]: 67
8648 04:50:48.488029
8649 04:50:48.488111 Set Vref, RX VrefLevel [Byte0]: 68
8650 04:50:48.491438 [Byte1]: 68
8651 04:50:48.495981
8652 04:50:48.496063 Set Vref, RX VrefLevel [Byte0]: 69
8653 04:50:48.498738 [Byte1]: 69
8654 04:50:48.503511
8655 04:50:48.503593 Set Vref, RX VrefLevel [Byte0]: 70
8656 04:50:48.506555 [Byte1]: 70
8657 04:50:48.511098
8658 04:50:48.511180 Set Vref, RX VrefLevel [Byte0]: 71
8659 04:50:48.513861 [Byte1]: 71
8660 04:50:48.518399
8661 04:50:48.518481 Set Vref, RX VrefLevel [Byte0]: 72
8662 04:50:48.521880 [Byte1]: 72
8663 04:50:48.525980
8664 04:50:48.526063 Set Vref, RX VrefLevel [Byte0]: 73
8665 04:50:48.529352 [Byte1]: 73
8666 04:50:48.533369
8667 04:50:48.533451 Set Vref, RX VrefLevel [Byte0]: 74
8668 04:50:48.536713 [Byte1]: 74
8669 04:50:48.540673
8670 04:50:48.540756 Set Vref, RX VrefLevel [Byte0]: 75
8671 04:50:48.544443 [Byte1]: 75
8672 04:50:48.548615
8673 04:50:48.548697 Set Vref, RX VrefLevel [Byte0]: 76
8674 04:50:48.551981 [Byte1]: 76
8675 04:50:48.556191
8676 04:50:48.556273 Set Vref, RX VrefLevel [Byte0]: 77
8677 04:50:48.558934 [Byte1]: 77
8678 04:50:48.563261
8679 04:50:48.563357 Final RX Vref Byte 0 = 58 to rank0
8680 04:50:48.566764 Final RX Vref Byte 1 = 52 to rank0
8681 04:50:48.570086 Final RX Vref Byte 0 = 58 to rank1
8682 04:50:48.573382 Final RX Vref Byte 1 = 52 to rank1==
8683 04:50:48.576721 Dram Type= 6, Freq= 0, CH_1, rank 0
8684 04:50:48.583231 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8685 04:50:48.583316 ==
8686 04:50:48.583383 DQS Delay:
8687 04:50:48.583443 DQS0 = 0, DQS1 = 0
8688 04:50:48.586811 DQM Delay:
8689 04:50:48.586893 DQM0 = 134, DQM1 = 130
8690 04:50:48.590268 DQ Delay:
8691 04:50:48.593371 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8692 04:50:48.596592 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =134
8693 04:50:48.599842 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =124
8694 04:50:48.603191 DQ12 =136, DQ13 =136, DQ14 =140, DQ15 =140
8695 04:50:48.603273
8696 04:50:48.603338
8697 04:50:48.603397
8698 04:50:48.606629 [DramC_TX_OE_Calibration] TA2
8699 04:50:48.609771 Original DQ_B0 (3 6) =30, OEN = 27
8700 04:50:48.613529 Original DQ_B1 (3 6) =30, OEN = 27
8701 04:50:48.616703 24, 0x0, End_B0=24 End_B1=24
8702 04:50:48.616812 25, 0x0, End_B0=25 End_B1=25
8703 04:50:48.620068 26, 0x0, End_B0=26 End_B1=26
8704 04:50:48.623289 27, 0x0, End_B0=27 End_B1=27
8705 04:50:48.626682 28, 0x0, End_B0=28 End_B1=28
8706 04:50:48.630011 29, 0x0, End_B0=29 End_B1=29
8707 04:50:48.630095 30, 0x0, End_B0=30 End_B1=30
8708 04:50:48.633416 31, 0x4141, End_B0=30 End_B1=30
8709 04:50:48.636800 Byte0 end_step=30 best_step=27
8710 04:50:48.639544 Byte1 end_step=30 best_step=27
8711 04:50:48.642816 Byte0 TX OE(2T, 0.5T) = (3, 3)
8712 04:50:48.646193 Byte1 TX OE(2T, 0.5T) = (3, 3)
8713 04:50:48.646276
8714 04:50:48.646340
8715 04:50:48.652913 [DQSOSCAuto] RK0, (LSB)MR18= 0x1422, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8716 04:50:48.656153 CH1 RK0: MR19=303, MR18=1422
8717 04:50:48.663057 CH1_RK0: MR19=0x303, MR18=0x1422, DQSOSC=392, MR23=63, INC=24, DEC=16
8718 04:50:48.663165
8719 04:50:48.666409 ----->DramcWriteLeveling(PI) begin...
8720 04:50:48.666493 ==
8721 04:50:48.669838 Dram Type= 6, Freq= 0, CH_1, rank 1
8722 04:50:48.673112 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8723 04:50:48.673220 ==
8724 04:50:48.676491 Write leveling (Byte 0): 26 => 26
8725 04:50:48.679700 Write leveling (Byte 1): 27 => 27
8726 04:50:48.683090 DramcWriteLeveling(PI) end<-----
8727 04:50:48.683172
8728 04:50:48.683236 ==
8729 04:50:48.686289 Dram Type= 6, Freq= 0, CH_1, rank 1
8730 04:50:48.689573 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8731 04:50:48.689655 ==
8732 04:50:48.692655 [Gating] SW mode calibration
8733 04:50:48.699819 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8734 04:50:48.706068 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8735 04:50:48.709470 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8736 04:50:48.712856 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8737 04:50:48.719839 1 4 8 | B1->B0 | 2d2d 2323 | 1 0 | (1 1) (0 0)
8738 04:50:48.722565 1 4 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
8739 04:50:48.726615 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8740 04:50:48.733115 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8741 04:50:48.736049 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8742 04:50:48.739681 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8743 04:50:48.746295 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8744 04:50:48.749626 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8745 04:50:48.752975 1 5 8 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
8746 04:50:48.759461 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8747 04:50:48.762861 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8748 04:50:48.765983 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8749 04:50:48.772198 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8750 04:50:48.776240 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8751 04:50:48.778932 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8752 04:50:48.786149 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8753 04:50:48.789576 1 6 8 | B1->B0 | 3838 2525 | 0 0 | (0 0) (0 0)
8754 04:50:48.792312 1 6 12 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
8755 04:50:48.799112 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8756 04:50:48.802475 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8757 04:50:48.805801 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8758 04:50:48.812828 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8759 04:50:48.816159 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8760 04:50:48.819516 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8761 04:50:48.825905 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8762 04:50:48.829011 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8763 04:50:48.832098 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 04:50:48.839133 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 04:50:48.842106 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 04:50:48.845318 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 04:50:48.848699 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 04:50:48.855770 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 04:50:48.858674 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 04:50:48.862365 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 04:50:48.868883 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 04:50:48.872110 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 04:50:48.875205 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 04:50:48.881735 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 04:50:48.885153 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 04:50:48.888230 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8777 04:50:48.895453 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8778 04:50:48.898225 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8779 04:50:48.901639 Total UI for P1: 0, mck2ui 16
8780 04:50:48.905010 best dqsien dly found for B1: ( 1, 9, 6)
8781 04:50:48.908229 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8782 04:50:48.911645 Total UI for P1: 0, mck2ui 16
8783 04:50:48.914915 best dqsien dly found for B0: ( 1, 9, 10)
8784 04:50:48.918200 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8785 04:50:48.921857 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8786 04:50:48.921951
8787 04:50:48.928203 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8788 04:50:48.931620 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8789 04:50:48.934944 [Gating] SW calibration Done
8790 04:50:48.935025 ==
8791 04:50:48.938356 Dram Type= 6, Freq= 0, CH_1, rank 1
8792 04:50:48.941603 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8793 04:50:48.941685 ==
8794 04:50:48.941749 RX Vref Scan: 0
8795 04:50:48.941808
8796 04:50:48.944893 RX Vref 0 -> 0, step: 1
8797 04:50:48.944975
8798 04:50:48.948119 RX Delay 0 -> 252, step: 8
8799 04:50:48.951836 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8800 04:50:48.955102 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8801 04:50:48.962077 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8802 04:50:48.965279 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8803 04:50:48.968554 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8804 04:50:48.971871 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8805 04:50:48.975081 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8806 04:50:48.978341 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8807 04:50:48.985316 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8808 04:50:48.988174 iDelay=208, Bit 9, Center 123 (72 ~ 175) 104
8809 04:50:48.991903 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8810 04:50:48.995204 iDelay=208, Bit 11, Center 131 (80 ~ 183) 104
8811 04:50:48.998445 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8812 04:50:49.005239 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8813 04:50:49.008635 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8814 04:50:49.011860 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8815 04:50:49.011942 ==
8816 04:50:49.014564 Dram Type= 6, Freq= 0, CH_1, rank 1
8817 04:50:49.021185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8818 04:50:49.021269 ==
8819 04:50:49.021334 DQS Delay:
8820 04:50:49.021395 DQS0 = 0, DQS1 = 0
8821 04:50:49.024603 DQM Delay:
8822 04:50:49.024685 DQM0 = 136, DQM1 = 134
8823 04:50:49.027864 DQ Delay:
8824 04:50:49.031696 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8825 04:50:49.034796 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8826 04:50:49.037977 DQ8 =119, DQ9 =123, DQ10 =135, DQ11 =131
8827 04:50:49.041365 DQ12 =143, DQ13 =143, DQ14 =135, DQ15 =143
8828 04:50:49.041446
8829 04:50:49.041511
8830 04:50:49.041572 ==
8831 04:50:49.044880 Dram Type= 6, Freq= 0, CH_1, rank 1
8832 04:50:49.047892 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8833 04:50:49.047973 ==
8834 04:50:49.051316
8835 04:50:49.051421
8836 04:50:49.051513 TX Vref Scan disable
8837 04:50:49.054478 == TX Byte 0 ==
8838 04:50:49.058405 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8839 04:50:49.061344 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8840 04:50:49.064597 == TX Byte 1 ==
8841 04:50:49.067654 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8842 04:50:49.070973 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8843 04:50:49.071057 ==
8844 04:50:49.074373 Dram Type= 6, Freq= 0, CH_1, rank 1
8845 04:50:49.081090 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8846 04:50:49.081173 ==
8847 04:50:49.092501
8848 04:50:49.095834 TX Vref early break, caculate TX vref
8849 04:50:49.099321 TX Vref=16, minBit 0, minWin=23, winSum=387
8850 04:50:49.102505 TX Vref=18, minBit 6, minWin=23, winSum=396
8851 04:50:49.106114 TX Vref=20, minBit 1, minWin=24, winSum=404
8852 04:50:49.109342 TX Vref=22, minBit 6, minWin=24, winSum=411
8853 04:50:49.112337 TX Vref=24, minBit 0, minWin=25, winSum=417
8854 04:50:49.119233 TX Vref=26, minBit 0, minWin=25, winSum=423
8855 04:50:49.122550 TX Vref=28, minBit 0, minWin=26, winSum=432
8856 04:50:49.125878 TX Vref=30, minBit 6, minWin=25, winSum=419
8857 04:50:49.129199 TX Vref=32, minBit 0, minWin=24, winSum=414
8858 04:50:49.132626 TX Vref=34, minBit 0, minWin=24, winSum=404
8859 04:50:49.139215 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 28
8860 04:50:49.139298
8861 04:50:49.142429 Final TX Range 0 Vref 28
8862 04:50:49.142511
8863 04:50:49.142576 ==
8864 04:50:49.145554 Dram Type= 6, Freq= 0, CH_1, rank 1
8865 04:50:49.149437 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8866 04:50:49.149521 ==
8867 04:50:49.149586
8868 04:50:49.149647
8869 04:50:49.152673 TX Vref Scan disable
8870 04:50:49.158737 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8871 04:50:49.158820 == TX Byte 0 ==
8872 04:50:49.162630 u2DelayCellOfst[0]=17 cells (5 PI)
8873 04:50:49.165624 u2DelayCellOfst[1]=13 cells (4 PI)
8874 04:50:49.169027 u2DelayCellOfst[2]=0 cells (0 PI)
8875 04:50:49.172067 u2DelayCellOfst[3]=6 cells (2 PI)
8876 04:50:49.175647 u2DelayCellOfst[4]=10 cells (3 PI)
8877 04:50:49.179038 u2DelayCellOfst[5]=17 cells (5 PI)
8878 04:50:49.182364 u2DelayCellOfst[6]=17 cells (5 PI)
8879 04:50:49.182451 u2DelayCellOfst[7]=6 cells (2 PI)
8880 04:50:49.188926 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8881 04:50:49.192162 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8882 04:50:49.192259 == TX Byte 1 ==
8883 04:50:49.195578 u2DelayCellOfst[8]=0 cells (0 PI)
8884 04:50:49.198985 u2DelayCellOfst[9]=3 cells (1 PI)
8885 04:50:49.202276 u2DelayCellOfst[10]=10 cells (3 PI)
8886 04:50:49.205539 u2DelayCellOfst[11]=3 cells (1 PI)
8887 04:50:49.209045 u2DelayCellOfst[12]=13 cells (4 PI)
8888 04:50:49.212131 u2DelayCellOfst[13]=13 cells (4 PI)
8889 04:50:49.215528 u2DelayCellOfst[14]=13 cells (4 PI)
8890 04:50:49.219218 u2DelayCellOfst[15]=17 cells (5 PI)
8891 04:50:49.222446 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8892 04:50:49.229165 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8893 04:50:49.229259 DramC Write-DBI on
8894 04:50:49.229334 ==
8895 04:50:49.232281 Dram Type= 6, Freq= 0, CH_1, rank 1
8896 04:50:49.235066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8897 04:50:49.238637 ==
8898 04:50:49.238720
8899 04:50:49.238785
8900 04:50:49.238845 TX Vref Scan disable
8901 04:50:49.242513 == TX Byte 0 ==
8902 04:50:49.245202 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8903 04:50:49.249210 == TX Byte 1 ==
8904 04:50:49.252317 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8905 04:50:49.255362 DramC Write-DBI off
8906 04:50:49.255547
8907 04:50:49.255652 [DATLAT]
8908 04:50:49.255736 Freq=1600, CH1 RK1
8909 04:50:49.255813
8910 04:50:49.259188 DATLAT Default: 0xf
8911 04:50:49.259380 0, 0xFFFF, sum = 0
8912 04:50:49.261971 1, 0xFFFF, sum = 0
8913 04:50:49.262147 2, 0xFFFF, sum = 0
8914 04:50:49.265430 3, 0xFFFF, sum = 0
8915 04:50:49.268686 4, 0xFFFF, sum = 0
8916 04:50:49.268850 5, 0xFFFF, sum = 0
8917 04:50:49.271907 6, 0xFFFF, sum = 0
8918 04:50:49.272062 7, 0xFFFF, sum = 0
8919 04:50:49.275842 8, 0xFFFF, sum = 0
8920 04:50:49.275998 9, 0xFFFF, sum = 0
8921 04:50:49.278708 10, 0xFFFF, sum = 0
8922 04:50:49.278970 11, 0xFFFF, sum = 0
8923 04:50:49.282497 12, 0xFFFF, sum = 0
8924 04:50:49.282791 13, 0xFFFF, sum = 0
8925 04:50:49.285319 14, 0x0, sum = 1
8926 04:50:49.285612 15, 0x0, sum = 2
8927 04:50:49.289186 16, 0x0, sum = 3
8928 04:50:49.289438 17, 0x0, sum = 4
8929 04:50:49.292588 best_step = 15
8930 04:50:49.292948
8931 04:50:49.293231 ==
8932 04:50:49.295681 Dram Type= 6, Freq= 0, CH_1, rank 1
8933 04:50:49.299179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8934 04:50:49.299542 ==
8935 04:50:49.299830 RX Vref Scan: 0
8936 04:50:49.302591
8937 04:50:49.302949 RX Vref 0 -> 0, step: 1
8938 04:50:49.303234
8939 04:50:49.305307 RX Delay 19 -> 252, step: 4
8940 04:50:49.308665 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8941 04:50:49.315354 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8942 04:50:49.319220 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8943 04:50:49.322382 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8944 04:50:49.325452 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8945 04:50:49.328676 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8946 04:50:49.331912 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8947 04:50:49.338530 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8948 04:50:49.341935 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8949 04:50:49.345059 iDelay=195, Bit 9, Center 120 (67 ~ 174) 108
8950 04:50:49.348093 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8951 04:50:49.351939 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8952 04:50:49.358769 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8953 04:50:49.361919 iDelay=195, Bit 13, Center 136 (87 ~ 186) 100
8954 04:50:49.365425 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8955 04:50:49.368566 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8956 04:50:49.368924 ==
8957 04:50:49.372356 Dram Type= 6, Freq= 0, CH_1, rank 1
8958 04:50:49.378828 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8959 04:50:49.379400 ==
8960 04:50:49.379704 DQS Delay:
8961 04:50:49.382055 DQS0 = 0, DQS1 = 0
8962 04:50:49.382519 DQM Delay:
8963 04:50:49.382808 DQM0 = 134, DQM1 = 130
8964 04:50:49.385444 DQ Delay:
8965 04:50:49.388902 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8966 04:50:49.391964 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8967 04:50:49.395816 DQ8 =118, DQ9 =120, DQ10 =130, DQ11 =124
8968 04:50:49.398812 DQ12 =140, DQ13 =136, DQ14 =136, DQ15 =140
8969 04:50:49.399300
8970 04:50:49.399614
8971 04:50:49.399897
8972 04:50:49.402006 [DramC_TX_OE_Calibration] TA2
8973 04:50:49.405310 Original DQ_B0 (3 6) =30, OEN = 27
8974 04:50:49.408648 Original DQ_B1 (3 6) =30, OEN = 27
8975 04:50:49.411986 24, 0x0, End_B0=24 End_B1=24
8976 04:50:49.412403 25, 0x0, End_B0=25 End_B1=25
8977 04:50:49.415527 26, 0x0, End_B0=26 End_B1=26
8978 04:50:49.418984 27, 0x0, End_B0=27 End_B1=27
8979 04:50:49.421713 28, 0x0, End_B0=28 End_B1=28
8980 04:50:49.425434 29, 0x0, End_B0=29 End_B1=29
8981 04:50:49.425798 30, 0x0, End_B0=30 End_B1=30
8982 04:50:49.428637 31, 0x4141, End_B0=30 End_B1=30
8983 04:50:49.432161 Byte0 end_step=30 best_step=27
8984 04:50:49.435413 Byte1 end_step=30 best_step=27
8985 04:50:49.438686 Byte0 TX OE(2T, 0.5T) = (3, 3)
8986 04:50:49.442062 Byte1 TX OE(2T, 0.5T) = (3, 3)
8987 04:50:49.442537
8988 04:50:49.442829
8989 04:50:49.448803 [DQSOSCAuto] RK1, (LSB)MR18= 0x2007, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
8990 04:50:49.451433 CH1 RK1: MR19=303, MR18=2007
8991 04:50:49.458689 CH1_RK1: MR19=0x303, MR18=0x2007, DQSOSC=393, MR23=63, INC=23, DEC=15
8992 04:50:49.461896 [RxdqsGatingPostProcess] freq 1600
8993 04:50:49.465061 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8994 04:50:49.468236 best DQS0 dly(2T, 0.5T) = (1, 1)
8995 04:50:49.471506 best DQS1 dly(2T, 0.5T) = (1, 1)
8996 04:50:49.475055 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8997 04:50:49.478087 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8998 04:50:49.481794 best DQS0 dly(2T, 0.5T) = (1, 1)
8999 04:50:49.484767 best DQS1 dly(2T, 0.5T) = (1, 1)
9000 04:50:49.488276 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9001 04:50:49.491355 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9002 04:50:49.494614 Pre-setting of DQS Precalculation
9003 04:50:49.498114 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9004 04:50:49.504668 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9005 04:50:49.514775 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9006 04:50:49.515202
9007 04:50:49.515610
9008 04:50:49.515893 [Calibration Summary] 3200 Mbps
9009 04:50:49.517874 CH 0, Rank 0
9010 04:50:49.521427 SW Impedance : PASS
9011 04:50:49.521785 DUTY Scan : NO K
9012 04:50:49.524899 ZQ Calibration : PASS
9013 04:50:49.525379 Jitter Meter : NO K
9014 04:50:49.528065 CBT Training : PASS
9015 04:50:49.531344 Write leveling : PASS
9016 04:50:49.531874 RX DQS gating : PASS
9017 04:50:49.534149 RX DQ/DQS(RDDQC) : PASS
9018 04:50:49.537660 TX DQ/DQS : PASS
9019 04:50:49.538071 RX DATLAT : PASS
9020 04:50:49.541609 RX DQ/DQS(Engine): PASS
9021 04:50:49.544273 TX OE : PASS
9022 04:50:49.544671 All Pass.
9023 04:50:49.544959
9024 04:50:49.545224 CH 0, Rank 1
9025 04:50:49.547812 SW Impedance : PASS
9026 04:50:49.551145 DUTY Scan : NO K
9027 04:50:49.551505 ZQ Calibration : PASS
9028 04:50:49.554544 Jitter Meter : NO K
9029 04:50:49.557875 CBT Training : PASS
9030 04:50:49.558234 Write leveling : PASS
9031 04:50:49.561126 RX DQS gating : PASS
9032 04:50:49.564546 RX DQ/DQS(RDDQC) : PASS
9033 04:50:49.564908 TX DQ/DQS : PASS
9034 04:50:49.567593 RX DATLAT : PASS
9035 04:50:49.571057 RX DQ/DQS(Engine): PASS
9036 04:50:49.571416 TX OE : PASS
9037 04:50:49.571704 All Pass.
9038 04:50:49.574276
9039 04:50:49.574631 CH 1, Rank 0
9040 04:50:49.577513 SW Impedance : PASS
9041 04:50:49.577909 DUTY Scan : NO K
9042 04:50:49.580886 ZQ Calibration : PASS
9043 04:50:49.581244 Jitter Meter : NO K
9044 04:50:49.584252 CBT Training : PASS
9045 04:50:49.587558 Write leveling : PASS
9046 04:50:49.587915 RX DQS gating : PASS
9047 04:50:49.590792 RX DQ/DQS(RDDQC) : PASS
9048 04:50:49.593996 TX DQ/DQS : PASS
9049 04:50:49.594356 RX DATLAT : PASS
9050 04:50:49.597627 RX DQ/DQS(Engine): PASS
9051 04:50:49.600551 TX OE : PASS
9052 04:50:49.600909 All Pass.
9053 04:50:49.601195
9054 04:50:49.601458 CH 1, Rank 1
9055 04:50:49.603941 SW Impedance : PASS
9056 04:50:49.607418 DUTY Scan : NO K
9057 04:50:49.607778 ZQ Calibration : PASS
9058 04:50:49.610943 Jitter Meter : NO K
9059 04:50:49.614235 CBT Training : PASS
9060 04:50:49.614593 Write leveling : PASS
9061 04:50:49.616998 RX DQS gating : PASS
9062 04:50:49.620169 RX DQ/DQS(RDDQC) : PASS
9063 04:50:49.620568 TX DQ/DQS : PASS
9064 04:50:49.623920 RX DATLAT : PASS
9065 04:50:49.627013 RX DQ/DQS(Engine): PASS
9066 04:50:49.627380 TX OE : PASS
9067 04:50:49.630593 All Pass.
9068 04:50:49.630950
9069 04:50:49.631235 DramC Write-DBI on
9070 04:50:49.633896 PER_BANK_REFRESH: Hybrid Mode
9071 04:50:49.634322 TX_TRACKING: ON
9072 04:50:49.644025 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9073 04:50:49.650788 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9074 04:50:49.661111 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9075 04:50:49.664321 [FAST_K] Save calibration result to emmc
9076 04:50:49.667207 sync common calibartion params.
9077 04:50:49.667600 sync cbt_mode0:1, 1:1
9078 04:50:49.670722 dram_init: ddr_geometry: 2
9079 04:50:49.673741 dram_init: ddr_geometry: 2
9080 04:50:49.674131 dram_init: ddr_geometry: 2
9081 04:50:49.677175 0:dram_rank_size:100000000
9082 04:50:49.679882 1:dram_rank_size:100000000
9083 04:50:49.686922 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9084 04:50:49.687312 DFS_SHUFFLE_HW_MODE: ON
9085 04:50:49.690283 dramc_set_vcore_voltage set vcore to 725000
9086 04:50:49.693847 Read voltage for 1600, 0
9087 04:50:49.694207 Vio18 = 0
9088 04:50:49.697188 Vcore = 725000
9089 04:50:49.697546 Vdram = 0
9090 04:50:49.697842 Vddq = 0
9091 04:50:49.700589 Vmddr = 0
9092 04:50:49.700946 switch to 3200 Mbps bootup
9093 04:50:49.703576 [DramcRunTimeConfig]
9094 04:50:49.703933 PHYPLL
9095 04:50:49.707337 DPM_CONTROL_AFTERK: ON
9096 04:50:49.707696 PER_BANK_REFRESH: ON
9097 04:50:49.709851 REFRESH_OVERHEAD_REDUCTION: ON
9098 04:50:49.713388 CMD_PICG_NEW_MODE: OFF
9099 04:50:49.713750 XRTWTW_NEW_MODE: ON
9100 04:50:49.716446 XRTRTR_NEW_MODE: ON
9101 04:50:49.716806 TX_TRACKING: ON
9102 04:50:49.719925 RDSEL_TRACKING: OFF
9103 04:50:49.723205 DQS Precalculation for DVFS: ON
9104 04:50:49.723564 RX_TRACKING: OFF
9105 04:50:49.726582 HW_GATING DBG: ON
9106 04:50:49.726966 ZQCS_ENABLE_LP4: ON
9107 04:50:49.729863 RX_PICG_NEW_MODE: ON
9108 04:50:49.730246 TX_PICG_NEW_MODE: ON
9109 04:50:49.733650 ENABLE_RX_DCM_DPHY: ON
9110 04:50:49.736567 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9111 04:50:49.739859 DUMMY_READ_FOR_TRACKING: OFF
9112 04:50:49.740331 !!! SPM_CONTROL_AFTERK: OFF
9113 04:50:49.743024 !!! SPM could not control APHY
9114 04:50:49.746489 IMPEDANCE_TRACKING: ON
9115 04:50:49.746892 TEMP_SENSOR: ON
9116 04:50:49.749700 HW_SAVE_FOR_SR: OFF
9117 04:50:49.752750 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9118 04:50:49.756429 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9119 04:50:49.756792 Read ODT Tracking: ON
9120 04:50:49.759506 Refresh Rate DeBounce: ON
9121 04:50:49.762856 DFS_NO_QUEUE_FLUSH: ON
9122 04:50:49.766265 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9123 04:50:49.766652 ENABLE_DFS_RUNTIME_MRW: OFF
9124 04:50:49.769741 DDR_RESERVE_NEW_MODE: ON
9125 04:50:49.773090 MR_CBT_SWITCH_FREQ: ON
9126 04:50:49.773476 =========================
9127 04:50:49.793550 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9128 04:50:49.796604 dram_init: ddr_geometry: 2
9129 04:50:49.815213 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9130 04:50:49.818565 dram_init: dram init end (result: 0)
9131 04:50:49.824857 DRAM-K: Full calibration passed in 24438 msecs
9132 04:50:49.828470 MRC: failed to locate region type 0.
9133 04:50:49.828832 DRAM rank0 size:0x100000000,
9134 04:50:49.831537 DRAM rank1 size=0x100000000
9135 04:50:49.841340 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9136 04:50:49.848313 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9137 04:50:49.855631 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9138 04:50:49.861637 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9139 04:50:49.864841 DRAM rank0 size:0x100000000,
9140 04:50:49.868245 DRAM rank1 size=0x100000000
9141 04:50:49.868667 CBMEM:
9142 04:50:49.871889 IMD: root @ 0xfffff000 254 entries.
9143 04:50:49.875372 IMD: root @ 0xffffec00 62 entries.
9144 04:50:49.877842 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9145 04:50:49.881212 WARNING: RO_VPD is uninitialized or empty.
9146 04:50:49.888175 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9147 04:50:49.895319 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9148 04:50:49.907915 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9149 04:50:49.919092 BS: romstage times (exec / console): total (unknown) / 23972 ms
9150 04:50:49.919485
9151 04:50:49.919794
9152 04:50:49.929337 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9153 04:50:49.932649 ARM64: Exception handlers installed.
9154 04:50:49.935516 ARM64: Testing exception
9155 04:50:49.938679 ARM64: Done test exception
9156 04:50:49.939101 Enumerating buses...
9157 04:50:49.942425 Show all devs... Before device enumeration.
9158 04:50:49.945470 Root Device: enabled 1
9159 04:50:49.948804 CPU_CLUSTER: 0: enabled 1
9160 04:50:49.949198 CPU: 00: enabled 1
9161 04:50:49.952900 Compare with tree...
9162 04:50:49.953288 Root Device: enabled 1
9163 04:50:49.956170 CPU_CLUSTER: 0: enabled 1
9164 04:50:49.959017 CPU: 00: enabled 1
9165 04:50:49.959405 Root Device scanning...
9166 04:50:49.962292 scan_static_bus for Root Device
9167 04:50:49.965747 CPU_CLUSTER: 0 enabled
9168 04:50:49.968963 scan_static_bus for Root Device done
9169 04:50:49.972713 scan_bus: bus Root Device finished in 8 msecs
9170 04:50:49.973105 done
9171 04:50:49.978897 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9172 04:50:49.982612 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9173 04:50:49.989302 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9174 04:50:49.992659 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9175 04:50:49.996259 Allocating resources...
9176 04:50:49.999436 Reading resources...
9177 04:50:50.002797 Root Device read_resources bus 0 link: 0
9178 04:50:50.003318 DRAM rank0 size:0x100000000,
9179 04:50:50.005921 DRAM rank1 size=0x100000000
9180 04:50:50.009158 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9181 04:50:50.012357 CPU: 00 missing read_resources
9182 04:50:50.015743 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9183 04:50:50.022590 Root Device read_resources bus 0 link: 0 done
9184 04:50:50.023222 Done reading resources.
9185 04:50:50.028970 Show resources in subtree (Root Device)...After reading.
9186 04:50:50.032322 Root Device child on link 0 CPU_CLUSTER: 0
9187 04:50:50.035557 CPU_CLUSTER: 0 child on link 0 CPU: 00
9188 04:50:50.045441 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9189 04:50:50.045869 CPU: 00
9190 04:50:50.048739 Root Device assign_resources, bus 0 link: 0
9191 04:50:50.051891 CPU_CLUSTER: 0 missing set_resources
9192 04:50:50.058854 Root Device assign_resources, bus 0 link: 0 done
9193 04:50:50.059276 Done setting resources.
9194 04:50:50.064871 Show resources in subtree (Root Device)...After assigning values.
9195 04:50:50.068864 Root Device child on link 0 CPU_CLUSTER: 0
9196 04:50:50.071570 CPU_CLUSTER: 0 child on link 0 CPU: 00
9197 04:50:50.081686 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9198 04:50:50.082075 CPU: 00
9199 04:50:50.085012 Done allocating resources.
9200 04:50:50.088555 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9201 04:50:50.091456 Enabling resources...
9202 04:50:50.091842 done.
9203 04:50:50.098530 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9204 04:50:50.098955 Initializing devices...
9205 04:50:50.101891 Root Device init
9206 04:50:50.102292 init hardware done!
9207 04:50:50.105176 0x00000018: ctrlr->caps
9208 04:50:50.108336 52.000 MHz: ctrlr->f_max
9209 04:50:50.108747 0.400 MHz: ctrlr->f_min
9210 04:50:50.112052 0x40ff8080: ctrlr->voltages
9211 04:50:50.112504 sclk: 390625
9212 04:50:50.114715 Bus Width = 1
9213 04:50:50.115112 sclk: 390625
9214 04:50:50.118587 Bus Width = 1
9215 04:50:50.118988 Early init status = 3
9216 04:50:50.125018 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9217 04:50:50.128358 in-header: 03 fc 00 00 01 00 00 00
9218 04:50:50.128749 in-data: 00
9219 04:50:50.135037 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9220 04:50:50.138185 in-header: 03 fd 00 00 00 00 00 00
9221 04:50:50.141605 in-data:
9222 04:50:50.144956 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9223 04:50:50.148141 in-header: 03 fc 00 00 01 00 00 00
9224 04:50:50.151874 in-data: 00
9225 04:50:50.154675 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9226 04:50:50.159982 in-header: 03 fd 00 00 00 00 00 00
9227 04:50:50.163145 in-data:
9228 04:50:50.166811 [SSUSB] Setting up USB HOST controller...
9229 04:50:50.170309 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9230 04:50:50.173040 [SSUSB] phy power-on done.
9231 04:50:50.176546 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9232 04:50:50.183045 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9233 04:50:50.186705 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9234 04:50:50.193104 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9235 04:50:50.200005 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9236 04:50:50.206332 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9237 04:50:50.213058 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9238 04:50:50.219485 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9239 04:50:50.222706 SPM: binary array size = 0x9dc
9240 04:50:50.225911 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9241 04:50:50.232448 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9242 04:50:50.239468 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9243 04:50:50.246267 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9244 04:50:50.248927 configure_display: Starting display init
9245 04:50:50.283534 anx7625_power_on_init: Init interface.
9246 04:50:50.286813 anx7625_disable_pd_protocol: Disabled PD feature.
9247 04:50:50.290093 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9248 04:50:50.317492 anx7625_start_dp_work: Secure OCM version=00
9249 04:50:50.320772 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9250 04:50:50.335898 sp_tx_get_edid_block: EDID Block = 1
9251 04:50:50.438660 Extracted contents:
9252 04:50:50.441914 header: 00 ff ff ff ff ff ff 00
9253 04:50:50.445306 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9254 04:50:50.448636 version: 01 04
9255 04:50:50.451915 basic params: 95 1f 11 78 0a
9256 04:50:50.454669 chroma info: 76 90 94 55 54 90 27 21 50 54
9257 04:50:50.459089 established: 00 00 00
9258 04:50:50.464979 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9259 04:50:50.468380 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9260 04:50:50.474688 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9261 04:50:50.481273 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9262 04:50:50.487841 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9263 04:50:50.491451 extensions: 00
9264 04:50:50.491870 checksum: fb
9265 04:50:50.492204
9266 04:50:50.494744 Manufacturer: IVO Model 57d Serial Number 0
9267 04:50:50.498335 Made week 0 of 2020
9268 04:50:50.501030 EDID version: 1.4
9269 04:50:50.501415 Digital display
9270 04:50:50.504201 6 bits per primary color channel
9271 04:50:50.504623 DisplayPort interface
9272 04:50:50.507701 Maximum image size: 31 cm x 17 cm
9273 04:50:50.510972 Gamma: 220%
9274 04:50:50.511355 Check DPMS levels
9275 04:50:50.514310 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9276 04:50:50.521124 First detailed timing is preferred timing
9277 04:50:50.521516 Established timings supported:
9278 04:50:50.524816 Standard timings supported:
9279 04:50:50.527770 Detailed timings
9280 04:50:50.530773 Hex of detail: 383680a07038204018303c0035ae10000019
9281 04:50:50.537410 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9282 04:50:50.540519 0780 0798 07c8 0820 hborder 0
9283 04:50:50.543673 0438 043b 0447 0458 vborder 0
9284 04:50:50.546909 -hsync -vsync
9285 04:50:50.546992 Did detailed timing
9286 04:50:50.554013 Hex of detail: 000000000000000000000000000000000000
9287 04:50:50.557298 Manufacturer-specified data, tag 0
9288 04:50:50.560040 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9289 04:50:50.564003 ASCII string: InfoVision
9290 04:50:50.566690 Hex of detail: 000000fe00523134304e574635205248200a
9291 04:50:50.570627 ASCII string: R140NWF5 RH
9292 04:50:50.570770 Checksum
9293 04:50:50.573316 Checksum: 0xfb (valid)
9294 04:50:50.577049 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9295 04:50:50.580081 DSI data_rate: 832800000 bps
9296 04:50:50.586735 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9297 04:50:50.590111 anx7625_parse_edid: pixelclock(138800).
9298 04:50:50.593682 hactive(1920), hsync(48), hfp(24), hbp(88)
9299 04:50:50.596780 vactive(1080), vsync(12), vfp(3), vbp(17)
9300 04:50:50.600196 anx7625_dsi_config: config dsi.
9301 04:50:50.606820 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9302 04:50:50.620246 anx7625_dsi_config: success to config DSI
9303 04:50:50.623598 anx7625_dp_start: MIPI phy setup OK.
9304 04:50:50.627338 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9305 04:50:50.630560 mtk_ddp_mode_set invalid vrefresh 60
9306 04:50:50.634272 main_disp_path_setup
9307 04:50:50.634791 ovl_layer_smi_id_en
9308 04:50:50.637081 ovl_layer_smi_id_en
9309 04:50:50.637529 ccorr_config
9310 04:50:50.637870 aal_config
9311 04:50:50.640256 gamma_config
9312 04:50:50.640828 postmask_config
9313 04:50:50.643773 dither_config
9314 04:50:50.647523 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9315 04:50:50.653471 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9316 04:50:50.656864 Root Device init finished in 552 msecs
9317 04:50:50.657285 CPU_CLUSTER: 0 init
9318 04:50:50.666803 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9319 04:50:50.670528 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9320 04:50:50.673817 APU_MBOX 0x190000b0 = 0x10001
9321 04:50:50.676772 APU_MBOX 0x190001b0 = 0x10001
9322 04:50:50.680668 APU_MBOX 0x190005b0 = 0x10001
9323 04:50:50.683915 APU_MBOX 0x190006b0 = 0x10001
9324 04:50:50.686765 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9325 04:50:50.698992 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9326 04:50:50.711642 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9327 04:50:50.718928 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9328 04:50:50.729952 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9329 04:50:50.739688 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9330 04:50:50.742909 CPU_CLUSTER: 0 init finished in 81 msecs
9331 04:50:50.745665 Devices initialized
9332 04:50:50.749454 Show all devs... After init.
9333 04:50:50.749874 Root Device: enabled 1
9334 04:50:50.752675 CPU_CLUSTER: 0: enabled 1
9335 04:50:50.755594 CPU: 00: enabled 1
9336 04:50:50.759123 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9337 04:50:50.762365 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9338 04:50:50.765752 ELOG: NV offset 0x57f000 size 0x1000
9339 04:50:50.772798 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9340 04:50:50.779182 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9341 04:50:50.782610 ELOG: Event(17) added with size 13 at 2024-02-04 04:48:07 UTC
9342 04:50:50.786161 out: cmd=0x121: 03 db 21 01 00 00 00 00
9343 04:50:50.789698 in-header: 03 f1 00 00 2c 00 00 00
9344 04:50:50.803041 in-data: 6e 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9345 04:50:50.809167 ELOG: Event(A1) added with size 10 at 2024-02-04 04:48:07 UTC
9346 04:50:50.816029 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9347 04:50:50.822554 ELOG: Event(A0) added with size 9 at 2024-02-04 04:48:07 UTC
9348 04:50:50.826430 elog_add_boot_reason: Logged dev mode boot
9349 04:50:50.829215 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9350 04:50:50.832545 Finalize devices...
9351 04:50:50.832969 Devices finalized
9352 04:50:50.839437 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9353 04:50:50.842669 Writing coreboot table at 0xffe64000
9354 04:50:50.846579 0. 000000000010a000-0000000000113fff: RAMSTAGE
9355 04:50:50.849562 1. 0000000040000000-00000000400fffff: RAM
9356 04:50:50.852959 2. 0000000040100000-000000004032afff: RAMSTAGE
9357 04:50:50.859366 3. 000000004032b000-00000000545fffff: RAM
9358 04:50:50.862475 4. 0000000054600000-000000005465ffff: BL31
9359 04:50:50.865958 5. 0000000054660000-00000000ffe63fff: RAM
9360 04:50:50.872690 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9361 04:50:50.876047 7. 0000000100000000-000000023fffffff: RAM
9362 04:50:50.876565 Passing 5 GPIOs to payload:
9363 04:50:50.882217 NAME | PORT | POLARITY | VALUE
9364 04:50:50.885520 EC in RW | 0x000000aa | low | undefined
9365 04:50:50.892045 EC interrupt | 0x00000005 | low | undefined
9366 04:50:50.895887 TPM interrupt | 0x000000ab | high | undefined
9367 04:50:50.898904 SD card detect | 0x00000011 | high | undefined
9368 04:50:50.905324 speaker enable | 0x00000093 | high | undefined
9369 04:50:50.908882 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9370 04:50:50.911947 in-header: 03 f9 00 00 02 00 00 00
9371 04:50:50.912463 in-data: 02 00
9372 04:50:50.915768 ADC[4]: Raw value=905096 ID=7
9373 04:50:50.918927 ADC[3]: Raw value=213441 ID=1
9374 04:50:50.919344 RAM Code: 0x71
9375 04:50:50.922155 ADC[6]: Raw value=75701 ID=0
9376 04:50:50.925522 ADC[5]: Raw value=213072 ID=1
9377 04:50:50.925969 SKU Code: 0x1
9378 04:50:50.932075 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b313
9379 04:50:50.936221 coreboot table: 964 bytes.
9380 04:50:50.939237 IMD ROOT 0. 0xfffff000 0x00001000
9381 04:50:50.942834 IMD SMALL 1. 0xffffe000 0x00001000
9382 04:50:50.945695 RO MCACHE 2. 0xffffc000 0x00001104
9383 04:50:50.948873 CONSOLE 3. 0xfff7c000 0x00080000
9384 04:50:50.952151 FMAP 4. 0xfff7b000 0x00000452
9385 04:50:50.955466 TIME STAMP 5. 0xfff7a000 0x00000910
9386 04:50:50.958770 VBOOT WORK 6. 0xfff66000 0x00014000
9387 04:50:50.962180 RAMOOPS 7. 0xffe66000 0x00100000
9388 04:50:50.965820 COREBOOT 8. 0xffe64000 0x00002000
9389 04:50:50.966201 IMD small region:
9390 04:50:50.968915 IMD ROOT 0. 0xffffec00 0x00000400
9391 04:50:50.972140 VPD 1. 0xffffeb80 0x0000006c
9392 04:50:50.975551 MMC STATUS 2. 0xffffeb60 0x00000004
9393 04:50:50.982121 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9394 04:50:50.982507 Probing TPM: done!
9395 04:50:50.989499 Connected to device vid:did:rid of 1ae0:0028:00
9396 04:50:50.995949 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9397 04:50:51.003718 Initialized TPM device CR50 revision 0
9398 04:50:51.004277 Checking cr50 for pending updates
9399 04:50:51.008847 Reading cr50 TPM mode
9400 04:50:51.017513 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9401 04:50:51.023908 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9402 04:50:51.064144 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9403 04:50:51.067469 Checking segment from ROM address 0x40100000
9404 04:50:51.070923 Checking segment from ROM address 0x4010001c
9405 04:50:51.077456 Loading segment from ROM address 0x40100000
9406 04:50:51.077849 code (compression=0)
9407 04:50:51.084369 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9408 04:50:51.094560 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9409 04:50:51.094984 it's not compressed!
9410 04:50:51.100985 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9411 04:50:51.104074 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9412 04:50:51.124645 Loading segment from ROM address 0x4010001c
9413 04:50:51.125066 Entry Point 0x80000000
9414 04:50:51.128142 Loaded segments
9415 04:50:51.131716 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9416 04:50:51.137889 Jumping to boot code at 0x80000000(0xffe64000)
9417 04:50:51.144734 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9418 04:50:51.151350 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9419 04:50:51.159497 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9420 04:50:51.162219 Checking segment from ROM address 0x40100000
9421 04:50:51.165533 Checking segment from ROM address 0x4010001c
9422 04:50:51.172307 Loading segment from ROM address 0x40100000
9423 04:50:51.172699 code (compression=1)
9424 04:50:51.178969 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9425 04:50:51.202601 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9426 04:50:51.203015 using LZMA
9427 04:50:51.203376 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9428 04:50:51.204360 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9429 04:50:51.207493 Loading segment from ROM address 0x4010001c
9430 04:50:51.207925 Entry Point 0x54601000
9431 04:50:51.210925 Loaded segments
9432 04:50:51.214967 NOTICE: MT8192 bl31_setup
9433 04:50:51.221191 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9434 04:50:51.224659 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9435 04:50:51.228034 WARNING: region 0:
9436 04:50:51.231166 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9437 04:50:51.231581 WARNING: region 1:
9438 04:50:51.238066 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9439 04:50:51.241106 WARNING: region 2:
9440 04:50:51.244100 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9441 04:50:51.247954 WARNING: region 3:
9442 04:50:51.251641 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9443 04:50:51.254668 WARNING: region 4:
9444 04:50:51.261262 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9445 04:50:51.261790 WARNING: region 5:
9446 04:50:51.264697 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9447 04:50:51.267488 WARNING: region 6:
9448 04:50:51.271454 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9449 04:50:51.274650 WARNING: region 7:
9450 04:50:51.278141 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9451 04:50:51.284997 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9452 04:50:51.287615 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9453 04:50:51.290886 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9454 04:50:51.297744 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9455 04:50:51.301016 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9456 04:50:51.304465 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9457 04:50:51.311022 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9458 04:50:51.314898 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9459 04:50:51.318183 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9460 04:50:51.324974 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9461 04:50:51.328175 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9462 04:50:51.335090 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9463 04:50:51.337857 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9464 04:50:51.341222 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9465 04:50:51.347896 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9466 04:50:51.351286 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9467 04:50:51.354541 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9468 04:50:51.361313 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9469 04:50:51.364595 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9470 04:50:51.367986 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9471 04:50:51.374882 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9472 04:50:51.378244 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9473 04:50:51.384792 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9474 04:50:51.388423 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9475 04:50:51.394847 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9476 04:50:51.398266 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9477 04:50:51.401471 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9478 04:50:51.408058 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9479 04:50:51.411723 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9480 04:50:51.414919 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9481 04:50:51.421589 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9482 04:50:51.424620 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9483 04:50:51.427759 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9484 04:50:51.435217 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9485 04:50:51.438506 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9486 04:50:51.441781 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9487 04:50:51.445156 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9488 04:50:51.451584 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9489 04:50:51.454805 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9490 04:50:51.458466 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9491 04:50:51.461801 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9492 04:50:51.468167 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9493 04:50:51.471333 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9494 04:50:51.474635 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9495 04:50:51.477975 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9496 04:50:51.484642 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9497 04:50:51.488762 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9498 04:50:51.492057 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9499 04:50:51.498242 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9500 04:50:51.501282 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9501 04:50:51.504618 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9502 04:50:51.511282 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9503 04:50:51.514626 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9504 04:50:51.521323 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9505 04:50:51.524539 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9506 04:50:51.530981 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9507 04:50:51.534413 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9508 04:50:51.541324 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9509 04:50:51.544621 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9510 04:50:51.547944 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9511 04:50:51.554738 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9512 04:50:51.557866 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9513 04:50:51.564575 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9514 04:50:51.567699 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9515 04:50:51.574341 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9516 04:50:51.577912 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9517 04:50:51.581423 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9518 04:50:51.588011 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9519 04:50:51.591637 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9520 04:50:51.598344 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9521 04:50:51.601522 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9522 04:50:51.607785 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9523 04:50:51.611342 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9524 04:50:51.614835 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9525 04:50:51.621316 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9526 04:50:51.624611 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9527 04:50:51.631510 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9528 04:50:51.634936 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9529 04:50:51.641489 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9530 04:50:51.644984 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9531 04:50:51.648443 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9532 04:50:51.655426 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9533 04:50:51.657921 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9534 04:50:51.664682 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9535 04:50:51.667859 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9536 04:50:51.674779 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9537 04:50:51.677901 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9538 04:50:51.681267 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9539 04:50:51.688259 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9540 04:50:51.691760 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9541 04:50:51.697987 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9542 04:50:51.701328 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9543 04:50:51.708067 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9544 04:50:51.711497 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9545 04:50:51.714750 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9546 04:50:51.721746 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9547 04:50:51.724696 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9548 04:50:51.728446 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9549 04:50:51.734914 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9550 04:50:51.738344 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9551 04:50:51.741767 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9552 04:50:51.748109 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9553 04:50:51.751813 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9554 04:50:51.755200 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9555 04:50:51.761563 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9556 04:50:51.764904 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9557 04:50:51.771753 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9558 04:50:51.775019 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9559 04:50:51.778045 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9560 04:50:51.785006 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9561 04:50:51.788138 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9562 04:50:51.791520 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9563 04:50:51.798208 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9564 04:50:51.801581 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9565 04:50:51.808555 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9566 04:50:51.811711 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9567 04:50:51.814958 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9568 04:50:51.821703 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9569 04:50:51.825107 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9570 04:50:51.828415 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9571 04:50:51.831677 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9572 04:50:51.839167 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9573 04:50:51.841748 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9574 04:50:51.845570 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9575 04:50:51.848372 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9576 04:50:51.855862 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9577 04:50:51.858869 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9578 04:50:51.865064 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9579 04:50:51.868406 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9580 04:50:51.871936 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9581 04:50:51.878897 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9582 04:50:51.882441 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9583 04:50:51.888345 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9584 04:50:51.892020 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9585 04:50:51.895106 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9586 04:50:51.902395 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9587 04:50:51.905462 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9588 04:50:51.908800 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9589 04:50:51.915091 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9590 04:50:51.918199 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9591 04:50:51.925198 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9592 04:50:51.928393 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9593 04:50:51.931833 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9594 04:50:51.938559 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9595 04:50:51.942218 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9596 04:50:51.948766 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9597 04:50:51.952114 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9598 04:50:51.955154 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9599 04:50:51.961692 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9600 04:50:51.965548 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9601 04:50:51.968696 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9602 04:50:51.975001 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9603 04:50:51.978630 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9604 04:50:51.985093 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9605 04:50:51.988480 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9606 04:50:51.991919 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9607 04:50:51.998513 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9608 04:50:52.002011 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9609 04:50:52.008686 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9610 04:50:52.012084 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9611 04:50:52.015323 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9612 04:50:52.021941 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9613 04:50:52.025256 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9614 04:50:52.031749 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9615 04:50:52.035318 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9616 04:50:52.038526 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9617 04:50:52.045057 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9618 04:50:52.048182 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9619 04:50:52.051577 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9620 04:50:52.058201 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9621 04:50:52.061370 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9622 04:50:52.067820 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9623 04:50:52.071502 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9624 04:50:52.074704 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9625 04:50:52.081148 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9626 04:50:52.084800 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9627 04:50:52.091677 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9628 04:50:52.094868 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9629 04:50:52.098264 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9630 04:50:52.105175 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9631 04:50:52.108543 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9632 04:50:52.111678 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9633 04:50:52.118140 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9634 04:50:52.121363 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9635 04:50:52.127901 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9636 04:50:52.131304 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9637 04:50:52.134720 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9638 04:50:52.141316 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9639 04:50:52.144858 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9640 04:50:52.151119 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9641 04:50:52.154901 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9642 04:50:52.160988 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9643 04:50:52.164553 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9644 04:50:52.167725 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9645 04:50:52.174646 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9646 04:50:52.177989 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9647 04:50:52.185033 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9648 04:50:52.188357 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9649 04:50:52.191865 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9650 04:50:52.198141 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9651 04:50:52.201834 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9652 04:50:52.208261 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9653 04:50:52.211682 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9654 04:50:52.215120 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9655 04:50:52.221518 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9656 04:50:52.224551 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9657 04:50:52.231359 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9658 04:50:52.234779 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9659 04:50:52.238163 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9660 04:50:52.244711 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9661 04:50:52.248334 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9662 04:50:52.254751 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9663 04:50:52.258208 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9664 04:50:52.264849 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9665 04:50:52.268017 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9666 04:50:52.271541 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9667 04:50:52.277862 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9668 04:50:52.280943 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9669 04:50:52.287802 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9670 04:50:52.291023 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9671 04:50:52.297592 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9672 04:50:52.301245 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9673 04:50:52.304194 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9674 04:50:52.310786 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9675 04:50:52.313957 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9676 04:50:52.321254 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9677 04:50:52.324343 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9678 04:50:52.327513 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9679 04:50:52.334690 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9680 04:50:52.338204 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9681 04:50:52.341193 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9682 04:50:52.344517 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9683 04:50:52.351157 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9684 04:50:52.354661 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9685 04:50:52.357994 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9686 04:50:52.364155 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9687 04:50:52.367968 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9688 04:50:52.370983 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9689 04:50:52.377431 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9690 04:50:52.380652 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9691 04:50:52.384004 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9692 04:50:52.391224 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9693 04:50:52.394625 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9694 04:50:52.401017 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9695 04:50:52.404428 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9696 04:50:52.407643 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9697 04:50:52.414031 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9698 04:50:52.417366 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9699 04:50:52.420576 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9700 04:50:52.427868 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9701 04:50:52.430941 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9702 04:50:52.437670 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9703 04:50:52.440670 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9704 04:50:52.443841 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9705 04:50:52.451196 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9706 04:50:52.454161 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9707 04:50:52.457156 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9708 04:50:52.464166 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9709 04:50:52.467256 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9710 04:50:52.471059 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9711 04:50:52.477354 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9712 04:50:52.480567 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9713 04:50:52.487405 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9714 04:50:52.490538 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9715 04:50:52.493674 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9716 04:50:52.500433 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9717 04:50:52.503969 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9718 04:50:52.507207 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9719 04:50:52.513836 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9720 04:50:52.517007 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9721 04:50:52.521029 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9722 04:50:52.523654 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9723 04:50:52.526916 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9724 04:50:52.533742 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9725 04:50:52.537058 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9726 04:50:52.540748 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9727 04:50:52.543720 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9728 04:50:52.550867 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9729 04:50:52.553883 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9730 04:50:52.556844 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9731 04:50:52.564100 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9732 04:50:52.566844 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9733 04:50:52.570259 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9734 04:50:52.576742 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9735 04:50:52.580632 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9736 04:50:52.586935 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9737 04:50:52.590471 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9738 04:50:52.593960 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9739 04:50:52.600025 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9740 04:50:52.603750 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9741 04:50:52.610307 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9742 04:50:52.613481 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9743 04:50:52.617005 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9744 04:50:52.623389 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9745 04:50:52.626900 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9746 04:50:52.633586 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9747 04:50:52.636863 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9748 04:50:52.640200 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9749 04:50:52.646584 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9750 04:50:52.649710 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9751 04:50:52.656405 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9752 04:50:52.659578 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9753 04:50:52.666573 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9754 04:50:52.669592 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9755 04:50:52.673134 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9756 04:50:52.679883 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9757 04:50:52.682765 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9758 04:50:52.689415 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9759 04:50:52.692804 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9760 04:50:52.696129 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9761 04:50:52.703545 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9762 04:50:52.706224 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9763 04:50:52.713036 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9764 04:50:52.716582 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9765 04:50:52.719476 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9766 04:50:52.726178 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9767 04:50:52.729478 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9768 04:50:52.735891 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9769 04:50:52.739635 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9770 04:50:52.746368 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9771 04:50:52.749725 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9772 04:50:52.752324 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9773 04:50:52.759745 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9774 04:50:52.763051 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9775 04:50:52.766129 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9776 04:50:52.772508 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9777 04:50:52.775867 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9778 04:50:52.782615 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9779 04:50:52.786315 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9780 04:50:52.789459 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9781 04:50:52.796091 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9782 04:50:52.799238 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9783 04:50:52.806001 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9784 04:50:52.808930 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9785 04:50:52.815654 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9786 04:50:52.819397 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9787 04:50:52.822524 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9788 04:50:52.829093 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9789 04:50:52.832232 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9790 04:50:52.839097 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9791 04:50:52.842154 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9792 04:50:52.845391 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9793 04:50:52.852445 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9794 04:50:52.855914 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9795 04:50:52.862625 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9796 04:50:52.865655 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9797 04:50:52.869176 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9798 04:50:52.875963 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9799 04:50:52.879220 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9800 04:50:52.885515 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9801 04:50:52.888750 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9802 04:50:52.895314 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9803 04:50:52.898659 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9804 04:50:52.902053 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9805 04:50:52.908273 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9806 04:50:52.912139 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9807 04:50:52.918350 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9808 04:50:52.921724 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9809 04:50:52.928560 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9810 04:50:52.931661 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9811 04:50:52.938677 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9812 04:50:52.941669 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9813 04:50:52.944925 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9814 04:50:52.951521 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9815 04:50:52.955242 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9816 04:50:52.961766 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9817 04:50:52.965412 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9818 04:50:52.972030 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9819 04:50:52.974756 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9820 04:50:52.978152 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9821 04:50:52.984771 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9822 04:50:52.988475 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9823 04:50:52.994998 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9824 04:50:52.998681 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9825 04:50:53.004488 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9826 04:50:53.008197 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9827 04:50:53.011693 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9828 04:50:53.017913 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9829 04:50:53.021019 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9830 04:50:53.028118 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9831 04:50:53.031392 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9832 04:50:53.038210 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9833 04:50:53.041078 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9834 04:50:53.047533 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9835 04:50:53.051454 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9836 04:50:53.054381 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9837 04:50:53.060849 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9838 04:50:53.064739 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9839 04:50:53.071330 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9840 04:50:53.074567 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9841 04:50:53.080927 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9842 04:50:53.084401 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9843 04:50:53.087671 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9844 04:50:53.094039 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9845 04:50:53.097551 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9846 04:50:53.103987 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9847 04:50:53.107725 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9848 04:50:53.113828 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9849 04:50:53.117224 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9850 04:50:53.120629 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9851 04:50:53.127335 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9852 04:50:53.131229 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9853 04:50:53.137230 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9854 04:50:53.140612 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9855 04:50:53.143984 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9856 04:50:53.151017 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9857 04:50:53.154221 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9858 04:50:53.160437 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9859 04:50:53.163769 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9860 04:50:53.170955 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9861 04:50:53.174022 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9862 04:50:53.180762 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9863 04:50:53.183932 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9864 04:50:53.190558 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9865 04:50:53.193795 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9866 04:50:53.200521 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9867 04:50:53.203906 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9868 04:50:53.210802 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9869 04:50:53.214020 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9870 04:50:53.220892 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9871 04:50:53.223524 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9872 04:50:53.230443 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9873 04:50:53.233770 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9874 04:50:53.240416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9875 04:50:53.243728 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9876 04:50:53.250576 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9877 04:50:53.253892 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9878 04:50:53.260795 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9879 04:50:53.263939 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9880 04:50:53.270542 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9881 04:50:53.273426 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9882 04:50:53.280221 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9883 04:50:53.283593 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9884 04:50:53.290168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9885 04:50:53.293353 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9886 04:50:53.296931 INFO: [APUAPC] vio 0
9887 04:50:53.300018 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9888 04:50:53.303639 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9889 04:50:53.306710 INFO: [APUAPC] D0_APC_0: 0x400510
9890 04:50:53.310339 INFO: [APUAPC] D0_APC_1: 0x0
9891 04:50:53.312970 INFO: [APUAPC] D0_APC_2: 0x1540
9892 04:50:53.316697 INFO: [APUAPC] D0_APC_3: 0x0
9893 04:50:53.320151 INFO: [APUAPC] D1_APC_0: 0xffffffff
9894 04:50:53.323530 INFO: [APUAPC] D1_APC_1: 0xffffffff
9895 04:50:53.326636 INFO: [APUAPC] D1_APC_2: 0x3fffff
9896 04:50:53.329920 INFO: [APUAPC] D1_APC_3: 0x0
9897 04:50:53.333382 INFO: [APUAPC] D2_APC_0: 0xffffffff
9898 04:50:53.336679 INFO: [APUAPC] D2_APC_1: 0xffffffff
9899 04:50:53.340100 INFO: [APUAPC] D2_APC_2: 0x3fffff
9900 04:50:53.343374 INFO: [APUAPC] D2_APC_3: 0x0
9901 04:50:53.345951 INFO: [APUAPC] D3_APC_0: 0xffffffff
9902 04:50:53.349186 INFO: [APUAPC] D3_APC_1: 0xffffffff
9903 04:50:53.352909 INFO: [APUAPC] D3_APC_2: 0x3fffff
9904 04:50:53.356244 INFO: [APUAPC] D3_APC_3: 0x0
9905 04:50:53.359741 INFO: [APUAPC] D4_APC_0: 0xffffffff
9906 04:50:53.362999 INFO: [APUAPC] D4_APC_1: 0xffffffff
9907 04:50:53.366393 INFO: [APUAPC] D4_APC_2: 0x3fffff
9908 04:50:53.369068 INFO: [APUAPC] D4_APC_3: 0x0
9909 04:50:53.372527 INFO: [APUAPC] D5_APC_0: 0xffffffff
9910 04:50:53.376415 INFO: [APUAPC] D5_APC_1: 0xffffffff
9911 04:50:53.379474 INFO: [APUAPC] D5_APC_2: 0x3fffff
9912 04:50:53.382381 INFO: [APUAPC] D5_APC_3: 0x0
9913 04:50:53.385932 INFO: [APUAPC] D6_APC_0: 0xffffffff
9914 04:50:53.389269 INFO: [APUAPC] D6_APC_1: 0xffffffff
9915 04:50:53.392682 INFO: [APUAPC] D6_APC_2: 0x3fffff
9916 04:50:53.396108 INFO: [APUAPC] D6_APC_3: 0x0
9917 04:50:53.399297 INFO: [APUAPC] D7_APC_0: 0xffffffff
9918 04:50:53.402670 INFO: [APUAPC] D7_APC_1: 0xffffffff
9919 04:50:53.406015 INFO: [APUAPC] D7_APC_2: 0x3fffff
9920 04:50:53.409500 INFO: [APUAPC] D7_APC_3: 0x0
9921 04:50:53.412781 INFO: [APUAPC] D8_APC_0: 0xffffffff
9922 04:50:53.415780 INFO: [APUAPC] D8_APC_1: 0xffffffff
9923 04:50:53.418866 INFO: [APUAPC] D8_APC_2: 0x3fffff
9924 04:50:53.422561 INFO: [APUAPC] D8_APC_3: 0x0
9925 04:50:53.425555 INFO: [APUAPC] D9_APC_0: 0xffffffff
9926 04:50:53.428765 INFO: [APUAPC] D9_APC_1: 0xffffffff
9927 04:50:53.432210 INFO: [APUAPC] D9_APC_2: 0x3fffff
9928 04:50:53.435656 INFO: [APUAPC] D9_APC_3: 0x0
9929 04:50:53.438892 INFO: [APUAPC] D10_APC_0: 0xffffffff
9930 04:50:53.442220 INFO: [APUAPC] D10_APC_1: 0xffffffff
9931 04:50:53.445592 INFO: [APUAPC] D10_APC_2: 0x3fffff
9932 04:50:53.448885 INFO: [APUAPC] D10_APC_3: 0x0
9933 04:50:53.452052 INFO: [APUAPC] D11_APC_0: 0xffffffff
9934 04:50:53.455350 INFO: [APUAPC] D11_APC_1: 0xffffffff
9935 04:50:53.458522 INFO: [APUAPC] D11_APC_2: 0x3fffff
9936 04:50:53.462330 INFO: [APUAPC] D11_APC_3: 0x0
9937 04:50:53.465754 INFO: [APUAPC] D12_APC_0: 0xffffffff
9938 04:50:53.469061 INFO: [APUAPC] D12_APC_1: 0xffffffff
9939 04:50:53.471967 INFO: [APUAPC] D12_APC_2: 0x3fffff
9940 04:50:53.475313 INFO: [APUAPC] D12_APC_3: 0x0
9941 04:50:53.478715 INFO: [APUAPC] D13_APC_0: 0xffffffff
9942 04:50:53.482096 INFO: [APUAPC] D13_APC_1: 0xffffffff
9943 04:50:53.485345 INFO: [APUAPC] D13_APC_2: 0x3fffff
9944 04:50:53.488555 INFO: [APUAPC] D13_APC_3: 0x0
9945 04:50:53.491695 INFO: [APUAPC] D14_APC_0: 0xffffffff
9946 04:50:53.495004 INFO: [APUAPC] D14_APC_1: 0xffffffff
9947 04:50:53.498779 INFO: [APUAPC] D14_APC_2: 0x3fffff
9948 04:50:53.501750 INFO: [APUAPC] D14_APC_3: 0x0
9949 04:50:53.505512 INFO: [APUAPC] D15_APC_0: 0xffffffff
9950 04:50:53.508840 INFO: [APUAPC] D15_APC_1: 0xffffffff
9951 04:50:53.512249 INFO: [APUAPC] D15_APC_2: 0x3fffff
9952 04:50:53.515572 INFO: [APUAPC] D15_APC_3: 0x0
9953 04:50:53.515993 INFO: [APUAPC] APC_CON: 0x4
9954 04:50:53.519038 INFO: [NOCDAPC] D0_APC_0: 0x0
9955 04:50:53.521686 INFO: [NOCDAPC] D0_APC_1: 0x0
9956 04:50:53.525114 INFO: [NOCDAPC] D1_APC_0: 0x0
9957 04:50:53.528240 INFO: [NOCDAPC] D1_APC_1: 0xfff
9958 04:50:53.531996 INFO: [NOCDAPC] D2_APC_0: 0x0
9959 04:50:53.535414 INFO: [NOCDAPC] D2_APC_1: 0xfff
9960 04:50:53.538776 INFO: [NOCDAPC] D3_APC_0: 0x0
9961 04:50:53.542154 INFO: [NOCDAPC] D3_APC_1: 0xfff
9962 04:50:53.545301 INFO: [NOCDAPC] D4_APC_0: 0x0
9963 04:50:53.548827 INFO: [NOCDAPC] D4_APC_1: 0xfff
9964 04:50:53.549249 INFO: [NOCDAPC] D5_APC_0: 0x0
9965 04:50:53.552103 INFO: [NOCDAPC] D5_APC_1: 0xfff
9966 04:50:53.555920 INFO: [NOCDAPC] D6_APC_0: 0x0
9967 04:50:53.559165 INFO: [NOCDAPC] D6_APC_1: 0xfff
9968 04:50:53.562002 INFO: [NOCDAPC] D7_APC_0: 0x0
9969 04:50:53.565001 INFO: [NOCDAPC] D7_APC_1: 0xfff
9970 04:50:53.568507 INFO: [NOCDAPC] D8_APC_0: 0x0
9971 04:50:53.571891 INFO: [NOCDAPC] D8_APC_1: 0xfff
9972 04:50:53.575320 INFO: [NOCDAPC] D9_APC_0: 0x0
9973 04:50:53.578233 INFO: [NOCDAPC] D9_APC_1: 0xfff
9974 04:50:53.578658 INFO: [NOCDAPC] D10_APC_0: 0x0
9975 04:50:53.581841 INFO: [NOCDAPC] D10_APC_1: 0xfff
9976 04:50:53.585463 INFO: [NOCDAPC] D11_APC_0: 0x0
9977 04:50:53.588794 INFO: [NOCDAPC] D11_APC_1: 0xfff
9978 04:50:53.591783 INFO: [NOCDAPC] D12_APC_0: 0x0
9979 04:50:53.594956 INFO: [NOCDAPC] D12_APC_1: 0xfff
9980 04:50:53.598593 INFO: [NOCDAPC] D13_APC_0: 0x0
9981 04:50:53.601690 INFO: [NOCDAPC] D13_APC_1: 0xfff
9982 04:50:53.604957 INFO: [NOCDAPC] D14_APC_0: 0x0
9983 04:50:53.608391 INFO: [NOCDAPC] D14_APC_1: 0xfff
9984 04:50:53.611740 INFO: [NOCDAPC] D15_APC_0: 0x0
9985 04:50:53.614860 INFO: [NOCDAPC] D15_APC_1: 0xfff
9986 04:50:53.618527 INFO: [NOCDAPC] APC_CON: 0x4
9987 04:50:53.621255 INFO: [APUAPC] set_apusys_apc done
9988 04:50:53.624631 INFO: [DEVAPC] devapc_init done
9989 04:50:53.628024 INFO: GICv3 without legacy support detected.
9990 04:50:53.631439 INFO: ARM GICv3 driver initialized in EL3
9991 04:50:53.634745 INFO: Maximum SPI INTID supported: 639
9992 04:50:53.637980 INFO: BL31: Initializing runtime services
9993 04:50:53.644549 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9994 04:50:53.648021 INFO: SPM: enable CPC mode
9995 04:50:53.655064 INFO: mcdi ready for mcusys-off-idle and system suspend
9996 04:50:53.658118 INFO: BL31: Preparing for EL3 exit to normal world
9997 04:50:53.661378 INFO: Entry point address = 0x80000000
9998 04:50:53.664562 INFO: SPSR = 0x8
9999 04:50:53.669154
10000 04:50:53.669574
10001 04:50:53.669910
10002 04:50:53.672595 Starting depthcharge on Spherion...
10003 04:50:53.673017
10004 04:50:53.673351 Wipe memory regions:
10005 04:50:53.673665
10006 04:50:53.676095 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10007 04:50:53.676640 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10008 04:50:53.677050 Setting prompt string to ['asurada:']
10009 04:50:53.677447 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10010 04:50:53.678114 [0x00000040000000, 0x00000054600000)
10011 04:50:53.798404
10012 04:50:53.798934 [0x00000054660000, 0x00000080000000)
10013 04:50:54.059286
10014 04:50:54.059809 [0x000000821a7280, 0x000000ffe64000)
10015 04:50:54.803408
10016 04:50:54.803946 [0x00000100000000, 0x00000240000000)
10017 04:50:56.693889
10018 04:50:56.696216 Initializing XHCI USB controller at 0x11200000.
10019 04:50:57.734407
10020 04:50:57.737482 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10021 04:50:57.737912
10022 04:50:57.738248
10023 04:50:57.738559
10024 04:50:57.739286 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10026 04:50:57.840452 asurada: tftpboot 192.168.201.1 12699854/tftp-deploy-u2wxkg8_/kernel/image.itb 12699854/tftp-deploy-u2wxkg8_/kernel/cmdline
10027 04:50:57.841164 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10028 04:50:57.841664 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10029 04:50:57.845916 tftpboot 192.168.201.1 12699854/tftp-deploy-u2wxkg8_/kernel/image.itp-deploy-u2wxkg8_/kernel/cmdline
10030 04:50:57.846326
10031 04:50:57.846662 Waiting for link
10032 04:50:58.006190
10033 04:50:58.006340 R8152: Initializing
10034 04:50:58.006407
10035 04:50:58.009153 Version 9 (ocp_data = 6010)
10036 04:50:58.009242
10037 04:50:58.012594 R8152: Done initializing
10038 04:50:58.012768
10039 04:50:58.012853 Adding net device
10040 04:50:59.882248
10041 04:50:59.882395 done.
10042 04:50:59.882471
10043 04:50:59.882554 MAC: 00:e0:4c:78:7a:aa
10044 04:50:59.882627
10045 04:50:59.885418 Sending DHCP discover... done.
10046 04:50:59.885526
10047 04:50:59.888745 Waiting for reply... done.
10048 04:50:59.888840
10049 04:50:59.892261 Sending DHCP request... done.
10050 04:50:59.892373
10051 04:50:59.892443 Waiting for reply... done.
10052 04:50:59.892572
10053 04:50:59.895461 My ip is 192.168.201.12
10054 04:50:59.895541
10055 04:50:59.898564 The DHCP server ip is 192.168.201.1
10056 04:50:59.898646
10057 04:50:59.902315 TFTP server IP predefined by user: 192.168.201.1
10058 04:50:59.902395
10059 04:50:59.908730 Bootfile predefined by user: 12699854/tftp-deploy-u2wxkg8_/kernel/image.itb
10060 04:50:59.908812
10061 04:50:59.912035 Sending tftp read request... done.
10062 04:50:59.912115
10063 04:50:59.915176 Waiting for the transfer...
10064 04:50:59.915294
10065 04:51:00.173519 00000000 ################################################################
10066 04:51:00.173666
10067 04:51:00.418969 00080000 ################################################################
10068 04:51:00.419116
10069 04:51:00.665169 00100000 ################################################################
10070 04:51:00.665319
10071 04:51:00.927800 00180000 ################################################################
10072 04:51:00.927948
10073 04:51:01.178854 00200000 ################################################################
10074 04:51:01.179004
10075 04:51:01.431730 00280000 ################################################################
10076 04:51:01.431930
10077 04:51:01.681565 00300000 ################################################################
10078 04:51:01.681711
10079 04:51:01.938990 00380000 ################################################################
10080 04:51:01.939146
10081 04:51:02.192431 00400000 ################################################################
10082 04:51:02.192579
10083 04:51:02.442719 00480000 ################################################################
10084 04:51:02.442864
10085 04:51:02.699168 00500000 ################################################################
10086 04:51:02.699318
10087 04:51:02.953409 00580000 ################################################################
10088 04:51:02.953554
10089 04:51:03.205569 00600000 ################################################################
10090 04:51:03.205727
10091 04:51:03.462844 00680000 ################################################################
10092 04:51:03.463016
10093 04:51:03.713407 00700000 ################################################################
10094 04:51:03.713551
10095 04:51:03.964123 00780000 ################################################################
10096 04:51:03.964306
10097 04:51:04.227464 00800000 ################################################################
10098 04:51:04.227612
10099 04:51:04.477758 00880000 ################################################################
10100 04:51:04.477926
10101 04:51:04.729886 00900000 ################################################################
10102 04:51:04.730028
10103 04:51:04.978590 00980000 ################################################################
10104 04:51:04.978761
10105 04:51:05.226987 00a00000 ################################################################
10106 04:51:05.227135
10107 04:51:05.492405 00a80000 ################################################################
10108 04:51:05.492554
10109 04:51:05.734476 00b00000 ################################################################
10110 04:51:05.734630
10111 04:51:05.985202 00b80000 ################################################################
10112 04:51:05.985334
10113 04:51:06.239403 00c00000 ################################################################
10114 04:51:06.239531
10115 04:51:06.494706 00c80000 ################################################################
10116 04:51:06.494860
10117 04:51:06.738907 00d00000 ################################################################
10118 04:51:06.739068
10119 04:51:06.989350 00d80000 ################################################################
10120 04:51:06.989479
10121 04:51:07.245668 00e00000 ################################################################
10122 04:51:07.245866
10123 04:51:07.497996 00e80000 ################################################################
10124 04:51:07.498125
10125 04:51:07.741851 00f00000 ################################################################
10126 04:51:07.742006
10127 04:51:08.003999 00f80000 ################################################################
10128 04:51:08.004128
10129 04:51:08.260826 01000000 ################################################################
10130 04:51:08.260981
10131 04:51:08.505048 01080000 ################################################################
10132 04:51:08.505180
10133 04:51:08.759878 01100000 ################################################################
10134 04:51:08.760044
10135 04:51:09.007485 01180000 ################################################################
10136 04:51:09.007643
10137 04:51:09.263811 01200000 ################################################################
10138 04:51:09.263967
10139 04:51:09.515342 01280000 ################################################################
10140 04:51:09.515479
10141 04:51:09.766948 01300000 ################################################################
10142 04:51:09.767084
10143 04:51:10.026651 01380000 ################################################################
10144 04:51:10.026781
10145 04:51:10.275173 01400000 ################################################################
10146 04:51:10.275356
10147 04:51:10.528088 01480000 ################################################################
10148 04:51:10.528218
10149 04:51:10.778757 01500000 ################################################################
10150 04:51:10.778906
10151 04:51:11.039571 01580000 ################################################################
10152 04:51:11.039710
10153 04:51:11.286591 01600000 ################################################################
10154 04:51:11.286726
10155 04:51:11.538927 01680000 ################################################################
10156 04:51:11.539063
10157 04:51:11.793569 01700000 ################################################################
10158 04:51:11.793708
10159 04:51:12.048235 01780000 ################################################################
10160 04:51:12.048422
10161 04:51:12.307231 01800000 ################################################################
10162 04:51:12.307382
10163 04:51:12.565069 01880000 ################################################################
10164 04:51:12.565227
10165 04:51:12.836402 01900000 ################################################################
10166 04:51:12.836546
10167 04:51:13.099939 01980000 ################################################################
10168 04:51:13.100083
10169 04:51:13.360385 01a00000 ################################################################
10170 04:51:13.360523
10171 04:51:13.619571 01a80000 ################################################################
10172 04:51:13.619715
10173 04:51:13.876114 01b00000 ################################################################
10174 04:51:13.876299
10175 04:51:14.149139 01b80000 ################################################################
10176 04:51:14.149286
10177 04:51:14.400992 01c00000 ################################################################
10178 04:51:14.401135
10179 04:51:14.665609 01c80000 ################################################################
10180 04:51:14.665761
10181 04:51:14.929669 01d00000 ################################################################
10182 04:51:14.929822
10183 04:51:15.203761 01d80000 ################################################################
10184 04:51:15.203896
10185 04:51:15.459957 01e00000 ################################################################
10186 04:51:15.460091
10187 04:51:15.705504 01e80000 ################################################################
10188 04:51:15.705637
10189 04:51:15.964552 01f00000 ################################################################
10190 04:51:15.964685
10191 04:51:16.227631 01f80000 ################################################################
10192 04:51:16.227762
10193 04:51:16.470065 02000000 ################################################################
10194 04:51:16.470203
10195 04:51:16.723848 02080000 ################################################################
10196 04:51:16.723983
10197 04:51:16.983182 02100000 ################################################################
10198 04:51:16.983341
10199 04:51:17.239712 02180000 ################################################################
10200 04:51:17.239879
10201 04:51:17.497722 02200000 ################################################################
10202 04:51:17.497862
10203 04:51:17.755509 02280000 ################################################################
10204 04:51:17.755671
10205 04:51:18.000194 02300000 ################################################################
10206 04:51:18.000363
10207 04:51:18.252396 02380000 ################################################################
10208 04:51:18.252559
10209 04:51:18.506884 02400000 ################################################################
10210 04:51:18.507051
10211 04:51:18.751932 02480000 ################################################################
10212 04:51:18.752071
10213 04:51:19.007372 02500000 ################################################################
10214 04:51:19.007545
10215 04:51:19.275580 02580000 ################################################################
10216 04:51:19.275742
10217 04:51:19.536708 02600000 ################################################################
10218 04:51:19.536846
10219 04:51:19.796089 02680000 ################################################################
10220 04:51:19.796252
10221 04:51:20.055381 02700000 ################################################################
10222 04:51:20.055561
10223 04:51:20.321892 02780000 ################################################################
10224 04:51:20.322031
10225 04:51:20.569662 02800000 ################################################################
10226 04:51:20.569799
10227 04:51:20.837712 02880000 ################################################################
10228 04:51:20.837882
10229 04:51:21.091828 02900000 ################################################################
10230 04:51:21.092004
10231 04:51:21.351503 02980000 ################################################################
10232 04:51:21.351674
10233 04:51:21.611692 02a00000 ################################################################
10234 04:51:21.611834
10235 04:51:21.870631 02a80000 ################################################################
10236 04:51:21.870799
10237 04:51:22.123613 02b00000 ################################################################
10238 04:51:22.123766
10239 04:51:22.371758 02b80000 ################################################################
10240 04:51:22.371902
10241 04:51:22.621574 02c00000 ################################################################
10242 04:51:22.621723
10243 04:51:22.871220 02c80000 ################################################################
10244 04:51:22.871391
10245 04:51:23.119850 02d00000 ################################################################
10246 04:51:23.120001
10247 04:51:23.383233 02d80000 ################################################################
10248 04:51:23.383410
10249 04:51:23.642060 02e00000 ################################################################
10250 04:51:23.642203
10251 04:51:23.886751 02e80000 ################################################################
10252 04:51:23.886899
10253 04:51:24.136569 02f00000 ################################################################
10254 04:51:24.136719
10255 04:51:24.393292 02f80000 ################################################################
10256 04:51:24.393442
10257 04:51:24.653979 03000000 ################################################################
10258 04:51:24.654145
10259 04:51:24.912651 03080000 ################################################################
10260 04:51:24.912779
10261 04:51:24.950418 03100000 ########## done.
10262 04:51:24.950519
10263 04:51:24.953722 The bootfile was 51458746 bytes long.
10264 04:51:24.953798
10265 04:51:24.956881 Sending tftp read request... done.
10266 04:51:24.956973
10267 04:51:24.960220 Waiting for the transfer...
10268 04:51:24.960340
10269 04:51:24.963822 00000000 # done.
10270 04:51:24.963902
10271 04:51:24.970076 Command line loaded dynamically from TFTP file: 12699854/tftp-deploy-u2wxkg8_/kernel/cmdline
10272 04:51:24.970189
10273 04:51:24.983370 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10274 04:51:24.983454
10275 04:51:24.983522 Loading FIT.
10276 04:51:24.986611
10277 04:51:24.986712 Image ramdisk-1 has 39360925 bytes.
10278 04:51:24.986777
10279 04:51:24.990248 Image fdt-1 has 47278 bytes.
10280 04:51:24.990356
10281 04:51:24.993552 Image kernel-1 has 12048508 bytes.
10282 04:51:24.993626
10283 04:51:25.003448 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10284 04:51:25.003525
10285 04:51:25.020371 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10286 04:51:25.020458
10287 04:51:25.027069 Choosing best match conf-1 for compat google,spherion-rev2.
10288 04:51:25.027156
10289 04:51:25.034625 Connected to device vid:did:rid of 1ae0:0028:00
10290 04:51:25.043087
10291 04:51:25.045915 tpm_get_response: command 0x17b, return code 0x0
10292 04:51:25.046016
10293 04:51:25.049110 ec_init: CrosEC protocol v3 supported (256, 248)
10294 04:51:25.053860
10295 04:51:25.057227 tpm_cleanup: add release locality here.
10296 04:51:25.057302
10297 04:51:25.057365 Shutting down all USB controllers.
10298 04:51:25.060618
10299 04:51:25.060696 Removing current net device
10300 04:51:25.060759
10301 04:51:25.067412 Exiting depthcharge with code 4 at timestamp: 60654143
10302 04:51:25.067489
10303 04:51:25.070720 LZMA decompressing kernel-1 to 0x821a6718
10304 04:51:25.070796
10305 04:51:25.074074 LZMA decompressing kernel-1 to 0x40000000
10306 04:51:26.572382
10307 04:51:26.572527 jumping to kernel
10308 04:51:26.573038 end: 2.2.4 bootloader-commands (duration 00:00:33) [common]
10309 04:51:26.573138 start: 2.2.5 auto-login-action (timeout 00:03:52) [common]
10310 04:51:26.573219 Setting prompt string to ['Linux version [0-9]']
10311 04:51:26.573290 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10312 04:51:26.573359 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10313 04:51:26.655132
10314 04:51:26.658511 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10315 04:51:26.662167 start: 2.2.5.1 login-action (timeout 00:03:52) [common]
10316 04:51:26.662254 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10317 04:51:26.662325 Setting prompt string to []
10318 04:51:26.662412 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10319 04:51:26.662487 Using line separator: #'\n'#
10320 04:51:26.662585 No login prompt set.
10321 04:51:26.662691 Parsing kernel messages
10322 04:51:26.662777 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10323 04:51:26.662946 [login-action] Waiting for messages, (timeout 00:03:52)
10324 04:51:26.682060 [ 0.000000] Linux version 6.1.75-cip14-rt8 (KernelCI@build-j97480-arm64-gcc-10-defconfig-arm64-chromebook-6n26j) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Feb 4 04:24:19 UTC 2024
10325 04:51:26.685191 [ 0.000000] random: crng init done
10326 04:51:26.691963 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10327 04:51:26.694864 [ 0.000000] efi: UEFI not found.
10328 04:51:26.701474 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10329 04:51:26.711688 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10330 04:51:26.718099 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10331 04:51:26.728167 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10332 04:51:26.734916 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10333 04:51:26.741631 [ 0.000000] printk: bootconsole [mtk8250] enabled
10334 04:51:26.748103 [ 0.000000] NUMA: No NUMA configuration found
10335 04:51:26.754944 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10336 04:51:26.758180 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10337 04:51:26.761445 [ 0.000000] Zone ranges:
10338 04:51:26.767912 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10339 04:51:26.771259 [ 0.000000] DMA32 empty
10340 04:51:26.778155 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10341 04:51:26.781513 [ 0.000000] Movable zone start for each node
10342 04:51:26.784924 [ 0.000000] Early memory node ranges
10343 04:51:26.791774 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10344 04:51:26.798225 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10345 04:51:26.804529 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10346 04:51:26.811197 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10347 04:51:26.814610 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10348 04:51:26.824621 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10349 04:51:26.880012 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10350 04:51:26.886619 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10351 04:51:26.893334 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10352 04:51:26.896502 [ 0.000000] psci: probing for conduit method from DT.
10353 04:51:26.903190 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10354 04:51:26.906382 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10355 04:51:26.913339 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10356 04:51:26.916677 [ 0.000000] psci: SMC Calling Convention v1.2
10357 04:51:26.923621 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10358 04:51:26.927008 [ 0.000000] Detected VIPT I-cache on CPU0
10359 04:51:26.933345 [ 0.000000] CPU features: detected: GIC system register CPU interface
10360 04:51:26.940070 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10361 04:51:26.946169 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10362 04:51:26.953342 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10363 04:51:26.959954 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10364 04:51:26.966527 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10365 04:51:26.972944 [ 0.000000] alternatives: applying boot alternatives
10366 04:51:26.976551 [ 0.000000] Fallback order for Node 0: 0
10367 04:51:26.986148 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10368 04:51:26.986232 [ 0.000000] Policy zone: Normal
10369 04:51:27.002943 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10370 04:51:27.013084 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10371 04:51:27.024251 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10372 04:51:27.034414 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10373 04:51:27.041015 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10374 04:51:27.044256 <6>[ 0.000000] software IO TLB: area num 8.
10375 04:51:27.101623 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10376 04:51:27.250734 <6>[ 0.000000] Memory: 7928756K/8385536K available (18048K kernel code, 4116K rwdata, 19608K rodata, 8448K init, 616K bss, 424012K reserved, 32768K cma-reserved)
10377 04:51:27.257504 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10378 04:51:27.264048 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10379 04:51:27.267750 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10380 04:51:27.274023 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10381 04:51:27.280740 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10382 04:51:27.283949 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10383 04:51:27.293793 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10384 04:51:27.300430 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10385 04:51:27.306948 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10386 04:51:27.313658 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10387 04:51:27.316905 <6>[ 0.000000] GICv3: 608 SPIs implemented
10388 04:51:27.320123 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10389 04:51:27.326881 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10390 04:51:27.330146 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10391 04:51:27.336971 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10392 04:51:27.350055 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10393 04:51:27.363535 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10394 04:51:27.370124 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10395 04:51:27.377428 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10396 04:51:27.391127 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10397 04:51:27.397748 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10398 04:51:27.404229 <6>[ 0.009183] Console: colour dummy device 80x25
10399 04:51:27.413946 <6>[ 0.013909] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10400 04:51:27.420509 <6>[ 0.024351] pid_max: default: 32768 minimum: 301
10401 04:51:27.424163 <6>[ 0.029252] LSM: Security Framework initializing
10402 04:51:27.430566 <6>[ 0.034189] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10403 04:51:27.440243 <6>[ 0.042043] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10404 04:51:27.447112 <6>[ 0.051461] cblist_init_generic: Setting adjustable number of callback queues.
10405 04:51:27.454087 <6>[ 0.058948] cblist_init_generic: Setting shift to 3 and lim to 1.
10406 04:51:27.463748 <6>[ 0.065286] cblist_init_generic: Setting adjustable number of callback queues.
10407 04:51:27.470597 <6>[ 0.072758] cblist_init_generic: Setting shift to 3 and lim to 1.
10408 04:51:27.473924 <6>[ 0.079196] rcu: Hierarchical SRCU implementation.
10409 04:51:27.480182 <6>[ 0.079199] rcu: Max phase no-delay instances is 1000.
10410 04:51:27.487040 <6>[ 0.079223] printk: bootconsole [mtk8250] printing thread started
10411 04:51:27.493852 <6>[ 0.097541] EFI services will not be available.
10412 04:51:27.497180 <6>[ 0.097745] smp: Bringing up secondary CPUs ...
10413 04:51:27.500495 <6>[ 0.098049] Detected VIPT I-cache on CPU1
10414 04:51:27.510457 <6>[ 0.098114] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10415 04:51:27.516677 <6>[ 0.098146] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10416 04:51:27.525607 <6>[ 0.126023] Detected VIPT I-cache on CPU2
10417 04:51:27.535661 <6>[ 0.126071] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10418 04:51:27.542483 <6>[ 0.126087] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10419 04:51:27.545790 <6>[ 0.126341] Detected VIPT I-cache on CPU3
10420 04:51:27.552417 <6>[ 0.126387] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10421 04:51:27.558872 <6>[ 0.126401] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10422 04:51:27.562154 <6>[ 0.126710] CPU features: detected: Spectre-v4
10423 04:51:27.568728 <6>[ 0.126717] CPU features: detected: Spectre-BHB
10424 04:51:27.572093 <6>[ 0.126722] Detected PIPT I-cache on CPU4
10425 04:51:27.578848 <6>[ 0.126779] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10426 04:51:27.585475 <6>[ 0.126795] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10427 04:51:27.592181 <6>[ 0.127088] Detected PIPT I-cache on CPU5
10428 04:51:27.598411 <6>[ 0.127147] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10429 04:51:27.605132 <6>[ 0.127163] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10430 04:51:27.608467 <6>[ 0.127436] Detected PIPT I-cache on CPU6
10431 04:51:27.615080 <6>[ 0.127501] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10432 04:51:27.621862 <6>[ 0.127517] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10433 04:51:27.630403 <6>[ 0.127805] Detected PIPT I-cache on CPU7
10434 04:51:27.636931 <6>[ 0.127869] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10435 04:51:27.643717 <6>[ 0.127885] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10436 04:51:27.647108 <6>[ 0.127930] smp: Brought up 1 node, 8 CPUs
10437 04:51:27.653904 <6>[ 0.127935] SMP: Total of 8 processors activated.
10438 04:51:27.657000 <6>[ 0.127938] CPU features: detected: 32-bit EL0 Support
10439 04:51:27.666871 <6>[ 0.127940] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10440 04:51:27.673445 <6>[ 0.127942] CPU features: detected: Common not Private translations
10441 04:51:27.680193 <6>[ 0.127944] CPU features: detected: CRC32 instructions
10442 04:51:27.683475 <6>[ 0.127946] CPU features: detected: RCpc load-acquire (LDAPR)
10443 04:51:27.690194 <6>[ 0.127948] CPU features: detected: LSE atomic instructions
10444 04:51:27.696588 <6>[ 0.127949] CPU features: detected: Privileged Access Never
10445 04:51:27.703237 <6>[ 0.127951] CPU features: detected: RAS Extension Support
10446 04:51:27.709729 <6>[ 0.127954] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10447 04:51:27.713081 <6>[ 0.128021] CPU: All CPU(s) started at EL2
10448 04:51:27.719836 <6>[ 0.128023] alternatives: applying system-wide alternatives
10449 04:51:27.723185 <6>[ 0.141097] devtmpfs: initialized
10450 04:51:27.733179 <6>[ 0.147341] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10451 04:51:27.739646 <6>[ 0.147356] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10452 04:51:27.771538 ������������Bzɑ����b���ª���ѕͱb����ɥjR�<6>[ 0.3<74650] printk: console [ttyS0] printing thread started
10453 04:51:27.774983 6<6>[ 0.374680] printk: console [ttyS0] enabled
10454 04:51:27.784818 >[ 0.247594] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10455 04:51:27.791414 <6>[ 0.374683] printk: bootconsole [mtk8250] disabled
10456 04:51:27.798258 <6>[ 0.393726] printk: bootconsole [mtk8250] printing thread stopped
10457 04:51:27.801628 <6>[ 0.394703] SuperH (H)SCI(F) driver initialized
10458 04:51:27.805087 <6>[ 0.395170] msm_serial: driver initialized
10459 04:51:27.814436 <6>[ 0.399745] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10460 04:51:27.821282 <6>[ 0.399781] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10461 04:51:27.839614 <6>[ 0.399812] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10462 04:51:27.839949 <6>[ 0.399841] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10463 04:51:27.853515 <6>[ 0.399862] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10464 04:51:27.874860 <6>[ 0.399890] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10465 04:51:27.875203 <6>[ 0.399917] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10466 04:51:27.880797 <6>[ 0.400018] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10467 04:51:27.885468 <6>[ 0.400048] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10468 04:51:27.889518 <6>[ 0.410618] loop: module loaded
10469 04:51:27.896667 <6>[ 0.413182] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10470 04:51:27.900634 <4>[ 0.429790] mtk-pmic-keys: Failed to locate of_node [id: -1]
10471 04:51:27.904091 <6>[ 0.430597] megasas: 07.719.03.00-rc1
10472 04:51:27.910231 <6>[ 0.442930] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10473 04:51:27.913679 <6>[ 0.443104] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10474 04:51:27.920802 <6>[ 0.454787] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10475 04:51:27.930338 <6>[ 0.509255] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10476 04:51:29.230079 <6>[ 1.832341] Freeing initrd memory: 38432K
10477 04:51:29.236574 <6>[ 1.838454] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10478 04:51:29.239832 <6>[ 1.843304] tun: Universal TUN/TAP device driver, 1.6
10479 04:51:29.243273 <6>[ 1.844097] thunder_xcv, ver 1.0
10480 04:51:29.246574 <6>[ 1.844121] thunder_bgx, ver 1.0
10481 04:51:29.249776 <6>[ 1.844135] nicpf, ver 1.0
10482 04:51:29.259780 <6>[ 1.845209] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10483 04:51:29.262979 <6>[ 1.845212] hns3: Copyright (c) 2017 Huawei Corporation.
10484 04:51:29.266230 <6>[ 1.845240] hclge is initializing
10485 04:51:29.273075 <6>[ 1.845254] e1000: Intel(R) PRO/1000 Network Driver
10486 04:51:29.280648 <6>[ 1.845255] e1000: Copyright (c) 1999-2006 Intel Corporation.
10487 04:51:29.283893 <6>[ 1.845272] e1000e: Intel(R) PRO/1000 Network Driver
10488 04:51:29.291275 <6>[ 1.845273] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10489 04:51:29.294707 <6>[ 1.845288] igb: Intel(R) Gigabit Ethernet Network Driver
10490 04:51:29.300894 <6>[ 1.845290] igb: Copyright (c) 2007-2014 Intel Corporation.
10491 04:51:29.307988 <6>[ 1.845304] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10492 04:51:29.315386 <6>[ 1.845306] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10493 04:51:29.318699 <6>[ 1.845620] sky2: driver version 1.30
10494 04:51:29.322057 <6>[ 1.846706] VFIO - User Level meta-driver version: 0.3
10495 04:51:29.328691 <6>[ 1.849500] usbcore: registered new interface driver usb-storage
10496 04:51:29.334774 <6>[ 1.849689] usbcore: registered new device driver onboard-usb-hub
10497 04:51:29.341385 <6>[ 1.852517] mt6397-rtc mt6359-rtc: registered as rtc0
10498 04:51:29.351623 <6>[ 1.852674] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-04T04:48:46 UTC (1707022126)
10499 04:51:29.354808 <6>[ 1.853296] i2c_dev: i2c /dev entries driver
10500 04:51:29.361413 <6>[ 1.860465] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10501 04:51:29.368332 <6>[ 1.875464] cpu cpu0: EM: created perf domain
10502 04:51:29.371730 <6>[ 1.875816] cpu cpu4: EM: created perf domain
10503 04:51:29.378435 <6>[ 1.877993] sdhci: Secure Digital Host Controller Interface driver
10504 04:51:29.381607 <6>[ 1.877994] sdhci: Copyright(c) Pierre Ossman
10505 04:51:29.388353 <6>[ 1.878351] Synopsys Designware Multimedia Card Interface Driver
10506 04:51:29.395007 <6>[ 1.878736] sdhci-pltfm: SDHCI platform and OF driver helper
10507 04:51:29.401722 <6>[ 1.882993] ledtrig-cpu: registered to indicate activity on CPUs
10508 04:51:29.405147 <6>[ 1.883722] mmc0: CQHCI version 5.10
10509 04:51:29.411366 <6>[ 1.883823] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10510 04:51:29.418016 <6>[ 1.884125] usbcore: registered new interface driver usbhid
10511 04:51:29.421053 <6>[ 1.884127] usbhid: USB HID core driver
10512 04:51:29.428017 <6>[ 1.884246] spi_master spi0: will run message pump with realtime priority
10513 04:51:29.441602 <6>[ 1.913527] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10514 04:51:29.454747 <6>[ 1.916468] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10515 04:51:29.461495 <6>[ 1.917649] cros-ec-spi spi0.0: Chrome EC device registered
10516 04:51:29.470957 <6>[ 1.929875] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10517 04:51:29.474356 <6>[ 1.930830] NET: Registered PF_PACKET protocol family
10518 04:51:29.481023 <6>[ 1.930902] 9pnet: Installing 9P2000 support
10519 04:51:29.484100 <5>[ 1.930934] Key type dns_resolver registered
10520 04:51:29.487977 <6>[ 1.931256] registered taskstats version 1
10521 04:51:29.494077 <5>[ 1.931271] Loading compiled-in X.509 certificates
10522 04:51:29.504402 <4>[ 1.947783] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10523 04:51:29.513774 <4>[ 1.947974] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10524 04:51:29.521038 <3>[ 1.947985] debugfs: File 'uA_load' in directory '/' already present!
10525 04:51:29.527285 <3>[ 1.947993] debugfs: File 'min_uV' in directory '/' already present!
10526 04:51:29.534088 <3>[ 1.947997] debugfs: File 'max_uV' in directory '/' already present!
10527 04:51:29.540789 <3>[ 1.948000] debugfs: File 'constraint_flags' in directory '/' already present!
10528 04:51:29.550974 <3>[ 1.950402] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10529 04:51:29.557579 <6>[ 1.959045] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10530 04:51:29.564024 <6>[ 1.959677] xhci-mtk 11200000.usb: xHCI Host Controller
10531 04:51:29.570643 <6>[ 1.959697] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10532 04:51:29.580883 <6>[ 1.959920] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10533 04:51:29.583593 <6>[ 1.959974] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10534 04:51:29.590952 <6>[ 1.960065] xhci-mtk 11200000.usb: xHCI Host Controller
10535 04:51:29.597004 <6>[ 1.960072] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10536 04:51:29.607449 <6>[ 1.960080] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10537 04:51:29.610925 <6>[ 1.960547] hub 1-0:1.0: USB hub found
10538 04:51:29.613694 <6>[ 1.960564] hub 1-0:1.0: 1 port detected
10539 04:51:29.623548 <6>[ 1.960774] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10540 04:51:29.627235 <6>[ 1.961063] hub 2-0:1.0: USB hub found
10541 04:51:29.630424 <6>[ 1.961105] hub 2-0:1.0: 1 port detected
10542 04:51:29.633553 <6>[ 1.964262] mtk-msdc 11f70000.mmc: Got CD GPIO
10543 04:51:29.640357 <6>[ 1.977878] mmc0: Command Queue Engine enabled
10544 04:51:29.646953 <6>[ 1.977891] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10545 04:51:29.650073 <6>[ 1.978529] mmcblk0: mmc0:0001 DA4128 116 GiB
10546 04:51:29.660146 <6>[ 1.980448] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10547 04:51:29.667122 <6>[ 1.980454] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10548 04:51:29.676466 <4>[ 1.980661] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10549 04:51:29.683299 <6>[ 1.981401] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10550 04:51:29.693364 <6>[ 1.981405] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10551 04:51:29.696793 <6>[ 1.981513] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10552 04:51:29.706153 <6>[ 1.981621] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10553 04:51:29.712673 <6>[ 1.981638] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10554 04:51:29.722604 <6>[ 1.981642] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10555 04:51:29.729521 <6>[ 1.981649] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10556 04:51:29.736166 <6>[ 1.982587] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10557 04:51:29.739536 <6>[ 1.983158] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10558 04:51:29.746279 <6>[ 1.983752] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10559 04:51:29.756178 <6>[ 1.985926] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10560 04:51:29.762829 <6>[ 1.985945] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10561 04:51:29.772565 <6>[ 1.985952] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10562 04:51:29.779325 <6>[ 1.985959] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10563 04:51:29.789121 <6>[ 1.985965] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10564 04:51:29.798879 <6>[ 1.985972] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10565 04:51:29.805742 <6>[ 1.985978] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10566 04:51:29.815770 <6>[ 1.985985] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10567 04:51:29.822295 <6>[ 1.985992] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10568 04:51:29.832381 <6>[ 1.985998] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10569 04:51:29.839118 <6>[ 1.986005] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10570 04:51:29.848528 <6>[ 1.986011] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10571 04:51:29.855234 <6>[ 1.986018] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10572 04:51:29.865616 <6>[ 1.986024] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10573 04:51:29.871804 <6>[ 1.986031] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10574 04:51:29.878579 <6>[ 1.986672] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10575 04:51:29.885457 <6>[ 1.987603] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10576 04:51:29.891516 <6>[ 1.988174] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10577 04:51:29.898220 <6>[ 1.988789] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10578 04:51:29.905329 <6>[ 1.989429] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10579 04:51:29.914836 <6>[ 1.989620] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10580 04:51:29.924885 <6>[ 1.989635] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10581 04:51:29.931449 <6>[ 1.989640] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10582 04:51:29.941594 <6>[ 1.989646] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10583 04:51:29.951557 <6>[ 1.989652] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10584 04:51:29.961687 <6>[ 1.989657] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10585 04:51:29.971217 <6>[ 1.989663] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10586 04:51:29.978364 <6>[ 1.989668] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10587 04:51:29.987856 <6>[ 1.989673] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10588 04:51:29.998095 <6>[ 1.989680] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10589 04:51:30.008161 <6>[ 1.989684] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10590 04:51:30.017720 <6>[ 1.990285] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10591 04:51:30.024365 <6>[ 2.343797] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10592 04:51:30.027800 <6>[ 2.370805] hub 2-1:1.0: USB hub found
10593 04:51:30.030997 <6>[ 2.371211] hub 2-1:1.0: 3 ports detected
10594 04:51:30.037738 <6>[ 2.373943] hub 2-1:1.0: USB hub found
10595 04:51:30.041158 <6>[ 2.374255] hub 2-1:1.0: 3 ports detected
10596 04:51:30.047385 <6>[ 2.491623] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10597 04:51:30.051104 <6>[ 2.644519] hub 1-1:1.0: USB hub found
10598 04:51:30.054067 <6>[ 2.644917] hub 1-1:1.0: 4 ports detected
10599 04:51:30.060821 <6>[ 2.648776] hub 1-1:1.0: USB hub found
10600 04:51:30.063876 <6>[ 2.649100] hub 1-1:1.0: 4 ports detected
10601 04:51:30.125233 <6>[ 2.723853] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10602 04:51:30.361614 <6>[ 2.959800] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10603 04:51:30.481883 <6>[ 3.087289] hub 1-1.4:1.0: USB hub found
10604 04:51:30.485463 <6>[ 3.087722] hub 1-1.4:1.0: 2 ports detected
10605 04:51:30.488772 <6>[ 3.091052] hub 1-1.4:1.0: USB hub found
10606 04:51:30.495506 <6>[ 3.091383] hub 1-1.4:1.0: 2 ports detected
10607 04:51:30.781341 <6>[ 3.379787] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10608 04:51:30.965459 <6>[ 3.563760] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10609 04:51:41.665447 <6>[ 14.272789] ALSA device list:
10610 04:51:41.672591 <6>[ 14.272811] No soundcards found.
10611 04:51:41.675804 <6>[ 14.277208] Freeing unused kernel memory: 8448K
10612 04:51:41.679057 <6>[ 14.277354] Run /init as init process
10613 04:51:41.712772 <6>[ 14.318647] NET: Registered PF_INET6 protocol family
10614 04:51:41.716526 <6>[ 14.319738] Segment Routing with IPv6
10615 04:51:41.722940 <6>[ 14.319760] In-situ OAM (IOAM) with IPv6
10616 04:51:41.728744
10617 04:51:41.752319 Welcome to [1mD<30>[ 14.338325] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10618 04:51:41.758443 <30>[ 14.338788] systemd[1]: Detected architecture arm64.
10619 04:51:41.761802 ebian GNU/Linux 11 (bullseye)[0m!
10620 04:51:41.761886
10621 04:51:41.780936 <30>[ 14.383715] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10622 04:51:41.892540 <30>[ 14.495369] systemd[1]: Queued start job for default target Graphical Interface.
10623 04:51:41.925383 [[0;32m OK [0m] Created slic<30>[ 14.528689] systemd[1]: Created slice system-getty.slice.
10624 04:51:41.929118 e [0;1;39msystem-getty.slice[0m.
10625 04:51:41.954009 [[0;32m OK [0m] Created slic<30>[ 14.557237] systemd[1]: Created slice system-modprobe.slice.
10626 04:51:41.957121 e [0;1;39msystem-modprobe.slice[0m.
10627 04:51:41.977835 [[0;32m OK [0m] Created slic<30>[ 14.580894] systemd[1]: Created slice system-serial\x2dgetty.slice.
10628 04:51:41.983973 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10629 04:51:42.002100 [[0;32m OK [0m] Created slic<30>[ 14.605604] systemd[1]: Created slice User and Session Slice.
10630 04:51:42.005410 e [0;1;39mUser and Session Slice[0m.
10631 04:51:42.028629 [[0;32m OK [0m] Started [0;<30>[ 14.628637] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10632 04:51:42.032273 1;39mDispatch Password …ts to Console Directory Watch[0m.
10633 04:51:42.056098 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 14.655961] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10634 04:51:42.059358 sword R…uests to Wall Directory Watch[0m.
10635 04:51:42.083807 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 14.679865] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10636 04:51:42.089829 <30>[ 14.680057] systemd[1]: Reached target Local Encrypted Volumes.
10637 04:51:42.093058 l Encrypted Volumes[0m.
10638 04:51:42.112594 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 14.715884] systemd[1]: Reached target Paths.
10639 04:51:42.112677 s[0m.
10640 04:51:42.135544 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 14.735771] systemd[1]: Reached target Remote File Systems.
10641 04:51:42.135629 te File Systems[0m.
10642 04:51:42.157129 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 14.760185] systemd[1]: Reached target Slices.
10643 04:51:42.157212 es[0m.
10644 04:51:42.176578 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 14.779807] systemd[1]: Reached target Swap.
10645 04:51:42.176663 [0m.
10646 04:51:42.200476 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 14.800295] systemd[1]: Listening on initctl Compatibility Named Pipe.
10647 04:51:42.203735 l Compatibility Named Pipe[0m.
10648 04:51:42.210522 <30>[ 14.815456] systemd[1]: Listening on Journal Audit Socket.
10649 04:51:42.216624 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10650 04:51:42.236161 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 14.836258] systemd[1]: Listening on Journal Socket (/dev/log).
10651 04:51:42.236270 l Socket (/dev/log)[0m.
10652 04:51:42.257602 [[0;32m OK [0m] Listening on<30>[ 14.861002] systemd[1]: Listening on Journal Socket.
10653 04:51:42.260976 [0;1;39mJournal Socket[0m.
10654 04:51:42.280789 [[0;32m OK [0m] Listening on [0;1;39mNetwor<30>[ 14.880477] systemd[1]: Listening on Network Service Netlink Socket.
10655 04:51:42.283439 k Service Netlink Socket[0m.
10656 04:51:42.300998 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 14.904320] systemd[1]: Listening on udev Control Socket.
10657 04:51:42.304556 ontrol Socket[0m.
10658 04:51:42.325327 [[0;32m OK [0m] Listening on<30>[ 14.928866] systemd[1]: Listening on udev Kernel Socket.
10659 04:51:42.328675 [0;1;39mudev Kernel Socket[0m.
10660 04:51:42.384256 Mounting [0;1;39mHuge Pages File Syste<30>[ 14.984306] systemd[1]: Mounting Huge Pages File System...
10661 04:51:42.384392 m[0m...
10662 04:51:42.407982 Mounting [0;1;39mPOSIX Message Queue F<30>[ 15.008057] systemd[1]: Mounting POSIX Message Queue File System...
10663 04:51:42.408098 ile System[0m...
10664 04:51:42.436289 Mounting [0;1;39mKernel Debug File Sys<30>[ 15.036113] systemd[1]: Mounting Kernel Debug File System...
10665 04:51:42.436377 tem[0m...
10666 04:51:42.456426 <30>[ 15.056326] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10667 04:51:42.466118 <30>[ 15.060909] systemd[1]: Starting Create list of static device nodes for the current kernel...
10668 04:51:42.472775 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10669 04:51:42.520409 Starting [0;1;39mLoad Kernel Module co<30>[ 15.120495] systemd[1]: Starting Load Kernel Module configfs...
10670 04:51:42.520502 nfigfs[0m...
10671 04:51:42.544270 Starting [0;1;39mLoad Kernel Module dr<30>[ 15.144396] systemd[1]: Starting Load Kernel Module drm...
10672 04:51:42.544362 m[0m...
10673 04:51:42.564494 <30>[ 15.164223] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10674 04:51:42.577965 Starting [0;1;39mJourn<30>[ 15.181103] systemd[1]: Starting Journal Service...
10675 04:51:42.578073 al Service[0m...
10676 04:51:42.598524 Starting [0;1;39mLoad <30>[ 15.201769] systemd[1]: Starting Load Kernel Modules...
10677 04:51:42.601941 Kernel Modules[0m...
10678 04:51:42.622507 Starting [0;1;39mRemou<30>[ 15.225601] systemd[1]: Starting Remount Root and Kernel File Systems...
10679 04:51:42.625432 nt Root and Kernel File Systems[0m...
10680 04:51:42.647272 Startin<30>[ 15.250613] systemd[1]: Starting Coldplug All udev Devices...
10681 04:51:42.650661 g [0;1;39mColdplug All udev Devices[0m...
10682 04:51:42.668258 [[0;32m OK [<30>[ 15.275198] systemd[1]: Started Journal Service.
10683 04:51:42.675149 0m] Started [0;1;39mJournal Service[0m.
10684 04:51:42.692603 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10685 04:51:42.710545 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10686 04:51:42.726115 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10687 04:51:42.746223 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10688 04:51:42.767013 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10689 04:51:42.786156 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10690 04:51:42.802168 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10691 04:51:42.826154 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10692 04:51:42.844825 See 'systemctl status systemd-remount-fs.service' for details.
10693 04:51:42.897085 Mounting [0;1;39mKernel Configuration File System[0m...
10694 04:51:42.922125 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10695 04:51:42.936080 <46>[ 15.538866] systemd-journald[186]: Received client request to flush runtime journal.
10696 04:51:42.946550 Starting [0;1;39mLoad/Save Random Seed[0m...
10697 04:51:42.965988 Starting [0;1;39mApply Kernel Variables[0m...
10698 04:51:42.987391 Starting [0;1;39mCreate System Users[0m...
10699 04:51:43.006918 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10700 04:51:43.026251 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10701 04:51:43.049982 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10702 04:51:43.066442 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10703 04:51:43.087277 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10704 04:51:43.105510 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10705 04:51:43.170473 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10706 04:51:43.190428 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10707 04:51:43.205864 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10708 04:51:43.224940 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10709 04:51:43.286060 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10710 04:51:43.312729 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10711 04:51:43.336004 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10712 04:51:43.355127 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10713 04:51:43.438540 Starting [0;1;39mNetwork Service[0m...
10714 04:51:43.460176 Starting [0;1;39mNetwork Time Synchronization[0m...
10715 04:51:43.480141 <6>[ 16.080926] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10716 04:51:43.482995 <6>[ 16.088193] remoteproc remoteproc0: scp is available
10717 04:51:43.489817 Startin<6>[ 16.088268] remoteproc remoteproc0: powering up scp
10718 04:51:43.499556 g [0;1;39mUpdat<6>[ 16.088274] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10719 04:51:43.509512 e UTMP about Sys<6>[ 16.088300] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10720 04:51:43.509595 tem Boot/Shutdown[0m...
10721 04:51:43.527728 <6>[ 16.130210] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10722 04:51:43.534665 <6>[ 16.130280] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10723 04:51:43.544209 <6>[ 16.130294] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10724 04:51:43.554354 <3>[ 16.140236] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10725 04:51:43.561058 <3>[ 16.140269] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10726 04:51:43.571149 [[0;32m OK [0m] Finished [0<3>[ 16.140276] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 04:51:43.581088 ;1;39mUpdate UTM<3>[ 16.148903] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10728 04:51:43.590491 P about System B<3>[ 16.148922] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10729 04:51:43.600757 <3>[ 16.148925] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10730 04:51:43.607374 <3>[ 16.148930] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10731 04:51:43.617489 <3>[ 16.148934] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10732 04:51:43.624095 oot/Shutdown[0m<3>[ 16.148969] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10733 04:51:43.633477 <3>[ 16.149009] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 04:51:43.633586 .
10735 04:51:43.640371 <3>[ 16.149011] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 04:51:43.650406 <3>[ 16.149014] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10737 04:51:43.656628 <3>[ 16.149031] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10738 04:51:43.667006 <3>[ 16.149034] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10739 04:51:43.677535 [[0;32m OK [0m] Started [0;<3>[ 16.149037] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 04:51:43.687216 1;39mNetwork Ser<3>[ 16.149039] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10741 04:51:43.694115 <3>[ 16.149041] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10742 04:51:43.700853 <3>[ 16.149053] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10743 04:51:43.707570 <6>[ 16.196794] usbcore: registered new device driver r8152-cfgselector
10744 04:51:43.710955 vice[0m.
10745 04:51:43.718285 <6>[ 16.213932] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10746 04:51:43.725252 <6>[ 16.219565] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10747 04:51:43.731388 <6>[ 16.219583] remoteproc remoteproc0: remote processor scp is now up
10748 04:51:43.734736 <6>[ 16.221474] mc: Linux media interface: v0.10
10749 04:51:43.742066 <6>[ 16.245313] videodev: Linux video capture interface: v2.00
10750 04:51:43.748899 <6>[ 16.253322] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10751 04:51:43.758909 [[0;32m OK [<6>[ 16.254277] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10752 04:51:43.765549 0m] Started [0;<6>[ 16.254296] pci_bus 0000:00: root bus resource [bus 00-ff]
10753 04:51:43.772733 1;39mNetwork Tim<6>[ 16.254305] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10754 04:51:43.783022 <6>[ 16.254310] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10755 04:51:43.792566 e Synchronizatio<6>[ 16.254372] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10756 04:51:43.799534 <6>[ 16.254398] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10757 04:51:43.802812 <6>[ 16.254506] pci 0000:00:00.0: supports D1 D2
10758 04:51:43.809578 <6>[ 16.254509] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10759 04:51:43.818995 <6>[ 16.256328] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10760 04:51:43.829227 <4>[ 16.273645] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10761 04:51:43.832581 <4>[ 16.273645] Fallback method does not support PEC.
10762 04:51:43.832687 n[0m.
10763 04:51:43.838842 <6>[ 16.277063] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10764 04:51:43.845549 <6>[ 16.277130] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10765 04:51:43.856273 <6>[ 16.277154] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10766 04:51:43.863485 [[0;32m OK [<6>[ 16.277173] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10767 04:51:43.870737 0m] Found device<6>[ 16.277333] pci 0000:01:00.0: supports D1 D2
10768 04:51:43.878117 [0;1;39m/dev/t<6>[ 16.277338] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10769 04:51:43.878226 tyS0[0m.
10770 04:51:43.887982 <6>[ 16.281883] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10771 04:51:43.894533 <4>[ 16.290291] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10772 04:51:43.904549 <3>[ 16.290561] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10773 04:51:43.911403 <4>[ 16.294562] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10774 04:51:43.917876 <4>[ 16.312658] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10775 04:51:43.927942 <4>[ 16.312682] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10776 04:51:43.935048 <3>[ 16.314194] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10777 04:51:43.942531 <6>[ 16.315604] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10778 04:51:43.952566 <6>[ 16.315684] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10779 04:51:43.958768 <6>[ 16.315690] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10780 04:51:43.965451 <6>[ 16.315701] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10781 04:51:43.975377 <6>[ 16.315714] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10782 04:51:43.982064 <6>[ 16.315727] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10783 04:51:43.989428 <6>[ 16.315742] pci 0000:00:00.0: PCI bridge to [bus 01]
10784 04:51:43.996931 <6>[ 16.315748] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10785 04:51:44.003992 [[0;32m OK [<6>[ 16.318790] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10786 04:51:44.010375 0m] Created slic<6>[ 16.320043] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10787 04:51:44.020625 e [0;1;39msyste<6>[ 16.320311] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10788 04:51:44.030105 m-systemd\x2dbac<3>[ 16.334301] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10789 04:51:44.037519 klight.slice[0m<3>[ 16.356814] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10790 04:51:44.040997 .
10791 04:51:44.043997 <6>[ 16.381456] r8152 2-1.3:1.0 eth0: v1.12.13
10792 04:51:44.050762 <6>[ 16.383029] usbcore: registered new interface driver r8152
10793 04:51:44.058083 <6>[ 16.385822] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10794 04:51:44.068164 <6>[ 16.386148] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10795 04:51:44.078684 <3>[ 16.386301] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10796 04:51:44.085548 <6>[ 16.397658] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10797 04:51:44.095619 [[0;32m OK [<6>[ 16.399373] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10798 04:51:44.106572 0m] Reached targ<6>[ 16.400442] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10799 04:51:44.113024 et [0;1;39mBlue<6>[ 16.424219] usbcore: registered new interface driver cdc_ether
10800 04:51:44.123029 <5>[ 16.425378] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10801 04:51:44.126401 <6>[ 16.432045] Bluetooth: Core ver 2.22
10802 04:51:44.129447 <6>[ 16.432164] NET: Registered PF_BLUETOOTH protocol family
10803 04:51:44.136520 <6>[ 16.432167] Bluetooth: HCI device and connection manager initialized
10804 04:51:44.143059 <6>[ 16.432193] Bluetooth: HCI socket layer initialized
10805 04:51:44.149147 <6>[ 16.432203] Bluetooth: L2CAP socket layer initialized
10806 04:51:44.152577 <6>[ 16.432218] Bluetooth: SCO socket layer initialized
10807 04:51:44.159142 <5>[ 16.438085] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10808 04:51:44.169033 <5>[ 16.438324] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10809 04:51:44.175742 <4>[ 16.438376] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10810 04:51:44.182506 <6>[ 16.438383] cfg80211: failed to load regulatory.db
10811 04:51:44.189048 <6>[ 16.444837] usbcore: registered new interface driver r8153_ecm
10812 04:51:44.195795 <6>[ 16.453917] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10813 04:51:44.208869 <6>[ 16.455999] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10814 04:51:44.212306 <6>[ 16.456252] usbcore: registered new interface driver uvcvideo
10815 04:51:44.222323 <3>[ 16.483689] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10816 04:51:44.228528 <6>[ 16.484733] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10817 04:51:44.239065 <3>[ 16.496925] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10818 04:51:44.242147 <6>[ 16.500652] usbcore: registered new interface driver btusb
10819 04:51:44.248734 <6>[ 16.500769] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10820 04:51:44.259021 <4>[ 16.501533] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10821 04:51:44.265245 <3>[ 16.501552] Bluetooth: hci0: Failed to load firmware file (-2)
10822 04:51:44.271964 <3>[ 16.501557] Bluetooth: hci0: Failed to set up firmware (-2)
10823 04:51:44.282041 <4>[ 16.501567] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10824 04:51:44.292041 <3>[ 16.557216] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10825 04:51:44.298350 <3>[ 16.558199] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10826 04:51:44.308213 <6>[ 16.558463] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10827 04:51:44.311720 <6>[ 16.558577] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10828 04:51:44.318363 <6>[ 16.575619] mt7921e 0000:01:00.0: ASIC revision: 79610010
10829 04:51:44.328476 <3>[ 16.619331] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10830 04:51:44.334961 <6>[ 16.666331] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10831 04:51:44.338334 <6>[ 16.666331]
10832 04:51:44.345057 <6>[ 16.925634] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10833 04:51:44.348403 tooth[0m.
10834 04:51:44.361050 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10835 04:51:44.377188 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10836 04:51:44.396485 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10837 04:51:44.433086 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10838 04:51:44.457267 Starting [0;1;39mNetwork Name Resolution[0m...
10839 04:51:44.479281 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10840 04:51:44.509754 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10841 04:51:44.524997 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10842 04:51:44.544124 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10843 04:51:44.557065 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10844 04:51:44.576629 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10845 04:51:44.592353 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10846 04:51:44.604485 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10847 04:51:44.624644 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10848 04:51:44.636568 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10849 04:51:44.652858 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10850 04:51:44.689828 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10851 04:51:44.728023 Starting [0;1;39mUser Login Management[0m...
10852 04:51:44.749525 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10853 04:51:44.771223 Starting [0;1;39mPermit User Sessions[0m...
10854 04:51:44.781319 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10855 04:51:44.799121 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10856 04:51:44.850189 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10857 04:51:44.897113 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10858 04:51:44.913428 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10859 04:51:44.933028 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10860 04:51:44.940539 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10861 04:51:44.957149 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10862 04:51:45.014251 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10863 04:51:45.048168 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10864 04:51:45.101135
10865 04:51:45.101236
10866 04:51:45.103804 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10867 04:51:45.103912
10868 04:51:45.107037 debian-bullseye-arm64 login: root (automatic login)
10869 04:51:45.107121
10870 04:51:45.107206
10871 04:51:45.123126 Linux debian-bullseye-arm64 6.1.75-cip14-rt8 #1 SMP PREEMPT Sun Feb 4 04:24:19 UTC 2024 aarch64
10872 04:51:45.123211
10873 04:51:45.130234 The programs included with the Debian GNU/Linux system are free software;
10874 04:51:45.136761 the exact distribution terms for each program are described in the
10875 04:51:45.140046 individual files in /usr/share/doc/*/copyright.
10876 04:51:45.140131
10877 04:51:45.146835 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10878 04:51:45.150243 permitted by applicable law.
10879 04:51:45.150610 Matched prompt #10: / #
10881 04:51:45.150834 Setting prompt string to ['/ #']
10882 04:51:45.150942 end: 2.2.5.1 login-action (duration 00:00:18) [common]
10884 04:51:45.151162 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
10885 04:51:45.151294 start: 2.2.6 expect-shell-connection (timeout 00:03:34) [common]
10886 04:51:45.151394 Setting prompt string to ['/ #']
10887 04:51:45.151489 Forcing a shell prompt, looking for ['/ #']
10889 04:51:45.201776 / #
10890 04:51:45.201888 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10891 04:51:45.201978 Waiting using forced prompt support (timeout 00:02:30)
10892 04:51:45.202096 <6>[ 17.769894] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10893 04:51:45.206323
10894 04:51:45.206594 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10895 04:51:45.206697 start: 2.2.7 export-device-env (timeout 00:03:34) [common]
10896 04:51:45.206804 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10897 04:51:45.206900 end: 2.2 depthcharge-retry (duration 00:01:26) [common]
10898 04:51:45.206997 end: 2 depthcharge-action (duration 00:01:26) [common]
10899 04:51:45.207100 start: 3 lava-test-retry (timeout 00:08:13) [common]
10900 04:51:45.207203 start: 3.1 lava-test-shell (timeout 00:08:13) [common]
10901 04:51:45.207285 Using namespace: common
10903 04:51:45.307679 / # #
10904 04:51:45.307828 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10905 04:51:45.313289 #
10906 04:51:45.313557 Using /lava-12699854
10908 04:51:45.413931 / # export SHELL=/bin/sh
10909 04:51:45.414157 <6>[ 17.950197] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c787aaa: link becomes ready
10910 04:51:45.414238 <6>[ 17.950703] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10911 04:51:45.419398 export SHELL=/bin/sh
10913 04:51:45.519951 / # . /lava-12699854/environment
10914 04:51:45.525490 . /lava-12699854/environment
10916 04:51:45.626036 / # /lava-12699854/bin/lava-test-runner /lava-12699854/0
10917 04:51:45.626205 Test shell timeout: 10s (minimum of the action and connection timeout)
10918 04:51:45.631103 /lava-12699854/bin/lava-test-runner /lava-12699854/0
10919 04:51:45.655562 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
10920 04:51:45.661660 + cd /lava-12699854/0/tests/0_v4l2-compliance-mtk-vcodec-enc
10921 04:51:45.661758 + cat uuid
10922 04:51:45.665595 + UUID=12699854_1.5.2.3.1
10923 04:51:45.665711 + set +x
10924 04:51:45.671703 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 12699854_1.5.2.3.1>
10925 04:51:45.672012 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 12699854_1.5.2.3.1
10926 04:51:45.672092 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (12699854_1.5.2.3.1)
10927 04:51:45.672221 Skipping test definition patterns.
10928 04:51:45.675088 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
10929 04:51:45.681732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
10930 04:51:45.681861 device: /dev/video2
10931 04:51:45.682153 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
10933 04:51:45.692228 <4>[ 18.294144] use of bytesused == 0 is deprecated and will be removed in the future,
10934 04:51:45.695632 <4>[ 18.294154] use the actual size instead.
10935 04:51:45.698253 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
10936 04:51:45.710115 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
10937 04:51:45.716562
10938 04:51:45.729565 Compliance test for mtk-vcodec-enc device /dev/video2:
10939 04:51:45.737080
10940 04:51:45.747538 Driver Info:
10941 04:51:45.758076 Driver name : mtk-vcodec-enc
10942 04:51:45.771500 Card type : MT8192 video encoder
10943 04:51:45.781803 Bus info : platform:17020000.vcodec
10944 04:51:45.787844 Driver version : 6.1.75
10945 04:51:45.800715 Capabilities : 0x84204000
10946 04:51:45.812233 Video Memory-to-Memory Multiplanar
10947 04:51:45.826170 Streaming
10948 04:51:45.838578 Extended Pix Format
10949 04:51:45.849811 Device Capabilities
10950 04:51:45.865056 Device Caps : 0x04204000
10951 04:51:45.877425 Video Memory-to-Memory Multiplanar
10952 04:51:45.892336 Streaming
10953 04:51:45.902846 Extended Pix Format
10954 04:51:45.914295 Detected Stateful Encoder
10955 04:51:45.929562
10956 04:51:45.940886 Required ioctls:
10957 04:51:45.959396 <LAVA_SIGNAL_TESTSET START Required-ioctls>
10958 04:51:45.959505 test VIDIOC_QUERYCAP: OK
10959 04:51:45.959770 Received signal: <TESTSET> START Required-ioctls
10960 04:51:45.959848 Starting test_set Required-ioctls
10961 04:51:45.986498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
10962 04:51:45.986789 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
10964 04:51:45.989403 test invalid ioctls: OK
10965 04:51:46.013066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
10966 04:51:46.013187
10967 04:51:46.013425 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
10969 04:51:46.022767 Allow for multiple opens:
10970 04:51:46.029488 <LAVA_SIGNAL_TESTSET STOP>
10971 04:51:46.029742 Received signal: <TESTSET> STOP
10972 04:51:46.029815 Closing test_set Required-ioctls
10973 04:51:46.039137 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
10974 04:51:46.039394 Received signal: <TESTSET> START Allow-for-multiple-opens
10975 04:51:46.039466 Starting test_set Allow-for-multiple-opens
10976 04:51:46.042462 test second /dev/video2 open: OK
10977 04:51:46.065034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
10978 04:51:46.065342 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
10980 04:51:46.068124 test VIDIOC_QUERYCAP: OK
10981 04:51:46.090442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
10982 04:51:46.090767 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
10984 04:51:46.093615 test VIDIOC_G/S_PRIORITY: OK
10985 04:51:46.114680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
10986 04:51:46.114971 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
10988 04:51:46.117622 test for unlimited opens: OK
10989 04:51:46.140737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
10990 04:51:46.140841
10991 04:51:46.141077 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
10993 04:51:46.151794 Debug ioctls:
10994 04:51:46.161061 <LAVA_SIGNAL_TESTSET STOP>
10995 04:51:46.161303 Received signal: <TESTSET> STOP
10996 04:51:46.161372 Closing test_set Allow-for-multiple-opens
10997 04:51:46.172398 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
10998 04:51:46.172645 Received signal: <TESTSET> START Debug-ioctls
10999 04:51:46.172713 Starting test_set Debug-ioctls
11000 04:51:46.175464 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11001 04:51:46.197824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11002 04:51:46.198111 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11004 04:51:46.204609 test VIDIOC_LOG_STATUS: OK (Not Supported)
11005 04:51:46.226907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11006 04:51:46.226991
11007 04:51:46.227229 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11009 04:51:46.238431 Input ioctls:
11010 04:51:46.247602 <LAVA_SIGNAL_TESTSET STOP>
11011 04:51:46.247873 Received signal: <TESTSET> STOP
11012 04:51:46.247967 Closing test_set Debug-ioctls
11013 04:51:46.257785 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11014 04:51:46.258031 Received signal: <TESTSET> START Input-ioctls
11015 04:51:46.258100 Starting test_set Input-ioctls
11016 04:51:46.260460 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11017 04:51:46.286349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11018 04:51:46.286710 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11020 04:51:46.288984 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11021 04:51:46.309301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11022 04:51:46.309621 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11024 04:51:46.315884 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11025 04:51:46.335686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11026 04:51:46.335944 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11028 04:51:46.338812 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11029 04:51:46.359618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11030 04:51:46.359871 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11032 04:51:46.362973 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11033 04:51:46.385643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11034 04:51:46.385894 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11036 04:51:46.388917 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11037 04:51:46.411552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11038 04:51:46.411803 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11040 04:51:46.414982 Inputs: 0 Audio Inputs: 0 Tuners: 0
11041 04:51:46.422638
11042 04:51:46.442367 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11043 04:51:46.463972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11044 04:51:46.464226 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11046 04:51:46.470593 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11047 04:51:46.490333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11048 04:51:46.490640 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11050 04:51:46.493690 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11051 04:51:46.519185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11052 04:51:46.519453 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11054 04:51:46.525825 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11055 04:51:46.564118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11056 04:51:46.564372 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11058 04:51:46.570492 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11059 04:51:46.592242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11060 04:51:46.592364
11061 04:51:46.592599 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11063 04:51:46.611521 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11064 04:51:46.638070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11065 04:51:46.638321 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11067 04:51:46.644532 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11068 04:51:46.665662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11069 04:51:46.665915 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11071 04:51:46.669442 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11072 04:51:46.688506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11073 04:51:46.688758 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11075 04:51:46.691719 test VIDIOC_G/S_EDID: OK (Not Supported)
11076 04:51:46.713296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11077 04:51:46.713403
11078 04:51:46.713667 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11080 04:51:46.724344 Control ioctls:
11081 04:51:46.732641 <LAVA_SIGNAL_TESTSET STOP>
11082 04:51:46.732913 Received signal: <TESTSET> STOP
11083 04:51:46.733009 Closing test_set Input-ioctls
11084 04:51:46.741338 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11085 04:51:46.741581 Received signal: <TESTSET> START Control-ioctls
11086 04:51:46.741648 Starting test_set Control-ioctls
11087 04:51:46.744615 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11088 04:51:46.771146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11089 04:51:46.771230 test VIDIOC_QUERYCTRL: OK
11090 04:51:46.771462 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11092 04:51:46.791416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11093 04:51:46.791671 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11095 04:51:46.794640 test VIDIOC_G/S_CTRL: OK
11096 04:51:46.816758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11097 04:51:46.817010 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11099 04:51:46.820105 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11100 04:51:46.841338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11101 04:51:46.841589 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11103 04:51:46.851116 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11104 04:51:46.858399 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11105 04:51:46.883001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11106 04:51:46.883284 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11108 04:51:46.886101 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11109 04:51:46.911310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11110 04:51:46.911564 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11112 04:51:46.914582 Standard Controls: 16 Private Controls: 0
11113 04:51:46.922387
11114 04:51:46.939089 Format ioctls:
11115 04:51:46.945521 <LAVA_SIGNAL_TESTSET STOP>
11116 04:51:46.945763 Received signal: <TESTSET> STOP
11117 04:51:46.945829 Closing test_set Control-ioctls
11118 04:51:46.955262 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11119 04:51:46.955529 Received signal: <TESTSET> START Format-ioctls
11120 04:51:46.955599 Starting test_set Format-ioctls
11121 04:51:46.958597 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11122 04:51:46.983025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11123 04:51:46.983304 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11125 04:51:46.986268 test VIDIOC_G/S_PARM: OK
11126 04:51:47.003438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11127 04:51:47.003718 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11129 04:51:47.006919 test VIDIOC_G_FBUF: OK (Not Supported)
11130 04:51:47.029014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11131 04:51:47.029290 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11133 04:51:47.032390 test VIDIOC_G_FMT: OK
11134 04:51:47.054403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11135 04:51:47.054653 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11137 04:51:47.057556 test VIDIOC_TRY_FMT: OK
11138 04:51:47.080103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11139 04:51:47.080377 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11141 04:51:47.089578 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11142 04:51:47.092911 test VIDIOC_S_FMT: FAIL
11143 04:51:47.122966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11144 04:51:47.123218 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11146 04:51:47.126319 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11147 04:51:47.146955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11148 04:51:47.147232 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11150 04:51:47.150272 test Cropping: OK
11151 04:51:47.175268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11152 04:51:47.175547 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11154 04:51:47.177910 test Composing: OK (Not Supported)
11155 04:51:47.203678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11156 04:51:47.203963 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11158 04:51:47.206716 test Scaling: OK (Not Supported)
11159 04:51:47.230468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11160 04:51:47.230548
11161 04:51:47.230787 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11163 04:51:47.241151 Codec ioctls:
11164 04:51:47.249147 <LAVA_SIGNAL_TESTSET STOP>
11165 04:51:47.249386 Received signal: <TESTSET> STOP
11166 04:51:47.249452 Closing test_set Format-ioctls
11167 04:51:47.258460 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11168 04:51:47.258704 Received signal: <TESTSET> START Codec-ioctls
11169 04:51:47.258772 Starting test_set Codec-ioctls
11170 04:51:47.261769 test VIDIOC_(TRY_)ENCODER_CMD: OK
11171 04:51:47.283623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11172 04:51:47.283887 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11174 04:51:47.289902 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11175 04:51:47.308703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11176 04:51:47.308955 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11178 04:51:47.315229 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11179 04:51:47.335347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11180 04:51:47.335455
11181 04:51:47.335719 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11183 04:51:47.345115 Buffer ioctls:
11184 04:51:47.356481 <LAVA_SIGNAL_TESTSET STOP>
11185 04:51:47.356722 Received signal: <TESTSET> STOP
11186 04:51:47.356788 Closing test_set Codec-ioctls
11187 04:51:47.370977 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11188 04:51:47.371218 Received signal: <TESTSET> START Buffer-ioctls
11189 04:51:47.371284 Starting test_set Buffer-ioctls
11190 04:51:47.374277 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11191 04:51:47.400707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11192 04:51:47.400789 test VIDIOC_EXPBUF: OK
11193 04:51:47.401027 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11195 04:51:47.422001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11196 04:51:47.422246 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11198 04:51:47.425078 test Requests: OK (Not Supported)
11199 04:51:47.446514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11200 04:51:47.446596
11201 04:51:47.446833 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11203 04:51:47.458129 Test input 0:
11204 04:51:47.467618
11205 04:51:47.479023 Streaming ioctls:
11206 04:51:47.486074 <LAVA_SIGNAL_TESTSET STOP>
11207 04:51:47.486349 Received signal: <TESTSET> STOP
11208 04:51:47.486417 Closing test_set Buffer-ioctls
11209 04:51:47.495804 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11210 04:51:47.496081 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11211 04:51:47.496179 Starting test_set Streaming-ioctls_Test-input-0
11212 04:51:47.498933 test read/write: OK (Not Supported)
11213 04:51:47.521275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11214 04:51:47.521533 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11216 04:51:47.527459 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2798): node->streamon(q.g_type())
11217 04:51:47.538911 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2845): testBlockingDQBuf(node, q)
11218 04:51:47.544407 test blocking wait: FAIL
11219 04:51:47.570995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11220 04:51:47.571248 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11222 04:51:47.580831 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11223 04:51:47.584045 test MMAP (select): FAIL
11224 04:51:47.609001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11225 04:51:47.609256 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11227 04:51:47.615759 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11228 04:51:47.619025 test MMAP (epoll): FAIL
11229 04:51:47.650710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11230 04:51:47.650962 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11232 04:51:47.660506 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11233 04:51:47.667168 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11234 04:51:47.671061 test USERPTR (select): FAIL
11235 04:51:47.696490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11236 04:51:47.696755 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11238 04:51:47.703373 test DMABUF: Cannot test, specify --expbuf-device
11239 04:51:47.707425
11240 04:51:47.725779 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11241 04:51:47.729674 <LAVA_TEST_RUNNER EXIT>
11242 04:51:47.729930 ok: lava_test_shell seems to have completed
11243 04:51:47.730012 Marking unfinished test run as failed
11245 04:51:47.730931 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11246 04:51:47.731062 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11247 04:51:47.731160 end: 3 lava-test-retry (duration 00:00:03) [common]
11248 04:51:47.731261 start: 4 finalize (timeout 00:08:11) [common]
11249 04:51:47.731366 start: 4.1 power-off (timeout 00:00:30) [common]
11250 04:51:47.731624 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11251 04:51:47.802940 >> Command sent successfully.
11252 04:51:47.805881 Returned 0 in 0 seconds
11253 04:51:47.906282 end: 4.1 power-off (duration 00:00:00) [common]
11255 04:51:47.906737 start: 4.2 read-feedback (timeout 00:08:11) [common]
11256 04:51:47.907052 Listened to connection for namespace 'common' for up to 1s
11257 04:51:48.907987 Finalising connection for namespace 'common'
11258 04:51:48.908168 Disconnecting from shell: Finalise
11259 04:51:48.908246 / #
11260 04:51:49.008606 end: 4.2 read-feedback (duration 00:00:01) [common]
11261 04:51:49.008758 end: 4 finalize (duration 00:00:01) [common]
11262 04:51:49.008870 Cleaning after the job
11263 04:51:49.008969 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699854/tftp-deploy-u2wxkg8_/ramdisk
11264 04:51:49.014603 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699854/tftp-deploy-u2wxkg8_/kernel
11265 04:51:49.023832 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699854/tftp-deploy-u2wxkg8_/dtb
11266 04:51:49.024002 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12699854/tftp-deploy-u2wxkg8_/modules
11267 04:51:49.031570 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12699854
11268 04:51:49.099942 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12699854
11269 04:51:49.100141 Job finished correctly