Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: FAIL
- Errors: 2
- Kernel Warnings: 17
- Kernel Errors: 25
1 12:36:50.649963 lava-dispatcher, installed at version: 2024.01
2 12:36:50.650187 start: 0 validate
3 12:36:50.650319 Start time: 2024-02-05 12:36:50.650312+00:00 (UTC)
4 12:36:50.650452 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:36:50.650586 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 12:36:50.653370 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:36:50.653494 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:37:34.436206 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:37:34.436909 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:37:34.706282 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:37:34.707028 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:37:38.477696 validate duration: 47.83
14 12:37:38.477966 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:37:38.478063 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:37:38.478147 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:37:38.478274 Not decompressing ramdisk as can be used compressed.
18 12:37:38.478356 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
19 12:37:38.478419 saving as /var/lib/lava/dispatcher/tmp/12703560/tftp-deploy-ggnh9y3q/ramdisk/rootfs.cpio.gz
20 12:37:38.478481 total size: 8181372 (7 MB)
21 12:37:38.743956 progress 0 % (0 MB)
22 12:37:38.746363 progress 5 % (0 MB)
23 12:37:38.748520 progress 10 % (0 MB)
24 12:37:38.750781 progress 15 % (1 MB)
25 12:37:38.752908 progress 20 % (1 MB)
26 12:37:38.755173 progress 25 % (1 MB)
27 12:37:38.757311 progress 30 % (2 MB)
28 12:37:38.759585 progress 35 % (2 MB)
29 12:37:38.761695 progress 40 % (3 MB)
30 12:37:38.763974 progress 45 % (3 MB)
31 12:37:38.766136 progress 50 % (3 MB)
32 12:37:38.768376 progress 55 % (4 MB)
33 12:37:38.770431 progress 60 % (4 MB)
34 12:37:38.772655 progress 65 % (5 MB)
35 12:37:38.774761 progress 70 % (5 MB)
36 12:37:38.776992 progress 75 % (5 MB)
37 12:37:38.779048 progress 80 % (6 MB)
38 12:37:38.781267 progress 85 % (6 MB)
39 12:37:38.783315 progress 90 % (7 MB)
40 12:37:38.785527 progress 95 % (7 MB)
41 12:37:38.787609 progress 100 % (7 MB)
42 12:37:38.787809 7 MB downloaded in 0.31 s (25.22 MB/s)
43 12:37:38.787964 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:37:38.788207 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:37:38.788295 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:37:38.788384 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:37:38.788524 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:37:38.788592 saving as /var/lib/lava/dispatcher/tmp/12703560/tftp-deploy-ggnh9y3q/kernel/Image
50 12:37:38.788654 total size: 51534336 (49 MB)
51 12:37:38.788715 No compression specified
52 12:37:38.789832 progress 0 % (0 MB)
53 12:37:38.803258 progress 5 % (2 MB)
54 12:37:38.816715 progress 10 % (4 MB)
55 12:37:38.830014 progress 15 % (7 MB)
56 12:37:38.843634 progress 20 % (9 MB)
57 12:37:38.857073 progress 25 % (12 MB)
58 12:37:38.870295 progress 30 % (14 MB)
59 12:37:38.883641 progress 35 % (17 MB)
60 12:37:38.900565 progress 40 % (19 MB)
61 12:37:38.919457 progress 45 % (22 MB)
62 12:37:38.933103 progress 50 % (24 MB)
63 12:37:38.946580 progress 55 % (27 MB)
64 12:37:38.960170 progress 60 % (29 MB)
65 12:37:38.973722 progress 65 % (31 MB)
66 12:37:38.986881 progress 70 % (34 MB)
67 12:37:39.000469 progress 75 % (36 MB)
68 12:37:39.014436 progress 80 % (39 MB)
69 12:37:39.028005 progress 85 % (41 MB)
70 12:37:39.041603 progress 90 % (44 MB)
71 12:37:39.055120 progress 95 % (46 MB)
72 12:37:39.068217 progress 100 % (49 MB)
73 12:37:39.068533 49 MB downloaded in 0.28 s (175.60 MB/s)
74 12:37:39.068696 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:37:39.068972 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:37:39.069061 start: 1.3 download-retry (timeout 00:09:59) [common]
78 12:37:39.069147 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 12:37:39.069287 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:37:39.069364 saving as /var/lib/lava/dispatcher/tmp/12703560/tftp-deploy-ggnh9y3q/dtb/mt8192-asurada-spherion-r0.dtb
81 12:37:39.069426 total size: 47278 (0 MB)
82 12:37:39.069503 No compression specified
83 12:37:39.070681 progress 69 % (0 MB)
84 12:37:39.070981 progress 100 % (0 MB)
85 12:37:39.071142 0 MB downloaded in 0.00 s (26.32 MB/s)
86 12:37:39.071281 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:37:39.071536 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:37:39.071622 start: 1.4 download-retry (timeout 00:09:59) [common]
90 12:37:39.071705 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 12:37:39.071819 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:37:39.071904 saving as /var/lib/lava/dispatcher/tmp/12703560/tftp-deploy-ggnh9y3q/modules/modules.tar
93 12:37:39.071979 total size: 8639964 (8 MB)
94 12:37:39.072040 Using unxz to decompress xz
95 12:37:39.076337 progress 0 % (0 MB)
96 12:37:39.097288 progress 5 % (0 MB)
97 12:37:39.121881 progress 10 % (0 MB)
98 12:37:39.146563 progress 15 % (1 MB)
99 12:37:39.171083 progress 20 % (1 MB)
100 12:37:39.196080 progress 25 % (2 MB)
101 12:37:39.224503 progress 30 % (2 MB)
102 12:37:39.249270 progress 35 % (2 MB)
103 12:37:39.273406 progress 40 % (3 MB)
104 12:37:39.298230 progress 45 % (3 MB)
105 12:37:39.324341 progress 50 % (4 MB)
106 12:37:39.352585 progress 55 % (4 MB)
107 12:37:39.378185 progress 60 % (4 MB)
108 12:37:39.404649 progress 65 % (5 MB)
109 12:37:39.430368 progress 70 % (5 MB)
110 12:37:39.454317 progress 75 % (6 MB)
111 12:37:39.482199 progress 80 % (6 MB)
112 12:37:39.512027 progress 85 % (7 MB)
113 12:37:39.538616 progress 90 % (7 MB)
114 12:37:39.572309 progress 95 % (7 MB)
115 12:37:39.609437 progress 100 % (8 MB)
116 12:37:39.615450 8 MB downloaded in 0.54 s (15.16 MB/s)
117 12:37:39.615813 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:37:39.616248 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:37:39.616386 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:37:39.616525 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:37:39.616658 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:37:39.616794 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:37:39.617097 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u
125 12:37:39.617288 makedir: /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/bin
126 12:37:39.617437 makedir: /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/tests
127 12:37:39.617580 makedir: /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/results
128 12:37:39.617743 Creating /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/bin/lava-add-keys
129 12:37:39.617947 Creating /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/bin/lava-add-sources
130 12:37:39.618129 Creating /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/bin/lava-background-process-start
131 12:37:39.618312 Creating /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/bin/lava-background-process-stop
132 12:37:39.618491 Creating /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/bin/lava-common-functions
133 12:37:39.618669 Creating /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/bin/lava-echo-ipv4
134 12:37:39.618847 Creating /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/bin/lava-install-packages
135 12:37:39.619032 Creating /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/bin/lava-installed-packages
136 12:37:39.619210 Creating /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/bin/lava-os-build
137 12:37:39.619425 Creating /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/bin/lava-probe-channel
138 12:37:39.619607 Creating /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/bin/lava-probe-ip
139 12:37:39.619788 Creating /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/bin/lava-target-ip
140 12:37:39.619972 Creating /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/bin/lava-target-mac
141 12:37:39.620150 Creating /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/bin/lava-target-storage
142 12:37:39.620334 Creating /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/bin/lava-test-case
143 12:37:39.620516 Creating /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/bin/lava-test-event
144 12:37:39.620696 Creating /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/bin/lava-test-feedback
145 12:37:39.620876 Creating /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/bin/lava-test-raise
146 12:37:39.621055 Creating /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/bin/lava-test-reference
147 12:37:39.621235 Creating /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/bin/lava-test-runner
148 12:37:39.621417 Creating /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/bin/lava-test-set
149 12:37:39.621597 Creating /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/bin/lava-test-shell
150 12:37:39.621784 Updating /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/bin/lava-install-packages (oe)
151 12:37:39.622003 Updating /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/bin/lava-installed-packages (oe)
152 12:37:39.622186 Creating /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/environment
153 12:37:39.622337 LAVA metadata
154 12:37:39.622447 - LAVA_JOB_ID=12703560
155 12:37:39.622553 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:37:39.622704 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:37:39.622805 skipped lava-vland-overlay
158 12:37:39.622921 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:37:39.623046 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:37:39.623141 skipped lava-multinode-overlay
161 12:37:39.623254 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:37:39.623414 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:37:39.623531 Loading test definitions
164 12:37:39.623669 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:37:39.623784 Using /lava-12703560 at stage 0
166 12:37:39.624233 uuid=12703560_1.5.2.3.1 testdef=None
167 12:37:39.624357 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:37:39.624483 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:37:39.625257 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:37:39.625589 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:37:39.626519 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:37:39.626873 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:37:39.627824 runner path: /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/0/tests/0_dmesg test_uuid 12703560_1.5.2.3.1
176 12:37:39.628035 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:37:39.628370 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:59) [common]
179 12:37:39.628482 Using /lava-12703560 at stage 1
180 12:37:39.628919 uuid=12703560_1.5.2.3.5 testdef=None
181 12:37:39.629045 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 12:37:39.629166 start: 1.5.2.3.6 test-overlay (timeout 00:09:59) [common]
183 12:37:39.629852 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 12:37:39.630176 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:59) [common]
186 12:37:39.631108 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 12:37:39.631492 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
189 12:37:39.632494 runner path: /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/1/tests/1_bootrr test_uuid 12703560_1.5.2.3.5
190 12:37:39.632697 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 12:37:39.633006 Creating lava-test-runner.conf files
193 12:37:39.633099 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/0 for stage 0
194 12:37:39.633231 - 0_dmesg
195 12:37:39.633346 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12703560/lava-overlay-ufxpjp8u/lava-12703560/1 for stage 1
196 12:37:39.633478 - 1_bootrr
197 12:37:39.633617 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 12:37:39.633737 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
199 12:37:39.645284 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 12:37:39.645453 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
201 12:37:39.645625 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 12:37:39.645747 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 12:37:39.645871 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
204 12:37:39.904945 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 12:37:39.905416 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
206 12:37:39.905568 extracting modules file /var/lib/lava/dispatcher/tmp/12703560/tftp-deploy-ggnh9y3q/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12703560/extract-overlay-ramdisk-v44m7s_r/ramdisk
207 12:37:40.152053 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 12:37:40.152229 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
209 12:37:40.152324 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12703560/compress-overlay-2tmvjmd4/overlay-1.5.2.4.tar.gz to ramdisk
210 12:37:40.152395 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12703560/compress-overlay-2tmvjmd4/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12703560/extract-overlay-ramdisk-v44m7s_r/ramdisk
211 12:37:40.160600 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 12:37:40.160720 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
213 12:37:40.160842 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 12:37:40.160927 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
215 12:37:40.161007 Building ramdisk /var/lib/lava/dispatcher/tmp/12703560/extract-overlay-ramdisk-v44m7s_r/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12703560/extract-overlay-ramdisk-v44m7s_r/ramdisk
216 12:37:40.564828 >> 145343 blocks
217 12:37:42.888623 rename /var/lib/lava/dispatcher/tmp/12703560/extract-overlay-ramdisk-v44m7s_r/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12703560/tftp-deploy-ggnh9y3q/ramdisk/ramdisk.cpio.gz
218 12:37:42.889093 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 12:37:42.889222 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
220 12:37:42.889326 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
221 12:37:42.889438 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12703560/tftp-deploy-ggnh9y3q/kernel/Image'
222 12:37:56.605436 Returned 0 in 13 seconds
223 12:37:56.706140 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12703560/tftp-deploy-ggnh9y3q/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12703560/tftp-deploy-ggnh9y3q/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12703560/tftp-deploy-ggnh9y3q/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12703560/tftp-deploy-ggnh9y3q/kernel/image.itb
224 12:37:57.148593 output: FIT description: Kernel Image image with one or more FDT blobs
225 12:37:57.149007 output: Created: Mon Feb 5 12:37:57 2024
226 12:37:57.149120 output: Image 0 (kernel-1)
227 12:37:57.149284 output: Description:
228 12:37:57.149398 output: Created: Mon Feb 5 12:37:57 2024
229 12:37:57.149524 output: Type: Kernel Image
230 12:37:57.149662 output: Compression: lzma compressed
231 12:37:57.149759 output: Data Size: 12052857 Bytes = 11770.37 KiB = 11.49 MiB
232 12:37:57.149871 output: Architecture: AArch64
233 12:37:57.149981 output: OS: Linux
234 12:37:57.150073 output: Load Address: 0x00000000
235 12:37:57.150162 output: Entry Point: 0x00000000
236 12:37:57.150251 output: Hash algo: crc32
237 12:37:57.150340 output: Hash value: 8a14336a
238 12:37:57.150426 output: Image 1 (fdt-1)
239 12:37:57.150513 output: Description: mt8192-asurada-spherion-r0
240 12:37:57.150599 output: Created: Mon Feb 5 12:37:57 2024
241 12:37:57.150681 output: Type: Flat Device Tree
242 12:37:57.150790 output: Compression: uncompressed
243 12:37:57.150872 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
244 12:37:57.150989 output: Architecture: AArch64
245 12:37:57.151070 output: Hash algo: crc32
246 12:37:57.151152 output: Hash value: cc4352de
247 12:37:57.151233 output: Image 2 (ramdisk-1)
248 12:37:57.151314 output: Description: unavailable
249 12:37:57.151437 output: Created: Mon Feb 5 12:37:57 2024
250 12:37:57.151520 output: Type: RAMDisk Image
251 12:37:57.151601 output: Compression: Unknown Compression
252 12:37:57.151683 output: Data Size: 21392506 Bytes = 20891.12 KiB = 20.40 MiB
253 12:37:57.151765 output: Architecture: AArch64
254 12:37:57.151846 output: OS: Linux
255 12:37:57.151928 output: Load Address: unavailable
256 12:37:57.152009 output: Entry Point: unavailable
257 12:37:57.152090 output: Hash algo: crc32
258 12:37:57.152171 output: Hash value: 95d39f7f
259 12:37:57.152252 output: Default Configuration: 'conf-1'
260 12:37:57.152333 output: Configuration 0 (conf-1)
261 12:37:57.152414 output: Description: mt8192-asurada-spherion-r0
262 12:37:57.152496 output: Kernel: kernel-1
263 12:37:57.152577 output: Init Ramdisk: ramdisk-1
264 12:37:57.152659 output: FDT: fdt-1
265 12:37:57.152740 output: Loadables: kernel-1
266 12:37:57.152821 output:
267 12:37:57.153109 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
268 12:37:57.153296 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
269 12:37:57.153412 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
270 12:37:57.153512 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
271 12:37:57.153594 No LXC device requested
272 12:37:57.153676 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 12:37:57.153765 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
274 12:37:57.153844 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 12:37:57.153918 Checking files for TFTP limit of 4294967296 bytes.
276 12:37:57.154463 end: 1 tftp-deploy (duration 00:00:19) [common]
277 12:37:57.154583 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 12:37:57.154693 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 12:37:57.154831 substitutions:
280 12:37:57.154903 - {DTB}: 12703560/tftp-deploy-ggnh9y3q/dtb/mt8192-asurada-spherion-r0.dtb
281 12:37:57.155004 - {INITRD}: 12703560/tftp-deploy-ggnh9y3q/ramdisk/ramdisk.cpio.gz
282 12:37:57.155126 - {KERNEL}: 12703560/tftp-deploy-ggnh9y3q/kernel/Image
283 12:37:57.155249 - {LAVA_MAC}: None
284 12:37:57.155338 - {PRESEED_CONFIG}: None
285 12:37:57.155430 - {PRESEED_LOCAL}: None
286 12:37:57.155487 - {RAMDISK}: 12703560/tftp-deploy-ggnh9y3q/ramdisk/ramdisk.cpio.gz
287 12:37:57.155544 - {ROOT_PART}: None
288 12:37:57.155598 - {ROOT}: None
289 12:37:57.155653 - {SERVER_IP}: 192.168.201.1
290 12:37:57.155707 - {TEE}: None
291 12:37:57.155761 Parsed boot commands:
292 12:37:57.155814 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 12:37:57.155997 Parsed boot commands: tftpboot 192.168.201.1 12703560/tftp-deploy-ggnh9y3q/kernel/image.itb 12703560/tftp-deploy-ggnh9y3q/kernel/cmdline
294 12:37:57.156088 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 12:37:57.156176 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 12:37:57.156267 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 12:37:57.156377 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 12:37:57.156451 Not connected, no need to disconnect.
299 12:37:57.156526 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 12:37:57.156622 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 12:37:57.156692 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
302 12:37:57.160955 Setting prompt string to ['lava-test: # ']
303 12:37:57.161568 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 12:37:57.161762 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 12:37:57.161960 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 12:37:57.162141 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 12:37:57.162703 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
308 12:38:02.297305 >> Command sent successfully.
309 12:38:02.300153 Returned 0 in 5 seconds
310 12:38:02.400600 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 12:38:02.400935 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 12:38:02.401038 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 12:38:02.401130 Setting prompt string to 'Starting depthcharge on Spherion...'
315 12:38:02.401203 Changing prompt to 'Starting depthcharge on Spherion...'
316 12:38:02.401274 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 12:38:02.401552 [Enter `^Ec?' for help]
318 12:38:02.573649
319 12:38:02.573800
320 12:38:02.573877 F0: 102B 0000
321 12:38:02.573943
322 12:38:02.574006 F3: 1001 0000 [0200]
323 12:38:02.576961
324 12:38:02.577047 F3: 1001 0000
325 12:38:02.577115
326 12:38:02.577175 F7: 102D 0000
327 12:38:02.577234
328 12:38:02.581016 F1: 0000 0000
329 12:38:02.581100
330 12:38:02.581165 V0: 0000 0000 [0001]
331 12:38:02.581229
332 12:38:02.583947 00: 0007 8000
333 12:38:02.584035
334 12:38:02.584101 01: 0000 0000
335 12:38:02.584165
336 12:38:02.587104 BP: 0C00 0209 [0000]
337 12:38:02.587187
338 12:38:02.587252 G0: 1182 0000
339 12:38:02.587313
340 12:38:02.590491 EC: 0000 0021 [4000]
341 12:38:02.590574
342 12:38:02.590640 S7: 0000 0000 [0000]
343 12:38:02.590702
344 12:38:02.594178 CC: 0000 0000 [0001]
345 12:38:02.594262
346 12:38:02.594329 T0: 0000 0040 [010F]
347 12:38:02.594391
348 12:38:02.594449 Jump to BL
349 12:38:02.597454
350 12:38:02.621097
351 12:38:02.621182
352 12:38:02.621249
353 12:38:02.628538 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 12:38:02.631856 ARM64: Exception handlers installed.
355 12:38:02.635839 ARM64: Testing exception
356 12:38:02.639118 ARM64: Done test exception
357 12:38:02.645597 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 12:38:02.656177 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 12:38:02.662572 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 12:38:02.672758 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 12:38:02.679179 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 12:38:02.685654 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 12:38:02.697272 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 12:38:02.703930 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 12:38:02.723464 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 12:38:02.727267 WDT: Last reset was cold boot
367 12:38:02.730079 SPI1(PAD0) initialized at 2873684 Hz
368 12:38:02.734130 SPI5(PAD0) initialized at 992727 Hz
369 12:38:02.737091 VBOOT: Loading verstage.
370 12:38:02.743467 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 12:38:02.746597 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 12:38:02.749868 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 12:38:02.753240 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 12:38:02.760890 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 12:38:02.767569 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 12:38:02.778373 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
377 12:38:02.778484
378 12:38:02.778578
379 12:38:02.788881 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 12:38:02.791935 ARM64: Exception handlers installed.
381 12:38:02.795196 ARM64: Testing exception
382 12:38:02.795278 ARM64: Done test exception
383 12:38:02.802290 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 12:38:02.806227 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 12:38:02.819226 Probing TPM: . done!
386 12:38:02.819336 TPM ready after 0 ms
387 12:38:02.826076 Connected to device vid:did:rid of 1ae0:0028:00
388 12:38:02.835959 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
389 12:38:02.892942 Initialized TPM device CR50 revision 0
390 12:38:02.902381 tlcl_send_startup: Startup return code is 0
391 12:38:02.902476 TPM: setup succeeded
392 12:38:02.913937 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 12:38:02.923050 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 12:38:02.933965 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 12:38:02.943603 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 12:38:02.946756 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 12:38:02.954950 in-header: 03 07 00 00 08 00 00 00
398 12:38:02.958306 in-data: aa e4 47 04 13 02 00 00
399 12:38:02.962024 Chrome EC: UHEPI supported
400 12:38:02.969094 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 12:38:02.973463 in-header: 03 95 00 00 08 00 00 00
402 12:38:02.976707 in-data: 18 20 20 08 00 00 00 00
403 12:38:02.976791 Phase 1
404 12:38:02.980179 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 12:38:02.987674 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 12:38:02.991056 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 12:38:02.994840 Recovery requested (1009000e)
408 12:38:03.003332 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 12:38:03.009123 tlcl_extend: response is 0
410 12:38:03.018972 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 12:38:03.023880 tlcl_extend: response is 0
412 12:38:03.030782 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 12:38:03.051257 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
414 12:38:03.057577 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 12:38:03.057660
416 12:38:03.057726
417 12:38:03.067387 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 12:38:03.070774 ARM64: Exception handlers installed.
419 12:38:03.074314 ARM64: Testing exception
420 12:38:03.074397 ARM64: Done test exception
421 12:38:03.096494 pmic_efuse_setting: Set efuses in 11 msecs
422 12:38:03.099587 pmwrap_interface_init: Select PMIF_VLD_RDY
423 12:38:03.106276 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 12:38:03.109550 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 12:38:03.116421 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 12:38:03.119870 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 12:38:03.123346 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 12:38:03.130622 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 12:38:03.134841 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 12:38:03.138278 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 12:38:03.142157 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 12:38:03.149700 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 12:38:03.153244 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 12:38:03.156990 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 12:38:03.160614 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 12:38:03.168357 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 12:38:03.175708 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 12:38:03.179473 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 12:38:03.186158 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 12:38:03.190178 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 12:38:03.197826 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 12:38:03.201170 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 12:38:03.208695 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 12:38:03.212557 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 12:38:03.219588 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 12:38:03.223138 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 12:38:03.230946 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 12:38:03.234031 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 12:38:03.242220 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 12:38:03.244868 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 12:38:03.249244 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 12:38:03.256480 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 12:38:03.260060 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 12:38:03.263568 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 12:38:03.270814 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 12:38:03.274557 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 12:38:03.281691 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 12:38:03.285471 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 12:38:03.289150 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 12:38:03.296548 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 12:38:03.300605 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 12:38:03.303717 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 12:38:03.307654 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 12:38:03.314896 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 12:38:03.318189 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 12:38:03.322216 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 12:38:03.326342 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 12:38:03.329839 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 12:38:03.334054 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 12:38:03.340576 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 12:38:03.344150 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 12:38:03.347906 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 12:38:03.351600 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 12:38:03.360067 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 12:38:03.366758 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 12:38:03.373974 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 12:38:03.380941 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 12:38:03.388608 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 12:38:03.392479 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 12:38:03.400140 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 12:38:03.403390 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 12:38:03.410872 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
483 12:38:03.413841 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 12:38:03.418019 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
485 12:38:03.425380 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 12:38:03.433713 [RTC]rtc_get_frequency_meter,154: input=15, output=853
487 12:38:03.443772 [RTC]rtc_get_frequency_meter,154: input=7, output=725
488 12:38:03.453507 [RTC]rtc_get_frequency_meter,154: input=11, output=788
489 12:38:03.462290 [RTC]rtc_get_frequency_meter,154: input=13, output=821
490 12:38:03.472149 [RTC]rtc_get_frequency_meter,154: input=12, output=807
491 12:38:03.480918 [RTC]rtc_get_frequency_meter,154: input=11, output=789
492 12:38:03.491370 [RTC]rtc_get_frequency_meter,154: input=12, output=805
493 12:38:03.494862 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
494 12:38:03.498646 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
495 12:38:03.502581 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
496 12:38:03.509291 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
497 12:38:03.513575 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
498 12:38:03.516765 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
499 12:38:03.520923 ADC[4]: Raw value=903694 ID=7
500 12:38:03.524115 ADC[3]: Raw value=213916 ID=1
501 12:38:03.524200 RAM Code: 0x71
502 12:38:03.528126 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
503 12:38:03.531677 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
504 12:38:03.542395 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
505 12:38:03.549928 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
506 12:38:03.553579 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
507 12:38:03.557184 in-header: 03 07 00 00 08 00 00 00
508 12:38:03.557304 in-data: aa e4 47 04 13 02 00 00
509 12:38:03.560590 Chrome EC: UHEPI supported
510 12:38:03.568503 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
511 12:38:03.572238 in-header: 03 95 00 00 08 00 00 00
512 12:38:03.575900 in-data: 18 20 20 08 00 00 00 00
513 12:38:03.579055 MRC: failed to locate region type 0.
514 12:38:03.582686 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
515 12:38:03.586569 DRAM-K: Running full calibration
516 12:38:03.594103 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
517 12:38:03.594208 header.status = 0x0
518 12:38:03.597844 header.version = 0x6 (expected: 0x6)
519 12:38:03.601058 header.size = 0xd00 (expected: 0xd00)
520 12:38:03.605220 header.flags = 0x0
521 12:38:03.608224 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
522 12:38:03.628118 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
523 12:38:03.635591 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
524 12:38:03.635683 dram_init: ddr_geometry: 2
525 12:38:03.640082 [EMI] MDL number = 2
526 12:38:03.643134 [EMI] Get MDL freq = 0
527 12:38:03.643209 dram_init: ddr_type: 0
528 12:38:03.646731 is_discrete_lpddr4: 1
529 12:38:03.650323 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
530 12:38:03.650413
531 12:38:03.650500
532 12:38:03.650583 [Bian_co] ETT version 0.0.0.1
533 12:38:03.658340 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
534 12:38:03.658427
535 12:38:03.661596 dramc_set_vcore_voltage set vcore to 650000
536 12:38:03.661682 Read voltage for 800, 4
537 12:38:03.664950 Vio18 = 0
538 12:38:03.665036 Vcore = 650000
539 12:38:03.665124 Vdram = 0
540 12:38:03.665206 Vddq = 0
541 12:38:03.668162 Vmddr = 0
542 12:38:03.668274 dram_init: config_dvfs: 1
543 12:38:03.674780 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
544 12:38:03.681600 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
545 12:38:03.685443 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
546 12:38:03.689013 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
547 12:38:03.692620 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
548 12:38:03.696650 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
549 12:38:03.696728 MEM_TYPE=3, freq_sel=18
550 12:38:03.699821 sv_algorithm_assistance_LP4_1600
551 12:38:03.703141 ============ PULL DRAM RESETB DOWN ============
552 12:38:03.710284 ========== PULL DRAM RESETB DOWN end =========
553 12:38:03.713350 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
554 12:38:03.716751 ===================================
555 12:38:03.719853 LPDDR4 DRAM CONFIGURATION
556 12:38:03.723549 ===================================
557 12:38:03.723642 EX_ROW_EN[0] = 0x0
558 12:38:03.727549 EX_ROW_EN[1] = 0x0
559 12:38:03.727635 LP4Y_EN = 0x0
560 12:38:03.729968 WORK_FSP = 0x0
561 12:38:03.733017 WL = 0x2
562 12:38:03.733095 RL = 0x2
563 12:38:03.736850 BL = 0x2
564 12:38:03.736932 RPST = 0x0
565 12:38:03.740144 RD_PRE = 0x0
566 12:38:03.740227 WR_PRE = 0x1
567 12:38:03.742994 WR_PST = 0x0
568 12:38:03.743075 DBI_WR = 0x0
569 12:38:03.746464 DBI_RD = 0x0
570 12:38:03.746546 OTF = 0x1
571 12:38:03.750206 ===================================
572 12:38:03.753109 ===================================
573 12:38:03.756860 ANA top config
574 12:38:03.760229 ===================================
575 12:38:03.760311 DLL_ASYNC_EN = 0
576 12:38:03.763251 ALL_SLAVE_EN = 1
577 12:38:03.766849 NEW_RANK_MODE = 1
578 12:38:03.769941 DLL_IDLE_MODE = 1
579 12:38:03.770023 LP45_APHY_COMB_EN = 1
580 12:38:03.773959 TX_ODT_DIS = 1
581 12:38:03.776671 NEW_8X_MODE = 1
582 12:38:03.780731 ===================================
583 12:38:03.783146 ===================================
584 12:38:03.787262 data_rate = 1600
585 12:38:03.790101 CKR = 1
586 12:38:03.790183 DQ_P2S_RATIO = 8
587 12:38:03.793396 ===================================
588 12:38:03.796954 CA_P2S_RATIO = 8
589 12:38:03.800308 DQ_CA_OPEN = 0
590 12:38:03.803815 DQ_SEMI_OPEN = 0
591 12:38:03.806721 CA_SEMI_OPEN = 0
592 12:38:03.806803 CA_FULL_RATE = 0
593 12:38:03.810508 DQ_CKDIV4_EN = 1
594 12:38:03.813677 CA_CKDIV4_EN = 1
595 12:38:03.817020 CA_PREDIV_EN = 0
596 12:38:03.820790 PH8_DLY = 0
597 12:38:03.824283 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
598 12:38:03.824365 DQ_AAMCK_DIV = 4
599 12:38:03.827038 CA_AAMCK_DIV = 4
600 12:38:03.830774 CA_ADMCK_DIV = 4
601 12:38:03.833803 DQ_TRACK_CA_EN = 0
602 12:38:03.836872 CA_PICK = 800
603 12:38:03.840937 CA_MCKIO = 800
604 12:38:03.841019 MCKIO_SEMI = 0
605 12:38:03.844005 PLL_FREQ = 3068
606 12:38:03.847467 DQ_UI_PI_RATIO = 32
607 12:38:03.851051 CA_UI_PI_RATIO = 0
608 12:38:03.855412 ===================================
609 12:38:03.858875 ===================================
610 12:38:03.858958 memory_type:LPDDR4
611 12:38:03.862669 GP_NUM : 10
612 12:38:03.862751 SRAM_EN : 1
613 12:38:03.866911 MD32_EN : 0
614 12:38:03.870207 ===================================
615 12:38:03.870293 [ANA_INIT] >>>>>>>>>>>>>>
616 12:38:03.873349 <<<<<< [CONFIGURE PHASE]: ANA_TX
617 12:38:03.877791 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
618 12:38:03.881183 ===================================
619 12:38:03.884432 data_rate = 1600,PCW = 0X7600
620 12:38:03.887169 ===================================
621 12:38:03.890537 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
622 12:38:03.897652 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 12:38:03.900318 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
624 12:38:03.907295 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
625 12:38:03.910586 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
626 12:38:03.913764 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
627 12:38:03.913865 [ANA_INIT] flow start
628 12:38:03.917246 [ANA_INIT] PLL >>>>>>>>
629 12:38:03.920373 [ANA_INIT] PLL <<<<<<<<
630 12:38:03.920457 [ANA_INIT] MIDPI >>>>>>>>
631 12:38:03.923640 [ANA_INIT] MIDPI <<<<<<<<
632 12:38:03.927095 [ANA_INIT] DLL >>>>>>>>
633 12:38:03.927180 [ANA_INIT] flow end
634 12:38:03.933548 ============ LP4 DIFF to SE enter ============
635 12:38:03.936982 ============ LP4 DIFF to SE exit ============
636 12:38:03.940451 [ANA_INIT] <<<<<<<<<<<<<
637 12:38:03.943888 [Flow] Enable top DCM control >>>>>
638 12:38:03.947018 [Flow] Enable top DCM control <<<<<
639 12:38:03.947102 Enable DLL master slave shuffle
640 12:38:03.953696 ==============================================================
641 12:38:03.956656 Gating Mode config
642 12:38:03.960080 ==============================================================
643 12:38:03.963953 Config description:
644 12:38:03.973510 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
645 12:38:03.980114 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
646 12:38:03.983017 SELPH_MODE 0: By rank 1: By Phase
647 12:38:03.989770 ==============================================================
648 12:38:03.993625 GAT_TRACK_EN = 1
649 12:38:03.996383 RX_GATING_MODE = 2
650 12:38:04.000009 RX_GATING_TRACK_MODE = 2
651 12:38:04.002916 SELPH_MODE = 1
652 12:38:04.006580 PICG_EARLY_EN = 1
653 12:38:04.006665 VALID_LAT_VALUE = 1
654 12:38:04.012755 ==============================================================
655 12:38:04.016298 Enter into Gating configuration >>>>
656 12:38:04.019501 Exit from Gating configuration <<<<
657 12:38:04.023564 Enter into DVFS_PRE_config >>>>>
658 12:38:04.033384 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
659 12:38:04.036417 Exit from DVFS_PRE_config <<<<<
660 12:38:04.039663 Enter into PICG configuration >>>>
661 12:38:04.043236 Exit from PICG configuration <<<<
662 12:38:04.046331 [RX_INPUT] configuration >>>>>
663 12:38:04.049499 [RX_INPUT] configuration <<<<<
664 12:38:04.053032 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
665 12:38:04.060224 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
666 12:38:04.066617 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
667 12:38:04.072897 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
668 12:38:04.079811 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
669 12:38:04.083142 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
670 12:38:04.089578 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
671 12:38:04.093313 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
672 12:38:04.096787 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
673 12:38:04.100074 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
674 12:38:04.106422 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
675 12:38:04.109877 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
676 12:38:04.112924 ===================================
677 12:38:04.116714 LPDDR4 DRAM CONFIGURATION
678 12:38:04.119933 ===================================
679 12:38:04.120018 EX_ROW_EN[0] = 0x0
680 12:38:04.123091 EX_ROW_EN[1] = 0x0
681 12:38:04.123173 LP4Y_EN = 0x0
682 12:38:04.126212 WORK_FSP = 0x0
683 12:38:04.126311 WL = 0x2
684 12:38:04.129592 RL = 0x2
685 12:38:04.129674 BL = 0x2
686 12:38:04.132804 RPST = 0x0
687 12:38:04.132887 RD_PRE = 0x0
688 12:38:04.136356 WR_PRE = 0x1
689 12:38:04.136438 WR_PST = 0x0
690 12:38:04.139532 DBI_WR = 0x0
691 12:38:04.139614 DBI_RD = 0x0
692 12:38:04.142586 OTF = 0x1
693 12:38:04.146027 ===================================
694 12:38:04.150325 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
695 12:38:04.152781 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
696 12:38:04.159529 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 12:38:04.162644 ===================================
698 12:38:04.166230 LPDDR4 DRAM CONFIGURATION
699 12:38:04.166348 ===================================
700 12:38:04.169475 EX_ROW_EN[0] = 0x10
701 12:38:04.172578 EX_ROW_EN[1] = 0x0
702 12:38:04.172686 LP4Y_EN = 0x0
703 12:38:04.176193 WORK_FSP = 0x0
704 12:38:04.176277 WL = 0x2
705 12:38:04.179599 RL = 0x2
706 12:38:04.179711 BL = 0x2
707 12:38:04.182621 RPST = 0x0
708 12:38:04.182721 RD_PRE = 0x0
709 12:38:04.186241 WR_PRE = 0x1
710 12:38:04.186350 WR_PST = 0x0
711 12:38:04.189544 DBI_WR = 0x0
712 12:38:04.189646 DBI_RD = 0x0
713 12:38:04.192675 OTF = 0x1
714 12:38:04.196006 ===================================
715 12:38:04.203370 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
716 12:38:04.205772 nWR fixed to 40
717 12:38:04.209728 [ModeRegInit_LP4] CH0 RK0
718 12:38:04.209811 [ModeRegInit_LP4] CH0 RK1
719 12:38:04.213023 [ModeRegInit_LP4] CH1 RK0
720 12:38:04.215998 [ModeRegInit_LP4] CH1 RK1
721 12:38:04.216079 match AC timing 13
722 12:38:04.222911 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
723 12:38:04.226474 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
724 12:38:04.229321 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
725 12:38:04.235642 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
726 12:38:04.239067 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
727 12:38:04.239150 [EMI DOE] emi_dcm 0
728 12:38:04.245677 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
729 12:38:04.245760 ==
730 12:38:04.249170 Dram Type= 6, Freq= 0, CH_0, rank 0
731 12:38:04.252559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
732 12:38:04.252642 ==
733 12:38:04.259754 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
734 12:38:04.262673 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
735 12:38:04.273302 [CA 0] Center 37 (7~68) winsize 62
736 12:38:04.276472 [CA 1] Center 37 (6~68) winsize 63
737 12:38:04.280538 [CA 2] Center 34 (4~65) winsize 62
738 12:38:04.283203 [CA 3] Center 35 (4~66) winsize 63
739 12:38:04.286316 [CA 4] Center 33 (3~64) winsize 62
740 12:38:04.289996 [CA 5] Center 33 (3~64) winsize 62
741 12:38:04.290079
742 12:38:04.293202 [CmdBusTrainingLP45] Vref(ca) range 1: 34
743 12:38:04.293285
744 12:38:04.296215 [CATrainingPosCal] consider 1 rank data
745 12:38:04.299854 u2DelayCellTimex100 = 270/100 ps
746 12:38:04.303519 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
747 12:38:04.306858 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
748 12:38:04.313284 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
749 12:38:04.316076 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
750 12:38:04.319640 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
751 12:38:04.322836 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
752 12:38:04.322920
753 12:38:04.326673 CA PerBit enable=1, Macro0, CA PI delay=33
754 12:38:04.326756
755 12:38:04.330566 [CBTSetCACLKResult] CA Dly = 33
756 12:38:04.330648 CS Dly: 5 (0~36)
757 12:38:04.333108 ==
758 12:38:04.333208 Dram Type= 6, Freq= 0, CH_0, rank 1
759 12:38:04.339787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
760 12:38:04.339871 ==
761 12:38:04.342998 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
762 12:38:04.349536 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
763 12:38:04.359717 [CA 0] Center 38 (7~69) winsize 63
764 12:38:04.362671 [CA 1] Center 37 (7~68) winsize 62
765 12:38:04.366683 [CA 2] Center 35 (4~66) winsize 63
766 12:38:04.369391 [CA 3] Center 35 (4~66) winsize 63
767 12:38:04.372759 [CA 4] Center 34 (3~65) winsize 63
768 12:38:04.376490 [CA 5] Center 33 (3~64) winsize 62
769 12:38:04.376573
770 12:38:04.379587 [CmdBusTrainingLP45] Vref(ca) range 1: 34
771 12:38:04.379686
772 12:38:04.382666 [CATrainingPosCal] consider 2 rank data
773 12:38:04.386309 u2DelayCellTimex100 = 270/100 ps
774 12:38:04.389699 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
775 12:38:04.395964 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
776 12:38:04.399152 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
777 12:38:04.402851 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
778 12:38:04.405888 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
779 12:38:04.410472 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
780 12:38:04.410555
781 12:38:04.412362 CA PerBit enable=1, Macro0, CA PI delay=33
782 12:38:04.412448
783 12:38:04.416222 [CBTSetCACLKResult] CA Dly = 33
784 12:38:04.416323 CS Dly: 6 (0~38)
785 12:38:04.419252
786 12:38:04.422569 ----->DramcWriteLeveling(PI) begin...
787 12:38:04.422651 ==
788 12:38:04.426711 Dram Type= 6, Freq= 0, CH_0, rank 0
789 12:38:04.430033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 12:38:04.430142 ==
791 12:38:04.434005 Write leveling (Byte 0): 32 => 32
792 12:38:04.434113 Write leveling (Byte 1): 26 => 26
793 12:38:04.437917 DramcWriteLeveling(PI) end<-----
794 12:38:04.438000
795 12:38:04.438065 ==
796 12:38:04.441206 Dram Type= 6, Freq= 0, CH_0, rank 0
797 12:38:04.445141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
798 12:38:04.445228 ==
799 12:38:04.448016 [Gating] SW mode calibration
800 12:38:04.454893 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
801 12:38:04.462298 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
802 12:38:04.465540 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
803 12:38:04.468389 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
804 12:38:04.475668 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
805 12:38:04.478388 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 12:38:04.481724 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:38:04.488768 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:38:04.491350 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:38:04.495539 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 12:38:04.501385 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 12:38:04.504896 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:38:04.508420 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 12:38:04.514667 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 12:38:04.517689 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 12:38:04.522195 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 12:38:04.527953 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 12:38:04.531135 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 12:38:04.534750 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 12:38:04.541222 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
820 12:38:04.544308 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
821 12:38:04.548415 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 12:38:04.554372 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:38:04.558127 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:38:04.561203 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 12:38:04.569076 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 12:38:04.571394 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:38:04.574680 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
828 12:38:04.581031 0 9 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
829 12:38:04.584482 0 9 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
830 12:38:04.587771 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 12:38:04.594180 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 12:38:04.597865 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
833 12:38:04.600774 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
834 12:38:04.608028 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
835 12:38:04.610800 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
836 12:38:04.614462 0 10 8 | B1->B0 | 3131 2525 | 0 0 | (0 1) (1 0)
837 12:38:04.621492 0 10 12 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
838 12:38:04.624071 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 12:38:04.627597 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 12:38:04.630587 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 12:38:04.637475 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 12:38:04.641130 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 12:38:04.644200 0 11 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
844 12:38:04.651071 0 11 8 | B1->B0 | 2c2c 4343 | 0 0 | (0 0) (0 0)
845 12:38:04.653862 0 11 12 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
846 12:38:04.657567 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 12:38:04.663844 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 12:38:04.667652 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 12:38:04.670388 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 12:38:04.677366 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 12:38:04.681066 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
852 12:38:04.683912 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
853 12:38:04.690777 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
854 12:38:04.693975 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 12:38:04.699206 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 12:38:04.704211 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 12:38:04.707103 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 12:38:04.710670 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 12:38:04.717321 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 12:38:04.720465 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 12:38:04.724203 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 12:38:04.730957 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 12:38:04.734082 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 12:38:04.737124 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 12:38:04.744244 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 12:38:04.747348 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 12:38:04.750525 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
868 12:38:04.753969 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
869 12:38:04.757420 Total UI for P1: 0, mck2ui 16
870 12:38:04.760502 best dqsien dly found for B0: ( 0, 14, 4)
871 12:38:04.767050 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
872 12:38:04.770347 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
873 12:38:04.773766 Total UI for P1: 0, mck2ui 16
874 12:38:04.777763 best dqsien dly found for B1: ( 0, 14, 10)
875 12:38:04.780450 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
876 12:38:04.783985 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
877 12:38:04.784096
878 12:38:04.787286 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
879 12:38:04.790436 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
880 12:38:04.793667 [Gating] SW calibration Done
881 12:38:04.793774 ==
882 12:38:04.797849 Dram Type= 6, Freq= 0, CH_0, rank 0
883 12:38:04.801343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
884 12:38:04.801450 ==
885 12:38:04.804209 RX Vref Scan: 0
886 12:38:04.804312
887 12:38:04.807587 RX Vref 0 -> 0, step: 1
888 12:38:04.807696
889 12:38:04.811143 RX Delay -130 -> 252, step: 16
890 12:38:04.814327 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
891 12:38:04.817946 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
892 12:38:04.820834 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
893 12:38:04.824019 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
894 12:38:04.830667 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
895 12:38:04.833941 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
896 12:38:04.837462 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
897 12:38:04.841340 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
898 12:38:04.844159 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
899 12:38:04.851149 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
900 12:38:04.854270 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
901 12:38:04.857250 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
902 12:38:04.860747 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
903 12:38:04.863970 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
904 12:38:04.870504 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
905 12:38:04.874047 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
906 12:38:04.874157 ==
907 12:38:04.877231 Dram Type= 6, Freq= 0, CH_0, rank 0
908 12:38:04.880645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
909 12:38:04.880754 ==
910 12:38:04.883990 DQS Delay:
911 12:38:04.884097 DQS0 = 0, DQS1 = 0
912 12:38:04.884193 DQM Delay:
913 12:38:04.887195 DQM0 = 89, DQM1 = 76
914 12:38:04.887304 DQ Delay:
915 12:38:04.891044 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
916 12:38:04.894147 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
917 12:38:04.897177 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
918 12:38:04.900237 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
919 12:38:04.900343
920 12:38:04.900436
921 12:38:04.900524 ==
922 12:38:04.903595 Dram Type= 6, Freq= 0, CH_0, rank 0
923 12:38:04.910432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
924 12:38:04.910542 ==
925 12:38:04.910637
926 12:38:04.910726
927 12:38:04.910815 TX Vref Scan disable
928 12:38:04.914089 == TX Byte 0 ==
929 12:38:04.917310 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
930 12:38:04.924115 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
931 12:38:04.924225 == TX Byte 1 ==
932 12:38:04.927179 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
933 12:38:04.933759 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
934 12:38:04.933874 ==
935 12:38:04.937372 Dram Type= 6, Freq= 0, CH_0, rank 0
936 12:38:04.940451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
937 12:38:04.940558 ==
938 12:38:04.954067 TX Vref=22, minBit 7, minWin=26, winSum=436
939 12:38:04.956917 TX Vref=24, minBit 1, minWin=27, winSum=442
940 12:38:04.960171 TX Vref=26, minBit 2, minWin=27, winSum=447
941 12:38:04.963657 TX Vref=28, minBit 2, minWin=27, winSum=451
942 12:38:04.967179 TX Vref=30, minBit 6, minWin=27, winSum=450
943 12:38:04.970544 TX Vref=32, minBit 2, minWin=27, winSum=446
944 12:38:04.976832 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 28
945 12:38:04.976941
946 12:38:04.980711 Final TX Range 1 Vref 28
947 12:38:04.980818
948 12:38:04.980911 ==
949 12:38:04.984035 Dram Type= 6, Freq= 0, CH_0, rank 0
950 12:38:04.987722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
951 12:38:04.987831 ==
952 12:38:04.987926
953 12:38:04.990846
954 12:38:04.990950 TX Vref Scan disable
955 12:38:04.993685 == TX Byte 0 ==
956 12:38:04.997271 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
957 12:38:05.000674 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
958 12:38:05.004214 == TX Byte 1 ==
959 12:38:05.007036 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
960 12:38:05.010270 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
961 12:38:05.013601
962 12:38:05.013710 [DATLAT]
963 12:38:05.013804 Freq=800, CH0 RK0
964 12:38:05.013897
965 12:38:05.016976 DATLAT Default: 0xa
966 12:38:05.017083 0, 0xFFFF, sum = 0
967 12:38:05.020267 1, 0xFFFF, sum = 0
968 12:38:05.020382 2, 0xFFFF, sum = 0
969 12:38:05.024248 3, 0xFFFF, sum = 0
970 12:38:05.024359 4, 0xFFFF, sum = 0
971 12:38:05.026887 5, 0xFFFF, sum = 0
972 12:38:05.026996 6, 0xFFFF, sum = 0
973 12:38:05.030752 7, 0xFFFF, sum = 0
974 12:38:05.033620 8, 0xFFFF, sum = 0
975 12:38:05.033730 9, 0x0, sum = 1
976 12:38:05.033826 10, 0x0, sum = 2
977 12:38:05.036871 11, 0x0, sum = 3
978 12:38:05.036983 12, 0x0, sum = 4
979 12:38:05.040339 best_step = 10
980 12:38:05.040448
981 12:38:05.040544 ==
982 12:38:05.043744 Dram Type= 6, Freq= 0, CH_0, rank 0
983 12:38:05.046821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
984 12:38:05.046929 ==
985 12:38:05.050175 RX Vref Scan: 1
986 12:38:05.050281
987 12:38:05.050375 Set Vref Range= 32 -> 127
988 12:38:05.053810
989 12:38:05.053915 RX Vref 32 -> 127, step: 1
990 12:38:05.054009
991 12:38:05.056848 RX Delay -95 -> 252, step: 8
992 12:38:05.056953
993 12:38:05.060336 Set Vref, RX VrefLevel [Byte0]: 32
994 12:38:05.063752 [Byte1]: 32
995 12:38:05.063859
996 12:38:05.067239 Set Vref, RX VrefLevel [Byte0]: 33
997 12:38:05.070274 [Byte1]: 33
998 12:38:05.074102
999 12:38:05.074210 Set Vref, RX VrefLevel [Byte0]: 34
1000 12:38:05.077027 [Byte1]: 34
1001 12:38:05.082024
1002 12:38:05.082132 Set Vref, RX VrefLevel [Byte0]: 35
1003 12:38:05.084842 [Byte1]: 35
1004 12:38:05.089200
1005 12:38:05.089308 Set Vref, RX VrefLevel [Byte0]: 36
1006 12:38:05.092660 [Byte1]: 36
1007 12:38:05.097064
1008 12:38:05.097173 Set Vref, RX VrefLevel [Byte0]: 37
1009 12:38:05.100659 [Byte1]: 37
1010 12:38:05.104873
1011 12:38:05.104983 Set Vref, RX VrefLevel [Byte0]: 38
1012 12:38:05.108133 [Byte1]: 38
1013 12:38:05.112222
1014 12:38:05.112331 Set Vref, RX VrefLevel [Byte0]: 39
1015 12:38:05.115669 [Byte1]: 39
1016 12:38:05.120050
1017 12:38:05.120161 Set Vref, RX VrefLevel [Byte0]: 40
1018 12:38:05.123171 [Byte1]: 40
1019 12:38:05.127161
1020 12:38:05.127268 Set Vref, RX VrefLevel [Byte0]: 41
1021 12:38:05.130498 [Byte1]: 41
1022 12:38:05.134846
1023 12:38:05.134952 Set Vref, RX VrefLevel [Byte0]: 42
1024 12:38:05.138249 [Byte1]: 42
1025 12:38:05.142115
1026 12:38:05.142223 Set Vref, RX VrefLevel [Byte0]: 43
1027 12:38:05.146540 [Byte1]: 43
1028 12:38:05.149803
1029 12:38:05.149904 Set Vref, RX VrefLevel [Byte0]: 44
1030 12:38:05.153585 [Byte1]: 44
1031 12:38:05.157501
1032 12:38:05.157607 Set Vref, RX VrefLevel [Byte0]: 45
1033 12:38:05.160759 [Byte1]: 45
1034 12:38:05.164951
1035 12:38:05.165058 Set Vref, RX VrefLevel [Byte0]: 46
1036 12:38:05.168300 [Byte1]: 46
1037 12:38:05.172858
1038 12:38:05.172967 Set Vref, RX VrefLevel [Byte0]: 47
1039 12:38:05.176252 [Byte1]: 47
1040 12:38:05.180850
1041 12:38:05.180958 Set Vref, RX VrefLevel [Byte0]: 48
1042 12:38:05.183633 [Byte1]: 48
1043 12:38:05.187723
1044 12:38:05.187828 Set Vref, RX VrefLevel [Byte0]: 49
1045 12:38:05.190962 [Byte1]: 49
1046 12:38:05.195899
1047 12:38:05.196005 Set Vref, RX VrefLevel [Byte0]: 50
1048 12:38:05.198913 [Byte1]: 50
1049 12:38:05.202912
1050 12:38:05.203018 Set Vref, RX VrefLevel [Byte0]: 51
1051 12:38:05.206782 [Byte1]: 51
1052 12:38:05.210783
1053 12:38:05.210890 Set Vref, RX VrefLevel [Byte0]: 52
1054 12:38:05.214526 [Byte1]: 52
1055 12:38:05.218585
1056 12:38:05.218694 Set Vref, RX VrefLevel [Byte0]: 53
1057 12:38:05.221509 [Byte1]: 53
1058 12:38:05.225991
1059 12:38:05.226099 Set Vref, RX VrefLevel [Byte0]: 54
1060 12:38:05.229202 [Byte1]: 54
1061 12:38:05.233376
1062 12:38:05.233485 Set Vref, RX VrefLevel [Byte0]: 55
1063 12:38:05.236617 [Byte1]: 55
1064 12:38:05.240952
1065 12:38:05.241060 Set Vref, RX VrefLevel [Byte0]: 56
1066 12:38:05.244633 [Byte1]: 56
1067 12:38:05.248561
1068 12:38:05.248670 Set Vref, RX VrefLevel [Byte0]: 57
1069 12:38:05.252491 [Byte1]: 57
1070 12:38:05.256163
1071 12:38:05.256272 Set Vref, RX VrefLevel [Byte0]: 58
1072 12:38:05.259842 [Byte1]: 58
1073 12:38:05.264018
1074 12:38:05.264126 Set Vref, RX VrefLevel [Byte0]: 59
1075 12:38:05.267272 [Byte1]: 59
1076 12:38:05.271352
1077 12:38:05.271480 Set Vref, RX VrefLevel [Byte0]: 60
1078 12:38:05.274718 [Byte1]: 60
1079 12:38:05.279652
1080 12:38:05.279761 Set Vref, RX VrefLevel [Byte0]: 61
1081 12:38:05.285651 [Byte1]: 61
1082 12:38:05.285759
1083 12:38:05.288961 Set Vref, RX VrefLevel [Byte0]: 62
1084 12:38:05.292039 [Byte1]: 62
1085 12:38:05.292142
1086 12:38:05.295154 Set Vref, RX VrefLevel [Byte0]: 63
1087 12:38:05.298464 [Byte1]: 63
1088 12:38:05.302164
1089 12:38:05.302272 Set Vref, RX VrefLevel [Byte0]: 64
1090 12:38:05.305198 [Byte1]: 64
1091 12:38:05.309566
1092 12:38:05.309674 Set Vref, RX VrefLevel [Byte0]: 65
1093 12:38:05.312687 [Byte1]: 65
1094 12:38:05.316835
1095 12:38:05.316943 Set Vref, RX VrefLevel [Byte0]: 66
1096 12:38:05.320062 [Byte1]: 66
1097 12:38:05.324433
1098 12:38:05.324540 Set Vref, RX VrefLevel [Byte0]: 67
1099 12:38:05.327619 [Byte1]: 67
1100 12:38:05.332032
1101 12:38:05.332141 Set Vref, RX VrefLevel [Byte0]: 68
1102 12:38:05.335469 [Byte1]: 68
1103 12:38:05.340553
1104 12:38:05.340663 Set Vref, RX VrefLevel [Byte0]: 69
1105 12:38:05.343350 [Byte1]: 69
1106 12:38:05.347234
1107 12:38:05.347341 Set Vref, RX VrefLevel [Byte0]: 70
1108 12:38:05.350995 [Byte1]: 70
1109 12:38:05.355109
1110 12:38:05.355216 Set Vref, RX VrefLevel [Byte0]: 71
1111 12:38:05.358122 [Byte1]: 71
1112 12:38:05.362600
1113 12:38:05.362707 Set Vref, RX VrefLevel [Byte0]: 72
1114 12:38:05.366197 [Byte1]: 72
1115 12:38:05.370296
1116 12:38:05.370402 Set Vref, RX VrefLevel [Byte0]: 73
1117 12:38:05.373306 [Byte1]: 73
1118 12:38:05.377993
1119 12:38:05.378098 Set Vref, RX VrefLevel [Byte0]: 74
1120 12:38:05.381367 [Byte1]: 74
1121 12:38:05.385438
1122 12:38:05.385544 Set Vref, RX VrefLevel [Byte0]: 75
1123 12:38:05.389170 [Byte1]: 75
1124 12:38:05.393317
1125 12:38:05.393421 Set Vref, RX VrefLevel [Byte0]: 76
1126 12:38:05.396877 [Byte1]: 76
1127 12:38:05.400784
1128 12:38:05.400889 Final RX Vref Byte 0 = 54 to rank0
1129 12:38:05.403597 Final RX Vref Byte 1 = 59 to rank0
1130 12:38:05.407122 Final RX Vref Byte 0 = 54 to rank1
1131 12:38:05.410499 Final RX Vref Byte 1 = 59 to rank1==
1132 12:38:05.413734 Dram Type= 6, Freq= 0, CH_0, rank 0
1133 12:38:05.420682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1134 12:38:05.420791 ==
1135 12:38:05.420879 DQS Delay:
1136 12:38:05.420964 DQS0 = 0, DQS1 = 0
1137 12:38:05.423641 DQM Delay:
1138 12:38:05.423752 DQM0 = 88, DQM1 = 75
1139 12:38:05.427565 DQ Delay:
1140 12:38:05.430249 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1141 12:38:05.433642 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1142 12:38:05.436872 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =68
1143 12:38:05.440277 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1144 12:38:05.440387
1145 12:38:05.440482
1146 12:38:05.446903 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f28, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
1147 12:38:05.450189 CH0 RK0: MR19=606, MR18=2F28
1148 12:38:05.457253 CH0_RK0: MR19=0x606, MR18=0x2F28, DQSOSC=397, MR23=63, INC=93, DEC=62
1149 12:38:05.457364
1150 12:38:05.460642 ----->DramcWriteLeveling(PI) begin...
1151 12:38:05.460750 ==
1152 12:38:05.463716 Dram Type= 6, Freq= 0, CH_0, rank 1
1153 12:38:05.466892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1154 12:38:05.466994 ==
1155 12:38:05.470500 Write leveling (Byte 0): 31 => 31
1156 12:38:05.473461 Write leveling (Byte 1): 30 => 30
1157 12:38:05.476723 DramcWriteLeveling(PI) end<-----
1158 12:38:05.476830
1159 12:38:05.476924 ==
1160 12:38:05.480865 Dram Type= 6, Freq= 0, CH_0, rank 1
1161 12:38:05.484005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1162 12:38:05.484115 ==
1163 12:38:05.487618 [Gating] SW mode calibration
1164 12:38:05.531382 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1165 12:38:05.531519 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1166 12:38:05.531898 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1167 12:38:05.532360 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1168 12:38:05.533022 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:38:05.533322 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 12:38:05.533428 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 12:38:05.533725 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 12:38:05.534275 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 12:38:05.538874 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 12:38:05.541958 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 12:38:05.542066 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:38:05.548806 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:38:05.553158 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:38:05.555146 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 12:38:05.562447 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 12:38:05.565200 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 12:38:05.568683 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 12:38:05.575189 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1183 12:38:05.578437 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1184 12:38:05.581645 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1185 12:38:05.589177 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1186 12:38:05.591732 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 12:38:05.594967 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 12:38:05.601784 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 12:38:05.605189 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 12:38:05.608235 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 12:38:05.614898 0 9 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1192 12:38:05.618266 0 9 8 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)
1193 12:38:05.621947 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1194 12:38:05.628260 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1195 12:38:05.631830 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1196 12:38:05.635045 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1197 12:38:05.641820 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1198 12:38:05.645078 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1199 12:38:05.647967 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
1200 12:38:05.655071 0 10 8 | B1->B0 | 3232 2323 | 1 0 | (1 1) (0 0)
1201 12:38:05.658723 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1202 12:38:05.661326 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 12:38:05.667955 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 12:38:05.671738 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 12:38:05.675011 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 12:38:05.678870 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 12:38:05.686230 0 11 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
1208 12:38:05.689833 0 11 8 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
1209 12:38:05.693918 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 12:38:05.696910 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 12:38:05.703254 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 12:38:05.706536 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 12:38:05.710463 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 12:38:05.712995 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 12:38:05.720409 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1216 12:38:05.723473 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1217 12:38:05.726872 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 12:38:05.733555 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 12:38:05.736318 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 12:38:05.740637 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 12:38:05.746294 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 12:38:05.749864 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 12:38:05.753805 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 12:38:05.760346 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 12:38:05.762965 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 12:38:05.766169 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 12:38:05.773976 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 12:38:05.776601 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 12:38:05.780536 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 12:38:05.786583 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 12:38:05.789735 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1232 12:38:05.793955 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1233 12:38:05.795931 Total UI for P1: 0, mck2ui 16
1234 12:38:05.799727 best dqsien dly found for B0: ( 0, 14, 4)
1235 12:38:05.803063 Total UI for P1: 0, mck2ui 16
1236 12:38:05.806382 best dqsien dly found for B1: ( 0, 14, 4)
1237 12:38:05.810224 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1238 12:38:05.812709 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1239 12:38:05.812814
1240 12:38:05.816501 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1241 12:38:05.822471 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1242 12:38:05.822580 [Gating] SW calibration Done
1243 12:38:05.822674 ==
1244 12:38:05.826120 Dram Type= 6, Freq= 0, CH_0, rank 1
1245 12:38:05.832889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1246 12:38:05.833019 ==
1247 12:38:05.833113 RX Vref Scan: 0
1248 12:38:05.833203
1249 12:38:05.835899 RX Vref 0 -> 0, step: 1
1250 12:38:05.836022
1251 12:38:05.839346 RX Delay -130 -> 252, step: 16
1252 12:38:05.842914 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1253 12:38:05.846125 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1254 12:38:05.849179 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1255 12:38:05.856037 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1256 12:38:05.859995 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1257 12:38:05.862748 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1258 12:38:05.866514 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1259 12:38:05.869248 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1260 12:38:05.875914 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1261 12:38:05.878983 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1262 12:38:05.882424 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1263 12:38:05.886010 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1264 12:38:05.889294 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1265 12:38:05.895612 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1266 12:38:05.899116 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1267 12:38:05.902351 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1268 12:38:05.902458 ==
1269 12:38:05.905790 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 12:38:05.909280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1271 12:38:05.912436 ==
1272 12:38:05.912544 DQS Delay:
1273 12:38:05.912637 DQS0 = 0, DQS1 = 0
1274 12:38:05.915721 DQM Delay:
1275 12:38:05.915826 DQM0 = 84, DQM1 = 77
1276 12:38:05.919231 DQ Delay:
1277 12:38:05.919336 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1278 12:38:05.922259 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =85
1279 12:38:05.925638 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1280 12:38:05.928685 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1281 12:38:05.928798
1282 12:38:05.932875
1283 12:38:05.933018 ==
1284 12:38:05.935917 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 12:38:05.938862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 12:38:05.938943 ==
1287 12:38:05.939008
1288 12:38:05.939068
1289 12:38:05.942287 TX Vref Scan disable
1290 12:38:05.942368 == TX Byte 0 ==
1291 12:38:05.948738 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1292 12:38:05.952458 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1293 12:38:05.952543 == TX Byte 1 ==
1294 12:38:05.959257 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1295 12:38:05.962762 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1296 12:38:05.962844 ==
1297 12:38:05.965498 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 12:38:05.969015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 12:38:05.969098 ==
1300 12:38:05.982315 TX Vref=22, minBit 1, minWin=27, winSum=444
1301 12:38:05.985781 TX Vref=24, minBit 1, minWin=27, winSum=448
1302 12:38:05.989004 TX Vref=26, minBit 1, minWin=27, winSum=449
1303 12:38:05.991835 TX Vref=28, minBit 3, minWin=27, winSum=454
1304 12:38:05.995095 TX Vref=30, minBit 1, minWin=27, winSum=452
1305 12:38:06.002156 TX Vref=32, minBit 0, minWin=28, winSum=451
1306 12:38:06.005308 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 32
1307 12:38:06.005389
1308 12:38:06.009131 Final TX Range 1 Vref 32
1309 12:38:06.009212
1310 12:38:06.009275 ==
1311 12:38:06.012195 Dram Type= 6, Freq= 0, CH_0, rank 1
1312 12:38:06.015483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1313 12:38:06.018523 ==
1314 12:38:06.018603
1315 12:38:06.018666
1316 12:38:06.018725 TX Vref Scan disable
1317 12:38:06.022248 == TX Byte 0 ==
1318 12:38:06.025409 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1319 12:38:06.032497 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1320 12:38:06.032589 == TX Byte 1 ==
1321 12:38:06.035351 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1322 12:38:06.041815 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1323 12:38:06.041921
1324 12:38:06.042013 [DATLAT]
1325 12:38:06.042100 Freq=800, CH0 RK1
1326 12:38:06.042185
1327 12:38:06.045442 DATLAT Default: 0xa
1328 12:38:06.045549 0, 0xFFFF, sum = 0
1329 12:38:06.048382 1, 0xFFFF, sum = 0
1330 12:38:06.048464 2, 0xFFFF, sum = 0
1331 12:38:06.051957 3, 0xFFFF, sum = 0
1332 12:38:06.055169 4, 0xFFFF, sum = 0
1333 12:38:06.055270 5, 0xFFFF, sum = 0
1334 12:38:06.058488 6, 0xFFFF, sum = 0
1335 12:38:06.058570 7, 0xFFFF, sum = 0
1336 12:38:06.062421 8, 0xFFFF, sum = 0
1337 12:38:06.062504 9, 0x0, sum = 1
1338 12:38:06.065453 10, 0x0, sum = 2
1339 12:38:06.065536 11, 0x0, sum = 3
1340 12:38:06.065601 12, 0x0, sum = 4
1341 12:38:06.068414 best_step = 10
1342 12:38:06.068495
1343 12:38:06.068558 ==
1344 12:38:06.071660 Dram Type= 6, Freq= 0, CH_0, rank 1
1345 12:38:06.075516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1346 12:38:06.075598 ==
1347 12:38:06.078819 RX Vref Scan: 0
1348 12:38:06.078899
1349 12:38:06.081679 RX Vref 0 -> 0, step: 1
1350 12:38:06.081759
1351 12:38:06.081822 RX Delay -95 -> 252, step: 8
1352 12:38:06.088498 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1353 12:38:06.092300 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1354 12:38:06.095528 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1355 12:38:06.098413 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1356 12:38:06.102413 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1357 12:38:06.108430 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1358 12:38:06.112117 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1359 12:38:06.115750 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1360 12:38:06.118647 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1361 12:38:06.121997 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1362 12:38:06.128754 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1363 12:38:06.132385 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1364 12:38:06.135285 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1365 12:38:06.139015 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1366 12:38:06.144988 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1367 12:38:06.148570 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1368 12:38:06.148651 ==
1369 12:38:06.151759 Dram Type= 6, Freq= 0, CH_0, rank 1
1370 12:38:06.154989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 12:38:06.155070 ==
1372 12:38:06.158301 DQS Delay:
1373 12:38:06.158382 DQS0 = 0, DQS1 = 0
1374 12:38:06.158446 DQM Delay:
1375 12:38:06.161988 DQM0 = 86, DQM1 = 77
1376 12:38:06.162068 DQ Delay:
1377 12:38:06.165469 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1378 12:38:06.168313 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1379 12:38:06.171698 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1380 12:38:06.175169 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1381 12:38:06.175275
1382 12:38:06.175372
1383 12:38:06.184940 [DQSOSCAuto] RK1, (LSB)MR18= 0x302c, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
1384 12:38:06.185022 CH0 RK1: MR19=606, MR18=302C
1385 12:38:06.191486 CH0_RK1: MR19=0x606, MR18=0x302C, DQSOSC=397, MR23=63, INC=93, DEC=62
1386 12:38:06.195248 [RxdqsGatingPostProcess] freq 800
1387 12:38:06.201527 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1388 12:38:06.204512 Pre-setting of DQS Precalculation
1389 12:38:06.208129 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1390 12:38:06.208211 ==
1391 12:38:06.211543 Dram Type= 6, Freq= 0, CH_1, rank 0
1392 12:38:06.218287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1393 12:38:06.218368 ==
1394 12:38:06.221446 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1395 12:38:06.227780 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1396 12:38:06.237006 [CA 0] Center 37 (6~68) winsize 63
1397 12:38:06.240278 [CA 1] Center 37 (6~68) winsize 63
1398 12:38:06.244087 [CA 2] Center 35 (5~65) winsize 61
1399 12:38:06.247415 [CA 3] Center 34 (4~65) winsize 62
1400 12:38:06.250236 [CA 4] Center 34 (4~65) winsize 62
1401 12:38:06.253885 [CA 5] Center 34 (3~65) winsize 63
1402 12:38:06.253965
1403 12:38:06.256949 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1404 12:38:06.257030
1405 12:38:06.260396 [CATrainingPosCal] consider 1 rank data
1406 12:38:06.263697 u2DelayCellTimex100 = 270/100 ps
1407 12:38:06.267296 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1408 12:38:06.271156 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1409 12:38:06.276931 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1410 12:38:06.280075 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1411 12:38:06.283614 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1412 12:38:06.287802 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1413 12:38:06.287884
1414 12:38:06.290305 CA PerBit enable=1, Macro0, CA PI delay=34
1415 12:38:06.290388
1416 12:38:06.293967 [CBTSetCACLKResult] CA Dly = 34
1417 12:38:06.294049 CS Dly: 4 (0~35)
1418 12:38:06.296834 ==
1419 12:38:06.299950 Dram Type= 6, Freq= 0, CH_1, rank 1
1420 12:38:06.303732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1421 12:38:06.303815 ==
1422 12:38:06.306832 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1423 12:38:06.313351 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1424 12:38:06.323309 [CA 0] Center 36 (6~67) winsize 62
1425 12:38:06.326487 [CA 1] Center 36 (6~67) winsize 62
1426 12:38:06.329686 [CA 2] Center 35 (5~65) winsize 61
1427 12:38:06.333424 [CA 3] Center 34 (3~65) winsize 63
1428 12:38:06.336693 [CA 4] Center 34 (4~65) winsize 62
1429 12:38:06.340178 [CA 5] Center 33 (3~64) winsize 62
1430 12:38:06.340259
1431 12:38:06.343475 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1432 12:38:06.343557
1433 12:38:06.347298 [CATrainingPosCal] consider 2 rank data
1434 12:38:06.351068 u2DelayCellTimex100 = 270/100 ps
1435 12:38:06.354687 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1436 12:38:06.358151 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1437 12:38:06.361928 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1438 12:38:06.365483 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1439 12:38:06.369315 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1440 12:38:06.372754 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1441 12:38:06.372861
1442 12:38:06.376808 CA PerBit enable=1, Macro0, CA PI delay=33
1443 12:38:06.376922
1444 12:38:06.379029 [CBTSetCACLKResult] CA Dly = 33
1445 12:38:06.382842 CS Dly: 5 (0~37)
1446 12:38:06.382950
1447 12:38:06.386386 ----->DramcWriteLeveling(PI) begin...
1448 12:38:06.386503 ==
1449 12:38:06.389568 Dram Type= 6, Freq= 0, CH_1, rank 0
1450 12:38:06.392894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1451 12:38:06.393004 ==
1452 12:38:06.396753 Write leveling (Byte 0): 28 => 28
1453 12:38:06.399368 Write leveling (Byte 1): 28 => 28
1454 12:38:06.402354 DramcWriteLeveling(PI) end<-----
1455 12:38:06.402460
1456 12:38:06.402552 ==
1457 12:38:06.405649 Dram Type= 6, Freq= 0, CH_1, rank 0
1458 12:38:06.409172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1459 12:38:06.409282 ==
1460 12:38:06.412646 [Gating] SW mode calibration
1461 12:38:06.419471 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1462 12:38:06.425917 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1463 12:38:06.428864 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1464 12:38:06.433086 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1465 12:38:06.439294 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:38:06.443022 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 12:38:06.446000 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 12:38:06.452315 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 12:38:06.455855 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 12:38:06.460380 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 12:38:06.465628 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 12:38:06.469209 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:38:06.472064 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:38:06.478919 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:38:06.482222 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 12:38:06.485715 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 12:38:06.489349 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 12:38:06.495732 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 12:38:06.499154 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 12:38:06.502051 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1481 12:38:06.508999 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 12:38:06.513577 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 12:38:06.515808 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 12:38:06.521927 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 12:38:06.525646 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 12:38:06.528692 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 12:38:06.535193 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 12:38:06.538585 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 12:38:06.541973 0 9 8 | B1->B0 | 2d2d 3434 | 0 0 | (0 0) (0 0)
1490 12:38:06.548529 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 12:38:06.552323 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1492 12:38:06.555353 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 12:38:06.562056 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1494 12:38:06.566429 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1495 12:38:06.568535 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1496 12:38:06.574956 0 10 4 | B1->B0 | 3232 2f2f | 1 1 | (1 0) (1 0)
1497 12:38:06.578298 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 12:38:06.581758 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 12:38:06.588656 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 12:38:06.592370 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 12:38:06.595055 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 12:38:06.601941 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 12:38:06.604985 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 12:38:06.608812 0 11 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1505 12:38:06.615067 0 11 8 | B1->B0 | 3f3f 4343 | 0 0 | (0 0) (0 0)
1506 12:38:06.618943 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 12:38:06.621753 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 12:38:06.628811 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 12:38:06.631664 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 12:38:06.634916 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 12:38:06.641269 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 12:38:06.644583 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1513 12:38:06.647851 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1514 12:38:06.654646 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 12:38:06.657666 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 12:38:06.661015 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 12:38:06.667632 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 12:38:06.671209 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 12:38:06.674672 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 12:38:06.681174 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 12:38:06.684567 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 12:38:06.688346 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 12:38:06.691276 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 12:38:06.697781 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 12:38:06.701434 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 12:38:06.704192 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 12:38:06.710760 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1528 12:38:06.714552 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1529 12:38:06.717948 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1530 12:38:06.721093 Total UI for P1: 0, mck2ui 16
1531 12:38:06.723939 best dqsien dly found for B0: ( 0, 14, 2)
1532 12:38:06.727518 Total UI for P1: 0, mck2ui 16
1533 12:38:06.730535 best dqsien dly found for B1: ( 0, 14, 4)
1534 12:38:06.734415 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1535 12:38:06.737704 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1536 12:38:06.740763
1537 12:38:06.744354 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1538 12:38:06.747477 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1539 12:38:06.750643 [Gating] SW calibration Done
1540 12:38:06.750747 ==
1541 12:38:06.754618 Dram Type= 6, Freq= 0, CH_1, rank 0
1542 12:38:06.757417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1543 12:38:06.757523 ==
1544 12:38:06.757614 RX Vref Scan: 0
1545 12:38:06.757702
1546 12:38:06.760597 RX Vref 0 -> 0, step: 1
1547 12:38:06.760700
1548 12:38:06.764015 RX Delay -130 -> 252, step: 16
1549 12:38:06.767145 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1550 12:38:06.770895 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1551 12:38:06.777564 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1552 12:38:06.781154 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1553 12:38:06.783829 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1554 12:38:06.787106 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1555 12:38:06.790599 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1556 12:38:06.797775 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1557 12:38:06.800482 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1558 12:38:06.804354 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1559 12:38:06.807113 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1560 12:38:06.810590 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1561 12:38:06.817361 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1562 12:38:06.820559 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1563 12:38:06.823637 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1564 12:38:06.827223 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1565 12:38:06.827326 ==
1566 12:38:06.830567 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 12:38:06.837295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 12:38:06.837406 ==
1569 12:38:06.837500 DQS Delay:
1570 12:38:06.840742 DQS0 = 0, DQS1 = 0
1571 12:38:06.840849 DQM Delay:
1572 12:38:06.840941 DQM0 = 87, DQM1 = 80
1573 12:38:06.843977 DQ Delay:
1574 12:38:06.847461 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1575 12:38:06.850471 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1576 12:38:06.854372 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1577 12:38:06.857152 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1578 12:38:06.857223
1579 12:38:06.857289
1580 12:38:06.857397 ==
1581 12:38:06.860693 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 12:38:06.863772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 12:38:06.863854 ==
1584 12:38:06.863917
1585 12:38:06.863975
1586 12:38:06.867610 TX Vref Scan disable
1587 12:38:06.867678 == TX Byte 0 ==
1588 12:38:06.873612 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1589 12:38:06.877364 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1590 12:38:06.877441 == TX Byte 1 ==
1591 12:38:06.883584 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1592 12:38:06.887221 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1593 12:38:06.887308 ==
1594 12:38:06.891222 Dram Type= 6, Freq= 0, CH_1, rank 0
1595 12:38:06.894368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1596 12:38:06.894442 ==
1597 12:38:06.907553 TX Vref=22, minBit 5, minWin=26, winSum=442
1598 12:38:06.911160 TX Vref=24, minBit 2, minWin=27, winSum=448
1599 12:38:06.914042 TX Vref=26, minBit 4, minWin=27, winSum=452
1600 12:38:06.917621 TX Vref=28, minBit 0, minWin=28, winSum=456
1601 12:38:06.921452 TX Vref=30, minBit 1, minWin=27, winSum=457
1602 12:38:06.925003 TX Vref=32, minBit 1, minWin=27, winSum=451
1603 12:38:06.932000 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 28
1604 12:38:06.932079
1605 12:38:06.934939 Final TX Range 1 Vref 28
1606 12:38:06.935016
1607 12:38:06.935076 ==
1608 12:38:06.938239 Dram Type= 6, Freq= 0, CH_1, rank 0
1609 12:38:06.941512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1610 12:38:06.941585 ==
1611 12:38:06.941646
1612 12:38:06.941702
1613 12:38:06.945573 TX Vref Scan disable
1614 12:38:06.948060 == TX Byte 0 ==
1615 12:38:06.951702 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1616 12:38:06.954573 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1617 12:38:06.958892 == TX Byte 1 ==
1618 12:38:06.961628 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1619 12:38:06.964506 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1620 12:38:06.964576
1621 12:38:06.969139 [DATLAT]
1622 12:38:06.969210 Freq=800, CH1 RK0
1623 12:38:06.969269
1624 12:38:06.971513 DATLAT Default: 0xa
1625 12:38:06.971583 0, 0xFFFF, sum = 0
1626 12:38:06.974612 1, 0xFFFF, sum = 0
1627 12:38:06.974693 2, 0xFFFF, sum = 0
1628 12:38:06.977707 3, 0xFFFF, sum = 0
1629 12:38:06.977787 4, 0xFFFF, sum = 0
1630 12:38:06.981384 5, 0xFFFF, sum = 0
1631 12:38:06.981460 6, 0xFFFF, sum = 0
1632 12:38:06.984595 7, 0xFFFF, sum = 0
1633 12:38:06.984670 8, 0xFFFF, sum = 0
1634 12:38:06.987832 9, 0x0, sum = 1
1635 12:38:06.987905 10, 0x0, sum = 2
1636 12:38:06.991176 11, 0x0, sum = 3
1637 12:38:06.991272 12, 0x0, sum = 4
1638 12:38:06.994287 best_step = 10
1639 12:38:06.994360
1640 12:38:06.994421 ==
1641 12:38:06.997684 Dram Type= 6, Freq= 0, CH_1, rank 0
1642 12:38:07.001348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1643 12:38:07.001428 ==
1644 12:38:07.004320 RX Vref Scan: 1
1645 12:38:07.004388
1646 12:38:07.004456 Set Vref Range= 32 -> 127
1647 12:38:07.004512
1648 12:38:07.008190 RX Vref 32 -> 127, step: 1
1649 12:38:07.008260
1650 12:38:07.011957 RX Delay -95 -> 252, step: 8
1651 12:38:07.012031
1652 12:38:07.014866 Set Vref, RX VrefLevel [Byte0]: 32
1653 12:38:07.018745 [Byte1]: 32
1654 12:38:07.018816
1655 12:38:07.021009 Set Vref, RX VrefLevel [Byte0]: 33
1656 12:38:07.025341 [Byte1]: 33
1657 12:38:07.027894
1658 12:38:07.027959 Set Vref, RX VrefLevel [Byte0]: 34
1659 12:38:07.031439 [Byte1]: 34
1660 12:38:07.035420
1661 12:38:07.035508 Set Vref, RX VrefLevel [Byte0]: 35
1662 12:38:07.038851 [Byte1]: 35
1663 12:38:07.042884
1664 12:38:07.042957 Set Vref, RX VrefLevel [Byte0]: 36
1665 12:38:07.047214 [Byte1]: 36
1666 12:38:07.050520
1667 12:38:07.050589 Set Vref, RX VrefLevel [Byte0]: 37
1668 12:38:07.053790 [Byte1]: 37
1669 12:38:07.058261
1670 12:38:07.058332 Set Vref, RX VrefLevel [Byte0]: 38
1671 12:38:07.061749 [Byte1]: 38
1672 12:38:07.066281
1673 12:38:07.066348 Set Vref, RX VrefLevel [Byte0]: 39
1674 12:38:07.069319 [Byte1]: 39
1675 12:38:07.073981
1676 12:38:07.074054 Set Vref, RX VrefLevel [Byte0]: 40
1677 12:38:07.077486 [Byte1]: 40
1678 12:38:07.081043
1679 12:38:07.081116 Set Vref, RX VrefLevel [Byte0]: 41
1680 12:38:07.084429 [Byte1]: 41
1681 12:38:07.088622
1682 12:38:07.088696 Set Vref, RX VrefLevel [Byte0]: 42
1683 12:38:07.091753 [Byte1]: 42
1684 12:38:07.096089
1685 12:38:07.096159 Set Vref, RX VrefLevel [Byte0]: 43
1686 12:38:07.099523 [Byte1]: 43
1687 12:38:07.103876
1688 12:38:07.103949 Set Vref, RX VrefLevel [Byte0]: 44
1689 12:38:07.107264 [Byte1]: 44
1690 12:38:07.111653
1691 12:38:07.111723 Set Vref, RX VrefLevel [Byte0]: 45
1692 12:38:07.114627 [Byte1]: 45
1693 12:38:07.118904
1694 12:38:07.118977 Set Vref, RX VrefLevel [Byte0]: 46
1695 12:38:07.122375 [Byte1]: 46
1696 12:38:07.126380
1697 12:38:07.126448 Set Vref, RX VrefLevel [Byte0]: 47
1698 12:38:07.130080 [Byte1]: 47
1699 12:38:07.134165
1700 12:38:07.134236 Set Vref, RX VrefLevel [Byte0]: 48
1701 12:38:07.137720 [Byte1]: 48
1702 12:38:07.142463
1703 12:38:07.142539 Set Vref, RX VrefLevel [Byte0]: 49
1704 12:38:07.144906 [Byte1]: 49
1705 12:38:07.149462
1706 12:38:07.149534 Set Vref, RX VrefLevel [Byte0]: 50
1707 12:38:07.152845 [Byte1]: 50
1708 12:38:07.156967
1709 12:38:07.157036 Set Vref, RX VrefLevel [Byte0]: 51
1710 12:38:07.160404 [Byte1]: 51
1711 12:38:07.164594
1712 12:38:07.164662 Set Vref, RX VrefLevel [Byte0]: 52
1713 12:38:07.167888 [Byte1]: 52
1714 12:38:07.172276
1715 12:38:07.172351 Set Vref, RX VrefLevel [Byte0]: 53
1716 12:38:07.175212 [Byte1]: 53
1717 12:38:07.179942
1718 12:38:07.180018 Set Vref, RX VrefLevel [Byte0]: 54
1719 12:38:07.183004 [Byte1]: 54
1720 12:38:07.187913
1721 12:38:07.187988 Set Vref, RX VrefLevel [Byte0]: 55
1722 12:38:07.190816 [Byte1]: 55
1723 12:38:07.195145
1724 12:38:07.195221 Set Vref, RX VrefLevel [Byte0]: 56
1725 12:38:07.198226 [Byte1]: 56
1726 12:38:07.202633
1727 12:38:07.202720 Set Vref, RX VrefLevel [Byte0]: 57
1728 12:38:07.206024 [Byte1]: 57
1729 12:38:07.210534
1730 12:38:07.210611 Set Vref, RX VrefLevel [Byte0]: 58
1731 12:38:07.213418 [Byte1]: 58
1732 12:38:07.217577
1733 12:38:07.217657 Set Vref, RX VrefLevel [Byte0]: 59
1734 12:38:07.220823 [Byte1]: 59
1735 12:38:07.225290
1736 12:38:07.225370 Set Vref, RX VrefLevel [Byte0]: 60
1737 12:38:07.228738 [Byte1]: 60
1738 12:38:07.233168
1739 12:38:07.233247 Set Vref, RX VrefLevel [Byte0]: 61
1740 12:38:07.236727 [Byte1]: 61
1741 12:38:07.240355
1742 12:38:07.240435 Set Vref, RX VrefLevel [Byte0]: 62
1743 12:38:07.243701 [Byte1]: 62
1744 12:38:07.248216
1745 12:38:07.248295 Set Vref, RX VrefLevel [Byte0]: 63
1746 12:38:07.251327 [Byte1]: 63
1747 12:38:07.255665
1748 12:38:07.255744 Set Vref, RX VrefLevel [Byte0]: 64
1749 12:38:07.259177 [Byte1]: 64
1750 12:38:07.263727
1751 12:38:07.263807 Set Vref, RX VrefLevel [Byte0]: 65
1752 12:38:07.266996 [Byte1]: 65
1753 12:38:07.271078
1754 12:38:07.271160 Set Vref, RX VrefLevel [Byte0]: 66
1755 12:38:07.274651 [Byte1]: 66
1756 12:38:07.278469
1757 12:38:07.278550 Set Vref, RX VrefLevel [Byte0]: 67
1758 12:38:07.282184 [Byte1]: 67
1759 12:38:07.285890
1760 12:38:07.285970 Set Vref, RX VrefLevel [Byte0]: 68
1761 12:38:07.289437 [Byte1]: 68
1762 12:38:07.293577
1763 12:38:07.293658 Set Vref, RX VrefLevel [Byte0]: 69
1764 12:38:07.297356 [Byte1]: 69
1765 12:38:07.301430
1766 12:38:07.301511 Set Vref, RX VrefLevel [Byte0]: 70
1767 12:38:07.304557 [Byte1]: 70
1768 12:38:07.308726
1769 12:38:07.308806 Set Vref, RX VrefLevel [Byte0]: 71
1770 12:38:07.311920 [Byte1]: 71
1771 12:38:07.316769
1772 12:38:07.316849 Set Vref, RX VrefLevel [Byte0]: 72
1773 12:38:07.319861 [Byte1]: 72
1774 12:38:07.324739
1775 12:38:07.324850 Set Vref, RX VrefLevel [Byte0]: 73
1776 12:38:07.327323 [Byte1]: 73
1777 12:38:07.331746
1778 12:38:07.331858 Set Vref, RX VrefLevel [Byte0]: 74
1779 12:38:07.335097 [Byte1]: 74
1780 12:38:07.339487
1781 12:38:07.339597 Set Vref, RX VrefLevel [Byte0]: 75
1782 12:38:07.342732 [Byte1]: 75
1783 12:38:07.346713
1784 12:38:07.346829 Final RX Vref Byte 0 = 57 to rank0
1785 12:38:07.350343 Final RX Vref Byte 1 = 56 to rank0
1786 12:38:07.354271 Final RX Vref Byte 0 = 57 to rank1
1787 12:38:07.356903 Final RX Vref Byte 1 = 56 to rank1==
1788 12:38:07.360458 Dram Type= 6, Freq= 0, CH_1, rank 0
1789 12:38:07.366917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1790 12:38:07.367037 ==
1791 12:38:07.367145 DQS Delay:
1792 12:38:07.367250 DQS0 = 0, DQS1 = 0
1793 12:38:07.370347 DQM Delay:
1794 12:38:07.370463 DQM0 = 85, DQM1 = 80
1795 12:38:07.373463 DQ Delay:
1796 12:38:07.376753 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1797 12:38:07.380255 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =80
1798 12:38:07.383151 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
1799 12:38:07.386789 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1800 12:38:07.386907
1801 12:38:07.387015
1802 12:38:07.393220 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d30, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
1803 12:38:07.396545 CH1 RK0: MR19=606, MR18=1D30
1804 12:38:07.403707 CH1_RK0: MR19=0x606, MR18=0x1D30, DQSOSC=397, MR23=63, INC=93, DEC=62
1805 12:38:07.403830
1806 12:38:07.406890 ----->DramcWriteLeveling(PI) begin...
1807 12:38:07.407007 ==
1808 12:38:07.409853 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 12:38:07.413545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1810 12:38:07.413663 ==
1811 12:38:07.416859 Write leveling (Byte 0): 27 => 27
1812 12:38:07.420164 Write leveling (Byte 1): 28 => 28
1813 12:38:07.423221 DramcWriteLeveling(PI) end<-----
1814 12:38:07.423353
1815 12:38:07.423482 ==
1816 12:38:07.426727 Dram Type= 6, Freq= 0, CH_1, rank 1
1817 12:38:07.430859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1818 12:38:07.431014 ==
1819 12:38:07.433071 [Gating] SW mode calibration
1820 12:38:07.440300 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1821 12:38:07.446297 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1822 12:38:07.450310 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1823 12:38:07.453518 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1824 12:38:07.459912 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 12:38:07.463161 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 12:38:07.466239 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 12:38:07.473247 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 12:38:07.476339 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 12:38:07.480136 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 12:38:07.486319 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 12:38:07.489860 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 12:38:07.492885 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 12:38:07.499731 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 12:38:07.502825 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 12:38:07.506168 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 12:38:07.513004 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 12:38:07.516058 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 12:38:07.519471 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 12:38:07.526430 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1840 12:38:07.529707 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1841 12:38:07.532928 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 12:38:07.539186 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 12:38:07.542686 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 12:38:07.546250 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 12:38:07.552445 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 12:38:07.556236 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 12:38:07.559145 0 9 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1848 12:38:07.565965 0 9 8 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
1849 12:38:07.569672 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 12:38:07.572694 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 12:38:07.576366 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 12:38:07.583067 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 12:38:07.586211 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 12:38:07.589304 0 10 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1855 12:38:07.595854 0 10 4 | B1->B0 | 3333 2828 | 1 1 | (1 0) (0 0)
1856 12:38:07.599544 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1857 12:38:07.603047 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 12:38:07.609236 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 12:38:07.612472 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 12:38:07.616039 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 12:38:07.622230 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 12:38:07.625900 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1863 12:38:07.629271 0 11 4 | B1->B0 | 2626 4040 | 0 0 | (0 0) (0 0)
1864 12:38:07.635786 0 11 8 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1865 12:38:07.639108 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 12:38:07.642504 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 12:38:07.649179 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 12:38:07.652168 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 12:38:07.655801 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 12:38:07.662191 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 12:38:07.665825 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1872 12:38:07.668839 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1873 12:38:07.675571 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 12:38:07.678951 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 12:38:07.683196 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 12:38:07.688653 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 12:38:07.692310 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 12:38:07.695574 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 12:38:07.702349 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 12:38:07.705332 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 12:38:07.709437 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 12:38:07.715343 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 12:38:07.718469 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 12:38:07.721844 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 12:38:07.728615 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 12:38:07.731794 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1887 12:38:07.735023 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1888 12:38:07.741849 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1889 12:38:07.741953 Total UI for P1: 0, mck2ui 16
1890 12:38:07.745162 best dqsien dly found for B0: ( 0, 14, 2)
1891 12:38:07.751909 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 12:38:07.755121 Total UI for P1: 0, mck2ui 16
1893 12:38:07.758263 best dqsien dly found for B1: ( 0, 14, 6)
1894 12:38:07.761786 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1895 12:38:07.764770 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1896 12:38:07.764864
1897 12:38:07.768700 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1898 12:38:07.772269 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1899 12:38:07.775248 [Gating] SW calibration Done
1900 12:38:07.775333 ==
1901 12:38:07.778193 Dram Type= 6, Freq= 0, CH_1, rank 1
1902 12:38:07.781225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1903 12:38:07.781313 ==
1904 12:38:07.784880 RX Vref Scan: 0
1905 12:38:07.784968
1906 12:38:07.788485 RX Vref 0 -> 0, step: 1
1907 12:38:07.788569
1908 12:38:07.788670 RX Delay -130 -> 252, step: 16
1909 12:38:07.794934 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1910 12:38:07.798288 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1911 12:38:07.801497 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1912 12:38:07.804946 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1913 12:38:07.808433 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1914 12:38:07.814768 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1915 12:38:07.818364 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1916 12:38:07.821140 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1917 12:38:07.825365 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1918 12:38:07.828011 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1919 12:38:07.834385 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1920 12:38:07.837770 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1921 12:38:07.841653 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1922 12:38:07.844429 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1923 12:38:07.848476 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1924 12:38:07.855086 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1925 12:38:07.855162 ==
1926 12:38:07.857712 Dram Type= 6, Freq= 0, CH_1, rank 1
1927 12:38:07.860979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1928 12:38:07.861053 ==
1929 12:38:07.861146 DQS Delay:
1930 12:38:07.865066 DQS0 = 0, DQS1 = 0
1931 12:38:07.865154 DQM Delay:
1932 12:38:07.867713 DQM0 = 82, DQM1 = 79
1933 12:38:07.867810 DQ Delay:
1934 12:38:07.871211 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1935 12:38:07.874233 DQ4 =85, DQ5 =85, DQ6 =85, DQ7 =85
1936 12:38:07.877384 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1937 12:38:07.881067 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1938 12:38:07.881164
1939 12:38:07.881252
1940 12:38:07.881344 ==
1941 12:38:07.884102 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 12:38:07.887561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 12:38:07.890818 ==
1944 12:38:07.890890
1945 12:38:07.890950
1946 12:38:07.891006 TX Vref Scan disable
1947 12:38:07.893909 == TX Byte 0 ==
1948 12:38:07.897633 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1949 12:38:07.900952 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1950 12:38:07.903863 == TX Byte 1 ==
1951 12:38:07.907144 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1952 12:38:07.910677 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1953 12:38:07.913903 ==
1954 12:38:07.917316 Dram Type= 6, Freq= 0, CH_1, rank 1
1955 12:38:07.920878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1956 12:38:07.920952 ==
1957 12:38:07.933085 TX Vref=22, minBit 1, minWin=27, winSum=449
1958 12:38:07.937117 TX Vref=24, minBit 1, minWin=27, winSum=451
1959 12:38:07.939823 TX Vref=26, minBit 0, minWin=28, winSum=455
1960 12:38:07.943016 TX Vref=28, minBit 1, minWin=27, winSum=454
1961 12:38:07.946293 TX Vref=30, minBit 0, minWin=28, winSum=455
1962 12:38:07.952928 TX Vref=32, minBit 1, minWin=27, winSum=454
1963 12:38:07.956192 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 26
1964 12:38:07.956278
1965 12:38:07.959799 Final TX Range 1 Vref 26
1966 12:38:07.959890
1967 12:38:07.959955 ==
1968 12:38:07.962899 Dram Type= 6, Freq= 0, CH_1, rank 1
1969 12:38:07.966054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1970 12:38:07.966129 ==
1971 12:38:07.969228
1972 12:38:07.969324
1973 12:38:07.969420 TX Vref Scan disable
1974 12:38:07.972986 == TX Byte 0 ==
1975 12:38:07.975941 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1976 12:38:07.982636 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1977 12:38:07.982734 == TX Byte 1 ==
1978 12:38:07.986159 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1979 12:38:07.993299 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1980 12:38:07.993382
1981 12:38:07.993445 [DATLAT]
1982 12:38:07.993504 Freq=800, CH1 RK1
1983 12:38:07.993578
1984 12:38:07.996101 DATLAT Default: 0xa
1985 12:38:07.996173 0, 0xFFFF, sum = 0
1986 12:38:07.999403 1, 0xFFFF, sum = 0
1987 12:38:07.999489 2, 0xFFFF, sum = 0
1988 12:38:08.003252 3, 0xFFFF, sum = 0
1989 12:38:08.005817 4, 0xFFFF, sum = 0
1990 12:38:08.005901 5, 0xFFFF, sum = 0
1991 12:38:08.009053 6, 0xFFFF, sum = 0
1992 12:38:08.009131 7, 0xFFFF, sum = 0
1993 12:38:08.012911 8, 0xFFFF, sum = 0
1994 12:38:08.012984 9, 0x0, sum = 1
1995 12:38:08.016198 10, 0x0, sum = 2
1996 12:38:08.016269 11, 0x0, sum = 3
1997 12:38:08.018779 12, 0x0, sum = 4
1998 12:38:08.018891 best_step = 10
1999 12:38:08.018980
2000 12:38:08.019063 ==
2001 12:38:08.022320 Dram Type= 6, Freq= 0, CH_1, rank 1
2002 12:38:08.025713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2003 12:38:08.025821 ==
2004 12:38:08.029374 RX Vref Scan: 0
2005 12:38:08.029475
2006 12:38:08.032598 RX Vref 0 -> 0, step: 1
2007 12:38:08.032719
2008 12:38:08.032823 RX Delay -95 -> 252, step: 8
2009 12:38:08.039545 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2010 12:38:08.043122 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
2011 12:38:08.045898 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2012 12:38:08.049781 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
2013 12:38:08.056291 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
2014 12:38:08.059392 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2015 12:38:08.062623 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2016 12:38:08.065712 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2017 12:38:08.069341 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2018 12:38:08.072627 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2019 12:38:08.079799 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2020 12:38:08.082710 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
2021 12:38:08.085907 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2022 12:38:08.088854 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2023 12:38:08.095834 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2024 12:38:08.099054 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2025 12:38:08.099135 ==
2026 12:38:08.102516 Dram Type= 6, Freq= 0, CH_1, rank 1
2027 12:38:08.105817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2028 12:38:08.105898 ==
2029 12:38:08.108844 DQS Delay:
2030 12:38:08.108921 DQS0 = 0, DQS1 = 0
2031 12:38:08.108985 DQM Delay:
2032 12:38:08.112320 DQM0 = 86, DQM1 = 81
2033 12:38:08.112393 DQ Delay:
2034 12:38:08.115634 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2035 12:38:08.119529 DQ4 =88, DQ5 =96, DQ6 =92, DQ7 =84
2036 12:38:08.122345 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =76
2037 12:38:08.125820 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2038 12:38:08.125926
2039 12:38:08.126014
2040 12:38:08.135534 [DQSOSCAuto] RK1, (LSB)MR18= 0x2641, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
2041 12:38:08.135627 CH1 RK1: MR19=606, MR18=2641
2042 12:38:08.142238 CH1_RK1: MR19=0x606, MR18=0x2641, DQSOSC=393, MR23=63, INC=95, DEC=63
2043 12:38:08.145465 [RxdqsGatingPostProcess] freq 800
2044 12:38:08.151956 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2045 12:38:08.155468 Pre-setting of DQS Precalculation
2046 12:38:08.158747 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2047 12:38:08.165287 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2048 12:38:08.175735 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2049 12:38:08.175842
2050 12:38:08.175908
2051 12:38:08.178705 [Calibration Summary] 1600 Mbps
2052 12:38:08.178792 CH 0, Rank 0
2053 12:38:08.182101 SW Impedance : PASS
2054 12:38:08.182178 DUTY Scan : NO K
2055 12:38:08.185116 ZQ Calibration : PASS
2056 12:38:08.189261 Jitter Meter : NO K
2057 12:38:08.189348 CBT Training : PASS
2058 12:38:08.192210 Write leveling : PASS
2059 12:38:08.192289 RX DQS gating : PASS
2060 12:38:08.195124 RX DQ/DQS(RDDQC) : PASS
2061 12:38:08.199271 TX DQ/DQS : PASS
2062 12:38:08.199386 RX DATLAT : PASS
2063 12:38:08.202006 RX DQ/DQS(Engine): PASS
2064 12:38:08.206084 TX OE : NO K
2065 12:38:08.206160 All Pass.
2066 12:38:08.206247
2067 12:38:08.206322 CH 0, Rank 1
2068 12:38:08.208643 SW Impedance : PASS
2069 12:38:08.212031 DUTY Scan : NO K
2070 12:38:08.212129 ZQ Calibration : PASS
2071 12:38:08.215267 Jitter Meter : NO K
2072 12:38:08.218460 CBT Training : PASS
2073 12:38:08.218536 Write leveling : PASS
2074 12:38:08.221922 RX DQS gating : PASS
2075 12:38:08.225115 RX DQ/DQS(RDDQC) : PASS
2076 12:38:08.225196 TX DQ/DQS : PASS
2077 12:38:08.228409 RX DATLAT : PASS
2078 12:38:08.231544 RX DQ/DQS(Engine): PASS
2079 12:38:08.231627 TX OE : NO K
2080 12:38:08.234835 All Pass.
2081 12:38:08.234912
2082 12:38:08.235008 CH 1, Rank 0
2083 12:38:08.238193 SW Impedance : PASS
2084 12:38:08.238273 DUTY Scan : NO K
2085 12:38:08.241571 ZQ Calibration : PASS
2086 12:38:08.244875 Jitter Meter : NO K
2087 12:38:08.244952 CBT Training : PASS
2088 12:38:08.247970 Write leveling : PASS
2089 12:38:08.252035 RX DQS gating : PASS
2090 12:38:08.252119 RX DQ/DQS(RDDQC) : PASS
2091 12:38:08.254942 TX DQ/DQS : PASS
2092 12:38:08.255027 RX DATLAT : PASS
2093 12:38:08.258200 RX DQ/DQS(Engine): PASS
2094 12:38:08.261401 TX OE : NO K
2095 12:38:08.261483 All Pass.
2096 12:38:08.261570
2097 12:38:08.261649 CH 1, Rank 1
2098 12:38:08.264597 SW Impedance : PASS
2099 12:38:08.268424 DUTY Scan : NO K
2100 12:38:08.268504 ZQ Calibration : PASS
2101 12:38:08.271492 Jitter Meter : NO K
2102 12:38:08.274488 CBT Training : PASS
2103 12:38:08.274564 Write leveling : PASS
2104 12:38:08.277824 RX DQS gating : PASS
2105 12:38:08.281475 RX DQ/DQS(RDDQC) : PASS
2106 12:38:08.281561 TX DQ/DQS : PASS
2107 12:38:08.284573 RX DATLAT : PASS
2108 12:38:08.288059 RX DQ/DQS(Engine): PASS
2109 12:38:08.288137 TX OE : NO K
2110 12:38:08.291134 All Pass.
2111 12:38:08.291276
2112 12:38:08.291379 DramC Write-DBI off
2113 12:38:08.294484 PER_BANK_REFRESH: Hybrid Mode
2114 12:38:08.294568 TX_TRACKING: ON
2115 12:38:08.298204 [GetDramInforAfterCalByMRR] Vendor 6.
2116 12:38:08.304446 [GetDramInforAfterCalByMRR] Revision 606.
2117 12:38:08.308155 [GetDramInforAfterCalByMRR] Revision 2 0.
2118 12:38:08.308237 MR0 0x3b3b
2119 12:38:08.308325 MR8 0x5151
2120 12:38:08.311380 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2121 12:38:08.311477
2122 12:38:08.314605 MR0 0x3b3b
2123 12:38:08.314686 MR8 0x5151
2124 12:38:08.317978 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2125 12:38:08.318059
2126 12:38:08.327814 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2127 12:38:08.331217 [FAST_K] Save calibration result to emmc
2128 12:38:08.334329 [FAST_K] Save calibration result to emmc
2129 12:38:08.338383 dram_init: config_dvfs: 1
2130 12:38:08.342355 dramc_set_vcore_voltage set vcore to 662500
2131 12:38:08.344481 Read voltage for 1200, 2
2132 12:38:08.344564 Vio18 = 0
2133 12:38:08.344628 Vcore = 662500
2134 12:38:08.347762 Vdram = 0
2135 12:38:08.347844 Vddq = 0
2136 12:38:08.347908 Vmddr = 0
2137 12:38:08.354470 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2138 12:38:08.357748 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2139 12:38:08.360903 MEM_TYPE=3, freq_sel=15
2140 12:38:08.364384 sv_algorithm_assistance_LP4_1600
2141 12:38:08.368033 ============ PULL DRAM RESETB DOWN ============
2142 12:38:08.370884 ========== PULL DRAM RESETB DOWN end =========
2143 12:38:08.377842 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2144 12:38:08.380774 ===================================
2145 12:38:08.380859 LPDDR4 DRAM CONFIGURATION
2146 12:38:08.384205 ===================================
2147 12:38:08.388133 EX_ROW_EN[0] = 0x0
2148 12:38:08.390704 EX_ROW_EN[1] = 0x0
2149 12:38:08.390785 LP4Y_EN = 0x0
2150 12:38:08.394283 WORK_FSP = 0x0
2151 12:38:08.394364 WL = 0x4
2152 12:38:08.397617 RL = 0x4
2153 12:38:08.397698 BL = 0x2
2154 12:38:08.400742 RPST = 0x0
2155 12:38:08.400823 RD_PRE = 0x0
2156 12:38:08.403941 WR_PRE = 0x1
2157 12:38:08.404023 WR_PST = 0x0
2158 12:38:08.407566 DBI_WR = 0x0
2159 12:38:08.407647 DBI_RD = 0x0
2160 12:38:08.410460 OTF = 0x1
2161 12:38:08.413905 ===================================
2162 12:38:08.417225 ===================================
2163 12:38:08.417306 ANA top config
2164 12:38:08.420533 ===================================
2165 12:38:08.423647 DLL_ASYNC_EN = 0
2166 12:38:08.427258 ALL_SLAVE_EN = 0
2167 12:38:08.430585 NEW_RANK_MODE = 1
2168 12:38:08.430675 DLL_IDLE_MODE = 1
2169 12:38:08.434285 LP45_APHY_COMB_EN = 1
2170 12:38:08.437432 TX_ODT_DIS = 1
2171 12:38:08.440648 NEW_8X_MODE = 1
2172 12:38:08.443730 ===================================
2173 12:38:08.447099 ===================================
2174 12:38:08.450676 data_rate = 2400
2175 12:38:08.450758 CKR = 1
2176 12:38:08.454599 DQ_P2S_RATIO = 8
2177 12:38:08.457790 ===================================
2178 12:38:08.460618 CA_P2S_RATIO = 8
2179 12:38:08.463922 DQ_CA_OPEN = 0
2180 12:38:08.467272 DQ_SEMI_OPEN = 0
2181 12:38:08.470483 CA_SEMI_OPEN = 0
2182 12:38:08.470565 CA_FULL_RATE = 0
2183 12:38:08.473659 DQ_CKDIV4_EN = 0
2184 12:38:08.477536 CA_CKDIV4_EN = 0
2185 12:38:08.480257 CA_PREDIV_EN = 0
2186 12:38:08.483686 PH8_DLY = 17
2187 12:38:08.487394 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2188 12:38:08.487490 DQ_AAMCK_DIV = 4
2189 12:38:08.491358 CA_AAMCK_DIV = 4
2190 12:38:08.493432 CA_ADMCK_DIV = 4
2191 12:38:08.497256 DQ_TRACK_CA_EN = 0
2192 12:38:08.500449 CA_PICK = 1200
2193 12:38:08.503581 CA_MCKIO = 1200
2194 12:38:08.507408 MCKIO_SEMI = 0
2195 12:38:08.507505 PLL_FREQ = 2366
2196 12:38:08.510543 DQ_UI_PI_RATIO = 32
2197 12:38:08.514145 CA_UI_PI_RATIO = 0
2198 12:38:08.517008 ===================================
2199 12:38:08.520451 ===================================
2200 12:38:08.523213 memory_type:LPDDR4
2201 12:38:08.526579 GP_NUM : 10
2202 12:38:08.526661 SRAM_EN : 1
2203 12:38:08.529949 MD32_EN : 0
2204 12:38:08.533303 ===================================
2205 12:38:08.533400 [ANA_INIT] >>>>>>>>>>>>>>
2206 12:38:08.536487 <<<<<< [CONFIGURE PHASE]: ANA_TX
2207 12:38:08.539703 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2208 12:38:08.543810 ===================================
2209 12:38:08.546400 data_rate = 2400,PCW = 0X5b00
2210 12:38:08.550014 ===================================
2211 12:38:08.553401 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2212 12:38:08.560479 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2213 12:38:08.566372 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2214 12:38:08.569806 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2215 12:38:08.572930 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2216 12:38:08.576404 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2217 12:38:08.579596 [ANA_INIT] flow start
2218 12:38:08.579679 [ANA_INIT] PLL >>>>>>>>
2219 12:38:08.583279 [ANA_INIT] PLL <<<<<<<<
2220 12:38:08.586808 [ANA_INIT] MIDPI >>>>>>>>
2221 12:38:08.586891 [ANA_INIT] MIDPI <<<<<<<<
2222 12:38:08.590203 [ANA_INIT] DLL >>>>>>>>
2223 12:38:08.592835 [ANA_INIT] DLL <<<<<<<<
2224 12:38:08.592917 [ANA_INIT] flow end
2225 12:38:08.599562 ============ LP4 DIFF to SE enter ============
2226 12:38:08.603221 ============ LP4 DIFF to SE exit ============
2227 12:38:08.603345 [ANA_INIT] <<<<<<<<<<<<<
2228 12:38:08.607007 [Flow] Enable top DCM control >>>>>
2229 12:38:08.609712 [Flow] Enable top DCM control <<<<<
2230 12:38:08.613542 Enable DLL master slave shuffle
2231 12:38:08.619572 ==============================================================
2232 12:38:08.622971 Gating Mode config
2233 12:38:08.626502 ==============================================================
2234 12:38:08.629661 Config description:
2235 12:38:08.639905 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2236 12:38:08.646410 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2237 12:38:08.649299 SELPH_MODE 0: By rank 1: By Phase
2238 12:38:08.655725 ==============================================================
2239 12:38:08.659511 GAT_TRACK_EN = 1
2240 12:38:08.662685 RX_GATING_MODE = 2
2241 12:38:08.666461 RX_GATING_TRACK_MODE = 2
2242 12:38:08.666551 SELPH_MODE = 1
2243 12:38:08.669070 PICG_EARLY_EN = 1
2244 12:38:08.672898 VALID_LAT_VALUE = 1
2245 12:38:08.679454 ==============================================================
2246 12:38:08.682500 Enter into Gating configuration >>>>
2247 12:38:08.686373 Exit from Gating configuration <<<<
2248 12:38:08.689514 Enter into DVFS_PRE_config >>>>>
2249 12:38:08.699451 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2250 12:38:08.702399 Exit from DVFS_PRE_config <<<<<
2251 12:38:08.705732 Enter into PICG configuration >>>>
2252 12:38:08.709080 Exit from PICG configuration <<<<
2253 12:38:08.712246 [RX_INPUT] configuration >>>>>
2254 12:38:08.715741 [RX_INPUT] configuration <<<<<
2255 12:38:08.719228 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2256 12:38:08.725822 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2257 12:38:08.732602 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2258 12:38:08.739048 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2259 12:38:08.745907 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2260 12:38:08.749100 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2261 12:38:08.755520 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2262 12:38:08.758773 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2263 12:38:08.762090 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2264 12:38:08.765508 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2265 12:38:08.769769 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2266 12:38:08.775470 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2267 12:38:08.779038 ===================================
2268 12:38:08.782199 LPDDR4 DRAM CONFIGURATION
2269 12:38:08.785782 ===================================
2270 12:38:08.785870 EX_ROW_EN[0] = 0x0
2271 12:38:08.789024 EX_ROW_EN[1] = 0x0
2272 12:38:08.789106 LP4Y_EN = 0x0
2273 12:38:08.792311 WORK_FSP = 0x0
2274 12:38:08.792393 WL = 0x4
2275 12:38:08.795349 RL = 0x4
2276 12:38:08.795455 BL = 0x2
2277 12:38:08.798811 RPST = 0x0
2278 12:38:08.798893 RD_PRE = 0x0
2279 12:38:08.801923 WR_PRE = 0x1
2280 12:38:08.802004 WR_PST = 0x0
2281 12:38:08.805460 DBI_WR = 0x0
2282 12:38:08.808360 DBI_RD = 0x0
2283 12:38:08.808442 OTF = 0x1
2284 12:38:08.812231 ===================================
2285 12:38:08.816007 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2286 12:38:08.818847 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2287 12:38:08.825318 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2288 12:38:08.829490 ===================================
2289 12:38:08.832413 LPDDR4 DRAM CONFIGURATION
2290 12:38:08.834986 ===================================
2291 12:38:08.835095 EX_ROW_EN[0] = 0x10
2292 12:38:08.838854 EX_ROW_EN[1] = 0x0
2293 12:38:08.838937 LP4Y_EN = 0x0
2294 12:38:08.842314 WORK_FSP = 0x0
2295 12:38:08.842398 WL = 0x4
2296 12:38:08.844923 RL = 0x4
2297 12:38:08.845005 BL = 0x2
2298 12:38:08.848200 RPST = 0x0
2299 12:38:08.848282 RD_PRE = 0x0
2300 12:38:08.851822 WR_PRE = 0x1
2301 12:38:08.851904 WR_PST = 0x0
2302 12:38:08.855030 DBI_WR = 0x0
2303 12:38:08.858221 DBI_RD = 0x0
2304 12:38:08.858304 OTF = 0x1
2305 12:38:08.861204 ===================================
2306 12:38:08.867824 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2307 12:38:08.867908 ==
2308 12:38:08.871310 Dram Type= 6, Freq= 0, CH_0, rank 0
2309 12:38:08.874494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2310 12:38:08.874577 ==
2311 12:38:08.877758 [Duty_Offset_Calibration]
2312 12:38:08.877862 B0:2 B1:0 CA:4
2313 12:38:08.881118
2314 12:38:08.884135 [DutyScan_Calibration_Flow] k_type=0
2315 12:38:08.891663
2316 12:38:08.891751 ==CLK 0==
2317 12:38:08.895055 Final CLK duty delay cell = -4
2318 12:38:08.898241 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2319 12:38:08.901298 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2320 12:38:08.904505 [-4] AVG Duty = 4937%(X100)
2321 12:38:08.904618
2322 12:38:08.908492 CH0 CLK Duty spec in!! Max-Min= 187%
2323 12:38:08.911513 [DutyScan_Calibration_Flow] ====Done====
2324 12:38:08.911606
2325 12:38:08.914279 [DutyScan_Calibration_Flow] k_type=1
2326 12:38:08.930930
2327 12:38:08.931039 ==DQS 0 ==
2328 12:38:08.934230 Final DQS duty delay cell = 0
2329 12:38:08.937588 [0] MAX Duty = 5156%(X100), DQS PI = 14
2330 12:38:08.941540 [0] MIN Duty = 5093%(X100), DQS PI = 2
2331 12:38:08.945204 [0] AVG Duty = 5124%(X100)
2332 12:38:08.945287
2333 12:38:08.945351 ==DQS 1 ==
2334 12:38:08.948008 Final DQS duty delay cell = 0
2335 12:38:08.951215 [0] MAX Duty = 5125%(X100), DQS PI = 4
2336 12:38:08.954107 [0] MIN Duty = 5000%(X100), DQS PI = 0
2337 12:38:08.954215 [0] AVG Duty = 5062%(X100)
2338 12:38:08.957740
2339 12:38:08.960955 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2340 12:38:08.961036
2341 12:38:08.964381 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2342 12:38:08.967730 [DutyScan_Calibration_Flow] ====Done====
2343 12:38:08.967812
2344 12:38:08.970987 [DutyScan_Calibration_Flow] k_type=3
2345 12:38:08.987620
2346 12:38:08.987736 ==DQM 0 ==
2347 12:38:08.990694 Final DQM duty delay cell = 0
2348 12:38:08.994332 [0] MAX Duty = 5125%(X100), DQS PI = 20
2349 12:38:08.997389 [0] MIN Duty = 4844%(X100), DQS PI = 52
2350 12:38:09.000355 [0] AVG Duty = 4984%(X100)
2351 12:38:09.000444
2352 12:38:09.000517 ==DQM 1 ==
2353 12:38:09.003863 Final DQM duty delay cell = 0
2354 12:38:09.006979 [0] MAX Duty = 4969%(X100), DQS PI = 2
2355 12:38:09.010344 [0] MIN Duty = 4875%(X100), DQS PI = 18
2356 12:38:09.013598 [0] AVG Duty = 4922%(X100)
2357 12:38:09.013698
2358 12:38:09.016988 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2359 12:38:09.017094
2360 12:38:09.020697 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2361 12:38:09.024079 [DutyScan_Calibration_Flow] ====Done====
2362 12:38:09.024165
2363 12:38:09.026928 [DutyScan_Calibration_Flow] k_type=2
2364 12:38:09.043635
2365 12:38:09.043757 ==DQ 0 ==
2366 12:38:09.047048 Final DQ duty delay cell = 0
2367 12:38:09.050209 [0] MAX Duty = 5156%(X100), DQS PI = 18
2368 12:38:09.053569 [0] MIN Duty = 5000%(X100), DQS PI = 10
2369 12:38:09.053641 [0] AVG Duty = 5078%(X100)
2370 12:38:09.056989
2371 12:38:09.057071 ==DQ 1 ==
2372 12:38:09.060345 Final DQ duty delay cell = 0
2373 12:38:09.063703 [0] MAX Duty = 5125%(X100), DQS PI = 4
2374 12:38:09.066708 [0] MIN Duty = 4938%(X100), DQS PI = 16
2375 12:38:09.066791 [0] AVG Duty = 5031%(X100)
2376 12:38:09.066855
2377 12:38:09.070300 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2378 12:38:09.074043
2379 12:38:09.077524 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2380 12:38:09.080338 [DutyScan_Calibration_Flow] ====Done====
2381 12:38:09.080427 ==
2382 12:38:09.083999 Dram Type= 6, Freq= 0, CH_1, rank 0
2383 12:38:09.086658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2384 12:38:09.086768 ==
2385 12:38:09.090348 [Duty_Offset_Calibration]
2386 12:38:09.090457 B0:0 B1:-1 CA:3
2387 12:38:09.090551
2388 12:38:09.093637 [DutyScan_Calibration_Flow] k_type=0
2389 12:38:09.102867
2390 12:38:09.102978 ==CLK 0==
2391 12:38:09.106138 Final CLK duty delay cell = -4
2392 12:38:09.110270 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2393 12:38:09.113145 [-4] MIN Duty = 4876%(X100), DQS PI = 52
2394 12:38:09.116802 [-4] AVG Duty = 4938%(X100)
2395 12:38:09.116908
2396 12:38:09.119742 CH1 CLK Duty spec in!! Max-Min= 124%
2397 12:38:09.122995 [DutyScan_Calibration_Flow] ====Done====
2398 12:38:09.123100
2399 12:38:09.127261 [DutyScan_Calibration_Flow] k_type=1
2400 12:38:09.141955
2401 12:38:09.142080 ==DQS 0 ==
2402 12:38:09.144827 Final DQS duty delay cell = 0
2403 12:38:09.149082 [0] MAX Duty = 5187%(X100), DQS PI = 18
2404 12:38:09.151754 [0] MIN Duty = 4907%(X100), DQS PI = 38
2405 12:38:09.154960 [0] AVG Duty = 5047%(X100)
2406 12:38:09.155066
2407 12:38:09.155160 ==DQS 1 ==
2408 12:38:09.158818 Final DQS duty delay cell = -4
2409 12:38:09.161329 [-4] MAX Duty = 5000%(X100), DQS PI = 10
2410 12:38:09.165390 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2411 12:38:09.168467 [-4] AVG Duty = 4937%(X100)
2412 12:38:09.168573
2413 12:38:09.171537 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2414 12:38:09.171644
2415 12:38:09.174777 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2416 12:38:09.178294 [DutyScan_Calibration_Flow] ====Done====
2417 12:38:09.178453
2418 12:38:09.181436 [DutyScan_Calibration_Flow] k_type=3
2419 12:38:09.198306
2420 12:38:09.198417 ==DQM 0 ==
2421 12:38:09.201964 Final DQM duty delay cell = 0
2422 12:38:09.204871 [0] MAX Duty = 5031%(X100), DQS PI = 28
2423 12:38:09.208201 [0] MIN Duty = 4813%(X100), DQS PI = 38
2424 12:38:09.211827 [0] AVG Duty = 4922%(X100)
2425 12:38:09.211935
2426 12:38:09.212026 ==DQM 1 ==
2427 12:38:09.215164 Final DQM duty delay cell = 0
2428 12:38:09.218437 [0] MAX Duty = 5000%(X100), DQS PI = 36
2429 12:38:09.221589 [0] MIN Duty = 4844%(X100), DQS PI = 0
2430 12:38:09.225563 [0] AVG Duty = 4922%(X100)
2431 12:38:09.225669
2432 12:38:09.228055 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2433 12:38:09.228159
2434 12:38:09.231502 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2435 12:38:09.235068 [DutyScan_Calibration_Flow] ====Done====
2436 12:38:09.235176
2437 12:38:09.238006 [DutyScan_Calibration_Flow] k_type=2
2438 12:38:09.254449
2439 12:38:09.254575 ==DQ 0 ==
2440 12:38:09.257371 Final DQ duty delay cell = -4
2441 12:38:09.260769 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2442 12:38:09.264115 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2443 12:38:09.267514 [-4] AVG Duty = 4937%(X100)
2444 12:38:09.267618
2445 12:38:09.267708 ==DQ 1 ==
2446 12:38:09.270884 Final DQ duty delay cell = 0
2447 12:38:09.274147 [0] MAX Duty = 5031%(X100), DQS PI = 34
2448 12:38:09.277474 [0] MIN Duty = 4844%(X100), DQS PI = 62
2449 12:38:09.280799 [0] AVG Duty = 4937%(X100)
2450 12:38:09.280906
2451 12:38:09.283859 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2452 12:38:09.283963
2453 12:38:09.287326 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2454 12:38:09.290498 [DutyScan_Calibration_Flow] ====Done====
2455 12:38:09.293893 nWR fixed to 30
2456 12:38:09.297239 [ModeRegInit_LP4] CH0 RK0
2457 12:38:09.297341 [ModeRegInit_LP4] CH0 RK1
2458 12:38:09.300489 [ModeRegInit_LP4] CH1 RK0
2459 12:38:09.303675 [ModeRegInit_LP4] CH1 RK1
2460 12:38:09.303779 match AC timing 7
2461 12:38:09.310712 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2462 12:38:09.313858 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2463 12:38:09.316963 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2464 12:38:09.324092 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2465 12:38:09.327059 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2466 12:38:09.327169 ==
2467 12:38:09.330224 Dram Type= 6, Freq= 0, CH_0, rank 0
2468 12:38:09.333994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2469 12:38:09.334101 ==
2470 12:38:09.340359 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2471 12:38:09.346955 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2472 12:38:09.354247 [CA 0] Center 39 (9~70) winsize 62
2473 12:38:09.357834 [CA 1] Center 38 (8~69) winsize 62
2474 12:38:09.360889 [CA 2] Center 35 (5~66) winsize 62
2475 12:38:09.365071 [CA 3] Center 35 (5~66) winsize 62
2476 12:38:09.368112 [CA 4] Center 33 (3~64) winsize 62
2477 12:38:09.370753 [CA 5] Center 33 (3~64) winsize 62
2478 12:38:09.370858
2479 12:38:09.374431 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2480 12:38:09.374517
2481 12:38:09.377379 [CATrainingPosCal] consider 1 rank data
2482 12:38:09.380681 u2DelayCellTimex100 = 270/100 ps
2483 12:38:09.384210 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2484 12:38:09.387901 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2485 12:38:09.394557 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2486 12:38:09.397398 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2487 12:38:09.401109 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2488 12:38:09.404590 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2489 12:38:09.404699
2490 12:38:09.408187 CA PerBit enable=1, Macro0, CA PI delay=33
2491 12:38:09.408294
2492 12:38:09.410834 [CBTSetCACLKResult] CA Dly = 33
2493 12:38:09.410939 CS Dly: 7 (0~38)
2494 12:38:09.413942 ==
2495 12:38:09.417784 Dram Type= 6, Freq= 0, CH_0, rank 1
2496 12:38:09.420707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2497 12:38:09.420813 ==
2498 12:38:09.428103 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2499 12:38:09.430679 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2500 12:38:09.440558 [CA 0] Center 39 (9~70) winsize 62
2501 12:38:09.443816 [CA 1] Center 39 (9~70) winsize 62
2502 12:38:09.446849 [CA 2] Center 35 (5~66) winsize 62
2503 12:38:09.450687 [CA 3] Center 35 (5~66) winsize 62
2504 12:38:09.453675 [CA 4] Center 34 (4~65) winsize 62
2505 12:38:09.457064 [CA 5] Center 33 (3~64) winsize 62
2506 12:38:09.457172
2507 12:38:09.459898 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2508 12:38:09.460006
2509 12:38:09.463378 [CATrainingPosCal] consider 2 rank data
2510 12:38:09.466495 u2DelayCellTimex100 = 270/100 ps
2511 12:38:09.469830 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2512 12:38:09.476731 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2513 12:38:09.479683 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2514 12:38:09.483552 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2515 12:38:09.486303 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2516 12:38:09.489682 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2517 12:38:09.489790
2518 12:38:09.492808 CA PerBit enable=1, Macro0, CA PI delay=33
2519 12:38:09.492914
2520 12:38:09.496337 [CBTSetCACLKResult] CA Dly = 33
2521 12:38:09.500045 CS Dly: 8 (0~41)
2522 12:38:09.500154
2523 12:38:09.503611 ----->DramcWriteLeveling(PI) begin...
2524 12:38:09.503721 ==
2525 12:38:09.506174 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 12:38:09.509523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 12:38:09.509631 ==
2528 12:38:09.513350 Write leveling (Byte 0): 33 => 33
2529 12:38:09.516560 Write leveling (Byte 1): 26 => 26
2530 12:38:09.519342 DramcWriteLeveling(PI) end<-----
2531 12:38:09.519465
2532 12:38:09.519531 ==
2533 12:38:09.522670 Dram Type= 6, Freq= 0, CH_0, rank 0
2534 12:38:09.526245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2535 12:38:09.526327 ==
2536 12:38:09.529981 [Gating] SW mode calibration
2537 12:38:09.536410 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2538 12:38:09.542763 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2539 12:38:09.546982 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2540 12:38:09.549376 0 15 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
2541 12:38:09.556186 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 12:38:09.559475 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 12:38:09.562866 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 12:38:09.569361 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 12:38:09.572616 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2546 12:38:09.575894 0 15 28 | B1->B0 | 3434 2626 | 1 1 | (1 1) (1 0)
2547 12:38:09.582329 1 0 0 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
2548 12:38:09.585611 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 12:38:09.589136 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 12:38:09.596138 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 12:38:09.599666 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 12:38:09.602490 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 12:38:09.609036 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2554 12:38:09.612295 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2555 12:38:09.615863 1 1 0 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
2556 12:38:09.623919 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 12:38:09.626404 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 12:38:09.628800 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 12:38:09.635231 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 12:38:09.638987 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 12:38:09.641764 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 12:38:09.648583 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2563 12:38:09.652643 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2564 12:38:09.655578 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 12:38:09.662321 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 12:38:09.665250 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 12:38:09.668578 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 12:38:09.671816 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 12:38:09.678354 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 12:38:09.681972 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 12:38:09.685319 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 12:38:09.691744 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 12:38:09.695350 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 12:38:09.698657 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 12:38:09.705208 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 12:38:09.708295 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 12:38:09.711674 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2578 12:38:09.718758 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2579 12:38:09.721763 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2580 12:38:09.725102 Total UI for P1: 0, mck2ui 16
2581 12:38:09.728576 best dqsien dly found for B0: ( 1, 3, 26)
2582 12:38:09.731462 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2583 12:38:09.738697 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2584 12:38:09.738805 Total UI for P1: 0, mck2ui 16
2585 12:38:09.745736 best dqsien dly found for B1: ( 1, 4, 4)
2586 12:38:09.748111 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2587 12:38:09.751353 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2588 12:38:09.751459
2589 12:38:09.754783 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2590 12:38:09.758304 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2591 12:38:09.761614 [Gating] SW calibration Done
2592 12:38:09.761716 ==
2593 12:38:09.764905 Dram Type= 6, Freq= 0, CH_0, rank 0
2594 12:38:09.768391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2595 12:38:09.768494 ==
2596 12:38:09.771936 RX Vref Scan: 0
2597 12:38:09.772041
2598 12:38:09.772134 RX Vref 0 -> 0, step: 1
2599 12:38:09.772223
2600 12:38:09.774585 RX Delay -40 -> 252, step: 8
2601 12:38:09.777879 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2602 12:38:09.784829 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2603 12:38:09.788091 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2604 12:38:09.791233 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2605 12:38:09.794908 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2606 12:38:09.797710 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2607 12:38:09.804506 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2608 12:38:09.807772 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2609 12:38:09.811670 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2610 12:38:09.814160 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2611 12:38:09.818012 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2612 12:38:09.824306 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2613 12:38:09.827544 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2614 12:38:09.831320 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2615 12:38:09.834160 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2616 12:38:09.841126 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2617 12:38:09.841224 ==
2618 12:38:09.844532 Dram Type= 6, Freq= 0, CH_0, rank 0
2619 12:38:09.847287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2620 12:38:09.847356 ==
2621 12:38:09.847431 DQS Delay:
2622 12:38:09.851459 DQS0 = 0, DQS1 = 0
2623 12:38:09.851540 DQM Delay:
2624 12:38:09.854555 DQM0 = 117, DQM1 = 107
2625 12:38:09.854636 DQ Delay:
2626 12:38:09.857569 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =111
2627 12:38:09.860874 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =127
2628 12:38:09.865068 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2629 12:38:09.867131 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2630 12:38:09.867212
2631 12:38:09.867275
2632 12:38:09.867334 ==
2633 12:38:09.870831 Dram Type= 6, Freq= 0, CH_0, rank 0
2634 12:38:09.877577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2635 12:38:09.877659 ==
2636 12:38:09.877723
2637 12:38:09.877782
2638 12:38:09.877839 TX Vref Scan disable
2639 12:38:09.881083 == TX Byte 0 ==
2640 12:38:09.884725 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2641 12:38:09.887745 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2642 12:38:09.891197 == TX Byte 1 ==
2643 12:38:09.894365 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2644 12:38:09.897747 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2645 12:38:09.901080 ==
2646 12:38:09.904712 Dram Type= 6, Freq= 0, CH_0, rank 0
2647 12:38:09.907569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2648 12:38:09.907676 ==
2649 12:38:09.919590 TX Vref=22, minBit 4, minWin=25, winSum=412
2650 12:38:09.922935 TX Vref=24, minBit 8, minWin=25, winSum=416
2651 12:38:09.926038 TX Vref=26, minBit 1, minWin=26, winSum=424
2652 12:38:09.929474 TX Vref=28, minBit 1, minWin=26, winSum=430
2653 12:38:09.932694 TX Vref=30, minBit 10, minWin=26, winSum=430
2654 12:38:09.939740 TX Vref=32, minBit 2, minWin=26, winSum=429
2655 12:38:09.942431 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 28
2656 12:38:09.942538
2657 12:38:09.945873 Final TX Range 1 Vref 28
2658 12:38:09.945979
2659 12:38:09.946071 ==
2660 12:38:09.949108 Dram Type= 6, Freq= 0, CH_0, rank 0
2661 12:38:09.952915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2662 12:38:09.953020 ==
2663 12:38:09.956382
2664 12:38:09.956486
2665 12:38:09.956578 TX Vref Scan disable
2666 12:38:09.959066 == TX Byte 0 ==
2667 12:38:09.962774 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2668 12:38:09.966101 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2669 12:38:09.969741 == TX Byte 1 ==
2670 12:38:09.972976 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2671 12:38:09.975718 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2672 12:38:09.979264
2673 12:38:09.979347 [DATLAT]
2674 12:38:09.979421 Freq=1200, CH0 RK0
2675 12:38:09.979497
2676 12:38:09.983222 DATLAT Default: 0xd
2677 12:38:09.983303 0, 0xFFFF, sum = 0
2678 12:38:09.985686 1, 0xFFFF, sum = 0
2679 12:38:09.985767 2, 0xFFFF, sum = 0
2680 12:38:09.988963 3, 0xFFFF, sum = 0
2681 12:38:09.992504 4, 0xFFFF, sum = 0
2682 12:38:09.992612 5, 0xFFFF, sum = 0
2683 12:38:09.995769 6, 0xFFFF, sum = 0
2684 12:38:09.995876 7, 0xFFFF, sum = 0
2685 12:38:09.999164 8, 0xFFFF, sum = 0
2686 12:38:09.999293 9, 0xFFFF, sum = 0
2687 12:38:10.002837 10, 0xFFFF, sum = 0
2688 12:38:10.002942 11, 0xFFFF, sum = 0
2689 12:38:10.005911 12, 0x0, sum = 1
2690 12:38:10.006017 13, 0x0, sum = 2
2691 12:38:10.009018 14, 0x0, sum = 3
2692 12:38:10.009105 15, 0x0, sum = 4
2693 12:38:10.013372 best_step = 13
2694 12:38:10.013456
2695 12:38:10.013541 ==
2696 12:38:10.016110 Dram Type= 6, Freq= 0, CH_0, rank 0
2697 12:38:10.019301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2698 12:38:10.019423 ==
2699 12:38:10.019510 RX Vref Scan: 1
2700 12:38:10.019592
2701 12:38:10.022760 Set Vref Range= 32 -> 127
2702 12:38:10.022845
2703 12:38:10.026132 RX Vref 32 -> 127, step: 1
2704 12:38:10.026233
2705 12:38:10.029676 RX Delay -21 -> 252, step: 4
2706 12:38:10.029761
2707 12:38:10.032589 Set Vref, RX VrefLevel [Byte0]: 32
2708 12:38:10.036001 [Byte1]: 32
2709 12:38:10.036086
2710 12:38:10.039053 Set Vref, RX VrefLevel [Byte0]: 33
2711 12:38:10.042259 [Byte1]: 33
2712 12:38:10.045519
2713 12:38:10.049082 Set Vref, RX VrefLevel [Byte0]: 34
2714 12:38:10.052484 [Byte1]: 34
2715 12:38:10.052572
2716 12:38:10.055554 Set Vref, RX VrefLevel [Byte0]: 35
2717 12:38:10.059070 [Byte1]: 35
2718 12:38:10.059155
2719 12:38:10.061983 Set Vref, RX VrefLevel [Byte0]: 36
2720 12:38:10.065322 [Byte1]: 36
2721 12:38:10.069617
2722 12:38:10.069700 Set Vref, RX VrefLevel [Byte0]: 37
2723 12:38:10.072876 [Byte1]: 37
2724 12:38:10.077269
2725 12:38:10.077353 Set Vref, RX VrefLevel [Byte0]: 38
2726 12:38:10.081154 [Byte1]: 38
2727 12:38:10.085549
2728 12:38:10.085633 Set Vref, RX VrefLevel [Byte0]: 39
2729 12:38:10.088425 [Byte1]: 39
2730 12:38:10.093267
2731 12:38:10.093351 Set Vref, RX VrefLevel [Byte0]: 40
2732 12:38:10.096582 [Byte1]: 40
2733 12:38:10.101609
2734 12:38:10.101693 Set Vref, RX VrefLevel [Byte0]: 41
2735 12:38:10.104646 [Byte1]: 41
2736 12:38:10.109664
2737 12:38:10.109748 Set Vref, RX VrefLevel [Byte0]: 42
2738 12:38:10.112402 [Byte1]: 42
2739 12:38:10.117613
2740 12:38:10.117697 Set Vref, RX VrefLevel [Byte0]: 43
2741 12:38:10.120402 [Byte1]: 43
2742 12:38:10.124801
2743 12:38:10.124884 Set Vref, RX VrefLevel [Byte0]: 44
2744 12:38:10.129001 [Byte1]: 44
2745 12:38:10.133195
2746 12:38:10.133316 Set Vref, RX VrefLevel [Byte0]: 45
2747 12:38:10.136201 [Byte1]: 45
2748 12:38:10.141082
2749 12:38:10.141211 Set Vref, RX VrefLevel [Byte0]: 46
2750 12:38:10.144184 [Byte1]: 46
2751 12:38:10.148611
2752 12:38:10.148692 Set Vref, RX VrefLevel [Byte0]: 47
2753 12:38:10.151906 [Byte1]: 47
2754 12:38:10.156802
2755 12:38:10.156881 Set Vref, RX VrefLevel [Byte0]: 48
2756 12:38:10.160209 [Byte1]: 48
2757 12:38:10.164379
2758 12:38:10.164458 Set Vref, RX VrefLevel [Byte0]: 49
2759 12:38:10.167977 [Byte1]: 49
2760 12:38:10.172603
2761 12:38:10.172722 Set Vref, RX VrefLevel [Byte0]: 50
2762 12:38:10.176053 [Byte1]: 50
2763 12:38:10.180359
2764 12:38:10.180440 Set Vref, RX VrefLevel [Byte0]: 51
2765 12:38:10.184198 [Byte1]: 51
2766 12:38:10.188517
2767 12:38:10.188596 Set Vref, RX VrefLevel [Byte0]: 52
2768 12:38:10.191934 [Byte1]: 52
2769 12:38:10.196471
2770 12:38:10.196551 Set Vref, RX VrefLevel [Byte0]: 53
2771 12:38:10.200134 [Byte1]: 53
2772 12:38:10.204059
2773 12:38:10.204138 Set Vref, RX VrefLevel [Byte0]: 54
2774 12:38:10.207511 [Byte1]: 54
2775 12:38:10.212166
2776 12:38:10.212245 Set Vref, RX VrefLevel [Byte0]: 55
2777 12:38:10.215441 [Byte1]: 55
2778 12:38:10.219968
2779 12:38:10.220048 Set Vref, RX VrefLevel [Byte0]: 56
2780 12:38:10.223584 [Byte1]: 56
2781 12:38:10.227769
2782 12:38:10.227849 Set Vref, RX VrefLevel [Byte0]: 57
2783 12:38:10.231545 [Byte1]: 57
2784 12:38:10.236025
2785 12:38:10.236131 Set Vref, RX VrefLevel [Byte0]: 58
2786 12:38:10.239345 [Byte1]: 58
2787 12:38:10.243942
2788 12:38:10.244022 Set Vref, RX VrefLevel [Byte0]: 59
2789 12:38:10.247100 [Byte1]: 59
2790 12:38:10.251689
2791 12:38:10.251770 Set Vref, RX VrefLevel [Byte0]: 60
2792 12:38:10.255202 [Byte1]: 60
2793 12:38:10.259558
2794 12:38:10.259638 Set Vref, RX VrefLevel [Byte0]: 61
2795 12:38:10.262922 [Byte1]: 61
2796 12:38:10.267358
2797 12:38:10.267474 Set Vref, RX VrefLevel [Byte0]: 62
2798 12:38:10.271102 [Byte1]: 62
2799 12:38:10.275595
2800 12:38:10.275674 Set Vref, RX VrefLevel [Byte0]: 63
2801 12:38:10.278890 [Byte1]: 63
2802 12:38:10.283500
2803 12:38:10.283580 Set Vref, RX VrefLevel [Byte0]: 64
2804 12:38:10.286538 [Byte1]: 64
2805 12:38:10.291414
2806 12:38:10.291494 Set Vref, RX VrefLevel [Byte0]: 65
2807 12:38:10.294745 [Byte1]: 65
2808 12:38:10.299560
2809 12:38:10.299646 Set Vref, RX VrefLevel [Byte0]: 66
2810 12:38:10.302557 [Byte1]: 66
2811 12:38:10.307632
2812 12:38:10.307711 Set Vref, RX VrefLevel [Byte0]: 67
2813 12:38:10.310395 [Byte1]: 67
2814 12:38:10.315620
2815 12:38:10.315699 Set Vref, RX VrefLevel [Byte0]: 68
2816 12:38:10.318736 [Byte1]: 68
2817 12:38:10.323084
2818 12:38:10.323163 Set Vref, RX VrefLevel [Byte0]: 69
2819 12:38:10.326614 [Byte1]: 69
2820 12:38:10.331597
2821 12:38:10.331693 Final RX Vref Byte 0 = 54 to rank0
2822 12:38:10.334530 Final RX Vref Byte 1 = 59 to rank0
2823 12:38:10.337747 Final RX Vref Byte 0 = 54 to rank1
2824 12:38:10.341143 Final RX Vref Byte 1 = 59 to rank1==
2825 12:38:10.344889 Dram Type= 6, Freq= 0, CH_0, rank 0
2826 12:38:10.351291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2827 12:38:10.351434 ==
2828 12:38:10.351527 DQS Delay:
2829 12:38:10.351614 DQS0 = 0, DQS1 = 0
2830 12:38:10.354258 DQM Delay:
2831 12:38:10.354337 DQM0 = 117, DQM1 = 105
2832 12:38:10.357885 DQ Delay:
2833 12:38:10.360796 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2834 12:38:10.364369 DQ4 =120, DQ5 =110, DQ6 =124, DQ7 =122
2835 12:38:10.367597 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2836 12:38:10.371019 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =112
2837 12:38:10.371099
2838 12:38:10.371162
2839 12:38:10.377580 [DQSOSCAuto] RK0, (LSB)MR18= 0x601, (MSB)MR19= 0x404, tDQSOscB0 = 409 ps tDQSOscB1 = 407 ps
2840 12:38:10.381290 CH0 RK0: MR19=404, MR18=601
2841 12:38:10.387330 CH0_RK0: MR19=0x404, MR18=0x601, DQSOSC=407, MR23=63, INC=39, DEC=26
2842 12:38:10.387457
2843 12:38:10.390817 ----->DramcWriteLeveling(PI) begin...
2844 12:38:10.390898 ==
2845 12:38:10.393777 Dram Type= 6, Freq= 0, CH_0, rank 1
2846 12:38:10.398608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2847 12:38:10.400525 ==
2848 12:38:10.400606 Write leveling (Byte 0): 33 => 33
2849 12:38:10.404406 Write leveling (Byte 1): 25 => 25
2850 12:38:10.407493 DramcWriteLeveling(PI) end<-----
2851 12:38:10.407587
2852 12:38:10.407650 ==
2853 12:38:10.410587 Dram Type= 6, Freq= 0, CH_0, rank 1
2854 12:38:10.417530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2855 12:38:10.417610 ==
2856 12:38:10.420729 [Gating] SW mode calibration
2857 12:38:10.427585 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2858 12:38:10.430812 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2859 12:38:10.437214 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2860 12:38:10.440851 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 12:38:10.443768 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 12:38:10.450513 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 12:38:10.453589 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 12:38:10.457160 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 12:38:10.463447 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2866 12:38:10.466663 0 15 28 | B1->B0 | 3434 2828 | 1 1 | (1 1) (1 0)
2867 12:38:10.470791 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
2868 12:38:10.477005 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 12:38:10.480112 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 12:38:10.483067 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 12:38:10.490221 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 12:38:10.493178 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 12:38:10.496812 1 0 24 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
2874 12:38:10.503556 1 0 28 | B1->B0 | 2d2d 4646 | 0 0 | (1 1) (0 0)
2875 12:38:10.506575 1 1 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2876 12:38:10.510560 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 12:38:10.516277 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 12:38:10.519611 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 12:38:10.523328 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 12:38:10.529609 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 12:38:10.533169 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2882 12:38:10.536165 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2883 12:38:10.539666 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 12:38:10.546435 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 12:38:10.549603 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 12:38:10.553181 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 12:38:10.559327 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 12:38:10.562802 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 12:38:10.566099 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 12:38:10.573210 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 12:38:10.576533 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 12:38:10.579909 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 12:38:10.586199 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 12:38:10.589416 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 12:38:10.592791 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 12:38:10.599286 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 12:38:10.602810 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2898 12:38:10.606160 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2899 12:38:10.612750 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2900 12:38:10.612831 Total UI for P1: 0, mck2ui 16
2901 12:38:10.619669 best dqsien dly found for B0: ( 1, 3, 26)
2902 12:38:10.619749 Total UI for P1: 0, mck2ui 16
2903 12:38:10.626116 best dqsien dly found for B1: ( 1, 3, 30)
2904 12:38:10.629820 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2905 12:38:10.632276 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2906 12:38:10.632357
2907 12:38:10.635988 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2908 12:38:10.639300 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2909 12:38:10.642644 [Gating] SW calibration Done
2910 12:38:10.642724 ==
2911 12:38:10.646347 Dram Type= 6, Freq= 0, CH_0, rank 1
2912 12:38:10.649336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2913 12:38:10.649417 ==
2914 12:38:10.652586 RX Vref Scan: 0
2915 12:38:10.652665
2916 12:38:10.652729 RX Vref 0 -> 0, step: 1
2917 12:38:10.652788
2918 12:38:10.655991 RX Delay -40 -> 252, step: 8
2919 12:38:10.659315 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2920 12:38:10.665858 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2921 12:38:10.669000 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2922 12:38:10.672183 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2923 12:38:10.676182 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2924 12:38:10.679249 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2925 12:38:10.686362 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2926 12:38:10.688962 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2927 12:38:10.692390 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2928 12:38:10.695554 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2929 12:38:10.698695 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2930 12:38:10.705884 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2931 12:38:10.709151 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2932 12:38:10.712783 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2933 12:38:10.715705 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2934 12:38:10.718637 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2935 12:38:10.722166 ==
2936 12:38:10.722247 Dram Type= 6, Freq= 0, CH_0, rank 1
2937 12:38:10.729100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2938 12:38:10.729181 ==
2939 12:38:10.729245 DQS Delay:
2940 12:38:10.732060 DQS0 = 0, DQS1 = 0
2941 12:38:10.732140 DQM Delay:
2942 12:38:10.735548 DQM0 = 116, DQM1 = 109
2943 12:38:10.735628 DQ Delay:
2944 12:38:10.738400 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2945 12:38:10.742385 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
2946 12:38:10.745330 DQ8 =99, DQ9 =91, DQ10 =111, DQ11 =103
2947 12:38:10.748743 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =115
2948 12:38:10.748824
2949 12:38:10.748887
2950 12:38:10.748945 ==
2951 12:38:10.752087 Dram Type= 6, Freq= 0, CH_0, rank 1
2952 12:38:10.758294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2953 12:38:10.758375 ==
2954 12:38:10.758439
2955 12:38:10.758497
2956 12:38:10.758554 TX Vref Scan disable
2957 12:38:10.761947 == TX Byte 0 ==
2958 12:38:10.765296 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2959 12:38:10.771926 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2960 12:38:10.772008 == TX Byte 1 ==
2961 12:38:10.774999 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2962 12:38:10.782333 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2963 12:38:10.782415 ==
2964 12:38:10.785377 Dram Type= 6, Freq= 0, CH_0, rank 1
2965 12:38:10.788470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2966 12:38:10.788551 ==
2967 12:38:10.800429 TX Vref=22, minBit 8, minWin=25, winSum=419
2968 12:38:10.804434 TX Vref=24, minBit 13, minWin=25, winSum=421
2969 12:38:10.807344 TX Vref=26, minBit 0, minWin=26, winSum=424
2970 12:38:10.810695 TX Vref=28, minBit 8, minWin=26, winSum=428
2971 12:38:10.813902 TX Vref=30, minBit 10, minWin=26, winSum=429
2972 12:38:10.820261 TX Vref=32, minBit 5, minWin=26, winSum=432
2973 12:38:10.823857 [TxChooseVref] Worse bit 5, Min win 26, Win sum 432, Final Vref 32
2974 12:38:10.823938
2975 12:38:10.826971 Final TX Range 1 Vref 32
2976 12:38:10.827052
2977 12:38:10.827116 ==
2978 12:38:10.830123 Dram Type= 6, Freq= 0, CH_0, rank 1
2979 12:38:10.833675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2980 12:38:10.833782 ==
2981 12:38:10.836803
2982 12:38:10.836882
2983 12:38:10.836945 TX Vref Scan disable
2984 12:38:10.840646 == TX Byte 0 ==
2985 12:38:10.844122 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2986 12:38:10.850609 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2987 12:38:10.850692 == TX Byte 1 ==
2988 12:38:10.853543 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2989 12:38:10.857969 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2990 12:38:10.860293
2991 12:38:10.860370 [DATLAT]
2992 12:38:10.860432 Freq=1200, CH0 RK1
2993 12:38:10.860492
2994 12:38:10.864339 DATLAT Default: 0xd
2995 12:38:10.864414 0, 0xFFFF, sum = 0
2996 12:38:10.866894 1, 0xFFFF, sum = 0
2997 12:38:10.867008 2, 0xFFFF, sum = 0
2998 12:38:10.870246 3, 0xFFFF, sum = 0
2999 12:38:10.873781 4, 0xFFFF, sum = 0
3000 12:38:10.873858 5, 0xFFFF, sum = 0
3001 12:38:10.877008 6, 0xFFFF, sum = 0
3002 12:38:10.877079 7, 0xFFFF, sum = 0
3003 12:38:10.880306 8, 0xFFFF, sum = 0
3004 12:38:10.880385 9, 0xFFFF, sum = 0
3005 12:38:10.883643 10, 0xFFFF, sum = 0
3006 12:38:10.883723 11, 0xFFFF, sum = 0
3007 12:38:10.887151 12, 0x0, sum = 1
3008 12:38:10.887223 13, 0x0, sum = 2
3009 12:38:10.890758 14, 0x0, sum = 3
3010 12:38:10.890840 15, 0x0, sum = 4
3011 12:38:10.893367 best_step = 13
3012 12:38:10.893447
3013 12:38:10.893510 ==
3014 12:38:10.896933 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 12:38:10.900493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 12:38:10.900574 ==
3017 12:38:10.900638 RX Vref Scan: 0
3018 12:38:10.900697
3019 12:38:10.903596 RX Vref 0 -> 0, step: 1
3020 12:38:10.903676
3021 12:38:10.906840 RX Delay -21 -> 252, step: 4
3022 12:38:10.910463 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3023 12:38:10.916546 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3024 12:38:10.919843 iDelay=195, Bit 2, Center 112 (47 ~ 178) 132
3025 12:38:10.923544 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3026 12:38:10.927198 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3027 12:38:10.930209 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3028 12:38:10.937249 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3029 12:38:10.940391 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3030 12:38:10.943323 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3031 12:38:10.946422 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3032 12:38:10.950039 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3033 12:38:10.956497 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3034 12:38:10.959720 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3035 12:38:10.962931 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3036 12:38:10.966522 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3037 12:38:10.972743 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3038 12:38:10.972851 ==
3039 12:38:10.976372 Dram Type= 6, Freq= 0, CH_0, rank 1
3040 12:38:10.979563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3041 12:38:10.979666 ==
3042 12:38:10.979766 DQS Delay:
3043 12:38:10.982855 DQS0 = 0, DQS1 = 0
3044 12:38:10.982968 DQM Delay:
3045 12:38:10.986578 DQM0 = 116, DQM1 = 106
3046 12:38:10.986685 DQ Delay:
3047 12:38:10.990083 DQ0 =114, DQ1 =116, DQ2 =112, DQ3 =112
3048 12:38:10.993076 DQ4 =118, DQ5 =110, DQ6 =126, DQ7 =122
3049 12:38:10.996304 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =102
3050 12:38:10.999664 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =112
3051 12:38:10.999770
3052 12:38:10.999869
3053 12:38:11.009631 [DQSOSCAuto] RK1, (LSB)MR18= 0xfc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
3054 12:38:11.012319 CH0 RK1: MR19=403, MR18=FC
3055 12:38:11.015787 CH0_RK1: MR19=0x403, MR18=0xFC, DQSOSC=410, MR23=63, INC=39, DEC=26
3056 12:38:11.019494 [RxdqsGatingPostProcess] freq 1200
3057 12:38:11.026074 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3058 12:38:11.029051 best DQS0 dly(2T, 0.5T) = (0, 11)
3059 12:38:11.032317 best DQS1 dly(2T, 0.5T) = (0, 12)
3060 12:38:11.035977 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3061 12:38:11.039103 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3062 12:38:11.042273 best DQS0 dly(2T, 0.5T) = (0, 11)
3063 12:38:11.046172 best DQS1 dly(2T, 0.5T) = (0, 11)
3064 12:38:11.049218 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3065 12:38:11.052336 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3066 12:38:11.052444 Pre-setting of DQS Precalculation
3067 12:38:11.059040 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3068 12:38:11.059151 ==
3069 12:38:11.062669 Dram Type= 6, Freq= 0, CH_1, rank 0
3070 12:38:11.065683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 12:38:11.065795 ==
3072 12:38:11.072185 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3073 12:38:11.078659 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3074 12:38:11.086662 [CA 0] Center 38 (8~68) winsize 61
3075 12:38:11.089677 [CA 1] Center 37 (7~68) winsize 62
3076 12:38:11.092858 [CA 2] Center 35 (5~65) winsize 61
3077 12:38:11.096732 [CA 3] Center 34 (4~64) winsize 61
3078 12:38:11.100221 [CA 4] Center 35 (5~65) winsize 61
3079 12:38:11.102900 [CA 5] Center 33 (3~64) winsize 62
3080 12:38:11.102982
3081 12:38:11.106448 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3082 12:38:11.106535
3083 12:38:11.109434 [CATrainingPosCal] consider 1 rank data
3084 12:38:11.113089 u2DelayCellTimex100 = 270/100 ps
3085 12:38:11.116463 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3086 12:38:11.123340 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3087 12:38:11.126999 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3088 12:38:11.129548 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3089 12:38:11.132918 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3090 12:38:11.136034 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3091 12:38:11.136115
3092 12:38:11.139105 CA PerBit enable=1, Macro0, CA PI delay=33
3093 12:38:11.139220
3094 12:38:11.142960 [CBTSetCACLKResult] CA Dly = 33
3095 12:38:11.143073 CS Dly: 5 (0~36)
3096 12:38:11.145929 ==
3097 12:38:11.149189 Dram Type= 6, Freq= 0, CH_1, rank 1
3098 12:38:11.152737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3099 12:38:11.152845 ==
3100 12:38:11.155840 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3101 12:38:11.162503 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3102 12:38:11.172110 [CA 0] Center 37 (7~68) winsize 62
3103 12:38:11.175541 [CA 1] Center 38 (8~69) winsize 62
3104 12:38:11.178290 [CA 2] Center 35 (5~65) winsize 61
3105 12:38:11.181719 [CA 3] Center 33 (3~64) winsize 62
3106 12:38:11.185271 [CA 4] Center 34 (4~64) winsize 61
3107 12:38:11.188822 [CA 5] Center 33 (3~63) winsize 61
3108 12:38:11.188933
3109 12:38:11.191601 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3110 12:38:11.191725
3111 12:38:11.195017 [CATrainingPosCal] consider 2 rank data
3112 12:38:11.198543 u2DelayCellTimex100 = 270/100 ps
3113 12:38:11.202435 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3114 12:38:11.208341 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3115 12:38:11.212052 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3116 12:38:11.215161 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3117 12:38:11.218575 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3118 12:38:11.221571 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3119 12:38:11.221683
3120 12:38:11.225803 CA PerBit enable=1, Macro0, CA PI delay=33
3121 12:38:11.225914
3122 12:38:11.228511 [CBTSetCACLKResult] CA Dly = 33
3123 12:38:11.228626 CS Dly: 6 (0~39)
3124 12:38:11.228720
3125 12:38:11.232351 ----->DramcWriteLeveling(PI) begin...
3126 12:38:11.235312 ==
3127 12:38:11.238124 Dram Type= 6, Freq= 0, CH_1, rank 0
3128 12:38:11.241834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3129 12:38:11.241947 ==
3130 12:38:11.244925 Write leveling (Byte 0): 25 => 25
3131 12:38:11.248466 Write leveling (Byte 1): 27 => 27
3132 12:38:11.251961 DramcWriteLeveling(PI) end<-----
3133 12:38:11.252076
3134 12:38:11.252168 ==
3135 12:38:11.255209 Dram Type= 6, Freq= 0, CH_1, rank 0
3136 12:38:11.258258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3137 12:38:11.258370 ==
3138 12:38:11.261801 [Gating] SW mode calibration
3139 12:38:11.268307 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3140 12:38:11.275237 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3141 12:38:11.278213 0 15 0 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
3142 12:38:11.281533 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 12:38:11.288230 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 12:38:11.292251 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 12:38:11.294682 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 12:38:11.298223 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 12:38:11.305181 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3148 12:38:11.307946 0 15 28 | B1->B0 | 2929 2323 | 1 1 | (1 0) (1 0)
3149 12:38:11.311326 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 12:38:11.318512 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 12:38:11.321710 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 12:38:11.324584 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 12:38:11.331586 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 12:38:11.334648 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 12:38:11.338602 1 0 24 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (1 1)
3156 12:38:11.344620 1 0 28 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
3157 12:38:11.347865 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 12:38:11.351200 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 12:38:11.358058 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 12:38:11.361284 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 12:38:11.364366 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 12:38:11.371497 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 12:38:11.374769 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 12:38:11.377592 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3165 12:38:11.384312 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 12:38:11.387504 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 12:38:11.391478 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 12:38:11.397791 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 12:38:11.401052 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 12:38:11.404255 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 12:38:11.411715 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 12:38:11.415134 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 12:38:11.417882 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 12:38:11.424506 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 12:38:11.427872 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 12:38:11.431490 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 12:38:11.437350 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 12:38:11.440756 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 12:38:11.444480 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 12:38:11.450801 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3181 12:38:11.450897 Total UI for P1: 0, mck2ui 16
3182 12:38:11.454192 best dqsien dly found for B0: ( 1, 3, 26)
3183 12:38:11.460827 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 12:38:11.464507 Total UI for P1: 0, mck2ui 16
3185 12:38:11.467698 best dqsien dly found for B1: ( 1, 3, 28)
3186 12:38:11.470836 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3187 12:38:11.473964 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3188 12:38:11.474050
3189 12:38:11.477211 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3190 12:38:11.480782 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3191 12:38:11.484264 [Gating] SW calibration Done
3192 12:38:11.484355 ==
3193 12:38:11.487309 Dram Type= 6, Freq= 0, CH_1, rank 0
3194 12:38:11.491349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3195 12:38:11.491478 ==
3196 12:38:11.494467 RX Vref Scan: 0
3197 12:38:11.494551
3198 12:38:11.497217 RX Vref 0 -> 0, step: 1
3199 12:38:11.497300
3200 12:38:11.497365 RX Delay -40 -> 252, step: 8
3201 12:38:11.508219 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3202 12:38:11.508332 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3203 12:38:11.510308 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3204 12:38:11.514449 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3205 12:38:11.517022 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3206 12:38:11.523892 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3207 12:38:11.528175 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3208 12:38:11.532252 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3209 12:38:11.533627 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3210 12:38:11.537034 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3211 12:38:11.543489 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3212 12:38:11.546888 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3213 12:38:11.550931 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3214 12:38:11.554105 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3215 12:38:11.557441 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3216 12:38:11.563878 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3217 12:38:11.563981 ==
3218 12:38:11.567012 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 12:38:11.570549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 12:38:11.570639 ==
3221 12:38:11.570705 DQS Delay:
3222 12:38:11.573795 DQS0 = 0, DQS1 = 0
3223 12:38:11.573879 DQM Delay:
3224 12:38:11.577222 DQM0 = 115, DQM1 = 113
3225 12:38:11.577307 DQ Delay:
3226 12:38:11.580892 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3227 12:38:11.583471 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3228 12:38:11.586802 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3229 12:38:11.590467 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3230 12:38:11.590558
3231 12:38:11.590622
3232 12:38:11.593448 ==
3233 12:38:11.597026 Dram Type= 6, Freq= 0, CH_1, rank 0
3234 12:38:11.600448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3235 12:38:11.600535 ==
3236 12:38:11.600601
3237 12:38:11.600660
3238 12:38:11.603556 TX Vref Scan disable
3239 12:38:11.603641 == TX Byte 0 ==
3240 12:38:11.606876 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3241 12:38:11.613499 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3242 12:38:11.613621 == TX Byte 1 ==
3243 12:38:11.617027 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3244 12:38:11.624234 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3245 12:38:11.624386 ==
3246 12:38:11.627250 Dram Type= 6, Freq= 0, CH_1, rank 0
3247 12:38:11.630614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3248 12:38:11.630731 ==
3249 12:38:11.642268 TX Vref=22, minBit 9, minWin=23, winSum=408
3250 12:38:11.645296 TX Vref=24, minBit 8, minWin=24, winSum=413
3251 12:38:11.648721 TX Vref=26, minBit 9, minWin=25, winSum=421
3252 12:38:11.652720 TX Vref=28, minBit 8, minWin=25, winSum=424
3253 12:38:11.655561 TX Vref=30, minBit 7, minWin=26, winSum=428
3254 12:38:11.658541 TX Vref=32, minBit 9, minWin=24, winSum=424
3255 12:38:11.665711 [TxChooseVref] Worse bit 7, Min win 26, Win sum 428, Final Vref 30
3256 12:38:11.665836
3257 12:38:11.668653 Final TX Range 1 Vref 30
3258 12:38:11.668757
3259 12:38:11.668837 ==
3260 12:38:11.671964 Dram Type= 6, Freq= 0, CH_1, rank 0
3261 12:38:11.675437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3262 12:38:11.675567 ==
3263 12:38:11.675667
3264 12:38:11.678732
3265 12:38:11.678849 TX Vref Scan disable
3266 12:38:11.682380 == TX Byte 0 ==
3267 12:38:11.685843 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3268 12:38:11.688587 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3269 12:38:11.692283 == TX Byte 1 ==
3270 12:38:11.695612 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3271 12:38:11.698891 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3272 12:38:11.699017
3273 12:38:11.701716 [DATLAT]
3274 12:38:11.701829 Freq=1200, CH1 RK0
3275 12:38:11.701926
3276 12:38:11.705273 DATLAT Default: 0xd
3277 12:38:11.705388 0, 0xFFFF, sum = 0
3278 12:38:11.708963 1, 0xFFFF, sum = 0
3279 12:38:11.709083 2, 0xFFFF, sum = 0
3280 12:38:11.712189 3, 0xFFFF, sum = 0
3281 12:38:11.712308 4, 0xFFFF, sum = 0
3282 12:38:11.715462 5, 0xFFFF, sum = 0
3283 12:38:11.715580 6, 0xFFFF, sum = 0
3284 12:38:11.718584 7, 0xFFFF, sum = 0
3285 12:38:11.722197 8, 0xFFFF, sum = 0
3286 12:38:11.722323 9, 0xFFFF, sum = 0
3287 12:38:11.725077 10, 0xFFFF, sum = 0
3288 12:38:11.725210 11, 0xFFFF, sum = 0
3289 12:38:11.729270 12, 0x0, sum = 1
3290 12:38:11.729394 13, 0x0, sum = 2
3291 12:38:11.731793 14, 0x0, sum = 3
3292 12:38:11.731910 15, 0x0, sum = 4
3293 12:38:11.732009 best_step = 13
3294 12:38:11.732101
3295 12:38:11.735631 ==
3296 12:38:11.739264 Dram Type= 6, Freq= 0, CH_1, rank 0
3297 12:38:11.741706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3298 12:38:11.741828 ==
3299 12:38:11.741923 RX Vref Scan: 1
3300 12:38:11.742017
3301 12:38:11.745250 Set Vref Range= 32 -> 127
3302 12:38:11.745394
3303 12:38:11.748361 RX Vref 32 -> 127, step: 1
3304 12:38:11.748499
3305 12:38:11.751614 RX Delay -13 -> 252, step: 4
3306 12:38:11.751755
3307 12:38:11.755060 Set Vref, RX VrefLevel [Byte0]: 32
3308 12:38:11.758488 [Byte1]: 32
3309 12:38:11.758618
3310 12:38:11.761451 Set Vref, RX VrefLevel [Byte0]: 33
3311 12:38:11.765182 [Byte1]: 33
3312 12:38:11.765343
3313 12:38:11.768407 Set Vref, RX VrefLevel [Byte0]: 34
3314 12:38:11.771784 [Byte1]: 34
3315 12:38:11.775904
3316 12:38:11.776066 Set Vref, RX VrefLevel [Byte0]: 35
3317 12:38:11.779697 [Byte1]: 35
3318 12:38:11.784353
3319 12:38:11.784552 Set Vref, RX VrefLevel [Byte0]: 36
3320 12:38:11.787851 [Byte1]: 36
3321 12:38:11.791751
3322 12:38:11.791906 Set Vref, RX VrefLevel [Byte0]: 37
3323 12:38:11.795264 [Byte1]: 37
3324 12:38:11.799631
3325 12:38:11.799789 Set Vref, RX VrefLevel [Byte0]: 38
3326 12:38:11.802884 [Byte1]: 38
3327 12:38:11.807712
3328 12:38:11.807871 Set Vref, RX VrefLevel [Byte0]: 39
3329 12:38:11.811296 [Byte1]: 39
3330 12:38:11.815535
3331 12:38:11.815693 Set Vref, RX VrefLevel [Byte0]: 40
3332 12:38:11.819200 [Byte1]: 40
3333 12:38:11.823731
3334 12:38:11.823894 Set Vref, RX VrefLevel [Byte0]: 41
3335 12:38:11.826647 [Byte1]: 41
3336 12:38:11.831154
3337 12:38:11.831305 Set Vref, RX VrefLevel [Byte0]: 42
3338 12:38:11.834780 [Byte1]: 42
3339 12:38:11.839108
3340 12:38:11.839243 Set Vref, RX VrefLevel [Byte0]: 43
3341 12:38:11.842816 [Byte1]: 43
3342 12:38:11.847303
3343 12:38:11.847511 Set Vref, RX VrefLevel [Byte0]: 44
3344 12:38:11.850278 [Byte1]: 44
3345 12:38:11.854786
3346 12:38:11.854926 Set Vref, RX VrefLevel [Byte0]: 45
3347 12:38:11.858103 [Byte1]: 45
3348 12:38:11.862488
3349 12:38:11.862635 Set Vref, RX VrefLevel [Byte0]: 46
3350 12:38:11.866679 [Byte1]: 46
3351 12:38:11.870995
3352 12:38:11.871134 Set Vref, RX VrefLevel [Byte0]: 47
3353 12:38:11.873889 [Byte1]: 47
3354 12:38:11.878300
3355 12:38:11.878411 Set Vref, RX VrefLevel [Byte0]: 48
3356 12:38:11.882129 [Byte1]: 48
3357 12:38:11.886675
3358 12:38:11.886823 Set Vref, RX VrefLevel [Byte0]: 49
3359 12:38:11.889738 [Byte1]: 49
3360 12:38:11.894110
3361 12:38:11.894236 Set Vref, RX VrefLevel [Byte0]: 50
3362 12:38:11.897438 [Byte1]: 50
3363 12:38:11.901945
3364 12:38:11.902071 Set Vref, RX VrefLevel [Byte0]: 51
3365 12:38:11.905944 [Byte1]: 51
3366 12:38:11.910273
3367 12:38:11.910394 Set Vref, RX VrefLevel [Byte0]: 52
3368 12:38:11.913332 [Byte1]: 52
3369 12:38:11.918604
3370 12:38:11.918746 Set Vref, RX VrefLevel [Byte0]: 53
3371 12:38:11.921192 [Byte1]: 53
3372 12:38:11.925756
3373 12:38:11.925914 Set Vref, RX VrefLevel [Byte0]: 54
3374 12:38:11.928852 [Byte1]: 54
3375 12:38:11.933835
3376 12:38:11.933999 Set Vref, RX VrefLevel [Byte0]: 55
3377 12:38:11.937943 [Byte1]: 55
3378 12:38:11.941376
3379 12:38:11.941531 Set Vref, RX VrefLevel [Byte0]: 56
3380 12:38:11.944599 [Byte1]: 56
3381 12:38:11.949630
3382 12:38:11.949790 Set Vref, RX VrefLevel [Byte0]: 57
3383 12:38:11.952523 [Byte1]: 57
3384 12:38:11.957121
3385 12:38:11.957245 Set Vref, RX VrefLevel [Byte0]: 58
3386 12:38:11.961113 [Byte1]: 58
3387 12:38:11.965011
3388 12:38:11.965129 Set Vref, RX VrefLevel [Byte0]: 59
3389 12:38:11.968691 [Byte1]: 59
3390 12:38:11.973208
3391 12:38:11.973328 Set Vref, RX VrefLevel [Byte0]: 60
3392 12:38:11.976979 [Byte1]: 60
3393 12:38:11.981126
3394 12:38:11.981246 Set Vref, RX VrefLevel [Byte0]: 61
3395 12:38:11.984910 [Byte1]: 61
3396 12:38:11.988665
3397 12:38:11.988810 Set Vref, RX VrefLevel [Byte0]: 62
3398 12:38:11.992246 [Byte1]: 62
3399 12:38:11.996652
3400 12:38:11.996803 Set Vref, RX VrefLevel [Byte0]: 63
3401 12:38:12.000602 [Byte1]: 63
3402 12:38:12.004671
3403 12:38:12.004826 Set Vref, RX VrefLevel [Byte0]: 64
3404 12:38:12.007817 [Byte1]: 64
3405 12:38:12.012396
3406 12:38:12.012547 Set Vref, RX VrefLevel [Byte0]: 65
3407 12:38:12.016277 [Byte1]: 65
3408 12:38:12.020234
3409 12:38:12.020370 Final RX Vref Byte 0 = 50 to rank0
3410 12:38:12.023386 Final RX Vref Byte 1 = 55 to rank0
3411 12:38:12.026974 Final RX Vref Byte 0 = 50 to rank1
3412 12:38:12.029994 Final RX Vref Byte 1 = 55 to rank1==
3413 12:38:12.033585 Dram Type= 6, Freq= 0, CH_1, rank 0
3414 12:38:12.039993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3415 12:38:12.040182 ==
3416 12:38:12.040275 DQS Delay:
3417 12:38:12.043464 DQS0 = 0, DQS1 = 0
3418 12:38:12.043585 DQM Delay:
3419 12:38:12.043679 DQM0 = 115, DQM1 = 113
3420 12:38:12.046773 DQ Delay:
3421 12:38:12.050153 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =114
3422 12:38:12.053431 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3423 12:38:12.057107 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =106
3424 12:38:12.059793 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =122
3425 12:38:12.059931
3426 12:38:12.060020
3427 12:38:12.070422 [DQSOSCAuto] RK0, (LSB)MR18= 0xf804, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 413 ps
3428 12:38:12.070577 CH1 RK0: MR19=304, MR18=F804
3429 12:38:12.076692 CH1_RK0: MR19=0x304, MR18=0xF804, DQSOSC=408, MR23=63, INC=39, DEC=26
3430 12:38:12.076826
3431 12:38:12.080337 ----->DramcWriteLeveling(PI) begin...
3432 12:38:12.080447 ==
3433 12:38:12.083535 Dram Type= 6, Freq= 0, CH_1, rank 1
3434 12:38:12.089942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3435 12:38:12.090088 ==
3436 12:38:12.093348 Write leveling (Byte 0): 25 => 25
3437 12:38:12.093459 Write leveling (Byte 1): 28 => 28
3438 12:38:12.096802 DramcWriteLeveling(PI) end<-----
3439 12:38:12.096903
3440 12:38:12.096989 ==
3441 12:38:12.100119 Dram Type= 6, Freq= 0, CH_1, rank 1
3442 12:38:12.106750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3443 12:38:12.106893 ==
3444 12:38:12.110032 [Gating] SW mode calibration
3445 12:38:12.116458 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3446 12:38:12.119928 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3447 12:38:12.126514 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3448 12:38:12.131232 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3449 12:38:12.133491 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3450 12:38:12.140022 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3451 12:38:12.143666 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 12:38:12.146884 0 15 20 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
3453 12:38:12.153183 0 15 24 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
3454 12:38:12.157116 0 15 28 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
3455 12:38:12.159957 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 12:38:12.163470 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 12:38:12.170125 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3458 12:38:12.173378 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 12:38:12.176519 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 12:38:12.183831 1 0 20 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
3461 12:38:12.186638 1 0 24 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
3462 12:38:12.189970 1 0 28 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
3463 12:38:12.196533 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 12:38:12.199765 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 12:38:12.203053 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 12:38:12.210271 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 12:38:12.212967 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 12:38:12.217141 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3469 12:38:12.223136 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3470 12:38:12.226397 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3471 12:38:12.229467 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 12:38:12.236148 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 12:38:12.239614 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 12:38:12.242991 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 12:38:12.250269 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 12:38:12.252925 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 12:38:12.255867 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 12:38:12.262391 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 12:38:12.266291 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 12:38:12.268974 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 12:38:12.275561 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 12:38:12.278993 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 12:38:12.282169 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 12:38:12.288893 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3485 12:38:12.292893 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3486 12:38:12.296075 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3487 12:38:12.298721 Total UI for P1: 0, mck2ui 16
3488 12:38:12.302765 best dqsien dly found for B0: ( 1, 3, 22)
3489 12:38:12.308551 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 12:38:12.308684 Total UI for P1: 0, mck2ui 16
3491 12:38:12.315333 best dqsien dly found for B1: ( 1, 3, 28)
3492 12:38:12.318650 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3493 12:38:12.321813 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3494 12:38:12.321923
3495 12:38:12.325302 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3496 12:38:12.328659 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3497 12:38:12.331922 [Gating] SW calibration Done
3498 12:38:12.332064 ==
3499 12:38:12.335238 Dram Type= 6, Freq= 0, CH_1, rank 1
3500 12:38:12.339111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3501 12:38:12.339267 ==
3502 12:38:12.341690 RX Vref Scan: 0
3503 12:38:12.341810
3504 12:38:12.341911 RX Vref 0 -> 0, step: 1
3505 12:38:12.345000
3506 12:38:12.345127 RX Delay -40 -> 252, step: 8
3507 12:38:12.351736 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3508 12:38:12.355261 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3509 12:38:12.358287 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3510 12:38:12.361148 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3511 12:38:12.364852 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3512 12:38:12.371117 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3513 12:38:12.374404 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3514 12:38:12.377756 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3515 12:38:12.381232 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3516 12:38:12.384268 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3517 12:38:12.390777 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3518 12:38:12.394275 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3519 12:38:12.397585 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3520 12:38:12.401048 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3521 12:38:12.407679 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3522 12:38:12.410675 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3523 12:38:12.410840 ==
3524 12:38:12.414216 Dram Type= 6, Freq= 0, CH_1, rank 1
3525 12:38:12.417006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3526 12:38:12.417112 ==
3527 12:38:12.420523 DQS Delay:
3528 12:38:12.420644 DQS0 = 0, DQS1 = 0
3529 12:38:12.420739 DQM Delay:
3530 12:38:12.424606 DQM0 = 113, DQM1 = 112
3531 12:38:12.424725 DQ Delay:
3532 12:38:12.427339 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3533 12:38:12.430366 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =111
3534 12:38:12.434057 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3535 12:38:12.440735 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3536 12:38:12.440885
3537 12:38:12.440955
3538 12:38:12.441022 ==
3539 12:38:12.443414 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 12:38:12.446895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 12:38:12.447025 ==
3542 12:38:12.447094
3543 12:38:12.447157
3544 12:38:12.449822 TX Vref Scan disable
3545 12:38:12.453217 == TX Byte 0 ==
3546 12:38:12.456470 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3547 12:38:12.460313 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3548 12:38:12.462836 == TX Byte 1 ==
3549 12:38:12.466722 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3550 12:38:12.469809 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3551 12:38:12.469939 ==
3552 12:38:12.473389 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 12:38:12.476600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 12:38:12.479909 ==
3555 12:38:12.489606 TX Vref=22, minBit 9, minWin=23, winSum=418
3556 12:38:12.493073 TX Vref=24, minBit 7, minWin=25, winSum=423
3557 12:38:12.496176 TX Vref=26, minBit 9, minWin=25, winSum=427
3558 12:38:12.499604 TX Vref=28, minBit 9, minWin=24, winSum=429
3559 12:38:12.502968 TX Vref=30, minBit 9, minWin=25, winSum=429
3560 12:38:12.509262 TX Vref=32, minBit 9, minWin=25, winSum=431
3561 12:38:12.512316 [TxChooseVref] Worse bit 9, Min win 25, Win sum 431, Final Vref 32
3562 12:38:12.512440
3563 12:38:12.516216 Final TX Range 1 Vref 32
3564 12:38:12.516353
3565 12:38:12.516424 ==
3566 12:38:12.519212 Dram Type= 6, Freq= 0, CH_1, rank 1
3567 12:38:12.525722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3568 12:38:12.525868 ==
3569 12:38:12.525940
3570 12:38:12.526001
3571 12:38:12.526059 TX Vref Scan disable
3572 12:38:12.529388 == TX Byte 0 ==
3573 12:38:12.533544 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3574 12:38:12.539175 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3575 12:38:12.539333 == TX Byte 1 ==
3576 12:38:12.542756 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3577 12:38:12.549186 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3578 12:38:12.549343
3579 12:38:12.549415 [DATLAT]
3580 12:38:12.549477 Freq=1200, CH1 RK1
3581 12:38:12.549538
3582 12:38:12.552193 DATLAT Default: 0xd
3583 12:38:12.555702 0, 0xFFFF, sum = 0
3584 12:38:12.555819 1, 0xFFFF, sum = 0
3585 12:38:12.558794 2, 0xFFFF, sum = 0
3586 12:38:12.558897 3, 0xFFFF, sum = 0
3587 12:38:12.562397 4, 0xFFFF, sum = 0
3588 12:38:12.562523 5, 0xFFFF, sum = 0
3589 12:38:12.565798 6, 0xFFFF, sum = 0
3590 12:38:12.565899 7, 0xFFFF, sum = 0
3591 12:38:12.568558 8, 0xFFFF, sum = 0
3592 12:38:12.568658 9, 0xFFFF, sum = 0
3593 12:38:12.571925 10, 0xFFFF, sum = 0
3594 12:38:12.572062 11, 0xFFFF, sum = 0
3595 12:38:12.575280 12, 0x0, sum = 1
3596 12:38:12.575416 13, 0x0, sum = 2
3597 12:38:12.579154 14, 0x0, sum = 3
3598 12:38:12.579291 15, 0x0, sum = 4
3599 12:38:12.582177 best_step = 13
3600 12:38:12.582262
3601 12:38:12.582327 ==
3602 12:38:12.585353 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 12:38:12.588571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 12:38:12.588682 ==
3605 12:38:12.591677 RX Vref Scan: 0
3606 12:38:12.591776
3607 12:38:12.591844 RX Vref 0 -> 0, step: 1
3608 12:38:12.591906
3609 12:38:12.594963 RX Delay -13 -> 252, step: 4
3610 12:38:12.601677 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3611 12:38:12.605255 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3612 12:38:12.608182 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3613 12:38:12.611603 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3614 12:38:12.618184 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3615 12:38:12.621402 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3616 12:38:12.625024 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3617 12:38:12.627895 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3618 12:38:12.630951 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3619 12:38:12.637847 iDelay=195, Bit 9, Center 104 (39 ~ 170) 132
3620 12:38:12.640938 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3621 12:38:12.644338 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3622 12:38:12.647754 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3623 12:38:12.651305 iDelay=195, Bit 13, Center 122 (59 ~ 186) 128
3624 12:38:12.657567 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3625 12:38:12.660739 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3626 12:38:12.660889 ==
3627 12:38:12.664272 Dram Type= 6, Freq= 0, CH_1, rank 1
3628 12:38:12.667123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3629 12:38:12.667222 ==
3630 12:38:12.670886 DQS Delay:
3631 12:38:12.671006 DQS0 = 0, DQS1 = 0
3632 12:38:12.674087 DQM Delay:
3633 12:38:12.674183 DQM0 = 115, DQM1 = 114
3634 12:38:12.674251 DQ Delay:
3635 12:38:12.677393 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3636 12:38:12.680967 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3637 12:38:12.687175 DQ8 =100, DQ9 =104, DQ10 =116, DQ11 =106
3638 12:38:12.690783 DQ12 =122, DQ13 =122, DQ14 =120, DQ15 =122
3639 12:38:12.690905
3640 12:38:12.690973
3641 12:38:12.697325 [DQSOSCAuto] RK1, (LSB)MR18= 0xf709, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3642 12:38:12.700261 CH1 RK1: MR19=304, MR18=F709
3643 12:38:12.707240 CH1_RK1: MR19=0x304, MR18=0xF709, DQSOSC=406, MR23=63, INC=39, DEC=26
3644 12:38:12.710667 [RxdqsGatingPostProcess] freq 1200
3645 12:38:12.716515 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3646 12:38:12.720206 best DQS0 dly(2T, 0.5T) = (0, 11)
3647 12:38:12.720328 best DQS1 dly(2T, 0.5T) = (0, 11)
3648 12:38:12.723410 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3649 12:38:12.726525 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3650 12:38:12.729684 best DQS0 dly(2T, 0.5T) = (0, 11)
3651 12:38:12.733173 best DQS1 dly(2T, 0.5T) = (0, 11)
3652 12:38:12.736299 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3653 12:38:12.740425 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3654 12:38:12.743002 Pre-setting of DQS Precalculation
3655 12:38:12.749546 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3656 12:38:12.756352 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3657 12:38:12.762780 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3658 12:38:12.762926
3659 12:38:12.762998
3660 12:38:12.765799 [Calibration Summary] 2400 Mbps
3661 12:38:12.765895 CH 0, Rank 0
3662 12:38:12.769922 SW Impedance : PASS
3663 12:38:12.772320 DUTY Scan : NO K
3664 12:38:12.772423 ZQ Calibration : PASS
3665 12:38:12.776018 Jitter Meter : NO K
3666 12:38:12.779546 CBT Training : PASS
3667 12:38:12.779661 Write leveling : PASS
3668 12:38:12.782972 RX DQS gating : PASS
3669 12:38:12.785867 RX DQ/DQS(RDDQC) : PASS
3670 12:38:12.785999 TX DQ/DQS : PASS
3671 12:38:12.789066 RX DATLAT : PASS
3672 12:38:12.792610 RX DQ/DQS(Engine): PASS
3673 12:38:12.792724 TX OE : NO K
3674 12:38:12.795832 All Pass.
3675 12:38:12.795924
3676 12:38:12.795996 CH 0, Rank 1
3677 12:38:12.799214 SW Impedance : PASS
3678 12:38:12.799313 DUTY Scan : NO K
3679 12:38:12.802402 ZQ Calibration : PASS
3680 12:38:12.805560 Jitter Meter : NO K
3681 12:38:12.805677 CBT Training : PASS
3682 12:38:12.808995 Write leveling : PASS
3683 12:38:12.811938 RX DQS gating : PASS
3684 12:38:12.812045 RX DQ/DQS(RDDQC) : PASS
3685 12:38:12.815543 TX DQ/DQS : PASS
3686 12:38:12.818837 RX DATLAT : PASS
3687 12:38:12.818938 RX DQ/DQS(Engine): PASS
3688 12:38:12.821899 TX OE : NO K
3689 12:38:12.821995 All Pass.
3690 12:38:12.822060
3691 12:38:12.825948 CH 1, Rank 0
3692 12:38:12.826037 SW Impedance : PASS
3693 12:38:12.829009 DUTY Scan : NO K
3694 12:38:12.832007 ZQ Calibration : PASS
3695 12:38:12.832100 Jitter Meter : NO K
3696 12:38:12.835294 CBT Training : PASS
3697 12:38:12.838232 Write leveling : PASS
3698 12:38:12.838322 RX DQS gating : PASS
3699 12:38:12.841567 RX DQ/DQS(RDDQC) : PASS
3700 12:38:12.841714 TX DQ/DQS : PASS
3701 12:38:12.846107 RX DATLAT : PASS
3702 12:38:12.848323 RX DQ/DQS(Engine): PASS
3703 12:38:12.848413 TX OE : NO K
3704 12:38:12.851586 All Pass.
3705 12:38:12.851682
3706 12:38:12.851747 CH 1, Rank 1
3707 12:38:12.855080 SW Impedance : PASS
3708 12:38:12.855169 DUTY Scan : NO K
3709 12:38:12.858564 ZQ Calibration : PASS
3710 12:38:12.861315 Jitter Meter : NO K
3711 12:38:12.861411 CBT Training : PASS
3712 12:38:12.864995 Write leveling : PASS
3713 12:38:12.867839 RX DQS gating : PASS
3714 12:38:12.867933 RX DQ/DQS(RDDQC) : PASS
3715 12:38:12.871082 TX DQ/DQS : PASS
3716 12:38:12.874582 RX DATLAT : PASS
3717 12:38:12.874708 RX DQ/DQS(Engine): PASS
3718 12:38:12.878126 TX OE : NO K
3719 12:38:12.878225 All Pass.
3720 12:38:12.878291
3721 12:38:12.881544 DramC Write-DBI off
3722 12:38:12.884415 PER_BANK_REFRESH: Hybrid Mode
3723 12:38:12.884547 TX_TRACKING: ON
3724 12:38:12.894606 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3725 12:38:12.898284 [FAST_K] Save calibration result to emmc
3726 12:38:12.901238 dramc_set_vcore_voltage set vcore to 650000
3727 12:38:12.904409 Read voltage for 600, 5
3728 12:38:12.904541 Vio18 = 0
3729 12:38:12.904636 Vcore = 650000
3730 12:38:12.907995 Vdram = 0
3731 12:38:12.908121 Vddq = 0
3732 12:38:12.908240 Vmddr = 0
3733 12:38:12.914636 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3734 12:38:12.921232 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3735 12:38:12.921382 MEM_TYPE=3, freq_sel=19
3736 12:38:12.924304 sv_algorithm_assistance_LP4_1600
3737 12:38:12.927241 ============ PULL DRAM RESETB DOWN ============
3738 12:38:12.934229 ========== PULL DRAM RESETB DOWN end =========
3739 12:38:12.937113 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3740 12:38:12.940489 ===================================
3741 12:38:12.944193 LPDDR4 DRAM CONFIGURATION
3742 12:38:12.946900 ===================================
3743 12:38:12.947047 EX_ROW_EN[0] = 0x0
3744 12:38:12.950668 EX_ROW_EN[1] = 0x0
3745 12:38:12.950781 LP4Y_EN = 0x0
3746 12:38:12.954536 WORK_FSP = 0x0
3747 12:38:12.954636 WL = 0x2
3748 12:38:12.956767 RL = 0x2
3749 12:38:12.960326 BL = 0x2
3750 12:38:12.960455 RPST = 0x0
3751 12:38:12.963293 RD_PRE = 0x0
3752 12:38:12.963418 WR_PRE = 0x1
3753 12:38:12.966873 WR_PST = 0x0
3754 12:38:12.966971 DBI_WR = 0x0
3755 12:38:12.969824 DBI_RD = 0x0
3756 12:38:12.969923 OTF = 0x1
3757 12:38:12.973591 ===================================
3758 12:38:12.977009 ===================================
3759 12:38:12.979712 ANA top config
3760 12:38:12.983518 ===================================
3761 12:38:12.983625 DLL_ASYNC_EN = 0
3762 12:38:12.986461 ALL_SLAVE_EN = 1
3763 12:38:12.989728 NEW_RANK_MODE = 1
3764 12:38:12.993045 DLL_IDLE_MODE = 1
3765 12:38:12.996523 LP45_APHY_COMB_EN = 1
3766 12:38:12.996646 TX_ODT_DIS = 1
3767 12:38:12.999619 NEW_8X_MODE = 1
3768 12:38:13.002912 ===================================
3769 12:38:13.006607 ===================================
3770 12:38:13.009356 data_rate = 1200
3771 12:38:13.012748 CKR = 1
3772 12:38:13.015864 DQ_P2S_RATIO = 8
3773 12:38:13.019660 ===================================
3774 12:38:13.022924 CA_P2S_RATIO = 8
3775 12:38:13.023034 DQ_CA_OPEN = 0
3776 12:38:13.025957 DQ_SEMI_OPEN = 0
3777 12:38:13.029643 CA_SEMI_OPEN = 0
3778 12:38:13.032845 CA_FULL_RATE = 0
3779 12:38:13.035853 DQ_CKDIV4_EN = 1
3780 12:38:13.039313 CA_CKDIV4_EN = 1
3781 12:38:13.039474 CA_PREDIV_EN = 0
3782 12:38:13.042343 PH8_DLY = 0
3783 12:38:13.045447 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3784 12:38:13.048919 DQ_AAMCK_DIV = 4
3785 12:38:13.051870 CA_AAMCK_DIV = 4
3786 12:38:13.055748 CA_ADMCK_DIV = 4
3787 12:38:13.055863 DQ_TRACK_CA_EN = 0
3788 12:38:13.058502 CA_PICK = 600
3789 12:38:13.062547 CA_MCKIO = 600
3790 12:38:13.065712 MCKIO_SEMI = 0
3791 12:38:13.068378 PLL_FREQ = 2288
3792 12:38:13.071933 DQ_UI_PI_RATIO = 32
3793 12:38:13.075562 CA_UI_PI_RATIO = 0
3794 12:38:13.078310 ===================================
3795 12:38:13.081900 ===================================
3796 12:38:13.082015 memory_type:LPDDR4
3797 12:38:13.085244 GP_NUM : 10
3798 12:38:13.088324 SRAM_EN : 1
3799 12:38:13.088470 MD32_EN : 0
3800 12:38:13.091812 ===================================
3801 12:38:13.094801 [ANA_INIT] >>>>>>>>>>>>>>
3802 12:38:13.097992 <<<<<< [CONFIGURE PHASE]: ANA_TX
3803 12:38:13.101810 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3804 12:38:13.104708 ===================================
3805 12:38:13.108570 data_rate = 1200,PCW = 0X5800
3806 12:38:13.111835 ===================================
3807 12:38:13.114777 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3808 12:38:13.117771 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3809 12:38:13.124524 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3810 12:38:13.130933 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3811 12:38:13.134305 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3812 12:38:13.137514 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3813 12:38:13.137631 [ANA_INIT] flow start
3814 12:38:13.141005 [ANA_INIT] PLL >>>>>>>>
3815 12:38:13.144578 [ANA_INIT] PLL <<<<<<<<
3816 12:38:13.144695 [ANA_INIT] MIDPI >>>>>>>>
3817 12:38:13.147264 [ANA_INIT] MIDPI <<<<<<<<
3818 12:38:13.150797 [ANA_INIT] DLL >>>>>>>>
3819 12:38:13.150909 [ANA_INIT] flow end
3820 12:38:13.157683 ============ LP4 DIFF to SE enter ============
3821 12:38:13.160980 ============ LP4 DIFF to SE exit ============
3822 12:38:13.164181 [ANA_INIT] <<<<<<<<<<<<<
3823 12:38:13.167285 [Flow] Enable top DCM control >>>>>
3824 12:38:13.170423 [Flow] Enable top DCM control <<<<<
3825 12:38:13.170521 Enable DLL master slave shuffle
3826 12:38:13.177223 ==============================================================
3827 12:38:13.180685 Gating Mode config
3828 12:38:13.183400 ==============================================================
3829 12:38:13.186908 Config description:
3830 12:38:13.196766 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3831 12:38:13.203354 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3832 12:38:13.206605 SELPH_MODE 0: By rank 1: By Phase
3833 12:38:13.213169 ==============================================================
3834 12:38:13.216436 GAT_TRACK_EN = 1
3835 12:38:13.219676 RX_GATING_MODE = 2
3836 12:38:13.223318 RX_GATING_TRACK_MODE = 2
3837 12:38:13.226335 SELPH_MODE = 1
3838 12:38:13.229796 PICG_EARLY_EN = 1
3839 12:38:13.232690 VALID_LAT_VALUE = 1
3840 12:38:13.236109 ==============================================================
3841 12:38:13.239440 Enter into Gating configuration >>>>
3842 12:38:13.243294 Exit from Gating configuration <<<<
3843 12:38:13.246175 Enter into DVFS_PRE_config >>>>>
3844 12:38:13.259270 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3845 12:38:13.262363 Exit from DVFS_PRE_config <<<<<
3846 12:38:13.262472 Enter into PICG configuration >>>>
3847 12:38:13.265814 Exit from PICG configuration <<<<
3848 12:38:13.269174 [RX_INPUT] configuration >>>>>
3849 12:38:13.272278 [RX_INPUT] configuration <<<<<
3850 12:38:13.279610 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3851 12:38:13.282674 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3852 12:38:13.289585 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3853 12:38:13.296119 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3854 12:38:13.301914 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3855 12:38:13.308743 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3856 12:38:13.312126 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3857 12:38:13.315558 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3858 12:38:13.318808 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3859 12:38:13.325467 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3860 12:38:13.328482 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3861 12:38:13.331963 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3862 12:38:13.335702 ===================================
3863 12:38:13.339173 LPDDR4 DRAM CONFIGURATION
3864 12:38:13.342384 ===================================
3865 12:38:13.345338 EX_ROW_EN[0] = 0x0
3866 12:38:13.345447 EX_ROW_EN[1] = 0x0
3867 12:38:13.349018 LP4Y_EN = 0x0
3868 12:38:13.349116 WORK_FSP = 0x0
3869 12:38:13.351612 WL = 0x2
3870 12:38:13.351703 RL = 0x2
3871 12:38:13.355370 BL = 0x2
3872 12:38:13.355472 RPST = 0x0
3873 12:38:13.358450 RD_PRE = 0x0
3874 12:38:13.358543 WR_PRE = 0x1
3875 12:38:13.361644 WR_PST = 0x0
3876 12:38:13.361742 DBI_WR = 0x0
3877 12:38:13.364656 DBI_RD = 0x0
3878 12:38:13.368163 OTF = 0x1
3879 12:38:13.371615 ===================================
3880 12:38:13.374728 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3881 12:38:13.378133 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3882 12:38:13.381219 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3883 12:38:13.384750 ===================================
3884 12:38:13.387606 LPDDR4 DRAM CONFIGURATION
3885 12:38:13.391013 ===================================
3886 12:38:13.394718 EX_ROW_EN[0] = 0x10
3887 12:38:13.394838 EX_ROW_EN[1] = 0x0
3888 12:38:13.397606 LP4Y_EN = 0x0
3889 12:38:13.397702 WORK_FSP = 0x0
3890 12:38:13.401077 WL = 0x2
3891 12:38:13.401177 RL = 0x2
3892 12:38:13.403877 BL = 0x2
3893 12:38:13.407556 RPST = 0x0
3894 12:38:13.407684 RD_PRE = 0x0
3895 12:38:13.410456 WR_PRE = 0x1
3896 12:38:13.410553 WR_PST = 0x0
3897 12:38:13.413988 DBI_WR = 0x0
3898 12:38:13.414088 DBI_RD = 0x0
3899 12:38:13.417171 OTF = 0x1
3900 12:38:13.420862 ===================================
3901 12:38:13.423747 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3902 12:38:13.429371 nWR fixed to 30
3903 12:38:13.432665 [ModeRegInit_LP4] CH0 RK0
3904 12:38:13.432776 [ModeRegInit_LP4] CH0 RK1
3905 12:38:13.436287 [ModeRegInit_LP4] CH1 RK0
3906 12:38:13.439020 [ModeRegInit_LP4] CH1 RK1
3907 12:38:13.439117 match AC timing 17
3908 12:38:13.446210 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3909 12:38:13.449219 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3910 12:38:13.452268 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3911 12:38:13.458826 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3912 12:38:13.462242 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3913 12:38:13.462358 ==
3914 12:38:13.465628 Dram Type= 6, Freq= 0, CH_0, rank 0
3915 12:38:13.468657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3916 12:38:13.468771 ==
3917 12:38:13.476125 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3918 12:38:13.481957 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3919 12:38:13.485379 [CA 0] Center 36 (6~67) winsize 62
3920 12:38:13.488784 [CA 1] Center 36 (5~67) winsize 63
3921 12:38:13.492242 [CA 2] Center 34 (3~65) winsize 63
3922 12:38:13.495356 [CA 3] Center 34 (3~65) winsize 63
3923 12:38:13.498759 [CA 4] Center 33 (3~64) winsize 62
3924 12:38:13.502046 [CA 5] Center 33 (3~64) winsize 62
3925 12:38:13.502197
3926 12:38:13.505282 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3927 12:38:13.505396
3928 12:38:13.508927 [CATrainingPosCal] consider 1 rank data
3929 12:38:13.511463 u2DelayCellTimex100 = 270/100 ps
3930 12:38:13.515294 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3931 12:38:13.518200 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3932 12:38:13.521815 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
3933 12:38:13.528475 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3934 12:38:13.531541 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3935 12:38:13.534951 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3936 12:38:13.535066
3937 12:38:13.537932 CA PerBit enable=1, Macro0, CA PI delay=33
3938 12:38:13.538029
3939 12:38:13.541684 [CBTSetCACLKResult] CA Dly = 33
3940 12:38:13.541814 CS Dly: 5 (0~36)
3941 12:38:13.544648 ==
3942 12:38:13.544740 Dram Type= 6, Freq= 0, CH_0, rank 1
3943 12:38:13.550997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3944 12:38:13.551139 ==
3945 12:38:13.554574 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3946 12:38:13.561098 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3947 12:38:13.564672 [CA 0] Center 36 (6~67) winsize 62
3948 12:38:13.568468 [CA 1] Center 36 (6~67) winsize 62
3949 12:38:13.571564 [CA 2] Center 34 (4~65) winsize 62
3950 12:38:13.574785 [CA 3] Center 34 (4~65) winsize 62
3951 12:38:13.578086 [CA 4] Center 34 (3~65) winsize 63
3952 12:38:13.581190 [CA 5] Center 33 (3~64) winsize 62
3953 12:38:13.581286
3954 12:38:13.584903 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3955 12:38:13.584998
3956 12:38:13.587746 [CATrainingPosCal] consider 2 rank data
3957 12:38:13.591202 u2DelayCellTimex100 = 270/100 ps
3958 12:38:13.594362 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3959 12:38:13.600690 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3960 12:38:13.604176 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3961 12:38:13.607300 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3962 12:38:13.611088 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3963 12:38:13.613962 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3964 12:38:13.614056
3965 12:38:13.617423 CA PerBit enable=1, Macro0, CA PI delay=33
3966 12:38:13.617513
3967 12:38:13.620547 [CBTSetCACLKResult] CA Dly = 33
3968 12:38:13.624202 CS Dly: 5 (0~37)
3969 12:38:13.624303
3970 12:38:13.627138 ----->DramcWriteLeveling(PI) begin...
3971 12:38:13.627263 ==
3972 12:38:13.630861 Dram Type= 6, Freq= 0, CH_0, rank 0
3973 12:38:13.634085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3974 12:38:13.634192 ==
3975 12:38:13.637498 Write leveling (Byte 0): 34 => 34
3976 12:38:13.641045 Write leveling (Byte 1): 27 => 27
3977 12:38:13.644272 DramcWriteLeveling(PI) end<-----
3978 12:38:13.644389
3979 12:38:13.644457 ==
3980 12:38:13.647071 Dram Type= 6, Freq= 0, CH_0, rank 0
3981 12:38:13.651195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3982 12:38:13.651315 ==
3983 12:38:13.653781 [Gating] SW mode calibration
3984 12:38:13.660639 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3985 12:38:13.668239 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3986 12:38:13.670189 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3987 12:38:13.673749 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3988 12:38:13.680429 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3989 12:38:13.683295 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
3990 12:38:13.686639 0 9 16 | B1->B0 | 2e2e 2b2b | 0 0 | (0 1) (0 0)
3991 12:38:13.693899 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 12:38:13.697037 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 12:38:13.700338 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 12:38:13.706910 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 12:38:13.709649 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 12:38:13.714062 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 12:38:13.719906 0 10 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
3998 12:38:13.722708 0 10 16 | B1->B0 | 3b3b 4343 | 0 0 | (0 0) (0 0)
3999 12:38:13.727158 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 12:38:13.732891 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 12:38:13.736451 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 12:38:13.739716 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 12:38:13.745764 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 12:38:13.749283 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 12:38:13.753024 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4006 12:38:13.759328 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4007 12:38:13.762481 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 12:38:13.766093 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 12:38:13.772717 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 12:38:13.775497 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 12:38:13.778933 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 12:38:13.785604 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 12:38:13.789070 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 12:38:13.792198 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 12:38:13.798908 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 12:38:13.802649 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 12:38:13.805153 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 12:38:13.811914 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 12:38:13.815016 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 12:38:13.818312 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 12:38:13.824718 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4022 12:38:13.828575 Total UI for P1: 0, mck2ui 16
4023 12:38:13.831789 best dqsien dly found for B0: ( 0, 13, 10)
4024 12:38:13.834823 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4025 12:38:13.837987 Total UI for P1: 0, mck2ui 16
4026 12:38:13.841333 best dqsien dly found for B1: ( 0, 13, 12)
4027 12:38:13.844691 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4028 12:38:13.847850 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4029 12:38:13.847967
4030 12:38:13.851327 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4031 12:38:13.857844 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4032 12:38:13.857980 [Gating] SW calibration Done
4033 12:38:13.858051 ==
4034 12:38:13.861146 Dram Type= 6, Freq= 0, CH_0, rank 0
4035 12:38:13.868602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4036 12:38:13.868751 ==
4037 12:38:13.868818 RX Vref Scan: 0
4038 12:38:13.868878
4039 12:38:13.871135 RX Vref 0 -> 0, step: 1
4040 12:38:13.871220
4041 12:38:13.874225 RX Delay -230 -> 252, step: 16
4042 12:38:13.878282 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4043 12:38:13.881008 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4044 12:38:13.887830 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4045 12:38:13.891124 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4046 12:38:13.894349 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4047 12:38:13.897831 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4048 12:38:13.904252 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4049 12:38:13.907306 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4050 12:38:13.910419 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4051 12:38:13.913767 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4052 12:38:13.917034 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4053 12:38:13.923685 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4054 12:38:13.926854 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4055 12:38:13.930546 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4056 12:38:13.936800 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4057 12:38:13.940461 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4058 12:38:13.940578 ==
4059 12:38:13.943614 Dram Type= 6, Freq= 0, CH_0, rank 0
4060 12:38:13.946720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4061 12:38:13.946832 ==
4062 12:38:13.949924 DQS Delay:
4063 12:38:13.950023 DQS0 = 0, DQS1 = 0
4064 12:38:13.950128 DQM Delay:
4065 12:38:13.954418 DQM0 = 40, DQM1 = 34
4066 12:38:13.954554 DQ Delay:
4067 12:38:13.957203 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4068 12:38:13.959788 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4069 12:38:13.963347 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4070 12:38:13.966985 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =33
4071 12:38:13.967184
4072 12:38:13.967281
4073 12:38:13.967394 ==
4074 12:38:13.969962 Dram Type= 6, Freq= 0, CH_0, rank 0
4075 12:38:13.976556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4076 12:38:13.976714 ==
4077 12:38:13.976811
4078 12:38:13.976903
4079 12:38:13.976988 TX Vref Scan disable
4080 12:38:13.980735 == TX Byte 0 ==
4081 12:38:13.983420 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4082 12:38:13.989826 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4083 12:38:13.990055 == TX Byte 1 ==
4084 12:38:13.993934 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4085 12:38:13.999913 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4086 12:38:14.000062 ==
4087 12:38:14.002799 Dram Type= 6, Freq= 0, CH_0, rank 0
4088 12:38:14.006247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4089 12:38:14.006381 ==
4090 12:38:14.006476
4091 12:38:14.006563
4092 12:38:14.009741 TX Vref Scan disable
4093 12:38:14.012996 == TX Byte 0 ==
4094 12:38:14.016303 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4095 12:38:14.020021 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4096 12:38:14.023226 == TX Byte 1 ==
4097 12:38:14.026204 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4098 12:38:14.029978 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4099 12:38:14.030138
4100 12:38:14.032538 [DATLAT]
4101 12:38:14.032628 Freq=600, CH0 RK0
4102 12:38:14.032693
4103 12:38:14.036152 DATLAT Default: 0x9
4104 12:38:14.036328 0, 0xFFFF, sum = 0
4105 12:38:14.039225 1, 0xFFFF, sum = 0
4106 12:38:14.039346 2, 0xFFFF, sum = 0
4107 12:38:14.042803 3, 0xFFFF, sum = 0
4108 12:38:14.042929 4, 0xFFFF, sum = 0
4109 12:38:14.045769 5, 0xFFFF, sum = 0
4110 12:38:14.045918 6, 0xFFFF, sum = 0
4111 12:38:14.048864 7, 0xFFFF, sum = 0
4112 12:38:14.048986 8, 0x0, sum = 1
4113 12:38:14.052725 9, 0x0, sum = 2
4114 12:38:14.052847 10, 0x0, sum = 3
4115 12:38:14.056136 11, 0x0, sum = 4
4116 12:38:14.056262 best_step = 9
4117 12:38:14.056353
4118 12:38:14.056439 ==
4119 12:38:14.059303 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 12:38:14.065601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 12:38:14.065749 ==
4122 12:38:14.065845 RX Vref Scan: 1
4123 12:38:14.065938
4124 12:38:14.068733 RX Vref 0 -> 0, step: 1
4125 12:38:14.068814
4126 12:38:14.071888 RX Delay -179 -> 252, step: 8
4127 12:38:14.072008
4128 12:38:14.075227 Set Vref, RX VrefLevel [Byte0]: 54
4129 12:38:14.078588 [Byte1]: 59
4130 12:38:14.078714
4131 12:38:14.081862 Final RX Vref Byte 0 = 54 to rank0
4132 12:38:14.085473 Final RX Vref Byte 1 = 59 to rank0
4133 12:38:14.088185 Final RX Vref Byte 0 = 54 to rank1
4134 12:38:14.091513 Final RX Vref Byte 1 = 59 to rank1==
4135 12:38:14.094930 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 12:38:14.098670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 12:38:14.098818 ==
4138 12:38:14.101409 DQS Delay:
4139 12:38:14.101500 DQS0 = 0, DQS1 = 0
4140 12:38:14.105040 DQM Delay:
4141 12:38:14.105167 DQM0 = 40, DQM1 = 32
4142 12:38:14.105291 DQ Delay:
4143 12:38:14.107997 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =36
4144 12:38:14.111701 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =44
4145 12:38:14.114935 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4146 12:38:14.118331 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4147 12:38:14.118444
4148 12:38:14.118510
4149 12:38:14.127782 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f47, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 394 ps
4150 12:38:14.131513 CH0 RK0: MR19=808, MR18=4F47
4151 12:38:14.137625 CH0_RK0: MR19=0x808, MR18=0x4F47, DQSOSC=394, MR23=63, INC=168, DEC=112
4152 12:38:14.137771
4153 12:38:14.140845 ----->DramcWriteLeveling(PI) begin...
4154 12:38:14.140971 ==
4155 12:38:14.144609 Dram Type= 6, Freq= 0, CH_0, rank 1
4156 12:38:14.147502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4157 12:38:14.147617 ==
4158 12:38:14.151313 Write leveling (Byte 0): 34 => 34
4159 12:38:14.154513 Write leveling (Byte 1): 30 => 30
4160 12:38:14.157454 DramcWriteLeveling(PI) end<-----
4161 12:38:14.157612
4162 12:38:14.157685 ==
4163 12:38:14.160908 Dram Type= 6, Freq= 0, CH_0, rank 1
4164 12:38:14.164668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 12:38:14.164781 ==
4166 12:38:14.167290 [Gating] SW mode calibration
4167 12:38:14.174140 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4168 12:38:14.180757 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4169 12:38:14.184150 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4170 12:38:14.187300 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4171 12:38:14.193556 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4172 12:38:14.197199 0 9 12 | B1->B0 | 3434 3131 | 0 1 | (0 1) (1 0)
4173 12:38:14.200224 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4174 12:38:14.206645 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 12:38:14.210286 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 12:38:14.213214 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 12:38:14.220262 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 12:38:14.223054 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 12:38:14.226941 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 12:38:14.233323 0 10 12 | B1->B0 | 2b2b 3535 | 0 0 | (0 0) (0 0)
4181 12:38:14.236844 0 10 16 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
4182 12:38:14.239608 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 12:38:14.246278 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 12:38:14.249676 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 12:38:14.253612 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 12:38:14.259524 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 12:38:14.263237 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 12:38:14.265912 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4189 12:38:14.273793 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4190 12:38:14.275975 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 12:38:14.279980 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 12:38:14.286624 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 12:38:14.288922 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 12:38:14.296295 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 12:38:14.298878 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 12:38:14.302925 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 12:38:14.305570 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 12:38:14.312482 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 12:38:14.315545 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 12:38:14.318868 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 12:38:14.325263 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 12:38:14.328655 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 12:38:14.334989 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4204 12:38:14.338782 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4205 12:38:14.341747 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4206 12:38:14.344936 Total UI for P1: 0, mck2ui 16
4207 12:38:14.348194 best dqsien dly found for B0: ( 0, 13, 10)
4208 12:38:14.351764 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4209 12:38:14.354601 Total UI for P1: 0, mck2ui 16
4210 12:38:14.358266 best dqsien dly found for B1: ( 0, 13, 14)
4211 12:38:14.364949 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4212 12:38:14.368172 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4213 12:38:14.368283
4214 12:38:14.371278 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4215 12:38:14.374835 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4216 12:38:14.378053 [Gating] SW calibration Done
4217 12:38:14.378161 ==
4218 12:38:14.381386 Dram Type= 6, Freq= 0, CH_0, rank 1
4219 12:38:14.384563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4220 12:38:14.384694 ==
4221 12:38:14.387853 RX Vref Scan: 0
4222 12:38:14.387971
4223 12:38:14.388067 RX Vref 0 -> 0, step: 1
4224 12:38:14.388156
4225 12:38:14.391342 RX Delay -230 -> 252, step: 16
4226 12:38:14.397555 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4227 12:38:14.401219 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4228 12:38:14.404323 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4229 12:38:14.408015 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4230 12:38:14.414302 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4231 12:38:14.417448 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4232 12:38:14.420586 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4233 12:38:14.424238 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4234 12:38:14.427264 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4235 12:38:14.433820 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4236 12:38:14.437508 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4237 12:38:14.441098 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4238 12:38:14.443433 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4239 12:38:14.450443 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4240 12:38:14.453725 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4241 12:38:14.456692 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4242 12:38:14.456833 ==
4243 12:38:14.460847 Dram Type= 6, Freq= 0, CH_0, rank 1
4244 12:38:14.466645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4245 12:38:14.466816 ==
4246 12:38:14.466916 DQS Delay:
4247 12:38:14.467007 DQS0 = 0, DQS1 = 0
4248 12:38:14.470857 DQM Delay:
4249 12:38:14.470988 DQM0 = 48, DQM1 = 34
4250 12:38:14.473220 DQ Delay:
4251 12:38:14.476571 DQ0 =41, DQ1 =49, DQ2 =49, DQ3 =49
4252 12:38:14.480474 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4253 12:38:14.480621 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4254 12:38:14.486294 DQ12 =41, DQ13 =33, DQ14 =49, DQ15 =41
4255 12:38:14.486454
4256 12:38:14.486555
4257 12:38:14.486644 ==
4258 12:38:14.490073 Dram Type= 6, Freq= 0, CH_0, rank 1
4259 12:38:14.493181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4260 12:38:14.493317 ==
4261 12:38:14.493415
4262 12:38:14.493505
4263 12:38:14.496317 TX Vref Scan disable
4264 12:38:14.496436 == TX Byte 0 ==
4265 12:38:14.502954 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4266 12:38:14.506591 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4267 12:38:14.509732 == TX Byte 1 ==
4268 12:38:14.512735 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4269 12:38:14.516558 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4270 12:38:14.516705 ==
4271 12:38:14.519308 Dram Type= 6, Freq= 0, CH_0, rank 1
4272 12:38:14.522623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4273 12:38:14.526422 ==
4274 12:38:14.526566
4275 12:38:14.526663
4276 12:38:14.526754 TX Vref Scan disable
4277 12:38:14.529949 == TX Byte 0 ==
4278 12:38:14.532949 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4279 12:38:14.539537 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4280 12:38:14.539701 == TX Byte 1 ==
4281 12:38:14.543251 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4282 12:38:14.550245 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4283 12:38:14.550425
4284 12:38:14.550528 [DATLAT]
4285 12:38:14.550617 Freq=600, CH0 RK1
4286 12:38:14.550707
4287 12:38:14.556399 DATLAT Default: 0x9
4288 12:38:14.556764 0, 0xFFFF, sum = 0
4289 12:38:14.556875 1, 0xFFFF, sum = 0
4290 12:38:14.559482 2, 0xFFFF, sum = 0
4291 12:38:14.559599 3, 0xFFFF, sum = 0
4292 12:38:14.562959 4, 0xFFFF, sum = 0
4293 12:38:14.563075 5, 0xFFFF, sum = 0
4294 12:38:14.566075 6, 0xFFFF, sum = 0
4295 12:38:14.566192 7, 0xFFFF, sum = 0
4296 12:38:14.569880 8, 0x0, sum = 1
4297 12:38:14.570003 9, 0x0, sum = 2
4298 12:38:14.572947 10, 0x0, sum = 3
4299 12:38:14.573080 11, 0x0, sum = 4
4300 12:38:14.573192 best_step = 9
4301 12:38:14.573281
4302 12:38:14.576002 ==
4303 12:38:14.579358 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 12:38:14.582485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 12:38:14.582616 ==
4306 12:38:14.582714 RX Vref Scan: 0
4307 12:38:14.582805
4308 12:38:14.586069 RX Vref 0 -> 0, step: 1
4309 12:38:14.586193
4310 12:38:14.589103 RX Delay -195 -> 252, step: 8
4311 12:38:14.595705 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4312 12:38:14.599121 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4313 12:38:14.601998 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4314 12:38:14.605582 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4315 12:38:14.612412 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4316 12:38:14.615518 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4317 12:38:14.618616 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4318 12:38:14.621872 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4319 12:38:14.625426 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4320 12:38:14.631518 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4321 12:38:14.635089 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4322 12:38:14.638256 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4323 12:38:14.641495 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4324 12:38:14.648257 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4325 12:38:14.651211 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4326 12:38:14.654873 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4327 12:38:14.655016 ==
4328 12:38:14.657787 Dram Type= 6, Freq= 0, CH_0, rank 1
4329 12:38:14.664914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4330 12:38:14.665084 ==
4331 12:38:14.665228 DQS Delay:
4332 12:38:14.668949 DQS0 = 0, DQS1 = 0
4333 12:38:14.669071 DQM Delay:
4334 12:38:14.669197 DQM0 = 40, DQM1 = 33
4335 12:38:14.671218 DQ Delay:
4336 12:38:14.674837 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =36
4337 12:38:14.677589 DQ4 =44, DQ5 =28, DQ6 =52, DQ7 =44
4338 12:38:14.680951 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =28
4339 12:38:14.684417 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4340 12:38:14.684550
4341 12:38:14.684645
4342 12:38:14.690886 [DQSOSCAuto] RK1, (LSB)MR18= 0x453f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4343 12:38:14.694369 CH0 RK1: MR19=808, MR18=453F
4344 12:38:14.700886 CH0_RK1: MR19=0x808, MR18=0x453F, DQSOSC=396, MR23=63, INC=167, DEC=111
4345 12:38:14.704201 [RxdqsGatingPostProcess] freq 600
4346 12:38:14.707509 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4347 12:38:14.710956 Pre-setting of DQS Precalculation
4348 12:38:14.717350 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4349 12:38:14.717524 ==
4350 12:38:14.721011 Dram Type= 6, Freq= 0, CH_1, rank 0
4351 12:38:14.724299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4352 12:38:14.724440 ==
4353 12:38:14.730936 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4354 12:38:14.737371 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4355 12:38:14.740678 [CA 0] Center 36 (6~66) winsize 61
4356 12:38:14.743994 [CA 1] Center 35 (5~66) winsize 62
4357 12:38:14.747014 [CA 2] Center 35 (5~65) winsize 61
4358 12:38:14.750809 [CA 3] Center 34 (4~65) winsize 62
4359 12:38:14.754013 [CA 4] Center 34 (4~65) winsize 62
4360 12:38:14.757776 [CA 5] Center 34 (3~65) winsize 63
4361 12:38:14.757918
4362 12:38:14.760311 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4363 12:38:14.760427
4364 12:38:14.763873 [CATrainingPosCal] consider 1 rank data
4365 12:38:14.767114 u2DelayCellTimex100 = 270/100 ps
4366 12:38:14.770292 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4367 12:38:14.773523 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4368 12:38:14.777035 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4369 12:38:14.781115 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4370 12:38:14.783151 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4371 12:38:14.786560 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4372 12:38:14.786701
4373 12:38:14.792953 CA PerBit enable=1, Macro0, CA PI delay=34
4374 12:38:14.793127
4375 12:38:14.796473 [CBTSetCACLKResult] CA Dly = 34
4376 12:38:14.796602 CS Dly: 4 (0~35)
4377 12:38:14.796698 ==
4378 12:38:14.799765 Dram Type= 6, Freq= 0, CH_1, rank 1
4379 12:38:14.803273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4380 12:38:14.803448 ==
4381 12:38:14.810145 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4382 12:38:14.816494 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4383 12:38:14.819344 [CA 0] Center 36 (6~66) winsize 61
4384 12:38:14.822741 [CA 1] Center 35 (5~66) winsize 62
4385 12:38:14.825868 [CA 2] Center 34 (4~65) winsize 62
4386 12:38:14.829166 [CA 3] Center 34 (3~65) winsize 63
4387 12:38:14.832644 [CA 4] Center 34 (4~65) winsize 62
4388 12:38:14.836081 [CA 5] Center 33 (3~64) winsize 62
4389 12:38:14.836228
4390 12:38:14.839146 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4391 12:38:14.839273
4392 12:38:14.842313 [CATrainingPosCal] consider 2 rank data
4393 12:38:14.845715 u2DelayCellTimex100 = 270/100 ps
4394 12:38:14.849466 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4395 12:38:14.852765 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4396 12:38:14.859140 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4397 12:38:14.862074 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4398 12:38:14.865632 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4399 12:38:14.868674 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4400 12:38:14.868809
4401 12:38:14.872037 CA PerBit enable=1, Macro0, CA PI delay=33
4402 12:38:14.872156
4403 12:38:14.875424 [CBTSetCACLKResult] CA Dly = 33
4404 12:38:14.875546 CS Dly: 4 (0~36)
4405 12:38:14.878408
4406 12:38:14.882386 ----->DramcWriteLeveling(PI) begin...
4407 12:38:14.882537 ==
4408 12:38:14.885131 Dram Type= 6, Freq= 0, CH_1, rank 0
4409 12:38:14.888950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4410 12:38:14.889090 ==
4411 12:38:14.892164 Write leveling (Byte 0): 28 => 28
4412 12:38:14.895150 Write leveling (Byte 1): 31 => 31
4413 12:38:14.898602 DramcWriteLeveling(PI) end<-----
4414 12:38:14.898749
4415 12:38:14.898847 ==
4416 12:38:14.901577 Dram Type= 6, Freq= 0, CH_1, rank 0
4417 12:38:14.904727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4418 12:38:14.904856 ==
4419 12:38:14.908297 [Gating] SW mode calibration
4420 12:38:14.914707 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4421 12:38:14.921921 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4422 12:38:14.924787 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4423 12:38:14.927731 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4424 12:38:14.935045 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4425 12:38:14.937604 0 9 12 | B1->B0 | 3030 2f2f | 1 0 | (1 0) (0 0)
4426 12:38:14.941452 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 12:38:14.947845 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 12:38:14.951215 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4429 12:38:14.954282 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 12:38:14.961404 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 12:38:14.964006 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 12:38:14.967483 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 12:38:14.974393 0 10 12 | B1->B0 | 3131 3636 | 0 0 | (0 0) (0 0)
4434 12:38:14.977132 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 12:38:14.980490 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 12:38:14.987046 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 12:38:14.990645 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 12:38:14.995326 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 12:38:15.000746 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 12:38:15.004177 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 12:38:15.006870 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 12:38:15.014014 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 12:38:15.016736 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 12:38:15.020035 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 12:38:15.026553 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 12:38:15.029808 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 12:38:15.033340 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 12:38:15.039970 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 12:38:15.043254 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 12:38:15.046410 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 12:38:15.053101 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 12:38:15.056444 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 12:38:15.059857 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 12:38:15.066249 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 12:38:15.069782 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 12:38:15.073637 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 12:38:15.079638 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4458 12:38:15.082764 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 12:38:15.086007 Total UI for P1: 0, mck2ui 16
4460 12:38:15.089425 best dqsien dly found for B0: ( 0, 13, 12)
4461 12:38:15.092504 Total UI for P1: 0, mck2ui 16
4462 12:38:15.096466 best dqsien dly found for B1: ( 0, 13, 12)
4463 12:38:15.099165 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4464 12:38:15.102668 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4465 12:38:15.102810
4466 12:38:15.105960 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4467 12:38:15.112540 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4468 12:38:15.112713 [Gating] SW calibration Done
4469 12:38:15.112818 ==
4470 12:38:15.115860 Dram Type= 6, Freq= 0, CH_1, rank 0
4471 12:38:15.122226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4472 12:38:15.122398 ==
4473 12:38:15.122503 RX Vref Scan: 0
4474 12:38:15.122593
4475 12:38:15.125852 RX Vref 0 -> 0, step: 1
4476 12:38:15.125968
4477 12:38:15.128929 RX Delay -230 -> 252, step: 16
4478 12:38:15.131889 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4479 12:38:15.135442 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4480 12:38:15.142616 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4481 12:38:15.145380 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4482 12:38:15.148628 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4483 12:38:15.152265 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4484 12:38:15.155217 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4485 12:38:15.161765 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4486 12:38:15.165018 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4487 12:38:15.168514 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4488 12:38:15.172437 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4489 12:38:15.178451 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4490 12:38:15.181653 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4491 12:38:15.184995 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4492 12:38:15.188184 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4493 12:38:15.195148 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4494 12:38:15.195328 ==
4495 12:38:15.198301 Dram Type= 6, Freq= 0, CH_1, rank 0
4496 12:38:15.201496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4497 12:38:15.201641 ==
4498 12:38:15.201741 DQS Delay:
4499 12:38:15.204791 DQS0 = 0, DQS1 = 0
4500 12:38:15.204914 DQM Delay:
4501 12:38:15.208212 DQM0 = 45, DQM1 = 38
4502 12:38:15.208333 DQ Delay:
4503 12:38:15.211782 DQ0 =57, DQ1 =33, DQ2 =33, DQ3 =41
4504 12:38:15.214678 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4505 12:38:15.217995 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4506 12:38:15.221229 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4507 12:38:15.221390
4508 12:38:15.221515
4509 12:38:15.221619 ==
4510 12:38:15.224932 Dram Type= 6, Freq= 0, CH_1, rank 0
4511 12:38:15.227525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4512 12:38:15.230720 ==
4513 12:38:15.230853
4514 12:38:15.230948
4515 12:38:15.231068 TX Vref Scan disable
4516 12:38:15.234396 == TX Byte 0 ==
4517 12:38:15.237562 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4518 12:38:15.244423 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4519 12:38:15.244682 == TX Byte 1 ==
4520 12:38:15.248075 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4521 12:38:15.254021 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4522 12:38:15.254190 ==
4523 12:38:15.257283 Dram Type= 6, Freq= 0, CH_1, rank 0
4524 12:38:15.260996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4525 12:38:15.261135 ==
4526 12:38:15.261232
4527 12:38:15.261320
4528 12:38:15.263892 TX Vref Scan disable
4529 12:38:15.267268 == TX Byte 0 ==
4530 12:38:15.270539 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4531 12:38:15.273875 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4532 12:38:15.277136 == TX Byte 1 ==
4533 12:38:15.280350 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4534 12:38:15.283687 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4535 12:38:15.283830
4536 12:38:15.283927 [DATLAT]
4537 12:38:15.286881 Freq=600, CH1 RK0
4538 12:38:15.286997
4539 12:38:15.290077 DATLAT Default: 0x9
4540 12:38:15.290194 0, 0xFFFF, sum = 0
4541 12:38:15.293790 1, 0xFFFF, sum = 0
4542 12:38:15.293940 2, 0xFFFF, sum = 0
4543 12:38:15.296818 3, 0xFFFF, sum = 0
4544 12:38:15.296938 4, 0xFFFF, sum = 0
4545 12:38:15.300271 5, 0xFFFF, sum = 0
4546 12:38:15.300403 6, 0xFFFF, sum = 0
4547 12:38:15.303778 7, 0xFFFF, sum = 0
4548 12:38:15.303902 8, 0x0, sum = 1
4549 12:38:15.307383 9, 0x0, sum = 2
4550 12:38:15.307514 10, 0x0, sum = 3
4551 12:38:15.310224 11, 0x0, sum = 4
4552 12:38:15.310351 best_step = 9
4553 12:38:15.310445
4554 12:38:15.310535 ==
4555 12:38:15.314038 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 12:38:15.316776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 12:38:15.316901 ==
4558 12:38:15.320362 RX Vref Scan: 1
4559 12:38:15.320485
4560 12:38:15.323387 RX Vref 0 -> 0, step: 1
4561 12:38:15.323503
4562 12:38:15.323599 RX Delay -179 -> 252, step: 8
4563 12:38:15.326801
4564 12:38:15.326916 Set Vref, RX VrefLevel [Byte0]: 50
4565 12:38:15.330096 [Byte1]: 55
4566 12:38:15.335496
4567 12:38:15.335633 Final RX Vref Byte 0 = 50 to rank0
4568 12:38:15.338035 Final RX Vref Byte 1 = 55 to rank0
4569 12:38:15.341367 Final RX Vref Byte 0 = 50 to rank1
4570 12:38:15.344619 Final RX Vref Byte 1 = 55 to rank1==
4571 12:38:15.347706 Dram Type= 6, Freq= 0, CH_1, rank 0
4572 12:38:15.354552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 12:38:15.354701 ==
4574 12:38:15.354772 DQS Delay:
4575 12:38:15.357614 DQS0 = 0, DQS1 = 0
4576 12:38:15.357706 DQM Delay:
4577 12:38:15.357772 DQM0 = 41, DQM1 = 33
4578 12:38:15.361496 DQ Delay:
4579 12:38:15.364214 DQ0 =48, DQ1 =36, DQ2 =32, DQ3 =40
4580 12:38:15.367423 DQ4 =36, DQ5 =48, DQ6 =56, DQ7 =36
4581 12:38:15.371085 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =28
4582 12:38:15.374421 DQ12 =40, DQ13 =44, DQ14 =40, DQ15 =40
4583 12:38:15.374536
4584 12:38:15.374614
4585 12:38:15.381310 [DQSOSCAuto] RK0, (LSB)MR18= 0x334c, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 400 ps
4586 12:38:15.383913 CH1 RK0: MR19=808, MR18=334C
4587 12:38:15.390338 CH1_RK0: MR19=0x808, MR18=0x334C, DQSOSC=395, MR23=63, INC=168, DEC=112
4588 12:38:15.390504
4589 12:38:15.393812 ----->DramcWriteLeveling(PI) begin...
4590 12:38:15.393926 ==
4591 12:38:15.397660 Dram Type= 6, Freq= 0, CH_1, rank 1
4592 12:38:15.400811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4593 12:38:15.400928 ==
4594 12:38:15.404021 Write leveling (Byte 0): 30 => 30
4595 12:38:15.406722 Write leveling (Byte 1): 30 => 30
4596 12:38:15.410197 DramcWriteLeveling(PI) end<-----
4597 12:38:15.410307
4598 12:38:15.410376 ==
4599 12:38:15.413810 Dram Type= 6, Freq= 0, CH_1, rank 1
4600 12:38:15.420139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4601 12:38:15.420274 ==
4602 12:38:15.420343 [Gating] SW mode calibration
4603 12:38:15.430438 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4604 12:38:15.433328 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4605 12:38:15.436829 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4606 12:38:15.443180 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4607 12:38:15.447324 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4608 12:38:15.450093 0 9 12 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (1 1)
4609 12:38:15.456971 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 12:38:15.460613 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 12:38:15.463066 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4612 12:38:15.470118 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 12:38:15.472980 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 12:38:15.476099 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 12:38:15.482811 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4616 12:38:15.486182 0 10 12 | B1->B0 | 3333 4040 | 1 0 | (0 0) (0 0)
4617 12:38:15.489580 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 12:38:15.496363 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 12:38:15.499821 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 12:38:15.502893 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 12:38:15.509565 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 12:38:15.513278 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 12:38:15.516550 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4624 12:38:15.523099 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4625 12:38:15.526128 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 12:38:15.529911 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 12:38:15.535873 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 12:38:15.539653 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 12:38:15.542857 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 12:38:15.549219 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 12:38:15.552398 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 12:38:15.555303 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 12:38:15.562392 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 12:38:15.565804 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 12:38:15.568645 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 12:38:15.575105 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 12:38:15.578500 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 12:38:15.581611 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 12:38:15.588512 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4640 12:38:15.591892 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 12:38:15.595102 Total UI for P1: 0, mck2ui 16
4642 12:38:15.598301 best dqsien dly found for B0: ( 0, 13, 8)
4643 12:38:15.601590 Total UI for P1: 0, mck2ui 16
4644 12:38:15.604913 best dqsien dly found for B1: ( 0, 13, 10)
4645 12:38:15.608049 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4646 12:38:15.611384 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4647 12:38:15.611510
4648 12:38:15.614445 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4649 12:38:15.622305 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4650 12:38:15.622444 [Gating] SW calibration Done
4651 12:38:15.622514 ==
4652 12:38:15.624602 Dram Type= 6, Freq= 0, CH_1, rank 1
4653 12:38:15.631499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4654 12:38:15.631631 ==
4655 12:38:15.631701 RX Vref Scan: 0
4656 12:38:15.631761
4657 12:38:15.634214 RX Vref 0 -> 0, step: 1
4658 12:38:15.634299
4659 12:38:15.638374 RX Delay -230 -> 252, step: 16
4660 12:38:15.641360 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4661 12:38:15.644627 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4662 12:38:15.651261 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4663 12:38:15.654320 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4664 12:38:15.657573 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4665 12:38:15.661328 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4666 12:38:15.664346 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4667 12:38:15.670996 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4668 12:38:15.674687 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4669 12:38:15.677677 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4670 12:38:15.680709 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4671 12:38:15.687121 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4672 12:38:15.691689 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4673 12:38:15.693902 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4674 12:38:15.697453 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4675 12:38:15.704037 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4676 12:38:15.704185 ==
4677 12:38:15.706931 Dram Type= 6, Freq= 0, CH_1, rank 1
4678 12:38:15.710141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4679 12:38:15.710244 ==
4680 12:38:15.710311 DQS Delay:
4681 12:38:15.713705 DQS0 = 0, DQS1 = 0
4682 12:38:15.713805 DQM Delay:
4683 12:38:15.717163 DQM0 = 43, DQM1 = 38
4684 12:38:15.717260 DQ Delay:
4685 12:38:15.720104 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4686 12:38:15.723786 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4687 12:38:15.726940 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4688 12:38:15.729898 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4689 12:38:15.730034
4690 12:38:15.730131
4691 12:38:15.730198 ==
4692 12:38:15.733800 Dram Type= 6, Freq= 0, CH_1, rank 1
4693 12:38:15.736854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4694 12:38:15.740166 ==
4695 12:38:15.740272
4696 12:38:15.740338
4697 12:38:15.740397 TX Vref Scan disable
4698 12:38:15.743158 == TX Byte 0 ==
4699 12:38:15.746639 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4700 12:38:15.753026 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4701 12:38:15.753197 == TX Byte 1 ==
4702 12:38:15.756376 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4703 12:38:15.763217 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4704 12:38:15.763360 ==
4705 12:38:15.765929 Dram Type= 6, Freq= 0, CH_1, rank 1
4706 12:38:15.769797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4707 12:38:15.769912 ==
4708 12:38:15.769979
4709 12:38:15.770039
4710 12:38:15.772872 TX Vref Scan disable
4711 12:38:15.776240 == TX Byte 0 ==
4712 12:38:15.779774 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4713 12:38:15.783013 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4714 12:38:15.786598 == TX Byte 1 ==
4715 12:38:15.789411 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4716 12:38:15.792452 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4717 12:38:15.792568
4718 12:38:15.792636 [DATLAT]
4719 12:38:15.796028 Freq=600, CH1 RK1
4720 12:38:15.796129
4721 12:38:15.799142 DATLAT Default: 0x9
4722 12:38:15.799237 0, 0xFFFF, sum = 0
4723 12:38:15.802735 1, 0xFFFF, sum = 0
4724 12:38:15.802830 2, 0xFFFF, sum = 0
4725 12:38:15.805935 3, 0xFFFF, sum = 0
4726 12:38:15.806033 4, 0xFFFF, sum = 0
4727 12:38:15.808917 5, 0xFFFF, sum = 0
4728 12:38:15.809013 6, 0xFFFF, sum = 0
4729 12:38:15.812979 7, 0xFFFF, sum = 0
4730 12:38:15.813083 8, 0x0, sum = 1
4731 12:38:15.815700 9, 0x0, sum = 2
4732 12:38:15.815816 10, 0x0, sum = 3
4733 12:38:15.818706 11, 0x0, sum = 4
4734 12:38:15.818842 best_step = 9
4735 12:38:15.818948
4736 12:38:15.819036 ==
4737 12:38:15.822419 Dram Type= 6, Freq= 0, CH_1, rank 1
4738 12:38:15.825886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4739 12:38:15.826038 ==
4740 12:38:15.828506 RX Vref Scan: 0
4741 12:38:15.828607
4742 12:38:15.832071 RX Vref 0 -> 0, step: 1
4743 12:38:15.832172
4744 12:38:15.832236 RX Delay -179 -> 252, step: 8
4745 12:38:15.839802 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4746 12:38:15.843659 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4747 12:38:15.846396 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4748 12:38:15.849855 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4749 12:38:15.856582 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4750 12:38:15.859585 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4751 12:38:15.863649 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4752 12:38:15.866526 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4753 12:38:15.873263 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4754 12:38:15.876089 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4755 12:38:15.879470 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4756 12:38:15.882872 iDelay=205, Bit 11, Center 28 (-131 ~ 188) 320
4757 12:38:15.886701 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4758 12:38:15.893134 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4759 12:38:15.896340 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4760 12:38:15.899939 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4761 12:38:15.900061 ==
4762 12:38:15.902808 Dram Type= 6, Freq= 0, CH_1, rank 1
4763 12:38:15.909366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4764 12:38:15.909504 ==
4765 12:38:15.909573 DQS Delay:
4766 12:38:15.912919 DQS0 = 0, DQS1 = 0
4767 12:38:15.913019 DQM Delay:
4768 12:38:15.913086 DQM0 = 37, DQM1 = 34
4769 12:38:15.916122 DQ Delay:
4770 12:38:15.919491 DQ0 =40, DQ1 =36, DQ2 =24, DQ3 =36
4771 12:38:15.922608 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4772 12:38:15.926117 DQ8 =20, DQ9 =24, DQ10 =40, DQ11 =28
4773 12:38:15.929387 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =44
4774 12:38:15.929494
4775 12:38:15.929562
4776 12:38:15.935944 [DQSOSCAuto] RK1, (LSB)MR18= 0x395d, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4777 12:38:15.939053 CH1 RK1: MR19=808, MR18=395D
4778 12:38:15.945844 CH1_RK1: MR19=0x808, MR18=0x395D, DQSOSC=392, MR23=63, INC=170, DEC=113
4779 12:38:15.948706 [RxdqsGatingPostProcess] freq 600
4780 12:38:15.952274 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4781 12:38:15.955832 Pre-setting of DQS Precalculation
4782 12:38:15.962334 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4783 12:38:15.968663 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4784 12:38:15.975221 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4785 12:38:15.975395
4786 12:38:15.975482
4787 12:38:15.978688 [Calibration Summary] 1200 Mbps
4788 12:38:15.981699 CH 0, Rank 0
4789 12:38:15.981805 SW Impedance : PASS
4790 12:38:15.985766 DUTY Scan : NO K
4791 12:38:15.985874 ZQ Calibration : PASS
4792 12:38:15.988204 Jitter Meter : NO K
4793 12:38:15.992391 CBT Training : PASS
4794 12:38:15.992519 Write leveling : PASS
4795 12:38:15.995552 RX DQS gating : PASS
4796 12:38:15.998115 RX DQ/DQS(RDDQC) : PASS
4797 12:38:15.998209 TX DQ/DQS : PASS
4798 12:38:16.001448 RX DATLAT : PASS
4799 12:38:16.005045 RX DQ/DQS(Engine): PASS
4800 12:38:16.005152 TX OE : NO K
4801 12:38:16.008826 All Pass.
4802 12:38:16.008923
4803 12:38:16.008988 CH 0, Rank 1
4804 12:38:16.011887 SW Impedance : PASS
4805 12:38:16.011977 DUTY Scan : NO K
4806 12:38:16.014948 ZQ Calibration : PASS
4807 12:38:16.018033 Jitter Meter : NO K
4808 12:38:16.018134 CBT Training : PASS
4809 12:38:16.021171 Write leveling : PASS
4810 12:38:16.024785 RX DQS gating : PASS
4811 12:38:16.024888 RX DQ/DQS(RDDQC) : PASS
4812 12:38:16.028106 TX DQ/DQS : PASS
4813 12:38:16.031061 RX DATLAT : PASS
4814 12:38:16.031155 RX DQ/DQS(Engine): PASS
4815 12:38:16.034538 TX OE : NO K
4816 12:38:16.034632 All Pass.
4817 12:38:16.034696
4818 12:38:16.037850 CH 1, Rank 0
4819 12:38:16.037961 SW Impedance : PASS
4820 12:38:16.041457 DUTY Scan : NO K
4821 12:38:16.044321 ZQ Calibration : PASS
4822 12:38:16.044405 Jitter Meter : NO K
4823 12:38:16.048350 CBT Training : PASS
4824 12:38:16.050703 Write leveling : PASS
4825 12:38:16.050796 RX DQS gating : PASS
4826 12:38:16.054291 RX DQ/DQS(RDDQC) : PASS
4827 12:38:16.057747 TX DQ/DQS : PASS
4828 12:38:16.057875 RX DATLAT : PASS
4829 12:38:16.060707 RX DQ/DQS(Engine): PASS
4830 12:38:16.064218 TX OE : NO K
4831 12:38:16.064327 All Pass.
4832 12:38:16.064394
4833 12:38:16.064453 CH 1, Rank 1
4834 12:38:16.067854 SW Impedance : PASS
4835 12:38:16.071067 DUTY Scan : NO K
4836 12:38:16.071185 ZQ Calibration : PASS
4837 12:38:16.073934 Jitter Meter : NO K
4838 12:38:16.074023 CBT Training : PASS
4839 12:38:16.077090 Write leveling : PASS
4840 12:38:16.081108 RX DQS gating : PASS
4841 12:38:16.081224 RX DQ/DQS(RDDQC) : PASS
4842 12:38:16.083659 TX DQ/DQS : PASS
4843 12:38:16.086987 RX DATLAT : PASS
4844 12:38:16.087093 RX DQ/DQS(Engine): PASS
4845 12:38:16.090366 TX OE : NO K
4846 12:38:16.090460 All Pass.
4847 12:38:16.090526
4848 12:38:16.094156 DramC Write-DBI off
4849 12:38:16.097295 PER_BANK_REFRESH: Hybrid Mode
4850 12:38:16.097401 TX_TRACKING: ON
4851 12:38:16.107105 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4852 12:38:16.110471 [FAST_K] Save calibration result to emmc
4853 12:38:16.113914 dramc_set_vcore_voltage set vcore to 662500
4854 12:38:16.116712 Read voltage for 933, 3
4855 12:38:16.116816 Vio18 = 0
4856 12:38:16.116882 Vcore = 662500
4857 12:38:16.120059 Vdram = 0
4858 12:38:16.120154 Vddq = 0
4859 12:38:16.120219 Vmddr = 0
4860 12:38:16.127014 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4861 12:38:16.129948 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4862 12:38:16.133364 MEM_TYPE=3, freq_sel=17
4863 12:38:16.136951 sv_algorithm_assistance_LP4_1600
4864 12:38:16.140782 ============ PULL DRAM RESETB DOWN ============
4865 12:38:16.147388 ========== PULL DRAM RESETB DOWN end =========
4866 12:38:16.150012 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4867 12:38:16.153420 ===================================
4868 12:38:16.156591 LPDDR4 DRAM CONFIGURATION
4869 12:38:16.159619 ===================================
4870 12:38:16.159722 EX_ROW_EN[0] = 0x0
4871 12:38:16.163033 EX_ROW_EN[1] = 0x0
4872 12:38:16.163149 LP4Y_EN = 0x0
4873 12:38:16.166179 WORK_FSP = 0x0
4874 12:38:16.166279 WL = 0x3
4875 12:38:16.169694 RL = 0x3
4876 12:38:16.173065 BL = 0x2
4877 12:38:16.173173 RPST = 0x0
4878 12:38:16.176143 RD_PRE = 0x0
4879 12:38:16.176244 WR_PRE = 0x1
4880 12:38:16.179665 WR_PST = 0x0
4881 12:38:16.179803 DBI_WR = 0x0
4882 12:38:16.182837 DBI_RD = 0x0
4883 12:38:16.182952 OTF = 0x1
4884 12:38:16.185979 ===================================
4885 12:38:16.189439 ===================================
4886 12:38:16.193052 ANA top config
4887 12:38:16.196319 ===================================
4888 12:38:16.196430 DLL_ASYNC_EN = 0
4889 12:38:16.199319 ALL_SLAVE_EN = 1
4890 12:38:16.203171 NEW_RANK_MODE = 1
4891 12:38:16.205807 DLL_IDLE_MODE = 1
4892 12:38:16.205924 LP45_APHY_COMB_EN = 1
4893 12:38:16.209303 TX_ODT_DIS = 1
4894 12:38:16.212730 NEW_8X_MODE = 1
4895 12:38:16.215785 ===================================
4896 12:38:16.218973 ===================================
4897 12:38:16.222178 data_rate = 1866
4898 12:38:16.225814 CKR = 1
4899 12:38:16.228948 DQ_P2S_RATIO = 8
4900 12:38:16.232142 ===================================
4901 12:38:16.232247 CA_P2S_RATIO = 8
4902 12:38:16.235581 DQ_CA_OPEN = 0
4903 12:38:16.238849 DQ_SEMI_OPEN = 0
4904 12:38:16.242223 CA_SEMI_OPEN = 0
4905 12:38:16.245879 CA_FULL_RATE = 0
4906 12:38:16.248425 DQ_CKDIV4_EN = 1
4907 12:38:16.252265 CA_CKDIV4_EN = 1
4908 12:38:16.252391 CA_PREDIV_EN = 0
4909 12:38:16.255228 PH8_DLY = 0
4910 12:38:16.258398 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4911 12:38:16.261994 DQ_AAMCK_DIV = 4
4912 12:38:16.264756 CA_AAMCK_DIV = 4
4913 12:38:16.268358 CA_ADMCK_DIV = 4
4914 12:38:16.268539 DQ_TRACK_CA_EN = 0
4915 12:38:16.271581 CA_PICK = 933
4916 12:38:16.274767 CA_MCKIO = 933
4917 12:38:16.278569 MCKIO_SEMI = 0
4918 12:38:16.281521 PLL_FREQ = 3732
4919 12:38:16.284769 DQ_UI_PI_RATIO = 32
4920 12:38:16.289400 CA_UI_PI_RATIO = 0
4921 12:38:16.291933 ===================================
4922 12:38:16.294637 ===================================
4923 12:38:16.294750 memory_type:LPDDR4
4924 12:38:16.298012 GP_NUM : 10
4925 12:38:16.301472 SRAM_EN : 1
4926 12:38:16.301586 MD32_EN : 0
4927 12:38:16.304514 ===================================
4928 12:38:16.308961 [ANA_INIT] >>>>>>>>>>>>>>
4929 12:38:16.311575 <<<<<< [CONFIGURE PHASE]: ANA_TX
4930 12:38:16.314895 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4931 12:38:16.317591 ===================================
4932 12:38:16.321053 data_rate = 1866,PCW = 0X8f00
4933 12:38:16.324229 ===================================
4934 12:38:16.327593 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4935 12:38:16.331052 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4936 12:38:16.337485 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4937 12:38:16.341491 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4938 12:38:16.344669 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4939 12:38:16.347315 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4940 12:38:16.351179 [ANA_INIT] flow start
4941 12:38:16.354541 [ANA_INIT] PLL >>>>>>>>
4942 12:38:16.354646 [ANA_INIT] PLL <<<<<<<<
4943 12:38:16.357333 [ANA_INIT] MIDPI >>>>>>>>
4944 12:38:16.361100 [ANA_INIT] MIDPI <<<<<<<<
4945 12:38:16.363863 [ANA_INIT] DLL >>>>>>>>
4946 12:38:16.363968 [ANA_INIT] flow end
4947 12:38:16.367641 ============ LP4 DIFF to SE enter ============
4948 12:38:16.373990 ============ LP4 DIFF to SE exit ============
4949 12:38:16.374121 [ANA_INIT] <<<<<<<<<<<<<
4950 12:38:16.377448 [Flow] Enable top DCM control >>>>>
4951 12:38:16.380422 [Flow] Enable top DCM control <<<<<
4952 12:38:16.383907 Enable DLL master slave shuffle
4953 12:38:16.390232 ==============================================================
4954 12:38:16.393836 Gating Mode config
4955 12:38:16.397221 ==============================================================
4956 12:38:16.400342 Config description:
4957 12:38:16.410311 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4958 12:38:16.416879 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4959 12:38:16.419945 SELPH_MODE 0: By rank 1: By Phase
4960 12:38:16.426777 ==============================================================
4961 12:38:16.429962 GAT_TRACK_EN = 1
4962 12:38:16.432947 RX_GATING_MODE = 2
4963 12:38:16.436276 RX_GATING_TRACK_MODE = 2
4964 12:38:16.439807 SELPH_MODE = 1
4965 12:38:16.439928 PICG_EARLY_EN = 1
4966 12:38:16.442733 VALID_LAT_VALUE = 1
4967 12:38:16.449811 ==============================================================
4968 12:38:16.453098 Enter into Gating configuration >>>>
4969 12:38:16.456216 Exit from Gating configuration <<<<
4970 12:38:16.459359 Enter into DVFS_PRE_config >>>>>
4971 12:38:16.469043 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4972 12:38:16.472457 Exit from DVFS_PRE_config <<<<<
4973 12:38:16.475606 Enter into PICG configuration >>>>
4974 12:38:16.479188 Exit from PICG configuration <<<<
4975 12:38:16.482581 [RX_INPUT] configuration >>>>>
4976 12:38:16.485615 [RX_INPUT] configuration <<<<<
4977 12:38:16.492085 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4978 12:38:16.495738 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4979 12:38:16.503120 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4980 12:38:16.510261 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4981 12:38:16.515499 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4982 12:38:16.521798 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4983 12:38:16.525123 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4984 12:38:16.528652 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4985 12:38:16.531913 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4986 12:38:16.538216 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4987 12:38:16.541657 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4988 12:38:16.545662 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4989 12:38:16.548536 ===================================
4990 12:38:16.552316 LPDDR4 DRAM CONFIGURATION
4991 12:38:16.554943 ===================================
4992 12:38:16.558170 EX_ROW_EN[0] = 0x0
4993 12:38:16.558293 EX_ROW_EN[1] = 0x0
4994 12:38:16.561756 LP4Y_EN = 0x0
4995 12:38:16.561855 WORK_FSP = 0x0
4996 12:38:16.564865 WL = 0x3
4997 12:38:16.564967 RL = 0x3
4998 12:38:16.568093 BL = 0x2
4999 12:38:16.568187 RPST = 0x0
5000 12:38:16.571674 RD_PRE = 0x0
5001 12:38:16.571776 WR_PRE = 0x1
5002 12:38:16.574602 WR_PST = 0x0
5003 12:38:16.574692 DBI_WR = 0x0
5004 12:38:16.578373 DBI_RD = 0x0
5005 12:38:16.578471 OTF = 0x1
5006 12:38:16.580958 ===================================
5007 12:38:16.587540 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5008 12:38:16.591131 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5009 12:38:16.594718 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5010 12:38:16.597398 ===================================
5011 12:38:16.601548 LPDDR4 DRAM CONFIGURATION
5012 12:38:16.603869 ===================================
5013 12:38:16.607245 EX_ROW_EN[0] = 0x10
5014 12:38:16.607410 EX_ROW_EN[1] = 0x0
5015 12:38:16.610525 LP4Y_EN = 0x0
5016 12:38:16.610622 WORK_FSP = 0x0
5017 12:38:16.614572 WL = 0x3
5018 12:38:16.614672 RL = 0x3
5019 12:38:16.617171 BL = 0x2
5020 12:38:16.617263 RPST = 0x0
5021 12:38:16.620379 RD_PRE = 0x0
5022 12:38:16.620473 WR_PRE = 0x1
5023 12:38:16.623586 WR_PST = 0x0
5024 12:38:16.623680 DBI_WR = 0x0
5025 12:38:16.627106 DBI_RD = 0x0
5026 12:38:16.630734 OTF = 0x1
5027 12:38:16.633700 ===================================
5028 12:38:16.636762 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5029 12:38:16.642099 nWR fixed to 30
5030 12:38:16.645685 [ModeRegInit_LP4] CH0 RK0
5031 12:38:16.645814 [ModeRegInit_LP4] CH0 RK1
5032 12:38:16.649111 [ModeRegInit_LP4] CH1 RK0
5033 12:38:16.652074 [ModeRegInit_LP4] CH1 RK1
5034 12:38:16.652184 match AC timing 9
5035 12:38:16.658787 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5036 12:38:16.661751 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5037 12:38:16.665314 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5038 12:38:16.672633 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5039 12:38:16.674902 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5040 12:38:16.675001 ==
5041 12:38:16.678333 Dram Type= 6, Freq= 0, CH_0, rank 0
5042 12:38:16.682411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5043 12:38:16.682533 ==
5044 12:38:16.688216 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5045 12:38:16.694838 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5046 12:38:16.698166 [CA 0] Center 37 (7~68) winsize 62
5047 12:38:16.701362 [CA 1] Center 37 (7~68) winsize 62
5048 12:38:16.705005 [CA 2] Center 34 (4~65) winsize 62
5049 12:38:16.708053 [CA 3] Center 34 (4~64) winsize 61
5050 12:38:16.711129 [CA 4] Center 32 (2~63) winsize 62
5051 12:38:16.714760 [CA 5] Center 32 (2~63) winsize 62
5052 12:38:16.714875
5053 12:38:16.718029 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5054 12:38:16.718126
5055 12:38:16.722094 [CATrainingPosCal] consider 1 rank data
5056 12:38:16.725571 u2DelayCellTimex100 = 270/100 ps
5057 12:38:16.728037 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5058 12:38:16.731185 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5059 12:38:16.734800 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5060 12:38:16.741046 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5061 12:38:16.744494 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5062 12:38:16.747591 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5063 12:38:16.747707
5064 12:38:16.750573 CA PerBit enable=1, Macro0, CA PI delay=32
5065 12:38:16.750675
5066 12:38:16.754632 [CBTSetCACLKResult] CA Dly = 32
5067 12:38:16.754745 CS Dly: 5 (0~36)
5068 12:38:16.754812 ==
5069 12:38:16.757294 Dram Type= 6, Freq= 0, CH_0, rank 1
5070 12:38:16.763840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5071 12:38:16.763981 ==
5072 12:38:16.767372 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5073 12:38:16.773907 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5074 12:38:16.778297 [CA 0] Center 37 (7~68) winsize 62
5075 12:38:16.780798 [CA 1] Center 37 (7~68) winsize 62
5076 12:38:16.783692 [CA 2] Center 34 (4~65) winsize 62
5077 12:38:16.787091 [CA 3] Center 34 (3~65) winsize 63
5078 12:38:16.790635 [CA 4] Center 33 (3~64) winsize 62
5079 12:38:16.793769 [CA 5] Center 32 (2~63) winsize 62
5080 12:38:16.793888
5081 12:38:16.796874 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5082 12:38:16.796981
5083 12:38:16.800413 [CATrainingPosCal] consider 2 rank data
5084 12:38:16.803337 u2DelayCellTimex100 = 270/100 ps
5085 12:38:16.806834 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5086 12:38:16.813589 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5087 12:38:16.816890 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5088 12:38:16.820026 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5089 12:38:16.823183 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5090 12:38:16.826589 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5091 12:38:16.826698
5092 12:38:16.830008 CA PerBit enable=1, Macro0, CA PI delay=32
5093 12:38:16.830104
5094 12:38:16.833896 [CBTSetCACLKResult] CA Dly = 32
5095 12:38:16.836781 CS Dly: 6 (0~39)
5096 12:38:16.836903
5097 12:38:16.839928 ----->DramcWriteLeveling(PI) begin...
5098 12:38:16.840023 ==
5099 12:38:16.843489 Dram Type= 6, Freq= 0, CH_0, rank 0
5100 12:38:16.846339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5101 12:38:16.846441 ==
5102 12:38:16.849974 Write leveling (Byte 0): 31 => 31
5103 12:38:16.853060 Write leveling (Byte 1): 26 => 26
5104 12:38:16.857124 DramcWriteLeveling(PI) end<-----
5105 12:38:16.857242
5106 12:38:16.857308 ==
5107 12:38:16.859401 Dram Type= 6, Freq= 0, CH_0, rank 0
5108 12:38:16.863114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5109 12:38:16.863254 ==
5110 12:38:16.867095 [Gating] SW mode calibration
5111 12:38:16.872826 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5112 12:38:16.879243 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5113 12:38:16.882824 0 14 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
5114 12:38:16.889188 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 12:38:16.893352 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5116 12:38:16.895725 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5117 12:38:16.899102 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5118 12:38:16.905729 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5119 12:38:16.908915 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5120 12:38:16.915583 0 14 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
5121 12:38:16.919293 0 15 0 | B1->B0 | 3030 2626 | 0 0 | (0 0) (0 0)
5122 12:38:16.922393 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5123 12:38:16.929190 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5124 12:38:16.932093 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5125 12:38:16.935322 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5126 12:38:16.942207 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 12:38:16.946079 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
5128 12:38:16.948764 0 15 28 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
5129 12:38:16.955606 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5130 12:38:16.958688 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 12:38:16.961839 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 12:38:16.968918 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 12:38:16.971994 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 12:38:16.975016 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 12:38:16.981855 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 12:38:16.985329 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5137 12:38:16.988228 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5138 12:38:16.994749 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5139 12:38:16.998360 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 12:38:17.001075 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 12:38:17.008418 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 12:38:17.011581 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 12:38:17.014593 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 12:38:17.021094 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 12:38:17.024481 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 12:38:17.027327 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 12:38:17.034679 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 12:38:17.038548 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 12:38:17.040669 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 12:38:17.047127 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 12:38:17.050479 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5152 12:38:17.053630 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5153 12:38:17.060515 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5154 12:38:17.060664 Total UI for P1: 0, mck2ui 16
5155 12:38:17.067173 best dqsien dly found for B0: ( 1, 2, 26)
5156 12:38:17.070226 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5157 12:38:17.073644 Total UI for P1: 0, mck2ui 16
5158 12:38:17.076706 best dqsien dly found for B1: ( 1, 3, 2)
5159 12:38:17.080843 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5160 12:38:17.083589 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5161 12:38:17.083688
5162 12:38:17.086999 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5163 12:38:17.090166 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5164 12:38:17.093250 [Gating] SW calibration Done
5165 12:38:17.093343 ==
5166 12:38:17.096880 Dram Type= 6, Freq= 0, CH_0, rank 0
5167 12:38:17.100232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5168 12:38:17.104160 ==
5169 12:38:17.104278 RX Vref Scan: 0
5170 12:38:17.104372
5171 12:38:17.106759 RX Vref 0 -> 0, step: 1
5172 12:38:17.106836
5173 12:38:17.109956 RX Delay -80 -> 252, step: 8
5174 12:38:17.113592 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5175 12:38:17.117170 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5176 12:38:17.119712 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5177 12:38:17.123506 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5178 12:38:17.126652 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5179 12:38:17.132513 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5180 12:38:17.136482 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5181 12:38:17.139223 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5182 12:38:17.142382 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5183 12:38:17.145679 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5184 12:38:17.149432 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5185 12:38:17.156101 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5186 12:38:17.158907 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5187 12:38:17.162284 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5188 12:38:17.166275 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5189 12:38:17.168881 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5190 12:38:17.172568 ==
5191 12:38:17.172682 Dram Type= 6, Freq= 0, CH_0, rank 0
5192 12:38:17.178719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5193 12:38:17.178846 ==
5194 12:38:17.178913 DQS Delay:
5195 12:38:17.182614 DQS0 = 0, DQS1 = 0
5196 12:38:17.182706 DQM Delay:
5197 12:38:17.185286 DQM0 = 100, DQM1 = 89
5198 12:38:17.185364 DQ Delay:
5199 12:38:17.188672 DQ0 =103, DQ1 =103, DQ2 =95, DQ3 =95
5200 12:38:17.192143 DQ4 =103, DQ5 =91, DQ6 =107, DQ7 =103
5201 12:38:17.195346 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =83
5202 12:38:17.199318 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5203 12:38:17.199485
5204 12:38:17.199551
5205 12:38:17.199639 ==
5206 12:38:17.201757 Dram Type= 6, Freq= 0, CH_0, rank 0
5207 12:38:17.205134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5208 12:38:17.205240 ==
5209 12:38:17.208557
5210 12:38:17.208651
5211 12:38:17.208767 TX Vref Scan disable
5212 12:38:17.211954 == TX Byte 0 ==
5213 12:38:17.215651 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5214 12:38:17.218273 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5215 12:38:17.221807 == TX Byte 1 ==
5216 12:38:17.224908 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5217 12:38:17.228881 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5218 12:38:17.228996 ==
5219 12:38:17.231575 Dram Type= 6, Freq= 0, CH_0, rank 0
5220 12:38:17.238310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5221 12:38:17.238460 ==
5222 12:38:17.238528
5223 12:38:17.238588
5224 12:38:17.242432 TX Vref Scan disable
5225 12:38:17.242532 == TX Byte 0 ==
5226 12:38:17.248331 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5227 12:38:17.251341 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5228 12:38:17.251498 == TX Byte 1 ==
5229 12:38:17.257931 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5230 12:38:17.261316 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5231 12:38:17.261462
5232 12:38:17.261541 [DATLAT]
5233 12:38:17.265469 Freq=933, CH0 RK0
5234 12:38:17.265565
5235 12:38:17.265627 DATLAT Default: 0xd
5236 12:38:17.267845 0, 0xFFFF, sum = 0
5237 12:38:17.267944 1, 0xFFFF, sum = 0
5238 12:38:17.271222 2, 0xFFFF, sum = 0
5239 12:38:17.271336 3, 0xFFFF, sum = 0
5240 12:38:17.274257 4, 0xFFFF, sum = 0
5241 12:38:17.274347 5, 0xFFFF, sum = 0
5242 12:38:17.278344 6, 0xFFFF, sum = 0
5243 12:38:17.281502 7, 0xFFFF, sum = 0
5244 12:38:17.281690 8, 0xFFFF, sum = 0
5245 12:38:17.284585 9, 0xFFFF, sum = 0
5246 12:38:17.284686 10, 0x0, sum = 1
5247 12:38:17.287561 11, 0x0, sum = 2
5248 12:38:17.287699 12, 0x0, sum = 3
5249 12:38:17.287780 13, 0x0, sum = 4
5250 12:38:17.290925 best_step = 11
5251 12:38:17.291029
5252 12:38:17.291095 ==
5253 12:38:17.293967 Dram Type= 6, Freq= 0, CH_0, rank 0
5254 12:38:17.297610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5255 12:38:17.297736 ==
5256 12:38:17.300610 RX Vref Scan: 1
5257 12:38:17.300702
5258 12:38:17.305099 RX Vref 0 -> 0, step: 1
5259 12:38:17.305271
5260 12:38:17.305338 RX Delay -53 -> 252, step: 4
5261 12:38:17.305399
5262 12:38:17.307474 Set Vref, RX VrefLevel [Byte0]: 54
5263 12:38:17.310703 [Byte1]: 59
5264 12:38:17.315279
5265 12:38:17.315444 Final RX Vref Byte 0 = 54 to rank0
5266 12:38:17.318491 Final RX Vref Byte 1 = 59 to rank0
5267 12:38:17.322521 Final RX Vref Byte 0 = 54 to rank1
5268 12:38:17.325254 Final RX Vref Byte 1 = 59 to rank1==
5269 12:38:17.328345 Dram Type= 6, Freq= 0, CH_0, rank 0
5270 12:38:17.334853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5271 12:38:17.334990 ==
5272 12:38:17.335082 DQS Delay:
5273 12:38:17.338967 DQS0 = 0, DQS1 = 0
5274 12:38:17.339109 DQM Delay:
5275 12:38:17.339176 DQM0 = 99, DQM1 = 87
5276 12:38:17.341673 DQ Delay:
5277 12:38:17.345196 DQ0 =100, DQ1 =98, DQ2 =94, DQ3 =96
5278 12:38:17.348212 DQ4 =100, DQ5 =90, DQ6 =108, DQ7 =106
5279 12:38:17.352035 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =84
5280 12:38:17.354814 DQ12 =96, DQ13 =92, DQ14 =96, DQ15 =94
5281 12:38:17.354944
5282 12:38:17.355035
5283 12:38:17.361842 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b15, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
5284 12:38:17.365606 CH0 RK0: MR19=505, MR18=1B15
5285 12:38:17.371684 CH0_RK0: MR19=0x505, MR18=0x1B15, DQSOSC=413, MR23=63, INC=63, DEC=42
5286 12:38:17.371943
5287 12:38:17.374953 ----->DramcWriteLeveling(PI) begin...
5288 12:38:17.375051 ==
5289 12:38:17.378295 Dram Type= 6, Freq= 0, CH_0, rank 1
5290 12:38:17.381316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5291 12:38:17.381417 ==
5292 12:38:17.384390 Write leveling (Byte 0): 32 => 32
5293 12:38:17.387465 Write leveling (Byte 1): 31 => 31
5294 12:38:17.391148 DramcWriteLeveling(PI) end<-----
5295 12:38:17.391302
5296 12:38:17.391419 ==
5297 12:38:17.394263 Dram Type= 6, Freq= 0, CH_0, rank 1
5298 12:38:17.401040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5299 12:38:17.401192 ==
5300 12:38:17.401263 [Gating] SW mode calibration
5301 12:38:17.410663 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5302 12:38:17.414216 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5303 12:38:17.420662 0 14 0 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
5304 12:38:17.423937 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5305 12:38:17.426933 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5306 12:38:17.433709 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 12:38:17.437051 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5308 12:38:17.440991 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 12:38:17.446720 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 12:38:17.450215 0 14 28 | B1->B0 | 3333 2a2a | 1 0 | (1 0) (1 0)
5311 12:38:17.453249 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
5312 12:38:17.459734 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5313 12:38:17.463112 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 12:38:17.467040 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5315 12:38:17.473075 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5316 12:38:17.476407 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 12:38:17.479560 0 15 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
5318 12:38:17.486545 0 15 28 | B1->B0 | 2c2c 3b3b | 0 0 | (0 0) (0 0)
5319 12:38:17.490561 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5320 12:38:17.493149 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 12:38:17.499398 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 12:38:17.503011 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 12:38:17.505938 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 12:38:17.512785 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 12:38:17.516330 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 12:38:17.519746 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5327 12:38:17.525802 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5328 12:38:17.530583 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 12:38:17.532495 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 12:38:17.539753 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 12:38:17.542553 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 12:38:17.545588 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 12:38:17.553151 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 12:38:17.555572 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 12:38:17.559066 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 12:38:17.565546 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 12:38:17.568507 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 12:38:17.571750 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 12:38:17.578492 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 12:38:17.581717 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 12:38:17.584826 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 12:38:17.591570 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5343 12:38:17.594495 Total UI for P1: 0, mck2ui 16
5344 12:38:17.597985 best dqsien dly found for B0: ( 1, 2, 26)
5345 12:38:17.601351 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 12:38:17.604830 Total UI for P1: 0, mck2ui 16
5347 12:38:17.608232 best dqsien dly found for B1: ( 1, 2, 28)
5348 12:38:17.611296 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5349 12:38:17.614470 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5350 12:38:17.614580
5351 12:38:17.618062 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5352 12:38:17.621105 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5353 12:38:17.624121 [Gating] SW calibration Done
5354 12:38:17.624225 ==
5355 12:38:17.627531 Dram Type= 6, Freq= 0, CH_0, rank 1
5356 12:38:17.634711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5357 12:38:17.634853 ==
5358 12:38:17.634924 RX Vref Scan: 0
5359 12:38:17.634984
5360 12:38:17.637755 RX Vref 0 -> 0, step: 1
5361 12:38:17.637844
5362 12:38:17.640861 RX Delay -80 -> 252, step: 8
5363 12:38:17.644069 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5364 12:38:17.647302 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5365 12:38:17.650924 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5366 12:38:17.654789 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5367 12:38:17.660483 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5368 12:38:17.663593 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5369 12:38:17.667566 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5370 12:38:17.670310 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5371 12:38:17.673837 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5372 12:38:17.676958 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5373 12:38:17.683516 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5374 12:38:17.686679 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5375 12:38:17.690328 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5376 12:38:17.693535 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5377 12:38:17.696644 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5378 12:38:17.703207 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5379 12:38:17.703404 ==
5380 12:38:17.707329 Dram Type= 6, Freq= 0, CH_0, rank 1
5381 12:38:17.710251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5382 12:38:17.710356 ==
5383 12:38:17.710424 DQS Delay:
5384 12:38:17.713626 DQS0 = 0, DQS1 = 0
5385 12:38:17.713719 DQM Delay:
5386 12:38:17.716750 DQM0 = 97, DQM1 = 91
5387 12:38:17.716848 DQ Delay:
5388 12:38:17.719773 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5389 12:38:17.723082 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5390 12:38:17.726223 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5391 12:38:17.730016 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5392 12:38:17.730165
5393 12:38:17.730231
5394 12:38:17.730290 ==
5395 12:38:17.733124 Dram Type= 6, Freq= 0, CH_0, rank 1
5396 12:38:17.736502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5397 12:38:17.739724 ==
5398 12:38:17.739832
5399 12:38:17.739900
5400 12:38:17.739960 TX Vref Scan disable
5401 12:38:17.743037 == TX Byte 0 ==
5402 12:38:17.746013 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5403 12:38:17.749537 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5404 12:38:17.753394 == TX Byte 1 ==
5405 12:38:17.755787 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5406 12:38:17.759479 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5407 12:38:17.762337 ==
5408 12:38:17.765769 Dram Type= 6, Freq= 0, CH_0, rank 1
5409 12:38:17.769253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5410 12:38:17.769364 ==
5411 12:38:17.769431
5412 12:38:17.769491
5413 12:38:17.772730 TX Vref Scan disable
5414 12:38:17.772823 == TX Byte 0 ==
5415 12:38:17.778967 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5416 12:38:17.782223 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5417 12:38:17.782331 == TX Byte 1 ==
5418 12:38:17.788772 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5419 12:38:17.791844 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5420 12:38:17.791956
5421 12:38:17.792023 [DATLAT]
5422 12:38:17.795278 Freq=933, CH0 RK1
5423 12:38:17.795398
5424 12:38:17.795479 DATLAT Default: 0xb
5425 12:38:17.798439 0, 0xFFFF, sum = 0
5426 12:38:17.798539 1, 0xFFFF, sum = 0
5427 12:38:17.801996 2, 0xFFFF, sum = 0
5428 12:38:17.805277 3, 0xFFFF, sum = 0
5429 12:38:17.805383 4, 0xFFFF, sum = 0
5430 12:38:17.808643 5, 0xFFFF, sum = 0
5431 12:38:17.808775 6, 0xFFFF, sum = 0
5432 12:38:17.811404 7, 0xFFFF, sum = 0
5433 12:38:17.811508 8, 0xFFFF, sum = 0
5434 12:38:17.814984 9, 0xFFFF, sum = 0
5435 12:38:17.815088 10, 0x0, sum = 1
5436 12:38:17.818594 11, 0x0, sum = 2
5437 12:38:17.818696 12, 0x0, sum = 3
5438 12:38:17.821660 13, 0x0, sum = 4
5439 12:38:17.821753 best_step = 11
5440 12:38:17.821818
5441 12:38:17.821877 ==
5442 12:38:17.824882 Dram Type= 6, Freq= 0, CH_0, rank 1
5443 12:38:17.828490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5444 12:38:17.828614 ==
5445 12:38:17.831328 RX Vref Scan: 0
5446 12:38:17.831474
5447 12:38:17.834641 RX Vref 0 -> 0, step: 1
5448 12:38:17.834761
5449 12:38:17.834853 RX Delay -53 -> 252, step: 4
5450 12:38:17.842514 iDelay=195, Bit 0, Center 96 (11 ~ 182) 172
5451 12:38:17.846058 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5452 12:38:17.849752 iDelay=195, Bit 2, Center 94 (7 ~ 182) 176
5453 12:38:17.852544 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5454 12:38:17.855996 iDelay=195, Bit 4, Center 100 (11 ~ 190) 180
5455 12:38:17.863183 iDelay=195, Bit 5, Center 86 (-5 ~ 178) 184
5456 12:38:17.865465 iDelay=195, Bit 6, Center 106 (19 ~ 194) 176
5457 12:38:17.869279 iDelay=195, Bit 7, Center 106 (19 ~ 194) 176
5458 12:38:17.872058 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5459 12:38:17.876065 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5460 12:38:17.878888 iDelay=195, Bit 10, Center 90 (-1 ~ 182) 184
5461 12:38:17.885465 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5462 12:38:17.889058 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5463 12:38:17.892168 iDelay=195, Bit 13, Center 96 (7 ~ 186) 180
5464 12:38:17.896865 iDelay=195, Bit 14, Center 98 (7 ~ 190) 184
5465 12:38:17.898780 iDelay=195, Bit 15, Center 98 (11 ~ 186) 176
5466 12:38:17.901873 ==
5467 12:38:17.902007 Dram Type= 6, Freq= 0, CH_0, rank 1
5468 12:38:17.908432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5469 12:38:17.908571 ==
5470 12:38:17.908642 DQS Delay:
5471 12:38:17.911709 DQS0 = 0, DQS1 = 0
5472 12:38:17.911797 DQM Delay:
5473 12:38:17.914948 DQM0 = 97, DQM1 = 89
5474 12:38:17.915029 DQ Delay:
5475 12:38:17.918538 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5476 12:38:17.922170 DQ4 =100, DQ5 =86, DQ6 =106, DQ7 =106
5477 12:38:17.925235 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =84
5478 12:38:17.928184 DQ12 =94, DQ13 =96, DQ14 =98, DQ15 =98
5479 12:38:17.928273
5480 12:38:17.928334
5481 12:38:17.935040 [DQSOSCAuto] RK1, (LSB)MR18= 0x1511, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5482 12:38:17.938160 CH0 RK1: MR19=505, MR18=1511
5483 12:38:17.944816 CH0_RK1: MR19=0x505, MR18=0x1511, DQSOSC=415, MR23=63, INC=62, DEC=41
5484 12:38:17.948196 [RxdqsGatingPostProcess] freq 933
5485 12:38:17.955104 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5486 12:38:17.958068 best DQS0 dly(2T, 0.5T) = (0, 10)
5487 12:38:17.961148 best DQS1 dly(2T, 0.5T) = (0, 11)
5488 12:38:17.964607 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5489 12:38:17.967465 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5490 12:38:17.967561 best DQS0 dly(2T, 0.5T) = (0, 10)
5491 12:38:17.970867 best DQS1 dly(2T, 0.5T) = (0, 10)
5492 12:38:17.974377 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5493 12:38:17.978290 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5494 12:38:17.981272 Pre-setting of DQS Precalculation
5495 12:38:17.987706 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5496 12:38:17.987848 ==
5497 12:38:17.991124 Dram Type= 6, Freq= 0, CH_1, rank 0
5498 12:38:17.994028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5499 12:38:17.994151 ==
5500 12:38:18.001316 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5501 12:38:18.007637 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5502 12:38:18.010630 [CA 0] Center 37 (7~67) winsize 61
5503 12:38:18.013652 [CA 1] Center 36 (6~67) winsize 62
5504 12:38:18.018206 [CA 2] Center 35 (5~65) winsize 61
5505 12:38:18.020238 [CA 3] Center 34 (4~65) winsize 62
5506 12:38:18.024045 [CA 4] Center 34 (4~65) winsize 62
5507 12:38:18.027155 [CA 5] Center 33 (3~64) winsize 62
5508 12:38:18.027264
5509 12:38:18.030093 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5510 12:38:18.030181
5511 12:38:18.034382 [CATrainingPosCal] consider 1 rank data
5512 12:38:18.037055 u2DelayCellTimex100 = 270/100 ps
5513 12:38:18.040098 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5514 12:38:18.043457 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5515 12:38:18.046772 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5516 12:38:18.050169 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5517 12:38:18.053356 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5518 12:38:18.056621 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5519 12:38:18.059923
5520 12:38:18.063299 CA PerBit enable=1, Macro0, CA PI delay=33
5521 12:38:18.063460
5522 12:38:18.066838 [CBTSetCACLKResult] CA Dly = 33
5523 12:38:18.066938 CS Dly: 6 (0~37)
5524 12:38:18.067017 ==
5525 12:38:18.069851 Dram Type= 6, Freq= 0, CH_1, rank 1
5526 12:38:18.073075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5527 12:38:18.073175 ==
5528 12:38:18.079645 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5529 12:38:18.086371 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5530 12:38:18.089569 [CA 0] Center 36 (6~67) winsize 62
5531 12:38:18.093114 [CA 1] Center 36 (6~67) winsize 62
5532 12:38:18.096820 [CA 2] Center 34 (4~65) winsize 62
5533 12:38:18.099199 [CA 3] Center 33 (3~64) winsize 62
5534 12:38:18.102919 [CA 4] Center 34 (4~64) winsize 61
5535 12:38:18.106057 [CA 5] Center 33 (3~64) winsize 62
5536 12:38:18.106172
5537 12:38:18.109180 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5538 12:38:18.109304
5539 12:38:18.112365 [CATrainingPosCal] consider 2 rank data
5540 12:38:18.116216 u2DelayCellTimex100 = 270/100 ps
5541 12:38:18.119480 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5542 12:38:18.122654 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5543 12:38:18.125736 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5544 12:38:18.132781 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5545 12:38:18.135684 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5546 12:38:18.138735 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5547 12:38:18.138856
5548 12:38:18.142047 CA PerBit enable=1, Macro0, CA PI delay=33
5549 12:38:18.142148
5550 12:38:18.145558 [CBTSetCACLKResult] CA Dly = 33
5551 12:38:18.145662 CS Dly: 7 (0~39)
5552 12:38:18.145728
5553 12:38:18.148627 ----->DramcWriteLeveling(PI) begin...
5554 12:38:18.151975 ==
5555 12:38:18.155072 Dram Type= 6, Freq= 0, CH_1, rank 0
5556 12:38:18.158636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5557 12:38:18.158772 ==
5558 12:38:18.161732 Write leveling (Byte 0): 25 => 25
5559 12:38:18.165471 Write leveling (Byte 1): 27 => 27
5560 12:38:18.168370 DramcWriteLeveling(PI) end<-----
5561 12:38:18.168476
5562 12:38:18.168544 ==
5563 12:38:18.172764 Dram Type= 6, Freq= 0, CH_1, rank 0
5564 12:38:18.175356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5565 12:38:18.175522 ==
5566 12:38:18.178854 [Gating] SW mode calibration
5567 12:38:18.184833 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5568 12:38:18.191526 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5569 12:38:18.194750 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 12:38:18.197947 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5571 12:38:18.206395 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5572 12:38:18.208008 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 12:38:18.211539 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5574 12:38:18.218147 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5575 12:38:18.221262 0 14 24 | B1->B0 | 3434 3030 | 0 1 | (0 0) (1 0)
5576 12:38:18.224655 0 14 28 | B1->B0 | 2525 2424 | 0 0 | (1 0) (0 0)
5577 12:38:18.231094 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 12:38:18.235165 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 12:38:18.237538 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 12:38:18.244520 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 12:38:18.247897 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5582 12:38:18.251092 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 12:38:18.258042 0 15 24 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
5584 12:38:18.261758 0 15 28 | B1->B0 | 3b3b 4444 | 0 0 | (0 0) (0 0)
5585 12:38:18.264802 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 12:38:18.270875 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 12:38:18.274577 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 12:38:18.277387 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 12:38:18.284058 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 12:38:18.287814 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 12:38:18.290667 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 12:38:18.297299 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5593 12:38:18.300786 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 12:38:18.303609 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 12:38:18.310234 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 12:38:18.313643 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 12:38:18.317095 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 12:38:18.323578 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 12:38:18.327016 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 12:38:18.330623 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 12:38:18.336630 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 12:38:18.340497 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 12:38:18.343523 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 12:38:18.350413 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 12:38:18.353089 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 12:38:18.357007 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 12:38:18.363011 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 12:38:18.366329 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 12:38:18.369609 Total UI for P1: 0, mck2ui 16
5610 12:38:18.374139 best dqsien dly found for B0: ( 1, 2, 26)
5611 12:38:18.376298 Total UI for P1: 0, mck2ui 16
5612 12:38:18.379659 best dqsien dly found for B1: ( 1, 2, 26)
5613 12:38:18.383429 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5614 12:38:18.386088 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5615 12:38:18.386208
5616 12:38:18.389657 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5617 12:38:18.392814 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5618 12:38:18.395787 [Gating] SW calibration Done
5619 12:38:18.395896 ==
5620 12:38:18.399910 Dram Type= 6, Freq= 0, CH_1, rank 0
5621 12:38:18.403130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5622 12:38:18.405978 ==
5623 12:38:18.406100 RX Vref Scan: 0
5624 12:38:18.406169
5625 12:38:18.409289 RX Vref 0 -> 0, step: 1
5626 12:38:18.409380
5627 12:38:18.409444 RX Delay -80 -> 252, step: 8
5628 12:38:18.416025 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5629 12:38:18.419265 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5630 12:38:18.422441 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5631 12:38:18.426186 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5632 12:38:18.429622 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5633 12:38:18.432605 iDelay=208, Bit 5, Center 103 (8 ~ 199) 192
5634 12:38:18.439214 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5635 12:38:18.442536 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5636 12:38:18.446659 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5637 12:38:18.449009 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5638 12:38:18.453238 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5639 12:38:18.458814 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5640 12:38:18.462209 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5641 12:38:18.465524 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5642 12:38:18.469542 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5643 12:38:18.472008 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5644 12:38:18.475721 ==
5645 12:38:18.475888 Dram Type= 6, Freq= 0, CH_1, rank 0
5646 12:38:18.482288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5647 12:38:18.482422 ==
5648 12:38:18.482492 DQS Delay:
5649 12:38:18.485091 DQS0 = 0, DQS1 = 0
5650 12:38:18.485185 DQM Delay:
5651 12:38:18.488906 DQM0 = 97, DQM1 = 93
5652 12:38:18.489008 DQ Delay:
5653 12:38:18.491917 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =99
5654 12:38:18.495148 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5655 12:38:18.498467 DQ8 =79, DQ9 =87, DQ10 =91, DQ11 =87
5656 12:38:18.502151 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =103
5657 12:38:18.502267
5658 12:38:18.502358
5659 12:38:18.502444 ==
5660 12:38:18.504893 Dram Type= 6, Freq= 0, CH_1, rank 0
5661 12:38:18.508832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5662 12:38:18.508941 ==
5663 12:38:18.511669
5664 12:38:18.511744
5665 12:38:18.511833 TX Vref Scan disable
5666 12:38:18.514816 == TX Byte 0 ==
5667 12:38:18.518273 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5668 12:38:18.521316 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5669 12:38:18.524708 == TX Byte 1 ==
5670 12:38:18.528088 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5671 12:38:18.531615 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5672 12:38:18.535089 ==
5673 12:38:18.535204 Dram Type= 6, Freq= 0, CH_1, rank 0
5674 12:38:18.541421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5675 12:38:18.541525 ==
5676 12:38:18.541609
5677 12:38:18.541684
5678 12:38:18.544291 TX Vref Scan disable
5679 12:38:18.544389 == TX Byte 0 ==
5680 12:38:18.551243 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5681 12:38:18.554195 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5682 12:38:18.554297 == TX Byte 1 ==
5683 12:38:18.560855 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5684 12:38:18.564011 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5685 12:38:18.564110
5686 12:38:18.564196 [DATLAT]
5687 12:38:18.567663 Freq=933, CH1 RK0
5688 12:38:18.567767
5689 12:38:18.567853 DATLAT Default: 0xd
5690 12:38:18.570615 0, 0xFFFF, sum = 0
5691 12:38:18.570695 1, 0xFFFF, sum = 0
5692 12:38:18.573783 2, 0xFFFF, sum = 0
5693 12:38:18.573866 3, 0xFFFF, sum = 0
5694 12:38:18.577456 4, 0xFFFF, sum = 0
5695 12:38:18.580760 5, 0xFFFF, sum = 0
5696 12:38:18.580850 6, 0xFFFF, sum = 0
5697 12:38:18.583586 7, 0xFFFF, sum = 0
5698 12:38:18.583672 8, 0xFFFF, sum = 0
5699 12:38:18.587281 9, 0xFFFF, sum = 0
5700 12:38:18.587394 10, 0x0, sum = 1
5701 12:38:18.590718 11, 0x0, sum = 2
5702 12:38:18.590805 12, 0x0, sum = 3
5703 12:38:18.593595 13, 0x0, sum = 4
5704 12:38:18.593681 best_step = 11
5705 12:38:18.593746
5706 12:38:18.593866 ==
5707 12:38:18.596842 Dram Type= 6, Freq= 0, CH_1, rank 0
5708 12:38:18.600120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5709 12:38:18.600221 ==
5710 12:38:18.603493 RX Vref Scan: 1
5711 12:38:18.603580
5712 12:38:18.606736 RX Vref 0 -> 0, step: 1
5713 12:38:18.606824
5714 12:38:18.606890 RX Delay -61 -> 252, step: 4
5715 12:38:18.606951
5716 12:38:18.609865 Set Vref, RX VrefLevel [Byte0]: 50
5717 12:38:18.613178 [Byte1]: 55
5718 12:38:18.618414
5719 12:38:18.618518 Final RX Vref Byte 0 = 50 to rank0
5720 12:38:18.621586 Final RX Vref Byte 1 = 55 to rank0
5721 12:38:18.624714 Final RX Vref Byte 0 = 50 to rank1
5722 12:38:18.627891 Final RX Vref Byte 1 = 55 to rank1==
5723 12:38:18.632050 Dram Type= 6, Freq= 0, CH_1, rank 0
5724 12:38:18.638861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 12:38:18.638979 ==
5726 12:38:18.639048 DQS Delay:
5727 12:38:18.639110 DQS0 = 0, DQS1 = 0
5728 12:38:18.641464 DQM Delay:
5729 12:38:18.641548 DQM0 = 96, DQM1 = 94
5730 12:38:18.645335 DQ Delay:
5731 12:38:18.648339 DQ0 =104, DQ1 =92, DQ2 =86, DQ3 =96
5732 12:38:18.652234 DQ4 =92, DQ5 =106, DQ6 =106, DQ7 =92
5733 12:38:18.654617 DQ8 =80, DQ9 =86, DQ10 =90, DQ11 =88
5734 12:38:18.657917 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =102
5735 12:38:18.658019
5736 12:38:18.658087
5737 12:38:18.664754 [DQSOSCAuto] RK0, (LSB)MR18= 0x919, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 419 ps
5738 12:38:18.667768 CH1 RK0: MR19=505, MR18=919
5739 12:38:18.674573 CH1_RK0: MR19=0x505, MR18=0x919, DQSOSC=413, MR23=63, INC=63, DEC=42
5740 12:38:18.674692
5741 12:38:18.678094 ----->DramcWriteLeveling(PI) begin...
5742 12:38:18.678183 ==
5743 12:38:18.680949 Dram Type= 6, Freq= 0, CH_1, rank 1
5744 12:38:18.684948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5745 12:38:18.685042 ==
5746 12:38:18.687826 Write leveling (Byte 0): 29 => 29
5747 12:38:18.691147 Write leveling (Byte 1): 29 => 29
5748 12:38:18.694870 DramcWriteLeveling(PI) end<-----
5749 12:38:18.694964
5750 12:38:18.695029 ==
5751 12:38:18.697454 Dram Type= 6, Freq= 0, CH_1, rank 1
5752 12:38:18.701265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5753 12:38:18.704328 ==
5754 12:38:18.704427 [Gating] SW mode calibration
5755 12:38:18.714346 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5756 12:38:18.717128 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5757 12:38:18.720883 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 12:38:18.727232 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 12:38:18.730521 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5760 12:38:18.733780 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5761 12:38:18.740319 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5762 12:38:18.743955 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5763 12:38:18.746937 0 14 24 | B1->B0 | 3232 2e2e | 1 0 | (1 0) (1 0)
5764 12:38:18.753936 0 14 28 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
5765 12:38:18.757557 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 12:38:18.760238 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 12:38:18.767003 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5768 12:38:18.770655 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5769 12:38:18.773130 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5770 12:38:18.779804 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5771 12:38:18.783344 0 15 24 | B1->B0 | 2525 3939 | 0 0 | (0 0) (0 0)
5772 12:38:18.786634 0 15 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5773 12:38:18.793203 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 12:38:18.796271 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 12:38:18.799385 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 12:38:18.806003 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 12:38:18.809732 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 12:38:18.812906 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5779 12:38:18.819227 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5780 12:38:18.823133 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5781 12:38:18.826055 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 12:38:18.832334 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 12:38:18.835881 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 12:38:18.839356 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 12:38:18.845435 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 12:38:18.849031 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 12:38:18.852409 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 12:38:18.858959 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 12:38:18.861849 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 12:38:18.869709 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 12:38:18.871984 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 12:38:18.875477 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 12:38:18.881595 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 12:38:18.885433 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 12:38:18.888487 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5796 12:38:18.892244 Total UI for P1: 0, mck2ui 16
5797 12:38:18.895506 best dqsien dly found for B0: ( 1, 2, 22)
5798 12:38:18.898184 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 12:38:18.901558 Total UI for P1: 0, mck2ui 16
5800 12:38:18.904774 best dqsien dly found for B1: ( 1, 2, 24)
5801 12:38:18.912075 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5802 12:38:18.914731 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5803 12:38:18.914839
5804 12:38:18.918144 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5805 12:38:18.921761 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5806 12:38:18.924870 [Gating] SW calibration Done
5807 12:38:18.924980 ==
5808 12:38:18.928118 Dram Type= 6, Freq= 0, CH_1, rank 1
5809 12:38:18.931441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5810 12:38:18.931535 ==
5811 12:38:18.934674 RX Vref Scan: 0
5812 12:38:18.934782
5813 12:38:18.934874 RX Vref 0 -> 0, step: 1
5814 12:38:18.934967
5815 12:38:18.937680 RX Delay -80 -> 252, step: 8
5816 12:38:18.941506 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5817 12:38:18.947742 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5818 12:38:18.951092 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5819 12:38:18.954250 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5820 12:38:18.957472 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5821 12:38:18.960895 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5822 12:38:18.964439 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5823 12:38:18.970749 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5824 12:38:18.974325 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5825 12:38:18.977555 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5826 12:38:18.980799 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5827 12:38:18.984104 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5828 12:38:18.990625 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5829 12:38:18.994173 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5830 12:38:18.997472 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5831 12:38:19.000058 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5832 12:38:19.000159 ==
5833 12:38:19.003520 Dram Type= 6, Freq= 0, CH_1, rank 1
5834 12:38:19.009889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5835 12:38:19.010000 ==
5836 12:38:19.010084 DQS Delay:
5837 12:38:19.010159 DQS0 = 0, DQS1 = 0
5838 12:38:19.013209 DQM Delay:
5839 12:38:19.013296 DQM0 = 96, DQM1 = 93
5840 12:38:19.016739 DQ Delay:
5841 12:38:19.020008 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =91
5842 12:38:19.023647 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5843 12:38:19.026850 DQ8 =79, DQ9 =87, DQ10 =91, DQ11 =87
5844 12:38:19.029895 DQ12 =103, DQ13 =103, DQ14 =95, DQ15 =103
5845 12:38:19.029978
5846 12:38:19.030105
5847 12:38:19.030196 ==
5848 12:38:19.033299 Dram Type= 6, Freq= 0, CH_1, rank 1
5849 12:38:19.036211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5850 12:38:19.036289 ==
5851 12:38:19.036370
5852 12:38:19.036430
5853 12:38:19.039699 TX Vref Scan disable
5854 12:38:19.043469 == TX Byte 0 ==
5855 12:38:19.046432 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5856 12:38:19.049492 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5857 12:38:19.053355 == TX Byte 1 ==
5858 12:38:19.056424 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5859 12:38:19.059716 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5860 12:38:19.059793 ==
5861 12:38:19.063121 Dram Type= 6, Freq= 0, CH_1, rank 1
5862 12:38:19.069486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5863 12:38:19.069574 ==
5864 12:38:19.069639
5865 12:38:19.069700
5866 12:38:19.069759 TX Vref Scan disable
5867 12:38:19.072974 == TX Byte 0 ==
5868 12:38:19.077129 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5869 12:38:19.083582 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5870 12:38:19.083678 == TX Byte 1 ==
5871 12:38:19.086501 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5872 12:38:19.092973 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5873 12:38:19.093065
5874 12:38:19.093131 [DATLAT]
5875 12:38:19.093191 Freq=933, CH1 RK1
5876 12:38:19.093250
5877 12:38:19.096335 DATLAT Default: 0xb
5878 12:38:19.096418 0, 0xFFFF, sum = 0
5879 12:38:19.099827 1, 0xFFFF, sum = 0
5880 12:38:19.102846 2, 0xFFFF, sum = 0
5881 12:38:19.102930 3, 0xFFFF, sum = 0
5882 12:38:19.106473 4, 0xFFFF, sum = 0
5883 12:38:19.106563 5, 0xFFFF, sum = 0
5884 12:38:19.109419 6, 0xFFFF, sum = 0
5885 12:38:19.109503 7, 0xFFFF, sum = 0
5886 12:38:19.112846 8, 0xFFFF, sum = 0
5887 12:38:19.112931 9, 0xFFFF, sum = 0
5888 12:38:19.115748 10, 0x0, sum = 1
5889 12:38:19.115832 11, 0x0, sum = 2
5890 12:38:19.119723 12, 0x0, sum = 3
5891 12:38:19.119807 13, 0x0, sum = 4
5892 12:38:19.119874 best_step = 11
5893 12:38:19.122561
5894 12:38:19.122643 ==
5895 12:38:19.125884 Dram Type= 6, Freq= 0, CH_1, rank 1
5896 12:38:19.129070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5897 12:38:19.129153 ==
5898 12:38:19.129219 RX Vref Scan: 0
5899 12:38:19.129281
5900 12:38:19.132517 RX Vref 0 -> 0, step: 1
5901 12:38:19.132600
5902 12:38:19.136123 RX Delay -61 -> 252, step: 4
5903 12:38:19.142184 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5904 12:38:19.145536 iDelay=199, Bit 1, Center 92 (-1 ~ 186) 188
5905 12:38:19.149090 iDelay=199, Bit 2, Center 84 (-9 ~ 178) 188
5906 12:38:19.152097 iDelay=199, Bit 3, Center 96 (3 ~ 190) 188
5907 12:38:19.155297 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5908 12:38:19.158932 iDelay=199, Bit 5, Center 104 (11 ~ 198) 188
5909 12:38:19.165644 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5910 12:38:19.168847 iDelay=199, Bit 7, Center 92 (-1 ~ 186) 188
5911 12:38:19.171893 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5912 12:38:19.175474 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5913 12:38:19.178609 iDelay=199, Bit 10, Center 94 (3 ~ 186) 184
5914 12:38:19.185363 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5915 12:38:19.188594 iDelay=199, Bit 12, Center 102 (11 ~ 194) 184
5916 12:38:19.191675 iDelay=199, Bit 13, Center 102 (11 ~ 194) 184
5917 12:38:19.195860 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5918 12:38:19.202021 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5919 12:38:19.202119 ==
5920 12:38:19.205359 Dram Type= 6, Freq= 0, CH_1, rank 1
5921 12:38:19.208030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5922 12:38:19.208115 ==
5923 12:38:19.208180 DQS Delay:
5924 12:38:19.211660 DQS0 = 0, DQS1 = 0
5925 12:38:19.211743 DQM Delay:
5926 12:38:19.215266 DQM0 = 96, DQM1 = 93
5927 12:38:19.215347 DQ Delay:
5928 12:38:19.217820 DQ0 =102, DQ1 =92, DQ2 =84, DQ3 =96
5929 12:38:19.221948 DQ4 =96, DQ5 =104, DQ6 =102, DQ7 =92
5930 12:38:19.225244 DQ8 =80, DQ9 =82, DQ10 =94, DQ11 =86
5931 12:38:19.228099 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =102
5932 12:38:19.228181
5933 12:38:19.228245
5934 12:38:19.237776 [DQSOSCAuto] RK1, (LSB)MR18= 0xb22, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
5935 12:38:19.237869 CH1 RK1: MR19=505, MR18=B22
5936 12:38:19.244726 CH1_RK1: MR19=0x505, MR18=0xB22, DQSOSC=411, MR23=63, INC=64, DEC=42
5937 12:38:19.247530 [RxdqsGatingPostProcess] freq 933
5938 12:38:19.254101 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5939 12:38:19.258026 best DQS0 dly(2T, 0.5T) = (0, 10)
5940 12:38:19.260720 best DQS1 dly(2T, 0.5T) = (0, 10)
5941 12:38:19.264086 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5942 12:38:19.267847 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5943 12:38:19.270818 best DQS0 dly(2T, 0.5T) = (0, 10)
5944 12:38:19.270908 best DQS1 dly(2T, 0.5T) = (0, 10)
5945 12:38:19.274313 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5946 12:38:19.277842 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5947 12:38:19.280872 Pre-setting of DQS Precalculation
5948 12:38:19.287484 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5949 12:38:19.293936 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5950 12:38:19.300602 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5951 12:38:19.300733
5952 12:38:19.300832
5953 12:38:19.303614 [Calibration Summary] 1866 Mbps
5954 12:38:19.306882 CH 0, Rank 0
5955 12:38:19.306971 SW Impedance : PASS
5956 12:38:19.310391 DUTY Scan : NO K
5957 12:38:19.314094 ZQ Calibration : PASS
5958 12:38:19.314180 Jitter Meter : NO K
5959 12:38:19.317079 CBT Training : PASS
5960 12:38:19.320346 Write leveling : PASS
5961 12:38:19.320462 RX DQS gating : PASS
5962 12:38:19.323357 RX DQ/DQS(RDDQC) : PASS
5963 12:38:19.327227 TX DQ/DQS : PASS
5964 12:38:19.327336 RX DATLAT : PASS
5965 12:38:19.329789 RX DQ/DQS(Engine): PASS
5966 12:38:19.329872 TX OE : NO K
5967 12:38:19.333556 All Pass.
5968 12:38:19.333639
5969 12:38:19.333703 CH 0, Rank 1
5970 12:38:19.337030 SW Impedance : PASS
5971 12:38:19.337112 DUTY Scan : NO K
5972 12:38:19.339924 ZQ Calibration : PASS
5973 12:38:19.343228 Jitter Meter : NO K
5974 12:38:19.343338 CBT Training : PASS
5975 12:38:19.346546 Write leveling : PASS
5976 12:38:19.349578 RX DQS gating : PASS
5977 12:38:19.349667 RX DQ/DQS(RDDQC) : PASS
5978 12:38:19.352661 TX DQ/DQS : PASS
5979 12:38:19.356783 RX DATLAT : PASS
5980 12:38:19.356907 RX DQ/DQS(Engine): PASS
5981 12:38:19.359530 TX OE : NO K
5982 12:38:19.359613 All Pass.
5983 12:38:19.359678
5984 12:38:19.362903 CH 1, Rank 0
5985 12:38:19.362987 SW Impedance : PASS
5986 12:38:19.366017 DUTY Scan : NO K
5987 12:38:19.369173 ZQ Calibration : PASS
5988 12:38:19.369259 Jitter Meter : NO K
5989 12:38:19.372862 CBT Training : PASS
5990 12:38:19.376205 Write leveling : PASS
5991 12:38:19.376291 RX DQS gating : PASS
5992 12:38:19.379050 RX DQ/DQS(RDDQC) : PASS
5993 12:38:19.382656 TX DQ/DQS : PASS
5994 12:38:19.382741 RX DATLAT : PASS
5995 12:38:19.386081 RX DQ/DQS(Engine): PASS
5996 12:38:19.388982 TX OE : NO K
5997 12:38:19.389065 All Pass.
5998 12:38:19.389131
5999 12:38:19.389190 CH 1, Rank 1
6000 12:38:19.392764 SW Impedance : PASS
6001 12:38:19.395944 DUTY Scan : NO K
6002 12:38:19.396027 ZQ Calibration : PASS
6003 12:38:19.399231 Jitter Meter : NO K
6004 12:38:19.402225 CBT Training : PASS
6005 12:38:19.402320 Write leveling : PASS
6006 12:38:19.405403 RX DQS gating : PASS
6007 12:38:19.409124 RX DQ/DQS(RDDQC) : PASS
6008 12:38:19.409256 TX DQ/DQS : PASS
6009 12:38:19.411858 RX DATLAT : PASS
6010 12:38:19.415680 RX DQ/DQS(Engine): PASS
6011 12:38:19.415782 TX OE : NO K
6012 12:38:19.415848 All Pass.
6013 12:38:19.418575
6014 12:38:19.418660 DramC Write-DBI off
6015 12:38:19.421854 PER_BANK_REFRESH: Hybrid Mode
6016 12:38:19.421948 TX_TRACKING: ON
6017 12:38:19.431741 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6018 12:38:19.435657 [FAST_K] Save calibration result to emmc
6019 12:38:19.438325 dramc_set_vcore_voltage set vcore to 650000
6020 12:38:19.441659 Read voltage for 400, 6
6021 12:38:19.441767 Vio18 = 0
6022 12:38:19.445256 Vcore = 650000
6023 12:38:19.445381 Vdram = 0
6024 12:38:19.445475 Vddq = 0
6025 12:38:19.448268 Vmddr = 0
6026 12:38:19.451914 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6027 12:38:19.458234 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6028 12:38:19.458503 MEM_TYPE=3, freq_sel=20
6029 12:38:19.461432 sv_algorithm_assistance_LP4_800
6030 12:38:19.464941 ============ PULL DRAM RESETB DOWN ============
6031 12:38:19.471984 ========== PULL DRAM RESETB DOWN end =========
6032 12:38:19.474830 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6033 12:38:19.478229 ===================================
6034 12:38:19.481372 LPDDR4 DRAM CONFIGURATION
6035 12:38:19.484540 ===================================
6036 12:38:19.484651 EX_ROW_EN[0] = 0x0
6037 12:38:19.487936 EX_ROW_EN[1] = 0x0
6038 12:38:19.491313 LP4Y_EN = 0x0
6039 12:38:19.491452 WORK_FSP = 0x0
6040 12:38:19.495180 WL = 0x2
6041 12:38:19.495290 RL = 0x2
6042 12:38:19.498032 BL = 0x2
6043 12:38:19.498120 RPST = 0x0
6044 12:38:19.501063 RD_PRE = 0x0
6045 12:38:19.501188 WR_PRE = 0x1
6046 12:38:19.504917 WR_PST = 0x0
6047 12:38:19.505012 DBI_WR = 0x0
6048 12:38:19.508082 DBI_RD = 0x0
6049 12:38:19.508167 OTF = 0x1
6050 12:38:19.510969 ===================================
6051 12:38:19.514238 ===================================
6052 12:38:19.518513 ANA top config
6053 12:38:19.520968 ===================================
6054 12:38:19.521054 DLL_ASYNC_EN = 0
6055 12:38:19.524683 ALL_SLAVE_EN = 1
6056 12:38:19.527503 NEW_RANK_MODE = 1
6057 12:38:19.531150 DLL_IDLE_MODE = 1
6058 12:38:19.534216 LP45_APHY_COMB_EN = 1
6059 12:38:19.534333 TX_ODT_DIS = 1
6060 12:38:19.537075 NEW_8X_MODE = 1
6061 12:38:19.540595 ===================================
6062 12:38:19.544215 ===================================
6063 12:38:19.547769 data_rate = 800
6064 12:38:19.550811 CKR = 1
6065 12:38:19.554136 DQ_P2S_RATIO = 4
6066 12:38:19.557034 ===================================
6067 12:38:19.560812 CA_P2S_RATIO = 4
6068 12:38:19.560899 DQ_CA_OPEN = 0
6069 12:38:19.563582 DQ_SEMI_OPEN = 1
6070 12:38:19.567449 CA_SEMI_OPEN = 1
6071 12:38:19.570103 CA_FULL_RATE = 0
6072 12:38:19.573393 DQ_CKDIV4_EN = 0
6073 12:38:19.577049 CA_CKDIV4_EN = 1
6074 12:38:19.577136 CA_PREDIV_EN = 0
6075 12:38:19.579858 PH8_DLY = 0
6076 12:38:19.583310 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6077 12:38:19.587259 DQ_AAMCK_DIV = 0
6078 12:38:19.590121 CA_AAMCK_DIV = 0
6079 12:38:19.593634 CA_ADMCK_DIV = 4
6080 12:38:19.596933 DQ_TRACK_CA_EN = 0
6081 12:38:19.597052 CA_PICK = 800
6082 12:38:19.599956 CA_MCKIO = 400
6083 12:38:19.602880 MCKIO_SEMI = 400
6084 12:38:19.606368 PLL_FREQ = 3016
6085 12:38:19.610352 DQ_UI_PI_RATIO = 32
6086 12:38:19.613217 CA_UI_PI_RATIO = 32
6087 12:38:19.616153 ===================================
6088 12:38:19.620041 ===================================
6089 12:38:19.623801 memory_type:LPDDR4
6090 12:38:19.623888 GP_NUM : 10
6091 12:38:19.626278 SRAM_EN : 1
6092 12:38:19.626360 MD32_EN : 0
6093 12:38:19.629546 ===================================
6094 12:38:19.633117 [ANA_INIT] >>>>>>>>>>>>>>
6095 12:38:19.636672 <<<<<< [CONFIGURE PHASE]: ANA_TX
6096 12:38:19.640171 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6097 12:38:19.643412 ===================================
6098 12:38:19.646106 data_rate = 800,PCW = 0X7400
6099 12:38:19.649453 ===================================
6100 12:38:19.652369 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6101 12:38:19.659220 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6102 12:38:19.669021 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6103 12:38:19.672279 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6104 12:38:19.675802 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6105 12:38:19.681936 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6106 12:38:19.682029 [ANA_INIT] flow start
6107 12:38:19.685355 [ANA_INIT] PLL >>>>>>>>
6108 12:38:19.688540 [ANA_INIT] PLL <<<<<<<<
6109 12:38:19.688624 [ANA_INIT] MIDPI >>>>>>>>
6110 12:38:19.692287 [ANA_INIT] MIDPI <<<<<<<<
6111 12:38:19.695044 [ANA_INIT] DLL >>>>>>>>
6112 12:38:19.695129 [ANA_INIT] flow end
6113 12:38:19.702094 ============ LP4 DIFF to SE enter ============
6114 12:38:19.705451 ============ LP4 DIFF to SE exit ============
6115 12:38:19.705546 [ANA_INIT] <<<<<<<<<<<<<
6116 12:38:19.708668 [Flow] Enable top DCM control >>>>>
6117 12:38:19.712332 [Flow] Enable top DCM control <<<<<
6118 12:38:19.715942 Enable DLL master slave shuffle
6119 12:38:19.721560 ==============================================================
6120 12:38:19.725418 Gating Mode config
6121 12:38:19.728126 ==============================================================
6122 12:38:19.731553 Config description:
6123 12:38:19.741295 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6124 12:38:19.748050 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6125 12:38:19.751342 SELPH_MODE 0: By rank 1: By Phase
6126 12:38:19.759066 ==============================================================
6127 12:38:19.761464 GAT_TRACK_EN = 0
6128 12:38:19.765388 RX_GATING_MODE = 2
6129 12:38:19.767717 RX_GATING_TRACK_MODE = 2
6130 12:38:19.771152 SELPH_MODE = 1
6131 12:38:19.771249 PICG_EARLY_EN = 1
6132 12:38:19.774413 VALID_LAT_VALUE = 1
6133 12:38:19.781063 ==============================================================
6134 12:38:19.784807 Enter into Gating configuration >>>>
6135 12:38:19.787825 Exit from Gating configuration <<<<
6136 12:38:19.791297 Enter into DVFS_PRE_config >>>>>
6137 12:38:19.801314 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6138 12:38:19.803981 Exit from DVFS_PRE_config <<<<<
6139 12:38:19.808083 Enter into PICG configuration >>>>
6140 12:38:19.811058 Exit from PICG configuration <<<<
6141 12:38:19.813781 [RX_INPUT] configuration >>>>>
6142 12:38:19.817271 [RX_INPUT] configuration <<<<<
6143 12:38:19.820667 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6144 12:38:19.827783 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6145 12:38:19.834131 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6146 12:38:19.840313 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6147 12:38:19.847372 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6148 12:38:19.853516 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6149 12:38:19.856655 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6150 12:38:19.860124 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6151 12:38:19.863520 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6152 12:38:19.870212 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6153 12:38:19.872957 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6154 12:38:19.876534 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6155 12:38:19.879632 ===================================
6156 12:38:19.883113 LPDDR4 DRAM CONFIGURATION
6157 12:38:19.886210 ===================================
6158 12:38:19.889530 EX_ROW_EN[0] = 0x0
6159 12:38:19.889625 EX_ROW_EN[1] = 0x0
6160 12:38:19.892740 LP4Y_EN = 0x0
6161 12:38:19.892827 WORK_FSP = 0x0
6162 12:38:19.896212 WL = 0x2
6163 12:38:19.896301 RL = 0x2
6164 12:38:19.899321 BL = 0x2
6165 12:38:19.899434 RPST = 0x0
6166 12:38:19.902632 RD_PRE = 0x0
6167 12:38:19.902726 WR_PRE = 0x1
6168 12:38:19.906432 WR_PST = 0x0
6169 12:38:19.906531 DBI_WR = 0x0
6170 12:38:19.909511 DBI_RD = 0x0
6171 12:38:19.909601 OTF = 0x1
6172 12:38:19.912642 ===================================
6173 12:38:19.918939 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6174 12:38:19.922120 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6175 12:38:19.925672 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6176 12:38:19.929280 ===================================
6177 12:38:19.932248 LPDDR4 DRAM CONFIGURATION
6178 12:38:19.935787 ===================================
6179 12:38:19.938698 EX_ROW_EN[0] = 0x10
6180 12:38:19.938792 EX_ROW_EN[1] = 0x0
6181 12:38:19.942181 LP4Y_EN = 0x0
6182 12:38:19.942273 WORK_FSP = 0x0
6183 12:38:19.945568 WL = 0x2
6184 12:38:19.945700 RL = 0x2
6185 12:38:19.949001 BL = 0x2
6186 12:38:19.949087 RPST = 0x0
6187 12:38:19.952669 RD_PRE = 0x0
6188 12:38:19.952756 WR_PRE = 0x1
6189 12:38:19.955209 WR_PST = 0x0
6190 12:38:19.958843 DBI_WR = 0x0
6191 12:38:19.958933 DBI_RD = 0x0
6192 12:38:19.962131 OTF = 0x1
6193 12:38:19.965218 ===================================
6194 12:38:19.968447 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6195 12:38:19.974194 nWR fixed to 30
6196 12:38:19.976832 [ModeRegInit_LP4] CH0 RK0
6197 12:38:19.976938 [ModeRegInit_LP4] CH0 RK1
6198 12:38:19.980249 [ModeRegInit_LP4] CH1 RK0
6199 12:38:19.983321 [ModeRegInit_LP4] CH1 RK1
6200 12:38:19.983434 match AC timing 19
6201 12:38:19.990442 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6202 12:38:19.993317 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6203 12:38:19.996737 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6204 12:38:20.003260 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6205 12:38:20.006922 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6206 12:38:20.007044 ==
6207 12:38:20.009895 Dram Type= 6, Freq= 0, CH_0, rank 0
6208 12:38:20.012979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6209 12:38:20.013090 ==
6210 12:38:20.019918 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6211 12:38:20.026266 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6212 12:38:20.029603 [CA 0] Center 36 (8~64) winsize 57
6213 12:38:20.033201 [CA 1] Center 36 (8~64) winsize 57
6214 12:38:20.036473 [CA 2] Center 36 (8~64) winsize 57
6215 12:38:20.039528 [CA 3] Center 36 (8~64) winsize 57
6216 12:38:20.042867 [CA 4] Center 36 (8~64) winsize 57
6217 12:38:20.046467 [CA 5] Center 36 (8~64) winsize 57
6218 12:38:20.046578
6219 12:38:20.049188 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6220 12:38:20.049277
6221 12:38:20.052485 [CATrainingPosCal] consider 1 rank data
6222 12:38:20.056450 u2DelayCellTimex100 = 270/100 ps
6223 12:38:20.060155 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 12:38:20.062620 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 12:38:20.066286 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 12:38:20.069516 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 12:38:20.072693 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 12:38:20.076126 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 12:38:20.076210
6230 12:38:20.082414 CA PerBit enable=1, Macro0, CA PI delay=36
6231 12:38:20.082498
6232 12:38:20.082563 [CBTSetCACLKResult] CA Dly = 36
6233 12:38:20.086082 CS Dly: 1 (0~32)
6234 12:38:20.086164 ==
6235 12:38:20.088678 Dram Type= 6, Freq= 0, CH_0, rank 1
6236 12:38:20.092097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6237 12:38:20.092210 ==
6238 12:38:20.098603 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6239 12:38:20.105260 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6240 12:38:20.108372 [CA 0] Center 36 (8~64) winsize 57
6241 12:38:20.112059 [CA 1] Center 36 (8~64) winsize 57
6242 12:38:20.114843 [CA 2] Center 36 (8~64) winsize 57
6243 12:38:20.118590 [CA 3] Center 36 (8~64) winsize 57
6244 12:38:20.122150 [CA 4] Center 36 (8~64) winsize 57
6245 12:38:20.122235 [CA 5] Center 36 (8~64) winsize 57
6246 12:38:20.125260
6247 12:38:20.128528 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6248 12:38:20.128629
6249 12:38:20.131918 [CATrainingPosCal] consider 2 rank data
6250 12:38:20.134887 u2DelayCellTimex100 = 270/100 ps
6251 12:38:20.138224 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 12:38:20.141793 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 12:38:20.145075 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 12:38:20.148269 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 12:38:20.151507 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 12:38:20.154494 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 12:38:20.154571
6258 12:38:20.158218 CA PerBit enable=1, Macro0, CA PI delay=36
6259 12:38:20.158296
6260 12:38:20.161426 [CBTSetCACLKResult] CA Dly = 36
6261 12:38:20.164533 CS Dly: 1 (0~32)
6262 12:38:20.164616
6263 12:38:20.167918 ----->DramcWriteLeveling(PI) begin...
6264 12:38:20.168007 ==
6265 12:38:20.171562 Dram Type= 6, Freq= 0, CH_0, rank 0
6266 12:38:20.174910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6267 12:38:20.174986 ==
6268 12:38:20.178785 Write leveling (Byte 0): 40 => 8
6269 12:38:20.181049 Write leveling (Byte 1): 40 => 8
6270 12:38:20.184645 DramcWriteLeveling(PI) end<-----
6271 12:38:20.184719
6272 12:38:20.184780 ==
6273 12:38:20.188474 Dram Type= 6, Freq= 0, CH_0, rank 0
6274 12:38:20.190854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6275 12:38:20.190923 ==
6276 12:38:20.194359 [Gating] SW mode calibration
6277 12:38:20.201286 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6278 12:38:20.207976 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6279 12:38:20.210754 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6280 12:38:20.217192 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6281 12:38:20.220726 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6282 12:38:20.223988 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6283 12:38:20.230400 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6284 12:38:20.233891 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6285 12:38:20.237212 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6286 12:38:20.244385 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6287 12:38:20.246863 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6288 12:38:20.250020 Total UI for P1: 0, mck2ui 16
6289 12:38:20.253369 best dqsien dly found for B0: ( 0, 14, 24)
6290 12:38:20.256876 Total UI for P1: 0, mck2ui 16
6291 12:38:20.260199 best dqsien dly found for B1: ( 0, 14, 24)
6292 12:38:20.263410 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6293 12:38:20.266509 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6294 12:38:20.266621
6295 12:38:20.269904 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6296 12:38:20.277093 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6297 12:38:20.277185 [Gating] SW calibration Done
6298 12:38:20.277250 ==
6299 12:38:20.280106 Dram Type= 6, Freq= 0, CH_0, rank 0
6300 12:38:20.286356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6301 12:38:20.286446 ==
6302 12:38:20.286523 RX Vref Scan: 0
6303 12:38:20.286584
6304 12:38:20.290001 RX Vref 0 -> 0, step: 1
6305 12:38:20.290075
6306 12:38:20.293415 RX Delay -410 -> 252, step: 16
6307 12:38:20.296449 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6308 12:38:20.300077 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6309 12:38:20.306378 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6310 12:38:20.309554 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6311 12:38:20.313162 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6312 12:38:20.316282 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6313 12:38:20.322632 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6314 12:38:20.326417 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6315 12:38:20.329250 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6316 12:38:20.332373 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6317 12:38:20.339860 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6318 12:38:20.342457 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6319 12:38:20.345577 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6320 12:38:20.352321 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6321 12:38:20.355275 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6322 12:38:20.358719 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6323 12:38:20.358800 ==
6324 12:38:20.362235 Dram Type= 6, Freq= 0, CH_0, rank 0
6325 12:38:20.365618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 12:38:20.365694 ==
6327 12:38:20.369032 DQS Delay:
6328 12:38:20.369105 DQS0 = 35, DQS1 = 59
6329 12:38:20.372481 DQM Delay:
6330 12:38:20.372563 DQM0 = 6, DQM1 = 18
6331 12:38:20.375293 DQ Delay:
6332 12:38:20.375445 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6333 12:38:20.378758 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6334 12:38:20.382259 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =16
6335 12:38:20.385221 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6336 12:38:20.385298
6337 12:38:20.385365
6338 12:38:20.385425 ==
6339 12:38:20.388497 Dram Type= 6, Freq= 0, CH_0, rank 0
6340 12:38:20.395635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6341 12:38:20.395770 ==
6342 12:38:20.395836
6343 12:38:20.395895
6344 12:38:20.395966 TX Vref Scan disable
6345 12:38:20.398682 == TX Byte 0 ==
6346 12:38:20.402236 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6347 12:38:20.405482 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6348 12:38:20.408996 == TX Byte 1 ==
6349 12:38:20.411708 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6350 12:38:20.414848 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6351 12:38:20.418293 ==
6352 12:38:20.421907 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 12:38:20.425297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 12:38:20.425385 ==
6355 12:38:20.425449
6356 12:38:20.425508
6357 12:38:20.428832 TX Vref Scan disable
6358 12:38:20.428917 == TX Byte 0 ==
6359 12:38:20.431927 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6360 12:38:20.438117 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6361 12:38:20.438226 == TX Byte 1 ==
6362 12:38:20.441756 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6363 12:38:20.447835 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6364 12:38:20.447929
6365 12:38:20.447993 [DATLAT]
6366 12:38:20.448052 Freq=400, CH0 RK0
6367 12:38:20.448110
6368 12:38:20.451712 DATLAT Default: 0xf
6369 12:38:20.454560 0, 0xFFFF, sum = 0
6370 12:38:20.454647 1, 0xFFFF, sum = 0
6371 12:38:20.458113 2, 0xFFFF, sum = 0
6372 12:38:20.458199 3, 0xFFFF, sum = 0
6373 12:38:20.461278 4, 0xFFFF, sum = 0
6374 12:38:20.461363 5, 0xFFFF, sum = 0
6375 12:38:20.464745 6, 0xFFFF, sum = 0
6376 12:38:20.464828 7, 0xFFFF, sum = 0
6377 12:38:20.467668 8, 0xFFFF, sum = 0
6378 12:38:20.467742 9, 0xFFFF, sum = 0
6379 12:38:20.471025 10, 0xFFFF, sum = 0
6380 12:38:20.471098 11, 0xFFFF, sum = 0
6381 12:38:20.474381 12, 0xFFFF, sum = 0
6382 12:38:20.474466 13, 0x0, sum = 1
6383 12:38:20.477687 14, 0x0, sum = 2
6384 12:38:20.477758 15, 0x0, sum = 3
6385 12:38:20.480944 16, 0x0, sum = 4
6386 12:38:20.481019 best_step = 14
6387 12:38:20.481080
6388 12:38:20.481137 ==
6389 12:38:20.484156 Dram Type= 6, Freq= 0, CH_0, rank 0
6390 12:38:20.490969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6391 12:38:20.491099 ==
6392 12:38:20.491183 RX Vref Scan: 1
6393 12:38:20.491242
6394 12:38:20.494200 RX Vref 0 -> 0, step: 1
6395 12:38:20.494270
6396 12:38:20.498103 RX Delay -359 -> 252, step: 8
6397 12:38:20.498180
6398 12:38:20.500992 Set Vref, RX VrefLevel [Byte0]: 54
6399 12:38:20.503806 [Byte1]: 59
6400 12:38:20.503943
6401 12:38:20.507958 Final RX Vref Byte 0 = 54 to rank0
6402 12:38:20.510779 Final RX Vref Byte 1 = 59 to rank0
6403 12:38:20.513949 Final RX Vref Byte 0 = 54 to rank1
6404 12:38:20.517639 Final RX Vref Byte 1 = 59 to rank1==
6405 12:38:20.520476 Dram Type= 6, Freq= 0, CH_0, rank 0
6406 12:38:20.523755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6407 12:38:20.527259 ==
6408 12:38:20.527428 DQS Delay:
6409 12:38:20.527611 DQS0 = 44, DQS1 = 60
6410 12:38:20.531031 DQM Delay:
6411 12:38:20.531138 DQM0 = 10, DQM1 = 16
6412 12:38:20.533972 DQ Delay:
6413 12:38:20.537104 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6414 12:38:20.537216 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6415 12:38:20.540530 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6416 12:38:20.543858 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6417 12:38:20.543976
6418 12:38:20.546782
6419 12:38:20.553967 [DQSOSCAuto] RK0, (LSB)MR18= 0x9e93, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 390 ps
6420 12:38:20.557188 CH0 RK0: MR19=C0C, MR18=9E93
6421 12:38:20.563571 CH0_RK0: MR19=0xC0C, MR18=0x9E93, DQSOSC=390, MR23=63, INC=388, DEC=258
6422 12:38:20.563713 ==
6423 12:38:20.566654 Dram Type= 6, Freq= 0, CH_0, rank 1
6424 12:38:20.570045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6425 12:38:20.570158 ==
6426 12:38:20.573124 [Gating] SW mode calibration
6427 12:38:20.581368 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6428 12:38:20.586126 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6429 12:38:20.589707 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6430 12:38:20.593169 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6431 12:38:20.599236 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6432 12:38:20.602879 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6433 12:38:20.605794 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6434 12:38:20.612612 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6435 12:38:20.616027 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6436 12:38:20.619113 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6437 12:38:20.626169 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6438 12:38:20.628964 Total UI for P1: 0, mck2ui 16
6439 12:38:20.632395 best dqsien dly found for B0: ( 0, 14, 24)
6440 12:38:20.632508 Total UI for P1: 0, mck2ui 16
6441 12:38:20.638724 best dqsien dly found for B1: ( 0, 14, 24)
6442 12:38:20.642374 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6443 12:38:20.645500 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6444 12:38:20.645609
6445 12:38:20.649000 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6446 12:38:20.652218 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6447 12:38:20.655850 [Gating] SW calibration Done
6448 12:38:20.655968 ==
6449 12:38:20.658730 Dram Type= 6, Freq= 0, CH_0, rank 1
6450 12:38:20.661776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6451 12:38:20.661889 ==
6452 12:38:20.665276 RX Vref Scan: 0
6453 12:38:20.665383
6454 12:38:20.668438 RX Vref 0 -> 0, step: 1
6455 12:38:20.668542
6456 12:38:20.668635 RX Delay -410 -> 252, step: 16
6457 12:38:20.675979 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6458 12:38:20.678442 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6459 12:38:20.681796 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6460 12:38:20.688533 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6461 12:38:20.692551 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6462 12:38:20.694951 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6463 12:38:20.698000 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6464 12:38:20.704587 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6465 12:38:20.708154 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6466 12:38:20.711067 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6467 12:38:20.714839 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6468 12:38:20.720979 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6469 12:38:20.724191 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6470 12:38:20.727675 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6471 12:38:20.734522 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6472 12:38:20.737609 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6473 12:38:20.737726 ==
6474 12:38:20.741028 Dram Type= 6, Freq= 0, CH_0, rank 1
6475 12:38:20.744071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 12:38:20.744184 ==
6477 12:38:20.747608 DQS Delay:
6478 12:38:20.747718 DQS0 = 35, DQS1 = 59
6479 12:38:20.747811 DQM Delay:
6480 12:38:20.750842 DQM0 = 5, DQM1 = 16
6481 12:38:20.750949 DQ Delay:
6482 12:38:20.754094 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6483 12:38:20.757400 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6484 12:38:20.760401 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6485 12:38:20.764321 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6486 12:38:20.764434
6487 12:38:20.764526
6488 12:38:20.764612 ==
6489 12:38:20.768105 Dram Type= 6, Freq= 0, CH_0, rank 1
6490 12:38:20.770398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6491 12:38:20.773648 ==
6492 12:38:20.773754
6493 12:38:20.773844
6494 12:38:20.773933 TX Vref Scan disable
6495 12:38:20.776987 == TX Byte 0 ==
6496 12:38:20.780547 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6497 12:38:20.783815 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6498 12:38:20.786790 == TX Byte 1 ==
6499 12:38:20.790144 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6500 12:38:20.793309 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6501 12:38:20.793418 ==
6502 12:38:20.796980 Dram Type= 6, Freq= 0, CH_0, rank 1
6503 12:38:20.803109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 12:38:20.803214 ==
6505 12:38:20.803334
6506 12:38:20.803429
6507 12:38:20.803523 TX Vref Scan disable
6508 12:38:20.806781 == TX Byte 0 ==
6509 12:38:20.810083 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6510 12:38:20.814198 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6511 12:38:20.816803 == TX Byte 1 ==
6512 12:38:20.819937 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6513 12:38:20.823121 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6514 12:38:20.823221
6515 12:38:20.826579 [DATLAT]
6516 12:38:20.826681 Freq=400, CH0 RK1
6517 12:38:20.826772
6518 12:38:20.829866 DATLAT Default: 0xe
6519 12:38:20.829965 0, 0xFFFF, sum = 0
6520 12:38:20.832922 1, 0xFFFF, sum = 0
6521 12:38:20.833026 2, 0xFFFF, sum = 0
6522 12:38:20.836410 3, 0xFFFF, sum = 0
6523 12:38:20.836512 4, 0xFFFF, sum = 0
6524 12:38:20.839777 5, 0xFFFF, sum = 0
6525 12:38:20.839887 6, 0xFFFF, sum = 0
6526 12:38:20.843123 7, 0xFFFF, sum = 0
6527 12:38:20.843225 8, 0xFFFF, sum = 0
6528 12:38:20.846314 9, 0xFFFF, sum = 0
6529 12:38:20.846414 10, 0xFFFF, sum = 0
6530 12:38:20.849445 11, 0xFFFF, sum = 0
6531 12:38:20.852999 12, 0xFFFF, sum = 0
6532 12:38:20.853111 13, 0x0, sum = 1
6533 12:38:20.856018 14, 0x0, sum = 2
6534 12:38:20.856129 15, 0x0, sum = 3
6535 12:38:20.856223 16, 0x0, sum = 4
6536 12:38:20.859539 best_step = 14
6537 12:38:20.859645
6538 12:38:20.859736 ==
6539 12:38:20.862775 Dram Type= 6, Freq= 0, CH_0, rank 1
6540 12:38:20.866202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6541 12:38:20.866357 ==
6542 12:38:20.869620 RX Vref Scan: 0
6543 12:38:20.869726
6544 12:38:20.872332 RX Vref 0 -> 0, step: 1
6545 12:38:20.872433
6546 12:38:20.872522 RX Delay -359 -> 252, step: 8
6547 12:38:20.881951 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6548 12:38:20.885475 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6549 12:38:20.887655 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6550 12:38:20.894312 iDelay=217, Bit 3, Center -36 (-271 ~ 200) 472
6551 12:38:20.897517 iDelay=217, Bit 4, Center -28 (-263 ~ 208) 472
6552 12:38:20.901112 iDelay=217, Bit 5, Center -44 (-279 ~ 192) 472
6553 12:38:20.904539 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6554 12:38:20.910828 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6555 12:38:20.914328 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6556 12:38:20.917296 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6557 12:38:20.921082 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6558 12:38:20.926994 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6559 12:38:20.930366 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6560 12:38:20.933823 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6561 12:38:20.940167 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6562 12:38:20.943320 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6563 12:38:20.943472 ==
6564 12:38:20.947043 Dram Type= 6, Freq= 0, CH_0, rank 1
6565 12:38:20.950142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6566 12:38:20.950250 ==
6567 12:38:20.953446 DQS Delay:
6568 12:38:20.953550 DQS0 = 44, DQS1 = 60
6569 12:38:20.953636 DQM Delay:
6570 12:38:20.956771 DQM0 = 10, DQM1 = 16
6571 12:38:20.956875 DQ Delay:
6572 12:38:20.960068 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6573 12:38:20.963433 DQ4 =16, DQ5 =0, DQ6 =20, DQ7 =16
6574 12:38:20.966812 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6575 12:38:20.969971 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6576 12:38:20.970077
6577 12:38:20.970162
6578 12:38:20.979667 [DQSOSCAuto] RK1, (LSB)MR18= 0x8c83, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6579 12:38:20.979817 CH0 RK1: MR19=C0C, MR18=8C83
6580 12:38:20.986892 CH0_RK1: MR19=0xC0C, MR18=0x8C83, DQSOSC=392, MR23=63, INC=384, DEC=256
6581 12:38:20.990159 [RxdqsGatingPostProcess] freq 400
6582 12:38:20.996770 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6583 12:38:20.999462 best DQS0 dly(2T, 0.5T) = (0, 10)
6584 12:38:21.003638 best DQS1 dly(2T, 0.5T) = (0, 10)
6585 12:38:21.006272 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6586 12:38:21.009262 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6587 12:38:21.012700 best DQS0 dly(2T, 0.5T) = (0, 10)
6588 12:38:21.016212 best DQS1 dly(2T, 0.5T) = (0, 10)
6589 12:38:21.018981 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6590 12:38:21.022716 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6591 12:38:21.026020 Pre-setting of DQS Precalculation
6592 12:38:21.028995 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6593 12:38:21.029083 ==
6594 12:38:21.032509 Dram Type= 6, Freq= 0, CH_1, rank 0
6595 12:38:21.036055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6596 12:38:21.036174 ==
6597 12:38:21.042241 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6598 12:38:21.048816 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6599 12:38:21.052379 [CA 0] Center 36 (8~64) winsize 57
6600 12:38:21.055356 [CA 1] Center 36 (8~64) winsize 57
6601 12:38:21.058985 [CA 2] Center 36 (8~64) winsize 57
6602 12:38:21.062137 [CA 3] Center 36 (8~64) winsize 57
6603 12:38:21.065316 [CA 4] Center 36 (8~64) winsize 57
6604 12:38:21.068483 [CA 5] Center 36 (8~64) winsize 57
6605 12:38:21.068595
6606 12:38:21.071788 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6607 12:38:21.071899
6608 12:38:21.075324 [CATrainingPosCal] consider 1 rank data
6609 12:38:21.078469 u2DelayCellTimex100 = 270/100 ps
6610 12:38:21.081868 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 12:38:21.085018 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 12:38:21.088250 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 12:38:21.091688 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 12:38:21.095651 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 12:38:21.098676 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 12:38:21.098790
6617 12:38:21.105102 CA PerBit enable=1, Macro0, CA PI delay=36
6618 12:38:21.105222
6619 12:38:21.105290 [CBTSetCACLKResult] CA Dly = 36
6620 12:38:21.108061 CS Dly: 1 (0~32)
6621 12:38:21.108149 ==
6622 12:38:21.111837 Dram Type= 6, Freq= 0, CH_1, rank 1
6623 12:38:21.114539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6624 12:38:21.114626 ==
6625 12:38:21.121142 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6626 12:38:21.128850 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6627 12:38:21.131305 [CA 0] Center 36 (8~64) winsize 57
6628 12:38:21.135095 [CA 1] Center 36 (8~64) winsize 57
6629 12:38:21.138492 [CA 2] Center 36 (8~64) winsize 57
6630 12:38:21.141346 [CA 3] Center 36 (8~64) winsize 57
6631 12:38:21.141438 [CA 4] Center 36 (8~64) winsize 57
6632 12:38:21.144300 [CA 5] Center 36 (8~64) winsize 57
6633 12:38:21.144404
6634 12:38:21.150861 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6635 12:38:21.151054
6636 12:38:21.154219 [CATrainingPosCal] consider 2 rank data
6637 12:38:21.157715 u2DelayCellTimex100 = 270/100 ps
6638 12:38:21.160932 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 12:38:21.163957 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 12:38:21.167416 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 12:38:21.170921 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 12:38:21.173861 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 12:38:21.177336 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 12:38:21.177450
6645 12:38:21.180432 CA PerBit enable=1, Macro0, CA PI delay=36
6646 12:38:21.180540
6647 12:38:21.183731 [CBTSetCACLKResult] CA Dly = 36
6648 12:38:21.187577 CS Dly: 1 (0~32)
6649 12:38:21.187690
6650 12:38:21.190389 ----->DramcWriteLeveling(PI) begin...
6651 12:38:21.190497 ==
6652 12:38:21.194084 Dram Type= 6, Freq= 0, CH_1, rank 0
6653 12:38:21.197026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6654 12:38:21.197140 ==
6655 12:38:21.200238 Write leveling (Byte 0): 40 => 8
6656 12:38:21.203546 Write leveling (Byte 1): 40 => 8
6657 12:38:21.207217 DramcWriteLeveling(PI) end<-----
6658 12:38:21.207373
6659 12:38:21.207484 ==
6660 12:38:21.210282 Dram Type= 6, Freq= 0, CH_1, rank 0
6661 12:38:21.213423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6662 12:38:21.213541 ==
6663 12:38:21.217154 [Gating] SW mode calibration
6664 12:38:21.223493 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6665 12:38:21.230283 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6666 12:38:21.233799 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6667 12:38:21.239968 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6668 12:38:21.243667 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6669 12:38:21.246544 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6670 12:38:21.253575 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6671 12:38:21.256699 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6672 12:38:21.259640 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6673 12:38:21.266754 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6674 12:38:21.269756 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6675 12:38:21.273095 Total UI for P1: 0, mck2ui 16
6676 12:38:21.276639 best dqsien dly found for B0: ( 0, 14, 24)
6677 12:38:21.279636 Total UI for P1: 0, mck2ui 16
6678 12:38:21.282627 best dqsien dly found for B1: ( 0, 14, 24)
6679 12:38:21.286415 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6680 12:38:21.289241 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6681 12:38:21.289360
6682 12:38:21.292576 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6683 12:38:21.296032 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6684 12:38:21.299078 [Gating] SW calibration Done
6685 12:38:21.299197 ==
6686 12:38:21.302458 Dram Type= 6, Freq= 0, CH_1, rank 0
6687 12:38:21.309190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6688 12:38:21.309361 ==
6689 12:38:21.309464 RX Vref Scan: 0
6690 12:38:21.309554
6691 12:38:21.313320 RX Vref 0 -> 0, step: 1
6692 12:38:21.313433
6693 12:38:21.315652 RX Delay -410 -> 252, step: 16
6694 12:38:21.318844 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6695 12:38:21.322661 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6696 12:38:21.328829 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6697 12:38:21.332432 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6698 12:38:21.335991 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6699 12:38:21.339198 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6700 12:38:21.345536 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6701 12:38:21.348612 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6702 12:38:21.352961 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6703 12:38:21.355312 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6704 12:38:21.361949 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6705 12:38:21.365130 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6706 12:38:21.368333 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6707 12:38:21.371803 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6708 12:38:21.378262 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6709 12:38:21.381397 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6710 12:38:21.381520 ==
6711 12:38:21.384673 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 12:38:21.387946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 12:38:21.388063 ==
6714 12:38:21.391439 DQS Delay:
6715 12:38:21.391559 DQS0 = 43, DQS1 = 51
6716 12:38:21.394860 DQM Delay:
6717 12:38:21.394972 DQM0 = 13, DQM1 = 14
6718 12:38:21.398529 DQ Delay:
6719 12:38:21.398647 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6720 12:38:21.401291 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6721 12:38:21.406735 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6722 12:38:21.408355 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =16
6723 12:38:21.408473
6724 12:38:21.408566
6725 12:38:21.408656 ==
6726 12:38:21.411589 Dram Type= 6, Freq= 0, CH_1, rank 0
6727 12:38:21.417764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6728 12:38:21.417909 ==
6729 12:38:21.418009
6730 12:38:21.418101
6731 12:38:21.418191 TX Vref Scan disable
6732 12:38:21.421065 == TX Byte 0 ==
6733 12:38:21.424930 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6734 12:38:21.427994 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6735 12:38:21.430931 == TX Byte 1 ==
6736 12:38:21.434235 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6737 12:38:21.437736 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6738 12:38:21.440715 ==
6739 12:38:21.444274 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 12:38:21.447456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 12:38:21.447580 ==
6742 12:38:21.447673
6743 12:38:21.447760
6744 12:38:21.450563 TX Vref Scan disable
6745 12:38:21.450671 == TX Byte 0 ==
6746 12:38:21.454092 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6747 12:38:21.460332 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6748 12:38:21.460489 == TX Byte 1 ==
6749 12:38:21.463613 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6750 12:38:21.470604 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6751 12:38:21.470733
6752 12:38:21.470802 [DATLAT]
6753 12:38:21.470868 Freq=400, CH1 RK0
6754 12:38:21.473770
6755 12:38:21.473849 DATLAT Default: 0xf
6756 12:38:21.477048 0, 0xFFFF, sum = 0
6757 12:38:21.477129 1, 0xFFFF, sum = 0
6758 12:38:21.480994 2, 0xFFFF, sum = 0
6759 12:38:21.481086 3, 0xFFFF, sum = 0
6760 12:38:21.483279 4, 0xFFFF, sum = 0
6761 12:38:21.483423 5, 0xFFFF, sum = 0
6762 12:38:21.487170 6, 0xFFFF, sum = 0
6763 12:38:21.487246 7, 0xFFFF, sum = 0
6764 12:38:21.490589 8, 0xFFFF, sum = 0
6765 12:38:21.490674 9, 0xFFFF, sum = 0
6766 12:38:21.493521 10, 0xFFFF, sum = 0
6767 12:38:21.493600 11, 0xFFFF, sum = 0
6768 12:38:21.496922 12, 0xFFFF, sum = 0
6769 12:38:21.496994 13, 0x0, sum = 1
6770 12:38:21.500224 14, 0x0, sum = 2
6771 12:38:21.500311 15, 0x0, sum = 3
6772 12:38:21.503629 16, 0x0, sum = 4
6773 12:38:21.503747 best_step = 14
6774 12:38:21.503837
6775 12:38:21.503923 ==
6776 12:38:21.507408 Dram Type= 6, Freq= 0, CH_1, rank 0
6777 12:38:21.513263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6778 12:38:21.513384 ==
6779 12:38:21.513454 RX Vref Scan: 1
6780 12:38:21.513517
6781 12:38:21.516543 RX Vref 0 -> 0, step: 1
6782 12:38:21.516626
6783 12:38:21.519764 RX Delay -343 -> 252, step: 8
6784 12:38:21.519847
6785 12:38:21.523109 Set Vref, RX VrefLevel [Byte0]: 50
6786 12:38:21.526394 [Byte1]: 55
6787 12:38:21.526482
6788 12:38:21.529808 Final RX Vref Byte 0 = 50 to rank0
6789 12:38:21.533391 Final RX Vref Byte 1 = 55 to rank0
6790 12:38:21.538140 Final RX Vref Byte 0 = 50 to rank1
6791 12:38:21.539618 Final RX Vref Byte 1 = 55 to rank1==
6792 12:38:21.543104 Dram Type= 6, Freq= 0, CH_1, rank 0
6793 12:38:21.549561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6794 12:38:21.549661 ==
6795 12:38:21.549726 DQS Delay:
6796 12:38:21.549785 DQS0 = 44, DQS1 = 52
6797 12:38:21.553494 DQM Delay:
6798 12:38:21.553577 DQM0 = 10, DQM1 = 10
6799 12:38:21.556916 DQ Delay:
6800 12:38:21.559992 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6801 12:38:21.560112 DQ4 =8, DQ5 =16, DQ6 =24, DQ7 =4
6802 12:38:21.562647 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6803 12:38:21.566155 DQ12 =16, DQ13 =20, DQ14 =16, DQ15 =16
6804 12:38:21.566235
6805 12:38:21.569788
6806 12:38:21.576390 [DQSOSCAuto] RK0, (LSB)MR18= 0x6a91, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 396 ps
6807 12:38:21.579648 CH1 RK0: MR19=C0C, MR18=6A91
6808 12:38:21.585494 CH1_RK0: MR19=0xC0C, MR18=0x6A91, DQSOSC=391, MR23=63, INC=386, DEC=257
6809 12:38:21.585610 ==
6810 12:38:21.589466 Dram Type= 6, Freq= 0, CH_1, rank 1
6811 12:38:21.592543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6812 12:38:21.592636 ==
6813 12:38:21.595557 [Gating] SW mode calibration
6814 12:38:21.601989 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6815 12:38:21.608820 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6816 12:38:21.612281 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6817 12:38:21.615671 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6818 12:38:21.622677 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6819 12:38:21.625345 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6820 12:38:21.628700 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6821 12:38:21.635237 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6822 12:38:21.638279 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6823 12:38:21.641841 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6824 12:38:21.648831 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6825 12:38:21.648979 Total UI for P1: 0, mck2ui 16
6826 12:38:21.655748 best dqsien dly found for B0: ( 0, 14, 24)
6827 12:38:21.655885 Total UI for P1: 0, mck2ui 16
6828 12:38:21.661260 best dqsien dly found for B1: ( 0, 14, 24)
6829 12:38:21.664944 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6830 12:38:21.668103 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6831 12:38:21.668191
6832 12:38:21.671383 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6833 12:38:21.674885 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6834 12:38:21.678180 [Gating] SW calibration Done
6835 12:38:21.678285 ==
6836 12:38:21.681214 Dram Type= 6, Freq= 0, CH_1, rank 1
6837 12:38:21.684535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6838 12:38:21.684626 ==
6839 12:38:21.687905 RX Vref Scan: 0
6840 12:38:21.688003
6841 12:38:21.688109 RX Vref 0 -> 0, step: 1
6842 12:38:21.691710
6843 12:38:21.691810 RX Delay -410 -> 252, step: 16
6844 12:38:21.698694 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6845 12:38:21.701964 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6846 12:38:21.704804 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6847 12:38:21.707691 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6848 12:38:21.714339 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6849 12:38:21.717327 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6850 12:38:21.721784 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6851 12:38:21.727532 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6852 12:38:21.731212 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6853 12:38:21.733835 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6854 12:38:21.737623 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6855 12:38:21.744264 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6856 12:38:21.747218 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6857 12:38:21.750832 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6858 12:38:21.753816 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6859 12:38:21.760434 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6860 12:38:21.760552 ==
6861 12:38:21.763883 Dram Type= 6, Freq= 0, CH_1, rank 1
6862 12:38:21.767175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 12:38:21.767273 ==
6864 12:38:21.767351 DQS Delay:
6865 12:38:21.770374 DQS0 = 43, DQS1 = 51
6866 12:38:21.770447 DQM Delay:
6867 12:38:21.773509 DQM0 = 10, DQM1 = 13
6868 12:38:21.773580 DQ Delay:
6869 12:38:21.777422 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6870 12:38:21.781186 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6871 12:38:21.783987 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6872 12:38:21.786928 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6873 12:38:21.787041
6874 12:38:21.787130
6875 12:38:21.787214 ==
6876 12:38:21.789894 Dram Type= 6, Freq= 0, CH_1, rank 1
6877 12:38:21.793339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6878 12:38:21.793428 ==
6879 12:38:21.793522
6880 12:38:21.797105
6881 12:38:21.797181 TX Vref Scan disable
6882 12:38:21.799855 == TX Byte 0 ==
6883 12:38:21.803315 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6884 12:38:21.806344 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6885 12:38:21.809667 == TX Byte 1 ==
6886 12:38:21.813144 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6887 12:38:21.816459 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6888 12:38:21.816571 ==
6889 12:38:21.819841 Dram Type= 6, Freq= 0, CH_1, rank 1
6890 12:38:21.823256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 12:38:21.826230 ==
6892 12:38:21.826350
6893 12:38:21.826441
6894 12:38:21.826543 TX Vref Scan disable
6895 12:38:21.829813 == TX Byte 0 ==
6896 12:38:21.833107 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6897 12:38:21.835976 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6898 12:38:21.839003 == TX Byte 1 ==
6899 12:38:21.842502 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6900 12:38:21.845930 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6901 12:38:21.846041
6902 12:38:21.849099 [DATLAT]
6903 12:38:21.849210 Freq=400, CH1 RK1
6904 12:38:21.849302
6905 12:38:21.852553 DATLAT Default: 0xe
6906 12:38:21.852648 0, 0xFFFF, sum = 0
6907 12:38:21.855758 1, 0xFFFF, sum = 0
6908 12:38:21.855850 2, 0xFFFF, sum = 0
6909 12:38:21.859610 3, 0xFFFF, sum = 0
6910 12:38:21.859695 4, 0xFFFF, sum = 0
6911 12:38:21.862268 5, 0xFFFF, sum = 0
6912 12:38:21.862353 6, 0xFFFF, sum = 0
6913 12:38:21.866227 7, 0xFFFF, sum = 0
6914 12:38:21.866307 8, 0xFFFF, sum = 0
6915 12:38:21.869606 9, 0xFFFF, sum = 0
6916 12:38:21.869678 10, 0xFFFF, sum = 0
6917 12:38:21.872061 11, 0xFFFF, sum = 0
6918 12:38:21.875650 12, 0xFFFF, sum = 0
6919 12:38:21.875723 13, 0x0, sum = 1
6920 12:38:21.879293 14, 0x0, sum = 2
6921 12:38:21.879375 15, 0x0, sum = 3
6922 12:38:21.879454 16, 0x0, sum = 4
6923 12:38:21.882477 best_step = 14
6924 12:38:21.882543
6925 12:38:21.882603 ==
6926 12:38:21.885214 Dram Type= 6, Freq= 0, CH_1, rank 1
6927 12:38:21.888571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6928 12:38:21.888647 ==
6929 12:38:21.891875 RX Vref Scan: 0
6930 12:38:21.891968
6931 12:38:21.895746 RX Vref 0 -> 0, step: 1
6932 12:38:21.895854
6933 12:38:21.895948 RX Delay -343 -> 252, step: 8
6934 12:38:21.903640 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6935 12:38:21.907190 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6936 12:38:21.910760 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6937 12:38:21.916757 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6938 12:38:21.920214 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6939 12:38:21.923528 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6940 12:38:21.926738 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6941 12:38:21.933575 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6942 12:38:21.936479 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6943 12:38:21.940222 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6944 12:38:21.944583 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6945 12:38:21.949769 iDelay=217, Bit 11, Center -48 (-295 ~ 200) 496
6946 12:38:21.953237 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6947 12:38:21.956488 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6948 12:38:21.959924 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6949 12:38:21.966372 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6950 12:38:21.966486 ==
6951 12:38:21.969463 Dram Type= 6, Freq= 0, CH_1, rank 1
6952 12:38:21.973121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6953 12:38:21.973216 ==
6954 12:38:21.976270 DQS Delay:
6955 12:38:21.976384 DQS0 = 48, DQS1 = 52
6956 12:38:21.976474 DQM Delay:
6957 12:38:21.979610 DQM0 = 11, DQM1 = 10
6958 12:38:21.979705 DQ Delay:
6959 12:38:21.982723 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6960 12:38:21.986182 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6961 12:38:21.989486 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6962 12:38:21.993130 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6963 12:38:21.993235
6964 12:38:21.993324
6965 12:38:22.002752 [DQSOSCAuto] RK1, (LSB)MR18= 0x75ac, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
6966 12:38:22.002873 CH1 RK1: MR19=C0C, MR18=75AC
6967 12:38:22.009027 CH1_RK1: MR19=0xC0C, MR18=0x75AC, DQSOSC=388, MR23=63, INC=392, DEC=261
6968 12:38:22.012312 [RxdqsGatingPostProcess] freq 400
6969 12:38:22.019622 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6970 12:38:22.021898 best DQS0 dly(2T, 0.5T) = (0, 10)
6971 12:38:22.026022 best DQS1 dly(2T, 0.5T) = (0, 10)
6972 12:38:22.028838 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6973 12:38:22.032716 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6974 12:38:22.035396 best DQS0 dly(2T, 0.5T) = (0, 10)
6975 12:38:22.038789 best DQS1 dly(2T, 0.5T) = (0, 10)
6976 12:38:22.042263 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6977 12:38:22.045025 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6978 12:38:22.045113 Pre-setting of DQS Precalculation
6979 12:38:22.052034 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6980 12:38:22.059337 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6981 12:38:22.065705 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6982 12:38:22.065872
6983 12:38:22.065939
6984 12:38:22.068677 [Calibration Summary] 800 Mbps
6985 12:38:22.071641 CH 0, Rank 0
6986 12:38:22.071728 SW Impedance : PASS
6987 12:38:22.075142 DUTY Scan : NO K
6988 12:38:22.078000 ZQ Calibration : PASS
6989 12:38:22.078078 Jitter Meter : NO K
6990 12:38:22.081495 CBT Training : PASS
6991 12:38:22.084761 Write leveling : PASS
6992 12:38:22.084923 RX DQS gating : PASS
6993 12:38:22.087986 RX DQ/DQS(RDDQC) : PASS
6994 12:38:22.091584 TX DQ/DQS : PASS
6995 12:38:22.091672 RX DATLAT : PASS
6996 12:38:22.094655 RX DQ/DQS(Engine): PASS
6997 12:38:22.094741 TX OE : NO K
6998 12:38:22.098634 All Pass.
6999 12:38:22.098721
7000 12:38:22.098786 CH 0, Rank 1
7001 12:38:22.101428 SW Impedance : PASS
7002 12:38:22.101513 DUTY Scan : NO K
7003 12:38:22.104513 ZQ Calibration : PASS
7004 12:38:22.108023 Jitter Meter : NO K
7005 12:38:22.108123 CBT Training : PASS
7006 12:38:22.111274 Write leveling : NO K
7007 12:38:22.114355 RX DQS gating : PASS
7008 12:38:22.114464 RX DQ/DQS(RDDQC) : PASS
7009 12:38:22.119058 TX DQ/DQS : PASS
7010 12:38:22.121418 RX DATLAT : PASS
7011 12:38:22.121506 RX DQ/DQS(Engine): PASS
7012 12:38:22.124248 TX OE : NO K
7013 12:38:22.124332 All Pass.
7014 12:38:22.124398
7015 12:38:22.127585 CH 1, Rank 0
7016 12:38:22.127669 SW Impedance : PASS
7017 12:38:22.131164 DUTY Scan : NO K
7018 12:38:22.134207 ZQ Calibration : PASS
7019 12:38:22.134292 Jitter Meter : NO K
7020 12:38:22.137883 CBT Training : PASS
7021 12:38:22.140745 Write leveling : PASS
7022 12:38:22.140856 RX DQS gating : PASS
7023 12:38:22.143889 RX DQ/DQS(RDDQC) : PASS
7024 12:38:22.147294 TX DQ/DQS : PASS
7025 12:38:22.147436 RX DATLAT : PASS
7026 12:38:22.150401 RX DQ/DQS(Engine): PASS
7027 12:38:22.153961 TX OE : NO K
7028 12:38:22.154048 All Pass.
7029 12:38:22.154113
7030 12:38:22.154174 CH 1, Rank 1
7031 12:38:22.157730 SW Impedance : PASS
7032 12:38:22.160389 DUTY Scan : NO K
7033 12:38:22.160475 ZQ Calibration : PASS
7034 12:38:22.163605 Jitter Meter : NO K
7035 12:38:22.166801 CBT Training : PASS
7036 12:38:22.166936 Write leveling : NO K
7037 12:38:22.170417 RX DQS gating : PASS
7038 12:38:22.173784 RX DQ/DQS(RDDQC) : PASS
7039 12:38:22.173872 TX DQ/DQS : PASS
7040 12:38:22.176763 RX DATLAT : PASS
7041 12:38:22.181112 RX DQ/DQS(Engine): PASS
7042 12:38:22.181202 TX OE : NO K
7043 12:38:22.181271 All Pass.
7044 12:38:22.183310
7045 12:38:22.183434 DramC Write-DBI off
7046 12:38:22.186705 PER_BANK_REFRESH: Hybrid Mode
7047 12:38:22.186794 TX_TRACKING: ON
7048 12:38:22.196602 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7049 12:38:22.199694 [FAST_K] Save calibration result to emmc
7050 12:38:22.203281 dramc_set_vcore_voltage set vcore to 725000
7051 12:38:22.206427 Read voltage for 1600, 0
7052 12:38:22.206590 Vio18 = 0
7053 12:38:22.209795 Vcore = 725000
7054 12:38:22.209922 Vdram = 0
7055 12:38:22.210020 Vddq = 0
7056 12:38:22.213336 Vmddr = 0
7057 12:38:22.216104 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7058 12:38:22.223377 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7059 12:38:22.223490 MEM_TYPE=3, freq_sel=13
7060 12:38:22.226111 sv_algorithm_assistance_LP4_3733
7061 12:38:22.232589 ============ PULL DRAM RESETB DOWN ============
7062 12:38:22.236042 ========== PULL DRAM RESETB DOWN end =========
7063 12:38:22.239111 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7064 12:38:22.243027 ===================================
7065 12:38:22.245926 LPDDR4 DRAM CONFIGURATION
7066 12:38:22.249140 ===================================
7067 12:38:22.252122 EX_ROW_EN[0] = 0x0
7068 12:38:22.252232 EX_ROW_EN[1] = 0x0
7069 12:38:22.255671 LP4Y_EN = 0x0
7070 12:38:22.255754 WORK_FSP = 0x1
7071 12:38:22.260052 WL = 0x5
7072 12:38:22.260142 RL = 0x5
7073 12:38:22.262225 BL = 0x2
7074 12:38:22.262309 RPST = 0x0
7075 12:38:22.266317 RD_PRE = 0x0
7076 12:38:22.266401 WR_PRE = 0x1
7077 12:38:22.269218 WR_PST = 0x1
7078 12:38:22.269301 DBI_WR = 0x0
7079 12:38:22.272736 DBI_RD = 0x0
7080 12:38:22.272820 OTF = 0x1
7081 12:38:22.275592 ===================================
7082 12:38:22.278654 ===================================
7083 12:38:22.282319 ANA top config
7084 12:38:22.285488 ===================================
7085 12:38:22.288809 DLL_ASYNC_EN = 0
7086 12:38:22.288896 ALL_SLAVE_EN = 0
7087 12:38:22.292316 NEW_RANK_MODE = 1
7088 12:38:22.295514 DLL_IDLE_MODE = 1
7089 12:38:22.298427 LP45_APHY_COMB_EN = 1
7090 12:38:22.302922 TX_ODT_DIS = 0
7091 12:38:22.303024 NEW_8X_MODE = 1
7092 12:38:22.304963 ===================================
7093 12:38:22.308445 ===================================
7094 12:38:22.311614 data_rate = 3200
7095 12:38:22.315179 CKR = 1
7096 12:38:22.318455 DQ_P2S_RATIO = 8
7097 12:38:22.321857 ===================================
7098 12:38:22.325293 CA_P2S_RATIO = 8
7099 12:38:22.328161 DQ_CA_OPEN = 0
7100 12:38:22.328248 DQ_SEMI_OPEN = 0
7101 12:38:22.331317 CA_SEMI_OPEN = 0
7102 12:38:22.335174 CA_FULL_RATE = 0
7103 12:38:22.338272 DQ_CKDIV4_EN = 0
7104 12:38:22.341618 CA_CKDIV4_EN = 0
7105 12:38:22.345099 CA_PREDIV_EN = 0
7106 12:38:22.345187 PH8_DLY = 12
7107 12:38:22.347787 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7108 12:38:22.351214 DQ_AAMCK_DIV = 4
7109 12:38:22.354600 CA_AAMCK_DIV = 4
7110 12:38:22.358105 CA_ADMCK_DIV = 4
7111 12:38:22.361635 DQ_TRACK_CA_EN = 0
7112 12:38:22.364581 CA_PICK = 1600
7113 12:38:22.367680 CA_MCKIO = 1600
7114 12:38:22.367767 MCKIO_SEMI = 0
7115 12:38:22.371694 PLL_FREQ = 3068
7116 12:38:22.374298 DQ_UI_PI_RATIO = 32
7117 12:38:22.377599 CA_UI_PI_RATIO = 0
7118 12:38:22.380799 ===================================
7119 12:38:22.384522 ===================================
7120 12:38:22.387320 memory_type:LPDDR4
7121 12:38:22.387431 GP_NUM : 10
7122 12:38:22.391239 SRAM_EN : 1
7123 12:38:22.394046 MD32_EN : 0
7124 12:38:22.397975 ===================================
7125 12:38:22.398062 [ANA_INIT] >>>>>>>>>>>>>>
7126 12:38:22.400670 <<<<<< [CONFIGURE PHASE]: ANA_TX
7127 12:38:22.403963 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7128 12:38:22.407227 ===================================
7129 12:38:22.410899 data_rate = 3200,PCW = 0X7600
7130 12:38:22.414163 ===================================
7131 12:38:22.417475 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7132 12:38:22.424063 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7133 12:38:22.427218 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7134 12:38:22.433577 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7135 12:38:22.437393 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7136 12:38:22.440611 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7137 12:38:22.440696 [ANA_INIT] flow start
7138 12:38:22.443895 [ANA_INIT] PLL >>>>>>>>
7139 12:38:22.446911 [ANA_INIT] PLL <<<<<<<<
7140 12:38:22.450343 [ANA_INIT] MIDPI >>>>>>>>
7141 12:38:22.450428 [ANA_INIT] MIDPI <<<<<<<<
7142 12:38:22.453755 [ANA_INIT] DLL >>>>>>>>
7143 12:38:22.457220 [ANA_INIT] DLL <<<<<<<<
7144 12:38:22.457306 [ANA_INIT] flow end
7145 12:38:22.460569 ============ LP4 DIFF to SE enter ============
7146 12:38:22.467027 ============ LP4 DIFF to SE exit ============
7147 12:38:22.467134 [ANA_INIT] <<<<<<<<<<<<<
7148 12:38:22.470535 [Flow] Enable top DCM control >>>>>
7149 12:38:22.473477 [Flow] Enable top DCM control <<<<<
7150 12:38:22.476991 Enable DLL master slave shuffle
7151 12:38:22.483351 ==============================================================
7152 12:38:22.483461 Gating Mode config
7153 12:38:22.490091 ==============================================================
7154 12:38:22.493505 Config description:
7155 12:38:22.503353 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7156 12:38:22.509633 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7157 12:38:22.512633 SELPH_MODE 0: By rank 1: By Phase
7158 12:38:22.519036 ==============================================================
7159 12:38:22.522981 GAT_TRACK_EN = 1
7160 12:38:22.525618 RX_GATING_MODE = 2
7161 12:38:22.529094 RX_GATING_TRACK_MODE = 2
7162 12:38:22.533053 SELPH_MODE = 1
7163 12:38:22.533151 PICG_EARLY_EN = 1
7164 12:38:22.535610 VALID_LAT_VALUE = 1
7165 12:38:22.542040 ==============================================================
7166 12:38:22.545649 Enter into Gating configuration >>>>
7167 12:38:22.548919 Exit from Gating configuration <<<<
7168 12:38:22.552478 Enter into DVFS_PRE_config >>>>>
7169 12:38:22.562892 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7170 12:38:22.565205 Exit from DVFS_PRE_config <<<<<
7171 12:38:22.568982 Enter into PICG configuration >>>>
7172 12:38:22.572209 Exit from PICG configuration <<<<
7173 12:38:22.575506 [RX_INPUT] configuration >>>>>
7174 12:38:22.578724 [RX_INPUT] configuration <<<<<
7175 12:38:22.582262 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7176 12:38:22.588570 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7177 12:38:22.595564 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7178 12:38:22.602310 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7179 12:38:22.608555 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7180 12:38:22.615890 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7181 12:38:22.618335 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7182 12:38:22.621907 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7183 12:38:22.625347 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7184 12:38:22.631796 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7185 12:38:22.634643 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7186 12:38:22.638312 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7187 12:38:22.641394 ===================================
7188 12:38:22.644736 LPDDR4 DRAM CONFIGURATION
7189 12:38:22.648373 ===================================
7190 12:38:22.648455 EX_ROW_EN[0] = 0x0
7191 12:38:22.651533 EX_ROW_EN[1] = 0x0
7192 12:38:22.654577 LP4Y_EN = 0x0
7193 12:38:22.654655 WORK_FSP = 0x1
7194 12:38:22.657611 WL = 0x5
7195 12:38:22.657690 RL = 0x5
7196 12:38:22.661438 BL = 0x2
7197 12:38:22.661644 RPST = 0x0
7198 12:38:22.664888 RD_PRE = 0x0
7199 12:38:22.664970 WR_PRE = 0x1
7200 12:38:22.667382 WR_PST = 0x1
7201 12:38:22.667483 DBI_WR = 0x0
7202 12:38:22.671022 DBI_RD = 0x0
7203 12:38:22.671103 OTF = 0x1
7204 12:38:22.674135 ===================================
7205 12:38:22.681551 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7206 12:38:22.684298 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7207 12:38:22.687530 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7208 12:38:22.691121 ===================================
7209 12:38:22.694474 LPDDR4 DRAM CONFIGURATION
7210 12:38:22.697897 ===================================
7211 12:38:22.700784 EX_ROW_EN[0] = 0x10
7212 12:38:22.700867 EX_ROW_EN[1] = 0x0
7213 12:38:22.704239 LP4Y_EN = 0x0
7214 12:38:22.704337 WORK_FSP = 0x1
7215 12:38:22.706915 WL = 0x5
7216 12:38:22.707011 RL = 0x5
7217 12:38:22.711170 BL = 0x2
7218 12:38:22.711256 RPST = 0x0
7219 12:38:22.713926 RD_PRE = 0x0
7220 12:38:22.714008 WR_PRE = 0x1
7221 12:38:22.717853 WR_PST = 0x1
7222 12:38:22.717935 DBI_WR = 0x0
7223 12:38:22.720440 DBI_RD = 0x0
7224 12:38:22.720521 OTF = 0x1
7225 12:38:22.724002 ===================================
7226 12:38:22.730236 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7227 12:38:22.730325 ==
7228 12:38:22.733838 Dram Type= 6, Freq= 0, CH_0, rank 0
7229 12:38:22.740353 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7230 12:38:22.740441 ==
7231 12:38:22.740507 [Duty_Offset_Calibration]
7232 12:38:22.743133 B0:2 B1:0 CA:4
7233 12:38:22.743239
7234 12:38:22.746189 [DutyScan_Calibration_Flow] k_type=0
7235 12:38:22.755250
7236 12:38:22.755337 ==CLK 0==
7237 12:38:22.759548 Final CLK duty delay cell = -4
7238 12:38:22.762025 [-4] MAX Duty = 5031%(X100), DQS PI = 32
7239 12:38:22.764980 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7240 12:38:22.768402 [-4] AVG Duty = 4937%(X100)
7241 12:38:22.768489
7242 12:38:22.771853 CH0 CLK Duty spec in!! Max-Min= 187%
7243 12:38:22.775241 [DutyScan_Calibration_Flow] ====Done====
7244 12:38:22.775315
7245 12:38:22.778033 [DutyScan_Calibration_Flow] k_type=1
7246 12:38:22.795566
7247 12:38:22.795802 ==DQS 0 ==
7248 12:38:22.799121 Final DQS duty delay cell = 0
7249 12:38:22.802003 [0] MAX Duty = 5218%(X100), DQS PI = 22
7250 12:38:22.805431 [0] MIN Duty = 5093%(X100), DQS PI = 6
7251 12:38:22.808792 [0] AVG Duty = 5155%(X100)
7252 12:38:22.808903
7253 12:38:22.808983 ==DQS 1 ==
7254 12:38:22.812200 Final DQS duty delay cell = 0
7255 12:38:22.815200 [0] MAX Duty = 5187%(X100), DQS PI = 2
7256 12:38:22.818935 [0] MIN Duty = 4969%(X100), DQS PI = 10
7257 12:38:22.822311 [0] AVG Duty = 5078%(X100)
7258 12:38:22.822412
7259 12:38:22.825123 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7260 12:38:22.825205
7261 12:38:22.828310 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7262 12:38:22.831891 [DutyScan_Calibration_Flow] ====Done====
7263 12:38:22.831988
7264 12:38:22.834811 [DutyScan_Calibration_Flow] k_type=3
7265 12:38:22.852767
7266 12:38:22.852982 ==DQM 0 ==
7267 12:38:22.855635 Final DQM duty delay cell = 0
7268 12:38:22.859021 [0] MAX Duty = 5124%(X100), DQS PI = 22
7269 12:38:22.862470 [0] MIN Duty = 4875%(X100), DQS PI = 54
7270 12:38:22.865941 [0] AVG Duty = 4999%(X100)
7271 12:38:22.866114
7272 12:38:22.866181 ==DQM 1 ==
7273 12:38:22.869541 Final DQM duty delay cell = 0
7274 12:38:22.872181 [0] MAX Duty = 5000%(X100), DQS PI = 2
7275 12:38:22.875670 [0] MIN Duty = 4844%(X100), DQS PI = 16
7276 12:38:22.878658 [0] AVG Duty = 4922%(X100)
7277 12:38:22.878771
7278 12:38:22.882279 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7279 12:38:22.882377
7280 12:38:22.885892 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7281 12:38:22.888733 [DutyScan_Calibration_Flow] ====Done====
7282 12:38:22.888837
7283 12:38:22.892273 [DutyScan_Calibration_Flow] k_type=2
7284 12:38:22.909832
7285 12:38:22.909990 ==DQ 0 ==
7286 12:38:22.912826 Final DQ duty delay cell = 0
7287 12:38:22.916077 [0] MAX Duty = 5156%(X100), DQS PI = 22
7288 12:38:22.919588 [0] MIN Duty = 4969%(X100), DQS PI = 12
7289 12:38:22.919708 [0] AVG Duty = 5062%(X100)
7290 12:38:22.922840
7291 12:38:22.922961 ==DQ 1 ==
7292 12:38:22.926184 Final DQ duty delay cell = 0
7293 12:38:22.929194 [0] MAX Duty = 5218%(X100), DQS PI = 2
7294 12:38:22.933114 [0] MIN Duty = 4907%(X100), DQS PI = 34
7295 12:38:22.933253 [0] AVG Duty = 5062%(X100)
7296 12:38:22.935979
7297 12:38:22.939048 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7298 12:38:22.939168
7299 12:38:22.942823 CH0 DQ 1 Duty spec in!! Max-Min= 311%
7300 12:38:22.945937 [DutyScan_Calibration_Flow] ====Done====
7301 12:38:22.946069 ==
7302 12:38:22.949980 Dram Type= 6, Freq= 0, CH_1, rank 0
7303 12:38:22.953132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7304 12:38:22.953246 ==
7305 12:38:22.955926 [Duty_Offset_Calibration]
7306 12:38:22.956017 B0:0 B1:-1 CA:3
7307 12:38:22.956091
7308 12:38:22.959074 [DutyScan_Calibration_Flow] k_type=0
7309 12:38:22.969467
7310 12:38:22.969631 ==CLK 0==
7311 12:38:22.972632 Final CLK duty delay cell = -4
7312 12:38:22.976079 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7313 12:38:22.978789 [-4] MIN Duty = 4875%(X100), DQS PI = 12
7314 12:38:22.982317 [-4] AVG Duty = 4937%(X100)
7315 12:38:22.982444
7316 12:38:22.985407 CH1 CLK Duty spec in!! Max-Min= 125%
7317 12:38:22.988968 [DutyScan_Calibration_Flow] ====Done====
7318 12:38:22.989070
7319 12:38:22.992531 [DutyScan_Calibration_Flow] k_type=1
7320 12:38:23.007979
7321 12:38:23.008329 ==DQS 0 ==
7322 12:38:23.011707 Final DQS duty delay cell = 0
7323 12:38:23.015262 [0] MAX Duty = 5250%(X100), DQS PI = 30
7324 12:38:23.018353 [0] MIN Duty = 4938%(X100), DQS PI = 40
7325 12:38:23.021552 [0] AVG Duty = 5094%(X100)
7326 12:38:23.021654
7327 12:38:23.021722 ==DQS 1 ==
7328 12:38:23.024770 Final DQS duty delay cell = -4
7329 12:38:23.028133 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7330 12:38:23.031279 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7331 12:38:23.034541 [-4] AVG Duty = 4922%(X100)
7332 12:38:23.034655
7333 12:38:23.038245 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7334 12:38:23.038354
7335 12:38:23.041254 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7336 12:38:23.044751 [DutyScan_Calibration_Flow] ====Done====
7337 12:38:23.044873
7338 12:38:23.047642 [DutyScan_Calibration_Flow] k_type=3
7339 12:38:23.065481
7340 12:38:23.065633 ==DQM 0 ==
7341 12:38:23.068869 Final DQM duty delay cell = 0
7342 12:38:23.072075 [0] MAX Duty = 5062%(X100), DQS PI = 30
7343 12:38:23.075471 [0] MIN Duty = 4782%(X100), DQS PI = 40
7344 12:38:23.078560 [0] AVG Duty = 4922%(X100)
7345 12:38:23.078653
7346 12:38:23.078717 ==DQM 1 ==
7347 12:38:23.081829 Final DQM duty delay cell = 0
7348 12:38:23.085861 [0] MAX Duty = 5000%(X100), DQS PI = 32
7349 12:38:23.088685 [0] MIN Duty = 4813%(X100), DQS PI = 0
7350 12:38:23.091868 [0] AVG Duty = 4906%(X100)
7351 12:38:23.091948
7352 12:38:23.094979 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7353 12:38:23.095058
7354 12:38:23.098646 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7355 12:38:23.101338 [DutyScan_Calibration_Flow] ====Done====
7356 12:38:23.101415
7357 12:38:23.105024 [DutyScan_Calibration_Flow] k_type=2
7358 12:38:23.121398
7359 12:38:23.121553 ==DQ 0 ==
7360 12:38:23.126292 Final DQ duty delay cell = -4
7361 12:38:23.128027 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7362 12:38:23.131696 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7363 12:38:23.134495 [-4] AVG Duty = 4891%(X100)
7364 12:38:23.134615
7365 12:38:23.134713 ==DQ 1 ==
7366 12:38:23.138216 Final DQ duty delay cell = 0
7367 12:38:23.140983 [0] MAX Duty = 5031%(X100), DQS PI = 32
7368 12:38:23.144450 [0] MIN Duty = 4875%(X100), DQS PI = 56
7369 12:38:23.147911 [0] AVG Duty = 4953%(X100)
7370 12:38:23.148023
7371 12:38:23.151219 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7372 12:38:23.151322
7373 12:38:23.154785 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7374 12:38:23.157959 [DutyScan_Calibration_Flow] ====Done====
7375 12:38:23.160838 nWR fixed to 30
7376 12:38:23.164338 [ModeRegInit_LP4] CH0 RK0
7377 12:38:23.164467 [ModeRegInit_LP4] CH0 RK1
7378 12:38:23.167992 [ModeRegInit_LP4] CH1 RK0
7379 12:38:23.171380 [ModeRegInit_LP4] CH1 RK1
7380 12:38:23.171540 match AC timing 5
7381 12:38:23.177404 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7382 12:38:23.181932 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7383 12:38:23.185256 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7384 12:38:23.190501 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7385 12:38:23.193796 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7386 12:38:23.197326 [MiockJmeterHQA]
7387 12:38:23.197415
7388 12:38:23.200407 [DramcMiockJmeter] u1RxGatingPI = 0
7389 12:38:23.200478 0 : 4252, 4027
7390 12:38:23.200541 4 : 4253, 4026
7391 12:38:23.204312 8 : 4368, 4142
7392 12:38:23.204394 12 : 4363, 4138
7393 12:38:23.206795 16 : 4363, 4138
7394 12:38:23.206905 20 : 4252, 4027
7395 12:38:23.210394 24 : 4252, 4027
7396 12:38:23.210500 28 : 4253, 4027
7397 12:38:23.213308 32 : 4363, 4137
7398 12:38:23.213399 36 : 4252, 4027
7399 12:38:23.213464 40 : 4363, 4137
7400 12:38:23.217542 44 : 4252, 4027
7401 12:38:23.217663 48 : 4252, 4027
7402 12:38:23.220061 52 : 4250, 4027
7403 12:38:23.220170 56 : 4252, 4029
7404 12:38:23.223847 60 : 4361, 4138
7405 12:38:23.223926 64 : 4252, 4027
7406 12:38:23.226753 68 : 4361, 4137
7407 12:38:23.226828 72 : 4250, 4026
7408 12:38:23.226893 76 : 4250, 4027
7409 12:38:23.230209 80 : 4250, 4027
7410 12:38:23.230298 84 : 4361, 4138
7411 12:38:23.233724 88 : 4250, 4027
7412 12:38:23.233795 92 : 4361, 4138
7413 12:38:23.236688 96 : 4250, 3017
7414 12:38:23.236763 100 : 4250, 0
7415 12:38:23.236835 104 : 4250, 0
7416 12:38:23.239845 108 : 4252, 0
7417 12:38:23.239925 112 : 4250, 0
7418 12:38:23.243162 116 : 4252, 0
7419 12:38:23.243264 120 : 4361, 0
7420 12:38:23.243355 124 : 4250, 0
7421 12:38:23.246585 128 : 4250, 0
7422 12:38:23.246666 132 : 4250, 0
7423 12:38:23.249545 136 : 4361, 0
7424 12:38:23.249618 140 : 4360, 0
7425 12:38:23.249690 144 : 4250, 0
7426 12:38:23.253392 148 : 4250, 0
7427 12:38:23.253469 152 : 4249, 0
7428 12:38:23.256616 156 : 4252, 0
7429 12:38:23.256700 160 : 4250, 0
7430 12:38:23.256763 164 : 4250, 0
7431 12:38:23.259880 168 : 4252, 0
7432 12:38:23.259976 172 : 4361, 0
7433 12:38:23.260043 176 : 4249, 0
7434 12:38:23.263629 180 : 4250, 0
7435 12:38:23.263716 184 : 4250, 0
7436 12:38:23.266210 188 : 4361, 0
7437 12:38:23.266286 192 : 4250, 0
7438 12:38:23.266355 196 : 4250, 0
7439 12:38:23.269545 200 : 4250, 0
7440 12:38:23.269630 204 : 4363, 0
7441 12:38:23.272983 208 : 4250, 0
7442 12:38:23.273063 212 : 4250, 0
7443 12:38:23.273129 216 : 4250, 0
7444 12:38:23.276308 220 : 4252, 501
7445 12:38:23.276384 224 : 4250, 3992
7446 12:38:23.279233 228 : 4250, 4027
7447 12:38:23.279351 232 : 4250, 4027
7448 12:38:23.282935 236 : 4250, 4027
7449 12:38:23.283024 240 : 4250, 4027
7450 12:38:23.285812 244 : 4250, 4026
7451 12:38:23.285897 248 : 4250, 4027
7452 12:38:23.289512 252 : 4252, 4029
7453 12:38:23.289597 256 : 4250, 4027
7454 12:38:23.293365 260 : 4361, 4137
7455 12:38:23.293451 264 : 4361, 4138
7456 12:38:23.295965 268 : 4250, 4027
7457 12:38:23.296075 272 : 4363, 4140
7458 12:38:23.296201 276 : 4250, 4027
7459 12:38:23.299490 280 : 4250, 4027
7460 12:38:23.299607 284 : 4250, 4027
7461 12:38:23.302549 288 : 4252, 4029
7462 12:38:23.302665 292 : 4250, 4027
7463 12:38:23.306240 296 : 4250, 4026
7464 12:38:23.306331 300 : 4250, 4027
7465 12:38:23.309412 304 : 4252, 4029
7466 12:38:23.309518 308 : 4250, 4027
7467 12:38:23.312176 312 : 4361, 4137
7468 12:38:23.312334 316 : 4361, 4138
7469 12:38:23.315788 320 : 4250, 4027
7470 12:38:23.315889 324 : 4363, 4140
7471 12:38:23.318863 328 : 4250, 4027
7472 12:38:23.318985 332 : 4250, 4009
7473 12:38:23.321965 336 : 4250, 2364
7474 12:38:23.322076 340 : 4252, 5
7475 12:38:23.322168
7476 12:38:23.325404 MIOCK jitter meter ch=0
7477 12:38:23.325496
7478 12:38:23.328682 1T = (340-100) = 240 dly cells
7479 12:38:23.332373 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7480 12:38:23.332459 ==
7481 12:38:23.335260 Dram Type= 6, Freq= 0, CH_0, rank 0
7482 12:38:23.341986 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7483 12:38:23.342102 ==
7484 12:38:23.345962 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7485 12:38:23.351761 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7486 12:38:23.355311 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7487 12:38:23.362064 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7488 12:38:23.369398 [CA 0] Center 43 (13~74) winsize 62
7489 12:38:23.373387 [CA 1] Center 42 (12~73) winsize 62
7490 12:38:23.376072 [CA 2] Center 37 (8~67) winsize 60
7491 12:38:23.379166 [CA 3] Center 37 (8~67) winsize 60
7492 12:38:23.382320 [CA 4] Center 36 (6~66) winsize 61
7493 12:38:23.386599 [CA 5] Center 35 (5~66) winsize 62
7494 12:38:23.386744
7495 12:38:23.389273 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7496 12:38:23.389365
7497 12:38:23.395585 [CATrainingPosCal] consider 1 rank data
7498 12:38:23.395696 u2DelayCellTimex100 = 271/100 ps
7499 12:38:23.402722 CA0 delay=43 (13~74),Diff = 8 PI (28 cell)
7500 12:38:23.405494 CA1 delay=42 (12~73),Diff = 7 PI (25 cell)
7501 12:38:23.408856 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7502 12:38:23.413041 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7503 12:38:23.415551 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7504 12:38:23.418907 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7505 12:38:23.419056
7506 12:38:23.422100 CA PerBit enable=1, Macro0, CA PI delay=35
7507 12:38:23.422260
7508 12:38:23.425790 [CBTSetCACLKResult] CA Dly = 35
7509 12:38:23.429195 CS Dly: 11 (0~42)
7510 12:38:23.432026 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7511 12:38:23.435759 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7512 12:38:23.435901 ==
7513 12:38:23.438498 Dram Type= 6, Freq= 0, CH_0, rank 1
7514 12:38:23.445539 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7515 12:38:23.445663 ==
7516 12:38:23.448528 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7517 12:38:23.455198 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7518 12:38:23.458499 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7519 12:38:23.465400 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7520 12:38:23.472797 [CA 0] Center 44 (14~75) winsize 62
7521 12:38:23.476456 [CA 1] Center 44 (14~74) winsize 61
7522 12:38:23.479670 [CA 2] Center 39 (10~69) winsize 60
7523 12:38:23.483214 [CA 3] Center 39 (10~68) winsize 59
7524 12:38:23.485903 [CA 4] Center 37 (7~67) winsize 61
7525 12:38:23.489171 [CA 5] Center 36 (7~66) winsize 60
7526 12:38:23.489256
7527 12:38:23.493136 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7528 12:38:23.493219
7529 12:38:23.498880 [CATrainingPosCal] consider 2 rank data
7530 12:38:23.498969 u2DelayCellTimex100 = 271/100 ps
7531 12:38:23.506033 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7532 12:38:23.509046 CA1 delay=43 (14~73),Diff = 7 PI (25 cell)
7533 12:38:23.512176 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7534 12:38:23.515632 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7535 12:38:23.519122 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7536 12:38:23.522318 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7537 12:38:23.522419
7538 12:38:23.525675 CA PerBit enable=1, Macro0, CA PI delay=36
7539 12:38:23.525771
7540 12:38:23.528610 [CBTSetCACLKResult] CA Dly = 36
7541 12:38:23.532150 CS Dly: 11 (0~43)
7542 12:38:23.535976 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7543 12:38:23.538582 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7544 12:38:23.538661
7545 12:38:23.545325 ----->DramcWriteLeveling(PI) begin...
7546 12:38:23.545418 ==
7547 12:38:23.548410 Dram Type= 6, Freq= 0, CH_0, rank 0
7548 12:38:23.551945 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7549 12:38:23.552031 ==
7550 12:38:23.554954 Write leveling (Byte 0): 34 => 34
7551 12:38:23.558361 Write leveling (Byte 1): 26 => 26
7552 12:38:23.561527 DramcWriteLeveling(PI) end<-----
7553 12:38:23.561616
7554 12:38:23.561683 ==
7555 12:38:23.564812 Dram Type= 6, Freq= 0, CH_0, rank 0
7556 12:38:23.568126 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7557 12:38:23.568212 ==
7558 12:38:23.571561 [Gating] SW mode calibration
7559 12:38:23.578112 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7560 12:38:23.584508 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7561 12:38:23.587721 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7562 12:38:23.591044 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7563 12:38:23.597654 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7564 12:38:23.601346 1 4 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7565 12:38:23.604673 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7566 12:38:23.611506 1 4 20 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
7567 12:38:23.614286 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7568 12:38:23.617412 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7569 12:38:23.624564 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7570 12:38:23.627250 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7571 12:38:23.630712 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7572 12:38:23.637016 1 5 12 | B1->B0 | 3434 2525 | 1 1 | (1 1) (1 0)
7573 12:38:23.641256 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7574 12:38:23.643906 1 5 20 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
7575 12:38:23.650389 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7576 12:38:23.653639 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 12:38:23.657018 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7578 12:38:23.663853 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7579 12:38:23.667480 1 6 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
7580 12:38:23.670567 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7581 12:38:23.676690 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7582 12:38:23.680265 1 6 20 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
7583 12:38:23.683509 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7584 12:38:23.690751 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7585 12:38:23.693498 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7586 12:38:23.696481 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7587 12:38:23.703214 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7588 12:38:23.706272 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7589 12:38:23.710084 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7590 12:38:23.716396 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7591 12:38:23.719581 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 12:38:23.723016 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 12:38:23.729699 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 12:38:23.732707 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 12:38:23.735904 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 12:38:23.743215 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 12:38:23.746126 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 12:38:23.749116 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 12:38:23.755662 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 12:38:23.759513 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 12:38:23.762696 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 12:38:23.769150 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7603 12:38:23.772967 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7604 12:38:23.775670 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7605 12:38:23.778794 Total UI for P1: 0, mck2ui 16
7606 12:38:23.782104 best dqsien dly found for B0: ( 1, 9, 6)
7607 12:38:23.789099 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7608 12:38:23.792161 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7609 12:38:23.795453 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7610 12:38:23.801844 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 12:38:23.801934 Total UI for P1: 0, mck2ui 16
7612 12:38:23.808466 best dqsien dly found for B1: ( 1, 9, 22)
7613 12:38:23.812272 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
7614 12:38:23.815416 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7615 12:38:23.815502
7616 12:38:23.818838 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
7617 12:38:23.822169 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7618 12:38:23.825349 [Gating] SW calibration Done
7619 12:38:23.825435 ==
7620 12:38:23.829539 Dram Type= 6, Freq= 0, CH_0, rank 0
7621 12:38:23.831694 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7622 12:38:23.831780 ==
7623 12:38:23.835414 RX Vref Scan: 0
7624 12:38:23.835499
7625 12:38:23.835564 RX Vref 0 -> 0, step: 1
7626 12:38:23.835624
7627 12:38:23.838296 RX Delay 0 -> 252, step: 8
7628 12:38:23.841676 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7629 12:38:23.848166 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7630 12:38:23.851852 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7631 12:38:23.855753 iDelay=192, Bit 3, Center 131 (80 ~ 183) 104
7632 12:38:23.858294 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7633 12:38:23.861511 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7634 12:38:23.868545 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7635 12:38:23.871880 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7636 12:38:23.874635 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7637 12:38:23.877937 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
7638 12:38:23.884356 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7639 12:38:23.887654 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7640 12:38:23.891277 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7641 12:38:23.894158 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7642 12:38:23.897470 iDelay=192, Bit 14, Center 139 (88 ~ 191) 104
7643 12:38:23.904306 iDelay=192, Bit 15, Center 131 (80 ~ 183) 104
7644 12:38:23.904400 ==
7645 12:38:23.907383 Dram Type= 6, Freq= 0, CH_0, rank 0
7646 12:38:23.911162 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7647 12:38:23.911255 ==
7648 12:38:23.911386 DQS Delay:
7649 12:38:23.914261 DQS0 = 0, DQS1 = 0
7650 12:38:23.914344 DQM Delay:
7651 12:38:23.917098 DQM0 = 132, DQM1 = 127
7652 12:38:23.917181 DQ Delay:
7653 12:38:23.920557 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
7654 12:38:23.923622 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7655 12:38:23.927576 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
7656 12:38:23.934081 DQ12 =135, DQ13 =131, DQ14 =139, DQ15 =131
7657 12:38:23.934168
7658 12:38:23.934233
7659 12:38:23.934293 ==
7660 12:38:23.937962 Dram Type= 6, Freq= 0, CH_0, rank 0
7661 12:38:23.940271 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7662 12:38:23.940355 ==
7663 12:38:23.940420
7664 12:38:23.940479
7665 12:38:23.944300 TX Vref Scan disable
7666 12:38:23.944382 == TX Byte 0 ==
7667 12:38:23.950485 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7668 12:38:23.953568 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7669 12:38:23.953653 == TX Byte 1 ==
7670 12:38:23.960153 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7671 12:38:23.963203 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7672 12:38:23.963305 ==
7673 12:38:23.966733 Dram Type= 6, Freq= 0, CH_0, rank 0
7674 12:38:23.970106 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7675 12:38:23.970191 ==
7676 12:38:23.984762
7677 12:38:23.988700 TX Vref early break, caculate TX vref
7678 12:38:23.991193 TX Vref=16, minBit 1, minWin=22, winSum=369
7679 12:38:23.994813 TX Vref=18, minBit 1, minWin=23, winSum=382
7680 12:38:23.997630 TX Vref=20, minBit 8, minWin=23, winSum=389
7681 12:38:24.001184 TX Vref=22, minBit 8, minWin=23, winSum=399
7682 12:38:24.004587 TX Vref=24, minBit 7, minWin=24, winSum=412
7683 12:38:24.010867 TX Vref=26, minBit 1, minWin=25, winSum=416
7684 12:38:24.014354 TX Vref=28, minBit 2, minWin=25, winSum=422
7685 12:38:24.017449 TX Vref=30, minBit 4, minWin=25, winSum=419
7686 12:38:24.020958 TX Vref=32, minBit 4, minWin=24, winSum=406
7687 12:38:24.024291 TX Vref=34, minBit 0, minWin=24, winSum=399
7688 12:38:24.030711 [TxChooseVref] Worse bit 2, Min win 25, Win sum 422, Final Vref 28
7689 12:38:24.030805
7690 12:38:24.033883 Final TX Range 0 Vref 28
7691 12:38:24.033966
7692 12:38:24.034030 ==
7693 12:38:24.037514 Dram Type= 6, Freq= 0, CH_0, rank 0
7694 12:38:24.040600 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7695 12:38:24.040684 ==
7696 12:38:24.040748
7697 12:38:24.040808
7698 12:38:24.043986 TX Vref Scan disable
7699 12:38:24.051302 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7700 12:38:24.051437 == TX Byte 0 ==
7701 12:38:24.054281 u2DelayCellOfst[0]=10 cells (3 PI)
7702 12:38:24.057145 u2DelayCellOfst[1]=14 cells (4 PI)
7703 12:38:24.060438 u2DelayCellOfst[2]=10 cells (3 PI)
7704 12:38:24.063934 u2DelayCellOfst[3]=10 cells (3 PI)
7705 12:38:24.067293 u2DelayCellOfst[4]=10 cells (3 PI)
7706 12:38:24.070971 u2DelayCellOfst[5]=0 cells (0 PI)
7707 12:38:24.073900 u2DelayCellOfst[6]=18 cells (5 PI)
7708 12:38:24.077245 u2DelayCellOfst[7]=14 cells (4 PI)
7709 12:38:24.080562 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7710 12:38:24.084512 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7711 12:38:24.086740 == TX Byte 1 ==
7712 12:38:24.090288 u2DelayCellOfst[8]=0 cells (0 PI)
7713 12:38:24.093347 u2DelayCellOfst[9]=0 cells (0 PI)
7714 12:38:24.096741 u2DelayCellOfst[10]=3 cells (1 PI)
7715 12:38:24.100520 u2DelayCellOfst[11]=3 cells (1 PI)
7716 12:38:24.100608 u2DelayCellOfst[12]=7 cells (2 PI)
7717 12:38:24.103248 u2DelayCellOfst[13]=10 cells (3 PI)
7718 12:38:24.106978 u2DelayCellOfst[14]=14 cells (4 PI)
7719 12:38:24.109856 u2DelayCellOfst[15]=10 cells (3 PI)
7720 12:38:24.116363 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7721 12:38:24.119710 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7722 12:38:24.123046 DramC Write-DBI on
7723 12:38:24.123133 ==
7724 12:38:24.126939 Dram Type= 6, Freq= 0, CH_0, rank 0
7725 12:38:24.129987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7726 12:38:24.130072 ==
7727 12:38:24.130137
7728 12:38:24.130196
7729 12:38:24.132688 TX Vref Scan disable
7730 12:38:24.132770 == TX Byte 0 ==
7731 12:38:24.140045 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7732 12:38:24.140135 == TX Byte 1 ==
7733 12:38:24.142350 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7734 12:38:24.145809 DramC Write-DBI off
7735 12:38:24.145925
7736 12:38:24.146019 [DATLAT]
7737 12:38:24.149198 Freq=1600, CH0 RK0
7738 12:38:24.149306
7739 12:38:24.149400 DATLAT Default: 0xf
7740 12:38:24.152690 0, 0xFFFF, sum = 0
7741 12:38:24.155795 1, 0xFFFF, sum = 0
7742 12:38:24.155944 2, 0xFFFF, sum = 0
7743 12:38:24.159167 3, 0xFFFF, sum = 0
7744 12:38:24.159276 4, 0xFFFF, sum = 0
7745 12:38:24.162372 5, 0xFFFF, sum = 0
7746 12:38:24.162486 6, 0xFFFF, sum = 0
7747 12:38:24.165421 7, 0xFFFF, sum = 0
7748 12:38:24.165530 8, 0xFFFF, sum = 0
7749 12:38:24.169193 9, 0xFFFF, sum = 0
7750 12:38:24.169303 10, 0xFFFF, sum = 0
7751 12:38:24.172032 11, 0xFFFF, sum = 0
7752 12:38:24.172125 12, 0xFFFF, sum = 0
7753 12:38:24.175866 13, 0xFFFF, sum = 0
7754 12:38:24.175951 14, 0x0, sum = 1
7755 12:38:24.179111 15, 0x0, sum = 2
7756 12:38:24.179197 16, 0x0, sum = 3
7757 12:38:24.182502 17, 0x0, sum = 4
7758 12:38:24.182589 best_step = 15
7759 12:38:24.182674
7760 12:38:24.182755 ==
7761 12:38:24.185546 Dram Type= 6, Freq= 0, CH_0, rank 0
7762 12:38:24.192490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7763 12:38:24.192583 ==
7764 12:38:24.192668 RX Vref Scan: 1
7765 12:38:24.192748
7766 12:38:24.195311 Set Vref Range= 24 -> 127
7767 12:38:24.195418
7768 12:38:24.199016 RX Vref 24 -> 127, step: 1
7769 12:38:24.199099
7770 12:38:24.199184 RX Delay 19 -> 252, step: 4
7771 12:38:24.201810
7772 12:38:24.201894 Set Vref, RX VrefLevel [Byte0]: 24
7773 12:38:24.205483 [Byte1]: 24
7774 12:38:24.209380
7775 12:38:24.209469 Set Vref, RX VrefLevel [Byte0]: 25
7776 12:38:24.213104 [Byte1]: 25
7777 12:38:24.216827
7778 12:38:24.216918 Set Vref, RX VrefLevel [Byte0]: 26
7779 12:38:24.220353 [Byte1]: 26
7780 12:38:24.224663
7781 12:38:24.224757 Set Vref, RX VrefLevel [Byte0]: 27
7782 12:38:24.228018 [Byte1]: 27
7783 12:38:24.232271
7784 12:38:24.232359 Set Vref, RX VrefLevel [Byte0]: 28
7785 12:38:24.235152 [Byte1]: 28
7786 12:38:24.239620
7787 12:38:24.239708 Set Vref, RX VrefLevel [Byte0]: 29
7788 12:38:24.243224 [Byte1]: 29
7789 12:38:24.247321
7790 12:38:24.247429 Set Vref, RX VrefLevel [Byte0]: 30
7791 12:38:24.250893 [Byte1]: 30
7792 12:38:24.255044
7793 12:38:24.255133 Set Vref, RX VrefLevel [Byte0]: 31
7794 12:38:24.261497 [Byte1]: 31
7795 12:38:24.261589
7796 12:38:24.264568 Set Vref, RX VrefLevel [Byte0]: 32
7797 12:38:24.267896 [Byte1]: 32
7798 12:38:24.268007
7799 12:38:24.271238 Set Vref, RX VrefLevel [Byte0]: 33
7800 12:38:24.274661 [Byte1]: 33
7801 12:38:24.277689
7802 12:38:24.277773 Set Vref, RX VrefLevel [Byte0]: 34
7803 12:38:24.281079 [Byte1]: 34
7804 12:38:24.285112
7805 12:38:24.285195 Set Vref, RX VrefLevel [Byte0]: 35
7806 12:38:24.288373 [Byte1]: 35
7807 12:38:24.292772
7808 12:38:24.292856 Set Vref, RX VrefLevel [Byte0]: 36
7809 12:38:24.296159 [Byte1]: 36
7810 12:38:24.300436
7811 12:38:24.300522 Set Vref, RX VrefLevel [Byte0]: 37
7812 12:38:24.303542 [Byte1]: 37
7813 12:38:24.307976
7814 12:38:24.308061 Set Vref, RX VrefLevel [Byte0]: 38
7815 12:38:24.311212 [Byte1]: 38
7816 12:38:24.315121
7817 12:38:24.315232 Set Vref, RX VrefLevel [Byte0]: 39
7818 12:38:24.318936 [Byte1]: 39
7819 12:38:24.322981
7820 12:38:24.323089 Set Vref, RX VrefLevel [Byte0]: 40
7821 12:38:24.326528 [Byte1]: 40
7822 12:38:24.330521
7823 12:38:24.330604 Set Vref, RX VrefLevel [Byte0]: 41
7824 12:38:24.333959 [Byte1]: 41
7825 12:38:24.337867
7826 12:38:24.337950 Set Vref, RX VrefLevel [Byte0]: 42
7827 12:38:24.341240 [Byte1]: 42
7828 12:38:24.345940
7829 12:38:24.346024 Set Vref, RX VrefLevel [Byte0]: 43
7830 12:38:24.348831 [Byte1]: 43
7831 12:38:24.353167
7832 12:38:24.353251 Set Vref, RX VrefLevel [Byte0]: 44
7833 12:38:24.356524 [Byte1]: 44
7834 12:38:24.361216
7835 12:38:24.361301 Set Vref, RX VrefLevel [Byte0]: 45
7836 12:38:24.363919 [Byte1]: 45
7837 12:38:24.368673
7838 12:38:24.368756 Set Vref, RX VrefLevel [Byte0]: 46
7839 12:38:24.372143 [Byte1]: 46
7840 12:38:24.375812
7841 12:38:24.375896 Set Vref, RX VrefLevel [Byte0]: 47
7842 12:38:24.379457 [Byte1]: 47
7843 12:38:24.383415
7844 12:38:24.383498 Set Vref, RX VrefLevel [Byte0]: 48
7845 12:38:24.386481 [Byte1]: 48
7846 12:38:24.391688
7847 12:38:24.391772 Set Vref, RX VrefLevel [Byte0]: 49
7848 12:38:24.394559 [Byte1]: 49
7849 12:38:24.398627
7850 12:38:24.398710 Set Vref, RX VrefLevel [Byte0]: 50
7851 12:38:24.402535 [Byte1]: 50
7852 12:38:24.406584
7853 12:38:24.406666 Set Vref, RX VrefLevel [Byte0]: 51
7854 12:38:24.409721 [Byte1]: 51
7855 12:38:24.414301
7856 12:38:24.414388 Set Vref, RX VrefLevel [Byte0]: 52
7857 12:38:24.417333 [Byte1]: 52
7858 12:38:24.421672
7859 12:38:24.421755 Set Vref, RX VrefLevel [Byte0]: 53
7860 12:38:24.424390 [Byte1]: 53
7861 12:38:24.429003
7862 12:38:24.429087 Set Vref, RX VrefLevel [Byte0]: 54
7863 12:38:24.432528 [Byte1]: 54
7864 12:38:24.436572
7865 12:38:24.436656 Set Vref, RX VrefLevel [Byte0]: 55
7866 12:38:24.440377 [Byte1]: 55
7867 12:38:24.444022
7868 12:38:24.444106 Set Vref, RX VrefLevel [Byte0]: 56
7869 12:38:24.447204 [Byte1]: 56
7870 12:38:24.451759
7871 12:38:24.451843 Set Vref, RX VrefLevel [Byte0]: 57
7872 12:38:24.457977 [Byte1]: 57
7873 12:38:24.458086
7874 12:38:24.461159 Set Vref, RX VrefLevel [Byte0]: 58
7875 12:38:24.465057 [Byte1]: 58
7876 12:38:24.465142
7877 12:38:24.467918 Set Vref, RX VrefLevel [Byte0]: 59
7878 12:38:24.471706 [Byte1]: 59
7879 12:38:24.471792
7880 12:38:24.474560 Set Vref, RX VrefLevel [Byte0]: 60
7881 12:38:24.478031 [Byte1]: 60
7882 12:38:24.482196
7883 12:38:24.482280 Set Vref, RX VrefLevel [Byte0]: 61
7884 12:38:24.485328 [Byte1]: 61
7885 12:38:24.490119
7886 12:38:24.490203 Set Vref, RX VrefLevel [Byte0]: 62
7887 12:38:24.492604 [Byte1]: 62
7888 12:38:24.496939
7889 12:38:24.497023 Set Vref, RX VrefLevel [Byte0]: 63
7890 12:38:24.501563 [Byte1]: 63
7891 12:38:24.504730
7892 12:38:24.504814 Set Vref, RX VrefLevel [Byte0]: 64
7893 12:38:24.508459 [Byte1]: 64
7894 12:38:24.512763
7895 12:38:24.512850 Set Vref, RX VrefLevel [Byte0]: 65
7896 12:38:24.515851 [Byte1]: 65
7897 12:38:24.520111
7898 12:38:24.520195 Set Vref, RX VrefLevel [Byte0]: 66
7899 12:38:24.523099 [Byte1]: 66
7900 12:38:24.527622
7901 12:38:24.527706 Set Vref, RX VrefLevel [Byte0]: 67
7902 12:38:24.530810 [Byte1]: 67
7903 12:38:24.535128
7904 12:38:24.535235 Set Vref, RX VrefLevel [Byte0]: 68
7905 12:38:24.538209 [Byte1]: 68
7906 12:38:24.543081
7907 12:38:24.543191 Set Vref, RX VrefLevel [Byte0]: 69
7908 12:38:24.545541 [Byte1]: 69
7909 12:38:24.550264
7910 12:38:24.550353 Set Vref, RX VrefLevel [Byte0]: 70
7911 12:38:24.553865 [Byte1]: 70
7912 12:38:24.557861
7913 12:38:24.557946 Set Vref, RX VrefLevel [Byte0]: 71
7914 12:38:24.561059 [Byte1]: 71
7915 12:38:24.565302
7916 12:38:24.565387 Set Vref, RX VrefLevel [Byte0]: 72
7917 12:38:24.569481 [Byte1]: 72
7918 12:38:24.572825
7919 12:38:24.572910 Set Vref, RX VrefLevel [Byte0]: 73
7920 12:38:24.576056 [Byte1]: 73
7921 12:38:24.580296
7922 12:38:24.580382 Set Vref, RX VrefLevel [Byte0]: 74
7923 12:38:24.583547 [Byte1]: 74
7924 12:38:24.588024
7925 12:38:24.588109 Set Vref, RX VrefLevel [Byte0]: 75
7926 12:38:24.591304 [Byte1]: 75
7927 12:38:24.595954
7928 12:38:24.596040 Set Vref, RX VrefLevel [Byte0]: 76
7929 12:38:24.599314 [Byte1]: 76
7930 12:38:24.603126
7931 12:38:24.603209 Final RX Vref Byte 0 = 54 to rank0
7932 12:38:24.606242 Final RX Vref Byte 1 = 58 to rank0
7933 12:38:24.610374 Final RX Vref Byte 0 = 54 to rank1
7934 12:38:24.613166 Final RX Vref Byte 1 = 58 to rank1==
7935 12:38:24.616449 Dram Type= 6, Freq= 0, CH_0, rank 0
7936 12:38:24.623194 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7937 12:38:24.623313 ==
7938 12:38:24.623459 DQS Delay:
7939 12:38:24.626604 DQS0 = 0, DQS1 = 0
7940 12:38:24.626689 DQM Delay:
7941 12:38:24.626772 DQM0 = 128, DQM1 = 124
7942 12:38:24.629515 DQ Delay:
7943 12:38:24.632770 DQ0 =132, DQ1 =130, DQ2 =124, DQ3 =124
7944 12:38:24.636117 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =134
7945 12:38:24.639446 DQ8 =112, DQ9 =110, DQ10 =126, DQ11 =120
7946 12:38:24.642817 DQ12 =132, DQ13 =130, DQ14 =134, DQ15 =130
7947 12:38:24.642926
7948 12:38:24.643025
7949 12:38:24.643122
7950 12:38:24.646768 [DramC_TX_OE_Calibration] TA2
7951 12:38:24.649942 Original DQ_B0 (3 6) =30, OEN = 27
7952 12:38:24.652986 Original DQ_B1 (3 6) =30, OEN = 27
7953 12:38:24.655715 24, 0x0, End_B0=24 End_B1=24
7954 12:38:24.659545 25, 0x0, End_B0=25 End_B1=25
7955 12:38:24.659631 26, 0x0, End_B0=26 End_B1=26
7956 12:38:24.662255 27, 0x0, End_B0=27 End_B1=27
7957 12:38:24.665514 28, 0x0, End_B0=28 End_B1=28
7958 12:38:24.669302 29, 0x0, End_B0=29 End_B1=29
7959 12:38:24.669390 30, 0x0, End_B0=30 End_B1=30
7960 12:38:24.672488 31, 0x5151, End_B0=30 End_B1=30
7961 12:38:24.675572 Byte0 end_step=30 best_step=27
7962 12:38:24.678883 Byte1 end_step=30 best_step=27
7963 12:38:24.681958 Byte0 TX OE(2T, 0.5T) = (3, 3)
7964 12:38:24.685538 Byte1 TX OE(2T, 0.5T) = (3, 3)
7965 12:38:24.685628
7966 12:38:24.685713
7967 12:38:24.692609 [DQSOSCAuto] RK0, (LSB)MR18= 0x1613, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
7968 12:38:24.695067 CH0 RK0: MR19=303, MR18=1613
7969 12:38:24.702064 CH0_RK0: MR19=0x303, MR18=0x1613, DQSOSC=398, MR23=63, INC=23, DEC=15
7970 12:38:24.702162
7971 12:38:24.705245 ----->DramcWriteLeveling(PI) begin...
7972 12:38:24.705334 ==
7973 12:38:24.708347 Dram Type= 6, Freq= 0, CH_0, rank 1
7974 12:38:24.711773 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7975 12:38:24.711859 ==
7976 12:38:24.714943 Write leveling (Byte 0): 35 => 35
7977 12:38:24.718643 Write leveling (Byte 1): 27 => 27
7978 12:38:24.721787 DramcWriteLeveling(PI) end<-----
7979 12:38:24.721871
7980 12:38:24.721936 ==
7981 12:38:24.725021 Dram Type= 6, Freq= 0, CH_0, rank 1
7982 12:38:24.731647 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7983 12:38:24.731731 ==
7984 12:38:24.731796 [Gating] SW mode calibration
7985 12:38:24.742070 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7986 12:38:24.744708 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7987 12:38:24.748679 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7988 12:38:24.754417 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7989 12:38:24.758014 1 4 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
7990 12:38:24.764271 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7991 12:38:24.767602 1 4 16 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
7992 12:38:24.771257 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7993 12:38:24.774934 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7994 12:38:24.781069 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7995 12:38:24.784174 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7996 12:38:24.791088 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7997 12:38:24.793827 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
7998 12:38:24.797306 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
7999 12:38:24.803746 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8000 12:38:24.806993 1 5 20 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
8001 12:38:24.811208 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8002 12:38:24.816911 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8003 12:38:24.820191 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 12:38:24.823170 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8005 12:38:24.829865 1 6 8 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8006 12:38:24.833263 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8007 12:38:24.836192 1 6 16 | B1->B0 | 3030 4646 | 1 0 | (0 0) (0 0)
8008 12:38:24.843245 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8009 12:38:24.846295 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8010 12:38:24.849675 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8011 12:38:24.856041 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8012 12:38:24.859367 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8013 12:38:24.863276 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8014 12:38:24.869129 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8015 12:38:24.872719 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8016 12:38:24.876715 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8017 12:38:24.882709 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8018 12:38:24.885631 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 12:38:24.889075 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 12:38:24.895604 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 12:38:24.898711 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 12:38:24.902155 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 12:38:24.909192 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 12:38:24.912297 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 12:38:24.915916 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 12:38:24.922225 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 12:38:24.925367 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 12:38:24.928513 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8029 12:38:24.935493 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8030 12:38:24.938573 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8031 12:38:24.941628 Total UI for P1: 0, mck2ui 16
8032 12:38:24.945021 best dqsien dly found for B0: ( 1, 9, 6)
8033 12:38:24.948697 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8034 12:38:24.954908 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8035 12:38:24.957915 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 12:38:24.961308 Total UI for P1: 0, mck2ui 16
8037 12:38:24.964685 best dqsien dly found for B1: ( 1, 9, 18)
8038 12:38:24.967849 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8039 12:38:24.971179 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8040 12:38:24.971277
8041 12:38:24.974713 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8042 12:38:24.977752 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8043 12:38:24.981252 [Gating] SW calibration Done
8044 12:38:24.981334 ==
8045 12:38:24.984808 Dram Type= 6, Freq= 0, CH_0, rank 1
8046 12:38:24.991385 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8047 12:38:24.991483 ==
8048 12:38:24.991546 RX Vref Scan: 0
8049 12:38:24.991606
8050 12:38:24.994224 RX Vref 0 -> 0, step: 1
8051 12:38:24.994304
8052 12:38:24.997900 RX Delay 0 -> 252, step: 8
8053 12:38:25.001326 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8054 12:38:25.005015 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8055 12:38:25.007493 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8056 12:38:25.014335 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8057 12:38:25.018159 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8058 12:38:25.020660 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8059 12:38:25.025201 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8060 12:38:25.027272 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8061 12:38:25.033884 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8062 12:38:25.037250 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8063 12:38:25.040821 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8064 12:38:25.044034 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8065 12:38:25.046864 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8066 12:38:25.053690 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8067 12:38:25.057904 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8068 12:38:25.060285 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8069 12:38:25.060369 ==
8070 12:38:25.063903 Dram Type= 6, Freq= 0, CH_0, rank 1
8071 12:38:25.067380 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8072 12:38:25.070487 ==
8073 12:38:25.070569 DQS Delay:
8074 12:38:25.070634 DQS0 = 0, DQS1 = 0
8075 12:38:25.073408 DQM Delay:
8076 12:38:25.073490 DQM0 = 132, DQM1 = 125
8077 12:38:25.076711 DQ Delay:
8078 12:38:25.080160 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =127
8079 12:38:25.083186 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8080 12:38:25.087223 DQ8 =115, DQ9 =111, DQ10 =131, DQ11 =119
8081 12:38:25.089894 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8082 12:38:25.089977
8083 12:38:25.090042
8084 12:38:25.090101 ==
8085 12:38:25.093141 Dram Type= 6, Freq= 0, CH_0, rank 1
8086 12:38:25.096788 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8087 12:38:25.096872 ==
8088 12:38:25.100071
8089 12:38:25.100151
8090 12:38:25.100215 TX Vref Scan disable
8091 12:38:25.103551 == TX Byte 0 ==
8092 12:38:25.106477 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8093 12:38:25.110050 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8094 12:38:25.112983 == TX Byte 1 ==
8095 12:38:25.116141 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8096 12:38:25.119398 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8097 12:38:25.119507 ==
8098 12:38:25.122705 Dram Type= 6, Freq= 0, CH_0, rank 1
8099 12:38:25.129164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8100 12:38:25.129247 ==
8101 12:38:25.142061
8102 12:38:25.145472 TX Vref early break, caculate TX vref
8103 12:38:25.148626 TX Vref=16, minBit 1, minWin=23, winSum=384
8104 12:38:25.152207 TX Vref=18, minBit 8, minWin=23, winSum=389
8105 12:38:25.155293 TX Vref=20, minBit 1, minWin=24, winSum=397
8106 12:38:25.158780 TX Vref=22, minBit 2, minWin=24, winSum=404
8107 12:38:25.162167 TX Vref=24, minBit 2, minWin=25, winSum=415
8108 12:38:25.168450 TX Vref=26, minBit 1, minWin=25, winSum=419
8109 12:38:25.171669 TX Vref=28, minBit 0, minWin=26, winSum=426
8110 12:38:25.175100 TX Vref=30, minBit 1, minWin=25, winSum=419
8111 12:38:25.178498 TX Vref=32, minBit 0, minWin=24, winSum=406
8112 12:38:25.182064 TX Vref=34, minBit 6, minWin=24, winSum=398
8113 12:38:25.188278 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
8114 12:38:25.188391
8115 12:38:25.191716 Final TX Range 0 Vref 28
8116 12:38:25.191798
8117 12:38:25.191861 ==
8118 12:38:25.195394 Dram Type= 6, Freq= 0, CH_0, rank 1
8119 12:38:25.198311 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8120 12:38:25.198392 ==
8121 12:38:25.198457
8122 12:38:25.198515
8123 12:38:25.201727 TX Vref Scan disable
8124 12:38:25.208789 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8125 12:38:25.208870 == TX Byte 0 ==
8126 12:38:25.211635 u2DelayCellOfst[0]=10 cells (3 PI)
8127 12:38:25.215083 u2DelayCellOfst[1]=14 cells (4 PI)
8128 12:38:25.217836 u2DelayCellOfst[2]=7 cells (2 PI)
8129 12:38:25.221440 u2DelayCellOfst[3]=10 cells (3 PI)
8130 12:38:25.224687 u2DelayCellOfst[4]=7 cells (2 PI)
8131 12:38:25.228138 u2DelayCellOfst[5]=0 cells (0 PI)
8132 12:38:25.231184 u2DelayCellOfst[6]=14 cells (4 PI)
8133 12:38:25.234348 u2DelayCellOfst[7]=14 cells (4 PI)
8134 12:38:25.238068 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8135 12:38:25.241214 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8136 12:38:25.244779 == TX Byte 1 ==
8137 12:38:25.247914 u2DelayCellOfst[8]=0 cells (0 PI)
8138 12:38:25.251211 u2DelayCellOfst[9]=0 cells (0 PI)
8139 12:38:25.251319 u2DelayCellOfst[10]=7 cells (2 PI)
8140 12:38:25.254354 u2DelayCellOfst[11]=0 cells (0 PI)
8141 12:38:25.257584 u2DelayCellOfst[12]=10 cells (3 PI)
8142 12:38:25.260896 u2DelayCellOfst[13]=10 cells (3 PI)
8143 12:38:25.264381 u2DelayCellOfst[14]=18 cells (5 PI)
8144 12:38:25.267515 u2DelayCellOfst[15]=10 cells (3 PI)
8145 12:38:25.274149 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8146 12:38:25.277792 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8147 12:38:25.277954 DramC Write-DBI on
8148 12:38:25.278030 ==
8149 12:38:25.281274 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 12:38:25.287421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 12:38:25.287597 ==
8152 12:38:25.287681
8153 12:38:25.287749
8154 12:38:25.291432 TX Vref Scan disable
8155 12:38:25.291585 == TX Byte 0 ==
8156 12:38:25.297729 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8157 12:38:25.297887 == TX Byte 1 ==
8158 12:38:25.300792 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8159 12:38:25.303772 DramC Write-DBI off
8160 12:38:25.303935
8161 12:38:25.304014 [DATLAT]
8162 12:38:25.307236 Freq=1600, CH0 RK1
8163 12:38:25.307420
8164 12:38:25.307528 DATLAT Default: 0xf
8165 12:38:25.310512 0, 0xFFFF, sum = 0
8166 12:38:25.310658 1, 0xFFFF, sum = 0
8167 12:38:25.313437 2, 0xFFFF, sum = 0
8168 12:38:25.313540 3, 0xFFFF, sum = 0
8169 12:38:25.317340 4, 0xFFFF, sum = 0
8170 12:38:25.317531 5, 0xFFFF, sum = 0
8171 12:38:25.320205 6, 0xFFFF, sum = 0
8172 12:38:25.323975 7, 0xFFFF, sum = 0
8173 12:38:25.324175 8, 0xFFFF, sum = 0
8174 12:38:25.326921 9, 0xFFFF, sum = 0
8175 12:38:25.327118 10, 0xFFFF, sum = 0
8176 12:38:25.330336 11, 0xFFFF, sum = 0
8177 12:38:25.330610 12, 0xFFFF, sum = 0
8178 12:38:25.333534 13, 0xFFFF, sum = 0
8179 12:38:25.333774 14, 0x0, sum = 1
8180 12:38:25.336969 15, 0x0, sum = 2
8181 12:38:25.337204 16, 0x0, sum = 3
8182 12:38:25.340101 17, 0x0, sum = 4
8183 12:38:25.340302 best_step = 15
8184 12:38:25.340443
8185 12:38:25.340570 ==
8186 12:38:25.343797 Dram Type= 6, Freq= 0, CH_0, rank 1
8187 12:38:25.347317 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8188 12:38:25.350142 ==
8189 12:38:25.350464 RX Vref Scan: 0
8190 12:38:25.350668
8191 12:38:25.353528 RX Vref 0 -> 0, step: 1
8192 12:38:25.353924
8193 12:38:25.354178 RX Delay 11 -> 252, step: 4
8194 12:38:25.360991 iDelay=191, Bit 0, Center 126 (79 ~ 174) 96
8195 12:38:25.364140 iDelay=191, Bit 1, Center 132 (79 ~ 186) 108
8196 12:38:25.367843 iDelay=191, Bit 2, Center 126 (75 ~ 178) 104
8197 12:38:25.370394 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8198 12:38:25.374367 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8199 12:38:25.381052 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8200 12:38:25.383532 iDelay=191, Bit 6, Center 138 (91 ~ 186) 96
8201 12:38:25.386888 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8202 12:38:25.390269 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8203 12:38:25.393331 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8204 12:38:25.400196 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8205 12:38:25.403500 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8206 12:38:25.406513 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8207 12:38:25.409907 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8208 12:38:25.416523 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8209 12:38:25.419524 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8210 12:38:25.419625 ==
8211 12:38:25.422915 Dram Type= 6, Freq= 0, CH_0, rank 1
8212 12:38:25.426537 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8213 12:38:25.426638 ==
8214 12:38:25.429817 DQS Delay:
8215 12:38:25.429905 DQS0 = 0, DQS1 = 0
8216 12:38:25.429972 DQM Delay:
8217 12:38:25.432877 DQM0 = 129, DQM1 = 124
8218 12:38:25.432959 DQ Delay:
8219 12:38:25.436520 DQ0 =126, DQ1 =132, DQ2 =126, DQ3 =126
8220 12:38:25.439479 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =134
8221 12:38:25.446544 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8222 12:38:25.449288 DQ12 =128, DQ13 =130, DQ14 =136, DQ15 =132
8223 12:38:25.449371
8224 12:38:25.449436
8225 12:38:25.449496
8226 12:38:25.452639 [DramC_TX_OE_Calibration] TA2
8227 12:38:25.455845 Original DQ_B0 (3 6) =30, OEN = 27
8228 12:38:25.459190 Original DQ_B1 (3 6) =30, OEN = 27
8229 12:38:25.459273 24, 0x0, End_B0=24 End_B1=24
8230 12:38:25.462776 25, 0x0, End_B0=25 End_B1=25
8231 12:38:25.466668 26, 0x0, End_B0=26 End_B1=26
8232 12:38:25.469405 27, 0x0, End_B0=27 End_B1=27
8233 12:38:25.469488 28, 0x0, End_B0=28 End_B1=28
8234 12:38:25.472350 29, 0x0, End_B0=29 End_B1=29
8235 12:38:25.475880 30, 0x0, End_B0=30 End_B1=30
8236 12:38:25.479635 31, 0x5151, End_B0=30 End_B1=30
8237 12:38:25.482898 Byte0 end_step=30 best_step=27
8238 12:38:25.485614 Byte1 end_step=30 best_step=27
8239 12:38:25.485696 Byte0 TX OE(2T, 0.5T) = (3, 3)
8240 12:38:25.489365 Byte1 TX OE(2T, 0.5T) = (3, 3)
8241 12:38:25.489446
8242 12:38:25.489510
8243 12:38:25.499300 [DQSOSCAuto] RK1, (LSB)MR18= 0x1411, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 399 ps
8244 12:38:25.502278 CH0 RK1: MR19=303, MR18=1411
8245 12:38:25.508503 CH0_RK1: MR19=0x303, MR18=0x1411, DQSOSC=399, MR23=63, INC=23, DEC=15
8246 12:38:25.508586 [RxdqsGatingPostProcess] freq 1600
8247 12:38:25.515533 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8248 12:38:25.518941 best DQS0 dly(2T, 0.5T) = (1, 1)
8249 12:38:25.521956 best DQS1 dly(2T, 0.5T) = (1, 1)
8250 12:38:25.525234 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8251 12:38:25.528407 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8252 12:38:25.531757 best DQS0 dly(2T, 0.5T) = (1, 1)
8253 12:38:25.535078 best DQS1 dly(2T, 0.5T) = (1, 1)
8254 12:38:25.538416 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8255 12:38:25.541601 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8256 12:38:25.541682 Pre-setting of DQS Precalculation
8257 12:38:25.548663 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8258 12:38:25.548771 ==
8259 12:38:25.551485 Dram Type= 6, Freq= 0, CH_1, rank 0
8260 12:38:25.555201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8261 12:38:25.555283 ==
8262 12:38:25.561210 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8263 12:38:25.564860 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8264 12:38:25.571246 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8265 12:38:25.575355 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8266 12:38:25.584819 [CA 0] Center 42 (12~72) winsize 61
8267 12:38:25.587907 [CA 1] Center 42 (13~72) winsize 60
8268 12:38:25.591809 [CA 2] Center 38 (9~68) winsize 60
8269 12:38:25.594519 [CA 3] Center 37 (8~67) winsize 60
8270 12:38:25.597993 [CA 4] Center 38 (8~69) winsize 62
8271 12:38:25.600907 [CA 5] Center 37 (7~67) winsize 61
8272 12:38:25.600988
8273 12:38:25.604267 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8274 12:38:25.604349
8275 12:38:25.611352 [CATrainingPosCal] consider 1 rank data
8276 12:38:25.611466 u2DelayCellTimex100 = 271/100 ps
8277 12:38:25.617381 CA0 delay=42 (12~72),Diff = 5 PI (18 cell)
8278 12:38:25.620926 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8279 12:38:25.624408 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8280 12:38:25.627656 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8281 12:38:25.630454 CA4 delay=38 (8~69),Diff = 1 PI (3 cell)
8282 12:38:25.634107 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8283 12:38:25.634188
8284 12:38:25.637453 CA PerBit enable=1, Macro0, CA PI delay=37
8285 12:38:25.637534
8286 12:38:25.640236 [CBTSetCACLKResult] CA Dly = 37
8287 12:38:25.644316 CS Dly: 8 (0~39)
8288 12:38:25.647639 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8289 12:38:25.650310 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8290 12:38:25.650423 ==
8291 12:38:25.653583 Dram Type= 6, Freq= 0, CH_1, rank 1
8292 12:38:25.660438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8293 12:38:25.660523 ==
8294 12:38:25.664185 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8295 12:38:25.670784 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8296 12:38:25.673671 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8297 12:38:25.680294 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8298 12:38:25.687797 [CA 0] Center 42 (12~72) winsize 61
8299 12:38:25.691181 [CA 1] Center 42 (13~72) winsize 60
8300 12:38:25.694385 [CA 2] Center 38 (9~68) winsize 60
8301 12:38:25.697552 [CA 3] Center 36 (7~66) winsize 60
8302 12:38:25.700979 [CA 4] Center 37 (8~67) winsize 60
8303 12:38:25.704247 [CA 5] Center 37 (7~67) winsize 61
8304 12:38:25.704333
8305 12:38:25.707647 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8306 12:38:25.707728
8307 12:38:25.714755 [CATrainingPosCal] consider 2 rank data
8308 12:38:25.714837 u2DelayCellTimex100 = 271/100 ps
8309 12:38:25.720723 CA0 delay=42 (12~72),Diff = 5 PI (18 cell)
8310 12:38:25.724454 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8311 12:38:25.728023 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8312 12:38:25.730398 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8313 12:38:25.733661 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8314 12:38:25.737466 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8315 12:38:25.737569
8316 12:38:25.740882 CA PerBit enable=1, Macro0, CA PI delay=37
8317 12:38:25.740975
8318 12:38:25.743607 [CBTSetCACLKResult] CA Dly = 37
8319 12:38:25.747244 CS Dly: 9 (0~42)
8320 12:38:25.750297 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8321 12:38:25.753731 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8322 12:38:25.753814
8323 12:38:25.757330 ----->DramcWriteLeveling(PI) begin...
8324 12:38:25.757414 ==
8325 12:38:25.760046 Dram Type= 6, Freq= 0, CH_1, rank 0
8326 12:38:25.766726 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8327 12:38:25.766840 ==
8328 12:38:25.770293 Write leveling (Byte 0): 25 => 25
8329 12:38:25.773580 Write leveling (Byte 1): 27 => 27
8330 12:38:25.773739 DramcWriteLeveling(PI) end<-----
8331 12:38:25.777013
8332 12:38:25.777170 ==
8333 12:38:25.780938 Dram Type= 6, Freq= 0, CH_1, rank 0
8334 12:38:25.783472 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8335 12:38:25.783629 ==
8336 12:38:25.787608 [Gating] SW mode calibration
8337 12:38:25.793362 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8338 12:38:25.796379 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8339 12:38:25.803498 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 12:38:25.806392 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8341 12:38:25.810173 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
8342 12:38:25.816579 1 4 12 | B1->B0 | 2525 3333 | 0 1 | (0 0) (1 1)
8343 12:38:25.819816 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8344 12:38:25.823045 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8345 12:38:25.829643 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8346 12:38:25.832774 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8347 12:38:25.839796 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 12:38:25.843279 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 12:38:25.846750 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8350 12:38:25.853150 1 5 12 | B1->B0 | 3333 2727 | 0 0 | (0 1) (1 0)
8351 12:38:25.856064 1 5 16 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8352 12:38:25.859330 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8353 12:38:25.865775 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 12:38:25.869583 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 12:38:25.872742 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 12:38:25.878939 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 12:38:25.882286 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8358 12:38:25.885627 1 6 12 | B1->B0 | 2828 4242 | 1 1 | (0 0) (0 0)
8359 12:38:25.892212 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8360 12:38:25.895285 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8361 12:38:25.898891 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 12:38:25.905100 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 12:38:25.908417 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 12:38:25.912069 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 12:38:25.918380 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 12:38:25.921870 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8367 12:38:25.925388 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8368 12:38:25.931594 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 12:38:25.934988 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 12:38:25.938533 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 12:38:25.945066 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 12:38:25.948519 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 12:38:25.951852 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 12:38:25.957863 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 12:38:25.961085 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 12:38:25.965415 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 12:38:25.967716 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 12:38:25.975306 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 12:38:25.978138 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 12:38:25.981369 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 12:38:25.987978 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 12:38:25.991029 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8383 12:38:25.994723 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8384 12:38:26.000993 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 12:38:26.004485 Total UI for P1: 0, mck2ui 16
8386 12:38:26.007878 best dqsien dly found for B0: ( 1, 9, 14)
8387 12:38:26.011000 Total UI for P1: 0, mck2ui 16
8388 12:38:26.014620 best dqsien dly found for B1: ( 1, 9, 14)
8389 12:38:26.017811 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8390 12:38:26.020922 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8391 12:38:26.021282
8392 12:38:26.024056 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8393 12:38:26.027243 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8394 12:38:26.031117 [Gating] SW calibration Done
8395 12:38:26.031510 ==
8396 12:38:26.034393 Dram Type= 6, Freq= 0, CH_1, rank 0
8397 12:38:26.037333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8398 12:38:26.037691 ==
8399 12:38:26.040942 RX Vref Scan: 0
8400 12:38:26.041297
8401 12:38:26.044077 RX Vref 0 -> 0, step: 1
8402 12:38:26.044436
8403 12:38:26.044717 RX Delay 0 -> 252, step: 8
8404 12:38:26.050436 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8405 12:38:26.054341 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8406 12:38:26.057083 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8407 12:38:26.060288 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8408 12:38:26.063849 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8409 12:38:26.070145 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8410 12:38:26.073435 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8411 12:38:26.076594 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8412 12:38:26.080413 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8413 12:38:26.087329 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8414 12:38:26.089815 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8415 12:38:26.093290 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8416 12:38:26.096585 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8417 12:38:26.099785 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8418 12:38:26.106204 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8419 12:38:26.109738 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8420 12:38:26.109940 ==
8421 12:38:26.112897 Dram Type= 6, Freq= 0, CH_1, rank 0
8422 12:38:26.116268 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8423 12:38:26.116512 ==
8424 12:38:26.119465 DQS Delay:
8425 12:38:26.119665 DQS0 = 0, DQS1 = 0
8426 12:38:26.119826 DQM Delay:
8427 12:38:26.122860 DQM0 = 134, DQM1 = 130
8428 12:38:26.123061 DQ Delay:
8429 12:38:26.126009 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8430 12:38:26.129724 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =127
8431 12:38:26.136279 DQ8 =111, DQ9 =119, DQ10 =131, DQ11 =123
8432 12:38:26.139436 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8433 12:38:26.139637
8434 12:38:26.139794
8435 12:38:26.139940 ==
8436 12:38:26.142811 Dram Type= 6, Freq= 0, CH_1, rank 0
8437 12:38:26.145732 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8438 12:38:26.145933 ==
8439 12:38:26.146091
8440 12:38:26.146236
8441 12:38:26.149416 TX Vref Scan disable
8442 12:38:26.152498 == TX Byte 0 ==
8443 12:38:26.155965 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8444 12:38:26.159086 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8445 12:38:26.162363 == TX Byte 1 ==
8446 12:38:26.165870 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8447 12:38:26.169058 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8448 12:38:26.169258 ==
8449 12:38:26.172615 Dram Type= 6, Freq= 0, CH_1, rank 0
8450 12:38:26.175894 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8451 12:38:26.178596 ==
8452 12:38:26.189981
8453 12:38:26.193718 TX Vref early break, caculate TX vref
8454 12:38:26.196558 TX Vref=16, minBit 8, minWin=21, winSum=365
8455 12:38:26.199677 TX Vref=18, minBit 8, minWin=22, winSum=378
8456 12:38:26.203219 TX Vref=20, minBit 8, minWin=23, winSum=387
8457 12:38:26.206372 TX Vref=22, minBit 8, minWin=23, winSum=397
8458 12:38:26.209600 TX Vref=24, minBit 8, minWin=24, winSum=405
8459 12:38:26.216131 TX Vref=26, minBit 3, minWin=25, winSum=412
8460 12:38:26.219636 TX Vref=28, minBit 0, minWin=25, winSum=419
8461 12:38:26.222869 TX Vref=30, minBit 0, minWin=25, winSum=417
8462 12:38:26.226264 TX Vref=32, minBit 9, minWin=24, winSum=403
8463 12:38:26.229405 TX Vref=34, minBit 8, minWin=24, winSum=397
8464 12:38:26.236332 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 28
8465 12:38:26.236855
8466 12:38:26.239506 Final TX Range 0 Vref 28
8467 12:38:26.239912
8468 12:38:26.240217 ==
8469 12:38:26.243401 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 12:38:26.246817 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 12:38:26.247360 ==
8472 12:38:26.247761
8473 12:38:26.248068
8474 12:38:26.249671 TX Vref Scan disable
8475 12:38:26.256627 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8476 12:38:26.257157 == TX Byte 0 ==
8477 12:38:26.259717 u2DelayCellOfst[0]=18 cells (5 PI)
8478 12:38:26.262771 u2DelayCellOfst[1]=10 cells (3 PI)
8479 12:38:26.266280 u2DelayCellOfst[2]=0 cells (0 PI)
8480 12:38:26.268904 u2DelayCellOfst[3]=7 cells (2 PI)
8481 12:38:26.272206 u2DelayCellOfst[4]=10 cells (3 PI)
8482 12:38:26.276195 u2DelayCellOfst[5]=18 cells (5 PI)
8483 12:38:26.278851 u2DelayCellOfst[6]=18 cells (5 PI)
8484 12:38:26.282822 u2DelayCellOfst[7]=7 cells (2 PI)
8485 12:38:26.285473 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8486 12:38:26.289282 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8487 12:38:26.291884 == TX Byte 1 ==
8488 12:38:26.295063 u2DelayCellOfst[8]=0 cells (0 PI)
8489 12:38:26.298577 u2DelayCellOfst[9]=3 cells (1 PI)
8490 12:38:26.302040 u2DelayCellOfst[10]=10 cells (3 PI)
8491 12:38:26.302418 u2DelayCellOfst[11]=7 cells (2 PI)
8492 12:38:26.305250 u2DelayCellOfst[12]=14 cells (4 PI)
8493 12:38:26.308715 u2DelayCellOfst[13]=18 cells (5 PI)
8494 12:38:26.311968 u2DelayCellOfst[14]=18 cells (5 PI)
8495 12:38:26.315050 u2DelayCellOfst[15]=18 cells (5 PI)
8496 12:38:26.321508 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8497 12:38:26.325082 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8498 12:38:26.325476 DramC Write-DBI on
8499 12:38:26.327914 ==
8500 12:38:26.331704 Dram Type= 6, Freq= 0, CH_1, rank 0
8501 12:38:26.334682 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8502 12:38:26.335071 ==
8503 12:38:26.335425
8504 12:38:26.335727
8505 12:38:26.338071 TX Vref Scan disable
8506 12:38:26.338395 == TX Byte 0 ==
8507 12:38:26.344547 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8508 12:38:26.344827 == TX Byte 1 ==
8509 12:38:26.347695 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8510 12:38:26.351397 DramC Write-DBI off
8511 12:38:26.351611
8512 12:38:26.351780 [DATLAT]
8513 12:38:26.354276 Freq=1600, CH1 RK0
8514 12:38:26.354488
8515 12:38:26.354656 DATLAT Default: 0xf
8516 12:38:26.357927 0, 0xFFFF, sum = 0
8517 12:38:26.358142 1, 0xFFFF, sum = 0
8518 12:38:26.361129 2, 0xFFFF, sum = 0
8519 12:38:26.361344 3, 0xFFFF, sum = 0
8520 12:38:26.364665 4, 0xFFFF, sum = 0
8521 12:38:26.364966 5, 0xFFFF, sum = 0
8522 12:38:26.367969 6, 0xFFFF, sum = 0
8523 12:38:26.371384 7, 0xFFFF, sum = 0
8524 12:38:26.371687 8, 0xFFFF, sum = 0
8525 12:38:26.374875 9, 0xFFFF, sum = 0
8526 12:38:26.375173 10, 0xFFFF, sum = 0
8527 12:38:26.378030 11, 0xFFFF, sum = 0
8528 12:38:26.378380 12, 0xFFFF, sum = 0
8529 12:38:26.381301 13, 0xFFFF, sum = 0
8530 12:38:26.381563 14, 0x0, sum = 1
8531 12:38:26.384164 15, 0x0, sum = 2
8532 12:38:26.384582 16, 0x0, sum = 3
8533 12:38:26.387439 17, 0x0, sum = 4
8534 12:38:26.387772 best_step = 15
8535 12:38:26.388030
8536 12:38:26.388273 ==
8537 12:38:26.391264 Dram Type= 6, Freq= 0, CH_1, rank 0
8538 12:38:26.394088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8539 12:38:26.397750 ==
8540 12:38:26.398074 RX Vref Scan: 1
8541 12:38:26.398334
8542 12:38:26.400675 Set Vref Range= 24 -> 127
8543 12:38:26.401002
8544 12:38:26.403689 RX Vref 24 -> 127, step: 1
8545 12:38:26.404015
8546 12:38:26.404272 RX Delay 11 -> 252, step: 4
8547 12:38:26.404515
8548 12:38:26.407418 Set Vref, RX VrefLevel [Byte0]: 24
8549 12:38:26.410534 [Byte1]: 24
8550 12:38:26.414597
8551 12:38:26.414922 Set Vref, RX VrefLevel [Byte0]: 25
8552 12:38:26.417836 [Byte1]: 25
8553 12:38:26.422178
8554 12:38:26.422621 Set Vref, RX VrefLevel [Byte0]: 26
8555 12:38:26.425054 [Byte1]: 26
8556 12:38:26.429868
8557 12:38:26.432698 Set Vref, RX VrefLevel [Byte0]: 27
8558 12:38:26.436560 [Byte1]: 27
8559 12:38:26.436980
8560 12:38:26.439783 Set Vref, RX VrefLevel [Byte0]: 28
8561 12:38:26.442809 [Byte1]: 28
8562 12:38:26.443223
8563 12:38:26.445623 Set Vref, RX VrefLevel [Byte0]: 29
8564 12:38:26.449148 [Byte1]: 29
8565 12:38:26.452326
8566 12:38:26.452745 Set Vref, RX VrefLevel [Byte0]: 30
8567 12:38:26.455522 [Byte1]: 30
8568 12:38:26.459972
8569 12:38:26.460290 Set Vref, RX VrefLevel [Byte0]: 31
8570 12:38:26.463626 [Byte1]: 31
8571 12:38:26.467510
8572 12:38:26.467824 Set Vref, RX VrefLevel [Byte0]: 32
8573 12:38:26.470956 [Byte1]: 32
8574 12:38:26.475263
8575 12:38:26.475711 Set Vref, RX VrefLevel [Byte0]: 33
8576 12:38:26.478816 [Byte1]: 33
8577 12:38:26.482940
8578 12:38:26.483263 Set Vref, RX VrefLevel [Byte0]: 34
8579 12:38:26.486316 [Byte1]: 34
8580 12:38:26.490454
8581 12:38:26.490946 Set Vref, RX VrefLevel [Byte0]: 35
8582 12:38:26.494099 [Byte1]: 35
8583 12:38:26.498103
8584 12:38:26.498425 Set Vref, RX VrefLevel [Byte0]: 36
8585 12:38:26.501076 [Byte1]: 36
8586 12:38:26.509076
8587 12:38:26.509400 Set Vref, RX VrefLevel [Byte0]: 37
8588 12:38:26.509661 [Byte1]: 37
8589 12:38:26.513530
8590 12:38:26.513928 Set Vref, RX VrefLevel [Byte0]: 38
8591 12:38:26.516564 [Byte1]: 38
8592 12:38:26.521112
8593 12:38:26.521610 Set Vref, RX VrefLevel [Byte0]: 39
8594 12:38:26.524155 [Byte1]: 39
8595 12:38:26.528674
8596 12:38:26.528994 Set Vref, RX VrefLevel [Byte0]: 40
8597 12:38:26.531803 [Byte1]: 40
8598 12:38:26.535738
8599 12:38:26.536067 Set Vref, RX VrefLevel [Byte0]: 41
8600 12:38:26.539271 [Byte1]: 41
8601 12:38:26.544052
8602 12:38:26.544293 Set Vref, RX VrefLevel [Byte0]: 42
8603 12:38:26.547455 [Byte1]: 42
8604 12:38:26.551543
8605 12:38:26.551781 Set Vref, RX VrefLevel [Byte0]: 43
8606 12:38:26.554472 [Byte1]: 43
8607 12:38:26.559075
8608 12:38:26.559313 Set Vref, RX VrefLevel [Byte0]: 44
8609 12:38:26.562324 [Byte1]: 44
8610 12:38:26.566696
8611 12:38:26.566937 Set Vref, RX VrefLevel [Byte0]: 45
8612 12:38:26.570061 [Byte1]: 45
8613 12:38:26.574108
8614 12:38:26.574349 Set Vref, RX VrefLevel [Byte0]: 46
8615 12:38:26.577590 [Byte1]: 46
8616 12:38:26.581829
8617 12:38:26.582071 Set Vref, RX VrefLevel [Byte0]: 47
8618 12:38:26.585401 [Byte1]: 47
8619 12:38:26.589464
8620 12:38:26.589702 Set Vref, RX VrefLevel [Byte0]: 48
8621 12:38:26.592886 [Byte1]: 48
8622 12:38:26.596859
8623 12:38:26.597099 Set Vref, RX VrefLevel [Byte0]: 49
8624 12:38:26.600577 [Byte1]: 49
8625 12:38:26.604515
8626 12:38:26.604755 Set Vref, RX VrefLevel [Byte0]: 50
8627 12:38:26.608002 [Byte1]: 50
8628 12:38:26.612167
8629 12:38:26.612407 Set Vref, RX VrefLevel [Byte0]: 51
8630 12:38:26.615414 [Byte1]: 51
8631 12:38:26.619576
8632 12:38:26.619818 Set Vref, RX VrefLevel [Byte0]: 52
8633 12:38:26.623444 [Byte1]: 52
8634 12:38:26.627472
8635 12:38:26.627713 Set Vref, RX VrefLevel [Byte0]: 53
8636 12:38:26.630848 [Byte1]: 53
8637 12:38:26.634923
8638 12:38:26.635164 Set Vref, RX VrefLevel [Byte0]: 54
8639 12:38:26.638170 [Byte1]: 54
8640 12:38:26.643232
8641 12:38:26.643512 Set Vref, RX VrefLevel [Byte0]: 55
8642 12:38:26.645811 [Byte1]: 55
8643 12:38:26.650121
8644 12:38:26.650361 Set Vref, RX VrefLevel [Byte0]: 56
8645 12:38:26.653533 [Byte1]: 56
8646 12:38:26.657921
8647 12:38:26.658189 Set Vref, RX VrefLevel [Byte0]: 57
8648 12:38:26.661370 [Byte1]: 57
8649 12:38:26.665778
8650 12:38:26.666018 Set Vref, RX VrefLevel [Byte0]: 58
8651 12:38:26.668960 [Byte1]: 58
8652 12:38:26.673603
8653 12:38:26.673853 Set Vref, RX VrefLevel [Byte0]: 59
8654 12:38:26.677082 [Byte1]: 59
8655 12:38:26.680585
8656 12:38:26.680842 Set Vref, RX VrefLevel [Byte0]: 60
8657 12:38:26.684298 [Byte1]: 60
8658 12:38:26.688283
8659 12:38:26.688524 Set Vref, RX VrefLevel [Byte0]: 61
8660 12:38:26.691337 [Byte1]: 61
8661 12:38:26.696414
8662 12:38:26.696652 Set Vref, RX VrefLevel [Byte0]: 62
8663 12:38:26.699531 [Byte1]: 62
8664 12:38:26.703481
8665 12:38:26.703718 Set Vref, RX VrefLevel [Byte0]: 63
8666 12:38:26.706850 [Byte1]: 63
8667 12:38:26.711442
8668 12:38:26.711678 Set Vref, RX VrefLevel [Byte0]: 64
8669 12:38:26.714634 [Byte1]: 64
8670 12:38:26.719148
8671 12:38:26.719504 Set Vref, RX VrefLevel [Byte0]: 65
8672 12:38:26.722058 [Byte1]: 65
8673 12:38:26.726701
8674 12:38:26.726937 Set Vref, RX VrefLevel [Byte0]: 66
8675 12:38:26.729680 [Byte1]: 66
8676 12:38:26.733949
8677 12:38:26.734187 Set Vref, RX VrefLevel [Byte0]: 67
8678 12:38:26.737504 [Byte1]: 67
8679 12:38:26.741538
8680 12:38:26.741774 Set Vref, RX VrefLevel [Byte0]: 68
8681 12:38:26.745005 [Byte1]: 68
8682 12:38:26.749717
8683 12:38:26.749957 Set Vref, RX VrefLevel [Byte0]: 69
8684 12:38:26.752518 [Byte1]: 69
8685 12:38:26.756550
8686 12:38:26.756864 Set Vref, RX VrefLevel [Byte0]: 70
8687 12:38:26.760040 [Byte1]: 70
8688 12:38:26.764536
8689 12:38:26.764778 Set Vref, RX VrefLevel [Byte0]: 71
8690 12:38:26.767731 [Byte1]: 71
8691 12:38:26.772505
8692 12:38:26.772743 Final RX Vref Byte 0 = 61 to rank0
8693 12:38:26.775354 Final RX Vref Byte 1 = 60 to rank0
8694 12:38:26.778518 Final RX Vref Byte 0 = 61 to rank1
8695 12:38:26.782556 Final RX Vref Byte 1 = 60 to rank1==
8696 12:38:26.785771 Dram Type= 6, Freq= 0, CH_1, rank 0
8697 12:38:26.792356 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8698 12:38:26.792743 ==
8699 12:38:26.792996 DQS Delay:
8700 12:38:26.795670 DQS0 = 0, DQS1 = 0
8701 12:38:26.796056 DQM Delay:
8702 12:38:26.796301 DQM0 = 132, DQM1 = 128
8703 12:38:26.798830 DQ Delay:
8704 12:38:26.801795 DQ0 =138, DQ1 =130, DQ2 =118, DQ3 =130
8705 12:38:26.805295 DQ4 =128, DQ5 =142, DQ6 =146, DQ7 =130
8706 12:38:26.808695 DQ8 =114, DQ9 =116, DQ10 =128, DQ11 =120
8707 12:38:26.811947 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =138
8708 12:38:26.812369
8709 12:38:26.812706
8710 12:38:26.813012
8711 12:38:26.814812 [DramC_TX_OE_Calibration] TA2
8712 12:38:26.818467 Original DQ_B0 (3 6) =30, OEN = 27
8713 12:38:26.821888 Original DQ_B1 (3 6) =30, OEN = 27
8714 12:38:26.824918 24, 0x0, End_B0=24 End_B1=24
8715 12:38:26.828378 25, 0x0, End_B0=25 End_B1=25
8716 12:38:26.828936 26, 0x0, End_B0=26 End_B1=26
8717 12:38:26.831830 27, 0x0, End_B0=27 End_B1=27
8718 12:38:26.834689 28, 0x0, End_B0=28 End_B1=28
8719 12:38:26.838105 29, 0x0, End_B0=29 End_B1=29
8720 12:38:26.838659 30, 0x0, End_B0=30 End_B1=30
8721 12:38:26.841562 31, 0x4141, End_B0=30 End_B1=30
8722 12:38:26.845168 Byte0 end_step=30 best_step=27
8723 12:38:26.848003 Byte1 end_step=30 best_step=27
8724 12:38:26.851440 Byte0 TX OE(2T, 0.5T) = (3, 3)
8725 12:38:26.854592 Byte1 TX OE(2T, 0.5T) = (3, 3)
8726 12:38:26.854896
8727 12:38:26.855203
8728 12:38:26.860865 [DQSOSCAuto] RK0, (LSB)MR18= 0x1019, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 401 ps
8729 12:38:26.864473 CH1 RK0: MR19=303, MR18=1019
8730 12:38:26.870666 CH1_RK0: MR19=0x303, MR18=0x1019, DQSOSC=397, MR23=63, INC=23, DEC=15
8731 12:38:26.870897
8732 12:38:26.873861 ----->DramcWriteLeveling(PI) begin...
8733 12:38:26.874079 ==
8734 12:38:26.876983 Dram Type= 6, Freq= 0, CH_1, rank 1
8735 12:38:26.880323 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8736 12:38:26.880498 ==
8737 12:38:26.883989 Write leveling (Byte 0): 25 => 25
8738 12:38:26.887135 Write leveling (Byte 1): 26 => 26
8739 12:38:26.890126 DramcWriteLeveling(PI) end<-----
8740 12:38:26.890289
8741 12:38:26.890422 ==
8742 12:38:26.893788 Dram Type= 6, Freq= 0, CH_1, rank 1
8743 12:38:26.900388 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8744 12:38:26.900685 ==
8745 12:38:26.900865 [Gating] SW mode calibration
8746 12:38:26.910344 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8747 12:38:26.913747 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8748 12:38:26.920138 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8749 12:38:26.923235 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8750 12:38:26.926808 1 4 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8751 12:38:26.933461 1 4 12 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
8752 12:38:26.936729 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8753 12:38:26.940098 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8754 12:38:26.946353 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8755 12:38:26.949949 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8756 12:38:26.953128 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8757 12:38:26.959237 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8758 12:38:26.963045 1 5 8 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
8759 12:38:26.965844 1 5 12 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
8760 12:38:26.972600 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8761 12:38:26.976016 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8762 12:38:26.979483 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8763 12:38:26.986151 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 12:38:26.988848 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 12:38:26.992343 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8766 12:38:26.999838 1 6 8 | B1->B0 | 2424 4444 | 0 0 | (0 0) (0 0)
8767 12:38:27.002755 1 6 12 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
8768 12:38:27.005663 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8769 12:38:27.012457 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8770 12:38:27.015646 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8771 12:38:27.019231 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8772 12:38:27.025449 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8773 12:38:27.028733 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 12:38:27.032008 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8775 12:38:27.038693 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8776 12:38:27.041867 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8777 12:38:27.045966 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 12:38:27.052154 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 12:38:27.055184 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 12:38:27.058637 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 12:38:27.065115 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 12:38:27.068167 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 12:38:27.071877 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 12:38:27.078423 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 12:38:27.081456 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 12:38:27.084566 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 12:38:27.091399 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 12:38:27.094981 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 12:38:27.098293 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8790 12:38:27.104237 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8791 12:38:27.108579 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8792 12:38:27.110788 Total UI for P1: 0, mck2ui 16
8793 12:38:27.114285 best dqsien dly found for B0: ( 1, 9, 6)
8794 12:38:27.117531 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 12:38:27.120665 Total UI for P1: 0, mck2ui 16
8796 12:38:27.124518 best dqsien dly found for B1: ( 1, 9, 12)
8797 12:38:27.127415 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8798 12:38:27.130536 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8799 12:38:27.130679
8800 12:38:27.137240 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8801 12:38:27.140923 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8802 12:38:27.143803 [Gating] SW calibration Done
8803 12:38:27.143945 ==
8804 12:38:27.146709 Dram Type= 6, Freq= 0, CH_1, rank 1
8805 12:38:27.150813 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8806 12:38:27.150957 ==
8807 12:38:27.151070 RX Vref Scan: 0
8808 12:38:27.151174
8809 12:38:27.153803 RX Vref 0 -> 0, step: 1
8810 12:38:27.153945
8811 12:38:27.157218 RX Delay 0 -> 252, step: 8
8812 12:38:27.160353 iDelay=200, Bit 0, Center 139 (80 ~ 199) 120
8813 12:38:27.163277 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8814 12:38:27.170323 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8815 12:38:27.173147 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8816 12:38:27.176581 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8817 12:38:27.179944 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8818 12:38:27.183256 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8819 12:38:27.189808 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8820 12:38:27.193010 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8821 12:38:27.196630 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8822 12:38:27.199771 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8823 12:38:27.203228 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8824 12:38:27.209988 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8825 12:38:27.213342 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8826 12:38:27.216091 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8827 12:38:27.219573 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8828 12:38:27.220145 ==
8829 12:38:27.222957 Dram Type= 6, Freq= 0, CH_1, rank 1
8830 12:38:27.229671 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8831 12:38:27.230208 ==
8832 12:38:27.230724 DQS Delay:
8833 12:38:27.232765 DQS0 = 0, DQS1 = 0
8834 12:38:27.233289 DQM Delay:
8835 12:38:27.236052 DQM0 = 133, DQM1 = 129
8836 12:38:27.236578 DQ Delay:
8837 12:38:27.239826 DQ0 =139, DQ1 =131, DQ2 =119, DQ3 =131
8838 12:38:27.242729 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =135
8839 12:38:27.246524 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8840 12:38:27.248977 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8841 12:38:27.249514
8842 12:38:27.250041
8843 12:38:27.250489 ==
8844 12:38:27.252661 Dram Type= 6, Freq= 0, CH_1, rank 1
8845 12:38:27.259102 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8846 12:38:27.259703 ==
8847 12:38:27.260191
8848 12:38:27.260712
8849 12:38:27.261169 TX Vref Scan disable
8850 12:38:27.262717 == TX Byte 0 ==
8851 12:38:27.266402 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8852 12:38:27.272332 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8853 12:38:27.272748 == TX Byte 1 ==
8854 12:38:27.275789 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8855 12:38:27.282706 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8856 12:38:27.283154 ==
8857 12:38:27.286001 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 12:38:27.288861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 12:38:27.289244 ==
8860 12:38:27.302670
8861 12:38:27.305664 TX Vref early break, caculate TX vref
8862 12:38:27.309228 TX Vref=16, minBit 9, minWin=22, winSum=378
8863 12:38:27.313119 TX Vref=18, minBit 9, minWin=22, winSum=385
8864 12:38:27.316762 TX Vref=20, minBit 9, minWin=22, winSum=388
8865 12:38:27.319333 TX Vref=22, minBit 9, minWin=23, winSum=404
8866 12:38:27.322775 TX Vref=24, minBit 9, minWin=23, winSum=407
8867 12:38:27.329079 TX Vref=26, minBit 1, minWin=25, winSum=416
8868 12:38:27.332577 TX Vref=28, minBit 9, minWin=24, winSum=419
8869 12:38:27.335669 TX Vref=30, minBit 8, minWin=24, winSum=416
8870 12:38:27.339007 TX Vref=32, minBit 5, minWin=25, winSum=413
8871 12:38:27.342018 TX Vref=34, minBit 9, minWin=23, winSum=403
8872 12:38:27.349148 TX Vref=36, minBit 8, minWin=23, winSum=395
8873 12:38:27.352760 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 26
8874 12:38:27.353310
8875 12:38:27.355833 Final TX Range 0 Vref 26
8876 12:38:27.356404
8877 12:38:27.356868 ==
8878 12:38:27.359103 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 12:38:27.362277 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 12:38:27.362735 ==
8881 12:38:27.364967
8882 12:38:27.365566
8883 12:38:27.365907 TX Vref Scan disable
8884 12:38:27.371956 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8885 12:38:27.372393 == TX Byte 0 ==
8886 12:38:27.375040 u2DelayCellOfst[0]=14 cells (4 PI)
8887 12:38:27.378504 u2DelayCellOfst[1]=10 cells (3 PI)
8888 12:38:27.381885 u2DelayCellOfst[2]=0 cells (0 PI)
8889 12:38:27.384969 u2DelayCellOfst[3]=7 cells (2 PI)
8890 12:38:27.388307 u2DelayCellOfst[4]=7 cells (2 PI)
8891 12:38:27.391540 u2DelayCellOfst[5]=18 cells (5 PI)
8892 12:38:27.394932 u2DelayCellOfst[6]=18 cells (5 PI)
8893 12:38:27.398313 u2DelayCellOfst[7]=3 cells (1 PI)
8894 12:38:27.401367 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8895 12:38:27.404774 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8896 12:38:27.408145 == TX Byte 1 ==
8897 12:38:27.411325 u2DelayCellOfst[8]=0 cells (0 PI)
8898 12:38:27.414449 u2DelayCellOfst[9]=0 cells (0 PI)
8899 12:38:27.418059 u2DelayCellOfst[10]=10 cells (3 PI)
8900 12:38:27.420836 u2DelayCellOfst[11]=7 cells (2 PI)
8901 12:38:27.424078 u2DelayCellOfst[12]=14 cells (4 PI)
8902 12:38:27.428031 u2DelayCellOfst[13]=14 cells (4 PI)
8903 12:38:27.428323 u2DelayCellOfst[14]=18 cells (5 PI)
8904 12:38:27.431215 u2DelayCellOfst[15]=18 cells (5 PI)
8905 12:38:27.437589 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8906 12:38:27.440624 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8907 12:38:27.443772 DramC Write-DBI on
8908 12:38:27.444072 ==
8909 12:38:27.447660 Dram Type= 6, Freq= 0, CH_1, rank 1
8910 12:38:27.450974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8911 12:38:27.451227 ==
8912 12:38:27.451538
8913 12:38:27.451794
8914 12:38:27.453911 TX Vref Scan disable
8915 12:38:27.454215 == TX Byte 0 ==
8916 12:38:27.460785 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8917 12:38:27.461077 == TX Byte 1 ==
8918 12:38:27.466966 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8919 12:38:27.467263 DramC Write-DBI off
8920 12:38:27.467559
8921 12:38:27.467838 [DATLAT]
8922 12:38:27.470067 Freq=1600, CH1 RK1
8923 12:38:27.470342
8924 12:38:27.470583 DATLAT Default: 0xf
8925 12:38:27.473707 0, 0xFFFF, sum = 0
8926 12:38:27.476925 1, 0xFFFF, sum = 0
8927 12:38:27.477174 2, 0xFFFF, sum = 0
8928 12:38:27.480677 3, 0xFFFF, sum = 0
8929 12:38:27.480985 4, 0xFFFF, sum = 0
8930 12:38:27.483999 5, 0xFFFF, sum = 0
8931 12:38:27.484311 6, 0xFFFF, sum = 0
8932 12:38:27.487043 7, 0xFFFF, sum = 0
8933 12:38:27.487350 8, 0xFFFF, sum = 0
8934 12:38:27.490537 9, 0xFFFF, sum = 0
8935 12:38:27.490897 10, 0xFFFF, sum = 0
8936 12:38:27.493761 11, 0xFFFF, sum = 0
8937 12:38:27.494218 12, 0xFFFF, sum = 0
8938 12:38:27.497170 13, 0xFFFF, sum = 0
8939 12:38:27.497660 14, 0x0, sum = 1
8940 12:38:27.500301 15, 0x0, sum = 2
8941 12:38:27.500815 16, 0x0, sum = 3
8942 12:38:27.503978 17, 0x0, sum = 4
8943 12:38:27.504495 best_step = 15
8944 12:38:27.504827
8945 12:38:27.505126 ==
8946 12:38:27.507291 Dram Type= 6, Freq= 0, CH_1, rank 1
8947 12:38:27.514132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8948 12:38:27.514647 ==
8949 12:38:27.514979 RX Vref Scan: 0
8950 12:38:27.515284
8951 12:38:27.516508 RX Vref 0 -> 0, step: 1
8952 12:38:27.516917
8953 12:38:27.520111 RX Delay 11 -> 252, step: 4
8954 12:38:27.523455 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8955 12:38:27.526550 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8956 12:38:27.533828 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8957 12:38:27.537452 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8958 12:38:27.539778 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8959 12:38:27.543081 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8960 12:38:27.546501 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8961 12:38:27.553188 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8962 12:38:27.555978 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8963 12:38:27.559466 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8964 12:38:27.563102 iDelay=195, Bit 10, Center 130 (75 ~ 186) 112
8965 12:38:27.566364 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8966 12:38:27.572516 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8967 12:38:27.575980 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8968 12:38:27.579763 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8969 12:38:27.582631 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8970 12:38:27.583051 ==
8971 12:38:27.586153 Dram Type= 6, Freq= 0, CH_1, rank 1
8972 12:38:27.592348 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8973 12:38:27.592893 ==
8974 12:38:27.593234 DQS Delay:
8975 12:38:27.595824 DQS0 = 0, DQS1 = 0
8976 12:38:27.596351 DQM Delay:
8977 12:38:27.598794 DQM0 = 132, DQM1 = 128
8978 12:38:27.599319 DQ Delay:
8979 12:38:27.602333 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =128
8980 12:38:27.605675 DQ4 =128, DQ5 =144, DQ6 =140, DQ7 =130
8981 12:38:27.608783 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
8982 12:38:27.612426 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
8983 12:38:27.612847
8984 12:38:27.613175
8985 12:38:27.613480
8986 12:38:27.615484 [DramC_TX_OE_Calibration] TA2
8987 12:38:27.619106 Original DQ_B0 (3 6) =30, OEN = 27
8988 12:38:27.622026 Original DQ_B1 (3 6) =30, OEN = 27
8989 12:38:27.625540 24, 0x0, End_B0=24 End_B1=24
8990 12:38:27.628872 25, 0x0, End_B0=25 End_B1=25
8991 12:38:27.629405 26, 0x0, End_B0=26 End_B1=26
8992 12:38:27.631933 27, 0x0, End_B0=27 End_B1=27
8993 12:38:27.634942 28, 0x0, End_B0=28 End_B1=28
8994 12:38:27.638703 29, 0x0, End_B0=29 End_B1=29
8995 12:38:27.642069 30, 0x0, End_B0=30 End_B1=30
8996 12:38:27.642644 31, 0x4141, End_B0=30 End_B1=30
8997 12:38:27.645404 Byte0 end_step=30 best_step=27
8998 12:38:27.648328 Byte1 end_step=30 best_step=27
8999 12:38:27.651863 Byte0 TX OE(2T, 0.5T) = (3, 3)
9000 12:38:27.655469 Byte1 TX OE(2T, 0.5T) = (3, 3)
9001 12:38:27.655978
9002 12:38:27.656328
9003 12:38:27.661580 [DQSOSCAuto] RK1, (LSB)MR18= 0xd1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
9004 12:38:27.664929 CH1 RK1: MR19=303, MR18=D1B
9005 12:38:27.671407 CH1_RK1: MR19=0x303, MR18=0xD1B, DQSOSC=396, MR23=63, INC=23, DEC=15
9006 12:38:27.674777 [RxdqsGatingPostProcess] freq 1600
9007 12:38:27.681561 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9008 12:38:27.684763 best DQS0 dly(2T, 0.5T) = (1, 1)
9009 12:38:27.685281 best DQS1 dly(2T, 0.5T) = (1, 1)
9010 12:38:27.687827 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9011 12:38:27.691147 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9012 12:38:27.694317 best DQS0 dly(2T, 0.5T) = (1, 1)
9013 12:38:27.697763 best DQS1 dly(2T, 0.5T) = (1, 1)
9014 12:38:27.701098 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9015 12:38:27.704741 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9016 12:38:27.707526 Pre-setting of DQS Precalculation
9017 12:38:27.711585 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9018 12:38:27.720951 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9019 12:38:27.727756 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9020 12:38:27.728274
9021 12:38:27.728603
9022 12:38:27.730580 [Calibration Summary] 3200 Mbps
9023 12:38:27.731035 CH 0, Rank 0
9024 12:38:27.733660 SW Impedance : PASS
9025 12:38:27.734077 DUTY Scan : NO K
9026 12:38:27.737353 ZQ Calibration : PASS
9027 12:38:27.740409 Jitter Meter : NO K
9028 12:38:27.740827 CBT Training : PASS
9029 12:38:27.743722 Write leveling : PASS
9030 12:38:27.747469 RX DQS gating : PASS
9031 12:38:27.747890 RX DQ/DQS(RDDQC) : PASS
9032 12:38:27.750270 TX DQ/DQS : PASS
9033 12:38:27.754203 RX DATLAT : PASS
9034 12:38:27.754619 RX DQ/DQS(Engine): PASS
9035 12:38:27.756975 TX OE : PASS
9036 12:38:27.757520 All Pass.
9037 12:38:27.757987
9038 12:38:27.760072 CH 0, Rank 1
9039 12:38:27.760624 SW Impedance : PASS
9040 12:38:27.763418 DUTY Scan : NO K
9041 12:38:27.767542 ZQ Calibration : PASS
9042 12:38:27.767962 Jitter Meter : NO K
9043 12:38:27.770354 CBT Training : PASS
9044 12:38:27.773447 Write leveling : PASS
9045 12:38:27.773869 RX DQS gating : PASS
9046 12:38:27.777214 RX DQ/DQS(RDDQC) : PASS
9047 12:38:27.779820 TX DQ/DQS : PASS
9048 12:38:27.780240 RX DATLAT : PASS
9049 12:38:27.783850 RX DQ/DQS(Engine): PASS
9050 12:38:27.786701 TX OE : PASS
9051 12:38:27.787355 All Pass.
9052 12:38:27.787888
9053 12:38:27.788218 CH 1, Rank 0
9054 12:38:27.789648 SW Impedance : PASS
9055 12:38:27.793283 DUTY Scan : NO K
9056 12:38:27.793806 ZQ Calibration : PASS
9057 12:38:27.796582 Jitter Meter : NO K
9058 12:38:27.800097 CBT Training : PASS
9059 12:38:27.800615 Write leveling : PASS
9060 12:38:27.803000 RX DQS gating : PASS
9061 12:38:27.806519 RX DQ/DQS(RDDQC) : PASS
9062 12:38:27.806935 TX DQ/DQS : PASS
9063 12:38:27.809804 RX DATLAT : PASS
9064 12:38:27.810326 RX DQ/DQS(Engine): PASS
9065 12:38:27.812791 TX OE : PASS
9066 12:38:27.813213 All Pass.
9067 12:38:27.813541
9068 12:38:27.816152 CH 1, Rank 1
9069 12:38:27.816610 SW Impedance : PASS
9070 12:38:27.819752 DUTY Scan : NO K
9071 12:38:27.822523 ZQ Calibration : PASS
9072 12:38:27.823169 Jitter Meter : NO K
9073 12:38:27.826330 CBT Training : PASS
9074 12:38:27.829580 Write leveling : PASS
9075 12:38:27.829999 RX DQS gating : PASS
9076 12:38:27.833090 RX DQ/DQS(RDDQC) : PASS
9077 12:38:27.836232 TX DQ/DQS : PASS
9078 12:38:27.836682 RX DATLAT : PASS
9079 12:38:27.839274 RX DQ/DQS(Engine): PASS
9080 12:38:27.842539 TX OE : PASS
9081 12:38:27.842955 All Pass.
9082 12:38:27.843278
9083 12:38:27.846043 DramC Write-DBI on
9084 12:38:27.846459 PER_BANK_REFRESH: Hybrid Mode
9085 12:38:27.849438 TX_TRACKING: ON
9086 12:38:27.859050 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9087 12:38:27.865378 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9088 12:38:27.872437 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9089 12:38:27.875499 [FAST_K] Save calibration result to emmc
9090 12:38:27.879120 sync common calibartion params.
9091 12:38:27.882362 sync cbt_mode0:1, 1:1
9092 12:38:27.882934 dram_init: ddr_geometry: 2
9093 12:38:27.885395 dram_init: ddr_geometry: 2
9094 12:38:27.888755 dram_init: ddr_geometry: 2
9095 12:38:27.892064 0:dram_rank_size:100000000
9096 12:38:27.892489 1:dram_rank_size:100000000
9097 12:38:27.898749 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9098 12:38:27.901599 DFS_SHUFFLE_HW_MODE: ON
9099 12:38:27.904915 dramc_set_vcore_voltage set vcore to 725000
9100 12:38:27.908097 Read voltage for 1600, 0
9101 12:38:27.908178 Vio18 = 0
9102 12:38:27.908241 Vcore = 725000
9103 12:38:27.911192 Vdram = 0
9104 12:38:27.911272 Vddq = 0
9105 12:38:27.911336 Vmddr = 0
9106 12:38:27.914791 switch to 3200 Mbps bootup
9107 12:38:27.914899 [DramcRunTimeConfig]
9108 12:38:27.917981 PHYPLL
9109 12:38:27.918086 DPM_CONTROL_AFTERK: ON
9110 12:38:27.921046 PER_BANK_REFRESH: ON
9111 12:38:27.924638 REFRESH_OVERHEAD_REDUCTION: ON
9112 12:38:27.924744 CMD_PICG_NEW_MODE: OFF
9113 12:38:27.928144 XRTWTW_NEW_MODE: ON
9114 12:38:27.928240 XRTRTR_NEW_MODE: ON
9115 12:38:27.931244 TX_TRACKING: ON
9116 12:38:27.931338 RDSEL_TRACKING: OFF
9117 12:38:27.934398 DQS Precalculation for DVFS: ON
9118 12:38:27.937698 RX_TRACKING: OFF
9119 12:38:27.937777 HW_GATING DBG: ON
9120 12:38:27.940940 ZQCS_ENABLE_LP4: ON
9121 12:38:27.941020 RX_PICG_NEW_MODE: ON
9122 12:38:27.944201 TX_PICG_NEW_MODE: ON
9123 12:38:27.947750 ENABLE_RX_DCM_DPHY: ON
9124 12:38:27.951013 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9125 12:38:27.951092 DUMMY_READ_FOR_TRACKING: OFF
9126 12:38:27.953950 !!! SPM_CONTROL_AFTERK: OFF
9127 12:38:27.957716 !!! SPM could not control APHY
9128 12:38:27.960474 IMPEDANCE_TRACKING: ON
9129 12:38:27.960555 TEMP_SENSOR: ON
9130 12:38:27.964132 HW_SAVE_FOR_SR: OFF
9131 12:38:27.964212 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9132 12:38:27.970574 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9133 12:38:27.970659 Read ODT Tracking: ON
9134 12:38:27.973898 Refresh Rate DeBounce: ON
9135 12:38:27.973978 DFS_NO_QUEUE_FLUSH: ON
9136 12:38:27.977413 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9137 12:38:27.980172 ENABLE_DFS_RUNTIME_MRW: OFF
9138 12:38:27.983624 DDR_RESERVE_NEW_MODE: ON
9139 12:38:27.987090 MR_CBT_SWITCH_FREQ: ON
9140 12:38:27.987170 =========================
9141 12:38:28.006658 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9142 12:38:28.010000 dram_init: ddr_geometry: 2
9143 12:38:28.028863 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9144 12:38:28.031768 dram_init: dram init end (result: 0)
9145 12:38:28.038652 DRAM-K: Full calibration passed in 24439 msecs
9146 12:38:28.041627 MRC: failed to locate region type 0.
9147 12:38:28.042039 DRAM rank0 size:0x100000000,
9148 12:38:28.045243 DRAM rank1 size=0x100000000
9149 12:38:28.055037 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9150 12:38:28.061746 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9151 12:38:28.068100 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9152 12:38:28.077798 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9153 12:38:28.078238 DRAM rank0 size:0x100000000,
9154 12:38:28.081375 DRAM rank1 size=0x100000000
9155 12:38:28.081802 CBMEM:
9156 12:38:28.084630 IMD: root @ 0xfffff000 254 entries.
9157 12:38:28.088020 IMD: root @ 0xffffec00 62 entries.
9158 12:38:28.091683 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9159 12:38:28.097579 WARNING: RO_VPD is uninitialized or empty.
9160 12:38:28.101191 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9161 12:38:28.108441 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9162 12:38:28.121544 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9163 12:38:28.133126 BS: romstage times (exec / console): total (unknown) / 23967 ms
9164 12:38:28.133565
9165 12:38:28.134036
9166 12:38:28.142249 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9167 12:38:28.145731 ARM64: Exception handlers installed.
9168 12:38:28.149034 ARM64: Testing exception
9169 12:38:28.152370 ARM64: Done test exception
9170 12:38:28.152451 Enumerating buses...
9171 12:38:28.155295 Show all devs... Before device enumeration.
9172 12:38:28.158666 Root Device: enabled 1
9173 12:38:28.162103 CPU_CLUSTER: 0: enabled 1
9174 12:38:28.162182 CPU: 00: enabled 1
9175 12:38:28.165260 Compare with tree...
9176 12:38:28.165370 Root Device: enabled 1
9177 12:38:28.168844 CPU_CLUSTER: 0: enabled 1
9178 12:38:28.172304 CPU: 00: enabled 1
9179 12:38:28.172384 Root Device scanning...
9180 12:38:28.175299 scan_static_bus for Root Device
9181 12:38:28.179489 CPU_CLUSTER: 0 enabled
9182 12:38:28.182454 scan_static_bus for Root Device done
9183 12:38:28.185152 scan_bus: bus Root Device finished in 8 msecs
9184 12:38:28.185233 done
9185 12:38:28.191986 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9186 12:38:28.195591 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9187 12:38:28.201888 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9188 12:38:28.205014 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9189 12:38:28.208594 Allocating resources...
9190 12:38:28.211465 Reading resources...
9191 12:38:28.214970 Root Device read_resources bus 0 link: 0
9192 12:38:28.218366 DRAM rank0 size:0x100000000,
9193 12:38:28.218448 DRAM rank1 size=0x100000000
9194 12:38:28.221580 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9195 12:38:28.225011 CPU: 00 missing read_resources
9196 12:38:28.231560 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9197 12:38:28.235274 Root Device read_resources bus 0 link: 0 done
9198 12:38:28.235358 Done reading resources.
9199 12:38:28.241356 Show resources in subtree (Root Device)...After reading.
9200 12:38:28.244921 Root Device child on link 0 CPU_CLUSTER: 0
9201 12:38:28.247725 CPU_CLUSTER: 0 child on link 0 CPU: 00
9202 12:38:28.257784 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9203 12:38:28.257955 CPU: 00
9204 12:38:28.261531 Root Device assign_resources, bus 0 link: 0
9205 12:38:28.264663 CPU_CLUSTER: 0 missing set_resources
9206 12:38:28.270903 Root Device assign_resources, bus 0 link: 0 done
9207 12:38:28.271074 Done setting resources.
9208 12:38:28.277767 Show resources in subtree (Root Device)...After assigning values.
9209 12:38:28.280953 Root Device child on link 0 CPU_CLUSTER: 0
9210 12:38:28.287386 CPU_CLUSTER: 0 child on link 0 CPU: 00
9211 12:38:28.294374 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9212 12:38:28.297569 CPU: 00
9213 12:38:28.297900 Done allocating resources.
9214 12:38:28.303990 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9215 12:38:28.304397 Enabling resources...
9216 12:38:28.307234 done.
9217 12:38:28.310665 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9218 12:38:28.313801 Initializing devices...
9219 12:38:28.314317 Root Device init
9220 12:38:28.317071 init hardware done!
9221 12:38:28.317530 0x00000018: ctrlr->caps
9222 12:38:28.320707 52.000 MHz: ctrlr->f_max
9223 12:38:28.324109 0.400 MHz: ctrlr->f_min
9224 12:38:28.326909 0x40ff8080: ctrlr->voltages
9225 12:38:28.327327 sclk: 390625
9226 12:38:28.327707 Bus Width = 1
9227 12:38:28.330768 sclk: 390625
9228 12:38:28.331278 Bus Width = 1
9229 12:38:28.333561 Early init status = 3
9230 12:38:28.337193 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9231 12:38:28.340754 in-header: 03 fc 00 00 01 00 00 00
9232 12:38:28.343243 in-data: 00
9233 12:38:28.346720 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9234 12:38:28.351111 in-header: 03 fd 00 00 00 00 00 00
9235 12:38:28.355189 in-data:
9236 12:38:28.357987 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9237 12:38:28.361441 in-header: 03 fc 00 00 01 00 00 00
9238 12:38:28.364950 in-data: 00
9239 12:38:28.367847 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9240 12:38:28.372528 in-header: 03 fd 00 00 00 00 00 00
9241 12:38:28.376009 in-data:
9242 12:38:28.379269 [SSUSB] Setting up USB HOST controller...
9243 12:38:28.382272 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9244 12:38:28.385950 [SSUSB] phy power-on done.
9245 12:38:28.389343 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9246 12:38:28.395530 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9247 12:38:28.399289 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9248 12:38:28.405614 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9249 12:38:28.412710 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9250 12:38:28.418995 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9251 12:38:28.425806 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9252 12:38:28.431923 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9253 12:38:28.435284 SPM: binary array size = 0x9dc
9254 12:38:28.438890 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9255 12:38:28.446128 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9256 12:38:28.451854 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9257 12:38:28.458814 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9258 12:38:28.461619 configure_display: Starting display init
9259 12:38:28.496081 anx7625_power_on_init: Init interface.
9260 12:38:28.499727 anx7625_disable_pd_protocol: Disabled PD feature.
9261 12:38:28.503095 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9262 12:38:28.530684 anx7625_start_dp_work: Secure OCM version=00
9263 12:38:28.533929 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9264 12:38:28.548379 sp_tx_get_edid_block: EDID Block = 1
9265 12:38:28.651157 Extracted contents:
9266 12:38:28.654862 header: 00 ff ff ff ff ff ff 00
9267 12:38:28.657585 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9268 12:38:28.660891 version: 01 04
9269 12:38:28.664357 basic params: 95 1f 11 78 0a
9270 12:38:28.667838 chroma info: 76 90 94 55 54 90 27 21 50 54
9271 12:38:28.670560 established: 00 00 00
9272 12:38:28.677537 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9273 12:38:28.683687 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9274 12:38:28.687067 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9275 12:38:28.693768 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9276 12:38:28.700315 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9277 12:38:28.703347 extensions: 00
9278 12:38:28.703816 checksum: fb
9279 12:38:28.704238
9280 12:38:28.707020 Manufacturer: IVO Model 57d Serial Number 0
9281 12:38:28.710051 Made week 0 of 2020
9282 12:38:28.713963 EDID version: 1.4
9283 12:38:28.714231 Digital display
9284 12:38:28.716940 6 bits per primary color channel
9285 12:38:28.717132 DisplayPort interface
9286 12:38:28.719794 Maximum image size: 31 cm x 17 cm
9287 12:38:28.722859 Gamma: 220%
9288 12:38:28.722963 Check DPMS levels
9289 12:38:28.729603 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9290 12:38:28.733046 First detailed timing is preferred timing
9291 12:38:28.733128 Established timings supported:
9292 12:38:28.736347 Standard timings supported:
9293 12:38:28.739686 Detailed timings
9294 12:38:28.742953 Hex of detail: 383680a07038204018303c0035ae10000019
9295 12:38:28.749492 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9296 12:38:28.753544 0780 0798 07c8 0820 hborder 0
9297 12:38:28.757095 0438 043b 0447 0458 vborder 0
9298 12:38:28.760182 -hsync -vsync
9299 12:38:28.760597 Did detailed timing
9300 12:38:28.766307 Hex of detail: 000000000000000000000000000000000000
9301 12:38:28.769526 Manufacturer-specified data, tag 0
9302 12:38:28.772719 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9303 12:38:28.775973 ASCII string: InfoVision
9304 12:38:28.779472 Hex of detail: 000000fe00523134304e574635205248200a
9305 12:38:28.782663 ASCII string: R140NWF5 RH
9306 12:38:28.783095 Checksum
9307 12:38:28.786611 Checksum: 0xfb (valid)
9308 12:38:28.789099 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9309 12:38:28.792586 DSI data_rate: 832800000 bps
9310 12:38:28.798938 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9311 12:38:28.802154 anx7625_parse_edid: pixelclock(138800).
9312 12:38:28.806076 hactive(1920), hsync(48), hfp(24), hbp(88)
9313 12:38:28.809186 vactive(1080), vsync(12), vfp(3), vbp(17)
9314 12:38:28.812060 anx7625_dsi_config: config dsi.
9315 12:38:28.818813 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9316 12:38:28.832412 anx7625_dsi_config: success to config DSI
9317 12:38:28.835835 anx7625_dp_start: MIPI phy setup OK.
9318 12:38:28.839413 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9319 12:38:28.842472 mtk_ddp_mode_set invalid vrefresh 60
9320 12:38:28.845681 main_disp_path_setup
9321 12:38:28.845880 ovl_layer_smi_id_en
9322 12:38:28.849166 ovl_layer_smi_id_en
9323 12:38:28.849315 ccorr_config
9324 12:38:28.849455 aal_config
9325 12:38:28.853140 gamma_config
9326 12:38:28.853342 postmask_config
9327 12:38:28.855974 dither_config
9328 12:38:28.859172 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9329 12:38:28.865781 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9330 12:38:28.869421 Root Device init finished in 551 msecs
9331 12:38:28.872478 CPU_CLUSTER: 0 init
9332 12:38:28.878875 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9333 12:38:28.885471 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9334 12:38:28.885551 APU_MBOX 0x190000b0 = 0x10001
9335 12:38:28.888695 APU_MBOX 0x190001b0 = 0x10001
9336 12:38:28.891890 APU_MBOX 0x190005b0 = 0x10001
9337 12:38:28.895624 APU_MBOX 0x190006b0 = 0x10001
9338 12:38:28.902151 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9339 12:38:28.912214 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9340 12:38:28.924428 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9341 12:38:28.930689 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9342 12:38:28.942183 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9343 12:38:28.951442 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9344 12:38:28.954415 CPU_CLUSTER: 0 init finished in 81 msecs
9345 12:38:28.958210 Devices initialized
9346 12:38:28.961520 Show all devs... After init.
9347 12:38:28.961613 Root Device: enabled 1
9348 12:38:28.964776 CPU_CLUSTER: 0: enabled 1
9349 12:38:28.967554 CPU: 00: enabled 1
9350 12:38:28.970937 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9351 12:38:28.975006 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9352 12:38:28.977666 ELOG: NV offset 0x57f000 size 0x1000
9353 12:38:28.984791 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9354 12:38:28.991157 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9355 12:38:28.994433 ELOG: Event(17) added with size 13 at 2024-02-05 12:38:32 UTC
9356 12:38:29.001213 out: cmd=0x121: 03 db 21 01 00 00 00 00
9357 12:38:29.004365 in-header: 03 26 00 00 2c 00 00 00
9358 12:38:29.014424 in-data: 39 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9359 12:38:29.021174 ELOG: Event(A1) added with size 10 at 2024-02-05 12:38:32 UTC
9360 12:38:29.028211 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9361 12:38:29.034308 ELOG: Event(A0) added with size 9 at 2024-02-05 12:38:32 UTC
9362 12:38:29.038444 elog_add_boot_reason: Logged dev mode boot
9363 12:38:29.044209 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9364 12:38:29.044731 Finalize devices...
9365 12:38:29.047982 Devices finalized
9366 12:38:29.051146 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9367 12:38:29.053830 Writing coreboot table at 0xffe64000
9368 12:38:29.057351 0. 000000000010a000-0000000000113fff: RAMSTAGE
9369 12:38:29.063934 1. 0000000040000000-00000000400fffff: RAM
9370 12:38:29.067461 2. 0000000040100000-000000004032afff: RAMSTAGE
9371 12:38:29.070994 3. 000000004032b000-00000000545fffff: RAM
9372 12:38:29.073985 4. 0000000054600000-000000005465ffff: BL31
9373 12:38:29.076873 5. 0000000054660000-00000000ffe63fff: RAM
9374 12:38:29.083793 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9375 12:38:29.087302 7. 0000000100000000-000000023fffffff: RAM
9376 12:38:29.090181 Passing 5 GPIOs to payload:
9377 12:38:29.093784 NAME | PORT | POLARITY | VALUE
9378 12:38:29.100137 EC in RW | 0x000000aa | low | undefined
9379 12:38:29.103586 EC interrupt | 0x00000005 | low | undefined
9380 12:38:29.106911 TPM interrupt | 0x000000ab | high | undefined
9381 12:38:29.113796 SD card detect | 0x00000011 | high | undefined
9382 12:38:29.116851 speaker enable | 0x00000093 | high | undefined
9383 12:38:29.120209 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9384 12:38:29.123129 in-header: 03 f9 00 00 02 00 00 00
9385 12:38:29.126714 in-data: 02 00
9386 12:38:29.130267 ADC[4]: Raw value=902955 ID=7
9387 12:38:29.133434 ADC[3]: Raw value=213546 ID=1
9388 12:38:29.133733 RAM Code: 0x71
9389 12:38:29.136132 ADC[6]: Raw value=74630 ID=0
9390 12:38:29.140074 ADC[5]: Raw value=213177 ID=1
9391 12:38:29.140305 SKU Code: 0x1
9392 12:38:29.146262 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 8928
9393 12:38:29.146512 coreboot table: 964 bytes.
9394 12:38:29.149814 IMD ROOT 0. 0xfffff000 0x00001000
9395 12:38:29.153125 IMD SMALL 1. 0xffffe000 0x00001000
9396 12:38:29.155895 RO MCACHE 2. 0xffffc000 0x00001104
9397 12:38:29.159199 CONSOLE 3. 0xfff7c000 0x00080000
9398 12:38:29.162634 FMAP 4. 0xfff7b000 0x00000452
9399 12:38:29.165954 TIME STAMP 5. 0xfff7a000 0x00000910
9400 12:38:29.169546 VBOOT WORK 6. 0xfff66000 0x00014000
9401 12:38:29.172698 RAMOOPS 7. 0xffe66000 0x00100000
9402 12:38:29.175917 COREBOOT 8. 0xffe64000 0x00002000
9403 12:38:29.178998 IMD small region:
9404 12:38:29.183209 IMD ROOT 0. 0xffffec00 0x00000400
9405 12:38:29.185665 VPD 1. 0xffffeb80 0x0000006c
9406 12:38:29.188686 MMC STATUS 2. 0xffffeb60 0x00000004
9407 12:38:29.195422 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9408 12:38:29.195527 Probing TPM: done!
9409 12:38:29.202568 Connected to device vid:did:rid of 1ae0:0028:00
9410 12:38:29.209197 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9411 12:38:29.212773 Initialized TPM device CR50 revision 0
9412 12:38:29.216335 Checking cr50 for pending updates
9413 12:38:29.221387 Reading cr50 TPM mode
9414 12:38:29.230147 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9415 12:38:29.236222 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9416 12:38:29.276790 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9417 12:38:29.280153 Checking segment from ROM address 0x40100000
9418 12:38:29.283147 Checking segment from ROM address 0x4010001c
9419 12:38:29.290219 Loading segment from ROM address 0x40100000
9420 12:38:29.290390 code (compression=0)
9421 12:38:29.300372 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9422 12:38:29.306666 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9423 12:38:29.306864 it's not compressed!
9424 12:38:29.313245 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9425 12:38:29.320031 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9426 12:38:29.337543 Loading segment from ROM address 0x4010001c
9427 12:38:29.338031 Entry Point 0x80000000
9428 12:38:29.340626 Loaded segments
9429 12:38:29.344565 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9430 12:38:29.350794 Jumping to boot code at 0x80000000(0xffe64000)
9431 12:38:29.357633 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9432 12:38:29.363802 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9433 12:38:29.371944 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9434 12:38:29.375076 Checking segment from ROM address 0x40100000
9435 12:38:29.378403 Checking segment from ROM address 0x4010001c
9436 12:38:29.385250 Loading segment from ROM address 0x40100000
9437 12:38:29.385666 code (compression=1)
9438 12:38:29.391961 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9439 12:38:29.401801 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9440 12:38:29.402315 using LZMA
9441 12:38:29.410429 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9442 12:38:29.417596 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9443 12:38:29.420178 Loading segment from ROM address 0x4010001c
9444 12:38:29.420690 Entry Point 0x54601000
9445 12:38:29.423645 Loaded segments
9446 12:38:29.427116 NOTICE: MT8192 bl31_setup
9447 12:38:29.433909 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9448 12:38:29.437584 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9449 12:38:29.440930 WARNING: region 0:
9450 12:38:29.443722 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9451 12:38:29.444136 WARNING: region 1:
9452 12:38:29.450818 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9453 12:38:29.454026 WARNING: region 2:
9454 12:38:29.457908 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9455 12:38:29.460683 WARNING: region 3:
9456 12:38:29.464091 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9457 12:38:29.467071 WARNING: region 4:
9458 12:38:29.473522 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9459 12:38:29.474042 WARNING: region 5:
9460 12:38:29.476893 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9461 12:38:29.480953 WARNING: region 6:
9462 12:38:29.483715 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9463 12:38:29.486694 WARNING: region 7:
9464 12:38:29.490036 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9465 12:38:29.497015 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9466 12:38:29.500151 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9467 12:38:29.506868 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9468 12:38:29.510149 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9469 12:38:29.513075 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9470 12:38:29.520037 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9471 12:38:29.522968 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9472 12:38:29.526403 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9473 12:38:29.533250 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9474 12:38:29.536685 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9475 12:38:29.543027 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9476 12:38:29.546846 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9477 12:38:29.550066 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9478 12:38:29.556337 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9479 12:38:29.559618 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9480 12:38:29.563401 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9481 12:38:29.569825 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9482 12:38:29.573374 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9483 12:38:29.580087 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9484 12:38:29.583843 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9485 12:38:29.586299 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9486 12:38:29.593410 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9487 12:38:29.596083 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9488 12:38:29.599653 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9489 12:38:29.606376 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9490 12:38:29.609326 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9491 12:38:29.615838 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9492 12:38:29.618889 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9493 12:38:29.625948 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9494 12:38:29.629303 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9495 12:38:29.632602 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9496 12:38:29.638975 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9497 12:38:29.642485 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9498 12:38:29.645813 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9499 12:38:29.649406 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9500 12:38:29.655777 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9501 12:38:29.659028 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9502 12:38:29.662112 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9503 12:38:29.665455 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9504 12:38:29.672475 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9505 12:38:29.675894 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9506 12:38:29.679307 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9507 12:38:29.682695 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9508 12:38:29.689034 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9509 12:38:29.692742 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9510 12:38:29.696348 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9511 12:38:29.702504 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9512 12:38:29.706065 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9513 12:38:29.709003 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9514 12:38:29.715834 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9515 12:38:29.718819 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9516 12:38:29.726549 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9517 12:38:29.729151 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9518 12:38:29.731832 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9519 12:38:29.739201 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9520 12:38:29.742280 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9521 12:38:29.749073 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9522 12:38:29.752268 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9523 12:38:29.759087 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9524 12:38:29.762049 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9525 12:38:29.765907 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9526 12:38:29.772031 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9527 12:38:29.775634 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9528 12:38:29.782200 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9529 12:38:29.786419 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9530 12:38:29.791991 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9531 12:38:29.795560 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9532 12:38:29.802469 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9533 12:38:29.805700 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9534 12:38:29.808764 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9535 12:38:29.815301 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9536 12:38:29.818819 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9537 12:38:29.825768 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9538 12:38:29.828281 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9539 12:38:29.835619 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9540 12:38:29.838752 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9541 12:38:29.841868 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9542 12:38:29.847969 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9543 12:38:29.851257 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9544 12:38:29.858512 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9545 12:38:29.861815 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9546 12:38:29.868308 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9547 12:38:29.871240 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9548 12:38:29.878716 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9549 12:38:29.881726 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9550 12:38:29.884995 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9551 12:38:29.891477 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9552 12:38:29.894783 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9553 12:38:29.901926 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9554 12:38:29.905126 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9555 12:38:29.911456 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9556 12:38:29.915030 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9557 12:38:29.918458 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9558 12:38:29.925835 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9559 12:38:29.928047 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9560 12:38:29.934191 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9561 12:38:29.937853 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9562 12:38:29.941330 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9563 12:38:29.947743 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9564 12:38:29.951177 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9565 12:38:29.954441 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9566 12:38:29.961304 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9567 12:38:29.963968 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9568 12:38:29.968174 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9569 12:38:29.974328 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9570 12:38:29.977810 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9571 12:38:29.984379 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9572 12:38:29.987986 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9573 12:38:29.991516 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9574 12:38:29.998005 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9575 12:38:30.001216 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9576 12:38:30.007172 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9577 12:38:30.010504 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9578 12:38:30.014813 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9579 12:38:30.020841 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9580 12:38:30.024209 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9581 12:38:30.027526 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9582 12:38:30.033822 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9583 12:38:30.038064 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9584 12:38:30.040892 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9585 12:38:30.047976 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9586 12:38:30.050917 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9587 12:38:30.054002 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9588 12:38:30.057234 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9589 12:38:30.063906 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9590 12:38:30.067492 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9591 12:38:30.070552 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9592 12:38:30.077377 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9593 12:38:30.080502 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9594 12:38:30.087131 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9595 12:38:30.090398 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9596 12:38:30.093970 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9597 12:38:30.100318 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9598 12:38:30.104015 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9599 12:38:30.111012 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9600 12:38:30.114115 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9601 12:38:30.117832 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9602 12:38:30.123848 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9603 12:38:30.127477 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9604 12:38:30.134115 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9605 12:38:30.137579 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9606 12:38:30.140070 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9607 12:38:30.146870 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9608 12:38:30.150699 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9609 12:38:30.153681 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9610 12:38:30.160298 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9611 12:38:30.163747 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9612 12:38:30.170156 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9613 12:38:30.173302 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9614 12:38:30.176860 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9615 12:38:30.183615 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9616 12:38:30.187046 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9617 12:38:30.193496 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9618 12:38:30.197122 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9619 12:38:30.200366 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9620 12:38:30.206924 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9621 12:38:30.209934 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9622 12:38:30.216317 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9623 12:38:30.219981 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9624 12:38:30.223534 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9625 12:38:30.229418 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9626 12:38:30.233403 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9627 12:38:30.239835 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9628 12:38:30.243142 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9629 12:38:30.245979 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9630 12:38:30.252851 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9631 12:38:30.256272 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9632 12:38:30.262851 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9633 12:38:30.266210 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9634 12:38:30.269304 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9635 12:38:30.275941 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9636 12:38:30.279465 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9637 12:38:30.285806 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9638 12:38:30.289119 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9639 12:38:30.292740 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9640 12:38:30.298889 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9641 12:38:30.302434 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9642 12:38:30.309058 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9643 12:38:30.312049 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9644 12:38:30.315779 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9645 12:38:30.322670 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9646 12:38:30.325571 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9647 12:38:30.332514 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9648 12:38:30.335448 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9649 12:38:30.338744 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9650 12:38:30.345496 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9651 12:38:30.348737 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9652 12:38:30.355324 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9653 12:38:30.358685 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9654 12:38:30.362036 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9655 12:38:30.368624 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9656 12:38:30.372066 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9657 12:38:30.378235 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9658 12:38:30.381860 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9659 12:38:30.388595 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9660 12:38:30.391591 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9661 12:38:30.394455 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9662 12:38:30.402357 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9663 12:38:30.404844 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9664 12:38:30.411770 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9665 12:38:30.414966 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9666 12:38:30.418063 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9667 12:38:30.424849 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9668 12:38:30.427644 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9669 12:38:30.434250 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9670 12:38:30.437485 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9671 12:38:30.444230 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9672 12:38:30.448107 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9673 12:38:30.450868 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9674 12:38:30.457976 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9675 12:38:30.461170 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9676 12:38:30.467548 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9677 12:38:30.471168 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9678 12:38:30.477469 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9679 12:38:30.480467 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9680 12:38:30.484031 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9681 12:38:30.490825 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9682 12:38:30.494454 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9683 12:38:30.500729 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9684 12:38:30.503991 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9685 12:38:30.510418 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9686 12:38:30.513857 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9687 12:38:30.516735 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9688 12:38:30.524216 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9689 12:38:30.526572 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9690 12:38:30.533558 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9691 12:38:30.536790 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9692 12:38:30.543287 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9693 12:38:30.546242 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9694 12:38:30.549642 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9695 12:38:30.553044 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9696 12:38:30.559204 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9697 12:38:30.562974 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9698 12:38:30.566000 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9699 12:38:30.573512 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9700 12:38:30.576040 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9701 12:38:30.579469 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9702 12:38:30.585841 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9703 12:38:30.589406 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9704 12:38:30.592479 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9705 12:38:30.599476 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9706 12:38:30.602422 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9707 12:38:30.609090 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9708 12:38:30.612459 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9709 12:38:30.616047 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9710 12:38:30.622052 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9711 12:38:30.625430 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9712 12:38:30.632199 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9713 12:38:30.635705 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9714 12:38:30.638711 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9715 12:38:30.645540 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9716 12:38:30.648401 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9717 12:38:30.652085 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9718 12:38:30.658746 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9719 12:38:30.661434 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9720 12:38:30.668505 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9721 12:38:30.671412 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9722 12:38:30.674917 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9723 12:38:30.681207 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9724 12:38:30.684851 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9725 12:38:30.688203 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9726 12:38:30.695134 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9727 12:38:30.698244 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9728 12:38:30.701413 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9729 12:38:30.708111 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9730 12:38:30.711437 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9731 12:38:30.717558 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9732 12:38:30.721094 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9733 12:38:30.724213 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9734 12:38:30.731119 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9735 12:38:30.734890 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9736 12:38:30.737698 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9737 12:38:30.740992 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9738 12:38:30.743841 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9739 12:38:30.750615 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9740 12:38:30.754204 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9741 12:38:30.757807 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9742 12:38:30.760229 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9743 12:38:30.767341 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9744 12:38:30.771217 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9745 12:38:30.773713 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9746 12:38:30.780530 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9747 12:38:30.783675 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9748 12:38:30.790005 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9749 12:38:30.794192 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9750 12:38:30.796734 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9751 12:38:30.803637 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9752 12:38:30.807056 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9753 12:38:30.813271 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9754 12:38:30.816406 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9755 12:38:30.820011 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9756 12:38:30.826342 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9757 12:38:30.830192 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9758 12:38:30.836430 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9759 12:38:30.839642 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9760 12:38:30.846198 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9761 12:38:30.850242 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9762 12:38:30.853022 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9763 12:38:30.859494 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9764 12:38:30.863020 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9765 12:38:30.869278 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9766 12:38:30.872395 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9767 12:38:30.876270 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9768 12:38:30.882592 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9769 12:38:30.885712 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9770 12:38:30.892695 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9771 12:38:30.895698 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9772 12:38:30.902511 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9773 12:38:30.905546 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9774 12:38:30.908717 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9775 12:38:30.915827 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9776 12:38:30.918642 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9777 12:38:30.925411 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9778 12:38:30.928793 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9779 12:38:30.932013 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9780 12:38:30.938781 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9781 12:38:30.941779 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9782 12:38:30.948777 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9783 12:38:30.951514 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9784 12:38:30.958102 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9785 12:38:30.961830 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9786 12:38:30.964844 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9787 12:38:30.971736 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9788 12:38:30.975092 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9789 12:38:30.982321 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9790 12:38:30.985193 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9791 12:38:30.991468 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9792 12:38:30.994757 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9793 12:38:30.997946 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9794 12:38:31.004520 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9795 12:38:31.008113 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9796 12:38:31.014799 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9797 12:38:31.017883 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9798 12:38:31.021012 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9799 12:38:31.027513 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9800 12:38:31.030688 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9801 12:38:31.037372 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9802 12:38:31.041097 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9803 12:38:31.044082 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9804 12:38:31.050469 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9805 12:38:31.054302 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9806 12:38:31.060853 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9807 12:38:31.064144 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9808 12:38:31.070439 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9809 12:38:31.073869 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9810 12:38:31.077355 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9811 12:38:31.083974 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9812 12:38:31.087437 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9813 12:38:31.093939 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9814 12:38:31.097264 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9815 12:38:31.100391 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9816 12:38:31.107287 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9817 12:38:31.110059 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9818 12:38:31.116942 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9819 12:38:31.120477 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9820 12:38:31.126835 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9821 12:38:31.130058 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9822 12:38:31.133095 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9823 12:38:31.139905 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9824 12:38:31.142817 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9825 12:38:31.150167 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9826 12:38:31.153218 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9827 12:38:31.159758 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9828 12:38:31.162793 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9829 12:38:31.169359 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9830 12:38:31.173150 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9831 12:38:31.176362 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9832 12:38:31.183004 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9833 12:38:31.186617 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9834 12:38:31.192789 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9835 12:38:31.196432 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9836 12:38:31.202907 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9837 12:38:31.206431 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9838 12:38:31.212796 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9839 12:38:31.215563 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9840 12:38:31.222426 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9841 12:38:31.225617 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9842 12:38:31.229086 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9843 12:38:31.236348 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9844 12:38:31.238904 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9845 12:38:31.245168 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9846 12:38:31.248399 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9847 12:38:31.255618 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9848 12:38:31.259313 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9849 12:38:31.265591 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9850 12:38:31.268539 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9851 12:38:31.271632 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9852 12:38:31.278457 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9853 12:38:31.281423 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9854 12:38:31.288290 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9855 12:38:31.291527 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9856 12:38:31.298288 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9857 12:38:31.301429 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9858 12:38:31.304608 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9859 12:38:31.311278 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9860 12:38:31.314487 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9861 12:38:31.321330 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9862 12:38:31.324393 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9863 12:38:31.330888 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9864 12:38:31.334316 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9865 12:38:31.341076 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9866 12:38:31.344561 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9867 12:38:31.347473 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9868 12:38:31.354902 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9869 12:38:31.357239 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9870 12:38:31.364205 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9871 12:38:31.367773 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9872 12:38:31.374229 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9873 12:38:31.377359 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9874 12:38:31.383749 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9875 12:38:31.387415 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9876 12:38:31.394160 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9877 12:38:31.397342 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9878 12:38:31.403786 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9879 12:38:31.407491 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9880 12:38:31.414009 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9881 12:38:31.417215 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9882 12:38:31.424034 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9883 12:38:31.427067 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9884 12:38:31.430208 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9885 12:38:31.436737 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9886 12:38:31.439861 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9887 12:38:31.446842 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9888 12:38:31.453505 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9889 12:38:31.456613 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9890 12:38:31.462983 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9891 12:38:31.466489 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9892 12:38:31.473152 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9893 12:38:31.476267 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9894 12:38:31.483521 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9895 12:38:31.486768 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9896 12:38:31.493192 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9897 12:38:31.496551 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9898 12:38:31.503142 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9899 12:38:31.506372 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9900 12:38:31.506883 INFO: [APUAPC] vio 0
9901 12:38:31.513945 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9902 12:38:31.517009 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9903 12:38:31.520149 INFO: [APUAPC] D0_APC_0: 0x400510
9904 12:38:31.523416 INFO: [APUAPC] D0_APC_1: 0x0
9905 12:38:31.526882 INFO: [APUAPC] D0_APC_2: 0x1540
9906 12:38:31.530423 INFO: [APUAPC] D0_APC_3: 0x0
9907 12:38:31.533824 INFO: [APUAPC] D1_APC_0: 0xffffffff
9908 12:38:31.536864 INFO: [APUAPC] D1_APC_1: 0xffffffff
9909 12:38:31.540048 INFO: [APUAPC] D1_APC_2: 0x3fffff
9910 12:38:31.543536 INFO: [APUAPC] D1_APC_3: 0x0
9911 12:38:31.546731 INFO: [APUAPC] D2_APC_0: 0xffffffff
9912 12:38:31.550045 INFO: [APUAPC] D2_APC_1: 0xffffffff
9913 12:38:31.553227 INFO: [APUAPC] D2_APC_2: 0x3fffff
9914 12:38:31.556758 INFO: [APUAPC] D2_APC_3: 0x0
9915 12:38:31.560145 INFO: [APUAPC] D3_APC_0: 0xffffffff
9916 12:38:31.563074 INFO: [APUAPC] D3_APC_1: 0xffffffff
9917 12:38:31.566536 INFO: [APUAPC] D3_APC_2: 0x3fffff
9918 12:38:31.570113 INFO: [APUAPC] D3_APC_3: 0x0
9919 12:38:31.572906 INFO: [APUAPC] D4_APC_0: 0xffffffff
9920 12:38:31.576772 INFO: [APUAPC] D4_APC_1: 0xffffffff
9921 12:38:31.579560 INFO: [APUAPC] D4_APC_2: 0x3fffff
9922 12:38:31.582794 INFO: [APUAPC] D4_APC_3: 0x0
9923 12:38:31.586513 INFO: [APUAPC] D5_APC_0: 0xffffffff
9924 12:38:31.589942 INFO: [APUAPC] D5_APC_1: 0xffffffff
9925 12:38:31.592942 INFO: [APUAPC] D5_APC_2: 0x3fffff
9926 12:38:31.596334 INFO: [APUAPC] D5_APC_3: 0x0
9927 12:38:31.599648 INFO: [APUAPC] D6_APC_0: 0xffffffff
9928 12:38:31.602982 INFO: [APUAPC] D6_APC_1: 0xffffffff
9929 12:38:31.606534 INFO: [APUAPC] D6_APC_2: 0x3fffff
9930 12:38:31.606947 INFO: [APUAPC] D6_APC_3: 0x0
9931 12:38:31.609315 INFO: [APUAPC] D7_APC_0: 0xffffffff
9932 12:38:31.616208 INFO: [APUAPC] D7_APC_1: 0xffffffff
9933 12:38:31.619270 INFO: [APUAPC] D7_APC_2: 0x3fffff
9934 12:38:31.619717 INFO: [APUAPC] D7_APC_3: 0x0
9935 12:38:31.622818 INFO: [APUAPC] D8_APC_0: 0xffffffff
9936 12:38:31.625908 INFO: [APUAPC] D8_APC_1: 0xffffffff
9937 12:38:31.629713 INFO: [APUAPC] D8_APC_2: 0x3fffff
9938 12:38:31.633266 INFO: [APUAPC] D8_APC_3: 0x0
9939 12:38:31.635804 INFO: [APUAPC] D9_APC_0: 0xffffffff
9940 12:38:31.639326 INFO: [APUAPC] D9_APC_1: 0xffffffff
9941 12:38:31.642881 INFO: [APUAPC] D9_APC_2: 0x3fffff
9942 12:38:31.646161 INFO: [APUAPC] D9_APC_3: 0x0
9943 12:38:31.649313 INFO: [APUAPC] D10_APC_0: 0xffffffff
9944 12:38:31.652518 INFO: [APUAPC] D10_APC_1: 0xffffffff
9945 12:38:31.656166 INFO: [APUAPC] D10_APC_2: 0x3fffff
9946 12:38:31.658882 INFO: [APUAPC] D10_APC_3: 0x0
9947 12:38:31.662322 INFO: [APUAPC] D11_APC_0: 0xffffffff
9948 12:38:31.665488 INFO: [APUAPC] D11_APC_1: 0xffffffff
9949 12:38:31.668996 INFO: [APUAPC] D11_APC_2: 0x3fffff
9950 12:38:31.672703 INFO: [APUAPC] D11_APC_3: 0x0
9951 12:38:31.676535 INFO: [APUAPC] D12_APC_0: 0xffffffff
9952 12:38:31.678889 INFO: [APUAPC] D12_APC_1: 0xffffffff
9953 12:38:31.682145 INFO: [APUAPC] D12_APC_2: 0x3fffff
9954 12:38:31.685690 INFO: [APUAPC] D12_APC_3: 0x0
9955 12:38:31.688704 INFO: [APUAPC] D13_APC_0: 0xffffffff
9956 12:38:31.695409 INFO: [APUAPC] D13_APC_1: 0xffffffff
9957 12:38:31.698397 INFO: [APUAPC] D13_APC_2: 0x3fffff
9958 12:38:31.698822 INFO: [APUAPC] D13_APC_3: 0x0
9959 12:38:31.702118 INFO: [APUAPC] D14_APC_0: 0xffffffff
9960 12:38:31.709026 INFO: [APUAPC] D14_APC_1: 0xffffffff
9961 12:38:31.711987 INFO: [APUAPC] D14_APC_2: 0x3fffff
9962 12:38:31.712403 INFO: [APUAPC] D14_APC_3: 0x0
9963 12:38:31.718833 INFO: [APUAPC] D15_APC_0: 0xffffffff
9964 12:38:31.721496 INFO: [APUAPC] D15_APC_1: 0xffffffff
9965 12:38:31.724902 INFO: [APUAPC] D15_APC_2: 0x3fffff
9966 12:38:31.728104 INFO: [APUAPC] D15_APC_3: 0x0
9967 12:38:31.728532 INFO: [APUAPC] APC_CON: 0x4
9968 12:38:31.731783 INFO: [NOCDAPC] D0_APC_0: 0x0
9969 12:38:31.735111 INFO: [NOCDAPC] D0_APC_1: 0x0
9970 12:38:31.738401 INFO: [NOCDAPC] D1_APC_0: 0x0
9971 12:38:31.741713 INFO: [NOCDAPC] D1_APC_1: 0xfff
9972 12:38:31.744992 INFO: [NOCDAPC] D2_APC_0: 0x0
9973 12:38:31.748043 INFO: [NOCDAPC] D2_APC_1: 0xfff
9974 12:38:31.751507 INFO: [NOCDAPC] D3_APC_0: 0x0
9975 12:38:31.754976 INFO: [NOCDAPC] D3_APC_1: 0xfff
9976 12:38:31.758162 INFO: [NOCDAPC] D4_APC_0: 0x0
9977 12:38:31.758710 INFO: [NOCDAPC] D4_APC_1: 0xfff
9978 12:38:31.761481 INFO: [NOCDAPC] D5_APC_0: 0x0
9979 12:38:31.764726 INFO: [NOCDAPC] D5_APC_1: 0xfff
9980 12:38:31.768143 INFO: [NOCDAPC] D6_APC_0: 0x0
9981 12:38:31.771044 INFO: [NOCDAPC] D6_APC_1: 0xfff
9982 12:38:31.774251 INFO: [NOCDAPC] D7_APC_0: 0x0
9983 12:38:31.778141 INFO: [NOCDAPC] D7_APC_1: 0xfff
9984 12:38:31.781039 INFO: [NOCDAPC] D8_APC_0: 0x0
9985 12:38:31.784538 INFO: [NOCDAPC] D8_APC_1: 0xfff
9986 12:38:31.787987 INFO: [NOCDAPC] D9_APC_0: 0x0
9987 12:38:31.790976 INFO: [NOCDAPC] D9_APC_1: 0xfff
9988 12:38:31.794260 INFO: [NOCDAPC] D10_APC_0: 0x0
9989 12:38:31.794673 INFO: [NOCDAPC] D10_APC_1: 0xfff
9990 12:38:31.797441 INFO: [NOCDAPC] D11_APC_0: 0x0
9991 12:38:31.801168 INFO: [NOCDAPC] D11_APC_1: 0xfff
9992 12:38:31.804006 INFO: [NOCDAPC] D12_APC_0: 0x0
9993 12:38:31.807605 INFO: [NOCDAPC] D12_APC_1: 0xfff
9994 12:38:31.810897 INFO: [NOCDAPC] D13_APC_0: 0x0
9995 12:38:31.813909 INFO: [NOCDAPC] D13_APC_1: 0xfff
9996 12:38:31.817368 INFO: [NOCDAPC] D14_APC_0: 0x0
9997 12:38:31.820702 INFO: [NOCDAPC] D14_APC_1: 0xfff
9998 12:38:31.823878 INFO: [NOCDAPC] D15_APC_0: 0x0
9999 12:38:31.827270 INFO: [NOCDAPC] D15_APC_1: 0xfff
10000 12:38:31.830545 INFO: [NOCDAPC] APC_CON: 0x4
10001 12:38:31.833948 INFO: [APUAPC] set_apusys_apc done
10002 12:38:31.837031 INFO: [DEVAPC] devapc_init done
10003 12:38:31.840191 INFO: GICv3 without legacy support detected.
10004 12:38:31.843963 INFO: ARM GICv3 driver initialized in EL3
10005 12:38:31.846950 INFO: Maximum SPI INTID supported: 639
10006 12:38:31.850643 INFO: BL31: Initializing runtime services
10007 12:38:31.857030 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10008 12:38:31.860259 INFO: SPM: enable CPC mode
10009 12:38:31.866974 INFO: mcdi ready for mcusys-off-idle and system suspend
10010 12:38:31.870494 INFO: BL31: Preparing for EL3 exit to normal world
10011 12:38:31.873970 INFO: Entry point address = 0x80000000
10012 12:38:31.876507 INFO: SPSR = 0x8
10013 12:38:31.882104
10014 12:38:31.882518
10015 12:38:31.882848
10016 12:38:31.885205 Starting depthcharge on Spherion...
10017 12:38:31.885731
10018 12:38:31.886124 Wipe memory regions:
10019 12:38:31.886453
10020 12:38:31.889159 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10021 12:38:31.889672 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10022 12:38:31.890072 Setting prompt string to ['asurada:']
10023 12:38:31.890540 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10024 12:38:31.891215 [0x00000040000000, 0x00000054600000)
10025 12:38:32.011016
10026 12:38:32.011628 [0x00000054660000, 0x00000080000000)
10027 12:38:32.271241
10028 12:38:32.271765 [0x000000821a7280, 0x000000ffe64000)
10029 12:38:33.016212
10030 12:38:33.016748 [0x00000100000000, 0x00000240000000)
10031 12:38:34.907562
10032 12:38:34.910175 Initializing XHCI USB controller at 0x11200000.
10033 12:38:35.947411
10034 12:38:35.950703 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10035 12:38:35.950790
10036 12:38:35.950854
10037 12:38:35.950914
10038 12:38:35.951205 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10040 12:38:36.051641 asurada: tftpboot 192.168.201.1 12703560/tftp-deploy-ggnh9y3q/kernel/image.itb 12703560/tftp-deploy-ggnh9y3q/kernel/cmdline
10041 12:38:36.051768 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10042 12:38:36.051851 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10043 12:38:36.056389 tftpboot 192.168.201.1 12703560/tftp-deploy-ggnh9y3q/kernel/image.ittp-deploy-ggnh9y3q/kernel/cmdline
10044 12:38:36.056473
10045 12:38:36.056536 Waiting for link
10046 12:38:36.216805
10047 12:38:36.216924 R8152: Initializing
10048 12:38:36.216990
10049 12:38:36.220113 Version 6 (ocp_data = 5c30)
10050 12:38:36.220195
10051 12:38:36.223928 R8152: Done initializing
10052 12:38:36.224010
10053 12:38:36.224074 Adding net device
10054 12:38:38.094366
10055 12:38:38.094509 done.
10056 12:38:38.094577
10057 12:38:38.094637 MAC: 00:24:32:30:7c:7b
10058 12:38:38.094696
10059 12:38:38.098620 Sending DHCP discover... done.
10060 12:38:38.098701
10061 12:38:43.903600 Waiting for reply... done.
10062 12:38:43.903736
10063 12:38:43.903818 Sending DHCP request... done.
10064 12:38:43.906899
10065 12:38:43.912739 Waiting for reply... done.
10066 12:38:43.912815
10067 12:38:43.912924 My ip is 192.168.201.14
10068 12:38:43.913025
10069 12:38:43.916161 The DHCP server ip is 192.168.201.1
10070 12:38:43.916237
10071 12:38:43.922726 TFTP server IP predefined by user: 192.168.201.1
10072 12:38:43.922800
10073 12:38:43.929297 Bootfile predefined by user: 12703560/tftp-deploy-ggnh9y3q/kernel/image.itb
10074 12:38:43.929378
10075 12:38:43.933052 Sending tftp read request... done.
10076 12:38:43.933131
10077 12:38:43.936204 Waiting for the transfer...
10078 12:38:43.936290
10079 12:38:44.458880 00000000 ################################################################
10080 12:38:44.459028
10081 12:38:44.982959 00080000 ################################################################
10082 12:38:44.983096
10083 12:38:45.508480 00100000 ################################################################
10084 12:38:45.508613
10085 12:38:46.042925 00180000 ################################################################
10086 12:38:46.043054
10087 12:38:46.577226 00200000 ################################################################
10088 12:38:46.577390
10089 12:38:47.098532 00280000 ################################################################
10090 12:38:47.098680
10091 12:38:47.620780 00300000 ################################################################
10092 12:38:47.620922
10093 12:38:48.156331 00380000 ################################################################
10094 12:38:48.156462
10095 12:38:48.677876 00400000 ################################################################
10096 12:38:48.678022
10097 12:38:49.215155 00480000 ################################################################
10098 12:38:49.215314
10099 12:38:49.739569 00500000 ################################################################
10100 12:38:49.739702
10101 12:38:50.259465 00580000 ################################################################
10102 12:38:50.259600
10103 12:38:50.781736 00600000 ################################################################
10104 12:38:50.781891
10105 12:38:51.326406 00680000 ################################################################
10106 12:38:51.326574
10107 12:38:51.875097 00700000 ################################################################
10108 12:38:51.875228
10109 12:38:52.406016 00780000 ################################################################
10110 12:38:52.406150
10111 12:38:52.962753 00800000 ################################################################
10112 12:38:52.962913
10113 12:38:53.482488 00880000 ################################################################
10114 12:38:53.482644
10115 12:38:54.014668 00900000 ################################################################
10116 12:38:54.014799
10117 12:38:54.538717 00980000 ################################################################
10118 12:38:54.538873
10119 12:38:55.079905 00a00000 ################################################################
10120 12:38:55.080055
10121 12:38:55.610072 00a80000 ################################################################
10122 12:38:55.610229
10123 12:38:56.145976 00b00000 ################################################################
10124 12:38:56.146109
10125 12:38:56.714311 00b80000 ################################################################
10126 12:38:56.714518
10127 12:38:57.264073 00c00000 ################################################################
10128 12:38:57.264219
10129 12:38:57.792635 00c80000 ################################################################
10130 12:38:57.792766
10131 12:38:58.314364 00d00000 ################################################################
10132 12:38:58.314517
10133 12:38:58.941164 00d80000 ################################################################
10134 12:38:58.941693
10135 12:38:59.667135 00e00000 ################################################################
10136 12:38:59.667769
10137 12:39:00.387656 00e80000 ################################################################
10138 12:39:00.388382
10139 12:39:01.081941 00f00000 ################################################################
10140 12:39:01.082444
10141 12:39:01.796400 00f80000 ################################################################
10142 12:39:01.796899
10143 12:39:02.494378 01000000 ################################################################
10144 12:39:02.494896
10145 12:39:03.198461 01080000 ################################################################
10146 12:39:03.198961
10147 12:39:03.905773 01100000 ################################################################
10148 12:39:03.906269
10149 12:39:04.618402 01180000 ################################################################
10150 12:39:04.618938
10151 12:39:05.341432 01200000 ################################################################
10152 12:39:05.341959
10153 12:39:06.048210 01280000 ################################################################
10154 12:39:06.048750
10155 12:39:06.770151 01300000 ################################################################
10156 12:39:06.770706
10157 12:39:07.492600 01380000 ################################################################
10158 12:39:07.493356
10159 12:39:08.207638 01400000 ################################################################
10160 12:39:08.208162
10161 12:39:08.939573 01480000 ################################################################
10162 12:39:08.940099
10163 12:39:09.615994 01500000 ################################################################
10164 12:39:09.616517
10165 12:39:10.328579 01580000 ################################################################
10166 12:39:10.329096
10167 12:39:11.055459 01600000 ################################################################
10168 12:39:11.056022
10169 12:39:11.771656 01680000 ################################################################
10170 12:39:11.772310
10171 12:39:12.430171 01700000 ################################################################
10172 12:39:12.430321
10173 12:39:13.101324 01780000 ################################################################
10174 12:39:13.101846
10175 12:39:13.779097 01800000 ################################################################
10176 12:39:13.779251
10177 12:39:14.450803 01880000 ################################################################
10178 12:39:14.451303
10179 12:39:15.155671 01900000 ################################################################
10180 12:39:15.156169
10181 12:39:15.815669 01980000 ################################################################
10182 12:39:15.815799
10183 12:39:16.383400 01a00000 ################################################################
10184 12:39:16.383563
10185 12:39:16.940916 01a80000 ################################################################
10186 12:39:16.941052
10187 12:39:17.574301 01b00000 ################################################################
10188 12:39:17.574785
10189 12:39:18.168921 01b80000 ################################################################
10190 12:39:18.169074
10191 12:39:18.805265 01c00000 ################################################################
10192 12:39:18.805753
10193 12:39:19.513563 01c80000 ################################################################
10194 12:39:19.514074
10195 12:39:20.168761 01d00000 ################################################################
10196 12:39:20.168896
10197 12:39:20.724254 01d80000 ################################################################
10198 12:39:20.724404
10199 12:39:21.336407 01e00000 ################################################################
10200 12:39:21.336544
10201 12:39:21.966486 01e80000 ################################################################
10202 12:39:21.966980
10203 12:39:22.600166 01f00000 ################################################################
10204 12:39:22.600302
10205 12:39:23.185029 01f80000 ######################################################### done.
10206 12:39:23.185164
10207 12:39:23.188096 The bootfile was 33494678 bytes long.
10208 12:39:23.188181
10209 12:39:23.191916 Sending tftp read request... done.
10210 12:39:23.192005
10211 12:39:23.192074 Waiting for the transfer...
10212 12:39:23.192140
10213 12:39:23.195056 00000000 # done.
10214 12:39:23.195153
10215 12:39:23.201707 Command line loaded dynamically from TFTP file: 12703560/tftp-deploy-ggnh9y3q/kernel/cmdline
10216 12:39:23.201810
10217 12:39:23.214732 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10218 12:39:23.214941
10219 12:39:23.218397 Loading FIT.
10220 12:39:23.218625
10221 12:39:23.221259 Image ramdisk-1 has 21392506 bytes.
10222 12:39:23.221479
10223 12:39:23.224714 Image fdt-1 has 47278 bytes.
10224 12:39:23.224894
10225 12:39:23.227887 Image kernel-1 has 12052857 bytes.
10226 12:39:23.228061
10227 12:39:23.234561 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10228 12:39:23.234645
10229 12:39:23.254385 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10230 12:39:23.254506
10231 12:39:23.257320 Choosing best match conf-1 for compat google,spherion-rev2.
10232 12:39:23.261865
10233 12:39:23.266530 Connected to device vid:did:rid of 1ae0:0028:00
10234 12:39:23.273775
10235 12:39:23.276990 tpm_get_response: command 0x17b, return code 0x0
10236 12:39:23.277166
10237 12:39:23.280319 ec_init: CrosEC protocol v3 supported (256, 248)
10238 12:39:23.284590
10239 12:39:23.288083 tpm_cleanup: add release locality here.
10240 12:39:23.288391
10241 12:39:23.288629 Shutting down all USB controllers.
10242 12:39:23.291652
10243 12:39:23.291950 Removing current net device
10244 12:39:23.292190
10245 12:39:23.297792 Exiting depthcharge with code 4 at timestamp: 80673314
10246 12:39:23.298234
10247 12:39:23.301618 LZMA decompressing kernel-1 to 0x821a6718
10248 12:39:23.302070
10249 12:39:23.304785 LZMA decompressing kernel-1 to 0x40000000
10250 12:39:24.803582
10251 12:39:24.803734 jumping to kernel
10252 12:39:24.804199 end: 2.2.4 bootloader-commands (duration 00:00:53) [common]
10253 12:39:24.804303 start: 2.2.5 auto-login-action (timeout 00:03:32) [common]
10254 12:39:24.804381 Setting prompt string to ['Linux version [0-9]']
10255 12:39:24.804451 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10256 12:39:24.804525 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10257 12:39:24.886009
10258 12:39:24.888793 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10259 12:39:24.892325 start: 2.2.5.1 login-action (timeout 00:03:32) [common]
10260 12:39:24.892412 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10261 12:39:24.892486 Setting prompt string to []
10262 12:39:24.892566 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10263 12:39:24.892642 Using line separator: #'\n'#
10264 12:39:24.892701 No login prompt set.
10265 12:39:24.892759 Parsing kernel messages
10266 12:39:24.892814 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10267 12:39:24.892919 [login-action] Waiting for messages, (timeout 00:03:32)
10268 12:39:24.892983 Waiting using forced prompt support (timeout 00:01:46)
10269 12:39:24.912118 [ 0.000000] Linux version 6.1.75-cip14 (KernelCI@build-j98433-arm64-gcc-10-defconfig-arm64-chromebook-89n64) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Feb 5 12:20:06 UTC 2024
10270 12:39:24.915514 [ 0.000000] random: crng init done
10271 12:39:24.922064 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10272 12:39:24.925652 [ 0.000000] efi: UEFI not found.
10273 12:39:24.932105 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10274 12:39:24.938278 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10275 12:39:24.948151 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10276 12:39:24.958655 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10277 12:39:24.964663 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10278 12:39:24.971488 [ 0.000000] printk: bootconsole [mtk8250] enabled
10279 12:39:24.977846 [ 0.000000] NUMA: No NUMA configuration found
10280 12:39:24.984667 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10281 12:39:24.987660 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10282 12:39:24.991683 [ 0.000000] Zone ranges:
10283 12:39:24.997767 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10284 12:39:25.001210 [ 0.000000] DMA32 empty
10285 12:39:25.007825 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10286 12:39:25.010975 [ 0.000000] Movable zone start for each node
10287 12:39:25.014131 [ 0.000000] Early memory node ranges
10288 12:39:25.021143 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10289 12:39:25.027699 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10290 12:39:25.033958 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10291 12:39:25.041468 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10292 12:39:25.047470 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10293 12:39:25.054048 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10294 12:39:25.110113 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10295 12:39:25.116777 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10296 12:39:25.123205 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10297 12:39:25.126873 [ 0.000000] psci: probing for conduit method from DT.
10298 12:39:25.133572 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10299 12:39:25.136488 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10300 12:39:25.143254 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10301 12:39:25.146337 [ 0.000000] psci: SMC Calling Convention v1.2
10302 12:39:25.152790 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10303 12:39:25.156130 [ 0.000000] Detected VIPT I-cache on CPU0
10304 12:39:25.162860 [ 0.000000] CPU features: detected: GIC system register CPU interface
10305 12:39:25.169397 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10306 12:39:25.176460 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10307 12:39:25.182767 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10308 12:39:25.189337 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10309 12:39:25.199110 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10310 12:39:25.202382 [ 0.000000] alternatives: applying boot alternatives
10311 12:39:25.209734 [ 0.000000] Fallback order for Node 0: 0
10312 12:39:25.215554 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10313 12:39:25.218911 [ 0.000000] Policy zone: Normal
10314 12:39:25.232360 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10315 12:39:25.242040 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10316 12:39:25.254499 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10317 12:39:25.263958 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10318 12:39:25.270395 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10319 12:39:25.274079 <6>[ 0.000000] software IO TLB: area num 8.
10320 12:39:25.330513 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10321 12:39:25.479625 <6>[ 0.000000] Memory: 7946364K/8385536K available (17984K kernel code, 4118K rwdata, 19612K rodata, 8448K init, 616K bss, 406404K reserved, 32768K cma-reserved)
10322 12:39:25.486066 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10323 12:39:25.492933 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10324 12:39:25.496199 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10325 12:39:25.502624 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10326 12:39:25.509625 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10327 12:39:25.512659 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10328 12:39:25.522446 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10329 12:39:25.529391 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10330 12:39:25.535742 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10331 12:39:25.542306 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10332 12:39:25.545947 <6>[ 0.000000] GICv3: 608 SPIs implemented
10333 12:39:25.549086 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10334 12:39:25.555604 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10335 12:39:25.559102 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10336 12:39:25.565403 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10337 12:39:25.579011 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10338 12:39:25.591718 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10339 12:39:25.598797 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10340 12:39:25.606585 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10341 12:39:25.620114 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10342 12:39:25.626202 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10343 12:39:25.632624 <6>[ 0.009181] Console: colour dummy device 80x25
10344 12:39:25.642659 <6>[ 0.013898] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10345 12:39:25.649105 <6>[ 0.024404] pid_max: default: 32768 minimum: 301
10346 12:39:25.652434 <6>[ 0.029305] LSM: Security Framework initializing
10347 12:39:25.659267 <6>[ 0.034243] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10348 12:39:25.668842 <6>[ 0.042057] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10349 12:39:25.679001 <6>[ 0.051473] cblist_init_generic: Setting adjustable number of callback queues.
10350 12:39:25.682317 <6>[ 0.058917] cblist_init_generic: Setting shift to 3 and lim to 1.
10351 12:39:25.691869 <6>[ 0.065294] cblist_init_generic: Setting adjustable number of callback queues.
10352 12:39:25.698522 <6>[ 0.072721] cblist_init_generic: Setting shift to 3 and lim to 1.
10353 12:39:25.701649 <6>[ 0.079121] rcu: Hierarchical SRCU implementation.
10354 12:39:25.708460 <6>[ 0.084136] rcu: Max phase no-delay instances is 1000.
10355 12:39:25.715252 <6>[ 0.091168] EFI services will not be available.
10356 12:39:25.718213 <6>[ 0.096123] smp: Bringing up secondary CPUs ...
10357 12:39:25.727511 <6>[ 0.101174] Detected VIPT I-cache on CPU1
10358 12:39:25.733801 <6>[ 0.101241] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10359 12:39:25.740527 <6>[ 0.101273] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10360 12:39:25.743495 <6>[ 0.101615] Detected VIPT I-cache on CPU2
10361 12:39:25.750034 <6>[ 0.101665] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10362 12:39:25.760196 <6>[ 0.101683] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10363 12:39:25.763879 <6>[ 0.101942] Detected VIPT I-cache on CPU3
10364 12:39:25.770104 <6>[ 0.101990] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10365 12:39:25.776845 <6>[ 0.102005] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10366 12:39:25.779819 <6>[ 0.102310] CPU features: detected: Spectre-v4
10367 12:39:25.786384 <6>[ 0.102316] CPU features: detected: Spectre-BHB
10368 12:39:25.789810 <6>[ 0.102321] Detected PIPT I-cache on CPU4
10369 12:39:25.796239 <6>[ 0.102379] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10370 12:39:25.803147 <6>[ 0.102396] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10371 12:39:25.809531 <6>[ 0.102688] Detected PIPT I-cache on CPU5
10372 12:39:25.816026 <6>[ 0.102750] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10373 12:39:25.822817 <6>[ 0.102766] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10374 12:39:25.826100 <6>[ 0.103047] Detected PIPT I-cache on CPU6
10375 12:39:25.832660 <6>[ 0.103110] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10376 12:39:25.839260 <6>[ 0.103126] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10377 12:39:25.845871 <6>[ 0.103424] Detected PIPT I-cache on CPU7
10378 12:39:25.852581 <6>[ 0.103488] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10379 12:39:25.859103 <6>[ 0.103505] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10380 12:39:25.862265 <6>[ 0.103552] smp: Brought up 1 node, 8 CPUs
10381 12:39:25.868753 <6>[ 0.244782] SMP: Total of 8 processors activated.
10382 12:39:25.872318 <6>[ 0.249703] CPU features: detected: 32-bit EL0 Support
10383 12:39:25.881988 <6>[ 0.255066] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10384 12:39:25.889148 <6>[ 0.263865] CPU features: detected: Common not Private translations
10385 12:39:25.895516 <6>[ 0.270380] CPU features: detected: CRC32 instructions
10386 12:39:25.898714 <6>[ 0.275731] CPU features: detected: RCpc load-acquire (LDAPR)
10387 12:39:25.905281 <6>[ 0.281728] CPU features: detected: LSE atomic instructions
10388 12:39:25.912127 <6>[ 0.287509] CPU features: detected: Privileged Access Never
10389 12:39:25.918615 <6>[ 0.293289] CPU features: detected: RAS Extension Support
10390 12:39:25.925304 <6>[ 0.298932] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10391 12:39:25.928599 <6>[ 0.306149] CPU: All CPU(s) started at EL2
10392 12:39:25.934606 <6>[ 0.310466] alternatives: applying system-wide alternatives
10393 12:39:25.944433 <6>[ 0.321184] devtmpfs: initialized
10394 12:39:25.959893 <6>[ 0.330090] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10395 12:39:25.966776 <6>[ 0.340051] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10396 12:39:25.973097 <6>[ 0.348070] pinctrl core: initialized pinctrl subsystem
10397 12:39:25.976587 <6>[ 0.354698] DMI not present or invalid.
10398 12:39:25.983090 <6>[ 0.359110] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10399 12:39:25.993305 <6>[ 0.365897] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10400 12:39:25.999384 <6>[ 0.373479] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10401 12:39:26.009656 <6>[ 0.381696] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10402 12:39:26.012554 <6>[ 0.389942] audit: initializing netlink subsys (disabled)
10403 12:39:26.022775 <5>[ 0.395632] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10404 12:39:26.029478 <6>[ 0.396338] thermal_sys: Registered thermal governor 'step_wise'
10405 12:39:26.035794 <6>[ 0.403603] thermal_sys: Registered thermal governor 'power_allocator'
10406 12:39:26.038869 <6>[ 0.409859] cpuidle: using governor menu
10407 12:39:26.045775 <6>[ 0.420819] NET: Registered PF_QIPCRTR protocol family
10408 12:39:26.052089 <6>[ 0.426291] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10409 12:39:26.058499 <6>[ 0.433392] ASID allocator initialised with 32768 entries
10410 12:39:26.061882 <6>[ 0.439950] Serial: AMBA PL011 UART driver
10411 12:39:26.072346 <4>[ 0.448723] Trying to register duplicate clock ID: 134
10412 12:39:26.126101 <6>[ 0.506030] KASLR enabled
10413 12:39:26.141148 <6>[ 0.513688] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10414 12:39:26.146725 <6>[ 0.520701] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10415 12:39:26.153648 <6>[ 0.527189] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10416 12:39:26.160002 <6>[ 0.534193] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10417 12:39:26.166834 <6>[ 0.540680] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10418 12:39:26.173415 <6>[ 0.547684] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10419 12:39:26.180052 <6>[ 0.554170] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10420 12:39:26.186261 <6>[ 0.561173] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10421 12:39:26.189837 <6>[ 0.568638] ACPI: Interpreter disabled.
10422 12:39:26.198633 <6>[ 0.575081] iommu: Default domain type: Translated
10423 12:39:26.204901 <6>[ 0.580193] iommu: DMA domain TLB invalidation policy: strict mode
10424 12:39:26.208398 <5>[ 0.586853] SCSI subsystem initialized
10425 12:39:26.215006 <6>[ 0.591105] usbcore: registered new interface driver usbfs
10426 12:39:26.221775 <6>[ 0.596835] usbcore: registered new interface driver hub
10427 12:39:26.224720 <6>[ 0.602389] usbcore: registered new device driver usb
10428 12:39:26.232270 <6>[ 0.608510] pps_core: LinuxPPS API ver. 1 registered
10429 12:39:26.241706 <6>[ 0.613703] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10430 12:39:26.245174 <6>[ 0.623051] PTP clock support registered
10431 12:39:26.248172 <6>[ 0.627293] EDAC MC: Ver: 3.0.0
10432 12:39:26.256142 <6>[ 0.632477] FPGA manager framework
10433 12:39:26.262375 <6>[ 0.636151] Advanced Linux Sound Architecture Driver Initialized.
10434 12:39:26.265473 <6>[ 0.642923] vgaarb: loaded
10435 12:39:26.272175 <6>[ 0.646064] clocksource: Switched to clocksource arch_sys_counter
10436 12:39:26.275711 <5>[ 0.652510] VFS: Disk quotas dquot_6.6.0
10437 12:39:26.282242 <6>[ 0.656697] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10438 12:39:26.285803 <6>[ 0.663886] pnp: PnP ACPI: disabled
10439 12:39:26.293843 <6>[ 0.670526] NET: Registered PF_INET protocol family
10440 12:39:26.303526 <6>[ 0.676115] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10441 12:39:26.315276 <6>[ 0.688443] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10442 12:39:26.325110 <6>[ 0.697262] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10443 12:39:26.331659 <6>[ 0.705233] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10444 12:39:26.341399 <6>[ 0.713934] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10445 12:39:26.348700 <6>[ 0.723696] TCP: Hash tables configured (established 65536 bind 65536)
10446 12:39:26.354823 <6>[ 0.730569] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10447 12:39:26.364566 <6>[ 0.737771] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10448 12:39:26.371022 <6>[ 0.745474] NET: Registered PF_UNIX/PF_LOCAL protocol family
10449 12:39:26.378052 <6>[ 0.751604] RPC: Registered named UNIX socket transport module.
10450 12:39:26.381198 <6>[ 0.757755] RPC: Registered udp transport module.
10451 12:39:26.387799 <6>[ 0.762687] RPC: Registered tcp transport module.
10452 12:39:26.394016 <6>[ 0.767620] RPC: Registered tcp NFSv4.1 backchannel transport module.
10453 12:39:26.397334 <6>[ 0.774284] PCI: CLS 0 bytes, default 64
10454 12:39:26.400867 <6>[ 0.778630] Unpacking initramfs...
10455 12:39:26.424902 <6>[ 0.798153] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10456 12:39:26.435051 <6>[ 0.806824] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10457 12:39:26.437931 <6>[ 0.815689] kvm [1]: IPA Size Limit: 40 bits
10458 12:39:26.444915 <6>[ 0.820219] kvm [1]: GICv3: no GICV resource entry
10459 12:39:26.448188 <6>[ 0.825243] kvm [1]: disabling GICv2 emulation
10460 12:39:26.454587 <6>[ 0.829941] kvm [1]: GIC system register CPU interface enabled
10461 12:39:26.458020 <6>[ 0.836108] kvm [1]: vgic interrupt IRQ18
10462 12:39:26.464596 <6>[ 0.840463] kvm [1]: VHE mode initialized successfully
10463 12:39:26.471387 <5>[ 0.847005] Initialise system trusted keyrings
10464 12:39:26.477752 <6>[ 0.851786] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10465 12:39:26.485033 <6>[ 0.861753] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10466 12:39:26.491652 <5>[ 0.868151] NFS: Registering the id_resolver key type
10467 12:39:26.495374 <5>[ 0.873452] Key type id_resolver registered
10468 12:39:26.502050 <5>[ 0.877866] Key type id_legacy registered
10469 12:39:26.508172 <6>[ 0.882143] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10470 12:39:26.515089 <6>[ 0.889065] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10471 12:39:26.521393 <6>[ 0.896775] 9p: Installing v9fs 9p2000 file system support
10472 12:39:26.557854 <5>[ 0.934469] Key type asymmetric registered
10473 12:39:26.561881 <5>[ 0.938799] Asymmetric key parser 'x509' registered
10474 12:39:26.571305 <6>[ 0.943978] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10475 12:39:26.574315 <6>[ 0.951597] io scheduler mq-deadline registered
10476 12:39:26.577990 <6>[ 0.956366] io scheduler kyber registered
10477 12:39:26.596881 <6>[ 0.973481] EINJ: ACPI disabled.
10478 12:39:26.628823 <4>[ 0.998904] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10479 12:39:26.638888 <4>[ 1.009548] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10480 12:39:26.654202 <6>[ 1.030779] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10481 12:39:26.662142 <6>[ 1.038950] printk: console [ttyS0] disabled
10482 12:39:26.690390 <6>[ 1.063589] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10483 12:39:26.697596 <6>[ 1.073069] printk: console [ttyS0] enabled
10484 12:39:26.700636 <6>[ 1.073069] printk: console [ttyS0] enabled
10485 12:39:26.707157 <6>[ 1.081961] printk: bootconsole [mtk8250] disabled
10486 12:39:26.710452 <6>[ 1.081961] printk: bootconsole [mtk8250] disabled
10487 12:39:26.717511 <6>[ 1.093163] SuperH (H)SCI(F) driver initialized
10488 12:39:26.720641 <6>[ 1.098434] msm_serial: driver initialized
10489 12:39:26.734268 <6>[ 1.107329] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10490 12:39:26.744177 <6>[ 1.115874] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10491 12:39:26.751598 <6>[ 1.124415] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10492 12:39:26.760738 <6>[ 1.133043] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10493 12:39:26.771058 <6>[ 1.141750] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10494 12:39:26.777181 <6>[ 1.150463] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10495 12:39:26.787019 <6>[ 1.159003] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10496 12:39:26.793335 <6>[ 1.167808] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10497 12:39:26.803724 <6>[ 1.176353] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10498 12:39:26.815572 <6>[ 1.192076] loop: module loaded
10499 12:39:26.822059 <6>[ 1.198084] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10500 12:39:26.844611 <4>[ 1.220778] mtk-pmic-keys: Failed to locate of_node [id: -1]
10501 12:39:26.851412 <6>[ 1.227727] megasas: 07.719.03.00-rc1
10502 12:39:26.860574 <6>[ 1.237305] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10503 12:39:26.869013 <6>[ 1.245442] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10504 12:39:26.886078 <6>[ 1.262136] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10505 12:39:26.942300 <6>[ 1.312072] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10506 12:39:27.306546 <6>[ 1.683416] Freeing initrd memory: 20888K
10507 12:39:27.322909 <6>[ 1.699263] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10508 12:39:27.333888 <6>[ 1.710366] tun: Universal TUN/TAP device driver, 1.6
10509 12:39:27.337415 <6>[ 1.716428] thunder_xcv, ver 1.0
10510 12:39:27.340247 <6>[ 1.719937] thunder_bgx, ver 1.0
10511 12:39:27.343792 <6>[ 1.723432] nicpf, ver 1.0
10512 12:39:27.354055 <6>[ 1.727460] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10513 12:39:27.357861 <6>[ 1.734937] hns3: Copyright (c) 2017 Huawei Corporation.
10514 12:39:27.360683 <6>[ 1.740525] hclge is initializing
10515 12:39:27.367701 <6>[ 1.744106] e1000: Intel(R) PRO/1000 Network Driver
10516 12:39:27.374821 <6>[ 1.749236] e1000: Copyright (c) 1999-2006 Intel Corporation.
10517 12:39:27.377754 <6>[ 1.755249] e1000e: Intel(R) PRO/1000 Network Driver
10518 12:39:27.384049 <6>[ 1.760464] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10519 12:39:27.390646 <6>[ 1.766651] igb: Intel(R) Gigabit Ethernet Network Driver
10520 12:39:27.397424 <6>[ 1.772300] igb: Copyright (c) 2007-2014 Intel Corporation.
10521 12:39:27.404342 <6>[ 1.778141] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10522 12:39:27.411515 <6>[ 1.784658] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10523 12:39:27.414744 <6>[ 1.791120] sky2: driver version 1.30
10524 12:39:27.420613 <6>[ 1.796129] VFIO - User Level meta-driver version: 0.3
10525 12:39:27.427970 <6>[ 1.804382] usbcore: registered new interface driver usb-storage
10526 12:39:27.434543 <6>[ 1.810834] usbcore: registered new device driver onboard-usb-hub
10527 12:39:27.443336 <6>[ 1.820001] mt6397-rtc mt6359-rtc: registered as rtc0
10528 12:39:27.453325 <6>[ 1.825465] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-05T12:39:31 UTC (1707136771)
10529 12:39:27.456694 <6>[ 1.835031] i2c_dev: i2c /dev entries driver
10530 12:39:27.473231 <6>[ 1.846764] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10531 12:39:27.494367 <6>[ 1.870747] cpu cpu0: EM: created perf domain
10532 12:39:27.497496 <6>[ 1.875687] cpu cpu4: EM: created perf domain
10533 12:39:27.504697 <6>[ 1.881283] sdhci: Secure Digital Host Controller Interface driver
10534 12:39:27.511690 <6>[ 1.887716] sdhci: Copyright(c) Pierre Ossman
10535 12:39:27.517943 <6>[ 1.892673] Synopsys Designware Multimedia Card Interface Driver
10536 12:39:27.524368 <6>[ 1.899300] sdhci-pltfm: SDHCI platform and OF driver helper
10537 12:39:27.527598 <6>[ 1.899334] mmc0: CQHCI version 5.10
10538 12:39:27.534444 <6>[ 1.909210] ledtrig-cpu: registered to indicate activity on CPUs
10539 12:39:27.540855 <6>[ 1.916175] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10540 12:39:27.547517 <6>[ 1.923221] usbcore: registered new interface driver usbhid
10541 12:39:27.550797 <6>[ 1.929044] usbhid: USB HID core driver
10542 12:39:27.557809 <6>[ 1.933240] spi_master spi0: will run message pump with realtime priority
10543 12:39:27.604378 <6>[ 1.974018] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10544 12:39:27.619867 <6>[ 1.989670] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10545 12:39:27.627575 <6>[ 2.003841] mmc0: Command Queue Engine enabled
10546 12:39:27.634416 <6>[ 2.004851] cros-ec-spi spi0.0: Chrome EC device registered
10547 12:39:27.638094 <6>[ 2.008609] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10548 12:39:27.645065 <6>[ 2.021901] mmcblk0: mmc0:0001 DA4128 116 GiB
10549 12:39:27.656521 <6>[ 2.029665] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10550 12:39:27.663105 <6>[ 2.034345] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10551 12:39:27.669474 <6>[ 2.040005] NET: Registered PF_PACKET protocol family
10552 12:39:27.673115 <6>[ 2.045801] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10553 12:39:27.679747 <6>[ 2.050266] 9pnet: Installing 9P2000 support
10554 12:39:27.683038 <6>[ 2.056100] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10555 12:39:27.689355 <5>[ 2.059978] Key type dns_resolver registered
10556 12:39:27.696045 <6>[ 2.065786] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10557 12:39:27.699663 <6>[ 2.070136] registered taskstats version 1
10558 12:39:27.702430 <5>[ 2.080571] Loading compiled-in X.509 certificates
10559 12:39:27.731441 <4>[ 2.101814] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10560 12:39:27.741421 <4>[ 2.112537] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10561 12:39:27.748054 <3>[ 2.123066] debugfs: File 'uA_load' in directory '/' already present!
10562 12:39:27.755039 <3>[ 2.129765] debugfs: File 'min_uV' in directory '/' already present!
10563 12:39:27.761940 <3>[ 2.136373] debugfs: File 'max_uV' in directory '/' already present!
10564 12:39:27.768307 <3>[ 2.143038] debugfs: File 'constraint_flags' in directory '/' already present!
10565 12:39:27.779583 <3>[ 2.152637] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10566 12:39:27.790645 <6>[ 2.167052] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10567 12:39:27.797234 <6>[ 2.173788] xhci-mtk 11200000.usb: xHCI Host Controller
10568 12:39:27.803597 <6>[ 2.179303] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10569 12:39:27.813777 <6>[ 2.187167] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10570 12:39:27.820485 <6>[ 2.196602] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10571 12:39:27.827927 <6>[ 2.202677] xhci-mtk 11200000.usb: xHCI Host Controller
10572 12:39:27.833418 <6>[ 2.208164] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10573 12:39:27.840000 <6>[ 2.215813] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10574 12:39:27.846722 <6>[ 2.223562] hub 1-0:1.0: USB hub found
10575 12:39:27.850249 <6>[ 2.227579] hub 1-0:1.0: 1 port detected
10576 12:39:27.857092 <6>[ 2.231856] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10577 12:39:27.863696 <6>[ 2.240426] hub 2-0:1.0: USB hub found
10578 12:39:27.867314 <6>[ 2.244435] hub 2-0:1.0: 1 port detected
10579 12:39:27.876417 <6>[ 2.252732] mtk-msdc 11f70000.mmc: Got CD GPIO
10580 12:39:27.889130 <6>[ 2.262675] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10581 12:39:27.896327 <6>[ 2.270686] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10582 12:39:27.906525 <4>[ 2.278584] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10583 12:39:27.915966 <6>[ 2.288114] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10584 12:39:27.922801 <6>[ 2.296192] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10585 12:39:27.929205 <6>[ 2.304212] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10586 12:39:27.939078 <6>[ 2.312137] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10587 12:39:27.945744 <6>[ 2.319956] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10588 12:39:27.955829 <6>[ 2.327772] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10589 12:39:27.966023 <6>[ 2.338080] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10590 12:39:27.972508 <6>[ 2.346452] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10591 12:39:27.982116 <6>[ 2.354796] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10592 12:39:27.989056 <6>[ 2.363135] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10593 12:39:27.998543 <6>[ 2.371475] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10594 12:39:28.005745 <6>[ 2.379814] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10595 12:39:28.015640 <6>[ 2.388152] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10596 12:39:28.021857 <6>[ 2.396491] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10597 12:39:28.031835 <6>[ 2.404830] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10598 12:39:28.038536 <6>[ 2.413182] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10599 12:39:28.048366 <6>[ 2.421523] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10600 12:39:28.055014 <6>[ 2.429862] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10601 12:39:28.065095 <6>[ 2.438201] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10602 12:39:28.075377 <6>[ 2.446539] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10603 12:39:28.081110 <6>[ 2.454879] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10604 12:39:28.088049 <6>[ 2.463628] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10605 12:39:28.094588 <6>[ 2.470850] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10606 12:39:28.100830 <6>[ 2.477640] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10607 12:39:28.110826 <6>[ 2.484498] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10608 12:39:28.117363 <6>[ 2.491473] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10609 12:39:28.124248 <6>[ 2.498324] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10610 12:39:28.133816 <6>[ 2.507454] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10611 12:39:28.144726 <6>[ 2.516574] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10612 12:39:28.153825 <6>[ 2.525869] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10613 12:39:28.164187 <6>[ 2.535336] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10614 12:39:28.173626 <6>[ 2.544804] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10615 12:39:28.180573 <6>[ 2.553923] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10616 12:39:28.190258 <6>[ 2.563397] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10617 12:39:28.200508 <6>[ 2.572516] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10618 12:39:28.210106 <6>[ 2.581809] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10619 12:39:28.219816 <6>[ 2.591969] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10620 12:39:28.229955 <6>[ 2.603609] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10621 12:39:28.277838 <6>[ 2.650466] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10622 12:39:28.431838 <6>[ 2.808416] hub 1-1:1.0: USB hub found
10623 12:39:28.435587 <6>[ 2.812926] hub 1-1:1.0: 4 ports detected
10624 12:39:28.444454 <6>[ 2.821537] hub 1-1:1.0: USB hub found
10625 12:39:28.447852 <6>[ 2.825888] hub 1-1:1.0: 4 ports detected
10626 12:39:28.557417 <6>[ 2.930681] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10627 12:39:28.583852 <6>[ 2.960038] hub 2-1:1.0: USB hub found
10628 12:39:28.586755 <6>[ 2.964526] hub 2-1:1.0: 3 ports detected
10629 12:39:28.596580 <6>[ 2.972750] hub 2-1:1.0: USB hub found
10630 12:39:28.599354 <6>[ 2.977203] hub 2-1:1.0: 3 ports detected
10631 12:39:28.773696 <6>[ 3.146360] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10632 12:39:28.904537 <6>[ 3.281437] hub 1-1.4:1.0: USB hub found
10633 12:39:28.908110 <6>[ 3.286034] hub 1-1.4:1.0: 2 ports detected
10634 12:39:28.917409 <6>[ 3.294265] hub 1-1.4:1.0: USB hub found
10635 12:39:28.920601 <6>[ 3.298917] hub 1-1.4:1.0: 2 ports detected
10636 12:39:28.989200 <6>[ 3.362556] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10637 12:39:29.217101 <6>[ 3.590365] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10638 12:39:29.409154 <6>[ 3.782383] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10639 12:39:40.513792 <6>[ 14.895352] ALSA device list:
10640 12:39:40.520622 <6>[ 14.898639] No soundcards found.
10641 12:39:40.528560 <6>[ 14.906647] Freeing unused kernel memory: 8448K
10642 12:39:40.531578 <6>[ 14.911627] Run /init as init process
10643 12:39:40.560806 Starting syslogd: OK
10644 12:39:40.566411 Starting klogd: OK
10645 12:39:40.575322 Running sysctl: OK
10646 12:39:40.581728 Populating /dev using udev: <30>[ 14.961308] udevd[185]: starting version 3.2.9
10647 12:39:40.589885 <27>[ 14.968033] udevd[185]: specified user 'tss' unknown
10648 12:39:40.596687 <27>[ 14.973383] udevd[185]: specified group 'tss' unknown
10649 12:39:40.600077 <30>[ 14.979642] udevd[186]: starting eudev-3.2.9
10650 12:39:40.617526 <27>[ 14.995631] udevd[186]: specified user 'tss' unknown
10651 12:39:40.625026 <27>[ 15.000983] udevd[186]: specified group 'tss' unknown
10652 12:39:40.733089 <6>[ 15.108046] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10653 12:39:40.744482 <6>[ 15.119509] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10654 12:39:40.751369 <6>[ 15.127345] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10655 12:39:40.761520 <6>[ 15.139286] remoteproc remoteproc0: scp is available
10656 12:39:40.770958 <6>[ 15.141431] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10657 12:39:40.774375 <6>[ 15.144690] remoteproc remoteproc0: powering up scp
10658 12:39:40.784378 <6>[ 15.158558] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10659 12:39:40.791308 <3>[ 15.165977] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10660 12:39:40.797938 <6>[ 15.167025] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10661 12:39:40.807521 <3>[ 15.180960] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10662 12:39:40.811806 <6>[ 15.185507] usbcore: registered new device driver r8152-cfgselector
10663 12:39:40.820914 <3>[ 15.189132] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10664 12:39:40.827743 <6>[ 15.204653] mc: Linux media interface: v0.10
10665 12:39:40.833839 <4>[ 15.205212] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10666 12:39:40.840728 <3>[ 15.205645] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10667 12:39:40.850613 <3>[ 15.205671] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10668 12:39:40.857320 <3>[ 15.205687] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10669 12:39:40.867332 <3>[ 15.205706] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10670 12:39:40.874118 <3>[ 15.205714] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10671 12:39:40.880432 <6>[ 15.209938] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10672 12:39:40.890226 <4>[ 15.216740] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10673 12:39:40.897168 <3>[ 15.220728] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10674 12:39:40.907068 <3>[ 15.220798] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10675 12:39:40.913899 <3>[ 15.220802] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10676 12:39:40.920095 <3>[ 15.220805] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10677 12:39:40.930242 <3>[ 15.221057] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10678 12:39:40.937035 <3>[ 15.221062] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10679 12:39:40.946499 <3>[ 15.221066] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10680 12:39:40.953283 <3>[ 15.221070] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10681 12:39:40.963155 <3>[ 15.221073] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10682 12:39:40.969387 <3>[ 15.221094] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10683 12:39:40.979333 <4>[ 15.251459] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10684 12:39:40.983023 <4>[ 15.251459] Fallback method does not support PEC.
10685 12:39:40.989580 <6>[ 15.265424] videodev: Linux video capture interface: v2.00
10686 12:39:40.995875 <6>[ 15.277433] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10687 12:39:41.002280 <6>[ 15.292300] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10688 12:39:41.012260 <6>[ 15.296631] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10689 12:39:41.019091 <6>[ 15.297127] pci_bus 0000:00: root bus resource [bus 00-ff]
10690 12:39:41.025952 <6>[ 15.297133] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10691 12:39:41.035773 <6>[ 15.297136] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10692 12:39:41.043083 <6>[ 15.297165] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10693 12:39:41.048945 <6>[ 15.297178] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10694 12:39:41.052693 <6>[ 15.297243] pci 0000:00:00.0: supports D1 D2
10695 12:39:41.059698 <6>[ 15.297245] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10696 12:39:41.069475 <6>[ 15.298227] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10697 12:39:41.076020 <6>[ 15.298339] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10698 12:39:41.082721 <6>[ 15.298363] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10699 12:39:41.089064 <6>[ 15.298380] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10700 12:39:41.096128 <6>[ 15.298395] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10701 12:39:41.102347 <6>[ 15.298499] pci 0000:01:00.0: supports D1 D2
10702 12:39:41.109194 <6>[ 15.298501] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10703 12:39:41.115355 <6>[ 15.304947] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10704 12:39:41.122101 <6>[ 15.312800] remoteproc remoteproc0: remote processor scp is now up
10705 12:39:41.132307 <6>[ 15.313092] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10706 12:39:41.141917 <6>[ 15.313301] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10707 12:39:41.148594 <6>[ 15.314127] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10708 12:39:41.158651 <6>[ 15.314165] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10709 12:39:41.165409 <6>[ 15.314171] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10710 12:39:41.172001 <6>[ 15.314180] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10711 12:39:41.181546 <6>[ 15.314193] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10712 12:39:41.189051 <6>[ 15.314205] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10713 12:39:41.195554 <6>[ 15.314218] pci 0000:00:00.0: PCI bridge to [bus 01]
10714 12:39:41.201522 <6>[ 15.314224] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10715 12:39:41.208041 <6>[ 15.314360] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10716 12:39:41.214862 <6>[ 15.315056] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10717 12:39:41.221647 <6>[ 15.315244] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10718 12:39:41.231151 <4>[ 15.342303] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10719 12:39:41.237969 <6>[ 15.424470] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10720 12:39:41.247599 <4>[ 15.431690] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10721 12:39:41.251042 <6>[ 15.458599] Bluetooth: Core ver 2.22
10722 12:39:41.261225 <6>[ 15.466425] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10723 12:39:41.267647 <5>[ 15.468982] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10724 12:39:41.274042 <6>[ 15.472896] NET: Registered PF_BLUETOOTH protocol family
10725 12:39:41.280694 <6>[ 15.481883] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10726 12:39:41.287200 <6>[ 15.484428] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10727 12:39:41.297561 <3>[ 15.484805] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10728 12:39:41.303854 <6>[ 15.484896] Bluetooth: HCI device and connection manager initialized
10729 12:39:41.310951 <5>[ 15.489173] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10730 12:39:41.320447 <5>[ 15.489685] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10731 12:39:41.327546 <4>[ 15.489756] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10732 12:39:41.334460 <6>[ 15.489765] cfg80211: failed to load regulatory.db
10733 12:39:41.340481 <6>[ 15.493933] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10734 12:39:41.350158 <6>[ 15.494605] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10735 12:39:41.356691 <6>[ 15.494875] usbcore: registered new interface driver uvcvideo
10736 12:39:41.363574 <6>[ 15.500157] Bluetooth: HCI socket layer initialized
10737 12:39:41.367074 <6>[ 15.522379] r8152 2-1.3:1.0 eth0: v1.12.13
10738 12:39:41.373451 <6>[ 15.525702] Bluetooth: L2CAP socket layer initialized
10739 12:39:41.380508 <6>[ 15.532667] usbcore: registered new interface driver r8152
10740 12:39:41.383203 <6>[ 15.540815] Bluetooth: SCO socket layer initialized
10741 12:39:41.389557 <6>[ 15.578369] usbcore: registered new interface driver cdc_ether
10742 12:39:41.396838 <6>[ 15.584070] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10743 12:39:41.402948 <6>[ 15.584171] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10744 12:39:41.409255 <6>[ 15.602247] mt7921e 0000:01:00.0: ASIC revision: 79610010
10745 12:39:41.416653 <6>[ 15.613784] usbcore: registered new interface driver r8153_ecm
10746 12:39:41.419181 <6>[ 15.631398] usbcore: registered new interface driver btusb
10747 12:39:41.432661 <4>[ 15.635392] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10748 12:39:41.438990 <6>[ 15.716974] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10749 12:39:41.442587 <6>[ 15.716974]
10750 12:39:41.446168 <3>[ 15.722682] Bluetooth: hci0: Failed to load firmware file (-2)
10751 12:39:41.449904 done
10752 12:39:41.455636 Saving ran<3>[ 15.830552] Bluetooth: hci0: Failed to set up firmware (-2)
10753 12:39:41.465839 <4>[ 15.837803] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10754 12:39:41.465966 dom seed: OK
10755 12:39:41.468587 Starting network: OK
10756 12:39:41.488696 Starting dropbear sshd: <3>[ 15.862921] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10757 12:39:41.498946 <6>[ 15.877233] NET: Registered PF_INET6 protocol family
10758 12:39:41.506020 <6>[ 15.884032] Segment Routing with IPv6
10759 12:39:41.509506 <6>[ 15.887971] In-situ OAM (IOAM) with IPv6
10760 12:39:41.513398 OK
10761 12:39:41.523069 /bin/sh: can't access tty; job control turned off
10762 12:39:41.523458 Matched prompt #10: / #
10764 12:39:41.523681 Setting prompt string to ['/ #']
10765 12:39:41.523773 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10767 12:39:41.523967 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10768 12:39:41.524061 start: 2.2.6 expect-shell-connection (timeout 00:03:16) [common]
10769 12:39:41.524134 Setting prompt string to ['/ #']
10770 12:39:41.524193 Forcing a shell prompt, looking for ['/ #']
10772 12:39:41.574428 / #
10773 12:39:41.574613 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10774 12:39:41.574695 Waiting using forced prompt support (timeout 00:02:30)
10775 12:39:41.580423
10776 12:39:41.580722 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10777 12:39:41.580823 start: 2.2.7 export-device-env (timeout 00:03:16) [common]
10778 12:39:41.580916 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10779 12:39:41.581005 end: 2.2 depthcharge-retry (duration 00:01:44) [common]
10780 12:39:41.581088 end: 2 depthcharge-action (duration 00:01:44) [common]
10781 12:39:41.581180 start: 3 lava-test-retry (timeout 00:01:00) [common]
10782 12:39:41.581266 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10783 12:39:41.581340 Using namespace: common
10785 12:39:41.681711 / # #
10786 12:39:41.681872 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10787 12:39:41.682004 <6>[ 15.997015] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10788 12:39:41.687732 #
10789 12:39:41.688027 Using /lava-12703560
10791 12:39:41.788413 / # export SHELL=/bin/sh
10792 12:39:41.794080 export SHELL=/bin/sh
10794 12:39:41.894690 / # . /lava-12703560/environment
10795 12:39:41.900156 . /lava-12703560/environment
10797 12:39:42.000776 / # /lava-12703560/bin/lava-test-runner /lava-12703560/0
10798 12:39:42.000961 Test shell timeout: 10s (minimum of the action and connection timeout)
10799 12:39:42.006772 /lava-12703560/bin/lava-test-runner /lava-12703560/0
10800 12:39:42.026625 + export 'TESTRUN_ID=0_dmesg'
10801 12:39:42.033275 +<8>[ 16.410000] <LAVA_SIGNAL_STARTRUN 0_dmesg 12703560_1.5.2.3.1>
10802 12:39:42.033568 Received signal: <STARTRUN> 0_dmesg 12703560_1.5.2.3.1
10803 12:39:42.033648 Starting test lava.0_dmesg (12703560_1.5.2.3.1)
10804 12:39:42.033733 Skipping test definition patterns.
10805 12:39:42.036619 cd /lava-12703560/0/tests/0_dmesg
10806 12:39:42.036703 + cat uuid
10807 12:39:42.039551 + UUID=12703560_1.5.2.3.1
10808 12:39:42.039637 + set +x
10809 12:39:42.046533 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10810 12:39:42.052944 <8>[ 16.428365] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10811 12:39:42.053244 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10813 12:39:42.075323 <8>[ 16.449787] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10814 12:39:42.075684 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10816 12:39:42.094663 <8>[ 16.469226] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10817 12:39:42.094988 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10819 12:39:42.097430 + set +x
10820 12:39:42.100948 <8>[ 16.478898] <LAVA_SIGNAL_ENDRUN 0_dmesg 12703560_1.5.2.3.1>
10821 12:39:42.101211 Received signal: <ENDRUN> 0_dmesg 12703560_1.5.2.3.1
10822 12:39:42.101299 Ending use of test pattern.
10823 12:39:42.101361 Ending test lava.0_dmesg (12703560_1.5.2.3.1), duration 0.07
10825 12:39:42.105779 <LAVA_TEST_RUNNER EXIT>
10826 12:39:42.106040 ok: lava_test_shell seems to have completed
10827 12:39:42.106148 alert: pass
crit: pass
emerg: pass
10828 12:39:42.106237 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10829 12:39:42.106320 end: 3 lava-test-retry (duration 00:00:01) [common]
10830 12:39:42.106408 start: 4 lava-test-retry (timeout 00:01:00) [common]
10831 12:39:42.106489 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10832 12:39:42.106552 Using namespace: common
10834 12:39:42.206932 / # #
10835 12:39:42.207119 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10836 12:39:42.207252 Using /lava-12703560
10838 12:39:42.307662 export SHELL=/bin/sh
10839 12:39:42.307865 #
10841 12:39:42.408460 / # export SHELL=/bin/sh. /lava-12703560/environment
10842 12:39:42.408646
10844 12:39:42.509230 / # . /lava-12703560/environment/lava-12703560/bin/lava-test-runner /lava-12703560/1
10845 12:39:42.509409 Test shell timeout: 10s (minimum of the action and connection timeout)
10846 12:39:42.509531
10847 12:39:42.509599 / # <6>[ 16.845016] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10848 12:39:42.509661 <4>[ 16.851060] ttyS ttyS0: 1 input overrun(s)
10849 12:39:42.514671 /lava-12703560/bin/lava-test-run
10850 12:39:42.555622 /bin/sh: /lava-12703560/bin/lava-test-run: not found
10851 12:40:11.773882 / # <6>[ 46.158529] vpu: disabling
10852 12:40:11.776745 <6>[ 46.161601] vproc2: disabling
10853 12:40:11.779951 <6>[ 46.164883] vproc1: disabling
10854 12:40:11.783788 <6>[ 46.168145] vaud18: disabling
10855 12:40:11.789724 <6>[ 46.171562] vsram_others: disabling
10856 12:40:11.793462 <6>[ 46.175500] va09: disabling
10857 12:40:11.796784 <6>[ 46.178663] vsram_md: disabling
10858 12:40:11.800356 <6>[ 46.182216] Vgpu: disabling
10860 12:40:42.106773 end: 4.1 lava-test-shell (duration 00:01:00) [common]
10862 12:40:42.106957 lava-test-retry failed: 1 of 5 attempts. 'lava-test-shell timed out after 60 seconds'
10864 12:40:42.107107 end: 4 lava-test-retry (duration 00:01:00) [common]
10866 12:40:42.107330 Cleaning after the job
10867 12:40:42.107459 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703560/tftp-deploy-ggnh9y3q/ramdisk
10868 12:40:42.110407 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703560/tftp-deploy-ggnh9y3q/kernel
10869 12:40:42.123608 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703560/tftp-deploy-ggnh9y3q/dtb
10870 12:40:42.123798 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703560/tftp-deploy-ggnh9y3q/modules
10871 12:40:42.130865 start: 5.1 power-off (timeout 00:00:30) [common]
10872 12:40:42.131033 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
10873 12:40:42.210125 >> Command sent successfully.
10874 12:40:42.212472 Returned 0 in 0 seconds
10875 12:40:42.312857 end: 5.1 power-off (duration 00:00:00) [common]
10877 12:40:42.313207 start: 5.2 read-feedback (timeout 00:10:00) [common]
10878 12:40:42.313458 Listened to connection for namespace 'common' for up to 1s
10879 12:40:43.314408 Finalising connection for namespace 'common'
10880 12:40:43.314583 Disconnecting from shell: Finalise
10881 12:40:43.414936 end: 5.2 read-feedback (duration 00:00:01) [common]
10882 12:40:43.415100 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12703560
10883 12:40:43.462554 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12703560
10884 12:40:43.462737 TestError: A test failed to run, look at the error message.