Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 1
- Kernel Warnings: 13
- Kernel Errors: 32
1 12:43:24.624921 lava-dispatcher, installed at version: 2024.01
2 12:43:24.625141 start: 0 validate
3 12:43:24.625283 Start time: 2024-02-05 12:43:24.625274+00:00 (UTC)
4 12:43:24.625421 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:43:24.625554 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 12:43:24.905922 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:43:24.906103 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:43:25.176650 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:43:25.176833 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:43:25.444142 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:43:25.444333 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:43:25.710714 validate duration: 1.09
14 12:43:25.711007 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:43:25.711109 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:43:25.711196 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:43:25.711318 Not decompressing ramdisk as can be used compressed.
18 12:43:25.711401 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 12:43:25.711464 saving as /var/lib/lava/dispatcher/tmp/12703582/tftp-deploy-afe2j7qq/ramdisk/rootfs.cpio.gz
20 12:43:25.711526 total size: 34390042 (32 MB)
21 12:43:25.712563 progress 0 % (0 MB)
22 12:43:25.721592 progress 5 % (1 MB)
23 12:43:25.730348 progress 10 % (3 MB)
24 12:43:25.739218 progress 15 % (4 MB)
25 12:43:25.748265 progress 20 % (6 MB)
26 12:43:25.757383 progress 25 % (8 MB)
27 12:43:25.766703 progress 30 % (9 MB)
28 12:43:25.775610 progress 35 % (11 MB)
29 12:43:25.784333 progress 40 % (13 MB)
30 12:43:25.793539 progress 45 % (14 MB)
31 12:43:25.802262 progress 50 % (16 MB)
32 12:43:25.811166 progress 55 % (18 MB)
33 12:43:25.820130 progress 60 % (19 MB)
34 12:43:25.829033 progress 65 % (21 MB)
35 12:43:25.837765 progress 70 % (22 MB)
36 12:43:25.846851 progress 75 % (24 MB)
37 12:43:25.855767 progress 80 % (26 MB)
38 12:43:25.864887 progress 85 % (27 MB)
39 12:43:25.873860 progress 90 % (29 MB)
40 12:43:25.882690 progress 95 % (31 MB)
41 12:43:25.891527 progress 100 % (32 MB)
42 12:43:25.891729 32 MB downloaded in 0.18 s (182.00 MB/s)
43 12:43:25.891891 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:43:25.892137 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:43:25.892223 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:43:25.892308 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:43:25.892445 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:43:25.892513 saving as /var/lib/lava/dispatcher/tmp/12703582/tftp-deploy-afe2j7qq/kernel/Image
50 12:43:25.892574 total size: 51534336 (49 MB)
51 12:43:25.892634 No compression specified
52 12:43:25.893830 progress 0 % (0 MB)
53 12:43:25.907178 progress 5 % (2 MB)
54 12:43:25.920501 progress 10 % (4 MB)
55 12:43:25.933696 progress 15 % (7 MB)
56 12:43:25.947197 progress 20 % (9 MB)
57 12:43:25.960651 progress 25 % (12 MB)
58 12:43:25.974105 progress 30 % (14 MB)
59 12:43:25.987592 progress 35 % (17 MB)
60 12:43:26.001196 progress 40 % (19 MB)
61 12:43:26.014654 progress 45 % (22 MB)
62 12:43:26.028137 progress 50 % (24 MB)
63 12:43:26.041748 progress 55 % (27 MB)
64 12:43:26.055385 progress 60 % (29 MB)
65 12:43:26.069032 progress 65 % (31 MB)
66 12:43:26.082341 progress 70 % (34 MB)
67 12:43:26.095698 progress 75 % (36 MB)
68 12:43:26.109056 progress 80 % (39 MB)
69 12:43:26.122204 progress 85 % (41 MB)
70 12:43:26.135760 progress 90 % (44 MB)
71 12:43:26.149577 progress 95 % (46 MB)
72 12:43:26.162875 progress 100 % (49 MB)
73 12:43:26.163143 49 MB downloaded in 0.27 s (181.65 MB/s)
74 12:43:26.163301 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:43:26.163535 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:43:26.163627 start: 1.3 download-retry (timeout 00:10:00) [common]
78 12:43:26.163713 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 12:43:26.163857 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:43:26.163937 saving as /var/lib/lava/dispatcher/tmp/12703582/tftp-deploy-afe2j7qq/dtb/mt8192-asurada-spherion-r0.dtb
81 12:43:26.164001 total size: 47278 (0 MB)
82 12:43:26.164064 No compression specified
83 12:43:26.165272 progress 69 % (0 MB)
84 12:43:26.165559 progress 100 % (0 MB)
85 12:43:26.165718 0 MB downloaded in 0.00 s (26.30 MB/s)
86 12:43:26.165880 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:43:26.166104 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:43:26.166189 start: 1.4 download-retry (timeout 00:10:00) [common]
90 12:43:26.166272 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 12:43:26.166388 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:43:26.166455 saving as /var/lib/lava/dispatcher/tmp/12703582/tftp-deploy-afe2j7qq/modules/modules.tar
93 12:43:26.166515 total size: 8639964 (8 MB)
94 12:43:26.166576 Using unxz to decompress xz
95 12:43:26.170926 progress 0 % (0 MB)
96 12:43:26.191762 progress 5 % (0 MB)
97 12:43:26.214978 progress 10 % (0 MB)
98 12:43:26.238415 progress 15 % (1 MB)
99 12:43:26.262230 progress 20 % (1 MB)
100 12:43:26.286315 progress 25 % (2 MB)
101 12:43:26.313562 progress 30 % (2 MB)
102 12:43:26.337595 progress 35 % (2 MB)
103 12:43:26.361120 progress 40 % (3 MB)
104 12:43:26.385729 progress 45 % (3 MB)
105 12:43:26.411021 progress 50 % (4 MB)
106 12:43:26.436866 progress 55 % (4 MB)
107 12:43:26.461753 progress 60 % (4 MB)
108 12:43:26.487532 progress 65 % (5 MB)
109 12:43:26.512523 progress 70 % (5 MB)
110 12:43:26.535868 progress 75 % (6 MB)
111 12:43:26.562854 progress 80 % (6 MB)
112 12:43:26.590482 progress 85 % (7 MB)
113 12:43:26.615292 progress 90 % (7 MB)
114 12:43:26.645105 progress 95 % (7 MB)
115 12:43:26.673150 progress 100 % (8 MB)
116 12:43:26.678980 8 MB downloaded in 0.51 s (16.08 MB/s)
117 12:43:26.679239 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:43:26.679508 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:43:26.679604 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:43:26.679701 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:43:26.679783 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:43:26.679876 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:43:26.680103 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r
125 12:43:26.680239 makedir: /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r/lava-12703582/bin
126 12:43:26.680344 makedir: /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r/lava-12703582/tests
127 12:43:26.680445 makedir: /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r/lava-12703582/results
128 12:43:26.680561 Creating /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r/lava-12703582/bin/lava-add-keys
129 12:43:26.680723 Creating /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r/lava-12703582/bin/lava-add-sources
130 12:43:26.680856 Creating /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r/lava-12703582/bin/lava-background-process-start
131 12:43:26.680990 Creating /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r/lava-12703582/bin/lava-background-process-stop
132 12:43:26.681120 Creating /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r/lava-12703582/bin/lava-common-functions
133 12:43:26.681248 Creating /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r/lava-12703582/bin/lava-echo-ipv4
134 12:43:26.681375 Creating /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r/lava-12703582/bin/lava-install-packages
135 12:43:26.681501 Creating /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r/lava-12703582/bin/lava-installed-packages
136 12:43:26.681627 Creating /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r/lava-12703582/bin/lava-os-build
137 12:43:26.681753 Creating /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r/lava-12703582/bin/lava-probe-channel
138 12:43:26.681885 Creating /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r/lava-12703582/bin/lava-probe-ip
139 12:43:26.682013 Creating /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r/lava-12703582/bin/lava-target-ip
140 12:43:26.682139 Creating /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r/lava-12703582/bin/lava-target-mac
141 12:43:26.682267 Creating /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r/lava-12703582/bin/lava-target-storage
142 12:43:26.682399 Creating /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r/lava-12703582/bin/lava-test-case
143 12:43:26.682526 Creating /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r/lava-12703582/bin/lava-test-event
144 12:43:26.682657 Creating /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r/lava-12703582/bin/lava-test-feedback
145 12:43:26.682783 Creating /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r/lava-12703582/bin/lava-test-raise
146 12:43:26.682911 Creating /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r/lava-12703582/bin/lava-test-reference
147 12:43:26.683037 Creating /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r/lava-12703582/bin/lava-test-runner
148 12:43:26.683164 Creating /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r/lava-12703582/bin/lava-test-set
149 12:43:26.683293 Creating /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r/lava-12703582/bin/lava-test-shell
150 12:43:26.683424 Updating /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r/lava-12703582/bin/lava-install-packages (oe)
151 12:43:26.683579 Updating /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r/lava-12703582/bin/lava-installed-packages (oe)
152 12:43:26.683705 Creating /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r/lava-12703582/environment
153 12:43:26.683807 LAVA metadata
154 12:43:26.683884 - LAVA_JOB_ID=12703582
155 12:43:26.683948 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:43:26.684051 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:43:26.684120 skipped lava-vland-overlay
158 12:43:26.684194 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:43:26.684280 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:43:26.684342 skipped lava-multinode-overlay
161 12:43:26.684415 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:43:26.684499 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:43:26.684572 Loading test definitions
164 12:43:26.684673 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:43:26.684760 Using /lava-12703582 at stage 0
166 12:43:26.685069 uuid=12703582_1.5.2.3.1 testdef=None
167 12:43:26.685157 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:43:26.685247 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:43:26.685772 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:43:26.685988 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:43:26.686604 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:43:26.686836 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:43:26.687897 runner path: /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r/lava-12703582/0/tests/0_cros-ec test_uuid 12703582_1.5.2.3.1
176 12:43:26.688053 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:43:26.688257 Creating lava-test-runner.conf files
179 12:43:26.688320 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12703582/lava-overlay-8c1dfn5r/lava-12703582/0 for stage 0
180 12:43:26.688411 - 0_cros-ec
181 12:43:26.688508 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:43:26.688593 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 12:43:26.695824 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:43:26.695932 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 12:43:26.696020 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:43:26.696106 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:43:26.696193 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 12:43:27.685814 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:43:27.686225 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 12:43:27.686345 extracting modules file /var/lib/lava/dispatcher/tmp/12703582/tftp-deploy-afe2j7qq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12703582/extract-overlay-ramdisk-ijx2hmk7/ramdisk
191 12:43:27.916125 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:43:27.916304 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 12:43:27.916403 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12703582/compress-overlay-ub8oy9qe/overlay-1.5.2.4.tar.gz to ramdisk
194 12:43:27.916506 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12703582/compress-overlay-ub8oy9qe/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12703582/extract-overlay-ramdisk-ijx2hmk7/ramdisk
195 12:43:27.923533 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:43:27.923662 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 12:43:27.923756 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:43:27.923849 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 12:43:27.923926 Building ramdisk /var/lib/lava/dispatcher/tmp/12703582/extract-overlay-ramdisk-ijx2hmk7/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12703582/extract-overlay-ramdisk-ijx2hmk7/ramdisk
200 12:43:28.666727 >> 271099 blocks
201 12:43:33.410226 rename /var/lib/lava/dispatcher/tmp/12703582/extract-overlay-ramdisk-ijx2hmk7/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12703582/tftp-deploy-afe2j7qq/ramdisk/ramdisk.cpio.gz
202 12:43:33.410668 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 12:43:33.410790 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 12:43:33.410888 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 12:43:33.411003 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12703582/tftp-deploy-afe2j7qq/kernel/Image'
206 12:43:46.220248 Returned 0 in 12 seconds
207 12:43:46.320865 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12703582/tftp-deploy-afe2j7qq/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12703582/tftp-deploy-afe2j7qq/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12703582/tftp-deploy-afe2j7qq/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12703582/tftp-deploy-afe2j7qq/kernel/image.itb
208 12:43:47.062659 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:43:47.063044 output: Created: Mon Feb 5 12:43:46 2024
210 12:43:47.063123 output: Image 0 (kernel-1)
211 12:43:47.063190 output: Description:
212 12:43:47.063260 output: Created: Mon Feb 5 12:43:46 2024
213 12:43:47.063339 output: Type: Kernel Image
214 12:43:47.063402 output: Compression: lzma compressed
215 12:43:47.063462 output: Data Size: 12052857 Bytes = 11770.37 KiB = 11.49 MiB
216 12:43:47.063522 output: Architecture: AArch64
217 12:43:47.063578 output: OS: Linux
218 12:43:47.063633 output: Load Address: 0x00000000
219 12:43:47.063689 output: Entry Point: 0x00000000
220 12:43:47.063743 output: Hash algo: crc32
221 12:43:47.063801 output: Hash value: 8a14336a
222 12:43:47.063857 output: Image 1 (fdt-1)
223 12:43:47.063914 output: Description: mt8192-asurada-spherion-r0
224 12:43:47.063970 output: Created: Mon Feb 5 12:43:46 2024
225 12:43:47.064024 output: Type: Flat Device Tree
226 12:43:47.064078 output: Compression: uncompressed
227 12:43:47.064131 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 12:43:47.064185 output: Architecture: AArch64
229 12:43:47.064238 output: Hash algo: crc32
230 12:43:47.064292 output: Hash value: cc4352de
231 12:43:47.064344 output: Image 2 (ramdisk-1)
232 12:43:47.064397 output: Description: unavailable
233 12:43:47.064450 output: Created: Mon Feb 5 12:43:46 2024
234 12:43:47.064504 output: Type: RAMDisk Image
235 12:43:47.064557 output: Compression: Unknown Compression
236 12:43:47.064610 output: Data Size: 47540031 Bytes = 46425.81 KiB = 45.34 MiB
237 12:43:47.064663 output: Architecture: AArch64
238 12:43:47.064725 output: OS: Linux
239 12:43:47.064781 output: Load Address: unavailable
240 12:43:47.064834 output: Entry Point: unavailable
241 12:43:47.064887 output: Hash algo: crc32
242 12:43:47.064940 output: Hash value: 667fcecb
243 12:43:47.064993 output: Default Configuration: 'conf-1'
244 12:43:47.065046 output: Configuration 0 (conf-1)
245 12:43:47.065099 output: Description: mt8192-asurada-spherion-r0
246 12:43:47.065151 output: Kernel: kernel-1
247 12:43:47.065204 output: Init Ramdisk: ramdisk-1
248 12:43:47.065256 output: FDT: fdt-1
249 12:43:47.065309 output: Loadables: kernel-1
250 12:43:47.065361 output:
251 12:43:47.065567 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 12:43:47.065668 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 12:43:47.065769 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 12:43:47.065866 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 12:43:47.065954 No LXC device requested
256 12:43:47.066037 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:43:47.066122 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 12:43:47.066201 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:43:47.066272 Checking files for TFTP limit of 4294967296 bytes.
260 12:43:47.066779 end: 1 tftp-deploy (duration 00:00:21) [common]
261 12:43:47.066881 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:43:47.066978 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:43:47.067105 substitutions:
264 12:43:47.067172 - {DTB}: 12703582/tftp-deploy-afe2j7qq/dtb/mt8192-asurada-spherion-r0.dtb
265 12:43:47.067238 - {INITRD}: 12703582/tftp-deploy-afe2j7qq/ramdisk/ramdisk.cpio.gz
266 12:43:47.067298 - {KERNEL}: 12703582/tftp-deploy-afe2j7qq/kernel/Image
267 12:43:47.067356 - {LAVA_MAC}: None
268 12:43:47.067412 - {PRESEED_CONFIG}: None
269 12:43:47.067467 - {PRESEED_LOCAL}: None
270 12:43:47.067522 - {RAMDISK}: 12703582/tftp-deploy-afe2j7qq/ramdisk/ramdisk.cpio.gz
271 12:43:47.067577 - {ROOT_PART}: None
272 12:43:47.067634 - {ROOT}: None
273 12:43:47.067690 - {SERVER_IP}: 192.168.201.1
274 12:43:47.067745 - {TEE}: None
275 12:43:47.067799 Parsed boot commands:
276 12:43:47.067853 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:43:47.068031 Parsed boot commands: tftpboot 192.168.201.1 12703582/tftp-deploy-afe2j7qq/kernel/image.itb 12703582/tftp-deploy-afe2j7qq/kernel/cmdline
278 12:43:47.068120 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:43:47.068206 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:43:47.068309 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:43:47.068398 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:43:47.068473 Not connected, no need to disconnect.
283 12:43:47.068547 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:43:47.068630 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:43:47.068698 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 12:43:47.072777 Setting prompt string to ['lava-test: # ']
287 12:43:47.073159 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:43:47.073270 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:43:47.073374 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:43:47.073463 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:43:47.073697 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
292 12:43:52.220117 >> Command sent successfully.
293 12:43:52.230679 Returned 0 in 5 seconds
294 12:43:52.331544 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:43:52.331857 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:43:52.331959 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:43:52.332048 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:43:52.332117 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:43:52.332187 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:43:52.332453 [Enter `^Ec?' for help]
302 12:43:52.505611
303 12:43:52.505750
304 12:43:52.505820 F0: 102B 0000
305 12:43:52.505883
306 12:43:52.505946 F3: 1001 0000 [0200]
307 12:43:52.508421
308 12:43:52.508505 F3: 1001 0000
309 12:43:52.508572
310 12:43:52.508634 F7: 102D 0000
311 12:43:52.508693
312 12:43:52.512144 F1: 0000 0000
313 12:43:52.512227
314 12:43:52.512311 V0: 0000 0000 [0001]
315 12:43:52.512374
316 12:43:52.512434 00: 0007 8000
317 12:43:52.512498
318 12:43:52.515970 01: 0000 0000
319 12:43:52.516054
320 12:43:52.516119 BP: 0C00 0209 [0000]
321 12:43:52.516181
322 12:43:52.519529 G0: 1182 0000
323 12:43:52.519611
324 12:43:52.519677 EC: 0000 0021 [4000]
325 12:43:52.519737
326 12:43:52.523250 S7: 0000 0000 [0000]
327 12:43:52.523332
328 12:43:52.523397 CC: 0000 0000 [0001]
329 12:43:52.523458
330 12:43:52.526291 T0: 0000 0040 [010F]
331 12:43:52.526374
332 12:43:52.526476 Jump to BL
333 12:43:52.526537
334 12:43:52.552083
335 12:43:52.552169
336 12:43:52.552235
337 12:43:52.559127 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:43:52.563110 ARM64: Exception handlers installed.
339 12:43:52.566292 ARM64: Testing exception
340 12:43:52.569371 ARM64: Done test exception
341 12:43:52.575822 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:43:52.586162 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:43:52.592383 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:43:52.602613 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:43:52.609595 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:43:52.620149 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:43:52.629668 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:43:52.636191 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:43:52.655012 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:43:52.657981 WDT: Last reset was cold boot
351 12:43:52.661375 SPI1(PAD0) initialized at 2873684 Hz
352 12:43:52.664998 SPI5(PAD0) initialized at 992727 Hz
353 12:43:52.667731 VBOOT: Loading verstage.
354 12:43:52.674430 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:43:52.677936 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:43:52.681020 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:43:52.684692 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:43:52.691837 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:43:52.698707 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:43:52.710045 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 12:43:52.710130
362 12:43:52.710197
363 12:43:52.719256 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:43:52.722948 ARM64: Exception handlers installed.
365 12:43:52.726254 ARM64: Testing exception
366 12:43:52.726337 ARM64: Done test exception
367 12:43:52.732739 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:43:52.736606 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:43:52.750749 Probing TPM: . done!
370 12:43:52.750832 TPM ready after 0 ms
371 12:43:52.757235 Connected to device vid:did:rid of 1ae0:0028:00
372 12:43:52.764411 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
373 12:43:52.805825 Initialized TPM device CR50 revision 0
374 12:43:52.817621 tlcl_send_startup: Startup return code is 0
375 12:43:52.817708 TPM: setup succeeded
376 12:43:52.829644 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:43:52.838373 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:43:52.848501 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:43:52.857700 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:43:52.860940 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:43:52.865163 in-header: 03 07 00 00 08 00 00 00
382 12:43:52.867558 in-data: aa e4 47 04 13 02 00 00
383 12:43:52.870823 Chrome EC: UHEPI supported
384 12:43:52.877474 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:43:52.880578 in-header: 03 9d 00 00 08 00 00 00
386 12:43:52.883578 in-data: 10 20 20 08 00 00 00 00
387 12:43:52.883661 Phase 1
388 12:43:52.886880 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:43:52.893667 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:43:52.900519 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:43:52.904105 Recovery requested (1009000e)
392 12:43:52.910466 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:43:52.917485 tlcl_extend: response is 0
394 12:43:52.924053 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:43:52.929432 tlcl_extend: response is 0
396 12:43:52.936009 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:43:52.957079 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 12:43:52.964175 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 12:43:52.964258
400 12:43:52.964324
401 12:43:52.973768 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:43:52.976810 ARM64: Exception handlers installed.
403 12:43:52.979993 ARM64: Testing exception
404 12:43:52.980076 ARM64: Done test exception
405 12:43:53.003474 pmic_efuse_setting: Set efuses in 11 msecs
406 12:43:53.006022 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:43:53.013372 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:43:53.016326 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:43:53.023440 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:43:53.026607 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:43:53.030498 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:43:53.033896 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:43:53.041992 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:43:53.046043 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:43:53.051989 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:43:53.054481 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:43:53.060998 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:43:53.064298 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:43:53.068165 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:43:53.075299 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:43:53.081320 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:43:53.084469 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:43:53.091217 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:43:53.098359 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:43:53.105049 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:43:53.107661 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:43:53.114414 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:43:53.121984 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:43:53.124511 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:43:53.130968 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:43:53.134858 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:43:53.141125 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:43:53.149731 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:43:53.151162 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:43:53.158283 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:43:53.161176 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:43:53.168009 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:43:53.171299 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:43:53.177746 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:43:53.181236 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:43:53.184965 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:43:53.191121 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:43:53.198127 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:43:53.201755 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:43:53.204286 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:43:53.211223 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:43:53.214511 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:43:53.217605 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:43:53.224594 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:43:53.228647 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:43:53.231007 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:43:53.237520 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:43:53.241690 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:43:53.244263 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:43:53.248450 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:43:53.255183 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:43:53.258108 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:43:53.264764 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:43:53.274563 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:43:53.279172 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:43:53.287454 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:43:53.294283 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:43:53.300697 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:43:53.304892 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:43:53.307620 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:43:53.316178 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 12:43:53.321577 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:43:53.325288 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 12:43:53.328135 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:43:53.339547 [RTC]rtc_get_frequency_meter,154: input=15, output=763
471 12:43:53.348903 [RTC]rtc_get_frequency_meter,154: input=23, output=948
472 12:43:53.358606 [RTC]rtc_get_frequency_meter,154: input=19, output=857
473 12:43:53.368721 [RTC]rtc_get_frequency_meter,154: input=17, output=810
474 12:43:53.377772 [RTC]rtc_get_frequency_meter,154: input=16, output=788
475 12:43:53.387532 [RTC]rtc_get_frequency_meter,154: input=16, output=787
476 12:43:53.396930 [RTC]rtc_get_frequency_meter,154: input=17, output=810
477 12:43:53.402017 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 12:43:53.407332 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 12:43:53.410500 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 12:43:53.413890 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 12:43:53.420402 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 12:43:53.423768 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 12:43:53.427091 ADC[4]: Raw value=670432 ID=5
484 12:43:53.427173 ADC[3]: Raw value=212549 ID=1
485 12:43:53.431208 RAM Code: 0x51
486 12:43:53.435618 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 12:43:53.440582 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 12:43:53.447120 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
489 12:43:53.454218 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
490 12:43:53.457224 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 12:43:53.460426 in-header: 03 07 00 00 08 00 00 00
492 12:43:53.463996 in-data: aa e4 47 04 13 02 00 00
493 12:43:53.467733 Chrome EC: UHEPI supported
494 12:43:53.475559 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 12:43:53.477920 in-header: 03 d5 00 00 08 00 00 00
496 12:43:53.480433 in-data: 98 20 60 08 00 00 00 00
497 12:43:53.483959 MRC: failed to locate region type 0.
498 12:43:53.487620 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 12:43:53.491001 DRAM-K: Running full calibration
500 12:43:53.497143 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
501 12:43:53.500928 header.status = 0x0
502 12:43:53.504402 header.version = 0x6 (expected: 0x6)
503 12:43:53.508176 header.size = 0xd00 (expected: 0xd00)
504 12:43:53.508259 header.flags = 0x0
505 12:43:53.514209 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 12:43:53.531627 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 12:43:53.538168 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 12:43:53.541772 dram_init: ddr_geometry: 0
509 12:43:53.545139 [EMI] MDL number = 0
510 12:43:53.545221 [EMI] Get MDL freq = 0
511 12:43:53.548457 dram_init: ddr_type: 0
512 12:43:53.548539 is_discrete_lpddr4: 1
513 12:43:53.552107 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 12:43:53.552189
515 12:43:53.552254
516 12:43:53.555785 [Bian_co] ETT version 0.0.0.1
517 12:43:53.559327 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
518 12:43:53.559418
519 12:43:53.565527 dramc_set_vcore_voltage set vcore to 650000
520 12:43:53.565610 Read voltage for 800, 4
521 12:43:53.569046 Vio18 = 0
522 12:43:53.569129 Vcore = 650000
523 12:43:53.569194 Vdram = 0
524 12:43:53.572320 Vddq = 0
525 12:43:53.572402 Vmddr = 0
526 12:43:53.576122 dram_init: config_dvfs: 1
527 12:43:53.579633 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 12:43:53.586233 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 12:43:53.589232 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 12:43:53.592262 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 12:43:53.596333 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 12:43:53.599374 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 12:43:53.602302 MEM_TYPE=3, freq_sel=18
534 12:43:53.605853 sv_algorithm_assistance_LP4_1600
535 12:43:53.609455 ============ PULL DRAM RESETB DOWN ============
536 12:43:53.612910 ========== PULL DRAM RESETB DOWN end =========
537 12:43:53.619095 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 12:43:53.622701 ===================================
539 12:43:53.622784 LPDDR4 DRAM CONFIGURATION
540 12:43:53.626482 ===================================
541 12:43:53.629012 EX_ROW_EN[0] = 0x0
542 12:43:53.629094 EX_ROW_EN[1] = 0x0
543 12:43:53.632548 LP4Y_EN = 0x0
544 12:43:53.632630 WORK_FSP = 0x0
545 12:43:53.635878 WL = 0x2
546 12:43:53.635960 RL = 0x2
547 12:43:53.639269 BL = 0x2
548 12:43:53.642784 RPST = 0x0
549 12:43:53.642866 RD_PRE = 0x0
550 12:43:53.646383 WR_PRE = 0x1
551 12:43:53.646466 WR_PST = 0x0
552 12:43:53.649631 DBI_WR = 0x0
553 12:43:53.649714 DBI_RD = 0x0
554 12:43:53.652466 OTF = 0x1
555 12:43:53.656080 ===================================
556 12:43:53.659200 ===================================
557 12:43:53.659283 ANA top config
558 12:43:53.662846 ===================================
559 12:43:53.665989 DLL_ASYNC_EN = 0
560 12:43:53.669402 ALL_SLAVE_EN = 1
561 12:43:53.669485 NEW_RANK_MODE = 1
562 12:43:53.672514 DLL_IDLE_MODE = 1
563 12:43:53.676122 LP45_APHY_COMB_EN = 1
564 12:43:53.678867 TX_ODT_DIS = 1
565 12:43:53.678950 NEW_8X_MODE = 1
566 12:43:53.682120 ===================================
567 12:43:53.686812 ===================================
568 12:43:53.689079 data_rate = 1600
569 12:43:53.692354 CKR = 1
570 12:43:53.695920 DQ_P2S_RATIO = 8
571 12:43:53.698924 ===================================
572 12:43:53.703738 CA_P2S_RATIO = 8
573 12:43:53.706094 DQ_CA_OPEN = 0
574 12:43:53.706178 DQ_SEMI_OPEN = 0
575 12:43:53.708885 CA_SEMI_OPEN = 0
576 12:43:53.712783 CA_FULL_RATE = 0
577 12:43:53.715512 DQ_CKDIV4_EN = 1
578 12:43:53.718845 CA_CKDIV4_EN = 1
579 12:43:53.722423 CA_PREDIV_EN = 0
580 12:43:53.722506 PH8_DLY = 0
581 12:43:53.725822 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 12:43:53.728880 DQ_AAMCK_DIV = 4
583 12:43:53.732306 CA_AAMCK_DIV = 4
584 12:43:53.735657 CA_ADMCK_DIV = 4
585 12:43:53.739889 DQ_TRACK_CA_EN = 0
586 12:43:53.739973 CA_PICK = 800
587 12:43:53.742344 CA_MCKIO = 800
588 12:43:53.746741 MCKIO_SEMI = 0
589 12:43:53.749104 PLL_FREQ = 3068
590 12:43:53.752388 DQ_UI_PI_RATIO = 32
591 12:43:53.756356 CA_UI_PI_RATIO = 0
592 12:43:53.758909 ===================================
593 12:43:53.762289 ===================================
594 12:43:53.762373 memory_type:LPDDR4
595 12:43:53.765629 GP_NUM : 10
596 12:43:53.769268 SRAM_EN : 1
597 12:43:53.769351 MD32_EN : 0
598 12:43:53.772264 ===================================
599 12:43:53.775884 [ANA_INIT] >>>>>>>>>>>>>>
600 12:43:53.779036 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 12:43:53.782814 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 12:43:53.785614 ===================================
603 12:43:53.789230 data_rate = 1600,PCW = 0X7600
604 12:43:53.793150 ===================================
605 12:43:53.796243 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 12:43:53.799327 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 12:43:53.805598 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 12:43:53.808995 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 12:43:53.812614 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 12:43:53.815552 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 12:43:53.819700 [ANA_INIT] flow start
612 12:43:53.822573 [ANA_INIT] PLL >>>>>>>>
613 12:43:53.822656 [ANA_INIT] PLL <<<<<<<<
614 12:43:53.825950 [ANA_INIT] MIDPI >>>>>>>>
615 12:43:53.829163 [ANA_INIT] MIDPI <<<<<<<<
616 12:43:53.832200 [ANA_INIT] DLL >>>>>>>>
617 12:43:53.832283 [ANA_INIT] flow end
618 12:43:53.836425 ============ LP4 DIFF to SE enter ============
619 12:43:53.842465 ============ LP4 DIFF to SE exit ============
620 12:43:53.842565 [ANA_INIT] <<<<<<<<<<<<<
621 12:43:53.845868 [Flow] Enable top DCM control >>>>>
622 12:43:53.849175 [Flow] Enable top DCM control <<<<<
623 12:43:53.852850 Enable DLL master slave shuffle
624 12:43:53.859664 ==============================================================
625 12:43:53.859748 Gating Mode config
626 12:43:53.865715 ==============================================================
627 12:43:53.868837 Config description:
628 12:43:53.875765 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 12:43:53.882576 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 12:43:53.888972 SELPH_MODE 0: By rank 1: By Phase
631 12:43:53.895796 ==============================================================
632 12:43:53.895880 GAT_TRACK_EN = 1
633 12:43:53.899411 RX_GATING_MODE = 2
634 12:43:53.902561 RX_GATING_TRACK_MODE = 2
635 12:43:53.905808 SELPH_MODE = 1
636 12:43:53.908759 PICG_EARLY_EN = 1
637 12:43:53.912571 VALID_LAT_VALUE = 1
638 12:43:53.919548 ==============================================================
639 12:43:53.922585 Enter into Gating configuration >>>>
640 12:43:53.925585 Exit from Gating configuration <<<<
641 12:43:53.929335 Enter into DVFS_PRE_config >>>>>
642 12:43:53.938918 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 12:43:53.942181 Exit from DVFS_PRE_config <<<<<
644 12:43:53.945366 Enter into PICG configuration >>>>
645 12:43:53.949192 Exit from PICG configuration <<<<
646 12:43:53.952111 [RX_INPUT] configuration >>>>>
647 12:43:53.952194 [RX_INPUT] configuration <<<<<
648 12:43:53.958721 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 12:43:53.965446 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 12:43:53.968736 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 12:43:53.975771 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 12:43:53.982145 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 12:43:53.988667 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 12:43:53.992540 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 12:43:53.995584 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 12:43:54.002139 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 12:43:54.006701 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 12:43:54.008647 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 12:43:54.012227 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 12:43:54.015991 ===================================
661 12:43:54.018604 LPDDR4 DRAM CONFIGURATION
662 12:43:54.022496 ===================================
663 12:43:54.025548 EX_ROW_EN[0] = 0x0
664 12:43:54.025632 EX_ROW_EN[1] = 0x0
665 12:43:54.029002 LP4Y_EN = 0x0
666 12:43:54.029086 WORK_FSP = 0x0
667 12:43:54.032887 WL = 0x2
668 12:43:54.032970 RL = 0x2
669 12:43:54.035906 BL = 0x2
670 12:43:54.035990 RPST = 0x0
671 12:43:54.038938 RD_PRE = 0x0
672 12:43:54.039022 WR_PRE = 0x1
673 12:43:54.042102 WR_PST = 0x0
674 12:43:54.042185 DBI_WR = 0x0
675 12:43:54.045519 DBI_RD = 0x0
676 12:43:54.045602 OTF = 0x1
677 12:43:54.049786 ===================================
678 12:43:54.055423 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 12:43:54.059144 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 12:43:54.061875 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 12:43:54.065483 ===================================
682 12:43:54.069066 LPDDR4 DRAM CONFIGURATION
683 12:43:54.072243 ===================================
684 12:43:54.076392 EX_ROW_EN[0] = 0x10
685 12:43:54.076475 EX_ROW_EN[1] = 0x0
686 12:43:54.078766 LP4Y_EN = 0x0
687 12:43:54.078850 WORK_FSP = 0x0
688 12:43:54.082770 WL = 0x2
689 12:43:54.082853 RL = 0x2
690 12:43:54.085254 BL = 0x2
691 12:43:54.085337 RPST = 0x0
692 12:43:54.088882 RD_PRE = 0x0
693 12:43:54.088965 WR_PRE = 0x1
694 12:43:54.091646 WR_PST = 0x0
695 12:43:54.091730 DBI_WR = 0x0
696 12:43:54.095318 DBI_RD = 0x0
697 12:43:54.095401 OTF = 0x1
698 12:43:54.098649 ===================================
699 12:43:54.105103 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 12:43:54.110178 nWR fixed to 40
701 12:43:54.114355 [ModeRegInit_LP4] CH0 RK0
702 12:43:54.114438 [ModeRegInit_LP4] CH0 RK1
703 12:43:54.116863 [ModeRegInit_LP4] CH1 RK0
704 12:43:54.120866 [ModeRegInit_LP4] CH1 RK1
705 12:43:54.120949 match AC timing 12
706 12:43:54.126566 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
707 12:43:54.130211 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 12:43:54.133160 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 12:43:54.140323 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 12:43:54.143578 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 12:43:54.143662 [EMI DOE] emi_dcm 0
712 12:43:54.149856 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 12:43:54.149940 ==
714 12:43:54.153023 Dram Type= 6, Freq= 0, CH_0, rank 0
715 12:43:54.156440 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
716 12:43:54.156526 ==
717 12:43:54.163428 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 12:43:54.169586 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 12:43:54.177765 [CA 0] Center 37 (7~68) winsize 62
720 12:43:54.181001 [CA 1] Center 37 (7~68) winsize 62
721 12:43:54.184159 [CA 2] Center 35 (5~66) winsize 62
722 12:43:54.187447 [CA 3] Center 35 (5~66) winsize 62
723 12:43:54.190463 [CA 4] Center 34 (4~65) winsize 62
724 12:43:54.193972 [CA 5] Center 33 (3~64) winsize 62
725 12:43:54.194055
726 12:43:54.197723 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 12:43:54.197807
728 12:43:54.200634 [CATrainingPosCal] consider 1 rank data
729 12:43:54.204239 u2DelayCellTimex100 = 270/100 ps
730 12:43:54.207397 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 12:43:54.210865 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
732 12:43:54.217198 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
733 12:43:54.221015 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
734 12:43:54.224438 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
735 12:43:54.227218 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 12:43:54.227301
737 12:43:54.230666 CA PerBit enable=1, Macro0, CA PI delay=33
738 12:43:54.230750
739 12:43:54.233644 [CBTSetCACLKResult] CA Dly = 33
740 12:43:54.233727 CS Dly: 5 (0~36)
741 12:43:54.237227 ==
742 12:43:54.240475 Dram Type= 6, Freq= 0, CH_0, rank 1
743 12:43:54.243821 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
744 12:43:54.243904 ==
745 12:43:54.246977 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 12:43:54.253504 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 12:43:54.263345 [CA 0] Center 37 (6~68) winsize 63
748 12:43:54.267129 [CA 1] Center 37 (6~68) winsize 63
749 12:43:54.270001 [CA 2] Center 35 (4~66) winsize 63
750 12:43:54.273563 [CA 3] Center 34 (4~65) winsize 62
751 12:43:54.277103 [CA 4] Center 33 (3~64) winsize 62
752 12:43:54.279778 [CA 5] Center 33 (3~64) winsize 62
753 12:43:54.279861
754 12:43:54.283657 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 12:43:54.283741
756 12:43:54.286671 [CATrainingPosCal] consider 2 rank data
757 12:43:54.290126 u2DelayCellTimex100 = 270/100 ps
758 12:43:54.293574 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 12:43:54.300092 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 12:43:54.303783 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
761 12:43:54.307686 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
762 12:43:54.310324 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
763 12:43:54.313258 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 12:43:54.313342
765 12:43:54.316871 CA PerBit enable=1, Macro0, CA PI delay=33
766 12:43:54.316955
767 12:43:54.320236 [CBTSetCACLKResult] CA Dly = 33
768 12:43:54.320319 CS Dly: 6 (0~38)
769 12:43:54.323601
770 12:43:54.327823 ----->DramcWriteLeveling(PI) begin...
771 12:43:54.327908 ==
772 12:43:54.330429 Dram Type= 6, Freq= 0, CH_0, rank 0
773 12:43:54.333374 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
774 12:43:54.333458 ==
775 12:43:54.336664 Write leveling (Byte 0): 30 => 30
776 12:43:54.339953 Write leveling (Byte 1): 30 => 30
777 12:43:54.342868 DramcWriteLeveling(PI) end<-----
778 12:43:54.342950
779 12:43:54.343017 ==
780 12:43:54.346304 Dram Type= 6, Freq= 0, CH_0, rank 0
781 12:43:54.349424 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 12:43:54.349509 ==
783 12:43:54.352960 [Gating] SW mode calibration
784 12:43:54.359787 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 12:43:54.366240 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 12:43:54.369516 0 6 0 | B1->B0 | 3131 2f2f | 0 1 | (0 1) (1 0)
787 12:43:54.372466 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 12:43:54.379362 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 12:43:54.382519 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 12:43:54.386041 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:43:54.392638 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:43:54.396201 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:43:54.399987 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:43:54.406344 0 7 0 | B1->B0 | 2828 2a2a | 1 0 | (0 0) (0 0)
795 12:43:54.409587 0 7 4 | B1->B0 | 3939 4141 | 0 0 | (0 0) (0 0)
796 12:43:54.412859 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 12:43:54.415866 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 12:43:54.423432 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 12:43:54.426370 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 12:43:54.429472 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 12:43:54.436385 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
802 12:43:54.439736 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
803 12:43:54.442883 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
804 12:43:54.449408 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 12:43:54.452848 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 12:43:54.456398 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 12:43:54.462971 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 12:43:54.465971 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 12:43:54.469082 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 12:43:54.476470 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 12:43:54.479564 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 12:43:54.483174 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 12:43:54.489829 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 12:43:54.493087 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 12:43:54.495948 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 12:43:54.502932 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 12:43:54.505966 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
818 12:43:54.509339 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
819 12:43:54.512868 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
820 12:43:54.516429 Total UI for P1: 0, mck2ui 16
821 12:43:54.519375 best dqsien dly found for B0: ( 0, 10, 2)
822 12:43:54.522996 Total UI for P1: 0, mck2ui 16
823 12:43:54.526467 best dqsien dly found for B1: ( 0, 10, 0)
824 12:43:54.529129 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
825 12:43:54.532812 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
826 12:43:54.536113
827 12:43:54.539150 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
828 12:43:54.542627 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
829 12:43:54.546135 [Gating] SW calibration Done
830 12:43:54.546218 ==
831 12:43:54.549528 Dram Type= 6, Freq= 0, CH_0, rank 0
832 12:43:54.553340 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
833 12:43:54.553424 ==
834 12:43:54.553490 RX Vref Scan: 0
835 12:43:54.553552
836 12:43:54.556557 RX Vref 0 -> 0, step: 1
837 12:43:54.556666
838 12:43:54.559997 RX Delay -130 -> 252, step: 16
839 12:43:54.562966 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
840 12:43:54.567770 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
841 12:43:54.569628 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
842 12:43:54.576777 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
843 12:43:54.579882 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
844 12:43:54.583546 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
845 12:43:54.586260 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
846 12:43:54.589545 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
847 12:43:54.596438 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
848 12:43:54.599770 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
849 12:43:54.603341 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
850 12:43:54.606705 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
851 12:43:54.610004 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
852 12:43:54.616178 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
853 12:43:54.619614 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
854 12:43:54.623251 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
855 12:43:54.623333 ==
856 12:43:54.626734 Dram Type= 6, Freq= 0, CH_0, rank 0
857 12:43:54.629958 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
858 12:43:54.632874 ==
859 12:43:54.632960 DQS Delay:
860 12:43:54.633056 DQS0 = 0, DQS1 = 0
861 12:43:54.636340 DQM Delay:
862 12:43:54.636449 DQM0 = 86, DQM1 = 76
863 12:43:54.639512 DQ Delay:
864 12:43:54.639595 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
865 12:43:54.642787 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
866 12:43:54.646067 DQ8 =69, DQ9 =53, DQ10 =77, DQ11 =69
867 12:43:54.649386 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
868 12:43:54.649468
869 12:43:54.649540
870 12:43:54.653013 ==
871 12:43:54.656829 Dram Type= 6, Freq= 0, CH_0, rank 0
872 12:43:54.659633 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
873 12:43:54.659715 ==
874 12:43:54.659781
875 12:43:54.659841
876 12:43:54.662944 TX Vref Scan disable
877 12:43:54.663027 == TX Byte 0 ==
878 12:43:54.666718 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
879 12:43:54.673098 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
880 12:43:54.673181 == TX Byte 1 ==
881 12:43:54.677149 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
882 12:43:54.683221 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
883 12:43:54.683304 ==
884 12:43:54.686501 Dram Type= 6, Freq= 0, CH_0, rank 0
885 12:43:54.690067 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
886 12:43:54.690150 ==
887 12:43:54.702729 TX Vref=22, minBit 1, minWin=27, winSum=443
888 12:43:54.706867 TX Vref=24, minBit 0, minWin=27, winSum=448
889 12:43:54.709618 TX Vref=26, minBit 0, minWin=28, winSum=452
890 12:43:54.712566 TX Vref=28, minBit 0, minWin=28, winSum=457
891 12:43:54.715671 TX Vref=30, minBit 0, minWin=28, winSum=457
892 12:43:54.719128 TX Vref=32, minBit 0, minWin=28, winSum=452
893 12:43:54.726137 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 28
894 12:43:54.726220
895 12:43:54.729699 Final TX Range 1 Vref 28
896 12:43:54.729781
897 12:43:54.729846 ==
898 12:43:54.733832 Dram Type= 6, Freq= 0, CH_0, rank 0
899 12:43:54.736488 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 12:43:54.736571 ==
901 12:43:54.736636
902 12:43:54.739636
903 12:43:54.739718 TX Vref Scan disable
904 12:43:54.743026 == TX Byte 0 ==
905 12:43:54.746024 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
906 12:43:54.749318 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
907 12:43:54.752641 == TX Byte 1 ==
908 12:43:54.756283 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
909 12:43:54.762230 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
910 12:43:54.762313
911 12:43:54.762377 [DATLAT]
912 12:43:54.762439 Freq=800, CH0 RK0
913 12:43:54.762498
914 12:43:54.765423 DATLAT Default: 0xa
915 12:43:54.765505 0, 0xFFFF, sum = 0
916 12:43:54.768915 1, 0xFFFF, sum = 0
917 12:43:54.772143 2, 0xFFFF, sum = 0
918 12:43:54.772227 3, 0xFFFF, sum = 0
919 12:43:54.775931 4, 0xFFFF, sum = 0
920 12:43:54.776016 5, 0xFFFF, sum = 0
921 12:43:54.779075 6, 0xFFFF, sum = 0
922 12:43:54.779159 7, 0xFFFF, sum = 0
923 12:43:54.782505 8, 0x0, sum = 1
924 12:43:54.782590 9, 0x0, sum = 2
925 12:43:54.782656 10, 0x0, sum = 3
926 12:43:54.785603 11, 0x0, sum = 4
927 12:43:54.785687 best_step = 9
928 12:43:54.785752
929 12:43:54.785813 ==
930 12:43:54.788945 Dram Type= 6, Freq= 0, CH_0, rank 0
931 12:43:54.795822 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
932 12:43:54.795905 ==
933 12:43:54.795971 RX Vref Scan: 1
934 12:43:54.796033
935 12:43:54.799010 Set Vref Range= 32 -> 127
936 12:43:54.799093
937 12:43:54.802915 RX Vref 32 -> 127, step: 1
938 12:43:54.802999
939 12:43:54.805655 RX Delay -111 -> 252, step: 8
940 12:43:54.805737
941 12:43:54.808904 Set Vref, RX VrefLevel [Byte0]: 32
942 12:43:54.813086 [Byte1]: 32
943 12:43:54.813169
944 12:43:54.815839 Set Vref, RX VrefLevel [Byte0]: 33
945 12:43:54.818903 [Byte1]: 33
946 12:43:54.818985
947 12:43:54.821998 Set Vref, RX VrefLevel [Byte0]: 34
948 12:43:54.825213 [Byte1]: 34
949 12:43:54.828874
950 12:43:54.828956 Set Vref, RX VrefLevel [Byte0]: 35
951 12:43:54.832390 [Byte1]: 35
952 12:43:54.836381
953 12:43:54.836462 Set Vref, RX VrefLevel [Byte0]: 36
954 12:43:54.839665 [Byte1]: 36
955 12:43:54.844883
956 12:43:54.844965 Set Vref, RX VrefLevel [Byte0]: 37
957 12:43:54.847194 [Byte1]: 37
958 12:43:54.851821
959 12:43:54.851903 Set Vref, RX VrefLevel [Byte0]: 38
960 12:43:54.855249 [Byte1]: 38
961 12:43:54.859732
962 12:43:54.859814 Set Vref, RX VrefLevel [Byte0]: 39
963 12:43:54.863150 [Byte1]: 39
964 12:43:54.867211
965 12:43:54.867293 Set Vref, RX VrefLevel [Byte0]: 40
966 12:43:54.870672 [Byte1]: 40
967 12:43:54.875187
968 12:43:54.875269 Set Vref, RX VrefLevel [Byte0]: 41
969 12:43:54.878369 [Byte1]: 41
970 12:43:54.882471
971 12:43:54.882553 Set Vref, RX VrefLevel [Byte0]: 42
972 12:43:54.885556 [Byte1]: 42
973 12:43:54.889818
974 12:43:54.889900 Set Vref, RX VrefLevel [Byte0]: 43
975 12:43:54.893084 [Byte1]: 43
976 12:43:54.897666
977 12:43:54.897749 Set Vref, RX VrefLevel [Byte0]: 44
978 12:43:54.900782 [Byte1]: 44
979 12:43:54.905263
980 12:43:54.905346 Set Vref, RX VrefLevel [Byte0]: 45
981 12:43:54.908614 [Byte1]: 45
982 12:43:54.912890
983 12:43:54.912971 Set Vref, RX VrefLevel [Byte0]: 46
984 12:43:54.916416 [Byte1]: 46
985 12:43:54.920703
986 12:43:54.920827 Set Vref, RX VrefLevel [Byte0]: 47
987 12:43:54.923804 [Byte1]: 47
988 12:43:54.929028
989 12:43:54.929110 Set Vref, RX VrefLevel [Byte0]: 48
990 12:43:54.931180 [Byte1]: 48
991 12:43:54.935904
992 12:43:54.935985 Set Vref, RX VrefLevel [Byte0]: 49
993 12:43:54.939480 [Byte1]: 49
994 12:43:54.943483
995 12:43:54.943564 Set Vref, RX VrefLevel [Byte0]: 50
996 12:43:54.947934 [Byte1]: 50
997 12:43:54.951090
998 12:43:54.951172 Set Vref, RX VrefLevel [Byte0]: 51
999 12:43:54.954334 [Byte1]: 51
1000 12:43:54.958730
1001 12:43:54.958811 Set Vref, RX VrefLevel [Byte0]: 52
1002 12:43:54.961959 [Byte1]: 52
1003 12:43:54.966247
1004 12:43:54.966328 Set Vref, RX VrefLevel [Byte0]: 53
1005 12:43:54.969481 [Byte1]: 53
1006 12:43:54.975081
1007 12:43:54.975164 Set Vref, RX VrefLevel [Byte0]: 54
1008 12:43:54.977146 [Byte1]: 54
1009 12:43:54.981826
1010 12:43:54.981908 Set Vref, RX VrefLevel [Byte0]: 55
1011 12:43:54.985130 [Byte1]: 55
1012 12:43:54.989074
1013 12:43:54.989157 Set Vref, RX VrefLevel [Byte0]: 56
1014 12:43:54.992920 [Byte1]: 56
1015 12:43:54.996973
1016 12:43:54.997054 Set Vref, RX VrefLevel [Byte0]: 57
1017 12:43:55.002094 [Byte1]: 57
1018 12:43:55.004546
1019 12:43:55.004628 Set Vref, RX VrefLevel [Byte0]: 58
1020 12:43:55.007936 [Byte1]: 58
1021 12:43:55.012087
1022 12:43:55.012170 Set Vref, RX VrefLevel [Byte0]: 59
1023 12:43:55.015294 [Byte1]: 59
1024 12:43:55.019964
1025 12:43:55.023352 Set Vref, RX VrefLevel [Byte0]: 60
1026 12:43:55.023435 [Byte1]: 60
1027 12:43:55.028199
1028 12:43:55.028281 Set Vref, RX VrefLevel [Byte0]: 61
1029 12:43:55.030917 [Byte1]: 61
1030 12:43:55.034987
1031 12:43:55.035069 Set Vref, RX VrefLevel [Byte0]: 62
1032 12:43:55.038490 [Byte1]: 62
1033 12:43:55.042947
1034 12:43:55.043031 Set Vref, RX VrefLevel [Byte0]: 63
1035 12:43:55.047555 [Byte1]: 63
1036 12:43:55.050411
1037 12:43:55.050491 Set Vref, RX VrefLevel [Byte0]: 64
1038 12:43:55.053741 [Byte1]: 64
1039 12:43:55.057925
1040 12:43:55.058006 Set Vref, RX VrefLevel [Byte0]: 65
1041 12:43:55.061281 [Byte1]: 65
1042 12:43:55.066433
1043 12:43:55.066514 Set Vref, RX VrefLevel [Byte0]: 66
1044 12:43:55.068936 [Byte1]: 66
1045 12:43:55.073271
1046 12:43:55.073352 Set Vref, RX VrefLevel [Byte0]: 67
1047 12:43:55.076645 [Byte1]: 67
1048 12:43:55.081992
1049 12:43:55.082073 Set Vref, RX VrefLevel [Byte0]: 68
1050 12:43:55.084408 [Byte1]: 68
1051 12:43:55.088599
1052 12:43:55.088680 Set Vref, RX VrefLevel [Byte0]: 69
1053 12:43:55.092492 [Byte1]: 69
1054 12:43:55.096680
1055 12:43:55.096770 Set Vref, RX VrefLevel [Byte0]: 70
1056 12:43:55.099842 [Byte1]: 70
1057 12:43:55.105351
1058 12:43:55.105433 Set Vref, RX VrefLevel [Byte0]: 71
1059 12:43:55.108171 [Byte1]: 71
1060 12:43:55.112259
1061 12:43:55.112340 Set Vref, RX VrefLevel [Byte0]: 72
1062 12:43:55.115215 [Byte1]: 72
1063 12:43:55.119427
1064 12:43:55.119508 Set Vref, RX VrefLevel [Byte0]: 73
1065 12:43:55.122632 [Byte1]: 73
1066 12:43:55.126994
1067 12:43:55.127075 Final RX Vref Byte 0 = 51 to rank0
1068 12:43:55.130166 Final RX Vref Byte 1 = 55 to rank0
1069 12:43:55.133643 Final RX Vref Byte 0 = 51 to rank1
1070 12:43:55.136868 Final RX Vref Byte 1 = 55 to rank1==
1071 12:43:55.140279 Dram Type= 6, Freq= 0, CH_0, rank 0
1072 12:43:55.147006 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1073 12:43:55.147089 ==
1074 12:43:55.147155 DQS Delay:
1075 12:43:55.147216 DQS0 = 0, DQS1 = 0
1076 12:43:55.151960 DQM Delay:
1077 12:43:55.152042 DQM0 = 83, DQM1 = 73
1078 12:43:55.153682 DQ Delay:
1079 12:43:55.156869 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1080 12:43:55.159962 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1081 12:43:55.163311 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1082 12:43:55.166430 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1083 12:43:55.166512
1084 12:43:55.166577
1085 12:43:55.173632 [DQSOSCAuto] RK0, (LSB)MR18= 0x3b3b, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1086 12:43:55.176618 CH0 RK0: MR19=606, MR18=3B3B
1087 12:43:55.184277 CH0_RK0: MR19=0x606, MR18=0x3B3B, DQSOSC=394, MR23=63, INC=95, DEC=63
1088 12:43:55.184363
1089 12:43:55.186946 ----->DramcWriteLeveling(PI) begin...
1090 12:43:55.187030 ==
1091 12:43:55.189882 Dram Type= 6, Freq= 0, CH_0, rank 1
1092 12:43:55.193987 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1093 12:43:55.194073 ==
1094 12:43:55.196680 Write leveling (Byte 0): 28 => 28
1095 12:43:55.200517 Write leveling (Byte 1): 28 => 28
1096 12:43:55.203458 DramcWriteLeveling(PI) end<-----
1097 12:43:55.203540
1098 12:43:55.203605 ==
1099 12:43:55.206981 Dram Type= 6, Freq= 0, CH_0, rank 1
1100 12:43:55.210204 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1101 12:43:55.210286 ==
1102 12:43:55.213218 [Gating] SW mode calibration
1103 12:43:55.220828 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1104 12:43:55.226875 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1105 12:43:55.230018 0 6 0 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 0)
1106 12:43:55.233571 0 6 4 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
1107 12:43:55.240072 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1108 12:43:55.243133 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1109 12:43:55.247528 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1110 12:43:55.253322 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1111 12:43:55.256861 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1112 12:43:55.260366 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1113 12:43:55.266795 0 7 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
1114 12:43:55.270079 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1115 12:43:55.273569 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1116 12:43:55.280273 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1117 12:43:55.284278 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1118 12:43:55.286864 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1119 12:43:55.293303 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1120 12:43:55.297051 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1121 12:43:55.299764 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1122 12:43:55.303501 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1123 12:43:55.310488 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1124 12:43:55.313670 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1125 12:43:55.316889 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1126 12:43:55.323662 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1127 12:43:55.326903 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1128 12:43:55.330384 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1129 12:43:55.337007 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1130 12:43:55.340476 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1131 12:43:55.344259 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 12:43:55.349932 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 12:43:55.353104 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 12:43:55.357150 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 12:43:55.363371 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 12:43:55.366542 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 12:43:55.370570 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1138 12:43:55.376515 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1139 12:43:55.379897 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1140 12:43:55.383137 Total UI for P1: 0, mck2ui 16
1141 12:43:55.387241 best dqsien dly found for B0: ( 0, 10, 4)
1142 12:43:55.389947 Total UI for P1: 0, mck2ui 16
1143 12:43:55.393036 best dqsien dly found for B1: ( 0, 10, 2)
1144 12:43:55.396588 best DQS0 dly(MCK, UI, PI) = (0, 10, 4)
1145 12:43:55.399943 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
1146 12:43:55.400024
1147 12:43:55.403373 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 4)
1148 12:43:55.406429 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
1149 12:43:55.409678 [Gating] SW calibration Done
1150 12:43:55.409759 ==
1151 12:43:55.413570 Dram Type= 6, Freq= 0, CH_0, rank 1
1152 12:43:55.417242 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1153 12:43:55.417324 ==
1154 12:43:55.419819 RX Vref Scan: 0
1155 12:43:55.419901
1156 12:43:55.423751 RX Vref 0 -> 0, step: 1
1157 12:43:55.423832
1158 12:43:55.423897 RX Delay -130 -> 252, step: 16
1159 12:43:55.429831 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1160 12:43:55.473771 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1161 12:43:55.473853 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1162 12:43:55.474358 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1163 12:43:55.474625 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1164 12:43:55.475053 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1165 12:43:55.475134 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1166 12:43:55.475919 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1167 12:43:55.476740 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1168 12:43:55.476822 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1169 12:43:55.477072 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1170 12:43:55.477402 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1171 12:43:55.507299 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1172 12:43:55.507386 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1173 12:43:55.507882 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1174 12:43:55.508300 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1175 12:43:55.508381 ==
1176 12:43:55.508942 Dram Type= 6, Freq= 0, CH_0, rank 1
1177 12:43:55.509024 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1178 12:43:55.509090 ==
1179 12:43:55.509336 DQS Delay:
1180 12:43:55.509399 DQS0 = 0, DQS1 = 0
1181 12:43:55.509459 DQM Delay:
1182 12:43:55.509516 DQM0 = 86, DQM1 = 75
1183 12:43:55.509644 DQ Delay:
1184 12:43:55.509724 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1185 12:43:55.511994 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
1186 12:43:55.512075 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1187 12:43:55.515230 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1188 12:43:55.515312
1189 12:43:55.515376
1190 12:43:55.515437 ==
1191 12:43:55.518902 Dram Type= 6, Freq= 0, CH_0, rank 1
1192 12:43:55.525142 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1193 12:43:55.525224 ==
1194 12:43:55.525288
1195 12:43:55.525348
1196 12:43:55.529482 TX Vref Scan disable
1197 12:43:55.529564 == TX Byte 0 ==
1198 12:43:55.531867 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1199 12:43:55.538775 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1200 12:43:55.538856 == TX Byte 1 ==
1201 12:43:55.541713 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1202 12:43:55.548575 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1203 12:43:55.548656 ==
1204 12:43:55.551959 Dram Type= 6, Freq= 0, CH_0, rank 1
1205 12:43:55.555767 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1206 12:43:55.555849 ==
1207 12:43:55.568281 TX Vref=22, minBit 0, minWin=27, winSum=442
1208 12:43:55.571450 TX Vref=24, minBit 2, minWin=27, winSum=447
1209 12:43:55.574651 TX Vref=26, minBit 1, minWin=28, winSum=451
1210 12:43:55.578163 TX Vref=28, minBit 4, minWin=28, winSum=456
1211 12:43:55.581261 TX Vref=30, minBit 2, minWin=28, winSum=458
1212 12:43:55.584906 TX Vref=32, minBit 2, minWin=28, winSum=459
1213 12:43:55.591553 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 32
1214 12:43:55.591636
1215 12:43:55.595731 Final TX Range 1 Vref 32
1216 12:43:55.595813
1217 12:43:55.595879 ==
1218 12:43:55.599413 Dram Type= 6, Freq= 0, CH_0, rank 1
1219 12:43:55.601954 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1220 12:43:55.602070 ==
1221 12:43:55.602138
1222 12:43:55.602200
1223 12:43:55.604851 TX Vref Scan disable
1224 12:43:55.607959 == TX Byte 0 ==
1225 12:43:55.611404 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1226 12:43:55.614505 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1227 12:43:55.618166 == TX Byte 1 ==
1228 12:43:55.621560 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1229 12:43:55.625023 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1230 12:43:55.628980
1231 12:43:55.629061 [DATLAT]
1232 12:43:55.629127 Freq=800, CH0 RK1
1233 12:43:55.629189
1234 12:43:55.631354 DATLAT Default: 0x9
1235 12:43:55.631439 0, 0xFFFF, sum = 0
1236 12:43:55.634790 1, 0xFFFF, sum = 0
1237 12:43:55.634873 2, 0xFFFF, sum = 0
1238 12:43:55.637711 3, 0xFFFF, sum = 0
1239 12:43:55.637795 4, 0xFFFF, sum = 0
1240 12:43:55.642754 5, 0xFFFF, sum = 0
1241 12:43:55.642841 6, 0xFFFF, sum = 0
1242 12:43:55.645903 7, 0xFFFF, sum = 0
1243 12:43:55.645986 8, 0x0, sum = 1
1244 12:43:55.648630 9, 0x0, sum = 2
1245 12:43:55.648721 10, 0x0, sum = 3
1246 12:43:55.651504 11, 0x0, sum = 4
1247 12:43:55.651587 best_step = 9
1248 12:43:55.651653
1249 12:43:55.651713 ==
1250 12:43:55.654380 Dram Type= 6, Freq= 0, CH_0, rank 1
1251 12:43:55.661275 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1252 12:43:55.661358 ==
1253 12:43:55.661423 RX Vref Scan: 0
1254 12:43:55.661484
1255 12:43:55.664433 RX Vref 0 -> 0, step: 1
1256 12:43:55.664516
1257 12:43:55.668272 RX Delay -95 -> 252, step: 8
1258 12:43:55.671081 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1259 12:43:55.674655 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1260 12:43:55.681282 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1261 12:43:55.684484 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1262 12:43:55.688328 iDelay=217, Bit 4, Center 92 (-23 ~ 208) 232
1263 12:43:55.691740 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1264 12:43:55.694767 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1265 12:43:55.698653 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1266 12:43:55.705177 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1267 12:43:55.708318 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1268 12:43:55.711715 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1269 12:43:55.714727 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1270 12:43:55.718988 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1271 12:43:55.724496 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1272 12:43:55.727726 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1273 12:43:55.731846 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1274 12:43:55.731929 ==
1275 12:43:55.735009 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 12:43:55.737905 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1277 12:43:55.740775 ==
1278 12:43:55.740857 DQS Delay:
1279 12:43:55.740923 DQS0 = 0, DQS1 = 0
1280 12:43:55.744516 DQM Delay:
1281 12:43:55.744598 DQM0 = 87, DQM1 = 74
1282 12:43:55.747762 DQ Delay:
1283 12:43:55.747843 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1284 12:43:55.751133 DQ4 =92, DQ5 =76, DQ6 =92, DQ7 =96
1285 12:43:55.754271 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1286 12:43:55.757986 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
1287 12:43:55.758078
1288 12:43:55.761096
1289 12:43:55.767497 [DQSOSCAuto] RK1, (LSB)MR18= 0x4242, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1290 12:43:55.770829 CH0 RK1: MR19=606, MR18=4242
1291 12:43:55.777390 CH0_RK1: MR19=0x606, MR18=0x4242, DQSOSC=393, MR23=63, INC=95, DEC=63
1292 12:43:55.780918 [RxdqsGatingPostProcess] freq 800
1293 12:43:55.784580 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1294 12:43:55.787454 Pre-setting of DQS Precalculation
1295 12:43:55.791781 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1296 12:43:55.793958 ==
1297 12:43:55.797469 Dram Type= 6, Freq= 0, CH_1, rank 0
1298 12:43:55.800678 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1299 12:43:55.800820 ==
1300 12:43:55.804920 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1301 12:43:55.810955 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1302 12:43:55.820662 [CA 0] Center 36 (6~67) winsize 62
1303 12:43:55.824060 [CA 1] Center 36 (6~67) winsize 62
1304 12:43:55.826912 [CA 2] Center 34 (4~65) winsize 62
1305 12:43:55.830234 [CA 3] Center 34 (4~64) winsize 61
1306 12:43:55.833644 [CA 4] Center 33 (3~64) winsize 62
1307 12:43:55.837131 [CA 5] Center 33 (3~64) winsize 62
1308 12:43:55.837212
1309 12:43:55.840939 [CmdBusTrainingLP45] Vref(ca) range 1: 28
1310 12:43:55.841020
1311 12:43:55.843755 [CATrainingPosCal] consider 1 rank data
1312 12:43:55.847315 u2DelayCellTimex100 = 270/100 ps
1313 12:43:55.850235 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1314 12:43:55.853561 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1315 12:43:55.860253 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1316 12:43:55.863595 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1317 12:43:55.867034 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1318 12:43:55.870322 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1319 12:43:55.870402
1320 12:43:55.873928 CA PerBit enable=1, Macro0, CA PI delay=33
1321 12:43:55.874015
1322 12:43:55.877032 [CBTSetCACLKResult] CA Dly = 33
1323 12:43:55.877133 CS Dly: 4 (0~35)
1324 12:43:55.880127 ==
1325 12:43:55.880201 Dram Type= 6, Freq= 0, CH_1, rank 1
1326 12:43:55.887080 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1327 12:43:55.887180 ==
1328 12:43:55.890311 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1329 12:43:55.897138 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1330 12:43:55.907001 [CA 0] Center 36 (6~67) winsize 62
1331 12:43:55.909791 [CA 1] Center 36 (5~67) winsize 63
1332 12:43:55.912694 [CA 2] Center 34 (4~65) winsize 62
1333 12:43:55.916231 [CA 3] Center 34 (4~65) winsize 62
1334 12:43:55.919989 [CA 4] Center 33 (3~63) winsize 61
1335 12:43:55.923869 [CA 5] Center 32 (2~63) winsize 62
1336 12:43:55.923970
1337 12:43:55.926675 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1338 12:43:55.926772
1339 12:43:55.929973 [CATrainingPosCal] consider 2 rank data
1340 12:43:55.932898 u2DelayCellTimex100 = 270/100 ps
1341 12:43:55.936215 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1342 12:43:55.939954 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1343 12:43:55.946516 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1344 12:43:55.949688 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1345 12:43:55.953528 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
1346 12:43:55.956195 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
1347 12:43:55.956267
1348 12:43:55.959687 CA PerBit enable=1, Macro0, CA PI delay=33
1349 12:43:55.959758
1350 12:43:55.962839 [CBTSetCACLKResult] CA Dly = 33
1351 12:43:55.962914 CS Dly: 4 (0~36)
1352 12:43:55.962976
1353 12:43:55.966292 ----->DramcWriteLeveling(PI) begin...
1354 12:43:55.969750 ==
1355 12:43:55.972856 Dram Type= 6, Freq= 0, CH_1, rank 0
1356 12:43:55.976362 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1357 12:43:55.976433 ==
1358 12:43:55.979676 Write leveling (Byte 0): 25 => 25
1359 12:43:55.982660 Write leveling (Byte 1): 25 => 25
1360 12:43:55.986827 DramcWriteLeveling(PI) end<-----
1361 12:43:55.986897
1362 12:43:55.986956 ==
1363 12:43:55.989621 Dram Type= 6, Freq= 0, CH_1, rank 0
1364 12:43:55.993135 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1365 12:43:55.993205 ==
1366 12:43:55.996821 [Gating] SW mode calibration
1367 12:43:56.002707 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1368 12:43:56.006229 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1369 12:43:56.012581 0 6 0 | B1->B0 | 2f2f 2424 | 1 0 | (1 0) (1 0)
1370 12:43:56.016373 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1371 12:43:56.019711 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1372 12:43:56.026532 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1373 12:43:56.029428 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1374 12:43:56.032929 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1375 12:43:56.039649 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1376 12:43:56.042540 0 6 28 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1377 12:43:56.046352 0 7 0 | B1->B0 | 2d2d 3e3e | 0 0 | (1 1) (0 0)
1378 12:43:56.053595 0 7 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1379 12:43:56.056049 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1380 12:43:56.059424 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1381 12:43:56.066175 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1382 12:43:56.069185 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1383 12:43:56.072591 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1384 12:43:56.079794 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1385 12:43:56.082510 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1386 12:43:56.085809 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1387 12:43:56.092356 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1388 12:43:56.095881 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1389 12:43:56.100392 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1390 12:43:56.106446 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1391 12:43:56.109370 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1392 12:43:56.112447 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1393 12:43:56.119293 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1394 12:43:56.122235 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 12:43:56.126395 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 12:43:56.128911 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 12:43:56.136380 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 12:43:56.139056 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 12:43:56.143379 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1400 12:43:56.150169 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1401 12:43:56.152864 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1402 12:43:56.156257 Total UI for P1: 0, mck2ui 16
1403 12:43:56.159909 best dqsien dly found for B0: ( 0, 9, 30)
1404 12:43:56.162605 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1405 12:43:56.166084 Total UI for P1: 0, mck2ui 16
1406 12:43:56.169547 best dqsien dly found for B1: ( 0, 10, 0)
1407 12:43:56.173137 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1408 12:43:56.176269 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1409 12:43:56.176352
1410 12:43:56.182622 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1411 12:43:56.186539 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1412 12:43:56.186622 [Gating] SW calibration Done
1413 12:43:56.189798 ==
1414 12:43:56.189882 Dram Type= 6, Freq= 0, CH_1, rank 0
1415 12:43:56.196290 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1416 12:43:56.196374 ==
1417 12:43:56.196459 RX Vref Scan: 0
1418 12:43:56.196558
1419 12:43:56.199619 RX Vref 0 -> 0, step: 1
1420 12:43:56.199717
1421 12:43:56.202785 RX Delay -130 -> 252, step: 16
1422 12:43:56.206125 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1423 12:43:56.209148 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1424 12:43:56.213025 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1425 12:43:56.219798 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1426 12:43:56.222652 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1427 12:43:56.225858 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1428 12:43:56.229296 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1429 12:43:56.235548 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1430 12:43:56.238974 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1431 12:43:56.242523 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1432 12:43:56.245408 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1433 12:43:56.249530 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1434 12:43:56.255660 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1435 12:43:56.259102 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1436 12:43:56.262248 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1437 12:43:56.265713 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1438 12:43:56.265786 ==
1439 12:43:56.269813 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 12:43:56.275498 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1441 12:43:56.275573 ==
1442 12:43:56.275639 DQS Delay:
1443 12:43:56.275698 DQS0 = 0, DQS1 = 0
1444 12:43:56.279066 DQM Delay:
1445 12:43:56.279131 DQM0 = 80, DQM1 = 69
1446 12:43:56.282165 DQ Delay:
1447 12:43:56.285677 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1448 12:43:56.285743 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1449 12:43:56.288808 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =61
1450 12:43:56.292647 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1451 12:43:56.295461
1452 12:43:56.295532
1453 12:43:56.295619 ==
1454 12:43:56.298749 Dram Type= 6, Freq= 0, CH_1, rank 0
1455 12:43:56.302045 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1456 12:43:56.302113 ==
1457 12:43:56.302173
1458 12:43:56.302237
1459 12:43:56.305284 TX Vref Scan disable
1460 12:43:56.305354 == TX Byte 0 ==
1461 12:43:56.312629 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1462 12:43:56.316268 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1463 12:43:56.316374 == TX Byte 1 ==
1464 12:43:56.322273 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1465 12:43:56.326862 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1466 12:43:56.326962 ==
1467 12:43:56.329317 Dram Type= 6, Freq= 0, CH_1, rank 0
1468 12:43:56.331887 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1469 12:43:56.331960 ==
1470 12:43:56.345344 TX Vref=22, minBit 8, minWin=27, winSum=445
1471 12:43:56.349136 TX Vref=24, minBit 9, minWin=27, winSum=446
1472 12:43:56.352275 TX Vref=26, minBit 0, minWin=28, winSum=452
1473 12:43:56.355348 TX Vref=28, minBit 0, minWin=28, winSum=455
1474 12:43:56.358682 TX Vref=30, minBit 2, minWin=28, winSum=457
1475 12:43:56.361868 TX Vref=32, minBit 2, minWin=28, winSum=455
1476 12:43:56.369002 [TxChooseVref] Worse bit 2, Min win 28, Win sum 457, Final Vref 30
1477 12:43:56.369076
1478 12:43:56.371883 Final TX Range 1 Vref 30
1479 12:43:56.371952
1480 12:43:56.372019 ==
1481 12:43:56.375168 Dram Type= 6, Freq= 0, CH_1, rank 0
1482 12:43:56.378717 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1483 12:43:56.378795 ==
1484 12:43:56.378856
1485 12:43:56.382744
1486 12:43:56.382813 TX Vref Scan disable
1487 12:43:56.385245 == TX Byte 0 ==
1488 12:43:56.389229 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1489 12:43:56.391920 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1490 12:43:56.395248 == TX Byte 1 ==
1491 12:43:56.398651 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1492 12:43:56.402199 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1493 12:43:56.405619
1494 12:43:56.405692 [DATLAT]
1495 12:43:56.405761 Freq=800, CH1 RK0
1496 12:43:56.405822
1497 12:43:56.408949 DATLAT Default: 0xa
1498 12:43:56.409025 0, 0xFFFF, sum = 0
1499 12:43:56.411962 1, 0xFFFF, sum = 0
1500 12:43:56.412039 2, 0xFFFF, sum = 0
1501 12:43:56.415663 3, 0xFFFF, sum = 0
1502 12:43:56.415733 4, 0xFFFF, sum = 0
1503 12:43:56.418793 5, 0xFFFF, sum = 0
1504 12:43:56.422197 6, 0xFFFF, sum = 0
1505 12:43:56.422275 7, 0xFFFF, sum = 0
1506 12:43:56.422339 8, 0x0, sum = 1
1507 12:43:56.425654 9, 0x0, sum = 2
1508 12:43:56.425728 10, 0x0, sum = 3
1509 12:43:56.428788 11, 0x0, sum = 4
1510 12:43:56.428858 best_step = 9
1511 12:43:56.428918
1512 12:43:56.428981 ==
1513 12:43:56.432256 Dram Type= 6, Freq= 0, CH_1, rank 0
1514 12:43:56.438777 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1515 12:43:56.438851 ==
1516 12:43:56.438913 RX Vref Scan: 1
1517 12:43:56.438978
1518 12:43:56.441963 Set Vref Range= 32 -> 127
1519 12:43:56.442037
1520 12:43:56.445187 RX Vref 32 -> 127, step: 1
1521 12:43:56.445283
1522 12:43:56.448487 RX Delay -111 -> 252, step: 8
1523 12:43:56.448556
1524 12:43:56.448614 Set Vref, RX VrefLevel [Byte0]: 32
1525 12:43:56.451969 [Byte1]: 32
1526 12:43:56.456302
1527 12:43:56.456375 Set Vref, RX VrefLevel [Byte0]: 33
1528 12:43:56.459528 [Byte1]: 33
1529 12:43:56.463553
1530 12:43:56.463626 Set Vref, RX VrefLevel [Byte0]: 34
1531 12:43:56.467274 [Byte1]: 34
1532 12:43:56.471404
1533 12:43:56.471484 Set Vref, RX VrefLevel [Byte0]: 35
1534 12:43:56.474882 [Byte1]: 35
1535 12:43:56.479710
1536 12:43:56.479790 Set Vref, RX VrefLevel [Byte0]: 36
1537 12:43:56.483062 [Byte1]: 36
1538 12:43:56.487302
1539 12:43:56.487382 Set Vref, RX VrefLevel [Byte0]: 37
1540 12:43:56.490441 [Byte1]: 37
1541 12:43:56.494888
1542 12:43:56.494969 Set Vref, RX VrefLevel [Byte0]: 38
1543 12:43:56.497770 [Byte1]: 38
1544 12:43:56.502017
1545 12:43:56.502099 Set Vref, RX VrefLevel [Byte0]: 39
1546 12:43:56.505171 [Byte1]: 39
1547 12:43:56.510325
1548 12:43:56.510406 Set Vref, RX VrefLevel [Byte0]: 40
1549 12:43:56.512922 [Byte1]: 40
1550 12:43:56.517224
1551 12:43:56.517305 Set Vref, RX VrefLevel [Byte0]: 41
1552 12:43:56.520689 [Byte1]: 41
1553 12:43:56.525097
1554 12:43:56.525179 Set Vref, RX VrefLevel [Byte0]: 42
1555 12:43:56.528846 [Byte1]: 42
1556 12:43:56.533365
1557 12:43:56.533445 Set Vref, RX VrefLevel [Byte0]: 43
1558 12:43:56.535725 [Byte1]: 43
1559 12:43:56.540145
1560 12:43:56.540226 Set Vref, RX VrefLevel [Byte0]: 44
1561 12:43:56.543587 [Byte1]: 44
1562 12:43:56.548165
1563 12:43:56.548247 Set Vref, RX VrefLevel [Byte0]: 45
1564 12:43:56.551394 [Byte1]: 45
1565 12:43:56.555734
1566 12:43:56.555815 Set Vref, RX VrefLevel [Byte0]: 46
1567 12:43:56.558968 [Byte1]: 46
1568 12:43:56.563785
1569 12:43:56.563866 Set Vref, RX VrefLevel [Byte0]: 47
1570 12:43:56.566958 [Byte1]: 47
1571 12:43:56.570797
1572 12:43:56.570879 Set Vref, RX VrefLevel [Byte0]: 48
1573 12:43:56.574286 [Byte1]: 48
1574 12:43:56.578618
1575 12:43:56.578699 Set Vref, RX VrefLevel [Byte0]: 49
1576 12:43:56.581861 [Byte1]: 49
1577 12:43:56.586296
1578 12:43:56.586378 Set Vref, RX VrefLevel [Byte0]: 50
1579 12:43:56.589543 [Byte1]: 50
1580 12:43:56.593945
1581 12:43:56.594027 Set Vref, RX VrefLevel [Byte0]: 51
1582 12:43:56.597642 [Byte1]: 51
1583 12:43:56.601437
1584 12:43:56.601518 Set Vref, RX VrefLevel [Byte0]: 52
1585 12:43:56.604701 [Byte1]: 52
1586 12:43:56.609295
1587 12:43:56.609378 Set Vref, RX VrefLevel [Byte0]: 53
1588 12:43:56.612796 [Byte1]: 53
1589 12:43:56.616860
1590 12:43:56.616967 Set Vref, RX VrefLevel [Byte0]: 54
1591 12:43:56.620223 [Byte1]: 54
1592 12:43:56.625683
1593 12:43:56.625765 Set Vref, RX VrefLevel [Byte0]: 55
1594 12:43:56.628129 [Byte1]: 55
1595 12:43:56.632247
1596 12:43:56.632329 Set Vref, RX VrefLevel [Byte0]: 56
1597 12:43:56.636224 [Byte1]: 56
1598 12:43:56.640024
1599 12:43:56.640105 Set Vref, RX VrefLevel [Byte0]: 57
1600 12:43:56.642973 [Byte1]: 57
1601 12:43:56.647489
1602 12:43:56.647570 Set Vref, RX VrefLevel [Byte0]: 58
1603 12:43:56.650975 [Byte1]: 58
1604 12:43:56.656020
1605 12:43:56.656101 Set Vref, RX VrefLevel [Byte0]: 59
1606 12:43:56.658256 [Byte1]: 59
1607 12:43:56.663346
1608 12:43:56.663427 Set Vref, RX VrefLevel [Byte0]: 60
1609 12:43:56.666225 [Byte1]: 60
1610 12:43:56.670599
1611 12:43:56.670682 Set Vref, RX VrefLevel [Byte0]: 61
1612 12:43:56.673634 [Byte1]: 61
1613 12:43:56.678065
1614 12:43:56.678147 Set Vref, RX VrefLevel [Byte0]: 62
1615 12:43:56.681894 [Byte1]: 62
1616 12:43:56.685519
1617 12:43:56.685602 Set Vref, RX VrefLevel [Byte0]: 63
1618 12:43:56.689302 [Byte1]: 63
1619 12:43:56.693173
1620 12:43:56.693256 Set Vref, RX VrefLevel [Byte0]: 64
1621 12:43:56.696565 [Byte1]: 64
1622 12:43:56.700982
1623 12:43:56.701065 Set Vref, RX VrefLevel [Byte0]: 65
1624 12:43:56.704253 [Byte1]: 65
1625 12:43:56.708894
1626 12:43:56.708978 Set Vref, RX VrefLevel [Byte0]: 66
1627 12:43:56.712124 [Byte1]: 66
1628 12:43:56.716502
1629 12:43:56.716585 Set Vref, RX VrefLevel [Byte0]: 67
1630 12:43:56.719847 [Byte1]: 67
1631 12:43:56.724114
1632 12:43:56.724197 Set Vref, RX VrefLevel [Byte0]: 68
1633 12:43:56.727269 [Byte1]: 68
1634 12:43:56.732161
1635 12:43:56.732244 Set Vref, RX VrefLevel [Byte0]: 69
1636 12:43:56.735014 [Byte1]: 69
1637 12:43:56.739370
1638 12:43:56.739454 Set Vref, RX VrefLevel [Byte0]: 70
1639 12:43:56.742353 [Byte1]: 70
1640 12:43:56.747420
1641 12:43:56.747518 Set Vref, RX VrefLevel [Byte0]: 71
1642 12:43:56.750374 [Byte1]: 71
1643 12:43:56.754367
1644 12:43:56.754451 Set Vref, RX VrefLevel [Byte0]: 72
1645 12:43:56.757686 [Byte1]: 72
1646 12:43:56.763264
1647 12:43:56.763347 Set Vref, RX VrefLevel [Byte0]: 73
1648 12:43:56.765257 [Byte1]: 73
1649 12:43:56.769882
1650 12:43:56.769965 Set Vref, RX VrefLevel [Byte0]: 74
1651 12:43:56.773261 [Byte1]: 74
1652 12:43:56.777168
1653 12:43:56.777251 Set Vref, RX VrefLevel [Byte0]: 75
1654 12:43:56.780744 [Byte1]: 75
1655 12:43:56.785702
1656 12:43:56.785785 Set Vref, RX VrefLevel [Byte0]: 76
1657 12:43:56.788517 [Byte1]: 76
1658 12:43:56.792559
1659 12:43:56.792642 Set Vref, RX VrefLevel [Byte0]: 77
1660 12:43:56.796024 [Byte1]: 77
1661 12:43:56.800177
1662 12:43:56.800261 Set Vref, RX VrefLevel [Byte0]: 78
1663 12:43:56.803413 [Byte1]: 78
1664 12:43:56.808378
1665 12:43:56.808461 Set Vref, RX VrefLevel [Byte0]: 79
1666 12:43:56.811090 [Byte1]: 79
1667 12:43:56.815422
1668 12:43:56.815505 Set Vref, RX VrefLevel [Byte0]: 80
1669 12:43:56.819022 [Byte1]: 80
1670 12:43:56.823235
1671 12:43:56.826506 Final RX Vref Byte 0 = 63 to rank0
1672 12:43:56.826591 Final RX Vref Byte 1 = 60 to rank0
1673 12:43:56.830102 Final RX Vref Byte 0 = 63 to rank1
1674 12:43:56.832916 Final RX Vref Byte 1 = 60 to rank1==
1675 12:43:56.837108 Dram Type= 6, Freq= 0, CH_1, rank 0
1676 12:43:56.843069 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1677 12:43:56.843153 ==
1678 12:43:56.843238 DQS Delay:
1679 12:43:56.843319 DQS0 = 0, DQS1 = 0
1680 12:43:56.846920 DQM Delay:
1681 12:43:56.847003 DQM0 = 80, DQM1 = 71
1682 12:43:56.850982 DQ Delay:
1683 12:43:56.853277 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =76
1684 12:43:56.853361 DQ4 =76, DQ5 =92, DQ6 =88, DQ7 =76
1685 12:43:56.856850 DQ8 =56, DQ9 =60, DQ10 =72, DQ11 =64
1686 12:43:56.859974 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
1687 12:43:56.863509
1688 12:43:56.863592
1689 12:43:56.870874 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
1690 12:43:56.874439 CH1 RK0: MR19=606, MR18=4A4A
1691 12:43:56.880250 CH1_RK0: MR19=0x606, MR18=0x4A4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1692 12:43:56.880335
1693 12:43:56.883318 ----->DramcWriteLeveling(PI) begin...
1694 12:43:56.883403 ==
1695 12:43:56.886650 Dram Type= 6, Freq= 0, CH_1, rank 1
1696 12:43:56.890618 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1697 12:43:56.890702 ==
1698 12:43:56.893879 Write leveling (Byte 0): 26 => 26
1699 12:43:56.897710 Write leveling (Byte 1): 26 => 26
1700 12:43:56.900389 DramcWriteLeveling(PI) end<-----
1701 12:43:56.900470
1702 12:43:56.900535 ==
1703 12:43:56.903132 Dram Type= 6, Freq= 0, CH_1, rank 1
1704 12:43:56.906827 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1705 12:43:56.906913 ==
1706 12:43:56.910120 [Gating] SW mode calibration
1707 12:43:56.916647 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1708 12:43:56.923525 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1709 12:43:56.926600 0 6 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (1 0)
1710 12:43:56.930215 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1711 12:43:56.936618 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1712 12:43:56.940091 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1713 12:43:56.943827 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1714 12:43:56.949866 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1715 12:43:56.953632 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1716 12:43:56.957045 0 6 28 | B1->B0 | 2626 3333 | 0 0 | (0 0) (0 0)
1717 12:43:56.963903 0 7 0 | B1->B0 | 3737 4646 | 0 0 | (1 1) (0 0)
1718 12:43:56.966771 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1719 12:43:56.969750 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1720 12:43:56.976423 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1721 12:43:56.979950 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1722 12:43:56.983339 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1723 12:43:56.989550 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1724 12:43:56.993514 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1725 12:43:56.996663 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1726 12:43:57.000151 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1727 12:43:57.006219 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1728 12:43:57.009945 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1729 12:43:57.013238 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1730 12:43:57.019694 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1731 12:43:57.023160 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1732 12:43:57.026618 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1733 12:43:57.032912 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1734 12:43:57.036449 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1735 12:43:57.039906 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1736 12:43:57.046360 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1737 12:43:57.050512 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1738 12:43:57.052849 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1739 12:43:57.060871 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1740 12:43:57.063482 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1741 12:43:57.067124 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1742 12:43:57.069643 Total UI for P1: 0, mck2ui 16
1743 12:43:57.073647 best dqsien dly found for B0: ( 0, 9, 28)
1744 12:43:57.076926 Total UI for P1: 0, mck2ui 16
1745 12:43:57.079531 best dqsien dly found for B1: ( 0, 9, 28)
1746 12:43:57.083000 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1747 12:43:57.086428 best DQS1 dly(MCK, UI, PI) = (0, 9, 28)
1748 12:43:57.086537
1749 12:43:57.090167 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1750 12:43:57.096412 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 28)
1751 12:43:57.096527 [Gating] SW calibration Done
1752 12:43:57.096620 ==
1753 12:43:57.099999 Dram Type= 6, Freq= 0, CH_1, rank 1
1754 12:43:57.106604 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1755 12:43:57.106695 ==
1756 12:43:57.106780 RX Vref Scan: 0
1757 12:43:57.106861
1758 12:43:57.110945 RX Vref 0 -> 0, step: 1
1759 12:43:57.111029
1760 12:43:57.113274 RX Delay -130 -> 252, step: 16
1761 12:43:57.116873 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1762 12:43:57.120171 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1763 12:43:57.124019 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1764 12:43:57.129696 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1765 12:43:57.133216 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1766 12:43:57.136387 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1767 12:43:57.140070 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1768 12:43:57.142980 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1769 12:43:57.149798 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1770 12:43:57.153464 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1771 12:43:57.157292 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1772 12:43:57.160341 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1773 12:43:57.163058 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1774 12:43:57.170624 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1775 12:43:57.173468 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1776 12:43:57.176657 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1777 12:43:57.176749 ==
1778 12:43:57.180175 Dram Type= 6, Freq= 0, CH_1, rank 1
1779 12:43:57.183542 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1780 12:43:57.183626 ==
1781 12:43:57.186403 DQS Delay:
1782 12:43:57.186486 DQS0 = 0, DQS1 = 0
1783 12:43:57.190729 DQM Delay:
1784 12:43:57.190812 DQM0 = 82, DQM1 = 69
1785 12:43:57.190897 DQ Delay:
1786 12:43:57.193288 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1787 12:43:57.196517 DQ4 =77, DQ5 =101, DQ6 =85, DQ7 =77
1788 12:43:57.200596 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =61
1789 12:43:57.202871 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1790 12:43:57.202955
1791 12:43:57.203055
1792 12:43:57.206176 ==
1793 12:43:57.209944 Dram Type= 6, Freq= 0, CH_1, rank 1
1794 12:43:57.213117 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1795 12:43:57.213201 ==
1796 12:43:57.213287
1797 12:43:57.213368
1798 12:43:57.216285 TX Vref Scan disable
1799 12:43:57.216370 == TX Byte 0 ==
1800 12:43:57.219428 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1801 12:43:57.226613 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1802 12:43:57.226697 == TX Byte 1 ==
1803 12:43:57.229542 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1804 12:43:57.236466 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1805 12:43:57.236549 ==
1806 12:43:57.239844 Dram Type= 6, Freq= 0, CH_1, rank 1
1807 12:43:57.244083 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1808 12:43:57.244167 ==
1809 12:43:57.256685 TX Vref=22, minBit 10, minWin=27, winSum=448
1810 12:43:57.259129 TX Vref=24, minBit 13, minWin=27, winSum=451
1811 12:43:57.262526 TX Vref=26, minBit 0, minWin=28, winSum=456
1812 12:43:57.265591 TX Vref=28, minBit 0, minWin=28, winSum=456
1813 12:43:57.269146 TX Vref=30, minBit 0, minWin=28, winSum=457
1814 12:43:57.275854 TX Vref=32, minBit 0, minWin=28, winSum=453
1815 12:43:57.279520 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 30
1816 12:43:57.279604
1817 12:43:57.282786 Final TX Range 1 Vref 30
1818 12:43:57.282870
1819 12:43:57.282954 ==
1820 12:43:57.285959 Dram Type= 6, Freq= 0, CH_1, rank 1
1821 12:43:57.289142 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1822 12:43:57.291984 ==
1823 12:43:57.292067
1824 12:43:57.292151
1825 12:43:57.292232 TX Vref Scan disable
1826 12:43:57.295676 == TX Byte 0 ==
1827 12:43:57.299663 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1828 12:43:57.306608 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1829 12:43:57.306693 == TX Byte 1 ==
1830 12:43:57.309559 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1831 12:43:57.313835 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1832 12:43:57.316172
1833 12:43:57.316255 [DATLAT]
1834 12:43:57.316340 Freq=800, CH1 RK1
1835 12:43:57.316421
1836 12:43:57.319074 DATLAT Default: 0x9
1837 12:43:57.319158 0, 0xFFFF, sum = 0
1838 12:43:57.322626 1, 0xFFFF, sum = 0
1839 12:43:57.322711 2, 0xFFFF, sum = 0
1840 12:43:57.326151 3, 0xFFFF, sum = 0
1841 12:43:57.326237 4, 0xFFFF, sum = 0
1842 12:43:57.329196 5, 0xFFFF, sum = 0
1843 12:43:57.332391 6, 0xFFFF, sum = 0
1844 12:43:57.332476 7, 0xFFFF, sum = 0
1845 12:43:57.335712 8, 0x0, sum = 1
1846 12:43:57.335796 9, 0x0, sum = 2
1847 12:43:57.335884 10, 0x0, sum = 3
1848 12:43:57.340202 11, 0x0, sum = 4
1849 12:43:57.340286 best_step = 9
1850 12:43:57.340371
1851 12:43:57.340451 ==
1852 12:43:57.342862 Dram Type= 6, Freq= 0, CH_1, rank 1
1853 12:43:57.349654 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1854 12:43:57.349738 ==
1855 12:43:57.349823 RX Vref Scan: 0
1856 12:43:57.349904
1857 12:43:57.352602 RX Vref 0 -> 0, step: 1
1858 12:43:57.352685
1859 12:43:57.355714 RX Delay -111 -> 252, step: 8
1860 12:43:57.359487 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1861 12:43:57.362478 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1862 12:43:57.369278 iDelay=209, Bit 2, Center 72 (-47 ~ 192) 240
1863 12:43:57.373329 iDelay=209, Bit 3, Center 80 (-39 ~ 200) 240
1864 12:43:57.376040 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1865 12:43:57.379538 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
1866 12:43:57.384056 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1867 12:43:57.388968 iDelay=209, Bit 7, Center 80 (-39 ~ 200) 240
1868 12:43:57.392583 iDelay=209, Bit 8, Center 56 (-63 ~ 176) 240
1869 12:43:57.395865 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1870 12:43:57.399463 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1871 12:43:57.402075 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1872 12:43:57.408794 iDelay=209, Bit 12, Center 84 (-39 ~ 208) 248
1873 12:43:57.412422 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
1874 12:43:57.415723 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1875 12:43:57.418696 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1876 12:43:57.418778 ==
1877 12:43:57.422238 Dram Type= 6, Freq= 0, CH_1, rank 1
1878 12:43:57.428956 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1879 12:43:57.429038 ==
1880 12:43:57.429104 DQS Delay:
1881 12:43:57.429165 DQS0 = 0, DQS1 = 0
1882 12:43:57.432336 DQM Delay:
1883 12:43:57.432418 DQM0 = 82, DQM1 = 71
1884 12:43:57.435561 DQ Delay:
1885 12:43:57.438731 DQ0 =84, DQ1 =80, DQ2 =72, DQ3 =80
1886 12:43:57.442182 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =80
1887 12:43:57.445427 DQ8 =56, DQ9 =56, DQ10 =72, DQ11 =64
1888 12:43:57.449306 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =80
1889 12:43:57.449388
1890 12:43:57.449452
1891 12:43:57.455380 [DQSOSCAuto] RK1, (LSB)MR18= 0x4141, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1892 12:43:57.458853 CH1 RK1: MR19=606, MR18=4141
1893 12:43:57.465978 CH1_RK1: MR19=0x606, MR18=0x4141, DQSOSC=393, MR23=63, INC=95, DEC=63
1894 12:43:57.468878 [RxdqsGatingPostProcess] freq 800
1895 12:43:57.474268 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1896 12:43:57.476196 Pre-setting of DQS Precalculation
1897 12:43:57.481971 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1898 12:43:57.488702 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1899 12:43:57.496699 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1900 12:43:57.496822
1901 12:43:57.496907
1902 12:43:57.499230 [Calibration Summary] 1600 Mbps
1903 12:43:57.499313 CH 0, Rank 0
1904 12:43:57.502545 SW Impedance : PASS
1905 12:43:57.505831 DUTY Scan : NO K
1906 12:43:57.505939 ZQ Calibration : PASS
1907 12:43:57.508860 Jitter Meter : NO K
1908 12:43:57.508944 CBT Training : PASS
1909 12:43:57.512365 Write leveling : PASS
1910 12:43:57.515279 RX DQS gating : PASS
1911 12:43:57.515363 RX DQ/DQS(RDDQC) : PASS
1912 12:43:57.519928 TX DQ/DQS : PASS
1913 12:43:57.522626 RX DATLAT : PASS
1914 12:43:57.522709 RX DQ/DQS(Engine): PASS
1915 12:43:57.526154 TX OE : NO K
1916 12:43:57.526241 All Pass.
1917 12:43:57.526326
1918 12:43:57.528398 CH 0, Rank 1
1919 12:43:57.528483 SW Impedance : PASS
1920 12:43:57.532401 DUTY Scan : NO K
1921 12:43:57.535592 ZQ Calibration : PASS
1922 12:43:57.535675 Jitter Meter : NO K
1923 12:43:57.538684 CBT Training : PASS
1924 12:43:57.542614 Write leveling : PASS
1925 12:43:57.542697 RX DQS gating : PASS
1926 12:43:57.545160 RX DQ/DQS(RDDQC) : PASS
1927 12:43:57.548619 TX DQ/DQS : PASS
1928 12:43:57.548703 RX DATLAT : PASS
1929 12:43:57.551814 RX DQ/DQS(Engine): PASS
1930 12:43:57.555362 TX OE : NO K
1931 12:43:57.555446 All Pass.
1932 12:43:57.555530
1933 12:43:57.555610 CH 1, Rank 0
1934 12:43:57.558215 SW Impedance : PASS
1935 12:43:57.561623 DUTY Scan : NO K
1936 12:43:57.561706 ZQ Calibration : PASS
1937 12:43:57.565540 Jitter Meter : NO K
1938 12:43:57.565623 CBT Training : PASS
1939 12:43:57.568761 Write leveling : PASS
1940 12:43:57.572659 RX DQS gating : PASS
1941 12:43:57.572751 RX DQ/DQS(RDDQC) : PASS
1942 12:43:57.575282 TX DQ/DQS : PASS
1943 12:43:57.579129 RX DATLAT : PASS
1944 12:43:57.579212 RX DQ/DQS(Engine): PASS
1945 12:43:57.582282 TX OE : NO K
1946 12:43:57.582365 All Pass.
1947 12:43:57.582450
1948 12:43:57.586246 CH 1, Rank 1
1949 12:43:57.586330 SW Impedance : PASS
1950 12:43:57.589809 DUTY Scan : NO K
1951 12:43:57.592065 ZQ Calibration : PASS
1952 12:43:57.592149 Jitter Meter : NO K
1953 12:43:57.595343 CBT Training : PASS
1954 12:43:57.599428 Write leveling : PASS
1955 12:43:57.599511 RX DQS gating : PASS
1956 12:43:57.602226 RX DQ/DQS(RDDQC) : PASS
1957 12:43:57.602309 TX DQ/DQS : PASS
1958 12:43:57.605242 RX DATLAT : PASS
1959 12:43:57.608858 RX DQ/DQS(Engine): PASS
1960 12:43:57.608942 TX OE : NO K
1961 12:43:57.612636 All Pass.
1962 12:43:57.612742
1963 12:43:57.612842 DramC Write-DBI off
1964 12:43:57.615625 PER_BANK_REFRESH: Hybrid Mode
1965 12:43:57.618820 TX_TRACKING: ON
1966 12:43:57.622196 [GetDramInforAfterCalByMRR] Vendor 6.
1967 12:43:57.625296 [GetDramInforAfterCalByMRR] Revision 606.
1968 12:43:57.628759 [GetDramInforAfterCalByMRR] Revision 2 0.
1969 12:43:57.628856 MR0 0x3939
1970 12:43:57.628941 MR8 0x1111
1971 12:43:57.635114 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1972 12:43:57.635198
1973 12:43:57.635282 MR0 0x3939
1974 12:43:57.635362 MR8 0x1111
1975 12:43:57.638295 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1976 12:43:57.638379
1977 12:43:57.648625 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1978 12:43:57.652840 [FAST_K] Save calibration result to emmc
1979 12:43:57.655483 [FAST_K] Save calibration result to emmc
1980 12:43:57.658857 dram_init: config_dvfs: 1
1981 12:43:57.661807 dramc_set_vcore_voltage set vcore to 662500
1982 12:43:57.665017 Read voltage for 1200, 2
1983 12:43:57.665100 Vio18 = 0
1984 12:43:57.665185 Vcore = 662500
1985 12:43:57.668427 Vdram = 0
1986 12:43:57.668510 Vddq = 0
1987 12:43:57.668610 Vmddr = 0
1988 12:43:57.675342 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1989 12:43:57.678838 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1990 12:43:57.682132 MEM_TYPE=3, freq_sel=15
1991 12:43:57.685201 sv_algorithm_assistance_LP4_1600
1992 12:43:57.688728 ============ PULL DRAM RESETB DOWN ============
1993 12:43:57.692340 ========== PULL DRAM RESETB DOWN end =========
1994 12:43:57.698518 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1995 12:43:57.702073 ===================================
1996 12:43:57.702155 LPDDR4 DRAM CONFIGURATION
1997 12:43:57.705640 ===================================
1998 12:43:57.708555 EX_ROW_EN[0] = 0x0
1999 12:43:57.711771 EX_ROW_EN[1] = 0x0
2000 12:43:57.711852 LP4Y_EN = 0x0
2001 12:43:57.715428 WORK_FSP = 0x0
2002 12:43:57.715509 WL = 0x4
2003 12:43:57.718545 RL = 0x4
2004 12:43:57.718626 BL = 0x2
2005 12:43:57.722639 RPST = 0x0
2006 12:43:57.722720 RD_PRE = 0x0
2007 12:43:57.725229 WR_PRE = 0x1
2008 12:43:57.725310 WR_PST = 0x0
2009 12:43:57.728468 DBI_WR = 0x0
2010 12:43:57.728549 DBI_RD = 0x0
2011 12:43:57.732442 OTF = 0x1
2012 12:43:57.735466 ===================================
2013 12:43:57.738425 ===================================
2014 12:43:57.738506 ANA top config
2015 12:43:57.741599 ===================================
2016 12:43:57.744910 DLL_ASYNC_EN = 0
2017 12:43:57.749026 ALL_SLAVE_EN = 0
2018 12:43:57.751568 NEW_RANK_MODE = 1
2019 12:43:57.751649 DLL_IDLE_MODE = 1
2020 12:43:57.755930 LP45_APHY_COMB_EN = 1
2021 12:43:57.758276 TX_ODT_DIS = 1
2022 12:43:57.761561 NEW_8X_MODE = 1
2023 12:43:57.764964 ===================================
2024 12:43:57.768649 ===================================
2025 12:43:57.771877 data_rate = 2400
2026 12:43:57.771958 CKR = 1
2027 12:43:57.775090 DQ_P2S_RATIO = 8
2028 12:43:57.778095 ===================================
2029 12:43:57.781916 CA_P2S_RATIO = 8
2030 12:43:57.784551 DQ_CA_OPEN = 0
2031 12:43:57.788439 DQ_SEMI_OPEN = 0
2032 12:43:57.791515 CA_SEMI_OPEN = 0
2033 12:43:57.791596 CA_FULL_RATE = 0
2034 12:43:57.794943 DQ_CKDIV4_EN = 0
2035 12:43:57.798153 CA_CKDIV4_EN = 0
2036 12:43:57.802365 CA_PREDIV_EN = 0
2037 12:43:57.804565 PH8_DLY = 17
2038 12:43:57.808916 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2039 12:43:57.808998 DQ_AAMCK_DIV = 4
2040 12:43:57.811456 CA_AAMCK_DIV = 4
2041 12:43:57.815044 CA_ADMCK_DIV = 4
2042 12:43:57.818626 DQ_TRACK_CA_EN = 0
2043 12:43:57.820993 CA_PICK = 1200
2044 12:43:57.825072 CA_MCKIO = 1200
2045 12:43:57.828194 MCKIO_SEMI = 0
2046 12:43:57.831643 PLL_FREQ = 2366
2047 12:43:57.831724 DQ_UI_PI_RATIO = 32
2048 12:43:57.834817 CA_UI_PI_RATIO = 0
2049 12:43:57.838423 ===================================
2050 12:43:57.841138 ===================================
2051 12:43:57.844661 memory_type:LPDDR4
2052 12:43:57.849287 GP_NUM : 10
2053 12:43:57.849369 SRAM_EN : 1
2054 12:43:57.851006 MD32_EN : 0
2055 12:43:57.854483 ===================================
2056 12:43:57.854564 [ANA_INIT] >>>>>>>>>>>>>>
2057 12:43:57.857679 <<<<<< [CONFIGURE PHASE]: ANA_TX
2058 12:43:57.861195 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2059 12:43:57.864740 ===================================
2060 12:43:57.868099 data_rate = 2400,PCW = 0X5b00
2061 12:43:57.871529 ===================================
2062 12:43:57.875514 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2063 12:43:57.880927 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2064 12:43:57.884662 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2065 12:43:57.891977 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2066 12:43:57.894819 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2067 12:43:57.897743 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2068 12:43:57.901403 [ANA_INIT] flow start
2069 12:43:57.901483 [ANA_INIT] PLL >>>>>>>>
2070 12:43:57.904600 [ANA_INIT] PLL <<<<<<<<
2071 12:43:57.907618 [ANA_INIT] MIDPI >>>>>>>>
2072 12:43:57.907700 [ANA_INIT] MIDPI <<<<<<<<
2073 12:43:57.911103 [ANA_INIT] DLL >>>>>>>>
2074 12:43:57.914711 [ANA_INIT] DLL <<<<<<<<
2075 12:43:57.914791 [ANA_INIT] flow end
2076 12:43:57.917990 ============ LP4 DIFF to SE enter ============
2077 12:43:57.924415 ============ LP4 DIFF to SE exit ============
2078 12:43:57.924497 [ANA_INIT] <<<<<<<<<<<<<
2079 12:43:57.928212 [Flow] Enable top DCM control >>>>>
2080 12:43:57.930912 [Flow] Enable top DCM control <<<<<
2081 12:43:57.934200 Enable DLL master slave shuffle
2082 12:43:57.940625 ==============================================================
2083 12:43:57.940737 Gating Mode config
2084 12:43:57.948662 ==============================================================
2085 12:43:57.951023 Config description:
2086 12:43:57.960783 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2087 12:43:57.967472 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2088 12:43:57.972220 SELPH_MODE 0: By rank 1: By Phase
2089 12:43:57.977223 ==============================================================
2090 12:43:57.980883 GAT_TRACK_EN = 1
2091 12:43:57.984721 RX_GATING_MODE = 2
2092 12:43:57.984806 RX_GATING_TRACK_MODE = 2
2093 12:43:57.987825 SELPH_MODE = 1
2094 12:43:57.990859 PICG_EARLY_EN = 1
2095 12:43:57.994991 VALID_LAT_VALUE = 1
2096 12:43:58.000899 ==============================================================
2097 12:43:58.003879 Enter into Gating configuration >>>>
2098 12:43:58.009880 Exit from Gating configuration <<<<
2099 12:43:58.010764 Enter into DVFS_PRE_config >>>>>
2100 12:43:58.020624 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2101 12:43:58.024079 Exit from DVFS_PRE_config <<<<<
2102 12:43:58.027811 Enter into PICG configuration >>>>
2103 12:43:58.030890 Exit from PICG configuration <<<<
2104 12:43:58.034039 [RX_INPUT] configuration >>>>>
2105 12:43:58.038280 [RX_INPUT] configuration <<<<<
2106 12:43:58.041331 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2107 12:43:58.047697 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2108 12:43:58.054658 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2109 12:43:58.058129 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2110 12:43:58.065614 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2111 12:43:58.071026 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2112 12:43:58.073980 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2113 12:43:58.077699 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2114 12:43:58.084059 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2115 12:43:58.087487 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2116 12:43:58.090898 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2117 12:43:58.097853 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2118 12:43:58.101140 ===================================
2119 12:43:58.101222 LPDDR4 DRAM CONFIGURATION
2120 12:43:58.104322 ===================================
2121 12:43:58.107512 EX_ROW_EN[0] = 0x0
2122 12:43:58.111722 EX_ROW_EN[1] = 0x0
2123 12:43:58.111804 LP4Y_EN = 0x0
2124 12:43:58.114802 WORK_FSP = 0x0
2125 12:43:58.114883 WL = 0x4
2126 12:43:58.117659 RL = 0x4
2127 12:43:58.117741 BL = 0x2
2128 12:43:58.120391 RPST = 0x0
2129 12:43:58.120473 RD_PRE = 0x0
2130 12:43:58.123866 WR_PRE = 0x1
2131 12:43:58.123948 WR_PST = 0x0
2132 12:43:58.127393 DBI_WR = 0x0
2133 12:43:58.127475 DBI_RD = 0x0
2134 12:43:58.130861 OTF = 0x1
2135 12:43:58.133758 ===================================
2136 12:43:58.137327 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2137 12:43:58.140678 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2138 12:43:58.147459 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2139 12:43:58.151909 ===================================
2140 12:43:58.151992 LPDDR4 DRAM CONFIGURATION
2141 12:43:58.153701 ===================================
2142 12:43:58.156994 EX_ROW_EN[0] = 0x10
2143 12:43:58.157075 EX_ROW_EN[1] = 0x0
2144 12:43:58.160718 LP4Y_EN = 0x0
2145 12:43:58.160832 WORK_FSP = 0x0
2146 12:43:58.164048 WL = 0x4
2147 12:43:58.164128 RL = 0x4
2148 12:43:58.167489 BL = 0x2
2149 12:43:58.170772 RPST = 0x0
2150 12:43:58.170852 RD_PRE = 0x0
2151 12:43:58.173857 WR_PRE = 0x1
2152 12:43:58.173937 WR_PST = 0x0
2153 12:43:58.177518 DBI_WR = 0x0
2154 12:43:58.177599 DBI_RD = 0x0
2155 12:43:58.180839 OTF = 0x1
2156 12:43:58.184430 ===================================
2157 12:43:58.188428 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2158 12:43:58.190853 ==
2159 12:43:58.194036 Dram Type= 6, Freq= 0, CH_0, rank 0
2160 12:43:58.197130 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2161 12:43:58.197211 ==
2162 12:43:58.200929 [Duty_Offset_Calibration]
2163 12:43:58.201009 B0:0 B1:2 CA:1
2164 12:43:58.201075
2165 12:43:58.204422 [DutyScan_Calibration_Flow] k_type=0
2166 12:43:58.213867
2167 12:43:58.213949 ==CLK 0==
2168 12:43:58.216888 Final CLK duty delay cell = 0
2169 12:43:58.219615 [0] MAX Duty = 5093%(X100), DQS PI = 12
2170 12:43:58.222883 [0] MIN Duty = 4938%(X100), DQS PI = 52
2171 12:43:58.226213 [0] AVG Duty = 5015%(X100)
2172 12:43:58.226295
2173 12:43:58.230408 CH0 CLK Duty spec in!! Max-Min= 155%
2174 12:43:58.233170 [DutyScan_Calibration_Flow] ====Done====
2175 12:43:58.233250
2176 12:43:58.237090 [DutyScan_Calibration_Flow] k_type=1
2177 12:43:58.252525
2178 12:43:58.252605 ==DQS 0 ==
2179 12:43:58.256328 Final DQS duty delay cell = 0
2180 12:43:58.259195 [0] MAX Duty = 5125%(X100), DQS PI = 30
2181 12:43:58.263210 [0] MIN Duty = 5031%(X100), DQS PI = 6
2182 12:43:58.263291 [0] AVG Duty = 5078%(X100)
2183 12:43:58.266560
2184 12:43:58.266640 ==DQS 1 ==
2185 12:43:58.269594 Final DQS duty delay cell = 0
2186 12:43:58.272436 [0] MAX Duty = 5062%(X100), DQS PI = 58
2187 12:43:58.275618 [0] MIN Duty = 4906%(X100), DQS PI = 14
2188 12:43:58.279047 [0] AVG Duty = 4984%(X100)
2189 12:43:58.279127
2190 12:43:58.282597 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2191 12:43:58.282678
2192 12:43:58.285635 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2193 12:43:58.289656 [DutyScan_Calibration_Flow] ====Done====
2194 12:43:58.289754
2195 12:43:58.293058 [DutyScan_Calibration_Flow] k_type=3
2196 12:43:58.309087
2197 12:43:58.309169 ==DQM 0 ==
2198 12:43:58.312360 Final DQM duty delay cell = 0
2199 12:43:58.315860 [0] MAX Duty = 5187%(X100), DQS PI = 22
2200 12:43:58.319276 [0] MIN Duty = 4969%(X100), DQS PI = 56
2201 12:43:58.322348 [0] AVG Duty = 5078%(X100)
2202 12:43:58.322430
2203 12:43:58.322493 ==DQM 1 ==
2204 12:43:58.325971 Final DQM duty delay cell = 0
2205 12:43:58.329835 [0] MAX Duty = 5000%(X100), DQS PI = 56
2206 12:43:58.332304 [0] MIN Duty = 4844%(X100), DQS PI = 0
2207 12:43:58.332386 [0] AVG Duty = 4922%(X100)
2208 12:43:58.335467
2209 12:43:58.339114 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2210 12:43:58.339195
2211 12:43:58.342453 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2212 12:43:58.345972 [DutyScan_Calibration_Flow] ====Done====
2213 12:43:58.346052
2214 12:43:58.348792 [DutyScan_Calibration_Flow] k_type=2
2215 12:43:58.364244
2216 12:43:58.364325 ==DQ 0 ==
2217 12:43:58.366967 Final DQ duty delay cell = -4
2218 12:43:58.370966 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2219 12:43:58.373618 [-4] MIN Duty = 4813%(X100), DQS PI = 54
2220 12:43:58.377019 [-4] AVG Duty = 4937%(X100)
2221 12:43:58.377100
2222 12:43:58.377163 ==DQ 1 ==
2223 12:43:58.380530 Final DQ duty delay cell = -4
2224 12:43:58.385518 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2225 12:43:58.388028 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2226 12:43:58.390276 [-4] AVG Duty = 4969%(X100)
2227 12:43:58.390357
2228 12:43:58.393764 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2229 12:43:58.393845
2230 12:43:58.397149 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2231 12:43:58.400409 [DutyScan_Calibration_Flow] ====Done====
2232 12:43:58.400490 ==
2233 12:43:58.403992 Dram Type= 6, Freq= 0, CH_1, rank 0
2234 12:43:58.407484 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2235 12:43:58.407566 ==
2236 12:43:58.410858 [Duty_Offset_Calibration]
2237 12:43:58.410938 B0:0 B1:4 CA:-5
2238 12:43:58.411002
2239 12:43:58.414445 [DutyScan_Calibration_Flow] k_type=0
2240 12:43:58.424863
2241 12:43:58.424944 ==CLK 0==
2242 12:43:58.428866 Final CLK duty delay cell = 0
2243 12:43:58.431049 [0] MAX Duty = 5093%(X100), DQS PI = 42
2244 12:43:58.434841 [0] MIN Duty = 4907%(X100), DQS PI = 12
2245 12:43:58.434922 [0] AVG Duty = 5000%(X100)
2246 12:43:58.437845
2247 12:43:58.440966 CH1 CLK Duty spec in!! Max-Min= 186%
2248 12:43:58.444497 [DutyScan_Calibration_Flow] ====Done====
2249 12:43:58.444577
2250 12:43:58.447839 [DutyScan_Calibration_Flow] k_type=1
2251 12:43:58.463491
2252 12:43:58.463572 ==DQS 0 ==
2253 12:43:58.466633 Final DQS duty delay cell = 0
2254 12:43:58.470233 [0] MAX Duty = 5124%(X100), DQS PI = 48
2255 12:43:58.473373 [0] MIN Duty = 4875%(X100), DQS PI = 8
2256 12:43:58.473454 [0] AVG Duty = 4999%(X100)
2257 12:43:58.476278
2258 12:43:58.476358 ==DQS 1 ==
2259 12:43:58.480034 Final DQS duty delay cell = -4
2260 12:43:58.483711 [-4] MAX Duty = 5031%(X100), DQS PI = 36
2261 12:43:58.486690 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2262 12:43:58.489504 [-4] AVG Duty = 4969%(X100)
2263 12:43:58.489585
2264 12:43:58.493143 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2265 12:43:58.493223
2266 12:43:58.497630 CH1 DQS 1 Duty spec in!! Max-Min= 124%
2267 12:43:58.499406 [DutyScan_Calibration_Flow] ====Done====
2268 12:43:58.499487
2269 12:43:58.503089 [DutyScan_Calibration_Flow] k_type=3
2270 12:43:58.518575
2271 12:43:58.518658 ==DQM 0 ==
2272 12:43:58.521671 Final DQM duty delay cell = -4
2273 12:43:58.525015 [-4] MAX Duty = 5062%(X100), DQS PI = 0
2274 12:43:58.529500 [-4] MIN Duty = 4875%(X100), DQS PI = 6
2275 12:43:58.531728 [-4] AVG Duty = 4968%(X100)
2276 12:43:58.531819
2277 12:43:58.531884 ==DQM 1 ==
2278 12:43:58.535459 Final DQM duty delay cell = -4
2279 12:43:58.538216 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2280 12:43:58.542047 [-4] MIN Duty = 4907%(X100), DQS PI = 14
2281 12:43:58.545556 [-4] AVG Duty = 4984%(X100)
2282 12:43:58.545637
2283 12:43:58.548563 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2284 12:43:58.548644
2285 12:43:58.551611 CH1 DQM 1 Duty spec in!! Max-Min= 155%
2286 12:43:58.555122 [DutyScan_Calibration_Flow] ====Done====
2287 12:43:58.555204
2288 12:43:58.558299 [DutyScan_Calibration_Flow] k_type=2
2289 12:43:58.575790
2290 12:43:58.575872 ==DQ 0 ==
2291 12:43:58.578783 Final DQ duty delay cell = 0
2292 12:43:58.582857 [0] MAX Duty = 5093%(X100), DQS PI = 32
2293 12:43:58.585258 [0] MIN Duty = 4969%(X100), DQS PI = 12
2294 12:43:58.585339 [0] AVG Duty = 5031%(X100)
2295 12:43:58.585404
2296 12:43:58.589177 ==DQ 1 ==
2297 12:43:58.592787 Final DQ duty delay cell = 0
2298 12:43:58.595565 [0] MAX Duty = 5031%(X100), DQS PI = 38
2299 12:43:58.599130 [0] MIN Duty = 4875%(X100), DQS PI = 0
2300 12:43:58.599223 [0] AVG Duty = 4953%(X100)
2301 12:43:58.599299
2302 12:43:58.602496 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2303 12:43:58.602577
2304 12:43:58.605487 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2305 12:43:58.612385 [DutyScan_Calibration_Flow] ====Done====
2306 12:43:58.615557 nWR fixed to 30
2307 12:43:58.615638 [ModeRegInit_LP4] CH0 RK0
2308 12:43:58.618575 [ModeRegInit_LP4] CH0 RK1
2309 12:43:58.622120 [ModeRegInit_LP4] CH1 RK0
2310 12:43:58.622201 [ModeRegInit_LP4] CH1 RK1
2311 12:43:58.626724 match AC timing 6
2312 12:43:58.629048 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2313 12:43:58.632733 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2314 12:43:58.639507 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2315 12:43:58.642068 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2316 12:43:58.649084 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2317 12:43:58.649165 ==
2318 12:43:58.651996 Dram Type= 6, Freq= 0, CH_0, rank 0
2319 12:43:58.655827 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2320 12:43:58.655911 ==
2321 12:43:58.662386 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2322 12:43:58.665466 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2323 12:43:58.675688 [CA 0] Center 39 (9~70) winsize 62
2324 12:43:58.678410 [CA 1] Center 39 (8~70) winsize 63
2325 12:43:58.682192 [CA 2] Center 36 (5~67) winsize 63
2326 12:43:58.685313 [CA 3] Center 35 (5~66) winsize 62
2327 12:43:58.688691 [CA 4] Center 34 (3~65) winsize 63
2328 12:43:58.691878 [CA 5] Center 33 (3~64) winsize 62
2329 12:43:58.691996
2330 12:43:58.695182 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2331 12:43:58.695263
2332 12:43:58.698784 [CATrainingPosCal] consider 1 rank data
2333 12:43:58.702198 u2DelayCellTimex100 = 270/100 ps
2334 12:43:58.705472 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2335 12:43:58.708719 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2336 12:43:58.716481 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2337 12:43:58.718362 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2338 12:43:58.721761 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2339 12:43:58.725459 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2340 12:43:58.725540
2341 12:43:58.730692 CA PerBit enable=1, Macro0, CA PI delay=33
2342 12:43:58.730773
2343 12:43:58.731934 [CBTSetCACLKResult] CA Dly = 33
2344 12:43:58.732014 CS Dly: 7 (0~38)
2345 12:43:58.735251 ==
2346 12:43:58.735333 Dram Type= 6, Freq= 0, CH_0, rank 1
2347 12:43:58.742383 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2348 12:43:58.742465 ==
2349 12:43:58.745750 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2350 12:43:58.752025 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2351 12:43:58.760928 [CA 0] Center 39 (8~70) winsize 63
2352 12:43:58.764922 [CA 1] Center 39 (8~70) winsize 63
2353 12:43:58.767213 [CA 2] Center 36 (5~67) winsize 63
2354 12:43:58.770632 [CA 3] Center 35 (4~66) winsize 63
2355 12:43:58.773985 [CA 4] Center 33 (3~64) winsize 62
2356 12:43:58.777646 [CA 5] Center 34 (3~65) winsize 63
2357 12:43:58.777728
2358 12:43:58.780714 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2359 12:43:58.780810
2360 12:43:58.784187 [CATrainingPosCal] consider 2 rank data
2361 12:43:58.787389 u2DelayCellTimex100 = 270/100 ps
2362 12:43:58.791120 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2363 12:43:58.794448 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2364 12:43:58.800973 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2365 12:43:58.803871 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2366 12:43:58.807325 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2367 12:43:58.810957 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2368 12:43:58.811039
2369 12:43:58.814539 CA PerBit enable=1, Macro0, CA PI delay=33
2370 12:43:58.814621
2371 12:43:58.817617 [CBTSetCACLKResult] CA Dly = 33
2372 12:43:58.817698 CS Dly: 8 (0~40)
2373 12:43:58.817762
2374 12:43:58.820812 ----->DramcWriteLeveling(PI) begin...
2375 12:43:58.824262 ==
2376 12:43:58.827578 Dram Type= 6, Freq= 0, CH_0, rank 0
2377 12:43:58.831006 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2378 12:43:58.831087 ==
2379 12:43:58.834729 Write leveling (Byte 0): 28 => 28
2380 12:43:58.837619 Write leveling (Byte 1): 26 => 26
2381 12:43:58.840816 DramcWriteLeveling(PI) end<-----
2382 12:43:58.840898
2383 12:43:58.840961 ==
2384 12:43:58.844556 Dram Type= 6, Freq= 0, CH_0, rank 0
2385 12:43:58.847300 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2386 12:43:58.847382 ==
2387 12:43:58.850412 [Gating] SW mode calibration
2388 12:43:58.857124 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2389 12:43:58.860780 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2390 12:43:58.867020 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2391 12:43:58.870849 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2392 12:43:58.873733 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2393 12:43:58.881512 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2394 12:43:58.884105 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2395 12:43:58.887525 0 11 20 | B1->B0 | 3030 2c2c | 1 0 | (1 0) (0 0)
2396 12:43:58.893875 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2397 12:43:58.897881 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2398 12:43:58.900366 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2399 12:43:58.907567 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2400 12:43:58.910481 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2401 12:43:58.913663 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2402 12:43:58.920407 0 12 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2403 12:43:58.924146 0 12 20 | B1->B0 | 3a3a 4040 | 0 0 | (1 1) (0 0)
2404 12:43:58.927424 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2405 12:43:58.933856 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2406 12:43:58.937010 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2407 12:43:58.940407 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2408 12:43:58.947299 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2409 12:43:58.950992 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2410 12:43:58.953591 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2411 12:43:58.960596 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2412 12:43:58.964385 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2413 12:43:58.967225 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2414 12:43:58.970785 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2415 12:43:58.977011 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2416 12:43:58.980597 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2417 12:43:58.983984 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2418 12:43:58.990205 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2419 12:43:58.994140 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2420 12:43:58.996882 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2421 12:43:59.003527 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2422 12:43:59.007002 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2423 12:43:59.010469 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2424 12:43:59.017549 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2425 12:43:59.021141 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2426 12:43:59.023790 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2427 12:43:59.030554 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2428 12:43:59.033817 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2429 12:43:59.037194 Total UI for P1: 0, mck2ui 16
2430 12:43:59.043253 best dqsien dly found for B0: ( 0, 15, 18)
2431 12:43:59.044391 Total UI for P1: 0, mck2ui 16
2432 12:43:59.047237 best dqsien dly found for B1: ( 0, 15, 20)
2433 12:43:59.050715 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2434 12:43:59.053797 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2435 12:43:59.053879
2436 12:43:59.057886 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2437 12:43:59.061700 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2438 12:43:59.063604 [Gating] SW calibration Done
2439 12:43:59.063686 ==
2440 12:43:59.067575 Dram Type= 6, Freq= 0, CH_0, rank 0
2441 12:43:59.071422 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2442 12:43:59.073567 ==
2443 12:43:59.073649 RX Vref Scan: 0
2444 12:43:59.073714
2445 12:43:59.076763 RX Vref 0 -> 0, step: 1
2446 12:43:59.076846
2447 12:43:59.076911 RX Delay -40 -> 252, step: 8
2448 12:43:59.083678 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2449 12:43:59.088345 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2450 12:43:59.091093 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2451 12:43:59.094475 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2452 12:43:59.098004 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2453 12:43:59.103869 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2454 12:43:59.106878 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2455 12:43:59.110784 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2456 12:43:59.114097 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2457 12:43:59.117194 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2458 12:43:59.124162 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2459 12:43:59.127674 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2460 12:43:59.130487 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2461 12:43:59.133883 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2462 12:43:59.137630 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2463 12:43:59.144152 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2464 12:43:59.144234 ==
2465 12:43:59.147228 Dram Type= 6, Freq= 0, CH_0, rank 0
2466 12:43:59.150884 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2467 12:43:59.150970 ==
2468 12:43:59.151036 DQS Delay:
2469 12:43:59.154267 DQS0 = 0, DQS1 = 0
2470 12:43:59.154349 DQM Delay:
2471 12:43:59.157394 DQM0 = 115, DQM1 = 106
2472 12:43:59.157475 DQ Delay:
2473 12:43:59.160855 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2474 12:43:59.164743 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2475 12:43:59.167096 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2476 12:43:59.171015 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2477 12:43:59.171098
2478 12:43:59.171162
2479 12:43:59.173865 ==
2480 12:43:59.173948 Dram Type= 6, Freq= 0, CH_0, rank 0
2481 12:43:59.180428 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2482 12:43:59.180510 ==
2483 12:43:59.180574
2484 12:43:59.180634
2485 12:43:59.183630 TX Vref Scan disable
2486 12:43:59.183711 == TX Byte 0 ==
2487 12:43:59.187133 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2488 12:43:59.193788 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2489 12:43:59.193870 == TX Byte 1 ==
2490 12:43:59.196897 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2491 12:43:59.203925 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2492 12:43:59.204007 ==
2493 12:43:59.207180 Dram Type= 6, Freq= 0, CH_0, rank 0
2494 12:43:59.210003 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2495 12:43:59.210095 ==
2496 12:43:59.222323 TX Vref=22, minBit 8, minWin=25, winSum=417
2497 12:43:59.225733 TX Vref=24, minBit 13, minWin=24, winSum=418
2498 12:43:59.229317 TX Vref=26, minBit 8, minWin=25, winSum=425
2499 12:43:59.232575 TX Vref=28, minBit 8, minWin=26, winSum=433
2500 12:43:59.235610 TX Vref=30, minBit 8, minWin=26, winSum=434
2501 12:43:59.242575 TX Vref=32, minBit 8, minWin=26, winSum=432
2502 12:43:59.245598 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 30
2503 12:43:59.245704
2504 12:43:59.249057 Final TX Range 1 Vref 30
2505 12:43:59.249140
2506 12:43:59.249203 ==
2507 12:43:59.252113 Dram Type= 6, Freq= 0, CH_0, rank 0
2508 12:43:59.256496 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2509 12:43:59.258991 ==
2510 12:43:59.259095
2511 12:43:59.259185
2512 12:43:59.259270 TX Vref Scan disable
2513 12:43:59.261844 == TX Byte 0 ==
2514 12:43:59.265618 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2515 12:43:59.268685 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2516 12:43:59.272655 == TX Byte 1 ==
2517 12:43:59.276901 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2518 12:43:59.282424 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2519 12:43:59.282495
2520 12:43:59.282569 [DATLAT]
2521 12:43:59.282632 Freq=1200, CH0 RK0
2522 12:43:59.282690
2523 12:43:59.285432 DATLAT Default: 0xd
2524 12:43:59.285500 0, 0xFFFF, sum = 0
2525 12:43:59.288273 1, 0xFFFF, sum = 0
2526 12:43:59.288376 2, 0xFFFF, sum = 0
2527 12:43:59.291910 3, 0xFFFF, sum = 0
2528 12:43:59.296099 4, 0xFFFF, sum = 0
2529 12:43:59.296195 5, 0xFFFF, sum = 0
2530 12:43:59.299459 6, 0xFFFF, sum = 0
2531 12:43:59.299564 7, 0xFFFF, sum = 0
2532 12:43:59.302148 8, 0xFFFF, sum = 0
2533 12:43:59.302246 9, 0xFFFF, sum = 0
2534 12:43:59.305669 10, 0xFFFF, sum = 0
2535 12:43:59.305771 11, 0x0, sum = 1
2536 12:43:59.308765 12, 0x0, sum = 2
2537 12:43:59.308868 13, 0x0, sum = 3
2538 12:43:59.308944 14, 0x0, sum = 4
2539 12:43:59.312401 best_step = 12
2540 12:43:59.312502
2541 12:43:59.312589 ==
2542 12:43:59.315419 Dram Type= 6, Freq= 0, CH_0, rank 0
2543 12:43:59.318876 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2544 12:43:59.318988 ==
2545 12:43:59.322108 RX Vref Scan: 1
2546 12:43:59.322191
2547 12:43:59.325715 Set Vref Range= 32 -> 127
2548 12:43:59.325813
2549 12:43:59.325902 RX Vref 32 -> 127, step: 1
2550 12:43:59.325999
2551 12:43:59.328555 RX Delay -21 -> 252, step: 4
2552 12:43:59.328650
2553 12:43:59.331791 Set Vref, RX VrefLevel [Byte0]: 32
2554 12:43:59.336510 [Byte1]: 32
2555 12:43:59.338756
2556 12:43:59.338859 Set Vref, RX VrefLevel [Byte0]: 33
2557 12:43:59.342302 [Byte1]: 33
2558 12:43:59.346769
2559 12:43:59.346843 Set Vref, RX VrefLevel [Byte0]: 34
2560 12:43:59.349609 [Byte1]: 34
2561 12:43:59.355486
2562 12:43:59.355582 Set Vref, RX VrefLevel [Byte0]: 35
2563 12:43:59.358161 [Byte1]: 35
2564 12:43:59.362482
2565 12:43:59.362577 Set Vref, RX VrefLevel [Byte0]: 36
2566 12:43:59.365932 [Byte1]: 36
2567 12:43:59.370675
2568 12:43:59.370771 Set Vref, RX VrefLevel [Byte0]: 37
2569 12:43:59.373999 [Byte1]: 37
2570 12:43:59.378431
2571 12:43:59.378500 Set Vref, RX VrefLevel [Byte0]: 38
2572 12:43:59.382286 [Byte1]: 38
2573 12:43:59.386726
2574 12:43:59.386827 Set Vref, RX VrefLevel [Byte0]: 39
2575 12:43:59.389919 [Byte1]: 39
2576 12:43:59.394153
2577 12:43:59.394255 Set Vref, RX VrefLevel [Byte0]: 40
2578 12:43:59.397464 [Byte1]: 40
2579 12:43:59.402408
2580 12:43:59.402505 Set Vref, RX VrefLevel [Byte0]: 41
2581 12:43:59.405616 [Byte1]: 41
2582 12:43:59.409903
2583 12:43:59.409975 Set Vref, RX VrefLevel [Byte0]: 42
2584 12:43:59.413739 [Byte1]: 42
2585 12:43:59.417808
2586 12:43:59.417880 Set Vref, RX VrefLevel [Byte0]: 43
2587 12:43:59.421775 [Byte1]: 43
2588 12:43:59.425833
2589 12:43:59.425904 Set Vref, RX VrefLevel [Byte0]: 44
2590 12:43:59.429166 [Byte1]: 44
2591 12:43:59.433653
2592 12:43:59.433729 Set Vref, RX VrefLevel [Byte0]: 45
2593 12:43:59.437282 [Byte1]: 45
2594 12:43:59.441524
2595 12:43:59.441594 Set Vref, RX VrefLevel [Byte0]: 46
2596 12:43:59.445477 [Byte1]: 46
2597 12:43:59.449937
2598 12:43:59.450036 Set Vref, RX VrefLevel [Byte0]: 47
2599 12:43:59.453060 [Byte1]: 47
2600 12:43:59.457395
2601 12:43:59.457499 Set Vref, RX VrefLevel [Byte0]: 48
2602 12:43:59.460624 [Byte1]: 48
2603 12:43:59.465657
2604 12:43:59.465756 Set Vref, RX VrefLevel [Byte0]: 49
2605 12:43:59.469080 [Byte1]: 49
2606 12:43:59.473384
2607 12:43:59.473480 Set Vref, RX VrefLevel [Byte0]: 50
2608 12:43:59.477434 [Byte1]: 50
2609 12:43:59.481593
2610 12:43:59.481661 Set Vref, RX VrefLevel [Byte0]: 51
2611 12:43:59.484655 [Byte1]: 51
2612 12:43:59.489643
2613 12:43:59.489750 Set Vref, RX VrefLevel [Byte0]: 52
2614 12:43:59.492955 [Byte1]: 52
2615 12:43:59.497282
2616 12:43:59.497351 Set Vref, RX VrefLevel [Byte0]: 53
2617 12:43:59.500865 [Byte1]: 53
2618 12:43:59.505176
2619 12:43:59.505274 Set Vref, RX VrefLevel [Byte0]: 54
2620 12:43:59.508440 [Byte1]: 54
2621 12:43:59.513273
2622 12:43:59.513369 Set Vref, RX VrefLevel [Byte0]: 55
2623 12:43:59.516496 [Byte1]: 55
2624 12:43:59.521410
2625 12:43:59.521479 Set Vref, RX VrefLevel [Byte0]: 56
2626 12:43:59.525095 [Byte1]: 56
2627 12:43:59.528813
2628 12:43:59.528907 Set Vref, RX VrefLevel [Byte0]: 57
2629 12:43:59.532127 [Byte1]: 57
2630 12:43:59.537121
2631 12:43:59.537188 Set Vref, RX VrefLevel [Byte0]: 58
2632 12:43:59.540118 [Byte1]: 58
2633 12:43:59.545426
2634 12:43:59.545495 Set Vref, RX VrefLevel [Byte0]: 59
2635 12:43:59.548283 [Byte1]: 59
2636 12:43:59.552854
2637 12:43:59.552926 Set Vref, RX VrefLevel [Byte0]: 60
2638 12:43:59.556498 [Byte1]: 60
2639 12:43:59.561609
2640 12:43:59.561676 Set Vref, RX VrefLevel [Byte0]: 61
2641 12:43:59.563901 [Byte1]: 61
2642 12:43:59.568677
2643 12:43:59.568747 Set Vref, RX VrefLevel [Byte0]: 62
2644 12:43:59.571805 [Byte1]: 62
2645 12:43:59.576283
2646 12:43:59.576351 Set Vref, RX VrefLevel [Byte0]: 63
2647 12:43:59.580310 [Byte1]: 63
2648 12:43:59.584360
2649 12:43:59.584423 Set Vref, RX VrefLevel [Byte0]: 64
2650 12:43:59.587739 [Byte1]: 64
2651 12:43:59.592869
2652 12:43:59.592937 Set Vref, RX VrefLevel [Byte0]: 65
2653 12:43:59.595821 [Byte1]: 65
2654 12:43:59.600699
2655 12:43:59.600819 Set Vref, RX VrefLevel [Byte0]: 66
2656 12:43:59.604386 [Byte1]: 66
2657 12:43:59.608071
2658 12:43:59.608152 Final RX Vref Byte 0 = 46 to rank0
2659 12:43:59.612796 Final RX Vref Byte 1 = 50 to rank0
2660 12:43:59.614671 Final RX Vref Byte 0 = 46 to rank1
2661 12:43:59.617786 Final RX Vref Byte 1 = 50 to rank1==
2662 12:43:59.621258 Dram Type= 6, Freq= 0, CH_0, rank 0
2663 12:43:59.627880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2664 12:43:59.627979 ==
2665 12:43:59.628068 DQS Delay:
2666 12:43:59.628154 DQS0 = 0, DQS1 = 0
2667 12:43:59.631313 DQM Delay:
2668 12:43:59.631406 DQM0 = 114, DQM1 = 105
2669 12:43:59.634783 DQ Delay:
2670 12:43:59.637693 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2671 12:43:59.641057 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2672 12:43:59.644665 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =96
2673 12:43:59.648086 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2674 12:43:59.648153
2675 12:43:59.648216
2676 12:43:59.654969 [DQSOSCAuto] RK0, (LSB)MR18= 0x606, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
2677 12:43:59.658130 CH0 RK0: MR19=404, MR18=606
2678 12:43:59.664860 CH0_RK0: MR19=0x404, MR18=0x606, DQSOSC=407, MR23=63, INC=39, DEC=26
2679 12:43:59.664931
2680 12:43:59.668135 ----->DramcWriteLeveling(PI) begin...
2681 12:43:59.668202 ==
2682 12:43:59.671464 Dram Type= 6, Freq= 0, CH_0, rank 1
2683 12:43:59.674916 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2684 12:43:59.675011 ==
2685 12:43:59.678631 Write leveling (Byte 0): 28 => 28
2686 12:43:59.681486 Write leveling (Byte 1): 24 => 24
2687 12:43:59.685041 DramcWriteLeveling(PI) end<-----
2688 12:43:59.685132
2689 12:43:59.685221 ==
2690 12:43:59.688433 Dram Type= 6, Freq= 0, CH_0, rank 1
2691 12:43:59.691126 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2692 12:43:59.694475 ==
2693 12:43:59.694566 [Gating] SW mode calibration
2694 12:43:59.704740 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2695 12:43:59.708078 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2696 12:43:59.711762 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2697 12:43:59.717737 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2698 12:43:59.721269 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2699 12:43:59.725225 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2700 12:43:59.731687 0 11 16 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
2701 12:43:59.735369 0 11 20 | B1->B0 | 3232 2626 | 0 1 | (0 1) (1 0)
2702 12:43:59.738270 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2703 12:43:59.744807 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2704 12:43:59.748416 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2705 12:43:59.751761 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2706 12:43:59.758335 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2707 12:43:59.761442 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2708 12:43:59.764716 0 12 16 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
2709 12:43:59.771439 0 12 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2710 12:43:59.774824 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2711 12:43:59.778183 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2712 12:43:59.781310 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2713 12:43:59.788120 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2714 12:43:59.791233 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2715 12:43:59.795295 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2716 12:43:59.801344 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2717 12:43:59.804668 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2718 12:43:59.808686 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2719 12:43:59.814927 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2720 12:43:59.817652 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2721 12:43:59.821634 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2722 12:43:59.828035 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2723 12:43:59.831403 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2724 12:43:59.834750 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2725 12:43:59.841348 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2726 12:43:59.844897 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2727 12:43:59.847674 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2728 12:43:59.854613 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2729 12:43:59.857888 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2730 12:43:59.861373 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2731 12:43:59.867560 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2732 12:43:59.871460 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2733 12:43:59.874196 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2734 12:43:59.877710 Total UI for P1: 0, mck2ui 16
2735 12:43:59.881759 best dqsien dly found for B0: ( 0, 15, 16)
2736 12:43:59.884617 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2737 12:43:59.887581 Total UI for P1: 0, mck2ui 16
2738 12:43:59.891730 best dqsien dly found for B1: ( 0, 15, 18)
2739 12:43:59.898477 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2740 12:43:59.900885 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2741 12:43:59.900967
2742 12:43:59.904893 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2743 12:43:59.908141 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2744 12:43:59.911043 [Gating] SW calibration Done
2745 12:43:59.911114 ==
2746 12:43:59.914322 Dram Type= 6, Freq= 0, CH_0, rank 1
2747 12:43:59.917540 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2748 12:43:59.917614 ==
2749 12:43:59.921257 RX Vref Scan: 0
2750 12:43:59.921326
2751 12:43:59.921392 RX Vref 0 -> 0, step: 1
2752 12:43:59.921449
2753 12:43:59.924626 RX Delay -40 -> 252, step: 8
2754 12:43:59.928360 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2755 12:43:59.934665 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2756 12:43:59.937562 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2757 12:43:59.940918 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2758 12:43:59.944279 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2759 12:43:59.947818 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2760 12:43:59.954403 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2761 12:43:59.957725 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2762 12:43:59.961513 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2763 12:43:59.964097 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2764 12:43:59.968326 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2765 12:43:59.971552 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2766 12:43:59.977714 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2767 12:43:59.980961 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2768 12:43:59.984190 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2769 12:43:59.988190 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2770 12:43:59.988284 ==
2771 12:43:59.991165 Dram Type= 6, Freq= 0, CH_0, rank 1
2772 12:43:59.997553 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2773 12:43:59.997639 ==
2774 12:43:59.997719 DQS Delay:
2775 12:44:00.001089 DQS0 = 0, DQS1 = 0
2776 12:44:00.001162 DQM Delay:
2777 12:44:00.001242 DQM0 = 114, DQM1 = 107
2778 12:44:00.004103 DQ Delay:
2779 12:44:00.007330 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =111
2780 12:44:00.011111 DQ4 =115, DQ5 =107, DQ6 =119, DQ7 =123
2781 12:44:00.014458 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2782 12:44:00.017158 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2783 12:44:00.017240
2784 12:44:00.017305
2785 12:44:00.017366 ==
2786 12:44:00.020600 Dram Type= 6, Freq= 0, CH_0, rank 1
2787 12:44:00.024454 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2788 12:44:00.024562 ==
2789 12:44:00.027230
2790 12:44:00.027312
2791 12:44:00.027376 TX Vref Scan disable
2792 12:44:00.031155 == TX Byte 0 ==
2793 12:44:00.033958 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2794 12:44:00.037595 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2795 12:44:00.041863 == TX Byte 1 ==
2796 12:44:00.043940 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2797 12:44:00.048223 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2798 12:44:00.048308 ==
2799 12:44:00.050712 Dram Type= 6, Freq= 0, CH_0, rank 1
2800 12:44:00.057842 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2801 12:44:00.057922 ==
2802 12:44:00.068474 TX Vref=22, minBit 8, minWin=25, winSum=416
2803 12:44:00.071438 TX Vref=24, minBit 1, minWin=26, winSum=427
2804 12:44:00.074912 TX Vref=26, minBit 1, minWin=26, winSum=425
2805 12:44:00.078557 TX Vref=28, minBit 8, minWin=26, winSum=430
2806 12:44:00.081731 TX Vref=30, minBit 9, minWin=26, winSum=437
2807 12:44:00.085185 TX Vref=32, minBit 7, minWin=27, winSum=440
2808 12:44:00.092534 [TxChooseVref] Worse bit 7, Min win 27, Win sum 440, Final Vref 32
2809 12:44:00.092630
2810 12:44:00.095193 Final TX Range 1 Vref 32
2811 12:44:00.095291
2812 12:44:00.095378 ==
2813 12:44:00.098763 Dram Type= 6, Freq= 0, CH_0, rank 1
2814 12:44:00.102035 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2815 12:44:00.102106 ==
2816 12:44:00.102169
2817 12:44:00.102241
2818 12:44:00.105210 TX Vref Scan disable
2819 12:44:00.108293 == TX Byte 0 ==
2820 12:44:00.112009 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2821 12:44:00.114850 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2822 12:44:00.118626 == TX Byte 1 ==
2823 12:44:00.121453 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2824 12:44:00.124992 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2825 12:44:00.125065
2826 12:44:00.128236 [DATLAT]
2827 12:44:00.128332 Freq=1200, CH0 RK1
2828 12:44:00.128425
2829 12:44:00.131817 DATLAT Default: 0xc
2830 12:44:00.131949 0, 0xFFFF, sum = 0
2831 12:44:00.135704 1, 0xFFFF, sum = 0
2832 12:44:00.135776 2, 0xFFFF, sum = 0
2833 12:44:00.138894 3, 0xFFFF, sum = 0
2834 12:44:00.139000 4, 0xFFFF, sum = 0
2835 12:44:00.141776 5, 0xFFFF, sum = 0
2836 12:44:00.141872 6, 0xFFFF, sum = 0
2837 12:44:00.145394 7, 0xFFFF, sum = 0
2838 12:44:00.145492 8, 0xFFFF, sum = 0
2839 12:44:00.148246 9, 0xFFFF, sum = 0
2840 12:44:00.151417 10, 0xFFFF, sum = 0
2841 12:44:00.151514 11, 0x0, sum = 1
2842 12:44:00.151615 12, 0x0, sum = 2
2843 12:44:00.155431 13, 0x0, sum = 3
2844 12:44:00.155526 14, 0x0, sum = 4
2845 12:44:00.158447 best_step = 12
2846 12:44:00.158514
2847 12:44:00.158585 ==
2848 12:44:00.161543 Dram Type= 6, Freq= 0, CH_0, rank 1
2849 12:44:00.164738 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2850 12:44:00.164821 ==
2851 12:44:00.168737 RX Vref Scan: 0
2852 12:44:00.168844
2853 12:44:00.168932 RX Vref 0 -> 0, step: 1
2854 12:44:00.169028
2855 12:44:00.172679 RX Delay -21 -> 252, step: 4
2856 12:44:00.178808 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2857 12:44:00.182847 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2858 12:44:00.185375 iDelay=195, Bit 2, Center 114 (43 ~ 186) 144
2859 12:44:00.188455 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2860 12:44:00.191835 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2861 12:44:00.198613 iDelay=195, Bit 5, Center 108 (39 ~ 178) 140
2862 12:44:00.201936 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
2863 12:44:00.205673 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
2864 12:44:00.208964 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
2865 12:44:00.211892 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128
2866 12:44:00.218638 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
2867 12:44:00.221597 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2868 12:44:00.224653 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
2869 12:44:00.228053 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2870 12:44:00.231436 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
2871 12:44:00.239123 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
2872 12:44:00.239226 ==
2873 12:44:00.242311 Dram Type= 6, Freq= 0, CH_0, rank 1
2874 12:44:00.244660 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2875 12:44:00.244785 ==
2876 12:44:00.244849 DQS Delay:
2877 12:44:00.247954 DQS0 = 0, DQS1 = 0
2878 12:44:00.248023 DQM Delay:
2879 12:44:00.251613 DQM0 = 115, DQM1 = 106
2880 12:44:00.251711 DQ Delay:
2881 12:44:00.255085 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2882 12:44:00.258242 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =122
2883 12:44:00.261339 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2884 12:44:00.265288 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =116
2885 12:44:00.265398
2886 12:44:00.265496
2887 12:44:00.274827 [DQSOSCAuto] RK1, (LSB)MR18= 0x1111, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps
2888 12:44:00.278087 CH0 RK1: MR19=404, MR18=1111
2889 12:44:00.284815 CH0_RK1: MR19=0x404, MR18=0x1111, DQSOSC=403, MR23=63, INC=40, DEC=26
2890 12:44:00.284913 [RxdqsGatingPostProcess] freq 1200
2891 12:44:00.291104 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2892 12:44:00.294807 Pre-setting of DQS Precalculation
2893 12:44:00.301452 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2894 12:44:00.301535 ==
2895 12:44:00.304550 Dram Type= 6, Freq= 0, CH_1, rank 0
2896 12:44:00.308216 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2897 12:44:00.308302 ==
2898 12:44:00.311322 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2899 12:44:00.317929 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=23, u1VrefScanEnd=33
2900 12:44:00.326717 [CA 0] Center 37 (8~67) winsize 60
2901 12:44:00.330780 [CA 1] Center 37 (7~67) winsize 61
2902 12:44:00.333863 [CA 2] Center 34 (4~64) winsize 61
2903 12:44:00.337263 [CA 3] Center 34 (4~64) winsize 61
2904 12:44:00.340604 [CA 4] Center 32 (2~62) winsize 61
2905 12:44:00.343798 [CA 5] Center 32 (2~62) winsize 61
2906 12:44:00.343873
2907 12:44:00.347255 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2908 12:44:00.347349
2909 12:44:00.350796 [CATrainingPosCal] consider 1 rank data
2910 12:44:00.353513 u2DelayCellTimex100 = 270/100 ps
2911 12:44:00.357193 CA0 delay=37 (8~67),Diff = 5 PI (24 cell)
2912 12:44:00.360409 CA1 delay=37 (7~67),Diff = 5 PI (24 cell)
2913 12:44:00.367112 CA2 delay=34 (4~64),Diff = 2 PI (9 cell)
2914 12:44:00.370751 CA3 delay=34 (4~64),Diff = 2 PI (9 cell)
2915 12:44:00.373416 CA4 delay=32 (2~62),Diff = 0 PI (0 cell)
2916 12:44:00.376912 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
2917 12:44:00.376979
2918 12:44:00.380005 CA PerBit enable=1, Macro0, CA PI delay=32
2919 12:44:00.380097
2920 12:44:00.383591 [CBTSetCACLKResult] CA Dly = 32
2921 12:44:00.383689 CS Dly: 5 (0~36)
2922 12:44:00.386540 ==
2923 12:44:00.386629 Dram Type= 6, Freq= 0, CH_1, rank 1
2924 12:44:00.393088 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2925 12:44:00.393166 ==
2926 12:44:00.397118 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2927 12:44:00.403680 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2928 12:44:00.412618 [CA 0] Center 37 (7~67) winsize 61
2929 12:44:00.415979 [CA 1] Center 37 (6~68) winsize 63
2930 12:44:00.419256 [CA 2] Center 34 (4~64) winsize 61
2931 12:44:00.422044 [CA 3] Center 33 (3~64) winsize 62
2932 12:44:00.426620 [CA 4] Center 32 (2~63) winsize 62
2933 12:44:00.428807 [CA 5] Center 31 (1~62) winsize 62
2934 12:44:00.428881
2935 12:44:00.432582 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2936 12:44:00.432687
2937 12:44:00.435969 [CATrainingPosCal] consider 2 rank data
2938 12:44:00.438887 u2DelayCellTimex100 = 270/100 ps
2939 12:44:00.442643 CA0 delay=37 (8~67),Diff = 5 PI (24 cell)
2940 12:44:00.445660 CA1 delay=37 (7~67),Diff = 5 PI (24 cell)
2941 12:44:00.452905 CA2 delay=34 (4~64),Diff = 2 PI (9 cell)
2942 12:44:00.455873 CA3 delay=34 (4~64),Diff = 2 PI (9 cell)
2943 12:44:00.458986 CA4 delay=32 (2~62),Diff = 0 PI (0 cell)
2944 12:44:00.462590 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
2945 12:44:00.462659
2946 12:44:00.466573 CA PerBit enable=1, Macro0, CA PI delay=32
2947 12:44:00.466671
2948 12:44:00.469385 [CBTSetCACLKResult] CA Dly = 32
2949 12:44:00.469480 CS Dly: 6 (0~38)
2950 12:44:00.469566
2951 12:44:00.473974 ----->DramcWriteLeveling(PI) begin...
2952 12:44:00.475754 ==
2953 12:44:00.475845 Dram Type= 6, Freq= 0, CH_1, rank 0
2954 12:44:00.482127 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2955 12:44:00.482216 ==
2956 12:44:00.486786 Write leveling (Byte 0): 20 => 20
2957 12:44:00.488635 Write leveling (Byte 1): 21 => 21
2958 12:44:00.492173 DramcWriteLeveling(PI) end<-----
2959 12:44:00.492244
2960 12:44:00.492309 ==
2961 12:44:00.495713 Dram Type= 6, Freq= 0, CH_1, rank 0
2962 12:44:00.499031 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2963 12:44:00.499131 ==
2964 12:44:00.502411 [Gating] SW mode calibration
2965 12:44:00.508629 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2966 12:44:00.511950 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2967 12:44:00.518602 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2968 12:44:00.522691 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2969 12:44:00.526326 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2970 12:44:00.532872 0 11 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2971 12:44:00.535395 0 11 16 | B1->B0 | 3333 2727 | 0 0 | (0 1) (0 0)
2972 12:44:00.538961 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2973 12:44:00.545889 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2974 12:44:00.549745 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2975 12:44:00.552016 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2976 12:44:00.558628 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2977 12:44:00.562369 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2978 12:44:00.565515 0 12 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2979 12:44:00.572396 0 12 16 | B1->B0 | 2f2f 4444 | 0 0 | (0 0) (0 0)
2980 12:44:00.575486 0 12 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2981 12:44:00.578595 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2982 12:44:00.585460 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2983 12:44:00.589748 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2984 12:44:00.592254 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2985 12:44:00.598509 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2986 12:44:00.602056 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2987 12:44:00.605267 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2988 12:44:00.609126 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2989 12:44:00.616045 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 12:44:00.618811 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 12:44:00.622133 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 12:44:00.628645 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2993 12:44:00.631915 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2994 12:44:00.635536 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2995 12:44:00.642246 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2996 12:44:00.645081 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2997 12:44:00.648679 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2998 12:44:00.655437 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2999 12:44:00.658609 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3000 12:44:00.662390 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3001 12:44:00.669066 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3002 12:44:00.673067 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3003 12:44:00.675268 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3004 12:44:00.681829 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3005 12:44:00.681911 Total UI for P1: 0, mck2ui 16
3006 12:44:00.688681 best dqsien dly found for B0: ( 0, 15, 14)
3007 12:44:00.692415 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3008 12:44:00.695733 Total UI for P1: 0, mck2ui 16
3009 12:44:00.698825 best dqsien dly found for B1: ( 0, 15, 18)
3010 12:44:00.701857 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3011 12:44:00.705275 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3012 12:44:00.705357
3013 12:44:00.708591 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3014 12:44:00.711785 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3015 12:44:00.715474 [Gating] SW calibration Done
3016 12:44:00.715555 ==
3017 12:44:00.719553 Dram Type= 6, Freq= 0, CH_1, rank 0
3018 12:44:00.721852 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3019 12:44:00.725819 ==
3020 12:44:00.725900 RX Vref Scan: 0
3021 12:44:00.725969
3022 12:44:00.728743 RX Vref 0 -> 0, step: 1
3023 12:44:00.728838
3024 12:44:00.728903 RX Delay -40 -> 252, step: 8
3025 12:44:00.735362 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3026 12:44:00.738769 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3027 12:44:00.742051 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3028 12:44:00.745229 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3029 12:44:00.748734 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3030 12:44:00.755499 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3031 12:44:00.759227 iDelay=208, Bit 6, Center 119 (40 ~ 199) 160
3032 12:44:00.762435 iDelay=208, Bit 7, Center 111 (32 ~ 191) 160
3033 12:44:00.765291 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3034 12:44:00.768977 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3035 12:44:00.775455 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152
3036 12:44:00.778409 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3037 12:44:00.782001 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3038 12:44:00.785234 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3039 12:44:00.789424 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3040 12:44:00.795603 iDelay=208, Bit 15, Center 115 (40 ~ 191) 152
3041 12:44:00.795688 ==
3042 12:44:00.801262 Dram Type= 6, Freq= 0, CH_1, rank 0
3043 12:44:00.802857 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3044 12:44:00.802941 ==
3045 12:44:00.803006 DQS Delay:
3046 12:44:00.805878 DQS0 = 0, DQS1 = 0
3047 12:44:00.805959 DQM Delay:
3048 12:44:00.808746 DQM0 = 115, DQM1 = 107
3049 12:44:00.808867 DQ Delay:
3050 12:44:00.812315 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3051 12:44:00.815918 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =111
3052 12:44:00.819387 DQ8 =87, DQ9 =95, DQ10 =107, DQ11 =103
3053 12:44:00.822300 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3054 12:44:00.822382
3055 12:44:00.822447
3056 12:44:00.822506 ==
3057 12:44:00.826015 Dram Type= 6, Freq= 0, CH_1, rank 0
3058 12:44:00.831937 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3059 12:44:00.832020 ==
3060 12:44:00.832085
3061 12:44:00.832145
3062 12:44:00.832203 TX Vref Scan disable
3063 12:44:00.836107 == TX Byte 0 ==
3064 12:44:00.839602 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3065 12:44:00.845802 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3066 12:44:00.845884 == TX Byte 1 ==
3067 12:44:00.849196 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3068 12:44:00.855955 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3069 12:44:00.856037 ==
3070 12:44:00.859070 Dram Type= 6, Freq= 0, CH_1, rank 0
3071 12:44:00.862563 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3072 12:44:00.862674 ==
3073 12:44:00.873890 TX Vref=22, minBit 8, minWin=25, winSum=417
3074 12:44:00.876613 TX Vref=24, minBit 9, minWin=25, winSum=423
3075 12:44:00.881198 TX Vref=26, minBit 8, minWin=26, winSum=431
3076 12:44:00.883724 TX Vref=28, minBit 11, minWin=26, winSum=437
3077 12:44:00.886597 TX Vref=30, minBit 9, minWin=26, winSum=432
3078 12:44:00.890120 TX Vref=32, minBit 9, minWin=26, winSum=431
3079 12:44:00.896999 [TxChooseVref] Worse bit 11, Min win 26, Win sum 437, Final Vref 28
3080 12:44:00.897091
3081 12:44:00.900739 Final TX Range 1 Vref 28
3082 12:44:00.900837
3083 12:44:00.900923 ==
3084 12:44:00.903250 Dram Type= 6, Freq= 0, CH_1, rank 0
3085 12:44:00.907175 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3086 12:44:00.907260 ==
3087 12:44:00.910804
3088 12:44:00.910945
3089 12:44:00.911073 TX Vref Scan disable
3090 12:44:00.913698 == TX Byte 0 ==
3091 12:44:00.917197 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3092 12:44:00.920215 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3093 12:44:00.923402 == TX Byte 1 ==
3094 12:44:00.927137 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3095 12:44:00.930589 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3096 12:44:00.930675
3097 12:44:00.933990 [DATLAT]
3098 12:44:00.934072 Freq=1200, CH1 RK0
3099 12:44:00.934138
3100 12:44:00.936944 DATLAT Default: 0xd
3101 12:44:00.937026 0, 0xFFFF, sum = 0
3102 12:44:00.939991 1, 0xFFFF, sum = 0
3103 12:44:00.940074 2, 0xFFFF, sum = 0
3104 12:44:00.943810 3, 0xFFFF, sum = 0
3105 12:44:00.943893 4, 0xFFFF, sum = 0
3106 12:44:00.946622 5, 0xFFFF, sum = 0
3107 12:44:00.946705 6, 0xFFFF, sum = 0
3108 12:44:00.950405 7, 0xFFFF, sum = 0
3109 12:44:00.950488 8, 0xFFFF, sum = 0
3110 12:44:00.953457 9, 0xFFFF, sum = 0
3111 12:44:00.956698 10, 0xFFFF, sum = 0
3112 12:44:00.956818 11, 0x0, sum = 1
3113 12:44:00.956884 12, 0x0, sum = 2
3114 12:44:00.959816 13, 0x0, sum = 3
3115 12:44:00.959899 14, 0x0, sum = 4
3116 12:44:00.963669 best_step = 12
3117 12:44:00.963751
3118 12:44:00.963816 ==
3119 12:44:00.967159 Dram Type= 6, Freq= 0, CH_1, rank 0
3120 12:44:00.970080 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3121 12:44:00.970164 ==
3122 12:44:00.974020 RX Vref Scan: 1
3123 12:44:00.974102
3124 12:44:00.974166 Set Vref Range= 32 -> 127
3125 12:44:00.976605
3126 12:44:00.976687 RX Vref 32 -> 127, step: 1
3127 12:44:00.976796
3128 12:44:00.980263 RX Delay -29 -> 252, step: 4
3129 12:44:00.980344
3130 12:44:00.984559 Set Vref, RX VrefLevel [Byte0]: 32
3131 12:44:00.986599 [Byte1]: 32
3132 12:44:00.990210
3133 12:44:00.990287 Set Vref, RX VrefLevel [Byte0]: 33
3134 12:44:00.993415 [Byte1]: 33
3135 12:44:00.997897
3136 12:44:00.997980 Set Vref, RX VrefLevel [Byte0]: 34
3137 12:44:01.001305 [Byte1]: 34
3138 12:44:01.006001
3139 12:44:01.006113 Set Vref, RX VrefLevel [Byte0]: 35
3140 12:44:01.009184 [Byte1]: 35
3141 12:44:01.013805
3142 12:44:01.013893 Set Vref, RX VrefLevel [Byte0]: 36
3143 12:44:01.017374 [Byte1]: 36
3144 12:44:01.021995
3145 12:44:01.022077 Set Vref, RX VrefLevel [Byte0]: 37
3146 12:44:01.025629 [Byte1]: 37
3147 12:44:01.029866
3148 12:44:01.029948 Set Vref, RX VrefLevel [Byte0]: 38
3149 12:44:01.033604 [Byte1]: 38
3150 12:44:01.037992
3151 12:44:01.038074 Set Vref, RX VrefLevel [Byte0]: 39
3152 12:44:01.041094 [Byte1]: 39
3153 12:44:01.045549
3154 12:44:01.045631 Set Vref, RX VrefLevel [Byte0]: 40
3155 12:44:01.049050 [Byte1]: 40
3156 12:44:01.053711
3157 12:44:01.053793 Set Vref, RX VrefLevel [Byte0]: 41
3158 12:44:01.057409 [Byte1]: 41
3159 12:44:01.062037
3160 12:44:01.062118 Set Vref, RX VrefLevel [Byte0]: 42
3161 12:44:01.065443 [Byte1]: 42
3162 12:44:01.070455
3163 12:44:01.070536 Set Vref, RX VrefLevel [Byte0]: 43
3164 12:44:01.073265 [Byte1]: 43
3165 12:44:01.078005
3166 12:44:01.078086 Set Vref, RX VrefLevel [Byte0]: 44
3167 12:44:01.081150 [Byte1]: 44
3168 12:44:01.086109
3169 12:44:01.086190 Set Vref, RX VrefLevel [Byte0]: 45
3170 12:44:01.088925 [Byte1]: 45
3171 12:44:01.093679
3172 12:44:01.093760 Set Vref, RX VrefLevel [Byte0]: 46
3173 12:44:01.097174 [Byte1]: 46
3174 12:44:01.103307
3175 12:44:01.103414 Set Vref, RX VrefLevel [Byte0]: 47
3176 12:44:01.105263 [Byte1]: 47
3177 12:44:01.109798
3178 12:44:01.109880 Set Vref, RX VrefLevel [Byte0]: 48
3179 12:44:01.112755 [Byte1]: 48
3180 12:44:01.117225
3181 12:44:01.117305 Set Vref, RX VrefLevel [Byte0]: 49
3182 12:44:01.120718 [Byte1]: 49
3183 12:44:01.125602
3184 12:44:01.125683 Set Vref, RX VrefLevel [Byte0]: 50
3185 12:44:01.129735 [Byte1]: 50
3186 12:44:01.133488
3187 12:44:01.133569 Set Vref, RX VrefLevel [Byte0]: 51
3188 12:44:01.136866 [Byte1]: 51
3189 12:44:01.141246
3190 12:44:01.141327 Set Vref, RX VrefLevel [Byte0]: 52
3191 12:44:01.144371 [Byte1]: 52
3192 12:44:01.149303
3193 12:44:01.149384 Set Vref, RX VrefLevel [Byte0]: 53
3194 12:44:01.152639 [Byte1]: 53
3195 12:44:01.157375
3196 12:44:01.157457 Set Vref, RX VrefLevel [Byte0]: 54
3197 12:44:01.160866 [Byte1]: 54
3198 12:44:01.165008
3199 12:44:01.165089 Set Vref, RX VrefLevel [Byte0]: 55
3200 12:44:01.168678 [Byte1]: 55
3201 12:44:01.173214
3202 12:44:01.173295 Set Vref, RX VrefLevel [Byte0]: 56
3203 12:44:01.176249 [Byte1]: 56
3204 12:44:01.181061
3205 12:44:01.181142 Set Vref, RX VrefLevel [Byte0]: 57
3206 12:44:01.184454 [Byte1]: 57
3207 12:44:01.188867
3208 12:44:01.188948 Set Vref, RX VrefLevel [Byte0]: 58
3209 12:44:01.192302 [Byte1]: 58
3210 12:44:01.197180
3211 12:44:01.197262 Set Vref, RX VrefLevel [Byte0]: 59
3212 12:44:01.200437 [Byte1]: 59
3213 12:44:01.205855
3214 12:44:01.205936 Set Vref, RX VrefLevel [Byte0]: 60
3215 12:44:01.208242 [Byte1]: 60
3216 12:44:01.213750
3217 12:44:01.213832 Set Vref, RX VrefLevel [Byte0]: 61
3218 12:44:01.216363 [Byte1]: 61
3219 12:44:01.220953
3220 12:44:01.221034 Set Vref, RX VrefLevel [Byte0]: 62
3221 12:44:01.224206 [Byte1]: 62
3222 12:44:01.229281
3223 12:44:01.229363 Set Vref, RX VrefLevel [Byte0]: 63
3224 12:44:01.232345 [Byte1]: 63
3225 12:44:01.237975
3226 12:44:01.238057 Set Vref, RX VrefLevel [Byte0]: 64
3227 12:44:01.239969 [Byte1]: 64
3228 12:44:01.244863
3229 12:44:01.244945 Set Vref, RX VrefLevel [Byte0]: 65
3230 12:44:01.248189 [Byte1]: 65
3231 12:44:01.253207
3232 12:44:01.253289 Set Vref, RX VrefLevel [Byte0]: 66
3233 12:44:01.256586 [Byte1]: 66
3234 12:44:01.260660
3235 12:44:01.260778 Set Vref, RX VrefLevel [Byte0]: 67
3236 12:44:01.263939 [Byte1]: 67
3237 12:44:01.268767
3238 12:44:01.268849 Final RX Vref Byte 0 = 54 to rank0
3239 12:44:01.272130 Final RX Vref Byte 1 = 50 to rank0
3240 12:44:01.275145 Final RX Vref Byte 0 = 54 to rank1
3241 12:44:01.278647 Final RX Vref Byte 1 = 50 to rank1==
3242 12:44:01.282067 Dram Type= 6, Freq= 0, CH_1, rank 0
3243 12:44:01.288816 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3244 12:44:01.288898 ==
3245 12:44:01.288963 DQS Delay:
3246 12:44:01.289023 DQS0 = 0, DQS1 = 0
3247 12:44:01.292127 DQM Delay:
3248 12:44:01.292208 DQM0 = 113, DQM1 = 106
3249 12:44:01.295135 DQ Delay:
3250 12:44:01.298393 DQ0 =118, DQ1 =108, DQ2 =104, DQ3 =112
3251 12:44:01.302253 DQ4 =112, DQ5 =122, DQ6 =120, DQ7 =112
3252 12:44:01.305150 DQ8 =88, DQ9 =94, DQ10 =108, DQ11 =98
3253 12:44:01.308903 DQ12 =114, DQ13 =116, DQ14 =116, DQ15 =116
3254 12:44:01.308985
3255 12:44:01.309049
3256 12:44:01.315390 [DQSOSCAuto] RK0, (LSB)MR18= 0x1818, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
3257 12:44:01.318541 CH1 RK0: MR19=404, MR18=1818
3258 12:44:01.324905 CH1_RK0: MR19=0x404, MR18=0x1818, DQSOSC=400, MR23=63, INC=40, DEC=27
3259 12:44:01.324988
3260 12:44:01.328429 ----->DramcWriteLeveling(PI) begin...
3261 12:44:01.328513 ==
3262 12:44:01.331940 Dram Type= 6, Freq= 0, CH_1, rank 1
3263 12:44:01.335023 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3264 12:44:01.338411 ==
3265 12:44:01.338526 Write leveling (Byte 0): 21 => 21
3266 12:44:01.341839 Write leveling (Byte 1): 21 => 21
3267 12:44:01.344937 DramcWriteLeveling(PI) end<-----
3268 12:44:01.345036
3269 12:44:01.345117 ==
3270 12:44:01.348961 Dram Type= 6, Freq= 0, CH_1, rank 1
3271 12:44:01.355096 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3272 12:44:01.355202 ==
3273 12:44:01.355282 [Gating] SW mode calibration
3274 12:44:01.365963 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3275 12:44:01.369982 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3276 12:44:01.371660 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3277 12:44:01.379263 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3278 12:44:01.382085 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3279 12:44:01.385192 0 11 12 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
3280 12:44:01.392457 0 11 16 | B1->B0 | 3333 2323 | 0 0 | (0 1) (1 0)
3281 12:44:01.395967 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3282 12:44:01.399291 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3283 12:44:01.405535 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3284 12:44:01.409441 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3285 12:44:01.411707 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3286 12:44:01.419180 0 12 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
3287 12:44:01.421716 0 12 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
3288 12:44:01.425561 0 12 16 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
3289 12:44:01.431675 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3290 12:44:01.435946 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3291 12:44:01.438344 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3292 12:44:01.445687 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3293 12:44:01.448355 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3294 12:44:01.451908 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3295 12:44:01.455168 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3296 12:44:01.461755 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3297 12:44:01.465338 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3298 12:44:01.468449 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3299 12:44:01.475211 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3300 12:44:01.478397 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3301 12:44:01.482131 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3302 12:44:01.489104 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3303 12:44:01.491805 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3304 12:44:01.495886 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3305 12:44:01.502379 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3306 12:44:01.504957 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3307 12:44:01.508377 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3308 12:44:01.515439 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3309 12:44:01.518344 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3310 12:44:01.521979 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3311 12:44:01.528827 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3312 12:44:01.532293 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3313 12:44:01.535218 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3314 12:44:01.538081 Total UI for P1: 0, mck2ui 16
3315 12:44:01.541870 best dqsien dly found for B0: ( 0, 15, 14)
3316 12:44:01.545132 Total UI for P1: 0, mck2ui 16
3317 12:44:01.548211 best dqsien dly found for B1: ( 0, 15, 16)
3318 12:44:01.551708 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3319 12:44:01.554976 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3320 12:44:01.555057
3321 12:44:01.562163 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3322 12:44:01.564923 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3323 12:44:01.565003 [Gating] SW calibration Done
3324 12:44:01.568665 ==
3325 12:44:01.568752 Dram Type= 6, Freq= 0, CH_1, rank 1
3326 12:44:01.575061 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3327 12:44:01.575143 ==
3328 12:44:01.575207 RX Vref Scan: 0
3329 12:44:01.575268
3330 12:44:01.578048 RX Vref 0 -> 0, step: 1
3331 12:44:01.578129
3332 12:44:01.582016 RX Delay -40 -> 252, step: 8
3333 12:44:01.586467 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3334 12:44:01.588246 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3335 12:44:01.591383 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3336 12:44:01.598020 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3337 12:44:01.601670 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3338 12:44:01.604994 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3339 12:44:01.609006 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3340 12:44:01.611386 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3341 12:44:01.618307 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3342 12:44:01.621863 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3343 12:44:01.625143 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3344 12:44:01.628507 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3345 12:44:01.631442 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3346 12:44:01.638007 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3347 12:44:01.641694 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3348 12:44:01.644631 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3349 12:44:01.644723 ==
3350 12:44:01.647629 Dram Type= 6, Freq= 0, CH_1, rank 1
3351 12:44:01.651611 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3352 12:44:01.651694 ==
3353 12:44:01.655171 DQS Delay:
3354 12:44:01.655252 DQS0 = 0, DQS1 = 0
3355 12:44:01.658118 DQM Delay:
3356 12:44:01.658200 DQM0 = 117, DQM1 = 108
3357 12:44:01.658265 DQ Delay:
3358 12:44:01.665157 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =119
3359 12:44:01.667840 DQ4 =119, DQ5 =123, DQ6 =123, DQ7 =115
3360 12:44:01.671328 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
3361 12:44:01.675078 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3362 12:44:01.675160
3363 12:44:01.675224
3364 12:44:01.675284 ==
3365 12:44:01.677882 Dram Type= 6, Freq= 0, CH_1, rank 1
3366 12:44:01.681262 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3367 12:44:01.681345 ==
3368 12:44:01.681409
3369 12:44:01.681468
3370 12:44:01.684899 TX Vref Scan disable
3371 12:44:01.687891 == TX Byte 0 ==
3372 12:44:01.691213 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3373 12:44:01.694424 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3374 12:44:01.697947 == TX Byte 1 ==
3375 12:44:01.702017 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3376 12:44:01.704731 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3377 12:44:01.704828 ==
3378 12:44:01.707933 Dram Type= 6, Freq= 0, CH_1, rank 1
3379 12:44:01.711396 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3380 12:44:01.715458 ==
3381 12:44:01.724605 TX Vref=22, minBit 0, minWin=26, winSum=424
3382 12:44:01.727553 TX Vref=24, minBit 0, minWin=26, winSum=424
3383 12:44:01.731192 TX Vref=26, minBit 3, minWin=26, winSum=428
3384 12:44:01.734169 TX Vref=28, minBit 0, minWin=26, winSum=432
3385 12:44:01.737771 TX Vref=30, minBit 0, minWin=26, winSum=436
3386 12:44:01.741030 TX Vref=32, minBit 0, minWin=26, winSum=434
3387 12:44:01.747825 [TxChooseVref] Worse bit 0, Min win 26, Win sum 436, Final Vref 30
3388 12:44:01.747907
3389 12:44:01.750850 Final TX Range 1 Vref 30
3390 12:44:01.750932
3391 12:44:01.750996 ==
3392 12:44:01.754333 Dram Type= 6, Freq= 0, CH_1, rank 1
3393 12:44:01.758145 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3394 12:44:01.758227 ==
3395 12:44:01.758292
3396 12:44:01.761300
3397 12:44:01.761381 TX Vref Scan disable
3398 12:44:01.764421 == TX Byte 0 ==
3399 12:44:01.767673 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3400 12:44:01.770924 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3401 12:44:01.774034 == TX Byte 1 ==
3402 12:44:01.777466 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3403 12:44:01.781880 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3404 12:44:01.781961
3405 12:44:01.784783 [DATLAT]
3406 12:44:01.784865 Freq=1200, CH1 RK1
3407 12:44:01.784930
3408 12:44:01.787304 DATLAT Default: 0xc
3409 12:44:01.787385 0, 0xFFFF, sum = 0
3410 12:44:01.790682 1, 0xFFFF, sum = 0
3411 12:44:01.790765 2, 0xFFFF, sum = 0
3412 12:44:01.794958 3, 0xFFFF, sum = 0
3413 12:44:01.795041 4, 0xFFFF, sum = 0
3414 12:44:01.797597 5, 0xFFFF, sum = 0
3415 12:44:01.797679 6, 0xFFFF, sum = 0
3416 12:44:01.800672 7, 0xFFFF, sum = 0
3417 12:44:01.800794 8, 0xFFFF, sum = 0
3418 12:44:01.804300 9, 0xFFFF, sum = 0
3419 12:44:01.807500 10, 0xFFFF, sum = 0
3420 12:44:01.807582 11, 0x0, sum = 1
3421 12:44:01.807648 12, 0x0, sum = 2
3422 12:44:01.810681 13, 0x0, sum = 3
3423 12:44:01.810764 14, 0x0, sum = 4
3424 12:44:01.814737 best_step = 12
3425 12:44:01.814819
3426 12:44:01.814884 ==
3427 12:44:01.817740 Dram Type= 6, Freq= 0, CH_1, rank 1
3428 12:44:01.820616 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3429 12:44:01.820698 ==
3430 12:44:01.824681 RX Vref Scan: 0
3431 12:44:01.824807
3432 12:44:01.824873 RX Vref 0 -> 0, step: 1
3433 12:44:01.824933
3434 12:44:01.827993 RX Delay -21 -> 252, step: 4
3435 12:44:01.834183 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3436 12:44:01.837365 iDelay=199, Bit 1, Center 112 (43 ~ 182) 140
3437 12:44:01.840966 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3438 12:44:01.844631 iDelay=199, Bit 3, Center 114 (47 ~ 182) 136
3439 12:44:01.847764 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3440 12:44:01.854464 iDelay=199, Bit 5, Center 126 (55 ~ 198) 144
3441 12:44:01.858409 iDelay=199, Bit 6, Center 124 (55 ~ 194) 140
3442 12:44:01.861175 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3443 12:44:01.864144 iDelay=199, Bit 8, Center 88 (19 ~ 158) 140
3444 12:44:01.868081 iDelay=199, Bit 9, Center 90 (23 ~ 158) 136
3445 12:44:01.874649 iDelay=199, Bit 10, Center 108 (43 ~ 174) 132
3446 12:44:01.878137 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3447 12:44:01.881307 iDelay=199, Bit 12, Center 116 (47 ~ 186) 140
3448 12:44:01.884751 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3449 12:44:01.888217 iDelay=199, Bit 14, Center 116 (47 ~ 186) 140
3450 12:44:01.894086 iDelay=199, Bit 15, Center 112 (47 ~ 178) 132
3451 12:44:01.894168 ==
3452 12:44:01.897458 Dram Type= 6, Freq= 0, CH_1, rank 1
3453 12:44:01.900624 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3454 12:44:01.900728 ==
3455 12:44:01.900810 DQS Delay:
3456 12:44:01.904253 DQS0 = 0, DQS1 = 0
3457 12:44:01.904335 DQM Delay:
3458 12:44:01.907549 DQM0 = 116, DQM1 = 105
3459 12:44:01.907630 DQ Delay:
3460 12:44:01.911124 DQ0 =116, DQ1 =112, DQ2 =110, DQ3 =114
3461 12:44:01.914233 DQ4 =116, DQ5 =126, DQ6 =124, DQ7 =114
3462 12:44:01.917995 DQ8 =88, DQ9 =90, DQ10 =108, DQ11 =98
3463 12:44:01.920991 DQ12 =116, DQ13 =112, DQ14 =116, DQ15 =112
3464 12:44:01.921073
3465 12:44:01.921137
3466 12:44:01.931176 [DQSOSCAuto] RK1, (LSB)MR18= 0xd0d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
3467 12:44:01.934830 CH1 RK1: MR19=404, MR18=D0D
3468 12:44:01.938148 CH1_RK1: MR19=0x404, MR18=0xD0D, DQSOSC=405, MR23=63, INC=39, DEC=26
3469 12:44:01.940926 [RxdqsGatingPostProcess] freq 1200
3470 12:44:01.947467 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3471 12:44:01.950706 Pre-setting of DQS Precalculation
3472 12:44:01.954273 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3473 12:44:01.964044 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3474 12:44:01.970847 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3475 12:44:01.970929
3476 12:44:01.970993
3477 12:44:01.974423 [Calibration Summary] 2400 Mbps
3478 12:44:01.974505 CH 0, Rank 0
3479 12:44:01.977641 SW Impedance : PASS
3480 12:44:01.977723 DUTY Scan : NO K
3481 12:44:01.980985 ZQ Calibration : PASS
3482 12:44:01.984811 Jitter Meter : NO K
3483 12:44:01.984893 CBT Training : PASS
3484 12:44:01.988112 Write leveling : PASS
3485 12:44:01.991026 RX DQS gating : PASS
3486 12:44:01.991107 RX DQ/DQS(RDDQC) : PASS
3487 12:44:01.994667 TX DQ/DQS : PASS
3488 12:44:01.994749 RX DATLAT : PASS
3489 12:44:01.997652 RX DQ/DQS(Engine): PASS
3490 12:44:02.001222 TX OE : NO K
3491 12:44:02.001304 All Pass.
3492 12:44:02.001369
3493 12:44:02.001428 CH 0, Rank 1
3494 12:44:02.004234 SW Impedance : PASS
3495 12:44:02.007732 DUTY Scan : NO K
3496 12:44:02.007813 ZQ Calibration : PASS
3497 12:44:02.011494 Jitter Meter : NO K
3498 12:44:02.014424 CBT Training : PASS
3499 12:44:02.014505 Write leveling : PASS
3500 12:44:02.018022 RX DQS gating : PASS
3501 12:44:02.021246 RX DQ/DQS(RDDQC) : PASS
3502 12:44:02.021328 TX DQ/DQS : PASS
3503 12:44:02.024488 RX DATLAT : PASS
3504 12:44:02.027600 RX DQ/DQS(Engine): PASS
3505 12:44:02.027681 TX OE : NO K
3506 12:44:02.027759 All Pass.
3507 12:44:02.031003
3508 12:44:02.031084 CH 1, Rank 0
3509 12:44:02.034293 SW Impedance : PASS
3510 12:44:02.034375 DUTY Scan : NO K
3511 12:44:02.038047 ZQ Calibration : PASS
3512 12:44:02.038129 Jitter Meter : NO K
3513 12:44:02.041368 CBT Training : PASS
3514 12:44:02.044128 Write leveling : PASS
3515 12:44:02.044209 RX DQS gating : PASS
3516 12:44:02.047781 RX DQ/DQS(RDDQC) : PASS
3517 12:44:02.050969 TX DQ/DQS : PASS
3518 12:44:02.051052 RX DATLAT : PASS
3519 12:44:02.054153 RX DQ/DQS(Engine): PASS
3520 12:44:02.057537 TX OE : NO K
3521 12:44:02.057619 All Pass.
3522 12:44:02.057684
3523 12:44:02.057743 CH 1, Rank 1
3524 12:44:02.061044 SW Impedance : PASS
3525 12:44:02.064510 DUTY Scan : NO K
3526 12:44:02.064591 ZQ Calibration : PASS
3527 12:44:02.067717 Jitter Meter : NO K
3528 12:44:02.070807 CBT Training : PASS
3529 12:44:02.070888 Write leveling : PASS
3530 12:44:02.073867 RX DQS gating : PASS
3531 12:44:02.077834 RX DQ/DQS(RDDQC) : PASS
3532 12:44:02.077916 TX DQ/DQS : PASS
3533 12:44:02.080850 RX DATLAT : PASS
3534 12:44:02.084156 RX DQ/DQS(Engine): PASS
3535 12:44:02.084238 TX OE : NO K
3536 12:44:02.084303 All Pass.
3537 12:44:02.087950
3538 12:44:02.088032 DramC Write-DBI off
3539 12:44:02.092099 PER_BANK_REFRESH: Hybrid Mode
3540 12:44:02.092180 TX_TRACKING: ON
3541 12:44:02.100857 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3542 12:44:02.104474 [FAST_K] Save calibration result to emmc
3543 12:44:02.107266 dramc_set_vcore_voltage set vcore to 650000
3544 12:44:02.111597 Read voltage for 600, 5
3545 12:44:02.111679 Vio18 = 0
3546 12:44:02.114689 Vcore = 650000
3547 12:44:02.114771 Vdram = 0
3548 12:44:02.114836 Vddq = 0
3549 12:44:02.114896 Vmddr = 0
3550 12:44:02.120654 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3551 12:44:02.124171 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3552 12:44:02.127663 MEM_TYPE=3, freq_sel=19
3553 12:44:02.131025 sv_algorithm_assistance_LP4_1600
3554 12:44:02.133973 ============ PULL DRAM RESETB DOWN ============
3555 12:44:02.140630 ========== PULL DRAM RESETB DOWN end =========
3556 12:44:02.144101 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3557 12:44:02.147199 ===================================
3558 12:44:02.151490 LPDDR4 DRAM CONFIGURATION
3559 12:44:02.154260 ===================================
3560 12:44:02.154342 EX_ROW_EN[0] = 0x0
3561 12:44:02.157631 EX_ROW_EN[1] = 0x0
3562 12:44:02.157713 LP4Y_EN = 0x0
3563 12:44:02.160684 WORK_FSP = 0x0
3564 12:44:02.160807 WL = 0x2
3565 12:44:02.163995 RL = 0x2
3566 12:44:02.164076 BL = 0x2
3567 12:44:02.167228 RPST = 0x0
3568 12:44:02.170840 RD_PRE = 0x0
3569 12:44:02.170921 WR_PRE = 0x1
3570 12:44:02.174335 WR_PST = 0x0
3571 12:44:02.174416 DBI_WR = 0x0
3572 12:44:02.177093 DBI_RD = 0x0
3573 12:44:02.177174 OTF = 0x1
3574 12:44:02.180433 ===================================
3575 12:44:02.184703 ===================================
3576 12:44:02.186652 ANA top config
3577 12:44:02.190003 ===================================
3578 12:44:02.190086 DLL_ASYNC_EN = 0
3579 12:44:02.193648 ALL_SLAVE_EN = 1
3580 12:44:02.196692 NEW_RANK_MODE = 1
3581 12:44:02.200124 DLL_IDLE_MODE = 1
3582 12:44:02.200206 LP45_APHY_COMB_EN = 1
3583 12:44:02.203195 TX_ODT_DIS = 1
3584 12:44:02.206690 NEW_8X_MODE = 1
3585 12:44:02.210078 ===================================
3586 12:44:02.214026 ===================================
3587 12:44:02.216365 data_rate = 1200
3588 12:44:02.220095 CKR = 1
3589 12:44:02.223723 DQ_P2S_RATIO = 8
3590 12:44:02.226630 ===================================
3591 12:44:02.226712 CA_P2S_RATIO = 8
3592 12:44:02.229899 DQ_CA_OPEN = 0
3593 12:44:02.235253 DQ_SEMI_OPEN = 0
3594 12:44:02.236275 CA_SEMI_OPEN = 0
3595 12:44:02.239580 CA_FULL_RATE = 0
3596 12:44:02.243382 DQ_CKDIV4_EN = 1
3597 12:44:02.243463 CA_CKDIV4_EN = 1
3598 12:44:02.246797 CA_PREDIV_EN = 0
3599 12:44:02.250309 PH8_DLY = 0
3600 12:44:02.253829 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3601 12:44:02.256467 DQ_AAMCK_DIV = 4
3602 12:44:02.259386 CA_AAMCK_DIV = 4
3603 12:44:02.259467 CA_ADMCK_DIV = 4
3604 12:44:02.264644 DQ_TRACK_CA_EN = 0
3605 12:44:02.266277 CA_PICK = 600
3606 12:44:02.270218 CA_MCKIO = 600
3607 12:44:02.273295 MCKIO_SEMI = 0
3608 12:44:02.276414 PLL_FREQ = 2288
3609 12:44:02.279134 DQ_UI_PI_RATIO = 32
3610 12:44:02.279215 CA_UI_PI_RATIO = 0
3611 12:44:02.282665 ===================================
3612 12:44:02.286261 ===================================
3613 12:44:02.289167 memory_type:LPDDR4
3614 12:44:02.292419 GP_NUM : 10
3615 12:44:02.292500 SRAM_EN : 1
3616 12:44:02.296628 MD32_EN : 0
3617 12:44:02.299078 ===================================
3618 12:44:02.302819 [ANA_INIT] >>>>>>>>>>>>>>
3619 12:44:02.306105 <<<<<< [CONFIGURE PHASE]: ANA_TX
3620 12:44:02.309409 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3621 12:44:02.313524 ===================================
3622 12:44:02.313609 data_rate = 1200,PCW = 0X5800
3623 12:44:02.316564 ===================================
3624 12:44:02.319398 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3625 12:44:02.325928 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3626 12:44:02.332377 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3627 12:44:02.336352 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3628 12:44:02.339541 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3629 12:44:02.342390 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3630 12:44:02.346079 [ANA_INIT] flow start
3631 12:44:02.349210 [ANA_INIT] PLL >>>>>>>>
3632 12:44:02.349292 [ANA_INIT] PLL <<<<<<<<
3633 12:44:02.352229 [ANA_INIT] MIDPI >>>>>>>>
3634 12:44:02.355589 [ANA_INIT] MIDPI <<<<<<<<
3635 12:44:02.355670 [ANA_INIT] DLL >>>>>>>>
3636 12:44:02.359311 [ANA_INIT] flow end
3637 12:44:02.362158 ============ LP4 DIFF to SE enter ============
3638 12:44:02.365480 ============ LP4 DIFF to SE exit ============
3639 12:44:02.369163 [ANA_INIT] <<<<<<<<<<<<<
3640 12:44:02.372551 [Flow] Enable top DCM control >>>>>
3641 12:44:02.377765 [Flow] Enable top DCM control <<<<<
3642 12:44:02.379440 Enable DLL master slave shuffle
3643 12:44:02.386528 ==============================================================
3644 12:44:02.386609 Gating Mode config
3645 12:44:02.391952 ==============================================================
3646 12:44:02.392035 Config description:
3647 12:44:02.401895 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3648 12:44:02.408803 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3649 12:44:02.415436 SELPH_MODE 0: By rank 1: By Phase
3650 12:44:02.418368 ==============================================================
3651 12:44:02.422107 GAT_TRACK_EN = 1
3652 12:44:02.425325 RX_GATING_MODE = 2
3653 12:44:02.428586 RX_GATING_TRACK_MODE = 2
3654 12:44:02.432358 SELPH_MODE = 1
3655 12:44:02.434924 PICG_EARLY_EN = 1
3656 12:44:02.438473 VALID_LAT_VALUE = 1
3657 12:44:02.445678 ==============================================================
3658 12:44:02.448612 Enter into Gating configuration >>>>
3659 12:44:02.452608 Exit from Gating configuration <<<<
3660 12:44:02.454793 Enter into DVFS_PRE_config >>>>>
3661 12:44:02.464917 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3662 12:44:02.468642 Exit from DVFS_PRE_config <<<<<
3663 12:44:02.471899 Enter into PICG configuration >>>>
3664 12:44:02.474995 Exit from PICG configuration <<<<
3665 12:44:02.478041 [RX_INPUT] configuration >>>>>
3666 12:44:02.478122 [RX_INPUT] configuration <<<<<
3667 12:44:02.484961 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3668 12:44:02.492044 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3669 12:44:02.494580 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3670 12:44:02.502314 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3671 12:44:02.507931 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3672 12:44:02.514472 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3673 12:44:02.517826 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3674 12:44:02.521145 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3675 12:44:02.527674 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3676 12:44:02.530994 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3677 12:44:02.534821 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3678 12:44:02.541802 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3679 12:44:02.545117 ===================================
3680 12:44:02.545199 LPDDR4 DRAM CONFIGURATION
3681 12:44:02.548356 ===================================
3682 12:44:02.551404 EX_ROW_EN[0] = 0x0
3683 12:44:02.551485 EX_ROW_EN[1] = 0x0
3684 12:44:02.554790 LP4Y_EN = 0x0
3685 12:44:02.554872 WORK_FSP = 0x0
3686 12:44:02.557923 WL = 0x2
3687 12:44:02.561197 RL = 0x2
3688 12:44:02.561278 BL = 0x2
3689 12:44:02.564864 RPST = 0x0
3690 12:44:02.564945 RD_PRE = 0x0
3691 12:44:02.568245 WR_PRE = 0x1
3692 12:44:02.568327 WR_PST = 0x0
3693 12:44:02.571158 DBI_WR = 0x0
3694 12:44:02.571239 DBI_RD = 0x0
3695 12:44:02.574260 OTF = 0x1
3696 12:44:02.577435 ===================================
3697 12:44:02.581251 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3698 12:44:02.584569 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3699 12:44:02.591299 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3700 12:44:02.591381 ===================================
3701 12:44:02.594365 LPDDR4 DRAM CONFIGURATION
3702 12:44:02.598469 ===================================
3703 12:44:02.601225 EX_ROW_EN[0] = 0x10
3704 12:44:02.601306 EX_ROW_EN[1] = 0x0
3705 12:44:02.604021 LP4Y_EN = 0x0
3706 12:44:02.604102 WORK_FSP = 0x0
3707 12:44:02.607580 WL = 0x2
3708 12:44:02.612016 RL = 0x2
3709 12:44:02.612098 BL = 0x2
3710 12:44:02.614299 RPST = 0x0
3711 12:44:02.614399 RD_PRE = 0x0
3712 12:44:02.617426 WR_PRE = 0x1
3713 12:44:02.617508 WR_PST = 0x0
3714 12:44:02.620668 DBI_WR = 0x0
3715 12:44:02.620795 DBI_RD = 0x0
3716 12:44:02.624118 OTF = 0x1
3717 12:44:02.627575 ===================================
3718 12:44:02.634111 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3719 12:44:02.637372 nWR fixed to 30
3720 12:44:02.637455 [ModeRegInit_LP4] CH0 RK0
3721 12:44:02.640495 [ModeRegInit_LP4] CH0 RK1
3722 12:44:02.643693 [ModeRegInit_LP4] CH1 RK0
3723 12:44:02.643775 [ModeRegInit_LP4] CH1 RK1
3724 12:44:02.647375 match AC timing 16
3725 12:44:02.650304 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3726 12:44:02.653728 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3727 12:44:02.660574 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3728 12:44:02.663532 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3729 12:44:02.670345 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3730 12:44:02.670427 ==
3731 12:44:02.673548 Dram Type= 6, Freq= 0, CH_0, rank 0
3732 12:44:02.676858 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3733 12:44:02.676941 ==
3734 12:44:02.683840 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3735 12:44:02.690221 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3736 12:44:02.694157 [CA 0] Center 36 (6~66) winsize 61
3737 12:44:02.698140 [CA 1] Center 35 (5~66) winsize 62
3738 12:44:02.699834 [CA 2] Center 34 (4~65) winsize 62
3739 12:44:02.704002 [CA 3] Center 34 (4~65) winsize 62
3740 12:44:02.706746 [CA 4] Center 33 (3~64) winsize 62
3741 12:44:02.710672 [CA 5] Center 33 (3~64) winsize 62
3742 12:44:02.710754
3743 12:44:02.713700 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3744 12:44:02.713782
3745 12:44:02.716599 [CATrainingPosCal] consider 1 rank data
3746 12:44:02.720166 u2DelayCellTimex100 = 270/100 ps
3747 12:44:02.723231 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3748 12:44:02.726254 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3749 12:44:02.729970 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3750 12:44:02.733200 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3751 12:44:02.736687 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3752 12:44:02.740122 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3753 12:44:02.740203
3754 12:44:02.746758 CA PerBit enable=1, Macro0, CA PI delay=33
3755 12:44:02.746839
3756 12:44:02.746904 [CBTSetCACLKResult] CA Dly = 33
3757 12:44:02.749924 CS Dly: 4 (0~35)
3758 12:44:02.750005 ==
3759 12:44:02.753103 Dram Type= 6, Freq= 0, CH_0, rank 1
3760 12:44:02.756183 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3761 12:44:02.756265 ==
3762 12:44:02.762888 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3763 12:44:02.769553 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3764 12:44:02.772731 [CA 0] Center 35 (5~66) winsize 62
3765 12:44:02.777492 [CA 1] Center 35 (5~66) winsize 62
3766 12:44:02.779339 [CA 2] Center 34 (4~65) winsize 62
3767 12:44:02.782864 [CA 3] Center 34 (4~65) winsize 62
3768 12:44:02.786012 [CA 4] Center 33 (3~64) winsize 62
3769 12:44:02.789209 [CA 5] Center 33 (3~64) winsize 62
3770 12:44:02.789291
3771 12:44:02.793220 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3772 12:44:02.793302
3773 12:44:02.796062 [CATrainingPosCal] consider 2 rank data
3774 12:44:02.800326 u2DelayCellTimex100 = 270/100 ps
3775 12:44:02.802788 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3776 12:44:02.806029 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3777 12:44:02.809540 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3778 12:44:02.812554 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3779 12:44:02.815915 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3780 12:44:02.819349 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3781 12:44:02.822508
3782 12:44:02.825660 CA PerBit enable=1, Macro0, CA PI delay=33
3783 12:44:02.825746
3784 12:44:02.829606 [CBTSetCACLKResult] CA Dly = 33
3785 12:44:02.829687 CS Dly: 4 (0~36)
3786 12:44:02.829752
3787 12:44:02.833058 ----->DramcWriteLeveling(PI) begin...
3788 12:44:02.833141 ==
3789 12:44:02.837068 Dram Type= 6, Freq= 0, CH_0, rank 0
3790 12:44:02.838987 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3791 12:44:02.842077 ==
3792 12:44:02.842160 Write leveling (Byte 0): 32 => 32
3793 12:44:02.845787 Write leveling (Byte 1): 30 => 30
3794 12:44:02.849027 DramcWriteLeveling(PI) end<-----
3795 12:44:02.849108
3796 12:44:02.849172 ==
3797 12:44:02.852483 Dram Type= 6, Freq= 0, CH_0, rank 0
3798 12:44:02.858762 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3799 12:44:02.858844 ==
3800 12:44:02.862344 [Gating] SW mode calibration
3801 12:44:02.868600 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3802 12:44:02.872228 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3803 12:44:02.875640 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3804 12:44:02.883212 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3805 12:44:02.885906 0 5 8 | B1->B0 | 3333 2f2f | 0 1 | (0 1) (0 0)
3806 12:44:02.888946 0 5 12 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
3807 12:44:02.895910 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3808 12:44:02.898856 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3809 12:44:02.902735 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3810 12:44:02.908417 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3811 12:44:02.912120 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3812 12:44:02.915228 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3813 12:44:02.922591 0 6 8 | B1->B0 | 2f2f 3535 | 0 1 | (0 0) (0 0)
3814 12:44:02.925735 0 6 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
3815 12:44:02.928885 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3816 12:44:02.935349 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3817 12:44:02.938167 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3818 12:44:02.941692 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3819 12:44:02.949457 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3820 12:44:02.951858 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3821 12:44:02.955401 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3822 12:44:02.961696 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3823 12:44:02.964659 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3824 12:44:02.969230 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3825 12:44:02.975044 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3826 12:44:02.978071 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3827 12:44:02.981122 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3828 12:44:02.987820 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3829 12:44:02.990905 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3830 12:44:02.995047 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3831 12:44:03.001694 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3832 12:44:03.004404 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3833 12:44:03.007695 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3834 12:44:03.014704 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3835 12:44:03.017438 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3836 12:44:03.021111 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3837 12:44:03.027526 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3838 12:44:03.031074 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3839 12:44:03.034421 Total UI for P1: 0, mck2ui 16
3840 12:44:03.037283 best dqsien dly found for B0: ( 0, 9, 8)
3841 12:44:03.040901 Total UI for P1: 0, mck2ui 16
3842 12:44:03.043801 best dqsien dly found for B1: ( 0, 9, 8)
3843 12:44:03.047078 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
3844 12:44:03.051402 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3845 12:44:03.051484
3846 12:44:03.053943 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
3847 12:44:03.057448 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3848 12:44:03.060550 [Gating] SW calibration Done
3849 12:44:03.060632 ==
3850 12:44:03.063722 Dram Type= 6, Freq= 0, CH_0, rank 0
3851 12:44:03.070753 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3852 12:44:03.070835 ==
3853 12:44:03.070899 RX Vref Scan: 0
3854 12:44:03.070960
3855 12:44:03.074242 RX Vref 0 -> 0, step: 1
3856 12:44:03.074323
3857 12:44:03.077231 RX Delay -230 -> 252, step: 16
3858 12:44:03.080035 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3859 12:44:03.083946 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3860 12:44:03.086665 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3861 12:44:03.093199 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3862 12:44:03.096928 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3863 12:44:03.099898 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3864 12:44:03.103810 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3865 12:44:03.110846 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
3866 12:44:03.113116 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3867 12:44:03.116577 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3868 12:44:03.119927 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3869 12:44:03.126456 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3870 12:44:03.129823 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3871 12:44:03.133270 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3872 12:44:03.136569 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3873 12:44:03.139726 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3874 12:44:03.142939 ==
3875 12:44:03.146884 Dram Type= 6, Freq= 0, CH_0, rank 0
3876 12:44:03.150079 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3877 12:44:03.150161 ==
3878 12:44:03.150225 DQS Delay:
3879 12:44:03.152836 DQS0 = 0, DQS1 = 0
3880 12:44:03.152917 DQM Delay:
3881 12:44:03.157102 DQM0 = 39, DQM1 = 33
3882 12:44:03.157183 DQ Delay:
3883 12:44:03.160138 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3884 12:44:03.164061 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =57
3885 12:44:03.166791 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3886 12:44:03.169608 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3887 12:44:03.169689
3888 12:44:03.169753
3889 12:44:03.169813 ==
3890 12:44:03.173508 Dram Type= 6, Freq= 0, CH_0, rank 0
3891 12:44:03.176813 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3892 12:44:03.176895 ==
3893 12:44:03.176960
3894 12:44:03.177020
3895 12:44:03.179569 TX Vref Scan disable
3896 12:44:03.183164 == TX Byte 0 ==
3897 12:44:03.185997 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
3898 12:44:03.189120 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
3899 12:44:03.193779 == TX Byte 1 ==
3900 12:44:03.196453 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3901 12:44:03.199112 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3902 12:44:03.199194 ==
3903 12:44:03.202816 Dram Type= 6, Freq= 0, CH_0, rank 0
3904 12:44:03.209771 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3905 12:44:03.209852 ==
3906 12:44:03.209917
3907 12:44:03.209976
3908 12:44:03.210034 TX Vref Scan disable
3909 12:44:03.213705 == TX Byte 0 ==
3910 12:44:03.217047 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
3911 12:44:03.224748 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
3912 12:44:03.224831 == TX Byte 1 ==
3913 12:44:03.226855 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3914 12:44:03.233326 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3915 12:44:03.233411
3916 12:44:03.233476 [DATLAT]
3917 12:44:03.233536 Freq=600, CH0 RK0
3918 12:44:03.233596
3919 12:44:03.237623 DATLAT Default: 0x9
3920 12:44:03.237704 0, 0xFFFF, sum = 0
3921 12:44:03.240140 1, 0xFFFF, sum = 0
3922 12:44:03.243404 2, 0xFFFF, sum = 0
3923 12:44:03.243486 3, 0xFFFF, sum = 0
3924 12:44:03.246616 4, 0xFFFF, sum = 0
3925 12:44:03.246750 5, 0xFFFF, sum = 0
3926 12:44:03.249991 6, 0xFFFF, sum = 0
3927 12:44:03.250100 7, 0x0, sum = 1
3928 12:44:03.250195 8, 0x0, sum = 2
3929 12:44:03.253732 9, 0x0, sum = 3
3930 12:44:03.253815 10, 0x0, sum = 4
3931 12:44:03.256476 best_step = 8
3932 12:44:03.256557
3933 12:44:03.256621 ==
3934 12:44:03.259917 Dram Type= 6, Freq= 0, CH_0, rank 0
3935 12:44:03.263086 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3936 12:44:03.263168 ==
3937 12:44:03.266632 RX Vref Scan: 1
3938 12:44:03.266713
3939 12:44:03.266778 RX Vref 0 -> 0, step: 1
3940 12:44:03.266838
3941 12:44:03.270045 RX Delay -195 -> 252, step: 8
3942 12:44:03.270127
3943 12:44:03.272962 Set Vref, RX VrefLevel [Byte0]: 46
3944 12:44:03.276561 [Byte1]: 50
3945 12:44:03.280471
3946 12:44:03.280553 Final RX Vref Byte 0 = 46 to rank0
3947 12:44:03.284177 Final RX Vref Byte 1 = 50 to rank0
3948 12:44:03.287425 Final RX Vref Byte 0 = 46 to rank1
3949 12:44:03.290510 Final RX Vref Byte 1 = 50 to rank1==
3950 12:44:03.293763 Dram Type= 6, Freq= 0, CH_0, rank 0
3951 12:44:03.300588 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3952 12:44:03.300670 ==
3953 12:44:03.300761 DQS Delay:
3954 12:44:03.300835 DQS0 = 0, DQS1 = 0
3955 12:44:03.303705 DQM Delay:
3956 12:44:03.303786 DQM0 = 39, DQM1 = 30
3957 12:44:03.307844 DQ Delay:
3958 12:44:03.310582 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =36
3959 12:44:03.314050 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =44
3960 12:44:03.316913 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
3961 12:44:03.320619 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =40
3962 12:44:03.320701
3963 12:44:03.320808
3964 12:44:03.327527 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d4d, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
3965 12:44:03.330237 CH0 RK0: MR19=808, MR18=4D4D
3966 12:44:03.337014 CH0_RK0: MR19=0x808, MR18=0x4D4D, DQSOSC=395, MR23=63, INC=168, DEC=112
3967 12:44:03.337096
3968 12:44:03.340258 ----->DramcWriteLeveling(PI) begin...
3969 12:44:03.340340 ==
3970 12:44:03.344944 Dram Type= 6, Freq= 0, CH_0, rank 1
3971 12:44:03.346851 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3972 12:44:03.346934 ==
3973 12:44:03.350490 Write leveling (Byte 0): 32 => 32
3974 12:44:03.353567 Write leveling (Byte 1): 29 => 29
3975 12:44:03.356603 DramcWriteLeveling(PI) end<-----
3976 12:44:03.356684
3977 12:44:03.356755 ==
3978 12:44:03.360312 Dram Type= 6, Freq= 0, CH_0, rank 1
3979 12:44:03.363602 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3980 12:44:03.363684 ==
3981 12:44:03.366523 [Gating] SW mode calibration
3982 12:44:03.373882 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3983 12:44:03.380639 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3984 12:44:03.383387 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3985 12:44:03.389846 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3986 12:44:03.392939 0 5 8 | B1->B0 | 3333 2f2f | 0 0 | (1 1) (0 0)
3987 12:44:03.396441 0 5 12 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
3988 12:44:03.403040 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 12:44:03.406765 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 12:44:03.409652 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 12:44:03.415916 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 12:44:03.420025 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 12:44:03.422957 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 12:44:03.429600 0 6 8 | B1->B0 | 2525 3737 | 0 0 | (0 0) (0 0)
3995 12:44:03.432736 0 6 12 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
3996 12:44:03.436017 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 12:44:03.443192 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 12:44:03.447185 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 12:44:03.450067 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 12:44:03.456828 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 12:44:03.459867 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 12:44:03.462761 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 12:44:03.469605 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 12:44:03.472532 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 12:44:03.475896 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 12:44:03.479071 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 12:44:03.485671 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 12:44:03.488888 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 12:44:03.492658 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 12:44:03.498969 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 12:44:03.502610 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 12:44:03.505488 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 12:44:03.512438 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 12:44:03.515876 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 12:44:03.519068 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 12:44:03.525271 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 12:44:03.529332 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4018 12:44:03.533183 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4019 12:44:03.538562 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4020 12:44:03.542442 Total UI for P1: 0, mck2ui 16
4021 12:44:03.545442 best dqsien dly found for B0: ( 0, 9, 6)
4022 12:44:03.548553 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 12:44:03.552360 Total UI for P1: 0, mck2ui 16
4024 12:44:03.555637 best dqsien dly found for B1: ( 0, 9, 10)
4025 12:44:03.558992 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4026 12:44:03.563456 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4027 12:44:03.563538
4028 12:44:03.565965 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4029 12:44:03.568861 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4030 12:44:03.572344 [Gating] SW calibration Done
4031 12:44:03.572427 ==
4032 12:44:03.575017 Dram Type= 6, Freq= 0, CH_0, rank 1
4033 12:44:03.582133 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4034 12:44:03.582215 ==
4035 12:44:03.582279 RX Vref Scan: 0
4036 12:44:03.582340
4037 12:44:03.585291 RX Vref 0 -> 0, step: 1
4038 12:44:03.585373
4039 12:44:03.588567 RX Delay -230 -> 252, step: 16
4040 12:44:03.591860 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4041 12:44:03.594928 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4042 12:44:03.598526 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4043 12:44:03.605123 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4044 12:44:03.608341 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4045 12:44:03.611811 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4046 12:44:03.614789 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4047 12:44:03.621655 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4048 12:44:03.624616 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4049 12:44:03.628965 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4050 12:44:03.631302 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4051 12:44:03.637781 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4052 12:44:03.641113 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4053 12:44:03.645039 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4054 12:44:03.648497 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4055 12:44:03.655143 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4056 12:44:03.655251 ==
4057 12:44:03.657928 Dram Type= 6, Freq= 0, CH_0, rank 1
4058 12:44:03.660972 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4059 12:44:03.661054 ==
4060 12:44:03.661118 DQS Delay:
4061 12:44:03.665254 DQS0 = 0, DQS1 = 0
4062 12:44:03.665335 DQM Delay:
4063 12:44:03.668070 DQM0 = 42, DQM1 = 33
4064 12:44:03.668157 DQ Delay:
4065 12:44:03.671235 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =33
4066 12:44:03.674504 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =57
4067 12:44:03.677886 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4068 12:44:03.681225 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4069 12:44:03.681306
4070 12:44:03.681370
4071 12:44:03.681429 ==
4072 12:44:03.684214 Dram Type= 6, Freq= 0, CH_0, rank 1
4073 12:44:03.688109 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4074 12:44:03.688191 ==
4075 12:44:03.688256
4076 12:44:03.688315
4077 12:44:03.691120 TX Vref Scan disable
4078 12:44:03.694665 == TX Byte 0 ==
4079 12:44:03.697914 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4080 12:44:03.701094 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4081 12:44:03.703903 == TX Byte 1 ==
4082 12:44:03.707456 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4083 12:44:03.711392 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4084 12:44:03.711473 ==
4085 12:44:03.714129 Dram Type= 6, Freq= 0, CH_0, rank 1
4086 12:44:03.720283 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4087 12:44:03.720365 ==
4088 12:44:03.720430
4089 12:44:03.720490
4090 12:44:03.720547 TX Vref Scan disable
4091 12:44:03.725789 == TX Byte 0 ==
4092 12:44:03.729299 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4093 12:44:03.736257 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4094 12:44:03.736339 == TX Byte 1 ==
4095 12:44:03.738742 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4096 12:44:03.744874 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4097 12:44:03.744956
4098 12:44:03.745021 [DATLAT]
4099 12:44:03.745081 Freq=600, CH0 RK1
4100 12:44:03.745139
4101 12:44:03.749528 DATLAT Default: 0x8
4102 12:44:03.749610 0, 0xFFFF, sum = 0
4103 12:44:03.752153 1, 0xFFFF, sum = 0
4104 12:44:03.752235 2, 0xFFFF, sum = 0
4105 12:44:03.755682 3, 0xFFFF, sum = 0
4106 12:44:03.758149 4, 0xFFFF, sum = 0
4107 12:44:03.758232 5, 0xFFFF, sum = 0
4108 12:44:03.761469 6, 0xFFFF, sum = 0
4109 12:44:03.761551 7, 0x0, sum = 1
4110 12:44:03.761617 8, 0x0, sum = 2
4111 12:44:03.764654 9, 0x0, sum = 3
4112 12:44:03.764788 10, 0x0, sum = 4
4113 12:44:03.768026 best_step = 8
4114 12:44:03.768107
4115 12:44:03.768170 ==
4116 12:44:03.771742 Dram Type= 6, Freq= 0, CH_0, rank 1
4117 12:44:03.774516 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4118 12:44:03.774601 ==
4119 12:44:03.777889 RX Vref Scan: 0
4120 12:44:03.777971
4121 12:44:03.778035 RX Vref 0 -> 0, step: 1
4122 12:44:03.778096
4123 12:44:03.781604 RX Delay -195 -> 252, step: 8
4124 12:44:03.789031 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4125 12:44:03.792484 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4126 12:44:03.796063 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4127 12:44:03.799393 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4128 12:44:03.805908 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4129 12:44:03.809482 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4130 12:44:03.811944 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4131 12:44:03.815243 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4132 12:44:03.821750 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4133 12:44:03.825498 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4134 12:44:03.828621 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4135 12:44:03.831424 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4136 12:44:03.838702 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4137 12:44:03.842125 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4138 12:44:03.845177 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4139 12:44:03.848060 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4140 12:44:03.848142 ==
4141 12:44:03.851709 Dram Type= 6, Freq= 0, CH_0, rank 1
4142 12:44:03.858264 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4143 12:44:03.858346 ==
4144 12:44:03.858411 DQS Delay:
4145 12:44:03.861901 DQS0 = 0, DQS1 = 0
4146 12:44:03.861983 DQM Delay:
4147 12:44:03.862047 DQM0 = 40, DQM1 = 33
4148 12:44:03.864612 DQ Delay:
4149 12:44:03.867969 DQ0 =36, DQ1 =44, DQ2 =40, DQ3 =36
4150 12:44:03.871190 DQ4 =44, DQ5 =32, DQ6 =44, DQ7 =48
4151 12:44:03.874955 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4152 12:44:03.877951 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4153 12:44:03.878032
4154 12:44:03.878096
4155 12:44:03.884733 [DQSOSCAuto] RK1, (LSB)MR18= 0x6565, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
4156 12:44:03.887673 CH0 RK1: MR19=808, MR18=6565
4157 12:44:03.894393 CH0_RK1: MR19=0x808, MR18=0x6565, DQSOSC=390, MR23=63, INC=172, DEC=114
4158 12:44:03.898075 [RxdqsGatingPostProcess] freq 600
4159 12:44:03.901615 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4160 12:44:03.904641 Pre-setting of DQS Precalculation
4161 12:44:03.911539 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4162 12:44:03.911621 ==
4163 12:44:03.915167 Dram Type= 6, Freq= 0, CH_1, rank 0
4164 12:44:03.917534 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4165 12:44:03.917616 ==
4166 12:44:03.924665 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4167 12:44:03.931353 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4168 12:44:03.934454 [CA 0] Center 35 (5~66) winsize 62
4169 12:44:03.937699 [CA 1] Center 35 (5~65) winsize 61
4170 12:44:03.940847 [CA 2] Center 33 (3~64) winsize 62
4171 12:44:03.945974 [CA 3] Center 33 (3~64) winsize 62
4172 12:44:03.948555 [CA 4] Center 32 (2~63) winsize 62
4173 12:44:03.950935 [CA 5] Center 32 (2~63) winsize 62
4174 12:44:03.951016
4175 12:44:03.954142 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4176 12:44:03.954224
4177 12:44:03.957621 [CATrainingPosCal] consider 1 rank data
4178 12:44:03.960439 u2DelayCellTimex100 = 270/100 ps
4179 12:44:03.963804 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4180 12:44:03.967006 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4181 12:44:03.970761 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4182 12:44:03.975133 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4183 12:44:03.977182 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4184 12:44:03.980358 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4185 12:44:03.980440
4186 12:44:03.987333 CA PerBit enable=1, Macro0, CA PI delay=32
4187 12:44:03.987414
4188 12:44:03.987479 [CBTSetCACLKResult] CA Dly = 32
4189 12:44:03.990473 CS Dly: 4 (0~35)
4190 12:44:03.990581 ==
4191 12:44:03.993574 Dram Type= 6, Freq= 0, CH_1, rank 1
4192 12:44:03.996670 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4193 12:44:03.996803 ==
4194 12:44:04.003796 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4195 12:44:04.009973 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4196 12:44:04.013274 [CA 0] Center 35 (5~66) winsize 62
4197 12:44:04.017364 [CA 1] Center 34 (4~65) winsize 62
4198 12:44:04.020041 [CA 2] Center 33 (3~64) winsize 62
4199 12:44:04.023863 [CA 3] Center 33 (3~64) winsize 62
4200 12:44:04.026793 [CA 4] Center 32 (2~63) winsize 62
4201 12:44:04.029992 [CA 5] Center 32 (2~63) winsize 62
4202 12:44:04.030074
4203 12:44:04.033451 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4204 12:44:04.033532
4205 12:44:04.037128 [CATrainingPosCal] consider 2 rank data
4206 12:44:04.039866 u2DelayCellTimex100 = 270/100 ps
4207 12:44:04.043188 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4208 12:44:04.046656 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4209 12:44:04.049455 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4210 12:44:04.052846 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4211 12:44:04.059974 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4212 12:44:04.063002 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4213 12:44:04.063083
4214 12:44:04.066202 CA PerBit enable=1, Macro0, CA PI delay=32
4215 12:44:04.066284
4216 12:44:04.069782 [CBTSetCACLKResult] CA Dly = 32
4217 12:44:04.069863 CS Dly: 4 (0~36)
4218 12:44:04.069927
4219 12:44:04.073823 ----->DramcWriteLeveling(PI) begin...
4220 12:44:04.073906 ==
4221 12:44:04.076815 Dram Type= 6, Freq= 0, CH_1, rank 0
4222 12:44:04.083144 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4223 12:44:04.083226 ==
4224 12:44:04.086479 Write leveling (Byte 0): 25 => 25
4225 12:44:04.086560 Write leveling (Byte 1): 29 => 29
4226 12:44:04.089448 DramcWriteLeveling(PI) end<-----
4227 12:44:04.089530
4228 12:44:04.093591 ==
4229 12:44:04.093672 Dram Type= 6, Freq= 0, CH_1, rank 0
4230 12:44:04.099532 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4231 12:44:04.099615 ==
4232 12:44:04.102652 [Gating] SW mode calibration
4233 12:44:04.109145 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4234 12:44:04.113618 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4235 12:44:04.119697 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4236 12:44:04.123118 0 5 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
4237 12:44:04.126155 0 5 8 | B1->B0 | 2f2f 2626 | 1 0 | (1 1) (1 0)
4238 12:44:04.132885 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4239 12:44:04.135854 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 12:44:04.139054 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 12:44:04.145886 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 12:44:04.149630 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 12:44:04.152930 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 12:44:04.159551 0 6 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
4245 12:44:04.162385 0 6 8 | B1->B0 | 3535 3f3f | 0 0 | (0 0) (0 0)
4246 12:44:04.165844 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 12:44:04.169623 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 12:44:04.175898 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 12:44:04.179912 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 12:44:04.182695 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 12:44:04.189527 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 12:44:04.193009 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4253 12:44:04.196394 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4254 12:44:04.203423 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 12:44:04.205792 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 12:44:04.209703 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 12:44:04.215989 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 12:44:04.218907 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 12:44:04.222535 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 12:44:04.229427 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 12:44:04.233595 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 12:44:04.235683 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 12:44:04.242470 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 12:44:04.245891 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 12:44:04.248614 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 12:44:04.255819 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 12:44:04.259768 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 12:44:04.262362 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4269 12:44:04.265726 Total UI for P1: 0, mck2ui 16
4270 12:44:04.268517 best dqsien dly found for B0: ( 0, 9, 2)
4271 12:44:04.275310 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4272 12:44:04.278769 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4273 12:44:04.282003 Total UI for P1: 0, mck2ui 16
4274 12:44:04.286118 best dqsien dly found for B1: ( 0, 9, 6)
4275 12:44:04.288533 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4276 12:44:04.292021 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4277 12:44:04.292102
4278 12:44:04.295333 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4279 12:44:04.298668 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4280 12:44:04.301665 [Gating] SW calibration Done
4281 12:44:04.301746 ==
4282 12:44:04.305878 Dram Type= 6, Freq= 0, CH_1, rank 0
4283 12:44:04.309076 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4284 12:44:04.312004 ==
4285 12:44:04.312085 RX Vref Scan: 0
4286 12:44:04.312150
4287 12:44:04.315196 RX Vref 0 -> 0, step: 1
4288 12:44:04.315290
4289 12:44:04.318589 RX Delay -230 -> 252, step: 16
4290 12:44:04.321936 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4291 12:44:04.325378 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4292 12:44:04.328207 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4293 12:44:04.334831 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4294 12:44:04.338176 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4295 12:44:04.341726 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4296 12:44:04.344471 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4297 12:44:04.348565 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4298 12:44:04.354642 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4299 12:44:04.357774 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4300 12:44:04.361395 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4301 12:44:04.364607 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4302 12:44:04.371173 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4303 12:44:04.374917 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4304 12:44:04.378435 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4305 12:44:04.381159 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4306 12:44:04.381240 ==
4307 12:44:04.384402 Dram Type= 6, Freq= 0, CH_1, rank 0
4308 12:44:04.391601 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4309 12:44:04.391683 ==
4310 12:44:04.391746 DQS Delay:
4311 12:44:04.394584 DQS0 = 0, DQS1 = 0
4312 12:44:04.394665 DQM Delay:
4313 12:44:04.394728 DQM0 = 39, DQM1 = 34
4314 12:44:04.397638 DQ Delay:
4315 12:44:04.400641 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4316 12:44:04.404178 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4317 12:44:04.407502 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4318 12:44:04.411078 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =49
4319 12:44:04.411158
4320 12:44:04.411221
4321 12:44:04.411281 ==
4322 12:44:04.414483 Dram Type= 6, Freq= 0, CH_1, rank 0
4323 12:44:04.418468 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4324 12:44:04.418550 ==
4325 12:44:04.418614
4326 12:44:04.418673
4327 12:44:04.421265 TX Vref Scan disable
4328 12:44:04.424195 == TX Byte 0 ==
4329 12:44:04.427771 Update DQ dly =569 (2 ,1, 25) DQ OEN =(1 ,6)
4330 12:44:04.431086 Update DQM dly =569 (2 ,1, 25) DQM OEN =(1 ,6)
4331 12:44:04.433990 == TX Byte 1 ==
4332 12:44:04.438000 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4333 12:44:04.440656 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4334 12:44:04.440833 ==
4335 12:44:04.444094 Dram Type= 6, Freq= 0, CH_1, rank 0
4336 12:44:04.447604 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4337 12:44:04.450378 ==
4338 12:44:04.450459
4339 12:44:04.450523
4340 12:44:04.450582 TX Vref Scan disable
4341 12:44:04.454650 == TX Byte 0 ==
4342 12:44:04.458351 Update DQ dly =569 (2 ,1, 25) DQ OEN =(1 ,6)
4343 12:44:04.464434 Update DQM dly =569 (2 ,1, 25) DQM OEN =(1 ,6)
4344 12:44:04.464524 == TX Byte 1 ==
4345 12:44:04.468276 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4346 12:44:04.474483 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4347 12:44:04.474564
4348 12:44:04.474628 [DATLAT]
4349 12:44:04.474688 Freq=600, CH1 RK0
4350 12:44:04.474745
4351 12:44:04.477807 DATLAT Default: 0x9
4352 12:44:04.477887 0, 0xFFFF, sum = 0
4353 12:44:04.481140 1, 0xFFFF, sum = 0
4354 12:44:04.484695 2, 0xFFFF, sum = 0
4355 12:44:04.484819 3, 0xFFFF, sum = 0
4356 12:44:04.488144 4, 0xFFFF, sum = 0
4357 12:44:04.488227 5, 0xFFFF, sum = 0
4358 12:44:04.491317 6, 0xFFFF, sum = 0
4359 12:44:04.491400 7, 0x0, sum = 1
4360 12:44:04.491465 8, 0x0, sum = 2
4361 12:44:04.494068 9, 0x0, sum = 3
4362 12:44:04.494151 10, 0x0, sum = 4
4363 12:44:04.497914 best_step = 8
4364 12:44:04.497995
4365 12:44:04.498059 ==
4366 12:44:04.501567 Dram Type= 6, Freq= 0, CH_1, rank 0
4367 12:44:04.504592 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4368 12:44:04.504700 ==
4369 12:44:04.507701 RX Vref Scan: 1
4370 12:44:04.507782
4371 12:44:04.507846 RX Vref 0 -> 0, step: 1
4372 12:44:04.507906
4373 12:44:04.510754 RX Delay -195 -> 252, step: 8
4374 12:44:04.510836
4375 12:44:04.514759 Set Vref, RX VrefLevel [Byte0]: 54
4376 12:44:04.517519 [Byte1]: 50
4377 12:44:04.521673
4378 12:44:04.521755 Final RX Vref Byte 0 = 54 to rank0
4379 12:44:04.524859 Final RX Vref Byte 1 = 50 to rank0
4380 12:44:04.528626 Final RX Vref Byte 0 = 54 to rank1
4381 12:44:04.532341 Final RX Vref Byte 1 = 50 to rank1==
4382 12:44:04.534617 Dram Type= 6, Freq= 0, CH_1, rank 0
4383 12:44:04.541589 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4384 12:44:04.541671 ==
4385 12:44:04.541736 DQS Delay:
4386 12:44:04.544988 DQS0 = 0, DQS1 = 0
4387 12:44:04.545069 DQM Delay:
4388 12:44:04.545133 DQM0 = 38, DQM1 = 31
4389 12:44:04.548127 DQ Delay:
4390 12:44:04.551802 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4391 12:44:04.554851 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4392 12:44:04.558082 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =24
4393 12:44:04.561718 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4394 12:44:04.561800
4395 12:44:04.561864
4396 12:44:04.568233 [DQSOSCAuto] RK0, (LSB)MR18= 0x7979, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
4397 12:44:04.571438 CH1 RK0: MR19=808, MR18=7979
4398 12:44:04.577642 CH1_RK0: MR19=0x808, MR18=0x7979, DQSOSC=387, MR23=63, INC=175, DEC=116
4399 12:44:04.577724
4400 12:44:04.581534 ----->DramcWriteLeveling(PI) begin...
4401 12:44:04.581617 ==
4402 12:44:04.584986 Dram Type= 6, Freq= 0, CH_1, rank 1
4403 12:44:04.588146 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4404 12:44:04.588228 ==
4405 12:44:04.591001 Write leveling (Byte 0): 30 => 30
4406 12:44:04.594737 Write leveling (Byte 1): 27 => 27
4407 12:44:04.598098 DramcWriteLeveling(PI) end<-----
4408 12:44:04.598180
4409 12:44:04.598244 ==
4410 12:44:04.601267 Dram Type= 6, Freq= 0, CH_1, rank 1
4411 12:44:04.604902 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4412 12:44:04.607689 ==
4413 12:44:04.607770 [Gating] SW mode calibration
4414 12:44:04.614116 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4415 12:44:04.620944 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4416 12:44:04.624037 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4417 12:44:04.631390 0 5 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
4418 12:44:04.634370 0 5 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4419 12:44:04.637342 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 12:44:04.643704 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 12:44:04.646919 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 12:44:04.650612 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 12:44:04.657474 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 12:44:04.661090 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 12:44:04.663928 0 6 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
4426 12:44:04.670320 0 6 8 | B1->B0 | 3232 4141 | 0 0 | (0 0) (0 0)
4427 12:44:04.674594 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 12:44:04.677691 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 12:44:04.684217 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 12:44:04.687287 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 12:44:04.690658 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 12:44:04.697082 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 12:44:04.701499 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 12:44:04.704037 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4435 12:44:04.710262 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 12:44:04.714066 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 12:44:04.716853 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 12:44:04.723230 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 12:44:04.727049 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 12:44:04.729982 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 12:44:04.733489 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 12:44:04.740021 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 12:44:04.743288 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 12:44:04.746696 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 12:44:04.753007 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 12:44:04.756492 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 12:44:04.760003 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 12:44:04.767313 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 12:44:04.769970 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4450 12:44:04.773317 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 12:44:04.776498 Total UI for P1: 0, mck2ui 16
4452 12:44:04.779667 best dqsien dly found for B0: ( 0, 9, 4)
4453 12:44:04.783751 Total UI for P1: 0, mck2ui 16
4454 12:44:04.786885 best dqsien dly found for B1: ( 0, 9, 6)
4455 12:44:04.789448 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4456 12:44:04.792703 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4457 12:44:04.795901
4458 12:44:04.799765 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4459 12:44:04.802834 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4460 12:44:04.806362 [Gating] SW calibration Done
4461 12:44:04.806443 ==
4462 12:44:04.810284 Dram Type= 6, Freq= 0, CH_1, rank 1
4463 12:44:04.812937 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4464 12:44:04.813020 ==
4465 12:44:04.813085 RX Vref Scan: 0
4466 12:44:04.815499
4467 12:44:04.815580 RX Vref 0 -> 0, step: 1
4468 12:44:04.815645
4469 12:44:04.819119 RX Delay -230 -> 252, step: 16
4470 12:44:04.822577 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4471 12:44:04.829509 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4472 12:44:04.832895 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4473 12:44:04.835686 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4474 12:44:04.839447 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4475 12:44:04.845665 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4476 12:44:04.848737 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4477 12:44:04.852269 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4478 12:44:04.855964 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4479 12:44:04.858682 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4480 12:44:04.865843 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4481 12:44:04.868840 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4482 12:44:04.871947 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4483 12:44:04.875152 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4484 12:44:04.881878 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4485 12:44:04.885317 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4486 12:44:04.885399 ==
4487 12:44:04.889288 Dram Type= 6, Freq= 0, CH_1, rank 1
4488 12:44:04.891976 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4489 12:44:04.892058 ==
4490 12:44:04.895463 DQS Delay:
4491 12:44:04.895544 DQS0 = 0, DQS1 = 0
4492 12:44:04.895609 DQM Delay:
4493 12:44:04.898690 DQM0 = 42, DQM1 = 34
4494 12:44:04.898774 DQ Delay:
4495 12:44:04.902022 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4496 12:44:04.905243 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4497 12:44:04.908635 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4498 12:44:04.911681 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4499 12:44:04.911763
4500 12:44:04.911826
4501 12:44:04.911886 ==
4502 12:44:04.914786 Dram Type= 6, Freq= 0, CH_1, rank 1
4503 12:44:04.922025 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4504 12:44:04.922108 ==
4505 12:44:04.922172
4506 12:44:04.922257
4507 12:44:04.922392 TX Vref Scan disable
4508 12:44:04.926071 == TX Byte 0 ==
4509 12:44:04.929429 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4510 12:44:04.936380 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4511 12:44:04.936465 == TX Byte 1 ==
4512 12:44:04.938460 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4513 12:44:04.945340 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4514 12:44:04.945421 ==
4515 12:44:04.948691 Dram Type= 6, Freq= 0, CH_1, rank 1
4516 12:44:04.951941 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4517 12:44:04.952064 ==
4518 12:44:04.952129
4519 12:44:04.952190
4520 12:44:04.955757 TX Vref Scan disable
4521 12:44:04.958811 == TX Byte 0 ==
4522 12:44:04.962351 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4523 12:44:04.965049 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4524 12:44:04.969219 == TX Byte 1 ==
4525 12:44:04.971957 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4526 12:44:04.975368 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4527 12:44:04.975449
4528 12:44:04.975514 [DATLAT]
4529 12:44:04.978784 Freq=600, CH1 RK1
4530 12:44:04.978865
4531 12:44:04.982026 DATLAT Default: 0x8
4532 12:44:04.982107 0, 0xFFFF, sum = 0
4533 12:44:04.985499 1, 0xFFFF, sum = 0
4534 12:44:04.985582 2, 0xFFFF, sum = 0
4535 12:44:04.988964 3, 0xFFFF, sum = 0
4536 12:44:04.989047 4, 0xFFFF, sum = 0
4537 12:44:04.991652 5, 0xFFFF, sum = 0
4538 12:44:04.991735 6, 0xFFFF, sum = 0
4539 12:44:04.994940 7, 0x0, sum = 1
4540 12:44:04.995023 8, 0x0, sum = 2
4541 12:44:04.995089 9, 0x0, sum = 3
4542 12:44:04.998650 10, 0x0, sum = 4
4543 12:44:04.998732 best_step = 8
4544 12:44:04.998800
4545 12:44:04.998871 ==
4546 12:44:05.002351 Dram Type= 6, Freq= 0, CH_1, rank 1
4547 12:44:05.008404 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4548 12:44:05.008486 ==
4549 12:44:05.008551 RX Vref Scan: 0
4550 12:44:05.008611
4551 12:44:05.012833 RX Vref 0 -> 0, step: 1
4552 12:44:05.012915
4553 12:44:05.014740 RX Delay -195 -> 252, step: 8
4554 12:44:05.018440 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4555 12:44:05.025392 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4556 12:44:05.028636 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4557 12:44:05.031838 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4558 12:44:05.035655 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4559 12:44:05.041288 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4560 12:44:05.044564 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4561 12:44:05.048921 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4562 12:44:05.051528 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4563 12:44:05.054745 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4564 12:44:05.061478 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4565 12:44:05.064580 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4566 12:44:05.068611 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4567 12:44:05.074768 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4568 12:44:05.078258 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4569 12:44:05.081223 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4570 12:44:05.081304 ==
4571 12:44:05.084548 Dram Type= 6, Freq= 0, CH_1, rank 1
4572 12:44:05.088359 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4573 12:44:05.088441 ==
4574 12:44:05.090876 DQS Delay:
4575 12:44:05.090958 DQS0 = 0, DQS1 = 0
4576 12:44:05.094508 DQM Delay:
4577 12:44:05.094590 DQM0 = 37, DQM1 = 29
4578 12:44:05.094655 DQ Delay:
4579 12:44:05.097459 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4580 12:44:05.101012 DQ4 =40, DQ5 =48, DQ6 =44, DQ7 =32
4581 12:44:05.105504 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4582 12:44:05.107793 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4583 12:44:05.107874
4584 12:44:05.107939
4585 12:44:05.118007 [DQSOSCAuto] RK1, (LSB)MR18= 0x6060, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4586 12:44:05.121161 CH1 RK1: MR19=808, MR18=6060
4587 12:44:05.127713 CH1_RK1: MR19=0x808, MR18=0x6060, DQSOSC=391, MR23=63, INC=171, DEC=114
4588 12:44:05.131074 [RxdqsGatingPostProcess] freq 600
4589 12:44:05.134039 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4590 12:44:05.138187 Pre-setting of DQS Precalculation
4591 12:44:05.140909 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4592 12:44:05.150446 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4593 12:44:05.157209 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4594 12:44:05.157291
4595 12:44:05.157355
4596 12:44:05.160399 [Calibration Summary] 1200 Mbps
4597 12:44:05.160480 CH 0, Rank 0
4598 12:44:05.163828 SW Impedance : PASS
4599 12:44:05.166955 DUTY Scan : NO K
4600 12:44:05.167036 ZQ Calibration : PASS
4601 12:44:05.170334 Jitter Meter : NO K
4602 12:44:05.170416 CBT Training : PASS
4603 12:44:05.173826 Write leveling : PASS
4604 12:44:05.176772 RX DQS gating : PASS
4605 12:44:05.176867 RX DQ/DQS(RDDQC) : PASS
4606 12:44:05.180329 TX DQ/DQS : PASS
4607 12:44:05.183963 RX DATLAT : PASS
4608 12:44:05.184045 RX DQ/DQS(Engine): PASS
4609 12:44:05.187302 TX OE : NO K
4610 12:44:05.187383 All Pass.
4611 12:44:05.187448
4612 12:44:05.190456 CH 0, Rank 1
4613 12:44:05.190537 SW Impedance : PASS
4614 12:44:05.193549 DUTY Scan : NO K
4615 12:44:05.196964 ZQ Calibration : PASS
4616 12:44:05.197047 Jitter Meter : NO K
4617 12:44:05.200073 CBT Training : PASS
4618 12:44:05.203439 Write leveling : PASS
4619 12:44:05.203520 RX DQS gating : PASS
4620 12:44:05.206751 RX DQ/DQS(RDDQC) : PASS
4621 12:44:05.210440 TX DQ/DQS : PASS
4622 12:44:05.210522 RX DATLAT : PASS
4623 12:44:05.213366 RX DQ/DQS(Engine): PASS
4624 12:44:05.216287 TX OE : NO K
4625 12:44:05.216371 All Pass.
4626 12:44:05.216437
4627 12:44:05.216497 CH 1, Rank 0
4628 12:44:05.219896 SW Impedance : PASS
4629 12:44:05.223270 DUTY Scan : NO K
4630 12:44:05.223352 ZQ Calibration : PASS
4631 12:44:05.226514 Jitter Meter : NO K
4632 12:44:05.229820 CBT Training : PASS
4633 12:44:05.229901 Write leveling : PASS
4634 12:44:05.233273 RX DQS gating : PASS
4635 12:44:05.233354 RX DQ/DQS(RDDQC) : PASS
4636 12:44:05.237151 TX DQ/DQS : PASS
4637 12:44:05.239666 RX DATLAT : PASS
4638 12:44:05.239750 RX DQ/DQS(Engine): PASS
4639 12:44:05.243424 TX OE : NO K
4640 12:44:05.243506 All Pass.
4641 12:44:05.243571
4642 12:44:05.249615 CH 1, Rank 1
4643 12:44:05.249696 SW Impedance : PASS
4644 12:44:05.249946 DUTY Scan : NO K
4645 12:44:05.252578 ZQ Calibration : PASS
4646 12:44:05.252659 Jitter Meter : NO K
4647 12:44:05.256462 CBT Training : PASS
4648 12:44:05.259767 Write leveling : PASS
4649 12:44:05.259848 RX DQS gating : PASS
4650 12:44:05.262534 RX DQ/DQS(RDDQC) : PASS
4651 12:44:05.265766 TX DQ/DQS : PASS
4652 12:44:05.265849 RX DATLAT : PASS
4653 12:44:05.269466 RX DQ/DQS(Engine): PASS
4654 12:44:05.273019 TX OE : NO K
4655 12:44:05.273101 All Pass.
4656 12:44:05.273166
4657 12:44:05.273226 DramC Write-DBI off
4658 12:44:05.275794 PER_BANK_REFRESH: Hybrid Mode
4659 12:44:05.279535 TX_TRACKING: ON
4660 12:44:05.286004 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4661 12:44:05.293558 [FAST_K] Save calibration result to emmc
4662 12:44:05.296015 dramc_set_vcore_voltage set vcore to 662500
4663 12:44:05.296097 Read voltage for 933, 3
4664 12:44:05.299267 Vio18 = 0
4665 12:44:05.299349 Vcore = 662500
4666 12:44:05.299414 Vdram = 0
4667 12:44:05.302764 Vddq = 0
4668 12:44:05.302845 Vmddr = 0
4669 12:44:05.305970 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4670 12:44:05.312910 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4671 12:44:05.315823 MEM_TYPE=3, freq_sel=17
4672 12:44:05.319249 sv_algorithm_assistance_LP4_1600
4673 12:44:05.322590 ============ PULL DRAM RESETB DOWN ============
4674 12:44:05.325909 ========== PULL DRAM RESETB DOWN end =========
4675 12:44:05.332868 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4676 12:44:05.332950 ===================================
4677 12:44:05.335443 LPDDR4 DRAM CONFIGURATION
4678 12:44:05.339561 ===================================
4679 12:44:05.342836 EX_ROW_EN[0] = 0x0
4680 12:44:05.342918 EX_ROW_EN[1] = 0x0
4681 12:44:05.345776 LP4Y_EN = 0x0
4682 12:44:05.345857 WORK_FSP = 0x0
4683 12:44:05.348944 WL = 0x3
4684 12:44:05.349026 RL = 0x3
4685 12:44:05.354030 BL = 0x2
4686 12:44:05.356866 RPST = 0x0
4687 12:44:05.356947 RD_PRE = 0x0
4688 12:44:05.358738 WR_PRE = 0x1
4689 12:44:05.358819 WR_PST = 0x0
4690 12:44:05.363547 DBI_WR = 0x0
4691 12:44:05.363628 DBI_RD = 0x0
4692 12:44:05.366971 OTF = 0x1
4693 12:44:05.369291 ===================================
4694 12:44:05.372270 ===================================
4695 12:44:05.372352 ANA top config
4696 12:44:05.375732 ===================================
4697 12:44:05.378691 DLL_ASYNC_EN = 0
4698 12:44:05.381944 ALL_SLAVE_EN = 1
4699 12:44:05.382025 NEW_RANK_MODE = 1
4700 12:44:05.385474 DLL_IDLE_MODE = 1
4701 12:44:05.388161 LP45_APHY_COMB_EN = 1
4702 12:44:05.391498 TX_ODT_DIS = 1
4703 12:44:05.394794 NEW_8X_MODE = 1
4704 12:44:05.399152 ===================================
4705 12:44:05.399234 ===================================
4706 12:44:05.402213 data_rate = 1866
4707 12:44:05.405554 CKR = 1
4708 12:44:05.408681 DQ_P2S_RATIO = 8
4709 12:44:05.411445 ===================================
4710 12:44:05.415157 CA_P2S_RATIO = 8
4711 12:44:05.418279 DQ_CA_OPEN = 0
4712 12:44:05.421702 DQ_SEMI_OPEN = 0
4713 12:44:05.421792 CA_SEMI_OPEN = 0
4714 12:44:05.425281 CA_FULL_RATE = 0
4715 12:44:05.428063 DQ_CKDIV4_EN = 1
4716 12:44:05.431348 CA_CKDIV4_EN = 1
4717 12:44:05.435230 CA_PREDIV_EN = 0
4718 12:44:05.438643 PH8_DLY = 0
4719 12:44:05.438725 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4720 12:44:05.441140 DQ_AAMCK_DIV = 4
4721 12:44:05.444386 CA_AAMCK_DIV = 4
4722 12:44:05.447682 CA_ADMCK_DIV = 4
4723 12:44:05.451232 DQ_TRACK_CA_EN = 0
4724 12:44:05.455220 CA_PICK = 933
4725 12:44:05.457631 CA_MCKIO = 933
4726 12:44:05.457713 MCKIO_SEMI = 0
4727 12:44:05.461423 PLL_FREQ = 3732
4728 12:44:05.464514 DQ_UI_PI_RATIO = 32
4729 12:44:05.468175 CA_UI_PI_RATIO = 0
4730 12:44:05.471229 ===================================
4731 12:44:05.474909 ===================================
4732 12:44:05.478125 memory_type:LPDDR4
4733 12:44:05.478206 GP_NUM : 10
4734 12:44:05.481112 SRAM_EN : 1
4735 12:44:05.481193 MD32_EN : 0
4736 12:44:05.484881 ===================================
4737 12:44:05.487583 [ANA_INIT] >>>>>>>>>>>>>>
4738 12:44:05.491172 <<<<<< [CONFIGURE PHASE]: ANA_TX
4739 12:44:05.494424 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4740 12:44:05.497869 ===================================
4741 12:44:05.500989 data_rate = 1866,PCW = 0X8f00
4742 12:44:05.504381 ===================================
4743 12:44:05.508326 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4744 12:44:05.514410 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4745 12:44:05.517501 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4746 12:44:05.523965 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4747 12:44:05.527859 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4748 12:44:05.530459 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4749 12:44:05.530541 [ANA_INIT] flow start
4750 12:44:05.533948 [ANA_INIT] PLL >>>>>>>>
4751 12:44:05.537256 [ANA_INIT] PLL <<<<<<<<
4752 12:44:05.537338 [ANA_INIT] MIDPI >>>>>>>>
4753 12:44:05.540748 [ANA_INIT] MIDPI <<<<<<<<
4754 12:44:05.543797 [ANA_INIT] DLL >>>>>>>>
4755 12:44:05.543878 [ANA_INIT] flow end
4756 12:44:05.551012 ============ LP4 DIFF to SE enter ============
4757 12:44:05.553666 ============ LP4 DIFF to SE exit ============
4758 12:44:05.557177 [ANA_INIT] <<<<<<<<<<<<<
4759 12:44:05.560737 [Flow] Enable top DCM control >>>>>
4760 12:44:05.563441 [Flow] Enable top DCM control <<<<<
4761 12:44:05.566819 Enable DLL master slave shuffle
4762 12:44:05.570199 ==============================================================
4763 12:44:05.573470 Gating Mode config
4764 12:44:05.577725 ==============================================================
4765 12:44:05.580553 Config description:
4766 12:44:05.590541 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4767 12:44:05.596844 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4768 12:44:05.599794 SELPH_MODE 0: By rank 1: By Phase
4769 12:44:05.606615 ==============================================================
4770 12:44:05.610570 GAT_TRACK_EN = 1
4771 12:44:05.614192 RX_GATING_MODE = 2
4772 12:44:05.617125 RX_GATING_TRACK_MODE = 2
4773 12:44:05.619761 SELPH_MODE = 1
4774 12:44:05.623242 PICG_EARLY_EN = 1
4775 12:44:05.626706 VALID_LAT_VALUE = 1
4776 12:44:05.629726 ==============================================================
4777 12:44:05.633818 Enter into Gating configuration >>>>
4778 12:44:05.636407 Exit from Gating configuration <<<<
4779 12:44:05.639459 Enter into DVFS_PRE_config >>>>>
4780 12:44:05.652587 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4781 12:44:05.652673 Exit from DVFS_PRE_config <<<<<
4782 12:44:05.656355 Enter into PICG configuration >>>>
4783 12:44:05.660166 Exit from PICG configuration <<<<
4784 12:44:05.662715 [RX_INPUT] configuration >>>>>
4785 12:44:05.666555 [RX_INPUT] configuration <<<<<
4786 12:44:05.672620 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4787 12:44:05.676085 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4788 12:44:05.683601 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4789 12:44:05.689728 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4790 12:44:05.696431 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4791 12:44:05.703471 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4792 12:44:05.706406 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4793 12:44:05.710013 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4794 12:44:05.712905 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4795 12:44:05.719792 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4796 12:44:05.722670 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4797 12:44:05.726244 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4798 12:44:05.729525 ===================================
4799 12:44:05.732476 LPDDR4 DRAM CONFIGURATION
4800 12:44:05.735480 ===================================
4801 12:44:05.738868 EX_ROW_EN[0] = 0x0
4802 12:44:05.738993 EX_ROW_EN[1] = 0x0
4803 12:44:05.742242 LP4Y_EN = 0x0
4804 12:44:05.742323 WORK_FSP = 0x0
4805 12:44:05.745899 WL = 0x3
4806 12:44:05.745982 RL = 0x3
4807 12:44:05.748783 BL = 0x2
4808 12:44:05.748866 RPST = 0x0
4809 12:44:05.751970 RD_PRE = 0x0
4810 12:44:05.752053 WR_PRE = 0x1
4811 12:44:05.755845 WR_PST = 0x0
4812 12:44:05.755945 DBI_WR = 0x0
4813 12:44:05.758676 DBI_RD = 0x0
4814 12:44:05.758759 OTF = 0x1
4815 12:44:05.762577 ===================================
4816 12:44:05.766235 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4817 12:44:05.772294 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4818 12:44:05.776114 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4819 12:44:05.778714 ===================================
4820 12:44:05.781973 LPDDR4 DRAM CONFIGURATION
4821 12:44:05.785205 ===================================
4822 12:44:05.785290 EX_ROW_EN[0] = 0x10
4823 12:44:05.788650 EX_ROW_EN[1] = 0x0
4824 12:44:05.792240 LP4Y_EN = 0x0
4825 12:44:05.792326 WORK_FSP = 0x0
4826 12:44:05.795712 WL = 0x3
4827 12:44:05.795794 RL = 0x3
4828 12:44:05.800191 BL = 0x2
4829 12:44:05.800284 RPST = 0x0
4830 12:44:05.801746 RD_PRE = 0x0
4831 12:44:05.801830 WR_PRE = 0x1
4832 12:44:05.805332 WR_PST = 0x0
4833 12:44:05.805415 DBI_WR = 0x0
4834 12:44:05.808927 DBI_RD = 0x0
4835 12:44:05.809041 OTF = 0x1
4836 12:44:05.811677 ===================================
4837 12:44:05.818422 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4838 12:44:05.823362 nWR fixed to 30
4839 12:44:05.827484 [ModeRegInit_LP4] CH0 RK0
4840 12:44:05.827566 [ModeRegInit_LP4] CH0 RK1
4841 12:44:05.829371 [ModeRegInit_LP4] CH1 RK0
4842 12:44:05.833177 [ModeRegInit_LP4] CH1 RK1
4843 12:44:05.833259 match AC timing 8
4844 12:44:05.839245 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4845 12:44:05.842308 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4846 12:44:05.845879 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4847 12:44:05.853074 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4848 12:44:05.855591 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4849 12:44:05.855674 ==
4850 12:44:05.858811 Dram Type= 6, Freq= 0, CH_0, rank 0
4851 12:44:05.862744 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4852 12:44:05.862828 ==
4853 12:44:05.869337 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4854 12:44:05.875354 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4855 12:44:05.878900 [CA 0] Center 38 (8~69) winsize 62
4856 12:44:05.882118 [CA 1] Center 38 (8~69) winsize 62
4857 12:44:05.885178 [CA 2] Center 36 (6~67) winsize 62
4858 12:44:05.888767 [CA 3] Center 35 (5~66) winsize 62
4859 12:44:05.892451 [CA 4] Center 34 (4~65) winsize 62
4860 12:44:05.895426 [CA 5] Center 34 (4~65) winsize 62
4861 12:44:05.895508
4862 12:44:05.898593 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4863 12:44:05.898676
4864 12:44:05.901926 [CATrainingPosCal] consider 1 rank data
4865 12:44:05.905650 u2DelayCellTimex100 = 270/100 ps
4866 12:44:05.909398 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4867 12:44:05.912889 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4868 12:44:05.916347 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4869 12:44:05.918861 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4870 12:44:05.925257 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4871 12:44:05.929078 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4872 12:44:05.929162
4873 12:44:05.932054 CA PerBit enable=1, Macro0, CA PI delay=34
4874 12:44:05.932137
4875 12:44:05.935147 [CBTSetCACLKResult] CA Dly = 34
4876 12:44:05.935230 CS Dly: 7 (0~38)
4877 12:44:05.935295 ==
4878 12:44:05.938177 Dram Type= 6, Freq= 0, CH_0, rank 1
4879 12:44:05.944895 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4880 12:44:05.944978 ==
4881 12:44:05.948236 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4882 12:44:05.954989 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4883 12:44:05.958563 [CA 0] Center 38 (8~69) winsize 62
4884 12:44:05.961574 [CA 1] Center 38 (8~69) winsize 62
4885 12:44:05.965011 [CA 2] Center 36 (5~67) winsize 63
4886 12:44:05.968520 [CA 3] Center 35 (5~66) winsize 62
4887 12:44:05.971527 [CA 4] Center 34 (4~65) winsize 62
4888 12:44:05.975186 [CA 5] Center 34 (4~65) winsize 62
4889 12:44:05.975268
4890 12:44:05.978142 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4891 12:44:05.978227
4892 12:44:05.982070 [CATrainingPosCal] consider 2 rank data
4893 12:44:05.985069 u2DelayCellTimex100 = 270/100 ps
4894 12:44:05.987762 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4895 12:44:05.991615 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4896 12:44:05.997793 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4897 12:44:06.001516 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4898 12:44:06.004641 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4899 12:44:06.008043 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4900 12:44:06.008125
4901 12:44:06.011583 CA PerBit enable=1, Macro0, CA PI delay=34
4902 12:44:06.011666
4903 12:44:06.014741 [CBTSetCACLKResult] CA Dly = 34
4904 12:44:06.014824 CS Dly: 7 (0~39)
4905 12:44:06.018122
4906 12:44:06.021114 ----->DramcWriteLeveling(PI) begin...
4907 12:44:06.021198 ==
4908 12:44:06.024404 Dram Type= 6, Freq= 0, CH_0, rank 0
4909 12:44:06.027511 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4910 12:44:06.027595 ==
4911 12:44:06.031287 Write leveling (Byte 0): 27 => 27
4912 12:44:06.034970 Write leveling (Byte 1): 26 => 26
4913 12:44:06.038093 DramcWriteLeveling(PI) end<-----
4914 12:44:06.038175
4915 12:44:06.038239 ==
4916 12:44:06.040875 Dram Type= 6, Freq= 0, CH_0, rank 0
4917 12:44:06.043851 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4918 12:44:06.043935 ==
4919 12:44:06.047641 [Gating] SW mode calibration
4920 12:44:06.054236 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4921 12:44:06.060477 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4922 12:44:06.064017 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4923 12:44:06.068161 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4924 12:44:06.073706 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4925 12:44:06.077723 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4926 12:44:06.080208 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4927 12:44:06.088082 0 10 20 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
4928 12:44:06.091047 0 10 24 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
4929 12:44:06.093487 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4930 12:44:06.100694 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4931 12:44:06.104121 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4932 12:44:06.106836 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4933 12:44:06.113250 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4934 12:44:06.116838 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4935 12:44:06.120700 0 11 20 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
4936 12:44:06.126832 0 11 24 | B1->B0 | 3939 4141 | 0 0 | (0 0) (1 1)
4937 12:44:06.130347 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4938 12:44:06.133139 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4939 12:44:06.139794 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4940 12:44:06.143209 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4941 12:44:06.146120 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4942 12:44:06.153410 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4943 12:44:06.156659 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4944 12:44:06.159714 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4945 12:44:06.166365 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4946 12:44:06.169778 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4947 12:44:06.172738 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4948 12:44:06.179701 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4949 12:44:06.183741 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4950 12:44:06.186536 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4951 12:44:06.192749 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4952 12:44:06.195869 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4953 12:44:06.199600 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4954 12:44:06.205492 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4955 12:44:06.209036 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4956 12:44:06.212552 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4957 12:44:06.219220 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4958 12:44:06.222258 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4959 12:44:06.225940 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4960 12:44:06.232076 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4961 12:44:06.232186 Total UI for P1: 0, mck2ui 16
4962 12:44:06.238847 best dqsien dly found for B0: ( 0, 14, 20)
4963 12:44:06.238935 Total UI for P1: 0, mck2ui 16
4964 12:44:06.242102 best dqsien dly found for B1: ( 0, 14, 22)
4965 12:44:06.249067 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
4966 12:44:06.252318 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
4967 12:44:06.252402
4968 12:44:06.256311 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
4969 12:44:06.258889 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
4970 12:44:06.261664 [Gating] SW calibration Done
4971 12:44:06.261735 ==
4972 12:44:06.265210 Dram Type= 6, Freq= 0, CH_0, rank 0
4973 12:44:06.268367 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4974 12:44:06.268461 ==
4975 12:44:06.271818 RX Vref Scan: 0
4976 12:44:06.271911
4977 12:44:06.271998 RX Vref 0 -> 0, step: 1
4978 12:44:06.272095
4979 12:44:06.275029 RX Delay -80 -> 252, step: 8
4980 12:44:06.278549 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4981 12:44:06.285658 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4982 12:44:06.288696 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
4983 12:44:06.291484 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4984 12:44:06.295530 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4985 12:44:06.299016 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
4986 12:44:06.301977 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
4987 12:44:06.308220 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
4988 12:44:06.311756 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
4989 12:44:06.314972 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
4990 12:44:06.317756 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
4991 12:44:06.322068 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
4992 12:44:06.327935 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
4993 12:44:06.331069 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
4994 12:44:06.334790 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
4995 12:44:06.338156 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
4996 12:44:06.338231 ==
4997 12:44:06.341576 Dram Type= 6, Freq= 0, CH_0, rank 0
4998 12:44:06.347967 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4999 12:44:06.348077 ==
5000 12:44:06.348168 DQS Delay:
5001 12:44:06.348257 DQS0 = 0, DQS1 = 0
5002 12:44:06.350954 DQM Delay:
5003 12:44:06.351027 DQM0 = 96, DQM1 = 84
5004 12:44:06.354326 DQ Delay:
5005 12:44:06.357749 DQ0 =91, DQ1 =95, DQ2 =95, DQ3 =91
5006 12:44:06.361167 DQ4 =99, DQ5 =91, DQ6 =103, DQ7 =103
5007 12:44:06.364664 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =79
5008 12:44:06.367719 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5009 12:44:06.367826
5010 12:44:06.367916
5011 12:44:06.368007 ==
5012 12:44:06.370605 Dram Type= 6, Freq= 0, CH_0, rank 0
5013 12:44:06.374297 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5014 12:44:06.374397 ==
5015 12:44:06.374497
5016 12:44:06.374585
5017 12:44:06.377743 TX Vref Scan disable
5018 12:44:06.377833 == TX Byte 0 ==
5019 12:44:06.384676 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5020 12:44:06.387319 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5021 12:44:06.387426 == TX Byte 1 ==
5022 12:44:06.394607 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5023 12:44:06.397507 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5024 12:44:06.397582 ==
5025 12:44:06.400449 Dram Type= 6, Freq= 0, CH_0, rank 0
5026 12:44:06.404176 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5027 12:44:06.404282 ==
5028 12:44:06.404372
5029 12:44:06.407632
5030 12:44:06.407738 TX Vref Scan disable
5031 12:44:06.410651 == TX Byte 0 ==
5032 12:44:06.414401 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5033 12:44:06.417203 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5034 12:44:06.420879 == TX Byte 1 ==
5035 12:44:06.424202 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5036 12:44:06.427371 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5037 12:44:06.430804
5038 12:44:06.430902 [DATLAT]
5039 12:44:06.430991 Freq=933, CH0 RK0
5040 12:44:06.431081
5041 12:44:06.434498 DATLAT Default: 0xd
5042 12:44:06.434570 0, 0xFFFF, sum = 0
5043 12:44:06.438171 1, 0xFFFF, sum = 0
5044 12:44:06.438283 2, 0xFFFF, sum = 0
5045 12:44:06.440414 3, 0xFFFF, sum = 0
5046 12:44:06.445301 4, 0xFFFF, sum = 0
5047 12:44:06.445385 5, 0xFFFF, sum = 0
5048 12:44:06.447747 6, 0xFFFF, sum = 0
5049 12:44:06.447851 7, 0xFFFF, sum = 0
5050 12:44:06.450571 8, 0xFFFF, sum = 0
5051 12:44:06.450673 9, 0xFFFF, sum = 0
5052 12:44:06.453634 10, 0x0, sum = 1
5053 12:44:06.453707 11, 0x0, sum = 2
5054 12:44:06.457266 12, 0x0, sum = 3
5055 12:44:06.457356 13, 0x0, sum = 4
5056 12:44:06.457420 best_step = 11
5057 12:44:06.457477
5058 12:44:06.460627 ==
5059 12:44:06.465202 Dram Type= 6, Freq= 0, CH_0, rank 0
5060 12:44:06.467263 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5061 12:44:06.467361 ==
5062 12:44:06.467460 RX Vref Scan: 1
5063 12:44:06.467548
5064 12:44:06.469839 RX Vref 0 -> 0, step: 1
5065 12:44:06.469942
5066 12:44:06.473117 RX Delay -69 -> 252, step: 4
5067 12:44:06.473204
5068 12:44:06.477698 Set Vref, RX VrefLevel [Byte0]: 46
5069 12:44:06.479982 [Byte1]: 50
5070 12:44:06.483418
5071 12:44:06.483519 Final RX Vref Byte 0 = 46 to rank0
5072 12:44:06.486506 Final RX Vref Byte 1 = 50 to rank0
5073 12:44:06.490280 Final RX Vref Byte 0 = 46 to rank1
5074 12:44:06.493399 Final RX Vref Byte 1 = 50 to rank1==
5075 12:44:06.497031 Dram Type= 6, Freq= 0, CH_0, rank 0
5076 12:44:06.502806 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5077 12:44:06.502908 ==
5078 12:44:06.503009 DQS Delay:
5079 12:44:06.506768 DQS0 = 0, DQS1 = 0
5080 12:44:06.506866 DQM Delay:
5081 12:44:06.506965 DQM0 = 97, DQM1 = 87
5082 12:44:06.509609 DQ Delay:
5083 12:44:06.512638 DQ0 =94, DQ1 =98, DQ2 =96, DQ3 =96
5084 12:44:06.516242 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =104
5085 12:44:06.519500 DQ8 =78, DQ9 =72, DQ10 =88, DQ11 =78
5086 12:44:06.522829 DQ12 =92, DQ13 =94, DQ14 =98, DQ15 =98
5087 12:44:06.522929
5088 12:44:06.523019
5089 12:44:06.529911 [DQSOSCAuto] RK0, (LSB)MR18= 0x2222, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5090 12:44:06.532514 CH0 RK0: MR19=505, MR18=2222
5091 12:44:06.539489 CH0_RK0: MR19=0x505, MR18=0x2222, DQSOSC=411, MR23=63, INC=64, DEC=42
5092 12:44:06.539591
5093 12:44:06.542429 ----->DramcWriteLeveling(PI) begin...
5094 12:44:06.542539 ==
5095 12:44:06.546203 Dram Type= 6, Freq= 0, CH_0, rank 1
5096 12:44:06.549803 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5097 12:44:06.549902 ==
5098 12:44:06.553276 Write leveling (Byte 0): 30 => 30
5099 12:44:06.556012 Write leveling (Byte 1): 29 => 29
5100 12:44:06.559359 DramcWriteLeveling(PI) end<-----
5101 12:44:06.559458
5102 12:44:06.559557 ==
5103 12:44:06.563095 Dram Type= 6, Freq= 0, CH_0, rank 1
5104 12:44:06.565977 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5105 12:44:06.566079 ==
5106 12:44:06.569531 [Gating] SW mode calibration
5107 12:44:06.575813 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5108 12:44:06.582497 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5109 12:44:06.586349 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 12:44:06.592049 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 12:44:06.595537 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 12:44:06.599031 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 12:44:06.605805 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 12:44:06.608665 0 10 20 | B1->B0 | 3131 2f2f | 0 1 | (0 0) (1 1)
5115 12:44:06.612012 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5116 12:44:06.619648 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 12:44:06.622182 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 12:44:06.625595 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 12:44:06.632564 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 12:44:06.635291 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 12:44:06.638729 0 11 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5122 12:44:06.645951 0 11 20 | B1->B0 | 2525 3737 | 0 0 | (0 0) (0 0)
5123 12:44:06.649091 0 11 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5124 12:44:06.651865 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 12:44:06.658351 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 12:44:06.661737 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 12:44:06.665505 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 12:44:06.672505 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 12:44:06.675094 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 12:44:06.678567 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5131 12:44:06.685056 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 12:44:06.688350 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 12:44:06.691630 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 12:44:06.698021 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 12:44:06.701687 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 12:44:06.704665 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 12:44:06.711482 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 12:44:06.715677 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 12:44:06.719056 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 12:44:06.724656 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 12:44:06.728524 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 12:44:06.730903 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 12:44:06.737915 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 12:44:06.741282 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 12:44:06.744676 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 12:44:06.750695 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 12:44:06.754281 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5148 12:44:06.758315 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 12:44:06.761215 Total UI for P1: 0, mck2ui 16
5150 12:44:06.764569 best dqsien dly found for B0: ( 0, 14, 24)
5151 12:44:06.767635 Total UI for P1: 0, mck2ui 16
5152 12:44:06.771097 best dqsien dly found for B1: ( 0, 14, 24)
5153 12:44:06.774087 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
5154 12:44:06.777292 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
5155 12:44:06.777369
5156 12:44:06.783803 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 24)
5157 12:44:06.787673 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 24)
5158 12:44:06.787778 [Gating] SW calibration Done
5159 12:44:06.791624 ==
5160 12:44:06.791731 Dram Type= 6, Freq= 0, CH_0, rank 1
5161 12:44:06.797775 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5162 12:44:06.797871 ==
5163 12:44:06.797970 RX Vref Scan: 0
5164 12:44:06.798057
5165 12:44:06.800550 RX Vref 0 -> 0, step: 1
5166 12:44:06.800650
5167 12:44:06.805029 RX Delay -80 -> 252, step: 8
5168 12:44:06.807787 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5169 12:44:06.810028 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5170 12:44:06.813647 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5171 12:44:06.820900 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5172 12:44:06.823762 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5173 12:44:06.827020 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5174 12:44:06.830632 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5175 12:44:06.833837 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5176 12:44:06.836627 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5177 12:44:06.843175 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5178 12:44:06.846741 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5179 12:44:06.850323 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5180 12:44:06.853209 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5181 12:44:06.856566 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5182 12:44:06.863551 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5183 12:44:06.866680 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5184 12:44:06.866761 ==
5185 12:44:06.870695 Dram Type= 6, Freq= 0, CH_0, rank 1
5186 12:44:06.873463 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5187 12:44:06.873545 ==
5188 12:44:06.873610 DQS Delay:
5189 12:44:06.876508 DQS0 = 0, DQS1 = 0
5190 12:44:06.876589 DQM Delay:
5191 12:44:06.879658 DQM0 = 98, DQM1 = 87
5192 12:44:06.879739 DQ Delay:
5193 12:44:06.883315 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5194 12:44:06.886686 DQ4 =103, DQ5 =91, DQ6 =103, DQ7 =107
5195 12:44:06.889380 DQ8 =83, DQ9 =71, DQ10 =87, DQ11 =83
5196 12:44:06.893205 DQ12 =91, DQ13 =95, DQ14 =91, DQ15 =95
5197 12:44:06.893286
5198 12:44:06.893351
5199 12:44:06.893410 ==
5200 12:44:06.896983 Dram Type= 6, Freq= 0, CH_0, rank 1
5201 12:44:06.903053 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5202 12:44:06.903135 ==
5203 12:44:06.903199
5204 12:44:06.903258
5205 12:44:06.903316 TX Vref Scan disable
5206 12:44:06.906553 == TX Byte 0 ==
5207 12:44:06.909360 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5208 12:44:06.916910 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5209 12:44:06.916994 == TX Byte 1 ==
5210 12:44:06.919607 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5211 12:44:06.926679 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5212 12:44:06.926762 ==
5213 12:44:06.930167 Dram Type= 6, Freq= 0, CH_0, rank 1
5214 12:44:06.932692 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5215 12:44:06.932816 ==
5216 12:44:06.932880
5217 12:44:06.932940
5218 12:44:06.936475 TX Vref Scan disable
5219 12:44:06.936585 == TX Byte 0 ==
5220 12:44:06.942694 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5221 12:44:06.945998 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5222 12:44:06.949487 == TX Byte 1 ==
5223 12:44:06.952667 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5224 12:44:06.955732 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5225 12:44:06.955813
5226 12:44:06.955878 [DATLAT]
5227 12:44:06.959437 Freq=933, CH0 RK1
5228 12:44:06.959519
5229 12:44:06.959583 DATLAT Default: 0xb
5230 12:44:06.962313 0, 0xFFFF, sum = 0
5231 12:44:06.962396 1, 0xFFFF, sum = 0
5232 12:44:06.965665 2, 0xFFFF, sum = 0
5233 12:44:06.970070 3, 0xFFFF, sum = 0
5234 12:44:06.970153 4, 0xFFFF, sum = 0
5235 12:44:06.972329 5, 0xFFFF, sum = 0
5236 12:44:06.972413 6, 0xFFFF, sum = 0
5237 12:44:06.975729 7, 0xFFFF, sum = 0
5238 12:44:06.975812 8, 0xFFFF, sum = 0
5239 12:44:06.979494 9, 0xFFFF, sum = 0
5240 12:44:06.979577 10, 0x0, sum = 1
5241 12:44:06.982205 11, 0x0, sum = 2
5242 12:44:06.982288 12, 0x0, sum = 3
5243 12:44:06.985739 13, 0x0, sum = 4
5244 12:44:06.985822 best_step = 11
5245 12:44:06.985887
5246 12:44:06.985946 ==
5247 12:44:06.988914 Dram Type= 6, Freq= 0, CH_0, rank 1
5248 12:44:06.992580 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5249 12:44:06.992662 ==
5250 12:44:06.995459 RX Vref Scan: 0
5251 12:44:06.995541
5252 12:44:06.998807 RX Vref 0 -> 0, step: 1
5253 12:44:06.998889
5254 12:44:06.998954 RX Delay -69 -> 252, step: 4
5255 12:44:07.007276 iDelay=199, Bit 0, Center 94 (3 ~ 186) 184
5256 12:44:07.010789 iDelay=199, Bit 1, Center 100 (7 ~ 194) 188
5257 12:44:07.013371 iDelay=199, Bit 2, Center 96 (7 ~ 186) 180
5258 12:44:07.018584 iDelay=199, Bit 3, Center 94 (7 ~ 182) 176
5259 12:44:07.019950 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5260 12:44:07.023224 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5261 12:44:07.029994 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5262 12:44:07.033149 iDelay=199, Bit 7, Center 108 (19 ~ 198) 180
5263 12:44:07.036898 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5264 12:44:07.039691 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5265 12:44:07.043282 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5266 12:44:07.049518 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5267 12:44:07.053276 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5268 12:44:07.056443 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5269 12:44:07.060358 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5270 12:44:07.063495 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5271 12:44:07.063577 ==
5272 12:44:07.066499 Dram Type= 6, Freq= 0, CH_0, rank 1
5273 12:44:07.072906 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5274 12:44:07.072989 ==
5275 12:44:07.073053 DQS Delay:
5276 12:44:07.076914 DQS0 = 0, DQS1 = 0
5277 12:44:07.076996 DQM Delay:
5278 12:44:07.077060 DQM0 = 98, DQM1 = 86
5279 12:44:07.080302 DQ Delay:
5280 12:44:07.083223 DQ0 =94, DQ1 =100, DQ2 =96, DQ3 =94
5281 12:44:07.086950 DQ4 =102, DQ5 =88, DQ6 =102, DQ7 =108
5282 12:44:07.089258 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5283 12:44:07.092759 DQ12 =92, DQ13 =90, DQ14 =98, DQ15 =96
5284 12:44:07.092841
5285 12:44:07.092906
5286 12:44:07.099455 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b2b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5287 12:44:07.102610 CH0 RK1: MR19=505, MR18=2B2B
5288 12:44:07.109729 CH0_RK1: MR19=0x505, MR18=0x2B2B, DQSOSC=408, MR23=63, INC=65, DEC=43
5289 12:44:07.113044 [RxdqsGatingPostProcess] freq 933
5290 12:44:07.119499 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5291 12:44:07.119583 Pre-setting of DQS Precalculation
5292 12:44:07.125777 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5293 12:44:07.125859 ==
5294 12:44:07.129829 Dram Type= 6, Freq= 0, CH_1, rank 0
5295 12:44:07.132612 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5296 12:44:07.132715 ==
5297 12:44:07.139490 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5298 12:44:07.145583 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5299 12:44:07.148993 [CA 0] Center 37 (7~68) winsize 62
5300 12:44:07.153287 [CA 1] Center 37 (6~68) winsize 63
5301 12:44:07.156271 [CA 2] Center 35 (5~65) winsize 61
5302 12:44:07.159193 [CA 3] Center 34 (4~64) winsize 61
5303 12:44:07.162058 [CA 4] Center 33 (3~63) winsize 61
5304 12:44:07.165411 [CA 5] Center 33 (3~63) winsize 61
5305 12:44:07.165492
5306 12:44:07.168869 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5307 12:44:07.168950
5308 12:44:07.172528 [CATrainingPosCal] consider 1 rank data
5309 12:44:07.175823 u2DelayCellTimex100 = 270/100 ps
5310 12:44:07.178590 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5311 12:44:07.181880 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5312 12:44:07.185558 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5313 12:44:07.188516 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5314 12:44:07.192293 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
5315 12:44:07.199304 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5316 12:44:07.199385
5317 12:44:07.201846 CA PerBit enable=1, Macro0, CA PI delay=33
5318 12:44:07.201927
5319 12:44:07.204885 [CBTSetCACLKResult] CA Dly = 33
5320 12:44:07.204994 CS Dly: 4 (0~35)
5321 12:44:07.205085 ==
5322 12:44:07.208722 Dram Type= 6, Freq= 0, CH_1, rank 1
5323 12:44:07.211810 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5324 12:44:07.215952 ==
5325 12:44:07.218828 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5326 12:44:07.225482 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5327 12:44:07.228312 [CA 0] Center 37 (6~68) winsize 63
5328 12:44:07.231675 [CA 1] Center 37 (6~68) winsize 63
5329 12:44:07.234966 [CA 2] Center 34 (4~65) winsize 62
5330 12:44:07.238217 [CA 3] Center 34 (4~65) winsize 62
5331 12:44:07.241696 [CA 4] Center 33 (3~63) winsize 61
5332 12:44:07.244743 [CA 5] Center 33 (3~63) winsize 61
5333 12:44:07.244824
5334 12:44:07.249120 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5335 12:44:07.249201
5336 12:44:07.251807 [CATrainingPosCal] consider 2 rank data
5337 12:44:07.255381 u2DelayCellTimex100 = 270/100 ps
5338 12:44:07.258470 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5339 12:44:07.261569 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5340 12:44:07.264731 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5341 12:44:07.271490 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5342 12:44:07.274741 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
5343 12:44:07.278528 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5344 12:44:07.278609
5345 12:44:07.281915 CA PerBit enable=1, Macro0, CA PI delay=33
5346 12:44:07.281996
5347 12:44:07.284955 [CBTSetCACLKResult] CA Dly = 33
5348 12:44:07.285036 CS Dly: 5 (0~37)
5349 12:44:07.285101
5350 12:44:07.287982 ----->DramcWriteLeveling(PI) begin...
5351 12:44:07.288065 ==
5352 12:44:07.291303 Dram Type= 6, Freq= 0, CH_1, rank 0
5353 12:44:07.297606 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5354 12:44:07.297689 ==
5355 12:44:07.300977 Write leveling (Byte 0): 27 => 27
5356 12:44:07.304438 Write leveling (Byte 1): 25 => 25
5357 12:44:07.307829 DramcWriteLeveling(PI) end<-----
5358 12:44:07.307911
5359 12:44:07.307975 ==
5360 12:44:07.311357 Dram Type= 6, Freq= 0, CH_1, rank 0
5361 12:44:07.314288 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5362 12:44:07.314370 ==
5363 12:44:07.317631 [Gating] SW mode calibration
5364 12:44:07.324420 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5365 12:44:07.331389 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5366 12:44:07.334078 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5367 12:44:07.337966 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5368 12:44:07.341363 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5369 12:44:07.347608 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 12:44:07.351064 0 10 16 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
5371 12:44:07.354319 0 10 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
5372 12:44:07.360499 0 10 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5373 12:44:07.363681 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5374 12:44:07.367418 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5375 12:44:07.374031 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5376 12:44:07.377220 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5377 12:44:07.380668 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 12:44:07.387493 0 11 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5379 12:44:07.390735 0 11 20 | B1->B0 | 2d2d 4343 | 0 0 | (1 1) (0 0)
5380 12:44:07.393579 0 11 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5381 12:44:07.400593 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 12:44:07.404122 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 12:44:07.407150 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 12:44:07.413575 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 12:44:07.417362 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5386 12:44:07.420193 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5387 12:44:07.427035 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5388 12:44:07.430306 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 12:44:07.433562 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 12:44:07.439990 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 12:44:07.443587 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 12:44:07.446795 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 12:44:07.453144 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 12:44:07.456442 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 12:44:07.460153 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 12:44:07.467178 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 12:44:07.470029 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 12:44:07.473683 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 12:44:07.479832 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 12:44:07.483703 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 12:44:07.486103 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 12:44:07.493357 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5403 12:44:07.496113 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5404 12:44:07.499447 Total UI for P1: 0, mck2ui 16
5405 12:44:07.503751 best dqsien dly found for B0: ( 0, 14, 16)
5406 12:44:07.506905 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5407 12:44:07.509467 Total UI for P1: 0, mck2ui 16
5408 12:44:07.512626 best dqsien dly found for B1: ( 0, 14, 20)
5409 12:44:07.517369 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5410 12:44:07.520187 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5411 12:44:07.520270
5412 12:44:07.525785 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5413 12:44:07.530558 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5414 12:44:07.532511 [Gating] SW calibration Done
5415 12:44:07.532621 ==
5416 12:44:07.535826 Dram Type= 6, Freq= 0, CH_1, rank 0
5417 12:44:07.540233 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5418 12:44:07.540316 ==
5419 12:44:07.540380 RX Vref Scan: 0
5420 12:44:07.540441
5421 12:44:07.542850 RX Vref 0 -> 0, step: 1
5422 12:44:07.542932
5423 12:44:07.546276 RX Delay -80 -> 252, step: 8
5424 12:44:07.548660 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5425 12:44:07.552358 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5426 12:44:07.559402 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5427 12:44:07.562209 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5428 12:44:07.566035 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5429 12:44:07.569298 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5430 12:44:07.572660 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5431 12:44:07.575622 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5432 12:44:07.582394 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5433 12:44:07.586873 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5434 12:44:07.589144 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5435 12:44:07.592716 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5436 12:44:07.595399 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5437 12:44:07.602208 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5438 12:44:07.605078 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5439 12:44:07.608932 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5440 12:44:07.609014 ==
5441 12:44:07.611748 Dram Type= 6, Freq= 0, CH_1, rank 0
5442 12:44:07.615677 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5443 12:44:07.615832 ==
5444 12:44:07.618327 DQS Delay:
5445 12:44:07.618411 DQS0 = 0, DQS1 = 0
5446 12:44:07.621869 DQM Delay:
5447 12:44:07.621951 DQM0 = 94, DQM1 = 87
5448 12:44:07.622017 DQ Delay:
5449 12:44:07.625224 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5450 12:44:07.628430 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5451 12:44:07.631390 DQ8 =71, DQ9 =75, DQ10 =87, DQ11 =79
5452 12:44:07.634857 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =99
5453 12:44:07.634940
5454 12:44:07.635004
5455 12:44:07.639095 ==
5456 12:44:07.641635 Dram Type= 6, Freq= 0, CH_1, rank 0
5457 12:44:07.644679 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5458 12:44:07.644804 ==
5459 12:44:07.644869
5460 12:44:07.644930
5461 12:44:07.648640 TX Vref Scan disable
5462 12:44:07.648730 == TX Byte 0 ==
5463 12:44:07.655001 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5464 12:44:07.658529 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5465 12:44:07.658612 == TX Byte 1 ==
5466 12:44:07.664389 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5467 12:44:07.667923 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5468 12:44:07.668005 ==
5469 12:44:07.671628 Dram Type= 6, Freq= 0, CH_1, rank 0
5470 12:44:07.674719 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5471 12:44:07.674801 ==
5472 12:44:07.674866
5473 12:44:07.674926
5474 12:44:07.678546 TX Vref Scan disable
5475 12:44:07.681439 == TX Byte 0 ==
5476 12:44:07.684904 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5477 12:44:07.687759 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5478 12:44:07.691068 == TX Byte 1 ==
5479 12:44:07.695058 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5480 12:44:07.698365 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5481 12:44:07.698447
5482 12:44:07.701429 [DATLAT]
5483 12:44:07.701510 Freq=933, CH1 RK0
5484 12:44:07.701577
5485 12:44:07.704245 DATLAT Default: 0xd
5486 12:44:07.704327 0, 0xFFFF, sum = 0
5487 12:44:07.707632 1, 0xFFFF, sum = 0
5488 12:44:07.707715 2, 0xFFFF, sum = 0
5489 12:44:07.710720 3, 0xFFFF, sum = 0
5490 12:44:07.710803 4, 0xFFFF, sum = 0
5491 12:44:07.714427 5, 0xFFFF, sum = 0
5492 12:44:07.714510 6, 0xFFFF, sum = 0
5493 12:44:07.717638 7, 0xFFFF, sum = 0
5494 12:44:07.717722 8, 0xFFFF, sum = 0
5495 12:44:07.720545 9, 0xFFFF, sum = 0
5496 12:44:07.720655 10, 0x0, sum = 1
5497 12:44:07.724302 11, 0x0, sum = 2
5498 12:44:07.724386 12, 0x0, sum = 3
5499 12:44:07.727708 13, 0x0, sum = 4
5500 12:44:07.727791 best_step = 11
5501 12:44:07.727856
5502 12:44:07.727917 ==
5503 12:44:07.731284 Dram Type= 6, Freq= 0, CH_1, rank 0
5504 12:44:07.737588 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5505 12:44:07.737670 ==
5506 12:44:07.737736 RX Vref Scan: 1
5507 12:44:07.737797
5508 12:44:07.740637 RX Vref 0 -> 0, step: 1
5509 12:44:07.740781
5510 12:44:07.744138 RX Delay -69 -> 252, step: 4
5511 12:44:07.744257
5512 12:44:07.747673 Set Vref, RX VrefLevel [Byte0]: 54
5513 12:44:07.750956 [Byte1]: 50
5514 12:44:07.751042
5515 12:44:07.754040 Final RX Vref Byte 0 = 54 to rank0
5516 12:44:07.757702 Final RX Vref Byte 1 = 50 to rank0
5517 12:44:07.760673 Final RX Vref Byte 0 = 54 to rank1
5518 12:44:07.764119 Final RX Vref Byte 1 = 50 to rank1==
5519 12:44:07.767840 Dram Type= 6, Freq= 0, CH_1, rank 0
5520 12:44:07.771050 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5521 12:44:07.771133 ==
5522 12:44:07.773949 DQS Delay:
5523 12:44:07.774030 DQS0 = 0, DQS1 = 0
5524 12:44:07.777096 DQM Delay:
5525 12:44:07.777178 DQM0 = 94, DQM1 = 88
5526 12:44:07.777244 DQ Delay:
5527 12:44:07.781341 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =92
5528 12:44:07.783696 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =92
5529 12:44:07.787449 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =80
5530 12:44:07.790041 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =98
5531 12:44:07.790123
5532 12:44:07.790187
5533 12:44:07.800108 [DQSOSCAuto] RK0, (LSB)MR18= 0x3a3a, (MSB)MR19= 0x505, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps
5534 12:44:07.803715 CH1 RK0: MR19=505, MR18=3A3A
5535 12:44:07.810090 CH1_RK0: MR19=0x505, MR18=0x3A3A, DQSOSC=403, MR23=63, INC=66, DEC=44
5536 12:44:07.810196
5537 12:44:07.813216 ----->DramcWriteLeveling(PI) begin...
5538 12:44:07.813299 ==
5539 12:44:07.816862 Dram Type= 6, Freq= 0, CH_1, rank 1
5540 12:44:07.820400 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5541 12:44:07.820488 ==
5542 12:44:07.823254 Write leveling (Byte 0): 23 => 23
5543 12:44:07.826554 Write leveling (Byte 1): 23 => 23
5544 12:44:07.829681 DramcWriteLeveling(PI) end<-----
5545 12:44:07.829763
5546 12:44:07.829827 ==
5547 12:44:07.832993 Dram Type= 6, Freq= 0, CH_1, rank 1
5548 12:44:07.836501 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5549 12:44:07.836583 ==
5550 12:44:07.839624 [Gating] SW mode calibration
5551 12:44:07.846370 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5552 12:44:07.852669 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5553 12:44:07.856540 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5554 12:44:07.859749 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5555 12:44:07.866205 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5556 12:44:07.869130 0 10 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5557 12:44:07.872728 0 10 16 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 1)
5558 12:44:07.879213 0 10 20 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
5559 12:44:07.882700 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 12:44:07.886547 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5561 12:44:07.893113 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5562 12:44:07.896285 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5563 12:44:07.899090 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5564 12:44:07.905667 0 11 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
5565 12:44:07.909717 0 11 16 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (1 1)
5566 12:44:07.912902 0 11 20 | B1->B0 | 2e2e 4646 | 0 0 | (1 1) (0 0)
5567 12:44:07.919178 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 12:44:07.922938 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 12:44:07.925577 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 12:44:07.932374 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5571 12:44:07.935162 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5572 12:44:07.938843 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5573 12:44:07.945254 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5574 12:44:07.948850 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 12:44:07.951599 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 12:44:07.958591 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 12:44:07.962683 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 12:44:07.965748 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 12:44:07.971922 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 12:44:07.975040 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 12:44:07.978927 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 12:44:07.985167 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 12:44:07.987956 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 12:44:07.992064 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 12:44:07.998086 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 12:44:08.001362 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 12:44:08.005085 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 12:44:08.011200 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5589 12:44:08.014243 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5590 12:44:08.017671 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 12:44:08.021064 Total UI for P1: 0, mck2ui 16
5592 12:44:08.024449 best dqsien dly found for B0: ( 0, 14, 14)
5593 12:44:08.027654 Total UI for P1: 0, mck2ui 16
5594 12:44:08.030904 best dqsien dly found for B1: ( 0, 14, 18)
5595 12:44:08.034217 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5596 12:44:08.038625 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5597 12:44:08.040952
5598 12:44:08.044472 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5599 12:44:08.047866 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5600 12:44:08.051262 [Gating] SW calibration Done
5601 12:44:08.051343 ==
5602 12:44:08.054561 Dram Type= 6, Freq= 0, CH_1, rank 1
5603 12:44:08.057963 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5604 12:44:08.058046 ==
5605 12:44:08.058111 RX Vref Scan: 0
5606 12:44:08.058171
5607 12:44:08.061798 RX Vref 0 -> 0, step: 1
5608 12:44:08.061879
5609 12:44:08.064584 RX Delay -80 -> 252, step: 8
5610 12:44:08.067424 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5611 12:44:08.070884 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5612 12:44:08.077696 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5613 12:44:08.081156 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5614 12:44:08.084035 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5615 12:44:08.087674 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5616 12:44:08.091177 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5617 12:44:08.097716 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5618 12:44:08.100916 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5619 12:44:08.103680 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5620 12:44:08.107072 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5621 12:44:08.110629 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5622 12:44:08.116785 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5623 12:44:08.120286 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5624 12:44:08.124034 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5625 12:44:08.127778 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5626 12:44:08.127860 ==
5627 12:44:08.130172 Dram Type= 6, Freq= 0, CH_1, rank 1
5628 12:44:08.133753 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5629 12:44:08.136802 ==
5630 12:44:08.136890 DQS Delay:
5631 12:44:08.136956 DQS0 = 0, DQS1 = 0
5632 12:44:08.139911 DQM Delay:
5633 12:44:08.139992 DQM0 = 95, DQM1 = 86
5634 12:44:08.143571 DQ Delay:
5635 12:44:08.143653 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =91
5636 12:44:08.147408 DQ4 =91, DQ5 =111, DQ6 =111, DQ7 =91
5637 12:44:08.150068 DQ8 =75, DQ9 =75, DQ10 =83, DQ11 =79
5638 12:44:08.157027 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =95
5639 12:44:08.157108
5640 12:44:08.157173
5641 12:44:08.157233 ==
5642 12:44:08.159958 Dram Type= 6, Freq= 0, CH_1, rank 1
5643 12:44:08.163852 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5644 12:44:08.163934 ==
5645 12:44:08.163999
5646 12:44:08.164059
5647 12:44:08.167038 TX Vref Scan disable
5648 12:44:08.167119 == TX Byte 0 ==
5649 12:44:08.173394 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5650 12:44:08.176365 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5651 12:44:08.176446 == TX Byte 1 ==
5652 12:44:08.183007 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5653 12:44:08.186126 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5654 12:44:08.186208 ==
5655 12:44:08.190071 Dram Type= 6, Freq= 0, CH_1, rank 1
5656 12:44:08.193096 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5657 12:44:08.193179 ==
5658 12:44:08.193243
5659 12:44:08.193303
5660 12:44:08.196140 TX Vref Scan disable
5661 12:44:08.199469 == TX Byte 0 ==
5662 12:44:08.203013 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5663 12:44:08.206112 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5664 12:44:08.209496 == TX Byte 1 ==
5665 12:44:08.213317 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5666 12:44:08.216089 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5667 12:44:08.219631
5668 12:44:08.219712 [DATLAT]
5669 12:44:08.219776 Freq=933, CH1 RK1
5670 12:44:08.219838
5671 12:44:08.222586 DATLAT Default: 0xb
5672 12:44:08.222682 0, 0xFFFF, sum = 0
5673 12:44:08.226163 1, 0xFFFF, sum = 0
5674 12:44:08.226247 2, 0xFFFF, sum = 0
5675 12:44:08.229245 3, 0xFFFF, sum = 0
5676 12:44:08.229328 4, 0xFFFF, sum = 0
5677 12:44:08.232843 5, 0xFFFF, sum = 0
5678 12:44:08.235801 6, 0xFFFF, sum = 0
5679 12:44:08.235884 7, 0xFFFF, sum = 0
5680 12:44:08.239171 8, 0xFFFF, sum = 0
5681 12:44:08.239255 9, 0xFFFF, sum = 0
5682 12:44:08.243494 10, 0x0, sum = 1
5683 12:44:08.243577 11, 0x0, sum = 2
5684 12:44:08.243643 12, 0x0, sum = 3
5685 12:44:08.246257 13, 0x0, sum = 4
5686 12:44:08.246340 best_step = 11
5687 12:44:08.246404
5688 12:44:08.249082 ==
5689 12:44:08.252876 Dram Type= 6, Freq= 0, CH_1, rank 1
5690 12:44:08.256109 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5691 12:44:08.256217 ==
5692 12:44:08.256310 RX Vref Scan: 0
5693 12:44:08.256398
5694 12:44:08.259262 RX Vref 0 -> 0, step: 1
5695 12:44:08.259356
5696 12:44:08.262806 RX Delay -69 -> 252, step: 4
5697 12:44:08.265669 iDelay=203, Bit 0, Center 96 (3 ~ 190) 188
5698 12:44:08.272342 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5699 12:44:08.276008 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5700 12:44:08.279160 iDelay=203, Bit 3, Center 94 (3 ~ 186) 184
5701 12:44:08.281868 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5702 12:44:08.285521 iDelay=203, Bit 5, Center 108 (15 ~ 202) 188
5703 12:44:08.292320 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5704 12:44:08.295966 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5705 12:44:08.299087 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5706 12:44:08.302212 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5707 12:44:08.305373 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5708 12:44:08.309303 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5709 12:44:08.315131 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5710 12:44:08.318494 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5711 12:44:08.322637 iDelay=203, Bit 14, Center 98 (3 ~ 194) 192
5712 12:44:08.324971 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5713 12:44:08.325053 ==
5714 12:44:08.328898 Dram Type= 6, Freq= 0, CH_1, rank 1
5715 12:44:08.334818 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5716 12:44:08.334899 ==
5717 12:44:08.334964 DQS Delay:
5718 12:44:08.335024 DQS0 = 0, DQS1 = 0
5719 12:44:08.338127 DQM Delay:
5720 12:44:08.338209 DQM0 = 96, DQM1 = 88
5721 12:44:08.342628 DQ Delay:
5722 12:44:08.344962 DQ0 =96, DQ1 =90, DQ2 =88, DQ3 =94
5723 12:44:08.348056 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =94
5724 12:44:08.351867 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5725 12:44:08.355822 DQ12 =96, DQ13 =96, DQ14 =98, DQ15 =96
5726 12:44:08.355903
5727 12:44:08.355968
5728 12:44:08.361383 [DQSOSCAuto] RK1, (LSB)MR18= 0x2626, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5729 12:44:08.364461 CH1 RK1: MR19=505, MR18=2626
5730 12:44:08.371817 CH1_RK1: MR19=0x505, MR18=0x2626, DQSOSC=409, MR23=63, INC=64, DEC=43
5731 12:44:08.374658 [RxdqsGatingPostProcess] freq 933
5732 12:44:08.377688 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5733 12:44:08.381336 Pre-setting of DQS Precalculation
5734 12:44:08.387723 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5735 12:44:08.394291 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5736 12:44:08.401294 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5737 12:44:08.401376
5738 12:44:08.401440
5739 12:44:08.404976 [Calibration Summary] 1866 Mbps
5740 12:44:08.408062 CH 0, Rank 0
5741 12:44:08.408143 SW Impedance : PASS
5742 12:44:08.410993 DUTY Scan : NO K
5743 12:44:08.411075 ZQ Calibration : PASS
5744 12:44:08.413859 Jitter Meter : NO K
5745 12:44:08.417349 CBT Training : PASS
5746 12:44:08.417439 Write leveling : PASS
5747 12:44:08.421196 RX DQS gating : PASS
5748 12:44:08.424193 RX DQ/DQS(RDDQC) : PASS
5749 12:44:08.424274 TX DQ/DQS : PASS
5750 12:44:08.427636 RX DATLAT : PASS
5751 12:44:08.431544 RX DQ/DQS(Engine): PASS
5752 12:44:08.431626 TX OE : NO K
5753 12:44:08.433998 All Pass.
5754 12:44:08.434079
5755 12:44:08.434143 CH 0, Rank 1
5756 12:44:08.438059 SW Impedance : PASS
5757 12:44:08.438141 DUTY Scan : NO K
5758 12:44:08.440858 ZQ Calibration : PASS
5759 12:44:08.444164 Jitter Meter : NO K
5760 12:44:08.444244 CBT Training : PASS
5761 12:44:08.447025 Write leveling : PASS
5762 12:44:08.450488 RX DQS gating : PASS
5763 12:44:08.450567 RX DQ/DQS(RDDQC) : PASS
5764 12:44:08.454676 TX DQ/DQS : PASS
5765 12:44:08.456682 RX DATLAT : PASS
5766 12:44:08.456803 RX DQ/DQS(Engine): PASS
5767 12:44:08.460956 TX OE : NO K
5768 12:44:08.461037 All Pass.
5769 12:44:08.461100
5770 12:44:08.464013 CH 1, Rank 0
5771 12:44:08.464093 SW Impedance : PASS
5772 12:44:08.467100 DUTY Scan : NO K
5773 12:44:08.467180 ZQ Calibration : PASS
5774 12:44:08.470905 Jitter Meter : NO K
5775 12:44:08.473910 CBT Training : PASS
5776 12:44:08.473990 Write leveling : PASS
5777 12:44:08.477233 RX DQS gating : PASS
5778 12:44:08.480174 RX DQ/DQS(RDDQC) : PASS
5779 12:44:08.480253 TX DQ/DQS : PASS
5780 12:44:08.483577 RX DATLAT : PASS
5781 12:44:08.486701 RX DQ/DQS(Engine): PASS
5782 12:44:08.486781 TX OE : NO K
5783 12:44:08.490306 All Pass.
5784 12:44:08.490386
5785 12:44:08.490450 CH 1, Rank 1
5786 12:44:08.493344 SW Impedance : PASS
5787 12:44:08.493427 DUTY Scan : NO K
5788 12:44:08.496651 ZQ Calibration : PASS
5789 12:44:08.500681 Jitter Meter : NO K
5790 12:44:08.500799 CBT Training : PASS
5791 12:44:08.503598 Write leveling : PASS
5792 12:44:08.507061 RX DQS gating : PASS
5793 12:44:08.507140 RX DQ/DQS(RDDQC) : PASS
5794 12:44:08.510412 TX DQ/DQS : PASS
5795 12:44:08.513470 RX DATLAT : PASS
5796 12:44:08.513550 RX DQ/DQS(Engine): PASS
5797 12:44:08.516436 TX OE : NO K
5798 12:44:08.516516 All Pass.
5799 12:44:08.516579
5800 12:44:08.519880 DramC Write-DBI off
5801 12:44:08.523495 PER_BANK_REFRESH: Hybrid Mode
5802 12:44:08.523576 TX_TRACKING: ON
5803 12:44:08.533305 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5804 12:44:08.536237 [FAST_K] Save calibration result to emmc
5805 12:44:08.540126 dramc_set_vcore_voltage set vcore to 650000
5806 12:44:08.543471 Read voltage for 400, 6
5807 12:44:08.543551 Vio18 = 0
5808 12:44:08.543616 Vcore = 650000
5809 12:44:08.546611 Vdram = 0
5810 12:44:08.546690 Vddq = 0
5811 12:44:08.546754 Vmddr = 0
5812 12:44:08.553050 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5813 12:44:08.556734 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5814 12:44:08.560587 MEM_TYPE=3, freq_sel=20
5815 12:44:08.562897 sv_algorithm_assistance_LP4_800
5816 12:44:08.566426 ============ PULL DRAM RESETB DOWN ============
5817 12:44:08.570332 ========== PULL DRAM RESETB DOWN end =========
5818 12:44:08.576501 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5819 12:44:08.579791 ===================================
5820 12:44:08.582692 LPDDR4 DRAM CONFIGURATION
5821 12:44:08.586055 ===================================
5822 12:44:08.586135 EX_ROW_EN[0] = 0x0
5823 12:44:08.589515 EX_ROW_EN[1] = 0x0
5824 12:44:08.589597 LP4Y_EN = 0x0
5825 12:44:08.593202 WORK_FSP = 0x0
5826 12:44:08.593283 WL = 0x2
5827 12:44:08.597017 RL = 0x2
5828 12:44:08.597098 BL = 0x2
5829 12:44:08.599281 RPST = 0x0
5830 12:44:08.599395 RD_PRE = 0x0
5831 12:44:08.602983 WR_PRE = 0x1
5832 12:44:08.603064 WR_PST = 0x0
5833 12:44:08.606173 DBI_WR = 0x0
5834 12:44:08.606254 DBI_RD = 0x0
5835 12:44:08.609155 OTF = 0x1
5836 12:44:08.613262 ===================================
5837 12:44:08.615856 ===================================
5838 12:44:08.615938 ANA top config
5839 12:44:08.619557 ===================================
5840 12:44:08.622477 DLL_ASYNC_EN = 0
5841 12:44:08.625707 ALL_SLAVE_EN = 1
5842 12:44:08.628603 NEW_RANK_MODE = 1
5843 12:44:08.632959 DLL_IDLE_MODE = 1
5844 12:44:08.633041 LP45_APHY_COMB_EN = 1
5845 12:44:08.635186 TX_ODT_DIS = 1
5846 12:44:08.638355 NEW_8X_MODE = 1
5847 12:44:08.642865 ===================================
5848 12:44:08.645362 ===================================
5849 12:44:08.648446 data_rate = 800
5850 12:44:08.651706 CKR = 1
5851 12:44:08.651788 DQ_P2S_RATIO = 4
5852 12:44:08.655088 ===================================
5853 12:44:08.658294 CA_P2S_RATIO = 4
5854 12:44:08.662553 DQ_CA_OPEN = 0
5855 12:44:08.665637 DQ_SEMI_OPEN = 1
5856 12:44:08.668279 CA_SEMI_OPEN = 1
5857 12:44:08.672240 CA_FULL_RATE = 0
5858 12:44:08.672321 DQ_CKDIV4_EN = 0
5859 12:44:08.675128 CA_CKDIV4_EN = 1
5860 12:44:08.678960 CA_PREDIV_EN = 0
5861 12:44:08.681777 PH8_DLY = 0
5862 12:44:08.685043 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5863 12:44:08.688354 DQ_AAMCK_DIV = 0
5864 12:44:08.688436 CA_AAMCK_DIV = 0
5865 12:44:08.691765 CA_ADMCK_DIV = 4
5866 12:44:08.694925 DQ_TRACK_CA_EN = 0
5867 12:44:08.698207 CA_PICK = 800
5868 12:44:08.701354 CA_MCKIO = 400
5869 12:44:08.705458 MCKIO_SEMI = 400
5870 12:44:08.707838 PLL_FREQ = 3016
5871 12:44:08.711436 DQ_UI_PI_RATIO = 32
5872 12:44:08.711518 CA_UI_PI_RATIO = 32
5873 12:44:08.715424 ===================================
5874 12:44:08.718445 ===================================
5875 12:44:08.721604 memory_type:LPDDR4
5876 12:44:08.724357 GP_NUM : 10
5877 12:44:08.724439 SRAM_EN : 1
5878 12:44:08.727638 MD32_EN : 0
5879 12:44:08.731372 ===================================
5880 12:44:08.734146 [ANA_INIT] >>>>>>>>>>>>>>
5881 12:44:08.737467 <<<<<< [CONFIGURE PHASE]: ANA_TX
5882 12:44:08.740880 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5883 12:44:08.744358 ===================================
5884 12:44:08.744440 data_rate = 800,PCW = 0X7400
5885 12:44:08.747857 ===================================
5886 12:44:08.751082 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5887 12:44:08.757447 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5888 12:44:08.770891 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5889 12:44:08.774100 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5890 12:44:08.777767 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5891 12:44:08.780966 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5892 12:44:08.784499 [ANA_INIT] flow start
5893 12:44:08.784579 [ANA_INIT] PLL >>>>>>>>
5894 12:44:08.787180 [ANA_INIT] PLL <<<<<<<<
5895 12:44:08.790608 [ANA_INIT] MIDPI >>>>>>>>
5896 12:44:08.794392 [ANA_INIT] MIDPI <<<<<<<<
5897 12:44:08.794473 [ANA_INIT] DLL >>>>>>>>
5898 12:44:08.797137 [ANA_INIT] flow end
5899 12:44:08.801003 ============ LP4 DIFF to SE enter ============
5900 12:44:08.804420 ============ LP4 DIFF to SE exit ============
5901 12:44:08.807625 [ANA_INIT] <<<<<<<<<<<<<
5902 12:44:08.810434 [Flow] Enable top DCM control >>>>>
5903 12:44:08.813959 [Flow] Enable top DCM control <<<<<
5904 12:44:08.817137 Enable DLL master slave shuffle
5905 12:44:08.823358 ==============================================================
5906 12:44:08.823461 Gating Mode config
5907 12:44:08.831199 ==============================================================
5908 12:44:08.831281 Config description:
5909 12:44:08.840919 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5910 12:44:08.846818 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5911 12:44:08.853486 SELPH_MODE 0: By rank 1: By Phase
5912 12:44:08.856701 ==============================================================
5913 12:44:08.860015 GAT_TRACK_EN = 0
5914 12:44:08.863522 RX_GATING_MODE = 2
5915 12:44:08.866959 RX_GATING_TRACK_MODE = 2
5916 12:44:08.870018 SELPH_MODE = 1
5917 12:44:08.874162 PICG_EARLY_EN = 1
5918 12:44:08.876505 VALID_LAT_VALUE = 1
5919 12:44:08.883050 ==============================================================
5920 12:44:08.886799 Enter into Gating configuration >>>>
5921 12:44:08.889533 Exit from Gating configuration <<<<
5922 12:44:08.889615 Enter into DVFS_PRE_config >>>>>
5923 12:44:08.902951 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5924 12:44:08.906089 Exit from DVFS_PRE_config <<<<<
5925 12:44:08.909407 Enter into PICG configuration >>>>
5926 12:44:08.912619 Exit from PICG configuration <<<<
5927 12:44:08.912747 [RX_INPUT] configuration >>>>>
5928 12:44:08.916292 [RX_INPUT] configuration <<<<<
5929 12:44:08.922963 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5930 12:44:08.929233 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5931 12:44:08.932477 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5932 12:44:08.939433 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5933 12:44:08.946267 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5934 12:44:08.952653 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5935 12:44:08.955643 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5936 12:44:08.958983 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5937 12:44:08.965592 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5938 12:44:08.969835 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5939 12:44:08.972147 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5940 12:44:08.979188 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5941 12:44:08.981892 ===================================
5942 12:44:08.982000 LPDDR4 DRAM CONFIGURATION
5943 12:44:08.985247 ===================================
5944 12:44:08.988505 EX_ROW_EN[0] = 0x0
5945 12:44:08.988586 EX_ROW_EN[1] = 0x0
5946 12:44:08.992235 LP4Y_EN = 0x0
5947 12:44:08.995060 WORK_FSP = 0x0
5948 12:44:08.995141 WL = 0x2
5949 12:44:08.998437 RL = 0x2
5950 12:44:08.998518 BL = 0x2
5951 12:44:09.002708 RPST = 0x0
5952 12:44:09.002789 RD_PRE = 0x0
5953 12:44:09.005044 WR_PRE = 0x1
5954 12:44:09.005125 WR_PST = 0x0
5955 12:44:09.009018 DBI_WR = 0x0
5956 12:44:09.009100 DBI_RD = 0x0
5957 12:44:09.012454 OTF = 0x1
5958 12:44:09.015076 ===================================
5959 12:44:09.018537 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5960 12:44:09.022281 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5961 12:44:09.028106 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5962 12:44:09.031715 ===================================
5963 12:44:09.031798 LPDDR4 DRAM CONFIGURATION
5964 12:44:09.035171 ===================================
5965 12:44:09.038565 EX_ROW_EN[0] = 0x10
5966 12:44:09.038647 EX_ROW_EN[1] = 0x0
5967 12:44:09.041354 LP4Y_EN = 0x0
5968 12:44:09.044672 WORK_FSP = 0x0
5969 12:44:09.044771 WL = 0x2
5970 12:44:09.048064 RL = 0x2
5971 12:44:09.048168 BL = 0x2
5972 12:44:09.051862 RPST = 0x0
5973 12:44:09.051943 RD_PRE = 0x0
5974 12:44:09.054993 WR_PRE = 0x1
5975 12:44:09.055074 WR_PST = 0x0
5976 12:44:09.057812 DBI_WR = 0x0
5977 12:44:09.057894 DBI_RD = 0x0
5978 12:44:09.061379 OTF = 0x1
5979 12:44:09.064715 ===================================
5980 12:44:09.071412 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5981 12:44:09.075117 nWR fixed to 30
5982 12:44:09.075199 [ModeRegInit_LP4] CH0 RK0
5983 12:44:09.078449 [ModeRegInit_LP4] CH0 RK1
5984 12:44:09.081134 [ModeRegInit_LP4] CH1 RK0
5985 12:44:09.085629 [ModeRegInit_LP4] CH1 RK1
5986 12:44:09.085710 match AC timing 18
5987 12:44:09.087491 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5988 12:44:09.094578 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5989 12:44:09.097709 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5990 12:44:09.101273 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5991 12:44:09.107705 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5992 12:44:09.107787 ==
5993 12:44:09.111264 Dram Type= 6, Freq= 0, CH_0, rank 0
5994 12:44:09.115538 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5995 12:44:09.115621 ==
5996 12:44:09.121616 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5997 12:44:09.127971 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5998 12:44:09.128054 [CA 0] Center 36 (8~64) winsize 57
5999 12:44:09.130794 [CA 1] Center 36 (8~64) winsize 57
6000 12:44:09.134448 [CA 2] Center 36 (8~64) winsize 57
6001 12:44:09.137383 [CA 3] Center 36 (8~64) winsize 57
6002 12:44:09.141289 [CA 4] Center 36 (8~64) winsize 57
6003 12:44:09.144369 [CA 5] Center 36 (8~64) winsize 57
6004 12:44:09.144451
6005 12:44:09.148306 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6006 12:44:09.148388
6007 12:44:09.154018 [CATrainingPosCal] consider 1 rank data
6008 12:44:09.154100 u2DelayCellTimex100 = 270/100 ps
6009 12:44:09.160457 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6010 12:44:09.163849 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6011 12:44:09.168026 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6012 12:44:09.170309 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6013 12:44:09.174097 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6014 12:44:09.176980 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6015 12:44:09.177061
6016 12:44:09.180436 CA PerBit enable=1, Macro0, CA PI delay=36
6017 12:44:09.180517
6018 12:44:09.183660 [CBTSetCACLKResult] CA Dly = 36
6019 12:44:09.187380 CS Dly: 1 (0~32)
6020 12:44:09.187461 ==
6021 12:44:09.190064 Dram Type= 6, Freq= 0, CH_0, rank 1
6022 12:44:09.193354 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6023 12:44:09.193436 ==
6024 12:44:09.199887 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6025 12:44:09.203702 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6026 12:44:09.207173 [CA 0] Center 36 (8~64) winsize 57
6027 12:44:09.210868 [CA 1] Center 36 (8~64) winsize 57
6028 12:44:09.213820 [CA 2] Center 36 (8~64) winsize 57
6029 12:44:09.217185 [CA 3] Center 36 (8~64) winsize 57
6030 12:44:09.219859 [CA 4] Center 36 (8~64) winsize 57
6031 12:44:09.223766 [CA 5] Center 36 (8~64) winsize 57
6032 12:44:09.223848
6033 12:44:09.226315 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6034 12:44:09.226397
6035 12:44:09.231280 [CATrainingPosCal] consider 2 rank data
6036 12:44:09.232924 u2DelayCellTimex100 = 270/100 ps
6037 12:44:09.236880 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6038 12:44:09.240012 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6039 12:44:09.247372 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6040 12:44:09.249561 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6041 12:44:09.253039 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6042 12:44:09.256428 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6043 12:44:09.256510
6044 12:44:09.260017 CA PerBit enable=1, Macro0, CA PI delay=36
6045 12:44:09.260098
6046 12:44:09.263003 [CBTSetCACLKResult] CA Dly = 36
6047 12:44:09.263084 CS Dly: 1 (0~32)
6048 12:44:09.263149
6049 12:44:09.266830 ----->DramcWriteLeveling(PI) begin...
6050 12:44:09.269699 ==
6051 12:44:09.269781 Dram Type= 6, Freq= 0, CH_0, rank 0
6052 12:44:09.276197 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6053 12:44:09.276279 ==
6054 12:44:09.279437 Write leveling (Byte 0): 32 => 0
6055 12:44:09.283229 Write leveling (Byte 1): 32 => 0
6056 12:44:09.285779 DramcWriteLeveling(PI) end<-----
6057 12:44:09.285860
6058 12:44:09.285925 ==
6059 12:44:09.289654 Dram Type= 6, Freq= 0, CH_0, rank 0
6060 12:44:09.292224 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6061 12:44:09.292305 ==
6062 12:44:09.296101 [Gating] SW mode calibration
6063 12:44:09.302271 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6064 12:44:09.309350 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6065 12:44:09.312276 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6066 12:44:09.316080 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6067 12:44:09.322283 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6068 12:44:09.327113 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6069 12:44:09.328647 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6070 12:44:09.335943 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6071 12:44:09.338463 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6072 12:44:09.341787 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6073 12:44:09.348528 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6074 12:44:09.348610 Total UI for P1: 0, mck2ui 16
6075 12:44:09.351744 best dqsien dly found for B0: ( 0, 10, 16)
6076 12:44:09.355061 Total UI for P1: 0, mck2ui 16
6077 12:44:09.359626 best dqsien dly found for B1: ( 0, 10, 24)
6078 12:44:09.365166 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6079 12:44:09.368579 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6080 12:44:09.368660
6081 12:44:09.372066 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6082 12:44:09.375175 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6083 12:44:09.378590 [Gating] SW calibration Done
6084 12:44:09.378672 ==
6085 12:44:09.381932 Dram Type= 6, Freq= 0, CH_0, rank 0
6086 12:44:09.384694 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6087 12:44:09.384786 ==
6088 12:44:09.388514 RX Vref Scan: 0
6089 12:44:09.388595
6090 12:44:09.388660 RX Vref 0 -> 0, step: 1
6091 12:44:09.388760
6092 12:44:09.392006 RX Delay -410 -> 252, step: 16
6093 12:44:09.399164 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6094 12:44:09.401933 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6095 12:44:09.404575 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6096 12:44:09.409203 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6097 12:44:09.415052 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6098 12:44:09.418422 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6099 12:44:09.421296 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6100 12:44:09.424654 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6101 12:44:09.431959 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6102 12:44:09.434702 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6103 12:44:09.437932 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6104 12:44:09.441768 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6105 12:44:09.448006 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6106 12:44:09.451891 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6107 12:44:09.454919 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6108 12:44:09.457564 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6109 12:44:09.461408 ==
6110 12:44:09.465155 Dram Type= 6, Freq= 0, CH_0, rank 0
6111 12:44:09.468006 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6112 12:44:09.468088 ==
6113 12:44:09.468153 DQS Delay:
6114 12:44:09.471467 DQS0 = 51, DQS1 = 59
6115 12:44:09.471547 DQM Delay:
6116 12:44:09.474135 DQM0 = 12, DQM1 = 16
6117 12:44:09.474217 DQ Delay:
6118 12:44:09.477539 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6119 12:44:09.481607 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6120 12:44:09.485269 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6121 12:44:09.487476 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6122 12:44:09.487558
6123 12:44:09.487622
6124 12:44:09.487682 ==
6125 12:44:09.491017 Dram Type= 6, Freq= 0, CH_0, rank 0
6126 12:44:09.494554 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6127 12:44:09.494636 ==
6128 12:44:09.494700
6129 12:44:09.494761
6130 12:44:09.497561 TX Vref Scan disable
6131 12:44:09.497643 == TX Byte 0 ==
6132 12:44:09.503909 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6133 12:44:09.507560 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6134 12:44:09.507642 == TX Byte 1 ==
6135 12:44:09.513710 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6136 12:44:09.517472 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6137 12:44:09.517554 ==
6138 12:44:09.520814 Dram Type= 6, Freq= 0, CH_0, rank 0
6139 12:44:09.523745 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6140 12:44:09.523852 ==
6141 12:44:09.523945
6142 12:44:09.527619
6143 12:44:09.527701 TX Vref Scan disable
6144 12:44:09.530635 == TX Byte 0 ==
6145 12:44:09.533624 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6146 12:44:09.538149 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6147 12:44:09.540454 == TX Byte 1 ==
6148 12:44:09.543765 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6149 12:44:09.547570 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6150 12:44:09.547652
6151 12:44:09.550524 [DATLAT]
6152 12:44:09.550605 Freq=400, CH0 RK0
6153 12:44:09.550670
6154 12:44:09.555039 DATLAT Default: 0xf
6155 12:44:09.555120 0, 0xFFFF, sum = 0
6156 12:44:09.556742 1, 0xFFFF, sum = 0
6157 12:44:09.556838 2, 0xFFFF, sum = 0
6158 12:44:09.559902 3, 0xFFFF, sum = 0
6159 12:44:09.559985 4, 0xFFFF, sum = 0
6160 12:44:09.563130 5, 0xFFFF, sum = 0
6161 12:44:09.563213 6, 0xFFFF, sum = 0
6162 12:44:09.567192 7, 0xFFFF, sum = 0
6163 12:44:09.567274 8, 0xFFFF, sum = 0
6164 12:44:09.570466 9, 0xFFFF, sum = 0
6165 12:44:09.570549 10, 0xFFFF, sum = 0
6166 12:44:09.573898 11, 0xFFFF, sum = 0
6167 12:44:09.573981 12, 0x0, sum = 1
6168 12:44:09.577136 13, 0x0, sum = 2
6169 12:44:09.577218 14, 0x0, sum = 3
6170 12:44:09.579868 15, 0x0, sum = 4
6171 12:44:09.579950 best_step = 13
6172 12:44:09.580014
6173 12:44:09.580074 ==
6174 12:44:09.583358 Dram Type= 6, Freq= 0, CH_0, rank 0
6175 12:44:09.590416 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6176 12:44:09.590498 ==
6177 12:44:09.590563 RX Vref Scan: 1
6178 12:44:09.590623
6179 12:44:09.594885 RX Vref 0 -> 0, step: 1
6180 12:44:09.594967
6181 12:44:09.596338 RX Delay -359 -> 252, step: 8
6182 12:44:09.596419
6183 12:44:09.599867 Set Vref, RX VrefLevel [Byte0]: 46
6184 12:44:09.603052 [Byte1]: 50
6185 12:44:09.606124
6186 12:44:09.606205 Final RX Vref Byte 0 = 46 to rank0
6187 12:44:09.609807 Final RX Vref Byte 1 = 50 to rank0
6188 12:44:09.612739 Final RX Vref Byte 0 = 46 to rank1
6189 12:44:09.616229 Final RX Vref Byte 1 = 50 to rank1==
6190 12:44:09.619571 Dram Type= 6, Freq= 0, CH_0, rank 0
6191 12:44:09.626277 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6192 12:44:09.626360 ==
6193 12:44:09.626425 DQS Delay:
6194 12:44:09.630224 DQS0 = 52, DQS1 = 64
6195 12:44:09.630305 DQM Delay:
6196 12:44:09.630370 DQM0 = 9, DQM1 = 14
6197 12:44:09.632639 DQ Delay:
6198 12:44:09.636451 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6199 12:44:09.636532 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6200 12:44:09.639734 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6201 12:44:09.643359 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6202 12:44:09.643440
6203 12:44:09.645633
6204 12:44:09.652457 [DQSOSCAuto] RK0, (LSB)MR18= 0xa5a5, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6205 12:44:09.655762 CH0 RK0: MR19=C0C, MR18=A5A5
6206 12:44:09.662702 CH0_RK0: MR19=0xC0C, MR18=0xA5A5, DQSOSC=389, MR23=63, INC=390, DEC=260
6207 12:44:09.662784 ==
6208 12:44:09.665917 Dram Type= 6, Freq= 0, CH_0, rank 1
6209 12:44:09.669205 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6210 12:44:09.669287 ==
6211 12:44:09.672203 [Gating] SW mode calibration
6212 12:44:09.678998 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6213 12:44:09.685751 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6214 12:44:09.688971 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6215 12:44:09.692191 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6216 12:44:09.698432 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6217 12:44:09.702739 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6218 12:44:09.706142 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6219 12:44:09.712201 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6220 12:44:09.715201 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6221 12:44:09.718488 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6222 12:44:09.722536 Total UI for P1: 0, mck2ui 16
6223 12:44:09.725179 best dqsien dly found for B0: ( 0, 10, 8)
6224 12:44:09.728415 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6225 12:44:09.732404 Total UI for P1: 0, mck2ui 16
6226 12:44:09.735773 best dqsien dly found for B1: ( 0, 10, 16)
6227 12:44:09.738708 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6228 12:44:09.745239 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6229 12:44:09.745321
6230 12:44:09.748479 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6231 12:44:09.752080 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6232 12:44:09.755472 [Gating] SW calibration Done
6233 12:44:09.755553 ==
6234 12:44:09.758132 Dram Type= 6, Freq= 0, CH_0, rank 1
6235 12:44:09.761839 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6236 12:44:09.761921 ==
6237 12:44:09.764908 RX Vref Scan: 0
6238 12:44:09.764990
6239 12:44:09.765054 RX Vref 0 -> 0, step: 1
6240 12:44:09.765115
6241 12:44:09.768681 RX Delay -410 -> 252, step: 16
6242 12:44:09.772012 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6243 12:44:09.778405 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6244 12:44:09.781745 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6245 12:44:09.784845 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6246 12:44:09.788279 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6247 12:44:09.798606 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6248 12:44:09.799571 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6249 12:44:09.801840 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6250 12:44:09.804666 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6251 12:44:09.811483 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6252 12:44:09.815217 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6253 12:44:09.818270 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6254 12:44:09.824768 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6255 12:44:09.828348 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6256 12:44:09.831319 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6257 12:44:09.834476 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6258 12:44:09.834558 ==
6259 12:44:09.838150 Dram Type= 6, Freq= 0, CH_0, rank 1
6260 12:44:09.845352 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6261 12:44:09.845437 ==
6262 12:44:09.845502 DQS Delay:
6263 12:44:09.847591 DQS0 = 43, DQS1 = 59
6264 12:44:09.847672 DQM Delay:
6265 12:44:09.852239 DQM0 = 7, DQM1 = 15
6266 12:44:09.852319 DQ Delay:
6267 12:44:09.854613 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6268 12:44:09.857619 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6269 12:44:09.857700 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6270 12:44:09.864524 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6271 12:44:09.864605
6272 12:44:09.864668
6273 12:44:09.864766 ==
6274 12:44:09.867500 Dram Type= 6, Freq= 0, CH_0, rank 1
6275 12:44:09.871051 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6276 12:44:09.871132 ==
6277 12:44:09.871196
6278 12:44:09.871256
6279 12:44:09.873934 TX Vref Scan disable
6280 12:44:09.874014 == TX Byte 0 ==
6281 12:44:09.881086 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6282 12:44:09.884373 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6283 12:44:09.884454 == TX Byte 1 ==
6284 12:44:09.887258 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6285 12:44:09.894047 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6286 12:44:09.894128 ==
6287 12:44:09.897898 Dram Type= 6, Freq= 0, CH_0, rank 1
6288 12:44:09.900540 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6289 12:44:09.900621 ==
6290 12:44:09.900684
6291 12:44:09.900780
6292 12:44:09.903614 TX Vref Scan disable
6293 12:44:09.903694 == TX Byte 0 ==
6294 12:44:09.910126 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6295 12:44:09.914598 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6296 12:44:09.914678 == TX Byte 1 ==
6297 12:44:09.920573 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6298 12:44:09.923779 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6299 12:44:09.923860
6300 12:44:09.923922 [DATLAT]
6301 12:44:09.927239 Freq=400, CH0 RK1
6302 12:44:09.927319
6303 12:44:09.927382 DATLAT Default: 0xd
6304 12:44:09.930101 0, 0xFFFF, sum = 0
6305 12:44:09.930183 1, 0xFFFF, sum = 0
6306 12:44:09.933801 2, 0xFFFF, sum = 0
6307 12:44:09.933882 3, 0xFFFF, sum = 0
6308 12:44:09.936778 4, 0xFFFF, sum = 0
6309 12:44:09.936860 5, 0xFFFF, sum = 0
6310 12:44:09.940020 6, 0xFFFF, sum = 0
6311 12:44:09.940101 7, 0xFFFF, sum = 0
6312 12:44:09.943166 8, 0xFFFF, sum = 0
6313 12:44:09.943247 9, 0xFFFF, sum = 0
6314 12:44:09.946989 10, 0xFFFF, sum = 0
6315 12:44:09.949978 11, 0xFFFF, sum = 0
6316 12:44:09.950060 12, 0x0, sum = 1
6317 12:44:09.950124 13, 0x0, sum = 2
6318 12:44:09.953388 14, 0x0, sum = 3
6319 12:44:09.953469 15, 0x0, sum = 4
6320 12:44:09.956750 best_step = 13
6321 12:44:09.956844
6322 12:44:09.956907 ==
6323 12:44:09.960824 Dram Type= 6, Freq= 0, CH_0, rank 1
6324 12:44:09.963447 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6325 12:44:09.963527 ==
6326 12:44:09.966778 RX Vref Scan: 0
6327 12:44:09.966857
6328 12:44:09.966921 RX Vref 0 -> 0, step: 1
6329 12:44:09.969824
6330 12:44:09.969903 RX Delay -359 -> 252, step: 8
6331 12:44:09.978589 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6332 12:44:09.981569 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6333 12:44:09.985805 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6334 12:44:09.988149 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6335 12:44:09.995161 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6336 12:44:09.998722 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6337 12:44:10.001486 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6338 12:44:10.005257 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6339 12:44:10.011280 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6340 12:44:10.014776 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6341 12:44:10.018116 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6342 12:44:10.024869 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6343 12:44:10.028290 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6344 12:44:10.031468 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6345 12:44:10.034939 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6346 12:44:10.041490 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6347 12:44:10.041571 ==
6348 12:44:10.044343 Dram Type= 6, Freq= 0, CH_0, rank 1
6349 12:44:10.048198 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6350 12:44:10.048305 ==
6351 12:44:10.048398 DQS Delay:
6352 12:44:10.051146 DQS0 = 52, DQS1 = 64
6353 12:44:10.051264 DQM Delay:
6354 12:44:10.054553 DQM0 = 10, DQM1 = 14
6355 12:44:10.054634 DQ Delay:
6356 12:44:10.058182 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6357 12:44:10.061100 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6358 12:44:10.064668 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6359 12:44:10.067944 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6360 12:44:10.068026
6361 12:44:10.068090
6362 12:44:10.074112 [DQSOSCAuto] RK1, (LSB)MR18= 0xc5c5, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 385 ps
6363 12:44:10.077642 CH0 RK1: MR19=C0C, MR18=C5C5
6364 12:44:10.084451 CH0_RK1: MR19=0xC0C, MR18=0xC5C5, DQSOSC=385, MR23=63, INC=398, DEC=265
6365 12:44:10.088627 [RxdqsGatingPostProcess] freq 400
6366 12:44:10.095458 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6367 12:44:10.098488 Pre-setting of DQS Precalculation
6368 12:44:10.100839 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6369 12:44:10.100921 ==
6370 12:44:10.104164 Dram Type= 6, Freq= 0, CH_1, rank 0
6371 12:44:10.107781 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6372 12:44:10.107863 ==
6373 12:44:10.114115 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6374 12:44:10.120610 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6375 12:44:10.124193 [CA 0] Center 36 (8~64) winsize 57
6376 12:44:10.127394 [CA 1] Center 36 (8~64) winsize 57
6377 12:44:10.131052 [CA 2] Center 36 (8~64) winsize 57
6378 12:44:10.133618 [CA 3] Center 36 (8~64) winsize 57
6379 12:44:10.137745 [CA 4] Center 36 (8~64) winsize 57
6380 12:44:10.140253 [CA 5] Center 36 (8~64) winsize 57
6381 12:44:10.140337
6382 12:44:10.144731 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6383 12:44:10.144832
6384 12:44:10.148635 [CATrainingPosCal] consider 1 rank data
6385 12:44:10.150760 u2DelayCellTimex100 = 270/100 ps
6386 12:44:10.153544 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6387 12:44:10.157282 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6388 12:44:10.160608 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6389 12:44:10.163651 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6390 12:44:10.166805 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6391 12:44:10.170109 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6392 12:44:10.170192
6393 12:44:10.176517 CA PerBit enable=1, Macro0, CA PI delay=36
6394 12:44:10.176603
6395 12:44:10.176668 [CBTSetCACLKResult] CA Dly = 36
6396 12:44:10.180146 CS Dly: 1 (0~32)
6397 12:44:10.180257 ==
6398 12:44:10.183855 Dram Type= 6, Freq= 0, CH_1, rank 1
6399 12:44:10.186730 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6400 12:44:10.186825 ==
6401 12:44:10.193260 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6402 12:44:10.200132 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6403 12:44:10.203598 [CA 0] Center 36 (8~64) winsize 57
6404 12:44:10.206896 [CA 1] Center 36 (8~64) winsize 57
6405 12:44:10.209908 [CA 2] Center 36 (8~64) winsize 57
6406 12:44:10.209984 [CA 3] Center 36 (8~64) winsize 57
6407 12:44:10.213505 [CA 4] Center 32 (8~56) winsize 49
6408 12:44:10.216468 [CA 5] Center 32 (8~56) winsize 49
6409 12:44:10.216565
6410 12:44:10.223255 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6411 12:44:10.223360
6412 12:44:10.227165 [CATrainingPosCal] consider 2 rank data
6413 12:44:10.229926 u2DelayCellTimex100 = 270/100 ps
6414 12:44:10.233264 CA0 delay=36 (8~64),Diff = 4 PI (57 cell)
6415 12:44:10.237356 CA1 delay=36 (8~64),Diff = 4 PI (57 cell)
6416 12:44:10.239783 CA2 delay=36 (8~64),Diff = 4 PI (57 cell)
6417 12:44:10.243705 CA3 delay=36 (8~64),Diff = 4 PI (57 cell)
6418 12:44:10.246229 CA4 delay=32 (8~56),Diff = 0 PI (0 cell)
6419 12:44:10.249803 CA5 delay=32 (8~56),Diff = 0 PI (0 cell)
6420 12:44:10.249874
6421 12:44:10.253612 CA PerBit enable=1, Macro0, CA PI delay=32
6422 12:44:10.253696
6423 12:44:10.256660 [CBTSetCACLKResult] CA Dly = 32
6424 12:44:10.260204 CS Dly: 1 (0~32)
6425 12:44:10.260285
6426 12:44:10.263908 ----->DramcWriteLeveling(PI) begin...
6427 12:44:10.263991 ==
6428 12:44:10.266514 Dram Type= 6, Freq= 0, CH_1, rank 0
6429 12:44:10.269652 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6430 12:44:10.269734 ==
6431 12:44:10.273487 Write leveling (Byte 0): 32 => 0
6432 12:44:10.276525 Write leveling (Byte 1): 32 => 0
6433 12:44:10.280110 DramcWriteLeveling(PI) end<-----
6434 12:44:10.280192
6435 12:44:10.280257 ==
6436 12:44:10.283032 Dram Type= 6, Freq= 0, CH_1, rank 0
6437 12:44:10.286888 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6438 12:44:10.286970 ==
6439 12:44:10.289448 [Gating] SW mode calibration
6440 12:44:10.295887 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6441 12:44:10.302258 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6442 12:44:10.306361 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6443 12:44:10.312230 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6444 12:44:10.315867 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6445 12:44:10.320414 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6446 12:44:10.322927 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6447 12:44:10.328889 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6448 12:44:10.332786 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6449 12:44:10.336091 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6450 12:44:10.342291 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6451 12:44:10.345578 Total UI for P1: 0, mck2ui 16
6452 12:44:10.349069 best dqsien dly found for B0: ( 0, 10, 16)
6453 12:44:10.352141 Total UI for P1: 0, mck2ui 16
6454 12:44:10.355471 best dqsien dly found for B1: ( 0, 10, 16)
6455 12:44:10.358948 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6456 12:44:10.362246 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6457 12:44:10.362327
6458 12:44:10.365293 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6459 12:44:10.369303 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6460 12:44:10.372684 [Gating] SW calibration Done
6461 12:44:10.372772 ==
6462 12:44:10.375164 Dram Type= 6, Freq= 0, CH_1, rank 0
6463 12:44:10.379021 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6464 12:44:10.379103 ==
6465 12:44:10.382659 RX Vref Scan: 0
6466 12:44:10.382741
6467 12:44:10.386443 RX Vref 0 -> 0, step: 1
6468 12:44:10.386524
6469 12:44:10.386589 RX Delay -410 -> 252, step: 16
6470 12:44:10.393170 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6471 12:44:10.395301 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6472 12:44:10.398811 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6473 12:44:10.405581 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6474 12:44:10.408444 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6475 12:44:10.411803 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6476 12:44:10.415114 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6477 12:44:10.422123 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6478 12:44:10.425535 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6479 12:44:10.428563 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6480 12:44:10.431957 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6481 12:44:10.437947 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6482 12:44:10.441429 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6483 12:44:10.444864 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6484 12:44:10.448343 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6485 12:44:10.454479 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6486 12:44:10.454560 ==
6487 12:44:10.458290 Dram Type= 6, Freq= 0, CH_1, rank 0
6488 12:44:10.461344 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6489 12:44:10.461426 ==
6490 12:44:10.465014 DQS Delay:
6491 12:44:10.465095 DQS0 = 43, DQS1 = 59
6492 12:44:10.465161 DQM Delay:
6493 12:44:10.467816 DQM0 = 6, DQM1 = 15
6494 12:44:10.467897 DQ Delay:
6495 12:44:10.471651 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6496 12:44:10.474404 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6497 12:44:10.477862 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6498 12:44:10.481799 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6499 12:44:10.481880
6500 12:44:10.481944
6501 12:44:10.482004 ==
6502 12:44:10.484582 Dram Type= 6, Freq= 0, CH_1, rank 0
6503 12:44:10.488092 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6504 12:44:10.488174 ==
6505 12:44:10.490900
6506 12:44:10.490981
6507 12:44:10.491045 TX Vref Scan disable
6508 12:44:10.495353 == TX Byte 0 ==
6509 12:44:10.497592 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6510 12:44:10.501121 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6511 12:44:10.504283 == TX Byte 1 ==
6512 12:44:10.508101 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6513 12:44:10.511102 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6514 12:44:10.511184 ==
6515 12:44:10.514065 Dram Type= 6, Freq= 0, CH_1, rank 0
6516 12:44:10.521222 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6517 12:44:10.521335 ==
6518 12:44:10.521428
6519 12:44:10.521519
6520 12:44:10.521614 TX Vref Scan disable
6521 12:44:10.524015 == TX Byte 0 ==
6522 12:44:10.527116 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6523 12:44:10.530539 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6524 12:44:10.534144 == TX Byte 1 ==
6525 12:44:10.537605 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6526 12:44:10.540574 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6527 12:44:10.544034
6528 12:44:10.544116 [DATLAT]
6529 12:44:10.544181 Freq=400, CH1 RK0
6530 12:44:10.544241
6531 12:44:10.547033 DATLAT Default: 0xf
6532 12:44:10.547114 0, 0xFFFF, sum = 0
6533 12:44:10.550596 1, 0xFFFF, sum = 0
6534 12:44:10.550679 2, 0xFFFF, sum = 0
6535 12:44:10.553875 3, 0xFFFF, sum = 0
6536 12:44:10.553971 4, 0xFFFF, sum = 0
6537 12:44:10.556809 5, 0xFFFF, sum = 0
6538 12:44:10.560168 6, 0xFFFF, sum = 0
6539 12:44:10.560251 7, 0xFFFF, sum = 0
6540 12:44:10.563333 8, 0xFFFF, sum = 0
6541 12:44:10.563415 9, 0xFFFF, sum = 0
6542 12:44:10.566998 10, 0xFFFF, sum = 0
6543 12:44:10.567082 11, 0xFFFF, sum = 0
6544 12:44:10.570032 12, 0x0, sum = 1
6545 12:44:10.570114 13, 0x0, sum = 2
6546 12:44:10.573941 14, 0x0, sum = 3
6547 12:44:10.574024 15, 0x0, sum = 4
6548 12:44:10.577562 best_step = 13
6549 12:44:10.577642
6550 12:44:10.577707 ==
6551 12:44:10.580524 Dram Type= 6, Freq= 0, CH_1, rank 0
6552 12:44:10.583785 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6553 12:44:10.583904 ==
6554 12:44:10.583991 RX Vref Scan: 1
6555 12:44:10.584072
6556 12:44:10.586641 RX Vref 0 -> 0, step: 1
6557 12:44:10.586722
6558 12:44:10.590616 RX Delay -359 -> 252, step: 8
6559 12:44:10.590698
6560 12:44:10.594065 Set Vref, RX VrefLevel [Byte0]: 54
6561 12:44:10.596498 [Byte1]: 50
6562 12:44:10.600918
6563 12:44:10.600999 Final RX Vref Byte 0 = 54 to rank0
6564 12:44:10.603981 Final RX Vref Byte 1 = 50 to rank0
6565 12:44:10.608066 Final RX Vref Byte 0 = 54 to rank1
6566 12:44:10.610702 Final RX Vref Byte 1 = 50 to rank1==
6567 12:44:10.614511 Dram Type= 6, Freq= 0, CH_1, rank 0
6568 12:44:10.620493 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6569 12:44:10.620575 ==
6570 12:44:10.620640 DQS Delay:
6571 12:44:10.623845 DQS0 = 48, DQS1 = 64
6572 12:44:10.623927 DQM Delay:
6573 12:44:10.623992 DQM0 = 8, DQM1 = 15
6574 12:44:10.627479 DQ Delay:
6575 12:44:10.630797 DQ0 =8, DQ1 =4, DQ2 =0, DQ3 =4
6576 12:44:10.630878 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =4
6577 12:44:10.633683 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6578 12:44:10.637772 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6579 12:44:10.637854
6580 12:44:10.637918
6581 12:44:10.648649 [DQSOSCAuto] RK0, (LSB)MR18= 0xd0d0, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6582 12:44:10.650095 CH1 RK0: MR19=C0C, MR18=D0D0
6583 12:44:10.657509 CH1_RK0: MR19=0xC0C, MR18=0xD0D0, DQSOSC=384, MR23=63, INC=400, DEC=267
6584 12:44:10.657591 ==
6585 12:44:10.660406 Dram Type= 6, Freq= 0, CH_1, rank 1
6586 12:44:10.663896 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6587 12:44:10.663978 ==
6588 12:44:10.667120 [Gating] SW mode calibration
6589 12:44:10.673421 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6590 12:44:10.680048 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6591 12:44:10.684203 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6592 12:44:10.686520 0 7 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
6593 12:44:10.693360 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6594 12:44:10.697022 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6595 12:44:10.699821 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6596 12:44:10.703473 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6597 12:44:10.709735 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6598 12:44:10.713368 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6599 12:44:10.716463 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6600 12:44:10.719554 Total UI for P1: 0, mck2ui 16
6601 12:44:10.723412 best dqsien dly found for B0: ( 0, 10, 16)
6602 12:44:10.726805 Total UI for P1: 0, mck2ui 16
6603 12:44:10.729578 best dqsien dly found for B1: ( 0, 10, 16)
6604 12:44:10.733318 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6605 12:44:10.739552 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6606 12:44:10.739634
6607 12:44:10.743841 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6608 12:44:10.746624 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6609 12:44:10.749648 [Gating] SW calibration Done
6610 12:44:10.749729 ==
6611 12:44:10.753848 Dram Type= 6, Freq= 0, CH_1, rank 1
6612 12:44:10.756608 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6613 12:44:10.756691 ==
6614 12:44:10.759366 RX Vref Scan: 0
6615 12:44:10.759447
6616 12:44:10.759512 RX Vref 0 -> 0, step: 1
6617 12:44:10.759571
6618 12:44:10.763309 RX Delay -410 -> 252, step: 16
6619 12:44:10.769535 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6620 12:44:10.772764 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6621 12:44:10.775672 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6622 12:44:10.779137 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6623 12:44:10.785688 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6624 12:44:10.789536 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6625 12:44:10.792423 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6626 12:44:10.796040 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6627 12:44:10.803433 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6628 12:44:10.806685 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6629 12:44:10.809240 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6630 12:44:10.812365 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6631 12:44:10.818960 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6632 12:44:10.823623 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6633 12:44:10.825649 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6634 12:44:10.829071 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6635 12:44:10.833150 ==
6636 12:44:10.833233 Dram Type= 6, Freq= 0, CH_1, rank 1
6637 12:44:10.839004 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6638 12:44:10.839086 ==
6639 12:44:10.839151 DQS Delay:
6640 12:44:10.842374 DQS0 = 43, DQS1 = 59
6641 12:44:10.842483 DQM Delay:
6642 12:44:10.845665 DQM0 = 10, DQM1 = 18
6643 12:44:10.845746 DQ Delay:
6644 12:44:10.849205 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6645 12:44:10.852295 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6646 12:44:10.852406 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6647 12:44:10.860006 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6648 12:44:10.860087
6649 12:44:10.860152
6650 12:44:10.860211 ==
6651 12:44:10.862749 Dram Type= 6, Freq= 0, CH_1, rank 1
6652 12:44:10.865635 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6653 12:44:10.865717 ==
6654 12:44:10.865782
6655 12:44:10.865841
6656 12:44:10.869177 TX Vref Scan disable
6657 12:44:10.869258 == TX Byte 0 ==
6658 12:44:10.872493 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6659 12:44:10.878984 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6660 12:44:10.879065 == TX Byte 1 ==
6661 12:44:10.882877 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6662 12:44:10.888899 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6663 12:44:10.888981 ==
6664 12:44:10.891854 Dram Type= 6, Freq= 0, CH_1, rank 1
6665 12:44:10.895337 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6666 12:44:10.895420 ==
6667 12:44:10.895484
6668 12:44:10.895544
6669 12:44:10.898232 TX Vref Scan disable
6670 12:44:10.898313 == TX Byte 0 ==
6671 12:44:10.905714 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6672 12:44:10.908162 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6673 12:44:10.908244 == TX Byte 1 ==
6674 12:44:10.915768 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6675 12:44:10.918870 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6676 12:44:10.918952
6677 12:44:10.919016 [DATLAT]
6678 12:44:10.922613 Freq=400, CH1 RK1
6679 12:44:10.922695
6680 12:44:10.922760 DATLAT Default: 0xd
6681 12:44:10.924744 0, 0xFFFF, sum = 0
6682 12:44:10.924827 1, 0xFFFF, sum = 0
6683 12:44:10.928012 2, 0xFFFF, sum = 0
6684 12:44:10.928094 3, 0xFFFF, sum = 0
6685 12:44:10.931650 4, 0xFFFF, sum = 0
6686 12:44:10.931734 5, 0xFFFF, sum = 0
6687 12:44:10.935400 6, 0xFFFF, sum = 0
6688 12:44:10.935484 7, 0xFFFF, sum = 0
6689 12:44:10.938093 8, 0xFFFF, sum = 0
6690 12:44:10.938176 9, 0xFFFF, sum = 0
6691 12:44:10.941506 10, 0xFFFF, sum = 0
6692 12:44:10.945229 11, 0xFFFF, sum = 0
6693 12:44:10.945312 12, 0x0, sum = 1
6694 12:44:10.945377 13, 0x0, sum = 2
6695 12:44:10.947879 14, 0x0, sum = 3
6696 12:44:10.947961 15, 0x0, sum = 4
6697 12:44:10.951501 best_step = 13
6698 12:44:10.951581
6699 12:44:10.951645 ==
6700 12:44:10.954770 Dram Type= 6, Freq= 0, CH_1, rank 1
6701 12:44:10.958136 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6702 12:44:10.958218 ==
6703 12:44:10.961377 RX Vref Scan: 0
6704 12:44:10.961458
6705 12:44:10.961522 RX Vref 0 -> 0, step: 1
6706 12:44:10.961582
6707 12:44:10.964591 RX Delay -359 -> 252, step: 8
6708 12:44:10.974024 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6709 12:44:10.976859 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6710 12:44:10.979422 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6711 12:44:10.982977 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6712 12:44:10.989974 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6713 12:44:10.992527 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6714 12:44:10.996605 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6715 12:44:11.002856 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6716 12:44:11.006196 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6717 12:44:11.009610 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6718 12:44:11.012674 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6719 12:44:11.019024 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6720 12:44:11.022474 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6721 12:44:11.025828 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6722 12:44:11.028952 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6723 12:44:11.035598 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
6724 12:44:11.035681 ==
6725 12:44:11.040010 Dram Type= 6, Freq= 0, CH_1, rank 1
6726 12:44:11.042464 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6727 12:44:11.042545 ==
6728 12:44:11.042611 DQS Delay:
6729 12:44:11.045450 DQS0 = 48, DQS1 = 64
6730 12:44:11.045531 DQM Delay:
6731 12:44:11.048901 DQM0 = 9, DQM1 = 15
6732 12:44:11.048983 DQ Delay:
6733 12:44:11.052236 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6734 12:44:11.055637 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6735 12:44:11.059134 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6736 12:44:11.062562 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6737 12:44:11.062643
6738 12:44:11.062708
6739 12:44:11.069162 [DQSOSCAuto] RK1, (LSB)MR18= 0xa6a6, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6740 12:44:11.072347 CH1 RK1: MR19=C0C, MR18=A6A6
6741 12:44:11.079225 CH1_RK1: MR19=0xC0C, MR18=0xA6A6, DQSOSC=389, MR23=63, INC=390, DEC=260
6742 12:44:11.082062 [RxdqsGatingPostProcess] freq 400
6743 12:44:11.088853 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6744 12:44:11.091739 Pre-setting of DQS Precalculation
6745 12:44:11.095445 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6746 12:44:11.103089 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6747 12:44:11.108646 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6748 12:44:11.111365
6749 12:44:11.111446
6750 12:44:11.111509 [Calibration Summary] 800 Mbps
6751 12:44:11.114650 CH 0, Rank 0
6752 12:44:11.114731 SW Impedance : PASS
6753 12:44:11.119029 DUTY Scan : NO K
6754 12:44:11.121987 ZQ Calibration : PASS
6755 12:44:11.122068 Jitter Meter : NO K
6756 12:44:11.124639 CBT Training : PASS
6757 12:44:11.128067 Write leveling : PASS
6758 12:44:11.128149 RX DQS gating : PASS
6759 12:44:11.131799 RX DQ/DQS(RDDQC) : PASS
6760 12:44:11.135007 TX DQ/DQS : PASS
6761 12:44:11.135090 RX DATLAT : PASS
6762 12:44:11.138372 RX DQ/DQS(Engine): PASS
6763 12:44:11.141535 TX OE : NO K
6764 12:44:11.141635 All Pass.
6765 12:44:11.141725
6766 12:44:11.141815 CH 0, Rank 1
6767 12:44:11.144775 SW Impedance : PASS
6768 12:44:11.147968 DUTY Scan : NO K
6769 12:44:11.148041 ZQ Calibration : PASS
6770 12:44:11.151498 Jitter Meter : NO K
6771 12:44:11.155742 CBT Training : PASS
6772 12:44:11.155840 Write leveling : NO K
6773 12:44:11.157964 RX DQS gating : PASS
6774 12:44:11.161420 RX DQ/DQS(RDDQC) : PASS
6775 12:44:11.161494 TX DQ/DQS : PASS
6776 12:44:11.164423 RX DATLAT : PASS
6777 12:44:11.164492 RX DQ/DQS(Engine): PASS
6778 12:44:11.167918 TX OE : NO K
6779 12:44:11.167987 All Pass.
6780 12:44:11.168047
6781 12:44:11.171268 CH 1, Rank 0
6782 12:44:11.171336 SW Impedance : PASS
6783 12:44:11.174291 DUTY Scan : NO K
6784 12:44:11.178110 ZQ Calibration : PASS
6785 12:44:11.178183 Jitter Meter : NO K
6786 12:44:11.180613 CBT Training : PASS
6787 12:44:11.185974 Write leveling : PASS
6788 12:44:11.186047 RX DQS gating : PASS
6789 12:44:11.189433 RX DQ/DQS(RDDQC) : PASS
6790 12:44:11.191100 TX DQ/DQS : PASS
6791 12:44:11.191199 RX DATLAT : PASS
6792 12:44:11.194480 RX DQ/DQS(Engine): PASS
6793 12:44:11.197243 TX OE : NO K
6794 12:44:11.197341 All Pass.
6795 12:44:11.197434
6796 12:44:11.197522 CH 1, Rank 1
6797 12:44:11.200627 SW Impedance : PASS
6798 12:44:11.204149 DUTY Scan : NO K
6799 12:44:11.204247 ZQ Calibration : PASS
6800 12:44:11.207954 Jitter Meter : NO K
6801 12:44:11.211206 CBT Training : PASS
6802 12:44:11.211279 Write leveling : NO K
6803 12:44:11.214355 RX DQS gating : PASS
6804 12:44:11.217386 RX DQ/DQS(RDDQC) : PASS
6805 12:44:11.217456 TX DQ/DQS : PASS
6806 12:44:11.220679 RX DATLAT : PASS
6807 12:44:11.224396 RX DQ/DQS(Engine): PASS
6808 12:44:11.224512 TX OE : NO K
6809 12:44:11.224605 All Pass.
6810 12:44:11.227510
6811 12:44:11.227615 DramC Write-DBI off
6812 12:44:11.230626 PER_BANK_REFRESH: Hybrid Mode
6813 12:44:11.230724 TX_TRACKING: ON
6814 12:44:11.240531 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6815 12:44:11.243758 [FAST_K] Save calibration result to emmc
6816 12:44:11.247364 dramc_set_vcore_voltage set vcore to 725000
6817 12:44:11.250559 Read voltage for 1600, 0
6818 12:44:11.250658 Vio18 = 0
6819 12:44:11.253394 Vcore = 725000
6820 12:44:11.253491 Vdram = 0
6821 12:44:11.253590 Vddq = 0
6822 12:44:11.253678 Vmddr = 0
6823 12:44:11.260418 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6824 12:44:11.266842 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6825 12:44:11.266932 MEM_TYPE=3, freq_sel=13
6826 12:44:11.270114 sv_algorithm_assistance_LP4_3733
6827 12:44:11.274068 ============ PULL DRAM RESETB DOWN ============
6828 12:44:11.280270 ========== PULL DRAM RESETB DOWN end =========
6829 12:44:11.283375 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6830 12:44:11.286987 ===================================
6831 12:44:11.290567 LPDDR4 DRAM CONFIGURATION
6832 12:44:11.293803 ===================================
6833 12:44:11.293874 EX_ROW_EN[0] = 0x0
6834 12:44:11.296799 EX_ROW_EN[1] = 0x0
6835 12:44:11.300870 LP4Y_EN = 0x0
6836 12:44:11.300941 WORK_FSP = 0x1
6837 12:44:11.303173 WL = 0x5
6838 12:44:11.303269 RL = 0x5
6839 12:44:11.306922 BL = 0x2
6840 12:44:11.307019 RPST = 0x0
6841 12:44:11.310228 RD_PRE = 0x0
6842 12:44:11.310298 WR_PRE = 0x1
6843 12:44:11.313205 WR_PST = 0x1
6844 12:44:11.313278 DBI_WR = 0x0
6845 12:44:11.316453 DBI_RD = 0x0
6846 12:44:11.316526 OTF = 0x1
6847 12:44:11.319705 ===================================
6848 12:44:11.323181 ===================================
6849 12:44:11.326838 ANA top config
6850 12:44:11.330581 ===================================
6851 12:44:11.330663 DLL_ASYNC_EN = 0
6852 12:44:11.332985 ALL_SLAVE_EN = 0
6853 12:44:11.336452 NEW_RANK_MODE = 1
6854 12:44:11.340312 DLL_IDLE_MODE = 1
6855 12:44:11.342800 LP45_APHY_COMB_EN = 1
6856 12:44:11.342881 TX_ODT_DIS = 0
6857 12:44:11.346297 NEW_8X_MODE = 1
6858 12:44:11.349674 ===================================
6859 12:44:11.353055 ===================================
6860 12:44:11.355844 data_rate = 3200
6861 12:44:11.360311 CKR = 1
6862 12:44:11.363269 DQ_P2S_RATIO = 8
6863 12:44:11.366489 ===================================
6864 12:44:11.369084 CA_P2S_RATIO = 8
6865 12:44:11.369165 DQ_CA_OPEN = 0
6866 12:44:11.372987 DQ_SEMI_OPEN = 0
6867 12:44:11.376059 CA_SEMI_OPEN = 0
6868 12:44:11.379100 CA_FULL_RATE = 0
6869 12:44:11.382621 DQ_CKDIV4_EN = 0
6870 12:44:11.385900 CA_CKDIV4_EN = 0
6871 12:44:11.385982 CA_PREDIV_EN = 0
6872 12:44:11.389191 PH8_DLY = 12
6873 12:44:11.392287 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6874 12:44:11.395667 DQ_AAMCK_DIV = 4
6875 12:44:11.399393 CA_AAMCK_DIV = 4
6876 12:44:11.402233 CA_ADMCK_DIV = 4
6877 12:44:11.402315 DQ_TRACK_CA_EN = 0
6878 12:44:11.405674 CA_PICK = 1600
6879 12:44:11.408657 CA_MCKIO = 1600
6880 12:44:11.412597 MCKIO_SEMI = 0
6881 12:44:11.415345 PLL_FREQ = 3068
6882 12:44:11.418509 DQ_UI_PI_RATIO = 32
6883 12:44:11.421772 CA_UI_PI_RATIO = 0
6884 12:44:11.425468 ===================================
6885 12:44:11.428452 ===================================
6886 12:44:11.432141 memory_type:LPDDR4
6887 12:44:11.432223 GP_NUM : 10
6888 12:44:11.435269 SRAM_EN : 1
6889 12:44:11.435350 MD32_EN : 0
6890 12:44:11.438320 ===================================
6891 12:44:11.442129 [ANA_INIT] >>>>>>>>>>>>>>
6892 12:44:11.445427 <<<<<< [CONFIGURE PHASE]: ANA_TX
6893 12:44:11.448410 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6894 12:44:11.452275 ===================================
6895 12:44:11.455237 data_rate = 3200,PCW = 0X7600
6896 12:44:11.458332 ===================================
6897 12:44:11.461325 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6898 12:44:11.465457 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6899 12:44:11.473467 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6900 12:44:11.478349 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6901 12:44:11.481520 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6902 12:44:11.484905 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6903 12:44:11.484987 [ANA_INIT] flow start
6904 12:44:11.489109 [ANA_INIT] PLL >>>>>>>>
6905 12:44:11.491914 [ANA_INIT] PLL <<<<<<<<
6906 12:44:11.491995 [ANA_INIT] MIDPI >>>>>>>>
6907 12:44:11.495253 [ANA_INIT] MIDPI <<<<<<<<
6908 12:44:11.498301 [ANA_INIT] DLL >>>>>>>>
6909 12:44:11.498383 [ANA_INIT] DLL <<<<<<<<
6910 12:44:11.501911 [ANA_INIT] flow end
6911 12:44:11.504542 ============ LP4 DIFF to SE enter ============
6912 12:44:11.507865 ============ LP4 DIFF to SE exit ============
6913 12:44:11.511322 [ANA_INIT] <<<<<<<<<<<<<
6914 12:44:11.515208 [Flow] Enable top DCM control >>>>>
6915 12:44:11.517522 [Flow] Enable top DCM control <<<<<
6916 12:44:11.522262 Enable DLL master slave shuffle
6917 12:44:11.528109 ==============================================================
6918 12:44:11.528233 Gating Mode config
6919 12:44:11.534508 ==============================================================
6920 12:44:11.534590 Config description:
6921 12:44:11.544473 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6922 12:44:11.550616 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6923 12:44:11.557435 SELPH_MODE 0: By rank 1: By Phase
6924 12:44:11.564428 ==============================================================
6925 12:44:11.564510 GAT_TRACK_EN = 1
6926 12:44:11.567468 RX_GATING_MODE = 2
6927 12:44:11.571969 RX_GATING_TRACK_MODE = 2
6928 12:44:11.574820 SELPH_MODE = 1
6929 12:44:11.577953 PICG_EARLY_EN = 1
6930 12:44:11.580971 VALID_LAT_VALUE = 1
6931 12:44:11.587477 ==============================================================
6932 12:44:11.591082 Enter into Gating configuration >>>>
6933 12:44:11.594340 Exit from Gating configuration <<<<
6934 12:44:11.597227 Enter into DVFS_PRE_config >>>>>
6935 12:44:11.607823 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6936 12:44:11.610576 Exit from DVFS_PRE_config <<<<<
6937 12:44:11.613711 Enter into PICG configuration >>>>
6938 12:44:11.617513 Exit from PICG configuration <<<<
6939 12:44:11.620573 [RX_INPUT] configuration >>>>>
6940 12:44:11.620681 [RX_INPUT] configuration <<<<<
6941 12:44:11.627047 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6942 12:44:11.634223 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6943 12:44:11.640229 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6944 12:44:11.643477 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6945 12:44:11.650213 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6946 12:44:11.657019 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6947 12:44:11.660184 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6948 12:44:11.666921 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6949 12:44:11.670019 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6950 12:44:11.673477 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6951 12:44:11.676730 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6952 12:44:11.683603 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6953 12:44:11.686573 ===================================
6954 12:44:11.686655 LPDDR4 DRAM CONFIGURATION
6955 12:44:11.689878 ===================================
6956 12:44:11.693040 EX_ROW_EN[0] = 0x0
6957 12:44:11.695984 EX_ROW_EN[1] = 0x0
6958 12:44:11.696065 LP4Y_EN = 0x0
6959 12:44:11.699602 WORK_FSP = 0x1
6960 12:44:11.699684 WL = 0x5
6961 12:44:11.702760 RL = 0x5
6962 12:44:11.702841 BL = 0x2
6963 12:44:11.706352 RPST = 0x0
6964 12:44:11.706433 RD_PRE = 0x0
6965 12:44:11.709308 WR_PRE = 0x1
6966 12:44:11.709390 WR_PST = 0x1
6967 12:44:11.712920 DBI_WR = 0x0
6968 12:44:11.713001 DBI_RD = 0x0
6969 12:44:11.715723 OTF = 0x1
6970 12:44:11.719365 ===================================
6971 12:44:11.723324 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6972 12:44:11.726066 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6973 12:44:11.733020 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6974 12:44:11.736560 ===================================
6975 12:44:11.736669 LPDDR4 DRAM CONFIGURATION
6976 12:44:11.739215 ===================================
6977 12:44:11.742787 EX_ROW_EN[0] = 0x10
6978 12:44:11.746117 EX_ROW_EN[1] = 0x0
6979 12:44:11.746198 LP4Y_EN = 0x0
6980 12:44:11.750342 WORK_FSP = 0x1
6981 12:44:11.750423 WL = 0x5
6982 12:44:11.752984 RL = 0x5
6983 12:44:11.753065 BL = 0x2
6984 12:44:11.755867 RPST = 0x0
6985 12:44:11.755949 RD_PRE = 0x0
6986 12:44:11.758952 WR_PRE = 0x1
6987 12:44:11.759033 WR_PST = 0x1
6988 12:44:11.762651 DBI_WR = 0x0
6989 12:44:11.762732 DBI_RD = 0x0
6990 12:44:11.765609 OTF = 0x1
6991 12:44:11.768870 ===================================
6992 12:44:11.775622 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6993 12:44:11.775718 ==
6994 12:44:11.778657 Dram Type= 6, Freq= 0, CH_0, rank 0
6995 12:44:11.782404 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6996 12:44:11.782486 ==
6997 12:44:11.785367 [Duty_Offset_Calibration]
6998 12:44:11.785448 B0:0 B1:2 CA:1
6999 12:44:11.785512
7000 12:44:11.788938 [DutyScan_Calibration_Flow] k_type=0
7001 12:44:11.800050
7002 12:44:11.800131 ==CLK 0==
7003 12:44:11.803244 Final CLK duty delay cell = 0
7004 12:44:11.806549 [0] MAX Duty = 5187%(X100), DQS PI = 24
7005 12:44:11.809671 [0] MIN Duty = 4969%(X100), DQS PI = 32
7006 12:44:11.812853 [0] AVG Duty = 5078%(X100)
7007 12:44:11.812934
7008 12:44:11.816413 CH0 CLK Duty spec in!! Max-Min= 218%
7009 12:44:11.819226 [DutyScan_Calibration_Flow] ====Done====
7010 12:44:11.819307
7011 12:44:11.822812 [DutyScan_Calibration_Flow] k_type=1
7012 12:44:11.839700
7013 12:44:11.839793 ==DQS 0 ==
7014 12:44:11.843154 Final DQS duty delay cell = 0
7015 12:44:11.846423 [0] MAX Duty = 5125%(X100), DQS PI = 24
7016 12:44:11.849634 [0] MIN Duty = 5031%(X100), DQS PI = 56
7017 12:44:11.853421 [0] AVG Duty = 5078%(X100)
7018 12:44:11.853503
7019 12:44:11.853567 ==DQS 1 ==
7020 12:44:11.856369 Final DQS duty delay cell = 0
7021 12:44:11.859611 [0] MAX Duty = 5031%(X100), DQS PI = 2
7022 12:44:11.862815 [0] MIN Duty = 4876%(X100), DQS PI = 18
7023 12:44:11.866333 [0] AVG Duty = 4953%(X100)
7024 12:44:11.866415
7025 12:44:11.869580 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7026 12:44:11.869662
7027 12:44:11.872895 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7028 12:44:11.877081 [DutyScan_Calibration_Flow] ====Done====
7029 12:44:11.877162
7030 12:44:11.879846 [DutyScan_Calibration_Flow] k_type=3
7031 12:44:11.896885
7032 12:44:11.896967 ==DQM 0 ==
7033 12:44:11.900097 Final DQM duty delay cell = 0
7034 12:44:11.903691 [0] MAX Duty = 5187%(X100), DQS PI = 22
7035 12:44:11.907209 [0] MIN Duty = 4907%(X100), DQS PI = 42
7036 12:44:11.910333 [0] AVG Duty = 5047%(X100)
7037 12:44:11.910414
7038 12:44:11.910479 ==DQM 1 ==
7039 12:44:11.914162 Final DQM duty delay cell = 0
7040 12:44:11.916440 [0] MAX Duty = 5031%(X100), DQS PI = 4
7041 12:44:11.920007 [0] MIN Duty = 4782%(X100), DQS PI = 14
7042 12:44:11.923504 [0] AVG Duty = 4906%(X100)
7043 12:44:11.923585
7044 12:44:11.926587 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7045 12:44:11.926669
7046 12:44:11.929715 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7047 12:44:11.933431 [DutyScan_Calibration_Flow] ====Done====
7048 12:44:11.933512
7049 12:44:11.936617 [DutyScan_Calibration_Flow] k_type=2
7050 12:44:11.952787
7051 12:44:11.952869 ==DQ 0 ==
7052 12:44:11.956746 Final DQ duty delay cell = 0
7053 12:44:11.960993 [0] MAX Duty = 5218%(X100), DQS PI = 18
7054 12:44:11.962903 [0] MIN Duty = 4938%(X100), DQS PI = 56
7055 12:44:11.962985 [0] AVG Duty = 5078%(X100)
7056 12:44:11.966769
7057 12:44:11.966850 ==DQ 1 ==
7058 12:44:11.969312 Final DQ duty delay cell = -4
7059 12:44:11.972702 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7060 12:44:11.977269 [-4] MIN Duty = 4844%(X100), DQS PI = 36
7061 12:44:11.979423 [-4] AVG Duty = 4953%(X100)
7062 12:44:11.979505
7063 12:44:11.983027 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7064 12:44:11.983108
7065 12:44:11.986695 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7066 12:44:11.989517 [DutyScan_Calibration_Flow] ====Done====
7067 12:44:11.989599 ==
7068 12:44:11.992863 Dram Type= 6, Freq= 0, CH_1, rank 0
7069 12:44:11.996328 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7070 12:44:11.996410 ==
7071 12:44:11.999853 [Duty_Offset_Calibration]
7072 12:44:11.999934 B0:0 B1:5 CA:-5
7073 12:44:11.999999
7074 12:44:12.002688 [DutyScan_Calibration_Flow] k_type=0
7075 12:44:12.013934
7076 12:44:12.014015 ==CLK 0==
7077 12:44:12.017137 Final CLK duty delay cell = 0
7078 12:44:12.020009 [0] MAX Duty = 5156%(X100), DQS PI = 18
7079 12:44:12.024341 [0] MIN Duty = 4906%(X100), DQS PI = 50
7080 12:44:12.027059 [0] AVG Duty = 5031%(X100)
7081 12:44:12.027141
7082 12:44:12.030743 CH1 CLK Duty spec in!! Max-Min= 250%
7083 12:44:12.033365 [DutyScan_Calibration_Flow] ====Done====
7084 12:44:12.033446
7085 12:44:12.038215 [DutyScan_Calibration_Flow] k_type=1
7086 12:44:12.052577
7087 12:44:12.052685 ==DQS 0 ==
7088 12:44:12.056604 Final DQS duty delay cell = 0
7089 12:44:12.059387 [0] MAX Duty = 5156%(X100), DQS PI = 18
7090 12:44:12.063032 [0] MIN Duty = 4876%(X100), DQS PI = 42
7091 12:44:12.065704 [0] AVG Duty = 5016%(X100)
7092 12:44:12.065785
7093 12:44:12.065849 ==DQS 1 ==
7094 12:44:12.069772 Final DQS duty delay cell = -4
7095 12:44:12.072666 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7096 12:44:12.075797 [-4] MIN Duty = 4844%(X100), DQS PI = 40
7097 12:44:12.079284 [-4] AVG Duty = 4922%(X100)
7098 12:44:12.079366
7099 12:44:12.082684 CH1 DQS 0 Duty spec in!! Max-Min= 280%
7100 12:44:12.082766
7101 12:44:12.085494 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7102 12:44:12.089599 [DutyScan_Calibration_Flow] ====Done====
7103 12:44:12.089681
7104 12:44:12.092255 [DutyScan_Calibration_Flow] k_type=3
7105 12:44:12.108621
7106 12:44:12.108764 ==DQM 0 ==
7107 12:44:12.111604 Final DQM duty delay cell = -4
7108 12:44:12.115119 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7109 12:44:12.118498 [-4] MIN Duty = 4782%(X100), DQS PI = 46
7110 12:44:12.121547 [-4] AVG Duty = 4937%(X100)
7111 12:44:12.121629
7112 12:44:12.121692 ==DQM 1 ==
7113 12:44:12.124652 Final DQM duty delay cell = -4
7114 12:44:12.128544 [-4] MAX Duty = 5062%(X100), DQS PI = 16
7115 12:44:12.131511 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7116 12:44:12.135638 [-4] AVG Duty = 4984%(X100)
7117 12:44:12.135720
7118 12:44:12.139071 CH1 DQM 0 Duty spec in!! Max-Min= 311%
7119 12:44:12.139154
7120 12:44:12.141390 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7121 12:44:12.144998 [DutyScan_Calibration_Flow] ====Done====
7122 12:44:12.145080
7123 12:44:12.147875 [DutyScan_Calibration_Flow] k_type=2
7124 12:44:12.166053
7125 12:44:12.166135 ==DQ 0 ==
7126 12:44:12.169231 Final DQ duty delay cell = 0
7127 12:44:12.172885 [0] MAX Duty = 5093%(X100), DQS PI = 18
7128 12:44:12.175771 [0] MIN Duty = 4938%(X100), DQS PI = 48
7129 12:44:12.175852 [0] AVG Duty = 5015%(X100)
7130 12:44:12.180012
7131 12:44:12.180093 ==DQ 1 ==
7132 12:44:12.182631 Final DQ duty delay cell = 0
7133 12:44:12.186313 [0] MAX Duty = 5062%(X100), DQS PI = 6
7134 12:44:12.189360 [0] MIN Duty = 4907%(X100), DQS PI = 22
7135 12:44:12.189442 [0] AVG Duty = 4984%(X100)
7136 12:44:12.189507
7137 12:44:12.192660 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7138 12:44:12.195695
7139 12:44:12.199419 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7140 12:44:12.202336 [DutyScan_Calibration_Flow] ====Done====
7141 12:44:12.205875 nWR fixed to 30
7142 12:44:12.205980 [ModeRegInit_LP4] CH0 RK0
7143 12:44:12.209106 [ModeRegInit_LP4] CH0 RK1
7144 12:44:12.212719 [ModeRegInit_LP4] CH1 RK0
7145 12:44:12.215676 [ModeRegInit_LP4] CH1 RK1
7146 12:44:12.215757 match AC timing 4
7147 12:44:12.219264 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7148 12:44:12.225385 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7149 12:44:12.229012 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7150 12:44:12.235945 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7151 12:44:12.239018 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7152 12:44:12.239100 [MiockJmeterHQA]
7153 12:44:12.239165
7154 12:44:12.242340 [DramcMiockJmeter] u1RxGatingPI = 0
7155 12:44:12.245954 0 : 4255, 4030
7156 12:44:12.246037 4 : 4368, 4137
7157 12:44:12.249547 8 : 4252, 4027
7158 12:44:12.249629 12 : 4255, 4029
7159 12:44:12.249695 16 : 4363, 4138
7160 12:44:12.251981 20 : 4252, 4027
7161 12:44:12.252064 24 : 4252, 4027
7162 12:44:12.255213 28 : 4253, 4026
7163 12:44:12.255296 32 : 4363, 4138
7164 12:44:12.258595 36 : 4363, 4138
7165 12:44:12.258677 40 : 4253, 4027
7166 12:44:12.261958 44 : 4252, 4027
7167 12:44:12.262040 48 : 4253, 4027
7168 12:44:12.262126 52 : 4253, 4027
7169 12:44:12.265562 56 : 4255, 4030
7170 12:44:12.265645 60 : 4363, 4138
7171 12:44:12.268652 64 : 4250, 4027
7172 12:44:12.268771 68 : 4250, 4027
7173 12:44:12.272568 72 : 4250, 4027
7174 12:44:12.272651 76 : 4253, 4029
7175 12:44:12.275711 80 : 4250, 4027
7176 12:44:12.275793 84 : 4361, 4137
7177 12:44:12.275859 88 : 4360, 4138
7178 12:44:12.278776 92 : 4250, 4027
7179 12:44:12.278858 96 : 4250, 4027
7180 12:44:12.281648 100 : 4250, 2484
7181 12:44:12.281730 104 : 4250, 0
7182 12:44:12.286450 108 : 4250, 0
7183 12:44:12.286532 112 : 4252, 0
7184 12:44:12.286598 116 : 4250, 0
7185 12:44:12.289323 120 : 4251, 0
7186 12:44:12.289406 124 : 4252, 0
7187 12:44:12.289472 128 : 4252, 0
7188 12:44:12.291958 132 : 4252, 0
7189 12:44:12.292040 136 : 4250, 0
7190 12:44:12.295582 140 : 4361, 0
7191 12:44:12.295665 144 : 4361, 0
7192 12:44:12.295731 148 : 4250, 0
7193 12:44:12.298794 152 : 4250, 0
7194 12:44:12.298877 156 : 4363, 0
7195 12:44:12.302044 160 : 4249, 0
7196 12:44:12.302126 164 : 4250, 0
7197 12:44:12.302193 168 : 4250, 0
7198 12:44:12.304848 172 : 4250, 0
7199 12:44:12.304931 176 : 4252, 0
7200 12:44:12.308194 180 : 4250, 0
7201 12:44:12.308284 184 : 4250, 0
7202 12:44:12.308351 188 : 4252, 0
7203 12:44:12.311668 192 : 4361, 0
7204 12:44:12.311751 196 : 4361, 0
7205 12:44:12.315296 200 : 4363, 0
7206 12:44:12.315379 204 : 4250, 0
7207 12:44:12.315444 208 : 4250, 0
7208 12:44:12.318276 212 : 4250, 0
7209 12:44:12.318385 216 : 4250, 0
7210 12:44:12.321816 220 : 4250, 445
7211 12:44:12.321917 224 : 4252, 3981
7212 12:44:12.322009 228 : 4360, 4138
7213 12:44:12.325237 232 : 4361, 4137
7214 12:44:12.325343 236 : 4250, 4027
7215 12:44:12.328259 240 : 4250, 4027
7216 12:44:12.328370 244 : 4363, 4140
7217 12:44:12.331416 248 : 4250, 4027
7218 12:44:12.331525 252 : 4250, 4026
7219 12:44:12.334944 256 : 4250, 4027
7220 12:44:12.335027 260 : 4252, 4029
7221 12:44:12.338384 264 : 4250, 4027
7222 12:44:12.338467 268 : 4250, 4026
7223 12:44:12.341599 272 : 4361, 4138
7224 12:44:12.341709 276 : 4250, 4027
7225 12:44:12.345454 280 : 4251, 4027
7226 12:44:12.345555 284 : 4361, 4137
7227 12:44:12.345646 288 : 4250, 4027
7228 12:44:12.348367 292 : 4250, 4027
7229 12:44:12.348463 296 : 4363, 4140
7230 12:44:12.351505 300 : 4250, 4027
7231 12:44:12.351588 304 : 4250, 4026
7232 12:44:12.355353 308 : 4250, 4027
7233 12:44:12.355436 312 : 4252, 4029
7234 12:44:12.357736 316 : 4251, 4027
7235 12:44:12.357819 320 : 4250, 4027
7236 12:44:12.361288 324 : 4361, 4138
7237 12:44:12.361371 328 : 4250, 4027
7238 12:44:12.365153 332 : 4249, 4027
7239 12:44:12.365236 336 : 4361, 4062
7240 12:44:12.367886 340 : 4250, 2289
7241 12:44:12.367974 344 : 4250, 3
7242 12:44:12.368044
7243 12:44:12.371666 MIOCK jitter meter ch=0
7244 12:44:12.371747
7245 12:44:12.374583 1T = (344-104) = 240 dly cells
7246 12:44:12.377702 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7247 12:44:12.377785 ==
7248 12:44:12.381163 Dram Type= 6, Freq= 0, CH_0, rank 0
7249 12:44:12.387498 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7250 12:44:12.387581 ==
7251 12:44:12.391100 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7252 12:44:12.397947 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7253 12:44:12.400967 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7254 12:44:12.407554 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7255 12:44:12.414272 [CA 0] Center 41 (11~72) winsize 62
7256 12:44:12.417814 [CA 1] Center 41 (11~72) winsize 62
7257 12:44:12.421066 [CA 2] Center 37 (7~67) winsize 61
7258 12:44:12.424978 [CA 3] Center 37 (7~67) winsize 61
7259 12:44:12.427277 [CA 4] Center 35 (5~66) winsize 62
7260 12:44:12.430749 [CA 5] Center 35 (5~65) winsize 61
7261 12:44:12.430831
7262 12:44:12.434245 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7263 12:44:12.434328
7264 12:44:12.437906 [CATrainingPosCal] consider 1 rank data
7265 12:44:12.440963 u2DelayCellTimex100 = 271/100 ps
7266 12:44:12.447594 CA0 delay=41 (11~72),Diff = 6 PI (21 cell)
7267 12:44:12.451496 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7268 12:44:12.454694 CA2 delay=37 (7~67),Diff = 2 PI (7 cell)
7269 12:44:12.458759 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7270 12:44:12.460717 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7271 12:44:12.464300 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7272 12:44:12.464381
7273 12:44:12.467685 CA PerBit enable=1, Macro0, CA PI delay=35
7274 12:44:12.467767
7275 12:44:12.470882 [CBTSetCACLKResult] CA Dly = 35
7276 12:44:12.473962 CS Dly: 11 (0~42)
7277 12:44:12.477063 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7278 12:44:12.481597 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7279 12:44:12.481679 ==
7280 12:44:12.484097 Dram Type= 6, Freq= 0, CH_0, rank 1
7281 12:44:12.491249 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7282 12:44:12.491331 ==
7283 12:44:12.493913 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7284 12:44:12.500967 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7285 12:44:12.503938 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7286 12:44:12.513935 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7287 12:44:12.516994 [CA 0] Center 42 (12~73) winsize 62
7288 12:44:12.520963 [CA 1] Center 42 (12~73) winsize 62
7289 12:44:12.523560 [CA 2] Center 38 (9~68) winsize 60
7290 12:44:12.526920 [CA 3] Center 37 (8~67) winsize 60
7291 12:44:12.530066 [CA 4] Center 36 (6~66) winsize 61
7292 12:44:12.534176 [CA 5] Center 35 (5~66) winsize 62
7293 12:44:12.534257
7294 12:44:12.536683 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7295 12:44:12.536802
7296 12:44:12.540315 [CATrainingPosCal] consider 2 rank data
7297 12:44:12.543380 u2DelayCellTimex100 = 271/100 ps
7298 12:44:12.550391 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7299 12:44:12.553329 CA1 delay=42 (12~72),Diff = 7 PI (25 cell)
7300 12:44:12.556643 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7301 12:44:12.559973 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7302 12:44:12.563580 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7303 12:44:12.566559 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7304 12:44:12.566653
7305 12:44:12.569913 CA PerBit enable=1, Macro0, CA PI delay=35
7306 12:44:12.569983
7307 12:44:12.573246 [CBTSetCACLKResult] CA Dly = 35
7308 12:44:12.577009 CS Dly: 11 (0~42)
7309 12:44:12.579695 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7310 12:44:12.583036 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7311 12:44:12.583109
7312 12:44:12.586622 ----->DramcWriteLeveling(PI) begin...
7313 12:44:12.586689 ==
7314 12:44:12.590372 Dram Type= 6, Freq= 0, CH_0, rank 0
7315 12:44:12.596838 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7316 12:44:12.596911 ==
7317 12:44:12.599490 Write leveling (Byte 0): 30 => 30
7318 12:44:12.603173 Write leveling (Byte 1): 25 => 25
7319 12:44:12.603267 DramcWriteLeveling(PI) end<-----
7320 12:44:12.603356
7321 12:44:12.606171 ==
7322 12:44:12.609996 Dram Type= 6, Freq= 0, CH_0, rank 0
7323 12:44:12.612927 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7324 12:44:12.612997 ==
7325 12:44:12.616745 [Gating] SW mode calibration
7326 12:44:12.622673 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7327 12:44:12.626044 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7328 12:44:12.633122 0 12 0 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
7329 12:44:12.635849 0 12 4 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
7330 12:44:12.639769 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7331 12:44:12.645756 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7332 12:44:12.649210 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7333 12:44:12.652739 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7334 12:44:12.659317 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7335 12:44:12.662759 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7336 12:44:12.665911 0 13 0 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 0)
7337 12:44:12.672478 0 13 4 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
7338 12:44:12.675715 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7339 12:44:12.679320 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7340 12:44:12.685646 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7341 12:44:12.689014 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7342 12:44:12.692193 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7343 12:44:12.698957 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7344 12:44:12.702010 0 14 0 | B1->B0 | 2323 3737 | 0 0 | (0 0) (1 1)
7345 12:44:12.705766 0 14 4 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
7346 12:44:12.712263 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7347 12:44:12.715512 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7348 12:44:12.718527 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7349 12:44:12.726758 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7350 12:44:12.729560 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7351 12:44:12.732998 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7352 12:44:12.739311 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7353 12:44:12.741983 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7354 12:44:12.745461 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7355 12:44:12.752193 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7356 12:44:12.755056 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7357 12:44:12.758959 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7358 12:44:12.765231 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7359 12:44:12.768400 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7360 12:44:12.771831 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7361 12:44:12.778710 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7362 12:44:12.781922 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7363 12:44:12.785294 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7364 12:44:12.792580 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7365 12:44:12.795147 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7366 12:44:12.798019 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7367 12:44:12.804862 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7368 12:44:12.808116 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7369 12:44:12.812077 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7370 12:44:12.816137 Total UI for P1: 0, mck2ui 16
7371 12:44:12.817875 best dqsien dly found for B0: ( 1, 0, 30)
7372 12:44:12.824456 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7373 12:44:12.828063 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7374 12:44:12.831749 Total UI for P1: 0, mck2ui 16
7375 12:44:12.834476 best dqsien dly found for B1: ( 1, 1, 6)
7376 12:44:12.838359 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7377 12:44:12.841195 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7378 12:44:12.841267
7379 12:44:12.844390 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7380 12:44:12.847692 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7381 12:44:12.850968 [Gating] SW calibration Done
7382 12:44:12.851073 ==
7383 12:44:12.854464 Dram Type= 6, Freq= 0, CH_0, rank 0
7384 12:44:12.857959 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7385 12:44:12.858055 ==
7386 12:44:12.861450 RX Vref Scan: 0
7387 12:44:12.861525
7388 12:44:12.864634 RX Vref 0 -> 0, step: 1
7389 12:44:12.864773
7390 12:44:12.864853 RX Delay 0 -> 252, step: 8
7391 12:44:12.870650 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7392 12:44:12.874205 iDelay=192, Bit 1, Center 131 (72 ~ 191) 120
7393 12:44:12.877357 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7394 12:44:12.880923 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7395 12:44:12.884309 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7396 12:44:12.890636 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7397 12:44:12.895045 iDelay=192, Bit 6, Center 135 (80 ~ 191) 112
7398 12:44:12.897675 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7399 12:44:12.900575 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7400 12:44:12.904365 iDelay=192, Bit 9, Center 107 (56 ~ 159) 104
7401 12:44:12.910863 iDelay=192, Bit 10, Center 119 (64 ~ 175) 112
7402 12:44:12.914477 iDelay=192, Bit 11, Center 115 (64 ~ 167) 104
7403 12:44:12.917024 iDelay=192, Bit 12, Center 131 (80 ~ 183) 104
7404 12:44:12.920637 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7405 12:44:12.926927 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7406 12:44:12.930739 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7407 12:44:12.930826 ==
7408 12:44:12.933555 Dram Type= 6, Freq= 0, CH_0, rank 0
7409 12:44:12.937108 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7410 12:44:12.937191 ==
7411 12:44:12.937256 DQS Delay:
7412 12:44:12.940002 DQS0 = 0, DQS1 = 0
7413 12:44:12.940083 DQM Delay:
7414 12:44:12.944554 DQM0 = 129, DQM1 = 123
7415 12:44:12.944636 DQ Delay:
7416 12:44:12.948512 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7417 12:44:12.949869 DQ4 =135, DQ5 =119, DQ6 =135, DQ7 =135
7418 12:44:12.953713 DQ8 =115, DQ9 =107, DQ10 =119, DQ11 =115
7419 12:44:12.960586 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7420 12:44:12.960667
7421 12:44:12.960738
7422 12:44:12.960799 ==
7423 12:44:12.963265 Dram Type= 6, Freq= 0, CH_0, rank 0
7424 12:44:12.966942 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7425 12:44:12.967034 ==
7426 12:44:12.967100
7427 12:44:12.967159
7428 12:44:12.970670 TX Vref Scan disable
7429 12:44:12.970751 == TX Byte 0 ==
7430 12:44:12.976631 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7431 12:44:12.979965 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7432 12:44:12.980047 == TX Byte 1 ==
7433 12:44:12.986747 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7434 12:44:12.990279 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7435 12:44:12.990361 ==
7436 12:44:12.993231 Dram Type= 6, Freq= 0, CH_0, rank 0
7437 12:44:12.996504 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7438 12:44:12.996586 ==
7439 12:44:13.010428
7440 12:44:13.013757 TX Vref early break, caculate TX vref
7441 12:44:13.017476 TX Vref=16, minBit 10, minWin=21, winSum=368
7442 12:44:13.020638 TX Vref=18, minBit 8, minWin=22, winSum=379
7443 12:44:13.023614 TX Vref=20, minBit 7, minWin=23, winSum=384
7444 12:44:13.027354 TX Vref=22, minBit 10, minWin=23, winSum=393
7445 12:44:13.030461 TX Vref=24, minBit 10, minWin=23, winSum=406
7446 12:44:13.037046 TX Vref=26, minBit 7, minWin=25, winSum=413
7447 12:44:13.040387 TX Vref=28, minBit 1, minWin=25, winSum=415
7448 12:44:13.043379 TX Vref=30, minBit 6, minWin=24, winSum=408
7449 12:44:13.046711 TX Vref=32, minBit 8, minWin=23, winSum=400
7450 12:44:13.050301 TX Vref=34, minBit 0, minWin=24, winSum=392
7451 12:44:13.057911 [TxChooseVref] Worse bit 1, Min win 25, Win sum 415, Final Vref 28
7452 12:44:13.057993
7453 12:44:13.060328 Final TX Range 0 Vref 28
7454 12:44:13.060409
7455 12:44:13.060474 ==
7456 12:44:13.063384 Dram Type= 6, Freq= 0, CH_0, rank 0
7457 12:44:13.066560 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7458 12:44:13.066641 ==
7459 12:44:13.066706
7460 12:44:13.066765
7461 12:44:13.070331 TX Vref Scan disable
7462 12:44:13.076344 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7463 12:44:13.076458 == TX Byte 0 ==
7464 12:44:13.080129 u2DelayCellOfst[0]=14 cells (4 PI)
7465 12:44:13.083386 u2DelayCellOfst[1]=18 cells (5 PI)
7466 12:44:13.086331 u2DelayCellOfst[2]=14 cells (4 PI)
7467 12:44:13.090419 u2DelayCellOfst[3]=10 cells (3 PI)
7468 12:44:13.092996 u2DelayCellOfst[4]=10 cells (3 PI)
7469 12:44:13.096424 u2DelayCellOfst[5]=0 cells (0 PI)
7470 12:44:13.099658 u2DelayCellOfst[6]=18 cells (5 PI)
7471 12:44:13.103579 u2DelayCellOfst[7]=18 cells (5 PI)
7472 12:44:13.106536 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7473 12:44:13.109687 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7474 12:44:13.113333 == TX Byte 1 ==
7475 12:44:13.116469 u2DelayCellOfst[8]=3 cells (1 PI)
7476 12:44:13.119300 u2DelayCellOfst[9]=0 cells (0 PI)
7477 12:44:13.122553 u2DelayCellOfst[10]=10 cells (3 PI)
7478 12:44:13.126052 u2DelayCellOfst[11]=3 cells (1 PI)
7479 12:44:13.126128 u2DelayCellOfst[12]=18 cells (5 PI)
7480 12:44:13.129525 u2DelayCellOfst[13]=18 cells (5 PI)
7481 12:44:13.133304 u2DelayCellOfst[14]=18 cells (5 PI)
7482 12:44:13.136388 u2DelayCellOfst[15]=14 cells (4 PI)
7483 12:44:13.143383 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7484 12:44:13.145947 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7485 12:44:13.146044 DramC Write-DBI on
7486 12:44:13.149768 ==
7487 12:44:13.152430 Dram Type= 6, Freq= 0, CH_0, rank 0
7488 12:44:13.155928 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7489 12:44:13.156024 ==
7490 12:44:13.156111
7491 12:44:13.156208
7492 12:44:13.158845 TX Vref Scan disable
7493 12:44:13.158938 == TX Byte 0 ==
7494 12:44:13.165915 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7495 12:44:13.165997 == TX Byte 1 ==
7496 12:44:13.168822 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
7497 12:44:13.172268 DramC Write-DBI off
7498 12:44:13.172362
7499 12:44:13.172459 [DATLAT]
7500 12:44:13.175675 Freq=1600, CH0 RK0
7501 12:44:13.175776
7502 12:44:13.175864 DATLAT Default: 0xf
7503 12:44:13.178866 0, 0xFFFF, sum = 0
7504 12:44:13.178971 1, 0xFFFF, sum = 0
7505 12:44:13.182095 2, 0xFFFF, sum = 0
7506 12:44:13.182165 3, 0xFFFF, sum = 0
7507 12:44:13.185602 4, 0xFFFF, sum = 0
7508 12:44:13.185675 5, 0xFFFF, sum = 0
7509 12:44:13.189034 6, 0xFFFF, sum = 0
7510 12:44:13.192091 7, 0xFFFF, sum = 0
7511 12:44:13.192195 8, 0xFFFF, sum = 0
7512 12:44:13.195542 9, 0xFFFF, sum = 0
7513 12:44:13.195642 10, 0xFFFF, sum = 0
7514 12:44:13.198889 11, 0xFFFF, sum = 0
7515 12:44:13.198994 12, 0xBFF, sum = 0
7516 12:44:13.202190 13, 0x0, sum = 1
7517 12:44:13.202286 14, 0x0, sum = 2
7518 12:44:13.205788 15, 0x0, sum = 3
7519 12:44:13.205871 16, 0x0, sum = 4
7520 12:44:13.205932 best_step = 14
7521 12:44:13.205989
7522 12:44:13.208881 ==
7523 12:44:13.211995 Dram Type= 6, Freq= 0, CH_0, rank 0
7524 12:44:13.215257 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7525 12:44:13.215343 ==
7526 12:44:13.215406 RX Vref Scan: 1
7527 12:44:13.215465
7528 12:44:13.218843 Set Vref Range= 24 -> 127
7529 12:44:13.218937
7530 12:44:13.222004 RX Vref 24 -> 127, step: 1
7531 12:44:13.222097
7532 12:44:13.225782 RX Delay 11 -> 252, step: 4
7533 12:44:13.225879
7534 12:44:13.228329 Set Vref, RX VrefLevel [Byte0]: 24
7535 12:44:13.231549 [Byte1]: 24
7536 12:44:13.231648
7537 12:44:13.235112 Set Vref, RX VrefLevel [Byte0]: 25
7538 12:44:13.238292 [Byte1]: 25
7539 12:44:13.238390
7540 12:44:13.242477 Set Vref, RX VrefLevel [Byte0]: 26
7541 12:44:13.245380 [Byte1]: 26
7542 12:44:13.249125
7543 12:44:13.249195 Set Vref, RX VrefLevel [Byte0]: 27
7544 12:44:13.253086 [Byte1]: 27
7545 12:44:13.256152
7546 12:44:13.256251 Set Vref, RX VrefLevel [Byte0]: 28
7547 12:44:13.259878 [Byte1]: 28
7548 12:44:13.263874
7549 12:44:13.263956 Set Vref, RX VrefLevel [Byte0]: 29
7550 12:44:13.268038 [Byte1]: 29
7551 12:44:13.272149
7552 12:44:13.272219 Set Vref, RX VrefLevel [Byte0]: 30
7553 12:44:13.275310 [Byte1]: 30
7554 12:44:13.279476
7555 12:44:13.279575 Set Vref, RX VrefLevel [Byte0]: 31
7556 12:44:13.282637 [Byte1]: 31
7557 12:44:13.287302
7558 12:44:13.287427 Set Vref, RX VrefLevel [Byte0]: 32
7559 12:44:13.290356 [Byte1]: 32
7560 12:44:13.294401
7561 12:44:13.294472 Set Vref, RX VrefLevel [Byte0]: 33
7562 12:44:13.298871 [Byte1]: 33
7563 12:44:13.301786
7564 12:44:13.301859 Set Vref, RX VrefLevel [Byte0]: 34
7565 12:44:13.305786 [Byte1]: 34
7566 12:44:13.309953
7567 12:44:13.310026 Set Vref, RX VrefLevel [Byte0]: 35
7568 12:44:13.313291 [Byte1]: 35
7569 12:44:13.317139
7570 12:44:13.317236 Set Vref, RX VrefLevel [Byte0]: 36
7571 12:44:13.320927 [Byte1]: 36
7572 12:44:13.325422
7573 12:44:13.325495 Set Vref, RX VrefLevel [Byte0]: 37
7574 12:44:13.328476 [Byte1]: 37
7575 12:44:13.332662
7576 12:44:13.332769 Set Vref, RX VrefLevel [Byte0]: 38
7577 12:44:13.336549 [Byte1]: 38
7578 12:44:13.340643
7579 12:44:13.340763 Set Vref, RX VrefLevel [Byte0]: 39
7580 12:44:13.343727 [Byte1]: 39
7581 12:44:13.347854
7582 12:44:13.347936 Set Vref, RX VrefLevel [Byte0]: 40
7583 12:44:13.351866 [Byte1]: 40
7584 12:44:13.356862
7585 12:44:13.356943 Set Vref, RX VrefLevel [Byte0]: 41
7586 12:44:13.358968 [Byte1]: 41
7587 12:44:13.363428
7588 12:44:13.363510 Set Vref, RX VrefLevel [Byte0]: 42
7589 12:44:13.367248 [Byte1]: 42
7590 12:44:13.370830
7591 12:44:13.370911 Set Vref, RX VrefLevel [Byte0]: 43
7592 12:44:13.374385 [Byte1]: 43
7593 12:44:13.378260
7594 12:44:13.378342 Set Vref, RX VrefLevel [Byte0]: 44
7595 12:44:13.381448 [Byte1]: 44
7596 12:44:13.387217
7597 12:44:13.387299 Set Vref, RX VrefLevel [Byte0]: 45
7598 12:44:13.389016 [Byte1]: 45
7599 12:44:13.393753
7600 12:44:13.393834 Set Vref, RX VrefLevel [Byte0]: 46
7601 12:44:13.396851 [Byte1]: 46
7602 12:44:13.400875
7603 12:44:13.400956 Set Vref, RX VrefLevel [Byte0]: 47
7604 12:44:13.404106 [Byte1]: 47
7605 12:44:13.408838
7606 12:44:13.408918 Set Vref, RX VrefLevel [Byte0]: 48
7607 12:44:13.412332 [Byte1]: 48
7608 12:44:13.416537
7609 12:44:13.416619 Set Vref, RX VrefLevel [Byte0]: 49
7610 12:44:13.420025 [Byte1]: 49
7611 12:44:13.424335
7612 12:44:13.424417 Set Vref, RX VrefLevel [Byte0]: 50
7613 12:44:13.427196 [Byte1]: 50
7614 12:44:13.431513
7615 12:44:13.431594 Set Vref, RX VrefLevel [Byte0]: 51
7616 12:44:13.435597 [Byte1]: 51
7617 12:44:13.439104
7618 12:44:13.439187 Set Vref, RX VrefLevel [Byte0]: 52
7619 12:44:13.442193 [Byte1]: 52
7620 12:44:13.447691
7621 12:44:13.447772 Set Vref, RX VrefLevel [Byte0]: 53
7622 12:44:13.450915 [Byte1]: 53
7623 12:44:13.454255
7624 12:44:13.454337 Set Vref, RX VrefLevel [Byte0]: 54
7625 12:44:13.457709 [Byte1]: 54
7626 12:44:13.461930
7627 12:44:13.462011 Set Vref, RX VrefLevel [Byte0]: 55
7628 12:44:13.465589 [Byte1]: 55
7629 12:44:13.470595
7630 12:44:13.470677 Set Vref, RX VrefLevel [Byte0]: 56
7631 12:44:13.472919 [Byte1]: 56
7632 12:44:13.477403
7633 12:44:13.477484 Set Vref, RX VrefLevel [Byte0]: 57
7634 12:44:13.481005 [Byte1]: 57
7635 12:44:13.485130
7636 12:44:13.485212 Set Vref, RX VrefLevel [Byte0]: 58
7637 12:44:13.488203 [Byte1]: 58
7638 12:44:13.492210
7639 12:44:13.492291 Set Vref, RX VrefLevel [Byte0]: 59
7640 12:44:13.495748 [Byte1]: 59
7641 12:44:13.500354
7642 12:44:13.500435 Set Vref, RX VrefLevel [Byte0]: 60
7643 12:44:13.503882 [Byte1]: 60
7644 12:44:13.507703
7645 12:44:13.507785 Set Vref, RX VrefLevel [Byte0]: 61
7646 12:44:13.511394 [Byte1]: 61
7647 12:44:13.515394
7648 12:44:13.515476 Set Vref, RX VrefLevel [Byte0]: 62
7649 12:44:13.518330 [Byte1]: 62
7650 12:44:13.522616
7651 12:44:13.522698 Set Vref, RX VrefLevel [Byte0]: 63
7652 12:44:13.526610 [Byte1]: 63
7653 12:44:13.531245
7654 12:44:13.531328 Set Vref, RX VrefLevel [Byte0]: 64
7655 12:44:13.533971 [Byte1]: 64
7656 12:44:13.538235
7657 12:44:13.538316 Set Vref, RX VrefLevel [Byte0]: 65
7658 12:44:13.541672 [Byte1]: 65
7659 12:44:13.545777
7660 12:44:13.545859 Set Vref, RX VrefLevel [Byte0]: 66
7661 12:44:13.549140 [Byte1]: 66
7662 12:44:13.553976
7663 12:44:13.554057 Set Vref, RX VrefLevel [Byte0]: 67
7664 12:44:13.556898 [Byte1]: 67
7665 12:44:13.561022
7666 12:44:13.561104 Set Vref, RX VrefLevel [Byte0]: 68
7667 12:44:13.564827 [Byte1]: 68
7668 12:44:13.568779
7669 12:44:13.568861 Set Vref, RX VrefLevel [Byte0]: 69
7670 12:44:13.571513 [Byte1]: 69
7671 12:44:13.576317
7672 12:44:13.576399 Set Vref, RX VrefLevel [Byte0]: 70
7673 12:44:13.579484 [Byte1]: 70
7674 12:44:13.583628
7675 12:44:13.583709 Set Vref, RX VrefLevel [Byte0]: 71
7676 12:44:13.587744 [Byte1]: 71
7677 12:44:13.591446
7678 12:44:13.591527 Set Vref, RX VrefLevel [Byte0]: 72
7679 12:44:13.594503 [Byte1]: 72
7680 12:44:13.598921
7681 12:44:13.599002 Set Vref, RX VrefLevel [Byte0]: 73
7682 12:44:13.602455 [Byte1]: 73
7683 12:44:13.606535
7684 12:44:13.606642 Set Vref, RX VrefLevel [Byte0]: 74
7685 12:44:13.609901 [Byte1]: 74
7686 12:44:13.614339
7687 12:44:13.614421 Final RX Vref Byte 0 = 54 to rank0
7688 12:44:13.617599 Final RX Vref Byte 1 = 56 to rank0
7689 12:44:13.620922 Final RX Vref Byte 0 = 54 to rank1
7690 12:44:13.624557 Final RX Vref Byte 1 = 56 to rank1==
7691 12:44:13.627388 Dram Type= 6, Freq= 0, CH_0, rank 0
7692 12:44:13.633828 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7693 12:44:13.633933 ==
7694 12:44:13.634026 DQS Delay:
7695 12:44:13.637547 DQS0 = 0, DQS1 = 0
7696 12:44:13.637643 DQM Delay:
7697 12:44:13.637731 DQM0 = 126, DQM1 = 121
7698 12:44:13.641125 DQ Delay:
7699 12:44:13.644304 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7700 12:44:13.647211 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7701 12:44:13.650673 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7702 12:44:13.654311 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7703 12:44:13.654409
7704 12:44:13.654502
7705 12:44:13.654588
7706 12:44:13.658021 [DramC_TX_OE_Calibration] TA2
7707 12:44:13.660819 Original DQ_B0 (3 6) =30, OEN = 27
7708 12:44:13.663960 Original DQ_B1 (3 6) =30, OEN = 27
7709 12:44:13.667126 24, 0x0, End_B0=24 End_B1=24
7710 12:44:13.667194 25, 0x0, End_B0=25 End_B1=25
7711 12:44:13.670806 26, 0x0, End_B0=26 End_B1=26
7712 12:44:13.674123 27, 0x0, End_B0=27 End_B1=27
7713 12:44:13.676842 28, 0x0, End_B0=28 End_B1=28
7714 12:44:13.680695 29, 0x0, End_B0=29 End_B1=29
7715 12:44:13.680799 30, 0x0, End_B0=30 End_B1=30
7716 12:44:13.683439 31, 0x4141, End_B0=30 End_B1=30
7717 12:44:13.687313 Byte0 end_step=30 best_step=27
7718 12:44:13.690999 Byte1 end_step=30 best_step=27
7719 12:44:13.693644 Byte0 TX OE(2T, 0.5T) = (3, 3)
7720 12:44:13.697012 Byte1 TX OE(2T, 0.5T) = (3, 3)
7721 12:44:13.697096
7722 12:44:13.697158
7723 12:44:13.704089 [DQSOSCAuto] RK0, (LSB)MR18= 0x1818, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
7724 12:44:13.707428 CH0 RK0: MR19=303, MR18=1818
7725 12:44:13.714959 CH0_RK0: MR19=0x303, MR18=0x1818, DQSOSC=397, MR23=63, INC=23, DEC=15
7726 12:44:13.715060
7727 12:44:13.717447 ----->DramcWriteLeveling(PI) begin...
7728 12:44:13.717519 ==
7729 12:44:13.720867 Dram Type= 6, Freq= 0, CH_0, rank 1
7730 12:44:13.723486 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7731 12:44:13.723588 ==
7732 12:44:13.727164 Write leveling (Byte 0): 29 => 29
7733 12:44:13.730151 Write leveling (Byte 1): 29 => 29
7734 12:44:13.733451 DramcWriteLeveling(PI) end<-----
7735 12:44:13.733524
7736 12:44:13.733591 ==
7737 12:44:13.736563 Dram Type= 6, Freq= 0, CH_0, rank 1
7738 12:44:13.740378 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7739 12:44:13.740472 ==
7740 12:44:13.743190 [Gating] SW mode calibration
7741 12:44:13.750091 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7742 12:44:13.756388 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7743 12:44:13.760112 0 12 0 | B1->B0 | 2323 302f | 0 1 | (0 0) (1 1)
7744 12:44:13.766126 0 12 4 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7745 12:44:13.769402 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7746 12:44:13.772843 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7747 12:44:13.779476 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7748 12:44:13.782733 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7749 12:44:13.786178 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7750 12:44:13.793033 0 12 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7751 12:44:13.796018 0 13 0 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
7752 12:44:13.799149 0 13 4 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
7753 12:44:13.806349 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7754 12:44:13.809570 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7755 12:44:13.812996 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7756 12:44:13.819293 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7757 12:44:13.822653 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7758 12:44:13.826623 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7759 12:44:13.833075 0 14 0 | B1->B0 | 2323 4545 | 0 1 | (0 0) (0 0)
7760 12:44:13.835640 0 14 4 | B1->B0 | 3838 4646 | 0 0 | (1 1) (0 0)
7761 12:44:13.839684 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7762 12:44:13.846438 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7763 12:44:13.849262 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7764 12:44:13.852977 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7765 12:44:13.859131 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7766 12:44:13.862404 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7767 12:44:13.865830 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7768 12:44:13.869428 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7769 12:44:13.875949 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7770 12:44:13.878864 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7771 12:44:13.882652 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7772 12:44:13.888749 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7773 12:44:13.892417 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7774 12:44:13.895635 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7775 12:44:13.901796 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7776 12:44:13.905150 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7777 12:44:13.909458 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7778 12:44:13.915184 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7779 12:44:13.918584 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7780 12:44:13.922666 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7781 12:44:13.928675 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7782 12:44:13.932440 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7783 12:44:13.935500 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7784 12:44:13.941464 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7785 12:44:13.945902 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7786 12:44:13.949254 Total UI for P1: 0, mck2ui 16
7787 12:44:13.951911 best dqsien dly found for B0: ( 1, 1, 0)
7788 12:44:13.955223 Total UI for P1: 0, mck2ui 16
7789 12:44:13.958239 best dqsien dly found for B1: ( 1, 1, 2)
7790 12:44:13.961814 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7791 12:44:13.965068 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7792 12:44:13.965135
7793 12:44:13.968303 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7794 12:44:13.972399 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7795 12:44:13.975250 [Gating] SW calibration Done
7796 12:44:13.975316 ==
7797 12:44:13.978496 Dram Type= 6, Freq= 0, CH_0, rank 1
7798 12:44:13.981766 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7799 12:44:13.985195 ==
7800 12:44:13.985322 RX Vref Scan: 0
7801 12:44:13.985398
7802 12:44:13.988631 RX Vref 0 -> 0, step: 1
7803 12:44:13.988800
7804 12:44:13.988882 RX Delay 0 -> 252, step: 8
7805 12:44:13.995293 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7806 12:44:13.998952 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7807 12:44:14.001777 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7808 12:44:14.005178 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7809 12:44:14.008466 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7810 12:44:14.014744 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7811 12:44:14.018529 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7812 12:44:14.021712 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7813 12:44:14.024640 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7814 12:44:14.028835 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7815 12:44:14.035114 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7816 12:44:14.038250 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7817 12:44:14.042398 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7818 12:44:14.044696 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7819 12:44:14.051453 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7820 12:44:14.054917 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7821 12:44:14.055476 ==
7822 12:44:14.058494 Dram Type= 6, Freq= 0, CH_0, rank 1
7823 12:44:14.061725 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7824 12:44:14.062190 ==
7825 12:44:14.065193 DQS Delay:
7826 12:44:14.065719 DQS0 = 0, DQS1 = 0
7827 12:44:14.066088 DQM Delay:
7828 12:44:14.069002 DQM0 = 131, DQM1 = 125
7829 12:44:14.069461 DQ Delay:
7830 12:44:14.071572 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =127
7831 12:44:14.074477 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7832 12:44:14.078184 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7833 12:44:14.084773 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
7834 12:44:14.085335
7835 12:44:14.085885
7836 12:44:14.086410 ==
7837 12:44:14.087971 Dram Type= 6, Freq= 0, CH_0, rank 1
7838 12:44:14.092513 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7839 12:44:14.093117 ==
7840 12:44:14.093487
7841 12:44:14.093829
7842 12:44:14.094565 TX Vref Scan disable
7843 12:44:14.095082 == TX Byte 0 ==
7844 12:44:14.101335 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7845 12:44:14.104691 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7846 12:44:14.105285 == TX Byte 1 ==
7847 12:44:14.110758 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7848 12:44:14.114476 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7849 12:44:14.114951 ==
7850 12:44:14.117403 Dram Type= 6, Freq= 0, CH_0, rank 1
7851 12:44:14.122176 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7852 12:44:14.122740 ==
7853 12:44:14.134737
7854 12:44:14.138441 TX Vref early break, caculate TX vref
7855 12:44:14.142311 TX Vref=16, minBit 9, minWin=22, winSum=381
7856 12:44:14.144603 TX Vref=18, minBit 1, minWin=23, winSum=388
7857 12:44:14.148137 TX Vref=20, minBit 1, minWin=23, winSum=399
7858 12:44:14.151611 TX Vref=22, minBit 1, minWin=24, winSum=406
7859 12:44:14.154727 TX Vref=24, minBit 1, minWin=24, winSum=409
7860 12:44:14.161555 TX Vref=26, minBit 0, minWin=25, winSum=417
7861 12:44:14.165422 TX Vref=28, minBit 1, minWin=25, winSum=423
7862 12:44:14.168025 TX Vref=30, minBit 1, minWin=25, winSum=419
7863 12:44:14.171097 TX Vref=32, minBit 8, minWin=23, winSum=410
7864 12:44:14.174922 TX Vref=34, minBit 8, minWin=23, winSum=397
7865 12:44:14.181567 [TxChooseVref] Worse bit 1, Min win 25, Win sum 423, Final Vref 28
7866 12:44:14.182128
7867 12:44:14.184474 Final TX Range 0 Vref 28
7868 12:44:14.185070
7869 12:44:14.185439 ==
7870 12:44:14.187910 Dram Type= 6, Freq= 0, CH_0, rank 1
7871 12:44:14.191370 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7872 12:44:14.191961 ==
7873 12:44:14.192330
7874 12:44:14.192668
7875 12:44:14.194384 TX Vref Scan disable
7876 12:44:14.201669 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7877 12:44:14.202224 == TX Byte 0 ==
7878 12:44:14.204885 u2DelayCellOfst[0]=14 cells (4 PI)
7879 12:44:14.207585 u2DelayCellOfst[1]=18 cells (5 PI)
7880 12:44:14.211299 u2DelayCellOfst[2]=10 cells (3 PI)
7881 12:44:14.214489 u2DelayCellOfst[3]=14 cells (4 PI)
7882 12:44:14.217572 u2DelayCellOfst[4]=7 cells (2 PI)
7883 12:44:14.220958 u2DelayCellOfst[5]=0 cells (0 PI)
7884 12:44:14.224351 u2DelayCellOfst[6]=18 cells (5 PI)
7885 12:44:14.227347 u2DelayCellOfst[7]=18 cells (5 PI)
7886 12:44:14.230428 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7887 12:44:14.234806 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7888 12:44:14.237518 == TX Byte 1 ==
7889 12:44:14.240884 u2DelayCellOfst[8]=3 cells (1 PI)
7890 12:44:14.241359 u2DelayCellOfst[9]=0 cells (0 PI)
7891 12:44:14.244135 u2DelayCellOfst[10]=10 cells (3 PI)
7892 12:44:14.248190 u2DelayCellOfst[11]=7 cells (2 PI)
7893 12:44:14.251337 u2DelayCellOfst[12]=14 cells (4 PI)
7894 12:44:14.255284 u2DelayCellOfst[13]=14 cells (4 PI)
7895 12:44:14.258062 u2DelayCellOfst[14]=18 cells (5 PI)
7896 12:44:14.261554 u2DelayCellOfst[15]=14 cells (4 PI)
7897 12:44:14.264767 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7898 12:44:14.270609 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7899 12:44:14.271151 DramC Write-DBI on
7900 12:44:14.271517 ==
7901 12:44:14.273605 Dram Type= 6, Freq= 0, CH_0, rank 1
7902 12:44:14.280400 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7903 12:44:14.280990 ==
7904 12:44:14.281360
7905 12:44:14.281701
7906 12:44:14.282028 TX Vref Scan disable
7907 12:44:14.284298 == TX Byte 0 ==
7908 12:44:14.287504 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7909 12:44:14.291109 == TX Byte 1 ==
7910 12:44:14.294042 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7911 12:44:14.297878 DramC Write-DBI off
7912 12:44:14.298427
7913 12:44:14.298794 [DATLAT]
7914 12:44:14.299135 Freq=1600, CH0 RK1
7915 12:44:14.299460
7916 12:44:14.300549 DATLAT Default: 0xe
7917 12:44:14.303786 0, 0xFFFF, sum = 0
7918 12:44:14.304249 1, 0xFFFF, sum = 0
7919 12:44:14.307877 2, 0xFFFF, sum = 0
7920 12:44:14.308344 3, 0xFFFF, sum = 0
7921 12:44:14.310727 4, 0xFFFF, sum = 0
7922 12:44:14.311196 5, 0xFFFF, sum = 0
7923 12:44:14.314011 6, 0xFFFF, sum = 0
7924 12:44:14.314477 7, 0xFFFF, sum = 0
7925 12:44:14.317102 8, 0xFFFF, sum = 0
7926 12:44:14.317569 9, 0xFFFF, sum = 0
7927 12:44:14.320259 10, 0xFFFF, sum = 0
7928 12:44:14.320758 11, 0xFFFF, sum = 0
7929 12:44:14.323399 12, 0x8FFF, sum = 0
7930 12:44:14.323865 13, 0x0, sum = 1
7931 12:44:14.327285 14, 0x0, sum = 2
7932 12:44:14.327752 15, 0x0, sum = 3
7933 12:44:14.330552 16, 0x0, sum = 4
7934 12:44:14.331018 best_step = 14
7935 12:44:14.331378
7936 12:44:14.331719 ==
7937 12:44:14.333306 Dram Type= 6, Freq= 0, CH_0, rank 1
7938 12:44:14.340853 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7939 12:44:14.341409 ==
7940 12:44:14.341780 RX Vref Scan: 0
7941 12:44:14.342123
7942 12:44:14.344254 RX Vref 0 -> 0, step: 1
7943 12:44:14.344756
7944 12:44:14.347004 RX Delay 11 -> 252, step: 4
7945 12:44:14.350266 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7946 12:44:14.353526 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
7947 12:44:14.357162 iDelay=195, Bit 2, Center 128 (75 ~ 182) 108
7948 12:44:14.363815 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7949 12:44:14.366428 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7950 12:44:14.370263 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7951 12:44:14.373599 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7952 12:44:14.376331 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7953 12:44:14.383738 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7954 12:44:14.386630 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7955 12:44:14.390499 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7956 12:44:14.392899 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7957 12:44:14.400275 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7958 12:44:14.402937 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
7959 12:44:14.406874 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
7960 12:44:14.410023 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
7961 12:44:14.410483 ==
7962 12:44:14.412789 Dram Type= 6, Freq= 0, CH_0, rank 1
7963 12:44:14.419660 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7964 12:44:14.420220 ==
7965 12:44:14.420646 DQS Delay:
7966 12:44:14.421052 DQS0 = 0, DQS1 = 0
7967 12:44:14.422613 DQM Delay:
7968 12:44:14.423072 DQM0 = 129, DQM1 = 120
7969 12:44:14.426032 DQ Delay:
7970 12:44:14.429193 DQ0 =124, DQ1 =130, DQ2 =128, DQ3 =124
7971 12:44:14.432305 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
7972 12:44:14.436015 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7973 12:44:14.439715 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =132
7974 12:44:14.440283
7975 12:44:14.440647
7976 12:44:14.441040
7977 12:44:14.442531 [DramC_TX_OE_Calibration] TA2
7978 12:44:14.445560 Original DQ_B0 (3 6) =30, OEN = 27
7979 12:44:14.449311 Original DQ_B1 (3 6) =30, OEN = 27
7980 12:44:14.452897 24, 0x0, End_B0=24 End_B1=24
7981 12:44:14.453457 25, 0x0, End_B0=25 End_B1=25
7982 12:44:14.455554 26, 0x0, End_B0=26 End_B1=26
7983 12:44:14.459040 27, 0x0, End_B0=27 End_B1=27
7984 12:44:14.462529 28, 0x0, End_B0=28 End_B1=28
7985 12:44:14.466182 29, 0x0, End_B0=29 End_B1=29
7986 12:44:14.466739 30, 0x0, End_B0=30 End_B1=30
7987 12:44:14.469618 31, 0x4141, End_B0=30 End_B1=30
7988 12:44:14.472354 Byte0 end_step=30 best_step=27
7989 12:44:14.475596 Byte1 end_step=30 best_step=27
7990 12:44:14.478971 Byte0 TX OE(2T, 0.5T) = (3, 3)
7991 12:44:14.482708 Byte1 TX OE(2T, 0.5T) = (3, 3)
7992 12:44:14.483172
7993 12:44:14.483537
7994 12:44:14.488376 [DQSOSCAuto] RK1, (LSB)MR18= 0x2020, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
7995 12:44:14.491865 CH0 RK1: MR19=303, MR18=2020
7996 12:44:14.498689 CH0_RK1: MR19=0x303, MR18=0x2020, DQSOSC=393, MR23=63, INC=23, DEC=15
7997 12:44:14.503096 [RxdqsGatingPostProcess] freq 1600
7998 12:44:14.505424 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7999 12:44:14.508544 Pre-setting of DQS Precalculation
8000 12:44:14.515358 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8001 12:44:14.515996 ==
8002 12:44:14.519097 Dram Type= 6, Freq= 0, CH_1, rank 0
8003 12:44:14.522301 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8004 12:44:14.522859 ==
8005 12:44:14.528343 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8006 12:44:14.531612 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8007 12:44:14.535018 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8008 12:44:14.542034 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8009 12:44:14.550185 [CA 0] Center 41 (11~71) winsize 61
8010 12:44:14.553433 [CA 1] Center 41 (10~72) winsize 63
8011 12:44:14.557048 [CA 2] Center 37 (7~67) winsize 61
8012 12:44:14.560184 [CA 3] Center 36 (7~66) winsize 60
8013 12:44:14.563796 [CA 4] Center 34 (4~64) winsize 61
8014 12:44:14.567165 [CA 5] Center 34 (5~64) winsize 60
8015 12:44:14.567730
8016 12:44:14.570096 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8017 12:44:14.570597
8018 12:44:14.573135 [CATrainingPosCal] consider 1 rank data
8019 12:44:14.576688 u2DelayCellTimex100 = 271/100 ps
8020 12:44:14.585161 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
8021 12:44:14.586184 CA1 delay=41 (10~72),Diff = 7 PI (25 cell)
8022 12:44:14.589937 CA2 delay=37 (7~67),Diff = 3 PI (10 cell)
8023 12:44:14.593404 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
8024 12:44:14.596539 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8025 12:44:14.599428 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8026 12:44:14.599892
8027 12:44:14.603217 CA PerBit enable=1, Macro0, CA PI delay=34
8028 12:44:14.603763
8029 12:44:14.606597 [CBTSetCACLKResult] CA Dly = 34
8030 12:44:14.610153 CS Dly: 8 (0~39)
8031 12:44:14.614261 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8032 12:44:14.616428 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8033 12:44:14.617012 ==
8034 12:44:14.619558 Dram Type= 6, Freq= 0, CH_1, rank 1
8035 12:44:14.626252 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8036 12:44:14.626797 ==
8037 12:44:14.629709 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8038 12:44:14.633036 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8039 12:44:14.639599 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8040 12:44:14.646525 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8041 12:44:14.653355 [CA 0] Center 41 (11~71) winsize 61
8042 12:44:14.656328 [CA 1] Center 40 (10~71) winsize 62
8043 12:44:14.659592 [CA 2] Center 36 (7~66) winsize 60
8044 12:44:14.662951 [CA 3] Center 36 (7~65) winsize 59
8045 12:44:14.666214 [CA 4] Center 34 (5~64) winsize 60
8046 12:44:14.670396 [CA 5] Center 34 (4~64) winsize 61
8047 12:44:14.670954
8048 12:44:14.672663 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8049 12:44:14.673153
8050 12:44:14.676246 [CATrainingPosCal] consider 2 rank data
8051 12:44:14.679045 u2DelayCellTimex100 = 271/100 ps
8052 12:44:14.682624 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
8053 12:44:14.689279 CA1 delay=40 (10~71),Diff = 6 PI (21 cell)
8054 12:44:14.692880 CA2 delay=36 (7~66),Diff = 2 PI (7 cell)
8055 12:44:14.695603 CA3 delay=36 (7~65),Diff = 2 PI (7 cell)
8056 12:44:14.699253 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
8057 12:44:14.702478 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8058 12:44:14.703040
8059 12:44:14.705483 CA PerBit enable=1, Macro0, CA PI delay=34
8060 12:44:14.705941
8061 12:44:14.709021 [CBTSetCACLKResult] CA Dly = 34
8062 12:44:14.711999 CS Dly: 9 (0~41)
8063 12:44:14.715389 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8064 12:44:14.718695 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8065 12:44:14.719250
8066 12:44:14.722550 ----->DramcWriteLeveling(PI) begin...
8067 12:44:14.723112 ==
8068 12:44:14.725319 Dram Type= 6, Freq= 0, CH_1, rank 0
8069 12:44:14.732668 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8070 12:44:14.733272 ==
8071 12:44:14.735187 Write leveling (Byte 0): 21 => 21
8072 12:44:14.735648 Write leveling (Byte 1): 22 => 22
8073 12:44:14.739721 DramcWriteLeveling(PI) end<-----
8074 12:44:14.740279
8075 12:44:14.742560 ==
8076 12:44:14.745256 Dram Type= 6, Freq= 0, CH_1, rank 0
8077 12:44:14.748673 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8078 12:44:14.749269 ==
8079 12:44:14.751758 [Gating] SW mode calibration
8080 12:44:14.758320 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8081 12:44:14.761402 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8082 12:44:14.768328 0 12 0 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
8083 12:44:14.771792 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8084 12:44:14.775040 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8085 12:44:14.783186 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8086 12:44:14.785241 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8087 12:44:14.788335 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8088 12:44:14.795162 0 12 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8089 12:44:14.798706 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8090 12:44:14.802004 0 13 0 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
8091 12:44:14.808118 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8092 12:44:14.811171 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8093 12:44:14.814822 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8094 12:44:14.821188 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8095 12:44:14.824938 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8096 12:44:14.828159 0 13 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8097 12:44:14.834361 0 13 28 | B1->B0 | 2323 3d3d | 0 1 | (0 0) (0 0)
8098 12:44:14.838019 0 14 0 | B1->B0 | 2d2c 4646 | 1 0 | (0 0) (0 0)
8099 12:44:14.841117 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8100 12:44:14.847898 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8101 12:44:14.850991 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8102 12:44:14.854754 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8103 12:44:14.861176 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8104 12:44:14.864973 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8105 12:44:14.867971 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8106 12:44:14.874341 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8107 12:44:14.878026 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8108 12:44:14.881037 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 12:44:14.887989 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 12:44:14.890866 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 12:44:14.895073 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 12:44:14.900637 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 12:44:14.904486 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8114 12:44:14.907347 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8115 12:44:14.914645 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 12:44:14.917603 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8117 12:44:14.921585 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8118 12:44:14.927297 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8119 12:44:14.930295 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8120 12:44:14.933788 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8121 12:44:14.940385 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8122 12:44:14.944764 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8123 12:44:14.947071 Total UI for P1: 0, mck2ui 16
8124 12:44:14.950577 best dqsien dly found for B0: ( 1, 0, 28)
8125 12:44:14.953896 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8126 12:44:14.957201 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8127 12:44:14.960330 Total UI for P1: 0, mck2ui 16
8128 12:44:14.963823 best dqsien dly found for B1: ( 1, 1, 2)
8129 12:44:14.967015 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
8130 12:44:14.973434 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8131 12:44:14.974171
8132 12:44:14.977213 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
8133 12:44:14.980764 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8134 12:44:14.983237 [Gating] SW calibration Done
8135 12:44:14.983694 ==
8136 12:44:14.986768 Dram Type= 6, Freq= 0, CH_1, rank 0
8137 12:44:14.990162 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8138 12:44:14.990721 ==
8139 12:44:14.991086 RX Vref Scan: 0
8140 12:44:14.993478
8141 12:44:14.993936 RX Vref 0 -> 0, step: 1
8142 12:44:14.994302
8143 12:44:14.997283 RX Delay 0 -> 252, step: 8
8144 12:44:14.999808 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8145 12:44:15.003009 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8146 12:44:15.009439 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8147 12:44:15.012932 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8148 12:44:15.016242 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8149 12:44:15.020208 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8150 12:44:15.023336 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8151 12:44:15.029288 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8152 12:44:15.032990 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8153 12:44:15.035900 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8154 12:44:15.040112 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8155 12:44:15.043320 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8156 12:44:15.049621 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8157 12:44:15.052670 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8158 12:44:15.056485 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8159 12:44:15.059253 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8160 12:44:15.059815 ==
8161 12:44:15.063255 Dram Type= 6, Freq= 0, CH_1, rank 0
8162 12:44:15.069139 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8163 12:44:15.069693 ==
8164 12:44:15.070205 DQS Delay:
8165 12:44:15.072489 DQS0 = 0, DQS1 = 0
8166 12:44:15.072999 DQM Delay:
8167 12:44:15.076427 DQM0 = 129, DQM1 = 125
8168 12:44:15.077016 DQ Delay:
8169 12:44:15.079306 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8170 12:44:15.083386 DQ4 =127, DQ5 =143, DQ6 =135, DQ7 =127
8171 12:44:15.086232 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8172 12:44:15.089852 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8173 12:44:15.090407
8174 12:44:15.090774
8175 12:44:15.091111 ==
8176 12:44:15.092785 Dram Type= 6, Freq= 0, CH_1, rank 0
8177 12:44:15.099355 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8178 12:44:15.099909 ==
8179 12:44:15.100277
8180 12:44:15.100615
8181 12:44:15.100976 TX Vref Scan disable
8182 12:44:15.102657 == TX Byte 0 ==
8183 12:44:15.105629 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8184 12:44:15.109097 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8185 12:44:15.112566 == TX Byte 1 ==
8186 12:44:15.117851 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8187 12:44:15.122354 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8188 12:44:15.122916 ==
8189 12:44:15.125965 Dram Type= 6, Freq= 0, CH_1, rank 0
8190 12:44:15.128672 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8191 12:44:15.129174 ==
8192 12:44:15.141481
8193 12:44:15.144118 TX Vref early break, caculate TX vref
8194 12:44:15.147921 TX Vref=16, minBit 3, minWin=21, winSum=364
8195 12:44:15.151367 TX Vref=18, minBit 4, minWin=22, winSum=377
8196 12:44:15.155300 TX Vref=20, minBit 3, minWin=22, winSum=387
8197 12:44:15.158042 TX Vref=22, minBit 0, minWin=23, winSum=392
8198 12:44:15.161444 TX Vref=24, minBit 3, minWin=23, winSum=402
8199 12:44:15.167283 TX Vref=26, minBit 3, minWin=24, winSum=412
8200 12:44:15.170795 TX Vref=28, minBit 3, minWin=24, winSum=413
8201 12:44:15.174167 TX Vref=30, minBit 1, minWin=24, winSum=405
8202 12:44:15.177443 TX Vref=32, minBit 3, minWin=23, winSum=395
8203 12:44:15.181242 TX Vref=34, minBit 1, minWin=22, winSum=391
8204 12:44:15.187265 [TxChooseVref] Worse bit 3, Min win 24, Win sum 413, Final Vref 28
8205 12:44:15.187746
8206 12:44:15.190845 Final TX Range 0 Vref 28
8207 12:44:15.191398
8208 12:44:15.191768 ==
8209 12:44:15.193556 Dram Type= 6, Freq= 0, CH_1, rank 0
8210 12:44:15.197537 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8211 12:44:15.198096 ==
8212 12:44:15.198464
8213 12:44:15.198802
8214 12:44:15.200906 TX Vref Scan disable
8215 12:44:15.207984 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8216 12:44:15.208540 == TX Byte 0 ==
8217 12:44:15.210358 u2DelayCellOfst[0]=14 cells (4 PI)
8218 12:44:15.213434 u2DelayCellOfst[1]=7 cells (2 PI)
8219 12:44:15.217682 u2DelayCellOfst[2]=0 cells (0 PI)
8220 12:44:15.220343 u2DelayCellOfst[3]=3 cells (1 PI)
8221 12:44:15.223559 u2DelayCellOfst[4]=7 cells (2 PI)
8222 12:44:15.227484 u2DelayCellOfst[5]=14 cells (4 PI)
8223 12:44:15.230557 u2DelayCellOfst[6]=14 cells (4 PI)
8224 12:44:15.233699 u2DelayCellOfst[7]=3 cells (1 PI)
8225 12:44:15.236822 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8226 12:44:15.240325 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8227 12:44:15.244265 == TX Byte 1 ==
8228 12:44:15.244896 u2DelayCellOfst[8]=0 cells (0 PI)
8229 12:44:15.246826 u2DelayCellOfst[9]=7 cells (2 PI)
8230 12:44:15.249942 u2DelayCellOfst[10]=10 cells (3 PI)
8231 12:44:15.253353 u2DelayCellOfst[11]=3 cells (1 PI)
8232 12:44:15.256660 u2DelayCellOfst[12]=18 cells (5 PI)
8233 12:44:15.259788 u2DelayCellOfst[13]=21 cells (6 PI)
8234 12:44:15.263936 u2DelayCellOfst[14]=21 cells (6 PI)
8235 12:44:15.266448 u2DelayCellOfst[15]=18 cells (5 PI)
8236 12:44:15.270211 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8237 12:44:15.276513 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8238 12:44:15.277123 DramC Write-DBI on
8239 12:44:15.277561 ==
8240 12:44:15.279887 Dram Type= 6, Freq= 0, CH_1, rank 0
8241 12:44:15.286640 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8242 12:44:15.287231 ==
8243 12:44:15.287603
8244 12:44:15.287946
8245 12:44:15.288272 TX Vref Scan disable
8246 12:44:15.290023 == TX Byte 0 ==
8247 12:44:15.293332 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8248 12:44:15.296322 == TX Byte 1 ==
8249 12:44:15.300298 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8250 12:44:15.303917 DramC Write-DBI off
8251 12:44:15.304486
8252 12:44:15.304899 [DATLAT]
8253 12:44:15.305242 Freq=1600, CH1 RK0
8254 12:44:15.305570
8255 12:44:15.307861 DATLAT Default: 0xf
8256 12:44:15.308414 0, 0xFFFF, sum = 0
8257 12:44:15.309917 1, 0xFFFF, sum = 0
8258 12:44:15.312641 2, 0xFFFF, sum = 0
8259 12:44:15.313108 3, 0xFFFF, sum = 0
8260 12:44:15.316443 4, 0xFFFF, sum = 0
8261 12:44:15.316950 5, 0xFFFF, sum = 0
8262 12:44:15.320282 6, 0xFFFF, sum = 0
8263 12:44:15.320898 7, 0xFFFF, sum = 0
8264 12:44:15.323373 8, 0xFFFF, sum = 0
8265 12:44:15.323964 9, 0xFFFF, sum = 0
8266 12:44:15.326163 10, 0xFFFF, sum = 0
8267 12:44:15.326636 11, 0xFFFF, sum = 0
8268 12:44:15.330238 12, 0x8FFF, sum = 0
8269 12:44:15.330707 13, 0x0, sum = 1
8270 12:44:15.332673 14, 0x0, sum = 2
8271 12:44:15.333187 15, 0x0, sum = 3
8272 12:44:15.336076 16, 0x0, sum = 4
8273 12:44:15.336545 best_step = 14
8274 12:44:15.336974
8275 12:44:15.337321 ==
8276 12:44:15.339697 Dram Type= 6, Freq= 0, CH_1, rank 0
8277 12:44:15.343222 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8278 12:44:15.346292 ==
8279 12:44:15.346758 RX Vref Scan: 1
8280 12:44:15.347270
8281 12:44:15.350863 Set Vref Range= 24 -> 127
8282 12:44:15.351423
8283 12:44:15.352465 RX Vref 24 -> 127, step: 1
8284 12:44:15.352976
8285 12:44:15.353344 RX Delay 3 -> 252, step: 4
8286 12:44:15.353685
8287 12:44:15.356260 Set Vref, RX VrefLevel [Byte0]: 24
8288 12:44:15.359754 [Byte1]: 24
8289 12:44:15.364000
8290 12:44:15.364603 Set Vref, RX VrefLevel [Byte0]: 25
8291 12:44:15.366907 [Byte1]: 25
8292 12:44:15.370575
8293 12:44:15.371033 Set Vref, RX VrefLevel [Byte0]: 26
8294 12:44:15.374906 [Byte1]: 26
8295 12:44:15.378975
8296 12:44:15.379427 Set Vref, RX VrefLevel [Byte0]: 27
8297 12:44:15.382605 [Byte1]: 27
8298 12:44:15.386039
8299 12:44:15.386448 Set Vref, RX VrefLevel [Byte0]: 28
8300 12:44:15.389709 [Byte1]: 28
8301 12:44:15.394153
8302 12:44:15.394660 Set Vref, RX VrefLevel [Byte0]: 29
8303 12:44:15.397117 [Byte1]: 29
8304 12:44:15.401240
8305 12:44:15.401722 Set Vref, RX VrefLevel [Byte0]: 30
8306 12:44:15.405285 [Byte1]: 30
8307 12:44:15.409640
8308 12:44:15.410146 Set Vref, RX VrefLevel [Byte0]: 31
8309 12:44:15.412262 [Byte1]: 31
8310 12:44:15.416940
8311 12:44:15.417488 Set Vref, RX VrefLevel [Byte0]: 32
8312 12:44:15.420302 [Byte1]: 32
8313 12:44:15.424362
8314 12:44:15.425194 Set Vref, RX VrefLevel [Byte0]: 33
8315 12:44:15.427929 [Byte1]: 33
8316 12:44:15.432809
8317 12:44:15.433263 Set Vref, RX VrefLevel [Byte0]: 34
8318 12:44:15.435117 [Byte1]: 34
8319 12:44:15.439460
8320 12:44:15.439914 Set Vref, RX VrefLevel [Byte0]: 35
8321 12:44:15.443136 [Byte1]: 35
8322 12:44:15.448288
8323 12:44:15.448780 Set Vref, RX VrefLevel [Byte0]: 36
8324 12:44:15.451110 [Byte1]: 36
8325 12:44:15.456340
8326 12:44:15.456934 Set Vref, RX VrefLevel [Byte0]: 37
8327 12:44:15.459277 [Byte1]: 37
8328 12:44:15.463075
8329 12:44:15.463627 Set Vref, RX VrefLevel [Byte0]: 38
8330 12:44:15.466795 [Byte1]: 38
8331 12:44:15.470596
8332 12:44:15.471144 Set Vref, RX VrefLevel [Byte0]: 39
8333 12:44:15.473695 [Byte1]: 39
8334 12:44:15.478183
8335 12:44:15.478737 Set Vref, RX VrefLevel [Byte0]: 40
8336 12:44:15.481433 [Byte1]: 40
8337 12:44:15.486609
8338 12:44:15.487157 Set Vref, RX VrefLevel [Byte0]: 41
8339 12:44:15.489625 [Byte1]: 41
8340 12:44:15.493885
8341 12:44:15.494495 Set Vref, RX VrefLevel [Byte0]: 42
8342 12:44:15.496956 [Byte1]: 42
8343 12:44:15.501602
8344 12:44:15.502149 Set Vref, RX VrefLevel [Byte0]: 43
8345 12:44:15.504886 [Byte1]: 43
8346 12:44:15.508573
8347 12:44:15.509150 Set Vref, RX VrefLevel [Byte0]: 44
8348 12:44:15.511537 [Byte1]: 44
8349 12:44:15.516599
8350 12:44:15.517182 Set Vref, RX VrefLevel [Byte0]: 45
8351 12:44:15.519947 [Byte1]: 45
8352 12:44:15.525165
8353 12:44:15.525711 Set Vref, RX VrefLevel [Byte0]: 46
8354 12:44:15.527223 [Byte1]: 46
8355 12:44:15.532159
8356 12:44:15.532610 Set Vref, RX VrefLevel [Byte0]: 47
8357 12:44:15.534783 [Byte1]: 47
8358 12:44:15.539003
8359 12:44:15.539454 Set Vref, RX VrefLevel [Byte0]: 48
8360 12:44:15.542893 [Byte1]: 48
8361 12:44:15.547537
8362 12:44:15.548089 Set Vref, RX VrefLevel [Byte0]: 49
8363 12:44:15.550546 [Byte1]: 49
8364 12:44:15.556391
8365 12:44:15.556898 Set Vref, RX VrefLevel [Byte0]: 50
8366 12:44:15.558244 [Byte1]: 50
8367 12:44:15.562049
8368 12:44:15.562507 Set Vref, RX VrefLevel [Byte0]: 51
8369 12:44:15.566296 [Byte1]: 51
8370 12:44:15.570154
8371 12:44:15.570704 Set Vref, RX VrefLevel [Byte0]: 52
8372 12:44:15.573030 [Byte1]: 52
8373 12:44:15.577749
8374 12:44:15.578323 Set Vref, RX VrefLevel [Byte0]: 53
8375 12:44:15.580963 [Byte1]: 53
8376 12:44:15.585486
8377 12:44:15.585942 Set Vref, RX VrefLevel [Byte0]: 54
8378 12:44:15.588377 [Byte1]: 54
8379 12:44:15.593779
8380 12:44:15.594332 Set Vref, RX VrefLevel [Byte0]: 55
8381 12:44:15.596138 [Byte1]: 55
8382 12:44:15.600591
8383 12:44:15.601258 Set Vref, RX VrefLevel [Byte0]: 56
8384 12:44:15.604363 [Byte1]: 56
8385 12:44:15.607966
8386 12:44:15.608521 Set Vref, RX VrefLevel [Byte0]: 57
8387 12:44:15.611650 [Byte1]: 57
8388 12:44:15.615799
8389 12:44:15.616256 Set Vref, RX VrefLevel [Byte0]: 58
8390 12:44:15.618745 [Byte1]: 58
8391 12:44:15.623775
8392 12:44:15.624291 Set Vref, RX VrefLevel [Byte0]: 59
8393 12:44:15.626387 [Byte1]: 59
8394 12:44:15.631423
8395 12:44:15.631883 Set Vref, RX VrefLevel [Byte0]: 60
8396 12:44:15.635197 [Byte1]: 60
8397 12:44:15.639430
8398 12:44:15.640015 Set Vref, RX VrefLevel [Byte0]: 61
8399 12:44:15.642289 [Byte1]: 61
8400 12:44:15.646255
8401 12:44:15.646721 Set Vref, RX VrefLevel [Byte0]: 62
8402 12:44:15.649429 [Byte1]: 62
8403 12:44:15.654647
8404 12:44:15.655108 Set Vref, RX VrefLevel [Byte0]: 63
8405 12:44:15.657502 [Byte1]: 63
8406 12:44:15.661407
8407 12:44:15.661824 Set Vref, RX VrefLevel [Byte0]: 64
8408 12:44:15.664858 [Byte1]: 64
8409 12:44:15.670235
8410 12:44:15.670748 Set Vref, RX VrefLevel [Byte0]: 65
8411 12:44:15.672818 [Byte1]: 65
8412 12:44:15.677022
8413 12:44:15.677439 Set Vref, RX VrefLevel [Byte0]: 66
8414 12:44:15.680861 [Byte1]: 66
8415 12:44:15.684527
8416 12:44:15.685078 Set Vref, RX VrefLevel [Byte0]: 67
8417 12:44:15.688108 [Byte1]: 67
8418 12:44:15.692285
8419 12:44:15.692914 Set Vref, RX VrefLevel [Byte0]: 68
8420 12:44:15.695777 [Byte1]: 68
8421 12:44:15.699972
8422 12:44:15.700484 Set Vref, RX VrefLevel [Byte0]: 69
8423 12:44:15.703910 [Byte1]: 69
8424 12:44:15.707499
8425 12:44:15.708048 Set Vref, RX VrefLevel [Byte0]: 70
8426 12:44:15.711052 [Byte1]: 70
8427 12:44:15.715213
8428 12:44:15.715633 Set Vref, RX VrefLevel [Byte0]: 71
8429 12:44:15.718970 [Byte1]: 71
8430 12:44:15.723012
8431 12:44:15.723525 Set Vref, RX VrefLevel [Byte0]: 72
8432 12:44:15.726218 [Byte1]: 72
8433 12:44:15.730986
8434 12:44:15.731405 Set Vref, RX VrefLevel [Byte0]: 73
8435 12:44:15.733398 [Byte1]: 73
8436 12:44:15.738830
8437 12:44:15.739346 Set Vref, RX VrefLevel [Byte0]: 74
8438 12:44:15.741301 [Byte1]: 74
8439 12:44:15.746007
8440 12:44:15.746513 Set Vref, RX VrefLevel [Byte0]: 75
8441 12:44:15.749285 [Byte1]: 75
8442 12:44:15.753324
8443 12:44:15.753836 Final RX Vref Byte 0 = 59 to rank0
8444 12:44:15.756899 Final RX Vref Byte 1 = 53 to rank0
8445 12:44:15.760015 Final RX Vref Byte 0 = 59 to rank1
8446 12:44:15.763505 Final RX Vref Byte 1 = 53 to rank1==
8447 12:44:15.767238 Dram Type= 6, Freq= 0, CH_1, rank 0
8448 12:44:15.774185 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8449 12:44:15.774687 ==
8450 12:44:15.775020 DQS Delay:
8451 12:44:15.777667 DQS0 = 0, DQS1 = 0
8452 12:44:15.778186 DQM Delay:
8453 12:44:15.778623 DQM0 = 128, DQM1 = 124
8454 12:44:15.780350 DQ Delay:
8455 12:44:15.783734 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
8456 12:44:15.786344 DQ4 =128, DQ5 =138, DQ6 =136, DQ7 =124
8457 12:44:15.789992 DQ8 =106, DQ9 =114, DQ10 =126, DQ11 =114
8458 12:44:15.793945 DQ12 =130, DQ13 =134, DQ14 =134, DQ15 =134
8459 12:44:15.794457
8460 12:44:15.794790
8461 12:44:15.795099
8462 12:44:15.796924 [DramC_TX_OE_Calibration] TA2
8463 12:44:15.799925 Original DQ_B0 (3 6) =30, OEN = 27
8464 12:44:15.803418 Original DQ_B1 (3 6) =30, OEN = 27
8465 12:44:15.806638 24, 0x0, End_B0=24 End_B1=24
8466 12:44:15.807156 25, 0x0, End_B0=25 End_B1=25
8467 12:44:15.809664 26, 0x0, End_B0=26 End_B1=26
8468 12:44:15.813651 27, 0x0, End_B0=27 End_B1=27
8469 12:44:15.816703 28, 0x0, End_B0=28 End_B1=28
8470 12:44:15.820226 29, 0x0, End_B0=29 End_B1=29
8471 12:44:15.820657 30, 0x0, End_B0=30 End_B1=30
8472 12:44:15.823585 31, 0x4141, End_B0=30 End_B1=30
8473 12:44:15.825835 Byte0 end_step=30 best_step=27
8474 12:44:15.829211 Byte1 end_step=30 best_step=27
8475 12:44:15.834179 Byte0 TX OE(2T, 0.5T) = (3, 3)
8476 12:44:15.836686 Byte1 TX OE(2T, 0.5T) = (3, 3)
8477 12:44:15.837337
8478 12:44:15.837799
8479 12:44:15.843678 [DQSOSCAuto] RK0, (LSB)MR18= 0x2626, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
8480 12:44:15.846041 CH1 RK0: MR19=303, MR18=2626
8481 12:44:15.853342 CH1_RK0: MR19=0x303, MR18=0x2626, DQSOSC=390, MR23=63, INC=24, DEC=16
8482 12:44:15.853903
8483 12:44:15.856589 ----->DramcWriteLeveling(PI) begin...
8484 12:44:15.857210 ==
8485 12:44:15.859597 Dram Type= 6, Freq= 0, CH_1, rank 1
8486 12:44:15.862691 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8487 12:44:15.863279 ==
8488 12:44:15.866280 Write leveling (Byte 0): 22 => 22
8489 12:44:15.868866 Write leveling (Byte 1): 21 => 21
8490 12:44:15.872390 DramcWriteLeveling(PI) end<-----
8491 12:44:15.873000
8492 12:44:15.873376 ==
8493 12:44:15.876195 Dram Type= 6, Freq= 0, CH_1, rank 1
8494 12:44:15.879520 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8495 12:44:15.879985 ==
8496 12:44:15.882412 [Gating] SW mode calibration
8497 12:44:15.889029 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8498 12:44:15.895448 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8499 12:44:15.899673 0 12 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8500 12:44:15.905621 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8501 12:44:15.908571 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8502 12:44:15.912100 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8503 12:44:15.918928 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8504 12:44:15.922594 0 12 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8505 12:44:15.925379 0 12 24 | B1->B0 | 3434 2929 | 1 1 | (1 1) (0 0)
8506 12:44:15.932193 0 12 28 | B1->B0 | 3333 2323 | 0 0 | (1 0) (0 0)
8507 12:44:15.935779 0 13 0 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
8508 12:44:15.938168 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8509 12:44:15.945484 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8510 12:44:15.948331 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8511 12:44:15.952197 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8512 12:44:15.959173 0 13 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8513 12:44:15.962921 0 13 24 | B1->B0 | 2323 3535 | 0 0 | (0 0) (1 1)
8514 12:44:15.964939 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8515 12:44:15.971323 0 14 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8516 12:44:15.975101 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8517 12:44:15.977985 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8518 12:44:15.984527 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8519 12:44:15.987831 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8520 12:44:15.992215 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8521 12:44:15.998508 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8522 12:44:16.001665 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8523 12:44:16.004614 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8524 12:44:16.011132 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8525 12:44:16.015025 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8526 12:44:16.017699 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8527 12:44:16.024846 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8528 12:44:16.027883 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8529 12:44:16.030785 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8530 12:44:16.037464 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8531 12:44:16.041050 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8532 12:44:16.044411 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8533 12:44:16.051052 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8534 12:44:16.055142 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8535 12:44:16.057582 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8536 12:44:16.064311 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8537 12:44:16.067574 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8538 12:44:16.070589 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8539 12:44:16.074629 Total UI for P1: 0, mck2ui 16
8540 12:44:16.077375 best dqsien dly found for B0: ( 1, 0, 24)
8541 12:44:16.080823 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8542 12:44:16.087644 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8543 12:44:16.090792 Total UI for P1: 0, mck2ui 16
8544 12:44:16.094059 best dqsien dly found for B1: ( 1, 0, 30)
8545 12:44:16.097791 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8546 12:44:16.100880 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8547 12:44:16.101304
8548 12:44:16.104151 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8549 12:44:16.108169 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8550 12:44:16.111225 [Gating] SW calibration Done
8551 12:44:16.111665 ==
8552 12:44:16.113540 Dram Type= 6, Freq= 0, CH_1, rank 1
8553 12:44:16.117845 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8554 12:44:16.118353 ==
8555 12:44:16.120643 RX Vref Scan: 0
8556 12:44:16.121085
8557 12:44:16.123653 RX Vref 0 -> 0, step: 1
8558 12:44:16.124062
8559 12:44:16.124385 RX Delay 0 -> 252, step: 8
8560 12:44:16.130776 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8561 12:44:16.133577 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8562 12:44:16.136780 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8563 12:44:16.140459 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8564 12:44:16.143467 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8565 12:44:16.150297 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8566 12:44:16.153272 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8567 12:44:16.156484 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8568 12:44:16.161186 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8569 12:44:16.163629 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8570 12:44:16.170291 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8571 12:44:16.173390 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8572 12:44:16.176555 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8573 12:44:16.180264 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8574 12:44:16.183538 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8575 12:44:16.190617 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8576 12:44:16.191138 ==
8577 12:44:16.193244 Dram Type= 6, Freq= 0, CH_1, rank 1
8578 12:44:16.196472 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8579 12:44:16.197013 ==
8580 12:44:16.197348 DQS Delay:
8581 12:44:16.199731 DQS0 = 0, DQS1 = 0
8582 12:44:16.200279 DQM Delay:
8583 12:44:16.203236 DQM0 = 131, DQM1 = 126
8584 12:44:16.203725 DQ Delay:
8585 12:44:16.207118 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =131
8586 12:44:16.209972 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8587 12:44:16.213234 DQ8 =107, DQ9 =115, DQ10 =131, DQ11 =115
8588 12:44:16.220418 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8589 12:44:16.221003
8590 12:44:16.221340
8591 12:44:16.221647 ==
8592 12:44:16.223298 Dram Type= 6, Freq= 0, CH_1, rank 1
8593 12:44:16.226193 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8594 12:44:16.226610 ==
8595 12:44:16.226936
8596 12:44:16.227241
8597 12:44:16.230130 TX Vref Scan disable
8598 12:44:16.230555 == TX Byte 0 ==
8599 12:44:16.236089 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8600 12:44:16.239481 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8601 12:44:16.240010 == TX Byte 1 ==
8602 12:44:16.246810 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8603 12:44:16.249591 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8604 12:44:16.250008 ==
8605 12:44:16.253752 Dram Type= 6, Freq= 0, CH_1, rank 1
8606 12:44:16.256364 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8607 12:44:16.256930 ==
8608 12:44:16.270862
8609 12:44:16.273778 TX Vref early break, caculate TX vref
8610 12:44:16.277831 TX Vref=16, minBit 4, minWin=22, winSum=379
8611 12:44:16.281355 TX Vref=18, minBit 0, minWin=22, winSum=385
8612 12:44:16.284789 TX Vref=20, minBit 0, minWin=23, winSum=392
8613 12:44:16.287065 TX Vref=22, minBit 0, minWin=23, winSum=402
8614 12:44:16.290105 TX Vref=24, minBit 2, minWin=24, winSum=411
8615 12:44:16.297029 TX Vref=26, minBit 0, minWin=25, winSum=419
8616 12:44:16.300393 TX Vref=28, minBit 0, minWin=25, winSum=419
8617 12:44:16.303446 TX Vref=30, minBit 0, minWin=24, winSum=415
8618 12:44:16.306686 TX Vref=32, minBit 0, minWin=23, winSum=407
8619 12:44:16.311001 TX Vref=34, minBit 0, minWin=23, winSum=399
8620 12:44:16.313346 TX Vref=36, minBit 0, minWin=22, winSum=392
8621 12:44:16.320265 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 26
8622 12:44:16.320855
8623 12:44:16.323385 Final TX Range 0 Vref 26
8624 12:44:16.323843
8625 12:44:16.324202 ==
8626 12:44:16.326773 Dram Type= 6, Freq= 0, CH_1, rank 1
8627 12:44:16.330429 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8628 12:44:16.330886 ==
8629 12:44:16.331242
8630 12:44:16.331571
8631 12:44:16.333974 TX Vref Scan disable
8632 12:44:16.340252 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8633 12:44:16.340756 == TX Byte 0 ==
8634 12:44:16.343541 u2DelayCellOfst[0]=14 cells (4 PI)
8635 12:44:16.347063 u2DelayCellOfst[1]=7 cells (2 PI)
8636 12:44:16.350009 u2DelayCellOfst[2]=0 cells (0 PI)
8637 12:44:16.353244 u2DelayCellOfst[3]=7 cells (2 PI)
8638 12:44:16.356431 u2DelayCellOfst[4]=7 cells (2 PI)
8639 12:44:16.360211 u2DelayCellOfst[5]=14 cells (4 PI)
8640 12:44:16.363575 u2DelayCellOfst[6]=14 cells (4 PI)
8641 12:44:16.366977 u2DelayCellOfst[7]=3 cells (1 PI)
8642 12:44:16.369634 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8643 12:44:16.373495 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8644 12:44:16.376267 == TX Byte 1 ==
8645 12:44:16.376696 u2DelayCellOfst[8]=0 cells (0 PI)
8646 12:44:16.379761 u2DelayCellOfst[9]=3 cells (1 PI)
8647 12:44:16.384551 u2DelayCellOfst[10]=7 cells (2 PI)
8648 12:44:16.386569 u2DelayCellOfst[11]=3 cells (1 PI)
8649 12:44:16.390764 u2DelayCellOfst[12]=14 cells (4 PI)
8650 12:44:16.393777 u2DelayCellOfst[13]=18 cells (5 PI)
8651 12:44:16.396684 u2DelayCellOfst[14]=18 cells (5 PI)
8652 12:44:16.400826 u2DelayCellOfst[15]=18 cells (5 PI)
8653 12:44:16.402795 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8654 12:44:16.409365 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8655 12:44:16.409873 DramC Write-DBI on
8656 12:44:16.410253 ==
8657 12:44:16.413128 Dram Type= 6, Freq= 0, CH_1, rank 1
8658 12:44:16.419957 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8659 12:44:16.420495 ==
8660 12:44:16.421015
8661 12:44:16.421339
8662 12:44:16.421639 TX Vref Scan disable
8663 12:44:16.424036 == TX Byte 0 ==
8664 12:44:16.427076 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8665 12:44:16.430071 == TX Byte 1 ==
8666 12:44:16.432930 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8667 12:44:16.436542 DramC Write-DBI off
8668 12:44:16.437087
8669 12:44:16.437419 [DATLAT]
8670 12:44:16.437724 Freq=1600, CH1 RK1
8671 12:44:16.438021
8672 12:44:16.440335 DATLAT Default: 0xe
8673 12:44:16.440794 0, 0xFFFF, sum = 0
8674 12:44:16.443375 1, 0xFFFF, sum = 0
8675 12:44:16.446095 2, 0xFFFF, sum = 0
8676 12:44:16.446521 3, 0xFFFF, sum = 0
8677 12:44:16.450242 4, 0xFFFF, sum = 0
8678 12:44:16.450670 5, 0xFFFF, sum = 0
8679 12:44:16.452787 6, 0xFFFF, sum = 0
8680 12:44:16.453225 7, 0xFFFF, sum = 0
8681 12:44:16.456617 8, 0xFFFF, sum = 0
8682 12:44:16.457154 9, 0xFFFF, sum = 0
8683 12:44:16.459609 10, 0xFFFF, sum = 0
8684 12:44:16.460158 11, 0xFFFF, sum = 0
8685 12:44:16.463185 12, 0x8F7F, sum = 0
8686 12:44:16.463701 13, 0x0, sum = 1
8687 12:44:16.466469 14, 0x0, sum = 2
8688 12:44:16.466967 15, 0x0, sum = 3
8689 12:44:16.469474 16, 0x0, sum = 4
8690 12:44:16.469897 best_step = 14
8691 12:44:16.470225
8692 12:44:16.470528 ==
8693 12:44:16.472815 Dram Type= 6, Freq= 0, CH_1, rank 1
8694 12:44:16.477678 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8695 12:44:16.479903 ==
8696 12:44:16.480322 RX Vref Scan: 0
8697 12:44:16.480655
8698 12:44:16.483131 RX Vref 0 -> 0, step: 1
8699 12:44:16.483661
8700 12:44:16.484099 RX Delay 3 -> 252, step: 4
8701 12:44:16.490012 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8702 12:44:16.494192 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8703 12:44:16.497075 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8704 12:44:16.500124 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8705 12:44:16.503322 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8706 12:44:16.510269 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8707 12:44:16.513719 iDelay=195, Bit 6, Center 134 (79 ~ 190) 112
8708 12:44:16.517158 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8709 12:44:16.519960 iDelay=195, Bit 8, Center 108 (51 ~ 166) 116
8710 12:44:16.523380 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8711 12:44:16.531237 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8712 12:44:16.533395 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8713 12:44:16.537115 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8714 12:44:16.539368 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8715 12:44:16.546779 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8716 12:44:16.549581 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8717 12:44:16.550107 ==
8718 12:44:16.554622 Dram Type= 6, Freq= 0, CH_1, rank 1
8719 12:44:16.557080 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8720 12:44:16.557505 ==
8721 12:44:16.560145 DQS Delay:
8722 12:44:16.560699 DQS0 = 0, DQS1 = 0
8723 12:44:16.561099 DQM Delay:
8724 12:44:16.563204 DQM0 = 127, DQM1 = 122
8725 12:44:16.563669 DQ Delay:
8726 12:44:16.566567 DQ0 =128, DQ1 =124, DQ2 =116, DQ3 =124
8727 12:44:16.569787 DQ4 =126, DQ5 =138, DQ6 =134, DQ7 =126
8728 12:44:16.573188 DQ8 =108, DQ9 =110, DQ10 =124, DQ11 =112
8729 12:44:16.579658 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8730 12:44:16.580147
8731 12:44:16.580479
8732 12:44:16.580839
8733 12:44:16.583430 [DramC_TX_OE_Calibration] TA2
8734 12:44:16.583973 Original DQ_B0 (3 6) =30, OEN = 27
8735 12:44:16.586958 Original DQ_B1 (3 6) =30, OEN = 27
8736 12:44:16.590012 24, 0x0, End_B0=24 End_B1=24
8737 12:44:16.593086 25, 0x0, End_B0=25 End_B1=25
8738 12:44:16.596460 26, 0x0, End_B0=26 End_B1=26
8739 12:44:16.599814 27, 0x0, End_B0=27 End_B1=27
8740 12:44:16.600342 28, 0x0, End_B0=28 End_B1=28
8741 12:44:16.602934 29, 0x0, End_B0=29 End_B1=29
8742 12:44:16.606307 30, 0x0, End_B0=30 End_B1=30
8743 12:44:16.609568 31, 0x4141, End_B0=30 End_B1=30
8744 12:44:16.612821 Byte0 end_step=30 best_step=27
8745 12:44:16.613266 Byte1 end_step=30 best_step=27
8746 12:44:16.616057 Byte0 TX OE(2T, 0.5T) = (3, 3)
8747 12:44:16.619412 Byte1 TX OE(2T, 0.5T) = (3, 3)
8748 12:44:16.619912
8749 12:44:16.620250
8750 12:44:16.629311 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
8751 12:44:16.629900 CH1 RK1: MR19=303, MR18=1C1C
8752 12:44:16.636191 CH1_RK1: MR19=0x303, MR18=0x1C1C, DQSOSC=395, MR23=63, INC=23, DEC=15
8753 12:44:16.639131 [RxdqsGatingPostProcess] freq 1600
8754 12:44:16.645635 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8755 12:44:16.649423 Pre-setting of DQS Precalculation
8756 12:44:16.652438 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8757 12:44:16.660471 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8758 12:44:16.669467 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8759 12:44:16.670005
8760 12:44:16.670332
8761 12:44:16.672500 [Calibration Summary] 3200 Mbps
8762 12:44:16.673021 CH 0, Rank 0
8763 12:44:16.676067 SW Impedance : PASS
8764 12:44:16.676609 DUTY Scan : NO K
8765 12:44:16.679016 ZQ Calibration : PASS
8766 12:44:16.682683 Jitter Meter : NO K
8767 12:44:16.683268 CBT Training : PASS
8768 12:44:16.685906 Write leveling : PASS
8769 12:44:16.689745 RX DQS gating : PASS
8770 12:44:16.690201 RX DQ/DQS(RDDQC) : PASS
8771 12:44:16.692769 TX DQ/DQS : PASS
8772 12:44:16.693194 RX DATLAT : PASS
8773 12:44:16.695837 RX DQ/DQS(Engine): PASS
8774 12:44:16.700230 TX OE : PASS
8775 12:44:16.700803 All Pass.
8776 12:44:16.701147
8777 12:44:16.701454 CH 0, Rank 1
8778 12:44:16.702155 SW Impedance : PASS
8779 12:44:16.705920 DUTY Scan : NO K
8780 12:44:16.706341 ZQ Calibration : PASS
8781 12:44:16.709044 Jitter Meter : NO K
8782 12:44:16.712203 CBT Training : PASS
8783 12:44:16.712752 Write leveling : PASS
8784 12:44:16.715435 RX DQS gating : PASS
8785 12:44:16.718932 RX DQ/DQS(RDDQC) : PASS
8786 12:44:16.719450 TX DQ/DQS : PASS
8787 12:44:16.722076 RX DATLAT : PASS
8788 12:44:16.725807 RX DQ/DQS(Engine): PASS
8789 12:44:16.726251 TX OE : PASS
8790 12:44:16.729531 All Pass.
8791 12:44:16.730009
8792 12:44:16.730396 CH 1, Rank 0
8793 12:44:16.732084 SW Impedance : PASS
8794 12:44:16.732522 DUTY Scan : NO K
8795 12:44:16.735245 ZQ Calibration : PASS
8796 12:44:16.739529 Jitter Meter : NO K
8797 12:44:16.739950 CBT Training : PASS
8798 12:44:16.742973 Write leveling : PASS
8799 12:44:16.745556 RX DQS gating : PASS
8800 12:44:16.746067 RX DQ/DQS(RDDQC) : PASS
8801 12:44:16.748382 TX DQ/DQS : PASS
8802 12:44:16.748838 RX DATLAT : PASS
8803 12:44:16.752278 RX DQ/DQS(Engine): PASS
8804 12:44:16.755780 TX OE : PASS
8805 12:44:16.756317 All Pass.
8806 12:44:16.756663
8807 12:44:16.757079 CH 1, Rank 1
8808 12:44:16.759795 SW Impedance : PASS
8809 12:44:16.762539 DUTY Scan : NO K
8810 12:44:16.763072 ZQ Calibration : PASS
8811 12:44:16.765188 Jitter Meter : NO K
8812 12:44:16.769620 CBT Training : PASS
8813 12:44:16.770040 Write leveling : PASS
8814 12:44:16.772610 RX DQS gating : PASS
8815 12:44:16.774988 RX DQ/DQS(RDDQC) : PASS
8816 12:44:16.775408 TX DQ/DQS : PASS
8817 12:44:16.779839 RX DATLAT : PASS
8818 12:44:16.781771 RX DQ/DQS(Engine): PASS
8819 12:44:16.782193 TX OE : PASS
8820 12:44:16.785645 All Pass.
8821 12:44:16.786188
8822 12:44:16.786587 DramC Write-DBI on
8823 12:44:16.788543 PER_BANK_REFRESH: Hybrid Mode
8824 12:44:16.789025 TX_TRACKING: ON
8825 12:44:16.798675 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8826 12:44:16.808649 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8827 12:44:16.814546 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8828 12:44:16.818021 [FAST_K] Save calibration result to emmc
8829 12:44:16.821272 sync common calibartion params.
8830 12:44:16.821695 sync cbt_mode0:0, 1:0
8831 12:44:16.824487 dram_init: ddr_geometry: 0
8832 12:44:16.828305 dram_init: ddr_geometry: 0
8833 12:44:16.828770 dram_init: ddr_geometry: 0
8834 12:44:16.831150 0:dram_rank_size:80000000
8835 12:44:16.834493 1:dram_rank_size:80000000
8836 12:44:16.841407 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8837 12:44:16.841828 DFS_SHUFFLE_HW_MODE: ON
8838 12:44:16.844737 dramc_set_vcore_voltage set vcore to 725000
8839 12:44:16.847668 Read voltage for 1600, 0
8840 12:44:16.848081 Vio18 = 0
8841 12:44:16.851524 Vcore = 725000
8842 12:44:16.852026 Vdram = 0
8843 12:44:16.852356 Vddq = 0
8844 12:44:16.854619 Vmddr = 0
8845 12:44:16.855106 switch to 3200 Mbps bootup
8846 12:44:16.857663 [DramcRunTimeConfig]
8847 12:44:16.858075 PHYPLL
8848 12:44:16.861321 DPM_CONTROL_AFTERK: ON
8849 12:44:16.861731 PER_BANK_REFRESH: ON
8850 12:44:16.864911 REFRESH_OVERHEAD_REDUCTION: ON
8851 12:44:16.868268 CMD_PICG_NEW_MODE: OFF
8852 12:44:16.868791 XRTWTW_NEW_MODE: ON
8853 12:44:16.872100 XRTRTR_NEW_MODE: ON
8854 12:44:16.872682 TX_TRACKING: ON
8855 12:44:16.874375 RDSEL_TRACKING: OFF
8856 12:44:16.877534 DQS Precalculation for DVFS: ON
8857 12:44:16.877943 RX_TRACKING: OFF
8858 12:44:16.881282 HW_GATING DBG: ON
8859 12:44:16.881695 ZQCS_ENABLE_LP4: ON
8860 12:44:16.884885 RX_PICG_NEW_MODE: ON
8861 12:44:16.885411 TX_PICG_NEW_MODE: ON
8862 12:44:16.887668 ENABLE_RX_DCM_DPHY: ON
8863 12:44:16.890631 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8864 12:44:16.893961 DUMMY_READ_FOR_TRACKING: OFF
8865 12:44:16.894373 !!! SPM_CONTROL_AFTERK: OFF
8866 12:44:16.897196 !!! SPM could not control APHY
8867 12:44:16.901130 IMPEDANCE_TRACKING: ON
8868 12:44:16.901627 TEMP_SENSOR: ON
8869 12:44:16.904513 HW_SAVE_FOR_SR: OFF
8870 12:44:16.907145 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8871 12:44:16.911089 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8872 12:44:16.914144 Read ODT Tracking: ON
8873 12:44:16.914556 Refresh Rate DeBounce: ON
8874 12:44:16.917164 DFS_NO_QUEUE_FLUSH: ON
8875 12:44:16.920938 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8876 12:44:16.924317 ENABLE_DFS_RUNTIME_MRW: OFF
8877 12:44:16.924762 DDR_RESERVE_NEW_MODE: ON
8878 12:44:16.927659 MR_CBT_SWITCH_FREQ: ON
8879 12:44:16.930440 =========================
8880 12:44:16.947680 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8881 12:44:16.950908 dram_init: ddr_geometry: 0
8882 12:44:16.968971 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8883 12:44:16.972282 dram_init: dram init end (result: 0)
8884 12:44:16.980337 DRAM-K: Full calibration passed in 23475 msecs
8885 12:44:16.982500 MRC: failed to locate region type 0.
8886 12:44:16.983055 DRAM rank0 size:0x80000000,
8887 12:44:16.985902 DRAM rank1 size=0x80000000
8888 12:44:16.996189 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8889 12:44:17.002723 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8890 12:44:17.009540 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8891 12:44:17.016077 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8892 12:44:17.019375 DRAM rank0 size:0x80000000,
8893 12:44:17.022612 DRAM rank1 size=0x80000000
8894 12:44:17.023203 CBMEM:
8895 12:44:17.026372 IMD: root @ 0xfffff000 254 entries.
8896 12:44:17.028783 IMD: root @ 0xffffec00 62 entries.
8897 12:44:17.032133 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8898 12:44:17.035511 WARNING: RO_VPD is uninitialized or empty.
8899 12:44:17.041819 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8900 12:44:17.048500 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8901 12:44:17.061184 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8902 12:44:17.072962 BS: romstage times (exec / console): total (unknown) / 23006 ms
8903 12:44:17.073560
8904 12:44:17.073931
8905 12:44:17.082854 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8906 12:44:17.086271 ARM64: Exception handlers installed.
8907 12:44:17.090022 ARM64: Testing exception
8908 12:44:17.093301 ARM64: Done test exception
8909 12:44:17.093847 Enumerating buses...
8910 12:44:17.096434 Show all devs... Before device enumeration.
8911 12:44:17.099333 Root Device: enabled 1
8912 12:44:17.102694 CPU_CLUSTER: 0: enabled 1
8913 12:44:17.103152 CPU: 00: enabled 1
8914 12:44:17.105426 Compare with tree...
8915 12:44:17.105950 Root Device: enabled 1
8916 12:44:17.108876 CPU_CLUSTER: 0: enabled 1
8917 12:44:17.112102 CPU: 00: enabled 1
8918 12:44:17.112636 Root Device scanning...
8919 12:44:17.116342 scan_static_bus for Root Device
8920 12:44:17.119191 CPU_CLUSTER: 0 enabled
8921 12:44:17.122230 scan_static_bus for Root Device done
8922 12:44:17.125725 scan_bus: bus Root Device finished in 8 msecs
8923 12:44:17.126281 done
8924 12:44:17.132070 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8925 12:44:17.135525 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8926 12:44:17.142164 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8927 12:44:17.145491 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8928 12:44:17.148587 Allocating resources...
8929 12:44:17.152405 Reading resources...
8930 12:44:17.155104 Root Device read_resources bus 0 link: 0
8931 12:44:17.158535 DRAM rank0 size:0x80000000,
8932 12:44:17.159052 DRAM rank1 size=0x80000000
8933 12:44:17.161664 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8934 12:44:17.164935 CPU: 00 missing read_resources
8935 12:44:17.171541 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8936 12:44:17.175782 Root Device read_resources bus 0 link: 0 done
8937 12:44:17.176293 Done reading resources.
8938 12:44:17.181626 Show resources in subtree (Root Device)...After reading.
8939 12:44:17.185195 Root Device child on link 0 CPU_CLUSTER: 0
8940 12:44:17.188258 CPU_CLUSTER: 0 child on link 0 CPU: 00
8941 12:44:17.198123 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8942 12:44:17.198609 CPU: 00
8943 12:44:17.201336 Root Device assign_resources, bus 0 link: 0
8944 12:44:17.205433 CPU_CLUSTER: 0 missing set_resources
8945 12:44:17.211903 Root Device assign_resources, bus 0 link: 0 done
8946 12:44:17.212388 Done setting resources.
8947 12:44:17.218236 Show resources in subtree (Root Device)...After assigning values.
8948 12:44:17.221480 Root Device child on link 0 CPU_CLUSTER: 0
8949 12:44:17.225165 CPU_CLUSTER: 0 child on link 0 CPU: 00
8950 12:44:17.234089 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8951 12:44:17.234508 CPU: 00
8952 12:44:17.237900 Done allocating resources.
8953 12:44:17.246246 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8954 12:44:17.246778 Enabling resources...
8955 12:44:17.247134 done.
8956 12:44:17.251523 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8957 12:44:17.254647 Initializing devices...
8958 12:44:17.255060 Root Device init
8959 12:44:17.257773 init hardware done!
8960 12:44:17.258185 0x00000018: ctrlr->caps
8961 12:44:17.261315 52.000 MHz: ctrlr->f_max
8962 12:44:17.264845 0.400 MHz: ctrlr->f_min
8963 12:44:17.265358 0x40ff8080: ctrlr->voltages
8964 12:44:17.267531 sclk: 390625
8965 12:44:17.268020 Bus Width = 1
8966 12:44:17.268348 sclk: 390625
8967 12:44:17.270821 Bus Width = 1
8968 12:44:17.274209 Early init status = 3
8969 12:44:17.277275 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8970 12:44:17.281233 in-header: 03 fc 00 00 01 00 00 00
8971 12:44:17.284480 in-data: 00
8972 12:44:17.287216 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8973 12:44:17.291594 in-header: 03 fd 00 00 00 00 00 00
8974 12:44:17.295333 in-data:
8975 12:44:17.298805 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8976 12:44:17.301941 in-header: 03 fc 00 00 01 00 00 00
8977 12:44:17.305666 in-data: 00
8978 12:44:17.308832 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8979 12:44:17.313186 in-header: 03 fd 00 00 00 00 00 00
8980 12:44:17.317104 in-data:
8981 12:44:17.319239 [SSUSB] Setting up USB HOST controller...
8982 12:44:17.322802 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8983 12:44:17.326428 [SSUSB] phy power-on done.
8984 12:44:17.329378 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8985 12:44:17.336087 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8986 12:44:17.339229 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8987 12:44:17.345859 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8988 12:44:17.352909 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8989 12:44:17.359213 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8990 12:44:17.365743 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8991 12:44:17.372009 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8992 12:44:17.375594 SPM: binary array size = 0x9dc
8993 12:44:17.379543 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8994 12:44:17.385153 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8995 12:44:17.393496 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8996 12:44:17.398577 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8997 12:44:17.402162 configure_display: Starting display init
8998 12:44:17.435771 anx7625_power_on_init: Init interface.
8999 12:44:17.439400 anx7625_disable_pd_protocol: Disabled PD feature.
9000 12:44:17.443067 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9001 12:44:17.470888 anx7625_start_dp_work: Secure OCM version=00
9002 12:44:17.473444 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9003 12:44:17.488380 sp_tx_get_edid_block: EDID Block = 1
9004 12:44:17.591253 Extracted contents:
9005 12:44:17.594833 header: 00 ff ff ff ff ff ff 00
9006 12:44:17.597688 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9007 12:44:17.601229 version: 01 04
9008 12:44:17.604664 basic params: 95 1f 11 78 0a
9009 12:44:17.608008 chroma info: 76 90 94 55 54 90 27 21 50 54
9010 12:44:17.611313 established: 00 00 00
9011 12:44:17.618220 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9012 12:44:17.620847 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9013 12:44:17.627823 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9014 12:44:17.634033 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9015 12:44:17.640930 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9016 12:44:17.644300 extensions: 00
9017 12:44:17.644783 checksum: fb
9018 12:44:17.645169
9019 12:44:17.647802 Manufacturer: IVO Model 57d Serial Number 0
9020 12:44:17.650894 Made week 0 of 2020
9021 12:44:17.651352 EDID version: 1.4
9022 12:44:17.654138 Digital display
9023 12:44:17.657390 6 bits per primary color channel
9024 12:44:17.657857 DisplayPort interface
9025 12:44:17.661211 Maximum image size: 31 cm x 17 cm
9026 12:44:17.664173 Gamma: 220%
9027 12:44:17.664752 Check DPMS levels
9028 12:44:17.667337 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9029 12:44:17.674032 First detailed timing is preferred timing
9030 12:44:17.674588 Established timings supported:
9031 12:44:17.677136 Standard timings supported:
9032 12:44:17.680444 Detailed timings
9033 12:44:17.684222 Hex of detail: 383680a07038204018303c0035ae10000019
9034 12:44:17.690624 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9035 12:44:17.693934 0780 0798 07c8 0820 hborder 0
9036 12:44:17.697196 0438 043b 0447 0458 vborder 0
9037 12:44:17.700091 -hsync -vsync
9038 12:44:17.700596 Did detailed timing
9039 12:44:17.706637 Hex of detail: 000000000000000000000000000000000000
9040 12:44:17.709899 Manufacturer-specified data, tag 0
9041 12:44:17.713579 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9042 12:44:17.717279 ASCII string: InfoVision
9043 12:44:17.719960 Hex of detail: 000000fe00523134304e574635205248200a
9044 12:44:17.723604 ASCII string: R140NWF5 RH
9045 12:44:17.724082 Checksum
9046 12:44:17.726704 Checksum: 0xfb (valid)
9047 12:44:17.730501 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9048 12:44:17.733390 DSI data_rate: 832800000 bps
9049 12:44:17.740577 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9050 12:44:17.742949 anx7625_parse_edid: pixelclock(138800).
9051 12:44:17.746398 hactive(1920), hsync(48), hfp(24), hbp(88)
9052 12:44:17.749719 vactive(1080), vsync(12), vfp(3), vbp(17)
9053 12:44:17.753084 anx7625_dsi_config: config dsi.
9054 12:44:17.760105 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9055 12:44:17.773044 anx7625_dsi_config: success to config DSI
9056 12:44:17.776306 anx7625_dp_start: MIPI phy setup OK.
9057 12:44:17.780244 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9058 12:44:17.782874 mtk_ddp_mode_set invalid vrefresh 60
9059 12:44:17.786268 main_disp_path_setup
9060 12:44:17.786678 ovl_layer_smi_id_en
9061 12:44:17.789397 ovl_layer_smi_id_en
9062 12:44:17.789843 ccorr_config
9063 12:44:17.790281 aal_config
9064 12:44:17.793061 gamma_config
9065 12:44:17.793488 postmask_config
9066 12:44:17.796492 dither_config
9067 12:44:17.799795 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9068 12:44:17.806351 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9069 12:44:17.809921 Root Device init finished in 551 msecs
9070 12:44:17.813523 CPU_CLUSTER: 0 init
9071 12:44:17.819814 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9072 12:44:17.823547 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9073 12:44:17.826121 APU_MBOX 0x190000b0 = 0x10001
9074 12:44:17.829450 APU_MBOX 0x190001b0 = 0x10001
9075 12:44:17.832444 APU_MBOX 0x190005b0 = 0x10001
9076 12:44:17.835994 APU_MBOX 0x190006b0 = 0x10001
9077 12:44:17.839799 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9078 12:44:17.852032 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9079 12:44:17.864830 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9080 12:44:17.871447 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9081 12:44:17.882826 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9082 12:44:17.892192 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9083 12:44:17.895435 CPU_CLUSTER: 0 init finished in 81 msecs
9084 12:44:17.898303 Devices initialized
9085 12:44:17.901479 Show all devs... After init.
9086 12:44:17.902036 Root Device: enabled 1
9087 12:44:17.905614 CPU_CLUSTER: 0: enabled 1
9088 12:44:17.908878 CPU: 00: enabled 1
9089 12:44:17.911627 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9090 12:44:17.915567 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9091 12:44:17.918545 ELOG: NV offset 0x57f000 size 0x1000
9092 12:44:17.924911 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9093 12:44:17.932312 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9094 12:44:17.935572 ELOG: Event(17) added with size 13 at 2024-02-05 12:44:17 UTC
9095 12:44:17.939115 out: cmd=0x121: 03 db 21 01 00 00 00 00
9096 12:44:17.942591 in-header: 03 cb 00 00 2c 00 00 00
9097 12:44:17.956498 in-data: 98 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9098 12:44:17.962742 ELOG: Event(A1) added with size 10 at 2024-02-05 12:44:17 UTC
9099 12:44:17.969095 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9100 12:44:17.976143 ELOG: Event(A0) added with size 9 at 2024-02-05 12:44:18 UTC
9101 12:44:17.978889 elog_add_boot_reason: Logged dev mode boot
9102 12:44:17.982510 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9103 12:44:17.986272 Finalize devices...
9104 12:44:17.986828 Devices finalized
9105 12:44:17.992764 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9106 12:44:17.996394 Writing coreboot table at 0xffe64000
9107 12:44:17.998849 0. 000000000010a000-0000000000113fff: RAMSTAGE
9108 12:44:18.002821 1. 0000000040000000-00000000400fffff: RAM
9109 12:44:18.009310 2. 0000000040100000-000000004032afff: RAMSTAGE
9110 12:44:18.012422 3. 000000004032b000-00000000545fffff: RAM
9111 12:44:18.015804 4. 0000000054600000-000000005465ffff: BL31
9112 12:44:18.018801 5. 0000000054660000-00000000ffe63fff: RAM
9113 12:44:18.025539 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9114 12:44:18.029780 7. 0000000100000000-000000013fffffff: RAM
9115 12:44:18.032017 Passing 5 GPIOs to payload:
9116 12:44:18.035710 NAME | PORT | POLARITY | VALUE
9117 12:44:18.038120 EC in RW | 0x000000aa | low | undefined
9118 12:44:18.045119 EC interrupt | 0x00000005 | low | undefined
9119 12:44:18.048205 TPM interrupt | 0x000000ab | high | undefined
9120 12:44:18.055259 SD card detect | 0x00000011 | high | undefined
9121 12:44:18.058599 speaker enable | 0x00000093 | high | undefined
9122 12:44:18.062243 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9123 12:44:18.065252 in-header: 03 f8 00 00 02 00 00 00
9124 12:44:18.068255 in-data: 03 00
9125 12:44:18.069067 ADC[4]: Raw value=669327 ID=5
9126 12:44:18.071635 ADC[3]: Raw value=212549 ID=1
9127 12:44:18.075198 RAM Code: 0x51
9128 12:44:18.075764 ADC[6]: Raw value=74410 ID=0
9129 12:44:18.078438 ADC[5]: Raw value=211444 ID=1
9130 12:44:18.081478 SKU Code: 0x1
9131 12:44:18.085685 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 8923
9132 12:44:18.089431 coreboot table: 964 bytes.
9133 12:44:18.091766 IMD ROOT 0. 0xfffff000 0x00001000
9134 12:44:18.095056 IMD SMALL 1. 0xffffe000 0x00001000
9135 12:44:18.098317 RO MCACHE 2. 0xffffc000 0x00001104
9136 12:44:18.101733 CONSOLE 3. 0xfff7c000 0x00080000
9137 12:44:18.105289 FMAP 4. 0xfff7b000 0x00000452
9138 12:44:18.108056 TIME STAMP 5. 0xfff7a000 0x00000910
9139 12:44:18.111730 VBOOT WORK 6. 0xfff66000 0x00014000
9140 12:44:18.114910 RAMOOPS 7. 0xffe66000 0x00100000
9141 12:44:18.118572 COREBOOT 8. 0xffe64000 0x00002000
9142 12:44:18.119029 IMD small region:
9143 12:44:18.121261 IMD ROOT 0. 0xffffec00 0x00000400
9144 12:44:18.124653 VPD 1. 0xffffeb80 0x0000006c
9145 12:44:18.127923 MMC STATUS 2. 0xffffeb60 0x00000004
9146 12:44:18.134691 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9147 12:44:18.138424 Probing TPM: done!
9148 12:44:18.141850 Connected to device vid:did:rid of 1ae0:0028:00
9149 12:44:18.151693 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9150 12:44:18.155164 Initialized TPM device CR50 revision 0
9151 12:44:18.159156 Checking cr50 for pending updates
9152 12:44:18.162753 Reading cr50 TPM mode
9153 12:44:18.171870 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9154 12:44:18.177392 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9155 12:44:18.217128 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9156 12:44:18.220386 Checking segment from ROM address 0x40100000
9157 12:44:18.223903 Checking segment from ROM address 0x4010001c
9158 12:44:18.230246 Loading segment from ROM address 0x40100000
9159 12:44:18.230702 code (compression=0)
9160 12:44:18.240243 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9161 12:44:18.247149 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9162 12:44:18.247703 it's not compressed!
9163 12:44:18.254024 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9164 12:44:18.260107 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9165 12:44:18.277749 Loading segment from ROM address 0x4010001c
9166 12:44:18.278304 Entry Point 0x80000000
9167 12:44:18.280765 Loaded segments
9168 12:44:18.284189 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9169 12:44:18.291041 Jumping to boot code at 0x80000000(0xffe64000)
9170 12:44:18.297774 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9171 12:44:18.304639 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9172 12:44:18.312421 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9173 12:44:18.315478 Checking segment from ROM address 0x40100000
9174 12:44:18.318584 Checking segment from ROM address 0x4010001c
9175 12:44:18.325487 Loading segment from ROM address 0x40100000
9176 12:44:18.325965 code (compression=1)
9177 12:44:18.332246 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9178 12:44:18.342087 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9179 12:44:18.342662 using LZMA
9180 12:44:18.350136 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9181 12:44:18.356973 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9182 12:44:18.360823 Loading segment from ROM address 0x4010001c
9183 12:44:18.361376 Entry Point 0x54601000
9184 12:44:18.363643 Loaded segments
9185 12:44:18.366995 NOTICE: MT8192 bl31_setup
9186 12:44:18.374172 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9187 12:44:18.377943 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9188 12:44:18.380523 WARNING: region 0:
9189 12:44:18.384230 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9190 12:44:18.384837 WARNING: region 1:
9191 12:44:18.390388 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9192 12:44:18.394577 WARNING: region 2:
9193 12:44:18.397652 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9194 12:44:18.400825 WARNING: region 3:
9195 12:44:18.404305 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9196 12:44:18.407528 WARNING: region 4:
9197 12:44:18.413883 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9198 12:44:18.414436 WARNING: region 5:
9199 12:44:18.417400 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9200 12:44:18.420684 WARNING: region 6:
9201 12:44:18.423637 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9202 12:44:18.427090 WARNING: region 7:
9203 12:44:18.430556 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9204 12:44:18.436988 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9205 12:44:18.440939 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9206 12:44:18.444124 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9207 12:44:18.450946 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9208 12:44:18.453804 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9209 12:44:18.457560 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9210 12:44:18.464324 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9211 12:44:18.467654 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9212 12:44:18.474764 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9213 12:44:18.478683 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9214 12:44:18.480670 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9215 12:44:18.487650 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9216 12:44:18.490278 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9217 12:44:18.493817 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9218 12:44:18.500918 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9219 12:44:18.504037 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9220 12:44:18.510905 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9221 12:44:18.513948 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9222 12:44:18.517677 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9223 12:44:18.523401 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9224 12:44:18.526755 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9225 12:44:18.530215 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9226 12:44:18.538701 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9227 12:44:18.540250 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9228 12:44:18.546884 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9229 12:44:18.549863 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9230 12:44:18.557689 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9231 12:44:18.559966 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9232 12:44:18.563748 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9233 12:44:18.570527 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9234 12:44:18.573555 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9235 12:44:18.576329 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9236 12:44:18.583289 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9237 12:44:18.586480 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9238 12:44:18.590790 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9239 12:44:18.593562 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9240 12:44:18.599658 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9241 12:44:18.603648 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9242 12:44:18.607088 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9243 12:44:18.609656 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9244 12:44:18.616871 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9245 12:44:18.619929 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9246 12:44:18.623739 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9247 12:44:18.626705 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9248 12:44:18.633873 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9249 12:44:18.636531 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9250 12:44:18.640676 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9251 12:44:18.646260 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9252 12:44:18.649678 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9253 12:44:18.653365 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9254 12:44:18.659643 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9255 12:44:18.663850 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9256 12:44:18.669261 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9257 12:44:18.673269 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9258 12:44:18.679043 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9259 12:44:18.683469 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9260 12:44:18.686472 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9261 12:44:18.692871 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9262 12:44:18.695951 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9263 12:44:18.702844 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9264 12:44:18.706372 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9265 12:44:18.712304 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9266 12:44:18.716278 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9267 12:44:18.723091 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9268 12:44:18.726044 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9269 12:44:18.729583 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9270 12:44:18.736108 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9271 12:44:18.739510 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9272 12:44:18.746201 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9273 12:44:18.749727 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9274 12:44:18.755626 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9275 12:44:18.759194 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9276 12:44:18.762570 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9277 12:44:18.769903 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9278 12:44:18.772351 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9279 12:44:18.778855 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9280 12:44:18.782362 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9281 12:44:18.789256 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9282 12:44:18.792623 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9283 12:44:18.799386 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9284 12:44:18.802084 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9285 12:44:18.806207 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9286 12:44:18.812900 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9287 12:44:18.816263 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9288 12:44:18.822386 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9289 12:44:18.825491 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9290 12:44:18.832604 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9291 12:44:18.837006 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9292 12:44:18.838658 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9293 12:44:18.845849 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9294 12:44:18.849773 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9295 12:44:18.855654 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9296 12:44:18.859590 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9297 12:44:18.866193 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9298 12:44:18.869310 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9299 12:44:18.875408 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9300 12:44:18.878436 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9301 12:44:18.882598 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9302 12:44:18.885400 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9303 12:44:18.892622 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9304 12:44:18.895518 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9305 12:44:18.898781 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9306 12:44:18.905167 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9307 12:44:18.908476 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9308 12:44:18.912045 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9309 12:44:18.919008 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9310 12:44:18.922030 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9311 12:44:18.928959 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9312 12:44:18.932691 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9313 12:44:18.935620 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9314 12:44:18.941887 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9315 12:44:18.945067 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9316 12:44:18.952270 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9317 12:44:18.954892 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9318 12:44:18.959063 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9319 12:44:18.964928 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9320 12:44:18.968562 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9321 12:44:18.972366 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9322 12:44:18.978484 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9323 12:44:18.982486 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9324 12:44:18.985390 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9325 12:44:18.989444 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9326 12:44:18.995474 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9327 12:44:18.998746 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9328 12:44:19.002040 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9329 12:44:19.008754 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9330 12:44:19.011952 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9331 12:44:19.015287 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9332 12:44:19.022106 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9333 12:44:19.026312 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9334 12:44:19.033701 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9335 12:44:19.035325 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9336 12:44:19.039044 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9337 12:44:19.045343 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9338 12:44:19.048444 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9339 12:44:19.055105 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9340 12:44:19.059262 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9341 12:44:19.061483 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9342 12:44:19.069053 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9343 12:44:19.072405 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9344 12:44:19.075335 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9345 12:44:19.081451 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9346 12:44:19.085752 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9347 12:44:19.092605 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9348 12:44:19.095475 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9349 12:44:19.098750 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9350 12:44:19.105662 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9351 12:44:19.108861 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9352 12:44:19.115143 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9353 12:44:19.119179 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9354 12:44:19.121573 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9355 12:44:19.128501 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9356 12:44:19.131952 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9357 12:44:19.135634 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9358 12:44:19.142358 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9359 12:44:19.145119 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9360 12:44:19.153224 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9361 12:44:19.155267 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9362 12:44:19.158722 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9363 12:44:19.164836 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9364 12:44:19.168471 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9365 12:44:19.175367 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9366 12:44:19.178155 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9367 12:44:19.181642 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9368 12:44:19.188980 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9369 12:44:19.192039 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9370 12:44:19.198481 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9371 12:44:19.201370 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9372 12:44:19.204954 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9373 12:44:19.211624 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9374 12:44:19.215812 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9375 12:44:19.221966 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9376 12:44:19.224682 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9377 12:44:19.228616 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9378 12:44:19.234429 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9379 12:44:19.237507 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9380 12:44:19.244749 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9381 12:44:19.247877 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9382 12:44:19.251655 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9383 12:44:19.257642 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9384 12:44:19.261659 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9385 12:44:19.264295 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9386 12:44:19.271007 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9387 12:44:19.274173 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9388 12:44:19.280666 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9389 12:44:19.284378 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9390 12:44:19.287625 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9391 12:44:19.294051 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9392 12:44:19.297185 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9393 12:44:19.303630 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9394 12:44:19.307420 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9395 12:44:19.313221 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9396 12:44:19.317528 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9397 12:44:19.320412 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9398 12:44:19.327055 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9399 12:44:19.330028 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9400 12:44:19.336825 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9401 12:44:19.340926 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9402 12:44:19.346623 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9403 12:44:19.349828 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9404 12:44:19.353837 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9405 12:44:19.359696 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9406 12:44:19.362955 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9407 12:44:19.369508 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9408 12:44:19.373031 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9409 12:44:19.379572 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9410 12:44:19.382930 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9411 12:44:19.386115 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9412 12:44:19.392818 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9413 12:44:19.396117 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9414 12:44:19.403485 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9415 12:44:19.405751 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9416 12:44:19.412403 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9417 12:44:19.416093 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9418 12:44:19.420272 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9419 12:44:19.426199 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9420 12:44:19.429803 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9421 12:44:19.435508 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9422 12:44:19.438822 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9423 12:44:19.446162 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9424 12:44:19.449406 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9425 12:44:19.452869 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9426 12:44:19.460138 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9427 12:44:19.463087 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9428 12:44:19.469049 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9429 12:44:19.472405 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9430 12:44:19.475729 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9431 12:44:19.481920 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9432 12:44:19.485700 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9433 12:44:19.488551 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9434 12:44:19.495268 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9435 12:44:19.499340 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9436 12:44:19.502033 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9437 12:44:19.504944 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9438 12:44:19.511950 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9439 12:44:19.515155 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9440 12:44:19.521939 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9441 12:44:19.526160 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9442 12:44:19.529084 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9443 12:44:19.534937 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9444 12:44:19.538171 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9445 12:44:19.545469 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9446 12:44:19.547712 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9447 12:44:19.551963 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9448 12:44:19.557806 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9449 12:44:19.561568 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9450 12:44:19.565246 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9451 12:44:19.571138 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9452 12:44:19.575212 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9453 12:44:19.578601 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9454 12:44:19.584628 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9455 12:44:19.587500 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9456 12:44:19.594660 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9457 12:44:19.597702 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9458 12:44:19.601160 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9459 12:44:19.607183 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9460 12:44:19.610903 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9461 12:44:19.617387 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9462 12:44:19.620530 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9463 12:44:19.624138 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9464 12:44:19.630776 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9465 12:44:19.634706 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9466 12:44:19.637286 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9467 12:44:19.644039 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9468 12:44:19.647136 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9469 12:44:19.650341 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9470 12:44:19.656837 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9471 12:44:19.660002 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9472 12:44:19.664180 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9473 12:44:19.670321 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9474 12:44:19.673543 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9475 12:44:19.676912 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9476 12:44:19.680158 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9477 12:44:19.686875 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9478 12:44:19.690273 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9479 12:44:19.693669 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9480 12:44:19.696820 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9481 12:44:19.703043 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9482 12:44:19.706811 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9483 12:44:19.710194 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9484 12:44:19.716315 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9485 12:44:19.719505 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9486 12:44:19.723517 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9487 12:44:19.729569 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9488 12:44:19.733021 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9489 12:44:19.739856 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9490 12:44:19.742894 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9491 12:44:19.746169 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9492 12:44:19.752860 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9493 12:44:19.756845 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9494 12:44:19.762525 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9495 12:44:19.765592 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9496 12:44:19.768910 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9497 12:44:19.775868 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9498 12:44:19.779749 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9499 12:44:19.785551 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9500 12:44:19.789236 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9501 12:44:19.792731 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9502 12:44:19.799035 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9503 12:44:19.802024 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9504 12:44:19.809077 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9505 12:44:19.811883 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9506 12:44:19.818760 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9507 12:44:19.822498 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9508 12:44:19.825387 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9509 12:44:19.831985 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9510 12:44:19.835206 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9511 12:44:19.841734 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9512 12:44:19.845214 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9513 12:44:19.848429 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9514 12:44:19.854968 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9515 12:44:19.858915 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9516 12:44:19.865289 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9517 12:44:19.868624 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9518 12:44:19.875842 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9519 12:44:19.878840 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9520 12:44:19.881818 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9521 12:44:19.888141 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9522 12:44:19.891805 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9523 12:44:19.898743 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9524 12:44:19.901233 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9525 12:44:19.905292 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9526 12:44:19.912252 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9527 12:44:19.914349 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9528 12:44:19.921272 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9529 12:44:19.925255 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9530 12:44:19.931358 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9531 12:44:19.933879 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9532 12:44:19.937313 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9533 12:44:19.943988 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9534 12:44:19.948507 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9535 12:44:19.954085 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9536 12:44:19.958843 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9537 12:44:19.961308 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9538 12:44:19.968875 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9539 12:44:19.970244 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9540 12:44:19.977050 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9541 12:44:19.981285 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9542 12:44:19.984130 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9543 12:44:19.990140 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9544 12:44:19.993662 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9545 12:44:20.000454 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9546 12:44:20.003902 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9547 12:44:20.009887 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9548 12:44:20.013592 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9549 12:44:20.017187 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9550 12:44:20.023436 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9551 12:44:20.026539 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9552 12:44:20.034555 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9553 12:44:20.036386 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9554 12:44:20.043101 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9555 12:44:20.046156 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9556 12:44:20.049736 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9557 12:44:20.056093 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9558 12:44:20.059370 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9559 12:44:20.066289 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9560 12:44:20.069933 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9561 12:44:20.076211 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9562 12:44:20.079525 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9563 12:44:20.083057 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9564 12:44:20.089345 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9565 12:44:20.093203 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9566 12:44:20.099311 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9567 12:44:20.102965 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9568 12:44:20.109422 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9569 12:44:20.113166 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9570 12:44:20.119650 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9571 12:44:20.122734 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9572 12:44:20.125515 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9573 12:44:20.132267 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9574 12:44:20.135744 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9575 12:44:20.142503 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9576 12:44:20.145288 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9577 12:44:20.152214 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9578 12:44:20.155329 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9579 12:44:20.162071 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9580 12:44:20.165136 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9581 12:44:20.168788 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9582 12:44:20.175155 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9583 12:44:20.178868 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9584 12:44:20.185040 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9585 12:44:20.188843 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9586 12:44:20.195039 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9587 12:44:20.198465 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9588 12:44:20.206022 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9589 12:44:20.208607 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9590 12:44:20.212282 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9591 12:44:20.218671 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9592 12:44:20.221581 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9593 12:44:20.228491 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9594 12:44:20.231774 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9595 12:44:20.238621 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9596 12:44:20.241375 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9597 12:44:20.245327 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9598 12:44:20.251232 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9599 12:44:20.254894 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9600 12:44:20.261238 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9601 12:44:20.265151 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9602 12:44:20.271337 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9603 12:44:20.274368 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9604 12:44:20.280889 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9605 12:44:20.284351 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9606 12:44:20.287366 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9607 12:44:20.294132 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9608 12:44:20.297194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9609 12:44:20.304089 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9610 12:44:20.307565 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9611 12:44:20.314097 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9612 12:44:20.317035 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9613 12:44:20.324440 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9614 12:44:20.327151 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9615 12:44:20.333439 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9616 12:44:20.336938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9617 12:44:20.344139 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9618 12:44:20.347602 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9619 12:44:20.354358 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9620 12:44:20.357360 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9621 12:44:20.363490 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9622 12:44:20.367822 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9623 12:44:20.370562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9624 12:44:20.376470 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9625 12:44:20.379844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9626 12:44:20.386339 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9627 12:44:20.393262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9628 12:44:20.396247 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9629 12:44:20.403100 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9630 12:44:20.407269 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9631 12:44:20.414252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9632 12:44:20.416954 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9633 12:44:20.423403 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9634 12:44:20.426856 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9635 12:44:20.432893 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9636 12:44:20.435949 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9637 12:44:20.443075 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9638 12:44:20.445652 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9639 12:44:20.449065 INFO: [APUAPC] vio 0
9640 12:44:20.453153 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9641 12:44:20.455867 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9642 12:44:20.459607 INFO: [APUAPC] D0_APC_0: 0x400510
9643 12:44:20.462621 INFO: [APUAPC] D0_APC_1: 0x0
9644 12:44:20.466250 INFO: [APUAPC] D0_APC_2: 0x1540
9645 12:44:20.469354 INFO: [APUAPC] D0_APC_3: 0x0
9646 12:44:20.472578 INFO: [APUAPC] D1_APC_0: 0xffffffff
9647 12:44:20.475804 INFO: [APUAPC] D1_APC_1: 0xffffffff
9648 12:44:20.479277 INFO: [APUAPC] D1_APC_2: 0x3fffff
9649 12:44:20.482375 INFO: [APUAPC] D1_APC_3: 0x0
9650 12:44:20.486260 INFO: [APUAPC] D2_APC_0: 0xffffffff
9651 12:44:20.488840 INFO: [APUAPC] D2_APC_1: 0xffffffff
9652 12:44:20.492190 INFO: [APUAPC] D2_APC_2: 0x3fffff
9653 12:44:20.496051 INFO: [APUAPC] D2_APC_3: 0x0
9654 12:44:20.499300 INFO: [APUAPC] D3_APC_0: 0xffffffff
9655 12:44:20.502645 INFO: [APUAPC] D3_APC_1: 0xffffffff
9656 12:44:20.505326 INFO: [APUAPC] D3_APC_2: 0x3fffff
9657 12:44:20.509821 INFO: [APUAPC] D3_APC_3: 0x0
9658 12:44:20.512425 INFO: [APUAPC] D4_APC_0: 0xffffffff
9659 12:44:20.515448 INFO: [APUAPC] D4_APC_1: 0xffffffff
9660 12:44:20.519250 INFO: [APUAPC] D4_APC_2: 0x3fffff
9661 12:44:20.521959 INFO: [APUAPC] D4_APC_3: 0x0
9662 12:44:20.525088 INFO: [APUAPC] D5_APC_0: 0xffffffff
9663 12:44:20.528973 INFO: [APUAPC] D5_APC_1: 0xffffffff
9664 12:44:20.532163 INFO: [APUAPC] D5_APC_2: 0x3fffff
9665 12:44:20.535645 INFO: [APUAPC] D5_APC_3: 0x0
9666 12:44:20.538912 INFO: [APUAPC] D6_APC_0: 0xffffffff
9667 12:44:20.541413 INFO: [APUAPC] D6_APC_1: 0xffffffff
9668 12:44:20.545319 INFO: [APUAPC] D6_APC_2: 0x3fffff
9669 12:44:20.548560 INFO: [APUAPC] D6_APC_3: 0x0
9670 12:44:20.551455 INFO: [APUAPC] D7_APC_0: 0xffffffff
9671 12:44:20.555044 INFO: [APUAPC] D7_APC_1: 0xffffffff
9672 12:44:20.558096 INFO: [APUAPC] D7_APC_2: 0x3fffff
9673 12:44:20.561650 INFO: [APUAPC] D7_APC_3: 0x0
9674 12:44:20.564420 INFO: [APUAPC] D8_APC_0: 0xffffffff
9675 12:44:20.568523 INFO: [APUAPC] D8_APC_1: 0xffffffff
9676 12:44:20.571790 INFO: [APUAPC] D8_APC_2: 0x3fffff
9677 12:44:20.575157 INFO: [APUAPC] D8_APC_3: 0x0
9678 12:44:20.578198 INFO: [APUAPC] D9_APC_0: 0xffffffff
9679 12:44:20.581279 INFO: [APUAPC] D9_APC_1: 0xffffffff
9680 12:44:20.585287 INFO: [APUAPC] D9_APC_2: 0x3fffff
9681 12:44:20.588074 INFO: [APUAPC] D9_APC_3: 0x0
9682 12:44:20.591348 INFO: [APUAPC] D10_APC_0: 0xffffffff
9683 12:44:20.595331 INFO: [APUAPC] D10_APC_1: 0xffffffff
9684 12:44:20.597540 INFO: [APUAPC] D10_APC_2: 0x3fffff
9685 12:44:20.601413 INFO: [APUAPC] D10_APC_3: 0x0
9686 12:44:20.604806 INFO: [APUAPC] D11_APC_0: 0xffffffff
9687 12:44:20.607978 INFO: [APUAPC] D11_APC_1: 0xffffffff
9688 12:44:20.611365 INFO: [APUAPC] D11_APC_2: 0x3fffff
9689 12:44:20.614182 INFO: [APUAPC] D11_APC_3: 0x0
9690 12:44:20.617876 INFO: [APUAPC] D12_APC_0: 0xffffffff
9691 12:44:20.621546 INFO: [APUAPC] D12_APC_1: 0xffffffff
9692 12:44:20.624267 INFO: [APUAPC] D12_APC_2: 0x3fffff
9693 12:44:20.627423 INFO: [APUAPC] D12_APC_3: 0x0
9694 12:44:20.630394 INFO: [APUAPC] D13_APC_0: 0xffffffff
9695 12:44:20.634068 INFO: [APUAPC] D13_APC_1: 0xffffffff
9696 12:44:20.637360 INFO: [APUAPC] D13_APC_2: 0x3fffff
9697 12:44:20.640817 INFO: [APUAPC] D13_APC_3: 0x0
9698 12:44:20.643879 INFO: [APUAPC] D14_APC_0: 0xffffffff
9699 12:44:20.648271 INFO: [APUAPC] D14_APC_1: 0xffffffff
9700 12:44:20.651186 INFO: [APUAPC] D14_APC_2: 0x3fffff
9701 12:44:20.654618 INFO: [APUAPC] D14_APC_3: 0x0
9702 12:44:20.657722 INFO: [APUAPC] D15_APC_0: 0xffffffff
9703 12:44:20.660555 INFO: [APUAPC] D15_APC_1: 0xffffffff
9704 12:44:20.663953 INFO: [APUAPC] D15_APC_2: 0x3fffff
9705 12:44:20.667270 INFO: [APUAPC] D15_APC_3: 0x0
9706 12:44:20.670671 INFO: [APUAPC] APC_CON: 0x4
9707 12:44:20.673956 INFO: [NOCDAPC] D0_APC_0: 0x0
9708 12:44:20.677102 INFO: [NOCDAPC] D0_APC_1: 0x0
9709 12:44:20.677636 INFO: [NOCDAPC] D1_APC_0: 0x0
9710 12:44:20.680621 INFO: [NOCDAPC] D1_APC_1: 0xfff
9711 12:44:20.683532 INFO: [NOCDAPC] D2_APC_0: 0x0
9712 12:44:20.687155 INFO: [NOCDAPC] D2_APC_1: 0xfff
9713 12:44:20.690310 INFO: [NOCDAPC] D3_APC_0: 0x0
9714 12:44:20.693652 INFO: [NOCDAPC] D3_APC_1: 0xfff
9715 12:44:20.697004 INFO: [NOCDAPC] D4_APC_0: 0x0
9716 12:44:20.700343 INFO: [NOCDAPC] D4_APC_1: 0xfff
9717 12:44:20.703510 INFO: [NOCDAPC] D5_APC_0: 0x0
9718 12:44:20.707347 INFO: [NOCDAPC] D5_APC_1: 0xfff
9719 12:44:20.710323 INFO: [NOCDAPC] D6_APC_0: 0x0
9720 12:44:20.713551 INFO: [NOCDAPC] D6_APC_1: 0xfff
9721 12:44:20.714108 INFO: [NOCDAPC] D7_APC_0: 0x0
9722 12:44:20.716743 INFO: [NOCDAPC] D7_APC_1: 0xfff
9723 12:44:20.719998 INFO: [NOCDAPC] D8_APC_0: 0x0
9724 12:44:20.723202 INFO: [NOCDAPC] D8_APC_1: 0xfff
9725 12:44:20.726600 INFO: [NOCDAPC] D9_APC_0: 0x0
9726 12:44:20.730339 INFO: [NOCDAPC] D9_APC_1: 0xfff
9727 12:44:20.733355 INFO: [NOCDAPC] D10_APC_0: 0x0
9728 12:44:20.736776 INFO: [NOCDAPC] D10_APC_1: 0xfff
9729 12:44:20.739713 INFO: [NOCDAPC] D11_APC_0: 0x0
9730 12:44:20.742718 INFO: [NOCDAPC] D11_APC_1: 0xfff
9731 12:44:20.746324 INFO: [NOCDAPC] D12_APC_0: 0x0
9732 12:44:20.749299 INFO: [NOCDAPC] D12_APC_1: 0xfff
9733 12:44:20.753610 INFO: [NOCDAPC] D13_APC_0: 0x0
9734 12:44:20.754195 INFO: [NOCDAPC] D13_APC_1: 0xfff
9735 12:44:20.756234 INFO: [NOCDAPC] D14_APC_0: 0x0
9736 12:44:20.760165 INFO: [NOCDAPC] D14_APC_1: 0xfff
9737 12:44:20.762711 INFO: [NOCDAPC] D15_APC_0: 0x0
9738 12:44:20.766224 INFO: [NOCDAPC] D15_APC_1: 0xfff
9739 12:44:20.769264 INFO: [NOCDAPC] APC_CON: 0x4
9740 12:44:20.772751 INFO: [APUAPC] set_apusys_apc done
9741 12:44:20.776178 INFO: [DEVAPC] devapc_init done
9742 12:44:20.779195 INFO: GICv3 without legacy support detected.
9743 12:44:20.786310 INFO: ARM GICv3 driver initialized in EL3
9744 12:44:20.789119 INFO: Maximum SPI INTID supported: 639
9745 12:44:20.792341 INFO: BL31: Initializing runtime services
9746 12:44:20.798858 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9747 12:44:20.799326 INFO: SPM: enable CPC mode
9748 12:44:20.806603 INFO: mcdi ready for mcusys-off-idle and system suspend
9749 12:44:20.809649 INFO: BL31: Preparing for EL3 exit to normal world
9750 12:44:20.815548 INFO: Entry point address = 0x80000000
9751 12:44:20.816107 INFO: SPSR = 0x8
9752 12:44:20.822199
9753 12:44:20.822752
9754 12:44:20.823124
9755 12:44:20.825398 Starting depthcharge on Spherion...
9756 12:44:20.825861
9757 12:44:20.826229 Wipe memory regions:
9758 12:44:20.826573
9759 12:44:20.829545 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9760 12:44:20.830114 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9761 12:44:20.830564 Setting prompt string to ['asurada:']
9762 12:44:20.830996 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9763 12:44:20.831705 [0x00000040000000, 0x00000054600000)
9764 12:44:20.951302
9765 12:44:20.951864 [0x00000054660000, 0x00000080000000)
9766 12:44:21.210758
9767 12:44:21.211049 [0x000000821a7280, 0x000000ffe64000)
9768 12:44:21.956410
9769 12:44:21.957038 [0x00000100000000, 0x00000140000000)
9770 12:44:22.337389
9771 12:44:22.341048 Initializing XHCI USB controller at 0x11200000.
9772 12:44:23.378498
9773 12:44:23.382805 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9774 12:44:23.383270
9775 12:44:23.383632
9776 12:44:23.383967
9777 12:44:23.384823 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9779 12:44:23.486127 asurada: tftpboot 192.168.201.1 12703582/tftp-deploy-afe2j7qq/kernel/image.itb 12703582/tftp-deploy-afe2j7qq/kernel/cmdline
9780 12:44:23.486774 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9781 12:44:23.487486 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9782 12:44:23.491775 tftpboot 192.168.201.1 12703582/tftp-deploy-afe2j7qq/kernel/image.ittp-deploy-afe2j7qq/kernel/cmdline
9783 12:44:23.492258
9784 12:44:23.492618 Waiting for link
9785 12:44:23.652688
9786 12:44:23.653271 R8152: Initializing
9787 12:44:23.653636
9788 12:44:23.655416 Version 9 (ocp_data = 6010)
9789 12:44:23.655871
9790 12:44:23.658912 R8152: Done initializing
9791 12:44:23.659369
9792 12:44:23.659726 Adding net device
9793 12:44:25.540168
9794 12:44:25.540774 done.
9795 12:44:25.541148
9796 12:44:25.541488 MAC: 00:e0:4c:68:03:bd
9797 12:44:25.541813
9798 12:44:25.543340 Sending DHCP discover... done.
9799 12:44:25.543792
9800 12:44:28.990429 Waiting for reply... done.
9801 12:44:28.991033
9802 12:44:28.991409 Sending DHCP request... done.
9803 12:44:28.994032
9804 12:44:28.994588 Waiting for reply... done.
9805 12:44:28.994956
9806 12:44:28.997421 My ip is 192.168.201.16
9807 12:44:28.998009
9808 12:44:29.000518 The DHCP server ip is 192.168.201.1
9809 12:44:29.001147
9810 12:44:29.003797 TFTP server IP predefined by user: 192.168.201.1
9811 12:44:29.004358
9812 12:44:29.010940 Bootfile predefined by user: 12703582/tftp-deploy-afe2j7qq/kernel/image.itb
9813 12:44:29.011506
9814 12:44:29.013882 Sending tftp read request... done.
9815 12:44:29.014608
9816 12:44:29.022318 Waiting for the transfer...
9817 12:44:29.022794
9818 12:44:29.429111 00000000 ################################################################
9819 12:44:29.429647
9820 12:44:29.817324 00080000 ################################################################
9821 12:44:29.818141
9822 12:44:30.197840 00100000 ################################################################
9823 12:44:30.198383
9824 12:44:30.625314 00180000 ################################################################
9825 12:44:30.625842
9826 12:44:31.009729 00200000 ################################################################
9827 12:44:31.009880
9828 12:44:31.297534 00280000 ################################################################
9829 12:44:31.297672
9830 12:44:31.633725 00300000 ################################################################
9831 12:44:31.634236
9832 12:44:31.931482 00380000 ################################################################
9833 12:44:31.931624
9834 12:44:32.232199 00400000 ################################################################
9835 12:44:32.232339
9836 12:44:32.526166 00480000 ################################################################
9837 12:44:32.526310
9838 12:44:32.825211 00500000 ################################################################
9839 12:44:32.825347
9840 12:44:33.119823 00580000 ################################################################
9841 12:44:33.119963
9842 12:44:33.409289 00600000 ################################################################
9843 12:44:33.409429
9844 12:44:33.699380 00680000 ################################################################
9845 12:44:33.699516
9846 12:44:34.002080 00700000 ################################################################
9847 12:44:34.002209
9848 12:44:34.302017 00780000 ################################################################
9849 12:44:34.302149
9850 12:44:34.595102 00800000 ################################################################
9851 12:44:34.595229
9852 12:44:34.895892 00880000 ################################################################
9853 12:44:34.896023
9854 12:44:35.194543 00900000 ################################################################
9855 12:44:35.194668
9856 12:44:35.492306 00980000 ################################################################
9857 12:44:35.492435
9858 12:44:35.775194 00a00000 ################################################################
9859 12:44:35.775326
9860 12:44:36.068065 00a80000 ################################################################
9861 12:44:36.068200
9862 12:44:36.363310 00b00000 ################################################################
9863 12:44:36.363438
9864 12:44:36.657502 00b80000 ################################################################
9865 12:44:36.657638
9866 12:44:36.935619 00c00000 ################################################################
9867 12:44:36.935749
9868 12:44:37.186778 00c80000 ################################################################
9869 12:44:37.186906
9870 12:44:37.444647 00d00000 ################################################################
9871 12:44:37.444783
9872 12:44:37.709932 00d80000 ################################################################
9873 12:44:37.710064
9874 12:44:37.967635 00e00000 ################################################################
9875 12:44:37.967760
9876 12:44:38.238979 00e80000 ################################################################
9877 12:44:38.239114
9878 12:44:38.524825 00f00000 ################################################################
9879 12:44:38.524954
9880 12:44:38.780950 00f80000 ################################################################
9881 12:44:38.781081
9882 12:44:39.042893 01000000 ################################################################
9883 12:44:39.043026
9884 12:44:39.339258 01080000 ################################################################
9885 12:44:39.339386
9886 12:44:39.626618 01100000 ################################################################
9887 12:44:39.626748
9888 12:44:39.925215 01180000 ################################################################
9889 12:44:39.925357
9890 12:44:40.217321 01200000 ################################################################
9891 12:44:40.217466
9892 12:44:40.516986 01280000 ################################################################
9893 12:44:40.517114
9894 12:44:40.814514 01300000 ################################################################
9895 12:44:40.814654
9896 12:44:41.103735 01380000 ################################################################
9897 12:44:41.103880
9898 12:44:41.467326 01400000 ################################################################
9899 12:44:41.467847
9900 12:44:41.851851 01480000 ################################################################
9901 12:44:41.852358
9902 12:44:42.185562 01500000 ################################################################
9903 12:44:42.185698
9904 12:44:42.487486 01580000 ################################################################
9905 12:44:42.487638
9906 12:44:42.780121 01600000 ################################################################
9907 12:44:42.780261
9908 12:44:43.081068 01680000 ################################################################
9909 12:44:43.081205
9910 12:44:43.379115 01700000 ################################################################
9911 12:44:43.379285
9912 12:44:43.674439 01780000 ################################################################
9913 12:44:43.674580
9914 12:44:43.972555 01800000 ################################################################
9915 12:44:43.972725
9916 12:44:44.254683 01880000 ################################################################
9917 12:44:44.254823
9918 12:44:44.530196 01900000 ################################################################
9919 12:44:44.530339
9920 12:44:44.820206 01980000 ################################################################
9921 12:44:44.820343
9922 12:44:45.105617 01a00000 ################################################################
9923 12:44:45.105755
9924 12:44:45.407169 01a80000 ################################################################
9925 12:44:45.407310
9926 12:44:45.704933 01b00000 ################################################################
9927 12:44:45.705067
9928 12:44:46.003923 01b80000 ################################################################
9929 12:44:46.004063
9930 12:44:46.306077 01c00000 ################################################################
9931 12:44:46.306222
9932 12:44:46.606999 01c80000 ################################################################
9933 12:44:46.607141
9934 12:44:46.896535 01d00000 ################################################################
9935 12:44:46.896677
9936 12:44:47.184658 01d80000 ################################################################
9937 12:44:47.184838
9938 12:44:47.485047 01e00000 ################################################################
9939 12:44:47.485183
9940 12:44:47.779788 01e80000 ################################################################
9941 12:44:47.779932
9942 12:44:48.145564 01f00000 ################################################################
9943 12:44:48.146076
9944 12:44:48.477179 01f80000 ################################################################
9945 12:44:48.477449
9946 12:44:48.877906 02000000 ################################################################
9947 12:44:48.878418
9948 12:44:49.268288 02080000 ################################################################
9949 12:44:49.268837
9950 12:44:49.647638 02100000 ################################################################
9951 12:44:49.648297
9952 12:44:50.021731 02180000 ################################################################
9953 12:44:50.021876
9954 12:44:50.330435 02200000 ################################################################
9955 12:44:50.330956
9956 12:44:50.693681 02280000 ################################################################
9957 12:44:50.694190
9958 12:44:51.077767 02300000 ################################################################
9959 12:44:51.078282
9960 12:44:51.456702 02380000 ################################################################
9961 12:44:51.457257
9962 12:44:51.859209 02400000 ################################################################
9963 12:44:51.859728
9964 12:44:52.175996 02480000 ################################################################
9965 12:44:52.176139
9966 12:44:52.467003 02500000 ################################################################
9967 12:44:52.467154
9968 12:44:52.749678 02580000 ################################################################
9969 12:44:52.749813
9970 12:44:53.030512 02600000 ################################################################
9971 12:44:53.030646
9972 12:44:53.314444 02680000 ################################################################
9973 12:44:53.314586
9974 12:44:53.610685 02700000 ################################################################
9975 12:44:53.610821
9976 12:44:53.900499 02780000 ################################################################
9977 12:44:53.900640
9978 12:44:54.181380 02800000 ################################################################
9979 12:44:54.181517
9980 12:44:54.478962 02880000 ################################################################
9981 12:44:54.479103
9982 12:44:54.765011 02900000 ################################################################
9983 12:44:54.765148
9984 12:44:55.046037 02980000 ################################################################
9985 12:44:55.046173
9986 12:44:55.335912 02a00000 ################################################################
9987 12:44:55.336051
9988 12:44:55.627459 02a80000 ################################################################
9989 12:44:55.627601
9990 12:44:56.028043 02b00000 ################################################################
9991 12:44:56.028555
9992 12:44:56.409681 02b80000 ################################################################
9993 12:44:56.410199
9994 12:44:56.786765 02c00000 ################################################################
9995 12:44:56.787279
9996 12:44:57.166580 02c80000 ################################################################
9997 12:44:57.167092
9998 12:44:57.527310 02d00000 ################################################################
9999 12:44:57.527454
10000 12:44:57.830227 02d80000 ################################################################
10001 12:44:57.830382
10002 12:44:58.132516 02e00000 ################################################################
10003 12:44:58.132656
10004 12:44:58.434903 02e80000 ################################################################
10005 12:44:58.435042
10006 12:44:58.733138 02f00000 ################################################################
10007 12:44:58.733276
10008 12:44:59.069169 02f80000 ################################################################
10009 12:44:59.069682
10010 12:44:59.430025 03000000 ################################################################
10011 12:44:59.430170
10012 12:44:59.727643 03080000 ################################################################
10013 12:44:59.727784
10014 12:45:00.010300 03100000 ################################################################
10015 12:45:00.010446
10016 12:45:00.307229 03180000 ################################################################
10017 12:45:00.307739
10018 12:45:00.692136 03200000 ################################################################
10019 12:45:00.692645
10020 12:45:01.067444 03280000 ################################################################
10021 12:45:01.067961
10022 12:45:01.419193 03300000 ################################################################
10023 12:45:01.419373
10024 12:45:01.718333 03380000 ################################################################
10025 12:45:01.718480
10026 12:45:02.033587 03400000 ################################################################
10027 12:45:02.034100
10028 12:45:02.407131 03480000 ################################################################
10029 12:45:02.407695
10030 12:45:02.793917 03500000 ################################################################
10031 12:45:02.794434
10032 12:45:03.173523 03580000 ################################################################
10033 12:45:03.174035
10034 12:45:03.548778 03600000 ################################################################
10035 12:45:03.549293
10036 12:45:03.867739 03680000 ################################################################
10037 12:45:03.867881
10038 12:45:04.165581 03700000 ################################################################
10039 12:45:04.165725
10040 12:45:04.456030 03780000 ################################################################
10041 12:45:04.456172
10042 12:45:04.749665 03800000 ################################################################
10043 12:45:04.749812
10044 12:45:04.964366 03880000 ################################################# done.
10045 12:45:04.964546
10046 12:45:04.966213 The bootfile was 59642202 bytes long.
10047 12:45:04.966299
10048 12:45:04.969943 Sending tftp read request... done.
10049 12:45:04.970110
10050 12:45:04.972647 Waiting for the transfer...
10051 12:45:04.972833
10052 12:45:04.976213 00000000 # done.
10053 12:45:04.976396
10054 12:45:04.983308 Command line loaded dynamically from TFTP file: 12703582/tftp-deploy-afe2j7qq/kernel/cmdline
10055 12:45:04.983498
10056 12:45:04.996389 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10057 12:45:04.996634
10058 12:45:04.996800 Loading FIT.
10059 12:45:04.996940
10060 12:45:04.999325 Image ramdisk-1 has 47540031 bytes.
10061 12:45:04.999557
10062 12:45:05.002776 Image fdt-1 has 47278 bytes.
10063 12:45:05.002950
10064 12:45:05.005958 Image kernel-1 has 12052857 bytes.
10065 12:45:05.006151
10066 12:45:05.016685 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10067 12:45:05.017073
10068 12:45:05.032836 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10069 12:45:05.033416
10070 12:45:05.039737 Choosing best match conf-1 for compat google,spherion-rev3.
10071 12:45:05.040311
10072 12:45:05.047860 Connected to device vid:did:rid of 1ae0:0028:00
10073 12:45:05.055425
10074 12:45:05.058905 tpm_get_response: command 0x17b, return code 0x0
10075 12:45:05.059475
10076 12:45:05.062890 ec_init: CrosEC protocol v3 supported (256, 248)
10077 12:45:05.066581
10078 12:45:05.069963 tpm_cleanup: add release locality here.
10079 12:45:05.070537
10080 12:45:05.070908 Shutting down all USB controllers.
10081 12:45:05.074227
10082 12:45:05.074797 Removing current net device
10083 12:45:05.075175
10084 12:45:05.079588 Exiting depthcharge with code 4 at timestamp: 72523873
10085 12:45:05.080166
10086 12:45:05.083455 LZMA decompressing kernel-1 to 0x821a6718
10087 12:45:05.084022
10088 12:45:05.086095 LZMA decompressing kernel-1 to 0x40000000
10089 12:45:06.584841
10090 12:45:06.585406 jumping to kernel
10091 12:45:06.587591 end: 2.2.4 bootloader-commands (duration 00:00:46) [common]
10092 12:45:06.588186 start: 2.2.5 auto-login-action (timeout 00:03:40) [common]
10093 12:45:06.588623 Setting prompt string to ['Linux version [0-9]']
10094 12:45:06.589076 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10095 12:45:06.589520 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10096 12:45:06.635825
10097 12:45:06.638436 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10098 12:45:06.642371 start: 2.2.5.1 login-action (timeout 00:03:40) [common]
10099 12:45:06.642666 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10100 12:45:06.642835 Setting prompt string to []
10101 12:45:06.643013 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10102 12:45:06.643184 Using line separator: #'\n'#
10103 12:45:06.643321 No login prompt set.
10104 12:45:06.643464 Parsing kernel messages
10105 12:45:06.643591 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10106 12:45:06.643823 [login-action] Waiting for messages, (timeout 00:03:40)
10107 12:45:06.643973 Waiting using forced prompt support (timeout 00:01:50)
10108 12:45:06.662127 [ 0.000000] Linux version 6.1.75-cip14 (KernelCI@build-j98433-arm64-gcc-10-defconfig-arm64-chromebook-89n64) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Feb 5 12:20:06 UTC 2024
10109 12:45:06.665046 [ 0.000000] random: crng init done
10110 12:45:06.671825 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10111 12:45:06.675237 [ 0.000000] efi: UEFI not found.
10112 12:45:06.681873 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10113 12:45:06.688958 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10114 12:45:06.698153 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10115 12:45:06.708861 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10116 12:45:06.715027 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10117 12:45:06.721397 [ 0.000000] printk: bootconsole [mtk8250] enabled
10118 12:45:06.728066 [ 0.000000] NUMA: No NUMA configuration found
10119 12:45:06.734910 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10120 12:45:06.739006 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10121 12:45:06.741318 [ 0.000000] Zone ranges:
10122 12:45:06.747703 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10123 12:45:06.751893 [ 0.000000] DMA32 empty
10124 12:45:06.758374 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10125 12:45:06.760515 [ 0.000000] Movable zone start for each node
10126 12:45:06.764109 [ 0.000000] Early memory node ranges
10127 12:45:06.772227 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10128 12:45:06.777489 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10129 12:45:06.783715 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10130 12:45:06.790755 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10131 12:45:06.797092 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10132 12:45:06.804006 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10133 12:45:06.834700 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10134 12:45:06.842340 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10135 12:45:06.847642 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10136 12:45:06.851419 [ 0.000000] psci: probing for conduit method from DT.
10137 12:45:06.857347 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10138 12:45:06.861199 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10139 12:45:06.868079 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10140 12:45:06.871400 [ 0.000000] psci: SMC Calling Convention v1.2
10141 12:45:06.877669 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10142 12:45:06.880560 [ 0.000000] Detected VIPT I-cache on CPU0
10143 12:45:06.887376 [ 0.000000] CPU features: detected: GIC system register CPU interface
10144 12:45:06.894344 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10145 12:45:06.900810 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10146 12:45:06.906742 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10147 12:45:06.918009 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10148 12:45:06.923244 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10149 12:45:06.927013 [ 0.000000] alternatives: applying boot alternatives
10150 12:45:06.933239 [ 0.000000] Fallback order for Node 0: 0
10151 12:45:06.940377 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10152 12:45:06.943344 [ 0.000000] Policy zone: Normal
10153 12:45:06.956557 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10154 12:45:06.966434 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10155 12:45:06.977462 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10156 12:45:06.987279 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10157 12:45:06.994216 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10158 12:45:06.997406 <6>[ 0.000000] software IO TLB: area num 8.
10159 12:45:07.052812 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10160 12:45:07.133079 <6>[ 0.000000] Memory: 3806420K/4191232K available (17984K kernel code, 4118K rwdata, 19612K rodata, 8448K init, 616K bss, 352044K reserved, 32768K cma-reserved)
10161 12:45:07.139454 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10162 12:45:07.146060 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10163 12:45:07.149483 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10164 12:45:07.155978 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10165 12:45:07.162326 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10166 12:45:07.166192 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10167 12:45:07.177905 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10168 12:45:07.182634 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10169 12:45:07.189239 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10170 12:45:07.195603 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10171 12:45:07.199476 <6>[ 0.000000] GICv3: 608 SPIs implemented
10172 12:45:07.202713 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10173 12:45:07.208805 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10174 12:45:07.212140 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10175 12:45:07.218851 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10176 12:45:07.232535 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10177 12:45:07.241934 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10178 12:45:07.252064 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10179 12:45:07.259355 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10180 12:45:07.272315 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10181 12:45:07.279822 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10182 12:45:07.285926 <6>[ 0.009184] Console: colour dummy device 80x25
10183 12:45:07.295994 <6>[ 0.013911] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10184 12:45:07.302195 <6>[ 0.024352] pid_max: default: 32768 minimum: 301
10185 12:45:07.306132 <6>[ 0.029217] LSM: Security Framework initializing
10186 12:45:07.312439 <6>[ 0.034161] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10187 12:45:07.322397 <6>[ 0.041815] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10188 12:45:07.329083 <6>[ 0.051046] cblist_init_generic: Setting adjustable number of callback queues.
10189 12:45:07.335521 <6>[ 0.058489] cblist_init_generic: Setting shift to 3 and lim to 1.
10190 12:45:07.345412 <6>[ 0.064866] cblist_init_generic: Setting adjustable number of callback queues.
10191 12:45:07.348954 <6>[ 0.072339] cblist_init_generic: Setting shift to 3 and lim to 1.
10192 12:45:07.355639 <6>[ 0.078741] rcu: Hierarchical SRCU implementation.
10193 12:45:07.361879 <6>[ 0.083756] rcu: Max phase no-delay instances is 1000.
10194 12:45:07.368549 <6>[ 0.090813] EFI services will not be available.
10195 12:45:07.371574 <6>[ 0.095772] smp: Bringing up secondary CPUs ...
10196 12:45:07.379729 <6>[ 0.100824] Detected VIPT I-cache on CPU1
10197 12:45:07.386256 <6>[ 0.100893] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10198 12:45:07.392432 <6>[ 0.100923] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10199 12:45:07.396011 <6>[ 0.101265] Detected VIPT I-cache on CPU2
10200 12:45:07.405884 <6>[ 0.101318] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10201 12:45:07.412973 <6>[ 0.101336] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10202 12:45:07.415349 <6>[ 0.101597] Detected VIPT I-cache on CPU3
10203 12:45:07.422432 <6>[ 0.101643] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10204 12:45:07.429316 <6>[ 0.101657] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10205 12:45:07.435768 <6>[ 0.101961] CPU features: detected: Spectre-v4
10206 12:45:07.438677 <6>[ 0.101968] CPU features: detected: Spectre-BHB
10207 12:45:07.442521 <6>[ 0.101972] Detected PIPT I-cache on CPU4
10208 12:45:07.449645 <6>[ 0.102028] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10209 12:45:07.458877 <6>[ 0.102045] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10210 12:45:07.462125 <6>[ 0.102336] Detected PIPT I-cache on CPU5
10211 12:45:07.469360 <6>[ 0.102397] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10212 12:45:07.475430 <6>[ 0.102413] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10213 12:45:07.479280 <6>[ 0.102697] Detected PIPT I-cache on CPU6
10214 12:45:07.488694 <6>[ 0.102757] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10215 12:45:07.495599 <6>[ 0.102773] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10216 12:45:07.498190 <6>[ 0.103076] Detected PIPT I-cache on CPU7
10217 12:45:07.505849 <6>[ 0.103140] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10218 12:45:07.510875 <6>[ 0.103157] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10219 12:45:07.514468 <6>[ 0.103204] smp: Brought up 1 node, 8 CPUs
10220 12:45:07.521045 <6>[ 0.244755] SMP: Total of 8 processors activated.
10221 12:45:07.527770 <6>[ 0.249676] CPU features: detected: 32-bit EL0 Support
10222 12:45:07.535157 <6>[ 0.255071] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10223 12:45:07.540647 <6>[ 0.263871] CPU features: detected: Common not Private translations
10224 12:45:07.547647 <6>[ 0.270386] CPU features: detected: CRC32 instructions
10225 12:45:07.554237 <6>[ 0.275737] CPU features: detected: RCpc load-acquire (LDAPR)
10226 12:45:07.560349 <6>[ 0.281734] CPU features: detected: LSE atomic instructions
10227 12:45:07.564006 <6>[ 0.287532] CPU features: detected: Privileged Access Never
10228 12:45:07.570480 <6>[ 0.293312] CPU features: detected: RAS Extension Support
10229 12:45:07.577072 <6>[ 0.298932] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10230 12:45:07.583561 <6>[ 0.306152] CPU: All CPU(s) started at EL2
10231 12:45:07.586569 <6>[ 0.310468] alternatives: applying system-wide alternatives
10232 12:45:07.596600 <6>[ 0.320376] devtmpfs: initialized
10233 12:45:07.608279 <6>[ 0.328672] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10234 12:45:07.617882 <6>[ 0.338630] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10235 12:45:07.624776 <6>[ 0.346864] pinctrl core: initialized pinctrl subsystem
10236 12:45:07.629412 <6>[ 0.353511] DMI not present or invalid.
10237 12:45:07.634507 <6>[ 0.357914] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10238 12:45:07.644917 <6>[ 0.364674] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10239 12:45:07.651130 <6>[ 0.372121] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10240 12:45:07.660989 <6>[ 0.380211] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10241 12:45:07.664002 <6>[ 0.388371] audit: initializing netlink subsys (disabled)
10242 12:45:07.675107 <5>[ 0.394070] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10243 12:45:07.681223 <6>[ 0.394761] thermal_sys: Registered thermal governor 'step_wise'
10244 12:45:07.688172 <6>[ 0.402039] thermal_sys: Registered thermal governor 'power_allocator'
10245 12:45:07.691338 <6>[ 0.408293] cpuidle: using governor menu
10246 12:45:07.697150 <6>[ 0.419252] NET: Registered PF_QIPCRTR protocol family
10247 12:45:07.704300 <6>[ 0.424723] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10248 12:45:07.707943 <6>[ 0.431822] ASID allocator initialised with 32768 entries
10249 12:45:07.714471 <6>[ 0.438360] Serial: AMBA PL011 UART driver
10250 12:45:07.723397 <4>[ 0.447141] Trying to register duplicate clock ID: 134
10251 12:45:07.779967 <6>[ 0.506716] KASLR enabled
10252 12:45:07.794043 <6>[ 0.514446] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10253 12:45:07.801337 <6>[ 0.521459] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10254 12:45:07.807871 <6>[ 0.527950] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10255 12:45:07.815376 <6>[ 0.534953] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10256 12:45:07.820210 <6>[ 0.541442] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10257 12:45:07.827210 <6>[ 0.548447] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10258 12:45:07.833550 <6>[ 0.554933] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10259 12:45:07.840766 <6>[ 0.561936] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10260 12:45:07.843516 <6>[ 0.569445] ACPI: Interpreter disabled.
10261 12:45:07.852369 <6>[ 0.575865] iommu: Default domain type: Translated
10262 12:45:07.858568 <6>[ 0.580977] iommu: DMA domain TLB invalidation policy: strict mode
10263 12:45:07.862545 <5>[ 0.587638] SCSI subsystem initialized
10264 12:45:07.868441 <6>[ 0.591800] usbcore: registered new interface driver usbfs
10265 12:45:07.875237 <6>[ 0.597533] usbcore: registered new interface driver hub
10266 12:45:07.879689 <6>[ 0.603085] usbcore: registered new device driver usb
10267 12:45:07.885442 <6>[ 0.609191] pps_core: LinuxPPS API ver. 1 registered
10268 12:45:07.895546 <6>[ 0.614387] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10269 12:45:07.898934 <6>[ 0.623737] PTP clock support registered
10270 12:45:07.901930 <6>[ 0.627980] EDAC MC: Ver: 3.0.0
10271 12:45:07.909818 <6>[ 0.633100] FPGA manager framework
10272 12:45:07.916539 <6>[ 0.636781] Advanced Linux Sound Architecture Driver Initialized.
10273 12:45:07.920070 <6>[ 0.643563] vgaarb: loaded
10274 12:45:07.926357 <6>[ 0.646720] clocksource: Switched to clocksource arch_sys_counter
10275 12:45:07.930022 <5>[ 0.653156] VFS: Disk quotas dquot_6.6.0
10276 12:45:07.936595 <6>[ 0.657342] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10277 12:45:07.939492 <6>[ 0.664531] pnp: PnP ACPI: disabled
10278 12:45:07.947615 <6>[ 0.671189] NET: Registered PF_INET protocol family
10279 12:45:07.954069 <6>[ 0.676573] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10280 12:45:07.966505 <6>[ 0.686601] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10281 12:45:07.977072 <6>[ 0.695392] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10282 12:45:07.982859 <6>[ 0.703356] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10283 12:45:07.989529 <6>[ 0.711757] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10284 12:45:08.000503 <6>[ 0.720413] TCP: Hash tables configured (established 32768 bind 32768)
10285 12:45:08.006302 <6>[ 0.727270] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10286 12:45:08.013356 <6>[ 0.734293] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10287 12:45:08.021287 <6>[ 0.741814] NET: Registered PF_UNIX/PF_LOCAL protocol family
10288 12:45:08.027188 <6>[ 0.747962] RPC: Registered named UNIX socket transport module.
10289 12:45:08.029624 <6>[ 0.754117] RPC: Registered udp transport module.
10290 12:45:08.037112 <6>[ 0.759051] RPC: Registered tcp transport module.
10291 12:45:08.043082 <6>[ 0.763983] RPC: Registered tcp NFSv4.1 backchannel transport module.
10292 12:45:08.046481 <6>[ 0.770649] PCI: CLS 0 bytes, default 64
10293 12:45:08.049555 <6>[ 0.774988] Unpacking initramfs...
10294 12:45:08.075113 <6>[ 0.794957] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10295 12:45:08.084463 <6>[ 0.803603] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10296 12:45:08.087816 <6>[ 0.812440] kvm [1]: IPA Size Limit: 40 bits
10297 12:45:08.094434 <6>[ 0.816972] kvm [1]: GICv3: no GICV resource entry
10298 12:45:08.098011 <6>[ 0.821993] kvm [1]: disabling GICv2 emulation
10299 12:45:08.104823 <6>[ 0.826681] kvm [1]: GIC system register CPU interface enabled
10300 12:45:08.107600 <6>[ 0.832852] kvm [1]: vgic interrupt IRQ18
10301 12:45:08.114406 <6>[ 0.837216] kvm [1]: VHE mode initialized successfully
10302 12:45:08.120814 <5>[ 0.843664] Initialise system trusted keyrings
10303 12:45:08.127782 <6>[ 0.848440] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10304 12:45:08.134355 <6>[ 0.858453] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10305 12:45:08.140871 <5>[ 0.864851] NFS: Registering the id_resolver key type
10306 12:45:08.144421 <5>[ 0.870155] Key type id_resolver registered
10307 12:45:08.151264 <5>[ 0.874571] Key type id_legacy registered
10308 12:45:08.157902 <6>[ 0.878851] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10309 12:45:08.165241 <6>[ 0.885772] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10310 12:45:08.171208 <6>[ 0.893501] 9p: Installing v9fs 9p2000 file system support
10311 12:45:08.207230 <5>[ 0.930834] Key type asymmetric registered
10312 12:45:08.210311 <5>[ 0.935164] Asymmetric key parser 'x509' registered
10313 12:45:08.220258 <6>[ 0.940302] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10314 12:45:08.223942 <6>[ 0.947917] io scheduler mq-deadline registered
10315 12:45:08.228040 <6>[ 0.952702] io scheduler kyber registered
10316 12:45:08.245621 <6>[ 0.969500] EINJ: ACPI disabled.
10317 12:45:08.278827 <4>[ 0.994962] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10318 12:45:08.288143 <4>[ 1.005579] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10319 12:45:08.302573 <6>[ 1.026223] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10320 12:45:08.310656 <6>[ 1.034149] printk: console [ttyS0] disabled
10321 12:45:08.338670 <6>[ 1.058784] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10322 12:45:08.345020 <6>[ 1.068250] printk: console [ttyS0] enabled
10323 12:45:08.348955 <6>[ 1.068250] printk: console [ttyS0] enabled
10324 12:45:08.355098 <6>[ 1.077148] printk: bootconsole [mtk8250] disabled
10325 12:45:08.358613 <6>[ 1.077148] printk: bootconsole [mtk8250] disabled
10326 12:45:08.364930 <6>[ 1.088178] SuperH (H)SCI(F) driver initialized
10327 12:45:08.368415 <6>[ 1.093449] msm_serial: driver initialized
10328 12:45:08.382037 <6>[ 1.102311] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10329 12:45:08.392301 <6>[ 1.110857] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10330 12:45:08.398394 <6>[ 1.119399] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10331 12:45:08.408857 <6>[ 1.128028] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10332 12:45:08.415449 <6>[ 1.136734] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10333 12:45:08.424884 <6>[ 1.145447] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10334 12:45:08.435887 <6>[ 1.153988] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10335 12:45:08.441724 <6>[ 1.162779] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10336 12:45:08.451490 <6>[ 1.171323] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10337 12:45:08.463023 <6>[ 1.186549] loop: module loaded
10338 12:45:08.469624 <6>[ 1.192410] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10339 12:45:08.492078 <4>[ 1.215685] mtk-pmic-keys: Failed to locate of_node [id: -1]
10340 12:45:08.498673 <6>[ 1.222453] megasas: 07.719.03.00-rc1
10341 12:45:08.508946 <6>[ 1.231941] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10342 12:45:08.514996 <6>[ 1.238095] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10343 12:45:08.531176 <6>[ 1.254787] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10344 12:45:08.587706 <6>[ 1.304698] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10345 12:45:10.086994 <6>[ 2.810584] Freeing initrd memory: 46420K
10346 12:45:10.097285 <6>[ 2.821026] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10347 12:45:10.108045 <6>[ 2.831801] tun: Universal TUN/TAP device driver, 1.6
10348 12:45:10.111659 <6>[ 2.837849] thunder_xcv, ver 1.0
10349 12:45:10.114690 <6>[ 2.841353] thunder_bgx, ver 1.0
10350 12:45:10.117537 <6>[ 2.844849] nicpf, ver 1.0
10351 12:45:10.128093 <6>[ 2.848865] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10352 12:45:10.131527 <6>[ 2.856340] hns3: Copyright (c) 2017 Huawei Corporation.
10353 12:45:10.138649 <6>[ 2.861927] hclge is initializing
10354 12:45:10.141579 <6>[ 2.865501] e1000: Intel(R) PRO/1000 Network Driver
10355 12:45:10.148062 <6>[ 2.870630] e1000: Copyright (c) 1999-2006 Intel Corporation.
10356 12:45:10.151319 <6>[ 2.876648] e1000e: Intel(R) PRO/1000 Network Driver
10357 12:45:10.158293 <6>[ 2.881864] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10358 12:45:10.166211 <6>[ 2.888049] igb: Intel(R) Gigabit Ethernet Network Driver
10359 12:45:10.171308 <6>[ 2.893699] igb: Copyright (c) 2007-2014 Intel Corporation.
10360 12:45:10.177746 <6>[ 2.899535] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10361 12:45:10.184586 <6>[ 2.906053] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10362 12:45:10.188167 <6>[ 2.912514] sky2: driver version 1.30
10363 12:45:10.194473 <6>[ 2.917495] VFIO - User Level meta-driver version: 0.3
10364 12:45:10.201920 <6>[ 2.925704] usbcore: registered new interface driver usb-storage
10365 12:45:10.208911 <6>[ 2.932151] usbcore: registered new device driver onboard-usb-hub
10366 12:45:10.218111 <6>[ 2.941293] mt6397-rtc mt6359-rtc: registered as rtc0
10367 12:45:10.227553 <6>[ 2.946761] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-05T12:45:10 UTC (1707137110)
10368 12:45:10.231438 <6>[ 2.956324] i2c_dev: i2c /dev entries driver
10369 12:45:10.247453 <6>[ 2.967983] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10370 12:45:10.267209 <6>[ 2.990958] cpu cpu0: EM: created perf domain
10371 12:45:10.270337 <6>[ 2.995871] cpu cpu4: EM: created perf domain
10372 12:45:10.279213 <6>[ 3.001387] sdhci: Secure Digital Host Controller Interface driver
10373 12:45:10.284223 <6>[ 3.007820] sdhci: Copyright(c) Pierre Ossman
10374 12:45:10.290823 <6>[ 3.012725] Synopsys Designware Multimedia Card Interface Driver
10375 12:45:10.297176 <6>[ 3.019312] sdhci-pltfm: SDHCI platform and OF driver helper
10376 12:45:10.301078 <6>[ 3.019374] mmc0: CQHCI version 5.10
10377 12:45:10.307580 <6>[ 3.029467] ledtrig-cpu: registered to indicate activity on CPUs
10378 12:45:10.313897 <6>[ 3.036484] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10379 12:45:10.320267 <6>[ 3.043514] usbcore: registered new interface driver usbhid
10380 12:45:10.323525 <6>[ 3.049334] usbhid: USB HID core driver
10381 12:45:10.330355 <6>[ 3.053529] spi_master spi0: will run message pump with realtime priority
10382 12:45:10.376069 <6>[ 3.092920] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10383 12:45:10.394900 <6>[ 3.108875] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10384 12:45:10.397987 <6>[ 3.123736] mmc0: Command Queue Engine enabled
10385 12:45:10.405359 <6>[ 3.123774] cros-ec-spi spi0.0: Chrome EC device registered
10386 12:45:10.411755 <6>[ 3.128502] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10387 12:45:10.418338 <6>[ 3.141580] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10388 12:45:10.428443 <6>[ 3.147921] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10389 12:45:10.436078 <6>[ 3.154201] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10390 12:45:10.438331 <6>[ 3.158229] NET: Registered PF_PACKET protocol family
10391 12:45:10.445249 <6>[ 3.164637] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10392 12:45:10.449565 <6>[ 3.168546] 9pnet: Installing 9P2000 support
10393 12:45:10.455153 <6>[ 3.174352] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10394 12:45:10.459107 <5>[ 3.178242] Key type dns_resolver registered
10395 12:45:10.465070 <6>[ 3.184112] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10396 12:45:10.468293 <6>[ 3.188487] registered taskstats version 1
10397 12:45:10.475246 <5>[ 3.198836] Loading compiled-in X.509 certificates
10398 12:45:10.502251 <4>[ 3.219574] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10399 12:45:10.512636 <4>[ 3.230247] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10400 12:45:10.518777 <3>[ 3.240775] debugfs: File 'uA_load' in directory '/' already present!
10401 12:45:10.525181 <3>[ 3.247474] debugfs: File 'min_uV' in directory '/' already present!
10402 12:45:10.532450 <3>[ 3.254082] debugfs: File 'max_uV' in directory '/' already present!
10403 12:45:10.538336 <3>[ 3.260747] debugfs: File 'constraint_flags' in directory '/' already present!
10404 12:45:10.549573 <3>[ 3.270152] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10405 12:45:10.558418 <6>[ 3.282315] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10406 12:45:10.565396 <6>[ 3.288993] xhci-mtk 11200000.usb: xHCI Host Controller
10407 12:45:10.572885 <6>[ 3.294475] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10408 12:45:10.581787 <6>[ 3.302300] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10409 12:45:10.588146 <6>[ 3.311721] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10410 12:45:10.595602 <6>[ 3.317771] xhci-mtk 11200000.usb: xHCI Host Controller
10411 12:45:10.601635 <6>[ 3.323248] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10412 12:45:10.607975 <6>[ 3.330898] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10413 12:45:10.614580 <6>[ 3.338525] hub 1-0:1.0: USB hub found
10414 12:45:10.618553 <6>[ 3.342537] hub 1-0:1.0: 1 port detected
10415 12:45:10.624667 <6>[ 3.346812] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10416 12:45:10.632316 <6>[ 3.355515] hub 2-0:1.0: USB hub found
10417 12:45:10.635161 <6>[ 3.359537] hub 2-0:1.0: 1 port detected
10418 12:45:10.643695 <6>[ 3.367077] mtk-msdc 11f70000.mmc: Got CD GPIO
10419 12:45:10.653861 <6>[ 3.373138] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10420 12:45:10.659467 <6>[ 3.381166] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10421 12:45:10.670008 <4>[ 3.389063] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10422 12:45:10.677222 <6>[ 3.398582] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10423 12:45:10.686217 <6>[ 3.406661] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10424 12:45:10.693800 <6>[ 3.414671] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10425 12:45:10.703159 <6>[ 3.422586] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10426 12:45:10.710088 <6>[ 3.430402] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10427 12:45:10.720413 <6>[ 3.438220] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10428 12:45:10.726970 <6>[ 3.448148] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10429 12:45:10.735877 <6>[ 3.456514] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10430 12:45:10.743204 <6>[ 3.464859] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10431 12:45:10.753202 <6>[ 3.473204] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10432 12:45:10.762142 <6>[ 3.481543] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10433 12:45:10.769596 <6>[ 3.489881] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10434 12:45:10.779683 <6>[ 3.498219] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10435 12:45:10.785545 <6>[ 3.506558] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10436 12:45:10.795548 <6>[ 3.514896] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10437 12:45:10.801990 <6>[ 3.523248] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10438 12:45:10.811676 <6>[ 3.531587] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10439 12:45:10.818206 <6>[ 3.539924] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10440 12:45:10.828287 <6>[ 3.548263] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10441 12:45:10.835461 <6>[ 3.556601] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10442 12:45:10.845492 <6>[ 3.564939] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10443 12:45:10.851236 <6>[ 3.573700] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10444 12:45:10.858339 <6>[ 3.580833] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10445 12:45:10.865003 <6>[ 3.587574] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10446 12:45:10.872479 <6>[ 3.594307] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10447 12:45:10.878641 <6>[ 3.601222] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10448 12:45:10.887410 <6>[ 3.608059] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10449 12:45:10.898012 <6>[ 3.617188] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10450 12:45:10.907509 <6>[ 3.626307] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10451 12:45:10.917070 <6>[ 3.635600] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10452 12:45:10.924654 <6>[ 3.645067] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10453 12:45:10.933895 <6>[ 3.654533] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10454 12:45:10.943935 <6>[ 3.663652] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10455 12:45:10.954043 <6>[ 3.673117] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10456 12:45:10.963825 <6>[ 3.682236] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10457 12:45:10.973235 <6>[ 3.691531] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10458 12:45:10.983069 <6>[ 3.701690] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10459 12:45:10.993215 <6>[ 3.713397] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10460 12:45:11.050159 <6>[ 3.770982] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10461 12:45:11.205144 <6>[ 3.928738] hub 1-1:1.0: USB hub found
10462 12:45:11.208919 <6>[ 3.933258] hub 1-1:1.0: 4 ports detected
10463 12:45:11.217817 <6>[ 3.941469] hub 1-1:1.0: USB hub found
10464 12:45:11.220668 <6>[ 3.945874] hub 1-1:1.0: 4 ports detected
10465 12:45:11.334237 <6>[ 4.055384] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10466 12:45:11.360915 <6>[ 4.084900] hub 2-1:1.0: USB hub found
10467 12:45:11.365558 <6>[ 4.089406] hub 2-1:1.0: 3 ports detected
10468 12:45:11.373471 <6>[ 4.097572] hub 2-1:1.0: USB hub found
10469 12:45:11.376816 <6>[ 4.102021] hub 2-1:1.0: 3 ports detected
10470 12:45:11.550263 <6>[ 4.271013] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10471 12:45:11.682696 <6>[ 4.406038] hub 1-1.4:1.0: USB hub found
10472 12:45:11.685156 <6>[ 4.410631] hub 1-1.4:1.0: 2 ports detected
10473 12:45:11.694190 <6>[ 4.417998] hub 1-1.4:1.0: USB hub found
10474 12:45:11.696642 <6>[ 4.422553] hub 1-1.4:1.0: 2 ports detected
10475 12:45:11.766453 <6>[ 4.487061] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10476 12:45:11.994169 <6>[ 4.715030] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10477 12:45:12.186113 <6>[ 4.906997] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10478 12:45:23.287741 <6>[ 16.015998] ALSA device list:
10479 12:45:23.293488 <6>[ 16.019285] No soundcards found.
10480 12:45:23.302279 <6>[ 16.027114] Freeing unused kernel memory: 8448K
10481 12:45:23.304621 <6>[ 16.032104] Run /init as init process
10482 12:45:23.354726 <6>[ 16.080476] NET: Registered PF_INET6 protocol family
10483 12:45:23.362628 <6>[ 16.087346] Segment Routing with IPv6
10484 12:45:23.364900 <6>[ 16.091415] In-situ OAM (IOAM) with IPv6
10485 12:45:23.400451 <30>[ 16.105568] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10486 12:45:23.403223 <30>[ 16.129306] systemd[1]: Detected architecture arm64.
10487 12:45:23.403628
10488 12:45:23.409415 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10489 12:45:23.409881
10490 12:45:23.430467 <30>[ 16.155073] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10491 12:45:23.558589 <30>[ 16.280596] systemd[1]: Queued start job for default target Graphical Interface.
10492 12:45:23.582573 <30>[ 16.308108] systemd[1]: Created slice system-getty.slice.
10493 12:45:23.589074 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10494 12:45:23.605925 <30>[ 16.331581] systemd[1]: Created slice system-modprobe.slice.
10495 12:45:23.613388 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10496 12:45:23.630872 <30>[ 16.356072] systemd[1]: Created slice system-serial\x2dgetty.slice.
10497 12:45:23.640703 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10498 12:45:23.654615 <30>[ 16.380308] systemd[1]: Created slice User and Session Slice.
10499 12:45:23.661412 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10500 12:45:23.681654 <30>[ 16.403192] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10501 12:45:23.690835 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10502 12:45:23.706608 <30>[ 16.427119] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10503 12:45:23.711825 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10504 12:45:23.733018 <30>[ 16.451112] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10505 12:45:23.740040 <30>[ 16.463272] systemd[1]: Reached target Local Encrypted Volumes.
10506 12:45:23.745409 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10507 12:45:23.761775 <30>[ 16.487484] systemd[1]: Reached target Paths.
10508 12:45:23.768761 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10509 12:45:23.781662 <30>[ 16.507026] systemd[1]: Reached target Remote File Systems.
10510 12:45:23.788561 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10511 12:45:23.806739 <30>[ 16.531370] systemd[1]: Reached target Slices.
10512 12:45:23.812513 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10513 12:45:23.825252 <30>[ 16.551066] systemd[1]: Reached target Swap.
10514 12:45:23.829206 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10515 12:45:23.849308 <30>[ 16.571575] systemd[1]: Listening on initctl Compatibility Named Pipe.
10516 12:45:23.856143 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10517 12:45:23.862725 <30>[ 16.586813] systemd[1]: Listening on Journal Audit Socket.
10518 12:45:23.869830 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10519 12:45:23.882166 <30>[ 16.607493] systemd[1]: Listening on Journal Socket (/dev/log).
10520 12:45:23.889160 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10521 12:45:23.907328 <30>[ 16.632229] systemd[1]: Listening on Journal Socket.
10522 12:45:23.913037 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10523 12:45:23.929837 <30>[ 16.651740] systemd[1]: Listening on Network Service Netlink Socket.
10524 12:45:23.936203 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10525 12:45:23.949989 <30>[ 16.675589] systemd[1]: Listening on udev Control Socket.
10526 12:45:23.956420 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10527 12:45:23.974884 <30>[ 16.700079] systemd[1]: Listening on udev Kernel Socket.
10528 12:45:23.981484 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10529 12:45:24.038374 <30>[ 16.763340] systemd[1]: Mounting Huge Pages File System...
10530 12:45:24.044652 Mounting [0;1;39mHuge Pages File System[0m...
10531 12:45:24.061889 <30>[ 16.787358] systemd[1]: Mounting POSIX Message Queue File System...
10532 12:45:24.068832 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10533 12:45:24.087203 <30>[ 16.812743] systemd[1]: Mounting Kernel Debug File System...
10534 12:45:24.094348 Mounting [0;1;39mKernel Debug File System[0m...
10535 12:45:24.112881 <30>[ 16.835295] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10536 12:45:24.123810 <30>[ 16.846064] systemd[1]: Starting Create list of static device nodes for the current kernel...
10537 12:45:24.131011 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10538 12:45:24.148832 <30>[ 16.873896] systemd[1]: Starting Load Kernel Module configfs...
10539 12:45:24.154993 Starting [0;1;39mLoad Kernel Module configfs[0m...
10540 12:45:24.173783 <30>[ 16.899140] systemd[1]: Starting Load Kernel Module drm...
10541 12:45:24.180317 Starting [0;1;39mLoad Kernel Module drm[0m...
10542 12:45:24.197238 <30>[ 16.919353] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10543 12:45:24.222495 <30>[ 16.947753] systemd[1]: Starting Journal Service...
10544 12:45:24.225537 Starting [0;1;39mJournal Service[0m...
10545 12:45:24.246448 <30>[ 16.971726] systemd[1]: Starting Load Kernel Modules...
10546 12:45:24.252781 Starting [0;1;39mLoad Kernel Modules[0m...
10547 12:45:24.273178 <30>[ 16.995249] systemd[1]: Starting Remount Root and Kernel File Systems...
10548 12:45:24.280444 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10549 12:45:24.297120 <30>[ 17.022053] systemd[1]: Starting Coldplug All udev Devices...
10550 12:45:24.303399 Starting [0;1;39mColdplug All udev Devices[0m...
10551 12:45:24.321063 <30>[ 17.046860] systemd[1]: Started Journal Service.
10552 12:45:24.327889 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10553 12:45:24.345630 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10554 12:45:24.351726 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10555 12:45:24.366712 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10556 12:45:24.387594 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10557 12:45:24.404822 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10558 12:45:24.425187 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10559 12:45:24.443228 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10560 12:45:24.463331 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10561 12:45:24.477587 See 'systemctl status systemd-remount-fs.service' for details.
10562 12:45:24.519904 Mounting [0;1;39mKernel Configuration File System[0m...
10563 12:45:24.540046 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10564 12:45:24.552970 <46>[ 17.275389] systemd-journald[176]: Received client request to flush runtime journal.
10565 12:45:24.562569 Starting [0;1;39mLoad/Save Random Seed[0m...
10566 12:45:24.584913 Starting [0;1;39mApply Kernel Variables[0m...
10567 12:45:24.611272 Starting [0;1;39mCreate System Users[0m...
10568 12:45:24.634538 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10569 12:45:24.650388 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10570 12:45:24.674412 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10571 12:45:24.687488 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10572 12:45:24.703332 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10573 12:45:24.718965 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10574 12:45:24.755179 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10575 12:45:24.776765 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10576 12:45:24.790115 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10577 12:45:24.806004 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10578 12:45:24.859396 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10579 12:45:24.888517 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10580 12:45:24.906154 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10581 12:45:24.926951 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10582 12:45:24.977585 Starting [0;1;39mNetwork Service[0m...
10583 12:45:24.999231 Starting [0;1;39mNetwork Time Synchronization[0m...
10584 12:45:25.030629 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10585 12:45:25.047345 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10586 12:45:25.080479 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10587 12:45:25.106432 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10588 12:45:25.120079 <6>[ 17.842235] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10589 12:45:25.127101 <6>[ 17.842343] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10590 12:45:25.136555 <6>[ 17.857329] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10591 12:45:25.143996 <6>[ 17.866041] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10592 12:45:25.150190 <6>[ 17.868724] remoteproc remoteproc0: scp is available
10593 12:45:25.156359 [[0;32m OK [<6>[ 17.880255] remoteproc remoteproc0: powering up scp
10594 12:45:25.165780 0m] Found device<6>[ 17.887194] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10595 12:45:25.176224 [0;1;39m/dev/t<4>[ 17.891537] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10596 12:45:25.179853 <6>[ 17.893421] mc: Linux media interface: v0.10
10597 12:45:25.186158 <6>[ 17.896494] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10598 12:45:25.186747 tyS0[0m.
10599 12:45:25.192560 <3>[ 17.915369] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10600 12:45:25.202616 <4>[ 17.917821] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10601 12:45:25.209578 <3>[ 17.924357] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10602 12:45:25.215293 <3>[ 17.924365] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10603 12:45:25.229133 [[0;32m OK [0m] Created slic<3>[ 17.949744] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10604 12:45:25.239115 e [0;1;39msyste<6>[ 17.953646] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10605 12:45:25.245534 <3>[ 17.959141] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10606 12:45:25.255642 m-systemd\x2dbac<3>[ 17.976371] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10607 12:45:25.265557 klight.slice[0m<3>[ 17.985734] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10608 12:45:25.266119 .
10609 12:45:25.272066 <6>[ 17.989314] usbcore: registered new device driver r8152-cfgselector
10610 12:45:25.279106 <3>[ 17.995314] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10611 12:45:25.285446 <6>[ 17.995707] videodev: Linux video capture interface: v2.00
10612 12:45:25.292306 <3>[ 17.996873] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10613 12:45:25.302017 <3>[ 17.997799] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10614 12:45:25.309162 <3>[ 17.997807] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10615 12:45:25.318369 <3>[ 17.997810] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10616 12:45:25.325329 <3>[ 17.999474] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10617 12:45:25.335327 <3>[ 17.999482] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10618 12:45:25.342155 <3>[ 17.999485] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10619 12:45:25.348972 <3>[ 17.999489] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10620 12:45:25.359030 <3>[ 17.999491] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10621 12:45:25.365926 <6>[ 17.999645] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10622 12:45:25.373136 <6>[ 17.999654] pci_bus 0000:00: root bus resource [bus 00-ff]
10623 12:45:25.378802 <6>[ 17.999661] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10624 12:45:25.389131 <6>[ 17.999666] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10625 12:45:25.395261 <6>[ 17.999709] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10626 12:45:25.402423 <6>[ 17.999731] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10627 12:45:25.409644 <3>[ 17.999779] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10628 12:45:25.412515 <6>[ 17.999830] pci 0000:00:00.0: supports D1 D2
10629 12:45:25.422360 <6>[ 17.999834] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10630 12:45:25.428778 <6>[ 18.001547] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10631 12:45:25.435618 <6>[ 18.001653] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10632 12:45:25.442640 <6>[ 18.001685] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10633 12:45:25.449126 <6>[ 18.001705] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10634 12:45:25.458937 <6>[ 18.001724] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10635 12:45:25.462000 <6>[ 18.001840] pci 0000:01:00.0: supports D1 D2
10636 12:45:25.468647 <6>[ 18.001843] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10637 12:45:25.475543 <6>[ 18.010764] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10638 12:45:25.486533 <6>[ 18.015359] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10639 12:45:25.496351 <6>[ 18.015669] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10640 12:45:25.503616 <4>[ 18.034976] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10641 12:45:25.509912 <4>[ 18.034976] Fallback method does not support PEC.
10642 12:45:25.516743 <6>[ 18.040549] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10643 12:45:25.527093 <6>[ 18.040960] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10644 12:45:25.533139 <6>[ 18.040965] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10645 12:45:25.540611 <6>[ 18.040982] remoteproc remoteproc0: remote processor scp is now up
10646 12:45:25.548292 <3>[ 18.063581] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10647 12:45:25.558955 <6>[ 18.064545] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10648 12:45:25.565331 <6>[ 18.068776] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10649 12:45:25.574667 <6>[ 18.083471] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10650 12:45:25.581022 <6>[ 18.088799] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10651 12:45:25.592124 <6>[ 18.088812] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10652 12:45:25.598134 <6>[ 18.088826] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10653 12:45:25.604821 <6>[ 18.088841] pci 0000:00:00.0: PCI bridge to [bus 01]
10654 12:45:25.611130 <3>[ 18.134847] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10655 12:45:25.621570 <3>[ 18.136764] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10656 12:45:25.628412 <6>[ 18.138861] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10657 12:45:25.635431 <6>[ 18.140288] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10658 12:45:25.641733 <6>[ 18.143118] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10659 12:45:25.645249 <6>[ 18.143644] Bluetooth: Core ver 2.22
10660 12:45:25.652313 <6>[ 18.143968] NET: Registered PF_BLUETOOTH protocol family
10661 12:45:25.658035 <6>[ 18.143971] Bluetooth: HCI device and connection manager initialized
10662 12:45:25.665266 <6>[ 18.143990] Bluetooth: HCI socket layer initialized
10663 12:45:25.668584 <6>[ 18.143998] Bluetooth: L2CAP socket layer initialized
10664 12:45:25.675379 <6>[ 18.144008] Bluetooth: SCO socket layer initialized
10665 12:45:25.685240 <6>[ 18.148573] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10666 12:45:25.692191 <6>[ 18.151191] r8152 2-1.3:1.0: load rtl8153b-2 v1 10/23/19 successfully
10667 12:45:25.701776 <6>[ 18.151257] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10668 12:45:25.708312 <6>[ 18.156721] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10669 12:45:25.714651 <6>[ 18.157360] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10670 12:45:25.721553 <6>[ 18.161437] usbcore: registered new interface driver uvcvideo
10671 12:45:25.728648 <6>[ 18.161449] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10672 12:45:25.735607 <6>[ 18.166927] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10673 12:45:25.738652 <6>[ 18.200676] usbcore: registered new interface driver btusb
10674 12:45:25.752526 <4>[ 18.201428] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10675 12:45:25.755435 <3>[ 18.201440] Bluetooth: hci0: Failed to load firmware file (-2)
10676 12:45:25.762304 <3>[ 18.201444] Bluetooth: hci0: Failed to set up firmware (-2)
10677 12:45:25.771530 <4>[ 18.201447] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10678 12:45:25.779083 <6>[ 18.202848] r8152 2-1.3:1.0 eth0: v1.12.13
10679 12:45:25.782798 <6>[ 18.202901] usbcore: registered new interface driver r8152
10680 12:45:25.788314 <6>[ 18.227055] usbcore: registered new interface driver cdc_ether
10681 12:45:25.798641 <5>[ 18.228224] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10682 12:45:25.805037 <3>[ 18.236121] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10683 12:45:25.812879 <5>[ 18.238650] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10684 12:45:25.822669 <5>[ 18.238861] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10685 12:45:25.831786 <4>[ 18.238923] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10686 12:45:25.834836 <6>[ 18.238928] cfg80211: failed to load regulatory.db
10687 12:45:25.844771 <3>[ 18.279641] power_supply sbs-5-000b: driver failed to report `energy_full' property: -6
10688 12:45:25.848790 <6>[ 18.296479] usbcore: registered new interface driver r8153_ecm
10689 12:45:25.858666 <3>[ 18.313406] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10690 12:45:25.866060 <6>[ 18.332504] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10691 12:45:25.874715 <3>[ 18.362018] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10692 12:45:25.881552 <6>[ 18.365092] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10693 12:45:25.888274 <6>[ 18.367029] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10694 12:45:25.894815 <3>[ 18.401798] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10695 12:45:25.901443 <6>[ 18.425150] mt7921e 0000:01:00.0: ASIC revision: 79610010
10696 12:45:25.911459 <3>[ 18.459760] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10697 12:45:25.917986 <6>[ 18.561008] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10698 12:45:25.921114 <6>[ 18.561008]
10699 12:45:25.927925 <3>[ 18.584245] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10700 12:45:25.934373 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10701 12:45:25.953963 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10702 12:45:26.000956 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10703 12:45:26.022706 Starting [0;1;39mNetwork Name Resolution[0m...
10704 12:45:26.047310 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10705 12:45:26.091975 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10706 12:45:26.128648 <6>[ 18.849547] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10707 12:45:26.247064 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10708 12:45:26.261967 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10709 12:45:26.280746 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10710 12:45:26.293364 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10711 12:45:26.313427 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10712 12:45:26.328664 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10713 12:45:26.341675 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10714 12:45:26.360915 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10715 12:45:26.373953 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10716 12:45:26.389307 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10717 12:45:26.409341 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10718 12:45:26.438141 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10719 12:45:26.472297 Starting [0;1;39mUser Login Management[0m...
10720 12:45:26.489865 Starting [0;1;39mPermit User Sessions[0m...
10721 12:45:26.514538 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10722 12:45:26.566161 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10723 12:45:26.586487 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10724 12:45:26.602327 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10725 12:45:26.621355 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10726 12:45:26.638216 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10727 12:45:26.654074 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10728 12:45:26.671309 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10729 12:45:26.686066 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10730 12:45:26.722631 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10731 12:45:26.747257 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10732 12:45:26.797629
10733 12:45:26.798177
10734 12:45:26.801612 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10735 12:45:26.802086
10736 12:45:26.804380 debian-bullseye-arm64 login: root (automatic login)
10737 12:45:26.804896
10738 12:45:26.805267
10739 12:45:26.820533 Linux debian-bullseye-arm64 6.1.75-cip14 #1 SMP PREEMPT Mon Feb 5 12:20:06 UTC 2024 aarch64
10740 12:45:26.821377
10741 12:45:26.826697 The programs included with the Debian GNU/Linux system are free software;
10742 12:45:26.833042 the exact distribution terms for each program are described in the
10743 12:45:26.836957 individual files in /usr/share/doc/*/copyright.
10744 12:45:26.837507
10745 12:45:26.844067 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10746 12:45:26.846806 permitted by applicable law.
10747 12:45:26.848500 Matched prompt #10: / #
10749 12:45:26.849676 Setting prompt string to ['/ #']
10750 12:45:26.850154 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10752 12:45:26.851219 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10753 12:45:26.851732 start: 2.2.6 expect-shell-connection (timeout 00:03:20) [common]
10754 12:45:26.852124 Setting prompt string to ['/ #']
10755 12:45:26.852465 Forcing a shell prompt, looking for ['/ #']
10757 12:45:26.903399 / #
10758 12:45:26.904253 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10759 12:45:26.904754 Waiting using forced prompt support (timeout 00:02:30)
10760 12:45:26.910037
10761 12:45:26.910976 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10762 12:45:26.911492 start: 2.2.7 export-device-env (timeout 00:03:20) [common]
10763 12:45:26.912009 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10764 12:45:26.912503 end: 2.2 depthcharge-retry (duration 00:01:40) [common]
10765 12:45:26.913015 end: 2 depthcharge-action (duration 00:01:40) [common]
10766 12:45:26.913510 start: 3 lava-test-retry (timeout 00:05:00) [common]
10767 12:45:26.913993 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
10768 12:45:26.914417 Using namespace: common
10770 12:45:27.015715 / # #
10771 12:45:27.016362 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
10772 12:45:27.016998 #<6>[ 19.703250] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10773 12:45:27.022220
10774 12:45:27.023098 Using /lava-12703582
10776 12:45:27.124377 / # export SHELL=/bin/sh
10777 12:45:27.131751 export SHELL=/bin/sh
10779 12:45:27.233560 / # . /lava-12703582/environment
10780 12:45:27.234477 <6>[ 19.871197] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c6803bd: link becomes ready
10781 12:45:27.235003 <6>[ 19.879193] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10782 12:45:27.240442 . /lava-12703582/environment
10784 12:45:27.342294 / # /lava-12703582/bin/lava-test-runner /lava-12703582/0
10785 12:45:27.342929 Test shell timeout: 10s (minimum of the action and connection timeout)
10786 12:45:27.348856 /lava-12703582/bin/lava-test-runner /lava-12703582/0
10787 12:45:27.368181 + export TESTRUN_ID=0_cros-ec
10788 12:45:27.376860 +<8>[ 20.099883] <LAVA_SIGNAL_STARTRUN 0_cros-ec 12703582_1.5.2.3.1>
10789 12:45:27.377730 Received signal: <STARTRUN> 0_cros-ec 12703582_1.5.2.3.1
10790 12:45:27.378158 Starting test lava.0_cros-ec (12703582_1.5.2.3.1)
10791 12:45:27.378596 Skipping test definition patterns.
10792 12:45:27.379138 cd /lava-12703582/0/tests/0_cros-ec
10793 12:45:27.382255 + cat uuid
10794 12:45:27.382843 + UUID=12703582_1.5.2.3.1
10795 12:45:27.383222 + set +x
10796 12:45:27.387954 + python3 -m cros.runners.lava_runner -v
10797 12:45:27.729659 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
10798 12:45:27.740819 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
10799 12:45:27.741521
10800 12:45:27.746783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
10801 12:45:27.747678 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
10803 12:45:27.753726 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
10804 12:45:27.760038 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
10805 12:45:27.763743
10806 12:45:27.770371 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=ski<8
10807 12:45:27.771022 Bad test result: ski<8
10808 12:45:27.772915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=ski<8>[ 20.498377] <LAVA_SIGNAL_ENDRUN 0_cros-ec 12703582_1.5.2.3.1>
10809 12:45:27.773986 Received signal: <ENDRUN> 0_cros-ec 12703582_1.5.2.3.1
10810 12:45:27.774510 Ending use of test pattern.
10811 12:45:27.774874 Ending test lava.0_cros-ec (12703582_1.5.2.3.1), duration 0.40
10813 12:45:27.776460 p>
10814 12:45:27.779802 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
10815 12:45:27.787203 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
10816 12:45:27.787672
10817 12:45:27.792640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
10818 12:45:27.793415 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
10820 12:45:27.800848 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
10821 12:45:27.806306 Checks the standard ABI for the main Embedded Controller. ... ok
10822 12:45:27.806770
10823 12:45:27.809381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
10824 12:45:27.810114 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
10826 12:45:27.815970 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
10827 12:45:27.822890 Checks the main Embedded controller character device. ... ok
10828 12:45:27.823459
10829 12:45:27.826211 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
10831 12:45:27.829920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
10832 12:45:27.832613 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
10833 12:45:27.839021 Checks basic comunication with the main Embedded controller. ... ok
10834 12:45:27.839561
10835 12:45:27.845962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
10836 12:45:27.846776 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
10838 12:45:27.849045 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
10839 12:45:27.858731 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
10840 12:45:27.859351
10841 12:45:27.862837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
10842 12:45:27.863768 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
10844 12:45:27.868597 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
10845 12:45:27.875712 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
10846 12:45:27.876293
10847 12:45:27.882236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
10848 12:45:27.883113 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
10850 12:45:27.888789 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
10851 12:45:27.895529 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
10852 12:45:27.896112
10853 12:45:27.901885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
10854 12:45:27.902749 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
10856 12:45:27.904997 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
10857 12:45:27.915107 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
10858 12:45:27.915650
10859 12:45:27.920094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
10860 12:45:27.920946 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
10862 12:45:27.924623 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
10863 12:45:27.934565 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
10864 12:45:27.935036
10865 12:45:27.938558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
10866 12:45:27.939487 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
10868 12:45:27.945759 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
10869 12:45:27.951271 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
10870 12:45:27.951829
10871 12:45:27.957991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
10872 12:45:27.958828 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
10874 12:45:27.964462 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
10875 12:45:27.970919 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
10876 12:45:27.971464
10877 12:45:27.977617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
10878 12:45:27.978509 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
10880 12:45:27.984791 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
10881 12:45:27.990758 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
10882 12:45:27.991330
10883 12:45:27.998527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
10884 12:45:27.999386 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
10886 12:45:28.004674 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
10887 12:45:28.010672 Check the cros battery ABI. ... skipped 'No BAT found'
10888 12:45:28.011244
10889 12:45:28.017377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
10890 12:45:28.018241 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
10892 12:45:28.024080 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
10893 12:45:28.030542 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
10894 12:45:28.031026
10895 12:45:28.036805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
10896 12:45:28.037565 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
10898 12:45:28.040929 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
10899 12:45:28.047505 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
10900 12:45:28.050583
10901 12:45:28.054346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
10902 12:45:28.055224 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
10904 12:45:28.060527 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
10905 12:45:28.067264 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
10906 12:45:28.067811
10907 12:45:28.073653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
10908 12:45:28.074214
10909 12:45:28.074861 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
10911 12:45:28.079953 ----------------------------------------------------------------------
10912 12:45:28.083601 Ran 18 tests in 0.008s
10913 12:45:28.084162
10914 12:45:28.084604 OK (skipped=15)
10915 12:45:28.086939 + set +x
10916 12:45:28.087503 <LAVA_TEST_RUNNER EXIT>
10917 12:45:28.088149 ok: lava_test_shell seems to have completed
10918 12:45:28.089333 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
10919 12:45:28.089863 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10920 12:45:28.090341 end: 3 lava-test-retry (duration 00:00:01) [common]
10921 12:45:28.090884 start: 4 finalize (timeout 00:07:58) [common]
10922 12:45:28.091374 start: 4.1 power-off (timeout 00:00:30) [common]
10923 12:45:28.092199 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
10924 12:45:28.216921 >> Command sent successfully.
10925 12:45:28.221105 Returned 0 in 0 seconds
10926 12:45:28.322229 end: 4.1 power-off (duration 00:00:00) [common]
10928 12:45:28.323932 start: 4.2 read-feedback (timeout 00:07:57) [common]
10929 12:45:28.325319 Listened to connection for namespace 'common' for up to 1s
10930 12:45:29.325043 Finalising connection for namespace 'common'
10931 12:45:29.325778 Disconnecting from shell: Finalise
10932 12:45:29.326299 / #
10933 12:45:29.427631 end: 4.2 read-feedback (duration 00:00:01) [common]
10934 12:45:29.428448 end: 4 finalize (duration 00:00:01) [common]
10935 12:45:29.429260 Cleaning after the job
10936 12:45:29.429868 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703582/tftp-deploy-afe2j7qq/ramdisk
10937 12:45:29.462709 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703582/tftp-deploy-afe2j7qq/kernel
10938 12:45:29.482143 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703582/tftp-deploy-afe2j7qq/dtb
10939 12:45:29.482441 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703582/tftp-deploy-afe2j7qq/modules
10940 12:45:29.492342 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12703582
10941 12:45:29.612604 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12703582
10942 12:45:29.612837 Job finished correctly