Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 14
- Kernel Errors: 33
1 12:42:27.538413 lava-dispatcher, installed at version: 2024.01
2 12:42:27.538623 start: 0 validate
3 12:42:27.538756 Start time: 2024-02-05 12:42:27.538748+00:00 (UTC)
4 12:42:27.538875 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:42:27.539003 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 12:42:27.806781 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:42:27.807474 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:42:28.078045 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:42:28.078681 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:42:28.355049 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:42:28.355761 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:42:28.623572 validate duration: 1.08
14 12:42:28.623863 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:42:28.623968 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:42:28.624053 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:42:28.624178 Not decompressing ramdisk as can be used compressed.
18 12:42:28.624264 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230623.0/arm64/rootfs.cpio.gz
19 12:42:28.624341 saving as /var/lib/lava/dispatcher/tmp/12703541/tftp-deploy-ms6je3da/ramdisk/rootfs.cpio.gz
20 12:42:28.624405 total size: 43284872 (41 MB)
21 12:42:28.625604 progress 0 % (0 MB)
22 12:42:28.637537 progress 5 % (2 MB)
23 12:42:28.649049 progress 10 % (4 MB)
24 12:42:28.660719 progress 15 % (6 MB)
25 12:42:28.672250 progress 20 % (8 MB)
26 12:42:28.683525 progress 25 % (10 MB)
27 12:42:28.695410 progress 30 % (12 MB)
28 12:42:28.706861 progress 35 % (14 MB)
29 12:42:28.718539 progress 40 % (16 MB)
30 12:42:28.729910 progress 45 % (18 MB)
31 12:42:28.741212 progress 50 % (20 MB)
32 12:42:28.752739 progress 55 % (22 MB)
33 12:42:28.764151 progress 60 % (24 MB)
34 12:42:28.775781 progress 65 % (26 MB)
35 12:42:28.787492 progress 70 % (28 MB)
36 12:42:28.798963 progress 75 % (30 MB)
37 12:42:28.810300 progress 80 % (33 MB)
38 12:42:28.821620 progress 85 % (35 MB)
39 12:42:28.832652 progress 90 % (37 MB)
40 12:42:28.843696 progress 95 % (39 MB)
41 12:42:28.854763 progress 100 % (41 MB)
42 12:42:28.855032 41 MB downloaded in 0.23 s (178.99 MB/s)
43 12:42:28.855213 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:42:28.855514 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:42:28.855600 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:42:28.855683 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:42:28.855865 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:42:28.855958 saving as /var/lib/lava/dispatcher/tmp/12703541/tftp-deploy-ms6je3da/kernel/Image
50 12:42:28.856021 total size: 51534336 (49 MB)
51 12:42:28.856083 No compression specified
52 12:42:28.857347 progress 0 % (0 MB)
53 12:42:28.871097 progress 5 % (2 MB)
54 12:42:28.884502 progress 10 % (4 MB)
55 12:42:28.898171 progress 15 % (7 MB)
56 12:42:28.911699 progress 20 % (9 MB)
57 12:42:28.925504 progress 25 % (12 MB)
58 12:42:28.938743 progress 30 % (14 MB)
59 12:42:28.952112 progress 35 % (17 MB)
60 12:42:28.965479 progress 40 % (19 MB)
61 12:42:28.978526 progress 45 % (22 MB)
62 12:42:28.991825 progress 50 % (24 MB)
63 12:42:29.005033 progress 55 % (27 MB)
64 12:42:29.018366 progress 60 % (29 MB)
65 12:42:29.031748 progress 65 % (31 MB)
66 12:42:29.044941 progress 70 % (34 MB)
67 12:42:29.058567 progress 75 % (36 MB)
68 12:42:29.071925 progress 80 % (39 MB)
69 12:42:29.085075 progress 85 % (41 MB)
70 12:42:29.098335 progress 90 % (44 MB)
71 12:42:29.111435 progress 95 % (46 MB)
72 12:42:29.124351 progress 100 % (49 MB)
73 12:42:29.124593 49 MB downloaded in 0.27 s (183.00 MB/s)
74 12:42:29.124746 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:42:29.124976 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:42:29.125067 start: 1.3 download-retry (timeout 00:09:59) [common]
78 12:42:29.125152 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 12:42:29.125290 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:42:29.125365 saving as /var/lib/lava/dispatcher/tmp/12703541/tftp-deploy-ms6je3da/dtb/mt8192-asurada-spherion-r0.dtb
81 12:42:29.125424 total size: 47278 (0 MB)
82 12:42:29.125485 No compression specified
83 12:42:29.126626 progress 69 % (0 MB)
84 12:42:29.126900 progress 100 % (0 MB)
85 12:42:29.127055 0 MB downloaded in 0.00 s (27.68 MB/s)
86 12:42:29.127175 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:42:29.127402 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:42:29.127499 start: 1.4 download-retry (timeout 00:09:59) [common]
90 12:42:29.127589 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 12:42:29.127702 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:42:29.127769 saving as /var/lib/lava/dispatcher/tmp/12703541/tftp-deploy-ms6je3da/modules/modules.tar
93 12:42:29.127827 total size: 8639964 (8 MB)
94 12:42:29.127886 Using unxz to decompress xz
95 12:42:29.131868 progress 0 % (0 MB)
96 12:42:29.153342 progress 5 % (0 MB)
97 12:42:29.178561 progress 10 % (0 MB)
98 12:42:29.203693 progress 15 % (1 MB)
99 12:42:29.228802 progress 20 % (1 MB)
100 12:42:29.254316 progress 25 % (2 MB)
101 12:42:29.283823 progress 30 % (2 MB)
102 12:42:29.310004 progress 35 % (2 MB)
103 12:42:29.333608 progress 40 % (3 MB)
104 12:42:29.358139 progress 45 % (3 MB)
105 12:42:29.383396 progress 50 % (4 MB)
106 12:42:29.409717 progress 55 % (4 MB)
107 12:42:29.435140 progress 60 % (4 MB)
108 12:42:29.461370 progress 65 % (5 MB)
109 12:42:29.486440 progress 70 % (5 MB)
110 12:42:29.511436 progress 75 % (6 MB)
111 12:42:29.538925 progress 80 % (6 MB)
112 12:42:29.567004 progress 85 % (7 MB)
113 12:42:29.592077 progress 90 % (7 MB)
114 12:42:29.621730 progress 95 % (7 MB)
115 12:42:29.649495 progress 100 % (8 MB)
116 12:42:29.655362 8 MB downloaded in 0.53 s (15.62 MB/s)
117 12:42:29.655609 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:42:29.655878 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:42:29.655972 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:42:29.656070 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:42:29.656153 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:42:29.656246 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:42:29.656518 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav
125 12:42:29.656655 makedir: /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav/lava-12703541/bin
126 12:42:29.656761 makedir: /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav/lava-12703541/tests
127 12:42:29.656862 makedir: /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav/lava-12703541/results
128 12:42:29.656978 Creating /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav/lava-12703541/bin/lava-add-keys
129 12:42:29.657137 Creating /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav/lava-12703541/bin/lava-add-sources
130 12:42:29.657269 Creating /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav/lava-12703541/bin/lava-background-process-start
131 12:42:29.657407 Creating /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav/lava-12703541/bin/lava-background-process-stop
132 12:42:29.657538 Creating /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav/lava-12703541/bin/lava-common-functions
133 12:42:29.657670 Creating /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav/lava-12703541/bin/lava-echo-ipv4
134 12:42:29.657799 Creating /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav/lava-12703541/bin/lava-install-packages
135 12:42:29.657927 Creating /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav/lava-12703541/bin/lava-installed-packages
136 12:42:29.658055 Creating /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav/lava-12703541/bin/lava-os-build
137 12:42:29.658183 Creating /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav/lava-12703541/bin/lava-probe-channel
138 12:42:29.658312 Creating /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav/lava-12703541/bin/lava-probe-ip
139 12:42:29.658441 Creating /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav/lava-12703541/bin/lava-target-ip
140 12:42:29.658568 Creating /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav/lava-12703541/bin/lava-target-mac
141 12:42:29.658695 Creating /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav/lava-12703541/bin/lava-target-storage
142 12:42:29.658828 Creating /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav/lava-12703541/bin/lava-test-case
143 12:42:29.658955 Creating /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav/lava-12703541/bin/lava-test-event
144 12:42:29.659080 Creating /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav/lava-12703541/bin/lava-test-feedback
145 12:42:29.659210 Creating /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav/lava-12703541/bin/lava-test-raise
146 12:42:29.659338 Creating /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav/lava-12703541/bin/lava-test-reference
147 12:42:29.659465 Creating /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav/lava-12703541/bin/lava-test-runner
148 12:42:29.659592 Creating /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav/lava-12703541/bin/lava-test-set
149 12:42:29.659721 Creating /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav/lava-12703541/bin/lava-test-shell
150 12:42:29.659851 Updating /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav/lava-12703541/bin/lava-install-packages (oe)
151 12:42:29.660005 Updating /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav/lava-12703541/bin/lava-installed-packages (oe)
152 12:42:29.660135 Creating /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav/lava-12703541/environment
153 12:42:29.660237 LAVA metadata
154 12:42:29.660354 - LAVA_JOB_ID=12703541
155 12:42:29.660421 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:42:29.660529 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:42:29.660598 skipped lava-vland-overlay
158 12:42:29.660673 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:42:29.660755 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:42:29.660818 skipped lava-multinode-overlay
161 12:42:29.660900 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:42:29.660983 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:42:29.661059 Loading test definitions
164 12:42:29.661151 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:42:29.661226 Using /lava-12703541 at stage 0
166 12:42:29.661545 uuid=12703541_1.5.2.3.1 testdef=None
167 12:42:29.661634 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:42:29.661718 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:42:29.662255 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:42:29.662473 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:42:29.663120 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:42:29.663353 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:42:29.663964 runner path: /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav/lava-12703541/0/tests/0_igt-gpu-panfrost test_uuid 12703541_1.5.2.3.1
176 12:42:29.664127 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:42:29.664377 Creating lava-test-runner.conf files
179 12:42:29.664441 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12703541/lava-overlay-ztdf8vav/lava-12703541/0 for stage 0
180 12:42:29.664531 - 0_igt-gpu-panfrost
181 12:42:29.664633 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:42:29.664720 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 12:42:29.672198 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:42:29.672373 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 12:42:29.672467 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:42:29.672555 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:42:29.672643 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 12:42:31.089062 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:42:31.089449 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 12:42:31.089565 extracting modules file /var/lib/lava/dispatcher/tmp/12703541/tftp-deploy-ms6je3da/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12703541/extract-overlay-ramdisk-9cof8oe6/ramdisk
191 12:42:31.315371 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:42:31.315542 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 12:42:31.315637 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12703541/compress-overlay-pm1tzbac/overlay-1.5.2.4.tar.gz to ramdisk
194 12:42:31.315709 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12703541/compress-overlay-pm1tzbac/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12703541/extract-overlay-ramdisk-9cof8oe6/ramdisk
195 12:42:31.322432 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:42:31.322546 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 12:42:31.322641 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:42:31.322736 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 12:42:31.322815 Building ramdisk /var/lib/lava/dispatcher/tmp/12703541/extract-overlay-ramdisk-9cof8oe6/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12703541/extract-overlay-ramdisk-9cof8oe6/ramdisk
200 12:42:32.266170 >> 370008 blocks
201 12:42:38.069153 rename /var/lib/lava/dispatcher/tmp/12703541/extract-overlay-ramdisk-9cof8oe6/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12703541/tftp-deploy-ms6je3da/ramdisk/ramdisk.cpio.gz
202 12:42:38.069597 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 12:42:38.069720 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
204 12:42:38.069817 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
205 12:42:38.069927 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12703541/tftp-deploy-ms6je3da/kernel/Image'
206 12:42:51.208754 Returned 0 in 13 seconds
207 12:42:51.309928 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12703541/tftp-deploy-ms6je3da/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12703541/tftp-deploy-ms6je3da/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12703541/tftp-deploy-ms6je3da/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12703541/tftp-deploy-ms6je3da/kernel/image.itb
208 12:42:52.167956 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:42:52.168324 output: Created: Mon Feb 5 12:42:52 2024
210 12:42:52.168440 output: Image 0 (kernel-1)
211 12:42:52.168509 output: Description:
212 12:42:52.168572 output: Created: Mon Feb 5 12:42:52 2024
213 12:42:52.168635 output: Type: Kernel Image
214 12:42:52.168695 output: Compression: lzma compressed
215 12:42:52.168754 output: Data Size: 12052857 Bytes = 11770.37 KiB = 11.49 MiB
216 12:42:52.168813 output: Architecture: AArch64
217 12:42:52.168870 output: OS: Linux
218 12:42:52.168922 output: Load Address: 0x00000000
219 12:42:52.168976 output: Entry Point: 0x00000000
220 12:42:52.169029 output: Hash algo: crc32
221 12:42:52.169086 output: Hash value: 8a14336a
222 12:42:52.169140 output: Image 1 (fdt-1)
223 12:42:52.169195 output: Description: mt8192-asurada-spherion-r0
224 12:42:52.169248 output: Created: Mon Feb 5 12:42:52 2024
225 12:42:52.169301 output: Type: Flat Device Tree
226 12:42:52.169352 output: Compression: uncompressed
227 12:42:52.169404 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 12:42:52.169457 output: Architecture: AArch64
229 12:42:52.169509 output: Hash algo: crc32
230 12:42:52.169560 output: Hash value: cc4352de
231 12:42:52.169612 output: Image 2 (ramdisk-1)
232 12:42:52.169664 output: Description: unavailable
233 12:42:52.169715 output: Created: Mon Feb 5 12:42:52 2024
234 12:42:52.169767 output: Type: RAMDisk Image
235 12:42:52.169819 output: Compression: Unknown Compression
236 12:42:52.169871 output: Data Size: 56443512 Bytes = 55120.62 KiB = 53.83 MiB
237 12:42:52.169923 output: Architecture: AArch64
238 12:42:52.169975 output: OS: Linux
239 12:42:52.170026 output: Load Address: unavailable
240 12:42:52.170077 output: Entry Point: unavailable
241 12:42:52.170129 output: Hash algo: crc32
242 12:42:52.170180 output: Hash value: b56b9627
243 12:42:52.170232 output: Default Configuration: 'conf-1'
244 12:42:52.170283 output: Configuration 0 (conf-1)
245 12:42:52.170334 output: Description: mt8192-asurada-spherion-r0
246 12:42:52.170386 output: Kernel: kernel-1
247 12:42:52.170438 output: Init Ramdisk: ramdisk-1
248 12:42:52.170489 output: FDT: fdt-1
249 12:42:52.170540 output: Loadables: kernel-1
250 12:42:52.170592 output:
251 12:42:52.170797 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 12:42:52.170896 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 12:42:52.170997 end: 1.5 prepare-tftp-overlay (duration 00:00:23) [common]
254 12:42:52.171097 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:36) [common]
255 12:42:52.171182 No LXC device requested
256 12:42:52.171261 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:42:52.171345 start: 1.7 deploy-device-env (timeout 00:09:36) [common]
258 12:42:52.171423 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:42:52.171493 Checking files for TFTP limit of 4294967296 bytes.
260 12:42:52.171989 end: 1 tftp-deploy (duration 00:00:24) [common]
261 12:42:52.172091 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:42:52.172181 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:42:52.172337 substitutions:
264 12:42:52.172418 - {DTB}: 12703541/tftp-deploy-ms6je3da/dtb/mt8192-asurada-spherion-r0.dtb
265 12:42:52.172485 - {INITRD}: 12703541/tftp-deploy-ms6je3da/ramdisk/ramdisk.cpio.gz
266 12:42:52.172544 - {KERNEL}: 12703541/tftp-deploy-ms6je3da/kernel/Image
267 12:42:52.172600 - {LAVA_MAC}: None
268 12:42:52.172655 - {PRESEED_CONFIG}: None
269 12:42:52.172709 - {PRESEED_LOCAL}: None
270 12:42:52.172762 - {RAMDISK}: 12703541/tftp-deploy-ms6je3da/ramdisk/ramdisk.cpio.gz
271 12:42:52.172816 - {ROOT_PART}: None
272 12:42:52.172869 - {ROOT}: None
273 12:42:52.172922 - {SERVER_IP}: 192.168.201.1
274 12:42:52.172975 - {TEE}: None
275 12:42:52.173028 Parsed boot commands:
276 12:42:52.173082 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:42:52.173259 Parsed boot commands: tftpboot 192.168.201.1 12703541/tftp-deploy-ms6je3da/kernel/image.itb 12703541/tftp-deploy-ms6je3da/kernel/cmdline
278 12:42:52.173349 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:42:52.173436 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:42:52.173528 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:42:52.173614 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:42:52.173681 Not connected, no need to disconnect.
283 12:42:52.173754 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:42:52.173834 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:42:52.173902 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 12:42:52.177778 Setting prompt string to ['lava-test: # ']
287 12:42:52.178189 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:42:52.178297 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:42:52.178394 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:42:52.178488 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:42:52.178692 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 12:42:57.323692 >> Command sent successfully.
293 12:42:57.334508 Returned 0 in 5 seconds
294 12:42:57.435688 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:42:57.437231 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:42:57.437742 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:42:57.438162 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:42:57.438499 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:42:57.438846 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:42:57.440165 [Enter `^Ec?' for help]
302 12:42:57.599510
303 12:42:57.600012
304 12:42:57.600392 F0: 102B 0000
305 12:42:57.600733
306 12:42:57.601061 F3: 1001 0000 [0200]
307 12:42:57.602972
308 12:42:57.603403 F3: 1001 0000
309 12:42:57.603743
310 12:42:57.604053 F7: 102D 0000
311 12:42:57.604396
312 12:42:57.605908 F1: 0000 0000
313 12:42:57.606424
314 12:42:57.606762 V0: 0000 0000 [0001]
315 12:42:57.607092
316 12:42:57.609269 00: 0007 8000
317 12:42:57.609709
318 12:42:57.610045 01: 0000 0000
319 12:42:57.610382
320 12:42:57.612942 BP: 0C00 0209 [0000]
321 12:42:57.613363
322 12:42:57.613694 G0: 1182 0000
323 12:42:57.614006
324 12:42:57.616102 EC: 0000 0021 [4000]
325 12:42:57.616562
326 12:42:57.616899 S7: 0000 0000 [0000]
327 12:42:57.617209
328 12:42:57.620152 CC: 0000 0000 [0001]
329 12:42:57.620632
330 12:42:57.620968 T0: 0000 0040 [010F]
331 12:42:57.621281
332 12:42:57.621580 Jump to BL
333 12:42:57.621874
334 12:42:57.646644
335 12:42:57.647428
336 12:42:57.647823
337 12:42:57.653177 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:42:57.656732 ARM64: Exception handlers installed.
339 12:42:57.660029 ARM64: Testing exception
340 12:42:57.663574 ARM64: Done test exception
341 12:42:57.670208 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:42:57.680196 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:42:57.687648 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:42:57.697981 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:42:57.704679 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:42:57.714445 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:42:57.724418 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:42:57.731640 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:42:57.749149 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:42:57.752231 WDT: Last reset was cold boot
351 12:42:57.756036 SPI1(PAD0) initialized at 2873684 Hz
352 12:42:57.758958 SPI5(PAD0) initialized at 992727 Hz
353 12:42:57.762653 VBOOT: Loading verstage.
354 12:42:57.769698 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:42:57.772769 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:42:57.776652 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:42:57.779700 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:42:57.786807 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:42:57.793159 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:42:57.804812 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 12:42:57.805237
362 12:42:57.805749
363 12:42:57.815362 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:42:57.818484 ARM64: Exception handlers installed.
365 12:42:57.819008 ARM64: Testing exception
366 12:42:57.821705 ARM64: Done test exception
367 12:42:57.825116 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:42:57.831806 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:42:57.845714 Probing TPM: . done!
370 12:42:57.846240 TPM ready after 0 ms
371 12:42:57.853325 Connected to device vid:did:rid of 1ae0:0028:00
372 12:42:57.860032 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 12:42:57.918900 Initialized TPM device CR50 revision 0
374 12:42:57.931257 tlcl_send_startup: Startup return code is 0
375 12:42:57.931792 TPM: setup succeeded
376 12:42:57.942684 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:42:57.951185 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:42:57.963605 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:42:57.973113 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:42:57.976923 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:42:57.980956 in-header: 03 07 00 00 08 00 00 00
382 12:42:57.984029 in-data: aa e4 47 04 13 02 00 00
383 12:42:57.987890 Chrome EC: UHEPI supported
384 12:42:57.991325 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:42:57.995814 in-header: 03 95 00 00 08 00 00 00
386 12:42:58.000273 in-data: 18 20 20 08 00 00 00 00
387 12:42:58.000741 Phase 1
388 12:42:58.003286 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:42:58.010713 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:42:58.018715 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:42:58.019221 Recovery requested (1009000e)
392 12:42:58.029252 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:42:58.034334 tlcl_extend: response is 0
394 12:42:58.045743 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:42:58.049187 tlcl_extend: response is 0
396 12:42:58.056950 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:42:58.075905 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 12:42:58.083026 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 12:42:58.083531
400 12:42:58.083877
401 12:42:58.092671 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:42:58.096122 ARM64: Exception handlers installed.
403 12:42:58.098960 ARM64: Testing exception
404 12:42:58.099053 ARM64: Done test exception
405 12:42:58.121293 pmic_efuse_setting: Set efuses in 11 msecs
406 12:42:58.124654 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:42:58.131291 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:42:58.135192 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:42:58.142088 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:42:58.145995 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:42:58.149465 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:42:58.152774 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:42:58.160891 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:42:58.164084 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:42:58.168152 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:42:58.171725 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:42:58.179331 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:42:58.182853 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:42:58.186510 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:42:58.193476 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:42:58.201398 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:42:58.204835 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:42:58.212544 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:42:58.216122 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:42:58.223831 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:42:58.227323 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:42:58.234983 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:42:58.239165 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:42:58.245884 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:42:58.249798 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:42:58.253627 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:42:58.260716 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:42:58.264843 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:42:58.271984 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:42:58.276110 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:42:58.279765 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:42:58.286850 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:42:58.290889 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:42:58.294435 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:42:58.302085 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:42:58.305914 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:42:58.309913 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:42:58.316967 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:42:58.320492 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:42:58.324114 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:42:58.328218 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:42:58.335723 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:42:58.339245 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:42:58.342702 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:42:58.346915 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:42:58.350541 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:42:58.354108 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:42:58.358263 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:42:58.365154 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:42:58.369268 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:42:58.372511 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:42:58.376656 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:42:58.383807 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:42:58.391223 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:42:58.398715 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:42:58.406200 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:42:58.413581 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:42:58.417347 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:42:58.424887 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:42:58.429149 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:42:58.435833 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x38
467 12:42:58.440013 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:42:58.444166 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 12:42:58.450416 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:42:58.458979 [RTC]rtc_get_frequency_meter,154: input=15, output=760
471 12:42:58.468470 [RTC]rtc_get_frequency_meter,154: input=23, output=942
472 12:42:58.478071 [RTC]rtc_get_frequency_meter,154: input=19, output=850
473 12:42:58.487950 [RTC]rtc_get_frequency_meter,154: input=17, output=805
474 12:42:58.496749 [RTC]rtc_get_frequency_meter,154: input=16, output=783
475 12:42:58.506684 [RTC]rtc_get_frequency_meter,154: input=16, output=782
476 12:42:58.516761 [RTC]rtc_get_frequency_meter,154: input=17, output=805
477 12:42:58.520532 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 12:42:58.524421 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 12:42:58.528281 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 12:42:58.535791 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 12:42:58.539374 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 12:42:58.542817 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 12:42:58.546626 ADC[4]: Raw value=905834 ID=7
484 12:42:58.546736 ADC[3]: Raw value=213441 ID=1
485 12:42:58.549999 RAM Code: 0x71
486 12:42:58.554381 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 12:42:58.557791 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 12:42:58.565423 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 12:42:58.573216 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 12:42:58.576763 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 12:42:58.580176 in-header: 03 07 00 00 08 00 00 00
492 12:42:58.584186 in-data: aa e4 47 04 13 02 00 00
493 12:42:58.587723 Chrome EC: UHEPI supported
494 12:42:58.591147 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 12:42:58.595302 in-header: 03 95 00 00 08 00 00 00
496 12:42:58.599323 in-data: 18 20 20 08 00 00 00 00
497 12:42:58.602790 MRC: failed to locate region type 0.
498 12:42:58.610522 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 12:42:58.613977 DRAM-K: Running full calibration
500 12:42:58.617662 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 12:42:58.621476 header.status = 0x0
502 12:42:58.624923 header.version = 0x6 (expected: 0x6)
503 12:42:58.628928 header.size = 0xd00 (expected: 0xd00)
504 12:42:58.629057 header.flags = 0x0
505 12:42:58.636282 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 12:42:58.653923 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 12:42:58.661259 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 12:42:58.661374 dram_init: ddr_geometry: 2
509 12:42:58.665053 [EMI] MDL number = 2
510 12:42:58.665138 [EMI] Get MDL freq = 0
511 12:42:58.669143 dram_init: ddr_type: 0
512 12:42:58.671937 is_discrete_lpddr4: 1
513 12:42:58.672091 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 12:42:58.676052
515 12:42:58.676166
516 12:42:58.676299 [Bian_co] ETT version 0.0.0.1
517 12:42:58.679664 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 12:42:58.684048
519 12:42:58.687420 dramc_set_vcore_voltage set vcore to 650000
520 12:42:58.687503 Read voltage for 800, 4
521 12:42:58.687569 Vio18 = 0
522 12:42:58.691371 Vcore = 650000
523 12:42:58.691480 Vdram = 0
524 12:42:58.691574 Vddq = 0
525 12:42:58.691694 Vmddr = 0
526 12:42:58.694918 dram_init: config_dvfs: 1
527 12:42:58.701833 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 12:42:58.705391 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 12:42:58.709279 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 12:42:58.712761 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 12:42:58.716776 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 12:42:58.720841 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 12:42:58.724404 MEM_TYPE=3, freq_sel=18
534 12:42:58.724487 sv_algorithm_assistance_LP4_1600
535 12:42:58.730660 ============ PULL DRAM RESETB DOWN ============
536 12:42:58.734015 ========== PULL DRAM RESETB DOWN end =========
537 12:42:58.737182 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 12:42:58.741066 ===================================
539 12:42:58.744640 LPDDR4 DRAM CONFIGURATION
540 12:42:58.748140 ===================================
541 12:42:58.748243 EX_ROW_EN[0] = 0x0
542 12:42:58.751600 EX_ROW_EN[1] = 0x0
543 12:42:58.751702 LP4Y_EN = 0x0
544 12:42:58.755863 WORK_FSP = 0x0
545 12:42:58.755943 WL = 0x2
546 12:42:58.759323 RL = 0x2
547 12:42:58.759401 BL = 0x2
548 12:42:58.763239 RPST = 0x0
549 12:42:58.763360 RD_PRE = 0x0
550 12:42:58.766632 WR_PRE = 0x1
551 12:42:58.766738 WR_PST = 0x0
552 12:42:58.769655 DBI_WR = 0x0
553 12:42:58.769757 DBI_RD = 0x0
554 12:42:58.773268 OTF = 0x1
555 12:42:58.776400 ===================================
556 12:42:58.779636 ===================================
557 12:42:58.779747 ANA top config
558 12:42:58.783439 ===================================
559 12:42:58.786933 DLL_ASYNC_EN = 0
560 12:42:58.789631 ALL_SLAVE_EN = 1
561 12:42:58.789735 NEW_RANK_MODE = 1
562 12:42:58.793151 DLL_IDLE_MODE = 1
563 12:42:58.796427 LP45_APHY_COMB_EN = 1
564 12:42:58.800403 TX_ODT_DIS = 1
565 12:42:58.800512 NEW_8X_MODE = 1
566 12:42:58.804425 ===================================
567 12:42:58.807231 ===================================
568 12:42:58.810708 data_rate = 1600
569 12:42:58.814132 CKR = 1
570 12:42:58.817495 DQ_P2S_RATIO = 8
571 12:42:58.820756 ===================================
572 12:42:58.824186 CA_P2S_RATIO = 8
573 12:42:58.824292 DQ_CA_OPEN = 0
574 12:42:58.827754 DQ_SEMI_OPEN = 0
575 12:42:58.830679 CA_SEMI_OPEN = 0
576 12:42:58.833846 CA_FULL_RATE = 0
577 12:42:58.837325 DQ_CKDIV4_EN = 1
578 12:42:58.840625 CA_CKDIV4_EN = 1
579 12:42:58.840730 CA_PREDIV_EN = 0
580 12:42:58.843835 PH8_DLY = 0
581 12:42:58.847676 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 12:42:58.850571 DQ_AAMCK_DIV = 4
583 12:42:58.853895 CA_AAMCK_DIV = 4
584 12:42:58.857269 CA_ADMCK_DIV = 4
585 12:42:58.857354 DQ_TRACK_CA_EN = 0
586 12:42:58.860721 CA_PICK = 800
587 12:42:58.864204 CA_MCKIO = 800
588 12:42:58.868147 MCKIO_SEMI = 0
589 12:42:58.872200 PLL_FREQ = 3068
590 12:42:58.872282 DQ_UI_PI_RATIO = 32
591 12:42:58.875712 CA_UI_PI_RATIO = 0
592 12:42:58.880051 ===================================
593 12:42:58.883490 ===================================
594 12:42:58.883575 memory_type:LPDDR4
595 12:42:58.886922 GP_NUM : 10
596 12:42:58.890790 SRAM_EN : 1
597 12:42:58.890871 MD32_EN : 0
598 12:42:58.894621 ===================================
599 12:42:58.898108 [ANA_INIT] >>>>>>>>>>>>>>
600 12:42:58.898190 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 12:42:58.901601 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 12:42:58.905099 ===================================
603 12:42:58.908383 data_rate = 1600,PCW = 0X7600
604 12:42:58.911858 ===================================
605 12:42:58.915297 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 12:42:58.922168 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 12:42:58.925565 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 12:42:58.932017 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 12:42:58.935550 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 12:42:58.938744 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 12:42:58.938848 [ANA_INIT] flow start
612 12:42:58.942079 [ANA_INIT] PLL >>>>>>>>
613 12:42:58.945556 [ANA_INIT] PLL <<<<<<<<
614 12:42:58.948409 [ANA_INIT] MIDPI >>>>>>>>
615 12:42:58.948485 [ANA_INIT] MIDPI <<<<<<<<
616 12:42:58.951888 [ANA_INIT] DLL >>>>>>>>
617 12:42:58.951958 [ANA_INIT] flow end
618 12:42:58.958966 ============ LP4 DIFF to SE enter ============
619 12:42:58.962078 ============ LP4 DIFF to SE exit ============
620 12:42:58.965285 [ANA_INIT] <<<<<<<<<<<<<
621 12:42:58.968452 [Flow] Enable top DCM control >>>>>
622 12:42:58.971784 [Flow] Enable top DCM control <<<<<
623 12:42:58.975084 Enable DLL master slave shuffle
624 12:42:58.978666 ==============================================================
625 12:42:58.982093 Gating Mode config
626 12:42:58.985435 ==============================================================
627 12:42:58.988632 Config description:
628 12:42:58.998537 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 12:42:59.005113 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 12:42:59.008816 SELPH_MODE 0: By rank 1: By Phase
631 12:42:59.015699 ==============================================================
632 12:42:59.019042 GAT_TRACK_EN = 1
633 12:42:59.022458 RX_GATING_MODE = 2
634 12:42:59.025206 RX_GATING_TRACK_MODE = 2
635 12:42:59.025316 SELPH_MODE = 1
636 12:42:59.028614 PICG_EARLY_EN = 1
637 12:42:59.032199 VALID_LAT_VALUE = 1
638 12:42:59.039132 ==============================================================
639 12:42:59.042400 Enter into Gating configuration >>>>
640 12:42:59.045771 Exit from Gating configuration <<<<
641 12:42:59.049084 Enter into DVFS_PRE_config >>>>>
642 12:42:59.058846 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 12:42:59.062245 Exit from DVFS_PRE_config <<<<<
644 12:42:59.065684 Enter into PICG configuration >>>>
645 12:42:59.068977 Exit from PICG configuration <<<<
646 12:42:59.072155 [RX_INPUT] configuration >>>>>
647 12:42:59.076035 [RX_INPUT] configuration <<<<<
648 12:42:59.079206 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 12:42:59.085780 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 12:42:59.092324 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 12:42:59.099042 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 12:42:59.102567 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 12:42:59.108834 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 12:42:59.112417 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 12:42:59.115780 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 12:42:59.122455 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 12:42:59.126034 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 12:42:59.128962 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 12:42:59.135780 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 12:42:59.139292 ===================================
661 12:42:59.139374 LPDDR4 DRAM CONFIGURATION
662 12:42:59.142657 ===================================
663 12:42:59.145861 EX_ROW_EN[0] = 0x0
664 12:42:59.145943 EX_ROW_EN[1] = 0x0
665 12:42:59.149446 LP4Y_EN = 0x0
666 12:42:59.152655 WORK_FSP = 0x0
667 12:42:59.152736 WL = 0x2
668 12:42:59.155845 RL = 0x2
669 12:42:59.155927 BL = 0x2
670 12:42:59.159214 RPST = 0x0
671 12:42:59.159296 RD_PRE = 0x0
672 12:42:59.162667 WR_PRE = 0x1
673 12:42:59.162750 WR_PST = 0x0
674 12:42:59.166195 DBI_WR = 0x0
675 12:42:59.166276 DBI_RD = 0x0
676 12:42:59.169618 OTF = 0x1
677 12:42:59.172509 ===================================
678 12:42:59.175921 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 12:42:59.179295 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 12:42:59.182401 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 12:42:59.185759 ===================================
682 12:42:59.189026 LPDDR4 DRAM CONFIGURATION
683 12:42:59.193101 ===================================
684 12:42:59.196115 EX_ROW_EN[0] = 0x10
685 12:42:59.196216 EX_ROW_EN[1] = 0x0
686 12:42:59.199314 LP4Y_EN = 0x0
687 12:42:59.199390 WORK_FSP = 0x0
688 12:42:59.202682 WL = 0x2
689 12:42:59.202787 RL = 0x2
690 12:42:59.206234 BL = 0x2
691 12:42:59.206338 RPST = 0x0
692 12:42:59.209747 RD_PRE = 0x0
693 12:42:59.209850 WR_PRE = 0x1
694 12:42:59.213268 WR_PST = 0x0
695 12:42:59.213365 DBI_WR = 0x0
696 12:42:59.216038 DBI_RD = 0x0
697 12:42:59.216135 OTF = 0x1
698 12:42:59.219529 ===================================
699 12:42:59.225937 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 12:42:59.230777 nWR fixed to 40
701 12:42:59.234278 [ModeRegInit_LP4] CH0 RK0
702 12:42:59.234353 [ModeRegInit_LP4] CH0 RK1
703 12:42:59.237639 [ModeRegInit_LP4] CH1 RK0
704 12:42:59.240903 [ModeRegInit_LP4] CH1 RK1
705 12:42:59.240989 match AC timing 13
706 12:42:59.247930 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 12:42:59.250888 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 12:42:59.254222 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 12:42:59.261327 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 12:42:59.264238 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 12:42:59.264367 [EMI DOE] emi_dcm 0
712 12:42:59.270984 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 12:42:59.271090 ==
714 12:42:59.274726 Dram Type= 6, Freq= 0, CH_0, rank 0
715 12:42:59.278270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 12:42:59.278371 ==
717 12:42:59.284865 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 12:42:59.291049 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 12:42:59.298447 [CA 0] Center 36 (6~67) winsize 62
720 12:42:59.301796 [CA 1] Center 36 (6~67) winsize 62
721 12:42:59.305016 [CA 2] Center 34 (4~65) winsize 62
722 12:42:59.308252 [CA 3] Center 33 (3~64) winsize 62
723 12:42:59.312371 [CA 4] Center 33 (3~64) winsize 62
724 12:42:59.315162 [CA 5] Center 32 (3~62) winsize 60
725 12:42:59.315263
726 12:42:59.318586 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 12:42:59.318690
728 12:42:59.321953 [CATrainingPosCal] consider 1 rank data
729 12:42:59.325438 u2DelayCellTimex100 = 270/100 ps
730 12:42:59.328211 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 12:42:59.331672 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 12:42:59.338707 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 12:42:59.342144 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
734 12:42:59.345054 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
735 12:42:59.348574 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
736 12:42:59.348686
737 12:42:59.352167 CA PerBit enable=1, Macro0, CA PI delay=32
738 12:42:59.352267
739 12:42:59.355093 [CBTSetCACLKResult] CA Dly = 32
740 12:42:59.355170 CS Dly: 5 (0~36)
741 12:42:59.355234 ==
742 12:42:59.358391 Dram Type= 6, Freq= 0, CH_0, rank 1
743 12:42:59.365376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 12:42:59.365461 ==
745 12:42:59.368628 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 12:42:59.374995 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 12:42:59.384534 [CA 0] Center 36 (6~67) winsize 62
748 12:42:59.388404 [CA 1] Center 36 (6~67) winsize 62
749 12:42:59.391145 [CA 2] Center 34 (3~65) winsize 63
750 12:42:59.394929 [CA 3] Center 34 (3~65) winsize 63
751 12:42:59.397956 [CA 4] Center 33 (2~64) winsize 63
752 12:42:59.401492 [CA 5] Center 32 (2~63) winsize 62
753 12:42:59.401594
754 12:42:59.404617 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 12:42:59.404693
756 12:42:59.408016 [CATrainingPosCal] consider 2 rank data
757 12:42:59.411430 u2DelayCellTimex100 = 270/100 ps
758 12:42:59.414693 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 12:42:59.417941 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 12:42:59.424500 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 12:42:59.427742 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
762 12:42:59.431327 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
763 12:42:59.434803 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
764 12:42:59.434878
765 12:42:59.438399 CA PerBit enable=1, Macro0, CA PI delay=32
766 12:42:59.438500
767 12:42:59.441170 [CBTSetCACLKResult] CA Dly = 32
768 12:42:59.441269 CS Dly: 5 (0~37)
769 12:42:59.441365
770 12:42:59.444688 ----->DramcWriteLeveling(PI) begin...
771 12:42:59.448267 ==
772 12:42:59.448389 Dram Type= 6, Freq= 0, CH_0, rank 0
773 12:42:59.455909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 12:42:59.455992 ==
775 12:42:59.456092 Write leveling (Byte 0): 33 => 33
776 12:42:59.459520 Write leveling (Byte 1): 32 => 32
777 12:42:59.463095 DramcWriteLeveling(PI) end<-----
778 12:42:59.463176
779 12:42:59.463240 ==
780 12:42:59.466630 Dram Type= 6, Freq= 0, CH_0, rank 0
781 12:42:59.469380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 12:42:59.472900 ==
783 12:42:59.472983 [Gating] SW mode calibration
784 12:42:59.480457 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 12:42:59.486640 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 12:42:59.490613 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 12:42:59.493808 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 12:42:59.500327 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 12:42:59.503850 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 12:42:59.506640 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:42:59.513360 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:42:59.517087 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:42:59.520335 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:42:59.526798 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:42:59.530300 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:42:59.533441 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:42:59.539912 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:42:59.543667 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:42:59.546784 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:42:59.550199 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:42:59.557211 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:42:59.560717 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:42:59.563586 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 12:42:59.570635 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
805 12:42:59.573526 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:42:59.576877 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:42:59.583744 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:42:59.586980 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:42:59.590454 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 12:42:59.597015 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 12:42:59.600312 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:42:59.603618 0 9 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
813 12:42:59.610152 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
814 12:42:59.613690 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 12:42:59.617146 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 12:42:59.623345 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 12:42:59.626877 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 12:42:59.630289 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 12:42:59.637464 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
820 12:42:59.640010 0 10 8 | B1->B0 | 3030 2525 | 0 0 | (1 0) (1 0)
821 12:42:59.643874 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 12:42:59.650143 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:42:59.653683 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:42:59.657074 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 12:42:59.659961 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 12:42:59.667078 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:42:59.670656 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 12:42:59.674052 0 11 8 | B1->B0 | 2c2c 4343 | 0 0 | (0 0) (0 0)
829 12:42:59.680269 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
830 12:42:59.683834 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 12:42:59.687260 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 12:42:59.693502 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 12:42:59.696828 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 12:42:59.700459 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 12:42:59.707343 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 12:42:59.710783 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
837 12:42:59.714123 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 12:42:59.720716 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 12:42:59.724077 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:42:59.727478 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:42:59.730276 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:42:59.737410 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:42:59.740874 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:42:59.743655 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:42:59.750759 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:42:59.754139 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:42:59.757440 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:42:59.764232 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 12:42:59.767391 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 12:42:59.770748 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 12:42:59.777766 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 12:42:59.780810 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 12:42:59.784419 Total UI for P1: 0, mck2ui 16
854 12:42:59.787539 best dqsien dly found for B0: ( 0, 14, 4)
855 12:42:59.790915 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 12:42:59.794287 Total UI for P1: 0, mck2ui 16
857 12:42:59.798451 best dqsien dly found for B1: ( 0, 14, 8)
858 12:42:59.801823 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
859 12:42:59.805258 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 12:42:59.805341
861 12:42:59.808800 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
862 12:42:59.811619 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 12:42:59.815261 [Gating] SW calibration Done
864 12:42:59.815344 ==
865 12:42:59.818645 Dram Type= 6, Freq= 0, CH_0, rank 0
866 12:42:59.822086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 12:42:59.822170 ==
868 12:42:59.825349 RX Vref Scan: 0
869 12:42:59.825433
870 12:42:59.828672 RX Vref 0 -> 0, step: 1
871 12:42:59.828755
872 12:42:59.828821 RX Delay -130 -> 252, step: 16
873 12:42:59.834964 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 12:42:59.838371 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
875 12:42:59.841858 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 12:42:59.845671 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 12:42:59.848416 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 12:42:59.855393 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 12:42:59.858904 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
880 12:42:59.861714 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
881 12:42:59.865300 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
882 12:42:59.868954 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
883 12:42:59.875566 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 12:42:59.878372 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
885 12:42:59.881822 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 12:42:59.885692 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
887 12:42:59.888797 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
888 12:42:59.895536 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 12:42:59.895620 ==
890 12:42:59.898898 Dram Type= 6, Freq= 0, CH_0, rank 0
891 12:42:59.902028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 12:42:59.902143 ==
893 12:42:59.902234 DQS Delay:
894 12:42:59.905690 DQS0 = 0, DQS1 = 0
895 12:42:59.905773 DQM Delay:
896 12:42:59.908618 DQM0 = 89, DQM1 = 83
897 12:42:59.908701 DQ Delay:
898 12:42:59.912061 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
899 12:42:59.915831 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
900 12:42:59.919184 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
901 12:42:59.922775 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
902 12:42:59.922859
903 12:42:59.922925
904 12:42:59.922986 ==
905 12:42:59.925572 Dram Type= 6, Freq= 0, CH_0, rank 0
906 12:42:59.929147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 12:42:59.929231 ==
908 12:42:59.929297
909 12:42:59.929358
910 12:42:59.932566 TX Vref Scan disable
911 12:42:59.936046 == TX Byte 0 ==
912 12:42:59.939462 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
913 12:42:59.942788 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
914 12:42:59.945453 == TX Byte 1 ==
915 12:42:59.948962 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
916 12:42:59.952202 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
917 12:42:59.952332 ==
918 12:42:59.955928 Dram Type= 6, Freq= 0, CH_0, rank 0
919 12:42:59.958961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 12:42:59.962265 ==
921 12:42:59.973339 TX Vref=22, minBit 3, minWin=27, winSum=443
922 12:42:59.976891 TX Vref=24, minBit 11, minWin=27, winSum=452
923 12:42:59.980029 TX Vref=26, minBit 11, minWin=27, winSum=453
924 12:42:59.983453 TX Vref=28, minBit 0, minWin=28, winSum=455
925 12:42:59.986957 TX Vref=30, minBit 8, minWin=28, winSum=458
926 12:42:59.990448 TX Vref=32, minBit 11, minWin=27, winSum=451
927 12:42:59.997340 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 30
928 12:42:59.997423
929 12:43:00.000630 Final TX Range 1 Vref 30
930 12:43:00.000715
931 12:43:00.000781 ==
932 12:43:00.003851 Dram Type= 6, Freq= 0, CH_0, rank 0
933 12:43:00.007292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 12:43:00.007375 ==
935 12:43:00.007441
936 12:43:00.007502
937 12:43:00.010894 TX Vref Scan disable
938 12:43:00.013648 == TX Byte 0 ==
939 12:43:00.017041 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
940 12:43:00.020450 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
941 12:43:00.023623 == TX Byte 1 ==
942 12:43:00.027176 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
943 12:43:00.030219 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
944 12:43:00.030302
945 12:43:00.033631 [DATLAT]
946 12:43:00.033713 Freq=800, CH0 RK0
947 12:43:00.033779
948 12:43:00.037336 DATLAT Default: 0xa
949 12:43:00.037419 0, 0xFFFF, sum = 0
950 12:43:00.040506 1, 0xFFFF, sum = 0
951 12:43:00.040630 2, 0xFFFF, sum = 0
952 12:43:00.043736 3, 0xFFFF, sum = 0
953 12:43:00.043820 4, 0xFFFF, sum = 0
954 12:43:00.047352 5, 0xFFFF, sum = 0
955 12:43:00.047437 6, 0xFFFF, sum = 0
956 12:43:00.050825 7, 0xFFFF, sum = 0
957 12:43:00.050909 8, 0xFFFF, sum = 0
958 12:43:00.053639 9, 0x0, sum = 1
959 12:43:00.053724 10, 0x0, sum = 2
960 12:43:00.057141 11, 0x0, sum = 3
961 12:43:00.057249 12, 0x0, sum = 4
962 12:43:00.060559 best_step = 10
963 12:43:00.060641
964 12:43:00.060707 ==
965 12:43:00.063981 Dram Type= 6, Freq= 0, CH_0, rank 0
966 12:43:00.067102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 12:43:00.067184 ==
968 12:43:00.070698 RX Vref Scan: 1
969 12:43:00.070780
970 12:43:00.070846 Set Vref Range= 32 -> 127
971 12:43:00.070907
972 12:43:00.073794 RX Vref 32 -> 127, step: 1
973 12:43:00.073877
974 12:43:00.077611 RX Delay -79 -> 252, step: 8
975 12:43:00.077694
976 12:43:00.080443 Set Vref, RX VrefLevel [Byte0]: 32
977 12:43:00.083893 [Byte1]: 32
978 12:43:00.083975
979 12:43:00.087020 Set Vref, RX VrefLevel [Byte0]: 33
980 12:43:00.090669 [Byte1]: 33
981 12:43:00.093986
982 12:43:00.094069 Set Vref, RX VrefLevel [Byte0]: 34
983 12:43:00.097433 [Byte1]: 34
984 12:43:00.101705
985 12:43:00.101788 Set Vref, RX VrefLevel [Byte0]: 35
986 12:43:00.104480 [Byte1]: 35
987 12:43:00.109586
988 12:43:00.109668 Set Vref, RX VrefLevel [Byte0]: 36
989 12:43:00.112874 [Byte1]: 36
990 12:43:00.117065
991 12:43:00.117148 Set Vref, RX VrefLevel [Byte0]: 37
992 12:43:00.119841 [Byte1]: 37
993 12:43:00.124660
994 12:43:00.124743 Set Vref, RX VrefLevel [Byte0]: 38
995 12:43:00.127409 [Byte1]: 38
996 12:43:00.131690
997 12:43:00.131772 Set Vref, RX VrefLevel [Byte0]: 39
998 12:43:00.134957 [Byte1]: 39
999 12:43:00.139193
1000 12:43:00.142574 Set Vref, RX VrefLevel [Byte0]: 40
1001 12:43:00.142657 [Byte1]: 40
1002 12:43:00.147064
1003 12:43:00.147146 Set Vref, RX VrefLevel [Byte0]: 41
1004 12:43:00.150396 [Byte1]: 41
1005 12:43:00.154429
1006 12:43:00.154547 Set Vref, RX VrefLevel [Byte0]: 42
1007 12:43:00.157428 [Byte1]: 42
1008 12:43:00.161676
1009 12:43:00.161759 Set Vref, RX VrefLevel [Byte0]: 43
1010 12:43:00.165271 [Byte1]: 43
1011 12:43:00.169316
1012 12:43:00.169399 Set Vref, RX VrefLevel [Byte0]: 44
1013 12:43:00.172689 [Byte1]: 44
1014 12:43:00.177247
1015 12:43:00.177330 Set Vref, RX VrefLevel [Byte0]: 45
1016 12:43:00.179940 [Byte1]: 45
1017 12:43:00.184639
1018 12:43:00.184722 Set Vref, RX VrefLevel [Byte0]: 46
1019 12:43:00.187886 [Byte1]: 46
1020 12:43:00.192029
1021 12:43:00.192112 Set Vref, RX VrefLevel [Byte0]: 47
1022 12:43:00.195107 [Byte1]: 47
1023 12:43:00.199901
1024 12:43:00.199984 Set Vref, RX VrefLevel [Byte0]: 48
1025 12:43:00.202709 [Byte1]: 48
1026 12:43:00.207578
1027 12:43:00.207658 Set Vref, RX VrefLevel [Byte0]: 49
1028 12:43:00.210406 [Byte1]: 49
1029 12:43:00.214615
1030 12:43:00.214696 Set Vref, RX VrefLevel [Byte0]: 50
1031 12:43:00.218292 [Byte1]: 50
1032 12:43:00.222407
1033 12:43:00.222488 Set Vref, RX VrefLevel [Byte0]: 51
1034 12:43:00.225257 [Byte1]: 51
1035 12:43:00.229476
1036 12:43:00.229560 Set Vref, RX VrefLevel [Byte0]: 52
1037 12:43:00.232886 [Byte1]: 52
1038 12:43:00.237127
1039 12:43:00.237223 Set Vref, RX VrefLevel [Byte0]: 53
1040 12:43:00.240593 [Byte1]: 53
1041 12:43:00.244860
1042 12:43:00.244946 Set Vref, RX VrefLevel [Byte0]: 54
1043 12:43:00.248251 [Byte1]: 54
1044 12:43:00.252414
1045 12:43:00.252496 Set Vref, RX VrefLevel [Byte0]: 55
1046 12:43:00.255776 [Byte1]: 55
1047 12:43:00.259878
1048 12:43:00.259959 Set Vref, RX VrefLevel [Byte0]: 56
1049 12:43:00.263444 [Byte1]: 56
1050 12:43:00.267523
1051 12:43:00.267605 Set Vref, RX VrefLevel [Byte0]: 57
1052 12:43:00.270849 [Byte1]: 57
1053 12:43:00.274920
1054 12:43:00.275001 Set Vref, RX VrefLevel [Byte0]: 58
1055 12:43:00.278667 [Byte1]: 58
1056 12:43:00.282345
1057 12:43:00.282426 Set Vref, RX VrefLevel [Byte0]: 59
1058 12:43:00.285964 [Byte1]: 59
1059 12:43:00.290105
1060 12:43:00.290187 Set Vref, RX VrefLevel [Byte0]: 60
1061 12:43:00.293779 [Byte1]: 60
1062 12:43:00.297981
1063 12:43:00.298062 Set Vref, RX VrefLevel [Byte0]: 61
1064 12:43:00.301102 [Byte1]: 61
1065 12:43:00.305043
1066 12:43:00.305125 Set Vref, RX VrefLevel [Byte0]: 62
1067 12:43:00.308213 [Byte1]: 62
1068 12:43:00.312767
1069 12:43:00.312848 Set Vref, RX VrefLevel [Byte0]: 63
1070 12:43:00.316116 [Byte1]: 63
1071 12:43:00.320335
1072 12:43:00.320417 Set Vref, RX VrefLevel [Byte0]: 64
1073 12:43:00.323471 [Byte1]: 64
1074 12:43:00.327937
1075 12:43:00.328018 Set Vref, RX VrefLevel [Byte0]: 65
1076 12:43:00.331440 [Byte1]: 65
1077 12:43:00.335642
1078 12:43:00.335723 Set Vref, RX VrefLevel [Byte0]: 66
1079 12:43:00.338505 [Byte1]: 66
1080 12:43:00.342725
1081 12:43:00.342806 Set Vref, RX VrefLevel [Byte0]: 67
1082 12:43:00.346236 [Byte1]: 67
1083 12:43:00.350470
1084 12:43:00.350551 Set Vref, RX VrefLevel [Byte0]: 68
1085 12:43:00.353842 [Byte1]: 68
1086 12:43:00.358037
1087 12:43:00.358119 Set Vref, RX VrefLevel [Byte0]: 69
1088 12:43:00.361402 [Byte1]: 69
1089 12:43:00.365393
1090 12:43:00.365475 Set Vref, RX VrefLevel [Byte0]: 70
1091 12:43:00.372326 [Byte1]: 70
1092 12:43:00.372410
1093 12:43:00.375092 Set Vref, RX VrefLevel [Byte0]: 71
1094 12:43:00.378650 [Byte1]: 71
1095 12:43:00.378731
1096 12:43:00.382166 Set Vref, RX VrefLevel [Byte0]: 72
1097 12:43:00.385481 [Byte1]: 72
1098 12:43:00.385563
1099 12:43:00.388738 Set Vref, RX VrefLevel [Byte0]: 73
1100 12:43:00.392110 [Byte1]: 73
1101 12:43:00.396048
1102 12:43:00.396130 Set Vref, RX VrefLevel [Byte0]: 74
1103 12:43:00.399351 [Byte1]: 74
1104 12:43:00.403252
1105 12:43:00.403333 Set Vref, RX VrefLevel [Byte0]: 75
1106 12:43:00.406763 [Byte1]: 75
1107 12:43:00.410973
1108 12:43:00.411053 Set Vref, RX VrefLevel [Byte0]: 76
1109 12:43:00.413985 [Byte1]: 76
1110 12:43:00.418411
1111 12:43:00.418485 Final RX Vref Byte 0 = 54 to rank0
1112 12:43:00.422021 Final RX Vref Byte 1 = 59 to rank0
1113 12:43:00.425297 Final RX Vref Byte 0 = 54 to rank1
1114 12:43:00.428354 Final RX Vref Byte 1 = 59 to rank1==
1115 12:43:00.431958 Dram Type= 6, Freq= 0, CH_0, rank 0
1116 12:43:00.435388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1117 12:43:00.438680 ==
1118 12:43:00.438758 DQS Delay:
1119 12:43:00.438825 DQS0 = 0, DQS1 = 0
1120 12:43:00.442211 DQM Delay:
1121 12:43:00.442291 DQM0 = 91, DQM1 = 85
1122 12:43:00.445028 DQ Delay:
1123 12:43:00.448377 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1124 12:43:00.448456 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1125 12:43:00.451791 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =76
1126 12:43:00.458650 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1127 12:43:00.458733
1128 12:43:00.458798
1129 12:43:00.464906 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c42, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
1130 12:43:00.468476 CH0 RK0: MR19=606, MR18=4C42
1131 12:43:00.475271 CH0_RK0: MR19=0x606, MR18=0x4C42, DQSOSC=390, MR23=63, INC=97, DEC=64
1132 12:43:00.475356
1133 12:43:00.478649 ----->DramcWriteLeveling(PI) begin...
1134 12:43:00.478722 ==
1135 12:43:00.482132 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 12:43:00.485790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 12:43:00.485907 ==
1138 12:43:00.488726 Write leveling (Byte 0): 33 => 33
1139 12:43:00.492069 Write leveling (Byte 1): 29 => 29
1140 12:43:00.495483 DramcWriteLeveling(PI) end<-----
1141 12:43:00.495565
1142 12:43:00.495631 ==
1143 12:43:00.498740 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 12:43:00.502222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 12:43:00.502304 ==
1146 12:43:00.505818 [Gating] SW mode calibration
1147 12:43:00.511928 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1148 12:43:00.518744 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1149 12:43:00.562920 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 12:43:00.563011 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1151 12:43:00.563085 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1152 12:43:00.563347 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1153 12:43:00.563443 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 12:43:00.563579 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 12:43:00.563774 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 12:43:00.563836 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 12:43:00.563895 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 12:43:00.564256 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 12:43:00.607059 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 12:43:00.607811 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 12:43:00.607901 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 12:43:00.608166 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 12:43:00.608270 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:43:00.608440 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:43:00.608508 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:43:00.608567 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1167 12:43:00.608625 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1168 12:43:00.608702 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:43:00.651416 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 12:43:00.651517 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 12:43:00.651793 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 12:43:00.651874 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 12:43:00.651973 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 12:43:00.652072 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 12:43:00.652158 0 9 8 | B1->B0 | 2f2f 2d2d | 0 0 | (0 0) (0 0)
1176 12:43:00.652262 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 12:43:00.652374 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 12:43:00.652692 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 12:43:00.670300 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 12:43:00.670394 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 12:43:00.670652 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 12:43:00.670726 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
1183 12:43:00.673787 0 10 8 | B1->B0 | 2b2b 2e2e | 0 0 | (0 0) (0 0)
1184 12:43:00.677147 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1185 12:43:00.680516 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 12:43:00.683939 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 12:43:00.687646 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 12:43:00.694582 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 12:43:00.698826 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 12:43:00.702906 0 11 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1191 12:43:00.706324 0 11 8 | B1->B0 | 3e3e 3a3a | 0 0 | (1 1) (0 0)
1192 12:43:00.710431 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 12:43:00.716573 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 12:43:00.720844 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 12:43:00.723704 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 12:43:00.727035 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 12:43:00.734024 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 12:43:00.737038 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 12:43:00.740449 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1200 12:43:00.747176 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 12:43:00.750416 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 12:43:00.754073 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 12:43:00.760980 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 12:43:00.763720 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 12:43:00.767234 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 12:43:00.774097 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 12:43:00.777504 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 12:43:00.780770 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 12:43:00.784184 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 12:43:00.790713 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 12:43:00.793968 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 12:43:00.797735 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 12:43:00.803840 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 12:43:00.807350 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 12:43:00.810652 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1216 12:43:00.817583 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1217 12:43:00.817663 Total UI for P1: 0, mck2ui 16
1218 12:43:00.824543 best dqsien dly found for B0: ( 0, 14, 8)
1219 12:43:00.827935 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 12:43:00.830704 Total UI for P1: 0, mck2ui 16
1221 12:43:00.834176 best dqsien dly found for B1: ( 0, 14, 10)
1222 12:43:00.837432 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1223 12:43:00.840771 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1224 12:43:00.840850
1225 12:43:00.844032 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1226 12:43:00.847419 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1227 12:43:00.850875 [Gating] SW calibration Done
1228 12:43:00.850954 ==
1229 12:43:00.854260 Dram Type= 6, Freq= 0, CH_0, rank 1
1230 12:43:00.857577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1231 12:43:00.857654 ==
1232 12:43:00.860843 RX Vref Scan: 0
1233 12:43:00.860923
1234 12:43:00.864022 RX Vref 0 -> 0, step: 1
1235 12:43:00.864098
1236 12:43:00.864160 RX Delay -130 -> 252, step: 16
1237 12:43:00.870798 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1238 12:43:00.874844 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1239 12:43:00.877535 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1240 12:43:00.881062 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1241 12:43:00.884522 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1242 12:43:00.890969 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1243 12:43:00.894529 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1244 12:43:00.897948 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1245 12:43:00.901355 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1246 12:43:00.904816 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1247 12:43:00.911441 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1248 12:43:00.914721 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1249 12:43:00.918071 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1250 12:43:00.921064 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1251 12:43:00.924686 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1252 12:43:00.931062 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1253 12:43:00.931144 ==
1254 12:43:00.935018 Dram Type= 6, Freq= 0, CH_0, rank 1
1255 12:43:00.937798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1256 12:43:00.937881 ==
1257 12:43:00.937946 DQS Delay:
1258 12:43:00.941072 DQS0 = 0, DQS1 = 0
1259 12:43:00.941154 DQM Delay:
1260 12:43:00.944480 DQM0 = 93, DQM1 = 83
1261 12:43:00.944562 DQ Delay:
1262 12:43:00.947708 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1263 12:43:00.951114 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1264 12:43:00.954506 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1265 12:43:00.957958 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =93
1266 12:43:00.958041
1267 12:43:00.958106
1268 12:43:00.958166 ==
1269 12:43:00.961424 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 12:43:00.964896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1271 12:43:00.964978 ==
1272 12:43:00.965043
1273 12:43:00.965103
1274 12:43:00.968348 TX Vref Scan disable
1275 12:43:00.971629 == TX Byte 0 ==
1276 12:43:00.974798 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1277 12:43:00.977999 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1278 12:43:00.981496 == TX Byte 1 ==
1279 12:43:00.984955 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1280 12:43:00.988464 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1281 12:43:00.988545 ==
1282 12:43:00.991738 Dram Type= 6, Freq= 0, CH_0, rank 1
1283 12:43:00.997729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1284 12:43:00.997813 ==
1285 12:43:01.010289 TX Vref=22, minBit 8, minWin=27, winSum=444
1286 12:43:01.013739 TX Vref=24, minBit 10, minWin=27, winSum=451
1287 12:43:01.017225 TX Vref=26, minBit 10, minWin=27, winSum=453
1288 12:43:01.019844 TX Vref=28, minBit 4, minWin=28, winSum=457
1289 12:43:01.023374 TX Vref=30, minBit 7, minWin=28, winSum=458
1290 12:43:01.029979 TX Vref=32, minBit 2, minWin=28, winSum=453
1291 12:43:01.033258 [TxChooseVref] Worse bit 7, Min win 28, Win sum 458, Final Vref 30
1292 12:43:01.033331
1293 12:43:01.037098 Final TX Range 1 Vref 30
1294 12:43:01.037203
1295 12:43:01.037296 ==
1296 12:43:01.040041 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 12:43:01.043579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 12:43:01.043654 ==
1299 12:43:01.046824
1300 12:43:01.046899
1301 12:43:01.046968 TX Vref Scan disable
1302 12:43:01.050140 == TX Byte 0 ==
1303 12:43:01.053684 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1304 12:43:01.056982 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1305 12:43:01.060068 == TX Byte 1 ==
1306 12:43:01.063431 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1307 12:43:01.067022 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1308 12:43:01.070474
1309 12:43:01.070554 [DATLAT]
1310 12:43:01.070617 Freq=800, CH0 RK1
1311 12:43:01.070680
1312 12:43:01.073949 DATLAT Default: 0xa
1313 12:43:01.074027 0, 0xFFFF, sum = 0
1314 12:43:01.076729 1, 0xFFFF, sum = 0
1315 12:43:01.076802 2, 0xFFFF, sum = 0
1316 12:43:01.080144 3, 0xFFFF, sum = 0
1317 12:43:01.080244 4, 0xFFFF, sum = 0
1318 12:43:01.083365 5, 0xFFFF, sum = 0
1319 12:43:01.083437 6, 0xFFFF, sum = 0
1320 12:43:01.087207 7, 0xFFFF, sum = 0
1321 12:43:01.090222 8, 0xFFFF, sum = 0
1322 12:43:01.090293 9, 0x0, sum = 1
1323 12:43:01.090361 10, 0x0, sum = 2
1324 12:43:01.093862 11, 0x0, sum = 3
1325 12:43:01.093942 12, 0x0, sum = 4
1326 12:43:01.096587 best_step = 10
1327 12:43:01.096666
1328 12:43:01.096729 ==
1329 12:43:01.100517 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 12:43:01.103837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 12:43:01.103911 ==
1332 12:43:01.107260 RX Vref Scan: 0
1333 12:43:01.107329
1334 12:43:01.107388 RX Vref 0 -> 0, step: 1
1335 12:43:01.107451
1336 12:43:01.110085 RX Delay -95 -> 252, step: 8
1337 12:43:01.116936 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1338 12:43:01.120466 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1339 12:43:01.123739 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1340 12:43:01.126678 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1341 12:43:01.130184 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1342 12:43:01.137001 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1343 12:43:01.140472 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1344 12:43:01.144108 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1345 12:43:01.147254 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1346 12:43:01.150507 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1347 12:43:01.157168 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1348 12:43:01.160373 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1349 12:43:01.163801 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1350 12:43:01.167091 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1351 12:43:01.170345 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1352 12:43:01.177292 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1353 12:43:01.177378 ==
1354 12:43:01.180708 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 12:43:01.183538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 12:43:01.183612 ==
1357 12:43:01.183672 DQS Delay:
1358 12:43:01.187050 DQS0 = 0, DQS1 = 0
1359 12:43:01.187122 DQM Delay:
1360 12:43:01.190432 DQM0 = 93, DQM1 = 83
1361 12:43:01.190501 DQ Delay:
1362 12:43:01.193990 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1363 12:43:01.197242 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1364 12:43:01.200528 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1365 12:43:01.204130 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1366 12:43:01.204209
1367 12:43:01.204271
1368 12:43:01.210366 [DQSOSCAuto] RK1, (LSB)MR18= 0x4212, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1369 12:43:01.214210 CH0 RK1: MR19=606, MR18=4212
1370 12:43:01.220661 CH0_RK1: MR19=0x606, MR18=0x4212, DQSOSC=393, MR23=63, INC=95, DEC=63
1371 12:43:01.224033 [RxdqsGatingPostProcess] freq 800
1372 12:43:01.230933 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1373 12:43:01.231009 Pre-setting of DQS Precalculation
1374 12:43:01.237121 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1375 12:43:01.237223 ==
1376 12:43:01.240442 Dram Type= 6, Freq= 0, CH_1, rank 0
1377 12:43:01.243901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1378 12:43:01.243971 ==
1379 12:43:01.250556 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1380 12:43:01.256947 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1381 12:43:01.265114 [CA 0] Center 36 (6~67) winsize 62
1382 12:43:01.268248 [CA 1] Center 36 (6~67) winsize 62
1383 12:43:01.271769 [CA 2] Center 35 (4~66) winsize 63
1384 12:43:01.275187 [CA 3] Center 34 (4~65) winsize 62
1385 12:43:01.278451 [CA 4] Center 34 (4~65) winsize 62
1386 12:43:01.281689 [CA 5] Center 34 (4~65) winsize 62
1387 12:43:01.281769
1388 12:43:01.285348 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1389 12:43:01.285429
1390 12:43:01.288773 [CATrainingPosCal] consider 1 rank data
1391 12:43:01.291570 u2DelayCellTimex100 = 270/100 ps
1392 12:43:01.295056 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1393 12:43:01.298658 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1394 12:43:01.305507 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1395 12:43:01.308905 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1396 12:43:01.312228 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1397 12:43:01.315523 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1398 12:43:01.315596
1399 12:43:01.318808 CA PerBit enable=1, Macro0, CA PI delay=34
1400 12:43:01.318885
1401 12:43:01.321776 [CBTSetCACLKResult] CA Dly = 34
1402 12:43:01.321848 CS Dly: 5 (0~36)
1403 12:43:01.321915 ==
1404 12:43:01.324994 Dram Type= 6, Freq= 0, CH_1, rank 1
1405 12:43:01.331790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1406 12:43:01.331872 ==
1407 12:43:01.335394 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1408 12:43:01.341641 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1409 12:43:01.351701 [CA 0] Center 36 (6~67) winsize 62
1410 12:43:01.355171 [CA 1] Center 37 (6~68) winsize 63
1411 12:43:01.358710 [CA 2] Center 35 (4~66) winsize 63
1412 12:43:01.362156 [CA 3] Center 34 (4~65) winsize 62
1413 12:43:01.366191 [CA 4] Center 35 (5~66) winsize 62
1414 12:43:01.369732 [CA 5] Center 34 (4~65) winsize 62
1415 12:43:01.369817
1416 12:43:01.373108 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1417 12:43:01.373191
1418 12:43:01.376428 [CATrainingPosCal] consider 2 rank data
1419 12:43:01.379872 u2DelayCellTimex100 = 270/100 ps
1420 12:43:01.384039 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1421 12:43:01.388157 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1422 12:43:01.391440 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1423 12:43:01.394684 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1424 12:43:01.397781 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1425 12:43:01.401353 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1426 12:43:01.401431
1427 12:43:01.404846 CA PerBit enable=1, Macro0, CA PI delay=34
1428 12:43:01.404921
1429 12:43:01.408431 [CBTSetCACLKResult] CA Dly = 34
1430 12:43:01.408512 CS Dly: 6 (0~38)
1431 12:43:01.408573
1432 12:43:01.411276 ----->DramcWriteLeveling(PI) begin...
1433 12:43:01.414717 ==
1434 12:43:01.414794 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 12:43:01.421713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 12:43:01.421790 ==
1437 12:43:01.424954 Write leveling (Byte 0): 26 => 26
1438 12:43:01.428498 Write leveling (Byte 1): 27 => 27
1439 12:43:01.428575 DramcWriteLeveling(PI) end<-----
1440 12:43:01.431238
1441 12:43:01.431310 ==
1442 12:43:01.434486 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 12:43:01.438004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 12:43:01.438109 ==
1445 12:43:01.441363 [Gating] SW mode calibration
1446 12:43:01.448217 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1447 12:43:01.451800 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1448 12:43:01.457996 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1449 12:43:01.461832 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1450 12:43:01.465192 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 12:43:01.471819 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 12:43:01.475290 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 12:43:01.478725 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 12:43:01.485366 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 12:43:01.488065 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 12:43:01.491619 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 12:43:01.498642 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 12:43:01.501921 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:43:01.505370 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 12:43:01.508439 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 12:43:01.515302 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:43:01.518759 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:43:01.521456 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:43:01.528416 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1465 12:43:01.531971 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:43:01.535232 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1467 12:43:01.541669 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 12:43:01.545104 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 12:43:01.548734 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 12:43:01.555547 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 12:43:01.558825 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 12:43:01.562105 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:43:01.568434 0 9 4 | B1->B0 | 2323 2626 | 1 1 | (1 1) (1 1)
1474 12:43:01.571859 0 9 8 | B1->B0 | 2f2f 3434 | 0 1 | (1 1) (1 1)
1475 12:43:01.575403 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 12:43:01.582033 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 12:43:01.585597 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 12:43:01.588817 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 12:43:01.592127 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 12:43:01.598611 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 12:43:01.601999 0 10 4 | B1->B0 | 3232 2c2c | 0 1 | (0 1) (1 0)
1482 12:43:01.605513 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1483 12:43:01.611892 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 12:43:01.615370 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 12:43:01.618590 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 12:43:01.625291 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 12:43:01.628769 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 12:43:01.632099 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1489 12:43:01.638846 0 11 4 | B1->B0 | 2929 3736 | 0 1 | (0 0) (0 0)
1490 12:43:01.642203 0 11 8 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
1491 12:43:01.645580 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 12:43:01.649130 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 12:43:01.655388 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 12:43:01.658894 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 12:43:01.662380 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 12:43:01.669238 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 12:43:01.671942 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1498 12:43:01.675398 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1499 12:43:01.682057 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 12:43:01.685811 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 12:43:01.688896 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 12:43:01.695117 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 12:43:01.698883 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 12:43:01.702116 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 12:43:01.708934 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 12:43:01.712268 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 12:43:01.715479 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 12:43:01.721783 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 12:43:01.725159 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 12:43:01.728504 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 12:43:01.735318 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 12:43:01.739018 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 12:43:01.742107 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1514 12:43:01.748731 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 12:43:01.748821 Total UI for P1: 0, mck2ui 16
1516 12:43:01.752294 best dqsien dly found for B0: ( 0, 14, 4)
1517 12:43:01.755773 Total UI for P1: 0, mck2ui 16
1518 12:43:01.758519 best dqsien dly found for B1: ( 0, 14, 4)
1519 12:43:01.761932 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1520 12:43:01.768713 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1521 12:43:01.768853
1522 12:43:01.771953 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1523 12:43:01.775644 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1524 12:43:01.778962 [Gating] SW calibration Done
1525 12:43:01.779037 ==
1526 12:43:01.782422 Dram Type= 6, Freq= 0, CH_1, rank 0
1527 12:43:01.785243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1528 12:43:01.785314 ==
1529 12:43:01.785376 RX Vref Scan: 0
1530 12:43:01.785440
1531 12:43:01.788611 RX Vref 0 -> 0, step: 1
1532 12:43:01.788687
1533 12:43:01.791948 RX Delay -130 -> 252, step: 16
1534 12:43:01.795391 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1535 12:43:01.798860 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1536 12:43:01.805303 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1537 12:43:01.808451 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1538 12:43:01.812479 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1539 12:43:01.815701 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1540 12:43:01.818983 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1541 12:43:01.825421 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1542 12:43:01.828870 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1543 12:43:01.832273 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1544 12:43:01.835801 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1545 12:43:01.839173 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1546 12:43:01.845808 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1547 12:43:01.848874 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1548 12:43:01.852410 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1549 12:43:01.855319 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1550 12:43:01.855400 ==
1551 12:43:01.858801 Dram Type= 6, Freq= 0, CH_1, rank 0
1552 12:43:01.862496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1553 12:43:01.865795 ==
1554 12:43:01.865876 DQS Delay:
1555 12:43:01.865969 DQS0 = 0, DQS1 = 0
1556 12:43:01.869352 DQM Delay:
1557 12:43:01.869433 DQM0 = 92, DQM1 = 87
1558 12:43:01.872695 DQ Delay:
1559 12:43:01.872777 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1560 12:43:01.875508 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1561 12:43:01.878874 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1562 12:43:01.882298 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1563 12:43:01.882379
1564 12:43:01.885750
1565 12:43:01.885831 ==
1566 12:43:01.889217 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 12:43:01.892630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 12:43:01.892712 ==
1569 12:43:01.892776
1570 12:43:01.892835
1571 12:43:01.896013 TX Vref Scan disable
1572 12:43:01.896094 == TX Byte 0 ==
1573 12:43:01.902302 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1574 12:43:01.905841 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1575 12:43:01.905922 == TX Byte 1 ==
1576 12:43:01.912554 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1577 12:43:01.915865 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1578 12:43:01.915946 ==
1579 12:43:01.919246 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 12:43:01.922443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 12:43:01.922525 ==
1582 12:43:01.935884 TX Vref=22, minBit 0, minWin=26, winSum=434
1583 12:43:01.939756 TX Vref=24, minBit 1, minWin=26, winSum=439
1584 12:43:01.943176 TX Vref=26, minBit 1, minWin=27, winSum=445
1585 12:43:01.946701 TX Vref=28, minBit 1, minWin=27, winSum=447
1586 12:43:01.950067 TX Vref=30, minBit 1, minWin=27, winSum=448
1587 12:43:01.953473 TX Vref=32, minBit 0, minWin=27, winSum=447
1588 12:43:01.960207 [TxChooseVref] Worse bit 1, Min win 27, Win sum 448, Final Vref 30
1589 12:43:01.960330
1590 12:43:01.963333 Final TX Range 1 Vref 30
1591 12:43:01.963414
1592 12:43:01.963478 ==
1593 12:43:01.966468 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 12:43:01.970071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 12:43:01.970153 ==
1596 12:43:01.970217
1597 12:43:01.970276
1598 12:43:01.973144 TX Vref Scan disable
1599 12:43:01.976191 == TX Byte 0 ==
1600 12:43:01.979832 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1601 12:43:01.983451 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1602 12:43:01.986685 == TX Byte 1 ==
1603 12:43:01.989753 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1604 12:43:01.993277 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1605 12:43:01.993359
1606 12:43:01.996831 [DATLAT]
1607 12:43:01.996912 Freq=800, CH1 RK0
1608 12:43:01.996976
1609 12:43:02.000094 DATLAT Default: 0xa
1610 12:43:02.000175 0, 0xFFFF, sum = 0
1611 12:43:02.003594 1, 0xFFFF, sum = 0
1612 12:43:02.003676 2, 0xFFFF, sum = 0
1613 12:43:02.006374 3, 0xFFFF, sum = 0
1614 12:43:02.006456 4, 0xFFFF, sum = 0
1615 12:43:02.009905 5, 0xFFFF, sum = 0
1616 12:43:02.009987 6, 0xFFFF, sum = 0
1617 12:43:02.013340 7, 0xFFFF, sum = 0
1618 12:43:02.013422 8, 0xFFFF, sum = 0
1619 12:43:02.016743 9, 0x0, sum = 1
1620 12:43:02.016826 10, 0x0, sum = 2
1621 12:43:02.020024 11, 0x0, sum = 3
1622 12:43:02.020106 12, 0x0, sum = 4
1623 12:43:02.020171 best_step = 10
1624 12:43:02.020230
1625 12:43:02.023353 ==
1626 12:43:02.026731 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 12:43:02.030148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 12:43:02.030229 ==
1629 12:43:02.030293 RX Vref Scan: 1
1630 12:43:02.030353
1631 12:43:02.033592 Set Vref Range= 32 -> 127
1632 12:43:02.033673
1633 12:43:02.037128 RX Vref 32 -> 127, step: 1
1634 12:43:02.037209
1635 12:43:02.039918 RX Delay -79 -> 252, step: 8
1636 12:43:02.039998
1637 12:43:02.043347 Set Vref, RX VrefLevel [Byte0]: 32
1638 12:43:02.046690 [Byte1]: 32
1639 12:43:02.046771
1640 12:43:02.049854 Set Vref, RX VrefLevel [Byte0]: 33
1641 12:43:02.053129 [Byte1]: 33
1642 12:43:02.053210
1643 12:43:02.056438 Set Vref, RX VrefLevel [Byte0]: 34
1644 12:43:02.060021 [Byte1]: 34
1645 12:43:02.063423
1646 12:43:02.063503 Set Vref, RX VrefLevel [Byte0]: 35
1647 12:43:02.066966 [Byte1]: 35
1648 12:43:02.071107
1649 12:43:02.071187 Set Vref, RX VrefLevel [Byte0]: 36
1650 12:43:02.073923 [Byte1]: 36
1651 12:43:02.078336
1652 12:43:02.078417 Set Vref, RX VrefLevel [Byte0]: 37
1653 12:43:02.081565 [Byte1]: 37
1654 12:43:02.085951
1655 12:43:02.086032 Set Vref, RX VrefLevel [Byte0]: 38
1656 12:43:02.089211 [Byte1]: 38
1657 12:43:02.093401
1658 12:43:02.093482 Set Vref, RX VrefLevel [Byte0]: 39
1659 12:43:02.096692 [Byte1]: 39
1660 12:43:02.101218
1661 12:43:02.101299 Set Vref, RX VrefLevel [Byte0]: 40
1662 12:43:02.104330 [Byte1]: 40
1663 12:43:02.108796
1664 12:43:02.108877 Set Vref, RX VrefLevel [Byte0]: 41
1665 12:43:02.111804 [Byte1]: 41
1666 12:43:02.115897
1667 12:43:02.115978 Set Vref, RX VrefLevel [Byte0]: 42
1668 12:43:02.119293 [Byte1]: 42
1669 12:43:02.123410
1670 12:43:02.123491 Set Vref, RX VrefLevel [Byte0]: 43
1671 12:43:02.126895 [Byte1]: 43
1672 12:43:02.130990
1673 12:43:02.131070 Set Vref, RX VrefLevel [Byte0]: 44
1674 12:43:02.134417 [Byte1]: 44
1675 12:43:02.138496
1676 12:43:02.138577 Set Vref, RX VrefLevel [Byte0]: 45
1677 12:43:02.142010 [Byte1]: 45
1678 12:43:02.146180
1679 12:43:02.146261 Set Vref, RX VrefLevel [Byte0]: 46
1680 12:43:02.149554 [Byte1]: 46
1681 12:43:02.153714
1682 12:43:02.157116 Set Vref, RX VrefLevel [Byte0]: 47
1683 12:43:02.160321 [Byte1]: 47
1684 12:43:02.160403
1685 12:43:02.163716 Set Vref, RX VrefLevel [Byte0]: 48
1686 12:43:02.166948 [Byte1]: 48
1687 12:43:02.167029
1688 12:43:02.170428 Set Vref, RX VrefLevel [Byte0]: 49
1689 12:43:02.173925 [Byte1]: 49
1690 12:43:02.174006
1691 12:43:02.176877 Set Vref, RX VrefLevel [Byte0]: 50
1692 12:43:02.180306 [Byte1]: 50
1693 12:43:02.184251
1694 12:43:02.184374 Set Vref, RX VrefLevel [Byte0]: 51
1695 12:43:02.187733 [Byte1]: 51
1696 12:43:02.191735
1697 12:43:02.191815 Set Vref, RX VrefLevel [Byte0]: 52
1698 12:43:02.194934 [Byte1]: 52
1699 12:43:02.199104
1700 12:43:02.199185 Set Vref, RX VrefLevel [Byte0]: 53
1701 12:43:02.202463 [Byte1]: 53
1702 12:43:02.206597
1703 12:43:02.206678 Set Vref, RX VrefLevel [Byte0]: 54
1704 12:43:02.209888 [Byte1]: 54
1705 12:43:02.214147
1706 12:43:02.214227 Set Vref, RX VrefLevel [Byte0]: 55
1707 12:43:02.217401 [Byte1]: 55
1708 12:43:02.221866
1709 12:43:02.221947 Set Vref, RX VrefLevel [Byte0]: 56
1710 12:43:02.225142 [Byte1]: 56
1711 12:43:02.229098
1712 12:43:02.229179 Set Vref, RX VrefLevel [Byte0]: 57
1713 12:43:02.232701 [Byte1]: 57
1714 12:43:02.236593
1715 12:43:02.236674 Set Vref, RX VrefLevel [Byte0]: 58
1716 12:43:02.239880 [Byte1]: 58
1717 12:43:02.244453
1718 12:43:02.244533 Set Vref, RX VrefLevel [Byte0]: 59
1719 12:43:02.247877 [Byte1]: 59
1720 12:43:02.252107
1721 12:43:02.252187 Set Vref, RX VrefLevel [Byte0]: 60
1722 12:43:02.255565 [Byte1]: 60
1723 12:43:02.259639
1724 12:43:02.259720 Set Vref, RX VrefLevel [Byte0]: 61
1725 12:43:02.263025 [Byte1]: 61
1726 12:43:02.267040
1727 12:43:02.267121 Set Vref, RX VrefLevel [Byte0]: 62
1728 12:43:02.270374 [Byte1]: 62
1729 12:43:02.274292
1730 12:43:02.274373 Set Vref, RX VrefLevel [Byte0]: 63
1731 12:43:02.278106 [Byte1]: 63
1732 12:43:02.282374
1733 12:43:02.282454 Set Vref, RX VrefLevel [Byte0]: 64
1734 12:43:02.285693 [Byte1]: 64
1735 12:43:02.289727
1736 12:43:02.289808 Set Vref, RX VrefLevel [Byte0]: 65
1737 12:43:02.293191 [Byte1]: 65
1738 12:43:02.297184
1739 12:43:02.297265 Set Vref, RX VrefLevel [Byte0]: 66
1740 12:43:02.300732 [Byte1]: 66
1741 12:43:02.304648
1742 12:43:02.304729 Set Vref, RX VrefLevel [Byte0]: 67
1743 12:43:02.308325 [Byte1]: 67
1744 12:43:02.312176
1745 12:43:02.312257 Set Vref, RX VrefLevel [Byte0]: 68
1746 12:43:02.315643 [Byte1]: 68
1747 12:43:02.319829
1748 12:43:02.319910 Set Vref, RX VrefLevel [Byte0]: 69
1749 12:43:02.323265 [Byte1]: 69
1750 12:43:02.327440
1751 12:43:02.327521 Set Vref, RX VrefLevel [Byte0]: 70
1752 12:43:02.331021 [Byte1]: 70
1753 12:43:02.334937
1754 12:43:02.335017 Set Vref, RX VrefLevel [Byte0]: 71
1755 12:43:02.338374 [Byte1]: 71
1756 12:43:02.342380
1757 12:43:02.342461 Set Vref, RX VrefLevel [Byte0]: 72
1758 12:43:02.346188 [Byte1]: 72
1759 12:43:02.350293
1760 12:43:02.350374 Final RX Vref Byte 0 = 59 to rank0
1761 12:43:02.353736 Final RX Vref Byte 1 = 55 to rank0
1762 12:43:02.356964 Final RX Vref Byte 0 = 59 to rank1
1763 12:43:02.359983 Final RX Vref Byte 1 = 55 to rank1==
1764 12:43:02.363438 Dram Type= 6, Freq= 0, CH_1, rank 0
1765 12:43:02.366925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1766 12:43:02.370296 ==
1767 12:43:02.370374 DQS Delay:
1768 12:43:02.370446 DQS0 = 0, DQS1 = 0
1769 12:43:02.373866 DQM Delay:
1770 12:43:02.373948 DQM0 = 96, DQM1 = 89
1771 12:43:02.376663 DQ Delay:
1772 12:43:02.376739 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =92
1773 12:43:02.380086 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1774 12:43:02.383490 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1775 12:43:02.386705 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1776 12:43:02.390080
1777 12:43:02.390157
1778 12:43:02.396977 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1779 12:43:02.400431 CH1 RK0: MR19=606, MR18=2E4A
1780 12:43:02.406638 CH1_RK0: MR19=0x606, MR18=0x2E4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1781 12:43:02.406727
1782 12:43:02.410112 ----->DramcWriteLeveling(PI) begin...
1783 12:43:02.410194 ==
1784 12:43:02.413560 Dram Type= 6, Freq= 0, CH_1, rank 1
1785 12:43:02.416691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1786 12:43:02.416765 ==
1787 12:43:02.420435 Write leveling (Byte 0): 25 => 25
1788 12:43:02.423526 Write leveling (Byte 1): 31 => 31
1789 12:43:02.426657 DramcWriteLeveling(PI) end<-----
1790 12:43:02.426732
1791 12:43:02.426805 ==
1792 12:43:02.430053 Dram Type= 6, Freq= 0, CH_1, rank 1
1793 12:43:02.433540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1794 12:43:02.433612 ==
1795 12:43:02.437166 [Gating] SW mode calibration
1796 12:43:02.443925 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1797 12:43:02.450396 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1798 12:43:02.453834 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1799 12:43:02.457237 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1800 12:43:02.464043 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1801 12:43:02.467145 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 12:43:02.470421 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 12:43:02.476845 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 12:43:02.480542 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 12:43:02.483755 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 12:43:02.487271 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 12:43:02.493979 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 12:43:02.497097 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 12:43:02.500280 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 12:43:02.506878 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 12:43:02.510411 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 12:43:02.513894 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 12:43:02.520752 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 12:43:02.523455 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 12:43:02.526913 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1816 12:43:02.533824 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 12:43:02.537278 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 12:43:02.540586 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 12:43:02.547270 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 12:43:02.550779 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 12:43:02.553563 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 12:43:02.560692 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 12:43:02.563428 0 9 4 | B1->B0 | 2c2c 2323 | 1 0 | (1 1) (0 0)
1824 12:43:02.566850 0 9 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
1825 12:43:02.573759 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 12:43:02.577103 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 12:43:02.580235 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 12:43:02.583661 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 12:43:02.590272 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 12:43:02.593583 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1831 12:43:02.597312 0 10 4 | B1->B0 | 2a2a 3030 | 1 1 | (1 0) (1 0)
1832 12:43:02.603615 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 12:43:02.606957 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 12:43:02.610590 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 12:43:02.617131 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 12:43:02.620474 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 12:43:02.623628 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 12:43:02.630650 0 11 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1839 12:43:02.634086 0 11 4 | B1->B0 | 3f3f 2d2d | 0 0 | (0 0) (0 0)
1840 12:43:02.637517 0 11 8 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
1841 12:43:02.644106 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 12:43:02.647508 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 12:43:02.650866 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 12:43:02.657397 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 12:43:02.660863 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 12:43:02.664323 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 12:43:02.667062 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1848 12:43:02.673897 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 12:43:02.677428 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 12:43:02.680234 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 12:43:02.686909 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 12:43:02.690220 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 12:43:02.693655 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 12:43:02.700450 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 12:43:02.703683 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 12:43:02.707538 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 12:43:02.714161 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 12:43:02.717070 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 12:43:02.721022 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 12:43:02.727288 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 12:43:02.730909 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 12:43:02.733997 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 12:43:02.741064 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1864 12:43:02.741152 Total UI for P1: 0, mck2ui 16
1865 12:43:02.743874 best dqsien dly found for B0: ( 0, 14, 2)
1866 12:43:02.750835 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 12:43:02.754056 Total UI for P1: 0, mck2ui 16
1868 12:43:02.757459 best dqsien dly found for B1: ( 0, 14, 4)
1869 12:43:02.760771 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1870 12:43:02.763989 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1871 12:43:02.764064
1872 12:43:02.767314 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1873 12:43:02.770843 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1874 12:43:02.774347 [Gating] SW calibration Done
1875 12:43:02.774430 ==
1876 12:43:02.777754 Dram Type= 6, Freq= 0, CH_1, rank 1
1877 12:43:02.781126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1878 12:43:02.781224 ==
1879 12:43:02.784556 RX Vref Scan: 0
1880 12:43:02.784644
1881 12:43:02.784710 RX Vref 0 -> 0, step: 1
1882 12:43:02.784780
1883 12:43:02.787405 RX Delay -130 -> 252, step: 16
1884 12:43:02.790777 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1885 12:43:02.797528 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1886 12:43:02.801090 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1887 12:43:02.804798 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1888 12:43:02.808144 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1889 12:43:02.810784 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1890 12:43:02.817594 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1891 12:43:02.820967 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1892 12:43:02.824425 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1893 12:43:02.827903 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1894 12:43:02.831242 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1895 12:43:02.837678 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1896 12:43:02.840884 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1897 12:43:02.844638 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1898 12:43:02.847661 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1899 12:43:02.850854 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1900 12:43:02.854801 ==
1901 12:43:02.854947 Dram Type= 6, Freq= 0, CH_1, rank 1
1902 12:43:02.861326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1903 12:43:02.861411 ==
1904 12:43:02.861476 DQS Delay:
1905 12:43:02.864511 DQS0 = 0, DQS1 = 0
1906 12:43:02.864593 DQM Delay:
1907 12:43:02.868014 DQM0 = 94, DQM1 = 88
1908 12:43:02.868095 DQ Delay:
1909 12:43:02.871111 DQ0 =101, DQ1 =93, DQ2 =85, DQ3 =85
1910 12:43:02.874477 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1911 12:43:02.877912 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1912 12:43:02.881346 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1913 12:43:02.881421
1914 12:43:02.881483
1915 12:43:02.881550 ==
1916 12:43:02.884883 Dram Type= 6, Freq= 0, CH_1, rank 1
1917 12:43:02.888403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1918 12:43:02.888474 ==
1919 12:43:02.888534
1920 12:43:02.888602
1921 12:43:02.891915 TX Vref Scan disable
1922 12:43:02.891983 == TX Byte 0 ==
1923 12:43:02.897966 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1924 12:43:02.901580 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1925 12:43:02.901654 == TX Byte 1 ==
1926 12:43:02.908334 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1927 12:43:02.911855 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1928 12:43:02.911933 ==
1929 12:43:02.915167 Dram Type= 6, Freq= 0, CH_1, rank 1
1930 12:43:02.918627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1931 12:43:02.918698 ==
1932 12:43:02.932875 TX Vref=22, minBit 2, minWin=26, winSum=438
1933 12:43:02.936362 TX Vref=24, minBit 0, minWin=27, winSum=443
1934 12:43:02.939824 TX Vref=26, minBit 0, minWin=27, winSum=446
1935 12:43:02.943206 TX Vref=28, minBit 0, minWin=27, winSum=448
1936 12:43:02.945946 TX Vref=30, minBit 2, minWin=27, winSum=451
1937 12:43:02.949365 TX Vref=32, minBit 0, minWin=27, winSum=446
1938 12:43:02.956636 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 30
1939 12:43:02.956723
1940 12:43:02.959848 Final TX Range 1 Vref 30
1941 12:43:02.959927
1942 12:43:02.959997 ==
1943 12:43:02.963089 Dram Type= 6, Freq= 0, CH_1, rank 1
1944 12:43:02.966228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1945 12:43:02.966302 ==
1946 12:43:02.966370
1947 12:43:02.966468
1948 12:43:02.969938 TX Vref Scan disable
1949 12:43:02.972956 == TX Byte 0 ==
1950 12:43:02.976023 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1951 12:43:02.979636 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1952 12:43:02.982851 == TX Byte 1 ==
1953 12:43:02.986004 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1954 12:43:02.989802 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1955 12:43:02.993243
1956 12:43:02.993319 [DATLAT]
1957 12:43:02.993380 Freq=800, CH1 RK1
1958 12:43:02.993440
1959 12:43:02.995977 DATLAT Default: 0xa
1960 12:43:02.996051 0, 0xFFFF, sum = 0
1961 12:43:02.999336 1, 0xFFFF, sum = 0
1962 12:43:02.999409 2, 0xFFFF, sum = 0
1963 12:43:03.002953 3, 0xFFFF, sum = 0
1964 12:43:03.003045 4, 0xFFFF, sum = 0
1965 12:43:03.006360 5, 0xFFFF, sum = 0
1966 12:43:03.006447 6, 0xFFFF, sum = 0
1967 12:43:03.009484 7, 0xFFFF, sum = 0
1968 12:43:03.013185 8, 0xFFFF, sum = 0
1969 12:43:03.013267 9, 0x0, sum = 1
1970 12:43:03.013332 10, 0x0, sum = 2
1971 12:43:03.016494 11, 0x0, sum = 3
1972 12:43:03.016572 12, 0x0, sum = 4
1973 12:43:03.019903 best_step = 10
1974 12:43:03.019982
1975 12:43:03.020048 ==
1976 12:43:03.022750 Dram Type= 6, Freq= 0, CH_1, rank 1
1977 12:43:03.026190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1978 12:43:03.026286 ==
1979 12:43:03.029714 RX Vref Scan: 0
1980 12:43:03.029789
1981 12:43:03.029859 RX Vref 0 -> 0, step: 1
1982 12:43:03.029933
1983 12:43:03.033079 RX Delay -79 -> 252, step: 8
1984 12:43:03.039751 iDelay=209, Bit 0, Center 100 (1 ~ 200) 200
1985 12:43:03.043218 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1986 12:43:03.046652 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1987 12:43:03.049601 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1988 12:43:03.053033 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1989 12:43:03.056628 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
1990 12:43:03.063326 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1991 12:43:03.066206 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1992 12:43:03.069657 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1993 12:43:03.073078 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1994 12:43:03.076410 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
1995 12:43:03.083125 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
1996 12:43:03.086884 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
1997 12:43:03.089966 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
1998 12:43:03.092962 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
1999 12:43:03.096837 iDelay=209, Bit 15, Center 100 (-7 ~ 208) 216
2000 12:43:03.096925 ==
2001 12:43:03.099979 Dram Type= 6, Freq= 0, CH_1, rank 1
2002 12:43:03.106679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2003 12:43:03.106786 ==
2004 12:43:03.106869 DQS Delay:
2005 12:43:03.109795 DQS0 = 0, DQS1 = 0
2006 12:43:03.109939 DQM Delay:
2007 12:43:03.110033 DQM0 = 96, DQM1 = 91
2008 12:43:03.113179 DQ Delay:
2009 12:43:03.116593 DQ0 =100, DQ1 =92, DQ2 =84, DQ3 =92
2010 12:43:03.120029 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
2011 12:43:03.123628 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2012 12:43:03.126350 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =100
2013 12:43:03.126430
2014 12:43:03.126493
2015 12:43:03.133627 [DQSOSCAuto] RK1, (LSB)MR18= 0x4913, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
2016 12:43:03.136938 CH1 RK1: MR19=606, MR18=4913
2017 12:43:03.143211 CH1_RK1: MR19=0x606, MR18=0x4913, DQSOSC=391, MR23=63, INC=96, DEC=64
2018 12:43:03.146486 [RxdqsGatingPostProcess] freq 800
2019 12:43:03.149961 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2020 12:43:03.153385 Pre-setting of DQS Precalculation
2021 12:43:03.159732 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2022 12:43:03.166475 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2023 12:43:03.173453 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2024 12:43:03.173550
2025 12:43:03.173617
2026 12:43:03.177036 [Calibration Summary] 1600 Mbps
2027 12:43:03.177119 CH 0, Rank 0
2028 12:43:03.179765 SW Impedance : PASS
2029 12:43:03.183129 DUTY Scan : NO K
2030 12:43:03.183209 ZQ Calibration : PASS
2031 12:43:03.186646 Jitter Meter : NO K
2032 12:43:03.190154 CBT Training : PASS
2033 12:43:03.190231 Write leveling : PASS
2034 12:43:03.193639 RX DQS gating : PASS
2035 12:43:03.196983 RX DQ/DQS(RDDQC) : PASS
2036 12:43:03.197058 TX DQ/DQS : PASS
2037 12:43:03.200039 RX DATLAT : PASS
2038 12:43:03.200121 RX DQ/DQS(Engine): PASS
2039 12:43:03.203333 TX OE : NO K
2040 12:43:03.203411 All Pass.
2041 12:43:03.203479
2042 12:43:03.206535 CH 0, Rank 1
2043 12:43:03.206612 SW Impedance : PASS
2044 12:43:03.209795 DUTY Scan : NO K
2045 12:43:03.213740 ZQ Calibration : PASS
2046 12:43:03.213822 Jitter Meter : NO K
2047 12:43:03.217007 CBT Training : PASS
2048 12:43:03.220257 Write leveling : PASS
2049 12:43:03.220348 RX DQS gating : PASS
2050 12:43:03.223651 RX DQ/DQS(RDDQC) : PASS
2051 12:43:03.226690 TX DQ/DQS : PASS
2052 12:43:03.226766 RX DATLAT : PASS
2053 12:43:03.229888 RX DQ/DQS(Engine): PASS
2054 12:43:03.233606 TX OE : NO K
2055 12:43:03.233684 All Pass.
2056 12:43:03.233757
2057 12:43:03.233819 CH 1, Rank 0
2058 12:43:03.237051 SW Impedance : PASS
2059 12:43:03.239763 DUTY Scan : NO K
2060 12:43:03.239844 ZQ Calibration : PASS
2061 12:43:03.243186 Jitter Meter : NO K
2062 12:43:03.246700 CBT Training : PASS
2063 12:43:03.246772 Write leveling : PASS
2064 12:43:03.250543 RX DQS gating : PASS
2065 12:43:03.250619 RX DQ/DQS(RDDQC) : PASS
2066 12:43:03.253875 TX DQ/DQS : PASS
2067 12:43:03.256746 RX DATLAT : PASS
2068 12:43:03.256823 RX DQ/DQS(Engine): PASS
2069 12:43:03.260246 TX OE : NO K
2070 12:43:03.260337 All Pass.
2071 12:43:03.260426
2072 12:43:03.263690 CH 1, Rank 1
2073 12:43:03.263766 SW Impedance : PASS
2074 12:43:03.267099 DUTY Scan : NO K
2075 12:43:03.270441 ZQ Calibration : PASS
2076 12:43:03.270523 Jitter Meter : NO K
2077 12:43:03.273755 CBT Training : PASS
2078 12:43:03.277231 Write leveling : PASS
2079 12:43:03.277303 RX DQS gating : PASS
2080 12:43:03.280716 RX DQ/DQS(RDDQC) : PASS
2081 12:43:03.280795 TX DQ/DQS : PASS
2082 12:43:03.283559 RX DATLAT : PASS
2083 12:43:03.287104 RX DQ/DQS(Engine): PASS
2084 12:43:03.287181 TX OE : NO K
2085 12:43:03.290548 All Pass.
2086 12:43:03.290618
2087 12:43:03.290685 DramC Write-DBI off
2088 12:43:03.293973 PER_BANK_REFRESH: Hybrid Mode
2089 12:43:03.296853 TX_TRACKING: ON
2090 12:43:03.300315 [GetDramInforAfterCalByMRR] Vendor 6.
2091 12:43:03.303691 [GetDramInforAfterCalByMRR] Revision 606.
2092 12:43:03.307080 [GetDramInforAfterCalByMRR] Revision 2 0.
2093 12:43:03.307159 MR0 0x3b3b
2094 12:43:03.307224 MR8 0x5151
2095 12:43:03.313877 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2096 12:43:03.313965
2097 12:43:03.314032 MR0 0x3b3b
2098 12:43:03.314092 MR8 0x5151
2099 12:43:03.316979 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2100 12:43:03.317060
2101 12:43:03.327028 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2102 12:43:03.330369 [FAST_K] Save calibration result to emmc
2103 12:43:03.333764 [FAST_K] Save calibration result to emmc
2104 12:43:03.337114 dram_init: config_dvfs: 1
2105 12:43:03.340527 dramc_set_vcore_voltage set vcore to 662500
2106 12:43:03.343647 Read voltage for 1200, 2
2107 12:43:03.343723 Vio18 = 0
2108 12:43:03.343793 Vcore = 662500
2109 12:43:03.347445 Vdram = 0
2110 12:43:03.347524 Vddq = 0
2111 12:43:03.347587 Vmddr = 0
2112 12:43:03.353669 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2113 12:43:03.356859 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2114 12:43:03.360704 MEM_TYPE=3, freq_sel=15
2115 12:43:03.363842 sv_algorithm_assistance_LP4_1600
2116 12:43:03.367450 ============ PULL DRAM RESETB DOWN ============
2117 12:43:03.370916 ========== PULL DRAM RESETB DOWN end =========
2118 12:43:03.377400 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2119 12:43:03.380828 ===================================
2120 12:43:03.380931 LPDDR4 DRAM CONFIGURATION
2121 12:43:03.383596 ===================================
2122 12:43:03.387084 EX_ROW_EN[0] = 0x0
2123 12:43:03.391067 EX_ROW_EN[1] = 0x0
2124 12:43:03.391167 LP4Y_EN = 0x0
2125 12:43:03.393863 WORK_FSP = 0x0
2126 12:43:03.393958 WL = 0x4
2127 12:43:03.397223 RL = 0x4
2128 12:43:03.397297 BL = 0x2
2129 12:43:03.400680 RPST = 0x0
2130 12:43:03.400776 RD_PRE = 0x0
2131 12:43:03.404153 WR_PRE = 0x1
2132 12:43:03.404261 WR_PST = 0x0
2133 12:43:03.406956 DBI_WR = 0x0
2134 12:43:03.407025 DBI_RD = 0x0
2135 12:43:03.411110 OTF = 0x1
2136 12:43:03.413761 ===================================
2137 12:43:03.417220 ===================================
2138 12:43:03.417300 ANA top config
2139 12:43:03.420613 ===================================
2140 12:43:03.423909 DLL_ASYNC_EN = 0
2141 12:43:03.427134 ALL_SLAVE_EN = 0
2142 12:43:03.427238 NEW_RANK_MODE = 1
2143 12:43:03.430941 DLL_IDLE_MODE = 1
2144 12:43:03.434129 LP45_APHY_COMB_EN = 1
2145 12:43:03.437251 TX_ODT_DIS = 1
2146 12:43:03.440704 NEW_8X_MODE = 1
2147 12:43:03.444243 ===================================
2148 12:43:03.444378 ===================================
2149 12:43:03.447653 data_rate = 2400
2150 12:43:03.450437 CKR = 1
2151 12:43:03.453773 DQ_P2S_RATIO = 8
2152 12:43:03.457723 ===================================
2153 12:43:03.460969 CA_P2S_RATIO = 8
2154 12:43:03.464102 DQ_CA_OPEN = 0
2155 12:43:03.464201 DQ_SEMI_OPEN = 0
2156 12:43:03.467736 CA_SEMI_OPEN = 0
2157 12:43:03.470940 CA_FULL_RATE = 0
2158 12:43:03.473967 DQ_CKDIV4_EN = 0
2159 12:43:03.477709 CA_CKDIV4_EN = 0
2160 12:43:03.480580 CA_PREDIV_EN = 0
2161 12:43:03.480665 PH8_DLY = 17
2162 12:43:03.484199 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2163 12:43:03.487348 DQ_AAMCK_DIV = 4
2164 12:43:03.490811 CA_AAMCK_DIV = 4
2165 12:43:03.494288 CA_ADMCK_DIV = 4
2166 12:43:03.497767 DQ_TRACK_CA_EN = 0
2167 12:43:03.501447 CA_PICK = 1200
2168 12:43:03.501526 CA_MCKIO = 1200
2169 12:43:03.504463 MCKIO_SEMI = 0
2170 12:43:03.507330 PLL_FREQ = 2366
2171 12:43:03.510784 DQ_UI_PI_RATIO = 32
2172 12:43:03.514068 CA_UI_PI_RATIO = 0
2173 12:43:03.517317 ===================================
2174 12:43:03.520901 ===================================
2175 12:43:03.524435 memory_type:LPDDR4
2176 12:43:03.524510 GP_NUM : 10
2177 12:43:03.527691 SRAM_EN : 1
2178 12:43:03.527765 MD32_EN : 0
2179 12:43:03.530557 ===================================
2180 12:43:03.533984 [ANA_INIT] >>>>>>>>>>>>>>
2181 12:43:03.537430 <<<<<< [CONFIGURE PHASE]: ANA_TX
2182 12:43:03.540687 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2183 12:43:03.544377 ===================================
2184 12:43:03.547256 data_rate = 2400,PCW = 0X5b00
2185 12:43:03.551053 ===================================
2186 12:43:03.553903 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2187 12:43:03.557253 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2188 12:43:03.564207 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2189 12:43:03.567734 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2190 12:43:03.573792 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2191 12:43:03.577232 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2192 12:43:03.577310 [ANA_INIT] flow start
2193 12:43:03.580511 [ANA_INIT] PLL >>>>>>>>
2194 12:43:03.584441 [ANA_INIT] PLL <<<<<<<<
2195 12:43:03.584518 [ANA_INIT] MIDPI >>>>>>>>
2196 12:43:03.587826 [ANA_INIT] MIDPI <<<<<<<<
2197 12:43:03.590684 [ANA_INIT] DLL >>>>>>>>
2198 12:43:03.590774 [ANA_INIT] DLL <<<<<<<<
2199 12:43:03.593922 [ANA_INIT] flow end
2200 12:43:03.597632 ============ LP4 DIFF to SE enter ============
2201 12:43:03.600648 ============ LP4 DIFF to SE exit ============
2202 12:43:03.604420 [ANA_INIT] <<<<<<<<<<<<<
2203 12:43:03.607191 [Flow] Enable top DCM control >>>>>
2204 12:43:03.610684 [Flow] Enable top DCM control <<<<<
2205 12:43:03.614061 Enable DLL master slave shuffle
2206 12:43:03.620876 ==============================================================
2207 12:43:03.620960 Gating Mode config
2208 12:43:03.627199 ==============================================================
2209 12:43:03.627277 Config description:
2210 12:43:03.637634 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2211 12:43:03.644574 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2212 12:43:03.650793 SELPH_MODE 0: By rank 1: By Phase
2213 12:43:03.654119 ==============================================================
2214 12:43:03.657434 GAT_TRACK_EN = 1
2215 12:43:03.660530 RX_GATING_MODE = 2
2216 12:43:03.663954 RX_GATING_TRACK_MODE = 2
2217 12:43:03.667758 SELPH_MODE = 1
2218 12:43:03.671094 PICG_EARLY_EN = 1
2219 12:43:03.674638 VALID_LAT_VALUE = 1
2220 12:43:03.677433 ==============================================================
2221 12:43:03.680878 Enter into Gating configuration >>>>
2222 12:43:03.684399 Exit from Gating configuration <<<<
2223 12:43:03.687708 Enter into DVFS_PRE_config >>>>>
2224 12:43:03.701010 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2225 12:43:03.701103 Exit from DVFS_PRE_config <<<<<
2226 12:43:03.704273 Enter into PICG configuration >>>>
2227 12:43:03.707825 Exit from PICG configuration <<<<
2228 12:43:03.710881 [RX_INPUT] configuration >>>>>
2229 12:43:03.714661 [RX_INPUT] configuration <<<<<
2230 12:43:03.721058 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2231 12:43:03.724237 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2232 12:43:03.730725 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2233 12:43:03.737558 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2234 12:43:03.744434 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2235 12:43:03.751573 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2236 12:43:03.754423 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2237 12:43:03.757932 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2238 12:43:03.761413 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2239 12:43:03.767594 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2240 12:43:03.771433 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2241 12:43:03.774821 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2242 12:43:03.777809 ===================================
2243 12:43:03.781422 LPDDR4 DRAM CONFIGURATION
2244 12:43:03.784601 ===================================
2245 12:43:03.784671 EX_ROW_EN[0] = 0x0
2246 12:43:03.787968 EX_ROW_EN[1] = 0x0
2247 12:43:03.788045 LP4Y_EN = 0x0
2248 12:43:03.791422 WORK_FSP = 0x0
2249 12:43:03.791495 WL = 0x4
2250 12:43:03.794879 RL = 0x4
2251 12:43:03.794962 BL = 0x2
2252 12:43:03.798182 RPST = 0x0
2253 12:43:03.801497 RD_PRE = 0x0
2254 12:43:03.801620 WR_PRE = 0x1
2255 12:43:03.804750 WR_PST = 0x0
2256 12:43:03.804836 DBI_WR = 0x0
2257 12:43:03.808113 DBI_RD = 0x0
2258 12:43:03.808202 OTF = 0x1
2259 12:43:03.811386 ===================================
2260 12:43:03.814906 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2261 12:43:03.818182 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2262 12:43:03.824729 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2263 12:43:03.828115 ===================================
2264 12:43:03.831392 LPDDR4 DRAM CONFIGURATION
2265 12:43:03.831464 ===================================
2266 12:43:03.834683 EX_ROW_EN[0] = 0x10
2267 12:43:03.837792 EX_ROW_EN[1] = 0x0
2268 12:43:03.837863 LP4Y_EN = 0x0
2269 12:43:03.841413 WORK_FSP = 0x0
2270 12:43:03.841486 WL = 0x4
2271 12:43:03.844647 RL = 0x4
2272 12:43:03.844724 BL = 0x2
2273 12:43:03.848130 RPST = 0x0
2274 12:43:03.848226 RD_PRE = 0x0
2275 12:43:03.851618 WR_PRE = 0x1
2276 12:43:03.851693 WR_PST = 0x0
2277 12:43:03.855108 DBI_WR = 0x0
2278 12:43:03.855191 DBI_RD = 0x0
2279 12:43:03.857889 OTF = 0x1
2280 12:43:03.861353 ===================================
2281 12:43:03.868423 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2282 12:43:03.868528 ==
2283 12:43:03.871756 Dram Type= 6, Freq= 0, CH_0, rank 0
2284 12:43:03.874518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2285 12:43:03.874588 ==
2286 12:43:03.877907 [Duty_Offset_Calibration]
2287 12:43:03.877977 B0:2 B1:1 CA:1
2288 12:43:03.878036
2289 12:43:03.881247 [DutyScan_Calibration_Flow] k_type=0
2290 12:43:03.891744
2291 12:43:03.891826 ==CLK 0==
2292 12:43:03.894958 Final CLK duty delay cell = 0
2293 12:43:03.898192 [0] MAX Duty = 5218%(X100), DQS PI = 24
2294 12:43:03.901702 [0] MIN Duty = 4844%(X100), DQS PI = 48
2295 12:43:03.901813 [0] AVG Duty = 5031%(X100)
2296 12:43:03.905009
2297 12:43:03.908430 CH0 CLK Duty spec in!! Max-Min= 374%
2298 12:43:03.911686 [DutyScan_Calibration_Flow] ====Done====
2299 12:43:03.911757
2300 12:43:03.914926 [DutyScan_Calibration_Flow] k_type=1
2301 12:43:03.929411
2302 12:43:03.929488 ==DQS 0 ==
2303 12:43:03.933301 Final DQS duty delay cell = -4
2304 12:43:03.936059 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2305 12:43:03.939591 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2306 12:43:03.942910 [-4] AVG Duty = 4937%(X100)
2307 12:43:03.942983
2308 12:43:03.943043 ==DQS 1 ==
2309 12:43:03.946291 Final DQS duty delay cell = -4
2310 12:43:03.949607 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2311 12:43:03.952817 [-4] MIN Duty = 4844%(X100), DQS PI = 32
2312 12:43:03.956672 [-4] AVG Duty = 4906%(X100)
2313 12:43:03.956768
2314 12:43:03.959740 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2315 12:43:03.959821
2316 12:43:03.963047 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2317 12:43:03.966447 [DutyScan_Calibration_Flow] ====Done====
2318 12:43:03.966520
2319 12:43:03.969857 [DutyScan_Calibration_Flow] k_type=3
2320 12:43:03.986568
2321 12:43:03.986672 ==DQM 0 ==
2322 12:43:03.989823 Final DQM duty delay cell = 0
2323 12:43:03.993290 [0] MAX Duty = 5156%(X100), DQS PI = 28
2324 12:43:03.996756 [0] MIN Duty = 4938%(X100), DQS PI = 0
2325 12:43:03.996840 [0] AVG Duty = 5047%(X100)
2326 12:43:04.000084
2327 12:43:04.000154 ==DQM 1 ==
2328 12:43:04.003343 Final DQM duty delay cell = 0
2329 12:43:04.006745 [0] MAX Duty = 5124%(X100), DQS PI = 6
2330 12:43:04.010056 [0] MIN Duty = 5031%(X100), DQS PI = 16
2331 12:43:04.010126 [0] AVG Duty = 5077%(X100)
2332 12:43:04.010192
2333 12:43:04.013263 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2334 12:43:04.017119
2335 12:43:04.020437 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2336 12:43:04.023706 [DutyScan_Calibration_Flow] ====Done====
2337 12:43:04.023778
2338 12:43:04.027034 [DutyScan_Calibration_Flow] k_type=2
2339 12:43:04.043270
2340 12:43:04.043348 ==DQ 0 ==
2341 12:43:04.046481 Final DQ duty delay cell = 0
2342 12:43:04.049750 [0] MAX Duty = 5031%(X100), DQS PI = 26
2343 12:43:04.053177 [0] MIN Duty = 4844%(X100), DQS PI = 62
2344 12:43:04.053245 [0] AVG Duty = 4937%(X100)
2345 12:43:04.053305
2346 12:43:04.056721 ==DQ 1 ==
2347 12:43:04.060157 Final DQ duty delay cell = 0
2348 12:43:04.062972 [0] MAX Duty = 5093%(X100), DQS PI = 24
2349 12:43:04.066320 [0] MIN Duty = 4938%(X100), DQS PI = 34
2350 12:43:04.066390 [0] AVG Duty = 5015%(X100)
2351 12:43:04.066455
2352 12:43:04.069806 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2353 12:43:04.069884
2354 12:43:04.073023 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2355 12:43:04.079709 [DutyScan_Calibration_Flow] ====Done====
2356 12:43:04.079787 ==
2357 12:43:04.083085 Dram Type= 6, Freq= 0, CH_1, rank 0
2358 12:43:04.086817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2359 12:43:04.086888 ==
2360 12:43:04.090015 [Duty_Offset_Calibration]
2361 12:43:04.090083 B0:1 B1:0 CA:0
2362 12:43:04.090142
2363 12:43:04.093321 [DutyScan_Calibration_Flow] k_type=0
2364 12:43:04.102463
2365 12:43:04.102538 ==CLK 0==
2366 12:43:04.105785 Final CLK duty delay cell = -4
2367 12:43:04.109151 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2368 12:43:04.112615 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2369 12:43:04.115974 [-4] AVG Duty = 4953%(X100)
2370 12:43:04.116046
2371 12:43:04.118792 CH1 CLK Duty spec in!! Max-Min= 93%
2372 12:43:04.122177 [DutyScan_Calibration_Flow] ====Done====
2373 12:43:04.122250
2374 12:43:04.125960 [DutyScan_Calibration_Flow] k_type=1
2375 12:43:04.142136
2376 12:43:04.142221 ==DQS 0 ==
2377 12:43:04.145370 Final DQS duty delay cell = 0
2378 12:43:04.148777 [0] MAX Duty = 5094%(X100), DQS PI = 26
2379 12:43:04.152081 [0] MIN Duty = 4875%(X100), DQS PI = 0
2380 12:43:04.152183 [0] AVG Duty = 4984%(X100)
2381 12:43:04.155505
2382 12:43:04.155575 ==DQS 1 ==
2383 12:43:04.158246 Final DQS duty delay cell = 0
2384 12:43:04.161669 [0] MAX Duty = 5187%(X100), DQS PI = 18
2385 12:43:04.165166 [0] MIN Duty = 4969%(X100), DQS PI = 10
2386 12:43:04.165249 [0] AVG Duty = 5078%(X100)
2387 12:43:04.168672
2388 12:43:04.172222 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2389 12:43:04.172358
2390 12:43:04.174901 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2391 12:43:04.178564 [DutyScan_Calibration_Flow] ====Done====
2392 12:43:04.178637
2393 12:43:04.181866 [DutyScan_Calibration_Flow] k_type=3
2394 12:43:04.198765
2395 12:43:04.198853 ==DQM 0 ==
2396 12:43:04.201668 Final DQM duty delay cell = 0
2397 12:43:04.205077 [0] MAX Duty = 5156%(X100), DQS PI = 6
2398 12:43:04.208517 [0] MIN Duty = 5031%(X100), DQS PI = 0
2399 12:43:04.208623 [0] AVG Duty = 5093%(X100)
2400 12:43:04.211846
2401 12:43:04.211943 ==DQM 1 ==
2402 12:43:04.215588 Final DQM duty delay cell = 0
2403 12:43:04.218842 [0] MAX Duty = 5031%(X100), DQS PI = 16
2404 12:43:04.221648 [0] MIN Duty = 4907%(X100), DQS PI = 36
2405 12:43:04.221728 [0] AVG Duty = 4969%(X100)
2406 12:43:04.225050
2407 12:43:04.228465 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2408 12:43:04.228551
2409 12:43:04.231773 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2410 12:43:04.235099 [DutyScan_Calibration_Flow] ====Done====
2411 12:43:04.235179
2412 12:43:04.238243 [DutyScan_Calibration_Flow] k_type=2
2413 12:43:04.254105
2414 12:43:04.254184 ==DQ 0 ==
2415 12:43:04.257781 Final DQ duty delay cell = -4
2416 12:43:04.260953 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2417 12:43:04.264306 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2418 12:43:04.267815 [-4] AVG Duty = 4984%(X100)
2419 12:43:04.267893
2420 12:43:04.267956 ==DQ 1 ==
2421 12:43:04.271124 Final DQ duty delay cell = 0
2422 12:43:04.274694 [0] MAX Duty = 5125%(X100), DQS PI = 20
2423 12:43:04.278094 [0] MIN Duty = 4969%(X100), DQS PI = 12
2424 12:43:04.278173 [0] AVG Duty = 5047%(X100)
2425 12:43:04.278245
2426 12:43:04.284457 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2427 12:43:04.284537
2428 12:43:04.287897 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2429 12:43:04.291336 [DutyScan_Calibration_Flow] ====Done====
2430 12:43:04.294116 nWR fixed to 30
2431 12:43:04.294196 [ModeRegInit_LP4] CH0 RK0
2432 12:43:04.297343 [ModeRegInit_LP4] CH0 RK1
2433 12:43:04.301387 [ModeRegInit_LP4] CH1 RK0
2434 12:43:04.304386 [ModeRegInit_LP4] CH1 RK1
2435 12:43:04.304465 match AC timing 7
2436 12:43:04.308055 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2437 12:43:04.314131 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2438 12:43:04.317768 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2439 12:43:04.321022 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2440 12:43:04.327797 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2441 12:43:04.327876 ==
2442 12:43:04.331234 Dram Type= 6, Freq= 0, CH_0, rank 0
2443 12:43:04.334650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2444 12:43:04.334731 ==
2445 12:43:04.341612 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2446 12:43:04.344248 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2447 12:43:04.354322 [CA 0] Center 39 (8~70) winsize 63
2448 12:43:04.358286 [CA 1] Center 39 (8~70) winsize 63
2449 12:43:04.361559 [CA 2] Center 35 (4~66) winsize 63
2450 12:43:04.364868 [CA 3] Center 34 (4~65) winsize 62
2451 12:43:04.367863 [CA 4] Center 33 (3~64) winsize 62
2452 12:43:04.371627 [CA 5] Center 32 (3~62) winsize 60
2453 12:43:04.371708
2454 12:43:04.374740 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2455 12:43:04.374821
2456 12:43:04.378055 [CATrainingPosCal] consider 1 rank data
2457 12:43:04.381377 u2DelayCellTimex100 = 270/100 ps
2458 12:43:04.384906 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2459 12:43:04.387798 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2460 12:43:04.394701 CA2 delay=35 (4~66),Diff = 3 PI (14 cell)
2461 12:43:04.398118 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2462 12:43:04.401974 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2463 12:43:04.404559 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2464 12:43:04.404642
2465 12:43:04.408015 CA PerBit enable=1, Macro0, CA PI delay=32
2466 12:43:04.408090
2467 12:43:04.411372 [CBTSetCACLKResult] CA Dly = 32
2468 12:43:04.411446 CS Dly: 5 (0~36)
2469 12:43:04.411509 ==
2470 12:43:04.414725 Dram Type= 6, Freq= 0, CH_0, rank 1
2471 12:43:04.421611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2472 12:43:04.421690 ==
2473 12:43:04.424806 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2474 12:43:04.431474 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2475 12:43:04.440487 [CA 0] Center 38 (8~69) winsize 62
2476 12:43:04.443657 [CA 1] Center 38 (8~69) winsize 62
2477 12:43:04.446965 [CA 2] Center 35 (4~66) winsize 63
2478 12:43:04.450419 [CA 3] Center 34 (4~65) winsize 62
2479 12:43:04.453892 [CA 4] Center 33 (3~64) winsize 62
2480 12:43:04.456678 [CA 5] Center 32 (3~62) winsize 60
2481 12:43:04.456755
2482 12:43:04.460646 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2483 12:43:04.460724
2484 12:43:04.464033 [CATrainingPosCal] consider 2 rank data
2485 12:43:04.467122 u2DelayCellTimex100 = 270/100 ps
2486 12:43:04.470662 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2487 12:43:04.473996 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2488 12:43:04.480233 CA2 delay=35 (4~66),Diff = 3 PI (14 cell)
2489 12:43:04.484047 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2490 12:43:04.487447 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2491 12:43:04.490617 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2492 12:43:04.490690
2493 12:43:04.494036 CA PerBit enable=1, Macro0, CA PI delay=32
2494 12:43:04.494107
2495 12:43:04.497524 [CBTSetCACLKResult] CA Dly = 32
2496 12:43:04.497593 CS Dly: 6 (0~38)
2497 12:43:04.497661
2498 12:43:04.500277 ----->DramcWriteLeveling(PI) begin...
2499 12:43:04.500378 ==
2500 12:43:04.503848 Dram Type= 6, Freq= 0, CH_0, rank 0
2501 12:43:04.510801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2502 12:43:04.510889 ==
2503 12:43:04.513664 Write leveling (Byte 0): 34 => 34
2504 12:43:04.517176 Write leveling (Byte 1): 28 => 28
2505 12:43:04.517260 DramcWriteLeveling(PI) end<-----
2506 12:43:04.520319
2507 12:43:04.520412 ==
2508 12:43:04.524208 Dram Type= 6, Freq= 0, CH_0, rank 0
2509 12:43:04.527068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2510 12:43:04.527143 ==
2511 12:43:04.530502 [Gating] SW mode calibration
2512 12:43:04.537452 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2513 12:43:04.540843 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2514 12:43:04.547498 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2515 12:43:04.550885 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
2516 12:43:04.553818 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2517 12:43:04.560681 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2518 12:43:04.564112 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2519 12:43:04.567317 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2520 12:43:04.574080 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2521 12:43:04.577393 0 15 28 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
2522 12:43:04.580884 1 0 0 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
2523 12:43:04.587532 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 12:43:04.590708 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 12:43:04.594128 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 12:43:04.597364 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 12:43:04.604130 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 12:43:04.607603 1 0 24 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
2529 12:43:04.611055 1 0 28 | B1->B0 | 2828 4545 | 0 0 | (0 0) (0 0)
2530 12:43:04.617236 1 1 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
2531 12:43:04.620735 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2532 12:43:04.624124 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 12:43:04.630607 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 12:43:04.634049 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 12:43:04.637454 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 12:43:04.644230 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2537 12:43:04.647735 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2538 12:43:04.650609 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2539 12:43:04.657426 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 12:43:04.660836 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 12:43:04.664218 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 12:43:04.670891 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 12:43:04.674495 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 12:43:04.677447 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 12:43:04.680688 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 12:43:04.687410 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 12:43:04.691079 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 12:43:04.693967 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 12:43:04.700934 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 12:43:04.704000 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 12:43:04.707642 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 12:43:04.713976 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 12:43:04.717706 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2554 12:43:04.720575 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2555 12:43:04.724116 Total UI for P1: 0, mck2ui 16
2556 12:43:04.727506 best dqsien dly found for B0: ( 1, 3, 28)
2557 12:43:04.734330 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 12:43:04.734404 Total UI for P1: 0, mck2ui 16
2559 12:43:04.741036 best dqsien dly found for B1: ( 1, 4, 0)
2560 12:43:04.743942 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2561 12:43:04.747425 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2562 12:43:04.747502
2563 12:43:04.750883 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2564 12:43:04.754384 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2565 12:43:04.757260 [Gating] SW calibration Done
2566 12:43:04.757365 ==
2567 12:43:04.760578 Dram Type= 6, Freq= 0, CH_0, rank 0
2568 12:43:04.764120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2569 12:43:04.764225 ==
2570 12:43:04.767573 RX Vref Scan: 0
2571 12:43:04.767641
2572 12:43:04.767699 RX Vref 0 -> 0, step: 1
2573 12:43:04.767764
2574 12:43:04.771039 RX Delay -40 -> 252, step: 8
2575 12:43:04.774339 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2576 12:43:04.777785 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2577 12:43:04.784489 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2578 12:43:04.787266 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2579 12:43:04.790717 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2580 12:43:04.794165 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2581 12:43:04.797469 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2582 12:43:04.804430 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2583 12:43:04.807693 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2584 12:43:04.810822 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2585 12:43:04.814373 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2586 12:43:04.817425 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2587 12:43:04.824283 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2588 12:43:04.827307 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2589 12:43:04.830958 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2590 12:43:04.834039 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2591 12:43:04.834117 ==
2592 12:43:04.837856 Dram Type= 6, Freq= 0, CH_0, rank 0
2593 12:43:04.844276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2594 12:43:04.844385 ==
2595 12:43:04.844447 DQS Delay:
2596 12:43:04.847519 DQS0 = 0, DQS1 = 0
2597 12:43:04.847648 DQM Delay:
2598 12:43:04.847795 DQM0 = 121, DQM1 = 113
2599 12:43:04.850906 DQ Delay:
2600 12:43:04.854379 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2601 12:43:04.857785 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2602 12:43:04.861248 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2603 12:43:04.864575 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2604 12:43:04.864662
2605 12:43:04.864726
2606 12:43:04.864784 ==
2607 12:43:04.867416 Dram Type= 6, Freq= 0, CH_0, rank 0
2608 12:43:04.870795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2609 12:43:04.870873 ==
2610 12:43:04.874277
2611 12:43:04.874376
2612 12:43:04.874473 TX Vref Scan disable
2613 12:43:04.877750 == TX Byte 0 ==
2614 12:43:04.881237 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2615 12:43:04.884641 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2616 12:43:04.887932 == TX Byte 1 ==
2617 12:43:04.890635 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2618 12:43:04.894205 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2619 12:43:04.894280 ==
2620 12:43:04.897600 Dram Type= 6, Freq= 0, CH_0, rank 0
2621 12:43:04.904418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2622 12:43:04.904501 ==
2623 12:43:04.915080 TX Vref=22, minBit 0, minWin=25, winSum=407
2624 12:43:04.918716 TX Vref=24, minBit 0, minWin=25, winSum=417
2625 12:43:04.922316 TX Vref=26, minBit 0, minWin=26, winSum=422
2626 12:43:04.925607 TX Vref=28, minBit 0, minWin=26, winSum=424
2627 12:43:04.928587 TX Vref=30, minBit 0, minWin=26, winSum=420
2628 12:43:04.932203 TX Vref=32, minBit 0, minWin=26, winSum=423
2629 12:43:04.938692 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 28
2630 12:43:04.938806
2631 12:43:04.942018 Final TX Range 1 Vref 28
2632 12:43:04.942090
2633 12:43:04.942161 ==
2634 12:43:04.945235 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 12:43:04.948852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 12:43:04.948923 ==
2637 12:43:04.948993
2638 12:43:04.949051
2639 12:43:04.951850 TX Vref Scan disable
2640 12:43:04.955423 == TX Byte 0 ==
2641 12:43:04.959092 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2642 12:43:04.962013 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2643 12:43:04.965413 == TX Byte 1 ==
2644 12:43:04.968546 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2645 12:43:04.972489 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2646 12:43:04.972564
2647 12:43:04.975246 [DATLAT]
2648 12:43:04.975317 Freq=1200, CH0 RK0
2649 12:43:04.975378
2650 12:43:04.978827 DATLAT Default: 0xd
2651 12:43:04.978902 0, 0xFFFF, sum = 0
2652 12:43:04.982183 1, 0xFFFF, sum = 0
2653 12:43:04.982257 2, 0xFFFF, sum = 0
2654 12:43:04.985750 3, 0xFFFF, sum = 0
2655 12:43:04.985825 4, 0xFFFF, sum = 0
2656 12:43:04.988620 5, 0xFFFF, sum = 0
2657 12:43:04.988696 6, 0xFFFF, sum = 0
2658 12:43:04.992194 7, 0xFFFF, sum = 0
2659 12:43:04.992333 8, 0xFFFF, sum = 0
2660 12:43:04.995498 9, 0xFFFF, sum = 0
2661 12:43:04.995574 10, 0xFFFF, sum = 0
2662 12:43:04.998797 11, 0xFFFF, sum = 0
2663 12:43:04.998883 12, 0x0, sum = 1
2664 12:43:05.002210 13, 0x0, sum = 2
2665 12:43:05.002287 14, 0x0, sum = 3
2666 12:43:05.005535 15, 0x0, sum = 4
2667 12:43:05.005615 best_step = 13
2668 12:43:05.005679
2669 12:43:05.005737 ==
2670 12:43:05.009061 Dram Type= 6, Freq= 0, CH_0, rank 0
2671 12:43:05.015968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2672 12:43:05.016068 ==
2673 12:43:05.016168 RX Vref Scan: 1
2674 12:43:05.016259
2675 12:43:05.018797 Set Vref Range= 32 -> 127
2676 12:43:05.018877
2677 12:43:05.022194 RX Vref 32 -> 127, step: 1
2678 12:43:05.022273
2679 12:43:05.025788 RX Delay -13 -> 252, step: 4
2680 12:43:05.025867
2681 12:43:05.025935 Set Vref, RX VrefLevel [Byte0]: 32
2682 12:43:05.029261 [Byte1]: 32
2683 12:43:05.033707
2684 12:43:05.033784 Set Vref, RX VrefLevel [Byte0]: 33
2685 12:43:05.036814 [Byte1]: 33
2686 12:43:05.041789
2687 12:43:05.041861 Set Vref, RX VrefLevel [Byte0]: 34
2688 12:43:05.044877 [Byte1]: 34
2689 12:43:05.049063
2690 12:43:05.049148 Set Vref, RX VrefLevel [Byte0]: 35
2691 12:43:05.052537 [Byte1]: 35
2692 12:43:05.057480
2693 12:43:05.057559 Set Vref, RX VrefLevel [Byte0]: 36
2694 12:43:05.061040 [Byte1]: 36
2695 12:43:05.065144
2696 12:43:05.065257 Set Vref, RX VrefLevel [Byte0]: 37
2697 12:43:05.068727 [Byte1]: 37
2698 12:43:05.072911
2699 12:43:05.072990 Set Vref, RX VrefLevel [Byte0]: 38
2700 12:43:05.076124 [Byte1]: 38
2701 12:43:05.080925
2702 12:43:05.081004 Set Vref, RX VrefLevel [Byte0]: 39
2703 12:43:05.084267 [Byte1]: 39
2704 12:43:05.089027
2705 12:43:05.089107 Set Vref, RX VrefLevel [Byte0]: 40
2706 12:43:05.092009 [Byte1]: 40
2707 12:43:05.096835
2708 12:43:05.096931 Set Vref, RX VrefLevel [Byte0]: 41
2709 12:43:05.099946 [Byte1]: 41
2710 12:43:05.104497
2711 12:43:05.104577 Set Vref, RX VrefLevel [Byte0]: 42
2712 12:43:05.107761 [Byte1]: 42
2713 12:43:05.112228
2714 12:43:05.112363 Set Vref, RX VrefLevel [Byte0]: 43
2715 12:43:05.115668 [Byte1]: 43
2716 12:43:05.120505
2717 12:43:05.123952 Set Vref, RX VrefLevel [Byte0]: 44
2718 12:43:05.124026 [Byte1]: 44
2719 12:43:05.128086
2720 12:43:05.128186 Set Vref, RX VrefLevel [Byte0]: 45
2721 12:43:05.131676 [Byte1]: 45
2722 12:43:05.135829
2723 12:43:05.135919 Set Vref, RX VrefLevel [Byte0]: 46
2724 12:43:05.139287 [Byte1]: 46
2725 12:43:05.144251
2726 12:43:05.144340 Set Vref, RX VrefLevel [Byte0]: 47
2727 12:43:05.147110 [Byte1]: 47
2728 12:43:05.151882
2729 12:43:05.151987 Set Vref, RX VrefLevel [Byte0]: 48
2730 12:43:05.155167 [Byte1]: 48
2731 12:43:05.159549
2732 12:43:05.159636 Set Vref, RX VrefLevel [Byte0]: 49
2733 12:43:05.163264 [Byte1]: 49
2734 12:43:05.167675
2735 12:43:05.167769 Set Vref, RX VrefLevel [Byte0]: 50
2736 12:43:05.171188 [Byte1]: 50
2737 12:43:05.175857
2738 12:43:05.175961 Set Vref, RX VrefLevel [Byte0]: 51
2739 12:43:05.179194 [Byte1]: 51
2740 12:43:05.183454
2741 12:43:05.183528 Set Vref, RX VrefLevel [Byte0]: 52
2742 12:43:05.186952 [Byte1]: 52
2743 12:43:05.191172
2744 12:43:05.191270 Set Vref, RX VrefLevel [Byte0]: 53
2745 12:43:05.194478 [Byte1]: 53
2746 12:43:05.198929
2747 12:43:05.199021 Set Vref, RX VrefLevel [Byte0]: 54
2748 12:43:05.202868 [Byte1]: 54
2749 12:43:05.206916
2750 12:43:05.206996 Set Vref, RX VrefLevel [Byte0]: 55
2751 12:43:05.210847 [Byte1]: 55
2752 12:43:05.215065
2753 12:43:05.215174 Set Vref, RX VrefLevel [Byte0]: 56
2754 12:43:05.218161 [Byte1]: 56
2755 12:43:05.223008
2756 12:43:05.223087 Set Vref, RX VrefLevel [Byte0]: 57
2757 12:43:05.225969 [Byte1]: 57
2758 12:43:05.231100
2759 12:43:05.231182 Set Vref, RX VrefLevel [Byte0]: 58
2760 12:43:05.233881 [Byte1]: 58
2761 12:43:05.238838
2762 12:43:05.238943 Set Vref, RX VrefLevel [Byte0]: 59
2763 12:43:05.241631 [Byte1]: 59
2764 12:43:05.246532
2765 12:43:05.246611 Set Vref, RX VrefLevel [Byte0]: 60
2766 12:43:05.249984 [Byte1]: 60
2767 12:43:05.254193
2768 12:43:05.254297 Set Vref, RX VrefLevel [Byte0]: 61
2769 12:43:05.257800 [Byte1]: 61
2770 12:43:05.262704
2771 12:43:05.262783 Set Vref, RX VrefLevel [Byte0]: 62
2772 12:43:05.265522 [Byte1]: 62
2773 12:43:05.270250
2774 12:43:05.270360 Set Vref, RX VrefLevel [Byte0]: 63
2775 12:43:05.273805 [Byte1]: 63
2776 12:43:05.278418
2777 12:43:05.278499 Set Vref, RX VrefLevel [Byte0]: 64
2778 12:43:05.281772 [Byte1]: 64
2779 12:43:05.286331
2780 12:43:05.286410 Set Vref, RX VrefLevel [Byte0]: 65
2781 12:43:05.289357 [Byte1]: 65
2782 12:43:05.293700
2783 12:43:05.293784 Set Vref, RX VrefLevel [Byte0]: 66
2784 12:43:05.296980 [Byte1]: 66
2785 12:43:05.301773
2786 12:43:05.301852 Set Vref, RX VrefLevel [Byte0]: 67
2787 12:43:05.305137 [Byte1]: 67
2788 12:43:05.309972
2789 12:43:05.310052 Set Vref, RX VrefLevel [Byte0]: 68
2790 12:43:05.312797 [Byte1]: 68
2791 12:43:05.317654
2792 12:43:05.317734 Set Vref, RX VrefLevel [Byte0]: 69
2793 12:43:05.321213 [Byte1]: 69
2794 12:43:05.325323
2795 12:43:05.325403 Final RX Vref Byte 0 = 56 to rank0
2796 12:43:05.328646 Final RX Vref Byte 1 = 49 to rank0
2797 12:43:05.332036 Final RX Vref Byte 0 = 56 to rank1
2798 12:43:05.335744 Final RX Vref Byte 1 = 49 to rank1==
2799 12:43:05.338671 Dram Type= 6, Freq= 0, CH_0, rank 0
2800 12:43:05.345318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2801 12:43:05.345401 ==
2802 12:43:05.345465 DQS Delay:
2803 12:43:05.345523 DQS0 = 0, DQS1 = 0
2804 12:43:05.349068 DQM Delay:
2805 12:43:05.349148 DQM0 = 120, DQM1 = 112
2806 12:43:05.352634 DQ Delay:
2807 12:43:05.355399 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2808 12:43:05.358938 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2809 12:43:05.362509 DQ8 =100, DQ9 =100, DQ10 =114, DQ11 =106
2810 12:43:05.365998 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =122
2811 12:43:05.366078
2812 12:43:05.366140
2813 12:43:05.372209 [DQSOSCAuto] RK0, (LSB)MR18= 0x1811, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 400 ps
2814 12:43:05.375464 CH0 RK0: MR19=404, MR18=1811
2815 12:43:05.382089 CH0_RK0: MR19=0x404, MR18=0x1811, DQSOSC=400, MR23=63, INC=40, DEC=27
2816 12:43:05.382169
2817 12:43:05.385606 ----->DramcWriteLeveling(PI) begin...
2818 12:43:05.385683 ==
2819 12:43:05.389222 Dram Type= 6, Freq= 0, CH_0, rank 1
2820 12:43:05.392513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2821 12:43:05.392593 ==
2822 12:43:05.395684 Write leveling (Byte 0): 34 => 34
2823 12:43:05.398873 Write leveling (Byte 1): 27 => 27
2824 12:43:05.402320 DramcWriteLeveling(PI) end<-----
2825 12:43:05.402400
2826 12:43:05.402476 ==
2827 12:43:05.406157 Dram Type= 6, Freq= 0, CH_0, rank 1
2828 12:43:05.409244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2829 12:43:05.412740 ==
2830 12:43:05.412845 [Gating] SW mode calibration
2831 12:43:05.422640 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2832 12:43:05.426026 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2833 12:43:05.429429 0 15 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2834 12:43:05.435859 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2835 12:43:05.439129 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2836 12:43:05.442697 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2837 12:43:05.449814 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2838 12:43:05.452938 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 12:43:05.456082 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 12:43:05.462754 0 15 28 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (0 0)
2841 12:43:05.466417 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2842 12:43:05.469837 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2843 12:43:05.472629 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2844 12:43:05.479677 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 12:43:05.482885 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 12:43:05.486293 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 12:43:05.493359 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2848 12:43:05.496202 1 0 28 | B1->B0 | 3e3e 3f3f | 0 0 | (0 0) (0 0)
2849 12:43:05.499680 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2850 12:43:05.506121 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2851 12:43:05.509764 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 12:43:05.513448 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 12:43:05.519927 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 12:43:05.523370 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 12:43:05.526666 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2856 12:43:05.529888 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2857 12:43:05.536587 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2858 12:43:05.539917 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 12:43:05.543093 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 12:43:05.549931 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 12:43:05.553343 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 12:43:05.556691 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 12:43:05.563491 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 12:43:05.566910 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 12:43:05.570192 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 12:43:05.576593 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 12:43:05.580121 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 12:43:05.583223 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 12:43:05.589805 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 12:43:05.593107 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 12:43:05.596559 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 12:43:05.603593 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2873 12:43:05.606448 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2874 12:43:05.609971 Total UI for P1: 0, mck2ui 16
2875 12:43:05.613363 best dqsien dly found for B1: ( 1, 3, 28)
2876 12:43:05.616852 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 12:43:05.620230 Total UI for P1: 0, mck2ui 16
2878 12:43:05.623077 best dqsien dly found for B0: ( 1, 3, 30)
2879 12:43:05.626623 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2880 12:43:05.630000 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2881 12:43:05.630089
2882 12:43:05.633522 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2883 12:43:05.636951 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2884 12:43:05.639759 [Gating] SW calibration Done
2885 12:43:05.639838 ==
2886 12:43:05.643274 Dram Type= 6, Freq= 0, CH_0, rank 1
2887 12:43:05.650054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2888 12:43:05.650134 ==
2889 12:43:05.650203 RX Vref Scan: 0
2890 12:43:05.650297
2891 12:43:05.653408 RX Vref 0 -> 0, step: 1
2892 12:43:05.653487
2893 12:43:05.656574 RX Delay -40 -> 252, step: 8
2894 12:43:05.660116 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2895 12:43:05.663700 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2896 12:43:05.667051 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2897 12:43:05.670147 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2898 12:43:05.677029 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2899 12:43:05.680369 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2900 12:43:05.683650 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2901 12:43:05.686960 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2902 12:43:05.690113 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2903 12:43:05.693837 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2904 12:43:05.699987 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2905 12:43:05.703736 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2906 12:43:05.706937 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2907 12:43:05.710186 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2908 12:43:05.717027 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2909 12:43:05.720709 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2910 12:43:05.720790 ==
2911 12:43:05.723375 Dram Type= 6, Freq= 0, CH_0, rank 1
2912 12:43:05.726835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2913 12:43:05.726908 ==
2914 12:43:05.726969 DQS Delay:
2915 12:43:05.730188 DQS0 = 0, DQS1 = 0
2916 12:43:05.730258 DQM Delay:
2917 12:43:05.733770 DQM0 = 122, DQM1 = 112
2918 12:43:05.733849 DQ Delay:
2919 12:43:05.737222 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2920 12:43:05.739963 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2921 12:43:05.743364 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2922 12:43:05.750469 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2923 12:43:05.750570
2924 12:43:05.750666
2925 12:43:05.750753 ==
2926 12:43:05.753249 Dram Type= 6, Freq= 0, CH_0, rank 1
2927 12:43:05.756797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2928 12:43:05.756869 ==
2929 12:43:05.756929
2930 12:43:05.756985
2931 12:43:05.760168 TX Vref Scan disable
2932 12:43:05.760292 == TX Byte 0 ==
2933 12:43:05.767018 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2934 12:43:05.770603 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2935 12:43:05.770703 == TX Byte 1 ==
2936 12:43:05.777334 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2937 12:43:05.780585 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2938 12:43:05.780658 ==
2939 12:43:05.783809 Dram Type= 6, Freq= 0, CH_0, rank 1
2940 12:43:05.786895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2941 12:43:05.786975 ==
2942 12:43:05.799681 TX Vref=22, minBit 1, minWin=25, winSum=412
2943 12:43:05.803331 TX Vref=24, minBit 3, minWin=25, winSum=419
2944 12:43:05.806900 TX Vref=26, minBit 0, minWin=26, winSum=425
2945 12:43:05.809792 TX Vref=28, minBit 2, minWin=26, winSum=425
2946 12:43:05.813194 TX Vref=30, minBit 5, minWin=25, winSum=426
2947 12:43:05.816914 TX Vref=32, minBit 5, minWin=25, winSum=424
2948 12:43:05.823180 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 26
2949 12:43:05.823287
2950 12:43:05.826775 Final TX Range 1 Vref 26
2951 12:43:05.826850
2952 12:43:05.826919 ==
2953 12:43:05.829739 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 12:43:05.833483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 12:43:05.833558 ==
2956 12:43:05.833623
2957 12:43:05.836994
2958 12:43:05.837067 TX Vref Scan disable
2959 12:43:05.840091 == TX Byte 0 ==
2960 12:43:05.843447 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2961 12:43:05.846885 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2962 12:43:05.850266 == TX Byte 1 ==
2963 12:43:05.853093 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2964 12:43:05.856400 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2965 12:43:05.856502
2966 12:43:05.860066 [DATLAT]
2967 12:43:05.860180 Freq=1200, CH0 RK1
2968 12:43:05.860298
2969 12:43:05.863419 DATLAT Default: 0xd
2970 12:43:05.863517 0, 0xFFFF, sum = 0
2971 12:43:05.867025 1, 0xFFFF, sum = 0
2972 12:43:05.867113 2, 0xFFFF, sum = 0
2973 12:43:05.869884 3, 0xFFFF, sum = 0
2974 12:43:05.869966 4, 0xFFFF, sum = 0
2975 12:43:05.873334 5, 0xFFFF, sum = 0
2976 12:43:05.873434 6, 0xFFFF, sum = 0
2977 12:43:05.876793 7, 0xFFFF, sum = 0
2978 12:43:05.876869 8, 0xFFFF, sum = 0
2979 12:43:05.880144 9, 0xFFFF, sum = 0
2980 12:43:05.883727 10, 0xFFFF, sum = 0
2981 12:43:05.883805 11, 0xFFFF, sum = 0
2982 12:43:05.887160 12, 0x0, sum = 1
2983 12:43:05.887249 13, 0x0, sum = 2
2984 12:43:05.887316 14, 0x0, sum = 3
2985 12:43:05.890403 15, 0x0, sum = 4
2986 12:43:05.890485 best_step = 13
2987 12:43:05.890549
2988 12:43:05.890608 ==
2989 12:43:05.893264 Dram Type= 6, Freq= 0, CH_0, rank 1
2990 12:43:05.900067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2991 12:43:05.900148 ==
2992 12:43:05.900212 RX Vref Scan: 0
2993 12:43:05.900272
2994 12:43:05.903472 RX Vref 0 -> 0, step: 1
2995 12:43:05.903552
2996 12:43:05.906696 RX Delay -13 -> 252, step: 4
2997 12:43:05.910199 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
2998 12:43:05.913758 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
2999 12:43:05.919951 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3000 12:43:05.923334 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3001 12:43:05.926749 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3002 12:43:05.930226 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3003 12:43:05.933411 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3004 12:43:05.940144 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3005 12:43:05.943559 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3006 12:43:05.946867 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3007 12:43:05.949868 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3008 12:43:05.953426 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3009 12:43:05.960217 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3010 12:43:05.963665 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3011 12:43:05.966754 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3012 12:43:05.970319 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3013 12:43:05.970401 ==
3014 12:43:05.973410 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 12:43:05.977187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 12:43:05.980184 ==
3017 12:43:05.980265 DQS Delay:
3018 12:43:05.980374 DQS0 = 0, DQS1 = 0
3019 12:43:05.983592 DQM Delay:
3020 12:43:05.983673 DQM0 = 121, DQM1 = 110
3021 12:43:05.986944 DQ Delay:
3022 12:43:05.990366 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3023 12:43:05.993777 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3024 12:43:05.997206 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3025 12:43:05.999999 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3026 12:43:06.000079
3027 12:43:06.000143
3028 12:43:06.006801 [DQSOSCAuto] RK1, (LSB)MR18= 0xced, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3029 12:43:06.010110 CH0 RK1: MR19=403, MR18=CED
3030 12:43:06.016996 CH0_RK1: MR19=0x403, MR18=0xCED, DQSOSC=405, MR23=63, INC=39, DEC=26
3031 12:43:06.020433 [RxdqsGatingPostProcess] freq 1200
3032 12:43:06.026703 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3033 12:43:06.026781 best DQS0 dly(2T, 0.5T) = (0, 11)
3034 12:43:06.030204 best DQS1 dly(2T, 0.5T) = (0, 12)
3035 12:43:06.033673 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3036 12:43:06.037139 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3037 12:43:06.040589 best DQS0 dly(2T, 0.5T) = (0, 11)
3038 12:43:06.043350 best DQS1 dly(2T, 0.5T) = (0, 11)
3039 12:43:06.046870 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3040 12:43:06.050337 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3041 12:43:06.053792 Pre-setting of DQS Precalculation
3042 12:43:06.056645 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3043 12:43:06.060036 ==
3044 12:43:06.060111 Dram Type= 6, Freq= 0, CH_1, rank 0
3045 12:43:06.067021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3046 12:43:06.067134 ==
3047 12:43:06.070114 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3048 12:43:06.077256 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3049 12:43:06.085725 [CA 0] Center 37 (7~68) winsize 62
3050 12:43:06.089651 [CA 1] Center 37 (7~68) winsize 62
3051 12:43:06.092589 [CA 2] Center 35 (5~65) winsize 61
3052 12:43:06.095756 [CA 3] Center 34 (4~64) winsize 61
3053 12:43:06.099165 [CA 4] Center 34 (4~64) winsize 61
3054 12:43:06.102768 [CA 5] Center 33 (3~63) winsize 61
3055 12:43:06.102846
3056 12:43:06.106199 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3057 12:43:06.106307
3058 12:43:06.109576 [CATrainingPosCal] consider 1 rank data
3059 12:43:06.112957 u2DelayCellTimex100 = 270/100 ps
3060 12:43:06.116229 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3061 12:43:06.119397 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3062 12:43:06.123111 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3063 12:43:06.129485 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3064 12:43:06.133075 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3065 12:43:06.136497 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3066 12:43:06.136574
3067 12:43:06.140050 CA PerBit enable=1, Macro0, CA PI delay=33
3068 12:43:06.140136
3069 12:43:06.142835 [CBTSetCACLKResult] CA Dly = 33
3070 12:43:06.142907 CS Dly: 7 (0~38)
3071 12:43:06.142968 ==
3072 12:43:06.146456 Dram Type= 6, Freq= 0, CH_1, rank 1
3073 12:43:06.152739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 12:43:06.152821 ==
3075 12:43:06.156210 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3076 12:43:06.163077 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3077 12:43:06.171505 [CA 0] Center 37 (7~68) winsize 62
3078 12:43:06.174892 [CA 1] Center 37 (7~68) winsize 62
3079 12:43:06.178358 [CA 2] Center 35 (5~65) winsize 61
3080 12:43:06.181851 [CA 3] Center 34 (4~65) winsize 62
3081 12:43:06.185137 [CA 4] Center 34 (4~65) winsize 62
3082 12:43:06.188270 [CA 5] Center 34 (4~64) winsize 61
3083 12:43:06.188389
3084 12:43:06.191753 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3085 12:43:06.191839
3086 12:43:06.195145 [CATrainingPosCal] consider 2 rank data
3087 12:43:06.198551 u2DelayCellTimex100 = 270/100 ps
3088 12:43:06.201847 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3089 12:43:06.204706 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3090 12:43:06.211252 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3091 12:43:06.215094 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3092 12:43:06.218049 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3093 12:43:06.221219 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3094 12:43:06.221294
3095 12:43:06.224606 CA PerBit enable=1, Macro0, CA PI delay=33
3096 12:43:06.224707
3097 12:43:06.228656 [CBTSetCACLKResult] CA Dly = 33
3098 12:43:06.228738 CS Dly: 8 (0~41)
3099 12:43:06.228801
3100 12:43:06.231536 ----->DramcWriteLeveling(PI) begin...
3101 12:43:06.235110 ==
3102 12:43:06.238505 Dram Type= 6, Freq= 0, CH_1, rank 0
3103 12:43:06.241593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3104 12:43:06.241694 ==
3105 12:43:06.244711 Write leveling (Byte 0): 27 => 27
3106 12:43:06.248229 Write leveling (Byte 1): 28 => 28
3107 12:43:06.251783 DramcWriteLeveling(PI) end<-----
3108 12:43:06.251862
3109 12:43:06.251924 ==
3110 12:43:06.254966 Dram Type= 6, Freq= 0, CH_1, rank 0
3111 12:43:06.258252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3112 12:43:06.258332 ==
3113 12:43:06.261793 [Gating] SW mode calibration
3114 12:43:06.268053 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3115 12:43:06.271496 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3116 12:43:06.278517 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3117 12:43:06.281345 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3118 12:43:06.284799 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 12:43:06.292023 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 12:43:06.294849 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 12:43:06.298259 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 12:43:06.305014 0 15 24 | B1->B0 | 3232 2e2e | 0 0 | (0 0) (0 0)
3123 12:43:06.308429 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3124 12:43:06.311868 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 12:43:06.318691 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 12:43:06.322119 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 12:43:06.324842 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 12:43:06.332141 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 12:43:06.334816 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3130 12:43:06.338335 1 0 24 | B1->B0 | 3434 3d3d | 0 0 | (0 0) (0 0)
3131 12:43:06.341739 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3132 12:43:06.348904 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 12:43:06.352122 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 12:43:06.355348 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 12:43:06.362002 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 12:43:06.365075 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 12:43:06.368667 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 12:43:06.375647 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3139 12:43:06.378575 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3140 12:43:06.381889 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 12:43:06.388793 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 12:43:06.392061 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 12:43:06.395393 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 12:43:06.402158 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 12:43:06.405522 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 12:43:06.408933 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 12:43:06.412206 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 12:43:06.418588 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 12:43:06.422000 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 12:43:06.425998 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 12:43:06.432135 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 12:43:06.435402 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 12:43:06.438880 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 12:43:06.445723 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3155 12:43:06.449271 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 12:43:06.452601 Total UI for P1: 0, mck2ui 16
3157 12:43:06.455445 best dqsien dly found for B0: ( 1, 3, 24)
3158 12:43:06.458815 Total UI for P1: 0, mck2ui 16
3159 12:43:06.462192 best dqsien dly found for B1: ( 1, 3, 24)
3160 12:43:06.465734 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3161 12:43:06.469343 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3162 12:43:06.469423
3163 12:43:06.472151 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3164 12:43:06.475439 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3165 12:43:06.478876 [Gating] SW calibration Done
3166 12:43:06.478958 ==
3167 12:43:06.482074 Dram Type= 6, Freq= 0, CH_1, rank 0
3168 12:43:06.485737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3169 12:43:06.485810 ==
3170 12:43:06.488841 RX Vref Scan: 0
3171 12:43:06.488912
3172 12:43:06.492524 RX Vref 0 -> 0, step: 1
3173 12:43:06.492596
3174 12:43:06.492656 RX Delay -40 -> 252, step: 8
3175 12:43:06.499195 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3176 12:43:06.502147 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3177 12:43:06.505341 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3178 12:43:06.509095 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3179 12:43:06.512416 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3180 12:43:06.519180 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3181 12:43:06.522533 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3182 12:43:06.525955 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3183 12:43:06.529283 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3184 12:43:06.532826 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3185 12:43:06.539109 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3186 12:43:06.542458 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3187 12:43:06.545901 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3188 12:43:06.549325 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3189 12:43:06.552768 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3190 12:43:06.559102 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3191 12:43:06.559175 ==
3192 12:43:06.562552 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 12:43:06.565879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 12:43:06.565954 ==
3195 12:43:06.566015 DQS Delay:
3196 12:43:06.569527 DQS0 = 0, DQS1 = 0
3197 12:43:06.569608 DQM Delay:
3198 12:43:06.572979 DQM0 = 120, DQM1 = 116
3199 12:43:06.573061 DQ Delay:
3200 12:43:06.575765 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3201 12:43:06.579242 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =119
3202 12:43:06.582474 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3203 12:43:06.585753 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3204 12:43:06.585843
3205 12:43:06.585906
3206 12:43:06.589227 ==
3207 12:43:06.589299 Dram Type= 6, Freq= 0, CH_1, rank 0
3208 12:43:06.596206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3209 12:43:06.596333 ==
3210 12:43:06.596397
3211 12:43:06.596455
3212 12:43:06.599527 TX Vref Scan disable
3213 12:43:06.599601 == TX Byte 0 ==
3214 12:43:06.602698 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3215 12:43:06.609170 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3216 12:43:06.609251 == TX Byte 1 ==
3217 12:43:06.612546 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3218 12:43:06.618960 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3219 12:43:06.619040 ==
3220 12:43:06.622378 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 12:43:06.626094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 12:43:06.626174 ==
3223 12:43:06.637303 TX Vref=22, minBit 9, minWin=24, winSum=410
3224 12:43:06.641047 TX Vref=24, minBit 9, minWin=25, winSum=417
3225 12:43:06.643987 TX Vref=26, minBit 9, minWin=25, winSum=422
3226 12:43:06.647827 TX Vref=28, minBit 1, minWin=26, winSum=429
3227 12:43:06.650582 TX Vref=30, minBit 2, minWin=26, winSum=431
3228 12:43:06.654135 TX Vref=32, minBit 9, minWin=26, winSum=431
3229 12:43:06.660483 [TxChooseVref] Worse bit 2, Min win 26, Win sum 431, Final Vref 30
3230 12:43:06.660563
3231 12:43:06.663948 Final TX Range 1 Vref 30
3232 12:43:06.664028
3233 12:43:06.664089 ==
3234 12:43:06.667329 Dram Type= 6, Freq= 0, CH_1, rank 0
3235 12:43:06.670751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3236 12:43:06.670832 ==
3237 12:43:06.670895
3238 12:43:06.674238
3239 12:43:06.674343 TX Vref Scan disable
3240 12:43:06.677794 == TX Byte 0 ==
3241 12:43:06.680633 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3242 12:43:06.684082 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3243 12:43:06.687613 == TX Byte 1 ==
3244 12:43:06.690764 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3245 12:43:06.694220 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3246 12:43:06.694300
3247 12:43:06.697724 [DATLAT]
3248 12:43:06.697803 Freq=1200, CH1 RK0
3249 12:43:06.697866
3250 12:43:06.701250 DATLAT Default: 0xd
3251 12:43:06.701329 0, 0xFFFF, sum = 0
3252 12:43:06.703948 1, 0xFFFF, sum = 0
3253 12:43:06.704030 2, 0xFFFF, sum = 0
3254 12:43:06.707443 3, 0xFFFF, sum = 0
3255 12:43:06.707524 4, 0xFFFF, sum = 0
3256 12:43:06.710823 5, 0xFFFF, sum = 0
3257 12:43:06.710905 6, 0xFFFF, sum = 0
3258 12:43:06.714073 7, 0xFFFF, sum = 0
3259 12:43:06.714153 8, 0xFFFF, sum = 0
3260 12:43:06.717475 9, 0xFFFF, sum = 0
3261 12:43:06.717556 10, 0xFFFF, sum = 0
3262 12:43:06.720867 11, 0xFFFF, sum = 0
3263 12:43:06.720951 12, 0x0, sum = 1
3264 12:43:06.724310 13, 0x0, sum = 2
3265 12:43:06.724404 14, 0x0, sum = 3
3266 12:43:06.727796 15, 0x0, sum = 4
3267 12:43:06.727876 best_step = 13
3268 12:43:06.727944
3269 12:43:06.728001 ==
3270 12:43:06.731142 Dram Type= 6, Freq= 0, CH_1, rank 0
3271 12:43:06.737643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3272 12:43:06.737723 ==
3273 12:43:06.737785 RX Vref Scan: 1
3274 12:43:06.737843
3275 12:43:06.740838 Set Vref Range= 32 -> 127
3276 12:43:06.740917
3277 12:43:06.744480 RX Vref 32 -> 127, step: 1
3278 12:43:06.744559
3279 12:43:06.744621 RX Delay -5 -> 252, step: 4
3280 12:43:06.747950
3281 12:43:06.748059 Set Vref, RX VrefLevel [Byte0]: 32
3282 12:43:06.751148 [Byte1]: 32
3283 12:43:06.755356
3284 12:43:06.755435 Set Vref, RX VrefLevel [Byte0]: 33
3285 12:43:06.759293 [Byte1]: 33
3286 12:43:06.763346
3287 12:43:06.763426 Set Vref, RX VrefLevel [Byte0]: 34
3288 12:43:06.766794 [Byte1]: 34
3289 12:43:06.771389
3290 12:43:06.771479 Set Vref, RX VrefLevel [Byte0]: 35
3291 12:43:06.774276 [Byte1]: 35
3292 12:43:06.779288
3293 12:43:06.779405 Set Vref, RX VrefLevel [Byte0]: 36
3294 12:43:06.782040 [Byte1]: 36
3295 12:43:06.786846
3296 12:43:06.786924 Set Vref, RX VrefLevel [Byte0]: 37
3297 12:43:06.790375 [Byte1]: 37
3298 12:43:06.794429
3299 12:43:06.794516 Set Vref, RX VrefLevel [Byte0]: 38
3300 12:43:06.797743 [Byte1]: 38
3301 12:43:06.802567
3302 12:43:06.802677 Set Vref, RX VrefLevel [Byte0]: 39
3303 12:43:06.806120 [Byte1]: 39
3304 12:43:06.810304
3305 12:43:06.810374 Set Vref, RX VrefLevel [Byte0]: 40
3306 12:43:06.813861 [Byte1]: 40
3307 12:43:06.818533
3308 12:43:06.818616 Set Vref, RX VrefLevel [Byte0]: 41
3309 12:43:06.821712 [Byte1]: 41
3310 12:43:06.826430
3311 12:43:06.826513 Set Vref, RX VrefLevel [Byte0]: 42
3312 12:43:06.829248 [Byte1]: 42
3313 12:43:06.834170
3314 12:43:06.834276 Set Vref, RX VrefLevel [Byte0]: 43
3315 12:43:06.837154 [Byte1]: 43
3316 12:43:06.841659
3317 12:43:06.841740 Set Vref, RX VrefLevel [Byte0]: 44
3318 12:43:06.844984 [Byte1]: 44
3319 12:43:06.849762
3320 12:43:06.849837 Set Vref, RX VrefLevel [Byte0]: 45
3321 12:43:06.852967 [Byte1]: 45
3322 12:43:06.857843
3323 12:43:06.857917 Set Vref, RX VrefLevel [Byte0]: 46
3324 12:43:06.860606 [Byte1]: 46
3325 12:43:06.865183
3326 12:43:06.865259 Set Vref, RX VrefLevel [Byte0]: 47
3327 12:43:06.868683 [Byte1]: 47
3328 12:43:06.873348
3329 12:43:06.873445 Set Vref, RX VrefLevel [Byte0]: 48
3330 12:43:06.876641 [Byte1]: 48
3331 12:43:06.881267
3332 12:43:06.881348 Set Vref, RX VrefLevel [Byte0]: 49
3333 12:43:06.884500 [Byte1]: 49
3334 12:43:06.888901
3335 12:43:06.888992 Set Vref, RX VrefLevel [Byte0]: 50
3336 12:43:06.892085 [Byte1]: 50
3337 12:43:06.897058
3338 12:43:06.897136 Set Vref, RX VrefLevel [Byte0]: 51
3339 12:43:06.900174 [Byte1]: 51
3340 12:43:06.904778
3341 12:43:06.904857 Set Vref, RX VrefLevel [Byte0]: 52
3342 12:43:06.908197 [Byte1]: 52
3343 12:43:06.912452
3344 12:43:06.912531 Set Vref, RX VrefLevel [Byte0]: 53
3345 12:43:06.915860 [Byte1]: 53
3346 12:43:06.920651
3347 12:43:06.920729 Set Vref, RX VrefLevel [Byte0]: 54
3348 12:43:06.923404 [Byte1]: 54
3349 12:43:06.928044
3350 12:43:06.928123 Set Vref, RX VrefLevel [Byte0]: 55
3351 12:43:06.931360 [Byte1]: 55
3352 12:43:06.935786
3353 12:43:06.935864 Set Vref, RX VrefLevel [Byte0]: 56
3354 12:43:06.939399 [Byte1]: 56
3355 12:43:06.943704
3356 12:43:06.943820 Set Vref, RX VrefLevel [Byte0]: 57
3357 12:43:06.947037 [Byte1]: 57
3358 12:43:06.951487
3359 12:43:06.951565 Set Vref, RX VrefLevel [Byte0]: 58
3360 12:43:06.954958 [Byte1]: 58
3361 12:43:06.959547
3362 12:43:06.959625 Set Vref, RX VrefLevel [Byte0]: 59
3363 12:43:06.962999 [Byte1]: 59
3364 12:43:06.967153
3365 12:43:06.967257 Set Vref, RX VrefLevel [Byte0]: 60
3366 12:43:06.970451 [Byte1]: 60
3367 12:43:06.975346
3368 12:43:06.975425 Set Vref, RX VrefLevel [Byte0]: 61
3369 12:43:06.978755 [Byte1]: 61
3370 12:43:06.983305
3371 12:43:06.983386 Set Vref, RX VrefLevel [Byte0]: 62
3372 12:43:06.986791 [Byte1]: 62
3373 12:43:06.990993
3374 12:43:06.991072 Set Vref, RX VrefLevel [Byte0]: 63
3375 12:43:06.994248 [Byte1]: 63
3376 12:43:06.998487
3377 12:43:06.998565 Set Vref, RX VrefLevel [Byte0]: 64
3378 12:43:07.001847 [Byte1]: 64
3379 12:43:07.006495
3380 12:43:07.006585 Set Vref, RX VrefLevel [Byte0]: 65
3381 12:43:07.009832 [Byte1]: 65
3382 12:43:07.014506
3383 12:43:07.014591 Set Vref, RX VrefLevel [Byte0]: 66
3384 12:43:07.017676 [Byte1]: 66
3385 12:43:07.022574
3386 12:43:07.022664 Set Vref, RX VrefLevel [Byte0]: 67
3387 12:43:07.025332 [Byte1]: 67
3388 12:43:07.030323
3389 12:43:07.030403 Set Vref, RX VrefLevel [Byte0]: 68
3390 12:43:07.033789 [Byte1]: 68
3391 12:43:07.038427
3392 12:43:07.038507 Set Vref, RX VrefLevel [Byte0]: 69
3393 12:43:07.041033 [Byte1]: 69
3394 12:43:07.045859
3395 12:43:07.045936 Set Vref, RX VrefLevel [Byte0]: 70
3396 12:43:07.049347 [Byte1]: 70
3397 12:43:07.053612
3398 12:43:07.053686 Final RX Vref Byte 0 = 53 to rank0
3399 12:43:07.056769 Final RX Vref Byte 1 = 54 to rank0
3400 12:43:07.060110 Final RX Vref Byte 0 = 53 to rank1
3401 12:43:07.063627 Final RX Vref Byte 1 = 54 to rank1==
3402 12:43:07.067235 Dram Type= 6, Freq= 0, CH_1, rank 0
3403 12:43:07.070415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3404 12:43:07.073863 ==
3405 12:43:07.073941 DQS Delay:
3406 12:43:07.074003 DQS0 = 0, DQS1 = 0
3407 12:43:07.077117 DQM Delay:
3408 12:43:07.077192 DQM0 = 119, DQM1 = 117
3409 12:43:07.080620 DQ Delay:
3410 12:43:07.083857 DQ0 =122, DQ1 =114, DQ2 =110, DQ3 =116
3411 12:43:07.087359 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120
3412 12:43:07.090300 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3413 12:43:07.093780 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3414 12:43:07.093853
3415 12:43:07.093923
3416 12:43:07.100598 [DQSOSCAuto] RK0, (LSB)MR18= 0x13, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 410 ps
3417 12:43:07.104128 CH1 RK0: MR19=404, MR18=13
3418 12:43:07.110889 CH1_RK0: MR19=0x404, MR18=0x13, DQSOSC=402, MR23=63, INC=40, DEC=27
3419 12:43:07.110975
3420 12:43:07.114303 ----->DramcWriteLeveling(PI) begin...
3421 12:43:07.114385 ==
3422 12:43:07.117135 Dram Type= 6, Freq= 0, CH_1, rank 1
3423 12:43:07.120587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3424 12:43:07.120700 ==
3425 12:43:07.124078 Write leveling (Byte 0): 26 => 26
3426 12:43:07.127426 Write leveling (Byte 1): 29 => 29
3427 12:43:07.131239 DramcWriteLeveling(PI) end<-----
3428 12:43:07.131316
3429 12:43:07.131377 ==
3430 12:43:07.134582 Dram Type= 6, Freq= 0, CH_1, rank 1
3431 12:43:07.137627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3432 12:43:07.137697 ==
3433 12:43:07.140751 [Gating] SW mode calibration
3434 12:43:07.147404 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3435 12:43:07.154670 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3436 12:43:07.157539 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3437 12:43:07.160857 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 12:43:07.167489 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 12:43:07.170814 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 12:43:07.174122 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 12:43:07.181167 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3442 12:43:07.184674 0 15 24 | B1->B0 | 2929 3434 | 0 1 | (1 0) (1 0)
3443 12:43:07.187780 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
3444 12:43:07.194506 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 12:43:07.197952 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 12:43:07.200839 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 12:43:07.208156 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 12:43:07.210769 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 12:43:07.214191 1 0 20 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3450 12:43:07.221095 1 0 24 | B1->B0 | 4444 3131 | 0 1 | (0 0) (0 0)
3451 12:43:07.224578 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 12:43:07.227348 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 12:43:07.234325 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 12:43:07.237746 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 12:43:07.240983 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 12:43:07.247485 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 12:43:07.251308 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3458 12:43:07.254338 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3459 12:43:07.260815 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3460 12:43:07.264033 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 12:43:07.267392 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 12:43:07.270705 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 12:43:07.277496 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 12:43:07.281005 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 12:43:07.283739 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 12:43:07.290622 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 12:43:07.294021 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 12:43:07.297342 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 12:43:07.304015 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 12:43:07.307588 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 12:43:07.310382 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 12:43:07.317683 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 12:43:07.320736 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3474 12:43:07.324109 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3475 12:43:07.330352 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3476 12:43:07.330429 Total UI for P1: 0, mck2ui 16
3477 12:43:07.337357 best dqsien dly found for B1: ( 1, 3, 22)
3478 12:43:07.340828 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 12:43:07.343588 Total UI for P1: 0, mck2ui 16
3480 12:43:07.347046 best dqsien dly found for B0: ( 1, 3, 26)
3481 12:43:07.350414 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3482 12:43:07.353886 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3483 12:43:07.353956
3484 12:43:07.357403 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3485 12:43:07.360905 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3486 12:43:07.363675 [Gating] SW calibration Done
3487 12:43:07.363752 ==
3488 12:43:07.366925 Dram Type= 6, Freq= 0, CH_1, rank 1
3489 12:43:07.370261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3490 12:43:07.374112 ==
3491 12:43:07.374223 RX Vref Scan: 0
3492 12:43:07.374321
3493 12:43:07.377256 RX Vref 0 -> 0, step: 1
3494 12:43:07.377338
3495 12:43:07.380167 RX Delay -40 -> 252, step: 8
3496 12:43:07.383710 iDelay=200, Bit 0, Center 127 (64 ~ 191) 128
3497 12:43:07.386909 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3498 12:43:07.390402 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3499 12:43:07.393727 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3500 12:43:07.400678 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3501 12:43:07.403752 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3502 12:43:07.407233 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3503 12:43:07.410264 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3504 12:43:07.413692 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3505 12:43:07.420732 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3506 12:43:07.423485 iDelay=200, Bit 10, Center 119 (48 ~ 191) 144
3507 12:43:07.426819 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3508 12:43:07.430105 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3509 12:43:07.433352 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3510 12:43:07.440136 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3511 12:43:07.443586 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3512 12:43:07.443662 ==
3513 12:43:07.447111 Dram Type= 6, Freq= 0, CH_1, rank 1
3514 12:43:07.450638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3515 12:43:07.450714 ==
3516 12:43:07.453420 DQS Delay:
3517 12:43:07.453499 DQS0 = 0, DQS1 = 0
3518 12:43:07.453564 DQM Delay:
3519 12:43:07.456883 DQM0 = 121, DQM1 = 118
3520 12:43:07.456962 DQ Delay:
3521 12:43:07.460269 DQ0 =127, DQ1 =119, DQ2 =107, DQ3 =119
3522 12:43:07.463899 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =119
3523 12:43:07.466742 DQ8 =103, DQ9 =107, DQ10 =119, DQ11 =115
3524 12:43:07.473594 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3525 12:43:07.473677
3526 12:43:07.473743
3527 12:43:07.473801 ==
3528 12:43:07.477074 Dram Type= 6, Freq= 0, CH_1, rank 1
3529 12:43:07.479884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3530 12:43:07.479958 ==
3531 12:43:07.480022
3532 12:43:07.480078
3533 12:43:07.483386 TX Vref Scan disable
3534 12:43:07.483456 == TX Byte 0 ==
3535 12:43:07.490235 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3536 12:43:07.493639 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3537 12:43:07.493713 == TX Byte 1 ==
3538 12:43:07.500146 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3539 12:43:07.503319 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3540 12:43:07.503401 ==
3541 12:43:07.506965 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 12:43:07.510012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 12:43:07.510090 ==
3544 12:43:07.522564 TX Vref=22, minBit 9, minWin=25, winSum=420
3545 12:43:07.526254 TX Vref=24, minBit 9, minWin=25, winSum=425
3546 12:43:07.529107 TX Vref=26, minBit 10, minWin=25, winSum=429
3547 12:43:07.532747 TX Vref=28, minBit 2, minWin=26, winSum=432
3548 12:43:07.535992 TX Vref=30, minBit 9, minWin=26, winSum=434
3549 12:43:07.543059 TX Vref=32, minBit 9, minWin=26, winSum=434
3550 12:43:07.546174 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3551 12:43:07.546263
3552 12:43:07.549779 Final TX Range 1 Vref 30
3553 12:43:07.549858
3554 12:43:07.549921 ==
3555 12:43:07.552531 Dram Type= 6, Freq= 0, CH_1, rank 1
3556 12:43:07.555989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3557 12:43:07.556069 ==
3558 12:43:07.559483
3559 12:43:07.559563
3560 12:43:07.559625 TX Vref Scan disable
3561 12:43:07.562280 == TX Byte 0 ==
3562 12:43:07.565745 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3563 12:43:07.572772 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3564 12:43:07.572867 == TX Byte 1 ==
3565 12:43:07.576089 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3566 12:43:07.582487 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3567 12:43:07.582568
3568 12:43:07.582630 [DATLAT]
3569 12:43:07.582688 Freq=1200, CH1 RK1
3570 12:43:07.582744
3571 12:43:07.586058 DATLAT Default: 0xd
3572 12:43:07.586138 0, 0xFFFF, sum = 0
3573 12:43:07.588907 1, 0xFFFF, sum = 0
3574 12:43:07.592313 2, 0xFFFF, sum = 0
3575 12:43:07.592408 3, 0xFFFF, sum = 0
3576 12:43:07.595767 4, 0xFFFF, sum = 0
3577 12:43:07.595848 5, 0xFFFF, sum = 0
3578 12:43:07.599306 6, 0xFFFF, sum = 0
3579 12:43:07.599387 7, 0xFFFF, sum = 0
3580 12:43:07.602828 8, 0xFFFF, sum = 0
3581 12:43:07.602908 9, 0xFFFF, sum = 0
3582 12:43:07.605545 10, 0xFFFF, sum = 0
3583 12:43:07.605626 11, 0xFFFF, sum = 0
3584 12:43:07.608926 12, 0x0, sum = 1
3585 12:43:07.609006 13, 0x0, sum = 2
3586 12:43:07.612129 14, 0x0, sum = 3
3587 12:43:07.612209 15, 0x0, sum = 4
3588 12:43:07.612273 best_step = 13
3589 12:43:07.615695
3590 12:43:07.615773 ==
3591 12:43:07.619189 Dram Type= 6, Freq= 0, CH_1, rank 1
3592 12:43:07.622703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3593 12:43:07.622788 ==
3594 12:43:07.622851 RX Vref Scan: 0
3595 12:43:07.622909
3596 12:43:07.625387 RX Vref 0 -> 0, step: 1
3597 12:43:07.625466
3598 12:43:07.628860 RX Delay -5 -> 252, step: 4
3599 12:43:07.632632 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3600 12:43:07.639342 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3601 12:43:07.642059 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3602 12:43:07.645950 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3603 12:43:07.648733 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3604 12:43:07.652169 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3605 12:43:07.658605 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3606 12:43:07.661937 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3607 12:43:07.665281 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3608 12:43:07.668502 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3609 12:43:07.671913 iDelay=195, Bit 10, Center 120 (59 ~ 182) 124
3610 12:43:07.678856 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3611 12:43:07.681596 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3612 12:43:07.685131 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3613 12:43:07.688441 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3614 12:43:07.694978 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3615 12:43:07.695053 ==
3616 12:43:07.698429 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 12:43:07.701768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 12:43:07.701847 ==
3619 12:43:07.701912 DQS Delay:
3620 12:43:07.705287 DQS0 = 0, DQS1 = 0
3621 12:43:07.705357 DQM Delay:
3622 12:43:07.708052 DQM0 = 120, DQM1 = 118
3623 12:43:07.708149 DQ Delay:
3624 12:43:07.711517 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3625 12:43:07.714776 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3626 12:43:07.718215 DQ8 =106, DQ9 =108, DQ10 =120, DQ11 =112
3627 12:43:07.721635 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3628 12:43:07.721710
3629 12:43:07.721779
3630 12:43:07.731280 [DQSOSCAuto] RK1, (LSB)MR18= 0x11ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3631 12:43:07.734782 CH1 RK1: MR19=403, MR18=11EE
3632 12:43:07.738322 CH1_RK1: MR19=0x403, MR18=0x11EE, DQSOSC=403, MR23=63, INC=40, DEC=26
3633 12:43:07.741822 [RxdqsGatingPostProcess] freq 1200
3634 12:43:07.747947 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3635 12:43:07.751836 best DQS0 dly(2T, 0.5T) = (0, 11)
3636 12:43:07.755207 best DQS1 dly(2T, 0.5T) = (0, 11)
3637 12:43:07.758608 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3638 12:43:07.761357 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3639 12:43:07.764645 best DQS0 dly(2T, 0.5T) = (0, 11)
3640 12:43:07.768243 best DQS1 dly(2T, 0.5T) = (0, 11)
3641 12:43:07.771457 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3642 12:43:07.775204 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3643 12:43:07.778218 Pre-setting of DQS Precalculation
3644 12:43:07.781364 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3645 12:43:07.788065 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3646 12:43:07.794939 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3647 12:43:07.795018
3648 12:43:07.798249
3649 12:43:07.798335 [Calibration Summary] 2400 Mbps
3650 12:43:07.801198 CH 0, Rank 0
3651 12:43:07.801270 SW Impedance : PASS
3652 12:43:07.804600 DUTY Scan : NO K
3653 12:43:07.807686 ZQ Calibration : PASS
3654 12:43:07.807759 Jitter Meter : NO K
3655 12:43:07.811159 CBT Training : PASS
3656 12:43:07.814717 Write leveling : PASS
3657 12:43:07.814799 RX DQS gating : PASS
3658 12:43:07.818060 RX DQ/DQS(RDDQC) : PASS
3659 12:43:07.821411 TX DQ/DQS : PASS
3660 12:43:07.821482 RX DATLAT : PASS
3661 12:43:07.824821 RX DQ/DQS(Engine): PASS
3662 12:43:07.828392 TX OE : NO K
3663 12:43:07.828469 All Pass.
3664 12:43:07.828532
3665 12:43:07.828590 CH 0, Rank 1
3666 12:43:07.831128 SW Impedance : PASS
3667 12:43:07.834687 DUTY Scan : NO K
3668 12:43:07.834760 ZQ Calibration : PASS
3669 12:43:07.838095 Jitter Meter : NO K
3670 12:43:07.838174 CBT Training : PASS
3671 12:43:07.841136 Write leveling : PASS
3672 12:43:07.844618 RX DQS gating : PASS
3673 12:43:07.844694 RX DQ/DQS(RDDQC) : PASS
3674 12:43:07.848047 TX DQ/DQS : PASS
3675 12:43:07.851670 RX DATLAT : PASS
3676 12:43:07.851739 RX DQ/DQS(Engine): PASS
3677 12:43:07.854934 TX OE : NO K
3678 12:43:07.855005 All Pass.
3679 12:43:07.855083
3680 12:43:07.858209 CH 1, Rank 0
3681 12:43:07.858277 SW Impedance : PASS
3682 12:43:07.861523 DUTY Scan : NO K
3683 12:43:07.864756 ZQ Calibration : PASS
3684 12:43:07.864830 Jitter Meter : NO K
3685 12:43:07.868091 CBT Training : PASS
3686 12:43:07.871514 Write leveling : PASS
3687 12:43:07.871595 RX DQS gating : PASS
3688 12:43:07.874772 RX DQ/DQS(RDDQC) : PASS
3689 12:43:07.877962 TX DQ/DQS : PASS
3690 12:43:07.878039 RX DATLAT : PASS
3691 12:43:07.881360 RX DQ/DQS(Engine): PASS
3692 12:43:07.881454 TX OE : NO K
3693 12:43:07.884818 All Pass.
3694 12:43:07.884910
3695 12:43:07.884971 CH 1, Rank 1
3696 12:43:07.887625 SW Impedance : PASS
3697 12:43:07.887712 DUTY Scan : NO K
3698 12:43:07.891038 ZQ Calibration : PASS
3699 12:43:07.894498 Jitter Meter : NO K
3700 12:43:07.894597 CBT Training : PASS
3701 12:43:07.897645 Write leveling : PASS
3702 12:43:07.900885 RX DQS gating : PASS
3703 12:43:07.901001 RX DQ/DQS(RDDQC) : PASS
3704 12:43:07.904305 TX DQ/DQS : PASS
3705 12:43:07.907787 RX DATLAT : PASS
3706 12:43:07.907920 RX DQ/DQS(Engine): PASS
3707 12:43:07.911223 TX OE : NO K
3708 12:43:07.911302 All Pass.
3709 12:43:07.911365
3710 12:43:07.914505 DramC Write-DBI off
3711 12:43:07.917752 PER_BANK_REFRESH: Hybrid Mode
3712 12:43:07.917834 TX_TRACKING: ON
3713 12:43:07.927356 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3714 12:43:07.930814 [FAST_K] Save calibration result to emmc
3715 12:43:07.934383 dramc_set_vcore_voltage set vcore to 650000
3716 12:43:07.937202 Read voltage for 600, 5
3717 12:43:07.937277 Vio18 = 0
3718 12:43:07.937343 Vcore = 650000
3719 12:43:07.940717 Vdram = 0
3720 12:43:07.940794 Vddq = 0
3721 12:43:07.940856 Vmddr = 0
3722 12:43:07.947581 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3723 12:43:07.951005 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3724 12:43:07.953857 MEM_TYPE=3, freq_sel=19
3725 12:43:07.957345 sv_algorithm_assistance_LP4_1600
3726 12:43:07.960864 ============ PULL DRAM RESETB DOWN ============
3727 12:43:07.964186 ========== PULL DRAM RESETB DOWN end =========
3728 12:43:07.970814 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3729 12:43:07.974140 ===================================
3730 12:43:07.977485 LPDDR4 DRAM CONFIGURATION
3731 12:43:07.980882 ===================================
3732 12:43:07.980962 EX_ROW_EN[0] = 0x0
3733 12:43:07.984069 EX_ROW_EN[1] = 0x0
3734 12:43:07.984200 LP4Y_EN = 0x0
3735 12:43:07.987296 WORK_FSP = 0x0
3736 12:43:07.987376 WL = 0x2
3737 12:43:07.990571 RL = 0x2
3738 12:43:07.990651 BL = 0x2
3739 12:43:07.994036 RPST = 0x0
3740 12:43:07.994116 RD_PRE = 0x0
3741 12:43:07.997544 WR_PRE = 0x1
3742 12:43:07.997623 WR_PST = 0x0
3743 12:43:08.000986 DBI_WR = 0x0
3744 12:43:08.001065 DBI_RD = 0x0
3745 12:43:08.004258 OTF = 0x1
3746 12:43:08.006967 ===================================
3747 12:43:08.010794 ===================================
3748 12:43:08.010874 ANA top config
3749 12:43:08.014134 ===================================
3750 12:43:08.017617 DLL_ASYNC_EN = 0
3751 12:43:08.020388 ALL_SLAVE_EN = 1
3752 12:43:08.023827 NEW_RANK_MODE = 1
3753 12:43:08.023908 DLL_IDLE_MODE = 1
3754 12:43:08.027247 LP45_APHY_COMB_EN = 1
3755 12:43:08.030701 TX_ODT_DIS = 1
3756 12:43:08.034044 NEW_8X_MODE = 1
3757 12:43:08.037329 ===================================
3758 12:43:08.040623 ===================================
3759 12:43:08.043845 data_rate = 1200
3760 12:43:08.043925 CKR = 1
3761 12:43:08.047385 DQ_P2S_RATIO = 8
3762 12:43:08.050237 ===================================
3763 12:43:08.053629 CA_P2S_RATIO = 8
3764 12:43:08.057438 DQ_CA_OPEN = 0
3765 12:43:08.060917 DQ_SEMI_OPEN = 0
3766 12:43:08.063765 CA_SEMI_OPEN = 0
3767 12:43:08.063844 CA_FULL_RATE = 0
3768 12:43:08.067190 DQ_CKDIV4_EN = 1
3769 12:43:08.070528 CA_CKDIV4_EN = 1
3770 12:43:08.074320 CA_PREDIV_EN = 0
3771 12:43:08.076912 PH8_DLY = 0
3772 12:43:08.080183 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3773 12:43:08.080310 DQ_AAMCK_DIV = 4
3774 12:43:08.084132 CA_AAMCK_DIV = 4
3775 12:43:08.086735 CA_ADMCK_DIV = 4
3776 12:43:08.090086 DQ_TRACK_CA_EN = 0
3777 12:43:08.094075 CA_PICK = 600
3778 12:43:08.096769 CA_MCKIO = 600
3779 12:43:08.096849 MCKIO_SEMI = 0
3780 12:43:08.100193 PLL_FREQ = 2288
3781 12:43:08.103713 DQ_UI_PI_RATIO = 32
3782 12:43:08.107188 CA_UI_PI_RATIO = 0
3783 12:43:08.110554 ===================================
3784 12:43:08.113797 ===================================
3785 12:43:08.117214 memory_type:LPDDR4
3786 12:43:08.117294 GP_NUM : 10
3787 12:43:08.119831 SRAM_EN : 1
3788 12:43:08.123248 MD32_EN : 0
3789 12:43:08.126724 ===================================
3790 12:43:08.126834 [ANA_INIT] >>>>>>>>>>>>>>
3791 12:43:08.130029 <<<<<< [CONFIGURE PHASE]: ANA_TX
3792 12:43:08.133515 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3793 12:43:08.136947 ===================================
3794 12:43:08.139769 data_rate = 1200,PCW = 0X5800
3795 12:43:08.143233 ===================================
3796 12:43:08.146772 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3797 12:43:08.153011 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3798 12:43:08.156880 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3799 12:43:08.163342 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3800 12:43:08.166637 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3801 12:43:08.169642 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3802 12:43:08.173054 [ANA_INIT] flow start
3803 12:43:08.173134 [ANA_INIT] PLL >>>>>>>>
3804 12:43:08.176637 [ANA_INIT] PLL <<<<<<<<
3805 12:43:08.179934 [ANA_INIT] MIDPI >>>>>>>>
3806 12:43:08.180013 [ANA_INIT] MIDPI <<<<<<<<
3807 12:43:08.183393 [ANA_INIT] DLL >>>>>>>>
3808 12:43:08.186198 [ANA_INIT] flow end
3809 12:43:08.189515 ============ LP4 DIFF to SE enter ============
3810 12:43:08.192846 ============ LP4 DIFF to SE exit ============
3811 12:43:08.196173 [ANA_INIT] <<<<<<<<<<<<<
3812 12:43:08.199427 [Flow] Enable top DCM control >>>>>
3813 12:43:08.202786 [Flow] Enable top DCM control <<<<<
3814 12:43:08.206423 Enable DLL master slave shuffle
3815 12:43:08.209649 ==============================================================
3816 12:43:08.212494 Gating Mode config
3817 12:43:08.219220 ==============================================================
3818 12:43:08.219300 Config description:
3819 12:43:08.229266 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3820 12:43:08.235809 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3821 12:43:08.239227 SELPH_MODE 0: By rank 1: By Phase
3822 12:43:08.246137 ==============================================================
3823 12:43:08.249692 GAT_TRACK_EN = 1
3824 12:43:08.252566 RX_GATING_MODE = 2
3825 12:43:08.256012 RX_GATING_TRACK_MODE = 2
3826 12:43:08.259516 SELPH_MODE = 1
3827 12:43:08.262935 PICG_EARLY_EN = 1
3828 12:43:08.265724 VALID_LAT_VALUE = 1
3829 12:43:08.269238 ==============================================================
3830 12:43:08.272776 Enter into Gating configuration >>>>
3831 12:43:08.275760 Exit from Gating configuration <<<<
3832 12:43:08.278973 Enter into DVFS_PRE_config >>>>>
3833 12:43:08.292173 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3834 12:43:08.292260 Exit from DVFS_PRE_config <<<<<
3835 12:43:08.295796 Enter into PICG configuration >>>>
3836 12:43:08.298956 Exit from PICG configuration <<<<
3837 12:43:08.302186 [RX_INPUT] configuration >>>>>
3838 12:43:08.305592 [RX_INPUT] configuration <<<<<
3839 12:43:08.312262 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3840 12:43:08.315833 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3841 12:43:08.322162 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3842 12:43:08.328915 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3843 12:43:08.335838 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3844 12:43:08.342371 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3845 12:43:08.345664 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3846 12:43:08.348892 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3847 12:43:08.352440 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3848 12:43:08.358697 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3849 12:43:08.362077 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3850 12:43:08.365652 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3851 12:43:08.368954 ===================================
3852 12:43:08.372524 LPDDR4 DRAM CONFIGURATION
3853 12:43:08.375324 ===================================
3854 12:43:08.375404 EX_ROW_EN[0] = 0x0
3855 12:43:08.378817 EX_ROW_EN[1] = 0x0
3856 12:43:08.382343 LP4Y_EN = 0x0
3857 12:43:08.382424 WORK_FSP = 0x0
3858 12:43:08.385854 WL = 0x2
3859 12:43:08.385933 RL = 0x2
3860 12:43:08.389318 BL = 0x2
3861 12:43:08.389397 RPST = 0x0
3862 12:43:08.392021 RD_PRE = 0x0
3863 12:43:08.392100 WR_PRE = 0x1
3864 12:43:08.395582 WR_PST = 0x0
3865 12:43:08.395661 DBI_WR = 0x0
3866 12:43:08.399024 DBI_RD = 0x0
3867 12:43:08.399104 OTF = 0x1
3868 12:43:08.402419 ===================================
3869 12:43:08.405816 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3870 12:43:08.412459 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3871 12:43:08.415498 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3872 12:43:08.419016 ===================================
3873 12:43:08.421828 LPDDR4 DRAM CONFIGURATION
3874 12:43:08.425359 ===================================
3875 12:43:08.425439 EX_ROW_EN[0] = 0x10
3876 12:43:08.428730 EX_ROW_EN[1] = 0x0
3877 12:43:08.428810 LP4Y_EN = 0x0
3878 12:43:08.431825 WORK_FSP = 0x0
3879 12:43:08.431904 WL = 0x2
3880 12:43:08.435134 RL = 0x2
3881 12:43:08.438699 BL = 0x2
3882 12:43:08.438800 RPST = 0x0
3883 12:43:08.442236 RD_PRE = 0x0
3884 12:43:08.442315 WR_PRE = 0x1
3885 12:43:08.445244 WR_PST = 0x0
3886 12:43:08.445339 DBI_WR = 0x0
3887 12:43:08.448427 DBI_RD = 0x0
3888 12:43:08.448507 OTF = 0x1
3889 12:43:08.452078 ===================================
3890 12:43:08.458236 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3891 12:43:08.462504 nWR fixed to 30
3892 12:43:08.465694 [ModeRegInit_LP4] CH0 RK0
3893 12:43:08.465775 [ModeRegInit_LP4] CH0 RK1
3894 12:43:08.469227 [ModeRegInit_LP4] CH1 RK0
3895 12:43:08.472642 [ModeRegInit_LP4] CH1 RK1
3896 12:43:08.472721 match AC timing 17
3897 12:43:08.478956 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3898 12:43:08.482481 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3899 12:43:08.486107 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3900 12:43:08.492394 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3901 12:43:08.495880 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3902 12:43:08.495960 ==
3903 12:43:08.499281 Dram Type= 6, Freq= 0, CH_0, rank 0
3904 12:43:08.502204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3905 12:43:08.502285 ==
3906 12:43:08.508932 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3907 12:43:08.515907 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3908 12:43:08.519456 [CA 0] Center 35 (5~66) winsize 62
3909 12:43:08.522304 [CA 1] Center 35 (5~66) winsize 62
3910 12:43:08.525947 [CA 2] Center 33 (3~64) winsize 62
3911 12:43:08.529303 [CA 3] Center 33 (2~64) winsize 63
3912 12:43:08.532389 [CA 4] Center 33 (2~64) winsize 63
3913 12:43:08.535464 [CA 5] Center 32 (2~63) winsize 62
3914 12:43:08.535547
3915 12:43:08.538634 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3916 12:43:08.538715
3917 12:43:08.542363 [CATrainingPosCal] consider 1 rank data
3918 12:43:08.545624 u2DelayCellTimex100 = 270/100 ps
3919 12:43:08.548725 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3920 12:43:08.552424 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3921 12:43:08.555256 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3922 12:43:08.558648 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3923 12:43:08.562108 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3924 12:43:08.565576 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3925 12:43:08.568854
3926 12:43:08.572416 CA PerBit enable=1, Macro0, CA PI delay=32
3927 12:43:08.572496
3928 12:43:08.575369 [CBTSetCACLKResult] CA Dly = 32
3929 12:43:08.575456 CS Dly: 5 (0~36)
3930 12:43:08.575558 ==
3931 12:43:08.578663 Dram Type= 6, Freq= 0, CH_0, rank 1
3932 12:43:08.581977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3933 12:43:08.585016 ==
3934 12:43:08.588260 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3935 12:43:08.594723 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3936 12:43:08.598197 [CA 0] Center 35 (5~66) winsize 62
3937 12:43:08.601610 [CA 1] Center 35 (5~66) winsize 62
3938 12:43:08.605006 [CA 2] Center 34 (3~65) winsize 63
3939 12:43:08.608459 [CA 3] Center 33 (3~64) winsize 62
3940 12:43:08.612035 [CA 4] Center 33 (2~64) winsize 63
3941 12:43:08.614642 [CA 5] Center 32 (1~63) winsize 63
3942 12:43:08.614721
3943 12:43:08.618094 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3944 12:43:08.618174
3945 12:43:08.621876 [CATrainingPosCal] consider 2 rank data
3946 12:43:08.625132 u2DelayCellTimex100 = 270/100 ps
3947 12:43:08.627965 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3948 12:43:08.631542 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3949 12:43:08.635005 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3950 12:43:08.638642 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3951 12:43:08.644520 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3952 12:43:08.647932 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3953 12:43:08.648011
3954 12:43:08.651140 CA PerBit enable=1, Macro0, CA PI delay=32
3955 12:43:08.651224
3956 12:43:08.654578 [CBTSetCACLKResult] CA Dly = 32
3957 12:43:08.654658 CS Dly: 5 (0~36)
3958 12:43:08.654719
3959 12:43:08.658000 ----->DramcWriteLeveling(PI) begin...
3960 12:43:08.661477 ==
3961 12:43:08.661557 Dram Type= 6, Freq= 0, CH_0, rank 0
3962 12:43:08.667781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3963 12:43:08.667861 ==
3964 12:43:08.671327 Write leveling (Byte 0): 34 => 34
3965 12:43:08.674708 Write leveling (Byte 1): 30 => 30
3966 12:43:08.678199 DramcWriteLeveling(PI) end<-----
3967 12:43:08.678279
3968 12:43:08.678342 ==
3969 12:43:08.680961 Dram Type= 6, Freq= 0, CH_0, rank 0
3970 12:43:08.684543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3971 12:43:08.684623 ==
3972 12:43:08.688114 [Gating] SW mode calibration
3973 12:43:08.694295 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3974 12:43:08.697382 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3975 12:43:08.704478 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3976 12:43:08.707909 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3977 12:43:08.711153 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3978 12:43:08.717431 0 9 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 1)
3979 12:43:08.720738 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
3980 12:43:08.724363 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 12:43:08.731135 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 12:43:08.734627 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 12:43:08.737312 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 12:43:08.744396 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 12:43:08.747419 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 12:43:08.750749 0 10 12 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
3987 12:43:08.758023 0 10 16 | B1->B0 | 3131 4646 | 0 0 | (1 1) (0 0)
3988 12:43:08.760709 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 12:43:08.764065 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 12:43:08.771045 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 12:43:08.774346 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 12:43:08.777535 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 12:43:08.784296 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 12:43:08.787772 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3995 12:43:08.791155 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 12:43:08.794918 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 12:43:08.800854 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 12:43:08.804323 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 12:43:08.807843 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 12:43:08.814169 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 12:43:08.817697 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 12:43:08.821069 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 12:43:08.827776 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 12:43:08.830857 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 12:43:08.833999 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 12:43:08.840649 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 12:43:08.844140 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 12:43:08.847569 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 12:43:08.854128 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 12:43:08.857540 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 12:43:08.860814 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4012 12:43:08.864398 Total UI for P1: 0, mck2ui 16
4013 12:43:08.867670 best dqsien dly found for B0: ( 0, 13, 14)
4014 12:43:08.874103 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 12:43:08.874186 Total UI for P1: 0, mck2ui 16
4016 12:43:08.877575 best dqsien dly found for B1: ( 0, 13, 18)
4017 12:43:08.884437 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4018 12:43:08.887091 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4019 12:43:08.887189
4020 12:43:08.890963 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4021 12:43:08.894108 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4022 12:43:08.897196 [Gating] SW calibration Done
4023 12:43:08.897276 ==
4024 12:43:08.900610 Dram Type= 6, Freq= 0, CH_0, rank 0
4025 12:43:08.904148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4026 12:43:08.904245 ==
4027 12:43:08.906970 RX Vref Scan: 0
4028 12:43:08.907068
4029 12:43:08.907164 RX Vref 0 -> 0, step: 1
4030 12:43:08.907238
4031 12:43:08.910354 RX Delay -230 -> 252, step: 16
4032 12:43:08.917455 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4033 12:43:08.920783 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4034 12:43:08.923618 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4035 12:43:08.926976 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4036 12:43:08.930814 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4037 12:43:08.936721 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4038 12:43:08.940153 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4039 12:43:08.943724 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4040 12:43:08.947247 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4041 12:43:08.953946 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4042 12:43:08.957068 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4043 12:43:08.959994 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4044 12:43:08.963587 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4045 12:43:08.970502 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4046 12:43:08.973585 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4047 12:43:08.976592 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4048 12:43:08.976673 ==
4049 12:43:08.980232 Dram Type= 6, Freq= 0, CH_0, rank 0
4050 12:43:08.983345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4051 12:43:08.983425 ==
4052 12:43:08.987020 DQS Delay:
4053 12:43:08.987100 DQS0 = 0, DQS1 = 0
4054 12:43:08.990026 DQM Delay:
4055 12:43:08.990132 DQM0 = 49, DQM1 = 45
4056 12:43:08.990226 DQ Delay:
4057 12:43:08.994139 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4058 12:43:08.996626 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4059 12:43:09.000032 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4060 12:43:09.003430 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4061 12:43:09.003510
4062 12:43:09.003572
4063 12:43:09.003629 ==
4064 12:43:09.007086 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 12:43:09.013796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 12:43:09.013902 ==
4067 12:43:09.013968
4068 12:43:09.014028
4069 12:43:09.014085 TX Vref Scan disable
4070 12:43:09.017249 == TX Byte 0 ==
4071 12:43:09.020738 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4072 12:43:09.024127 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4073 12:43:09.027508 == TX Byte 1 ==
4074 12:43:09.031013 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4075 12:43:09.037288 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4076 12:43:09.037369 ==
4077 12:43:09.040540 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 12:43:09.043959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 12:43:09.044039 ==
4080 12:43:09.044104
4081 12:43:09.044162
4082 12:43:09.047434 TX Vref Scan disable
4083 12:43:09.050891 == TX Byte 0 ==
4084 12:43:09.053818 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4085 12:43:09.057352 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4086 12:43:09.060819 == TX Byte 1 ==
4087 12:43:09.064249 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4088 12:43:09.067455 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4089 12:43:09.067535
4090 12:43:09.067597 [DATLAT]
4091 12:43:09.070773 Freq=600, CH0 RK0
4092 12:43:09.070852
4093 12:43:09.073879 DATLAT Default: 0x9
4094 12:43:09.073959 0, 0xFFFF, sum = 0
4095 12:43:09.077150 1, 0xFFFF, sum = 0
4096 12:43:09.077233 2, 0xFFFF, sum = 0
4097 12:43:09.080737 3, 0xFFFF, sum = 0
4098 12:43:09.080819 4, 0xFFFF, sum = 0
4099 12:43:09.083931 5, 0xFFFF, sum = 0
4100 12:43:09.084013 6, 0xFFFF, sum = 0
4101 12:43:09.087061 7, 0xFFFF, sum = 0
4102 12:43:09.087141 8, 0x0, sum = 1
4103 12:43:09.090380 9, 0x0, sum = 2
4104 12:43:09.090461 10, 0x0, sum = 3
4105 12:43:09.090525 11, 0x0, sum = 4
4106 12:43:09.093772 best_step = 9
4107 12:43:09.093852
4108 12:43:09.093913 ==
4109 12:43:09.097411 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 12:43:09.100830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 12:43:09.100910 ==
4112 12:43:09.103962 RX Vref Scan: 1
4113 12:43:09.104041
4114 12:43:09.104103 RX Vref 0 -> 0, step: 1
4115 12:43:09.107161
4116 12:43:09.107240 RX Delay -163 -> 252, step: 8
4117 12:43:09.107303
4118 12:43:09.110190 Set Vref, RX VrefLevel [Byte0]: 56
4119 12:43:09.113794 [Byte1]: 49
4120 12:43:09.117767
4121 12:43:09.117846 Final RX Vref Byte 0 = 56 to rank0
4122 12:43:09.121292 Final RX Vref Byte 1 = 49 to rank0
4123 12:43:09.124426 Final RX Vref Byte 0 = 56 to rank1
4124 12:43:09.127690 Final RX Vref Byte 1 = 49 to rank1==
4125 12:43:09.131201 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 12:43:09.137575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 12:43:09.137655 ==
4128 12:43:09.137718 DQS Delay:
4129 12:43:09.137776 DQS0 = 0, DQS1 = 0
4130 12:43:09.141022 DQM Delay:
4131 12:43:09.141101 DQM0 = 52, DQM1 = 46
4132 12:43:09.144464 DQ Delay:
4133 12:43:09.147924 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4134 12:43:09.151303 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4135 12:43:09.151382 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4136 12:43:09.157504 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4137 12:43:09.157584
4138 12:43:09.157647
4139 12:43:09.164347 [DQSOSCAuto] RK0, (LSB)MR18= 0x7367, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps
4140 12:43:09.167765 CH0 RK0: MR19=808, MR18=7367
4141 12:43:09.174061 CH0_RK0: MR19=0x808, MR18=0x7367, DQSOSC=388, MR23=63, INC=174, DEC=116
4142 12:43:09.174140
4143 12:43:09.177362 ----->DramcWriteLeveling(PI) begin...
4144 12:43:09.177443 ==
4145 12:43:09.181210 Dram Type= 6, Freq= 0, CH_0, rank 1
4146 12:43:09.184376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 12:43:09.184456 ==
4148 12:43:09.187858 Write leveling (Byte 0): 35 => 35
4149 12:43:09.191436 Write leveling (Byte 1): 31 => 31
4150 12:43:09.194543 DramcWriteLeveling(PI) end<-----
4151 12:43:09.194622
4152 12:43:09.194684 ==
4153 12:43:09.197914 Dram Type= 6, Freq= 0, CH_0, rank 1
4154 12:43:09.200650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 12:43:09.200750 ==
4156 12:43:09.204211 [Gating] SW mode calibration
4157 12:43:09.210799 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4158 12:43:09.217710 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4159 12:43:09.221207 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4160 12:43:09.227643 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4161 12:43:09.230689 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4162 12:43:09.234042 0 9 12 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 1)
4163 12:43:09.237673 0 9 16 | B1->B0 | 2b2b 2b2b | 0 0 | (1 1) (0 0)
4164 12:43:09.244235 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 12:43:09.247749 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 12:43:09.251214 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 12:43:09.257453 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 12:43:09.260982 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 12:43:09.264021 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 12:43:09.270746 0 10 12 | B1->B0 | 2525 2f2e | 0 1 | (0 0) (0 0)
4171 12:43:09.274255 0 10 16 | B1->B0 | 3e3e 4343 | 0 0 | (0 0) (0 0)
4172 12:43:09.277798 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 12:43:09.284441 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 12:43:09.287756 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 12:43:09.290993 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 12:43:09.297679 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 12:43:09.301085 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 12:43:09.304337 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 12:43:09.310687 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4180 12:43:09.314053 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 12:43:09.317271 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 12:43:09.324176 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 12:43:09.327699 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 12:43:09.330883 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 12:43:09.337458 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 12:43:09.340780 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 12:43:09.344062 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 12:43:09.347475 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 12:43:09.353776 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 12:43:09.357122 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 12:43:09.360341 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 12:43:09.366835 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 12:43:09.370269 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 12:43:09.373976 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4195 12:43:09.380107 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4196 12:43:09.383561 Total UI for P1: 0, mck2ui 16
4197 12:43:09.387101 best dqsien dly found for B0: ( 0, 13, 12)
4198 12:43:09.390551 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 12:43:09.393290 Total UI for P1: 0, mck2ui 16
4200 12:43:09.396700 best dqsien dly found for B1: ( 0, 13, 16)
4201 12:43:09.400036 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4202 12:43:09.403864 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4203 12:43:09.403944
4204 12:43:09.406606 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4205 12:43:09.409934 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4206 12:43:09.413303 [Gating] SW calibration Done
4207 12:43:09.413416 ==
4208 12:43:09.416821 Dram Type= 6, Freq= 0, CH_0, rank 1
4209 12:43:09.423828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4210 12:43:09.423914 ==
4211 12:43:09.423978 RX Vref Scan: 0
4212 12:43:09.424037
4213 12:43:09.427100 RX Vref 0 -> 0, step: 1
4214 12:43:09.427181
4215 12:43:09.430540 RX Delay -230 -> 252, step: 16
4216 12:43:09.433891 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4217 12:43:09.436630 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4218 12:43:09.440002 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4219 12:43:09.447070 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4220 12:43:09.450325 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4221 12:43:09.453839 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4222 12:43:09.457067 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4223 12:43:09.460455 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4224 12:43:09.467143 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4225 12:43:09.470395 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4226 12:43:09.473596 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4227 12:43:09.476834 iDelay=218, Bit 11, Center 41 (-102 ~ 185) 288
4228 12:43:09.483810 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4229 12:43:09.486679 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4230 12:43:09.490008 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4231 12:43:09.493502 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4232 12:43:09.493583 ==
4233 12:43:09.496921 Dram Type= 6, Freq= 0, CH_0, rank 1
4234 12:43:09.504009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4235 12:43:09.504090 ==
4236 12:43:09.504154 DQS Delay:
4237 12:43:09.507284 DQS0 = 0, DQS1 = 0
4238 12:43:09.507365 DQM Delay:
4239 12:43:09.507429 DQM0 = 52, DQM1 = 44
4240 12:43:09.510635 DQ Delay:
4241 12:43:09.513358 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4242 12:43:09.516759 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4243 12:43:09.520007 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4244 12:43:09.523473 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4245 12:43:09.523553
4246 12:43:09.523616
4247 12:43:09.523676 ==
4248 12:43:09.526866 Dram Type= 6, Freq= 0, CH_0, rank 1
4249 12:43:09.530382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 12:43:09.530470 ==
4251 12:43:09.530533
4252 12:43:09.530592
4253 12:43:09.533727 TX Vref Scan disable
4254 12:43:09.533807 == TX Byte 0 ==
4255 12:43:09.540736 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4256 12:43:09.543431 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4257 12:43:09.543511 == TX Byte 1 ==
4258 12:43:09.550271 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4259 12:43:09.553470 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4260 12:43:09.553551 ==
4261 12:43:09.556736 Dram Type= 6, Freq= 0, CH_0, rank 1
4262 12:43:09.560152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4263 12:43:09.560232 ==
4264 12:43:09.560321
4265 12:43:09.563486
4266 12:43:09.563566 TX Vref Scan disable
4267 12:43:09.566875 == TX Byte 0 ==
4268 12:43:09.570885 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4269 12:43:09.573644 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4270 12:43:09.576963 == TX Byte 1 ==
4271 12:43:09.580484 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4272 12:43:09.583912 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4273 12:43:09.587333
4274 12:43:09.587414 [DATLAT]
4275 12:43:09.587477 Freq=600, CH0 RK1
4276 12:43:09.587537
4277 12:43:09.590858 DATLAT Default: 0x9
4278 12:43:09.590938 0, 0xFFFF, sum = 0
4279 12:43:09.593618 1, 0xFFFF, sum = 0
4280 12:43:09.593700 2, 0xFFFF, sum = 0
4281 12:43:09.597101 3, 0xFFFF, sum = 0
4282 12:43:09.597183 4, 0xFFFF, sum = 0
4283 12:43:09.600412 5, 0xFFFF, sum = 0
4284 12:43:09.603912 6, 0xFFFF, sum = 0
4285 12:43:09.604020 7, 0xFFFF, sum = 0
4286 12:43:09.606697 8, 0x0, sum = 1
4287 12:43:09.606778 9, 0x0, sum = 2
4288 12:43:09.606843 10, 0x0, sum = 3
4289 12:43:09.610183 11, 0x0, sum = 4
4290 12:43:09.610264 best_step = 9
4291 12:43:09.610328
4292 12:43:09.610387 ==
4293 12:43:09.613540 Dram Type= 6, Freq= 0, CH_0, rank 1
4294 12:43:09.619911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4295 12:43:09.620000 ==
4296 12:43:09.620067 RX Vref Scan: 0
4297 12:43:09.620130
4298 12:43:09.623273 RX Vref 0 -> 0, step: 1
4299 12:43:09.623364
4300 12:43:09.626487 RX Delay -163 -> 252, step: 8
4301 12:43:09.629952 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4302 12:43:09.636878 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4303 12:43:09.640222 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4304 12:43:09.643625 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4305 12:43:09.647140 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4306 12:43:09.649792 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4307 12:43:09.653731 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4308 12:43:09.659925 iDelay=205, Bit 7, Center 60 (-83 ~ 204) 288
4309 12:43:09.663203 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4310 12:43:09.666457 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4311 12:43:09.670342 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4312 12:43:09.676825 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4313 12:43:09.680157 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4314 12:43:09.683504 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4315 12:43:09.686838 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4316 12:43:09.690175 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4317 12:43:09.693587 ==
4318 12:43:09.696420 Dram Type= 6, Freq= 0, CH_0, rank 1
4319 12:43:09.699838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 12:43:09.699917 ==
4321 12:43:09.699980 DQS Delay:
4322 12:43:09.703135 DQS0 = 0, DQS1 = 0
4323 12:43:09.703214 DQM Delay:
4324 12:43:09.706582 DQM0 = 53, DQM1 = 46
4325 12:43:09.706661 DQ Delay:
4326 12:43:09.710083 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4327 12:43:09.712899 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =60
4328 12:43:09.716504 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4329 12:43:09.719970 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4330 12:43:09.720048
4331 12:43:09.720109
4332 12:43:09.726691 [DQSOSCAuto] RK1, (LSB)MR18= 0x6828, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4333 12:43:09.729964 CH0 RK1: MR19=808, MR18=6828
4334 12:43:09.736010 CH0_RK1: MR19=0x808, MR18=0x6828, DQSOSC=390, MR23=63, INC=172, DEC=114
4335 12:43:09.739385 [RxdqsGatingPostProcess] freq 600
4336 12:43:09.746258 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4337 12:43:09.749570 Pre-setting of DQS Precalculation
4338 12:43:09.752407 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4339 12:43:09.752487 ==
4340 12:43:09.755862 Dram Type= 6, Freq= 0, CH_1, rank 0
4341 12:43:09.759135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 12:43:09.759214 ==
4343 12:43:09.766113 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4344 12:43:09.772992 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4345 12:43:09.775612 [CA 0] Center 36 (5~67) winsize 63
4346 12:43:09.779443 [CA 1] Center 36 (5~67) winsize 63
4347 12:43:09.782893 [CA 2] Center 34 (4~65) winsize 62
4348 12:43:09.786012 [CA 3] Center 34 (4~65) winsize 62
4349 12:43:09.789121 [CA 4] Center 34 (4~65) winsize 62
4350 12:43:09.792338 [CA 5] Center 34 (3~65) winsize 63
4351 12:43:09.792418
4352 12:43:09.795744 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4353 12:43:09.795823
4354 12:43:09.799447 [CATrainingPosCal] consider 1 rank data
4355 12:43:09.802877 u2DelayCellTimex100 = 270/100 ps
4356 12:43:09.805567 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4357 12:43:09.808993 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4358 12:43:09.812548 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4359 12:43:09.816054 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4360 12:43:09.819525 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4361 12:43:09.822317 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4362 12:43:09.825809
4363 12:43:09.829208 CA PerBit enable=1, Macro0, CA PI delay=34
4364 12:43:09.829288
4365 12:43:09.832633 [CBTSetCACLKResult] CA Dly = 34
4366 12:43:09.832713 CS Dly: 5 (0~36)
4367 12:43:09.832775 ==
4368 12:43:09.835877 Dram Type= 6, Freq= 0, CH_1, rank 1
4369 12:43:09.839121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4370 12:43:09.839203 ==
4371 12:43:09.845835 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4372 12:43:09.852987 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4373 12:43:09.855644 [CA 0] Center 36 (5~67) winsize 63
4374 12:43:09.859165 [CA 1] Center 36 (5~67) winsize 63
4375 12:43:09.862528 [CA 2] Center 35 (4~66) winsize 63
4376 12:43:09.865867 [CA 3] Center 34 (4~65) winsize 62
4377 12:43:09.869332 [CA 4] Center 35 (4~66) winsize 63
4378 12:43:09.872539 [CA 5] Center 34 (3~65) winsize 63
4379 12:43:09.872619
4380 12:43:09.875971 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4381 12:43:09.876051
4382 12:43:09.879420 [CATrainingPosCal] consider 2 rank data
4383 12:43:09.882794 u2DelayCellTimex100 = 270/100 ps
4384 12:43:09.885662 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4385 12:43:09.889089 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4386 12:43:09.892649 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4387 12:43:09.895738 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4388 12:43:09.898981 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4389 12:43:09.905599 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4390 12:43:09.905679
4391 12:43:09.909122 CA PerBit enable=1, Macro0, CA PI delay=34
4392 12:43:09.909201
4393 12:43:09.912252 [CBTSetCACLKResult] CA Dly = 34
4394 12:43:09.912377 CS Dly: 6 (0~38)
4395 12:43:09.912440
4396 12:43:09.915902 ----->DramcWriteLeveling(PI) begin...
4397 12:43:09.915983 ==
4398 12:43:09.918988 Dram Type= 6, Freq= 0, CH_1, rank 0
4399 12:43:09.925883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4400 12:43:09.925964 ==
4401 12:43:09.929200 Write leveling (Byte 0): 30 => 30
4402 12:43:09.929280 Write leveling (Byte 1): 32 => 32
4403 12:43:09.932113 DramcWriteLeveling(PI) end<-----
4404 12:43:09.932220
4405 12:43:09.932345 ==
4406 12:43:09.935608 Dram Type= 6, Freq= 0, CH_1, rank 0
4407 12:43:09.942393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4408 12:43:09.942497 ==
4409 12:43:09.945663 [Gating] SW mode calibration
4410 12:43:09.952509 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4411 12:43:09.955739 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4412 12:43:09.962035 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4413 12:43:09.966089 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4414 12:43:09.968843 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4415 12:43:09.972207 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (1 1) (1 1)
4416 12:43:09.979069 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 12:43:09.982500 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 12:43:09.985864 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 12:43:09.991973 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 12:43:09.995448 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 12:43:09.998968 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 12:43:10.005819 0 10 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
4423 12:43:10.008480 0 10 12 | B1->B0 | 3535 3a3a | 1 0 | (0 0) (0 0)
4424 12:43:10.012008 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 12:43:10.019045 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 12:43:10.022268 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 12:43:10.025588 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 12:43:10.031762 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 12:43:10.035481 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 12:43:10.038266 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4431 12:43:10.045391 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4432 12:43:10.048568 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 12:43:10.051814 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 12:43:10.058725 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 12:43:10.062148 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 12:43:10.065376 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 12:43:10.072083 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 12:43:10.075456 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 12:43:10.078666 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 12:43:10.084728 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 12:43:10.088160 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 12:43:10.091473 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 12:43:10.098396 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 12:43:10.101869 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 12:43:10.104630 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 12:43:10.111584 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 12:43:10.114957 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4448 12:43:10.118398 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4449 12:43:10.121840 Total UI for P1: 0, mck2ui 16
4450 12:43:10.125240 best dqsien dly found for B0: ( 0, 13, 12)
4451 12:43:10.128175 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 12:43:10.131355 Total UI for P1: 0, mck2ui 16
4453 12:43:10.134642 best dqsien dly found for B1: ( 0, 13, 14)
4454 12:43:10.141606 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4455 12:43:10.144734 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4456 12:43:10.144815
4457 12:43:10.147798 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4458 12:43:10.151487 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4459 12:43:10.154848 [Gating] SW calibration Done
4460 12:43:10.154929 ==
4461 12:43:10.158065 Dram Type= 6, Freq= 0, CH_1, rank 0
4462 12:43:10.161583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4463 12:43:10.161665 ==
4464 12:43:10.164938 RX Vref Scan: 0
4465 12:43:10.165019
4466 12:43:10.165082 RX Vref 0 -> 0, step: 1
4467 12:43:10.165142
4468 12:43:10.168324 RX Delay -230 -> 252, step: 16
4469 12:43:10.171537 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4470 12:43:10.178162 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4471 12:43:10.181586 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4472 12:43:10.184878 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4473 12:43:10.188135 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4474 12:43:10.191485 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4475 12:43:10.198322 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4476 12:43:10.201786 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4477 12:43:10.204596 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4478 12:43:10.208069 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4479 12:43:10.214516 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4480 12:43:10.217948 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4481 12:43:10.221253 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4482 12:43:10.224715 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4483 12:43:10.231575 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4484 12:43:10.235024 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4485 12:43:10.235104 ==
4486 12:43:10.237965 Dram Type= 6, Freq= 0, CH_1, rank 0
4487 12:43:10.241188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4488 12:43:10.241270 ==
4489 12:43:10.241334 DQS Delay:
4490 12:43:10.244762 DQS0 = 0, DQS1 = 0
4491 12:43:10.244842 DQM Delay:
4492 12:43:10.248092 DQM0 = 50, DQM1 = 46
4493 12:43:10.248172 DQ Delay:
4494 12:43:10.251506 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4495 12:43:10.254804 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4496 12:43:10.258163 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4497 12:43:10.261409 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4498 12:43:10.261489
4499 12:43:10.261553
4500 12:43:10.261611 ==
4501 12:43:10.264795 Dram Type= 6, Freq= 0, CH_1, rank 0
4502 12:43:10.267896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4503 12:43:10.271794 ==
4504 12:43:10.271875
4505 12:43:10.271938
4506 12:43:10.271997 TX Vref Scan disable
4507 12:43:10.275273 == TX Byte 0 ==
4508 12:43:10.278574 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4509 12:43:10.281740 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4510 12:43:10.284975 == TX Byte 1 ==
4511 12:43:10.288420 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4512 12:43:10.291866 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4513 12:43:10.291947 ==
4514 12:43:10.295155 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 12:43:10.301350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 12:43:10.301432 ==
4517 12:43:10.301497
4518 12:43:10.301556
4519 12:43:10.301612 TX Vref Scan disable
4520 12:43:10.305986 == TX Byte 0 ==
4521 12:43:10.309416 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4522 12:43:10.316315 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4523 12:43:10.316411 == TX Byte 1 ==
4524 12:43:10.319099 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4525 12:43:10.325823 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4526 12:43:10.325904
4527 12:43:10.325968 [DATLAT]
4528 12:43:10.326027 Freq=600, CH1 RK0
4529 12:43:10.326085
4530 12:43:10.329170 DATLAT Default: 0x9
4531 12:43:10.329250 0, 0xFFFF, sum = 0
4532 12:43:10.332577 1, 0xFFFF, sum = 0
4533 12:43:10.335996 2, 0xFFFF, sum = 0
4534 12:43:10.336077 3, 0xFFFF, sum = 0
4535 12:43:10.339492 4, 0xFFFF, sum = 0
4536 12:43:10.339574 5, 0xFFFF, sum = 0
4537 12:43:10.342200 6, 0xFFFF, sum = 0
4538 12:43:10.342282 7, 0xFFFF, sum = 0
4539 12:43:10.346250 8, 0x0, sum = 1
4540 12:43:10.346332 9, 0x0, sum = 2
4541 12:43:10.346397 10, 0x0, sum = 3
4542 12:43:10.348958 11, 0x0, sum = 4
4543 12:43:10.349040 best_step = 9
4544 12:43:10.349104
4545 12:43:10.349162 ==
4546 12:43:10.352505 Dram Type= 6, Freq= 0, CH_1, rank 0
4547 12:43:10.359435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4548 12:43:10.359515 ==
4549 12:43:10.359578 RX Vref Scan: 1
4550 12:43:10.359637
4551 12:43:10.362246 RX Vref 0 -> 0, step: 1
4552 12:43:10.362327
4553 12:43:10.365851 RX Delay -163 -> 252, step: 8
4554 12:43:10.365932
4555 12:43:10.369111 Set Vref, RX VrefLevel [Byte0]: 53
4556 12:43:10.372578 [Byte1]: 54
4557 12:43:10.372660
4558 12:43:10.375782 Final RX Vref Byte 0 = 53 to rank0
4559 12:43:10.379350 Final RX Vref Byte 1 = 54 to rank0
4560 12:43:10.382857 Final RX Vref Byte 0 = 53 to rank1
4561 12:43:10.386013 Final RX Vref Byte 1 = 54 to rank1==
4562 12:43:10.388949 Dram Type= 6, Freq= 0, CH_1, rank 0
4563 12:43:10.392733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4564 12:43:10.392814 ==
4565 12:43:10.395898 DQS Delay:
4566 12:43:10.395978 DQS0 = 0, DQS1 = 0
4567 12:43:10.396042 DQM Delay:
4568 12:43:10.399127 DQM0 = 48, DQM1 = 44
4569 12:43:10.399207 DQ Delay:
4570 12:43:10.402506 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4571 12:43:10.405820 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4572 12:43:10.409066 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =40
4573 12:43:10.412184 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4574 12:43:10.412264
4575 12:43:10.412366
4576 12:43:10.422154 [DQSOSCAuto] RK0, (LSB)MR18= 0x476c, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4577 12:43:10.425684 CH1 RK0: MR19=808, MR18=476C
4578 12:43:10.429040 CH1_RK0: MR19=0x808, MR18=0x476C, DQSOSC=389, MR23=63, INC=173, DEC=115
4579 12:43:10.429139
4580 12:43:10.432444 ----->DramcWriteLeveling(PI) begin...
4581 12:43:10.435916 ==
4582 12:43:10.439359 Dram Type= 6, Freq= 0, CH_1, rank 1
4583 12:43:10.442781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 12:43:10.442863 ==
4585 12:43:10.445486 Write leveling (Byte 0): 29 => 29
4586 12:43:10.448896 Write leveling (Byte 1): 30 => 30
4587 12:43:10.452332 DramcWriteLeveling(PI) end<-----
4588 12:43:10.452413
4589 12:43:10.452476 ==
4590 12:43:10.455734 Dram Type= 6, Freq= 0, CH_1, rank 1
4591 12:43:10.459262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4592 12:43:10.459344 ==
4593 12:43:10.461973 [Gating] SW mode calibration
4594 12:43:10.468904 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4595 12:43:10.475729 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4596 12:43:10.478583 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4597 12:43:10.482080 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4598 12:43:10.488723 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4599 12:43:10.491774 0 9 12 | B1->B0 | 2f2f 3030 | 0 1 | (0 1) (1 1)
4600 12:43:10.495406 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
4601 12:43:10.498731 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 12:43:10.505384 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 12:43:10.508983 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 12:43:10.512143 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 12:43:10.518481 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 12:43:10.521718 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 12:43:10.525465 0 10 12 | B1->B0 | 3636 3232 | 1 0 | (0 0) (1 1)
4608 12:43:10.531812 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 12:43:10.534980 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 12:43:10.538429 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 12:43:10.545160 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 12:43:10.548488 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 12:43:10.551874 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 12:43:10.558480 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 12:43:10.561994 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4616 12:43:10.565450 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 12:43:10.571886 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 12:43:10.575277 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 12:43:10.578817 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 12:43:10.585075 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 12:43:10.588487 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 12:43:10.592048 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 12:43:10.595383 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 12:43:10.602107 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 12:43:10.605541 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 12:43:10.608908 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 12:43:10.615724 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 12:43:10.618820 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 12:43:10.621947 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 12:43:10.628618 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 12:43:10.631769 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 12:43:10.635517 Total UI for P1: 0, mck2ui 16
4633 12:43:10.638470 best dqsien dly found for B0: ( 0, 13, 10)
4634 12:43:10.642145 Total UI for P1: 0, mck2ui 16
4635 12:43:10.645268 best dqsien dly found for B1: ( 0, 13, 10)
4636 12:43:10.648516 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4637 12:43:10.652058 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4638 12:43:10.652138
4639 12:43:10.655127 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4640 12:43:10.658820 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4641 12:43:10.661898 [Gating] SW calibration Done
4642 12:43:10.661978 ==
4643 12:43:10.665404 Dram Type= 6, Freq= 0, CH_1, rank 1
4644 12:43:10.672084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4645 12:43:10.672167 ==
4646 12:43:10.672230 RX Vref Scan: 0
4647 12:43:10.672299
4648 12:43:10.674826 RX Vref 0 -> 0, step: 1
4649 12:43:10.674907
4650 12:43:10.678370 RX Delay -230 -> 252, step: 16
4651 12:43:10.681760 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4652 12:43:10.685292 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4653 12:43:10.688088 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4654 12:43:10.695094 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4655 12:43:10.698478 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4656 12:43:10.702109 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4657 12:43:10.704693 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4658 12:43:10.707984 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4659 12:43:10.714814 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4660 12:43:10.718320 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4661 12:43:10.721578 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4662 12:43:10.725020 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4663 12:43:10.731320 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4664 12:43:10.734799 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4665 12:43:10.738093 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4666 12:43:10.741448 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4667 12:43:10.745004 ==
4668 12:43:10.745085 Dram Type= 6, Freq= 0, CH_1, rank 1
4669 12:43:10.751304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4670 12:43:10.751386 ==
4671 12:43:10.751450 DQS Delay:
4672 12:43:10.754420 DQS0 = 0, DQS1 = 0
4673 12:43:10.754501 DQM Delay:
4674 12:43:10.757898 DQM0 = 50, DQM1 = 48
4675 12:43:10.757994 DQ Delay:
4676 12:43:10.761909 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4677 12:43:10.764677 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4678 12:43:10.768079 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4679 12:43:10.771534 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4680 12:43:10.771615
4681 12:43:10.771713
4682 12:43:10.771771 ==
4683 12:43:10.774905 Dram Type= 6, Freq= 0, CH_1, rank 1
4684 12:43:10.778372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4685 12:43:10.778453 ==
4686 12:43:10.778517
4687 12:43:10.778576
4688 12:43:10.781211 TX Vref Scan disable
4689 12:43:10.784499 == TX Byte 0 ==
4690 12:43:10.787799 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4691 12:43:10.790986 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4692 12:43:10.794485 == TX Byte 1 ==
4693 12:43:10.797954 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4694 12:43:10.801523 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4695 12:43:10.801604 ==
4696 12:43:10.804314 Dram Type= 6, Freq= 0, CH_1, rank 1
4697 12:43:10.807750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4698 12:43:10.811152 ==
4699 12:43:10.811233
4700 12:43:10.811297
4701 12:43:10.811355 TX Vref Scan disable
4702 12:43:10.814554 == TX Byte 0 ==
4703 12:43:10.818042 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4704 12:43:10.824973 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4705 12:43:10.825054 == TX Byte 1 ==
4706 12:43:10.828145 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4707 12:43:10.835104 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4708 12:43:10.835185
4709 12:43:10.835250 [DATLAT]
4710 12:43:10.835309 Freq=600, CH1 RK1
4711 12:43:10.835367
4712 12:43:10.837958 DATLAT Default: 0x9
4713 12:43:10.838039 0, 0xFFFF, sum = 0
4714 12:43:10.841455 1, 0xFFFF, sum = 0
4715 12:43:10.841537 2, 0xFFFF, sum = 0
4716 12:43:10.844817 3, 0xFFFF, sum = 0
4717 12:43:10.848713 4, 0xFFFF, sum = 0
4718 12:43:10.848795 5, 0xFFFF, sum = 0
4719 12:43:10.851233 6, 0xFFFF, sum = 0
4720 12:43:10.851315 7, 0xFFFF, sum = 0
4721 12:43:10.854408 8, 0x0, sum = 1
4722 12:43:10.854490 9, 0x0, sum = 2
4723 12:43:10.854555 10, 0x0, sum = 3
4724 12:43:10.858214 11, 0x0, sum = 4
4725 12:43:10.858296 best_step = 9
4726 12:43:10.858360
4727 12:43:10.858420 ==
4728 12:43:10.861264 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 12:43:10.867950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 12:43:10.868032 ==
4731 12:43:10.868096 RX Vref Scan: 0
4732 12:43:10.868155
4733 12:43:10.871342 RX Vref 0 -> 0, step: 1
4734 12:43:10.871434
4735 12:43:10.874413 RX Delay -163 -> 252, step: 8
4736 12:43:10.877652 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4737 12:43:10.884707 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4738 12:43:10.887955 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4739 12:43:10.891460 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4740 12:43:10.894555 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4741 12:43:10.897639 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4742 12:43:10.904552 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4743 12:43:10.907908 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4744 12:43:10.910811 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4745 12:43:10.914365 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4746 12:43:10.917557 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4747 12:43:10.924528 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4748 12:43:10.927959 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4749 12:43:10.931094 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4750 12:43:10.934412 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4751 12:43:10.941099 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4752 12:43:10.941180 ==
4753 12:43:10.944450 Dram Type= 6, Freq= 0, CH_1, rank 1
4754 12:43:10.947870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4755 12:43:10.947952 ==
4756 12:43:10.948016 DQS Delay:
4757 12:43:10.950657 DQS0 = 0, DQS1 = 0
4758 12:43:10.950737 DQM Delay:
4759 12:43:10.954047 DQM0 = 48, DQM1 = 45
4760 12:43:10.954127 DQ Delay:
4761 12:43:10.957497 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4762 12:43:10.960979 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4763 12:43:10.964166 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4764 12:43:10.967648 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4765 12:43:10.967760
4766 12:43:10.967855
4767 12:43:10.973943 [DQSOSCAuto] RK1, (LSB)MR18= 0x6920, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 390 ps
4768 12:43:10.977760 CH1 RK1: MR19=808, MR18=6920
4769 12:43:10.984324 CH1_RK1: MR19=0x808, MR18=0x6920, DQSOSC=390, MR23=63, INC=172, DEC=114
4770 12:43:10.987289 [RxdqsGatingPostProcess] freq 600
4771 12:43:10.993983 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4772 12:43:10.997193 Pre-setting of DQS Precalculation
4773 12:43:11.000799 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4774 12:43:11.007438 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4775 12:43:11.013946 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4776 12:43:11.014028
4777 12:43:11.014092
4778 12:43:11.017861 [Calibration Summary] 1200 Mbps
4779 12:43:11.021050 CH 0, Rank 0
4780 12:43:11.021131 SW Impedance : PASS
4781 12:43:11.024151 DUTY Scan : NO K
4782 12:43:11.027335 ZQ Calibration : PASS
4783 12:43:11.027442 Jitter Meter : NO K
4784 12:43:11.030549 CBT Training : PASS
4785 12:43:11.030629 Write leveling : PASS
4786 12:43:11.034023 RX DQS gating : PASS
4787 12:43:11.037570 RX DQ/DQS(RDDQC) : PASS
4788 12:43:11.037650 TX DQ/DQS : PASS
4789 12:43:11.040779 RX DATLAT : PASS
4790 12:43:11.044130 RX DQ/DQS(Engine): PASS
4791 12:43:11.044211 TX OE : NO K
4792 12:43:11.047246 All Pass.
4793 12:43:11.047327
4794 12:43:11.047389 CH 0, Rank 1
4795 12:43:11.050847 SW Impedance : PASS
4796 12:43:11.050928 DUTY Scan : NO K
4797 12:43:11.054210 ZQ Calibration : PASS
4798 12:43:11.056979 Jitter Meter : NO K
4799 12:43:11.057060 CBT Training : PASS
4800 12:43:11.060459 Write leveling : PASS
4801 12:43:11.063895 RX DQS gating : PASS
4802 12:43:11.063976 RX DQ/DQS(RDDQC) : PASS
4803 12:43:11.067265 TX DQ/DQS : PASS
4804 12:43:11.070645 RX DATLAT : PASS
4805 12:43:11.070726 RX DQ/DQS(Engine): PASS
4806 12:43:11.074029 TX OE : NO K
4807 12:43:11.074106 All Pass.
4808 12:43:11.074168
4809 12:43:11.076789 CH 1, Rank 0
4810 12:43:11.076869 SW Impedance : PASS
4811 12:43:11.080359 DUTY Scan : NO K
4812 12:43:11.083919 ZQ Calibration : PASS
4813 12:43:11.084000 Jitter Meter : NO K
4814 12:43:11.086763 CBT Training : PASS
4815 12:43:11.090125 Write leveling : PASS
4816 12:43:11.090206 RX DQS gating : PASS
4817 12:43:11.093530 RX DQ/DQS(RDDQC) : PASS
4818 12:43:11.093611 TX DQ/DQS : PASS
4819 12:43:11.096716 RX DATLAT : PASS
4820 12:43:11.099988 RX DQ/DQS(Engine): PASS
4821 12:43:11.100084 TX OE : NO K
4822 12:43:11.103707 All Pass.
4823 12:43:11.103787
4824 12:43:11.103851 CH 1, Rank 1
4825 12:43:11.106841 SW Impedance : PASS
4826 12:43:11.106922 DUTY Scan : NO K
4827 12:43:11.110224 ZQ Calibration : PASS
4828 12:43:11.113264 Jitter Meter : NO K
4829 12:43:11.113345 CBT Training : PASS
4830 12:43:11.116730 Write leveling : PASS
4831 12:43:11.120009 RX DQS gating : PASS
4832 12:43:11.120089 RX DQ/DQS(RDDQC) : PASS
4833 12:43:11.123439 TX DQ/DQS : PASS
4834 12:43:11.126892 RX DATLAT : PASS
4835 12:43:11.126972 RX DQ/DQS(Engine): PASS
4836 12:43:11.130270 TX OE : NO K
4837 12:43:11.130353 All Pass.
4838 12:43:11.130417
4839 12:43:11.133463 DramC Write-DBI off
4840 12:43:11.136700 PER_BANK_REFRESH: Hybrid Mode
4841 12:43:11.136854 TX_TRACKING: ON
4842 12:43:11.146993 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4843 12:43:11.150388 [FAST_K] Save calibration result to emmc
4844 12:43:11.153085 dramc_set_vcore_voltage set vcore to 662500
4845 12:43:11.156926 Read voltage for 933, 3
4846 12:43:11.157007 Vio18 = 0
4847 12:43:11.157071 Vcore = 662500
4848 12:43:11.159871 Vdram = 0
4849 12:43:11.159952 Vddq = 0
4850 12:43:11.160016 Vmddr = 0
4851 12:43:11.166872 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4852 12:43:11.174353 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4853 12:43:11.174436 MEM_TYPE=3, freq_sel=17
4854 12:43:11.176320 sv_algorithm_assistance_LP4_1600
4855 12:43:11.179790 ============ PULL DRAM RESETB DOWN ============
4856 12:43:11.183265 ========== PULL DRAM RESETB DOWN end =========
4857 12:43:11.190107 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4858 12:43:11.193425 ===================================
4859 12:43:11.193506 LPDDR4 DRAM CONFIGURATION
4860 12:43:11.196320 ===================================
4861 12:43:11.199696 EX_ROW_EN[0] = 0x0
4862 12:43:11.203078 EX_ROW_EN[1] = 0x0
4863 12:43:11.203159 LP4Y_EN = 0x0
4864 12:43:11.206614 WORK_FSP = 0x0
4865 12:43:11.206694 WL = 0x3
4866 12:43:11.209801 RL = 0x3
4867 12:43:11.209884 BL = 0x2
4868 12:43:11.213052 RPST = 0x0
4869 12:43:11.213133 RD_PRE = 0x0
4870 12:43:11.216482 WR_PRE = 0x1
4871 12:43:11.216563 WR_PST = 0x0
4872 12:43:11.219788 DBI_WR = 0x0
4873 12:43:11.219868 DBI_RD = 0x0
4874 12:43:11.222791 OTF = 0x1
4875 12:43:11.226496 ===================================
4876 12:43:11.229529 ===================================
4877 12:43:11.229610 ANA top config
4878 12:43:11.232745 ===================================
4879 12:43:11.236041 DLL_ASYNC_EN = 0
4880 12:43:11.239474 ALL_SLAVE_EN = 1
4881 12:43:11.242721 NEW_RANK_MODE = 1
4882 12:43:11.242841 DLL_IDLE_MODE = 1
4883 12:43:11.245968 LP45_APHY_COMB_EN = 1
4884 12:43:11.249316 TX_ODT_DIS = 1
4885 12:43:11.253132 NEW_8X_MODE = 1
4886 12:43:11.256140 ===================================
4887 12:43:11.259341 ===================================
4888 12:43:11.262834 data_rate = 1866
4889 12:43:11.262915 CKR = 1
4890 12:43:11.266003 DQ_P2S_RATIO = 8
4891 12:43:11.269756 ===================================
4892 12:43:11.272760 CA_P2S_RATIO = 8
4893 12:43:11.276241 DQ_CA_OPEN = 0
4894 12:43:11.279509 DQ_SEMI_OPEN = 0
4895 12:43:11.282856 CA_SEMI_OPEN = 0
4896 12:43:11.282981 CA_FULL_RATE = 0
4897 12:43:11.286337 DQ_CKDIV4_EN = 1
4898 12:43:11.289136 CA_CKDIV4_EN = 1
4899 12:43:11.292639 CA_PREDIV_EN = 0
4900 12:43:11.296218 PH8_DLY = 0
4901 12:43:11.296381 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4902 12:43:11.299581 DQ_AAMCK_DIV = 4
4903 12:43:11.302858 CA_AAMCK_DIV = 4
4904 12:43:11.306172 CA_ADMCK_DIV = 4
4905 12:43:11.309593 DQ_TRACK_CA_EN = 0
4906 12:43:11.312410 CA_PICK = 933
4907 12:43:11.315874 CA_MCKIO = 933
4908 12:43:11.315997 MCKIO_SEMI = 0
4909 12:43:11.319242 PLL_FREQ = 3732
4910 12:43:11.322709 DQ_UI_PI_RATIO = 32
4911 12:43:11.326155 CA_UI_PI_RATIO = 0
4912 12:43:11.329015 ===================================
4913 12:43:11.332326 ===================================
4914 12:43:11.336145 memory_type:LPDDR4
4915 12:43:11.336293 GP_NUM : 10
4916 12:43:11.339321 SRAM_EN : 1
4917 12:43:11.342362 MD32_EN : 0
4918 12:43:11.346135 ===================================
4919 12:43:11.346233 [ANA_INIT] >>>>>>>>>>>>>>
4920 12:43:11.349576 <<<<<< [CONFIGURE PHASE]: ANA_TX
4921 12:43:11.352658 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4922 12:43:11.356140 ===================================
4923 12:43:11.359471 data_rate = 1866,PCW = 0X8f00
4924 12:43:11.362675 ===================================
4925 12:43:11.365825 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4926 12:43:11.372270 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4927 12:43:11.375665 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4928 12:43:11.382475 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4929 12:43:11.385996 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4930 12:43:11.389118 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4931 12:43:11.389202 [ANA_INIT] flow start
4932 12:43:11.392503 [ANA_INIT] PLL >>>>>>>>
4933 12:43:11.395975 [ANA_INIT] PLL <<<<<<<<
4934 12:43:11.396056 [ANA_INIT] MIDPI >>>>>>>>
4935 12:43:11.399391 [ANA_INIT] MIDPI <<<<<<<<
4936 12:43:11.402077 [ANA_INIT] DLL >>>>>>>>
4937 12:43:11.402159 [ANA_INIT] flow end
4938 12:43:11.408871 ============ LP4 DIFF to SE enter ============
4939 12:43:11.412196 ============ LP4 DIFF to SE exit ============
4940 12:43:11.415760 [ANA_INIT] <<<<<<<<<<<<<
4941 12:43:11.418559 [Flow] Enable top DCM control >>>>>
4942 12:43:11.422503 [Flow] Enable top DCM control <<<<<
4943 12:43:11.422589 Enable DLL master slave shuffle
4944 12:43:11.428687 ==============================================================
4945 12:43:11.432097 Gating Mode config
4946 12:43:11.435532 ==============================================================
4947 12:43:11.439078 Config description:
4948 12:43:11.448910 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4949 12:43:11.455765 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4950 12:43:11.458806 SELPH_MODE 0: By rank 1: By Phase
4951 12:43:11.465820 ==============================================================
4952 12:43:11.469123 GAT_TRACK_EN = 1
4953 12:43:11.472113 RX_GATING_MODE = 2
4954 12:43:11.475447 RX_GATING_TRACK_MODE = 2
4955 12:43:11.479146 SELPH_MODE = 1
4956 12:43:11.479297 PICG_EARLY_EN = 1
4957 12:43:11.482158 VALID_LAT_VALUE = 1
4958 12:43:11.488480 ==============================================================
4959 12:43:11.491688 Enter into Gating configuration >>>>
4960 12:43:11.495456 Exit from Gating configuration <<<<
4961 12:43:11.498469 Enter into DVFS_PRE_config >>>>>
4962 12:43:11.508245 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4963 12:43:11.511791 Exit from DVFS_PRE_config <<<<<
4964 12:43:11.515216 Enter into PICG configuration >>>>
4965 12:43:11.518714 Exit from PICG configuration <<<<
4966 12:43:11.522126 [RX_INPUT] configuration >>>>>
4967 12:43:11.525363 [RX_INPUT] configuration <<<<<
4968 12:43:11.528164 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4969 12:43:11.534989 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4970 12:43:11.541849 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4971 12:43:11.548167 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4972 12:43:11.554775 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4973 12:43:11.561439 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4974 12:43:11.565280 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4975 12:43:11.568471 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4976 12:43:11.571756 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4977 12:43:11.575101 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4978 12:43:11.581707 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4979 12:43:11.585088 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4980 12:43:11.588365 ===================================
4981 12:43:11.591560 LPDDR4 DRAM CONFIGURATION
4982 12:43:11.595011 ===================================
4983 12:43:11.595093 EX_ROW_EN[0] = 0x0
4984 12:43:11.598389 EX_ROW_EN[1] = 0x0
4985 12:43:11.598471 LP4Y_EN = 0x0
4986 12:43:11.601856 WORK_FSP = 0x0
4987 12:43:11.601938 WL = 0x3
4988 12:43:11.604703 RL = 0x3
4989 12:43:11.604785 BL = 0x2
4990 12:43:11.607835 RPST = 0x0
4991 12:43:11.611728 RD_PRE = 0x0
4992 12:43:11.611809 WR_PRE = 0x1
4993 12:43:11.614751 WR_PST = 0x0
4994 12:43:11.614834 DBI_WR = 0x0
4995 12:43:11.617795 DBI_RD = 0x0
4996 12:43:11.617877 OTF = 0x1
4997 12:43:11.621600 ===================================
4998 12:43:11.624496 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4999 12:43:11.628051 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5000 12:43:11.634880 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5001 12:43:11.638257 ===================================
5002 12:43:11.641690 LPDDR4 DRAM CONFIGURATION
5003 12:43:11.645202 ===================================
5004 12:43:11.645284 EX_ROW_EN[0] = 0x10
5005 12:43:11.647894 EX_ROW_EN[1] = 0x0
5006 12:43:11.647975 LP4Y_EN = 0x0
5007 12:43:11.651462 WORK_FSP = 0x0
5008 12:43:11.651542 WL = 0x3
5009 12:43:11.654815 RL = 0x3
5010 12:43:11.654896 BL = 0x2
5011 12:43:11.658176 RPST = 0x0
5012 12:43:11.658258 RD_PRE = 0x0
5013 12:43:11.661563 WR_PRE = 0x1
5014 12:43:11.661644 WR_PST = 0x0
5015 12:43:11.665037 DBI_WR = 0x0
5016 12:43:11.665118 DBI_RD = 0x0
5017 12:43:11.668446 OTF = 0x1
5018 12:43:11.672002 ===================================
5019 12:43:11.678219 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5020 12:43:11.681624 nWR fixed to 30
5021 12:43:11.684712 [ModeRegInit_LP4] CH0 RK0
5022 12:43:11.684797 [ModeRegInit_LP4] CH0 RK1
5023 12:43:11.688112 [ModeRegInit_LP4] CH1 RK0
5024 12:43:11.691577 [ModeRegInit_LP4] CH1 RK1
5025 12:43:11.691658 match AC timing 9
5026 12:43:11.698080 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5027 12:43:11.701237 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5028 12:43:11.704474 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5029 12:43:11.711170 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5030 12:43:11.714673 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5031 12:43:11.714758 ==
5032 12:43:11.718344 Dram Type= 6, Freq= 0, CH_0, rank 0
5033 12:43:11.721428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5034 12:43:11.721504 ==
5035 12:43:11.727659 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5036 12:43:11.734745 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5037 12:43:11.737930 [CA 0] Center 37 (6~68) winsize 63
5038 12:43:11.740955 [CA 1] Center 37 (7~68) winsize 62
5039 12:43:11.744491 [CA 2] Center 34 (4~65) winsize 62
5040 12:43:11.747790 [CA 3] Center 34 (3~65) winsize 63
5041 12:43:11.751012 [CA 4] Center 33 (3~64) winsize 62
5042 12:43:11.754488 [CA 5] Center 32 (2~62) winsize 61
5043 12:43:11.754570
5044 12:43:11.757963 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5045 12:43:11.758044
5046 12:43:11.761414 [CATrainingPosCal] consider 1 rank data
5047 12:43:11.764750 u2DelayCellTimex100 = 270/100 ps
5048 12:43:11.767489 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5049 12:43:11.770797 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5050 12:43:11.774283 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5051 12:43:11.777759 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5052 12:43:11.780993 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5053 12:43:11.784238 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5054 12:43:11.784380
5055 12:43:11.791364 CA PerBit enable=1, Macro0, CA PI delay=32
5056 12:43:11.791477
5057 12:43:11.794645 [CBTSetCACLKResult] CA Dly = 32
5058 12:43:11.794747 CS Dly: 5 (0~36)
5059 12:43:11.794839 ==
5060 12:43:11.797907 Dram Type= 6, Freq= 0, CH_0, rank 1
5061 12:43:11.801315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5062 12:43:11.801426 ==
5063 12:43:11.807892 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5064 12:43:11.814653 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5065 12:43:11.817766 [CA 0] Center 37 (6~68) winsize 63
5066 12:43:11.821211 [CA 1] Center 37 (7~68) winsize 62
5067 12:43:11.824423 [CA 2] Center 34 (4~65) winsize 62
5068 12:43:11.827768 [CA 3] Center 34 (3~65) winsize 63
5069 12:43:11.831200 [CA 4] Center 32 (2~63) winsize 62
5070 12:43:11.833931 [CA 5] Center 32 (2~62) winsize 61
5071 12:43:11.834004
5072 12:43:11.837386 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5073 12:43:11.837455
5074 12:43:11.840760 [CATrainingPosCal] consider 2 rank data
5075 12:43:11.844066 u2DelayCellTimex100 = 270/100 ps
5076 12:43:11.847507 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5077 12:43:11.850879 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5078 12:43:11.854124 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5079 12:43:11.857177 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5080 12:43:11.860754 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5081 12:43:11.867132 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5082 12:43:11.867243
5083 12:43:11.870444 CA PerBit enable=1, Macro0, CA PI delay=32
5084 12:43:11.870543
5085 12:43:11.873830 [CBTSetCACLKResult] CA Dly = 32
5086 12:43:11.873931 CS Dly: 5 (0~37)
5087 12:43:11.874075
5088 12:43:11.877458 ----->DramcWriteLeveling(PI) begin...
5089 12:43:11.877564 ==
5090 12:43:11.880293 Dram Type= 6, Freq= 0, CH_0, rank 0
5091 12:43:11.887014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5092 12:43:11.887126 ==
5093 12:43:11.890421 Write leveling (Byte 0): 33 => 33
5094 12:43:11.890533 Write leveling (Byte 1): 30 => 30
5095 12:43:11.893875 DramcWriteLeveling(PI) end<-----
5096 12:43:11.893976
5097 12:43:11.894071 ==
5098 12:43:11.897164 Dram Type= 6, Freq= 0, CH_0, rank 0
5099 12:43:11.904022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5100 12:43:11.904124 ==
5101 12:43:11.907272 [Gating] SW mode calibration
5102 12:43:11.913781 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5103 12:43:11.917612 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5104 12:43:11.924144 0 14 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5105 12:43:11.927333 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 12:43:11.930412 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 12:43:11.937259 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 12:43:11.940669 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 12:43:11.943897 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 12:43:11.950608 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5111 12:43:11.953413 0 14 28 | B1->B0 | 3333 2a2a | 0 0 | (0 0) (0 0)
5112 12:43:11.956907 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
5113 12:43:11.963905 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 12:43:11.966973 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 12:43:11.970093 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 12:43:11.976797 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 12:43:11.980174 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 12:43:11.983510 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5119 12:43:11.987039 0 15 28 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (1 1)
5120 12:43:11.993637 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
5121 12:43:11.997072 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 12:43:12.000488 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 12:43:12.006756 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 12:43:12.010044 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 12:43:12.013208 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 12:43:12.019935 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 12:43:12.023724 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5128 12:43:12.026825 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 12:43:12.033736 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 12:43:12.036836 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 12:43:12.040049 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 12:43:12.046648 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 12:43:12.049978 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 12:43:12.053255 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 12:43:12.060165 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 12:43:12.063673 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 12:43:12.067102 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 12:43:12.073594 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 12:43:12.077028 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 12:43:12.079982 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 12:43:12.086889 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 12:43:12.089937 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5143 12:43:12.093586 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5144 12:43:12.096447 Total UI for P1: 0, mck2ui 16
5145 12:43:12.100108 best dqsien dly found for B0: ( 1, 2, 24)
5146 12:43:12.103379 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 12:43:12.106892 Total UI for P1: 0, mck2ui 16
5148 12:43:12.109782 best dqsien dly found for B1: ( 1, 2, 28)
5149 12:43:12.113146 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5150 12:43:12.116509 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5151 12:43:12.119806
5152 12:43:12.123196 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5153 12:43:12.126936 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5154 12:43:12.130543 [Gating] SW calibration Done
5155 12:43:12.130622 ==
5156 12:43:12.133515 Dram Type= 6, Freq= 0, CH_0, rank 0
5157 12:43:12.136630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5158 12:43:12.136701 ==
5159 12:43:12.136765 RX Vref Scan: 0
5160 12:43:12.136852
5161 12:43:12.139840 RX Vref 0 -> 0, step: 1
5162 12:43:12.139935
5163 12:43:12.142962 RX Delay -80 -> 252, step: 8
5164 12:43:12.146799 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5165 12:43:12.149990 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5166 12:43:12.156532 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5167 12:43:12.159417 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5168 12:43:12.163062 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5169 12:43:12.166241 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5170 12:43:12.169757 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5171 12:43:12.173087 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5172 12:43:12.180063 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5173 12:43:12.182887 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5174 12:43:12.186365 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5175 12:43:12.189841 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5176 12:43:12.193178 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5177 12:43:12.196538 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5178 12:43:12.202999 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5179 12:43:12.206647 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5180 12:43:12.206745 ==
5181 12:43:12.209744 Dram Type= 6, Freq= 0, CH_0, rank 0
5182 12:43:12.212945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5183 12:43:12.213046 ==
5184 12:43:12.216396 DQS Delay:
5185 12:43:12.216493 DQS0 = 0, DQS1 = 0
5186 12:43:12.216581 DQM Delay:
5187 12:43:12.219938 DQM0 = 104, DQM1 = 94
5188 12:43:12.220031 DQ Delay:
5189 12:43:12.223283 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5190 12:43:12.226476 DQ4 =103, DQ5 =91, DQ6 =115, DQ7 =115
5191 12:43:12.229313 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5192 12:43:12.232751 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5193 12:43:12.232852
5194 12:43:12.232941
5195 12:43:12.236228 ==
5196 12:43:12.236327 Dram Type= 6, Freq= 0, CH_0, rank 0
5197 12:43:12.242981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5198 12:43:12.243083 ==
5199 12:43:12.243177
5200 12:43:12.243264
5201 12:43:12.246408 TX Vref Scan disable
5202 12:43:12.246511 == TX Byte 0 ==
5203 12:43:12.249740 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5204 12:43:12.255859 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5205 12:43:12.255971 == TX Byte 1 ==
5206 12:43:12.259305 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5207 12:43:12.266160 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5208 12:43:12.266271 ==
5209 12:43:12.269442 Dram Type= 6, Freq= 0, CH_0, rank 0
5210 12:43:12.273169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5211 12:43:12.273265 ==
5212 12:43:12.273365
5213 12:43:12.273451
5214 12:43:12.276216 TX Vref Scan disable
5215 12:43:12.279744 == TX Byte 0 ==
5216 12:43:12.283141 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5217 12:43:12.286073 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5218 12:43:12.289626 == TX Byte 1 ==
5219 12:43:12.292938 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5220 12:43:12.296334 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5221 12:43:12.296428
5222 12:43:12.296494 [DATLAT]
5223 12:43:12.299747 Freq=933, CH0 RK0
5224 12:43:12.299842
5225 12:43:12.302617 DATLAT Default: 0xd
5226 12:43:12.302712 0, 0xFFFF, sum = 0
5227 12:43:12.306125 1, 0xFFFF, sum = 0
5228 12:43:12.306226 2, 0xFFFF, sum = 0
5229 12:43:12.309507 3, 0xFFFF, sum = 0
5230 12:43:12.309605 4, 0xFFFF, sum = 0
5231 12:43:12.312901 5, 0xFFFF, sum = 0
5232 12:43:12.313000 6, 0xFFFF, sum = 0
5233 12:43:12.315934 7, 0xFFFF, sum = 0
5234 12:43:12.316032 8, 0xFFFF, sum = 0
5235 12:43:12.318975 9, 0xFFFF, sum = 0
5236 12:43:12.319069 10, 0x0, sum = 1
5237 12:43:12.322472 11, 0x0, sum = 2
5238 12:43:12.322566 12, 0x0, sum = 3
5239 12:43:12.326210 13, 0x0, sum = 4
5240 12:43:12.326307 best_step = 11
5241 12:43:12.326395
5242 12:43:12.326482 ==
5243 12:43:12.329468 Dram Type= 6, Freq= 0, CH_0, rank 0
5244 12:43:12.332709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5245 12:43:12.336009 ==
5246 12:43:12.336104 RX Vref Scan: 1
5247 12:43:12.336204
5248 12:43:12.339489 RX Vref 0 -> 0, step: 1
5249 12:43:12.339592
5250 12:43:12.342307 RX Delay -53 -> 252, step: 4
5251 12:43:12.342403
5252 12:43:12.342491 Set Vref, RX VrefLevel [Byte0]: 56
5253 12:43:12.345827 [Byte1]: 49
5254 12:43:12.351023
5255 12:43:12.351122 Final RX Vref Byte 0 = 56 to rank0
5256 12:43:12.354063 Final RX Vref Byte 1 = 49 to rank0
5257 12:43:12.357331 Final RX Vref Byte 0 = 56 to rank1
5258 12:43:12.360872 Final RX Vref Byte 1 = 49 to rank1==
5259 12:43:12.364223 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 12:43:12.371133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 12:43:12.371243 ==
5262 12:43:12.371335 DQS Delay:
5263 12:43:12.371422 DQS0 = 0, DQS1 = 0
5264 12:43:12.374570 DQM Delay:
5265 12:43:12.374673 DQM0 = 104, DQM1 = 94
5266 12:43:12.377428 DQ Delay:
5267 12:43:12.380852 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5268 12:43:12.384122 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =110
5269 12:43:12.387488 DQ8 =82, DQ9 =84, DQ10 =94, DQ11 =90
5270 12:43:12.390634 DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =102
5271 12:43:12.390735
5272 12:43:12.390826
5273 12:43:12.397470 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f26, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 407 ps
5274 12:43:12.400454 CH0 RK0: MR19=505, MR18=2F26
5275 12:43:12.407081 CH0_RK0: MR19=0x505, MR18=0x2F26, DQSOSC=407, MR23=63, INC=65, DEC=43
5276 12:43:12.407182
5277 12:43:12.410714 ----->DramcWriteLeveling(PI) begin...
5278 12:43:12.410790 ==
5279 12:43:12.413843 Dram Type= 6, Freq= 0, CH_0, rank 1
5280 12:43:12.417165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5281 12:43:12.417264 ==
5282 12:43:12.420665 Write leveling (Byte 0): 32 => 32
5283 12:43:12.424148 Write leveling (Byte 1): 31 => 31
5284 12:43:12.427332 DramcWriteLeveling(PI) end<-----
5285 12:43:12.427425
5286 12:43:12.427516 ==
5287 12:43:12.430394 Dram Type= 6, Freq= 0, CH_0, rank 1
5288 12:43:12.437140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5289 12:43:12.437237 ==
5290 12:43:12.437305 [Gating] SW mode calibration
5291 12:43:12.446571 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5292 12:43:12.450067 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5293 12:43:12.456959 0 14 0 | B1->B0 | 3333 3232 | 1 1 | (1 1) (1 1)
5294 12:43:12.460165 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 12:43:12.463504 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 12:43:12.470187 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 12:43:12.473673 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 12:43:12.477208 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 12:43:12.480648 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 12:43:12.486683 0 14 28 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (1 0)
5301 12:43:12.490202 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5302 12:43:12.493706 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 12:43:12.500495 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 12:43:12.503719 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 12:43:12.506881 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 12:43:12.513356 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 12:43:12.516704 0 15 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5308 12:43:12.519898 0 15 28 | B1->B0 | 3939 3434 | 0 0 | (1 1) (1 1)
5309 12:43:12.526722 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 12:43:12.530153 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 12:43:12.533520 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 12:43:12.540146 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 12:43:12.543261 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 12:43:12.547007 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 12:43:12.553261 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 12:43:12.557162 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5317 12:43:12.560096 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 12:43:12.566924 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 12:43:12.570109 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 12:43:12.573366 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 12:43:12.576850 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 12:43:12.583097 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 12:43:12.586618 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 12:43:12.589956 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 12:43:12.596839 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 12:43:12.599670 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 12:43:12.603177 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 12:43:12.610037 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 12:43:12.613292 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 12:43:12.616304 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 12:43:12.622880 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 12:43:12.626318 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5333 12:43:12.629747 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5334 12:43:12.633094 Total UI for P1: 0, mck2ui 16
5335 12:43:12.636291 best dqsien dly found for B0: ( 1, 2, 28)
5336 12:43:12.643075 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 12:43:12.643177 Total UI for P1: 0, mck2ui 16
5338 12:43:12.649854 best dqsien dly found for B1: ( 1, 2, 30)
5339 12:43:12.653156 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5340 12:43:12.656447 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5341 12:43:12.656529
5342 12:43:12.659708 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5343 12:43:12.663153 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5344 12:43:12.666353 [Gating] SW calibration Done
5345 12:43:12.666434 ==
5346 12:43:12.669699 Dram Type= 6, Freq= 0, CH_0, rank 1
5347 12:43:12.672600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5348 12:43:12.672683 ==
5349 12:43:12.676183 RX Vref Scan: 0
5350 12:43:12.676264
5351 12:43:12.676370 RX Vref 0 -> 0, step: 1
5352 12:43:12.676431
5353 12:43:12.679733 RX Delay -80 -> 252, step: 8
5354 12:43:12.682801 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5355 12:43:12.689642 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5356 12:43:12.693093 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5357 12:43:12.695833 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5358 12:43:12.699807 iDelay=208, Bit 4, Center 111 (24 ~ 199) 176
5359 12:43:12.702610 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5360 12:43:12.709635 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5361 12:43:12.713034 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5362 12:43:12.715806 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5363 12:43:12.719204 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5364 12:43:12.723059 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5365 12:43:12.726013 iDelay=208, Bit 11, Center 91 (8 ~ 175) 168
5366 12:43:12.732909 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5367 12:43:12.735724 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5368 12:43:12.739178 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5369 12:43:12.742675 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5370 12:43:12.742756 ==
5371 12:43:12.745943 Dram Type= 6, Freq= 0, CH_0, rank 1
5372 12:43:12.749276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5373 12:43:12.752565 ==
5374 12:43:12.752653 DQS Delay:
5375 12:43:12.752719 DQS0 = 0, DQS1 = 0
5376 12:43:12.755690 DQM Delay:
5377 12:43:12.755772 DQM0 = 106, DQM1 = 94
5378 12:43:12.759449 DQ Delay:
5379 12:43:12.762472 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5380 12:43:12.766045 DQ4 =111, DQ5 =99, DQ6 =111, DQ7 =115
5381 12:43:12.769122 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5382 12:43:12.772254 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5383 12:43:12.772376
5384 12:43:12.772440
5385 12:43:12.772498 ==
5386 12:43:12.775564 Dram Type= 6, Freq= 0, CH_0, rank 1
5387 12:43:12.779065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5388 12:43:12.779147 ==
5389 12:43:12.779211
5390 12:43:12.779270
5391 12:43:12.782376 TX Vref Scan disable
5392 12:43:12.782457 == TX Byte 0 ==
5393 12:43:12.789410 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5394 12:43:12.792258 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5395 12:43:12.792366 == TX Byte 1 ==
5396 12:43:12.799054 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5397 12:43:12.802307 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5398 12:43:12.802392 ==
5399 12:43:12.805771 Dram Type= 6, Freq= 0, CH_0, rank 1
5400 12:43:12.809124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5401 12:43:12.809206 ==
5402 12:43:12.809270
5403 12:43:12.812668
5404 12:43:12.812749 TX Vref Scan disable
5405 12:43:12.815389 == TX Byte 0 ==
5406 12:43:12.818826 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5407 12:43:12.822346 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5408 12:43:12.825800 == TX Byte 1 ==
5409 12:43:12.828661 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5410 12:43:12.832032 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5411 12:43:12.835324
5412 12:43:12.835405 [DATLAT]
5413 12:43:12.835469 Freq=933, CH0 RK1
5414 12:43:12.835529
5415 12:43:12.839097 DATLAT Default: 0xb
5416 12:43:12.839178 0, 0xFFFF, sum = 0
5417 12:43:12.842239 1, 0xFFFF, sum = 0
5418 12:43:12.842326 2, 0xFFFF, sum = 0
5419 12:43:12.845514 3, 0xFFFF, sum = 0
5420 12:43:12.848987 4, 0xFFFF, sum = 0
5421 12:43:12.849069 5, 0xFFFF, sum = 0
5422 12:43:12.851661 6, 0xFFFF, sum = 0
5423 12:43:12.851743 7, 0xFFFF, sum = 0
5424 12:43:12.855195 8, 0xFFFF, sum = 0
5425 12:43:12.855279 9, 0xFFFF, sum = 0
5426 12:43:12.858677 10, 0x0, sum = 1
5427 12:43:12.858759 11, 0x0, sum = 2
5428 12:43:12.862139 12, 0x0, sum = 3
5429 12:43:12.862221 13, 0x0, sum = 4
5430 12:43:12.862287 best_step = 11
5431 12:43:12.862346
5432 12:43:12.864949 ==
5433 12:43:12.868303 Dram Type= 6, Freq= 0, CH_0, rank 1
5434 12:43:12.871585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5435 12:43:12.871666 ==
5436 12:43:12.871730 RX Vref Scan: 0
5437 12:43:12.871791
5438 12:43:12.875293 RX Vref 0 -> 0, step: 1
5439 12:43:12.875374
5440 12:43:12.878370 RX Delay -53 -> 252, step: 4
5441 12:43:12.882009 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5442 12:43:12.888194 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5443 12:43:12.891872 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5444 12:43:12.895361 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5445 12:43:12.898701 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5446 12:43:12.901926 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5447 12:43:12.908484 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5448 12:43:12.911732 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5449 12:43:12.914827 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5450 12:43:12.918563 iDelay=199, Bit 9, Center 84 (-1 ~ 170) 172
5451 12:43:12.921933 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5452 12:43:12.924735 iDelay=199, Bit 11, Center 86 (3 ~ 170) 168
5453 12:43:12.931724 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5454 12:43:12.935182 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5455 12:43:12.938459 iDelay=199, Bit 14, Center 104 (23 ~ 186) 164
5456 12:43:12.941841 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5457 12:43:12.941943 ==
5458 12:43:12.945166 Dram Type= 6, Freq= 0, CH_0, rank 1
5459 12:43:12.951573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5460 12:43:12.951677 ==
5461 12:43:12.951768 DQS Delay:
5462 12:43:12.954870 DQS0 = 0, DQS1 = 0
5463 12:43:12.954968 DQM Delay:
5464 12:43:12.955065 DQM0 = 105, DQM1 = 94
5465 12:43:12.958167 DQ Delay:
5466 12:43:12.961789 DQ0 =104, DQ1 =108, DQ2 =102, DQ3 =102
5467 12:43:12.964620 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5468 12:43:12.967972 DQ8 =86, DQ9 =84, DQ10 =94, DQ11 =86
5469 12:43:12.971484 DQ12 =98, DQ13 =98, DQ14 =104, DQ15 =102
5470 12:43:12.971566
5471 12:43:12.971630
5472 12:43:12.978443 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c05, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
5473 12:43:12.981734 CH0 RK1: MR19=505, MR18=2C05
5474 12:43:12.987857 CH0_RK1: MR19=0x505, MR18=0x2C05, DQSOSC=408, MR23=63, INC=65, DEC=43
5475 12:43:12.991188 [RxdqsGatingPostProcess] freq 933
5476 12:43:12.998520 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5477 12:43:12.998602 best DQS0 dly(2T, 0.5T) = (0, 10)
5478 12:43:13.001591 best DQS1 dly(2T, 0.5T) = (0, 10)
5479 12:43:13.004753 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5480 12:43:13.008225 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5481 12:43:13.011753 best DQS0 dly(2T, 0.5T) = (0, 10)
5482 12:43:13.014942 best DQS1 dly(2T, 0.5T) = (0, 10)
5483 12:43:13.018098 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5484 12:43:13.021335 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5485 12:43:13.025315 Pre-setting of DQS Precalculation
5486 12:43:13.031342 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5487 12:43:13.031424 ==
5488 12:43:13.034375 Dram Type= 6, Freq= 0, CH_1, rank 0
5489 12:43:13.038133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5490 12:43:13.038215 ==
5491 12:43:13.045008 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5492 12:43:13.047676 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5493 12:43:13.051950 [CA 0] Center 36 (6~67) winsize 62
5494 12:43:13.055032 [CA 1] Center 36 (6~67) winsize 62
5495 12:43:13.058236 [CA 2] Center 34 (4~65) winsize 62
5496 12:43:13.062417 [CA 3] Center 34 (4~65) winsize 62
5497 12:43:13.065109 [CA 4] Center 34 (4~65) winsize 62
5498 12:43:13.068522 [CA 5] Center 33 (3~64) winsize 62
5499 12:43:13.068604
5500 12:43:13.071951 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5501 12:43:13.072033
5502 12:43:13.075334 [CATrainingPosCal] consider 1 rank data
5503 12:43:13.078790 u2DelayCellTimex100 = 270/100 ps
5504 12:43:13.081576 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5505 12:43:13.084852 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5506 12:43:13.091478 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5507 12:43:13.094790 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5508 12:43:13.098126 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5509 12:43:13.101583 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5510 12:43:13.101665
5511 12:43:13.104987 CA PerBit enable=1, Macro0, CA PI delay=33
5512 12:43:13.105068
5513 12:43:13.108230 [CBTSetCACLKResult] CA Dly = 33
5514 12:43:13.108349 CS Dly: 6 (0~37)
5515 12:43:13.111519 ==
5516 12:43:13.111601 Dram Type= 6, Freq= 0, CH_1, rank 1
5517 12:43:13.118408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5518 12:43:13.118491 ==
5519 12:43:13.121799 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5520 12:43:13.128043 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5521 12:43:13.131649 [CA 0] Center 37 (6~68) winsize 63
5522 12:43:13.135527 [CA 1] Center 37 (6~68) winsize 63
5523 12:43:13.138653 [CA 2] Center 35 (4~66) winsize 63
5524 12:43:13.141796 [CA 3] Center 34 (4~65) winsize 62
5525 12:43:13.145169 [CA 4] Center 34 (4~65) winsize 62
5526 12:43:13.148379 [CA 5] Center 34 (4~64) winsize 61
5527 12:43:13.148497
5528 12:43:13.151621 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5529 12:43:13.151703
5530 12:43:13.154834 [CATrainingPosCal] consider 2 rank data
5531 12:43:13.158108 u2DelayCellTimex100 = 270/100 ps
5532 12:43:13.161426 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5533 12:43:13.165360 CA1 delay=36 (6~67),Diff = 2 PI (12 cell)
5534 12:43:13.171633 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
5535 12:43:13.174852 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5536 12:43:13.178390 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5537 12:43:13.181832 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5538 12:43:13.181913
5539 12:43:13.185254 CA PerBit enable=1, Macro0, CA PI delay=34
5540 12:43:13.185335
5541 12:43:13.188713 [CBTSetCACLKResult] CA Dly = 34
5542 12:43:13.188794 CS Dly: 7 (0~39)
5543 12:43:13.188857
5544 12:43:13.192040 ----->DramcWriteLeveling(PI) begin...
5545 12:43:13.195425 ==
5546 12:43:13.195506 Dram Type= 6, Freq= 0, CH_1, rank 0
5547 12:43:13.202167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5548 12:43:13.202249 ==
5549 12:43:13.205607 Write leveling (Byte 0): 27 => 27
5550 12:43:13.208399 Write leveling (Byte 1): 27 => 27
5551 12:43:13.211843 DramcWriteLeveling(PI) end<-----
5552 12:43:13.211924
5553 12:43:13.211987 ==
5554 12:43:13.215366 Dram Type= 6, Freq= 0, CH_1, rank 0
5555 12:43:13.218664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5556 12:43:13.218745 ==
5557 12:43:13.221942 [Gating] SW mode calibration
5558 12:43:13.228189 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5559 12:43:13.231775 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5560 12:43:13.238057 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 12:43:13.241482 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 12:43:13.244830 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 12:43:13.251587 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 12:43:13.255183 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 12:43:13.258675 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5566 12:43:13.264908 0 14 24 | B1->B0 | 3434 2b2b | 1 1 | (1 0) (1 0)
5567 12:43:13.268202 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5568 12:43:13.271736 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 12:43:13.277947 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 12:43:13.281556 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 12:43:13.284905 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 12:43:13.291706 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 12:43:13.295012 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5574 12:43:13.298307 0 15 24 | B1->B0 | 2323 3636 | 1 1 | (0 0) (0 0)
5575 12:43:13.305074 0 15 28 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
5576 12:43:13.308423 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 12:43:13.311650 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 12:43:13.318034 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 12:43:13.321468 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 12:43:13.324955 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 12:43:13.331236 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 12:43:13.334652 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5583 12:43:13.337901 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5584 12:43:13.344608 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 12:43:13.347699 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 12:43:13.351099 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 12:43:13.358090 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 12:43:13.361542 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 12:43:13.364395 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 12:43:13.371314 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 12:43:13.374715 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 12:43:13.377982 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 12:43:13.381103 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 12:43:13.387949 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 12:43:13.391107 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 12:43:13.394680 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 12:43:13.401075 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 12:43:13.404166 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5599 12:43:13.408109 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 12:43:13.410810 Total UI for P1: 0, mck2ui 16
5601 12:43:13.414165 best dqsien dly found for B0: ( 1, 2, 24)
5602 12:43:13.418191 Total UI for P1: 0, mck2ui 16
5603 12:43:13.420935 best dqsien dly found for B1: ( 1, 2, 24)
5604 12:43:13.424505 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5605 12:43:13.427836 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5606 12:43:13.427945
5607 12:43:13.434701 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5608 12:43:13.437469 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5609 12:43:13.440955 [Gating] SW calibration Done
5610 12:43:13.441027 ==
5611 12:43:13.444386 Dram Type= 6, Freq= 0, CH_1, rank 0
5612 12:43:13.447734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5613 12:43:13.447841 ==
5614 12:43:13.447932 RX Vref Scan: 0
5615 12:43:13.448021
5616 12:43:13.451108 RX Vref 0 -> 0, step: 1
5617 12:43:13.451205
5618 12:43:13.454362 RX Delay -80 -> 252, step: 8
5619 12:43:13.457481 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5620 12:43:13.460603 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5621 12:43:13.464488 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5622 12:43:13.470978 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5623 12:43:13.474388 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5624 12:43:13.477211 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5625 12:43:13.480630 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5626 12:43:13.484111 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5627 12:43:13.490781 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5628 12:43:13.493978 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5629 12:43:13.497350 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5630 12:43:13.500863 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5631 12:43:13.503794 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5632 12:43:13.506846 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5633 12:43:13.513745 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5634 12:43:13.516814 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5635 12:43:13.516889 ==
5636 12:43:13.520282 Dram Type= 6, Freq= 0, CH_1, rank 0
5637 12:43:13.523436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5638 12:43:13.523535 ==
5639 12:43:13.526717 DQS Delay:
5640 12:43:13.526825 DQS0 = 0, DQS1 = 0
5641 12:43:13.526915 DQM Delay:
5642 12:43:13.530149 DQM0 = 102, DQM1 = 97
5643 12:43:13.530236 DQ Delay:
5644 12:43:13.533695 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5645 12:43:13.537128 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5646 12:43:13.540649 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5647 12:43:13.543445 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =103
5648 12:43:13.543526
5649 12:43:13.546925
5650 12:43:13.547025 ==
5651 12:43:13.550311 Dram Type= 6, Freq= 0, CH_1, rank 0
5652 12:43:13.553816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5653 12:43:13.553925 ==
5654 12:43:13.554015
5655 12:43:13.554102
5656 12:43:13.557286 TX Vref Scan disable
5657 12:43:13.557376 == TX Byte 0 ==
5658 12:43:13.560719 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5659 12:43:13.567157 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5660 12:43:13.567259 == TX Byte 1 ==
5661 12:43:13.573943 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5662 12:43:13.576804 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5663 12:43:13.576913 ==
5664 12:43:13.580388 Dram Type= 6, Freq= 0, CH_1, rank 0
5665 12:43:13.583743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5666 12:43:13.583853 ==
5667 12:43:13.583944
5668 12:43:13.584039
5669 12:43:13.587144 TX Vref Scan disable
5670 12:43:13.590492 == TX Byte 0 ==
5671 12:43:13.593788 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5672 12:43:13.596992 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5673 12:43:13.600423 == TX Byte 1 ==
5674 12:43:13.603857 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5675 12:43:13.606682 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5676 12:43:13.606764
5677 12:43:13.610457 [DATLAT]
5678 12:43:13.610538 Freq=933, CH1 RK0
5679 12:43:13.610602
5680 12:43:13.613785 DATLAT Default: 0xd
5681 12:43:13.613866 0, 0xFFFF, sum = 0
5682 12:43:13.616685 1, 0xFFFF, sum = 0
5683 12:43:13.616766 2, 0xFFFF, sum = 0
5684 12:43:13.620070 3, 0xFFFF, sum = 0
5685 12:43:13.620151 4, 0xFFFF, sum = 0
5686 12:43:13.623333 5, 0xFFFF, sum = 0
5687 12:43:13.623416 6, 0xFFFF, sum = 0
5688 12:43:13.626455 7, 0xFFFF, sum = 0
5689 12:43:13.626537 8, 0xFFFF, sum = 0
5690 12:43:13.630128 9, 0xFFFF, sum = 0
5691 12:43:13.630210 10, 0x0, sum = 1
5692 12:43:13.633250 11, 0x0, sum = 2
5693 12:43:13.633332 12, 0x0, sum = 3
5694 12:43:13.636407 13, 0x0, sum = 4
5695 12:43:13.636489 best_step = 11
5696 12:43:13.636552
5697 12:43:13.636611 ==
5698 12:43:13.640058 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 12:43:13.643424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 12:43:13.646860 ==
5701 12:43:13.646959 RX Vref Scan: 1
5702 12:43:13.647050
5703 12:43:13.649753 RX Vref 0 -> 0, step: 1
5704 12:43:13.649833
5705 12:43:13.653470 RX Delay -45 -> 252, step: 4
5706 12:43:13.653549
5707 12:43:13.656911 Set Vref, RX VrefLevel [Byte0]: 53
5708 12:43:13.656991 [Byte1]: 54
5709 12:43:13.661824
5710 12:43:13.661903 Final RX Vref Byte 0 = 53 to rank0
5711 12:43:13.665175 Final RX Vref Byte 1 = 54 to rank0
5712 12:43:13.667974 Final RX Vref Byte 0 = 53 to rank1
5713 12:43:13.671458 Final RX Vref Byte 1 = 54 to rank1==
5714 12:43:13.674785 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 12:43:13.681160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 12:43:13.681240 ==
5717 12:43:13.681302 DQS Delay:
5718 12:43:13.685292 DQS0 = 0, DQS1 = 0
5719 12:43:13.685371 DQM Delay:
5720 12:43:13.685434 DQM0 = 103, DQM1 = 99
5721 12:43:13.688452 DQ Delay:
5722 12:43:13.691478 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5723 12:43:13.694496 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =102
5724 12:43:13.698011 DQ8 =90, DQ9 =92, DQ10 =98, DQ11 =94
5725 12:43:13.701158 DQ12 =106, DQ13 =106, DQ14 =106, DQ15 =106
5726 12:43:13.701238
5727 12:43:13.701300
5728 12:43:13.707910 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5729 12:43:13.711373 CH1 RK0: MR19=505, MR18=1A32
5730 12:43:13.718124 CH1_RK0: MR19=0x505, MR18=0x1A32, DQSOSC=406, MR23=63, INC=65, DEC=43
5731 12:43:13.718214
5732 12:43:13.721148 ----->DramcWriteLeveling(PI) begin...
5733 12:43:13.721248 ==
5734 12:43:13.724691 Dram Type= 6, Freq= 0, CH_1, rank 1
5735 12:43:13.728066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5736 12:43:13.728161 ==
5737 12:43:13.731481 Write leveling (Byte 0): 28 => 28
5738 12:43:13.734801 Write leveling (Byte 1): 28 => 28
5739 12:43:13.738136 DramcWriteLeveling(PI) end<-----
5740 12:43:13.738236
5741 12:43:13.738327 ==
5742 12:43:13.741355 Dram Type= 6, Freq= 0, CH_1, rank 1
5743 12:43:13.747657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5744 12:43:13.747758 ==
5745 12:43:13.747861 [Gating] SW mode calibration
5746 12:43:13.757655 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5747 12:43:13.761104 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5748 12:43:13.764568 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 12:43:13.771405 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 12:43:13.774804 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 12:43:13.778241 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 12:43:13.785075 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 12:43:13.787764 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 12:43:13.791343 0 14 24 | B1->B0 | 2d2d 3232 | 0 0 | (0 1) (0 0)
5755 12:43:13.797619 0 14 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5756 12:43:13.801130 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 12:43:13.804463 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 12:43:13.811013 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 12:43:13.814647 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 12:43:13.817691 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 12:43:13.824865 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 12:43:13.828232 0 15 24 | B1->B0 | 3535 2727 | 0 0 | (0 0) (0 0)
5763 12:43:13.831640 0 15 28 | B1->B0 | 4646 3e3e | 0 0 | (0 0) (1 1)
5764 12:43:13.835100 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 12:43:13.841681 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 12:43:13.844474 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 12:43:13.847939 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 12:43:13.854508 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 12:43:13.857839 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5770 12:43:13.861100 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5771 12:43:13.867860 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 12:43:13.871325 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 12:43:13.874739 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 12:43:13.881614 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 12:43:13.884322 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 12:43:13.887681 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 12:43:13.894445 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 12:43:13.897909 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 12:43:13.901404 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 12:43:13.907519 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 12:43:13.910986 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 12:43:13.914481 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 12:43:13.921196 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 12:43:13.924493 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 12:43:13.927480 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 12:43:13.934134 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5787 12:43:13.937169 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5788 12:43:13.940823 Total UI for P1: 0, mck2ui 16
5789 12:43:13.944177 best dqsien dly found for B1: ( 1, 2, 24)
5790 12:43:13.947253 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5791 12:43:13.953722 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 12:43:13.953805 Total UI for P1: 0, mck2ui 16
5793 12:43:13.960857 best dqsien dly found for B0: ( 1, 2, 30)
5794 12:43:13.963691 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5795 12:43:13.966993 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5796 12:43:13.967085
5797 12:43:13.970935 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5798 12:43:13.973736 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5799 12:43:13.977277 [Gating] SW calibration Done
5800 12:43:13.977359 ==
5801 12:43:13.980653 Dram Type= 6, Freq= 0, CH_1, rank 1
5802 12:43:13.984165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5803 12:43:13.984248 ==
5804 12:43:13.987000 RX Vref Scan: 0
5805 12:43:13.987082
5806 12:43:13.987165 RX Vref 0 -> 0, step: 1
5807 12:43:13.987243
5808 12:43:13.990401 RX Delay -80 -> 252, step: 8
5809 12:43:13.993726 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5810 12:43:14.000200 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5811 12:43:14.003626 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5812 12:43:14.007020 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5813 12:43:14.010334 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5814 12:43:14.013912 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5815 12:43:14.017416 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5816 12:43:14.023370 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5817 12:43:14.026734 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5818 12:43:14.030164 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5819 12:43:14.033599 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5820 12:43:14.036935 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5821 12:43:14.040189 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5822 12:43:14.047080 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5823 12:43:14.050249 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5824 12:43:14.053439 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5825 12:43:14.053521 ==
5826 12:43:14.057070 Dram Type= 6, Freq= 0, CH_1, rank 1
5827 12:43:14.060114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5828 12:43:14.060242 ==
5829 12:43:14.063627 DQS Delay:
5830 12:43:14.063705 DQS0 = 0, DQS1 = 0
5831 12:43:14.067019 DQM Delay:
5832 12:43:14.067119 DQM0 = 102, DQM1 = 98
5833 12:43:14.067210 DQ Delay:
5834 12:43:14.070357 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =95
5835 12:43:14.073330 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5836 12:43:14.076840 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5837 12:43:14.080076 DQ12 =107, DQ13 =107, DQ14 =99, DQ15 =107
5838 12:43:14.083382
5839 12:43:14.083454
5840 12:43:14.083519 ==
5841 12:43:14.086960 Dram Type= 6, Freq= 0, CH_1, rank 1
5842 12:43:14.090282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5843 12:43:14.090396 ==
5844 12:43:14.090492
5845 12:43:14.090578
5846 12:43:14.093751 TX Vref Scan disable
5847 12:43:14.093847 == TX Byte 0 ==
5848 12:43:14.099737 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5849 12:43:14.103598 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5850 12:43:14.103694 == TX Byte 1 ==
5851 12:43:14.109718 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5852 12:43:14.113101 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5853 12:43:14.113201 ==
5854 12:43:14.116630 Dram Type= 6, Freq= 0, CH_1, rank 1
5855 12:43:14.120172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5856 12:43:14.120266 ==
5857 12:43:14.120379
5858 12:43:14.120438
5859 12:43:14.122873 TX Vref Scan disable
5860 12:43:14.126433 == TX Byte 0 ==
5861 12:43:14.129859 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5862 12:43:14.133205 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5863 12:43:14.136733 == TX Byte 1 ==
5864 12:43:14.140249 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5865 12:43:14.142970 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5866 12:43:14.143062
5867 12:43:14.146428 [DATLAT]
5868 12:43:14.146525 Freq=933, CH1 RK1
5869 12:43:14.146617
5870 12:43:14.149779 DATLAT Default: 0xb
5871 12:43:14.149874 0, 0xFFFF, sum = 0
5872 12:43:14.153069 1, 0xFFFF, sum = 0
5873 12:43:14.153138 2, 0xFFFF, sum = 0
5874 12:43:14.156275 3, 0xFFFF, sum = 0
5875 12:43:14.156414 4, 0xFFFF, sum = 0
5876 12:43:14.159749 5, 0xFFFF, sum = 0
5877 12:43:14.159857 6, 0xFFFF, sum = 0
5878 12:43:14.162935 7, 0xFFFF, sum = 0
5879 12:43:14.163044 8, 0xFFFF, sum = 0
5880 12:43:14.166394 9, 0xFFFF, sum = 0
5881 12:43:14.166497 10, 0x0, sum = 1
5882 12:43:14.169769 11, 0x0, sum = 2
5883 12:43:14.169840 12, 0x0, sum = 3
5884 12:43:14.173121 13, 0x0, sum = 4
5885 12:43:14.173192 best_step = 11
5886 12:43:14.173250
5887 12:43:14.173322 ==
5888 12:43:14.176372 Dram Type= 6, Freq= 0, CH_1, rank 1
5889 12:43:14.182924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5890 12:43:14.183025 ==
5891 12:43:14.183123 RX Vref Scan: 0
5892 12:43:14.183210
5893 12:43:14.186334 RX Vref 0 -> 0, step: 1
5894 12:43:14.186432
5895 12:43:14.189742 RX Delay -45 -> 252, step: 4
5896 12:43:14.193199 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5897 12:43:14.196482 iDelay=203, Bit 1, Center 98 (15 ~ 182) 168
5898 12:43:14.203160 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5899 12:43:14.206573 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5900 12:43:14.209774 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5901 12:43:14.212897 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5902 12:43:14.216071 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172
5903 12:43:14.222772 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5904 12:43:14.226130 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5905 12:43:14.229451 iDelay=203, Bit 9, Center 90 (7 ~ 174) 168
5906 12:43:14.232857 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5907 12:43:14.236192 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5908 12:43:14.239468 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5909 12:43:14.246212 iDelay=203, Bit 13, Center 104 (19 ~ 190) 172
5910 12:43:14.249614 iDelay=203, Bit 14, Center 102 (19 ~ 186) 168
5911 12:43:14.253140 iDelay=203, Bit 15, Center 106 (19 ~ 194) 176
5912 12:43:14.253220 ==
5913 12:43:14.255899 Dram Type= 6, Freq= 0, CH_1, rank 1
5914 12:43:14.259829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5915 12:43:14.262948 ==
5916 12:43:14.263061 DQS Delay:
5917 12:43:14.263153 DQS0 = 0, DQS1 = 0
5918 12:43:14.266113 DQM Delay:
5919 12:43:14.266216 DQM0 = 104, DQM1 = 99
5920 12:43:14.269429 DQ Delay:
5921 12:43:14.272960 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =100
5922 12:43:14.276353 DQ4 =100, DQ5 =118, DQ6 =112, DQ7 =104
5923 12:43:14.279707 DQ8 =92, DQ9 =90, DQ10 =100, DQ11 =94
5924 12:43:14.283199 DQ12 =108, DQ13 =104, DQ14 =102, DQ15 =106
5925 12:43:14.283298
5926 12:43:14.283363
5927 12:43:14.289381 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f02, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5928 12:43:14.292708 CH1 RK1: MR19=505, MR18=2F02
5929 12:43:14.299728 CH1_RK1: MR19=0x505, MR18=0x2F02, DQSOSC=407, MR23=63, INC=65, DEC=43
5930 12:43:14.302840 [RxdqsGatingPostProcess] freq 933
5931 12:43:14.305981 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5932 12:43:14.309515 best DQS0 dly(2T, 0.5T) = (0, 10)
5933 12:43:14.312430 best DQS1 dly(2T, 0.5T) = (0, 10)
5934 12:43:14.316167 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5935 12:43:14.319424 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5936 12:43:14.322744 best DQS0 dly(2T, 0.5T) = (0, 10)
5937 12:43:14.326256 best DQS1 dly(2T, 0.5T) = (0, 10)
5938 12:43:14.329186 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5939 12:43:14.332547 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5940 12:43:14.335984 Pre-setting of DQS Precalculation
5941 12:43:14.339386 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5942 12:43:14.348719 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5943 12:43:14.355416 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5944 12:43:14.355522
5945 12:43:14.355614
5946 12:43:14.358887 [Calibration Summary] 1866 Mbps
5947 12:43:14.358978 CH 0, Rank 0
5948 12:43:14.362416 SW Impedance : PASS
5949 12:43:14.362511 DUTY Scan : NO K
5950 12:43:14.365826 ZQ Calibration : PASS
5951 12:43:14.368973 Jitter Meter : NO K
5952 12:43:14.369071 CBT Training : PASS
5953 12:43:14.372113 Write leveling : PASS
5954 12:43:14.375294 RX DQS gating : PASS
5955 12:43:14.375401 RX DQ/DQS(RDDQC) : PASS
5956 12:43:14.378922 TX DQ/DQS : PASS
5957 12:43:14.382258 RX DATLAT : PASS
5958 12:43:14.382359 RX DQ/DQS(Engine): PASS
5959 12:43:14.385764 TX OE : NO K
5960 12:43:14.385860 All Pass.
5961 12:43:14.385948
5962 12:43:14.388621 CH 0, Rank 1
5963 12:43:14.388720 SW Impedance : PASS
5964 12:43:14.391988 DUTY Scan : NO K
5965 12:43:14.395263 ZQ Calibration : PASS
5966 12:43:14.395357 Jitter Meter : NO K
5967 12:43:14.398705 CBT Training : PASS
5968 12:43:14.402237 Write leveling : PASS
5969 12:43:14.402332 RX DQS gating : PASS
5970 12:43:14.405520 RX DQ/DQS(RDDQC) : PASS
5971 12:43:14.405623 TX DQ/DQS : PASS
5972 12:43:14.408923 RX DATLAT : PASS
5973 12:43:14.412216 RX DQ/DQS(Engine): PASS
5974 12:43:14.412348 TX OE : NO K
5975 12:43:14.415686 All Pass.
5976 12:43:14.415782
5977 12:43:14.415869 CH 1, Rank 0
5978 12:43:14.419014 SW Impedance : PASS
5979 12:43:14.419107 DUTY Scan : NO K
5980 12:43:14.422114 ZQ Calibration : PASS
5981 12:43:14.425813 Jitter Meter : NO K
5982 12:43:14.425900 CBT Training : PASS
5983 12:43:14.429157 Write leveling : PASS
5984 12:43:14.432338 RX DQS gating : PASS
5985 12:43:14.432453 RX DQ/DQS(RDDQC) : PASS
5986 12:43:14.435550 TX DQ/DQS : PASS
5987 12:43:14.438729 RX DATLAT : PASS
5988 12:43:14.438854 RX DQ/DQS(Engine): PASS
5989 12:43:14.441940 TX OE : NO K
5990 12:43:14.442038 All Pass.
5991 12:43:14.442125
5992 12:43:14.445781 CH 1, Rank 1
5993 12:43:14.445873 SW Impedance : PASS
5994 12:43:14.448986 DUTY Scan : NO K
5995 12:43:14.452392 ZQ Calibration : PASS
5996 12:43:14.452460 Jitter Meter : NO K
5997 12:43:14.455678 CBT Training : PASS
5998 12:43:14.455774 Write leveling : PASS
5999 12:43:14.459045 RX DQS gating : PASS
6000 12:43:14.461821 RX DQ/DQS(RDDQC) : PASS
6001 12:43:14.461918 TX DQ/DQS : PASS
6002 12:43:14.465220 RX DATLAT : PASS
6003 12:43:14.468828 RX DQ/DQS(Engine): PASS
6004 12:43:14.468895 TX OE : NO K
6005 12:43:14.472171 All Pass.
6006 12:43:14.472263
6007 12:43:14.472358 DramC Write-DBI off
6008 12:43:14.475410 PER_BANK_REFRESH: Hybrid Mode
6009 12:43:14.478655 TX_TRACKING: ON
6010 12:43:14.485165 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6011 12:43:14.488797 [FAST_K] Save calibration result to emmc
6012 12:43:14.492078 dramc_set_vcore_voltage set vcore to 650000
6013 12:43:14.495579 Read voltage for 400, 6
6014 12:43:14.495679 Vio18 = 0
6015 12:43:14.498821 Vcore = 650000
6016 12:43:14.498916 Vdram = 0
6017 12:43:14.499003 Vddq = 0
6018 12:43:14.502204 Vmddr = 0
6019 12:43:14.504978 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6020 12:43:14.511687 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6021 12:43:14.511785 MEM_TYPE=3, freq_sel=20
6022 12:43:14.515113 sv_algorithm_assistance_LP4_800
6023 12:43:14.521948 ============ PULL DRAM RESETB DOWN ============
6024 12:43:14.525403 ========== PULL DRAM RESETB DOWN end =========
6025 12:43:14.528819 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6026 12:43:14.532040 ===================================
6027 12:43:14.535189 LPDDR4 DRAM CONFIGURATION
6028 12:43:14.538593 ===================================
6029 12:43:14.538691 EX_ROW_EN[0] = 0x0
6030 12:43:14.541876 EX_ROW_EN[1] = 0x0
6031 12:43:14.541975 LP4Y_EN = 0x0
6032 12:43:14.545293 WORK_FSP = 0x0
6033 12:43:14.548699 WL = 0x2
6034 12:43:14.548795 RL = 0x2
6035 12:43:14.551843 BL = 0x2
6036 12:43:14.551955 RPST = 0x0
6037 12:43:14.555740 RD_PRE = 0x0
6038 12:43:14.555841 WR_PRE = 0x1
6039 12:43:14.559097 WR_PST = 0x0
6040 12:43:14.559200 DBI_WR = 0x0
6041 12:43:14.562274 DBI_RD = 0x0
6042 12:43:14.562373 OTF = 0x1
6043 12:43:14.565552 ===================================
6044 12:43:14.568872 ===================================
6045 12:43:14.571661 ANA top config
6046 12:43:14.575113 ===================================
6047 12:43:14.575213 DLL_ASYNC_EN = 0
6048 12:43:14.578579 ALL_SLAVE_EN = 1
6049 12:43:14.581985 NEW_RANK_MODE = 1
6050 12:43:14.585310 DLL_IDLE_MODE = 1
6051 12:43:14.585395 LP45_APHY_COMB_EN = 1
6052 12:43:14.588748 TX_ODT_DIS = 1
6053 12:43:14.592026 NEW_8X_MODE = 1
6054 12:43:14.595357 ===================================
6055 12:43:14.598645 ===================================
6056 12:43:14.601956 data_rate = 800
6057 12:43:14.605237 CKR = 1
6058 12:43:14.608703 DQ_P2S_RATIO = 4
6059 12:43:14.612063 ===================================
6060 12:43:14.612145 CA_P2S_RATIO = 4
6061 12:43:14.615436 DQ_CA_OPEN = 0
6062 12:43:14.618744 DQ_SEMI_OPEN = 1
6063 12:43:14.621542 CA_SEMI_OPEN = 1
6064 12:43:14.624974 CA_FULL_RATE = 0
6065 12:43:14.628486 DQ_CKDIV4_EN = 0
6066 12:43:14.628563 CA_CKDIV4_EN = 1
6067 12:43:14.631968 CA_PREDIV_EN = 0
6068 12:43:14.635347 PH8_DLY = 0
6069 12:43:14.638111 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6070 12:43:14.642070 DQ_AAMCK_DIV = 0
6071 12:43:14.644801 CA_AAMCK_DIV = 0
6072 12:43:14.644901 CA_ADMCK_DIV = 4
6073 12:43:14.648678 DQ_TRACK_CA_EN = 0
6074 12:43:14.651343 CA_PICK = 800
6075 12:43:14.654808 CA_MCKIO = 400
6076 12:43:14.658122 MCKIO_SEMI = 400
6077 12:43:14.661511 PLL_FREQ = 3016
6078 12:43:14.664861 DQ_UI_PI_RATIO = 32
6079 12:43:14.664945 CA_UI_PI_RATIO = 32
6080 12:43:14.668711 ===================================
6081 12:43:14.671997 ===================================
6082 12:43:14.675269 memory_type:LPDDR4
6083 12:43:14.678473 GP_NUM : 10
6084 12:43:14.678554 SRAM_EN : 1
6085 12:43:14.681827 MD32_EN : 0
6086 12:43:14.685249 ===================================
6087 12:43:14.688666 [ANA_INIT] >>>>>>>>>>>>>>
6088 12:43:14.691937 <<<<<< [CONFIGURE PHASE]: ANA_TX
6089 12:43:14.695181 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6090 12:43:14.698687 ===================================
6091 12:43:14.698767 data_rate = 800,PCW = 0X7400
6092 12:43:14.701342 ===================================
6093 12:43:14.704681 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6094 12:43:14.711328 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6095 12:43:14.721634 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6096 12:43:14.728254 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6097 12:43:14.731743 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6098 12:43:14.734649 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6099 12:43:14.738103 [ANA_INIT] flow start
6100 12:43:14.738184 [ANA_INIT] PLL >>>>>>>>
6101 12:43:14.741527 [ANA_INIT] PLL <<<<<<<<
6102 12:43:14.744824 [ANA_INIT] MIDPI >>>>>>>>
6103 12:43:14.744905 [ANA_INIT] MIDPI <<<<<<<<
6104 12:43:14.748256 [ANA_INIT] DLL >>>>>>>>
6105 12:43:14.751049 [ANA_INIT] flow end
6106 12:43:14.754283 ============ LP4 DIFF to SE enter ============
6107 12:43:14.758362 ============ LP4 DIFF to SE exit ============
6108 12:43:14.761012 [ANA_INIT] <<<<<<<<<<<<<
6109 12:43:14.764506 [Flow] Enable top DCM control >>>>>
6110 12:43:14.768025 [Flow] Enable top DCM control <<<<<
6111 12:43:14.771386 Enable DLL master slave shuffle
6112 12:43:14.774634 ==============================================================
6113 12:43:14.778130 Gating Mode config
6114 12:43:14.784750 ==============================================================
6115 12:43:14.784832 Config description:
6116 12:43:14.794484 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6117 12:43:14.800886 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6118 12:43:14.804416 SELPH_MODE 0: By rank 1: By Phase
6119 12:43:14.811209 ==============================================================
6120 12:43:14.814496 GAT_TRACK_EN = 0
6121 12:43:14.818180 RX_GATING_MODE = 2
6122 12:43:14.821256 RX_GATING_TRACK_MODE = 2
6123 12:43:14.824255 SELPH_MODE = 1
6124 12:43:14.828083 PICG_EARLY_EN = 1
6125 12:43:14.830872 VALID_LAT_VALUE = 1
6126 12:43:14.834223 ==============================================================
6127 12:43:14.837805 Enter into Gating configuration >>>>
6128 12:43:14.841211 Exit from Gating configuration <<<<
6129 12:43:14.844411 Enter into DVFS_PRE_config >>>>>
6130 12:43:14.854685 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6131 12:43:14.857485 Exit from DVFS_PRE_config <<<<<
6132 12:43:14.860880 Enter into PICG configuration >>>>
6133 12:43:14.864421 Exit from PICG configuration <<<<
6134 12:43:14.867640 [RX_INPUT] configuration >>>>>
6135 12:43:14.870929 [RX_INPUT] configuration <<<<<
6136 12:43:14.877701 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6137 12:43:14.880980 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6138 12:43:14.887589 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6139 12:43:14.894237 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6140 12:43:14.900571 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6141 12:43:14.907465 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6142 12:43:14.910681 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6143 12:43:14.914135 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6144 12:43:14.917654 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6145 12:43:14.923908 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6146 12:43:14.927672 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6147 12:43:14.930761 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6148 12:43:14.933842 ===================================
6149 12:43:14.937387 LPDDR4 DRAM CONFIGURATION
6150 12:43:14.940417 ===================================
6151 12:43:14.940497 EX_ROW_EN[0] = 0x0
6152 12:43:14.943899 EX_ROW_EN[1] = 0x0
6153 12:43:14.947371 LP4Y_EN = 0x0
6154 12:43:14.947451 WORK_FSP = 0x0
6155 12:43:14.950566 WL = 0x2
6156 12:43:14.950646 RL = 0x2
6157 12:43:14.953848 BL = 0x2
6158 12:43:14.953928 RPST = 0x0
6159 12:43:14.957411 RD_PRE = 0x0
6160 12:43:14.957515 WR_PRE = 0x1
6161 12:43:14.960777 WR_PST = 0x0
6162 12:43:14.960870 DBI_WR = 0x0
6163 12:43:14.963720 DBI_RD = 0x0
6164 12:43:14.963800 OTF = 0x1
6165 12:43:14.967212 ===================================
6166 12:43:14.970650 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6167 12:43:14.977257 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6168 12:43:14.980665 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6169 12:43:14.983990 ===================================
6170 12:43:14.987401 LPDDR4 DRAM CONFIGURATION
6171 12:43:14.990634 ===================================
6172 12:43:14.990714 EX_ROW_EN[0] = 0x10
6173 12:43:14.993860 EX_ROW_EN[1] = 0x0
6174 12:43:14.993940 LP4Y_EN = 0x0
6175 12:43:14.997395 WORK_FSP = 0x0
6176 12:43:14.997475 WL = 0x2
6177 12:43:15.000067 RL = 0x2
6178 12:43:15.003505 BL = 0x2
6179 12:43:15.003585 RPST = 0x0
6180 12:43:15.006914 RD_PRE = 0x0
6181 12:43:15.006993 WR_PRE = 0x1
6182 12:43:15.010228 WR_PST = 0x0
6183 12:43:15.010308 DBI_WR = 0x0
6184 12:43:15.013369 DBI_RD = 0x0
6185 12:43:15.013449 OTF = 0x1
6186 12:43:15.016732 ===================================
6187 12:43:15.023364 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6188 12:43:15.027518 nWR fixed to 30
6189 12:43:15.030985 [ModeRegInit_LP4] CH0 RK0
6190 12:43:15.031066 [ModeRegInit_LP4] CH0 RK1
6191 12:43:15.034097 [ModeRegInit_LP4] CH1 RK0
6192 12:43:15.037511 [ModeRegInit_LP4] CH1 RK1
6193 12:43:15.037592 match AC timing 19
6194 12:43:15.044007 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6195 12:43:15.047220 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6196 12:43:15.050835 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6197 12:43:15.057118 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6198 12:43:15.060419 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6199 12:43:15.060500 ==
6200 12:43:15.063839 Dram Type= 6, Freq= 0, CH_0, rank 0
6201 12:43:15.067130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6202 12:43:15.067237 ==
6203 12:43:15.074047 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6204 12:43:15.080885 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6205 12:43:15.084150 [CA 0] Center 36 (8~64) winsize 57
6206 12:43:15.087035 [CA 1] Center 36 (8~64) winsize 57
6207 12:43:15.090555 [CA 2] Center 36 (8~64) winsize 57
6208 12:43:15.090636 [CA 3] Center 36 (8~64) winsize 57
6209 12:43:15.093912 [CA 4] Center 36 (8~64) winsize 57
6210 12:43:15.097304 [CA 5] Center 36 (8~64) winsize 57
6211 12:43:15.097384
6212 12:43:15.100482 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6213 12:43:15.103917
6214 12:43:15.107316 [CATrainingPosCal] consider 1 rank data
6215 12:43:15.107396 u2DelayCellTimex100 = 270/100 ps
6216 12:43:15.114143 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 12:43:15.117706 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 12:43:15.120454 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 12:43:15.123915 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 12:43:15.126953 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 12:43:15.130754 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 12:43:15.130835
6223 12:43:15.133810 CA PerBit enable=1, Macro0, CA PI delay=36
6224 12:43:15.133890
6225 12:43:15.136914 [CBTSetCACLKResult] CA Dly = 36
6226 12:43:15.140634 CS Dly: 1 (0~32)
6227 12:43:15.140714 ==
6228 12:43:15.143881 Dram Type= 6, Freq= 0, CH_0, rank 1
6229 12:43:15.147403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6230 12:43:15.147484 ==
6231 12:43:15.154008 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6232 12:43:15.156723 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6233 12:43:15.159991 [CA 0] Center 36 (8~64) winsize 57
6234 12:43:15.163794 [CA 1] Center 36 (8~64) winsize 57
6235 12:43:15.166817 [CA 2] Center 36 (8~64) winsize 57
6236 12:43:15.170258 [CA 3] Center 36 (8~64) winsize 57
6237 12:43:15.173357 [CA 4] Center 36 (8~64) winsize 57
6238 12:43:15.176953 [CA 5] Center 36 (8~64) winsize 57
6239 12:43:15.177034
6240 12:43:15.180108 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6241 12:43:15.180213
6242 12:43:15.183564 [CATrainingPosCal] consider 2 rank data
6243 12:43:15.186969 u2DelayCellTimex100 = 270/100 ps
6244 12:43:15.190261 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 12:43:15.193581 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 12:43:15.199764 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 12:43:15.203144 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 12:43:15.206573 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 12:43:15.209774 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 12:43:15.209855
6251 12:43:15.213158 CA PerBit enable=1, Macro0, CA PI delay=36
6252 12:43:15.213238
6253 12:43:15.216493 [CBTSetCACLKResult] CA Dly = 36
6254 12:43:15.216573 CS Dly: 1 (0~32)
6255 12:43:15.216636
6256 12:43:15.219902 ----->DramcWriteLeveling(PI) begin...
6257 12:43:15.223280 ==
6258 12:43:15.226807 Dram Type= 6, Freq= 0, CH_0, rank 0
6259 12:43:15.229551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6260 12:43:15.229632 ==
6261 12:43:15.232921 Write leveling (Byte 0): 40 => 8
6262 12:43:15.236280 Write leveling (Byte 1): 40 => 8
6263 12:43:15.239833 DramcWriteLeveling(PI) end<-----
6264 12:43:15.239912
6265 12:43:15.239975 ==
6266 12:43:15.243133 Dram Type= 6, Freq= 0, CH_0, rank 0
6267 12:43:15.246583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6268 12:43:15.246664 ==
6269 12:43:15.249851 [Gating] SW mode calibration
6270 12:43:15.256411 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6271 12:43:15.262597 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6272 12:43:15.266385 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6273 12:43:15.269859 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6274 12:43:15.273248 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6275 12:43:15.279605 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6276 12:43:15.282744 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 12:43:15.286099 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 12:43:15.292965 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 12:43:15.296174 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 12:43:15.299454 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6281 12:43:15.303085 Total UI for P1: 0, mck2ui 16
6282 12:43:15.306476 best dqsien dly found for B0: ( 0, 14, 24)
6283 12:43:15.309788 Total UI for P1: 0, mck2ui 16
6284 12:43:15.313078 best dqsien dly found for B1: ( 0, 14, 24)
6285 12:43:15.316464 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6286 12:43:15.319214 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6287 12:43:15.322590
6288 12:43:15.326061 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6289 12:43:15.329480 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6290 12:43:15.332868 [Gating] SW calibration Done
6291 12:43:15.332948 ==
6292 12:43:15.336259 Dram Type= 6, Freq= 0, CH_0, rank 0
6293 12:43:15.339710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6294 12:43:15.339790 ==
6295 12:43:15.339853 RX Vref Scan: 0
6296 12:43:15.339911
6297 12:43:15.342400 RX Vref 0 -> 0, step: 1
6298 12:43:15.342479
6299 12:43:15.345976 RX Delay -410 -> 252, step: 16
6300 12:43:15.349129 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6301 12:43:15.355732 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6302 12:43:15.359144 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6303 12:43:15.362458 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6304 12:43:15.365848 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6305 12:43:15.372645 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6306 12:43:15.375806 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6307 12:43:15.379670 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6308 12:43:15.382655 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6309 12:43:15.386122 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6310 12:43:15.392905 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6311 12:43:15.396126 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6312 12:43:15.399595 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6313 12:43:15.405669 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6314 12:43:15.409097 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6315 12:43:15.412460 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6316 12:43:15.412539 ==
6317 12:43:15.415745 Dram Type= 6, Freq= 0, CH_0, rank 0
6318 12:43:15.419093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6319 12:43:15.422441 ==
6320 12:43:15.422521 DQS Delay:
6321 12:43:15.422584 DQS0 = 27, DQS1 = 35
6322 12:43:15.425828 DQM Delay:
6323 12:43:15.425907 DQM0 = 11, DQM1 = 11
6324 12:43:15.429132 DQ Delay:
6325 12:43:15.429211 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6326 12:43:15.432569 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6327 12:43:15.436012 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6328 12:43:15.439332 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6329 12:43:15.439412
6330 12:43:15.439473
6331 12:43:15.439533 ==
6332 12:43:15.442704 Dram Type= 6, Freq= 0, CH_0, rank 0
6333 12:43:15.448976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6334 12:43:15.449056 ==
6335 12:43:15.449118
6336 12:43:15.449175
6337 12:43:15.449231 TX Vref Scan disable
6338 12:43:15.452308 == TX Byte 0 ==
6339 12:43:15.455696 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6340 12:43:15.459179 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6341 12:43:15.462319 == TX Byte 1 ==
6342 12:43:15.465664 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6343 12:43:15.469153 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6344 12:43:15.469233 ==
6345 12:43:15.472682 Dram Type= 6, Freq= 0, CH_0, rank 0
6346 12:43:15.479397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6347 12:43:15.479476 ==
6348 12:43:15.479538
6349 12:43:15.479595
6350 12:43:15.479650 TX Vref Scan disable
6351 12:43:15.482740 == TX Byte 0 ==
6352 12:43:15.485847 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6353 12:43:15.489045 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6354 12:43:15.492980 == TX Byte 1 ==
6355 12:43:15.496013 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6356 12:43:15.499229 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6357 12:43:15.499311
6358 12:43:15.502323 [DATLAT]
6359 12:43:15.502402 Freq=400, CH0 RK0
6360 12:43:15.502466
6361 12:43:15.505735 DATLAT Default: 0xf
6362 12:43:15.505816 0, 0xFFFF, sum = 0
6363 12:43:15.508869 1, 0xFFFF, sum = 0
6364 12:43:15.508951 2, 0xFFFF, sum = 0
6365 12:43:15.512810 3, 0xFFFF, sum = 0
6366 12:43:15.512891 4, 0xFFFF, sum = 0
6367 12:43:15.515954 5, 0xFFFF, sum = 0
6368 12:43:15.516036 6, 0xFFFF, sum = 0
6369 12:43:15.519422 7, 0xFFFF, sum = 0
6370 12:43:15.519503 8, 0xFFFF, sum = 0
6371 12:43:15.522812 9, 0xFFFF, sum = 0
6372 12:43:15.522893 10, 0xFFFF, sum = 0
6373 12:43:15.526107 11, 0xFFFF, sum = 0
6374 12:43:15.529516 12, 0xFFFF, sum = 0
6375 12:43:15.529597 13, 0x0, sum = 1
6376 12:43:15.532966 14, 0x0, sum = 2
6377 12:43:15.533047 15, 0x0, sum = 3
6378 12:43:15.533112 16, 0x0, sum = 4
6379 12:43:15.535695 best_step = 14
6380 12:43:15.535775
6381 12:43:15.535838 ==
6382 12:43:15.539058 Dram Type= 6, Freq= 0, CH_0, rank 0
6383 12:43:15.542461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6384 12:43:15.542541 ==
6385 12:43:15.545790 RX Vref Scan: 1
6386 12:43:15.545870
6387 12:43:15.545933 RX Vref 0 -> 0, step: 1
6388 12:43:15.549190
6389 12:43:15.549270 RX Delay -311 -> 252, step: 8
6390 12:43:15.549333
6391 12:43:15.552608 Set Vref, RX VrefLevel [Byte0]: 56
6392 12:43:15.555905 [Byte1]: 49
6393 12:43:15.560786
6394 12:43:15.560866 Final RX Vref Byte 0 = 56 to rank0
6395 12:43:15.564241 Final RX Vref Byte 1 = 49 to rank0
6396 12:43:15.567627 Final RX Vref Byte 0 = 56 to rank1
6397 12:43:15.570799 Final RX Vref Byte 1 = 49 to rank1==
6398 12:43:15.574095 Dram Type= 6, Freq= 0, CH_0, rank 0
6399 12:43:15.580746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6400 12:43:15.580827 ==
6401 12:43:15.580890 DQS Delay:
6402 12:43:15.584205 DQS0 = 24, DQS1 = 36
6403 12:43:15.584343 DQM Delay:
6404 12:43:15.584408 DQM0 = 7, DQM1 = 13
6405 12:43:15.587660 DQ Delay:
6406 12:43:15.587740 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6407 12:43:15.590409 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6408 12:43:15.593831 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6409 12:43:15.597167 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6410 12:43:15.597247
6411 12:43:15.597309
6412 12:43:15.607189 [DQSOSCAuto] RK0, (LSB)MR18= 0xd1be, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6413 12:43:15.610848 CH0 RK0: MR19=C0C, MR18=D1BE
6414 12:43:15.617257 CH0_RK0: MR19=0xC0C, MR18=0xD1BE, DQSOSC=384, MR23=63, INC=400, DEC=267
6415 12:43:15.617337 ==
6416 12:43:15.620268 Dram Type= 6, Freq= 0, CH_0, rank 1
6417 12:43:15.624031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6418 12:43:15.624111 ==
6419 12:43:15.627273 [Gating] SW mode calibration
6420 12:43:15.634009 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6421 12:43:15.636846 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6422 12:43:15.643615 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6423 12:43:15.646971 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6424 12:43:15.650393 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6425 12:43:15.657287 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6426 12:43:15.660572 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 12:43:15.663850 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 12:43:15.670893 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 12:43:15.673649 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 12:43:15.676834 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6431 12:43:15.680516 Total UI for P1: 0, mck2ui 16
6432 12:43:15.683681 best dqsien dly found for B0: ( 0, 14, 24)
6433 12:43:15.686886 Total UI for P1: 0, mck2ui 16
6434 12:43:15.690452 best dqsien dly found for B1: ( 0, 14, 24)
6435 12:43:15.693862 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6436 12:43:15.697151 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6437 12:43:15.697227
6438 12:43:15.703808 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6439 12:43:15.707204 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6440 12:43:15.707282 [Gating] SW calibration Done
6441 12:43:15.710758 ==
6442 12:43:15.710834 Dram Type= 6, Freq= 0, CH_0, rank 1
6443 12:43:15.717366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6444 12:43:15.717440 ==
6445 12:43:15.717512 RX Vref Scan: 0
6446 12:43:15.717570
6447 12:43:15.720511 RX Vref 0 -> 0, step: 1
6448 12:43:15.720589
6449 12:43:15.723962 RX Delay -410 -> 252, step: 16
6450 12:43:15.727164 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6451 12:43:15.730431 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6452 12:43:15.736964 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6453 12:43:15.740007 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6454 12:43:15.743797 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6455 12:43:15.746905 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6456 12:43:15.753244 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6457 12:43:15.756648 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6458 12:43:15.760127 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6459 12:43:15.763545 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6460 12:43:15.770300 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6461 12:43:15.773055 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6462 12:43:15.776678 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6463 12:43:15.783443 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6464 12:43:15.786609 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6465 12:43:15.789922 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6466 12:43:15.790002 ==
6467 12:43:15.793253 Dram Type= 6, Freq= 0, CH_0, rank 1
6468 12:43:15.796587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 12:43:15.799909 ==
6470 12:43:15.799989 DQS Delay:
6471 12:43:15.800052 DQS0 = 27, DQS1 = 35
6472 12:43:15.803237 DQM Delay:
6473 12:43:15.803317 DQM0 = 12, DQM1 = 11
6474 12:43:15.806679 DQ Delay:
6475 12:43:15.806792 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6476 12:43:15.810036 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6477 12:43:15.812885 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6478 12:43:15.816380 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6479 12:43:15.816486
6480 12:43:15.816565
6481 12:43:15.816626 ==
6482 12:43:15.819763 Dram Type= 6, Freq= 0, CH_0, rank 1
6483 12:43:15.826453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6484 12:43:15.826536 ==
6485 12:43:15.826600
6486 12:43:15.826657
6487 12:43:15.826713 TX Vref Scan disable
6488 12:43:15.829766 == TX Byte 0 ==
6489 12:43:15.833217 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6490 12:43:15.836741 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6491 12:43:15.839540 == TX Byte 1 ==
6492 12:43:15.842824 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6493 12:43:15.846676 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6494 12:43:15.846756 ==
6495 12:43:15.849707 Dram Type= 6, Freq= 0, CH_0, rank 1
6496 12:43:15.856632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6497 12:43:15.856713 ==
6498 12:43:15.856775
6499 12:43:15.856834
6500 12:43:15.856889 TX Vref Scan disable
6501 12:43:15.859751 == TX Byte 0 ==
6502 12:43:15.862870 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6503 12:43:15.866022 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6504 12:43:15.869747 == TX Byte 1 ==
6505 12:43:15.872980 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6506 12:43:15.876538 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6507 12:43:15.876618
6508 12:43:15.879353 [DATLAT]
6509 12:43:15.879432 Freq=400, CH0 RK1
6510 12:43:15.879496
6511 12:43:15.882914 DATLAT Default: 0xe
6512 12:43:15.882993 0, 0xFFFF, sum = 0
6513 12:43:15.886419 1, 0xFFFF, sum = 0
6514 12:43:15.886500 2, 0xFFFF, sum = 0
6515 12:43:15.889184 3, 0xFFFF, sum = 0
6516 12:43:15.889266 4, 0xFFFF, sum = 0
6517 12:43:15.892494 5, 0xFFFF, sum = 0
6518 12:43:15.892576 6, 0xFFFF, sum = 0
6519 12:43:15.895905 7, 0xFFFF, sum = 0
6520 12:43:15.899286 8, 0xFFFF, sum = 0
6521 12:43:15.899368 9, 0xFFFF, sum = 0
6522 12:43:15.902494 10, 0xFFFF, sum = 0
6523 12:43:15.902575 11, 0xFFFF, sum = 0
6524 12:43:15.906214 12, 0xFFFF, sum = 0
6525 12:43:15.906295 13, 0x0, sum = 1
6526 12:43:15.909394 14, 0x0, sum = 2
6527 12:43:15.909476 15, 0x0, sum = 3
6528 12:43:15.912657 16, 0x0, sum = 4
6529 12:43:15.912772 best_step = 14
6530 12:43:15.912839
6531 12:43:15.912897 ==
6532 12:43:15.915947 Dram Type= 6, Freq= 0, CH_0, rank 1
6533 12:43:15.919289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6534 12:43:15.919369 ==
6535 12:43:15.922868 RX Vref Scan: 0
6536 12:43:15.922949
6537 12:43:15.926170 RX Vref 0 -> 0, step: 1
6538 12:43:15.926250
6539 12:43:15.926312 RX Delay -311 -> 252, step: 8
6540 12:43:15.935209 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6541 12:43:15.937909 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6542 12:43:15.941173 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6543 12:43:15.944947 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6544 12:43:15.950856 iDelay=217, Bit 4, Center -12 (-231 ~ 208) 440
6545 12:43:15.954240 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6546 12:43:15.957483 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6547 12:43:15.960697 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6548 12:43:15.967176 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6549 12:43:15.970554 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6550 12:43:15.974313 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6551 12:43:15.980568 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6552 12:43:15.984392 iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432
6553 12:43:15.987505 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6554 12:43:15.990973 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6555 12:43:15.997471 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6556 12:43:15.997553 ==
6557 12:43:16.000762 Dram Type= 6, Freq= 0, CH_0, rank 1
6558 12:43:16.004197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6559 12:43:16.004277 ==
6560 12:43:16.004380 DQS Delay:
6561 12:43:16.007226 DQS0 = 24, DQS1 = 32
6562 12:43:16.007306 DQM Delay:
6563 12:43:16.010672 DQM0 = 9, DQM1 = 10
6564 12:43:16.010752 DQ Delay:
6565 12:43:16.013925 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6566 12:43:16.017166 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =16
6567 12:43:16.020315 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6568 12:43:16.024244 DQ12 =16, DQ13 =12, DQ14 =20, DQ15 =16
6569 12:43:16.024360
6570 12:43:16.024424
6571 12:43:16.030179 [DQSOSCAuto] RK1, (LSB)MR18= 0xc05f, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 386 ps
6572 12:43:16.033562 CH0 RK1: MR19=C0C, MR18=C05F
6573 12:43:16.040374 CH0_RK1: MR19=0xC0C, MR18=0xC05F, DQSOSC=386, MR23=63, INC=396, DEC=264
6574 12:43:16.043907 [RxdqsGatingPostProcess] freq 400
6575 12:43:16.050787 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6576 12:43:16.053651 best DQS0 dly(2T, 0.5T) = (0, 10)
6577 12:43:16.053731 best DQS1 dly(2T, 0.5T) = (0, 10)
6578 12:43:16.057267 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6579 12:43:16.060591 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6580 12:43:16.063455 best DQS0 dly(2T, 0.5T) = (0, 10)
6581 12:43:16.066737 best DQS1 dly(2T, 0.5T) = (0, 10)
6582 12:43:16.070669 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6583 12:43:16.073440 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6584 12:43:16.076863 Pre-setting of DQS Precalculation
6585 12:43:16.083397 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6586 12:43:16.083478 ==
6587 12:43:16.086922 Dram Type= 6, Freq= 0, CH_1, rank 0
6588 12:43:16.090268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6589 12:43:16.090344 ==
6590 12:43:16.096648 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6591 12:43:16.099664 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6592 12:43:16.103567 [CA 0] Center 36 (8~64) winsize 57
6593 12:43:16.106843 [CA 1] Center 36 (8~64) winsize 57
6594 12:43:16.110437 [CA 2] Center 36 (8~64) winsize 57
6595 12:43:16.113131 [CA 3] Center 36 (8~64) winsize 57
6596 12:43:16.116479 [CA 4] Center 36 (8~64) winsize 57
6597 12:43:16.119666 [CA 5] Center 36 (8~64) winsize 57
6598 12:43:16.119738
6599 12:43:16.123041 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6600 12:43:16.123113
6601 12:43:16.126343 [CATrainingPosCal] consider 1 rank data
6602 12:43:16.129659 u2DelayCellTimex100 = 270/100 ps
6603 12:43:16.133395 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 12:43:16.136698 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 12:43:16.139769 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 12:43:16.146575 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 12:43:16.150033 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 12:43:16.153006 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 12:43:16.153080
6610 12:43:16.156215 CA PerBit enable=1, Macro0, CA PI delay=36
6611 12:43:16.156295
6612 12:43:16.159715 [CBTSetCACLKResult] CA Dly = 36
6613 12:43:16.159793 CS Dly: 1 (0~32)
6614 12:43:16.159856 ==
6615 12:43:16.163218 Dram Type= 6, Freq= 0, CH_1, rank 1
6616 12:43:16.170184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6617 12:43:16.170262 ==
6618 12:43:16.172940 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6619 12:43:16.179776 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6620 12:43:16.183194 [CA 0] Center 36 (8~64) winsize 57
6621 12:43:16.186299 [CA 1] Center 36 (8~64) winsize 57
6622 12:43:16.190055 [CA 2] Center 36 (8~64) winsize 57
6623 12:43:16.193312 [CA 3] Center 36 (8~64) winsize 57
6624 12:43:16.196762 [CA 4] Center 36 (8~64) winsize 57
6625 12:43:16.200129 [CA 5] Center 36 (8~64) winsize 57
6626 12:43:16.200207
6627 12:43:16.202828 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6628 12:43:16.202895
6629 12:43:16.206227 [CATrainingPosCal] consider 2 rank data
6630 12:43:16.210161 u2DelayCellTimex100 = 270/100 ps
6631 12:43:16.213340 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 12:43:16.216380 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 12:43:16.219995 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 12:43:16.222999 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 12:43:16.226516 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 12:43:16.229604 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 12:43:16.229681
6638 12:43:16.236466 CA PerBit enable=1, Macro0, CA PI delay=36
6639 12:43:16.236547
6640 12:43:16.236610 [CBTSetCACLKResult] CA Dly = 36
6641 12:43:16.239865 CS Dly: 1 (0~32)
6642 12:43:16.239942
6643 12:43:16.243161 ----->DramcWriteLeveling(PI) begin...
6644 12:43:16.243236 ==
6645 12:43:16.246499 Dram Type= 6, Freq= 0, CH_1, rank 0
6646 12:43:16.249901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6647 12:43:16.249984 ==
6648 12:43:16.253098 Write leveling (Byte 0): 40 => 8
6649 12:43:16.256077 Write leveling (Byte 1): 40 => 8
6650 12:43:16.259527 DramcWriteLeveling(PI) end<-----
6651 12:43:16.259607
6652 12:43:16.259670 ==
6653 12:43:16.262932 Dram Type= 6, Freq= 0, CH_1, rank 0
6654 12:43:16.266367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6655 12:43:16.266447 ==
6656 12:43:16.269868 [Gating] SW mode calibration
6657 12:43:16.276750 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6658 12:43:16.282924 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6659 12:43:16.286273 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6660 12:43:16.293223 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6661 12:43:16.296422 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6662 12:43:16.299616 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6663 12:43:16.306897 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6664 12:43:16.309631 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6665 12:43:16.313048 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6666 12:43:16.316541 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 12:43:16.323384 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6668 12:43:16.326613 Total UI for P1: 0, mck2ui 16
6669 12:43:16.329841 best dqsien dly found for B0: ( 0, 14, 24)
6670 12:43:16.333084 Total UI for P1: 0, mck2ui 16
6671 12:43:16.336232 best dqsien dly found for B1: ( 0, 14, 24)
6672 12:43:16.339890 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6673 12:43:16.343388 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6674 12:43:16.343462
6675 12:43:16.346371 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6676 12:43:16.349518 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6677 12:43:16.353321 [Gating] SW calibration Done
6678 12:43:16.353395 ==
6679 12:43:16.356678 Dram Type= 6, Freq= 0, CH_1, rank 0
6680 12:43:16.359476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6681 12:43:16.359554 ==
6682 12:43:16.363244 RX Vref Scan: 0
6683 12:43:16.363330
6684 12:43:16.366319 RX Vref 0 -> 0, step: 1
6685 12:43:16.366398
6686 12:43:16.366461 RX Delay -410 -> 252, step: 16
6687 12:43:16.372853 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6688 12:43:16.376454 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6689 12:43:16.379734 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6690 12:43:16.383175 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6691 12:43:16.389959 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6692 12:43:16.392651 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6693 12:43:16.396512 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6694 12:43:16.399748 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6695 12:43:16.406110 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6696 12:43:16.409422 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6697 12:43:16.412602 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6698 12:43:16.416021 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6699 12:43:16.422942 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6700 12:43:16.426459 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6701 12:43:16.429850 iDelay=230, Bit 14, Center -11 (-250 ~ 229) 480
6702 12:43:16.436063 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6703 12:43:16.436140 ==
6704 12:43:16.439583 Dram Type= 6, Freq= 0, CH_1, rank 0
6705 12:43:16.443097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6706 12:43:16.443169 ==
6707 12:43:16.443230 DQS Delay:
6708 12:43:16.445910 DQS0 = 35, DQS1 = 35
6709 12:43:16.445986 DQM Delay:
6710 12:43:16.449288 DQM0 = 18, DQM1 = 14
6711 12:43:16.449359 DQ Delay:
6712 12:43:16.452451 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6713 12:43:16.455749 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6714 12:43:16.459371 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6715 12:43:16.462689 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6716 12:43:16.462762
6717 12:43:16.462822
6718 12:43:16.462890 ==
6719 12:43:16.465911 Dram Type= 6, Freq= 0, CH_1, rank 0
6720 12:43:16.469112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6721 12:43:16.469186 ==
6722 12:43:16.469255
6723 12:43:16.469316
6724 12:43:16.472431 TX Vref Scan disable
6725 12:43:16.475754 == TX Byte 0 ==
6726 12:43:16.479402 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6727 12:43:16.482416 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6728 12:43:16.482496 == TX Byte 1 ==
6729 12:43:16.489193 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6730 12:43:16.492670 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6731 12:43:16.492750 ==
6732 12:43:16.496092 Dram Type= 6, Freq= 0, CH_1, rank 0
6733 12:43:16.498870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6734 12:43:16.498950 ==
6735 12:43:16.499012
6736 12:43:16.502180
6737 12:43:16.502259 TX Vref Scan disable
6738 12:43:16.505483 == TX Byte 0 ==
6739 12:43:16.509028 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6740 12:43:16.512808 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6741 12:43:16.515449 == TX Byte 1 ==
6742 12:43:16.519307 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6743 12:43:16.522672 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6744 12:43:16.522777
6745 12:43:16.522868 [DATLAT]
6746 12:43:16.526068 Freq=400, CH1 RK0
6747 12:43:16.526147
6748 12:43:16.526210 DATLAT Default: 0xf
6749 12:43:16.529594 0, 0xFFFF, sum = 0
6750 12:43:16.529674 1, 0xFFFF, sum = 0
6751 12:43:16.532230 2, 0xFFFF, sum = 0
6752 12:43:16.532366 3, 0xFFFF, sum = 0
6753 12:43:16.535711 4, 0xFFFF, sum = 0
6754 12:43:16.535792 5, 0xFFFF, sum = 0
6755 12:43:16.539155 6, 0xFFFF, sum = 0
6756 12:43:16.542648 7, 0xFFFF, sum = 0
6757 12:43:16.542729 8, 0xFFFF, sum = 0
6758 12:43:16.546116 9, 0xFFFF, sum = 0
6759 12:43:16.546196 10, 0xFFFF, sum = 0
6760 12:43:16.549479 11, 0xFFFF, sum = 0
6761 12:43:16.549560 12, 0xFFFF, sum = 0
6762 12:43:16.552937 13, 0x0, sum = 1
6763 12:43:16.553017 14, 0x0, sum = 2
6764 12:43:16.555697 15, 0x0, sum = 3
6765 12:43:16.555777 16, 0x0, sum = 4
6766 12:43:16.555841 best_step = 14
6767 12:43:16.555899
6768 12:43:16.559176 ==
6769 12:43:16.562528 Dram Type= 6, Freq= 0, CH_1, rank 0
6770 12:43:16.565943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6771 12:43:16.566022 ==
6772 12:43:16.566084 RX Vref Scan: 1
6773 12:43:16.566141
6774 12:43:16.569221 RX Vref 0 -> 0, step: 1
6775 12:43:16.569300
6776 12:43:16.572929 RX Delay -311 -> 252, step: 8
6777 12:43:16.573009
6778 12:43:16.576163 Set Vref, RX VrefLevel [Byte0]: 53
6779 12:43:16.579443 [Byte1]: 54
6780 12:43:16.582680
6781 12:43:16.582762 Final RX Vref Byte 0 = 53 to rank0
6782 12:43:16.585816 Final RX Vref Byte 1 = 54 to rank0
6783 12:43:16.589325 Final RX Vref Byte 0 = 53 to rank1
6784 12:43:16.592811 Final RX Vref Byte 1 = 54 to rank1==
6785 12:43:16.596142 Dram Type= 6, Freq= 0, CH_1, rank 0
6786 12:43:16.602557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6787 12:43:16.602637 ==
6788 12:43:16.602699 DQS Delay:
6789 12:43:16.606026 DQS0 = 32, DQS1 = 32
6790 12:43:16.606105 DQM Delay:
6791 12:43:16.606168 DQM0 = 13, DQM1 = 10
6792 12:43:16.609638 DQ Delay:
6793 12:43:16.612933 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6794 12:43:16.613013 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
6795 12:43:16.616204 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6796 12:43:16.619195 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
6797 12:43:16.619274
6798 12:43:16.622318
6799 12:43:16.629485 [DQSOSCAuto] RK0, (LSB)MR18= 0x93cc, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6800 12:43:16.632821 CH1 RK0: MR19=C0C, MR18=93CC
6801 12:43:16.638983 CH1_RK0: MR19=0xC0C, MR18=0x93CC, DQSOSC=384, MR23=63, INC=400, DEC=267
6802 12:43:16.639063 ==
6803 12:43:16.642236 Dram Type= 6, Freq= 0, CH_1, rank 1
6804 12:43:16.645805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6805 12:43:16.645885 ==
6806 12:43:16.649185 [Gating] SW mode calibration
6807 12:43:16.656089 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6808 12:43:16.662418 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6809 12:43:16.665902 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6810 12:43:16.669398 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6811 12:43:16.675519 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6812 12:43:16.678863 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6813 12:43:16.682308 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6814 12:43:16.685731 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6815 12:43:16.692548 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6816 12:43:16.695719 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 12:43:16.698815 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6818 12:43:16.701990 Total UI for P1: 0, mck2ui 16
6819 12:43:16.705782 best dqsien dly found for B0: ( 0, 14, 24)
6820 12:43:16.709198 Total UI for P1: 0, mck2ui 16
6821 12:43:16.712437 best dqsien dly found for B1: ( 0, 14, 24)
6822 12:43:16.715866 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6823 12:43:16.722018 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6824 12:43:16.722098
6825 12:43:16.725322 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6826 12:43:16.728896 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6827 12:43:16.732216 [Gating] SW calibration Done
6828 12:43:16.732344 ==
6829 12:43:16.735601 Dram Type= 6, Freq= 0, CH_1, rank 1
6830 12:43:16.739075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 12:43:16.739160 ==
6832 12:43:16.739224 RX Vref Scan: 0
6833 12:43:16.742095
6834 12:43:16.742175 RX Vref 0 -> 0, step: 1
6835 12:43:16.742238
6836 12:43:16.745598 RX Delay -410 -> 252, step: 16
6837 12:43:16.749038 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6838 12:43:16.755444 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6839 12:43:16.758853 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6840 12:43:16.762250 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6841 12:43:16.765074 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6842 12:43:16.771930 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6843 12:43:16.775538 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6844 12:43:16.778741 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6845 12:43:16.781669 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6846 12:43:16.788233 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6847 12:43:16.791648 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6848 12:43:16.795123 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6849 12:43:16.798628 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6850 12:43:16.805354 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6851 12:43:16.808547 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6852 12:43:16.811860 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6853 12:43:16.811965 ==
6854 12:43:16.815138 Dram Type= 6, Freq= 0, CH_1, rank 1
6855 12:43:16.822043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 12:43:16.822159 ==
6857 12:43:16.822228 DQS Delay:
6858 12:43:16.825317 DQS0 = 35, DQS1 = 35
6859 12:43:16.825397 DQM Delay:
6860 12:43:16.825459 DQM0 = 18, DQM1 = 15
6861 12:43:16.828625 DQ Delay:
6862 12:43:16.831365 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6863 12:43:16.834723 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6864 12:43:16.834794 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6865 12:43:16.838105 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6866 12:43:16.841561
6867 12:43:16.841663
6868 12:43:16.841748 ==
6869 12:43:16.845185 Dram Type= 6, Freq= 0, CH_1, rank 1
6870 12:43:16.848314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6871 12:43:16.848390 ==
6872 12:43:16.848454
6873 12:43:16.848511
6874 12:43:16.851710 TX Vref Scan disable
6875 12:43:16.851782 == TX Byte 0 ==
6876 12:43:16.855032 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6877 12:43:16.861228 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6878 12:43:16.861324 == TX Byte 1 ==
6879 12:43:16.864913 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6880 12:43:16.871153 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6881 12:43:16.871229 ==
6882 12:43:16.874667 Dram Type= 6, Freq= 0, CH_1, rank 1
6883 12:43:16.877975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6884 12:43:16.878054 ==
6885 12:43:16.878115
6886 12:43:16.878172
6887 12:43:16.881446 TX Vref Scan disable
6888 12:43:16.881516 == TX Byte 0 ==
6889 12:43:16.884939 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6890 12:43:16.891739 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6891 12:43:16.891822 == TX Byte 1 ==
6892 12:43:16.895090 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6893 12:43:16.901184 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6894 12:43:16.901283
6895 12:43:16.901358 [DATLAT]
6896 12:43:16.901421 Freq=400, CH1 RK1
6897 12:43:16.901478
6898 12:43:16.904707 DATLAT Default: 0xe
6899 12:43:16.908045 0, 0xFFFF, sum = 0
6900 12:43:16.908117 1, 0xFFFF, sum = 0
6901 12:43:16.911588 2, 0xFFFF, sum = 0
6902 12:43:16.911668 3, 0xFFFF, sum = 0
6903 12:43:16.915193 4, 0xFFFF, sum = 0
6904 12:43:16.915266 5, 0xFFFF, sum = 0
6905 12:43:16.918187 6, 0xFFFF, sum = 0
6906 12:43:16.918261 7, 0xFFFF, sum = 0
6907 12:43:16.921447 8, 0xFFFF, sum = 0
6908 12:43:16.921523 9, 0xFFFF, sum = 0
6909 12:43:16.924588 10, 0xFFFF, sum = 0
6910 12:43:16.924671 11, 0xFFFF, sum = 0
6911 12:43:16.927693 12, 0xFFFF, sum = 0
6912 12:43:16.927760 13, 0x0, sum = 1
6913 12:43:16.931110 14, 0x0, sum = 2
6914 12:43:16.931185 15, 0x0, sum = 3
6915 12:43:16.934401 16, 0x0, sum = 4
6916 12:43:16.934480 best_step = 14
6917 12:43:16.934541
6918 12:43:16.934598 ==
6919 12:43:16.937755 Dram Type= 6, Freq= 0, CH_1, rank 1
6920 12:43:16.941073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6921 12:43:16.944643 ==
6922 12:43:16.944714 RX Vref Scan: 0
6923 12:43:16.944784
6924 12:43:16.948072 RX Vref 0 -> 0, step: 1
6925 12:43:16.948170
6926 12:43:16.951300 RX Delay -311 -> 252, step: 8
6927 12:43:16.954586 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6928 12:43:16.961336 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6929 12:43:16.964795 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6930 12:43:16.967665 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6931 12:43:16.970941 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6932 12:43:16.977674 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6933 12:43:16.981369 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6934 12:43:16.984544 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6935 12:43:16.987545 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6936 12:43:16.994620 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6937 12:43:16.998025 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6938 12:43:17.001044 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6939 12:43:17.004620 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6940 12:43:17.011430 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6941 12:43:17.014221 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6942 12:43:17.017562 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6943 12:43:17.017638 ==
6944 12:43:17.021061 Dram Type= 6, Freq= 0, CH_1, rank 1
6945 12:43:17.027667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6946 12:43:17.027751 ==
6947 12:43:17.027814 DQS Delay:
6948 12:43:17.031037 DQS0 = 28, DQS1 = 36
6949 12:43:17.031117 DQM Delay:
6950 12:43:17.031180 DQM0 = 11, DQM1 = 14
6951 12:43:17.034309 DQ Delay:
6952 12:43:17.037652 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6953 12:43:17.037731 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6954 12:43:17.041095 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6955 12:43:17.044435 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6956 12:43:17.044514
6957 12:43:17.047859
6958 12:43:17.054224 [DQSOSCAuto] RK1, (LSB)MR18= 0xc555, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
6959 12:43:17.057635 CH1 RK1: MR19=C0C, MR18=C555
6960 12:43:17.064445 CH1_RK1: MR19=0xC0C, MR18=0xC555, DQSOSC=385, MR23=63, INC=398, DEC=265
6961 12:43:17.067575 [RxdqsGatingPostProcess] freq 400
6962 12:43:17.070824 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6963 12:43:17.074296 best DQS0 dly(2T, 0.5T) = (0, 10)
6964 12:43:17.077854 best DQS1 dly(2T, 0.5T) = (0, 10)
6965 12:43:17.081056 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6966 12:43:17.084511 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6967 12:43:17.087865 best DQS0 dly(2T, 0.5T) = (0, 10)
6968 12:43:17.090623 best DQS1 dly(2T, 0.5T) = (0, 10)
6969 12:43:17.094044 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6970 12:43:17.097365 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6971 12:43:17.100663 Pre-setting of DQS Precalculation
6972 12:43:17.103823 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6973 12:43:17.110752 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6974 12:43:17.121059 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6975 12:43:17.121155
6976 12:43:17.121244
6977 12:43:17.121323 [Calibration Summary] 800 Mbps
6978 12:43:17.123884 CH 0, Rank 0
6979 12:43:17.127510 SW Impedance : PASS
6980 12:43:17.127605 DUTY Scan : NO K
6981 12:43:17.130830 ZQ Calibration : PASS
6982 12:43:17.130919 Jitter Meter : NO K
6983 12:43:17.134084 CBT Training : PASS
6984 12:43:17.137423 Write leveling : PASS
6985 12:43:17.137531 RX DQS gating : PASS
6986 12:43:17.140891 RX DQ/DQS(RDDQC) : PASS
6987 12:43:17.144248 TX DQ/DQS : PASS
6988 12:43:17.144358 RX DATLAT : PASS
6989 12:43:17.147766 RX DQ/DQS(Engine): PASS
6990 12:43:17.150926 TX OE : NO K
6991 12:43:17.151005 All Pass.
6992 12:43:17.151070
6993 12:43:17.151169 CH 0, Rank 1
6994 12:43:17.154227 SW Impedance : PASS
6995 12:43:17.157647 DUTY Scan : NO K
6996 12:43:17.157721 ZQ Calibration : PASS
6997 12:43:17.161121 Jitter Meter : NO K
6998 12:43:17.163743 CBT Training : PASS
6999 12:43:17.163815 Write leveling : NO K
7000 12:43:17.167145 RX DQS gating : PASS
7001 12:43:17.167222 RX DQ/DQS(RDDQC) : PASS
7002 12:43:17.170552 TX DQ/DQS : PASS
7003 12:43:17.173824 RX DATLAT : PASS
7004 12:43:17.173897 RX DQ/DQS(Engine): PASS
7005 12:43:17.177174 TX OE : NO K
7006 12:43:17.177260 All Pass.
7007 12:43:17.177324
7008 12:43:17.180580 CH 1, Rank 0
7009 12:43:17.180659 SW Impedance : PASS
7010 12:43:17.183679 DUTY Scan : NO K
7011 12:43:17.187157 ZQ Calibration : PASS
7012 12:43:17.187283 Jitter Meter : NO K
7013 12:43:17.190676 CBT Training : PASS
7014 12:43:17.194156 Write leveling : PASS
7015 12:43:17.194236 RX DQS gating : PASS
7016 12:43:17.197585 RX DQ/DQS(RDDQC) : PASS
7017 12:43:17.200268 TX DQ/DQS : PASS
7018 12:43:17.200389 RX DATLAT : PASS
7019 12:43:17.203743 RX DQ/DQS(Engine): PASS
7020 12:43:17.207142 TX OE : NO K
7021 12:43:17.207222 All Pass.
7022 12:43:17.207283
7023 12:43:17.207341 CH 1, Rank 1
7024 12:43:17.210550 SW Impedance : PASS
7025 12:43:17.213962 DUTY Scan : NO K
7026 12:43:17.214041 ZQ Calibration : PASS
7027 12:43:17.217010 Jitter Meter : NO K
7028 12:43:17.217089 CBT Training : PASS
7029 12:43:17.220924 Write leveling : NO K
7030 12:43:17.224062 RX DQS gating : PASS
7031 12:43:17.224167 RX DQ/DQS(RDDQC) : PASS
7032 12:43:17.227043 TX DQ/DQS : PASS
7033 12:43:17.230618 RX DATLAT : PASS
7034 12:43:17.230697 RX DQ/DQS(Engine): PASS
7035 12:43:17.234147 TX OE : NO K
7036 12:43:17.234231 All Pass.
7037 12:43:17.234293
7038 12:43:17.237347 DramC Write-DBI off
7039 12:43:17.240655 PER_BANK_REFRESH: Hybrid Mode
7040 12:43:17.240761 TX_TRACKING: ON
7041 12:43:17.250237 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7042 12:43:17.253700 [FAST_K] Save calibration result to emmc
7043 12:43:17.256972 dramc_set_vcore_voltage set vcore to 725000
7044 12:43:17.260249 Read voltage for 1600, 0
7045 12:43:17.260369 Vio18 = 0
7046 12:43:17.260443 Vcore = 725000
7047 12:43:17.263673 Vdram = 0
7048 12:43:17.263752 Vddq = 0
7049 12:43:17.263814 Vmddr = 0
7050 12:43:17.270231 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7051 12:43:17.273726 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7052 12:43:17.277038 MEM_TYPE=3, freq_sel=13
7053 12:43:17.280457 sv_algorithm_assistance_LP4_3733
7054 12:43:17.283825 ============ PULL DRAM RESETB DOWN ============
7055 12:43:17.290382 ========== PULL DRAM RESETB DOWN end =========
7056 12:43:17.293811 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7057 12:43:17.296930 ===================================
7058 12:43:17.300605 LPDDR4 DRAM CONFIGURATION
7059 12:43:17.303420 ===================================
7060 12:43:17.303500 EX_ROW_EN[0] = 0x0
7061 12:43:17.306880 EX_ROW_EN[1] = 0x0
7062 12:43:17.306959 LP4Y_EN = 0x0
7063 12:43:17.310287 WORK_FSP = 0x1
7064 12:43:17.310366 WL = 0x5
7065 12:43:17.313756 RL = 0x5
7066 12:43:17.313835 BL = 0x2
7067 12:43:17.317112 RPST = 0x0
7068 12:43:17.317193 RD_PRE = 0x0
7069 12:43:17.319875 WR_PRE = 0x1
7070 12:43:17.319957 WR_PST = 0x1
7071 12:43:17.323398 DBI_WR = 0x0
7072 12:43:17.323467 DBI_RD = 0x0
7073 12:43:17.326896 OTF = 0x1
7074 12:43:17.330209 ===================================
7075 12:43:17.333331 ===================================
7076 12:43:17.333404 ANA top config
7077 12:43:17.336510 ===================================
7078 12:43:17.340243 DLL_ASYNC_EN = 0
7079 12:43:17.343232 ALL_SLAVE_EN = 0
7080 12:43:17.346926 NEW_RANK_MODE = 1
7081 12:43:17.347002 DLL_IDLE_MODE = 1
7082 12:43:17.349986 LP45_APHY_COMB_EN = 1
7083 12:43:17.353783 TX_ODT_DIS = 0
7084 12:43:17.357122 NEW_8X_MODE = 1
7085 12:43:17.359975 ===================================
7086 12:43:17.363436 ===================================
7087 12:43:17.366612 data_rate = 3200
7088 12:43:17.366718 CKR = 1
7089 12:43:17.369996 DQ_P2S_RATIO = 8
7090 12:43:17.373287 ===================================
7091 12:43:17.376962 CA_P2S_RATIO = 8
7092 12:43:17.379664 DQ_CA_OPEN = 0
7093 12:43:17.383757 DQ_SEMI_OPEN = 0
7094 12:43:17.386439 CA_SEMI_OPEN = 0
7095 12:43:17.386517 CA_FULL_RATE = 0
7096 12:43:17.389850 DQ_CKDIV4_EN = 0
7097 12:43:17.393315 CA_CKDIV4_EN = 0
7098 12:43:17.396729 CA_PREDIV_EN = 0
7099 12:43:17.400072 PH8_DLY = 12
7100 12:43:17.403488 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7101 12:43:17.403598 DQ_AAMCK_DIV = 4
7102 12:43:17.406832 CA_AAMCK_DIV = 4
7103 12:43:17.409923 CA_ADMCK_DIV = 4
7104 12:43:17.413178 DQ_TRACK_CA_EN = 0
7105 12:43:17.416590 CA_PICK = 1600
7106 12:43:17.419889 CA_MCKIO = 1600
7107 12:43:17.423389 MCKIO_SEMI = 0
7108 12:43:17.423458 PLL_FREQ = 3068
7109 12:43:17.426803 DQ_UI_PI_RATIO = 32
7110 12:43:17.430355 CA_UI_PI_RATIO = 0
7111 12:43:17.433086 ===================================
7112 12:43:17.436700 ===================================
7113 12:43:17.439927 memory_type:LPDDR4
7114 12:43:17.440001 GP_NUM : 10
7115 12:43:17.443428 SRAM_EN : 1
7116 12:43:17.446740 MD32_EN : 0
7117 12:43:17.449881 ===================================
7118 12:43:17.449958 [ANA_INIT] >>>>>>>>>>>>>>
7119 12:43:17.453371 <<<<<< [CONFIGURE PHASE]: ANA_TX
7120 12:43:17.456487 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7121 12:43:17.460094 ===================================
7122 12:43:17.463519 data_rate = 3200,PCW = 0X7600
7123 12:43:17.466665 ===================================
7124 12:43:17.469973 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7125 12:43:17.476661 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7126 12:43:17.479957 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7127 12:43:17.486631 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7128 12:43:17.489783 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7129 12:43:17.493495 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7130 12:43:17.493572 [ANA_INIT] flow start
7131 12:43:17.496915 [ANA_INIT] PLL >>>>>>>>
7132 12:43:17.499554 [ANA_INIT] PLL <<<<<<<<
7133 12:43:17.502991 [ANA_INIT] MIDPI >>>>>>>>
7134 12:43:17.503094 [ANA_INIT] MIDPI <<<<<<<<
7135 12:43:17.506266 [ANA_INIT] DLL >>>>>>>>
7136 12:43:17.509762 [ANA_INIT] DLL <<<<<<<<
7137 12:43:17.509846 [ANA_INIT] flow end
7138 12:43:17.513093 ============ LP4 DIFF to SE enter ============
7139 12:43:17.519667 ============ LP4 DIFF to SE exit ============
7140 12:43:17.519745 [ANA_INIT] <<<<<<<<<<<<<
7141 12:43:17.522963 [Flow] Enable top DCM control >>>>>
7142 12:43:17.526366 [Flow] Enable top DCM control <<<<<
7143 12:43:17.529793 Enable DLL master slave shuffle
7144 12:43:17.536053 ==============================================================
7145 12:43:17.536131 Gating Mode config
7146 12:43:17.542949 ==============================================================
7147 12:43:17.546418 Config description:
7148 12:43:17.556360 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7149 12:43:17.562620 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7150 12:43:17.565973 SELPH_MODE 0: By rank 1: By Phase
7151 12:43:17.572924 ==============================================================
7152 12:43:17.576137 GAT_TRACK_EN = 1
7153 12:43:17.579666 RX_GATING_MODE = 2
7154 12:43:17.579741 RX_GATING_TRACK_MODE = 2
7155 12:43:17.582696 SELPH_MODE = 1
7156 12:43:17.586010 PICG_EARLY_EN = 1
7157 12:43:17.589327 VALID_LAT_VALUE = 1
7158 12:43:17.595969 ==============================================================
7159 12:43:17.599214 Enter into Gating configuration >>>>
7160 12:43:17.602923 Exit from Gating configuration <<<<
7161 12:43:17.605963 Enter into DVFS_PRE_config >>>>>
7162 12:43:17.615795 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7163 12:43:17.619093 Exit from DVFS_PRE_config <<<<<
7164 12:43:17.623025 Enter into PICG configuration >>>>
7165 12:43:17.625716 Exit from PICG configuration <<<<
7166 12:43:17.628948 [RX_INPUT] configuration >>>>>
7167 12:43:17.632904 [RX_INPUT] configuration <<<<<
7168 12:43:17.635749 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7169 12:43:17.642569 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7170 12:43:17.649388 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7171 12:43:17.656180 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7172 12:43:17.659503 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7173 12:43:17.666219 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7174 12:43:17.669054 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7175 12:43:17.675869 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7176 12:43:17.679228 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7177 12:43:17.682597 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7178 12:43:17.685928 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7179 12:43:17.692652 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7180 12:43:17.695860 ===================================
7181 12:43:17.695939 LPDDR4 DRAM CONFIGURATION
7182 12:43:17.698955 ===================================
7183 12:43:17.702294 EX_ROW_EN[0] = 0x0
7184 12:43:17.705681 EX_ROW_EN[1] = 0x0
7185 12:43:17.705753 LP4Y_EN = 0x0
7186 12:43:17.708982 WORK_FSP = 0x1
7187 12:43:17.709059 WL = 0x5
7188 12:43:17.712256 RL = 0x5
7189 12:43:17.712368 BL = 0x2
7190 12:43:17.715963 RPST = 0x0
7191 12:43:17.716037 RD_PRE = 0x0
7192 12:43:17.719219 WR_PRE = 0x1
7193 12:43:17.719298 WR_PST = 0x1
7194 12:43:17.722319 DBI_WR = 0x0
7195 12:43:17.722392 DBI_RD = 0x0
7196 12:43:17.725970 OTF = 0x1
7197 12:43:17.728941 ===================================
7198 12:43:17.732152 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7199 12:43:17.735911 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7200 12:43:17.742294 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7201 12:43:17.745739 ===================================
7202 12:43:17.745810 LPDDR4 DRAM CONFIGURATION
7203 12:43:17.749084 ===================================
7204 12:43:17.752413 EX_ROW_EN[0] = 0x10
7205 12:43:17.752486 EX_ROW_EN[1] = 0x0
7206 12:43:17.756008 LP4Y_EN = 0x0
7207 12:43:17.759377 WORK_FSP = 0x1
7208 12:43:17.759452 WL = 0x5
7209 12:43:17.762021 RL = 0x5
7210 12:43:17.762093 BL = 0x2
7211 12:43:17.766062 RPST = 0x0
7212 12:43:17.766142 RD_PRE = 0x0
7213 12:43:17.769145 WR_PRE = 0x1
7214 12:43:17.769225 WR_PST = 0x1
7215 12:43:17.772384 DBI_WR = 0x0
7216 12:43:17.772464 DBI_RD = 0x0
7217 12:43:17.775890 OTF = 0x1
7218 12:43:17.778651 ===================================
7219 12:43:17.785350 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7220 12:43:17.785431 ==
7221 12:43:17.788798 Dram Type= 6, Freq= 0, CH_0, rank 0
7222 12:43:17.792260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7223 12:43:17.792383 ==
7224 12:43:17.795732 [Duty_Offset_Calibration]
7225 12:43:17.795811 B0:2 B1:1 CA:1
7226 12:43:17.795874
7227 12:43:17.798936 [DutyScan_Calibration_Flow] k_type=0
7228 12:43:17.809245
7229 12:43:17.809329 ==CLK 0==
7230 12:43:17.812390 Final CLK duty delay cell = 0
7231 12:43:17.815873 [0] MAX Duty = 5187%(X100), DQS PI = 24
7232 12:43:17.819372 [0] MIN Duty = 4907%(X100), DQS PI = 0
7233 12:43:17.819476 [0] AVG Duty = 5047%(X100)
7234 12:43:17.822889
7235 12:43:17.822968 CH0 CLK Duty spec in!! Max-Min= 280%
7236 12:43:17.829199 [DutyScan_Calibration_Flow] ====Done====
7237 12:43:17.829307
7238 12:43:17.832610 [DutyScan_Calibration_Flow] k_type=1
7239 12:43:17.848054
7240 12:43:17.848134 ==DQS 0 ==
7241 12:43:17.851761 Final DQS duty delay cell = -4
7242 12:43:17.854775 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7243 12:43:17.858456 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7244 12:43:17.861473 [-4] AVG Duty = 4891%(X100)
7245 12:43:17.861553
7246 12:43:17.861615 ==DQS 1 ==
7247 12:43:17.864927 Final DQS duty delay cell = 0
7248 12:43:17.868312 [0] MAX Duty = 5187%(X100), DQS PI = 4
7249 12:43:17.871667 [0] MIN Duty = 5062%(X100), DQS PI = 30
7250 12:43:17.874868 [0] AVG Duty = 5124%(X100)
7251 12:43:17.874947
7252 12:43:17.878356 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7253 12:43:17.878436
7254 12:43:17.881768 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7255 12:43:17.884961 [DutyScan_Calibration_Flow] ====Done====
7256 12:43:17.885047
7257 12:43:17.888459 [DutyScan_Calibration_Flow] k_type=3
7258 12:43:17.905648
7259 12:43:17.905732 ==DQM 0 ==
7260 12:43:17.908972 Final DQM duty delay cell = 0
7261 12:43:17.911893 [0] MAX Duty = 5187%(X100), DQS PI = 26
7262 12:43:17.915319 [0] MIN Duty = 4875%(X100), DQS PI = 60
7263 12:43:17.918616 [0] AVG Duty = 5031%(X100)
7264 12:43:17.918693
7265 12:43:17.918753 ==DQM 1 ==
7266 12:43:17.922291 Final DQM duty delay cell = 0
7267 12:43:17.925564 [0] MAX Duty = 5187%(X100), DQS PI = 2
7268 12:43:17.928598 [0] MIN Duty = 5031%(X100), DQS PI = 48
7269 12:43:17.932008 [0] AVG Duty = 5109%(X100)
7270 12:43:17.932081
7271 12:43:17.935510 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7272 12:43:17.935581
7273 12:43:17.938921 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7274 12:43:17.942280 [DutyScan_Calibration_Flow] ====Done====
7275 12:43:17.942352
7276 12:43:17.945511 [DutyScan_Calibration_Flow] k_type=2
7277 12:43:17.962612
7278 12:43:17.962688 ==DQ 0 ==
7279 12:43:17.965916 Final DQ duty delay cell = 0
7280 12:43:17.969011 [0] MAX Duty = 5062%(X100), DQS PI = 24
7281 12:43:17.972841 [0] MIN Duty = 4907%(X100), DQS PI = 0
7282 12:43:17.972915 [0] AVG Duty = 4984%(X100)
7283 12:43:17.976023
7284 12:43:17.976093 ==DQ 1 ==
7285 12:43:17.979398 Final DQ duty delay cell = 0
7286 12:43:17.982792 [0] MAX Duty = 5125%(X100), DQS PI = 6
7287 12:43:17.985663 [0] MIN Duty = 4938%(X100), DQS PI = 34
7288 12:43:17.985744 [0] AVG Duty = 5031%(X100)
7289 12:43:17.985807
7290 12:43:17.988908 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7291 12:43:17.992243
7292 12:43:17.995700 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7293 12:43:17.999172 [DutyScan_Calibration_Flow] ====Done====
7294 12:43:17.999245 ==
7295 12:43:18.002693 Dram Type= 6, Freq= 0, CH_1, rank 0
7296 12:43:18.005996 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7297 12:43:18.006068 ==
7298 12:43:18.009376 [Duty_Offset_Calibration]
7299 12:43:18.009448 B0:1 B1:0 CA:0
7300 12:43:18.009508
7301 12:43:18.012173 [DutyScan_Calibration_Flow] k_type=0
7302 12:43:18.022377
7303 12:43:18.022452 ==CLK 0==
7304 12:43:18.025706 Final CLK duty delay cell = -4
7305 12:43:18.028531 [-4] MAX Duty = 5000%(X100), DQS PI = 24
7306 12:43:18.032274 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7307 12:43:18.035436 [-4] AVG Duty = 4922%(X100)
7308 12:43:18.035506
7309 12:43:18.038640 CH1 CLK Duty spec in!! Max-Min= 156%
7310 12:43:18.041812 [DutyScan_Calibration_Flow] ====Done====
7311 12:43:18.041886
7312 12:43:18.045237 [DutyScan_Calibration_Flow] k_type=1
7313 12:43:18.062129
7314 12:43:18.062212 ==DQS 0 ==
7315 12:43:18.065261 Final DQS duty delay cell = 0
7316 12:43:18.068806 [0] MAX Duty = 5094%(X100), DQS PI = 16
7317 12:43:18.071884 [0] MIN Duty = 4844%(X100), DQS PI = 48
7318 12:43:18.075753 [0] AVG Duty = 4969%(X100)
7319 12:43:18.075837
7320 12:43:18.075904 ==DQS 1 ==
7321 12:43:18.078881 Final DQS duty delay cell = 0
7322 12:43:18.082144 [0] MAX Duty = 5249%(X100), DQS PI = 18
7323 12:43:18.085232 [0] MIN Duty = 4938%(X100), DQS PI = 8
7324 12:43:18.088386 [0] AVG Duty = 5093%(X100)
7325 12:43:18.088461
7326 12:43:18.091987 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7327 12:43:18.092067
7328 12:43:18.095447 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7329 12:43:18.098272 [DutyScan_Calibration_Flow] ====Done====
7330 12:43:18.098345
7331 12:43:18.101672 [DutyScan_Calibration_Flow] k_type=3
7332 12:43:18.119213
7333 12:43:18.119291 ==DQM 0 ==
7334 12:43:18.122046 Final DQM duty delay cell = 0
7335 12:43:18.125544 [0] MAX Duty = 5218%(X100), DQS PI = 18
7336 12:43:18.128944 [0] MIN Duty = 4969%(X100), DQS PI = 48
7337 12:43:18.132429 [0] AVG Duty = 5093%(X100)
7338 12:43:18.132508
7339 12:43:18.132569 ==DQM 1 ==
7340 12:43:18.135777 Final DQM duty delay cell = 0
7341 12:43:18.139122 [0] MAX Duty = 5093%(X100), DQS PI = 16
7342 12:43:18.142291 [0] MIN Duty = 4938%(X100), DQS PI = 6
7343 12:43:18.142375 [0] AVG Duty = 5015%(X100)
7344 12:43:18.145942
7345 12:43:18.148961 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7346 12:43:18.149045
7347 12:43:18.152278 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7348 12:43:18.155683 [DutyScan_Calibration_Flow] ====Done====
7349 12:43:18.155765
7350 12:43:18.159098 [DutyScan_Calibration_Flow] k_type=2
7351 12:43:18.174828
7352 12:43:18.174910 ==DQ 0 ==
7353 12:43:18.178672 Final DQ duty delay cell = -4
7354 12:43:18.181841 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7355 12:43:18.184836 [-4] MIN Duty = 4875%(X100), DQS PI = 44
7356 12:43:18.188672 [-4] AVG Duty = 4953%(X100)
7357 12:43:18.188755
7358 12:43:18.188839 ==DQ 1 ==
7359 12:43:18.191631 Final DQ duty delay cell = 0
7360 12:43:18.194898 [0] MAX Duty = 5125%(X100), DQS PI = 18
7361 12:43:18.198260 [0] MIN Duty = 4938%(X100), DQS PI = 8
7362 12:43:18.201407 [0] AVG Duty = 5031%(X100)
7363 12:43:18.201489
7364 12:43:18.205105 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7365 12:43:18.205188
7366 12:43:18.208540 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7367 12:43:18.211350 [DutyScan_Calibration_Flow] ====Done====
7368 12:43:18.214728 nWR fixed to 30
7369 12:43:18.218095 [ModeRegInit_LP4] CH0 RK0
7370 12:43:18.218177 [ModeRegInit_LP4] CH0 RK1
7371 12:43:18.221476 [ModeRegInit_LP4] CH1 RK0
7372 12:43:18.224952 [ModeRegInit_LP4] CH1 RK1
7373 12:43:18.225035 match AC timing 5
7374 12:43:18.231734 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7375 12:43:18.235219 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7376 12:43:18.237921 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7377 12:43:18.244960 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7378 12:43:18.248324 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7379 12:43:18.248420 [MiockJmeterHQA]
7380 12:43:18.248503
7381 12:43:18.251673 [DramcMiockJmeter] u1RxGatingPI = 0
7382 12:43:18.254790 0 : 4255, 4029
7383 12:43:18.254875 4 : 4257, 4027
7384 12:43:18.257859 8 : 4255, 4030
7385 12:43:18.257943 12 : 4252, 4027
7386 12:43:18.258029 16 : 4255, 4029
7387 12:43:18.261598 20 : 4363, 4138
7388 12:43:18.261681 24 : 4253, 4026
7389 12:43:18.264899 28 : 4252, 4027
7390 12:43:18.264983 32 : 4252, 4027
7391 12:43:18.268258 36 : 4255, 4029
7392 12:43:18.268349 40 : 4252, 4027
7393 12:43:18.270981 44 : 4363, 4137
7394 12:43:18.271065 48 : 4363, 4137
7395 12:43:18.271150 52 : 4252, 4027
7396 12:43:18.274373 56 : 4252, 4027
7397 12:43:18.274457 60 : 4252, 4027
7398 12:43:18.277872 64 : 4252, 4027
7399 12:43:18.277956 68 : 4252, 4030
7400 12:43:18.281233 72 : 4360, 4137
7401 12:43:18.281316 76 : 4252, 4026
7402 12:43:18.284657 80 : 4249, 4027
7403 12:43:18.284741 84 : 4252, 4027
7404 12:43:18.284826 88 : 4253, 41
7405 12:43:18.288067 92 : 4250, 0
7406 12:43:18.288151 96 : 4363, 0
7407 12:43:18.290769 100 : 4252, 0
7408 12:43:18.290853 104 : 4250, 0
7409 12:43:18.290939 108 : 4252, 0
7410 12:43:18.294624 112 : 4361, 0
7411 12:43:18.294710 116 : 4361, 0
7412 12:43:18.294793 120 : 4250, 0
7413 12:43:18.297805 124 : 4249, 0
7414 12:43:18.297888 128 : 4250, 0
7415 12:43:18.301233 132 : 4252, 0
7416 12:43:18.301317 136 : 4249, 0
7417 12:43:18.301403 140 : 4361, 0
7418 12:43:18.304523 144 : 4250, 0
7419 12:43:18.304607 148 : 4250, 0
7420 12:43:18.308023 152 : 4250, 0
7421 12:43:18.308107 156 : 4250, 0
7422 12:43:18.308208 160 : 4360, 0
7423 12:43:18.310918 164 : 4360, 0
7424 12:43:18.311001 168 : 4363, 0
7425 12:43:18.314645 172 : 4250, 0
7426 12:43:18.314729 176 : 4360, 0
7427 12:43:18.314815 180 : 4250, 0
7428 12:43:18.317543 184 : 4250, 0
7429 12:43:18.317627 188 : 4249, 0
7430 12:43:18.317711 192 : 4361, 0
7431 12:43:18.320844 196 : 4360, 0
7432 12:43:18.320927 200 : 4250, 0
7433 12:43:18.324317 204 : 4250, 1340
7434 12:43:18.324414 208 : 4250, 4001
7435 12:43:18.327357 212 : 4250, 4026
7436 12:43:18.327441 216 : 4250, 4026
7437 12:43:18.330940 220 : 4250, 4027
7438 12:43:18.331024 224 : 4250, 4027
7439 12:43:18.334388 228 : 4361, 4137
7440 12:43:18.334472 232 : 4250, 4027
7441 12:43:18.334557 236 : 4250, 4027
7442 12:43:18.337909 240 : 4361, 4138
7443 12:43:18.337993 244 : 4249, 4027
7444 12:43:18.340682 248 : 4250, 4026
7445 12:43:18.340766 252 : 4363, 4140
7446 12:43:18.344085 256 : 4250, 4027
7447 12:43:18.344169 260 : 4249, 4027
7448 12:43:18.347659 264 : 4250, 4026
7449 12:43:18.347743 268 : 4253, 4029
7450 12:43:18.351011 272 : 4250, 4027
7451 12:43:18.351098 276 : 4249, 4027
7452 12:43:18.353832 280 : 4360, 4137
7453 12:43:18.353914 284 : 4250, 4027
7454 12:43:18.357248 288 : 4250, 4027
7455 12:43:18.357328 292 : 4361, 4138
7456 12:43:18.357401 296 : 4250, 4027
7457 12:43:18.360611 300 : 4250, 4026
7458 12:43:18.360719 304 : 4363, 4140
7459 12:43:18.363821 308 : 4250, 3980
7460 12:43:18.363900 312 : 4250, 2126
7461 12:43:18.367180 316 : 4250, 2
7462 12:43:18.367260
7463 12:43:18.367331 MIOCK jitter meter ch=0
7464 12:43:18.370969
7465 12:43:18.371048 1T = (316-88) = 228 dly cells
7466 12:43:18.377075 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7467 12:43:18.377155 ==
7468 12:43:18.380785 Dram Type= 6, Freq= 0, CH_0, rank 0
7469 12:43:18.384253 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7470 12:43:18.384381 ==
7471 12:43:18.390919 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7472 12:43:18.393774 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7473 12:43:18.397190 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7474 12:43:18.403728 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7475 12:43:18.414165 [CA 0] Center 43 (13~74) winsize 62
7476 12:43:18.417349 [CA 1] Center 43 (13~74) winsize 62
7477 12:43:18.420818 [CA 2] Center 38 (9~68) winsize 60
7478 12:43:18.424080 [CA 3] Center 38 (8~68) winsize 61
7479 12:43:18.427500 [CA 4] Center 36 (7~66) winsize 60
7480 12:43:18.430197 [CA 5] Center 36 (7~65) winsize 59
7481 12:43:18.430282
7482 12:43:18.433768 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7483 12:43:18.433848
7484 12:43:18.437317 [CATrainingPosCal] consider 1 rank data
7485 12:43:18.440808 u2DelayCellTimex100 = 285/100 ps
7486 12:43:18.443922 CA0 delay=43 (13~74),Diff = 7 PI (23 cell)
7487 12:43:18.450967 CA1 delay=43 (13~74),Diff = 7 PI (23 cell)
7488 12:43:18.453771 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7489 12:43:18.457287 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7490 12:43:18.460693 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7491 12:43:18.463634 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7492 12:43:18.463739
7493 12:43:18.467006 CA PerBit enable=1, Macro0, CA PI delay=36
7494 12:43:18.467087
7495 12:43:18.470278 [CBTSetCACLKResult] CA Dly = 36
7496 12:43:18.473790 CS Dly: 9 (0~40)
7497 12:43:18.476942 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7498 12:43:18.480407 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7499 12:43:18.480487 ==
7500 12:43:18.483748 Dram Type= 6, Freq= 0, CH_0, rank 1
7501 12:43:18.487170 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7502 12:43:18.487249 ==
7503 12:43:18.493344 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7504 12:43:18.496659 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7505 12:43:18.503466 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7506 12:43:18.506947 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7507 12:43:18.516983 [CA 0] Center 42 (12~73) winsize 62
7508 12:43:18.520654 [CA 1] Center 42 (12~73) winsize 62
7509 12:43:18.524015 [CA 2] Center 38 (8~68) winsize 61
7510 12:43:18.526855 [CA 3] Center 37 (7~67) winsize 61
7511 12:43:18.530586 [CA 4] Center 36 (6~66) winsize 61
7512 12:43:18.533981 [CA 5] Center 35 (5~65) winsize 61
7513 12:43:18.534061
7514 12:43:18.536759 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7515 12:43:18.536839
7516 12:43:18.540212 [CATrainingPosCal] consider 2 rank data
7517 12:43:18.543559 u2DelayCellTimex100 = 285/100 ps
7518 12:43:18.547025 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7519 12:43:18.553356 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7520 12:43:18.557155 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7521 12:43:18.560151 CA3 delay=37 (8~67),Diff = 1 PI (3 cell)
7522 12:43:18.563487 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7523 12:43:18.566865 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7524 12:43:18.566944
7525 12:43:18.570341 CA PerBit enable=1, Macro0, CA PI delay=36
7526 12:43:18.570421
7527 12:43:18.573719 [CBTSetCACLKResult] CA Dly = 36
7528 12:43:18.576612 CS Dly: 10 (0~42)
7529 12:43:18.579975 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7530 12:43:18.583283 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7531 12:43:18.583363
7532 12:43:18.586702 ----->DramcWriteLeveling(PI) begin...
7533 12:43:18.586782 ==
7534 12:43:18.590216 Dram Type= 6, Freq= 0, CH_0, rank 0
7535 12:43:18.596554 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7536 12:43:18.596660 ==
7537 12:43:18.599861 Write leveling (Byte 0): 36 => 36
7538 12:43:18.599968 Write leveling (Byte 1): 26 => 26
7539 12:43:18.603232 DramcWriteLeveling(PI) end<-----
7540 12:43:18.603311
7541 12:43:18.603373 ==
7542 12:43:18.606938 Dram Type= 6, Freq= 0, CH_0, rank 0
7543 12:43:18.613546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7544 12:43:18.613673 ==
7545 12:43:18.616672 [Gating] SW mode calibration
7546 12:43:18.623305 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7547 12:43:18.626606 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7548 12:43:18.633186 1 4 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7549 12:43:18.636372 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7550 12:43:18.640163 1 4 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
7551 12:43:18.646358 1 4 12 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
7552 12:43:18.649775 1 4 16 | B1->B0 | 2424 3534 | 1 1 | (1 1) (1 1)
7553 12:43:18.653227 1 4 20 | B1->B0 | 3434 3535 | 0 0 | (0 0) (0 0)
7554 12:43:18.656768 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7555 12:43:18.663599 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7556 12:43:18.666724 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
7557 12:43:18.669847 1 5 4 | B1->B0 | 3434 3534 | 1 1 | (1 1) (0 0)
7558 12:43:18.676629 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
7559 12:43:18.680080 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7560 12:43:18.683494 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7561 12:43:18.689974 1 5 20 | B1->B0 | 2626 2726 | 1 1 | (1 0) (0 0)
7562 12:43:18.693509 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7563 12:43:18.696198 1 5 28 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
7564 12:43:18.703120 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7565 12:43:18.706582 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 12:43:18.709960 1 6 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
7567 12:43:18.716539 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7568 12:43:18.719890 1 6 16 | B1->B0 | 2f2f 4646 | 1 0 | (0 0) (0 0)
7569 12:43:18.723095 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7570 12:43:18.729653 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7571 12:43:18.732722 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7572 12:43:18.735811 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7573 12:43:18.742587 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 12:43:18.746275 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7575 12:43:18.749426 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7576 12:43:18.755972 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7577 12:43:18.759595 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7578 12:43:18.762937 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 12:43:18.769242 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 12:43:18.772799 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 12:43:18.776421 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 12:43:18.782778 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 12:43:18.785841 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 12:43:18.789004 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 12:43:18.795604 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 12:43:18.799112 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 12:43:18.802556 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 12:43:18.808848 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 12:43:18.812377 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 12:43:18.815668 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7591 12:43:18.822533 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7592 12:43:18.825405 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7593 12:43:18.828844 Total UI for P1: 0, mck2ui 16
7594 12:43:18.832177 best dqsien dly found for B0: ( 1, 9, 10)
7595 12:43:18.835562 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7596 12:43:18.838884 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7597 12:43:18.842152 Total UI for P1: 0, mck2ui 16
7598 12:43:18.845310 best dqsien dly found for B1: ( 1, 9, 20)
7599 12:43:18.848707 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7600 12:43:18.855241 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7601 12:43:18.855321
7602 12:43:18.858562 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7603 12:43:18.862207 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7604 12:43:18.865494 [Gating] SW calibration Done
7605 12:43:18.865573 ==
7606 12:43:18.868760 Dram Type= 6, Freq= 0, CH_0, rank 0
7607 12:43:18.872229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7608 12:43:18.872333 ==
7609 12:43:18.875650 RX Vref Scan: 0
7610 12:43:18.875729
7611 12:43:18.875791 RX Vref 0 -> 0, step: 1
7612 12:43:18.875849
7613 12:43:18.878560 RX Delay 0 -> 252, step: 8
7614 12:43:18.881931 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7615 12:43:18.888867 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7616 12:43:18.892189 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7617 12:43:18.895563 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7618 12:43:18.898248 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7619 12:43:18.901474 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7620 12:43:18.905458 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7621 12:43:18.912032 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7622 12:43:18.914836 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7623 12:43:18.918277 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7624 12:43:18.921787 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7625 12:43:18.925188 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7626 12:43:18.931811 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7627 12:43:18.935237 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7628 12:43:18.938546 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7629 12:43:18.941281 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7630 12:43:18.941360 ==
7631 12:43:18.944759 Dram Type= 6, Freq= 0, CH_0, rank 0
7632 12:43:18.951281 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7633 12:43:18.951360 ==
7634 12:43:18.951422 DQS Delay:
7635 12:43:18.955614 DQS0 = 0, DQS1 = 0
7636 12:43:18.955693 DQM Delay:
7637 12:43:18.955756 DQM0 = 136, DQM1 = 130
7638 12:43:18.958452 DQ Delay:
7639 12:43:18.961945 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7640 12:43:18.964680 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7641 12:43:18.967945 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7642 12:43:18.971172 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =135
7643 12:43:18.971271
7644 12:43:18.971360
7645 12:43:18.971446 ==
7646 12:43:18.974448 Dram Type= 6, Freq= 0, CH_0, rank 0
7647 12:43:18.981514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7648 12:43:18.981594 ==
7649 12:43:18.981657
7650 12:43:18.981714
7651 12:43:18.981770 TX Vref Scan disable
7652 12:43:18.984921 == TX Byte 0 ==
7653 12:43:18.988439 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7654 12:43:18.991265 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7655 12:43:18.994577 == TX Byte 1 ==
7656 12:43:18.998042 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7657 12:43:19.001503 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7658 12:43:19.004801 ==
7659 12:43:19.008065 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 12:43:19.011509 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 12:43:19.011589 ==
7662 12:43:19.023250
7663 12:43:19.026672 TX Vref early break, caculate TX vref
7664 12:43:19.029606 TX Vref=16, minBit 7, minWin=22, winSum=377
7665 12:43:19.033043 TX Vref=18, minBit 4, minWin=23, winSum=386
7666 12:43:19.036712 TX Vref=20, minBit 3, minWin=24, winSum=401
7667 12:43:19.039971 TX Vref=22, minBit 0, minWin=24, winSum=410
7668 12:43:19.043102 TX Vref=24, minBit 7, minWin=24, winSum=411
7669 12:43:19.049967 TX Vref=26, minBit 1, minWin=25, winSum=419
7670 12:43:19.053373 TX Vref=28, minBit 2, minWin=25, winSum=426
7671 12:43:19.056689 TX Vref=30, minBit 1, minWin=25, winSum=414
7672 12:43:19.059965 TX Vref=32, minBit 6, minWin=23, winSum=402
7673 12:43:19.066427 [TxChooseVref] Worse bit 2, Min win 25, Win sum 426, Final Vref 28
7674 12:43:19.066508
7675 12:43:19.069996 Final TX Range 0 Vref 28
7676 12:43:19.070081
7677 12:43:19.070145 ==
7678 12:43:19.073493 Dram Type= 6, Freq= 0, CH_0, rank 0
7679 12:43:19.076261 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7680 12:43:19.076376 ==
7681 12:43:19.076439
7682 12:43:19.076496
7683 12:43:19.079777 TX Vref Scan disable
7684 12:43:19.083119 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7685 12:43:19.086483 == TX Byte 0 ==
7686 12:43:19.090215 u2DelayCellOfst[0]=13 cells (4 PI)
7687 12:43:19.093422 u2DelayCellOfst[1]=13 cells (4 PI)
7688 12:43:19.096908 u2DelayCellOfst[2]=10 cells (3 PI)
7689 12:43:19.099649 u2DelayCellOfst[3]=6 cells (2 PI)
7690 12:43:19.099729 u2DelayCellOfst[4]=6 cells (2 PI)
7691 12:43:19.103190 u2DelayCellOfst[5]=0 cells (0 PI)
7692 12:43:19.106531 u2DelayCellOfst[6]=17 cells (5 PI)
7693 12:43:19.109932 u2DelayCellOfst[7]=17 cells (5 PI)
7694 12:43:19.116582 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7695 12:43:19.120042 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7696 12:43:19.120121 == TX Byte 1 ==
7697 12:43:19.123474 u2DelayCellOfst[8]=0 cells (0 PI)
7698 12:43:19.126237 u2DelayCellOfst[9]=0 cells (0 PI)
7699 12:43:19.129690 u2DelayCellOfst[10]=10 cells (3 PI)
7700 12:43:19.133077 u2DelayCellOfst[11]=3 cells (1 PI)
7701 12:43:19.136272 u2DelayCellOfst[12]=10 cells (3 PI)
7702 12:43:19.140089 u2DelayCellOfst[13]=10 cells (3 PI)
7703 12:43:19.143189 u2DelayCellOfst[14]=17 cells (5 PI)
7704 12:43:19.146266 u2DelayCellOfst[15]=10 cells (3 PI)
7705 12:43:19.150117 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7706 12:43:19.153146 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7707 12:43:19.156624 DramC Write-DBI on
7708 12:43:19.156702 ==
7709 12:43:19.160001 Dram Type= 6, Freq= 0, CH_0, rank 0
7710 12:43:19.162956 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7711 12:43:19.163132 ==
7712 12:43:19.163204
7713 12:43:19.163268
7714 12:43:19.166148 TX Vref Scan disable
7715 12:43:19.169996 == TX Byte 0 ==
7716 12:43:19.173101 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7717 12:43:19.173185 == TX Byte 1 ==
7718 12:43:19.179692 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7719 12:43:19.179772 DramC Write-DBI off
7720 12:43:19.179835
7721 12:43:19.183139 [DATLAT]
7722 12:43:19.183220 Freq=1600, CH0 RK0
7723 12:43:19.183283
7724 12:43:19.186534 DATLAT Default: 0xf
7725 12:43:19.186614 0, 0xFFFF, sum = 0
7726 12:43:19.189401 1, 0xFFFF, sum = 0
7727 12:43:19.189482 2, 0xFFFF, sum = 0
7728 12:43:19.192980 3, 0xFFFF, sum = 0
7729 12:43:19.193062 4, 0xFFFF, sum = 0
7730 12:43:19.196164 5, 0xFFFF, sum = 0
7731 12:43:19.196302 6, 0xFFFF, sum = 0
7732 12:43:19.199472 7, 0xFFFF, sum = 0
7733 12:43:19.199554 8, 0xFFFF, sum = 0
7734 12:43:19.202853 9, 0xFFFF, sum = 0
7735 12:43:19.202935 10, 0xFFFF, sum = 0
7736 12:43:19.206197 11, 0xFFFF, sum = 0
7737 12:43:19.209737 12, 0xFFFF, sum = 0
7738 12:43:19.209819 13, 0xFFFF, sum = 0
7739 12:43:19.213063 14, 0x0, sum = 1
7740 12:43:19.213145 15, 0x0, sum = 2
7741 12:43:19.213210 16, 0x0, sum = 3
7742 12:43:19.216442 17, 0x0, sum = 4
7743 12:43:19.216557 best_step = 15
7744 12:43:19.216620
7745 12:43:19.219861 ==
7746 12:43:19.219941 Dram Type= 6, Freq= 0, CH_0, rank 0
7747 12:43:19.226072 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7748 12:43:19.226154 ==
7749 12:43:19.226217 RX Vref Scan: 1
7750 12:43:19.226277
7751 12:43:19.229463 Set Vref Range= 24 -> 127
7752 12:43:19.229544
7753 12:43:19.233024 RX Vref 24 -> 127, step: 1
7754 12:43:19.233105
7755 12:43:19.236547 RX Delay 19 -> 252, step: 4
7756 12:43:19.236628
7757 12:43:19.239218 Set Vref, RX VrefLevel [Byte0]: 24
7758 12:43:19.242694 [Byte1]: 24
7759 12:43:19.242775
7760 12:43:19.246018 Set Vref, RX VrefLevel [Byte0]: 25
7761 12:43:19.249305 [Byte1]: 25
7762 12:43:19.249386
7763 12:43:19.253190 Set Vref, RX VrefLevel [Byte0]: 26
7764 12:43:19.256505 [Byte1]: 26
7765 12:43:19.256586
7766 12:43:19.259246 Set Vref, RX VrefLevel [Byte0]: 27
7767 12:43:19.262710 [Byte1]: 27
7768 12:43:19.266706
7769 12:43:19.266786 Set Vref, RX VrefLevel [Byte0]: 28
7770 12:43:19.269984 [Byte1]: 28
7771 12:43:19.274178
7772 12:43:19.274259 Set Vref, RX VrefLevel [Byte0]: 29
7773 12:43:19.277692 [Byte1]: 29
7774 12:43:19.282145
7775 12:43:19.282229 Set Vref, RX VrefLevel [Byte0]: 30
7776 12:43:19.285394 [Byte1]: 30
7777 12:43:19.289776
7778 12:43:19.289856 Set Vref, RX VrefLevel [Byte0]: 31
7779 12:43:19.292862 [Byte1]: 31
7780 12:43:19.297194
7781 12:43:19.297275 Set Vref, RX VrefLevel [Byte0]: 32
7782 12:43:19.300658 [Byte1]: 32
7783 12:43:19.304644
7784 12:43:19.304747 Set Vref, RX VrefLevel [Byte0]: 33
7785 12:43:19.308163 [Byte1]: 33
7786 12:43:19.312167
7787 12:43:19.312265 Set Vref, RX VrefLevel [Byte0]: 34
7788 12:43:19.315473 [Byte1]: 34
7789 12:43:19.320104
7790 12:43:19.320210 Set Vref, RX VrefLevel [Byte0]: 35
7791 12:43:19.322881 [Byte1]: 35
7792 12:43:19.327763
7793 12:43:19.327864 Set Vref, RX VrefLevel [Byte0]: 36
7794 12:43:19.331153 [Byte1]: 36
7795 12:43:19.334692
7796 12:43:19.334787 Set Vref, RX VrefLevel [Byte0]: 37
7797 12:43:19.338112 [Byte1]: 37
7798 12:43:19.342927
7799 12:43:19.343034 Set Vref, RX VrefLevel [Byte0]: 38
7800 12:43:19.345682 [Byte1]: 38
7801 12:43:19.350278
7802 12:43:19.350363 Set Vref, RX VrefLevel [Byte0]: 39
7803 12:43:19.353787 [Byte1]: 39
7804 12:43:19.357416
7805 12:43:19.357490 Set Vref, RX VrefLevel [Byte0]: 40
7806 12:43:19.360769 [Byte1]: 40
7807 12:43:19.365573
7808 12:43:19.365653 Set Vref, RX VrefLevel [Byte0]: 41
7809 12:43:19.368310 [Byte1]: 41
7810 12:43:19.373177
7811 12:43:19.373257 Set Vref, RX VrefLevel [Byte0]: 42
7812 12:43:19.375838 [Byte1]: 42
7813 12:43:19.380875
7814 12:43:19.380955 Set Vref, RX VrefLevel [Byte0]: 43
7815 12:43:19.383581 [Byte1]: 43
7816 12:43:19.388171
7817 12:43:19.388251 Set Vref, RX VrefLevel [Byte0]: 44
7818 12:43:19.391430 [Byte1]: 44
7819 12:43:19.395617
7820 12:43:19.395698 Set Vref, RX VrefLevel [Byte0]: 45
7821 12:43:19.398666 [Byte1]: 45
7822 12:43:19.402846
7823 12:43:19.402927 Set Vref, RX VrefLevel [Byte0]: 46
7824 12:43:19.406355 [Byte1]: 46
7825 12:43:19.410770
7826 12:43:19.410851 Set Vref, RX VrefLevel [Byte0]: 47
7827 12:43:19.413786 [Byte1]: 47
7828 12:43:19.418176
7829 12:43:19.418257 Set Vref, RX VrefLevel [Byte0]: 48
7830 12:43:19.421620 [Byte1]: 48
7831 12:43:19.425673
7832 12:43:19.425753 Set Vref, RX VrefLevel [Byte0]: 49
7833 12:43:19.429345 [Byte1]: 49
7834 12:43:19.433408
7835 12:43:19.433489 Set Vref, RX VrefLevel [Byte0]: 50
7836 12:43:19.436487 [Byte1]: 50
7837 12:43:19.441220
7838 12:43:19.441304 Set Vref, RX VrefLevel [Byte0]: 51
7839 12:43:19.444056 [Byte1]: 51
7840 12:43:19.448816
7841 12:43:19.448897 Set Vref, RX VrefLevel [Byte0]: 52
7842 12:43:19.451702 [Byte1]: 52
7843 12:43:19.456272
7844 12:43:19.456361 Set Vref, RX VrefLevel [Byte0]: 53
7845 12:43:19.459740 [Byte1]: 53
7846 12:43:19.463629
7847 12:43:19.463710 Set Vref, RX VrefLevel [Byte0]: 54
7848 12:43:19.467295 [Byte1]: 54
7849 12:43:19.471560
7850 12:43:19.471640 Set Vref, RX VrefLevel [Byte0]: 55
7851 12:43:19.474942 [Byte1]: 55
7852 12:43:19.478936
7853 12:43:19.479017 Set Vref, RX VrefLevel [Byte0]: 56
7854 12:43:19.482366 [Byte1]: 56
7855 12:43:19.486480
7856 12:43:19.486560 Set Vref, RX VrefLevel [Byte0]: 57
7857 12:43:19.489894 [Byte1]: 57
7858 12:43:19.493938
7859 12:43:19.494019 Set Vref, RX VrefLevel [Byte0]: 58
7860 12:43:19.497297 [Byte1]: 58
7861 12:43:19.501398
7862 12:43:19.501479 Set Vref, RX VrefLevel [Byte0]: 59
7863 12:43:19.504967 [Byte1]: 59
7864 12:43:19.508956
7865 12:43:19.509036 Set Vref, RX VrefLevel [Byte0]: 60
7866 12:43:19.512424 [Byte1]: 60
7867 12:43:19.517017
7868 12:43:19.517097 Set Vref, RX VrefLevel [Byte0]: 61
7869 12:43:19.519729 [Byte1]: 61
7870 12:43:19.524527
7871 12:43:19.524607 Set Vref, RX VrefLevel [Byte0]: 62
7872 12:43:19.527740 [Byte1]: 62
7873 12:43:19.531933
7874 12:43:19.532013 Set Vref, RX VrefLevel [Byte0]: 63
7875 12:43:19.535126 [Byte1]: 63
7876 12:43:19.539608
7877 12:43:19.539689 Set Vref, RX VrefLevel [Byte0]: 64
7878 12:43:19.542665 [Byte1]: 64
7879 12:43:19.547077
7880 12:43:19.547158 Set Vref, RX VrefLevel [Byte0]: 65
7881 12:43:19.550598 [Byte1]: 65
7882 12:43:19.554911
7883 12:43:19.554992 Set Vref, RX VrefLevel [Byte0]: 66
7884 12:43:19.557996 [Byte1]: 66
7885 12:43:19.561909
7886 12:43:19.561990 Set Vref, RX VrefLevel [Byte0]: 67
7887 12:43:19.565325 [Byte1]: 67
7888 12:43:19.570009
7889 12:43:19.570090 Set Vref, RX VrefLevel [Byte0]: 68
7890 12:43:19.573145 [Byte1]: 68
7891 12:43:19.577095
7892 12:43:19.577176 Set Vref, RX VrefLevel [Byte0]: 69
7893 12:43:19.580537 [Byte1]: 69
7894 12:43:19.584747
7895 12:43:19.584828 Set Vref, RX VrefLevel [Byte0]: 70
7896 12:43:19.588179 [Byte1]: 70
7897 12:43:19.592325
7898 12:43:19.592406 Set Vref, RX VrefLevel [Byte0]: 71
7899 12:43:19.595859 [Byte1]: 71
7900 12:43:19.600323
7901 12:43:19.600420 Set Vref, RX VrefLevel [Byte0]: 72
7902 12:43:19.603637 [Byte1]: 72
7903 12:43:19.607766
7904 12:43:19.607847 Set Vref, RX VrefLevel [Byte0]: 73
7905 12:43:19.611140 [Byte1]: 73
7906 12:43:19.615311
7907 12:43:19.615392 Set Vref, RX VrefLevel [Byte0]: 74
7908 12:43:19.618827 [Byte1]: 74
7909 12:43:19.622826
7910 12:43:19.622906 Set Vref, RX VrefLevel [Byte0]: 75
7911 12:43:19.626091 [Byte1]: 75
7912 12:43:19.630097
7913 12:43:19.630178 Final RX Vref Byte 0 = 59 to rank0
7914 12:43:19.633973 Final RX Vref Byte 1 = 61 to rank0
7915 12:43:19.637224 Final RX Vref Byte 0 = 59 to rank1
7916 12:43:19.640024 Final RX Vref Byte 1 = 61 to rank1==
7917 12:43:19.643524 Dram Type= 6, Freq= 0, CH_0, rank 0
7918 12:43:19.650474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7919 12:43:19.650555 ==
7920 12:43:19.650620 DQS Delay:
7921 12:43:19.650680 DQS0 = 0, DQS1 = 0
7922 12:43:19.653839 DQM Delay:
7923 12:43:19.653918 DQM0 = 134, DQM1 = 127
7924 12:43:19.657169 DQ Delay:
7925 12:43:19.660195 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =134
7926 12:43:19.663212 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7927 12:43:19.666827 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7928 12:43:19.669935 DQ12 =130, DQ13 =132, DQ14 =138, DQ15 =134
7929 12:43:19.670016
7930 12:43:19.670079
7931 12:43:19.670138
7932 12:43:19.673290 [DramC_TX_OE_Calibration] TA2
7933 12:43:19.676761 Original DQ_B0 (3 6) =30, OEN = 27
7934 12:43:19.679867 Original DQ_B1 (3 6) =30, OEN = 27
7935 12:43:19.683486 24, 0x0, End_B0=24 End_B1=24
7936 12:43:19.683569 25, 0x0, End_B0=25 End_B1=25
7937 12:43:19.686860 26, 0x0, End_B0=26 End_B1=26
7938 12:43:19.690158 27, 0x0, End_B0=27 End_B1=27
7939 12:43:19.693528 28, 0x0, End_B0=28 End_B1=28
7940 12:43:19.696914 29, 0x0, End_B0=29 End_B1=29
7941 12:43:19.696999 30, 0x0, End_B0=30 End_B1=30
7942 12:43:19.699783 31, 0x4141, End_B0=30 End_B1=30
7943 12:43:19.703261 Byte0 end_step=30 best_step=27
7944 12:43:19.706518 Byte1 end_step=30 best_step=27
7945 12:43:19.710398 Byte0 TX OE(2T, 0.5T) = (3, 3)
7946 12:43:19.713643 Byte1 TX OE(2T, 0.5T) = (3, 3)
7947 12:43:19.713724
7948 12:43:19.713788
7949 12:43:19.720028 [DQSOSCAuto] RK0, (LSB)MR18= 0x2722, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
7950 12:43:19.723465 CH0 RK0: MR19=303, MR18=2722
7951 12:43:19.730175 CH0_RK0: MR19=0x303, MR18=0x2722, DQSOSC=390, MR23=63, INC=24, DEC=16
7952 12:43:19.730259
7953 12:43:19.733351 ----->DramcWriteLeveling(PI) begin...
7954 12:43:19.733432 ==
7955 12:43:19.736837 Dram Type= 6, Freq= 0, CH_0, rank 1
7956 12:43:19.739960 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7957 12:43:19.740042 ==
7958 12:43:19.742971 Write leveling (Byte 0): 36 => 36
7959 12:43:19.746369 Write leveling (Byte 1): 27 => 27
7960 12:43:19.749802 DramcWriteLeveling(PI) end<-----
7961 12:43:19.749882
7962 12:43:19.749946 ==
7963 12:43:19.753262 Dram Type= 6, Freq= 0, CH_0, rank 1
7964 12:43:19.756599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7965 12:43:19.756680 ==
7966 12:43:19.760125 [Gating] SW mode calibration
7967 12:43:19.766298 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7968 12:43:19.773116 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7969 12:43:19.776472 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7970 12:43:19.779762 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7971 12:43:19.785974 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7972 12:43:19.789505 1 4 12 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7973 12:43:19.793078 1 4 16 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
7974 12:43:19.799528 1 4 20 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7975 12:43:19.802500 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7976 12:43:19.805999 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7977 12:43:19.812847 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7978 12:43:19.815728 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7979 12:43:19.819088 1 5 8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7980 12:43:19.825592 1 5 12 | B1->B0 | 3434 3131 | 1 1 | (1 0) (0 0)
7981 12:43:19.829338 1 5 16 | B1->B0 | 2f2f 2929 | 0 0 | (0 1) (0 1)
7982 12:43:19.832944 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7983 12:43:19.839418 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7984 12:43:19.842729 1 5 28 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7985 12:43:19.845899 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7986 12:43:19.852226 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7987 12:43:19.855758 1 6 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
7988 12:43:19.859357 1 6 12 | B1->B0 | 2323 3433 | 0 1 | (0 0) (1 1)
7989 12:43:19.865511 1 6 16 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
7990 12:43:19.868830 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7991 12:43:19.872305 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7992 12:43:19.879069 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (1 1)
7993 12:43:19.882444 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7994 12:43:19.885945 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7995 12:43:19.892443 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7996 12:43:19.895978 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7997 12:43:19.899491 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7998 12:43:19.905689 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 12:43:19.909155 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 12:43:19.912531 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 12:43:19.918660 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 12:43:19.922573 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 12:43:19.925225 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 12:43:19.932233 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 12:43:19.935430 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 12:43:19.939120 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 12:43:19.945241 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 12:43:19.948893 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 12:43:19.951887 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 12:43:19.958654 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 12:43:19.961806 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 12:43:19.965339 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8013 12:43:19.968612 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8014 12:43:19.975476 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 12:43:19.978177 Total UI for P1: 0, mck2ui 16
8016 12:43:19.981731 best dqsien dly found for B0: ( 1, 9, 14)
8017 12:43:19.985030 Total UI for P1: 0, mck2ui 16
8018 12:43:19.988295 best dqsien dly found for B1: ( 1, 9, 14)
8019 12:43:19.991646 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8020 12:43:19.994942 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8021 12:43:19.995028
8022 12:43:19.998404 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8023 12:43:20.001949 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8024 12:43:20.005288 [Gating] SW calibration Done
8025 12:43:20.005367 ==
8026 12:43:20.008702 Dram Type= 6, Freq= 0, CH_0, rank 1
8027 12:43:20.011486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8028 12:43:20.011561 ==
8029 12:43:20.014977 RX Vref Scan: 0
8030 12:43:20.015053
8031 12:43:20.018495 RX Vref 0 -> 0, step: 1
8032 12:43:20.018570
8033 12:43:20.018657 RX Delay 0 -> 252, step: 8
8034 12:43:20.025210 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8035 12:43:20.028373 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8036 12:43:20.031753 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8037 12:43:20.035193 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8038 12:43:20.038018 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8039 12:43:20.044865 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8040 12:43:20.048369 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8041 12:43:20.051897 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
8042 12:43:20.054679 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8043 12:43:20.057943 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8044 12:43:20.061597 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8045 12:43:20.068590 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8046 12:43:20.071686 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8047 12:43:20.075252 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8048 12:43:20.078073 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8049 12:43:20.085018 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8050 12:43:20.085100 ==
8051 12:43:20.087960 Dram Type= 6, Freq= 0, CH_0, rank 1
8052 12:43:20.091476 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8053 12:43:20.091558 ==
8054 12:43:20.091621 DQS Delay:
8055 12:43:20.094882 DQS0 = 0, DQS1 = 0
8056 12:43:20.094963 DQM Delay:
8057 12:43:20.098141 DQM0 = 137, DQM1 = 128
8058 12:43:20.098227 DQ Delay:
8059 12:43:20.101341 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8060 12:43:20.104867 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =147
8061 12:43:20.107890 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8062 12:43:20.111510 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8063 12:43:20.111591
8064 12:43:20.111655
8065 12:43:20.114806 ==
8066 12:43:20.114888 Dram Type= 6, Freq= 0, CH_0, rank 1
8067 12:43:20.121700 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8068 12:43:20.121781 ==
8069 12:43:20.121845
8070 12:43:20.121904
8071 12:43:20.124438 TX Vref Scan disable
8072 12:43:20.124518 == TX Byte 0 ==
8073 12:43:20.127844 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8074 12:43:20.134414 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8075 12:43:20.134495 == TX Byte 1 ==
8076 12:43:20.137813 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8077 12:43:20.144727 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8078 12:43:20.144808 ==
8079 12:43:20.148179 Dram Type= 6, Freq= 0, CH_0, rank 1
8080 12:43:20.151465 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8081 12:43:20.151547 ==
8082 12:43:20.165096
8083 12:43:20.168439 TX Vref early break, caculate TX vref
8084 12:43:20.171871 TX Vref=16, minBit 1, minWin=23, winSum=389
8085 12:43:20.175304 TX Vref=18, minBit 0, minWin=24, winSum=396
8086 12:43:20.178777 TX Vref=20, minBit 4, minWin=23, winSum=403
8087 12:43:20.182225 TX Vref=22, minBit 1, minWin=24, winSum=412
8088 12:43:20.185735 TX Vref=24, minBit 1, minWin=24, winSum=418
8089 12:43:20.191802 TX Vref=26, minBit 1, minWin=25, winSum=429
8090 12:43:20.195152 TX Vref=28, minBit 3, minWin=25, winSum=427
8091 12:43:20.198267 TX Vref=30, minBit 0, minWin=25, winSum=419
8092 12:43:20.201585 TX Vref=32, minBit 0, minWin=25, winSum=411
8093 12:43:20.205332 TX Vref=34, minBit 1, minWin=24, winSum=403
8094 12:43:20.211762 [TxChooseVref] Worse bit 1, Min win 25, Win sum 429, Final Vref 26
8095 12:43:20.211846
8096 12:43:20.215114 Final TX Range 0 Vref 26
8097 12:43:20.215196
8098 12:43:20.215259 ==
8099 12:43:20.218914 Dram Type= 6, Freq= 0, CH_0, rank 1
8100 12:43:20.221912 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8101 12:43:20.221993 ==
8102 12:43:20.222057
8103 12:43:20.222116
8104 12:43:20.225243 TX Vref Scan disable
8105 12:43:20.231911 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8106 12:43:20.231994 == TX Byte 0 ==
8107 12:43:20.235415 u2DelayCellOfst[0]=10 cells (3 PI)
8108 12:43:20.238915 u2DelayCellOfst[1]=13 cells (4 PI)
8109 12:43:20.241764 u2DelayCellOfst[2]=10 cells (3 PI)
8110 12:43:20.245202 u2DelayCellOfst[3]=10 cells (3 PI)
8111 12:43:20.248621 u2DelayCellOfst[4]=3 cells (1 PI)
8112 12:43:20.251968 u2DelayCellOfst[5]=0 cells (0 PI)
8113 12:43:20.252049 u2DelayCellOfst[6]=13 cells (4 PI)
8114 12:43:20.255435 u2DelayCellOfst[7]=13 cells (4 PI)
8115 12:43:20.262303 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8116 12:43:20.265121 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8117 12:43:20.265203 == TX Byte 1 ==
8118 12:43:20.268544 u2DelayCellOfst[8]=0 cells (0 PI)
8119 12:43:20.271780 u2DelayCellOfst[9]=0 cells (0 PI)
8120 12:43:20.275251 u2DelayCellOfst[10]=6 cells (2 PI)
8121 12:43:20.278514 u2DelayCellOfst[11]=6 cells (2 PI)
8122 12:43:20.281979 u2DelayCellOfst[12]=10 cells (3 PI)
8123 12:43:20.285469 u2DelayCellOfst[13]=10 cells (3 PI)
8124 12:43:20.288942 u2DelayCellOfst[14]=13 cells (4 PI)
8125 12:43:20.291678 u2DelayCellOfst[15]=10 cells (3 PI)
8126 12:43:20.295080 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8127 12:43:20.298548 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8128 12:43:20.301956 DramC Write-DBI on
8129 12:43:20.302037 ==
8130 12:43:20.305358 Dram Type= 6, Freq= 0, CH_0, rank 1
8131 12:43:20.308851 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8132 12:43:20.308933 ==
8133 12:43:20.308997
8134 12:43:20.311629
8135 12:43:20.311709 TX Vref Scan disable
8136 12:43:20.315215 == TX Byte 0 ==
8137 12:43:20.318533 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8138 12:43:20.322000 == TX Byte 1 ==
8139 12:43:20.325400 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8140 12:43:20.325482 DramC Write-DBI off
8141 12:43:20.328702
8142 12:43:20.328810 [DATLAT]
8143 12:43:20.328876 Freq=1600, CH0 RK1
8144 12:43:20.328935
8145 12:43:20.331805 DATLAT Default: 0xf
8146 12:43:20.331885 0, 0xFFFF, sum = 0
8147 12:43:20.334928 1, 0xFFFF, sum = 0
8148 12:43:20.335029 2, 0xFFFF, sum = 0
8149 12:43:20.338059 3, 0xFFFF, sum = 0
8150 12:43:20.338141 4, 0xFFFF, sum = 0
8151 12:43:20.341543 5, 0xFFFF, sum = 0
8152 12:43:20.344833 6, 0xFFFF, sum = 0
8153 12:43:20.344915 7, 0xFFFF, sum = 0
8154 12:43:20.348228 8, 0xFFFF, sum = 0
8155 12:43:20.348343 9, 0xFFFF, sum = 0
8156 12:43:20.351638 10, 0xFFFF, sum = 0
8157 12:43:20.351720 11, 0xFFFF, sum = 0
8158 12:43:20.355190 12, 0xFFFF, sum = 0
8159 12:43:20.355272 13, 0xFFFF, sum = 0
8160 12:43:20.357895 14, 0x0, sum = 1
8161 12:43:20.357977 15, 0x0, sum = 2
8162 12:43:20.361288 16, 0x0, sum = 3
8163 12:43:20.361370 17, 0x0, sum = 4
8164 12:43:20.365130 best_step = 15
8165 12:43:20.365210
8166 12:43:20.365273 ==
8167 12:43:20.368293 Dram Type= 6, Freq= 0, CH_0, rank 1
8168 12:43:20.371370 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8169 12:43:20.371452 ==
8170 12:43:20.371516 RX Vref Scan: 0
8171 12:43:20.374912
8172 12:43:20.374992 RX Vref 0 -> 0, step: 1
8173 12:43:20.375056
8174 12:43:20.378094 RX Delay 19 -> 252, step: 4
8175 12:43:20.381398 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8176 12:43:20.388292 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8177 12:43:20.391687 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8178 12:43:20.394548 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8179 12:43:20.398064 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8180 12:43:20.401638 iDelay=191, Bit 5, Center 128 (75 ~ 182) 108
8181 12:43:20.404885 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8182 12:43:20.411724 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8183 12:43:20.415065 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8184 12:43:20.418548 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8185 12:43:20.421398 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8186 12:43:20.424820 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8187 12:43:20.431121 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8188 12:43:20.434508 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8189 12:43:20.437779 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8190 12:43:20.441598 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8191 12:43:20.441679 ==
8192 12:43:20.445075 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 12:43:20.451318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 12:43:20.451400 ==
8195 12:43:20.451463 DQS Delay:
8196 12:43:20.454745 DQS0 = 0, DQS1 = 0
8197 12:43:20.454826 DQM Delay:
8198 12:43:20.458249 DQM0 = 135, DQM1 = 127
8199 12:43:20.458330 DQ Delay:
8200 12:43:20.461026 DQ0 =134, DQ1 =138, DQ2 =132, DQ3 =134
8201 12:43:20.464564 DQ4 =136, DQ5 =128, DQ6 =140, DQ7 =140
8202 12:43:20.468002 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8203 12:43:20.471416 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8204 12:43:20.471498
8205 12:43:20.471561
8206 12:43:20.471619
8207 12:43:20.474726 [DramC_TX_OE_Calibration] TA2
8208 12:43:20.477967 Original DQ_B0 (3 6) =30, OEN = 27
8209 12:43:20.481114 Original DQ_B1 (3 6) =30, OEN = 27
8210 12:43:20.484520 24, 0x0, End_B0=24 End_B1=24
8211 12:43:20.487828 25, 0x0, End_B0=25 End_B1=25
8212 12:43:20.487908 26, 0x0, End_B0=26 End_B1=26
8213 12:43:20.491340 27, 0x0, End_B0=27 End_B1=27
8214 12:43:20.494576 28, 0x0, End_B0=28 End_B1=28
8215 12:43:20.497732 29, 0x0, End_B0=29 End_B1=29
8216 12:43:20.497815 30, 0x0, End_B0=30 End_B1=30
8217 12:43:20.501285 31, 0x4141, End_B0=30 End_B1=30
8218 12:43:20.504681 Byte0 end_step=30 best_step=27
8219 12:43:20.507888 Byte1 end_step=30 best_step=27
8220 12:43:20.510995 Byte0 TX OE(2T, 0.5T) = (3, 3)
8221 12:43:20.514404 Byte1 TX OE(2T, 0.5T) = (3, 3)
8222 12:43:20.514483
8223 12:43:20.514564
8224 12:43:20.520884 [DQSOSCAuto] RK1, (LSB)MR18= 0x2109, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8225 12:43:20.524619 CH0 RK1: MR19=303, MR18=2109
8226 12:43:20.530783 CH0_RK1: MR19=0x303, MR18=0x2109, DQSOSC=393, MR23=63, INC=23, DEC=15
8227 12:43:20.534179 [RxdqsGatingPostProcess] freq 1600
8228 12:43:20.537672 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8229 12:43:20.541138 best DQS0 dly(2T, 0.5T) = (1, 1)
8230 12:43:20.544124 best DQS1 dly(2T, 0.5T) = (1, 1)
8231 12:43:20.548040 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8232 12:43:20.551161 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8233 12:43:20.554278 best DQS0 dly(2T, 0.5T) = (1, 1)
8234 12:43:20.558036 best DQS1 dly(2T, 0.5T) = (1, 1)
8235 12:43:20.561368 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8236 12:43:20.564148 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8237 12:43:20.567538 Pre-setting of DQS Precalculation
8238 12:43:20.570861 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8239 12:43:20.570942 ==
8240 12:43:20.574362 Dram Type= 6, Freq= 0, CH_1, rank 0
8241 12:43:20.577870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8242 12:43:20.581295 ==
8243 12:43:20.584072 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8244 12:43:20.587427 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8245 12:43:20.594426 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8246 12:43:20.600796 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8247 12:43:20.607974 [CA 0] Center 41 (12~71) winsize 60
8248 12:43:20.611479 [CA 1] Center 41 (12~71) winsize 60
8249 12:43:20.614853 [CA 2] Center 39 (10~68) winsize 59
8250 12:43:20.618272 [CA 3] Center 37 (8~66) winsize 59
8251 12:43:20.621271 [CA 4] Center 37 (8~67) winsize 60
8252 12:43:20.624164 [CA 5] Center 36 (7~66) winsize 60
8253 12:43:20.624271
8254 12:43:20.627778 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8255 12:43:20.627854
8256 12:43:20.631009 [CATrainingPosCal] consider 1 rank data
8257 12:43:20.634363 u2DelayCellTimex100 = 285/100 ps
8258 12:43:20.640733 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8259 12:43:20.644204 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8260 12:43:20.647645 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
8261 12:43:20.651004 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8262 12:43:20.654271 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8263 12:43:20.657614 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8264 12:43:20.657695
8265 12:43:20.660826 CA PerBit enable=1, Macro0, CA PI delay=36
8266 12:43:20.660907
8267 12:43:20.664003 [CBTSetCACLKResult] CA Dly = 36
8268 12:43:20.667146 CS Dly: 10 (0~41)
8269 12:43:20.670796 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8270 12:43:20.674100 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8271 12:43:20.674181 ==
8272 12:43:20.677634 Dram Type= 6, Freq= 0, CH_1, rank 1
8273 12:43:20.683886 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8274 12:43:20.683967 ==
8275 12:43:20.687358 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8276 12:43:20.693933 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8277 12:43:20.697635 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8278 12:43:20.703628 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8279 12:43:20.711671 [CA 0] Center 42 (12~72) winsize 61
8280 12:43:20.714719 [CA 1] Center 42 (12~72) winsize 61
8281 12:43:20.718101 [CA 2] Center 38 (9~68) winsize 60
8282 12:43:20.721575 [CA 3] Center 38 (8~68) winsize 61
8283 12:43:20.724984 [CA 4] Center 39 (9~69) winsize 61
8284 12:43:20.727731 [CA 5] Center 37 (8~67) winsize 60
8285 12:43:20.727812
8286 12:43:20.731112 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8287 12:43:20.731193
8288 12:43:20.734589 [CATrainingPosCal] consider 2 rank data
8289 12:43:20.737886 u2DelayCellTimex100 = 285/100 ps
8290 12:43:20.741125 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8291 12:43:20.748060 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8292 12:43:20.751207 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8293 12:43:20.754846 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8294 12:43:20.757812 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8295 12:43:20.761185 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8296 12:43:20.761305
8297 12:43:20.764253 CA PerBit enable=1, Macro0, CA PI delay=37
8298 12:43:20.764359
8299 12:43:20.767862 [CBTSetCACLKResult] CA Dly = 37
8300 12:43:20.771414 CS Dly: 11 (0~44)
8301 12:43:20.774761 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8302 12:43:20.778016 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8303 12:43:20.778125
8304 12:43:20.781518 ----->DramcWriteLeveling(PI) begin...
8305 12:43:20.781640 ==
8306 12:43:20.784248 Dram Type= 6, Freq= 0, CH_1, rank 0
8307 12:43:20.788028 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8308 12:43:20.791337 ==
8309 12:43:20.791487 Write leveling (Byte 0): 25 => 25
8310 12:43:20.794710 Write leveling (Byte 1): 26 => 26
8311 12:43:20.798083 DramcWriteLeveling(PI) end<-----
8312 12:43:20.798253
8313 12:43:20.798387 ==
8314 12:43:20.801511 Dram Type= 6, Freq= 0, CH_1, rank 0
8315 12:43:20.807885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8316 12:43:20.808123 ==
8317 12:43:20.811312 [Gating] SW mode calibration
8318 12:43:20.818191 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8319 12:43:20.821492 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8320 12:43:20.828400 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8321 12:43:20.831151 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8322 12:43:20.834666 1 4 8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
8323 12:43:20.841128 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8324 12:43:20.844650 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8325 12:43:20.848066 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8326 12:43:20.851696 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8327 12:43:20.857904 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8328 12:43:20.861342 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8329 12:43:20.864800 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8330 12:43:20.871100 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
8331 12:43:20.874600 1 5 12 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (1 0)
8332 12:43:20.878169 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 12:43:20.884242 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 12:43:20.887416 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 12:43:20.891172 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8336 12:43:20.897515 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8337 12:43:20.900849 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 12:43:20.904446 1 6 8 | B1->B0 | 2626 4646 | 1 0 | (0 0) (0 0)
8339 12:43:20.910650 1 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8340 12:43:20.913973 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8341 12:43:20.917730 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 12:43:20.924453 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 12:43:20.927707 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8344 12:43:20.931017 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 12:43:20.937191 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 12:43:20.940653 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8347 12:43:20.944117 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8348 12:43:20.950988 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 12:43:20.954402 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 12:43:20.957764 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 12:43:20.964258 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 12:43:20.967147 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 12:43:20.970643 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 12:43:20.977290 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 12:43:20.980427 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 12:43:20.983948 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 12:43:20.987325 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 12:43:20.993974 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 12:43:20.997428 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 12:43:21.000868 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 12:43:21.007357 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 12:43:21.010434 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8363 12:43:21.013949 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8364 12:43:21.020893 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 12:43:21.023943 Total UI for P1: 0, mck2ui 16
8366 12:43:21.026842 best dqsien dly found for B0: ( 1, 9, 10)
8367 12:43:21.026924 Total UI for P1: 0, mck2ui 16
8368 12:43:21.033747 best dqsien dly found for B1: ( 1, 9, 10)
8369 12:43:21.037180 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8370 12:43:21.040579 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8371 12:43:21.040663
8372 12:43:21.043680 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8373 12:43:21.047249 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8374 12:43:21.050506 [Gating] SW calibration Done
8375 12:43:21.050587 ==
8376 12:43:21.054045 Dram Type= 6, Freq= 0, CH_1, rank 0
8377 12:43:21.057502 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8378 12:43:21.057584 ==
8379 12:43:21.060834 RX Vref Scan: 0
8380 12:43:21.060915
8381 12:43:21.060979 RX Vref 0 -> 0, step: 1
8382 12:43:21.061039
8383 12:43:21.064148 RX Delay 0 -> 252, step: 8
8384 12:43:21.067434 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8385 12:43:21.073594 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8386 12:43:21.077114 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8387 12:43:21.080336 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8388 12:43:21.083932 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8389 12:43:21.087387 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8390 12:43:21.093657 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8391 12:43:21.096911 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8392 12:43:21.100423 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8393 12:43:21.103267 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8394 12:43:21.106747 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8395 12:43:21.113773 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8396 12:43:21.116587 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8397 12:43:21.119890 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8398 12:43:21.123579 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8399 12:43:21.126566 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8400 12:43:21.129762 ==
8401 12:43:21.133152 Dram Type= 6, Freq= 0, CH_1, rank 0
8402 12:43:21.136523 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8403 12:43:21.136604 ==
8404 12:43:21.136668 DQS Delay:
8405 12:43:21.139912 DQS0 = 0, DQS1 = 0
8406 12:43:21.139993 DQM Delay:
8407 12:43:21.143689 DQM0 = 136, DQM1 = 132
8408 12:43:21.143770 DQ Delay:
8409 12:43:21.146981 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8410 12:43:21.150000 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =139
8411 12:43:21.153199 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8412 12:43:21.156904 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8413 12:43:21.156985
8414 12:43:21.157049
8415 12:43:21.157107 ==
8416 12:43:21.159742 Dram Type= 6, Freq= 0, CH_1, rank 0
8417 12:43:21.166694 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8418 12:43:21.166776 ==
8419 12:43:21.166840
8420 12:43:21.166899
8421 12:43:21.166956 TX Vref Scan disable
8422 12:43:21.170498 == TX Byte 0 ==
8423 12:43:21.173764 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8424 12:43:21.177016 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8425 12:43:21.180584 == TX Byte 1 ==
8426 12:43:21.183824 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8427 12:43:21.187246 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8428 12:43:21.190581 ==
8429 12:43:21.193898 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 12:43:21.196636 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 12:43:21.196717 ==
8432 12:43:21.210093
8433 12:43:21.213570 TX Vref early break, caculate TX vref
8434 12:43:21.216978 TX Vref=16, minBit 0, minWin=23, winSum=381
8435 12:43:21.219778 TX Vref=18, minBit 1, minWin=23, winSum=387
8436 12:43:21.223173 TX Vref=20, minBit 6, minWin=23, winSum=398
8437 12:43:21.226639 TX Vref=22, minBit 6, minWin=23, winSum=407
8438 12:43:21.230008 TX Vref=24, minBit 9, minWin=24, winSum=417
8439 12:43:21.236318 TX Vref=26, minBit 0, minWin=25, winSum=427
8440 12:43:21.239947 TX Vref=28, minBit 0, minWin=25, winSum=427
8441 12:43:21.242958 TX Vref=30, minBit 2, minWin=25, winSum=426
8442 12:43:21.246406 TX Vref=32, minBit 0, minWin=24, winSum=413
8443 12:43:21.249790 TX Vref=34, minBit 0, minWin=24, winSum=407
8444 12:43:21.253127 TX Vref=36, minBit 0, minWin=23, winSum=394
8445 12:43:21.259806 [TxChooseVref] Worse bit 0, Min win 25, Win sum 427, Final Vref 26
8446 12:43:21.259890
8447 12:43:21.263295 Final TX Range 0 Vref 26
8448 12:43:21.263376
8449 12:43:21.263441 ==
8450 12:43:21.266479 Dram Type= 6, Freq= 0, CH_1, rank 0
8451 12:43:21.269688 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8452 12:43:21.269770 ==
8453 12:43:21.269834
8454 12:43:21.269892
8455 12:43:21.272954 TX Vref Scan disable
8456 12:43:21.279927 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8457 12:43:21.280008 == TX Byte 0 ==
8458 12:43:21.283213 u2DelayCellOfst[0]=17 cells (5 PI)
8459 12:43:21.286411 u2DelayCellOfst[1]=10 cells (3 PI)
8460 12:43:21.290058 u2DelayCellOfst[2]=0 cells (0 PI)
8461 12:43:21.293081 u2DelayCellOfst[3]=3 cells (1 PI)
8462 12:43:21.296570 u2DelayCellOfst[4]=6 cells (2 PI)
8463 12:43:21.299611 u2DelayCellOfst[5]=17 cells (5 PI)
8464 12:43:21.303410 u2DelayCellOfst[6]=17 cells (5 PI)
8465 12:43:21.306213 u2DelayCellOfst[7]=6 cells (2 PI)
8466 12:43:21.309471 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8467 12:43:21.312867 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8468 12:43:21.316319 == TX Byte 1 ==
8469 12:43:21.316415 u2DelayCellOfst[8]=0 cells (0 PI)
8470 12:43:21.319776 u2DelayCellOfst[9]=3 cells (1 PI)
8471 12:43:21.323214 u2DelayCellOfst[10]=13 cells (4 PI)
8472 12:43:21.326594 u2DelayCellOfst[11]=3 cells (1 PI)
8473 12:43:21.330078 u2DelayCellOfst[12]=13 cells (4 PI)
8474 12:43:21.332871 u2DelayCellOfst[13]=17 cells (5 PI)
8475 12:43:21.336261 u2DelayCellOfst[14]=17 cells (5 PI)
8476 12:43:21.339764 u2DelayCellOfst[15]=17 cells (5 PI)
8477 12:43:21.343256 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8478 12:43:21.349614 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8479 12:43:21.349695 DramC Write-DBI on
8480 12:43:21.349759 ==
8481 12:43:21.352672 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 12:43:21.356221 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8483 12:43:21.359195 ==
8484 12:43:21.359275
8485 12:43:21.359338
8486 12:43:21.359396 TX Vref Scan disable
8487 12:43:21.362975 == TX Byte 0 ==
8488 12:43:21.366207 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8489 12:43:21.369772 == TX Byte 1 ==
8490 12:43:21.373194 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8491 12:43:21.373275 DramC Write-DBI off
8492 12:43:21.376227
8493 12:43:21.376350 [DATLAT]
8494 12:43:21.376415 Freq=1600, CH1 RK0
8495 12:43:21.376475
8496 12:43:21.379713 DATLAT Default: 0xf
8497 12:43:21.379794 0, 0xFFFF, sum = 0
8498 12:43:21.383073 1, 0xFFFF, sum = 0
8499 12:43:21.383156 2, 0xFFFF, sum = 0
8500 12:43:21.386497 3, 0xFFFF, sum = 0
8501 12:43:21.386579 4, 0xFFFF, sum = 0
8502 12:43:21.389782 5, 0xFFFF, sum = 0
8503 12:43:21.393229 6, 0xFFFF, sum = 0
8504 12:43:21.393311 7, 0xFFFF, sum = 0
8505 12:43:21.396411 8, 0xFFFF, sum = 0
8506 12:43:21.396493 9, 0xFFFF, sum = 0
8507 12:43:21.399471 10, 0xFFFF, sum = 0
8508 12:43:21.399553 11, 0xFFFF, sum = 0
8509 12:43:21.402712 12, 0xFFFF, sum = 0
8510 12:43:21.402794 13, 0xFFFF, sum = 0
8511 12:43:21.405969 14, 0x0, sum = 1
8512 12:43:21.406050 15, 0x0, sum = 2
8513 12:43:21.409917 16, 0x0, sum = 3
8514 12:43:21.409999 17, 0x0, sum = 4
8515 12:43:21.413029 best_step = 15
8516 12:43:21.413111
8517 12:43:21.413174 ==
8518 12:43:21.416208 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 12:43:21.419439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 12:43:21.419520 ==
8521 12:43:21.419584 RX Vref Scan: 1
8522 12:43:21.422896
8523 12:43:21.422976 Set Vref Range= 24 -> 127
8524 12:43:21.423040
8525 12:43:21.426346 RX Vref 24 -> 127, step: 1
8526 12:43:21.426427
8527 12:43:21.429865 RX Delay 27 -> 252, step: 4
8528 12:43:21.429946
8529 12:43:21.432669 Set Vref, RX VrefLevel [Byte0]: 24
8530 12:43:21.436176 [Byte1]: 24
8531 12:43:21.436256
8532 12:43:21.439550 Set Vref, RX VrefLevel [Byte0]: 25
8533 12:43:21.442971 [Byte1]: 25
8534 12:43:21.443051
8535 12:43:21.445852 Set Vref, RX VrefLevel [Byte0]: 26
8536 12:43:21.449351 [Byte1]: 26
8537 12:43:21.452969
8538 12:43:21.453049 Set Vref, RX VrefLevel [Byte0]: 27
8539 12:43:21.456351 [Byte1]: 27
8540 12:43:21.460986
8541 12:43:21.461066 Set Vref, RX VrefLevel [Byte0]: 28
8542 12:43:21.464183 [Byte1]: 28
8543 12:43:21.468239
8544 12:43:21.468358 Set Vref, RX VrefLevel [Byte0]: 29
8545 12:43:21.471112 [Byte1]: 29
8546 12:43:21.475787
8547 12:43:21.475868 Set Vref, RX VrefLevel [Byte0]: 30
8548 12:43:21.479353 [Byte1]: 30
8549 12:43:21.482952
8550 12:43:21.483033 Set Vref, RX VrefLevel [Byte0]: 31
8551 12:43:21.486698 [Byte1]: 31
8552 12:43:21.490520
8553 12:43:21.490600 Set Vref, RX VrefLevel [Byte0]: 32
8554 12:43:21.494539 [Byte1]: 32
8555 12:43:21.498073
8556 12:43:21.498154 Set Vref, RX VrefLevel [Byte0]: 33
8557 12:43:21.504746 [Byte1]: 33
8558 12:43:21.504827
8559 12:43:21.508128 Set Vref, RX VrefLevel [Byte0]: 34
8560 12:43:21.511420 [Byte1]: 34
8561 12:43:21.511501
8562 12:43:21.514855 Set Vref, RX VrefLevel [Byte0]: 35
8563 12:43:21.518221 [Byte1]: 35
8564 12:43:21.518302
8565 12:43:21.521613 Set Vref, RX VrefLevel [Byte0]: 36
8566 12:43:21.524275 [Byte1]: 36
8567 12:43:21.528119
8568 12:43:21.528204 Set Vref, RX VrefLevel [Byte0]: 37
8569 12:43:21.531923 [Byte1]: 37
8570 12:43:21.535889
8571 12:43:21.535968 Set Vref, RX VrefLevel [Byte0]: 38
8572 12:43:21.539330 [Byte1]: 38
8573 12:43:21.543691
8574 12:43:21.543771 Set Vref, RX VrefLevel [Byte0]: 39
8575 12:43:21.546981 [Byte1]: 39
8576 12:43:21.551156
8577 12:43:21.551236 Set Vref, RX VrefLevel [Byte0]: 40
8578 12:43:21.554614 [Byte1]: 40
8579 12:43:21.558764
8580 12:43:21.558843 Set Vref, RX VrefLevel [Byte0]: 41
8581 12:43:21.562211 [Byte1]: 41
8582 12:43:21.566332
8583 12:43:21.566412 Set Vref, RX VrefLevel [Byte0]: 42
8584 12:43:21.569045 [Byte1]: 42
8585 12:43:21.573927
8586 12:43:21.574017 Set Vref, RX VrefLevel [Byte0]: 43
8587 12:43:21.577114 [Byte1]: 43
8588 12:43:21.580946
8589 12:43:21.581026 Set Vref, RX VrefLevel [Byte0]: 44
8590 12:43:21.584475 [Byte1]: 44
8591 12:43:21.588756
8592 12:43:21.588835 Set Vref, RX VrefLevel [Byte0]: 45
8593 12:43:21.591898 [Byte1]: 45
8594 12:43:21.596131
8595 12:43:21.596243 Set Vref, RX VrefLevel [Byte0]: 46
8596 12:43:21.599833 [Byte1]: 46
8597 12:43:21.603580
8598 12:43:21.603679 Set Vref, RX VrefLevel [Byte0]: 47
8599 12:43:21.607343 [Byte1]: 47
8600 12:43:21.611330
8601 12:43:21.611410 Set Vref, RX VrefLevel [Byte0]: 48
8602 12:43:21.614703 [Byte1]: 48
8603 12:43:21.618869
8604 12:43:21.618948 Set Vref, RX VrefLevel [Byte0]: 49
8605 12:43:21.621847 [Byte1]: 49
8606 12:43:21.626204
8607 12:43:21.626285 Set Vref, RX VrefLevel [Byte0]: 50
8608 12:43:21.629713 [Byte1]: 50
8609 12:43:21.633697
8610 12:43:21.633777 Set Vref, RX VrefLevel [Byte0]: 51
8611 12:43:21.637232 [Byte1]: 51
8612 12:43:21.641663
8613 12:43:21.641743 Set Vref, RX VrefLevel [Byte0]: 52
8614 12:43:21.644667 [Byte1]: 52
8615 12:43:21.648753
8616 12:43:21.648834 Set Vref, RX VrefLevel [Byte0]: 53
8617 12:43:21.652123 [Byte1]: 53
8618 12:43:21.656257
8619 12:43:21.656377 Set Vref, RX VrefLevel [Byte0]: 54
8620 12:43:21.659791 [Byte1]: 54
8621 12:43:21.664070
8622 12:43:21.664150 Set Vref, RX VrefLevel [Byte0]: 55
8623 12:43:21.667435 [Byte1]: 55
8624 12:43:21.671716
8625 12:43:21.671797 Set Vref, RX VrefLevel [Byte0]: 56
8626 12:43:21.674627 [Byte1]: 56
8627 12:43:21.678855
8628 12:43:21.678936 Set Vref, RX VrefLevel [Byte0]: 57
8629 12:43:21.682252 [Byte1]: 57
8630 12:43:21.686379
8631 12:43:21.686460 Set Vref, RX VrefLevel [Byte0]: 58
8632 12:43:21.690125 [Byte1]: 58
8633 12:43:21.693875
8634 12:43:21.693955 Set Vref, RX VrefLevel [Byte0]: 59
8635 12:43:21.697341 [Byte1]: 59
8636 12:43:21.701442
8637 12:43:21.701523 Set Vref, RX VrefLevel [Byte0]: 60
8638 12:43:21.704948 [Byte1]: 60
8639 12:43:21.709069
8640 12:43:21.709150 Set Vref, RX VrefLevel [Byte0]: 61
8641 12:43:21.712215 [Byte1]: 61
8642 12:43:21.716776
8643 12:43:21.716857 Set Vref, RX VrefLevel [Byte0]: 62
8644 12:43:21.719967 [Byte1]: 62
8645 12:43:21.724423
8646 12:43:21.724504 Set Vref, RX VrefLevel [Byte0]: 63
8647 12:43:21.727330 [Byte1]: 63
8648 12:43:21.731442
8649 12:43:21.731522 Set Vref, RX VrefLevel [Byte0]: 64
8650 12:43:21.735204 [Byte1]: 64
8651 12:43:21.739622
8652 12:43:21.739703 Set Vref, RX VrefLevel [Byte0]: 65
8653 12:43:21.742570 [Byte1]: 65
8654 12:43:21.746569
8655 12:43:21.746649 Set Vref, RX VrefLevel [Byte0]: 66
8656 12:43:21.750204 [Byte1]: 66
8657 12:43:21.754095
8658 12:43:21.754175 Set Vref, RX VrefLevel [Byte0]: 67
8659 12:43:21.757755 [Byte1]: 67
8660 12:43:21.761689
8661 12:43:21.761769 Set Vref, RX VrefLevel [Byte0]: 68
8662 12:43:21.765067 [Byte1]: 68
8663 12:43:21.769122
8664 12:43:21.769202 Set Vref, RX VrefLevel [Byte0]: 69
8665 12:43:21.772546 [Byte1]: 69
8666 12:43:21.776626
8667 12:43:21.776706 Set Vref, RX VrefLevel [Byte0]: 70
8668 12:43:21.779983 [Byte1]: 70
8669 12:43:21.784245
8670 12:43:21.784331 Set Vref, RX VrefLevel [Byte0]: 71
8671 12:43:21.787817 [Byte1]: 71
8672 12:43:21.791933
8673 12:43:21.792012 Set Vref, RX VrefLevel [Byte0]: 72
8674 12:43:21.795283 [Byte1]: 72
8675 12:43:21.799743
8676 12:43:21.799829 Set Vref, RX VrefLevel [Byte0]: 73
8677 12:43:21.802721 [Byte1]: 73
8678 12:43:21.807205
8679 12:43:21.807285 Set Vref, RX VrefLevel [Byte0]: 74
8680 12:43:21.810563 [Byte1]: 74
8681 12:43:21.814662
8682 12:43:21.814742 Final RX Vref Byte 0 = 58 to rank0
8683 12:43:21.817991 Final RX Vref Byte 1 = 56 to rank0
8684 12:43:21.821384 Final RX Vref Byte 0 = 58 to rank1
8685 12:43:21.824813 Final RX Vref Byte 1 = 56 to rank1==
8686 12:43:21.827577 Dram Type= 6, Freq= 0, CH_1, rank 0
8687 12:43:21.834698 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8688 12:43:21.834778 ==
8689 12:43:21.834863 DQS Delay:
8690 12:43:21.834924 DQS0 = 0, DQS1 = 0
8691 12:43:21.838001 DQM Delay:
8692 12:43:21.838081 DQM0 = 134, DQM1 = 131
8693 12:43:21.841123 DQ Delay:
8694 12:43:21.844322 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8695 12:43:21.848034 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =132
8696 12:43:21.850867 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8697 12:43:21.854419 DQ12 =138, DQ13 =138, DQ14 =140, DQ15 =140
8698 12:43:21.854499
8699 12:43:21.854562
8700 12:43:21.854621
8701 12:43:21.857649 [DramC_TX_OE_Calibration] TA2
8702 12:43:21.861018 Original DQ_B0 (3 6) =30, OEN = 27
8703 12:43:21.864398 Original DQ_B1 (3 6) =30, OEN = 27
8704 12:43:21.867615 24, 0x0, End_B0=24 End_B1=24
8705 12:43:21.867696 25, 0x0, End_B0=25 End_B1=25
8706 12:43:21.871411 26, 0x0, End_B0=26 End_B1=26
8707 12:43:21.874486 27, 0x0, End_B0=27 End_B1=27
8708 12:43:21.877870 28, 0x0, End_B0=28 End_B1=28
8709 12:43:21.881331 29, 0x0, End_B0=29 End_B1=29
8710 12:43:21.881413 30, 0x0, End_B0=30 End_B1=30
8711 12:43:21.884126 31, 0x4141, End_B0=30 End_B1=30
8712 12:43:21.887588 Byte0 end_step=30 best_step=27
8713 12:43:21.891046 Byte1 end_step=30 best_step=27
8714 12:43:21.894457 Byte0 TX OE(2T, 0.5T) = (3, 3)
8715 12:43:21.897893 Byte1 TX OE(2T, 0.5T) = (3, 3)
8716 12:43:21.897973
8717 12:43:21.898036
8718 12:43:21.904121 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8719 12:43:21.907391 CH1 RK0: MR19=303, MR18=1826
8720 12:43:21.914460 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8721 12:43:21.914541
8722 12:43:21.917523 ----->DramcWriteLeveling(PI) begin...
8723 12:43:21.917604 ==
8724 12:43:21.921035 Dram Type= 6, Freq= 0, CH_1, rank 1
8725 12:43:21.924331 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8726 12:43:21.924431 ==
8727 12:43:21.927840 Write leveling (Byte 0): 26 => 26
8728 12:43:21.931157 Write leveling (Byte 1): 28 => 28
8729 12:43:21.934015 DramcWriteLeveling(PI) end<-----
8730 12:43:21.934095
8731 12:43:21.934158 ==
8732 12:43:21.937427 Dram Type= 6, Freq= 0, CH_1, rank 1
8733 12:43:21.940821 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8734 12:43:21.940901 ==
8735 12:43:21.944260 [Gating] SW mode calibration
8736 12:43:21.951187 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8737 12:43:21.957251 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8738 12:43:21.960894 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8739 12:43:21.963956 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8740 12:43:21.971085 1 4 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8741 12:43:21.974208 1 4 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
8742 12:43:21.977563 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8743 12:43:21.984441 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8744 12:43:21.987400 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8745 12:43:21.990522 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8746 12:43:21.997549 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8747 12:43:22.000965 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8748 12:43:22.003778 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8749 12:43:22.010588 1 5 12 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
8750 12:43:22.014002 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8751 12:43:22.017491 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8752 12:43:22.024235 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8753 12:43:22.027253 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 12:43:22.030270 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 12:43:22.036822 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 12:43:22.040172 1 6 8 | B1->B0 | 3f3f 2525 | 0 0 | (0 0) (0 0)
8757 12:43:22.043569 1 6 12 | B1->B0 | 4646 4544 | 0 1 | (0 0) (0 0)
8758 12:43:22.050298 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8759 12:43:22.053831 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8760 12:43:22.057280 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8761 12:43:22.063462 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8762 12:43:22.066932 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8763 12:43:22.070298 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8764 12:43:22.076680 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8765 12:43:22.080257 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8766 12:43:22.083420 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8767 12:43:22.086785 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 12:43:22.093541 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 12:43:22.097041 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 12:43:22.100240 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 12:43:22.107133 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 12:43:22.110288 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 12:43:22.113869 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 12:43:22.120554 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 12:43:22.123287 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 12:43:22.126696 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 12:43:22.133490 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 12:43:22.136862 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 12:43:22.139997 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8780 12:43:22.146583 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8781 12:43:22.150287 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8782 12:43:22.153419 Total UI for P1: 0, mck2ui 16
8783 12:43:22.156846 best dqsien dly found for B1: ( 1, 9, 6)
8784 12:43:22.160345 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 12:43:22.163097 Total UI for P1: 0, mck2ui 16
8786 12:43:22.166554 best dqsien dly found for B0: ( 1, 9, 12)
8787 12:43:22.170175 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8788 12:43:22.173415 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8789 12:43:22.173495
8790 12:43:22.176941 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8791 12:43:22.183174 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8792 12:43:22.183254 [Gating] SW calibration Done
8793 12:43:22.186894 ==
8794 12:43:22.186974 Dram Type= 6, Freq= 0, CH_1, rank 1
8795 12:43:22.193391 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8796 12:43:22.193471 ==
8797 12:43:22.193535 RX Vref Scan: 0
8798 12:43:22.193593
8799 12:43:22.196499 RX Vref 0 -> 0, step: 1
8800 12:43:22.196579
8801 12:43:22.200154 RX Delay 0 -> 252, step: 8
8802 12:43:22.203224 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8803 12:43:22.206570 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8804 12:43:22.210073 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8805 12:43:22.216637 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8806 12:43:22.219665 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8807 12:43:22.223588 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8808 12:43:22.226542 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8809 12:43:22.229550 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8810 12:43:22.236561 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8811 12:43:22.239933 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8812 12:43:22.243343 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8813 12:43:22.246137 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8814 12:43:22.249535 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8815 12:43:22.256137 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8816 12:43:22.259245 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8817 12:43:22.262966 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8818 12:43:22.263047 ==
8819 12:43:22.266066 Dram Type= 6, Freq= 0, CH_1, rank 1
8820 12:43:22.269406 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8821 12:43:22.272843 ==
8822 12:43:22.272922 DQS Delay:
8823 12:43:22.272986 DQS0 = 0, DQS1 = 0
8824 12:43:22.276348 DQM Delay:
8825 12:43:22.276428 DQM0 = 136, DQM1 = 133
8826 12:43:22.279099 DQ Delay:
8827 12:43:22.282409 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8828 12:43:22.285923 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8829 12:43:22.289436 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8830 12:43:22.292743 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8831 12:43:22.292825
8832 12:43:22.292889
8833 12:43:22.292948 ==
8834 12:43:22.296156 Dram Type= 6, Freq= 0, CH_1, rank 1
8835 12:43:22.299637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8836 12:43:22.299718 ==
8837 12:43:22.299782
8838 12:43:22.302990
8839 12:43:22.303070 TX Vref Scan disable
8840 12:43:22.306192 == TX Byte 0 ==
8841 12:43:22.309482 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8842 12:43:22.312711 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8843 12:43:22.315896 == TX Byte 1 ==
8844 12:43:22.319075 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8845 12:43:22.322472 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8846 12:43:22.322553 ==
8847 12:43:22.325813 Dram Type= 6, Freq= 0, CH_1, rank 1
8848 12:43:22.332485 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8849 12:43:22.332566 ==
8850 12:43:22.344988
8851 12:43:22.348299 TX Vref early break, caculate TX vref
8852 12:43:22.351769 TX Vref=16, minBit 0, minWin=23, winSum=379
8853 12:43:22.354552 TX Vref=18, minBit 1, minWin=24, winSum=399
8854 12:43:22.357902 TX Vref=20, minBit 4, minWin=24, winSum=405
8855 12:43:22.361169 TX Vref=22, minBit 0, minWin=23, winSum=407
8856 12:43:22.364935 TX Vref=24, minBit 0, minWin=25, winSum=419
8857 12:43:22.371052 TX Vref=26, minBit 0, minWin=26, winSum=425
8858 12:43:22.374799 TX Vref=28, minBit 0, minWin=24, winSum=421
8859 12:43:22.377786 TX Vref=30, minBit 0, minWin=25, winSum=421
8860 12:43:22.381043 TX Vref=32, minBit 1, minWin=25, winSum=416
8861 12:43:22.384526 TX Vref=34, minBit 0, minWin=24, winSum=403
8862 12:43:22.387831 TX Vref=36, minBit 1, minWin=23, winSum=394
8863 12:43:22.394228 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 26
8864 12:43:22.394309
8865 12:43:22.397604 Final TX Range 0 Vref 26
8866 12:43:22.397684
8867 12:43:22.397747 ==
8868 12:43:22.401030 Dram Type= 6, Freq= 0, CH_1, rank 1
8869 12:43:22.404569 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8870 12:43:22.404649 ==
8871 12:43:22.404713
8872 12:43:22.407984
8873 12:43:22.408089 TX Vref Scan disable
8874 12:43:22.414744 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8875 12:43:22.414824 == TX Byte 0 ==
8876 12:43:22.417588 u2DelayCellOfst[0]=17 cells (5 PI)
8877 12:43:22.421014 u2DelayCellOfst[1]=10 cells (3 PI)
8878 12:43:22.424218 u2DelayCellOfst[2]=0 cells (0 PI)
8879 12:43:22.427365 u2DelayCellOfst[3]=6 cells (2 PI)
8880 12:43:22.430604 u2DelayCellOfst[4]=10 cells (3 PI)
8881 12:43:22.433894 u2DelayCellOfst[5]=17 cells (5 PI)
8882 12:43:22.437216 u2DelayCellOfst[6]=17 cells (5 PI)
8883 12:43:22.440671 u2DelayCellOfst[7]=6 cells (2 PI)
8884 12:43:22.444092 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8885 12:43:22.447249 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8886 12:43:22.450894 == TX Byte 1 ==
8887 12:43:22.454145 u2DelayCellOfst[8]=0 cells (0 PI)
8888 12:43:22.457249 u2DelayCellOfst[9]=3 cells (1 PI)
8889 12:43:22.460704 u2DelayCellOfst[10]=6 cells (2 PI)
8890 12:43:22.460785 u2DelayCellOfst[11]=3 cells (1 PI)
8891 12:43:22.464060 u2DelayCellOfst[12]=13 cells (4 PI)
8892 12:43:22.467269 u2DelayCellOfst[13]=13 cells (4 PI)
8893 12:43:22.470404 u2DelayCellOfst[14]=13 cells (4 PI)
8894 12:43:22.473786 u2DelayCellOfst[15]=17 cells (5 PI)
8895 12:43:22.480082 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8896 12:43:22.484064 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8897 12:43:22.484146 DramC Write-DBI on
8898 12:43:22.487363 ==
8899 12:43:22.487444 Dram Type= 6, Freq= 0, CH_1, rank 1
8900 12:43:22.493587 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8901 12:43:22.493668 ==
8902 12:43:22.493732
8903 12:43:22.493791
8904 12:43:22.497149 TX Vref Scan disable
8905 12:43:22.497229 == TX Byte 0 ==
8906 12:43:22.503787 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8907 12:43:22.503869 == TX Byte 1 ==
8908 12:43:22.507235 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8909 12:43:22.510003 DramC Write-DBI off
8910 12:43:22.510084
8911 12:43:22.510148 [DATLAT]
8912 12:43:22.513430 Freq=1600, CH1 RK1
8913 12:43:22.513511
8914 12:43:22.513575 DATLAT Default: 0xf
8915 12:43:22.516827 0, 0xFFFF, sum = 0
8916 12:43:22.516909 1, 0xFFFF, sum = 0
8917 12:43:22.520250 2, 0xFFFF, sum = 0
8918 12:43:22.520385 3, 0xFFFF, sum = 0
8919 12:43:22.523686 4, 0xFFFF, sum = 0
8920 12:43:22.523768 5, 0xFFFF, sum = 0
8921 12:43:22.526566 6, 0xFFFF, sum = 0
8922 12:43:22.526648 7, 0xFFFF, sum = 0
8923 12:43:22.530032 8, 0xFFFF, sum = 0
8924 12:43:22.530114 9, 0xFFFF, sum = 0
8925 12:43:22.533387 10, 0xFFFF, sum = 0
8926 12:43:22.536614 11, 0xFFFF, sum = 0
8927 12:43:22.536697 12, 0xFFFF, sum = 0
8928 12:43:22.539835 13, 0xFFFF, sum = 0
8929 12:43:22.539916 14, 0x0, sum = 1
8930 12:43:22.543594 15, 0x0, sum = 2
8931 12:43:22.543676 16, 0x0, sum = 3
8932 12:43:22.546684 17, 0x0, sum = 4
8933 12:43:22.546765 best_step = 15
8934 12:43:22.546830
8935 12:43:22.546889 ==
8936 12:43:22.549902 Dram Type= 6, Freq= 0, CH_1, rank 1
8937 12:43:22.553697 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8938 12:43:22.553778 ==
8939 12:43:22.557077 RX Vref Scan: 0
8940 12:43:22.557160
8941 12:43:22.559926 RX Vref 0 -> 0, step: 1
8942 12:43:22.560006
8943 12:43:22.560070 RX Delay 19 -> 252, step: 4
8944 12:43:22.567032 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8945 12:43:22.570257 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8946 12:43:22.573344 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8947 12:43:22.576513 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8948 12:43:22.580274 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8949 12:43:22.586403 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8950 12:43:22.589991 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8951 12:43:22.593238 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8952 12:43:22.596716 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8953 12:43:22.599743 iDelay=195, Bit 9, Center 120 (67 ~ 174) 108
8954 12:43:22.606473 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8955 12:43:22.609807 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8956 12:43:22.613205 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8957 12:43:22.616627 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8958 12:43:22.623204 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8959 12:43:22.626562 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8960 12:43:22.626643 ==
8961 12:43:22.629988 Dram Type= 6, Freq= 0, CH_1, rank 1
8962 12:43:22.632780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8963 12:43:22.632861 ==
8964 12:43:22.632925 DQS Delay:
8965 12:43:22.636279 DQS0 = 0, DQS1 = 0
8966 12:43:22.636367 DQM Delay:
8967 12:43:22.639857 DQM0 = 134, DQM1 = 130
8968 12:43:22.639938 DQ Delay:
8969 12:43:22.643280 DQ0 =138, DQ1 =132, DQ2 =122, DQ3 =130
8970 12:43:22.646590 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8971 12:43:22.649947 DQ8 =118, DQ9 =120, DQ10 =132, DQ11 =124
8972 12:43:22.656130 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =138
8973 12:43:22.656236
8974 12:43:22.656375
8975 12:43:22.656442
8976 12:43:22.656499 [DramC_TX_OE_Calibration] TA2
8977 12:43:22.659414 Original DQ_B0 (3 6) =30, OEN = 27
8978 12:43:22.663092 Original DQ_B1 (3 6) =30, OEN = 27
8979 12:43:22.666209 24, 0x0, End_B0=24 End_B1=24
8980 12:43:22.669524 25, 0x0, End_B0=25 End_B1=25
8981 12:43:22.672961 26, 0x0, End_B0=26 End_B1=26
8982 12:43:22.673043 27, 0x0, End_B0=27 End_B1=27
8983 12:43:22.676342 28, 0x0, End_B0=28 End_B1=28
8984 12:43:22.679523 29, 0x0, End_B0=29 End_B1=29
8985 12:43:22.682703 30, 0x0, End_B0=30 End_B1=30
8986 12:43:22.686300 31, 0x4545, End_B0=30 End_B1=30
8987 12:43:22.686382 Byte0 end_step=30 best_step=27
8988 12:43:22.689661 Byte1 end_step=30 best_step=27
8989 12:43:22.692749 Byte0 TX OE(2T, 0.5T) = (3, 3)
8990 12:43:22.696404 Byte1 TX OE(2T, 0.5T) = (3, 3)
8991 12:43:22.696485
8992 12:43:22.696548
8993 12:43:22.705999 [DQSOSCAuto] RK1, (LSB)MR18= 0x250a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
8994 12:43:22.706082 CH1 RK1: MR19=303, MR18=250A
8995 12:43:22.712456 CH1_RK1: MR19=0x303, MR18=0x250A, DQSOSC=391, MR23=63, INC=24, DEC=16
8996 12:43:22.716027 [RxdqsGatingPostProcess] freq 1600
8997 12:43:22.722816 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8998 12:43:22.726206 best DQS0 dly(2T, 0.5T) = (1, 1)
8999 12:43:22.729661 best DQS1 dly(2T, 0.5T) = (1, 1)
9000 12:43:22.733098 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9001 12:43:22.733179 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9002 12:43:22.735827 best DQS0 dly(2T, 0.5T) = (1, 1)
9003 12:43:22.739282 best DQS1 dly(2T, 0.5T) = (1, 1)
9004 12:43:22.742695 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9005 12:43:22.746114 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9006 12:43:22.749664 Pre-setting of DQS Precalculation
9007 12:43:22.753075 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9008 12:43:22.763065 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9009 12:43:22.769327 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9010 12:43:22.769408
9011 12:43:22.769472
9012 12:43:22.772489 [Calibration Summary] 3200 Mbps
9013 12:43:22.772570 CH 0, Rank 0
9014 12:43:22.776273 SW Impedance : PASS
9015 12:43:22.776364 DUTY Scan : NO K
9016 12:43:22.779372 ZQ Calibration : PASS
9017 12:43:22.782609 Jitter Meter : NO K
9018 12:43:22.782689 CBT Training : PASS
9019 12:43:22.786137 Write leveling : PASS
9020 12:43:22.788969 RX DQS gating : PASS
9021 12:43:22.789050 RX DQ/DQS(RDDQC) : PASS
9022 12:43:22.792428 TX DQ/DQS : PASS
9023 12:43:22.795883 RX DATLAT : PASS
9024 12:43:22.795964 RX DQ/DQS(Engine): PASS
9025 12:43:22.798867 TX OE : PASS
9026 12:43:22.798957 All Pass.
9027 12:43:22.799021
9028 12:43:22.802829 CH 0, Rank 1
9029 12:43:22.802914 SW Impedance : PASS
9030 12:43:22.805777 DUTY Scan : NO K
9031 12:43:22.809237 ZQ Calibration : PASS
9032 12:43:22.809318 Jitter Meter : NO K
9033 12:43:22.812203 CBT Training : PASS
9034 12:43:22.815709 Write leveling : PASS
9035 12:43:22.815789 RX DQS gating : PASS
9036 12:43:22.819063 RX DQ/DQS(RDDQC) : PASS
9037 12:43:22.819145 TX DQ/DQS : PASS
9038 12:43:22.822488 RX DATLAT : PASS
9039 12:43:22.825860 RX DQ/DQS(Engine): PASS
9040 12:43:22.825940 TX OE : PASS
9041 12:43:22.829093 All Pass.
9042 12:43:22.829199
9043 12:43:22.829291 CH 1, Rank 0
9044 12:43:22.832777 SW Impedance : PASS
9045 12:43:22.832857 DUTY Scan : NO K
9046 12:43:22.835688 ZQ Calibration : PASS
9047 12:43:22.839474 Jitter Meter : NO K
9048 12:43:22.839555 CBT Training : PASS
9049 12:43:22.842358 Write leveling : PASS
9050 12:43:22.845777 RX DQS gating : PASS
9051 12:43:22.845858 RX DQ/DQS(RDDQC) : PASS
9052 12:43:22.849190 TX DQ/DQS : PASS
9053 12:43:22.852627 RX DATLAT : PASS
9054 12:43:22.852708 RX DQ/DQS(Engine): PASS
9055 12:43:22.855970 TX OE : PASS
9056 12:43:22.856051 All Pass.
9057 12:43:22.856115
9058 12:43:22.858717 CH 1, Rank 1
9059 12:43:22.858798 SW Impedance : PASS
9060 12:43:22.862193 DUTY Scan : NO K
9061 12:43:22.865510 ZQ Calibration : PASS
9062 12:43:22.865591 Jitter Meter : NO K
9063 12:43:22.868827 CBT Training : PASS
9064 12:43:22.872242 Write leveling : PASS
9065 12:43:22.872344 RX DQS gating : PASS
9066 12:43:22.875793 RX DQ/DQS(RDDQC) : PASS
9067 12:43:22.875874 TX DQ/DQS : PASS
9068 12:43:22.878623 RX DATLAT : PASS
9069 12:43:22.882055 RX DQ/DQS(Engine): PASS
9070 12:43:22.882136 TX OE : PASS
9071 12:43:22.885833 All Pass.
9072 12:43:22.885913
9073 12:43:22.885977 DramC Write-DBI on
9074 12:43:22.889058 PER_BANK_REFRESH: Hybrid Mode
9075 12:43:22.892240 TX_TRACKING: ON
9076 12:43:22.898436 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9077 12:43:22.908966 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9078 12:43:22.915416 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9079 12:43:22.918684 [FAST_K] Save calibration result to emmc
9080 12:43:22.921830 sync common calibartion params.
9081 12:43:22.921911 sync cbt_mode0:1, 1:1
9082 12:43:22.925344 dram_init: ddr_geometry: 2
9083 12:43:22.928272 dram_init: ddr_geometry: 2
9084 12:43:22.931659 dram_init: ddr_geometry: 2
9085 12:43:22.931739 0:dram_rank_size:100000000
9086 12:43:22.935130 1:dram_rank_size:100000000
9087 12:43:22.941799 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9088 12:43:22.941880 DFS_SHUFFLE_HW_MODE: ON
9089 12:43:22.948711 dramc_set_vcore_voltage set vcore to 725000
9090 12:43:22.948792 Read voltage for 1600, 0
9091 12:43:22.948856 Vio18 = 0
9092 12:43:22.951961 Vcore = 725000
9093 12:43:22.952042 Vdram = 0
9094 12:43:22.952105 Vddq = 0
9095 12:43:22.955464 Vmddr = 0
9096 12:43:22.955545 switch to 3200 Mbps bootup
9097 12:43:22.958948 [DramcRunTimeConfig]
9098 12:43:22.959029 PHYPLL
9099 12:43:22.961773 DPM_CONTROL_AFTERK: ON
9100 12:43:22.961855 PER_BANK_REFRESH: ON
9101 12:43:22.965140 REFRESH_OVERHEAD_REDUCTION: ON
9102 12:43:22.968436 CMD_PICG_NEW_MODE: OFF
9103 12:43:22.968516 XRTWTW_NEW_MODE: ON
9104 12:43:22.972083 XRTRTR_NEW_MODE: ON
9105 12:43:22.972163 TX_TRACKING: ON
9106 12:43:22.975317 RDSEL_TRACKING: OFF
9107 12:43:22.978182 DQS Precalculation for DVFS: ON
9108 12:43:22.978263 RX_TRACKING: OFF
9109 12:43:22.981713 HW_GATING DBG: ON
9110 12:43:22.981794 ZQCS_ENABLE_LP4: ON
9111 12:43:22.985119 RX_PICG_NEW_MODE: ON
9112 12:43:22.985208 TX_PICG_NEW_MODE: ON
9113 12:43:22.988473 ENABLE_RX_DCM_DPHY: ON
9114 12:43:22.991944 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9115 12:43:22.994785 DUMMY_READ_FOR_TRACKING: OFF
9116 12:43:22.998122 !!! SPM_CONTROL_AFTERK: OFF
9117 12:43:22.998211 !!! SPM could not control APHY
9118 12:43:23.001961 IMPEDANCE_TRACKING: ON
9119 12:43:23.002042 TEMP_SENSOR: ON
9120 12:43:23.005179 HW_SAVE_FOR_SR: OFF
9121 12:43:23.008637 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9122 12:43:23.011429 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9123 12:43:23.014772 Read ODT Tracking: ON
9124 12:43:23.014853 Refresh Rate DeBounce: ON
9125 12:43:23.018078 DFS_NO_QUEUE_FLUSH: ON
9126 12:43:23.021519 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9127 12:43:23.024791 ENABLE_DFS_RUNTIME_MRW: OFF
9128 12:43:23.024881 DDR_RESERVE_NEW_MODE: ON
9129 12:43:23.028147 MR_CBT_SWITCH_FREQ: ON
9130 12:43:23.031610 =========================
9131 12:43:23.049019 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9132 12:43:23.052422 dram_init: ddr_geometry: 2
9133 12:43:23.070864 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9134 12:43:23.074288 dram_init: dram init end (result: 0)
9135 12:43:23.081018 DRAM-K: Full calibration passed in 24456 msecs
9136 12:43:23.083846 MRC: failed to locate region type 0.
9137 12:43:23.083926 DRAM rank0 size:0x100000000,
9138 12:43:23.087194 DRAM rank1 size=0x100000000
9139 12:43:23.097498 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9140 12:43:23.103781 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9141 12:43:23.110323 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9142 12:43:23.117330 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9143 12:43:23.120857 DRAM rank0 size:0x100000000,
9144 12:43:23.124140 DRAM rank1 size=0x100000000
9145 12:43:23.124247 CBMEM:
9146 12:43:23.127534 IMD: root @ 0xfffff000 254 entries.
9147 12:43:23.130908 IMD: root @ 0xffffec00 62 entries.
9148 12:43:23.133761 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9149 12:43:23.137054 WARNING: RO_VPD is uninitialized or empty.
9150 12:43:23.143982 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9151 12:43:23.150772 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9152 12:43:23.163386 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9153 12:43:23.174913 BS: romstage times (exec / console): total (unknown) / 23988 ms
9154 12:43:23.174996
9155 12:43:23.175059
9156 12:43:23.184991 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9157 12:43:23.188451 ARM64: Exception handlers installed.
9158 12:43:23.192093 ARM64: Testing exception
9159 12:43:23.194783 ARM64: Done test exception
9160 12:43:23.194864 Enumerating buses...
9161 12:43:23.198178 Show all devs... Before device enumeration.
9162 12:43:23.201625 Root Device: enabled 1
9163 12:43:23.204872 CPU_CLUSTER: 0: enabled 1
9164 12:43:23.204952 CPU: 00: enabled 1
9165 12:43:23.208485 Compare with tree...
9166 12:43:23.208566 Root Device: enabled 1
9167 12:43:23.211309 CPU_CLUSTER: 0: enabled 1
9168 12:43:23.214709 CPU: 00: enabled 1
9169 12:43:23.214789 Root Device scanning...
9170 12:43:23.218124 scan_static_bus for Root Device
9171 12:43:23.221252 CPU_CLUSTER: 0 enabled
9172 12:43:23.225230 scan_static_bus for Root Device done
9173 12:43:23.228207 scan_bus: bus Root Device finished in 8 msecs
9174 12:43:23.228319 done
9175 12:43:23.234677 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9176 12:43:23.237818 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9177 12:43:23.244813 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9178 12:43:23.247629 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9179 12:43:23.251078 Allocating resources...
9180 12:43:23.254451 Reading resources...
9181 12:43:23.257908 Root Device read_resources bus 0 link: 0
9182 12:43:23.257989 DRAM rank0 size:0x100000000,
9183 12:43:23.261255 DRAM rank1 size=0x100000000
9184 12:43:23.264696 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9185 12:43:23.267474 CPU: 00 missing read_resources
9186 12:43:23.270907 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9187 12:43:23.277563 Root Device read_resources bus 0 link: 0 done
9188 12:43:23.277644 Done reading resources.
9189 12:43:23.284217 Show resources in subtree (Root Device)...After reading.
9190 12:43:23.287612 Root Device child on link 0 CPU_CLUSTER: 0
9191 12:43:23.290703 CPU_CLUSTER: 0 child on link 0 CPU: 00
9192 12:43:23.300807 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9193 12:43:23.300890 CPU: 00
9194 12:43:23.304108 Root Device assign_resources, bus 0 link: 0
9195 12:43:23.307761 CPU_CLUSTER: 0 missing set_resources
9196 12:43:23.313956 Root Device assign_resources, bus 0 link: 0 done
9197 12:43:23.314038 Done setting resources.
9198 12:43:23.320669 Show resources in subtree (Root Device)...After assigning values.
9199 12:43:23.324154 Root Device child on link 0 CPU_CLUSTER: 0
9200 12:43:23.327712 CPU_CLUSTER: 0 child on link 0 CPU: 00
9201 12:43:23.337067 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9202 12:43:23.337149 CPU: 00
9203 12:43:23.340610 Done allocating resources.
9204 12:43:23.344127 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9205 12:43:23.347292 Enabling resources...
9206 12:43:23.347373 done.
9207 12:43:23.354173 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9208 12:43:23.354254 Initializing devices...
9209 12:43:23.357102 Root Device init
9210 12:43:23.357183 init hardware done!
9211 12:43:23.360235 0x00000018: ctrlr->caps
9212 12:43:23.363772 52.000 MHz: ctrlr->f_max
9213 12:43:23.363854 0.400 MHz: ctrlr->f_min
9214 12:43:23.367318 0x40ff8080: ctrlr->voltages
9215 12:43:23.370811 sclk: 390625
9216 12:43:23.370892 Bus Width = 1
9217 12:43:23.370956 sclk: 390625
9218 12:43:23.373528 Bus Width = 1
9219 12:43:23.373609 Early init status = 3
9220 12:43:23.380211 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9221 12:43:23.383621 in-header: 03 fc 00 00 01 00 00 00
9222 12:43:23.387128 in-data: 00
9223 12:43:23.390507 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9224 12:43:23.395883 in-header: 03 fd 00 00 00 00 00 00
9225 12:43:23.398749 in-data:
9226 12:43:23.402251 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9227 12:43:23.406462 in-header: 03 fc 00 00 01 00 00 00
9228 12:43:23.409932 in-data: 00
9229 12:43:23.412901 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9230 12:43:23.418657 in-header: 03 fd 00 00 00 00 00 00
9231 12:43:23.421994 in-data:
9232 12:43:23.425259 [SSUSB] Setting up USB HOST controller...
9233 12:43:23.429040 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9234 12:43:23.432138 [SSUSB] phy power-on done.
9235 12:43:23.435724 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9236 12:43:23.441838 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9237 12:43:23.445804 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9238 12:43:23.452072 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9239 12:43:23.458934 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9240 12:43:23.465753 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9241 12:43:23.471792 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9242 12:43:23.478805 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9243 12:43:23.481679 SPM: binary array size = 0x9dc
9244 12:43:23.484960 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9245 12:43:23.491973 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9246 12:43:23.498214 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9247 12:43:23.501554 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9248 12:43:23.508488 configure_display: Starting display init
9249 12:43:23.542010 anx7625_power_on_init: Init interface.
9250 12:43:23.545336 anx7625_disable_pd_protocol: Disabled PD feature.
9251 12:43:23.548767 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9252 12:43:23.576307 anx7625_start_dp_work: Secure OCM version=00
9253 12:43:23.580061 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9254 12:43:23.594520 sp_tx_get_edid_block: EDID Block = 1
9255 12:43:23.697077 Extracted contents:
9256 12:43:23.700115 header: 00 ff ff ff ff ff ff 00
9257 12:43:23.703994 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9258 12:43:23.707026 version: 01 04
9259 12:43:23.710227 basic params: 95 1f 11 78 0a
9260 12:43:23.714140 chroma info: 76 90 94 55 54 90 27 21 50 54
9261 12:43:23.717478 established: 00 00 00
9262 12:43:23.720280 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9263 12:43:23.727320 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9264 12:43:23.734207 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9265 12:43:23.740396 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9266 12:43:23.747170 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9267 12:43:23.750577 extensions: 00
9268 12:43:23.750658 checksum: fb
9269 12:43:23.750722
9270 12:43:23.754088 Manufacturer: IVO Model 57d Serial Number 0
9271 12:43:23.756851 Made week 0 of 2020
9272 12:43:23.756932 EDID version: 1.4
9273 12:43:23.760073 Digital display
9274 12:43:23.763667 6 bits per primary color channel
9275 12:43:23.763750 DisplayPort interface
9276 12:43:23.766970 Maximum image size: 31 cm x 17 cm
9277 12:43:23.770451 Gamma: 220%
9278 12:43:23.770532 Check DPMS levels
9279 12:43:23.773720 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9280 12:43:23.776894 First detailed timing is preferred timing
9281 12:43:23.780504 Established timings supported:
9282 12:43:23.783383 Standard timings supported:
9283 12:43:23.783464 Detailed timings
9284 12:43:23.790314 Hex of detail: 383680a07038204018303c0035ae10000019
9285 12:43:23.793385 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9286 12:43:23.799721 0780 0798 07c8 0820 hborder 0
9287 12:43:23.803573 0438 043b 0447 0458 vborder 0
9288 12:43:23.806752 -hsync -vsync
9289 12:43:23.806834 Did detailed timing
9290 12:43:23.809906 Hex of detail: 000000000000000000000000000000000000
9291 12:43:23.813291 Manufacturer-specified data, tag 0
9292 12:43:23.820081 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9293 12:43:23.820162 ASCII string: InfoVision
9294 12:43:23.826931 Hex of detail: 000000fe00523134304e574635205248200a
9295 12:43:23.830241 ASCII string: R140NWF5 RH
9296 12:43:23.830321 Checksum
9297 12:43:23.830385 Checksum: 0xfb (valid)
9298 12:43:23.837003 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9299 12:43:23.839841 DSI data_rate: 832800000 bps
9300 12:43:23.843149 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9301 12:43:23.850261 anx7625_parse_edid: pixelclock(138800).
9302 12:43:23.853021 hactive(1920), hsync(48), hfp(24), hbp(88)
9303 12:43:23.856676 vactive(1080), vsync(12), vfp(3), vbp(17)
9304 12:43:23.860037 anx7625_dsi_config: config dsi.
9305 12:43:23.866765 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9306 12:43:23.879353 anx7625_dsi_config: success to config DSI
9307 12:43:23.882766 anx7625_dp_start: MIPI phy setup OK.
9308 12:43:23.885549 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9309 12:43:23.889476 mtk_ddp_mode_set invalid vrefresh 60
9310 12:43:23.892782 main_disp_path_setup
9311 12:43:23.892861 ovl_layer_smi_id_en
9312 12:43:23.895796 ovl_layer_smi_id_en
9313 12:43:23.895876 ccorr_config
9314 12:43:23.895939 aal_config
9315 12:43:23.898892 gamma_config
9316 12:43:23.898971 postmask_config
9317 12:43:23.902129 dither_config
9318 12:43:23.905413 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9319 12:43:23.912245 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9320 12:43:23.915419 Root Device init finished in 555 msecs
9321 12:43:23.918684 CPU_CLUSTER: 0 init
9322 12:43:23.925973 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9323 12:43:23.929230 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9324 12:43:23.932086 APU_MBOX 0x190000b0 = 0x10001
9325 12:43:23.935309 APU_MBOX 0x190001b0 = 0x10001
9326 12:43:23.939105 APU_MBOX 0x190005b0 = 0x10001
9327 12:43:23.942251 APU_MBOX 0x190006b0 = 0x10001
9328 12:43:23.945420 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9329 12:43:23.958309 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9330 12:43:23.971111 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9331 12:43:23.977501 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9332 12:43:23.989062 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9333 12:43:23.998062 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9334 12:43:24.001197 CPU_CLUSTER: 0 init finished in 81 msecs
9335 12:43:24.004434 Devices initialized
9336 12:43:24.007594 Show all devs... After init.
9337 12:43:24.007676 Root Device: enabled 1
9338 12:43:24.010982 CPU_CLUSTER: 0: enabled 1
9339 12:43:24.014340 CPU: 00: enabled 1
9340 12:43:24.017653 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9341 12:43:24.020947 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9342 12:43:24.024684 ELOG: NV offset 0x57f000 size 0x1000
9343 12:43:24.031200 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9344 12:43:24.037770 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9345 12:43:24.041104 ELOG: Event(17) added with size 13 at 2024-02-05 12:40:40 UTC
9346 12:43:24.044693 out: cmd=0x121: 03 db 21 01 00 00 00 00
9347 12:43:24.047941 in-header: 03 d9 00 00 2c 00 00 00
9348 12:43:24.061222 in-data: 86 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9349 12:43:24.068215 ELOG: Event(A1) added with size 10 at 2024-02-05 12:40:40 UTC
9350 12:43:24.075040 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9351 12:43:24.078356 ELOG: Event(A0) added with size 9 at 2024-02-05 12:40:40 UTC
9352 12:43:24.085062 elog_add_boot_reason: Logged dev mode boot
9353 12:43:24.088442 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9354 12:43:24.091851 Finalize devices...
9355 12:43:24.091933 Devices finalized
9356 12:43:24.098819 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9357 12:43:24.101590 Writing coreboot table at 0xffe64000
9358 12:43:24.105004 0. 000000000010a000-0000000000113fff: RAMSTAGE
9359 12:43:24.108420 1. 0000000040000000-00000000400fffff: RAM
9360 12:43:24.111459 2. 0000000040100000-000000004032afff: RAMSTAGE
9361 12:43:24.118400 3. 000000004032b000-00000000545fffff: RAM
9362 12:43:24.121718 4. 0000000054600000-000000005465ffff: BL31
9363 12:43:24.125190 5. 0000000054660000-00000000ffe63fff: RAM
9364 12:43:24.128584 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9365 12:43:24.135183 7. 0000000100000000-000000023fffffff: RAM
9366 12:43:24.135264 Passing 5 GPIOs to payload:
9367 12:43:24.141781 NAME | PORT | POLARITY | VALUE
9368 12:43:24.145169 EC in RW | 0x000000aa | low | undefined
9369 12:43:24.148247 EC interrupt | 0x00000005 | low | undefined
9370 12:43:24.154887 TPM interrupt | 0x000000ab | high | undefined
9371 12:43:24.158385 SD card detect | 0x00000011 | high | undefined
9372 12:43:24.165033 speaker enable | 0x00000093 | high | undefined
9373 12:43:24.168233 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9374 12:43:24.171602 in-header: 03 f9 00 00 02 00 00 00
9375 12:43:24.171683 in-data: 02 00
9376 12:43:24.175111 ADC[4]: Raw value=904726 ID=7
9377 12:43:24.178509 ADC[3]: Raw value=213441 ID=1
9378 12:43:24.178615 RAM Code: 0x71
9379 12:43:24.181288 ADC[6]: Raw value=75332 ID=0
9380 12:43:24.184699 ADC[5]: Raw value=213441 ID=1
9381 12:43:24.184779 SKU Code: 0x1
9382 12:43:24.191390 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 6c95
9383 12:43:24.194627 coreboot table: 964 bytes.
9384 12:43:24.198126 IMD ROOT 0. 0xfffff000 0x00001000
9385 12:43:24.201647 IMD SMALL 1. 0xffffe000 0x00001000
9386 12:43:24.205099 RO MCACHE 2. 0xffffc000 0x00001104
9387 12:43:24.208471 CONSOLE 3. 0xfff7c000 0x00080000
9388 12:43:24.211158 FMAP 4. 0xfff7b000 0x00000452
9389 12:43:24.214561 TIME STAMP 5. 0xfff7a000 0x00000910
9390 12:43:24.217833 VBOOT WORK 6. 0xfff66000 0x00014000
9391 12:43:24.221261 RAMOOPS 7. 0xffe66000 0x00100000
9392 12:43:24.224478 COREBOOT 8. 0xffe64000 0x00002000
9393 12:43:24.224595 IMD small region:
9394 12:43:24.227730 IMD ROOT 0. 0xffffec00 0x00000400
9395 12:43:24.231360 VPD 1. 0xffffeb80 0x0000006c
9396 12:43:24.234907 MMC STATUS 2. 0xffffeb60 0x00000004
9397 12:43:24.241488 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9398 12:43:24.241605 Probing TPM: done!
9399 12:43:24.248244 Connected to device vid:did:rid of 1ae0:0028:00
9400 12:43:24.254773 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9401 12:43:24.262514 Initialized TPM device CR50 revision 0
9402 12:43:24.262667 Checking cr50 for pending updates
9403 12:43:24.267829 Reading cr50 TPM mode
9404 12:43:24.276258 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9405 12:43:24.282823 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9406 12:43:24.323509 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9407 12:43:24.327292 Checking segment from ROM address 0x40100000
9408 12:43:24.330760 Checking segment from ROM address 0x4010001c
9409 12:43:24.336848 Loading segment from ROM address 0x40100000
9410 12:43:24.337313 code (compression=0)
9411 12:43:24.347071 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9412 12:43:24.353831 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9413 12:43:24.354256 it's not compressed!
9414 12:43:24.360137 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9415 12:43:24.363618 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9416 12:43:24.384175 Loading segment from ROM address 0x4010001c
9417 12:43:24.384917 Entry Point 0x80000000
9418 12:43:24.387239 Loaded segments
9419 12:43:24.390710 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9420 12:43:24.397300 Jumping to boot code at 0x80000000(0xffe64000)
9421 12:43:24.403963 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9422 12:43:24.410637 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9423 12:43:24.418555 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9424 12:43:24.422348 Checking segment from ROM address 0x40100000
9425 12:43:24.425751 Checking segment from ROM address 0x4010001c
9426 12:43:24.432058 Loading segment from ROM address 0x40100000
9427 12:43:24.432665 code (compression=1)
9428 12:43:24.438577 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9429 12:43:24.449044 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9430 12:43:24.449585 using LZMA
9431 12:43:24.457362 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9432 12:43:24.463762 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9433 12:43:24.467156 Loading segment from ROM address 0x4010001c
9434 12:43:24.467716 Entry Point 0x54601000
9435 12:43:24.470754 Loaded segments
9436 12:43:24.473879 NOTICE: MT8192 bl31_setup
9437 12:43:24.481090 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9438 12:43:24.484154 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9439 12:43:24.487533 WARNING: region 0:
9440 12:43:24.491000 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9441 12:43:24.491550 WARNING: region 1:
9442 12:43:24.497663 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9443 12:43:24.500081 WARNING: region 2:
9444 12:43:24.503914 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9445 12:43:24.507084 WARNING: region 3:
9446 12:43:24.510589 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9447 12:43:24.513945 WARNING: region 4:
9448 12:43:24.520762 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9449 12:43:24.521317 WARNING: region 5:
9450 12:43:24.523798 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9451 12:43:24.527468 WARNING: region 6:
9452 12:43:24.530364 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9453 12:43:24.530828 WARNING: region 7:
9454 12:43:24.536906 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9455 12:43:24.543801 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9456 12:43:24.547173 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9457 12:43:24.550452 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9458 12:43:24.557273 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9459 12:43:24.560867 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9460 12:43:24.564521 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9461 12:43:24.570624 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9462 12:43:24.573810 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9463 12:43:24.577348 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9464 12:43:24.584547 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9465 12:43:24.588036 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9466 12:43:24.594681 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9467 12:43:24.597203 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9468 12:43:24.601011 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9469 12:43:24.607076 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9470 12:43:24.610971 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9471 12:43:24.614684 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9472 12:43:24.621032 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9473 12:43:24.624207 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9474 12:43:24.627557 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9475 12:43:24.633894 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9476 12:43:24.637589 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9477 12:43:24.643868 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9478 12:43:24.647489 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9479 12:43:24.654125 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9480 12:43:24.657706 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9481 12:43:24.660928 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9482 12:43:24.668189 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9483 12:43:24.671002 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9484 12:43:24.674170 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9485 12:43:24.681227 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9486 12:43:24.684680 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9487 12:43:24.687649 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9488 12:43:24.694620 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9489 12:43:24.698069 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9490 12:43:24.701317 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9491 12:43:24.704384 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9492 12:43:24.711586 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9493 12:43:24.714090 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9494 12:43:24.717604 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9495 12:43:24.721267 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9496 12:43:24.727635 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9497 12:43:24.730840 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9498 12:43:24.734587 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9499 12:43:24.737643 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9500 12:43:24.744283 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9501 12:43:24.747539 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9502 12:43:24.751075 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9503 12:43:24.757459 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9504 12:43:24.760776 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9505 12:43:24.764629 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9506 12:43:24.771198 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9507 12:43:24.774060 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9508 12:43:24.781363 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9509 12:43:24.784434 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9510 12:43:24.791388 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9511 12:43:24.794797 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9512 12:43:24.797310 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9513 12:43:24.804244 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9514 12:43:24.807622 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9515 12:43:24.814596 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9516 12:43:24.817813 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9517 12:43:24.824147 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9518 12:43:24.827877 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9519 12:43:24.831118 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9520 12:43:24.837772 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9521 12:43:24.841248 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9522 12:43:24.847462 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9523 12:43:24.851222 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9524 12:43:24.857587 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9525 12:43:24.860959 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9526 12:43:24.864201 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9527 12:43:24.871168 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9528 12:43:24.874557 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9529 12:43:24.881012 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9530 12:43:24.884672 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9531 12:43:24.890919 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9532 12:43:24.894409 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9533 12:43:24.897723 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9534 12:43:24.904728 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9535 12:43:24.908123 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9536 12:43:24.914557 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9537 12:43:24.917754 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9538 12:43:24.924789 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9539 12:43:24.928008 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9540 12:43:24.931745 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9541 12:43:24.938014 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9542 12:43:24.941581 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9543 12:43:24.947914 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9544 12:43:24.951384 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9545 12:43:24.958313 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9546 12:43:24.961548 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9547 12:43:24.964834 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9548 12:43:24.971005 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9549 12:43:24.974689 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9550 12:43:24.981470 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9551 12:43:24.985049 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9552 12:43:24.988175 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9553 12:43:24.991590 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9554 12:43:24.997911 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9555 12:43:25.001536 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9556 12:43:25.004847 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9557 12:43:25.011306 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9558 12:43:25.014870 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9559 12:43:25.021461 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9560 12:43:25.024930 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9561 12:43:25.028283 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9562 12:43:25.034670 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9563 12:43:25.038405 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9564 12:43:25.044977 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9565 12:43:25.047578 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9566 12:43:25.051525 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9567 12:43:25.057896 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9568 12:43:25.061573 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9569 12:43:25.068176 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9570 12:43:25.071169 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9571 12:43:25.074274 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9572 12:43:25.077770 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9573 12:43:25.084421 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9574 12:43:25.087538 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9575 12:43:25.091321 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9576 12:43:25.094607 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9577 12:43:25.101381 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9578 12:43:25.104831 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9579 12:43:25.107819 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9580 12:43:25.114397 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9581 12:43:25.118234 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9582 12:43:25.125005 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9583 12:43:25.128226 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9584 12:43:25.131685 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9585 12:43:25.137878 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9586 12:43:25.141511 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9587 12:43:25.144941 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9588 12:43:25.151365 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9589 12:43:25.154668 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9590 12:43:25.161178 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9591 12:43:25.164539 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9592 12:43:25.167768 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9593 12:43:25.174621 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9594 12:43:25.178464 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9595 12:43:25.184537 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9596 12:43:25.187795 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9597 12:43:25.191236 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9598 12:43:25.198165 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9599 12:43:25.201278 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9600 12:43:25.204612 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9601 12:43:25.211245 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9602 12:43:25.215016 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9603 12:43:25.221736 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9604 12:43:25.224768 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9605 12:43:25.227952 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9606 12:43:25.234543 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9607 12:43:25.238754 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9608 12:43:25.244590 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9609 12:43:25.248127 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9610 12:43:25.251888 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9611 12:43:25.257907 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9612 12:43:25.261294 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9613 12:43:25.264619 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9614 12:43:25.271497 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9615 12:43:25.274505 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9616 12:43:25.281463 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9617 12:43:25.284838 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9618 12:43:25.288643 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9619 12:43:25.294806 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9620 12:43:25.297902 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9621 12:43:25.304466 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9622 12:43:25.308270 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9623 12:43:25.311634 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9624 12:43:25.318166 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9625 12:43:25.321488 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9626 12:43:25.327879 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9627 12:43:25.331424 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9628 12:43:25.334724 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9629 12:43:25.341316 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9630 12:43:25.344887 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9631 12:43:25.348072 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9632 12:43:25.354698 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9633 12:43:25.357800 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9634 12:43:25.363898 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9635 12:43:25.367645 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9636 12:43:25.371123 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9637 12:43:25.377896 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9638 12:43:25.381131 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9639 12:43:25.387915 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9640 12:43:25.390734 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9641 12:43:25.394081 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9642 12:43:25.400849 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9643 12:43:25.404088 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9644 12:43:25.410984 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9645 12:43:25.414122 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9646 12:43:25.420818 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9647 12:43:25.423530 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9648 12:43:25.427516 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9649 12:43:25.433681 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9650 12:43:25.437120 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9651 12:43:25.444183 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9652 12:43:25.447354 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9653 12:43:25.450506 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9654 12:43:25.456854 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9655 12:43:25.460283 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9656 12:43:25.466788 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9657 12:43:25.470043 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9658 12:43:25.476881 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9659 12:43:25.480439 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9660 12:43:25.483811 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9661 12:43:25.490490 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9662 12:43:25.493255 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9663 12:43:25.500439 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9664 12:43:25.503672 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9665 12:43:25.507178 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9666 12:43:25.513790 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9667 12:43:25.516798 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9668 12:43:25.523109 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9669 12:43:25.526937 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9670 12:43:25.529980 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9671 12:43:25.536772 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9672 12:43:25.539832 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9673 12:43:25.547395 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9674 12:43:25.550336 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9675 12:43:25.556674 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9676 12:43:25.559911 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9677 12:43:25.563176 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9678 12:43:25.570121 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9679 12:43:25.573536 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9680 12:43:25.580184 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9681 12:43:25.583086 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9682 12:43:25.589927 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9683 12:43:25.593516 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9684 12:43:25.596589 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9685 12:43:25.600201 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9686 12:43:25.603663 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9687 12:43:25.609930 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9688 12:43:25.613267 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9689 12:43:25.616977 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9690 12:43:25.623562 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9691 12:43:25.626535 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9692 12:43:25.633230 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9693 12:43:25.636370 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9694 12:43:25.639972 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9695 12:43:25.646238 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9696 12:43:25.649630 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9697 12:43:25.653540 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9698 12:43:25.659924 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9699 12:43:25.663148 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9700 12:43:25.666006 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9701 12:43:25.673361 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9702 12:43:25.676633 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9703 12:43:25.679962 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9704 12:43:25.686667 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9705 12:43:25.689782 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9706 12:43:25.696711 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9707 12:43:25.699539 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9708 12:43:25.703054 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9709 12:43:25.710090 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9710 12:43:25.713230 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9711 12:43:25.716637 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9712 12:43:25.722750 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9713 12:43:25.726296 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9714 12:43:25.729764 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9715 12:43:25.736058 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9716 12:43:25.739684 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9717 12:43:25.745807 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9718 12:43:25.749731 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9719 12:43:25.752659 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9720 12:43:25.759369 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9721 12:43:25.762929 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9722 12:43:25.765758 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9723 12:43:25.772457 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9724 12:43:25.776203 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9725 12:43:25.779285 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9726 12:43:25.782742 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9727 12:43:25.789467 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9728 12:43:25.792715 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9729 12:43:25.795818 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9730 12:43:25.799458 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9731 12:43:25.805850 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9732 12:43:25.809082 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9733 12:43:25.812969 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9734 12:43:25.815872 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9735 12:43:25.822793 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9736 12:43:25.826237 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9737 12:43:25.829705 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9738 12:43:25.835826 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9739 12:43:25.839384 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9740 12:43:25.846221 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9741 12:43:25.849337 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9742 12:43:25.852261 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9743 12:43:25.858989 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9744 12:43:25.862122 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9745 12:43:25.869415 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9746 12:43:25.872361 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9747 12:43:25.875426 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9748 12:43:25.882631 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9749 12:43:25.885700 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9750 12:43:25.892314 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9751 12:43:25.895634 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9752 12:43:25.899113 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9753 12:43:25.905927 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9754 12:43:25.909167 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9755 12:43:25.915853 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9756 12:43:25.918957 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9757 12:43:25.925549 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9758 12:43:25.928985 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9759 12:43:25.932414 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9760 12:43:25.938860 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9761 12:43:25.942439 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9762 12:43:25.948583 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9763 12:43:25.951922 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9764 12:43:25.955042 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9765 12:43:25.962037 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9766 12:43:25.965400 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9767 12:43:25.972149 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9768 12:43:25.974906 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9769 12:43:25.978850 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9770 12:43:25.985169 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9771 12:43:25.988324 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9772 12:43:25.995290 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9773 12:43:25.998632 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9774 12:43:26.002128 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9775 12:43:26.008626 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9776 12:43:26.011692 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9777 12:43:26.018503 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9778 12:43:26.021972 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9779 12:43:26.025027 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9780 12:43:26.031954 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9781 12:43:26.035357 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9782 12:43:26.041751 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9783 12:43:26.045144 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9784 12:43:26.048527 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9785 12:43:26.054986 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9786 12:43:26.058259 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9787 12:43:26.064843 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9788 12:43:26.068402 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9789 12:43:26.075097 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9790 12:43:26.078601 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9791 12:43:26.082109 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9792 12:43:26.088201 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9793 12:43:26.091930 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9794 12:43:26.098453 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9795 12:43:26.101722 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9796 12:43:26.104609 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9797 12:43:26.111644 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9798 12:43:26.114984 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9799 12:43:26.121796 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9800 12:43:26.124831 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9801 12:43:26.127973 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9802 12:43:26.134481 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9803 12:43:26.138251 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9804 12:43:26.144503 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9805 12:43:26.147933 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9806 12:43:26.154665 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9807 12:43:26.158273 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9808 12:43:26.161768 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9809 12:43:26.167904 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9810 12:43:26.171209 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9811 12:43:26.177828 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9812 12:43:26.181223 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9813 12:43:26.184763 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9814 12:43:26.191608 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9815 12:43:26.194282 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9816 12:43:26.201372 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9817 12:43:26.204628 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9818 12:43:26.210724 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9819 12:43:26.213914 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9820 12:43:26.217872 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9821 12:43:26.224251 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9822 12:43:26.227576 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9823 12:43:26.234061 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9824 12:43:26.237322 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9825 12:43:26.244188 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9826 12:43:26.247317 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9827 12:43:26.250380 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9828 12:43:26.257672 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9829 12:43:26.260534 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9830 12:43:26.267353 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9831 12:43:26.271062 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9832 12:43:26.276938 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9833 12:43:26.280277 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9834 12:43:26.287075 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9835 12:43:26.290610 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9836 12:43:26.294003 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9837 12:43:26.300305 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9838 12:43:26.303536 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9839 12:43:26.310354 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9840 12:43:26.313677 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9841 12:43:26.319991 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9842 12:43:26.323536 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9843 12:43:26.326835 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9844 12:43:26.333625 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9845 12:43:26.336691 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9846 12:43:26.343234 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9847 12:43:26.346412 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9848 12:43:26.353647 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9849 12:43:26.356930 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9850 12:43:26.363342 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9851 12:43:26.366719 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9852 12:43:26.370287 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9853 12:43:26.376506 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9854 12:43:26.380032 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9855 12:43:26.386764 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9856 12:43:26.389784 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9857 12:43:26.393247 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9858 12:43:26.400031 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9859 12:43:26.402914 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9860 12:43:26.409676 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9861 12:43:26.413054 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9862 12:43:26.419884 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9863 12:43:26.423585 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9864 12:43:26.429681 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9865 12:43:26.433145 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9866 12:43:26.439988 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9867 12:43:26.443358 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9868 12:43:26.450042 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9869 12:43:26.453110 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9870 12:43:26.459394 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9871 12:43:26.462751 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9872 12:43:26.469590 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9873 12:43:26.472980 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9874 12:43:26.479348 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9875 12:43:26.482849 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9876 12:43:26.489173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9877 12:43:26.492775 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9878 12:43:26.499349 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9879 12:43:26.502104 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9880 12:43:26.509141 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9881 12:43:26.512655 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9882 12:43:26.518926 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9883 12:43:26.522613 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9884 12:43:26.528980 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9885 12:43:26.532502 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9886 12:43:26.538688 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9887 12:43:26.542336 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9888 12:43:26.548935 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9889 12:43:26.552458 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9890 12:43:26.552540 INFO: [APUAPC] vio 0
9891 12:43:26.560001 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9892 12:43:26.563219 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9893 12:43:26.566536 INFO: [APUAPC] D0_APC_0: 0x400510
9894 12:43:26.569611 INFO: [APUAPC] D0_APC_1: 0x0
9895 12:43:26.572936 INFO: [APUAPC] D0_APC_2: 0x1540
9896 12:43:26.576250 INFO: [APUAPC] D0_APC_3: 0x0
9897 12:43:26.579583 INFO: [APUAPC] D1_APC_0: 0xffffffff
9898 12:43:26.582775 INFO: [APUAPC] D1_APC_1: 0xffffffff
9899 12:43:26.586720 INFO: [APUAPC] D1_APC_2: 0x3fffff
9900 12:43:26.590065 INFO: [APUAPC] D1_APC_3: 0x0
9901 12:43:26.593206 INFO: [APUAPC] D2_APC_0: 0xffffffff
9902 12:43:26.596968 INFO: [APUAPC] D2_APC_1: 0xffffffff
9903 12:43:26.599729 INFO: [APUAPC] D2_APC_2: 0x3fffff
9904 12:43:26.603084 INFO: [APUAPC] D2_APC_3: 0x0
9905 12:43:26.606465 INFO: [APUAPC] D3_APC_0: 0xffffffff
9906 12:43:26.609947 INFO: [APUAPC] D3_APC_1: 0xffffffff
9907 12:43:26.613452 INFO: [APUAPC] D3_APC_2: 0x3fffff
9908 12:43:26.613588 INFO: [APUAPC] D3_APC_3: 0x0
9909 12:43:26.616922 INFO: [APUAPC] D4_APC_0: 0xffffffff
9910 12:43:26.619834 INFO: [APUAPC] D4_APC_1: 0xffffffff
9911 12:43:26.623273 INFO: [APUAPC] D4_APC_2: 0x3fffff
9912 12:43:26.626667 INFO: [APUAPC] D4_APC_3: 0x0
9913 12:43:26.630303 INFO: [APUAPC] D5_APC_0: 0xffffffff
9914 12:43:26.633147 INFO: [APUAPC] D5_APC_1: 0xffffffff
9915 12:43:26.636639 INFO: [APUAPC] D5_APC_2: 0x3fffff
9916 12:43:26.640151 INFO: [APUAPC] D5_APC_3: 0x0
9917 12:43:26.642840 INFO: [APUAPC] D6_APC_0: 0xffffffff
9918 12:43:26.646570 INFO: [APUAPC] D6_APC_1: 0xffffffff
9919 12:43:26.649446 INFO: [APUAPC] D6_APC_2: 0x3fffff
9920 12:43:26.653144 INFO: [APUAPC] D6_APC_3: 0x0
9921 12:43:26.656030 INFO: [APUAPC] D7_APC_0: 0xffffffff
9922 12:43:26.659587 INFO: [APUAPC] D7_APC_1: 0xffffffff
9923 12:43:26.663020 INFO: [APUAPC] D7_APC_2: 0x3fffff
9924 12:43:26.666550 INFO: [APUAPC] D7_APC_3: 0x0
9925 12:43:26.669330 INFO: [APUAPC] D8_APC_0: 0xffffffff
9926 12:43:26.672778 INFO: [APUAPC] D8_APC_1: 0xffffffff
9927 12:43:26.676016 INFO: [APUAPC] D8_APC_2: 0x3fffff
9928 12:43:26.679227 INFO: [APUAPC] D8_APC_3: 0x0
9929 12:43:26.682659 INFO: [APUAPC] D9_APC_0: 0xffffffff
9930 12:43:26.685949 INFO: [APUAPC] D9_APC_1: 0xffffffff
9931 12:43:26.689352 INFO: [APUAPC] D9_APC_2: 0x3fffff
9932 12:43:26.692663 INFO: [APUAPC] D9_APC_3: 0x0
9933 12:43:26.696009 INFO: [APUAPC] D10_APC_0: 0xffffffff
9934 12:43:26.699231 INFO: [APUAPC] D10_APC_1: 0xffffffff
9935 12:43:26.702376 INFO: [APUAPC] D10_APC_2: 0x3fffff
9936 12:43:26.705872 INFO: [APUAPC] D10_APC_3: 0x0
9937 12:43:26.709109 INFO: [APUAPC] D11_APC_0: 0xffffffff
9938 12:43:26.712505 INFO: [APUAPC] D11_APC_1: 0xffffffff
9939 12:43:26.715346 INFO: [APUAPC] D11_APC_2: 0x3fffff
9940 12:43:26.718910 INFO: [APUAPC] D11_APC_3: 0x0
9941 12:43:26.722378 INFO: [APUAPC] D12_APC_0: 0xffffffff
9942 12:43:26.725668 INFO: [APUAPC] D12_APC_1: 0xffffffff
9943 12:43:26.729165 INFO: [APUAPC] D12_APC_2: 0x3fffff
9944 12:43:26.731993 INFO: [APUAPC] D12_APC_3: 0x0
9945 12:43:26.735496 INFO: [APUAPC] D13_APC_0: 0xffffffff
9946 12:43:26.738927 INFO: [APUAPC] D13_APC_1: 0xffffffff
9947 12:43:26.742405 INFO: [APUAPC] D13_APC_2: 0x3fffff
9948 12:43:26.745879 INFO: [APUAPC] D13_APC_3: 0x0
9949 12:43:26.749220 INFO: [APUAPC] D14_APC_0: 0xffffffff
9950 12:43:26.752664 INFO: [APUAPC] D14_APC_1: 0xffffffff
9951 12:43:26.755342 INFO: [APUAPC] D14_APC_2: 0x3fffff
9952 12:43:26.758920 INFO: [APUAPC] D14_APC_3: 0x0
9953 12:43:26.762500 INFO: [APUAPC] D15_APC_0: 0xffffffff
9954 12:43:26.765908 INFO: [APUAPC] D15_APC_1: 0xffffffff
9955 12:43:26.768820 INFO: [APUAPC] D15_APC_2: 0x3fffff
9956 12:43:26.772303 INFO: [APUAPC] D15_APC_3: 0x0
9957 12:43:26.775563 INFO: [APUAPC] APC_CON: 0x4
9958 12:43:26.779162 INFO: [NOCDAPC] D0_APC_0: 0x0
9959 12:43:26.782596 INFO: [NOCDAPC] D0_APC_1: 0x0
9960 12:43:26.786080 INFO: [NOCDAPC] D1_APC_0: 0x0
9961 12:43:26.788987 INFO: [NOCDAPC] D1_APC_1: 0xfff
9962 12:43:26.789317 INFO: [NOCDAPC] D2_APC_0: 0x0
9963 12:43:26.792666 INFO: [NOCDAPC] D2_APC_1: 0xfff
9964 12:43:26.795965 INFO: [NOCDAPC] D3_APC_0: 0x0
9965 12:43:26.799863 INFO: [NOCDAPC] D3_APC_1: 0xfff
9966 12:43:26.802655 INFO: [NOCDAPC] D4_APC_0: 0x0
9967 12:43:26.805692 INFO: [NOCDAPC] D4_APC_1: 0xfff
9968 12:43:26.808984 INFO: [NOCDAPC] D5_APC_0: 0x0
9969 12:43:26.812104 INFO: [NOCDAPC] D5_APC_1: 0xfff
9970 12:43:26.815215 INFO: [NOCDAPC] D6_APC_0: 0x0
9971 12:43:26.818973 INFO: [NOCDAPC] D6_APC_1: 0xfff
9972 12:43:26.822478 INFO: [NOCDAPC] D7_APC_0: 0x0
9973 12:43:26.825245 INFO: [NOCDAPC] D7_APC_1: 0xfff
9974 12:43:26.825850 INFO: [NOCDAPC] D8_APC_0: 0x0
9975 12:43:26.829040 INFO: [NOCDAPC] D8_APC_1: 0xfff
9976 12:43:26.832225 INFO: [NOCDAPC] D9_APC_0: 0x0
9977 12:43:26.835367 INFO: [NOCDAPC] D9_APC_1: 0xfff
9978 12:43:26.838556 INFO: [NOCDAPC] D10_APC_0: 0x0
9979 12:43:26.842007 INFO: [NOCDAPC] D10_APC_1: 0xfff
9980 12:43:26.845674 INFO: [NOCDAPC] D11_APC_0: 0x0
9981 12:43:26.848485 INFO: [NOCDAPC] D11_APC_1: 0xfff
9982 12:43:26.851931 INFO: [NOCDAPC] D12_APC_0: 0x0
9983 12:43:26.855166 INFO: [NOCDAPC] D12_APC_1: 0xfff
9984 12:43:26.858595 INFO: [NOCDAPC] D13_APC_0: 0x0
9985 12:43:26.861416 INFO: [NOCDAPC] D13_APC_1: 0xfff
9986 12:43:26.865089 INFO: [NOCDAPC] D14_APC_0: 0x0
9987 12:43:26.867839 INFO: [NOCDAPC] D14_APC_1: 0xfff
9988 12:43:26.867914 INFO: [NOCDAPC] D15_APC_0: 0x0
9989 12:43:26.871501 INFO: [NOCDAPC] D15_APC_1: 0xfff
9990 12:43:26.874821 INFO: [NOCDAPC] APC_CON: 0x4
9991 12:43:26.878498 INFO: [APUAPC] set_apusys_apc done
9992 12:43:26.881183 INFO: [DEVAPC] devapc_init done
9993 12:43:26.888092 INFO: GICv3 without legacy support detected.
9994 12:43:26.891610 INFO: ARM GICv3 driver initialized in EL3
9995 12:43:26.895394 INFO: Maximum SPI INTID supported: 639
9996 12:43:26.899014 INFO: BL31: Initializing runtime services
9997 12:43:26.904862 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9998 12:43:26.908542 INFO: SPM: enable CPC mode
9999 12:43:26.911827 INFO: mcdi ready for mcusys-off-idle and system suspend
10000 12:43:26.918586 INFO: BL31: Preparing for EL3 exit to normal world
10001 12:43:26.922005 INFO: Entry point address = 0x80000000
10002 12:43:26.922422 INFO: SPSR = 0x8
10003 12:43:26.927896
10004 12:43:26.928502
10005 12:43:26.928969
10006 12:43:26.931594 Starting depthcharge on Spherion...
10007 12:43:26.932220
10008 12:43:26.932650 Wipe memory regions:
10009 12:43:26.932967
10010 12:43:26.935915 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10011 12:43:26.936664 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10012 12:43:26.937116 Setting prompt string to ['asurada:']
10013 12:43:26.937559 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10014 12:43:26.938403 [0x00000040000000, 0x00000054600000)
10015 12:43:27.056885
10016 12:43:27.057029 [0x00000054660000, 0x00000080000000)
10017 12:43:27.317695
10018 12:43:27.317867 [0x000000821a7280, 0x000000ffe64000)
10019 12:43:28.062583
10020 12:43:28.063138 [0x00000100000000, 0x00000240000000)
10021 12:43:29.952684
10022 12:43:29.955368 Initializing XHCI USB controller at 0x11200000.
10023 12:43:30.994198
10024 12:43:30.997113 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10025 12:43:30.997576
10026 12:43:30.997941
10027 12:43:30.998279
10028 12:43:30.999069 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10030 12:43:31.100407 asurada: tftpboot 192.168.201.1 12703541/tftp-deploy-ms6je3da/kernel/image.itb 12703541/tftp-deploy-ms6je3da/kernel/cmdline
10031 12:43:31.100993 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10032 12:43:31.101378 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10033 12:43:31.106688 tftpboot 192.168.201.1 12703541/tftp-deploy-ms6je3da/kernel/image.ittp-deploy-ms6je3da/kernel/cmdline
10034 12:43:31.107122
10035 12:43:31.107453 Waiting for link
10036 12:43:31.267592
10037 12:43:31.268219 R8152: Initializing
10038 12:43:31.268687
10039 12:43:31.270751 Version 9 (ocp_data = 6010)
10040 12:43:31.271299
10041 12:43:31.273726 R8152: Done initializing
10042 12:43:31.274180
10043 12:43:31.274577 Adding net device
10044 12:43:33.142275
10045 12:43:33.142876 done.
10046 12:43:33.143367
10047 12:43:33.143794 MAC: 00:e0:4c:78:7a:aa
10048 12:43:33.144342
10049 12:43:33.145442 Sending DHCP discover... done.
10050 12:43:33.145867
10051 12:43:33.148943 Waiting for reply... done.
10052 12:43:33.149455
10053 12:43:33.151869 Sending DHCP request... done.
10054 12:43:33.152337
10055 12:43:33.155425 Waiting for reply... done.
10056 12:43:33.155901
10057 12:43:33.156275 My ip is 192.168.201.12
10058 12:43:33.156693
10059 12:43:33.158918 The DHCP server ip is 192.168.201.1
10060 12:43:33.159346
10061 12:43:33.165856 TFTP server IP predefined by user: 192.168.201.1
10062 12:43:33.166331
10063 12:43:33.172173 Bootfile predefined by user: 12703541/tftp-deploy-ms6je3da/kernel/image.itb
10064 12:43:33.172742
10065 12:43:33.173138 Sending tftp read request... done.
10066 12:43:33.175427
10067 12:43:33.181527 Waiting for the transfer...
10068 12:43:33.181998
10069 12:43:33.524918 00000000 ################################################################
10070 12:43:33.525067
10071 12:43:33.821735 00080000 ################################################################
10072 12:43:33.821907
10073 12:43:34.118782 00100000 ################################################################
10074 12:43:34.118924
10075 12:43:34.483018 00180000 ################################################################
10076 12:43:34.483527
10077 12:43:34.890220 00200000 ################################################################
10078 12:43:34.890363
10079 12:43:35.181551 00280000 ################################################################
10080 12:43:35.181694
10081 12:43:35.477116 00300000 ################################################################
10082 12:43:35.477257
10083 12:43:35.744007 00380000 ################################################################
10084 12:43:35.744165
10085 12:43:36.004201 00400000 ################################################################
10086 12:43:36.004354
10087 12:43:36.281875 00480000 ################################################################
10088 12:43:36.282008
10089 12:43:36.555074 00500000 ################################################################
10090 12:43:36.555202
10091 12:43:36.827092 00580000 ################################################################
10092 12:43:36.827235
10093 12:43:37.104187 00600000 ################################################################
10094 12:43:37.104358
10095 12:43:37.371663 00680000 ################################################################
10096 12:43:37.371827
10097 12:43:37.657717 00700000 ################################################################
10098 12:43:37.657879
10099 12:43:37.928908 00780000 ################################################################
10100 12:43:37.929093
10101 12:43:38.220111 00800000 ################################################################
10102 12:43:38.220277
10103 12:43:38.503808 00880000 ################################################################
10104 12:43:38.503953
10105 12:43:38.912720 00900000 ################################################################
10106 12:43:38.913245
10107 12:43:39.331029 00980000 ################################################################
10108 12:43:39.331517
10109 12:43:39.666377 00a00000 ################################################################
10110 12:43:39.666508
10111 12:43:39.957146 00a80000 ################################################################
10112 12:43:39.957314
10113 12:43:40.221263 00b00000 ################################################################
10114 12:43:40.221430
10115 12:43:40.491377 00b80000 ################################################################
10116 12:43:40.491519
10117 12:43:40.761365 00c00000 ################################################################
10118 12:43:40.761529
10119 12:43:41.045808 00c80000 ################################################################
10120 12:43:41.045956
10121 12:43:41.332113 00d00000 ################################################################
10122 12:43:41.332277
10123 12:43:41.603085 00d80000 ################################################################
10124 12:43:41.603248
10125 12:43:41.869321 00e00000 ################################################################
10126 12:43:41.869467
10127 12:43:42.203969 00e80000 ################################################################
10128 12:43:42.204112
10129 12:43:42.506946 00f00000 ################################################################
10130 12:43:42.507089
10131 12:43:42.796637 00f80000 ################################################################
10132 12:43:42.796785
10133 12:43:43.081625 01000000 ################################################################
10134 12:43:43.081778
10135 12:43:43.380652 01080000 ################################################################
10136 12:43:43.380809
10137 12:43:43.664449 01100000 ################################################################
10138 12:43:43.664616
10139 12:43:43.946363 01180000 ################################################################
10140 12:43:43.946502
10141 12:43:44.226159 01200000 ################################################################
10142 12:43:44.226322
10143 12:43:44.498576 01280000 ################################################################
10144 12:43:44.498711
10145 12:43:44.754541 01300000 ################################################################
10146 12:43:44.754679
10147 12:43:45.029201 01380000 ################################################################
10148 12:43:45.029333
10149 12:43:45.306795 01400000 ################################################################
10150 12:43:45.306928
10151 12:43:45.590463 01480000 ################################################################
10152 12:43:45.590597
10153 12:43:45.866835 01500000 ################################################################
10154 12:43:45.866964
10155 12:43:46.137956 01580000 ################################################################
10156 12:43:46.138093
10157 12:43:46.397096 01600000 ################################################################
10158 12:43:46.397230
10159 12:43:46.689461 01680000 ################################################################
10160 12:43:46.689634
10161 12:43:46.973948 01700000 ################################################################
10162 12:43:46.974115
10163 12:43:47.240060 01780000 ################################################################
10164 12:43:47.240192
10165 12:43:47.577296 01800000 ################################################################
10166 12:43:47.577486
10167 12:43:47.836936 01880000 ################################################################
10168 12:43:47.837126
10169 12:43:48.103605 01900000 ################################################################
10170 12:43:48.103827
10171 12:43:48.382055 01980000 ################################################################
10172 12:43:48.382203
10173 12:43:48.675082 01a00000 ################################################################
10174 12:43:48.675225
10175 12:43:48.959342 01a80000 ################################################################
10176 12:43:48.959487
10177 12:43:49.252006 01b00000 ################################################################
10178 12:43:49.252153
10179 12:43:49.535506 01b80000 ################################################################
10180 12:43:49.535639
10181 12:43:49.834401 01c00000 ################################################################
10182 12:43:49.834535
10183 12:43:50.116546 01c80000 ################################################################
10184 12:43:50.116708
10185 12:43:50.396525 01d00000 ################################################################
10186 12:43:50.396695
10187 12:43:50.669903 01d80000 ################################################################
10188 12:43:50.670049
10189 12:43:50.952315 01e00000 ################################################################
10190 12:43:50.952462
10191 12:43:51.219825 01e80000 ################################################################
10192 12:43:51.219949
10193 12:43:51.493967 01f00000 ################################################################
10194 12:43:51.494093
10195 12:43:51.762570 01f80000 ################################################################
10196 12:43:51.762704
10197 12:43:52.044229 02000000 ################################################################
10198 12:43:52.044414
10199 12:43:52.436272 02080000 ################################################################
10200 12:43:52.436810
10201 12:43:52.827918 02100000 ################################################################
10202 12:43:52.828454
10203 12:43:53.207976 02180000 ################################################################
10204 12:43:53.208526
10205 12:43:53.544967 02200000 ################################################################
10206 12:43:53.545111
10207 12:43:53.846812 02280000 ################################################################
10208 12:43:53.846955
10209 12:43:54.146171 02300000 ################################################################
10210 12:43:54.146312
10211 12:43:54.439090 02380000 ################################################################
10212 12:43:54.439232
10213 12:43:54.735544 02400000 ################################################################
10214 12:43:54.735712
10215 12:43:55.032160 02480000 ################################################################
10216 12:43:55.032325
10217 12:43:55.312886 02500000 ################################################################
10218 12:43:55.313064
10219 12:43:55.587658 02580000 ################################################################
10220 12:43:55.587827
10221 12:43:55.857883 02600000 ################################################################
10222 12:43:55.858018
10223 12:43:56.139536 02680000 ################################################################
10224 12:43:56.139680
10225 12:43:56.421981 02700000 ################################################################
10226 12:43:56.422129
10227 12:43:56.709905 02780000 ################################################################
10228 12:43:56.710047
10229 12:43:57.011519 02800000 ################################################################
10230 12:43:57.011665
10231 12:43:57.309813 02880000 ################################################################
10232 12:43:57.309956
10233 12:43:57.603306 02900000 ################################################################
10234 12:43:57.603453
10235 12:43:57.901556 02980000 ################################################################
10236 12:43:57.901692
10237 12:43:58.201932 02a00000 ################################################################
10238 12:43:58.202075
10239 12:43:58.521153 02a80000 ################################################################
10240 12:43:58.521300
10241 12:43:58.814509 02b00000 ################################################################
10242 12:43:58.814650
10243 12:43:59.101643 02b80000 ################################################################
10244 12:43:59.101771
10245 12:43:59.369325 02c00000 ################################################################
10246 12:43:59.369458
10247 12:43:59.636411 02c80000 ################################################################
10248 12:43:59.636567
10249 12:43:59.907631 02d00000 ################################################################
10250 12:43:59.907770
10251 12:44:00.162684 02d80000 ################################################################
10252 12:44:00.162851
10253 12:44:00.430902 02e00000 ################################################################
10254 12:44:00.431036
10255 12:44:00.712807 02e80000 ################################################################
10256 12:44:00.712940
10257 12:44:00.986603 02f00000 ################################################################
10258 12:44:00.986736
10259 12:44:01.265251 02f80000 ################################################################
10260 12:44:01.265382
10261 12:44:01.525726 03000000 ################################################################
10262 12:44:01.525860
10263 12:44:01.777913 03080000 ################################################################
10264 12:44:01.778039
10265 12:44:02.050761 03100000 ################################################################
10266 12:44:02.050894
10267 12:44:02.362060 03180000 ################################################################
10268 12:44:02.362816
10269 12:44:02.742799 03200000 ################################################################
10270 12:44:02.743314
10271 12:44:03.101104 03280000 ################################################################
10272 12:44:03.101605
10273 12:44:03.498693 03300000 ################################################################
10274 12:44:03.499374
10275 12:44:03.874834 03380000 ################################################################
10276 12:44:03.875418
10277 12:44:04.247187 03400000 ################################################################
10278 12:44:04.247333
10279 12:44:04.535276 03480000 ################################################################
10280 12:44:04.535419
10281 12:44:04.804837 03500000 ################################################################
10282 12:44:04.804979
10283 12:44:05.054992 03580000 ################################################################
10284 12:44:05.055153
10285 12:44:05.304920 03600000 ################################################################
10286 12:44:05.305055
10287 12:44:05.555753 03680000 ################################################################
10288 12:44:05.555891
10289 12:44:05.826608 03700000 ################################################################
10290 12:44:05.826745
10291 12:44:06.087640 03780000 ################################################################
10292 12:44:06.087779
10293 12:44:06.379454 03800000 ################################################################
10294 12:44:06.379594
10295 12:44:06.662802 03880000 ################################################################
10296 12:44:06.662941
10297 12:44:06.956764 03900000 ################################################################
10298 12:44:06.956906
10299 12:44:07.254047 03980000 ################################################################
10300 12:44:07.254188
10301 12:44:07.539955 03a00000 ################################################################
10302 12:44:07.540102
10303 12:44:07.823478 03a80000 ################################################################
10304 12:44:07.823614
10305 12:44:08.184373 03b00000 ################################################################
10306 12:44:08.184872
10307 12:44:08.546373 03b80000 ################################################################
10308 12:44:08.546516
10309 12:44:08.824475 03c00000 ################################################################
10310 12:44:08.824607
10311 12:44:09.103269 03c80000 ################################################################
10312 12:44:09.103402
10313 12:44:09.398482 03d00000 ################################################################
10314 12:44:09.398621
10315 12:44:09.689932 03d80000 ################################################################
10316 12:44:09.690069
10317 12:44:09.966192 03e00000 ################################################################
10318 12:44:09.966333
10319 12:44:10.329750 03e80000 ################################################################
10320 12:44:10.330261
10321 12:44:10.631311 03f00000 ################################################################
10322 12:44:10.631484
10323 12:44:10.885752 03f80000 ################################################################
10324 12:44:10.885907
10325 12:44:11.176207 04000000 ################################################################
10326 12:44:11.176409
10327 12:44:11.456711 04080000 ################################################################
10328 12:44:11.456865
10329 12:44:11.659329 04100000 ################################################ done.
10330 12:44:11.659483
10331 12:44:11.662765 The bootfile was 68545682 bytes long.
10332 12:44:11.662852
10333 12:44:11.666029 Sending tftp read request... done.
10334 12:44:11.666115
10335 12:44:11.669133 Waiting for the transfer...
10336 12:44:11.669221
10337 12:44:11.669307 00000000 # done.
10338 12:44:11.669389
10339 12:44:11.679227 Command line loaded dynamically from TFTP file: 12703541/tftp-deploy-ms6je3da/kernel/cmdline
10340 12:44:11.679313
10341 12:44:11.692585 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10342 12:44:11.692673
10343 12:44:11.692760 Loading FIT.
10344 12:44:11.692841
10345 12:44:11.695571 Image ramdisk-1 has 56443512 bytes.
10346 12:44:11.695656
10347 12:44:11.699149 Image fdt-1 has 47278 bytes.
10348 12:44:11.699234
10349 12:44:11.702603 Image kernel-1 has 12052857 bytes.
10350 12:44:11.702691
10351 12:44:11.712394 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10352 12:44:11.712481
10353 12:44:11.729142 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10354 12:44:11.729239
10355 12:44:11.732446 Choosing best match conf-1 for compat google,spherion-rev2.
10356 12:44:11.738054
10357 12:44:11.743339 Connected to device vid:did:rid of 1ae0:0028:00
10358 12:44:11.750996
10359 12:44:11.754651 tpm_get_response: command 0x17b, return code 0x0
10360 12:44:11.754736
10361 12:44:11.757586 ec_init: CrosEC protocol v3 supported (256, 248)
10362 12:44:11.761825
10363 12:44:11.765284 tpm_cleanup: add release locality here.
10364 12:44:11.765369
10365 12:44:11.765455 Shutting down all USB controllers.
10366 12:44:11.765537
10367 12:44:11.768734 Removing current net device
10368 12:44:11.768819
10369 12:44:11.775196 Exiting depthcharge with code 4 at timestamp: 74125332
10370 12:44:11.775281
10371 12:44:11.779090 LZMA decompressing kernel-1 to 0x821a6718
10372 12:44:11.779176
10373 12:44:11.782282 LZMA decompressing kernel-1 to 0x40000000
10374 12:44:13.281190
10375 12:44:13.281340 jumping to kernel
10376 12:44:13.281891 end: 2.2.4 bootloader-commands (duration 00:00:46) [common]
10377 12:44:13.282003 start: 2.2.5 auto-login-action (timeout 00:03:39) [common]
10378 12:44:13.282089 Setting prompt string to ['Linux version [0-9]']
10379 12:44:13.282174 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10380 12:44:13.282257 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10381 12:44:13.363414
10382 12:44:13.366859 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10383 12:44:13.370211 start: 2.2.5.1 login-action (timeout 00:03:39) [common]
10384 12:44:13.370309 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10385 12:44:13.370395 Setting prompt string to []
10386 12:44:13.370496 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10387 12:44:13.370586 Using line separator: #'\n'#
10388 12:44:13.370661 No login prompt set.
10389 12:44:13.370746 Parsing kernel messages
10390 12:44:13.370840 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10391 12:44:13.371022 [login-action] Waiting for messages, (timeout 00:03:39)
10392 12:44:13.371127 Waiting using forced prompt support (timeout 00:01:49)
10393 12:44:13.390117 [ 0.000000] Linux version 6.1.75-cip14 (KernelCI@build-j98433-arm64-gcc-10-defconfig-arm64-chromebook-89n64) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Feb 5 12:20:06 UTC 2024
10394 12:44:13.393235 [ 0.000000] random: crng init done
10395 12:44:13.396966 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10396 12:44:13.400083 [ 0.000000] efi: UEFI not found.
10397 12:44:13.410226 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10398 12:44:13.416711 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10399 12:44:13.426283 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10400 12:44:13.436794 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10401 12:44:13.443379 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10402 12:44:13.446739 [ 0.000000] printk: bootconsole [mtk8250] enabled
10403 12:44:13.455422 [ 0.000000] NUMA: No NUMA configuration found
10404 12:44:13.461865 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10405 12:44:13.468978 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10406 12:44:13.469078 [ 0.000000] Zone ranges:
10407 12:44:13.475064 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10408 12:44:13.478672 [ 0.000000] DMA32 empty
10409 12:44:13.485060 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10410 12:44:13.488229 [ 0.000000] Movable zone start for each node
10411 12:44:13.491477 [ 0.000000] Early memory node ranges
10412 12:44:13.498401 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10413 12:44:13.504903 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10414 12:44:13.511468 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10415 12:44:13.518438 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10416 12:44:13.524894 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10417 12:44:13.531275 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10418 12:44:13.588238 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10419 12:44:13.594786 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10420 12:44:13.601052 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10421 12:44:13.604818 [ 0.000000] psci: probing for conduit method from DT.
10422 12:44:13.611313 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10423 12:44:13.614668 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10424 12:44:13.621269 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10425 12:44:13.624526 [ 0.000000] psci: SMC Calling Convention v1.2
10426 12:44:13.631398 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10427 12:44:13.634689 [ 0.000000] Detected VIPT I-cache on CPU0
10428 12:44:13.641056 [ 0.000000] CPU features: detected: GIC system register CPU interface
10429 12:44:13.647537 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10430 12:44:13.654681 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10431 12:44:13.661053 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10432 12:44:13.667499 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10433 12:44:13.674567 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10434 12:44:13.681164 [ 0.000000] alternatives: applying boot alternatives
10435 12:44:13.684162 [ 0.000000] Fallback order for Node 0: 0
10436 12:44:13.691007 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10437 12:44:13.694238 [ 0.000000] Policy zone: Normal
10438 12:44:13.711052 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10439 12:44:13.720711 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10440 12:44:13.731780 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10441 12:44:13.741827 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10442 12:44:13.748365 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10443 12:44:13.751628 <6>[ 0.000000] software IO TLB: area num 8.
10444 12:44:13.808084 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10445 12:44:13.957382 <6>[ 0.000000] Memory: 7912132K/8385536K available (17984K kernel code, 4118K rwdata, 19612K rodata, 8448K init, 616K bss, 440636K reserved, 32768K cma-reserved)
10446 12:44:13.963866 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10447 12:44:13.970531 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10448 12:44:13.973960 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10449 12:44:13.980745 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10450 12:44:13.987431 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10451 12:44:13.990850 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10452 12:44:14.000764 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10453 12:44:14.007169 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10454 12:44:14.010553 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10455 12:44:14.018784 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10456 12:44:14.022033 <6>[ 0.000000] GICv3: 608 SPIs implemented
10457 12:44:14.028522 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10458 12:44:14.032132 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10459 12:44:14.035538 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10460 12:44:14.045523 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10461 12:44:14.054973 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10462 12:44:14.068508 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10463 12:44:14.074560 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10464 12:44:14.083966 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10465 12:44:14.097701 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10466 12:44:14.104015 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10467 12:44:14.110793 <6>[ 0.009185] Console: colour dummy device 80x25
10468 12:44:14.120554 <6>[ 0.013904] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10469 12:44:14.127331 <6>[ 0.024411] pid_max: default: 32768 minimum: 301
10470 12:44:14.130606 <6>[ 0.029281] LSM: Security Framework initializing
10471 12:44:14.137061 <6>[ 0.034251] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10472 12:44:14.147205 <6>[ 0.042065] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10473 12:44:14.154106 <6>[ 0.051540] cblist_init_generic: Setting adjustable number of callback queues.
10474 12:44:14.160453 <6>[ 0.058986] cblist_init_generic: Setting shift to 3 and lim to 1.
10475 12:44:14.170759 <6>[ 0.065325] cblist_init_generic: Setting adjustable number of callback queues.
10476 12:44:14.177246 <6>[ 0.072798] cblist_init_generic: Setting shift to 3 and lim to 1.
10477 12:44:14.180409 <6>[ 0.079199] rcu: Hierarchical SRCU implementation.
10478 12:44:14.186824 <6>[ 0.084214] rcu: Max phase no-delay instances is 1000.
10479 12:44:14.193337 <6>[ 0.091240] EFI services will not be available.
10480 12:44:14.196573 <6>[ 0.096195] smp: Bringing up secondary CPUs ...
10481 12:44:14.204922 <6>[ 0.101244] Detected VIPT I-cache on CPU1
10482 12:44:14.211773 <6>[ 0.101315] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10483 12:44:14.218569 <6>[ 0.101347] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10484 12:44:14.221716 <6>[ 0.101691] Detected VIPT I-cache on CPU2
10485 12:44:14.228692 <6>[ 0.101743] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10486 12:44:14.238048 <6>[ 0.101762] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10487 12:44:14.241389 <6>[ 0.102023] Detected VIPT I-cache on CPU3
10488 12:44:14.248167 <6>[ 0.102069] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10489 12:44:14.254784 <6>[ 0.102084] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10490 12:44:14.258317 <6>[ 0.102389] CPU features: detected: Spectre-v4
10491 12:44:14.264666 <6>[ 0.102395] CPU features: detected: Spectre-BHB
10492 12:44:14.267854 <6>[ 0.102400] Detected PIPT I-cache on CPU4
10493 12:44:14.274619 <6>[ 0.102455] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10494 12:44:14.281109 <6>[ 0.102473] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10495 12:44:14.288146 <6>[ 0.102763] Detected PIPT I-cache on CPU5
10496 12:44:14.294612 <6>[ 0.102826] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10497 12:44:14.301036 <6>[ 0.102842] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10498 12:44:14.304867 <6>[ 0.103125] Detected PIPT I-cache on CPU6
10499 12:44:14.311457 <6>[ 0.103188] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10500 12:44:14.317839 <6>[ 0.103204] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10501 12:44:14.324435 <6>[ 0.103502] Detected PIPT I-cache on CPU7
10502 12:44:14.331259 <6>[ 0.103567] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10503 12:44:14.337716 <6>[ 0.103583] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10504 12:44:14.340894 <6>[ 0.103630] smp: Brought up 1 node, 8 CPUs
10505 12:44:14.347885 <6>[ 0.245161] SMP: Total of 8 processors activated.
10506 12:44:14.351123 <6>[ 0.250083] CPU features: detected: 32-bit EL0 Support
10507 12:44:14.360797 <6>[ 0.255478] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10508 12:44:14.367670 <6>[ 0.264277] CPU features: detected: Common not Private translations
10509 12:44:14.374384 <6>[ 0.270753] CPU features: detected: CRC32 instructions
10510 12:44:14.377641 <6>[ 0.276104] CPU features: detected: RCpc load-acquire (LDAPR)
10511 12:44:14.383855 <6>[ 0.282064] CPU features: detected: LSE atomic instructions
10512 12:44:14.390928 <6>[ 0.287846] CPU features: detected: Privileged Access Never
10513 12:44:14.394200 <6>[ 0.293626] CPU features: detected: RAS Extension Support
10514 12:44:14.403926 <6>[ 0.299234] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10515 12:44:14.407210 <6>[ 0.306499] CPU: All CPU(s) started at EL2
10516 12:44:14.414003 <6>[ 0.310815] alternatives: applying system-wide alternatives
10517 12:44:14.422896 <6>[ 0.321545] devtmpfs: initialized
10518 12:44:14.438786 <6>[ 0.330464] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10519 12:44:14.445309 <6>[ 0.340423] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10520 12:44:14.451792 <6>[ 0.348443] pinctrl core: initialized pinctrl subsystem
10521 12:44:14.455002 <6>[ 0.355081] DMI not present or invalid.
10522 12:44:14.461615 <6>[ 0.359493] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10523 12:44:14.471707 <6>[ 0.366250] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10524 12:44:14.478069 <6>[ 0.373836] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10525 12:44:14.488310 <6>[ 0.382046] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10526 12:44:14.491746 <6>[ 0.390290] audit: initializing netlink subsys (disabled)
10527 12:44:14.501635 <5>[ 0.395983] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10528 12:44:14.507860 <6>[ 0.396690] thermal_sys: Registered thermal governor 'step_wise'
10529 12:44:14.514982 <6>[ 0.403951] thermal_sys: Registered thermal governor 'power_allocator'
10530 12:44:14.518007 <6>[ 0.410208] cpuidle: using governor menu
10531 12:44:14.521184 <6>[ 0.421167] NET: Registered PF_QIPCRTR protocol family
10532 12:44:14.531134 <6>[ 0.426642] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10533 12:44:14.534393 <6>[ 0.433746] ASID allocator initialised with 32768 entries
10534 12:44:14.541926 <6>[ 0.440308] Serial: AMBA PL011 UART driver
10535 12:44:14.550512 <4>[ 0.449086] Trying to register duplicate clock ID: 134
10536 12:44:14.604915 <6>[ 0.506563] KASLR enabled
10537 12:44:14.618875 <6>[ 0.514270] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10538 12:44:14.625751 <6>[ 0.521282] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10539 12:44:14.632264 <6>[ 0.527772] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10540 12:44:14.638823 <6>[ 0.534778] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10541 12:44:14.645589 <6>[ 0.541265] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10542 12:44:14.652019 <6>[ 0.548268] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10543 12:44:14.658850 <6>[ 0.554758] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10544 12:44:14.665502 <6>[ 0.561764] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10545 12:44:14.668738 <6>[ 0.569287] ACPI: Interpreter disabled.
10546 12:44:14.676986 <6>[ 0.575709] iommu: Default domain type: Translated
10547 12:44:14.683596 <6>[ 0.580821] iommu: DMA domain TLB invalidation policy: strict mode
10548 12:44:14.687140 <5>[ 0.587482] SCSI subsystem initialized
10549 12:44:14.693596 <6>[ 0.591648] usbcore: registered new interface driver usbfs
10550 12:44:14.700586 <6>[ 0.597382] usbcore: registered new interface driver hub
10551 12:44:14.703529 <6>[ 0.602933] usbcore: registered new device driver usb
10552 12:44:14.710673 <6>[ 0.609035] pps_core: LinuxPPS API ver. 1 registered
10553 12:44:14.720442 <6>[ 0.614231] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10554 12:44:14.723532 <6>[ 0.623580] PTP clock support registered
10555 12:44:14.727060 <6>[ 0.627822] EDAC MC: Ver: 3.0.0
10556 12:44:14.734324 <6>[ 0.632979] FPGA manager framework
10557 12:44:14.741254 <6>[ 0.636657] Advanced Linux Sound Architecture Driver Initialized.
10558 12:44:14.744510 <6>[ 0.643428] vgaarb: loaded
10559 12:44:14.750910 <6>[ 0.646576] clocksource: Switched to clocksource arch_sys_counter
10560 12:44:14.754651 <5>[ 0.653015] VFS: Disk quotas dquot_6.6.0
10561 12:44:14.761305 <6>[ 0.657202] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10562 12:44:14.764200 <6>[ 0.664395] pnp: PnP ACPI: disabled
10563 12:44:14.772574 <6>[ 0.671041] NET: Registered PF_INET protocol family
10564 12:44:14.782260 <6>[ 0.676629] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10565 12:44:14.793661 <6>[ 0.688942] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10566 12:44:14.803317 <6>[ 0.697757] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10567 12:44:14.810143 <6>[ 0.705730] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10568 12:44:14.820324 <6>[ 0.714430] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10569 12:44:14.826995 <6>[ 0.724176] TCP: Hash tables configured (established 65536 bind 65536)
10570 12:44:14.833666 <6>[ 0.731039] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10571 12:44:14.843378 <6>[ 0.738239] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10572 12:44:14.846507 <6>[ 0.745938] NET: Registered PF_UNIX/PF_LOCAL protocol family
10573 12:44:14.853582 <6>[ 0.752112] RPC: Registered named UNIX socket transport module.
10574 12:44:14.860495 <6>[ 0.758265] RPC: Registered udp transport module.
10575 12:44:14.863603 <6>[ 0.763198] RPC: Registered tcp transport module.
10576 12:44:14.870054 <6>[ 0.768130] RPC: Registered tcp NFSv4.1 backchannel transport module.
10577 12:44:14.876874 <6>[ 0.774800] PCI: CLS 0 bytes, default 64
10578 12:44:14.880390 <6>[ 0.779200] Unpacking initramfs...
10579 12:44:14.903460 <6>[ 0.798689] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10580 12:44:14.913665 <6>[ 0.807356] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10581 12:44:14.916559 <6>[ 0.816214] kvm [1]: IPA Size Limit: 40 bits
10582 12:44:14.923628 <6>[ 0.820743] kvm [1]: GICv3: no GICV resource entry
10583 12:44:14.926972 <6>[ 0.825766] kvm [1]: disabling GICv2 emulation
10584 12:44:14.933397 <6>[ 0.830453] kvm [1]: GIC system register CPU interface enabled
10585 12:44:14.936538 <6>[ 0.836615] kvm [1]: vgic interrupt IRQ18
10586 12:44:14.943347 <6>[ 0.840970] kvm [1]: VHE mode initialized successfully
10587 12:44:14.949939 <5>[ 0.847445] Initialise system trusted keyrings
10588 12:44:14.956364 <6>[ 0.852282] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10589 12:44:14.963494 <6>[ 0.862252] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10590 12:44:14.970381 <5>[ 0.868606] NFS: Registering the id_resolver key type
10591 12:44:14.974055 <5>[ 0.873909] Key type id_resolver registered
10592 12:44:14.980691 <5>[ 0.878325] Key type id_legacy registered
10593 12:44:14.987320 <6>[ 0.882614] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10594 12:44:14.994061 <6>[ 0.889537] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10595 12:44:15.000057 <6>[ 0.897250] 9p: Installing v9fs 9p2000 file system support
10596 12:44:15.036620 <5>[ 0.935101] Key type asymmetric registered
10597 12:44:15.039860 <5>[ 0.939431] Asymmetric key parser 'x509' registered
10598 12:44:15.049690 <6>[ 0.944609] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10599 12:44:15.052989 <6>[ 0.952228] io scheduler mq-deadline registered
10600 12:44:15.056097 <6>[ 0.957002] io scheduler kyber registered
10601 12:44:15.075229 <6>[ 0.973910] EINJ: ACPI disabled.
10602 12:44:15.107452 <4>[ 0.999333] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10603 12:44:15.117562 <4>[ 1.009964] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10604 12:44:15.132009 <6>[ 1.030645] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10605 12:44:15.139929 <6>[ 1.038691] printk: console [ttyS0] disabled
10606 12:44:15.167816 <6>[ 1.063318] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10607 12:44:15.175079 <6>[ 1.072799] printk: console [ttyS0] enabled
10608 12:44:15.178317 <6>[ 1.072799] printk: console [ttyS0] enabled
10609 12:44:15.184434 <6>[ 1.081692] printk: bootconsole [mtk8250] disabled
10610 12:44:15.188105 <6>[ 1.081692] printk: bootconsole [mtk8250] disabled
10611 12:44:15.194543 <6>[ 1.092979] SuperH (H)SCI(F) driver initialized
10612 12:44:15.197831 <6>[ 1.098274] msm_serial: driver initialized
10613 12:44:15.212158 <6>[ 1.107191] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10614 12:44:15.221917 <6>[ 1.115736] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10615 12:44:15.228643 <6>[ 1.124278] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10616 12:44:15.238282 <6>[ 1.132909] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10617 12:44:15.245021 <6>[ 1.141617] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10618 12:44:15.255065 <6>[ 1.150339] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10619 12:44:15.264883 <6>[ 1.158880] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10620 12:44:15.271529 <6>[ 1.167686] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10621 12:44:15.281647 <6>[ 1.176231] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10622 12:44:15.293179 <6>[ 1.191800] loop: module loaded
10623 12:44:15.299538 <6>[ 1.197747] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10624 12:44:15.322154 <4>[ 1.220734] mtk-pmic-keys: Failed to locate of_node [id: -1]
10625 12:44:15.329006 <6>[ 1.227751] megasas: 07.719.03.00-rc1
10626 12:44:15.339145 <6>[ 1.237497] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10627 12:44:15.347193 <6>[ 1.245967] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10628 12:44:15.364251 <6>[ 1.262757] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10629 12:44:15.420746 <6>[ 1.312840] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10630 12:44:17.291243 <6>[ 3.190291] Freeing initrd memory: 55116K
10631 12:44:17.302014 <6>[ 3.200642] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10632 12:44:17.313384 <6>[ 3.211853] tun: Universal TUN/TAP device driver, 1.6
10633 12:44:17.316555 <6>[ 3.217942] thunder_xcv, ver 1.0
10634 12:44:17.319626 <6>[ 3.221449] thunder_bgx, ver 1.0
10635 12:44:17.322718 <6>[ 3.224945] nicpf, ver 1.0
10636 12:44:17.333438 <6>[ 3.228970] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10637 12:44:17.336985 <6>[ 3.236445] hns3: Copyright (c) 2017 Huawei Corporation.
10638 12:44:17.340148 <6>[ 3.242033] hclge is initializing
10639 12:44:17.346998 <6>[ 3.245616] e1000: Intel(R) PRO/1000 Network Driver
10640 12:44:17.353452 <6>[ 3.250746] e1000: Copyright (c) 1999-2006 Intel Corporation.
10641 12:44:17.356704 <6>[ 3.256758] e1000e: Intel(R) PRO/1000 Network Driver
10642 12:44:17.363320 <6>[ 3.261973] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10643 12:44:17.370190 <6>[ 3.268158] igb: Intel(R) Gigabit Ethernet Network Driver
10644 12:44:17.376452 <6>[ 3.273808] igb: Copyright (c) 2007-2014 Intel Corporation.
10645 12:44:17.383218 <6>[ 3.279647] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10646 12:44:17.389887 <6>[ 3.286166] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10647 12:44:17.393217 <6>[ 3.292625] sky2: driver version 1.30
10648 12:44:17.399529 <6>[ 3.297642] VFIO - User Level meta-driver version: 0.3
10649 12:44:17.406833 <6>[ 3.305884] usbcore: registered new interface driver usb-storage
10650 12:44:17.413865 <6>[ 3.312340] usbcore: registered new device driver onboard-usb-hub
10651 12:44:17.422409 <6>[ 3.321503] mt6397-rtc mt6359-rtc: registered as rtc0
10652 12:44:17.432601 <6>[ 3.326968] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-05T12:41:33 UTC (1707136893)
10653 12:44:17.435932 <6>[ 3.336532] i2c_dev: i2c /dev entries driver
10654 12:44:17.452310 <6>[ 3.348278] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10655 12:44:17.472798 <6>[ 3.371276] cpu cpu0: EM: created perf domain
10656 12:44:17.475812 <6>[ 3.376212] cpu cpu4: EM: created perf domain
10657 12:44:17.482868 <6>[ 3.381849] sdhci: Secure Digital Host Controller Interface driver
10658 12:44:17.489855 <6>[ 3.388283] sdhci: Copyright(c) Pierre Ossman
10659 12:44:17.496402 <6>[ 3.393235] Synopsys Designware Multimedia Card Interface Driver
10660 12:44:17.503260 <6>[ 3.399872] sdhci-pltfm: SDHCI platform and OF driver helper
10661 12:44:17.506236 <6>[ 3.399924] mmc0: CQHCI version 5.10
10662 12:44:17.512985 <6>[ 3.409969] ledtrig-cpu: registered to indicate activity on CPUs
10663 12:44:17.519287 <6>[ 3.417131] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10664 12:44:17.526169 <6>[ 3.424190] usbcore: registered new interface driver usbhid
10665 12:44:17.529680 <6>[ 3.430013] usbhid: USB HID core driver
10666 12:44:17.536179 <6>[ 3.434224] spi_master spi0: will run message pump with realtime priority
10667 12:44:17.580948 <6>[ 3.473393] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10668 12:44:17.600217 <6>[ 3.489059] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10669 12:44:17.603568 <6>[ 3.502630] mmc0: Command Queue Engine enabled
10670 12:44:17.609960 <6>[ 3.507433] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10671 12:44:17.616722 <6>[ 3.514766] mmcblk0: mmc0:0001 DA4128 116 GiB
10672 12:44:17.620375 <6>[ 3.519736] cros-ec-spi spi0.0: Chrome EC device registered
10673 12:44:17.626510 <6>[ 3.523486] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10674 12:44:17.634802 <6>[ 3.533408] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10675 12:44:17.641155 <6>[ 3.539472] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10676 12:44:17.648013 <6>[ 3.545696] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10677 12:44:17.665854 <6>[ 3.561470] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10678 12:44:17.673082 <6>[ 3.572178] NET: Registered PF_PACKET protocol family
10679 12:44:17.676954 <6>[ 3.577580] 9pnet: Installing 9P2000 support
10680 12:44:17.683368 <5>[ 3.582143] Key type dns_resolver registered
10681 12:44:17.686476 <6>[ 3.587171] registered taskstats version 1
10682 12:44:17.692827 <5>[ 3.591557] Loading compiled-in X.509 certificates
10683 12:44:17.724911 <4>[ 3.617185] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10684 12:44:17.734757 <4>[ 3.627950] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10685 12:44:17.741475 <3>[ 3.638485] debugfs: File 'uA_load' in directory '/' already present!
10686 12:44:17.748137 <3>[ 3.645185] debugfs: File 'min_uV' in directory '/' already present!
10687 12:44:17.754594 <3>[ 3.651793] debugfs: File 'max_uV' in directory '/' already present!
10688 12:44:17.761019 <3>[ 3.658401] debugfs: File 'constraint_flags' in directory '/' already present!
10689 12:44:17.772221 <3>[ 3.667900] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10690 12:44:17.782245 <6>[ 3.681291] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10691 12:44:17.789292 <6>[ 3.688034] xhci-mtk 11200000.usb: xHCI Host Controller
10692 12:44:17.796026 <6>[ 3.693539] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10693 12:44:17.805734 <6>[ 3.701384] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10694 12:44:17.812267 <6>[ 3.710814] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10695 12:44:17.819105 <6>[ 3.716878] xhci-mtk 11200000.usb: xHCI Host Controller
10696 12:44:17.825684 <6>[ 3.722364] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10697 12:44:17.832553 <6>[ 3.730012] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10698 12:44:17.838924 <6>[ 3.737705] hub 1-0:1.0: USB hub found
10699 12:44:17.841998 <6>[ 3.741728] hub 1-0:1.0: 1 port detected
10700 12:44:17.851902 <6>[ 3.745998] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10701 12:44:17.855300 <6>[ 3.754816] hub 2-0:1.0: USB hub found
10702 12:44:17.858865 <6>[ 3.758843] hub 2-0:1.0: 1 port detected
10703 12:44:17.868096 <6>[ 3.766866] mtk-msdc 11f70000.mmc: Got CD GPIO
10704 12:44:17.878132 <6>[ 3.773399] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10705 12:44:17.884682 <6>[ 3.781423] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10706 12:44:17.894340 <4>[ 3.789321] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10707 12:44:17.904641 <6>[ 3.798848] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10708 12:44:17.911345 <6>[ 3.806926] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10709 12:44:17.917636 <6>[ 3.814965] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10710 12:44:17.927886 <6>[ 3.822882] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10711 12:44:17.934193 <6>[ 3.830700] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10712 12:44:17.944479 <6>[ 3.838519] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10713 12:44:17.954080 <6>[ 3.848815] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10714 12:44:17.961189 <6>[ 3.857177] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10715 12:44:17.970945 <6>[ 3.865523] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10716 12:44:17.977672 <6>[ 3.873869] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10717 12:44:17.987558 <6>[ 3.882208] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10718 12:44:17.993856 <6>[ 3.890547] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10719 12:44:18.004099 <6>[ 3.898886] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10720 12:44:18.010621 <6>[ 3.907225] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10721 12:44:18.020597 <6>[ 3.915577] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10722 12:44:18.027221 <6>[ 3.923916] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10723 12:44:18.037483 <6>[ 3.932256] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10724 12:44:18.043882 <6>[ 3.940595] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10725 12:44:18.053993 <6>[ 3.948934] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10726 12:44:18.060452 <6>[ 3.957274] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10727 12:44:18.070585 <6>[ 3.965614] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10728 12:44:18.076888 <6>[ 3.974383] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10729 12:44:18.083424 <6>[ 3.981614] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10730 12:44:18.090053 <6>[ 3.988482] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10731 12:44:18.096601 <6>[ 3.995345] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10732 12:44:18.107027 <6>[ 4.002338] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10733 12:44:18.113782 <6>[ 4.009201] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10734 12:44:18.123230 <6>[ 4.018332] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10735 12:44:18.133299 <6>[ 4.027452] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10736 12:44:18.143414 <6>[ 4.036746] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10737 12:44:18.153015 <6>[ 4.046213] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10738 12:44:18.159620 <6>[ 4.055681] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10739 12:44:18.169609 <6>[ 4.064800] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10740 12:44:18.179857 <6>[ 4.074266] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10741 12:44:18.189758 <6>[ 4.083384] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10742 12:44:18.199262 <6>[ 4.092678] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10743 12:44:18.209007 <6>[ 4.102838] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10744 12:44:18.219106 <6>[ 4.114502] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10745 12:44:18.267002 <6>[ 4.162848] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10746 12:44:18.422143 <6>[ 4.320878] hub 1-1:1.0: USB hub found
10747 12:44:18.424939 <6>[ 4.325402] hub 1-1:1.0: 4 ports detected
10748 12:44:18.434635 <6>[ 4.333916] hub 1-1:1.0: USB hub found
10749 12:44:18.438173 <6>[ 4.338278] hub 1-1:1.0: 4 ports detected
10750 12:44:18.547110 <6>[ 4.443091] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10751 12:44:18.573606 <6>[ 4.472645] hub 2-1:1.0: USB hub found
10752 12:44:18.576776 <6>[ 4.477137] hub 2-1:1.0: 3 ports detected
10753 12:44:18.586093 <6>[ 4.485173] hub 2-1:1.0: USB hub found
10754 12:44:18.589185 <6>[ 4.489651] hub 2-1:1.0: 3 ports detected
10755 12:44:18.762914 <6>[ 4.658875] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10756 12:44:18.895700 <6>[ 4.794497] hub 1-1.4:1.0: USB hub found
10757 12:44:18.898857 <6>[ 4.799095] hub 1-1.4:1.0: 2 ports detected
10758 12:44:18.907692 <6>[ 4.806555] hub 1-1.4:1.0: USB hub found
10759 12:44:18.910775 <6>[ 4.811187] hub 1-1.4:1.0: 2 ports detected
10760 12:44:18.975188 <6>[ 4.871116] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10761 12:44:19.206999 <6>[ 5.102889] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10762 12:44:19.399240 <6>[ 5.294895] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10763 12:44:30.496265 <6>[ 16.399899] ALSA device list:
10764 12:44:30.502460 <6>[ 16.403188] No soundcards found.
10765 12:44:30.510893 <6>[ 16.411200] Freeing unused kernel memory: 8448K
10766 12:44:30.514091 <6>[ 16.416197] Run /init as init process
10767 12:44:30.560357 <6>[ 16.460414] NET: Registered PF_INET6 protocol family
10768 12:44:30.566664 <6>[ 16.466550] Segment Routing with IPv6
10769 12:44:30.569901 <6>[ 16.470502] In-situ OAM (IOAM) with IPv6
10770 12:44:30.601288 <30>[ 16.485232] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10771 12:44:30.608760 <30>[ 16.509122] systemd[1]: Detected architecture arm64.
10772 12:44:30.608945
10773 12:44:30.615031 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10774 12:44:30.615171
10775 12:44:30.630434 <30>[ 16.530837] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10776 12:44:30.768695 <30>[ 16.665819] systemd[1]: Queued start job for default target Graphical Interface.
10777 12:44:30.803090 <30>[ 16.703631] systemd[1]: Created slice system-getty.slice.
10778 12:44:30.809853 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10779 12:44:30.827373 <30>[ 16.727527] systemd[1]: Created slice system-modprobe.slice.
10780 12:44:30.833800 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10781 12:44:30.851794 <30>[ 16.752266] systemd[1]: Created slice system-serial\x2dgetty.slice.
10782 12:44:30.861790 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10783 12:44:30.875924 <30>[ 16.776179] systemd[1]: Created slice User and Session Slice.
10784 12:44:30.882642 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10785 12:44:30.902599 <30>[ 16.799585] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10786 12:44:30.912490 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10787 12:44:30.930785 <30>[ 16.827636] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10788 12:44:30.937363 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10789 12:44:30.961339 <30>[ 16.854955] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10790 12:44:30.967733 <30>[ 16.867130] systemd[1]: Reached target Local Encrypted Volumes.
10791 12:44:30.974171 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10792 12:44:30.990954 <30>[ 16.891398] systemd[1]: Reached target Paths.
10793 12:44:30.997885 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10794 12:44:31.010726 <30>[ 16.910937] systemd[1]: Reached target Remote File Systems.
10795 12:44:31.017136 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10796 12:44:31.034470 <30>[ 16.934875] systemd[1]: Reached target Slices.
10797 12:44:31.040951 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10798 12:44:31.054383 <30>[ 16.954911] systemd[1]: Reached target Swap.
10799 12:44:31.058089 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10800 12:44:31.078237 <30>[ 16.975402] systemd[1]: Listening on initctl Compatibility Named Pipe.
10801 12:44:31.085013 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10802 12:44:31.091855 <30>[ 16.990651] systemd[1]: Listening on Journal Audit Socket.
10803 12:44:31.097967 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10804 12:44:31.110709 <30>[ 17.011388] systemd[1]: Listening on Journal Socket (/dev/log).
10805 12:44:31.117584 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10806 12:44:31.135975 <30>[ 17.036095] systemd[1]: Listening on Journal Socket.
10807 12:44:31.142554 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10808 12:44:31.154864 <30>[ 17.055491] systemd[1]: Listening on udev Control Socket.
10809 12:44:31.162073 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10810 12:44:31.179528 <30>[ 17.079886] systemd[1]: Listening on udev Kernel Socket.
10811 12:44:31.185966 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10812 12:44:31.239096 <30>[ 17.139216] systemd[1]: Mounting Huge Pages File System...
10813 12:44:31.245654 Mounting [0;1;39mHuge Pages File System[0m...
10814 12:44:31.262214 <30>[ 17.162872] systemd[1]: Mounting POSIX Message Queue File System...
10815 12:44:31.269305 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10816 12:44:31.310801 <30>[ 17.211040] systemd[1]: Mounting Kernel Debug File System...
10817 12:44:31.317117 Mounting [0;1;39mKernel Debug File System[0m...
10818 12:44:31.338156 <30>[ 17.235499] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10819 12:44:31.351395 <30>[ 17.248415] systemd[1]: Starting Create list of static device nodes for the current kernel...
10820 12:44:31.357824 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10821 12:44:31.379017 <30>[ 17.279372] systemd[1]: Starting Load Kernel Module configfs...
10822 12:44:31.385383 Starting [0;1;39mLoad Kernel Module configfs[0m...
10823 12:44:31.426854 <30>[ 17.327280] systemd[1]: Starting Load Kernel Module drm...
10824 12:44:31.433294 Starting [0;1;39mLoad Kernel Module drm[0m...
10825 12:44:31.453843 <30>[ 17.351200] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10826 12:44:31.467887 <30>[ 17.368537] systemd[1]: Starting Journal Service...
10827 12:44:31.471488 Starting [0;1;39mJournal Service[0m...
10828 12:44:31.489163 <30>[ 17.389708] systemd[1]: Starting Load Kernel Modules...
10829 12:44:31.495511 Starting [0;1;39mLoad Kernel Modules[0m...
10830 12:44:31.520769 <30>[ 17.417760] systemd[1]: Starting Remount Root and Kernel File Systems...
10831 12:44:31.526823 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10832 12:44:31.545303 <30>[ 17.445590] systemd[1]: Starting Coldplug All udev Devices...
10833 12:44:31.551867 Starting [0;1;39mColdplug All udev Devices[0m...
10834 12:44:31.575817 <30>[ 17.475863] systemd[1]: Started Journal Service.
10835 12:44:31.582162 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10836 12:44:31.597241 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10837 12:44:31.619226 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10838 12:44:31.636184 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10839 12:44:31.655359 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10840 12:44:31.675591 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10841 12:44:31.697624 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10842 12:44:31.716489 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10843 12:44:31.736225 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10844 12:44:31.750634 See 'systemctl status systemd-remount-fs.service' for details.
10845 12:44:31.792018 Mounting [0;1;39mKernel Configuration File System[0m...
10846 12:44:31.810394 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10847 12:44:31.824253 <46>[ 17.721308] systemd-journald[183]: Received client request to flush runtime journal.
10848 12:44:31.834452 Starting [0;1;39mLoad/Save Random Seed[0m...
10849 12:44:31.853976 Starting [0;1;39mApply Kernel Variables[0m...
10850 12:44:31.875398 Starting [0;1;39mCreate System Users[0m...
10851 12:44:31.895761 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10852 12:44:31.911770 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10853 12:44:31.935798 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10854 12:44:31.948039 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10855 12:44:31.964562 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10856 12:44:31.983889 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10857 12:44:32.035516 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10858 12:44:32.054534 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10859 12:44:32.066963 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10860 12:44:32.082196 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10861 12:44:32.118667 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10862 12:44:32.146645 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10863 12:44:32.177437 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10864 12:44:32.195721 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10865 12:44:32.245105 Starting [0;1;39mNetwork Time Synchronization[0m...
10866 12:44:32.268582 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10867 12:44:32.303016 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10868 12:44:32.339920 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10869 12:44:32.354099 <6>[ 18.251213] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10870 12:44:32.360667 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10871 12:44:32.368153 <6>[ 18.268522] remoteproc remoteproc0: scp is available
10872 12:44:32.374952 <6>[ 18.274068] remoteproc remoteproc0: powering up scp
10873 12:44:32.381508 <6>[ 18.279335] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10874 12:44:32.388036 <6>[ 18.287907] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10875 12:44:32.397773 [[0;32m OK [0m] Created slic<6>[ 18.296598] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10876 12:44:32.407958 e [0;1;39msyste<6>[ 18.304603] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10877 12:44:32.417788 m-systemd\x2dbac<3>[ 18.305638] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10878 12:44:32.427610 klight.slice[0m<6>[ 18.315182] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10879 12:44:32.427787 .
10880 12:44:32.437592 <3>[ 18.330032] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10881 12:44:32.444245 <3>[ 18.342853] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10882 12:44:32.454238 [[0;32m OK [0m] Reached targ<4>[ 18.352754] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10883 12:44:32.464528 et [0;1;39mSyst<4>[ 18.361780] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10884 12:44:32.474129 em Time Set[0m.<3>[ 18.361811] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10885 12:44:32.477929 <6>[ 18.362552] mc: Linux media interface: v0.10
10886 12:44:32.487379 <6>[ 18.363503] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10887 12:44:32.487570
10888 12:44:32.494396 <3>[ 18.391985] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10889 12:44:32.500888 <6>[ 18.394564] videodev: Linux video capture interface: v2.00
10890 12:44:32.507846 <6>[ 18.394766] usbcore: registered new device driver r8152-cfgselector
10891 12:44:32.514328 <3>[ 18.400277] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10892 12:44:32.524185 <4>[ 18.406610] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10893 12:44:32.527846 <4>[ 18.406610] Fallback method does not support PEC.
10894 12:44:32.537866 <3>[ 18.412589] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10895 12:44:32.544409 <6>[ 18.419097] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10896 12:44:32.551239 <6>[ 18.420925] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10897 12:44:32.561064 <3>[ 18.434336] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10898 12:44:32.567714 <3>[ 18.434484] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10899 12:44:32.574104 <6>[ 18.442846] remoteproc remoteproc0: remote processor scp is now up
10900 12:44:32.584139 <3>[ 18.449563] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10901 12:44:32.590841 <6>[ 18.462108] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10902 12:44:32.597538 <3>[ 18.466139] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10903 12:44:32.607047 <3>[ 18.466141] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10904 12:44:32.613929 <3>[ 18.466186] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10905 12:44:32.623740 <6>[ 18.467144] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10906 12:44:32.630644 <6>[ 18.468237] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10907 12:44:32.636989 <6>[ 18.474284] pci_bus 0000:00: root bus resource [bus 00-ff]
10908 12:44:32.643584 <3>[ 18.480680] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10909 12:44:32.653721 <3>[ 18.480684] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10910 12:44:32.660080 <3>[ 18.480687] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10911 12:44:32.670219 <6>[ 18.483170] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10912 12:44:32.676771 <6>[ 18.488781] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10913 12:44:32.686950 <6>[ 18.489456] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10914 12:44:32.694187 <3>[ 18.495629] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10915 12:44:32.701161 <3>[ 18.495651] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10916 12:44:32.710869 <6>[ 18.503740] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10917 12:44:32.721069 <6>[ 18.508067] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10918 12:44:32.730624 <6>[ 18.508271] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10919 12:44:32.740797 <4>[ 18.511089] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10920 12:44:32.747770 <4>[ 18.511106] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10921 12:44:32.751342 <6>[ 18.550849] Bluetooth: Core ver 2.22
10922 12:44:32.758290 <6>[ 18.558510] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10923 12:44:32.761509 <6>[ 18.558711] r8152 2-1.3:1.0 eth0: v1.12.13
10924 12:44:32.768564 <6>[ 18.558812] usbcore: registered new interface driver r8152
10925 12:44:32.775628 <6>[ 18.568061] NET: Registered PF_BLUETOOTH protocol family
10926 12:44:32.782676 <6>[ 18.568641] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10927 12:44:32.792486 <6>[ 18.570454] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10928 12:44:32.799669 <6>[ 18.570649] usbcore: registered new interface driver uvcvideo
10929 12:44:32.807304 <6>[ 18.575063] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10930 12:44:32.813586 <6>[ 18.575875] usbcore: registered new interface driver cdc_ether
10931 12:44:32.820256 <6>[ 18.582161] Bluetooth: HCI device and connection manager initialized
10932 12:44:32.823614 <6>[ 18.591702] pci 0000:00:00.0: supports D1 D2
10933 12:44:32.830548 <6>[ 18.591743] usbcore: registered new interface driver r8153_ecm
10934 12:44:32.834426 <6>[ 18.599508] Bluetooth: HCI socket layer initialized
10935 12:44:32.841348 <6>[ 18.607529] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10936 12:44:32.851035 <3>[ 18.608690] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10937 12:44:32.857723 <6>[ 18.612633] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10938 12:44:32.861984 <6>[ 18.617657] Bluetooth: L2CAP socket layer initialized
10939 12:44:32.868946 <6>[ 18.618148] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10940 12:44:32.875451 <6>[ 18.628432] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10941 12:44:32.881775 <6>[ 18.636561] Bluetooth: SCO socket layer initialized
10942 12:44:32.888909 <6>[ 18.645670] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10943 12:44:32.895832 <3>[ 18.672899] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 12:44:32.905974 <6>[ 18.673852] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10945 12:44:32.912903 <3>[ 18.679607] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10946 12:44:32.919536 <6>[ 18.686437] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10947 12:44:32.926348 <6>[ 18.686890] usbcore: registered new interface driver btusb
10948 12:44:32.936305 <4>[ 18.688079] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10949 12:44:32.942798 <3>[ 18.688087] Bluetooth: hci0: Failed to load firmware file (-2)
10950 12:44:32.949273 <3>[ 18.688090] Bluetooth: hci0: Failed to set up firmware (-2)
10951 12:44:32.959969 <4>[ 18.688093] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10952 12:44:32.966726 <3>[ 18.688316] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10953 12:44:32.977090 <3>[ 18.689150] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10954 12:44:32.987485 <3>[ 18.712209] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10955 12:44:32.993684 <6>[ 18.712323] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10956 12:44:33.000539 <3>[ 18.739806] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10957 12:44:33.007548 <6>[ 18.740823] pci 0000:01:00.0: supports D1 D2
10958 12:44:33.014538 <3>[ 18.770907] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 12:44:33.021599 <6>[ 18.774238] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10960 12:44:33.031834 <3>[ 18.802103] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10961 12:44:33.038257 <6>[ 18.814783] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10962 12:44:33.048643 <3>[ 18.840694] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10963 12:44:33.055362 <6>[ 18.842645] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10964 12:44:33.062087 <6>[ 18.960636] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10965 12:44:33.071443 <6>[ 18.968852] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10966 12:44:33.078238 <6>[ 18.976863] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10967 12:44:33.087826 <6>[ 18.984873] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10968 12:44:33.091703 <6>[ 18.992876] pci 0000:00:00.0: PCI bridge to [bus 01]
10969 12:44:33.101570 <6>[ 18.998092] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10970 12:44:33.108170 [[0;32m OK [<6>[ 19.006312] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10971 12:44:33.114532 0m] Reached targ<6>[ 19.014585] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10972 12:44:33.124599 et [0;1;39mSyst<6>[ 19.021915] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10973 12:44:33.124744 em Time Synchronized[0m.
10974 12:44:33.139941 <5>[ 19.037396] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10975 12:44:33.157563 <5>[ 19.054989] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10976 12:44:33.164085 <5>[ 19.062347] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10977 12:44:33.174106 <4>[ 19.070858] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10978 12:44:33.180726 <6>[ 19.079761] cfg80211: failed to load regulatory.db
10979 12:44:33.187957 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10980 12:44:33.223152 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of l<6>[ 19.121691] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10981 12:44:33.232756 eds:white:kbd_ba<6>[ 19.130320] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10982 12:44:33.232918 cklight[0m.
10983 12:44:33.257615 <6>[ 19.158329] mt7921e 0000:01:00.0: ASIC revision: 79610010
10984 12:44:33.361118 <6>[ 19.258484] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10985 12:44:33.364194 <6>[ 19.258484]
10986 12:44:33.391496 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10987 12:44:33.406201 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10988 12:44:33.425573 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10989 12:44:33.441818 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10990 12:44:33.454128 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10991 12:44:33.473886 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10992 12:44:33.486022 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10993 12:44:33.506096 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10994 12:44:33.526245 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10995 12:44:33.571290 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10996 12:44:33.608982 Starting [0;1;39mUser Login Management[0m...
10997 12:44:33.633743 Startin<6>[ 19.528704] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10998 12:44:33.637245 g [0;1;39mPermit User Sessions[0m...
10999 12:44:33.652996 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11000 12:44:33.669279 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11001 12:44:33.685177 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11002 12:44:33.702846 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11003 12:44:33.743207 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11004 12:44:33.760002 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11005 12:44:33.776611 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11006 12:44:33.796672 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11007 12:44:33.810242 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11008 12:44:33.854838 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11009 12:44:33.887585 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11010 12:44:33.905291
11011 12:44:33.905443
11012 12:44:33.908429 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11013 12:44:33.908520
11014 12:44:33.911583 debian-bullseye-arm64 login: root (automatic login)
11015 12:44:33.911675
11016 12:44:33.911741
11017 12:44:33.931156 Linux debian-bullseye-arm64 6.1.75-cip14 #1 SMP PREEMPT Mon Feb 5 12:20:06 UTC 2024 aarch64
11018 12:44:33.931305
11019 12:44:33.937604 The programs included with the Debian GNU/Linux system are free software;
11020 12:44:33.944175 the exact distribution terms for each program are described in the
11021 12:44:33.947060 individual files in /usr/share/doc/*/copyright.
11022 12:44:33.947164
11023 12:44:33.954190 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11024 12:44:33.957473 permitted by applicable law.
11025 12:44:33.957895 Matched prompt #10: / #
11027 12:44:33.958182 Setting prompt string to ['/ #']
11028 12:44:33.958304 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11030 12:44:33.958503 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11031 12:44:33.958592 start: 2.2.6 expect-shell-connection (timeout 00:03:18) [common]
11032 12:44:33.958664 Setting prompt string to ['/ #']
11033 12:44:33.958725 Forcing a shell prompt, looking for ['/ #']
11035 12:44:34.008930 / #
11036 12:44:34.009158 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11037 12:44:34.009281 Waiting using forced prompt support (timeout 00:02:30)
11038 12:44:34.013829
11039 12:44:34.014199 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11040 12:44:34.014316 start: 2.2.7 export-device-env (timeout 00:03:18) [common]
11041 12:44:34.014425 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11042 12:44:34.014514 end: 2.2 depthcharge-retry (duration 00:01:42) [common]
11043 12:44:34.014606 end: 2 depthcharge-action (duration 00:01:42) [common]
11044 12:44:34.014724 start: 3 lava-test-retry (timeout 00:07:55) [common]
11045 12:44:34.014843 start: 3.1 lava-test-shell (timeout 00:07:55) [common]
11046 12:44:34.014923 Using namespace: common
11048 12:44:34.115242 / # #
11049 12:44:34.115465 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11050 12:44:34.120908 #
11051 12:44:34.121263 Using /lava-12703541
11053 12:44:34.221646 / # export SHELL=/bin/sh
11054 12:44:34.226850 export SHELL=/bin/sh
11056 12:44:34.327491 / # . /lava-12703541/environment
11057 12:44:34.333127 . /lava-12703541/environment
11059 12:44:34.433752 / # /lava-12703541/bin/lava-test-runner /lava-12703541/0
11060 12:44:34.433956 Test shell timeout: 10s (minimum of the action and connection timeout)
11061 12:44:34.438939 /lava-12703541/bin/lava-test-runner /lava-12703541/0
11062 12:44:34.466821 + export TESTRUN_ID=0_igt-gpu-pa<8>[ 20.365731] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 12703541_1.5.2.3.1>
11063 12:44:34.467161 Received signal: <STARTRUN> 0_igt-gpu-panfrost 12703541_1.5.2.3.1
11064 12:44:34.467292 Starting test lava.0_igt-gpu-panfrost (12703541_1.5.2.3.1)
11065 12:44:34.467426 Skipping test definition patterns.
11066 12:44:34.470487 nfrost
11067 12:44:34.473927 + cd /lava-12703541/0/tests/0_igt-gpu-panfrost
11068 12:44:34.474042 + cat uuid
11069 12:44:34.476694 + UUID=12703541_1.5.2.3.1
11070 12:44:34.476788 + set +x
11071 12:44:34.487098 + IGT_FORCE_DRIVER=panfrost /usr/bin/ig<6>[ 20.385547] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11072 12:44:34.493405 <8>[ 20.392099] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
11073 12:44:34.493713 Received signal: <TESTSET> START panfrost_gem_new
11074 12:44:34.493801 Starting test_set panfrost_gem_new
11075 12:44:34.500160 t-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit
11076 12:44:34.508862 <14>[ 20.409519] [IGT] panfrost_gem_new: executing
11077 12:44:34.515413 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.416458] [IGT] panfrost_gem_new: exiting, ret=77
11078 12:44:34.518498 rch64) (Linux: 6.1.75-cip14 aarch64)
11079 12:44:34.528493 Test requirement not met i<8>[ 20.427112] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
11080 12:44:34.528820 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11082 12:44:34.535096 n function drm_open_driver, file ../lib/drmtest.c:621:
11083 12:44:34.535268 Test requirement: !(fd<0)
11084 12:44:34.541720 No known gpu found for chipset flags 0x32 (panfrost)
11085 12:44:34.545179 Last errno: 2, No such file or directory
11086 12:44:34.551556 [1mSubtest g<14>[ 20.450827] [IGT] panfrost_gem_new: executing
11087 12:44:34.551689 em-new-4096: SKIP (0.000s)[0m
11088 12:44:34.558196 IGT-Version: 1.2<14>[ 20.459559] [IGT] panfrost_gem_new: exiting, ret=77
11089 12:44:34.565511 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11090 12:44:34.575056 Test requirement not met in function drm_o<8>[ 20.473121] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
11091 12:44:34.575406 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11093 12:44:34.578702 pen_driver, file ../lib/drmtest.c:621:
11094 12:44:34.581790 Test requirement: !(fd<0)
11095 12:44:34.584891 No known gpu found for chipset flags 0x32 (panfrost)
11096 12:44:34.595084 Last errno: 2, No such file or director<14>[ 20.493443] [IGT] panfrost_gem_new: executing
11097 12:44:34.595216 y
11098 12:44:34.601716 [1mSubtest gem-new-0: SKIP (<14>[ 20.501598] [IGT] panfrost_gem_new: exiting, ret=77
11099 12:44:34.601843 0.000s)[0m
11100 12:44:34.614957 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.<8>[ 20.512166] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11101 12:44:34.615138 75-cip14 aarch64)
11102 12:44:34.615394 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11104 12:44:34.621629 Test requirem<8>[ 20.521674] <LAVA_SIGNAL_TESTSET STOP>
11105 12:44:34.621923 Received signal: <TESTSET> STOP
11106 12:44:34.622005 Closing test_set panfrost_gem_new
11107 12:44:34.628204 ent not met in function drm_open_driver, file ../lib/drmtest.c:621:
11108 12:44:34.628338 Test requirement: !(fd<0)
11109 12:44:34.634878 No known gpu found for chipset flags 0x32 (panfrost)
11110 12:44:34.641198 Last errno: 2, No such fil<8>[ 20.542052] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11111 12:44:34.641532 Received signal: <TESTSET> START panfrost_get_param
11112 12:44:34.641609 Starting test_set panfrost_get_param
11113 12:44:34.644809 e or directory
11114 12:44:34.647628 [1mSubtest gem-new-zeroed: SKIP (0.000s)[0m
11115 12:44:34.659811 <14>[ 20.560665] [IGT] panfrost_get_param: executing
11116 12:44:34.666533 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.567554] [IGT] panfrost_get_param: exiting, ret=77
11117 12:44:34.669610 rch64) (Linux: 6.1.75-cip14 aarch64)
11118 12:44:34.679968 Test requirement not met i<8>[ 20.578915] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11119 12:44:34.680305 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11121 12:44:34.686806 n function drm_open_driver, file ../lib/drmtest.c:621:
11122 12:44:34.686917 Test requirement: !(fd<0)
11123 12:44:34.693277 No known gpu found for chipset flags 0x32 (panfrost)
11124 12:44:34.696566 Last er<14>[ 20.598293] [IGT] panfrost_get_param: executing
11125 12:44:34.706656 rno: 2, No such file or director<14>[ 20.605840] [IGT] panfrost_get_param: exiting, ret=77
11126 12:44:34.706791 y
11127 12:44:34.709725 [1mSubtest base-params: SKIP (0.000s)[0m
11128 12:44:34.720097 IGT-Version: 1.27<8>[ 20.616727] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11129 12:44:34.720410 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11131 12:44:34.723194 .1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11132 12:44:34.729805 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11133 12:44:34.736413 Test requ<14>[ 20.636677] [IGT] panfrost_get_param: executing
11134 12:44:34.739557 irement: !(fd<0)
11135 12:44:34.746358 No known gpu f<14>[ 20.644315] [IGT] panfrost_get_param: exiting, ret=77
11136 12:44:34.749487 ound for chipset flags 0x32 (panfrost)
11137 12:44:34.755958 Last errno: 2, No such f<8>[ 20.655136] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11138 12:44:34.756258 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11140 12:44:34.759234 ile or directory
11141 12:44:34.763021 [1mSubtest ge<8>[ 20.664701] <LAVA_SIGNAL_TESTSET STOP>
11142 12:44:34.763298 Received signal: <TESTSET> STOP
11143 12:44:34.763373 Closing test_set panfrost_get_param
11144 12:44:34.766218 t-bad-param: SKIP (0.000s)[0m
11145 12:44:34.772851 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11146 12:44:34.785996 Test requirement not met in function drm_open_driver, file ../lib/drmtest.<8>[ 20.685050] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11147 12:44:34.786140 c:621:
11148 12:44:34.786387 Received signal: <TESTSET> START panfrost_prime
11149 12:44:34.786456 Starting test_set panfrost_prime
11150 12:44:34.789285 Test requirement: !(fd<0)
11151 12:44:34.792721 No known gpu found for chipset flags 0x32 (panfrost)
11152 12:44:34.796192 Last errno: 2, No such file or directory
11153 12:44:34.799062 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
11154 12:44:34.813259 <14>[ 20.713770] [IGT] panfrost_prime: executing
11155 12:44:34.823062 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 20.721568] [IGT] panfrost_prime: exiting, ret=77
11156 12:44:34.823201 .1.75-cip14 aarch64)
11157 12:44:34.836139 Test requirement not met in function drm_open_driver, file<8>[ 20.733475] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11158 12:44:34.836491 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11160 12:44:34.839478 ../lib/drmtest.c:621:
11161 12:44:34.842688 Test req<8>[ 20.743769] <LAVA_SIGNAL_TESTSET STOP>
11162 12:44:34.842950 Received signal: <TESTSET> STOP
11163 12:44:34.843020 Closing test_set panfrost_prime
11164 12:44:34.845857 uirement: !(fd<0)
11165 12:44:34.849633 No known gpu found for chipset flags 0x32 (panfrost)
11166 12:44:34.852627 Last errno: 2, No such file or directory
11167 12:44:34.855786 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
11168 12:44:34.863853 <8>[ 20.764209] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11169 12:44:34.864178 Received signal: <TESTSET> START panfrost_submit
11170 12:44:34.864293 Starting test_set panfrost_submit
11171 12:44:34.881333 <14>[ 20.782015] [IGT] panfrost_submit: executing
11172 12:44:34.887796 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.788705] [IGT] panfrost_submit: exiting, ret=77
11173 12:44:34.890808 rch64) (Linux: 6.1.75-cip14 aarch64)
11174 12:44:34.901127 Test requirement not met i<8>[ 20.799582] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11175 12:44:34.901430 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11177 12:44:34.907884 n function drm_open_driver, file ../lib/drmtest.c:621:
11178 12:44:34.908026 Test requirement: !(fd<0)
11179 12:44:34.914808 No known gpu found for chipset flags 0x32 (panfrost)
11180 12:44:34.917803 Last er<14>[ 20.819396] [IGT] panfrost_submit: executing
11181 12:44:34.928159 rno: 2, No such file or director<14>[ 20.826393] [IGT] panfrost_submit: exiting, ret=77
11182 12:44:34.928330 y
11183 12:44:34.931011 [1mSubtest pan-submit: SKIP (0.000s)[0m
11184 12:44:34.941045 IGT-Version: 1.27.<8>[ 20.837122] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11185 12:44:34.941353 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11187 12:44:34.944786 1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11188 12:44:34.950808 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11189 12:44:34.957828 Test requi<14>[ 20.857642] [IGT] panfrost_submit: executing
11190 12:44:34.957952 rement: !(fd<0)
11191 12:44:34.964051 No known gpu fo<14>[ 20.865065] [IGT] panfrost_submit: exiting, ret=77
11192 12:44:34.967924 und for chipset flags 0x32 (panfrost)
11193 12:44:34.971261 Last errno: 2, No such file or directory
11194 12:44:34.981121 <8>[ 20.877193] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11195 12:44:34.981257
11196 12:44:34.981506 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11198 12:44:34.984337 [1mSubtest pan-submit-error-no-jc: SKIP (0.000s)[0m
11199 12:44:34.990941 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11200 12:44:34.997840 Test requirement n<14>[ 20.898181] [IGT] panfrost_submit: executing
11201 12:44:35.004049 ot met in function drm_open_driv<14>[ 20.905481] [IGT] panfrost_submit: exiting, ret=77
11202 12:44:35.007243 er, file ../lib/drmtest.c:621:
11203 12:44:35.011340 Test requirement: !(fd<0)
11204 12:44:35.020945 No known gpu found fo<8>[ 20.917744] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11205 12:44:35.021254 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11207 12:44:35.024129 r chipset flags 0x32 (panfrost)
11208 12:44:35.027312 Last errno: 2, No such file or directory
11209 12:44:35.034188 [1mSubtest pan-submit-error-bad-in-syncs: SKIP (0.000s)[0m
11210 12:44:35.037235 IGT-Ver<14>[ 20.938950] [IGT] panfrost_submit: executing
11211 12:44:35.047387 sion: 1.27.1-g621c2d3 (aarch64) <14>[ 20.946276] [IGT] panfrost_submit: exiting, ret=77
11212 12:44:35.050910 (Linux: 6.1.75-cip14 aarch64)
11213 12:44:35.060392 Test requirement not met in funct<8>[ 20.957465] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11214 12:44:35.060748 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11216 12:44:35.064111 ion drm_open_driver, file ../lib/drmtest.c:621:
11217 12:44:35.067412 Test requirement: !(fd<0)
11218 12:44:35.073743 No known gpu found for chipset flags 0x32 (panfrost)
11219 12:44:35.077240 Last errno: 2,<14>[ 20.979173] [IGT] panfrost_submit: executing
11220 12:44:35.080678 No such file or directory
11221 12:44:35.087517 [1m<14>[ 20.985830] [IGT] panfrost_submit: exiting, ret=77
11222 12:44:35.090906 Subtest pan-submit-error-bad-bo-handles: SKIP (0.000s)[0m
11223 12:44:35.100392 IGT-<8>[ 20.996507] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11224 12:44:35.100687 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11226 12:44:35.107202 Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11227 12:44:35.117549 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:62<14>[ 21.017975] [IGT] panfrost_submit: executing
11228 12:44:35.117669 1:
11229 12:44:35.120685 Test requirement: !(fd<0)
11230 12:44:35.124025 N<14>[ 21.025077] [IGT] panfrost_submit: exiting, ret=77
11231 12:44:35.130501 o known gpu found for chipset flags 0x32 (panfrost)
11232 12:44:35.137404 Last errno:<8>[ 21.035581] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11233 12:44:35.137692 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11235 12:44:35.140632 2, No such file or directory
11236 12:44:35.147408 [1mSubtest pan-submit-error-bad-requirements: SKIP (0.000s)[0m
11237 12:44:35.153786 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: <14>[ 21.055183] [IGT] panfrost_submit: executing
11238 12:44:35.157024 6.1.75-cip14 aarch64)
11239 12:44:35.163539 Test requ<14>[ 21.062653] [IGT] panfrost_submit: exiting, ret=77
11240 12:44:35.176880 irement not met in function drm_open_driver, file ../lib/drmtest<8>[ 21.073140] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11241 12:44:35.177015 .c:621:
11242 12:44:35.177263 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11244 12:44:35.180487 Test requirement: !(fd<0)
11245 12:44:35.184027 No known gpu found for chipset flags 0x32 (panfrost)
11246 12:44:35.187533 Last errno: 2, No such file or directory
11247 12:44:35.193421 [1mSubtest <14>[ 21.093601] [IGT] panfrost_submit: executing
11248 12:44:35.200223 pan-submit-error-bad-out-sync: S<14>[ 21.101106] [IGT] panfrost_submit: exiting, ret=77
11249 12:44:35.203258 KIP (0.000s)[0m
11250 12:44:35.213434 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux:<8>[ 21.111433] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11251 12:44:35.213735 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11253 12:44:35.216513 6.1.75-cip14 aarch64)
11254 12:44:35.219895 Test req<8>[ 21.121971] <LAVA_SIGNAL_TESTSET STOP>
11255 12:44:35.220157 Received signal: <TESTSET> STOP
11256 12:44:35.220232 Closing test_set panfrost_submit
11257 12:44:35.229726 uirement not met<8>[ 21.128295] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 12703541_1.5.2.3.1>
11258 12:44:35.230019 Received signal: <ENDRUN> 0_igt-gpu-panfrost 12703541_1.5.2.3.1
11259 12:44:35.230113 Ending use of test pattern.
11260 12:44:35.230177 Ending test lava.0_igt-gpu-panfrost (12703541_1.5.2.3.1), duration 0.76
11262 12:44:35.232891 in function drm_open_driver, file ../lib/drmtest.c:621:
11263 12:44:35.236733 Test requirement: !(fd<0)
11264 12:44:35.243140 No known gpu found for chipset flags 0x32 (panfrost)
11265 12:44:35.246344 Last errno: 2, No such file or directory
11266 12:44:35.249978 [1mSubtest pan-reset: SKIP (0.000s)[0m
11267 12:44:35.256169 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11268 12:44:35.263159 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11269 12:44:35.266426 Test requirement: !(fd<0)
11270 12:44:35.269630 No known gpu found for chipset flags 0x32 (panfrost)
11271 12:44:35.272892 Last errno: 2, No such file or directory
11272 12:44:35.276033 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11273 12:44:35.283147 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11274 12:44:35.289677 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11275 12:44:35.292856 Test requirement: !(fd<0)
11276 12:44:35.299277 No known gpu found for chipset flags 0x32 (panfrost)
11277 12:44:35.302527 Last errno: 2, No such file or directory
11278 12:44:35.306307 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11279 12:44:35.306403 + set +x
11280 12:44:35.309453 <LAVA_TEST_RUNNER EXIT>
11281 12:44:35.309740 ok: lava_test_shell seems to have completed
11282 12:44:35.310115 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11283 12:44:35.310235 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11284 12:44:35.310340 end: 3 lava-test-retry (duration 00:00:01) [common]
11285 12:44:35.310448 start: 4 finalize (timeout 00:07:53) [common]
11286 12:44:35.310557 start: 4.1 power-off (timeout 00:00:30) [common]
11287 12:44:35.310851 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11288 12:44:35.384252 >> Command sent successfully.
11289 12:44:35.386800 Returned 0 in 0 seconds
11290 12:44:35.487231 end: 4.1 power-off (duration 00:00:00) [common]
11292 12:44:35.487573 start: 4.2 read-feedback (timeout 00:07:53) [common]
11293 12:44:35.487850 Listened to connection for namespace 'common' for up to 1s
11294 12:44:36.488359 Finalising connection for namespace 'common'
11295 12:44:36.488535 Disconnecting from shell: Finalise
11296 12:44:36.488615 / #
11297 12:44:36.588943 end: 4.2 read-feedback (duration 00:00:01) [common]
11298 12:44:36.589157 end: 4 finalize (duration 00:00:01) [common]
11299 12:44:36.589321 Cleaning after the job
11300 12:44:36.589461 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703541/tftp-deploy-ms6je3da/ramdisk
11301 12:44:36.599531 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703541/tftp-deploy-ms6je3da/kernel
11302 12:44:36.610530 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703541/tftp-deploy-ms6je3da/dtb
11303 12:44:36.610804 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703541/tftp-deploy-ms6je3da/modules
11304 12:44:36.617920 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12703541
11305 12:44:36.741216 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12703541
11306 12:44:36.741444 Job finished correctly