Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 15
- Kernel Errors: 34
1 12:36:48.331857 lava-dispatcher, installed at version: 2024.01
2 12:36:48.332074 start: 0 validate
3 12:36:48.332211 Start time: 2024-02-05 12:36:48.332203+00:00 (UTC)
4 12:36:48.332339 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:36:48.332497 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 12:36:48.606499 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:36:48.607217 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:37:33.123021 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:37:33.123666 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:37:33.395953 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:37:33.396694 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:37:45.165396 validate duration: 56.83
14 12:37:45.165722 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:37:45.165828 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:37:45.165944 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:37:45.166125 Not decompressing ramdisk as can be used compressed.
18 12:37:45.166209 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230623.0/arm64/rootfs.cpio.gz
19 12:37:45.166272 saving as /var/lib/lava/dispatcher/tmp/12703511/tftp-deploy-446whshk/ramdisk/rootfs.cpio.gz
20 12:37:45.166335 total size: 43284872 (41 MB)
21 12:37:45.433075 progress 0 % (0 MB)
22 12:37:45.447812 progress 5 % (2 MB)
23 12:37:45.459092 progress 10 % (4 MB)
24 12:37:45.470228 progress 15 % (6 MB)
25 12:37:45.481937 progress 20 % (8 MB)
26 12:37:45.493142 progress 25 % (10 MB)
27 12:37:45.504448 progress 30 % (12 MB)
28 12:37:45.515930 progress 35 % (14 MB)
29 12:37:45.527489 progress 40 % (16 MB)
30 12:37:45.538889 progress 45 % (18 MB)
31 12:37:45.550195 progress 50 % (20 MB)
32 12:37:45.561740 progress 55 % (22 MB)
33 12:37:45.573027 progress 60 % (24 MB)
34 12:37:45.584573 progress 65 % (26 MB)
35 12:37:45.596034 progress 70 % (28 MB)
36 12:37:45.607373 progress 75 % (30 MB)
37 12:37:45.618690 progress 80 % (33 MB)
38 12:37:45.630173 progress 85 % (35 MB)
39 12:37:45.641535 progress 90 % (37 MB)
40 12:37:45.652861 progress 95 % (39 MB)
41 12:37:45.664282 progress 100 % (41 MB)
42 12:37:45.664574 41 MB downloaded in 0.50 s (82.85 MB/s)
43 12:37:45.664738 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:37:45.664985 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:37:45.665072 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:37:45.665155 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:37:45.665297 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:37:45.665368 saving as /var/lib/lava/dispatcher/tmp/12703511/tftp-deploy-446whshk/kernel/Image
50 12:37:45.665429 total size: 51534336 (49 MB)
51 12:37:45.665491 No compression specified
52 12:37:45.666775 progress 0 % (0 MB)
53 12:37:45.680417 progress 5 % (2 MB)
54 12:37:45.693986 progress 10 % (4 MB)
55 12:37:45.707466 progress 15 % (7 MB)
56 12:37:45.720929 progress 20 % (9 MB)
57 12:37:45.734663 progress 25 % (12 MB)
58 12:37:45.747945 progress 30 % (14 MB)
59 12:37:45.761541 progress 35 % (17 MB)
60 12:37:45.775403 progress 40 % (19 MB)
61 12:37:45.788854 progress 45 % (22 MB)
62 12:37:45.802358 progress 50 % (24 MB)
63 12:37:45.815729 progress 55 % (27 MB)
64 12:37:45.829252 progress 60 % (29 MB)
65 12:37:45.842754 progress 65 % (31 MB)
66 12:37:45.856092 progress 70 % (34 MB)
67 12:37:45.869502 progress 75 % (36 MB)
68 12:37:45.883189 progress 80 % (39 MB)
69 12:37:45.896549 progress 85 % (41 MB)
70 12:37:45.909877 progress 90 % (44 MB)
71 12:37:45.923268 progress 95 % (46 MB)
72 12:37:45.936315 progress 100 % (49 MB)
73 12:37:45.936533 49 MB downloaded in 0.27 s (181.29 MB/s)
74 12:37:45.936688 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:37:45.936929 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:37:45.937022 start: 1.3 download-retry (timeout 00:09:59) [common]
78 12:37:45.937110 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 12:37:45.937254 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:37:45.937330 saving as /var/lib/lava/dispatcher/tmp/12703511/tftp-deploy-446whshk/dtb/mt8192-asurada-spherion-r0.dtb
81 12:37:45.937392 total size: 47278 (0 MB)
82 12:37:45.937453 No compression specified
83 12:37:46.200668 progress 69 % (0 MB)
84 12:37:46.201135 progress 100 % (0 MB)
85 12:37:46.201392 0 MB downloaded in 0.26 s (0.17 MB/s)
86 12:37:46.201596 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:37:46.201953 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:37:46.202083 start: 1.4 download-retry (timeout 00:09:59) [common]
90 12:37:46.202212 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 12:37:46.202405 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:37:46.202539 saving as /var/lib/lava/dispatcher/tmp/12703511/tftp-deploy-446whshk/modules/modules.tar
93 12:37:46.202638 total size: 8639964 (8 MB)
94 12:37:46.202734 Using unxz to decompress xz
95 12:37:46.207840 progress 0 % (0 MB)
96 12:37:46.230292 progress 5 % (0 MB)
97 12:37:46.254166 progress 10 % (0 MB)
98 12:37:46.278204 progress 15 % (1 MB)
99 12:37:46.302042 progress 20 % (1 MB)
100 12:37:46.326502 progress 25 % (2 MB)
101 12:37:46.355776 progress 30 % (2 MB)
102 12:37:46.381395 progress 35 % (2 MB)
103 12:37:46.406002 progress 40 % (3 MB)
104 12:37:46.431423 progress 45 % (3 MB)
105 12:37:46.457449 progress 50 % (4 MB)
106 12:37:46.484464 progress 55 % (4 MB)
107 12:37:46.510272 progress 60 % (4 MB)
108 12:37:46.536852 progress 65 % (5 MB)
109 12:37:46.562579 progress 70 % (5 MB)
110 12:37:46.588072 progress 75 % (6 MB)
111 12:37:46.616739 progress 80 % (6 MB)
112 12:37:46.645321 progress 85 % (7 MB)
113 12:37:46.671014 progress 90 % (7 MB)
114 12:37:46.701713 progress 95 % (7 MB)
115 12:37:46.730113 progress 100 % (8 MB)
116 12:37:46.736149 8 MB downloaded in 0.53 s (15.44 MB/s)
117 12:37:46.736409 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:37:46.736672 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:37:46.736766 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 12:37:46.736864 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 12:37:46.736944 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:37:46.737036 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 12:37:46.737269 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro
125 12:37:46.737404 makedir: /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro/lava-12703511/bin
126 12:37:46.737509 makedir: /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro/lava-12703511/tests
127 12:37:46.737608 makedir: /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro/lava-12703511/results
128 12:37:46.737751 Creating /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro/lava-12703511/bin/lava-add-keys
129 12:37:46.737899 Creating /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro/lava-12703511/bin/lava-add-sources
130 12:37:46.738028 Creating /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro/lava-12703511/bin/lava-background-process-start
131 12:37:46.738157 Creating /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro/lava-12703511/bin/lava-background-process-stop
132 12:37:46.738281 Creating /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro/lava-12703511/bin/lava-common-functions
133 12:37:46.738409 Creating /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro/lava-12703511/bin/lava-echo-ipv4
134 12:37:46.738571 Creating /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro/lava-12703511/bin/lava-install-packages
135 12:37:46.738695 Creating /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro/lava-12703511/bin/lava-installed-packages
136 12:37:46.738823 Creating /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro/lava-12703511/bin/lava-os-build
137 12:37:46.738949 Creating /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro/lava-12703511/bin/lava-probe-channel
138 12:37:46.739073 Creating /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro/lava-12703511/bin/lava-probe-ip
139 12:37:46.739197 Creating /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro/lava-12703511/bin/lava-target-ip
140 12:37:46.739319 Creating /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro/lava-12703511/bin/lava-target-mac
141 12:37:46.739442 Creating /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro/lava-12703511/bin/lava-target-storage
142 12:37:46.739571 Creating /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro/lava-12703511/bin/lava-test-case
143 12:37:46.739738 Creating /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro/lava-12703511/bin/lava-test-event
144 12:37:46.739863 Creating /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro/lava-12703511/bin/lava-test-feedback
145 12:37:46.739989 Creating /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro/lava-12703511/bin/lava-test-raise
146 12:37:46.740113 Creating /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro/lava-12703511/bin/lava-test-reference
147 12:37:46.740237 Creating /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro/lava-12703511/bin/lava-test-runner
148 12:37:46.740361 Creating /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro/lava-12703511/bin/lava-test-set
149 12:37:46.740487 Creating /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro/lava-12703511/bin/lava-test-shell
150 12:37:46.740615 Updating /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro/lava-12703511/bin/lava-install-packages (oe)
151 12:37:46.740767 Updating /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro/lava-12703511/bin/lava-installed-packages (oe)
152 12:37:46.740899 Creating /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro/lava-12703511/environment
153 12:37:46.741003 LAVA metadata
154 12:37:46.741078 - LAVA_JOB_ID=12703511
155 12:37:46.741142 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:37:46.741246 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:58) [common]
157 12:37:46.741311 skipped lava-vland-overlay
158 12:37:46.741383 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:37:46.741461 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:58) [common]
160 12:37:46.741523 skipped lava-multinode-overlay
161 12:37:46.741594 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:37:46.741702 start: 1.5.2.3 test-definition (timeout 00:09:58) [common]
163 12:37:46.741831 Loading test definitions
164 12:37:46.741932 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:58) [common]
165 12:37:46.742008 Using /lava-12703511 at stage 0
166 12:37:46.742323 uuid=12703511_1.5.2.3.1 testdef=None
167 12:37:46.742438 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:37:46.742537 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
169 12:37:46.743072 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:37:46.743297 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
172 12:37:46.744070 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:37:46.744299 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
175 12:37:46.744905 runner path: /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro/lava-12703511/0/tests/0_igt-kms-mediatek test_uuid 12703511_1.5.2.3.1
176 12:37:46.745061 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:37:46.745263 Creating lava-test-runner.conf files
179 12:37:46.745325 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12703511/lava-overlay-jkmfcoro/lava-12703511/0 for stage 0
180 12:37:46.745413 - 0_igt-kms-mediatek
181 12:37:46.745513 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:37:46.745595 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
183 12:37:46.752893 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:37:46.753003 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
185 12:37:46.753090 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:37:46.753173 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:37:46.753258 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
188 12:37:48.188905 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:37:48.189299 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 12:37:48.189417 extracting modules file /var/lib/lava/dispatcher/tmp/12703511/tftp-deploy-446whshk/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12703511/extract-overlay-ramdisk-6rjli9fh/ramdisk
191 12:37:48.449772 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:37:48.449940 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 12:37:48.450039 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12703511/compress-overlay-xgiuyfq3/overlay-1.5.2.4.tar.gz to ramdisk
194 12:37:48.450111 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12703511/compress-overlay-xgiuyfq3/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12703511/extract-overlay-ramdisk-6rjli9fh/ramdisk
195 12:37:48.456780 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:37:48.456895 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 12:37:48.456992 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:37:48.457088 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 12:37:48.457168 Building ramdisk /var/lib/lava/dispatcher/tmp/12703511/extract-overlay-ramdisk-6rjli9fh/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12703511/extract-overlay-ramdisk-6rjli9fh/ramdisk
200 12:37:49.498709 >> 370009 blocks
201 12:37:55.301245 rename /var/lib/lava/dispatcher/tmp/12703511/extract-overlay-ramdisk-6rjli9fh/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12703511/tftp-deploy-446whshk/ramdisk/ramdisk.cpio.gz
202 12:37:55.301798 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 12:37:55.301975 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 12:37:55.302124 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 12:37:55.302289 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12703511/tftp-deploy-446whshk/kernel/Image'
206 12:38:08.807824 Returned 0 in 13 seconds
207 12:38:08.908564 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12703511/tftp-deploy-446whshk/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12703511/tftp-deploy-446whshk/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12703511/tftp-deploy-446whshk/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12703511/tftp-deploy-446whshk/kernel/image.itb
208 12:38:09.748666 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:38:09.749142 output: Created: Mon Feb 5 12:38:09 2024
210 12:38:09.749254 output: Image 0 (kernel-1)
211 12:38:09.749351 output: Description:
212 12:38:09.749448 output: Created: Mon Feb 5 12:38:09 2024
213 12:38:09.749552 output: Type: Kernel Image
214 12:38:09.749646 output: Compression: lzma compressed
215 12:38:09.749743 output: Data Size: 12052857 Bytes = 11770.37 KiB = 11.49 MiB
216 12:38:09.749837 output: Architecture: AArch64
217 12:38:09.749934 output: OS: Linux
218 12:38:09.750024 output: Load Address: 0x00000000
219 12:38:09.750111 output: Entry Point: 0x00000000
220 12:38:09.750203 output: Hash algo: crc32
221 12:38:09.750292 output: Hash value: 8a14336a
222 12:38:09.750383 output: Image 1 (fdt-1)
223 12:38:09.750513 output: Description: mt8192-asurada-spherion-r0
224 12:38:09.750607 output: Created: Mon Feb 5 12:38:09 2024
225 12:38:09.750696 output: Type: Flat Device Tree
226 12:38:09.750782 output: Compression: uncompressed
227 12:38:09.750876 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 12:38:09.750963 output: Architecture: AArch64
229 12:38:09.751051 output: Hash algo: crc32
230 12:38:09.751138 output: Hash value: cc4352de
231 12:38:09.751226 output: Image 2 (ramdisk-1)
232 12:38:09.751312 output: Description: unavailable
233 12:38:09.751398 output: Created: Mon Feb 5 12:38:09 2024
234 12:38:09.751486 output: Type: RAMDisk Image
235 12:38:09.751574 output: Compression: Unknown Compression
236 12:38:09.751660 output: Data Size: 56433903 Bytes = 55111.23 KiB = 53.82 MiB
237 12:38:09.751747 output: Architecture: AArch64
238 12:38:09.751833 output: OS: Linux
239 12:38:09.751918 output: Load Address: unavailable
240 12:38:09.752004 output: Entry Point: unavailable
241 12:38:09.752089 output: Hash algo: crc32
242 12:38:09.752175 output: Hash value: 6002b86f
243 12:38:09.752261 output: Default Configuration: 'conf-1'
244 12:38:09.752345 output: Configuration 0 (conf-1)
245 12:38:09.752430 output: Description: mt8192-asurada-spherion-r0
246 12:38:09.752516 output: Kernel: kernel-1
247 12:38:09.752601 output: Init Ramdisk: ramdisk-1
248 12:38:09.752686 output: FDT: fdt-1
249 12:38:09.752771 output: Loadables: kernel-1
250 12:38:09.752855 output:
251 12:38:09.753123 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 12:38:09.753268 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 12:38:09.753415 end: 1.5 prepare-tftp-overlay (duration 00:00:23) [common]
254 12:38:09.753562 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:35) [common]
255 12:38:09.753683 No LXC device requested
256 12:38:09.753803 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:38:09.753930 start: 1.7 deploy-device-env (timeout 00:09:35) [common]
258 12:38:09.754051 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:38:09.754158 Checking files for TFTP limit of 4294967296 bytes.
260 12:38:09.754884 end: 1 tftp-deploy (duration 00:00:25) [common]
261 12:38:09.755023 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:38:09.755151 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:38:09.755329 substitutions:
264 12:38:09.755428 - {DTB}: 12703511/tftp-deploy-446whshk/dtb/mt8192-asurada-spherion-r0.dtb
265 12:38:09.755528 - {INITRD}: 12703511/tftp-deploy-446whshk/ramdisk/ramdisk.cpio.gz
266 12:38:09.755619 - {KERNEL}: 12703511/tftp-deploy-446whshk/kernel/Image
267 12:38:09.755709 - {LAVA_MAC}: None
268 12:38:09.755797 - {PRESEED_CONFIG}: None
269 12:38:09.755887 - {PRESEED_LOCAL}: None
270 12:38:09.755975 - {RAMDISK}: 12703511/tftp-deploy-446whshk/ramdisk/ramdisk.cpio.gz
271 12:38:09.756063 - {ROOT_PART}: None
272 12:38:09.756151 - {ROOT}: None
273 12:38:09.756239 - {SERVER_IP}: 192.168.201.1
274 12:38:09.756326 - {TEE}: None
275 12:38:09.756413 Parsed boot commands:
276 12:38:09.756498 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:38:09.756746 Parsed boot commands: tftpboot 192.168.201.1 12703511/tftp-deploy-446whshk/kernel/image.itb 12703511/tftp-deploy-446whshk/kernel/cmdline
278 12:38:09.756878 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:38:09.757003 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:38:09.757143 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:38:09.757275 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:38:09.757382 Not connected, no need to disconnect.
283 12:38:09.757497 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:38:09.757614 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:38:09.757716 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 12:38:09.762287 Setting prompt string to ['lava-test: # ']
287 12:38:09.762832 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:38:09.763009 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:38:09.763194 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:38:09.763322 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:38:09.763614 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
292 12:38:18.929952 >> Command sent successfully.
293 12:38:18.933148 Returned 0 in 9 seconds
294 12:38:19.033511 end: 2.2.2.1 pdu-reboot (duration 00:00:09) [common]
296 12:38:19.033910 end: 2.2.2 reset-device (duration 00:00:09) [common]
297 12:38:19.034025 start: 2.2.3 depthcharge-start (timeout 00:04:51) [common]
298 12:38:19.034129 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:38:19.034197 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:38:19.034266 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:38:19.034631 [Enter `^Ec?' for help]
302 12:38:19.209883
303 12:38:19.210059
304 12:38:19.210167 F0: 102B 0000
305 12:38:19.210262
306 12:38:19.210354 F3: 1001 0000 [0200]
307 12:38:19.210494
308 12:38:19.213560 F3: 1001 0000
309 12:38:19.213667
310 12:38:19.213761 F7: 102D 0000
311 12:38:19.213854
312 12:38:19.213939 F1: 0000 0000
313 12:38:19.214032
314 12:38:19.217081 V0: 0000 0000 [0001]
315 12:38:19.217166
316 12:38:19.217231 00: 0007 8000
317 12:38:19.217296
318 12:38:19.221183 01: 0000 0000
319 12:38:19.221278
320 12:38:19.221341 BP: 0C00 0209 [0000]
321 12:38:19.221399
322 12:38:19.221456 G0: 1182 0000
323 12:38:19.224493
324 12:38:19.224576 EC: 0000 0021 [4000]
325 12:38:19.224642
326 12:38:19.228175 S7: 0000 0000 [0000]
327 12:38:19.228264
328 12:38:19.228328 CC: 0000 0000 [0001]
329 12:38:19.228389
330 12:38:19.231356 T0: 0000 0040 [010F]
331 12:38:19.231442
332 12:38:19.231507 Jump to BL
333 12:38:19.231568
334 12:38:19.255875
335 12:38:19.256031
336 12:38:19.256100
337 12:38:19.263060 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:38:19.266705 ARM64: Exception handlers installed.
339 12:38:19.270234 ARM64: Testing exception
340 12:38:19.273998 ARM64: Done test exception
341 12:38:19.281174 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:38:19.291287 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:38:19.297896 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:38:19.308254 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:38:19.314977 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:38:19.321576 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:38:19.333422 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:38:19.340113 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:38:19.359150 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:38:19.362137 WDT: Last reset was cold boot
351 12:38:19.365547 SPI1(PAD0) initialized at 2873684 Hz
352 12:38:19.368898 SPI5(PAD0) initialized at 992727 Hz
353 12:38:19.372643 VBOOT: Loading verstage.
354 12:38:19.378826 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:38:19.382533 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:38:19.385930 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:38:19.388966 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:38:19.396755 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:38:19.403198 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:38:19.413866 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 12:38:19.414005
362 12:38:19.414073
363 12:38:19.423947 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:38:19.427544 ARM64: Exception handlers installed.
365 12:38:19.430640 ARM64: Testing exception
366 12:38:19.430733 ARM64: Done test exception
367 12:38:19.437632 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:38:19.440872 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:38:19.454743 Probing TPM: . done!
370 12:38:19.454886 TPM ready after 0 ms
371 12:38:19.462579 Connected to device vid:did:rid of 1ae0:0028:00
372 12:38:19.469134 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 12:38:19.598483 Initialized TPM device CR50 revision 0
374 12:38:19.602123 tlcl_send_startup: Startup return code is 0
375 12:38:19.609635 TPM: setup succeeded
376 12:38:19.623457 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:38:19.633598 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:38:19.644963 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:38:19.654819 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:38:19.658920 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:38:19.662285 in-header: 03 07 00 00 08 00 00 00
382 12:38:19.666763 in-data: aa e4 47 04 13 02 00 00
383 12:38:19.666863 Chrome EC: UHEPI supported
384 12:38:19.673882 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:38:19.677173 in-header: 03 ad 00 00 08 00 00 00
386 12:38:19.681169 in-data: 00 20 20 08 00 00 00 00
387 12:38:19.681264 Phase 1
388 12:38:19.684128 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:38:19.691439 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:38:19.698145 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:38:19.702005 Recovery requested (1009000e)
392 12:38:19.709629 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:38:19.715129 tlcl_extend: response is 0
394 12:38:19.722899 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:38:19.728447 tlcl_extend: response is 0
396 12:38:19.734892 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:38:19.755861 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 12:38:19.763318 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 12:38:19.763445
400 12:38:19.763512
401 12:38:19.770686 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:38:19.774735 ARM64: Exception handlers installed.
403 12:38:19.778237 ARM64: Testing exception
404 12:38:19.781385 ARM64: Done test exception
405 12:38:19.801597 pmic_efuse_setting: Set efuses in 11 msecs
406 12:38:19.805564 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:38:19.808832 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:38:19.816854 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:38:19.820242 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:38:19.824153 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:38:19.831768 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:38:19.835441 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:38:19.838902 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:38:19.842823 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:38:19.849740 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:38:19.853587 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:38:19.857058 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:38:19.860921 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:38:19.868828 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:38:19.872172 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:38:19.879736 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:38:19.886985 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:38:19.890368 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:38:19.897648 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:38:19.901044 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:38:19.908117 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:38:19.911697 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:38:19.919730 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:38:19.923077 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:38:19.930816 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:38:19.934383 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:38:19.941871 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:38:19.945084 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:38:19.949158 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:38:19.956113 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:38:19.960321 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:38:19.964136 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:38:19.971677 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:38:19.975105 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:38:19.978868 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:38:19.986306 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:38:19.989916 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:38:19.993410 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:38:20.001005 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:38:20.005451 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:38:20.008651 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:38:20.012556 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:38:20.019947 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:38:20.023336 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:38:20.027174 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:38:20.030652 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:38:20.034917 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:38:20.038285 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:38:20.041913 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:38:20.050297 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:38:20.053388 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:38:20.057051 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:38:20.065093 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:38:20.071840 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:38:20.075583 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:38:20.086711 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:38:20.093960 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:38:20.097620 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:38:20.101734 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:38:20.105297 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:38:20.114660 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0xc
467 12:38:20.118270 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:38:20.126035 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 12:38:20.129500 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:38:20.138589 [RTC]rtc_get_frequency_meter,154: input=15, output=790
471 12:38:20.148498 [RTC]rtc_get_frequency_meter,154: input=23, output=978
472 12:38:20.157726 [RTC]rtc_get_frequency_meter,154: input=19, output=885
473 12:38:20.167542 [RTC]rtc_get_frequency_meter,154: input=17, output=836
474 12:38:20.176897 [RTC]rtc_get_frequency_meter,154: input=16, output=813
475 12:38:20.186252 [RTC]rtc_get_frequency_meter,154: input=15, output=790
476 12:38:20.195871 [RTC]rtc_get_frequency_meter,154: input=16, output=814
477 12:38:20.199953 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
478 12:38:20.203160 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
479 12:38:20.206945 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 12:38:20.214703 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 12:38:20.218320 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 12:38:20.221870 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 12:38:20.225734 ADC[4]: Raw value=902066 ID=7
484 12:38:20.225831 ADC[3]: Raw value=213336 ID=1
485 12:38:20.228931 RAM Code: 0x71
486 12:38:20.233248 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 12:38:20.237049 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 12:38:20.248769 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 12:38:20.251914 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 12:38:20.255139 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 12:38:20.259356 in-header: 03 07 00 00 08 00 00 00
492 12:38:20.262958 in-data: aa e4 47 04 13 02 00 00
493 12:38:20.266693 Chrome EC: UHEPI supported
494 12:38:20.273664 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 12:38:20.277643 in-header: 03 ed 00 00 08 00 00 00
496 12:38:20.277749 in-data: 80 20 60 08 00 00 00 00
497 12:38:20.280988 MRC: failed to locate region type 0.
498 12:38:20.288642 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 12:38:20.292834 DRAM-K: Running full calibration
500 12:38:20.299911 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 12:38:20.300056 header.status = 0x0
502 12:38:20.303381 header.version = 0x6 (expected: 0x6)
503 12:38:20.306917 header.size = 0xd00 (expected: 0xd00)
504 12:38:20.307002 header.flags = 0x0
505 12:38:20.314382 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 12:38:20.331786 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 12:38:20.338880 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 12:38:20.342338 dram_init: ddr_geometry: 2
509 12:38:20.342482 [EMI] MDL number = 2
510 12:38:20.345751 [EMI] Get MDL freq = 0
511 12:38:20.349225 dram_init: ddr_type: 0
512 12:38:20.349335 is_discrete_lpddr4: 1
513 12:38:20.352306 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 12:38:20.352413
515 12:38:20.352503
516 12:38:20.355936 [Bian_co] ETT version 0.0.0.1
517 12:38:20.362220 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 12:38:20.362312
519 12:38:20.365522 dramc_set_vcore_voltage set vcore to 650000
520 12:38:20.365607 Read voltage for 800, 4
521 12:38:20.369146 Vio18 = 0
522 12:38:20.369220 Vcore = 650000
523 12:38:20.369281 Vdram = 0
524 12:38:20.372840 Vddq = 0
525 12:38:20.372934 Vmddr = 0
526 12:38:20.375982 dram_init: config_dvfs: 1
527 12:38:20.379197 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 12:38:20.386049 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 12:38:20.389223 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
530 12:38:20.392751 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
531 12:38:20.395689 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
532 12:38:20.399264 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
533 12:38:20.402837 MEM_TYPE=3, freq_sel=18
534 12:38:20.406038 sv_algorithm_assistance_LP4_1600
535 12:38:20.409460 ============ PULL DRAM RESETB DOWN ============
536 12:38:20.412930 ========== PULL DRAM RESETB DOWN end =========
537 12:38:20.419715 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 12:38:20.423038 ===================================
539 12:38:20.423135 LPDDR4 DRAM CONFIGURATION
540 12:38:20.426246 ===================================
541 12:38:20.429591 EX_ROW_EN[0] = 0x0
542 12:38:20.429683 EX_ROW_EN[1] = 0x0
543 12:38:20.432868 LP4Y_EN = 0x0
544 12:38:20.432953 WORK_FSP = 0x0
545 12:38:20.436136 WL = 0x2
546 12:38:20.440135 RL = 0x2
547 12:38:20.440223 BL = 0x2
548 12:38:20.443515 RPST = 0x0
549 12:38:20.443601 RD_PRE = 0x0
550 12:38:20.446338 WR_PRE = 0x1
551 12:38:20.446445 WR_PST = 0x0
552 12:38:20.449347 DBI_WR = 0x0
553 12:38:20.449429 DBI_RD = 0x0
554 12:38:20.453121 OTF = 0x1
555 12:38:20.456033 ===================================
556 12:38:20.459663 ===================================
557 12:38:20.459752 ANA top config
558 12:38:20.462809 ===================================
559 12:38:20.466589 DLL_ASYNC_EN = 0
560 12:38:20.466681 ALL_SLAVE_EN = 1
561 12:38:20.470023 NEW_RANK_MODE = 1
562 12:38:20.473008 DLL_IDLE_MODE = 1
563 12:38:20.476794 LP45_APHY_COMB_EN = 1
564 12:38:20.479615 TX_ODT_DIS = 1
565 12:38:20.479703 NEW_8X_MODE = 1
566 12:38:20.483103 ===================================
567 12:38:20.487273 ===================================
568 12:38:20.491027 data_rate = 1600
569 12:38:20.494904 CKR = 1
570 12:38:20.495001 DQ_P2S_RATIO = 8
571 12:38:20.498379 ===================================
572 12:38:20.502187 CA_P2S_RATIO = 8
573 12:38:20.505744 DQ_CA_OPEN = 0
574 12:38:20.510027 DQ_SEMI_OPEN = 0
575 12:38:20.510128 CA_SEMI_OPEN = 0
576 12:38:20.513077 CA_FULL_RATE = 0
577 12:38:20.517153 DQ_CKDIV4_EN = 1
578 12:38:20.520447 CA_CKDIV4_EN = 1
579 12:38:20.520601 CA_PREDIV_EN = 0
580 12:38:20.523861 PH8_DLY = 0
581 12:38:20.526965 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 12:38:20.530160 DQ_AAMCK_DIV = 4
583 12:38:20.533952 CA_AAMCK_DIV = 4
584 12:38:20.534061 CA_ADMCK_DIV = 4
585 12:38:20.536799 DQ_TRACK_CA_EN = 0
586 12:38:20.540283 CA_PICK = 800
587 12:38:20.543951 CA_MCKIO = 800
588 12:38:20.547126 MCKIO_SEMI = 0
589 12:38:20.550592 PLL_FREQ = 3068
590 12:38:20.553705 DQ_UI_PI_RATIO = 32
591 12:38:20.553814 CA_UI_PI_RATIO = 0
592 12:38:20.556925 ===================================
593 12:38:20.560583 ===================================
594 12:38:20.563970 memory_type:LPDDR4
595 12:38:20.567244 GP_NUM : 10
596 12:38:20.567329 SRAM_EN : 1
597 12:38:20.570833 MD32_EN : 0
598 12:38:20.574296 ===================================
599 12:38:20.577455 [ANA_INIT] >>>>>>>>>>>>>>
600 12:38:20.580688 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 12:38:20.584200 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 12:38:20.587627 ===================================
603 12:38:20.587706 data_rate = 1600,PCW = 0X7600
604 12:38:20.591001 ===================================
605 12:38:20.593895 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 12:38:20.601260 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 12:38:20.607613 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 12:38:20.610701 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 12:38:20.614216 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 12:38:20.617609 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 12:38:20.620881 [ANA_INIT] flow start
612 12:38:20.620999 [ANA_INIT] PLL >>>>>>>>
613 12:38:20.623954 [ANA_INIT] PLL <<<<<<<<
614 12:38:20.627953 [ANA_INIT] MIDPI >>>>>>>>
615 12:38:20.628046 [ANA_INIT] MIDPI <<<<<<<<
616 12:38:20.630947 [ANA_INIT] DLL >>>>>>>>
617 12:38:20.634364 [ANA_INIT] flow end
618 12:38:20.637809 ============ LP4 DIFF to SE enter ============
619 12:38:20.641292 ============ LP4 DIFF to SE exit ============
620 12:38:20.644465 [ANA_INIT] <<<<<<<<<<<<<
621 12:38:20.648411 [Flow] Enable top DCM control >>>>>
622 12:38:20.651660 [Flow] Enable top DCM control <<<<<
623 12:38:20.655132 Enable DLL master slave shuffle
624 12:38:20.658175 ==============================================================
625 12:38:20.661682 Gating Mode config
626 12:38:20.664580 ==============================================================
627 12:38:20.668002 Config description:
628 12:38:20.677944 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 12:38:20.684494 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 12:38:20.688217 SELPH_MODE 0: By rank 1: By Phase
631 12:38:20.694872 ==============================================================
632 12:38:20.698633 GAT_TRACK_EN = 1
633 12:38:20.702345 RX_GATING_MODE = 2
634 12:38:20.702510 RX_GATING_TRACK_MODE = 2
635 12:38:20.705306 SELPH_MODE = 1
636 12:38:20.709090 PICG_EARLY_EN = 1
637 12:38:20.712449 VALID_LAT_VALUE = 1
638 12:38:20.718617 ==============================================================
639 12:38:20.722188 Enter into Gating configuration >>>>
640 12:38:20.725704 Exit from Gating configuration <<<<
641 12:38:20.728565 Enter into DVFS_PRE_config >>>>>
642 12:38:20.739173 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 12:38:20.742355 Exit from DVFS_PRE_config <<<<<
644 12:38:20.745340 Enter into PICG configuration >>>>
645 12:38:20.749208 Exit from PICG configuration <<<<
646 12:38:20.752125 [RX_INPUT] configuration >>>>>
647 12:38:20.752211 [RX_INPUT] configuration <<<<<
648 12:38:20.759014 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 12:38:20.765639 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 12:38:20.768921 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 12:38:20.775490 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 12:38:20.782703 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 12:38:20.789246 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 12:38:20.792556 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 12:38:20.796024 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 12:38:20.802386 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 12:38:20.806313 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 12:38:20.809415 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 12:38:20.812520 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 12:38:20.816122 ===================================
661 12:38:20.820009 LPDDR4 DRAM CONFIGURATION
662 12:38:20.822754 ===================================
663 12:38:20.825953 EX_ROW_EN[0] = 0x0
664 12:38:20.826040 EX_ROW_EN[1] = 0x0
665 12:38:20.829378 LP4Y_EN = 0x0
666 12:38:20.829462 WORK_FSP = 0x0
667 12:38:20.832665 WL = 0x2
668 12:38:20.832750 RL = 0x2
669 12:38:20.836496 BL = 0x2
670 12:38:20.836580 RPST = 0x0
671 12:38:20.839466 RD_PRE = 0x0
672 12:38:20.839548 WR_PRE = 0x1
673 12:38:20.842737 WR_PST = 0x0
674 12:38:20.842824 DBI_WR = 0x0
675 12:38:20.846138 DBI_RD = 0x0
676 12:38:20.846220 OTF = 0x1
677 12:38:20.850070 ===================================
678 12:38:20.856115 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 12:38:20.859871 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 12:38:20.862731 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 12:38:20.866258 ===================================
682 12:38:20.869788 LPDDR4 DRAM CONFIGURATION
683 12:38:20.872905 ===================================
684 12:38:20.873032 EX_ROW_EN[0] = 0x10
685 12:38:20.876165 EX_ROW_EN[1] = 0x0
686 12:38:20.879498 LP4Y_EN = 0x0
687 12:38:20.879585 WORK_FSP = 0x0
688 12:38:20.883065 WL = 0x2
689 12:38:20.883150 RL = 0x2
690 12:38:20.887008 BL = 0x2
691 12:38:20.887092 RPST = 0x0
692 12:38:20.889669 RD_PRE = 0x0
693 12:38:20.889751 WR_PRE = 0x1
694 12:38:20.892983 WR_PST = 0x0
695 12:38:20.893067 DBI_WR = 0x0
696 12:38:20.896519 DBI_RD = 0x0
697 12:38:20.896602 OTF = 0x1
698 12:38:20.900109 ===================================
699 12:38:20.906835 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 12:38:20.910320 nWR fixed to 40
701 12:38:20.914203 [ModeRegInit_LP4] CH0 RK0
702 12:38:20.914293 [ModeRegInit_LP4] CH0 RK1
703 12:38:20.917701 [ModeRegInit_LP4] CH1 RK0
704 12:38:20.920554 [ModeRegInit_LP4] CH1 RK1
705 12:38:20.920642 match AC timing 13
706 12:38:20.927739 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 12:38:20.930793 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 12:38:20.934253 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 12:38:20.940798 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 12:38:20.944953 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 12:38:20.945045 [EMI DOE] emi_dcm 0
712 12:38:20.951545 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 12:38:20.951631 ==
714 12:38:20.954134 Dram Type= 6, Freq= 0, CH_0, rank 0
715 12:38:20.957610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 12:38:20.957698 ==
717 12:38:20.963890 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 12:38:20.967512 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 12:38:20.978530 [CA 0] Center 37 (7~68) winsize 62
720 12:38:20.981572 [CA 1] Center 37 (6~68) winsize 63
721 12:38:20.984998 [CA 2] Center 35 (5~66) winsize 62
722 12:38:20.988197 [CA 3] Center 34 (4~65) winsize 62
723 12:38:20.991836 [CA 4] Center 34 (3~65) winsize 63
724 12:38:20.995010 [CA 5] Center 33 (3~64) winsize 62
725 12:38:20.995100
726 12:38:20.998082 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 12:38:20.998200
728 12:38:21.001579 [CATrainingPosCal] consider 1 rank data
729 12:38:21.005009 u2DelayCellTimex100 = 270/100 ps
730 12:38:21.008635 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 12:38:21.011434 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 12:38:21.014940 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
733 12:38:21.021631 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 12:38:21.025285 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
735 12:38:21.028510 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 12:38:21.028617
737 12:38:21.031656 CA PerBit enable=1, Macro0, CA PI delay=33
738 12:38:21.031759
739 12:38:21.035069 [CBTSetCACLKResult] CA Dly = 33
740 12:38:21.035154 CS Dly: 5 (0~36)
741 12:38:21.035216 ==
742 12:38:21.038260 Dram Type= 6, Freq= 0, CH_0, rank 1
743 12:38:21.045117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 12:38:21.045261 ==
745 12:38:21.048356 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 12:38:21.055433 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 12:38:21.064462 [CA 0] Center 37 (7~68) winsize 62
748 12:38:21.068387 [CA 1] Center 37 (7~68) winsize 62
749 12:38:21.072031 [CA 2] Center 35 (5~66) winsize 62
750 12:38:21.075963 [CA 3] Center 35 (4~66) winsize 63
751 12:38:21.079996 [CA 4] Center 34 (3~65) winsize 63
752 12:38:21.080094 [CA 5] Center 33 (3~64) winsize 62
753 12:38:21.083021
754 12:38:21.086312 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 12:38:21.086461
756 12:38:21.089957 [CATrainingPosCal] consider 2 rank data
757 12:38:21.093334 u2DelayCellTimex100 = 270/100 ps
758 12:38:21.097422 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 12:38:21.100288 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 12:38:21.104043 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
761 12:38:21.107316 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 12:38:21.110377 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
763 12:38:21.113516 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 12:38:21.113602
765 12:38:21.116884 CA PerBit enable=1, Macro0, CA PI delay=33
766 12:38:21.117015
767 12:38:21.120498 [CBTSetCACLKResult] CA Dly = 33
768 12:38:21.123975 CS Dly: 6 (0~38)
769 12:38:21.124064
770 12:38:21.127043 ----->DramcWriteLeveling(PI) begin...
771 12:38:21.127134 ==
772 12:38:21.130515 Dram Type= 6, Freq= 0, CH_0, rank 0
773 12:38:21.133934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 12:38:21.134019 ==
775 12:38:21.137362 Write leveling (Byte 0): 27 => 27
776 12:38:21.140697 Write leveling (Byte 1): 31 => 31
777 12:38:21.143797 DramcWriteLeveling(PI) end<-----
778 12:38:21.143884
779 12:38:21.143949 ==
780 12:38:21.147689 Dram Type= 6, Freq= 0, CH_0, rank 0
781 12:38:21.150859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 12:38:21.150946 ==
783 12:38:21.153813 [Gating] SW mode calibration
784 12:38:21.160704 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 12:38:21.164036 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 12:38:21.171216 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 12:38:21.174337 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 12:38:21.177468 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 12:38:21.184492 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 12:38:21.187491 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:38:21.191143 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:38:21.197652 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:38:21.201071 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:38:21.204332 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:38:21.211057 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:38:21.214637 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:38:21.217580 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:38:21.224641 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:38:21.228031 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:38:21.231361 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:38:21.234335 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:38:21.240838 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:38:21.244389 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
804 12:38:21.247846 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 12:38:21.255222 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
806 12:38:21.257618 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:38:21.261166 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:38:21.267734 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:38:21.271643 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 12:38:21.275275 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 12:38:21.281383 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:38:21.284457 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 12:38:21.287760 0 9 12 | B1->B0 | 2929 3333 | 1 1 | (0 0) (1 1)
814 12:38:21.294360 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 12:38:21.297883 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 12:38:21.301519 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 12:38:21.304708 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 12:38:21.311317 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 12:38:21.314877 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 12:38:21.318203 0 10 8 | B1->B0 | 3131 3030 | 0 0 | (0 1) (0 1)
821 12:38:21.324625 0 10 12 | B1->B0 | 2f2f 2626 | 0 0 | (0 0) (0 0)
822 12:38:21.328729 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:38:21.331463 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:38:21.338121 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 12:38:21.341202 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 12:38:21.344888 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:38:21.351477 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 12:38:21.355015 0 11 8 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
829 12:38:21.358827 0 11 12 | B1->B0 | 3838 4545 | 0 1 | (0 0) (0 0)
830 12:38:21.364759 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 12:38:21.368547 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 12:38:21.371987 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 12:38:21.375855 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 12:38:21.381657 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 12:38:21.385126 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 12:38:21.388587 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 12:38:21.395022 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 12:38:21.398704 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 12:38:21.401833 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:38:21.408145 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:38:21.411735 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:38:21.414873 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:38:21.421624 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:38:21.425102 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:38:21.428583 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:38:21.435240 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:38:21.438310 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:38:21.441939 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 12:38:21.448546 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 12:38:21.451651 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 12:38:21.455158 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 12:38:21.459135 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
853 12:38:21.465905 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
854 12:38:21.468548 Total UI for P1: 0, mck2ui 16
855 12:38:21.472228 best dqsien dly found for B0: ( 0, 14, 8)
856 12:38:21.475217 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 12:38:21.478863 Total UI for P1: 0, mck2ui 16
858 12:38:21.482188 best dqsien dly found for B1: ( 0, 14, 10)
859 12:38:21.485728 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
860 12:38:21.488762 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
861 12:38:21.488876
862 12:38:21.492285 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 12:38:21.495187 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
864 12:38:21.499011 [Gating] SW calibration Done
865 12:38:21.499109 ==
866 12:38:21.502257 Dram Type= 6, Freq= 0, CH_0, rank 0
867 12:38:21.505791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 12:38:21.505886 ==
869 12:38:21.508832 RX Vref Scan: 0
870 12:38:21.508948
871 12:38:21.512523 RX Vref 0 -> 0, step: 1
872 12:38:21.512643
873 12:38:21.512744 RX Delay -130 -> 252, step: 16
874 12:38:21.518987 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
875 12:38:21.522456 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
876 12:38:21.525905 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
877 12:38:21.529390 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
878 12:38:21.532387 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
879 12:38:21.539154 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
880 12:38:21.542732 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
881 12:38:21.545711 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
882 12:38:21.549743 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
883 12:38:21.552656 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
884 12:38:21.555745 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
885 12:38:21.563458 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
886 12:38:21.566196 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
887 12:38:21.569562 iDelay=206, Bit 13, Center 77 (-34 ~ 189) 224
888 12:38:21.572358 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
889 12:38:21.579598 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
890 12:38:21.579717 ==
891 12:38:21.582933 Dram Type= 6, Freq= 0, CH_0, rank 0
892 12:38:21.586686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 12:38:21.586783 ==
894 12:38:21.586847 DQS Delay:
895 12:38:21.589467 DQS0 = 0, DQS1 = 0
896 12:38:21.589558 DQM Delay:
897 12:38:21.592620 DQM0 = 84, DQM1 = 77
898 12:38:21.592736 DQ Delay:
899 12:38:21.596337 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
900 12:38:21.599609 DQ4 =85, DQ5 =77, DQ6 =85, DQ7 =85
901 12:38:21.603060 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
902 12:38:21.606291 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
903 12:38:21.606379
904 12:38:21.606495
905 12:38:21.606555 ==
906 12:38:21.609780 Dram Type= 6, Freq= 0, CH_0, rank 0
907 12:38:21.613366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 12:38:21.613466 ==
909 12:38:21.613533
910 12:38:21.613593
911 12:38:21.616556 TX Vref Scan disable
912 12:38:21.619896 == TX Byte 0 ==
913 12:38:21.623503 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
914 12:38:21.626761 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
915 12:38:21.629628 == TX Byte 1 ==
916 12:38:21.633007 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
917 12:38:21.636675 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
918 12:38:21.636766 ==
919 12:38:21.639985 Dram Type= 6, Freq= 0, CH_0, rank 0
920 12:38:21.643483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 12:38:21.643573 ==
922 12:38:21.657541 TX Vref=22, minBit 7, minWin=26, winSum=436
923 12:38:21.660901 TX Vref=24, minBit 0, minWin=27, winSum=439
924 12:38:21.664665 TX Vref=26, minBit 3, minWin=27, winSum=443
925 12:38:21.667751 TX Vref=28, minBit 3, minWin=27, winSum=448
926 12:38:21.671307 TX Vref=30, minBit 0, minWin=28, winSum=453
927 12:38:21.674558 TX Vref=32, minBit 3, minWin=27, winSum=447
928 12:38:21.681494 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 30
929 12:38:21.681615
930 12:38:21.684459 Final TX Range 1 Vref 30
931 12:38:21.684535
932 12:38:21.684606 ==
933 12:38:21.687762 Dram Type= 6, Freq= 0, CH_0, rank 0
934 12:38:21.691574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 12:38:21.691660 ==
936 12:38:21.691774
937 12:38:21.691863
938 12:38:21.694754 TX Vref Scan disable
939 12:38:21.698163 == TX Byte 0 ==
940 12:38:21.701446 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
941 12:38:21.705624 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
942 12:38:21.709259 == TX Byte 1 ==
943 12:38:21.712163 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
944 12:38:21.715582 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
945 12:38:21.715684
946 12:38:21.715819 [DATLAT]
947 12:38:21.718743 Freq=800, CH0 RK0
948 12:38:21.718827
949 12:38:21.722142 DATLAT Default: 0xa
950 12:38:21.722253 0, 0xFFFF, sum = 0
951 12:38:21.725642 1, 0xFFFF, sum = 0
952 12:38:21.725733 2, 0xFFFF, sum = 0
953 12:38:21.728927 3, 0xFFFF, sum = 0
954 12:38:21.729012 4, 0xFFFF, sum = 0
955 12:38:21.733135 5, 0xFFFF, sum = 0
956 12:38:21.733226 6, 0xFFFF, sum = 0
957 12:38:21.733291 7, 0xFFFF, sum = 0
958 12:38:21.736227 8, 0xFFFF, sum = 0
959 12:38:21.736325 9, 0x0, sum = 1
960 12:38:21.740489 10, 0x0, sum = 2
961 12:38:21.740581 11, 0x0, sum = 3
962 12:38:21.743786 12, 0x0, sum = 4
963 12:38:21.743874 best_step = 10
964 12:38:21.743937
965 12:38:21.744000 ==
966 12:38:21.747845 Dram Type= 6, Freq= 0, CH_0, rank 0
967 12:38:21.751647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 12:38:21.751767 ==
969 12:38:21.755460 RX Vref Scan: 1
970 12:38:21.755548
971 12:38:21.755613 Set Vref Range= 32 -> 127
972 12:38:21.755673
973 12:38:21.759713 RX Vref 32 -> 127, step: 1
974 12:38:21.759801
975 12:38:21.763058 RX Delay -95 -> 252, step: 8
976 12:38:21.763171
977 12:38:21.763281 Set Vref, RX VrefLevel [Byte0]: 32
978 12:38:21.766549 [Byte1]: 32
979 12:38:21.770599
980 12:38:21.770693 Set Vref, RX VrefLevel [Byte0]: 33
981 12:38:21.774136 [Byte1]: 33
982 12:38:21.777922
983 12:38:21.778015 Set Vref, RX VrefLevel [Byte0]: 34
984 12:38:21.781526 [Byte1]: 34
985 12:38:21.785885
986 12:38:21.785973 Set Vref, RX VrefLevel [Byte0]: 35
987 12:38:21.789264 [Byte1]: 35
988 12:38:21.793582
989 12:38:21.793698 Set Vref, RX VrefLevel [Byte0]: 36
990 12:38:21.797004 [Byte1]: 36
991 12:38:21.800852
992 12:38:21.800941 Set Vref, RX VrefLevel [Byte0]: 37
993 12:38:21.804883 [Byte1]: 37
994 12:38:21.808600
995 12:38:21.808706 Set Vref, RX VrefLevel [Byte0]: 38
996 12:38:21.811752 [Byte1]: 38
997 12:38:21.816207
998 12:38:21.816299 Set Vref, RX VrefLevel [Byte0]: 39
999 12:38:21.819494 [Byte1]: 39
1000 12:38:21.823576
1001 12:38:21.823675 Set Vref, RX VrefLevel [Byte0]: 40
1002 12:38:21.826947 [Byte1]: 40
1003 12:38:21.830948
1004 12:38:21.831084 Set Vref, RX VrefLevel [Byte0]: 41
1005 12:38:21.834845 [Byte1]: 41
1006 12:38:21.838933
1007 12:38:21.839062 Set Vref, RX VrefLevel [Byte0]: 42
1008 12:38:21.841785 [Byte1]: 42
1009 12:38:21.846300
1010 12:38:21.846491 Set Vref, RX VrefLevel [Byte0]: 43
1011 12:38:21.849713 [Byte1]: 43
1012 12:38:21.854165
1013 12:38:21.854285 Set Vref, RX VrefLevel [Byte0]: 44
1014 12:38:21.856963 [Byte1]: 44
1015 12:38:21.861633
1016 12:38:21.861758 Set Vref, RX VrefLevel [Byte0]: 45
1017 12:38:21.865005 [Byte1]: 45
1018 12:38:21.868978
1019 12:38:21.869157 Set Vref, RX VrefLevel [Byte0]: 46
1020 12:38:21.872782 [Byte1]: 46
1021 12:38:21.876503
1022 12:38:21.876624 Set Vref, RX VrefLevel [Byte0]: 47
1023 12:38:21.879856 [Byte1]: 47
1024 12:38:21.884245
1025 12:38:21.884369 Set Vref, RX VrefLevel [Byte0]: 48
1026 12:38:21.887742 [Byte1]: 48
1027 12:38:21.892034
1028 12:38:21.892153 Set Vref, RX VrefLevel [Byte0]: 49
1029 12:38:21.895044 [Byte1]: 49
1030 12:38:21.899931
1031 12:38:21.900061 Set Vref, RX VrefLevel [Byte0]: 50
1032 12:38:21.903156 [Byte1]: 50
1033 12:38:21.907144
1034 12:38:21.907238 Set Vref, RX VrefLevel [Byte0]: 51
1035 12:38:21.910677 [Byte1]: 51
1036 12:38:21.914433
1037 12:38:21.914536 Set Vref, RX VrefLevel [Byte0]: 52
1038 12:38:21.917922 [Byte1]: 52
1039 12:38:21.922691
1040 12:38:21.922788 Set Vref, RX VrefLevel [Byte0]: 53
1041 12:38:21.925351 [Byte1]: 53
1042 12:38:21.930241
1043 12:38:21.930359 Set Vref, RX VrefLevel [Byte0]: 54
1044 12:38:21.933328 [Byte1]: 54
1045 12:38:21.937553
1046 12:38:21.937672 Set Vref, RX VrefLevel [Byte0]: 55
1047 12:38:21.940537 [Byte1]: 55
1048 12:38:21.944848
1049 12:38:21.945006 Set Vref, RX VrefLevel [Byte0]: 56
1050 12:38:21.948267 [Byte1]: 56
1051 12:38:21.952791
1052 12:38:21.953033 Set Vref, RX VrefLevel [Byte0]: 57
1053 12:38:21.955889 [Byte1]: 57
1054 12:38:21.960083
1055 12:38:21.960201 Set Vref, RX VrefLevel [Byte0]: 58
1056 12:38:21.963570 [Byte1]: 58
1057 12:38:21.967762
1058 12:38:21.967919 Set Vref, RX VrefLevel [Byte0]: 59
1059 12:38:21.971839 [Byte1]: 59
1060 12:38:21.975680
1061 12:38:21.975854 Set Vref, RX VrefLevel [Byte0]: 60
1062 12:38:21.979174 [Byte1]: 60
1063 12:38:21.982850
1064 12:38:21.982961 Set Vref, RX VrefLevel [Byte0]: 61
1065 12:38:21.986437 [Byte1]: 61
1066 12:38:21.990607
1067 12:38:21.990746 Set Vref, RX VrefLevel [Byte0]: 62
1068 12:38:21.994105 [Byte1]: 62
1069 12:38:21.998195
1070 12:38:21.998369 Set Vref, RX VrefLevel [Byte0]: 63
1071 12:38:22.001858 [Byte1]: 63
1072 12:38:22.005950
1073 12:38:22.006141 Set Vref, RX VrefLevel [Byte0]: 64
1074 12:38:22.008833 [Byte1]: 64
1075 12:38:22.014049
1076 12:38:22.014255 Set Vref, RX VrefLevel [Byte0]: 65
1077 12:38:22.016796 [Byte1]: 65
1078 12:38:22.021116
1079 12:38:22.021314 Set Vref, RX VrefLevel [Byte0]: 66
1080 12:38:22.024728 [Byte1]: 66
1081 12:38:22.028344
1082 12:38:22.028466 Set Vref, RX VrefLevel [Byte0]: 67
1083 12:38:22.031542 [Byte1]: 67
1084 12:38:22.036537
1085 12:38:22.036648 Set Vref, RX VrefLevel [Byte0]: 68
1086 12:38:22.039642 [Byte1]: 68
1087 12:38:22.043635
1088 12:38:22.043751 Set Vref, RX VrefLevel [Byte0]: 69
1089 12:38:22.046943 [Byte1]: 69
1090 12:38:22.051416
1091 12:38:22.051577 Set Vref, RX VrefLevel [Byte0]: 70
1092 12:38:22.054653 [Byte1]: 70
1093 12:38:22.059273
1094 12:38:22.059388 Set Vref, RX VrefLevel [Byte0]: 71
1095 12:38:22.062134 [Byte1]: 71
1096 12:38:22.066249
1097 12:38:22.066386 Set Vref, RX VrefLevel [Byte0]: 72
1098 12:38:22.069598 [Byte1]: 72
1099 12:38:22.074199
1100 12:38:22.074329 Set Vref, RX VrefLevel [Byte0]: 73
1101 12:38:22.077783 [Byte1]: 73
1102 12:38:22.081725
1103 12:38:22.081874 Set Vref, RX VrefLevel [Byte0]: 74
1104 12:38:22.085144 [Byte1]: 74
1105 12:38:22.088979
1106 12:38:22.089092 Set Vref, RX VrefLevel [Byte0]: 75
1107 12:38:22.092762 [Byte1]: 75
1108 12:38:22.097056
1109 12:38:22.097170 Set Vref, RX VrefLevel [Byte0]: 76
1110 12:38:22.099957 [Byte1]: 76
1111 12:38:22.105261
1112 12:38:22.105366 Set Vref, RX VrefLevel [Byte0]: 77
1113 12:38:22.108296 [Byte1]: 77
1114 12:38:22.111754
1115 12:38:22.111856 Final RX Vref Byte 0 = 61 to rank0
1116 12:38:22.115324 Final RX Vref Byte 1 = 58 to rank0
1117 12:38:22.119024 Final RX Vref Byte 0 = 61 to rank1
1118 12:38:22.122057 Final RX Vref Byte 1 = 58 to rank1==
1119 12:38:22.125661 Dram Type= 6, Freq= 0, CH_0, rank 0
1120 12:38:22.128998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1121 12:38:22.132707 ==
1122 12:38:22.132817 DQS Delay:
1123 12:38:22.132885 DQS0 = 0, DQS1 = 0
1124 12:38:22.136149 DQM Delay:
1125 12:38:22.136289 DQM0 = 87, DQM1 = 79
1126 12:38:22.138746 DQ Delay:
1127 12:38:22.138889 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1128 12:38:22.149906 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1129 12:38:22.167656 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1130 12:38:22.167836 DQ12 =80, DQ13 =80, DQ14 =92, DQ15 =88
1131 12:38:22.167945
1132 12:38:22.168040
1133 12:38:22.168332 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b12, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 398 ps
1134 12:38:22.168433 CH0 RK0: MR19=606, MR18=2B12
1135 12:38:22.168522 CH0_RK0: MR19=0x606, MR18=0x2B12, DQSOSC=398, MR23=63, INC=93, DEC=62
1136 12:38:22.168609
1137 12:38:22.182587 ----->DramcWriteLeveling(PI) begin...
1138 12:38:22.182818 ==
1139 12:38:22.183166 Dram Type= 6, Freq= 0, CH_0, rank 1
1140 12:38:22.183296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1141 12:38:22.183420 ==
1142 12:38:22.190232 Write leveling (Byte 0): 29 => 29
1143 12:38:22.190654 Write leveling (Byte 1): 29 => 29
1144 12:38:22.190790 DramcWriteLeveling(PI) end<-----
1145 12:38:22.190912
1146 12:38:22.191032 ==
1147 12:38:22.195677 Dram Type= 6, Freq= 0, CH_0, rank 1
1148 12:38:22.200699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1149 12:38:22.200878 ==
1150 12:38:22.200998 [Gating] SW mode calibration
1151 12:38:22.211270 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1152 12:38:22.211617 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1153 12:38:22.218226 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1154 12:38:22.225416 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1155 12:38:22.249149 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1156 12:38:22.249306 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 12:38:22.249567 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 12:38:22.249632 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 12:38:22.249880 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 12:38:22.250590 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 12:38:22.250670 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 12:38:22.293197 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 12:38:22.293833 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:38:22.294155 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:38:22.294271 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:38:22.294381 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:38:22.294517 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 12:38:22.294656 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:38:22.294905 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 12:38:22.295299 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1171 12:38:22.295381 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1172 12:38:22.337303 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 12:38:22.337647 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 12:38:22.337801 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 12:38:22.338157 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:38:22.338260 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:38:22.338533 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:38:22.338602 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 12:38:22.338906 0 9 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
1180 12:38:22.338993 0 9 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1181 12:38:22.339124 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 12:38:22.361293 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 12:38:22.361648 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 12:38:22.361754 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 12:38:22.361845 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 12:38:22.361932 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 0) (1 1)
1187 12:38:22.401830 0 10 8 | B1->B0 | 3232 2c2c | 0 0 | (1 1) (0 0)
1188 12:38:22.402202 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1189 12:38:22.402304 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 12:38:22.402922 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 12:38:22.403001 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 12:38:22.403286 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 12:38:22.403372 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 12:38:22.403446 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1195 12:38:22.406601 0 11 8 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
1196 12:38:22.406699 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1197 12:38:22.410216 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 12:38:22.413791 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 12:38:22.417057 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 12:38:22.423608 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 12:38:22.426871 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 12:38:22.430345 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 12:38:22.437172 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1204 12:38:22.439932 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 12:38:22.443430 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 12:38:22.447130 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 12:38:22.453617 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 12:38:22.457112 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 12:38:22.460234 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 12:38:22.466703 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 12:38:22.469987 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 12:38:22.473573 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 12:38:22.480583 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 12:38:22.483698 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 12:38:22.486825 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 12:38:22.493898 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 12:38:22.496968 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 12:38:22.501483 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1219 12:38:22.503943 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1220 12:38:22.507449 Total UI for P1: 0, mck2ui 16
1221 12:38:22.511173 best dqsien dly found for B0: ( 0, 14, 4)
1222 12:38:22.517640 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 12:38:22.517720 Total UI for P1: 0, mck2ui 16
1224 12:38:22.524185 best dqsien dly found for B1: ( 0, 14, 8)
1225 12:38:22.527427 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1226 12:38:22.531343 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1227 12:38:22.531423
1228 12:38:22.533821 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1229 12:38:22.537417 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1230 12:38:22.541166 [Gating] SW calibration Done
1231 12:38:22.541245 ==
1232 12:38:22.543949 Dram Type= 6, Freq= 0, CH_0, rank 1
1233 12:38:22.547469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1234 12:38:22.547549 ==
1235 12:38:22.550769 RX Vref Scan: 0
1236 12:38:22.550885
1237 12:38:22.550956 RX Vref 0 -> 0, step: 1
1238 12:38:22.551016
1239 12:38:22.554027 RX Delay -130 -> 252, step: 16
1240 12:38:22.557593 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1241 12:38:22.564345 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1242 12:38:22.567584 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1243 12:38:22.571055 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1244 12:38:22.574392 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1245 12:38:22.577692 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1246 12:38:22.581124 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1247 12:38:22.587676 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1248 12:38:22.591160 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1249 12:38:22.594522 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1250 12:38:22.598102 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1251 12:38:22.601482 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1252 12:38:22.607536 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1253 12:38:22.611766 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1254 12:38:22.614700 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1255 12:38:22.617999 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1256 12:38:22.618114 ==
1257 12:38:22.621465 Dram Type= 6, Freq= 0, CH_0, rank 1
1258 12:38:22.628077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1259 12:38:22.628212 ==
1260 12:38:22.628308 DQS Delay:
1261 12:38:22.628397 DQS0 = 0, DQS1 = 0
1262 12:38:22.631378 DQM Delay:
1263 12:38:22.631483 DQM0 = 84, DQM1 = 76
1264 12:38:22.635014 DQ Delay:
1265 12:38:22.638797 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1266 12:38:22.638911 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
1267 12:38:22.641764 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1268 12:38:22.644804 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1269 12:38:22.648791
1270 12:38:22.648909
1271 12:38:22.649004 ==
1272 12:38:22.651914 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 12:38:22.654988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1274 12:38:22.655073 ==
1275 12:38:22.655140
1276 12:38:22.655201
1277 12:38:22.657842 TX Vref Scan disable
1278 12:38:22.657949 == TX Byte 0 ==
1279 12:38:22.664982 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1280 12:38:22.668243 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1281 12:38:22.668322 == TX Byte 1 ==
1282 12:38:22.674913 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1283 12:38:22.678518 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1284 12:38:22.678598 ==
1285 12:38:22.682031 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 12:38:22.684849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 12:38:22.684934 ==
1288 12:38:22.698180 TX Vref=22, minBit 2, minWin=27, winSum=441
1289 12:38:22.701554 TX Vref=24, minBit 2, minWin=27, winSum=444
1290 12:38:22.705294 TX Vref=26, minBit 6, minWin=27, winSum=450
1291 12:38:22.708427 TX Vref=28, minBit 0, minWin=28, winSum=454
1292 12:38:22.711445 TX Vref=30, minBit 7, minWin=27, winSum=454
1293 12:38:22.715097 TX Vref=32, minBit 0, minWin=28, winSum=454
1294 12:38:22.721643 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 28
1295 12:38:22.721730
1296 12:38:22.724873 Final TX Range 1 Vref 28
1297 12:38:22.724980
1298 12:38:22.725072 ==
1299 12:38:22.728605 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 12:38:22.731736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 12:38:22.731811 ==
1302 12:38:22.731874
1303 12:38:22.731932
1304 12:38:22.734934 TX Vref Scan disable
1305 12:38:22.738778 == TX Byte 0 ==
1306 12:38:22.742020 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1307 12:38:22.745689 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1308 12:38:22.749014 == TX Byte 1 ==
1309 12:38:22.751751 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1310 12:38:22.755241 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1311 12:38:22.755348
1312 12:38:22.758638 [DATLAT]
1313 12:38:22.758720 Freq=800, CH0 RK1
1314 12:38:22.758784
1315 12:38:22.762153 DATLAT Default: 0xa
1316 12:38:22.762223 0, 0xFFFF, sum = 0
1317 12:38:22.765466 1, 0xFFFF, sum = 0
1318 12:38:22.765568 2, 0xFFFF, sum = 0
1319 12:38:22.769148 3, 0xFFFF, sum = 0
1320 12:38:22.769252 4, 0xFFFF, sum = 0
1321 12:38:22.772406 5, 0xFFFF, sum = 0
1322 12:38:22.772505 6, 0xFFFF, sum = 0
1323 12:38:22.775172 7, 0xFFFF, sum = 0
1324 12:38:22.775244 8, 0xFFFF, sum = 0
1325 12:38:22.778938 9, 0x0, sum = 1
1326 12:38:22.779015 10, 0x0, sum = 2
1327 12:38:22.782078 11, 0x0, sum = 3
1328 12:38:22.782177 12, 0x0, sum = 4
1329 12:38:22.785502 best_step = 10
1330 12:38:22.785574
1331 12:38:22.785634 ==
1332 12:38:22.788671 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 12:38:22.792107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 12:38:22.792213 ==
1335 12:38:22.792302 RX Vref Scan: 0
1336 12:38:22.795247
1337 12:38:22.795327 RX Vref 0 -> 0, step: 1
1338 12:38:22.795391
1339 12:38:22.798567 RX Delay -95 -> 252, step: 8
1340 12:38:22.805369 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1341 12:38:22.809351 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1342 12:38:22.812468 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1343 12:38:22.815679 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1344 12:38:22.818572 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1345 12:38:22.822075 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1346 12:38:22.829109 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1347 12:38:22.831962 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1348 12:38:22.835318 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1349 12:38:22.838943 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1350 12:38:22.842075 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1351 12:38:22.848873 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1352 12:38:22.851776 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1353 12:38:22.855616 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1354 12:38:22.858584 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1355 12:38:22.862161 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1356 12:38:22.865399 ==
1357 12:38:22.865500 Dram Type= 6, Freq= 0, CH_0, rank 1
1358 12:38:22.872306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1359 12:38:22.872391 ==
1360 12:38:22.872455 DQS Delay:
1361 12:38:22.875452 DQS0 = 0, DQS1 = 0
1362 12:38:22.875531 DQM Delay:
1363 12:38:22.879246 DQM0 = 87, DQM1 = 78
1364 12:38:22.879327 DQ Delay:
1365 12:38:22.882692 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1366 12:38:22.885629 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1367 12:38:22.889230 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1368 12:38:22.892365 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1369 12:38:22.892445
1370 12:38:22.892508
1371 12:38:22.899274 [DQSOSCAuto] RK1, (LSB)MR18= 0x331d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
1372 12:38:22.902646 CH0 RK1: MR19=606, MR18=331D
1373 12:38:22.909216 CH0_RK1: MR19=0x606, MR18=0x331D, DQSOSC=396, MR23=63, INC=94, DEC=62
1374 12:38:22.912500 [RxdqsGatingPostProcess] freq 800
1375 12:38:22.915722 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1376 12:38:22.919331 Pre-setting of DQS Precalculation
1377 12:38:22.926069 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1378 12:38:22.926156 ==
1379 12:38:22.929211 Dram Type= 6, Freq= 0, CH_1, rank 0
1380 12:38:22.932993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1381 12:38:22.933075 ==
1382 12:38:22.939716 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1383 12:38:22.942678 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1384 12:38:22.953261 [CA 0] Center 36 (6~67) winsize 62
1385 12:38:22.956549 [CA 1] Center 36 (6~67) winsize 62
1386 12:38:22.959801 [CA 2] Center 34 (4~64) winsize 61
1387 12:38:22.963406 [CA 3] Center 33 (3~64) winsize 62
1388 12:38:22.966202 [CA 4] Center 34 (3~65) winsize 63
1389 12:38:22.970209 [CA 5] Center 33 (3~64) winsize 62
1390 12:38:22.970290
1391 12:38:22.972951 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1392 12:38:22.973032
1393 12:38:22.976234 [CATrainingPosCal] consider 1 rank data
1394 12:38:22.980720 u2DelayCellTimex100 = 270/100 ps
1395 12:38:22.983724 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1396 12:38:22.987411 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1397 12:38:22.991235 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1398 12:38:22.994961 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1399 12:38:22.999037 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1400 12:38:23.002266 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1401 12:38:23.002350
1402 12:38:23.006180 CA PerBit enable=1, Macro0, CA PI delay=33
1403 12:38:23.006263
1404 12:38:23.010054 [CBTSetCACLKResult] CA Dly = 33
1405 12:38:23.010137 CS Dly: 4 (0~35)
1406 12:38:23.010215 ==
1407 12:38:23.013766 Dram Type= 6, Freq= 0, CH_1, rank 1
1408 12:38:23.017496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1409 12:38:23.017641 ==
1410 12:38:23.023942 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1411 12:38:23.031134 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1412 12:38:23.038835 [CA 0] Center 36 (5~67) winsize 63
1413 12:38:23.042553 [CA 1] Center 36 (5~67) winsize 63
1414 12:38:23.046005 [CA 2] Center 34 (4~64) winsize 61
1415 12:38:23.049437 [CA 3] Center 33 (3~64) winsize 62
1416 12:38:23.052600 [CA 4] Center 34 (3~65) winsize 63
1417 12:38:23.055891 [CA 5] Center 33 (3~64) winsize 62
1418 12:38:23.055971
1419 12:38:23.059509 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1420 12:38:23.059621
1421 12:38:23.063099 [CATrainingPosCal] consider 2 rank data
1422 12:38:23.065886 u2DelayCellTimex100 = 270/100 ps
1423 12:38:23.069283 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1424 12:38:23.073269 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1425 12:38:23.075678 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1426 12:38:23.082560 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1427 12:38:23.086146 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1428 12:38:23.089021 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1429 12:38:23.089100
1430 12:38:23.092962 CA PerBit enable=1, Macro0, CA PI delay=33
1431 12:38:23.093043
1432 12:38:23.095978 [CBTSetCACLKResult] CA Dly = 33
1433 12:38:23.096059 CS Dly: 5 (0~37)
1434 12:38:23.096123
1435 12:38:23.099868 ----->DramcWriteLeveling(PI) begin...
1436 12:38:23.099963 ==
1437 12:38:23.103489 Dram Type= 6, Freq= 0, CH_1, rank 0
1438 12:38:23.109610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 12:38:23.109692 ==
1440 12:38:23.113031 Write leveling (Byte 0): 27 => 27
1441 12:38:23.116342 Write leveling (Byte 1): 29 => 29
1442 12:38:23.116451 DramcWriteLeveling(PI) end<-----
1443 12:38:23.116516
1444 12:38:23.120097 ==
1445 12:38:23.120178 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 12:38:23.126441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 12:38:23.126585 ==
1448 12:38:23.129530 [Gating] SW mode calibration
1449 12:38:23.137049 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1450 12:38:23.139609 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1451 12:38:23.143621 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1452 12:38:23.149932 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1453 12:38:23.153422 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1454 12:38:23.156864 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 12:38:23.163189 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 12:38:23.167112 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 12:38:23.169910 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 12:38:23.177069 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:38:23.180878 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 12:38:23.183951 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 12:38:23.190155 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:38:23.194163 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:38:23.197158 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:38:23.204071 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 12:38:23.206935 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:38:23.210799 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 12:38:23.213653 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 12:38:23.220211 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 12:38:23.223567 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1470 12:38:23.227221 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 12:38:23.233989 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 12:38:23.236982 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:38:23.240114 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:38:23.246777 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:38:23.250738 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 12:38:23.253889 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 12:38:23.260230 0 9 8 | B1->B0 | 2727 3030 | 0 0 | (1 1) (0 0)
1478 12:38:23.263653 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 12:38:23.267256 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 12:38:23.273708 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 12:38:23.277040 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 12:38:23.280769 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 12:38:23.283633 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 12:38:23.291308 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (1 0) (1 0)
1485 12:38:23.293836 0 10 8 | B1->B0 | 2626 2c2c | 0 0 | (1 0) (0 0)
1486 12:38:23.297650 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 12:38:23.303795 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 12:38:23.307035 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 12:38:23.310750 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 12:38:23.317596 0 10 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1491 12:38:23.320941 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 12:38:23.324684 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 12:38:23.331235 0 11 8 | B1->B0 | 3636 3838 | 0 0 | (1 1) (0 0)
1494 12:38:23.334754 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 12:38:23.338521 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 12:38:23.344044 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 12:38:23.348024 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 12:38:23.350811 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 12:38:23.354240 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 12:38:23.361106 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1501 12:38:23.364724 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1502 12:38:23.367595 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 12:38:23.374193 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 12:38:23.377651 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 12:38:23.381009 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 12:38:23.387654 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 12:38:23.391428 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 12:38:23.394569 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 12:38:23.401446 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 12:38:23.404935 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 12:38:23.408370 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 12:38:23.411491 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 12:38:23.418027 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 12:38:23.421707 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 12:38:23.424786 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 12:38:23.431599 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 12:38:23.434987 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1518 12:38:23.438575 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 12:38:23.441790 Total UI for P1: 0, mck2ui 16
1520 12:38:23.445069 best dqsien dly found for B0: ( 0, 14, 8)
1521 12:38:23.448520 Total UI for P1: 0, mck2ui 16
1522 12:38:23.451867 best dqsien dly found for B1: ( 0, 14, 8)
1523 12:38:23.454804 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1524 12:38:23.458260 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1525 12:38:23.458341
1526 12:38:23.461472 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1527 12:38:23.469033 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1528 12:38:23.469117 [Gating] SW calibration Done
1529 12:38:23.469182 ==
1530 12:38:23.472031 Dram Type= 6, Freq= 0, CH_1, rank 0
1531 12:38:23.478564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1532 12:38:23.478653 ==
1533 12:38:23.478719 RX Vref Scan: 0
1534 12:38:23.478781
1535 12:38:23.481678 RX Vref 0 -> 0, step: 1
1536 12:38:23.481758
1537 12:38:23.485339 RX Delay -130 -> 252, step: 16
1538 12:38:23.488894 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1539 12:38:23.491889 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1540 12:38:23.495085 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1541 12:38:23.498686 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1542 12:38:23.505542 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1543 12:38:23.508459 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1544 12:38:23.512234 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1545 12:38:23.515386 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1546 12:38:23.518533 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1547 12:38:23.525724 iDelay=206, Bit 9, Center 61 (-66 ~ 189) 256
1548 12:38:23.528686 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1549 12:38:23.532181 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1550 12:38:23.535601 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1551 12:38:23.539366 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1552 12:38:23.545469 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1553 12:38:23.548809 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1554 12:38:23.548895 ==
1555 12:38:23.552202 Dram Type= 6, Freq= 0, CH_1, rank 0
1556 12:38:23.555751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1557 12:38:23.555835 ==
1558 12:38:23.555899 DQS Delay:
1559 12:38:23.559134 DQS0 = 0, DQS1 = 0
1560 12:38:23.559216 DQM Delay:
1561 12:38:23.562316 DQM0 = 80, DQM1 = 75
1562 12:38:23.562416 DQ Delay:
1563 12:38:23.566062 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1564 12:38:23.569710 DQ4 =85, DQ5 =85, DQ6 =93, DQ7 =69
1565 12:38:23.573544 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1566 12:38:23.576991 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1567 12:38:23.577102
1568 12:38:23.577168
1569 12:38:23.577229 ==
1570 12:38:23.579916 Dram Type= 6, Freq= 0, CH_1, rank 0
1571 12:38:23.583087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1572 12:38:23.583172 ==
1573 12:38:23.583237
1574 12:38:23.583296
1575 12:38:23.586385 TX Vref Scan disable
1576 12:38:23.589866 == TX Byte 0 ==
1577 12:38:23.593710 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1578 12:38:23.596706 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1579 12:38:23.599701 == TX Byte 1 ==
1580 12:38:23.603206 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1581 12:38:23.606601 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1582 12:38:23.606686 ==
1583 12:38:23.610147 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 12:38:23.613372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 12:38:23.613458 ==
1586 12:38:23.627466 TX Vref=22, minBit 0, minWin=27, winSum=437
1587 12:38:23.631279 TX Vref=24, minBit 0, minWin=27, winSum=442
1588 12:38:23.635073 TX Vref=26, minBit 4, minWin=27, winSum=445
1589 12:38:23.637960 TX Vref=28, minBit 13, minWin=27, winSum=450
1590 12:38:23.642271 TX Vref=30, minBit 0, minWin=28, winSum=453
1591 12:38:23.644580 TX Vref=32, minBit 1, minWin=28, winSum=452
1592 12:38:23.651155 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 30
1593 12:38:23.651244
1594 12:38:23.655005 Final TX Range 1 Vref 30
1595 12:38:23.655089
1596 12:38:23.655153 ==
1597 12:38:23.658306 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 12:38:23.661457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 12:38:23.661544 ==
1600 12:38:23.661620
1601 12:38:23.661682
1602 12:38:23.665263 TX Vref Scan disable
1603 12:38:23.668046 == TX Byte 0 ==
1604 12:38:23.671278 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1605 12:38:23.674836 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1606 12:38:23.678061 == TX Byte 1 ==
1607 12:38:23.681298 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1608 12:38:23.684621 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1609 12:38:23.684703
1610 12:38:23.688515 [DATLAT]
1611 12:38:23.688597 Freq=800, CH1 RK0
1612 12:38:23.688663
1613 12:38:23.691688 DATLAT Default: 0xa
1614 12:38:23.691771 0, 0xFFFF, sum = 0
1615 12:38:23.694892 1, 0xFFFF, sum = 0
1616 12:38:23.694977 2, 0xFFFF, sum = 0
1617 12:38:23.698941 3, 0xFFFF, sum = 0
1618 12:38:23.699027 4, 0xFFFF, sum = 0
1619 12:38:23.702724 5, 0xFFFF, sum = 0
1620 12:38:23.702811 6, 0xFFFF, sum = 0
1621 12:38:23.704942 7, 0xFFFF, sum = 0
1622 12:38:23.705027 8, 0xFFFF, sum = 0
1623 12:38:23.708656 9, 0x0, sum = 1
1624 12:38:23.708768 10, 0x0, sum = 2
1625 12:38:23.711563 11, 0x0, sum = 3
1626 12:38:23.711699 12, 0x0, sum = 4
1627 12:38:23.715073 best_step = 10
1628 12:38:23.715158
1629 12:38:23.715236 ==
1630 12:38:23.719028 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 12:38:23.721902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 12:38:23.722016 ==
1633 12:38:23.722110 RX Vref Scan: 1
1634 12:38:23.725154
1635 12:38:23.725263 Set Vref Range= 32 -> 127
1636 12:38:23.725358
1637 12:38:23.728374 RX Vref 32 -> 127, step: 1
1638 12:38:23.728482
1639 12:38:23.731817 RX Delay -111 -> 252, step: 8
1640 12:38:23.731923
1641 12:38:23.735277 Set Vref, RX VrefLevel [Byte0]: 32
1642 12:38:23.738471 [Byte1]: 32
1643 12:38:23.738584
1644 12:38:23.741915 Set Vref, RX VrefLevel [Byte0]: 33
1645 12:38:23.745206 [Byte1]: 33
1646 12:38:23.745316
1647 12:38:23.748678 Set Vref, RX VrefLevel [Byte0]: 34
1648 12:38:23.751809 [Byte1]: 34
1649 12:38:23.756033
1650 12:38:23.756117 Set Vref, RX VrefLevel [Byte0]: 35
1651 12:38:23.759006 [Byte1]: 35
1652 12:38:23.763588
1653 12:38:23.763675 Set Vref, RX VrefLevel [Byte0]: 36
1654 12:38:23.767200 [Byte1]: 36
1655 12:38:23.771201
1656 12:38:23.771294 Set Vref, RX VrefLevel [Byte0]: 37
1657 12:38:23.774962 [Byte1]: 37
1658 12:38:23.778724
1659 12:38:23.778839 Set Vref, RX VrefLevel [Byte0]: 38
1660 12:38:23.782097 [Byte1]: 38
1661 12:38:23.787003
1662 12:38:23.787098 Set Vref, RX VrefLevel [Byte0]: 39
1663 12:38:23.789572 [Byte1]: 39
1664 12:38:23.793953
1665 12:38:23.794036 Set Vref, RX VrefLevel [Byte0]: 40
1666 12:38:23.797535 [Byte1]: 40
1667 12:38:23.801628
1668 12:38:23.801713 Set Vref, RX VrefLevel [Byte0]: 41
1669 12:38:23.805218 [Byte1]: 41
1670 12:38:23.809486
1671 12:38:23.809570 Set Vref, RX VrefLevel [Byte0]: 42
1672 12:38:23.812622 [Byte1]: 42
1673 12:38:23.817102
1674 12:38:23.817185 Set Vref, RX VrefLevel [Byte0]: 43
1675 12:38:23.821056 [Byte1]: 43
1676 12:38:23.824856
1677 12:38:23.824940 Set Vref, RX VrefLevel [Byte0]: 44
1678 12:38:23.828734 [Byte1]: 44
1679 12:38:23.832700
1680 12:38:23.832785 Set Vref, RX VrefLevel [Byte0]: 45
1681 12:38:23.836115 [Byte1]: 45
1682 12:38:23.840289
1683 12:38:23.840375 Set Vref, RX VrefLevel [Byte0]: 46
1684 12:38:23.843260 [Byte1]: 46
1685 12:38:23.847862
1686 12:38:23.847947 Set Vref, RX VrefLevel [Byte0]: 47
1687 12:38:23.851139 [Byte1]: 47
1688 12:38:23.855031
1689 12:38:23.855115 Set Vref, RX VrefLevel [Byte0]: 48
1690 12:38:23.858592 [Byte1]: 48
1691 12:38:23.863486
1692 12:38:23.863592 Set Vref, RX VrefLevel [Byte0]: 49
1693 12:38:23.866282 [Byte1]: 49
1694 12:38:23.870875
1695 12:38:23.870960 Set Vref, RX VrefLevel [Byte0]: 50
1696 12:38:23.873834 [Byte1]: 50
1697 12:38:23.878296
1698 12:38:23.878381 Set Vref, RX VrefLevel [Byte0]: 51
1699 12:38:23.881763 [Byte1]: 51
1700 12:38:23.885547
1701 12:38:23.885631 Set Vref, RX VrefLevel [Byte0]: 52
1702 12:38:23.889248 [Byte1]: 52
1703 12:38:23.893330
1704 12:38:23.893402 Set Vref, RX VrefLevel [Byte0]: 53
1705 12:38:23.896723 [Byte1]: 53
1706 12:38:23.901467
1707 12:38:23.901546 Set Vref, RX VrefLevel [Byte0]: 54
1708 12:38:23.904899 [Byte1]: 54
1709 12:38:23.909300
1710 12:38:23.909386 Set Vref, RX VrefLevel [Byte0]: 55
1711 12:38:23.911924 [Byte1]: 55
1712 12:38:23.916899
1713 12:38:23.916976 Set Vref, RX VrefLevel [Byte0]: 56
1714 12:38:23.920437 [Byte1]: 56
1715 12:38:23.924099
1716 12:38:23.924174 Set Vref, RX VrefLevel [Byte0]: 57
1717 12:38:23.927603 [Byte1]: 57
1718 12:38:23.932082
1719 12:38:23.932157 Set Vref, RX VrefLevel [Byte0]: 58
1720 12:38:23.934975 [Byte1]: 58
1721 12:38:23.939444
1722 12:38:23.939527 Set Vref, RX VrefLevel [Byte0]: 59
1723 12:38:23.943112 [Byte1]: 59
1724 12:38:23.947088
1725 12:38:23.947172 Set Vref, RX VrefLevel [Byte0]: 60
1726 12:38:23.950738 [Byte1]: 60
1727 12:38:23.954432
1728 12:38:23.954515 Set Vref, RX VrefLevel [Byte0]: 61
1729 12:38:23.958017 [Byte1]: 61
1730 12:38:23.962447
1731 12:38:23.962530 Set Vref, RX VrefLevel [Byte0]: 62
1732 12:38:23.965905 [Byte1]: 62
1733 12:38:23.970762
1734 12:38:23.970843 Set Vref, RX VrefLevel [Byte0]: 63
1735 12:38:23.973160 [Byte1]: 63
1736 12:38:23.977621
1737 12:38:23.977703 Set Vref, RX VrefLevel [Byte0]: 64
1738 12:38:23.981531 [Byte1]: 64
1739 12:38:23.985214
1740 12:38:23.985299 Set Vref, RX VrefLevel [Byte0]: 65
1741 12:38:23.989066 [Byte1]: 65
1742 12:38:23.993347
1743 12:38:23.993428 Set Vref, RX VrefLevel [Byte0]: 66
1744 12:38:23.996139 [Byte1]: 66
1745 12:38:24.000604
1746 12:38:24.000686 Set Vref, RX VrefLevel [Byte0]: 67
1747 12:38:24.003870 [Byte1]: 67
1748 12:38:24.008798
1749 12:38:24.008879 Set Vref, RX VrefLevel [Byte0]: 68
1750 12:38:24.011834 [Byte1]: 68
1751 12:38:24.015990
1752 12:38:24.016071 Set Vref, RX VrefLevel [Byte0]: 69
1753 12:38:24.019364 [Byte1]: 69
1754 12:38:24.023709
1755 12:38:24.023789 Set Vref, RX VrefLevel [Byte0]: 70
1756 12:38:24.027164 [Byte1]: 70
1757 12:38:24.030939
1758 12:38:24.031018 Set Vref, RX VrefLevel [Byte0]: 71
1759 12:38:24.034440 [Byte1]: 71
1760 12:38:24.038554
1761 12:38:24.038661 Set Vref, RX VrefLevel [Byte0]: 72
1762 12:38:24.042532 [Byte1]: 72
1763 12:38:24.046582
1764 12:38:24.046663 Set Vref, RX VrefLevel [Byte0]: 73
1765 12:38:24.049680 [Byte1]: 73
1766 12:38:24.053912
1767 12:38:24.053992 Set Vref, RX VrefLevel [Byte0]: 74
1768 12:38:24.057375 [Byte1]: 74
1769 12:38:24.061705
1770 12:38:24.061785 Set Vref, RX VrefLevel [Byte0]: 75
1771 12:38:24.065168 [Byte1]: 75
1772 12:38:24.069360
1773 12:38:24.069440 Set Vref, RX VrefLevel [Byte0]: 76
1774 12:38:24.072733 [Byte1]: 76
1775 12:38:24.077046
1776 12:38:24.077126 Set Vref, RX VrefLevel [Byte0]: 77
1777 12:38:24.080564 [Byte1]: 77
1778 12:38:24.085075
1779 12:38:24.085155 Final RX Vref Byte 0 = 59 to rank0
1780 12:38:24.088043 Final RX Vref Byte 1 = 58 to rank0
1781 12:38:24.091600 Final RX Vref Byte 0 = 59 to rank1
1782 12:38:24.095161 Final RX Vref Byte 1 = 58 to rank1==
1783 12:38:24.098531 Dram Type= 6, Freq= 0, CH_1, rank 0
1784 12:38:24.101737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1785 12:38:24.104733 ==
1786 12:38:24.104855 DQS Delay:
1787 12:38:24.104919 DQS0 = 0, DQS1 = 0
1788 12:38:24.107998 DQM Delay:
1789 12:38:24.108078 DQM0 = 83, DQM1 = 74
1790 12:38:24.111414 DQ Delay:
1791 12:38:24.111494 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =84
1792 12:38:24.114877 DQ4 =84, DQ5 =92, DQ6 =96, DQ7 =80
1793 12:38:24.118129 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1794 12:38:24.121399 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =76
1795 12:38:24.121505
1796 12:38:24.125128
1797 12:38:24.131639 [DQSOSCAuto] RK0, (LSB)MR18= 0x27fc, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
1798 12:38:24.134788 CH1 RK0: MR19=605, MR18=27FC
1799 12:38:24.142132 CH1_RK0: MR19=0x605, MR18=0x27FC, DQSOSC=400, MR23=63, INC=92, DEC=61
1800 12:38:24.142218
1801 12:38:24.145511 ----->DramcWriteLeveling(PI) begin...
1802 12:38:24.145596 ==
1803 12:38:24.148668 Dram Type= 6, Freq= 0, CH_1, rank 1
1804 12:38:24.151917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1805 12:38:24.152001 ==
1806 12:38:24.155081 Write leveling (Byte 0): 29 => 29
1807 12:38:24.158170 Write leveling (Byte 1): 28 => 28
1808 12:38:24.161840 DramcWriteLeveling(PI) end<-----
1809 12:38:24.161923
1810 12:38:24.162007 ==
1811 12:38:24.165193 Dram Type= 6, Freq= 0, CH_1, rank 1
1812 12:38:24.168599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1813 12:38:24.168683 ==
1814 12:38:24.171537 [Gating] SW mode calibration
1815 12:38:24.178441 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1816 12:38:24.185214 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1817 12:38:24.188349 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1818 12:38:24.192135 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1819 12:38:24.194981 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 12:38:24.202067 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 12:38:24.205427 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 12:38:24.208389 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 12:38:24.215325 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 12:38:24.218623 0 6 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1825 12:38:24.222300 0 7 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1826 12:38:24.228882 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 12:38:24.232272 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 12:38:24.235915 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 12:38:24.242297 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 12:38:24.246269 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 12:38:24.249244 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1832 12:38:24.252415 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 12:38:24.259338 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1834 12:38:24.262199 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1835 12:38:24.265495 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1836 12:38:24.272419 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 12:38:24.276326 0 8 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1838 12:38:24.279254 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 12:38:24.285684 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 12:38:24.289021 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 12:38:24.292860 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 12:38:24.298803 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 12:38:24.302116 0 9 8 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
1844 12:38:24.306218 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 12:38:24.312895 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 12:38:24.316182 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 12:38:24.319121 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 12:38:24.325889 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 12:38:24.329186 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 12:38:24.332921 0 10 4 | B1->B0 | 2f2f 2e2e | 0 0 | (1 0) (0 0)
1851 12:38:24.336184 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1852 12:38:24.342386 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 12:38:24.346228 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 12:38:24.349760 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 12:38:24.355790 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 12:38:24.359046 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 12:38:24.362668 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 12:38:24.369325 0 11 4 | B1->B0 | 2929 3535 | 0 0 | (0 0) (0 0)
1859 12:38:24.372964 0 11 8 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1860 12:38:24.376023 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 12:38:24.382558 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 12:38:24.386391 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 12:38:24.389566 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 12:38:24.395996 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 12:38:24.399537 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 12:38:24.402604 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1867 12:38:24.406520 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 12:38:24.412451 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 12:38:24.416781 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 12:38:24.419587 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 12:38:24.426417 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 12:38:24.429557 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 12:38:24.433169 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 12:38:24.439357 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 12:38:24.442577 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 12:38:24.446411 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 12:38:24.452772 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 12:38:24.456369 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 12:38:24.460140 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 12:38:24.466118 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 12:38:24.469578 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 12:38:24.472921 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1883 12:38:24.479850 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1884 12:38:24.479948 Total UI for P1: 0, mck2ui 16
1885 12:38:24.483374 best dqsien dly found for B0: ( 0, 14, 4)
1886 12:38:24.486541 Total UI for P1: 0, mck2ui 16
1887 12:38:24.490068 best dqsien dly found for B1: ( 0, 14, 6)
1888 12:38:24.493223 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1889 12:38:24.496499 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1890 12:38:24.499632
1891 12:38:24.503454 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1892 12:38:24.506933 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1893 12:38:24.510132 [Gating] SW calibration Done
1894 12:38:24.510214 ==
1895 12:38:24.513312 Dram Type= 6, Freq= 0, CH_1, rank 1
1896 12:38:24.516481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1897 12:38:24.516555 ==
1898 12:38:24.516617 RX Vref Scan: 0
1899 12:38:24.516677
1900 12:38:24.519746 RX Vref 0 -> 0, step: 1
1901 12:38:24.519820
1902 12:38:24.523139 RX Delay -130 -> 252, step: 16
1903 12:38:24.526588 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1904 12:38:24.529849 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1905 12:38:24.533670 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1906 12:38:24.540353 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1907 12:38:24.543685 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1908 12:38:24.546524 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1909 12:38:24.549906 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1910 12:38:24.553763 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1911 12:38:24.560055 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1912 12:38:24.563678 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1913 12:38:24.566720 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1914 12:38:24.570416 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1915 12:38:24.574125 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1916 12:38:24.580509 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1917 12:38:24.584260 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1918 12:38:24.586796 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1919 12:38:24.586873 ==
1920 12:38:24.590364 Dram Type= 6, Freq= 0, CH_1, rank 1
1921 12:38:24.593776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1922 12:38:24.593882 ==
1923 12:38:24.597050 DQS Delay:
1924 12:38:24.597166 DQS0 = 0, DQS1 = 0
1925 12:38:24.597260 DQM Delay:
1926 12:38:24.600375 DQM0 = 79, DQM1 = 77
1927 12:38:24.600490 DQ Delay:
1928 12:38:24.604092 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1929 12:38:24.606976 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =69
1930 12:38:24.610485 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1931 12:38:24.614067 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1932 12:38:24.614139
1933 12:38:24.614200
1934 12:38:24.614268 ==
1935 12:38:24.617478 Dram Type= 6, Freq= 0, CH_1, rank 1
1936 12:38:24.623784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1937 12:38:24.623878 ==
1938 12:38:24.623944
1939 12:38:24.624005
1940 12:38:24.624063 TX Vref Scan disable
1941 12:38:24.627372 == TX Byte 0 ==
1942 12:38:24.631068 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1943 12:38:24.634073 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1944 12:38:24.638355 == TX Byte 1 ==
1945 12:38:24.640804 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1946 12:38:24.644556 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1947 12:38:24.647319 ==
1948 12:38:24.651227 Dram Type= 6, Freq= 0, CH_1, rank 1
1949 12:38:24.654431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1950 12:38:24.654520 ==
1951 12:38:24.666604 TX Vref=22, minBit 7, minWin=26, winSum=441
1952 12:38:24.669907 TX Vref=24, minBit 0, minWin=27, winSum=444
1953 12:38:24.673815 TX Vref=26, minBit 11, minWin=27, winSum=448
1954 12:38:24.676772 TX Vref=28, minBit 2, minWin=28, winSum=453
1955 12:38:24.679752 TX Vref=30, minBit 1, minWin=28, winSum=451
1956 12:38:24.683183 TX Vref=32, minBit 13, minWin=27, winSum=453
1957 12:38:24.689891 [TxChooseVref] Worse bit 2, Min win 28, Win sum 453, Final Vref 28
1958 12:38:24.690023
1959 12:38:24.693314 Final TX Range 1 Vref 28
1960 12:38:24.693394
1961 12:38:24.693456 ==
1962 12:38:24.696994 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 12:38:24.699977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 12:38:24.700063 ==
1965 12:38:24.700128
1966 12:38:24.703023
1967 12:38:24.703126 TX Vref Scan disable
1968 12:38:24.707042 == TX Byte 0 ==
1969 12:38:24.710480 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1970 12:38:24.713377 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1971 12:38:24.716826 == TX Byte 1 ==
1972 12:38:24.720089 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1973 12:38:24.723204 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1974 12:38:24.723331
1975 12:38:24.726632 [DATLAT]
1976 12:38:24.726756 Freq=800, CH1 RK1
1977 12:38:24.726869
1978 12:38:24.730269 DATLAT Default: 0xa
1979 12:38:24.730383 0, 0xFFFF, sum = 0
1980 12:38:24.733557 1, 0xFFFF, sum = 0
1981 12:38:24.733658 2, 0xFFFF, sum = 0
1982 12:38:24.736650 3, 0xFFFF, sum = 0
1983 12:38:24.736739 4, 0xFFFF, sum = 0
1984 12:38:24.740617 5, 0xFFFF, sum = 0
1985 12:38:24.740694 6, 0xFFFF, sum = 0
1986 12:38:24.743986 7, 0xFFFF, sum = 0
1987 12:38:24.744068 8, 0xFFFF, sum = 0
1988 12:38:24.746892 9, 0x0, sum = 1
1989 12:38:24.746974 10, 0x0, sum = 2
1990 12:38:24.750211 11, 0x0, sum = 3
1991 12:38:24.750309 12, 0x0, sum = 4
1992 12:38:24.753609 best_step = 10
1993 12:38:24.753707
1994 12:38:24.753772 ==
1995 12:38:24.756854 Dram Type= 6, Freq= 0, CH_1, rank 1
1996 12:38:24.760448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1997 12:38:24.760556 ==
1998 12:38:24.763651 RX Vref Scan: 0
1999 12:38:24.763744
2000 12:38:24.763807 RX Vref 0 -> 0, step: 1
2001 12:38:24.763866
2002 12:38:24.767138 RX Delay -95 -> 252, step: 8
2003 12:38:24.774216 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2004 12:38:24.777328 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2005 12:38:24.780171 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2006 12:38:24.783731 iDelay=209, Bit 3, Center 80 (-39 ~ 200) 240
2007 12:38:24.787424 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2008 12:38:24.790195 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2009 12:38:24.797710 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2010 12:38:24.800737 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2011 12:38:24.803869 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2012 12:38:24.807357 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2013 12:38:24.810545 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2014 12:38:24.817461 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2015 12:38:24.820764 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2016 12:38:24.824032 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2017 12:38:24.827460 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2018 12:38:24.830886 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2019 12:38:24.830974 ==
2020 12:38:24.834036 Dram Type= 6, Freq= 0, CH_1, rank 1
2021 12:38:24.840860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2022 12:38:24.840951 ==
2023 12:38:24.841018 DQS Delay:
2024 12:38:24.844110 DQS0 = 0, DQS1 = 0
2025 12:38:24.844194 DQM Delay:
2026 12:38:24.844259 DQM0 = 80, DQM1 = 75
2027 12:38:24.847336 DQ Delay:
2028 12:38:24.850857 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =80
2029 12:38:24.854194 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
2030 12:38:24.857708 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2031 12:38:24.860986 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2032 12:38:24.861069
2033 12:38:24.861134
2034 12:38:24.867773 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d29, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
2035 12:38:24.870905 CH1 RK1: MR19=606, MR18=1D29
2036 12:38:24.877702 CH1_RK1: MR19=0x606, MR18=0x1D29, DQSOSC=399, MR23=63, INC=92, DEC=61
2037 12:38:24.881369 [RxdqsGatingPostProcess] freq 800
2038 12:38:24.884778 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2039 12:38:24.887750 Pre-setting of DQS Precalculation
2040 12:38:24.894348 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2041 12:38:24.901973 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2042 12:38:24.908390 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2043 12:38:24.908486
2044 12:38:24.908551
2045 12:38:24.911829 [Calibration Summary] 1600 Mbps
2046 12:38:24.911912 CH 0, Rank 0
2047 12:38:24.914939 SW Impedance : PASS
2048 12:38:24.915023 DUTY Scan : NO K
2049 12:38:24.918043 ZQ Calibration : PASS
2050 12:38:24.921710 Jitter Meter : NO K
2051 12:38:24.921796 CBT Training : PASS
2052 12:38:24.924588 Write leveling : PASS
2053 12:38:24.927975 RX DQS gating : PASS
2054 12:38:24.928051 RX DQ/DQS(RDDQC) : PASS
2055 12:38:24.931612 TX DQ/DQS : PASS
2056 12:38:24.934918 RX DATLAT : PASS
2057 12:38:24.934995 RX DQ/DQS(Engine): PASS
2058 12:38:24.938301 TX OE : NO K
2059 12:38:24.938425 All Pass.
2060 12:38:24.938506
2061 12:38:24.942021 CH 0, Rank 1
2062 12:38:24.942093 SW Impedance : PASS
2063 12:38:24.945094 DUTY Scan : NO K
2064 12:38:24.948464 ZQ Calibration : PASS
2065 12:38:24.948535 Jitter Meter : NO K
2066 12:38:24.951660 CBT Training : PASS
2067 12:38:24.951729 Write leveling : PASS
2068 12:38:24.955129 RX DQS gating : PASS
2069 12:38:24.958307 RX DQ/DQS(RDDQC) : PASS
2070 12:38:24.958429 TX DQ/DQS : PASS
2071 12:38:24.961588 RX DATLAT : PASS
2072 12:38:24.965095 RX DQ/DQS(Engine): PASS
2073 12:38:24.965202 TX OE : NO K
2074 12:38:24.968343 All Pass.
2075 12:38:24.968424
2076 12:38:24.968488 CH 1, Rank 0
2077 12:38:24.971945 SW Impedance : PASS
2078 12:38:24.972055 DUTY Scan : NO K
2079 12:38:24.975508 ZQ Calibration : PASS
2080 12:38:24.978772 Jitter Meter : NO K
2081 12:38:24.978857 CBT Training : PASS
2082 12:38:24.981979 Write leveling : PASS
2083 12:38:24.982064 RX DQS gating : PASS
2084 12:38:24.985538 RX DQ/DQS(RDDQC) : PASS
2085 12:38:24.988926 TX DQ/DQS : PASS
2086 12:38:24.989010 RX DATLAT : PASS
2087 12:38:24.991929 RX DQ/DQS(Engine): PASS
2088 12:38:24.995322 TX OE : NO K
2089 12:38:24.995405 All Pass.
2090 12:38:24.995490
2091 12:38:24.995570 CH 1, Rank 1
2092 12:38:24.998687 SW Impedance : PASS
2093 12:38:25.002257 DUTY Scan : NO K
2094 12:38:25.002344 ZQ Calibration : PASS
2095 12:38:25.005638 Jitter Meter : NO K
2096 12:38:25.008922 CBT Training : PASS
2097 12:38:25.009009 Write leveling : PASS
2098 12:38:25.012168 RX DQS gating : PASS
2099 12:38:25.015671 RX DQ/DQS(RDDQC) : PASS
2100 12:38:25.015746 TX DQ/DQS : PASS
2101 12:38:25.018903 RX DATLAT : PASS
2102 12:38:25.018974 RX DQ/DQS(Engine): PASS
2103 12:38:25.022739 TX OE : NO K
2104 12:38:25.022812 All Pass.
2105 12:38:25.022881
2106 12:38:25.025937 DramC Write-DBI off
2107 12:38:25.029067 PER_BANK_REFRESH: Hybrid Mode
2108 12:38:25.029151 TX_TRACKING: ON
2109 12:38:25.031906 [GetDramInforAfterCalByMRR] Vendor 6.
2110 12:38:25.035363 [GetDramInforAfterCalByMRR] Revision 606.
2111 12:38:25.039036 [GetDramInforAfterCalByMRR] Revision 2 0.
2112 12:38:25.042521 MR0 0x3b3b
2113 12:38:25.042601 MR8 0x5151
2114 12:38:25.045768 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2115 12:38:25.045844
2116 12:38:25.049064 MR0 0x3b3b
2117 12:38:25.049141 MR8 0x5151
2118 12:38:25.052472 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2119 12:38:25.052548
2120 12:38:25.062057 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2121 12:38:25.065925 [FAST_K] Save calibration result to emmc
2122 12:38:25.068893 [FAST_K] Save calibration result to emmc
2123 12:38:25.072455 dram_init: config_dvfs: 1
2124 12:38:25.075686 dramc_set_vcore_voltage set vcore to 662500
2125 12:38:25.075758 Read voltage for 1200, 2
2126 12:38:25.079156 Vio18 = 0
2127 12:38:25.079232 Vcore = 662500
2128 12:38:25.079300 Vdram = 0
2129 12:38:25.082351 Vddq = 0
2130 12:38:25.082470 Vmddr = 0
2131 12:38:25.085530 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2132 12:38:25.092319 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2133 12:38:25.095735 MEM_TYPE=3, freq_sel=15
2134 12:38:25.099288 sv_algorithm_assistance_LP4_1600
2135 12:38:25.102538 ============ PULL DRAM RESETB DOWN ============
2136 12:38:25.105869 ========== PULL DRAM RESETB DOWN end =========
2137 12:38:25.108927 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2138 12:38:25.112695 ===================================
2139 12:38:25.116183 LPDDR4 DRAM CONFIGURATION
2140 12:38:25.119536 ===================================
2141 12:38:25.122600 EX_ROW_EN[0] = 0x0
2142 12:38:25.122683 EX_ROW_EN[1] = 0x0
2143 12:38:25.126192 LP4Y_EN = 0x0
2144 12:38:25.126294 WORK_FSP = 0x0
2145 12:38:25.129381 WL = 0x4
2146 12:38:25.129453 RL = 0x4
2147 12:38:25.132850 BL = 0x2
2148 12:38:25.132933 RPST = 0x0
2149 12:38:25.136607 RD_PRE = 0x0
2150 12:38:25.136734 WR_PRE = 0x1
2151 12:38:25.139760 WR_PST = 0x0
2152 12:38:25.139842 DBI_WR = 0x0
2153 12:38:25.142988 DBI_RD = 0x0
2154 12:38:25.143069 OTF = 0x1
2155 12:38:25.146240 ===================================
2156 12:38:25.149674 ===================================
2157 12:38:25.152556 ANA top config
2158 12:38:25.156511 ===================================
2159 12:38:25.156596 DLL_ASYNC_EN = 0
2160 12:38:25.159390 ALL_SLAVE_EN = 0
2161 12:38:25.162943 NEW_RANK_MODE = 1
2162 12:38:25.166401 DLL_IDLE_MODE = 1
2163 12:38:25.169768 LP45_APHY_COMB_EN = 1
2164 12:38:25.169851 TX_ODT_DIS = 1
2165 12:38:25.173006 NEW_8X_MODE = 1
2166 12:38:25.176479 ===================================
2167 12:38:25.180083 ===================================
2168 12:38:25.183124 data_rate = 2400
2169 12:38:25.186666 CKR = 1
2170 12:38:25.189606 DQ_P2S_RATIO = 8
2171 12:38:25.193133 ===================================
2172 12:38:25.193210 CA_P2S_RATIO = 8
2173 12:38:25.196726 DQ_CA_OPEN = 0
2174 12:38:25.199962 DQ_SEMI_OPEN = 0
2175 12:38:25.203300 CA_SEMI_OPEN = 0
2176 12:38:25.207174 CA_FULL_RATE = 0
2177 12:38:25.207256 DQ_CKDIV4_EN = 0
2178 12:38:25.210567 CA_CKDIV4_EN = 0
2179 12:38:25.213218 CA_PREDIV_EN = 0
2180 12:38:25.216637 PH8_DLY = 17
2181 12:38:25.220263 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2182 12:38:25.223611 DQ_AAMCK_DIV = 4
2183 12:38:25.223716 CA_AAMCK_DIV = 4
2184 12:38:25.226650 CA_ADMCK_DIV = 4
2185 12:38:25.230025 DQ_TRACK_CA_EN = 0
2186 12:38:25.233423 CA_PICK = 1200
2187 12:38:25.236874 CA_MCKIO = 1200
2188 12:38:25.240157 MCKIO_SEMI = 0
2189 12:38:25.243229 PLL_FREQ = 2366
2190 12:38:25.243307 DQ_UI_PI_RATIO = 32
2191 12:38:25.246610 CA_UI_PI_RATIO = 0
2192 12:38:25.249977 ===================================
2193 12:38:25.253762 ===================================
2194 12:38:25.257334 memory_type:LPDDR4
2195 12:38:25.260380 GP_NUM : 10
2196 12:38:25.260464 SRAM_EN : 1
2197 12:38:25.263685 MD32_EN : 0
2198 12:38:25.266984 ===================================
2199 12:38:25.267059 [ANA_INIT] >>>>>>>>>>>>>>
2200 12:38:25.270064 <<<<<< [CONFIGURE PHASE]: ANA_TX
2201 12:38:25.273419 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2202 12:38:25.277072 ===================================
2203 12:38:25.280537 data_rate = 2400,PCW = 0X5b00
2204 12:38:25.283406 ===================================
2205 12:38:25.286840 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2206 12:38:25.293723 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2207 12:38:25.297170 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2208 12:38:25.304197 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2209 12:38:25.307043 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2210 12:38:25.310384 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2211 12:38:25.310508 [ANA_INIT] flow start
2212 12:38:25.313752 [ANA_INIT] PLL >>>>>>>>
2213 12:38:25.317275 [ANA_INIT] PLL <<<<<<<<
2214 12:38:25.320459 [ANA_INIT] MIDPI >>>>>>>>
2215 12:38:25.320540 [ANA_INIT] MIDPI <<<<<<<<
2216 12:38:25.324058 [ANA_INIT] DLL >>>>>>>>
2217 12:38:25.327293 [ANA_INIT] DLL <<<<<<<<
2218 12:38:25.327374 [ANA_INIT] flow end
2219 12:38:25.330582 ============ LP4 DIFF to SE enter ============
2220 12:38:25.337378 ============ LP4 DIFF to SE exit ============
2221 12:38:25.337470 [ANA_INIT] <<<<<<<<<<<<<
2222 12:38:25.340899 [Flow] Enable top DCM control >>>>>
2223 12:38:25.343766 [Flow] Enable top DCM control <<<<<
2224 12:38:25.347737 Enable DLL master slave shuffle
2225 12:38:25.354051 ==============================================================
2226 12:38:25.354153 Gating Mode config
2227 12:38:25.361237 ==============================================================
2228 12:38:25.364707 Config description:
2229 12:38:25.370781 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2230 12:38:25.377638 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2231 12:38:25.384403 SELPH_MODE 0: By rank 1: By Phase
2232 12:38:25.387948 ==============================================================
2233 12:38:25.391304 GAT_TRACK_EN = 1
2234 12:38:25.394356 RX_GATING_MODE = 2
2235 12:38:25.397699 RX_GATING_TRACK_MODE = 2
2236 12:38:25.401090 SELPH_MODE = 1
2237 12:38:25.404663 PICG_EARLY_EN = 1
2238 12:38:25.408082 VALID_LAT_VALUE = 1
2239 12:38:25.411807 ==============================================================
2240 12:38:25.415325 Enter into Gating configuration >>>>
2241 12:38:25.417977 Exit from Gating configuration <<<<
2242 12:38:25.421198 Enter into DVFS_PRE_config >>>>>
2243 12:38:25.435510 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2244 12:38:25.438286 Exit from DVFS_PRE_config <<<<<
2245 12:38:25.438383 Enter into PICG configuration >>>>
2246 12:38:25.442001 Exit from PICG configuration <<<<
2247 12:38:25.445471 [RX_INPUT] configuration >>>>>
2248 12:38:25.448114 [RX_INPUT] configuration <<<<<
2249 12:38:25.455382 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2250 12:38:25.458160 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2251 12:38:25.465741 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2252 12:38:25.473068 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2253 12:38:25.478619 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2254 12:38:25.485319 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2255 12:38:25.489081 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2256 12:38:25.492650 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2257 12:38:25.495878 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2258 12:38:25.499611 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2259 12:38:25.505673 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2260 12:38:25.509100 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2261 12:38:25.511881 ===================================
2262 12:38:25.515829 LPDDR4 DRAM CONFIGURATION
2263 12:38:25.518728 ===================================
2264 12:38:25.518808 EX_ROW_EN[0] = 0x0
2265 12:38:25.521961 EX_ROW_EN[1] = 0x0
2266 12:38:25.522073 LP4Y_EN = 0x0
2267 12:38:25.525691 WORK_FSP = 0x0
2268 12:38:25.525775 WL = 0x4
2269 12:38:25.529203 RL = 0x4
2270 12:38:25.529285 BL = 0x2
2271 12:38:25.532266 RPST = 0x0
2272 12:38:25.532347 RD_PRE = 0x0
2273 12:38:25.535665 WR_PRE = 0x1
2274 12:38:25.535745 WR_PST = 0x0
2275 12:38:25.539201 DBI_WR = 0x0
2276 12:38:25.539281 DBI_RD = 0x0
2277 12:38:25.542413 OTF = 0x1
2278 12:38:25.545722 ===================================
2279 12:38:25.549321 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2280 12:38:25.552608 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2281 12:38:25.558900 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2282 12:38:25.562203 ===================================
2283 12:38:25.562292 LPDDR4 DRAM CONFIGURATION
2284 12:38:25.565724 ===================================
2285 12:38:25.569164 EX_ROW_EN[0] = 0x10
2286 12:38:25.572581 EX_ROW_EN[1] = 0x0
2287 12:38:25.572663 LP4Y_EN = 0x0
2288 12:38:25.576107 WORK_FSP = 0x0
2289 12:38:25.576188 WL = 0x4
2290 12:38:25.579503 RL = 0x4
2291 12:38:25.579583 BL = 0x2
2292 12:38:25.582427 RPST = 0x0
2293 12:38:25.582522 RD_PRE = 0x0
2294 12:38:25.586306 WR_PRE = 0x1
2295 12:38:25.586385 WR_PST = 0x0
2296 12:38:25.589277 DBI_WR = 0x0
2297 12:38:25.589356 DBI_RD = 0x0
2298 12:38:25.592544 OTF = 0x1
2299 12:38:25.596544 ===================================
2300 12:38:25.603276 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2301 12:38:25.603365 ==
2302 12:38:25.606085 Dram Type= 6, Freq= 0, CH_0, rank 0
2303 12:38:25.609596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2304 12:38:25.609671 ==
2305 12:38:25.612519 [Duty_Offset_Calibration]
2306 12:38:25.612615 B0:2 B1:-1 CA:1
2307 12:38:25.612711
2308 12:38:25.615866 [DutyScan_Calibration_Flow] k_type=0
2309 12:38:25.624898
2310 12:38:25.625005 ==CLK 0==
2311 12:38:25.628594 Final CLK duty delay cell = -4
2312 12:38:25.632264 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2313 12:38:25.634987 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2314 12:38:25.639190 [-4] AVG Duty = 4953%(X100)
2315 12:38:25.639265
2316 12:38:25.642146 CH0 CLK Duty spec in!! Max-Min= 156%
2317 12:38:25.645150 [DutyScan_Calibration_Flow] ====Done====
2318 12:38:25.645224
2319 12:38:25.648832 [DutyScan_Calibration_Flow] k_type=1
2320 12:38:25.663341
2321 12:38:25.663458 ==DQS 0 ==
2322 12:38:25.666966 Final DQS duty delay cell = -4
2323 12:38:25.670126 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2324 12:38:25.673169 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2325 12:38:25.676720 [-4] AVG Duty = 4938%(X100)
2326 12:38:25.676802
2327 12:38:25.676866 ==DQS 1 ==
2328 12:38:25.680487 Final DQS duty delay cell = -4
2329 12:38:25.683152 [-4] MAX Duty = 5124%(X100), DQS PI = 4
2330 12:38:25.686942 [-4] MIN Duty = 5000%(X100), DQS PI = 58
2331 12:38:25.689984 [-4] AVG Duty = 5062%(X100)
2332 12:38:25.690082
2333 12:38:25.693443 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2334 12:38:25.693538
2335 12:38:25.697176 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2336 12:38:25.700367 [DutyScan_Calibration_Flow] ====Done====
2337 12:38:25.700439
2338 12:38:25.703533 [DutyScan_Calibration_Flow] k_type=3
2339 12:38:25.720134
2340 12:38:25.720234 ==DQM 0 ==
2341 12:38:25.723922 Final DQM duty delay cell = 0
2342 12:38:25.727347 [0] MAX Duty = 5000%(X100), DQS PI = 54
2343 12:38:25.730932 [0] MIN Duty = 4907%(X100), DQS PI = 2
2344 12:38:25.731014 [0] AVG Duty = 4953%(X100)
2345 12:38:25.734052
2346 12:38:25.734132 ==DQM 1 ==
2347 12:38:25.737032 Final DQM duty delay cell = 0
2348 12:38:25.741054 [0] MAX Duty = 5156%(X100), DQS PI = 62
2349 12:38:25.743901 [0] MIN Duty = 4969%(X100), DQS PI = 10
2350 12:38:25.743982 [0] AVG Duty = 5062%(X100)
2351 12:38:25.747341
2352 12:38:25.750511 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2353 12:38:25.750594
2354 12:38:25.754215 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2355 12:38:25.756965 [DutyScan_Calibration_Flow] ====Done====
2356 12:38:25.757077
2357 12:38:25.760680 [DutyScan_Calibration_Flow] k_type=2
2358 12:38:25.775729
2359 12:38:25.775838 ==DQ 0 ==
2360 12:38:25.779534 Final DQ duty delay cell = -4
2361 12:38:25.783033 [-4] MAX Duty = 5093%(X100), DQS PI = 54
2362 12:38:25.786254 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2363 12:38:25.789273 [-4] AVG Duty = 5000%(X100)
2364 12:38:25.789375
2365 12:38:25.789465 ==DQ 1 ==
2366 12:38:25.792726 Final DQ duty delay cell = 0
2367 12:38:25.796240 [0] MAX Duty = 5031%(X100), DQS PI = 18
2368 12:38:25.799307 [0] MIN Duty = 4907%(X100), DQS PI = 46
2369 12:38:25.803205 [0] AVG Duty = 4969%(X100)
2370 12:38:25.803314
2371 12:38:25.805948 CH0 DQ 0 Duty spec in!! Max-Min= 186%
2372 12:38:25.806054
2373 12:38:25.809392 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2374 12:38:25.812671 [DutyScan_Calibration_Flow] ====Done====
2375 12:38:25.812770 ==
2376 12:38:25.816196 Dram Type= 6, Freq= 0, CH_1, rank 0
2377 12:38:25.820035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2378 12:38:25.820134 ==
2379 12:38:25.822852 [Duty_Offset_Calibration]
2380 12:38:25.822956 B0:1 B1:1 CA:2
2381 12:38:25.823053
2382 12:38:25.826185 [DutyScan_Calibration_Flow] k_type=0
2383 12:38:25.836492
2384 12:38:25.836595 ==CLK 0==
2385 12:38:25.839669 Final CLK duty delay cell = 0
2386 12:38:25.843065 [0] MAX Duty = 5187%(X100), DQS PI = 24
2387 12:38:25.846594 [0] MIN Duty = 4969%(X100), DQS PI = 40
2388 12:38:25.846668 [0] AVG Duty = 5078%(X100)
2389 12:38:25.846741
2390 12:38:25.849819 CH1 CLK Duty spec in!! Max-Min= 218%
2391 12:38:25.856317 [DutyScan_Calibration_Flow] ====Done====
2392 12:38:25.856394
2393 12:38:25.859988 [DutyScan_Calibration_Flow] k_type=1
2394 12:38:25.875684
2395 12:38:25.875788 ==DQS 0 ==
2396 12:38:25.878804 Final DQS duty delay cell = 0
2397 12:38:25.882462 [0] MAX Duty = 5031%(X100), DQS PI = 18
2398 12:38:25.885639 [0] MIN Duty = 4844%(X100), DQS PI = 48
2399 12:38:25.885715 [0] AVG Duty = 4937%(X100)
2400 12:38:25.889190
2401 12:38:25.889270 ==DQS 1 ==
2402 12:38:25.892686 Final DQS duty delay cell = 0
2403 12:38:25.895796 [0] MAX Duty = 5062%(X100), DQS PI = 36
2404 12:38:25.899319 [0] MIN Duty = 4907%(X100), DQS PI = 16
2405 12:38:25.899401 [0] AVG Duty = 4984%(X100)
2406 12:38:25.902667
2407 12:38:25.905762 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2408 12:38:25.905842
2409 12:38:25.909337 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2410 12:38:25.912872 [DutyScan_Calibration_Flow] ====Done====
2411 12:38:25.912954
2412 12:38:25.915730 [DutyScan_Calibration_Flow] k_type=3
2413 12:38:25.932139
2414 12:38:25.932233 ==DQM 0 ==
2415 12:38:25.935949 Final DQM duty delay cell = 0
2416 12:38:25.938946 [0] MAX Duty = 5093%(X100), DQS PI = 18
2417 12:38:25.942272 [0] MIN Duty = 4876%(X100), DQS PI = 50
2418 12:38:25.942352 [0] AVG Duty = 4984%(X100)
2419 12:38:25.945647
2420 12:38:25.945718 ==DQM 1 ==
2421 12:38:25.948829 Final DQM duty delay cell = 0
2422 12:38:25.952352 [0] MAX Duty = 5156%(X100), DQS PI = 62
2423 12:38:25.955352 [0] MIN Duty = 4938%(X100), DQS PI = 22
2424 12:38:25.955425 [0] AVG Duty = 5047%(X100)
2425 12:38:25.959360
2426 12:38:25.962175 CH1 DQM 0 Duty spec in!! Max-Min= 217%
2427 12:38:25.962247
2428 12:38:25.965904 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2429 12:38:25.969616 [DutyScan_Calibration_Flow] ====Done====
2430 12:38:25.969693
2431 12:38:25.972261 [DutyScan_Calibration_Flow] k_type=2
2432 12:38:25.987798
2433 12:38:25.987888 ==DQ 0 ==
2434 12:38:25.991442 Final DQ duty delay cell = 0
2435 12:38:25.994819 [0] MAX Duty = 5156%(X100), DQS PI = 18
2436 12:38:25.998039 [0] MIN Duty = 4938%(X100), DQS PI = 50
2437 12:38:25.998118 [0] AVG Duty = 5047%(X100)
2438 12:38:25.998179
2439 12:38:26.001331 ==DQ 1 ==
2440 12:38:26.004971 Final DQ duty delay cell = -4
2441 12:38:26.008060 [-4] MAX Duty = 4969%(X100), DQS PI = 10
2442 12:38:26.012260 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2443 12:38:26.012332 [-4] AVG Duty = 4938%(X100)
2444 12:38:26.012390
2445 12:38:26.018377 CH1 DQ 0 Duty spec in!! Max-Min= 218%
2446 12:38:26.018493
2447 12:38:26.021682 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2448 12:38:26.024776 [DutyScan_Calibration_Flow] ====Done====
2449 12:38:26.028296 nWR fixed to 30
2450 12:38:26.028392 [ModeRegInit_LP4] CH0 RK0
2451 12:38:26.032263 [ModeRegInit_LP4] CH0 RK1
2452 12:38:26.035335 [ModeRegInit_LP4] CH1 RK0
2453 12:38:26.035407 [ModeRegInit_LP4] CH1 RK1
2454 12:38:26.038372 match AC timing 7
2455 12:38:26.041546 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2456 12:38:26.044861 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2457 12:38:26.052023 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2458 12:38:26.054829 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2459 12:38:26.061789 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2460 12:38:26.061865 ==
2461 12:38:26.065125 Dram Type= 6, Freq= 0, CH_0, rank 0
2462 12:38:26.068457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2463 12:38:26.068531 ==
2464 12:38:26.075337 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2465 12:38:26.078898 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2466 12:38:26.088119 [CA 0] Center 40 (10~71) winsize 62
2467 12:38:26.091689 [CA 1] Center 39 (9~70) winsize 62
2468 12:38:26.094907 [CA 2] Center 36 (6~67) winsize 62
2469 12:38:26.098434 [CA 3] Center 35 (5~66) winsize 62
2470 12:38:26.101626 [CA 4] Center 34 (4~65) winsize 62
2471 12:38:26.105270 [CA 5] Center 34 (4~64) winsize 61
2472 12:38:26.105383
2473 12:38:26.108445 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2474 12:38:26.108518
2475 12:38:26.112230 [CATrainingPosCal] consider 1 rank data
2476 12:38:26.115187 u2DelayCellTimex100 = 270/100 ps
2477 12:38:26.118341 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2478 12:38:26.122033 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2479 12:38:26.128416 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2480 12:38:26.132239 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2481 12:38:26.135598 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2482 12:38:26.138957 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2483 12:38:26.139039
2484 12:38:26.141901 CA PerBit enable=1, Macro0, CA PI delay=34
2485 12:38:26.141971
2486 12:38:26.145499 [CBTSetCACLKResult] CA Dly = 34
2487 12:38:26.145570 CS Dly: 7 (0~38)
2488 12:38:26.145638 ==
2489 12:38:26.149048 Dram Type= 6, Freq= 0, CH_0, rank 1
2490 12:38:26.155861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2491 12:38:26.155939 ==
2492 12:38:26.158694 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2493 12:38:26.166001 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2494 12:38:26.174323 [CA 0] Center 39 (9~70) winsize 62
2495 12:38:26.178067 [CA 1] Center 40 (10~70) winsize 61
2496 12:38:26.181074 [CA 2] Center 36 (6~67) winsize 62
2497 12:38:26.184394 [CA 3] Center 36 (5~67) winsize 63
2498 12:38:26.187888 [CA 4] Center 34 (4~65) winsize 62
2499 12:38:26.191551 [CA 5] Center 34 (4~64) winsize 61
2500 12:38:26.191624
2501 12:38:26.194270 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2502 12:38:26.194366
2503 12:38:26.197822 [CATrainingPosCal] consider 2 rank data
2504 12:38:26.201363 u2DelayCellTimex100 = 270/100 ps
2505 12:38:26.204305 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2506 12:38:26.208041 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2507 12:38:26.215005 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2508 12:38:26.218102 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2509 12:38:26.221041 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2510 12:38:26.224410 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2511 12:38:26.224499
2512 12:38:26.227862 CA PerBit enable=1, Macro0, CA PI delay=34
2513 12:38:26.227935
2514 12:38:26.231215 [CBTSetCACLKResult] CA Dly = 34
2515 12:38:26.231287 CS Dly: 8 (0~41)
2516 12:38:26.231347
2517 12:38:26.235269 ----->DramcWriteLeveling(PI) begin...
2518 12:38:26.235348 ==
2519 12:38:26.238584 Dram Type= 6, Freq= 0, CH_0, rank 0
2520 12:38:26.244792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2521 12:38:26.244875 ==
2522 12:38:26.248148 Write leveling (Byte 0): 31 => 31
2523 12:38:26.251295 Write leveling (Byte 1): 27 => 27
2524 12:38:26.251375 DramcWriteLeveling(PI) end<-----
2525 12:38:26.251437
2526 12:38:26.254767 ==
2527 12:38:26.254838 Dram Type= 6, Freq= 0, CH_0, rank 0
2528 12:38:26.261785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2529 12:38:26.261861 ==
2530 12:38:26.265045 [Gating] SW mode calibration
2531 12:38:26.271757 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2532 12:38:26.274611 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2533 12:38:26.281658 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 12:38:26.285367 0 15 4 | B1->B0 | 2322 3030 | 1 0 | (0 0) (0 0)
2535 12:38:26.288440 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 12:38:26.294929 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 12:38:26.298291 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 12:38:26.301818 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 12:38:26.305464 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 12:38:26.312237 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 12:38:26.314986 1 0 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2542 12:38:26.318610 1 0 4 | B1->B0 | 2929 2323 | 1 0 | (1 0) (1 0)
2543 12:38:26.325741 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 12:38:26.328364 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 12:38:26.332033 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 12:38:26.338649 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 12:38:26.342044 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 12:38:26.345448 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 12:38:26.352707 1 1 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2550 12:38:26.355496 1 1 4 | B1->B0 | 3635 4242 | 1 0 | (1 1) (0 0)
2551 12:38:26.359035 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 12:38:26.365525 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 12:38:26.368698 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 12:38:26.372258 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 12:38:26.375191 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 12:38:26.381972 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 12:38:26.385881 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2558 12:38:26.388979 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2559 12:38:26.395235 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 12:38:26.398606 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 12:38:26.402312 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 12:38:26.409128 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 12:38:26.412192 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 12:38:26.415767 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 12:38:26.422695 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 12:38:26.425967 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 12:38:26.428844 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 12:38:26.435742 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 12:38:26.438979 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 12:38:26.442828 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 12:38:26.445702 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 12:38:26.452637 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 12:38:26.455931 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2574 12:38:26.459387 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2575 12:38:26.462321 Total UI for P1: 0, mck2ui 16
2576 12:38:26.466121 best dqsien dly found for B0: ( 1, 4, 0)
2577 12:38:26.472623 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2578 12:38:26.472704 Total UI for P1: 0, mck2ui 16
2579 12:38:26.479329 best dqsien dly found for B1: ( 1, 4, 2)
2580 12:38:26.482338 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2581 12:38:26.485808 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2582 12:38:26.485885
2583 12:38:26.489359 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2584 12:38:26.492884 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2585 12:38:26.495869 [Gating] SW calibration Done
2586 12:38:26.495943 ==
2587 12:38:26.499056 Dram Type= 6, Freq= 0, CH_0, rank 0
2588 12:38:26.502546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2589 12:38:26.502659 ==
2590 12:38:26.506154 RX Vref Scan: 0
2591 12:38:26.506267
2592 12:38:26.506356 RX Vref 0 -> 0, step: 1
2593 12:38:26.506491
2594 12:38:26.509769 RX Delay -40 -> 252, step: 8
2595 12:38:26.512775 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2596 12:38:26.516624 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2597 12:38:26.522698 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2598 12:38:26.526139 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2599 12:38:26.529801 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2600 12:38:26.532815 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2601 12:38:26.536387 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2602 12:38:26.542944 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2603 12:38:26.546741 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2604 12:38:26.549984 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2605 12:38:26.552986 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2606 12:38:26.556590 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2607 12:38:26.559519 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2608 12:38:26.566313 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2609 12:38:26.570112 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2610 12:38:26.573229 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2611 12:38:26.573317 ==
2612 12:38:26.576274 Dram Type= 6, Freq= 0, CH_0, rank 0
2613 12:38:26.579637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2614 12:38:26.579745 ==
2615 12:38:26.583582 DQS Delay:
2616 12:38:26.583664 DQS0 = 0, DQS1 = 0
2617 12:38:26.586194 DQM Delay:
2618 12:38:26.586267 DQM0 = 115, DQM1 = 106
2619 12:38:26.586335 DQ Delay:
2620 12:38:26.590178 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2621 12:38:26.596529 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2622 12:38:26.599641 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2623 12:38:26.603333 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2624 12:38:26.603417
2625 12:38:26.603481
2626 12:38:26.603541 ==
2627 12:38:26.606458 Dram Type= 6, Freq= 0, CH_0, rank 0
2628 12:38:26.610140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2629 12:38:26.610238 ==
2630 12:38:26.610334
2631 12:38:26.610455
2632 12:38:26.613645 TX Vref Scan disable
2633 12:38:26.613718 == TX Byte 0 ==
2634 12:38:26.620921 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2635 12:38:26.623633 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2636 12:38:26.623709 == TX Byte 1 ==
2637 12:38:26.630207 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2638 12:38:26.633864 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2639 12:38:26.633946 ==
2640 12:38:26.636767 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 12:38:26.640102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 12:38:26.640183 ==
2643 12:38:26.653415 TX Vref=22, minBit 7, minWin=24, winSum=417
2644 12:38:26.656830 TX Vref=24, minBit 7, minWin=24, winSum=424
2645 12:38:26.659896 TX Vref=26, minBit 0, minWin=26, winSum=429
2646 12:38:26.663012 TX Vref=28, minBit 0, minWin=26, winSum=434
2647 12:38:26.666778 TX Vref=30, minBit 0, minWin=26, winSum=434
2648 12:38:26.669784 TX Vref=32, minBit 1, minWin=26, winSum=433
2649 12:38:26.676748 [TxChooseVref] Worse bit 0, Min win 26, Win sum 434, Final Vref 28
2650 12:38:26.676852
2651 12:38:26.680201 Final TX Range 1 Vref 28
2652 12:38:26.680299
2653 12:38:26.680387 ==
2654 12:38:26.683160 Dram Type= 6, Freq= 0, CH_0, rank 0
2655 12:38:26.686572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2656 12:38:26.686680 ==
2657 12:38:26.686769
2658 12:38:26.686855
2659 12:38:26.689860 TX Vref Scan disable
2660 12:38:26.693595 == TX Byte 0 ==
2661 12:38:26.696949 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2662 12:38:26.699763 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2663 12:38:26.703253 == TX Byte 1 ==
2664 12:38:26.706752 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2665 12:38:26.710830 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2666 12:38:26.710912
2667 12:38:26.713226 [DATLAT]
2668 12:38:26.713331 Freq=1200, CH0 RK0
2669 12:38:26.713421
2670 12:38:26.716592 DATLAT Default: 0xd
2671 12:38:26.716671 0, 0xFFFF, sum = 0
2672 12:38:26.720085 1, 0xFFFF, sum = 0
2673 12:38:26.720193 2, 0xFFFF, sum = 0
2674 12:38:26.723179 3, 0xFFFF, sum = 0
2675 12:38:26.723291 4, 0xFFFF, sum = 0
2676 12:38:26.726564 5, 0xFFFF, sum = 0
2677 12:38:26.726649 6, 0xFFFF, sum = 0
2678 12:38:26.730197 7, 0xFFFF, sum = 0
2679 12:38:26.730342 8, 0xFFFF, sum = 0
2680 12:38:26.733552 9, 0xFFFF, sum = 0
2681 12:38:26.733652 10, 0xFFFF, sum = 0
2682 12:38:26.736682 11, 0xFFFF, sum = 0
2683 12:38:26.736797 12, 0x0, sum = 1
2684 12:38:26.740818 13, 0x0, sum = 2
2685 12:38:26.740902 14, 0x0, sum = 3
2686 12:38:26.743271 15, 0x0, sum = 4
2687 12:38:26.743359 best_step = 13
2688 12:38:26.743428
2689 12:38:26.743490 ==
2690 12:38:26.747038 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 12:38:26.754138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 12:38:26.754252 ==
2693 12:38:26.754346 RX Vref Scan: 1
2694 12:38:26.754466
2695 12:38:26.756801 Set Vref Range= 32 -> 127
2696 12:38:26.756880
2697 12:38:26.760335 RX Vref 32 -> 127, step: 1
2698 12:38:26.760414
2699 12:38:26.760478 RX Delay -21 -> 252, step: 4
2700 12:38:26.763345
2701 12:38:26.763424 Set Vref, RX VrefLevel [Byte0]: 32
2702 12:38:26.766843 [Byte1]: 32
2703 12:38:26.771878
2704 12:38:26.771957 Set Vref, RX VrefLevel [Byte0]: 33
2705 12:38:26.775678 [Byte1]: 33
2706 12:38:26.779477
2707 12:38:26.779558 Set Vref, RX VrefLevel [Byte0]: 34
2708 12:38:26.783102 [Byte1]: 34
2709 12:38:26.787633
2710 12:38:26.787714 Set Vref, RX VrefLevel [Byte0]: 35
2711 12:38:26.790859 [Byte1]: 35
2712 12:38:26.795496
2713 12:38:26.795576 Set Vref, RX VrefLevel [Byte0]: 36
2714 12:38:26.798661 [Byte1]: 36
2715 12:38:26.803573
2716 12:38:26.803653 Set Vref, RX VrefLevel [Byte0]: 37
2717 12:38:26.807398 [Byte1]: 37
2718 12:38:26.811162
2719 12:38:26.811242 Set Vref, RX VrefLevel [Byte0]: 38
2720 12:38:26.814411 [Byte1]: 38
2721 12:38:26.818848
2722 12:38:26.818955 Set Vref, RX VrefLevel [Byte0]: 39
2723 12:38:26.822794 [Byte1]: 39
2724 12:38:26.826886
2725 12:38:26.826992 Set Vref, RX VrefLevel [Byte0]: 40
2726 12:38:26.830802 [Byte1]: 40
2727 12:38:26.834757
2728 12:38:26.834838 Set Vref, RX VrefLevel [Byte0]: 41
2729 12:38:26.841398 [Byte1]: 41
2730 12:38:26.841480
2731 12:38:26.844481 Set Vref, RX VrefLevel [Byte0]: 42
2732 12:38:26.848094 [Byte1]: 42
2733 12:38:26.848175
2734 12:38:26.851307 Set Vref, RX VrefLevel [Byte0]: 43
2735 12:38:26.854807 [Byte1]: 43
2736 12:38:26.858856
2737 12:38:26.858938 Set Vref, RX VrefLevel [Byte0]: 44
2738 12:38:26.862295 [Byte1]: 44
2739 12:38:26.866972
2740 12:38:26.867051 Set Vref, RX VrefLevel [Byte0]: 45
2741 12:38:26.870059 [Byte1]: 45
2742 12:38:26.874832
2743 12:38:26.874922 Set Vref, RX VrefLevel [Byte0]: 46
2744 12:38:26.877587 [Byte1]: 46
2745 12:38:26.882605
2746 12:38:26.882685 Set Vref, RX VrefLevel [Byte0]: 47
2747 12:38:26.885567 [Byte1]: 47
2748 12:38:26.890295
2749 12:38:26.890420 Set Vref, RX VrefLevel [Byte0]: 48
2750 12:38:26.893832 [Byte1]: 48
2751 12:38:26.898389
2752 12:38:26.898506 Set Vref, RX VrefLevel [Byte0]: 49
2753 12:38:26.901541 [Byte1]: 49
2754 12:38:26.906148
2755 12:38:26.906251 Set Vref, RX VrefLevel [Byte0]: 50
2756 12:38:26.909643 [Byte1]: 50
2757 12:38:26.913950
2758 12:38:26.914030 Set Vref, RX VrefLevel [Byte0]: 51
2759 12:38:26.917354 [Byte1]: 51
2760 12:38:26.921826
2761 12:38:26.921918 Set Vref, RX VrefLevel [Byte0]: 52
2762 12:38:26.925373 [Byte1]: 52
2763 12:38:26.930220
2764 12:38:26.930319 Set Vref, RX VrefLevel [Byte0]: 53
2765 12:38:26.933353 [Byte1]: 53
2766 12:38:26.938151
2767 12:38:26.938256 Set Vref, RX VrefLevel [Byte0]: 54
2768 12:38:26.941565 [Byte1]: 54
2769 12:38:26.946269
2770 12:38:26.946377 Set Vref, RX VrefLevel [Byte0]: 55
2771 12:38:26.948976 [Byte1]: 55
2772 12:38:26.953562
2773 12:38:26.953639 Set Vref, RX VrefLevel [Byte0]: 56
2774 12:38:26.957141 [Byte1]: 56
2775 12:38:26.961657
2776 12:38:26.961735 Set Vref, RX VrefLevel [Byte0]: 57
2777 12:38:26.964975 [Byte1]: 57
2778 12:38:26.969321
2779 12:38:26.969401 Set Vref, RX VrefLevel [Byte0]: 58
2780 12:38:26.973117 [Byte1]: 58
2781 12:38:26.977511
2782 12:38:26.977593 Set Vref, RX VrefLevel [Byte0]: 59
2783 12:38:26.981046 [Byte1]: 59
2784 12:38:26.985608
2785 12:38:26.985727 Set Vref, RX VrefLevel [Byte0]: 60
2786 12:38:26.988882 [Byte1]: 60
2787 12:38:26.993188
2788 12:38:26.993268 Set Vref, RX VrefLevel [Byte0]: 61
2789 12:38:26.996733 [Byte1]: 61
2790 12:38:27.001377
2791 12:38:27.001488 Set Vref, RX VrefLevel [Byte0]: 62
2792 12:38:27.004533 [Byte1]: 62
2793 12:38:27.009056
2794 12:38:27.009157 Set Vref, RX VrefLevel [Byte0]: 63
2795 12:38:27.012571 [Byte1]: 63
2796 12:38:27.017274
2797 12:38:27.017377 Set Vref, RX VrefLevel [Byte0]: 64
2798 12:38:27.020962 [Byte1]: 64
2799 12:38:27.024802
2800 12:38:27.024885 Set Vref, RX VrefLevel [Byte0]: 65
2801 12:38:27.028176 [Byte1]: 65
2802 12:38:27.033288
2803 12:38:27.033371 Set Vref, RX VrefLevel [Byte0]: 66
2804 12:38:27.036822 [Byte1]: 66
2805 12:38:27.040831
2806 12:38:27.041006 Set Vref, RX VrefLevel [Byte0]: 67
2807 12:38:27.044101 [Byte1]: 67
2808 12:38:27.048853
2809 12:38:27.048993 Set Vref, RX VrefLevel [Byte0]: 68
2810 12:38:27.051862 [Byte1]: 68
2811 12:38:27.057012
2812 12:38:27.057094 Final RX Vref Byte 0 = 53 to rank0
2813 12:38:27.060222 Final RX Vref Byte 1 = 52 to rank0
2814 12:38:27.063629 Final RX Vref Byte 0 = 53 to rank1
2815 12:38:27.066980 Final RX Vref Byte 1 = 52 to rank1==
2816 12:38:27.070282 Dram Type= 6, Freq= 0, CH_0, rank 0
2817 12:38:27.073781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2818 12:38:27.077036 ==
2819 12:38:27.077118 DQS Delay:
2820 12:38:27.077184 DQS0 = 0, DQS1 = 0
2821 12:38:27.080723 DQM Delay:
2822 12:38:27.080802 DQM0 = 115, DQM1 = 104
2823 12:38:27.083637 DQ Delay:
2824 12:38:27.086827 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =114
2825 12:38:27.090469 DQ4 =116, DQ5 =110, DQ6 =120, DQ7 =122
2826 12:38:27.094002 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2827 12:38:27.097361 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2828 12:38:27.097461
2829 12:38:27.097562
2830 12:38:27.103686 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbea, (MSB)MR19= 0x303, tDQSOscB0 = 419 ps tDQSOscB1 = 412 ps
2831 12:38:27.107552 CH0 RK0: MR19=303, MR18=FBEA
2832 12:38:27.113842 CH0_RK0: MR19=0x303, MR18=0xFBEA, DQSOSC=412, MR23=63, INC=38, DEC=25
2833 12:38:27.113968
2834 12:38:27.117773 ----->DramcWriteLeveling(PI) begin...
2835 12:38:27.117857 ==
2836 12:38:27.120602 Dram Type= 6, Freq= 0, CH_0, rank 1
2837 12:38:27.123848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2838 12:38:27.123965 ==
2839 12:38:27.127335 Write leveling (Byte 0): 32 => 32
2840 12:38:27.130582 Write leveling (Byte 1): 30 => 30
2841 12:38:27.134585 DramcWriteLeveling(PI) end<-----
2842 12:38:27.134660
2843 12:38:27.134723 ==
2844 12:38:27.137422 Dram Type= 6, Freq= 0, CH_0, rank 1
2845 12:38:27.140400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2846 12:38:27.140484 ==
2847 12:38:27.144296 [Gating] SW mode calibration
2848 12:38:27.150355 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2849 12:38:27.157725 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2850 12:38:27.161369 0 15 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2851 12:38:27.167285 0 15 4 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
2852 12:38:27.170973 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 12:38:27.174010 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 12:38:27.177197 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 12:38:27.183963 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 12:38:27.187335 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2857 12:38:27.190995 0 15 28 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 1)
2858 12:38:27.197283 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
2859 12:38:27.200995 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2860 12:38:27.204371 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 12:38:27.211140 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 12:38:27.214366 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 12:38:27.218035 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 12:38:27.224130 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2865 12:38:27.227477 1 0 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
2866 12:38:27.230866 1 1 0 | B1->B0 | 3838 4545 | 0 0 | (0 0) (0 0)
2867 12:38:27.237613 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2868 12:38:27.241363 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 12:38:27.244347 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 12:38:27.248021 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 12:38:27.254518 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 12:38:27.258146 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 12:38:27.261723 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2874 12:38:27.267747 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2875 12:38:27.271687 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 12:38:27.274749 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 12:38:27.281650 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 12:38:27.284784 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 12:38:27.288148 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 12:38:27.294673 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 12:38:27.298157 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 12:38:27.301789 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 12:38:27.304511 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 12:38:27.311606 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 12:38:27.314811 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 12:38:27.318076 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 12:38:27.324947 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 12:38:27.328162 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2889 12:38:27.331528 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2890 12:38:27.338142 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2891 12:38:27.338232 Total UI for P1: 0, mck2ui 16
2892 12:38:27.345332 best dqsien dly found for B0: ( 1, 3, 26)
2893 12:38:27.348737 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2894 12:38:27.351777 Total UI for P1: 0, mck2ui 16
2895 12:38:27.355003 best dqsien dly found for B1: ( 1, 3, 30)
2896 12:38:27.358352 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2897 12:38:27.361648 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2898 12:38:27.361734
2899 12:38:27.365448 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2900 12:38:27.368301 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2901 12:38:27.371919 [Gating] SW calibration Done
2902 12:38:27.372000 ==
2903 12:38:27.375059 Dram Type= 6, Freq= 0, CH_0, rank 1
2904 12:38:27.378547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2905 12:38:27.378638 ==
2906 12:38:27.381692 RX Vref Scan: 0
2907 12:38:27.381771
2908 12:38:27.385449 RX Vref 0 -> 0, step: 1
2909 12:38:27.385532
2910 12:38:27.385594 RX Delay -40 -> 252, step: 8
2911 12:38:27.392024 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2912 12:38:27.395483 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2913 12:38:27.398637 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2914 12:38:27.402606 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2915 12:38:27.405758 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2916 12:38:27.411744 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2917 12:38:27.415699 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2918 12:38:27.419340 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2919 12:38:27.421969 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2920 12:38:27.425621 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2921 12:38:27.429396 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2922 12:38:27.435240 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2923 12:38:27.439747 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2924 12:38:27.442123 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2925 12:38:27.445847 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2926 12:38:27.448923 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2927 12:38:27.452114 ==
2928 12:38:27.452215 Dram Type= 6, Freq= 0, CH_0, rank 1
2929 12:38:27.459073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2930 12:38:27.459160 ==
2931 12:38:27.459226 DQS Delay:
2932 12:38:27.462389 DQS0 = 0, DQS1 = 0
2933 12:38:27.462509 DQM Delay:
2934 12:38:27.466220 DQM0 = 115, DQM1 = 106
2935 12:38:27.466301 DQ Delay:
2936 12:38:27.469110 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2937 12:38:27.472257 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2938 12:38:27.475902 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2939 12:38:27.478886 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2940 12:38:27.478968
2941 12:38:27.479051
2942 12:38:27.479114 ==
2943 12:38:27.482730 Dram Type= 6, Freq= 0, CH_0, rank 1
2944 12:38:27.486014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2945 12:38:27.489526 ==
2946 12:38:27.489616
2947 12:38:27.489678
2948 12:38:27.489737 TX Vref Scan disable
2949 12:38:27.492588 == TX Byte 0 ==
2950 12:38:27.495852 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2951 12:38:27.499603 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2952 12:38:27.502456 == TX Byte 1 ==
2953 12:38:27.506073 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2954 12:38:27.509207 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2955 12:38:27.509296 ==
2956 12:38:27.512722 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 12:38:27.519284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 12:38:27.519382 ==
2959 12:38:27.530161 TX Vref=22, minBit 3, minWin=25, winSum=426
2960 12:38:27.533460 TX Vref=24, minBit 1, minWin=26, winSum=432
2961 12:38:27.536573 TX Vref=26, minBit 12, minWin=26, winSum=434
2962 12:38:27.540281 TX Vref=28, minBit 3, minWin=26, winSum=437
2963 12:38:27.543422 TX Vref=30, minBit 3, minWin=26, winSum=434
2964 12:38:27.546871 TX Vref=32, minBit 5, minWin=26, winSum=435
2965 12:38:27.553777 [TxChooseVref] Worse bit 3, Min win 26, Win sum 437, Final Vref 28
2966 12:38:27.553889
2967 12:38:27.557283 Final TX Range 1 Vref 28
2968 12:38:27.557365
2969 12:38:27.557430 ==
2970 12:38:27.560495 Dram Type= 6, Freq= 0, CH_0, rank 1
2971 12:38:27.563327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2972 12:38:27.563426 ==
2973 12:38:27.563518
2974 12:38:27.563604
2975 12:38:27.566560 TX Vref Scan disable
2976 12:38:27.570759 == TX Byte 0 ==
2977 12:38:27.573939 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2978 12:38:27.576716 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2979 12:38:27.580335 == TX Byte 1 ==
2980 12:38:27.583856 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2981 12:38:27.586675 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2982 12:38:27.586812
2983 12:38:27.590694 [DATLAT]
2984 12:38:27.590800 Freq=1200, CH0 RK1
2985 12:38:27.590891
2986 12:38:27.593990 DATLAT Default: 0xd
2987 12:38:27.594102 0, 0xFFFF, sum = 0
2988 12:38:27.597247 1, 0xFFFF, sum = 0
2989 12:38:27.597375 2, 0xFFFF, sum = 0
2990 12:38:27.600140 3, 0xFFFF, sum = 0
2991 12:38:27.600234 4, 0xFFFF, sum = 0
2992 12:38:27.603744 5, 0xFFFF, sum = 0
2993 12:38:27.603852 6, 0xFFFF, sum = 0
2994 12:38:27.607048 7, 0xFFFF, sum = 0
2995 12:38:27.607146 8, 0xFFFF, sum = 0
2996 12:38:27.611034 9, 0xFFFF, sum = 0
2997 12:38:27.611239 10, 0xFFFF, sum = 0
2998 12:38:27.613548 11, 0xFFFF, sum = 0
2999 12:38:27.613699 12, 0x0, sum = 1
3000 12:38:27.617115 13, 0x0, sum = 2
3001 12:38:27.617299 14, 0x0, sum = 3
3002 12:38:27.620828 15, 0x0, sum = 4
3003 12:38:27.621059 best_step = 13
3004 12:38:27.621177
3005 12:38:27.621309 ==
3006 12:38:27.624027 Dram Type= 6, Freq= 0, CH_0, rank 1
3007 12:38:27.630584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3008 12:38:27.630776 ==
3009 12:38:27.630915 RX Vref Scan: 0
3010 12:38:27.631043
3011 12:38:27.633885 RX Vref 0 -> 0, step: 1
3012 12:38:27.634022
3013 12:38:27.636847 RX Delay -21 -> 252, step: 4
3014 12:38:27.641029 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3015 12:38:27.644045 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3016 12:38:27.650597 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3017 12:38:27.653690 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3018 12:38:27.657190 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3019 12:38:27.660831 iDelay=195, Bit 5, Center 106 (39 ~ 174) 136
3020 12:38:27.663978 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3021 12:38:27.667499 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3022 12:38:27.674334 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3023 12:38:27.677564 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3024 12:38:27.680837 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3025 12:38:27.684565 iDelay=195, Bit 11, Center 96 (31 ~ 162) 132
3026 12:38:27.687614 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3027 12:38:27.694722 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3028 12:38:27.697486 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3029 12:38:27.701265 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3030 12:38:27.701346 ==
3031 12:38:27.704330 Dram Type= 6, Freq= 0, CH_0, rank 1
3032 12:38:27.708245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3033 12:38:27.708325 ==
3034 12:38:27.711136 DQS Delay:
3035 12:38:27.711239 DQS0 = 0, DQS1 = 0
3036 12:38:27.711303 DQM Delay:
3037 12:38:27.714309 DQM0 = 114, DQM1 = 104
3038 12:38:27.714435 DQ Delay:
3039 12:38:27.718169 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3040 12:38:27.721373 DQ4 =112, DQ5 =106, DQ6 =122, DQ7 =122
3041 12:38:27.724588 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
3042 12:38:27.730693 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3043 12:38:27.730777
3044 12:38:27.730840
3045 12:38:27.737987 [DQSOSCAuto] RK1, (LSB)MR18= 0x4f5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 408 ps
3046 12:38:27.741214 CH0 RK1: MR19=403, MR18=4F5
3047 12:38:27.747631 CH0_RK1: MR19=0x403, MR18=0x4F5, DQSOSC=408, MR23=63, INC=39, DEC=26
3048 12:38:27.751624 [RxdqsGatingPostProcess] freq 1200
3049 12:38:27.754188 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3050 12:38:27.757597 best DQS0 dly(2T, 0.5T) = (0, 12)
3051 12:38:27.761722 best DQS1 dly(2T, 0.5T) = (0, 12)
3052 12:38:27.765081 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3053 12:38:27.767714 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3054 12:38:27.771201 best DQS0 dly(2T, 0.5T) = (0, 11)
3055 12:38:27.774804 best DQS1 dly(2T, 0.5T) = (0, 11)
3056 12:38:27.778141 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3057 12:38:27.781597 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3058 12:38:27.784588 Pre-setting of DQS Precalculation
3059 12:38:27.788342 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3060 12:38:27.788424 ==
3061 12:38:27.791436 Dram Type= 6, Freq= 0, CH_1, rank 0
3062 12:38:27.795005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3063 12:38:27.795085 ==
3064 12:38:27.801170 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3065 12:38:27.808122 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3066 12:38:27.815419 [CA 0] Center 38 (9~68) winsize 60
3067 12:38:27.818779 [CA 1] Center 38 (8~68) winsize 61
3068 12:38:27.822776 [CA 2] Center 35 (5~65) winsize 61
3069 12:38:27.825864 [CA 3] Center 34 (4~65) winsize 62
3070 12:38:27.829499 [CA 4] Center 34 (4~65) winsize 62
3071 12:38:27.832464 [CA 5] Center 34 (4~64) winsize 61
3072 12:38:27.832546
3073 12:38:27.835839 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3074 12:38:27.835918
3075 12:38:27.839293 [CATrainingPosCal] consider 1 rank data
3076 12:38:27.842617 u2DelayCellTimex100 = 270/100 ps
3077 12:38:27.845933 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3078 12:38:27.849441 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3079 12:38:27.852551 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3080 12:38:27.859155 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3081 12:38:27.862557 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3082 12:38:27.865888 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3083 12:38:27.865996
3084 12:38:27.869031 CA PerBit enable=1, Macro0, CA PI delay=34
3085 12:38:27.869114
3086 12:38:27.872984 [CBTSetCACLKResult] CA Dly = 34
3087 12:38:27.873065 CS Dly: 6 (0~37)
3088 12:38:27.873128 ==
3089 12:38:27.875913 Dram Type= 6, Freq= 0, CH_1, rank 1
3090 12:38:27.883132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3091 12:38:27.883235 ==
3092 12:38:27.886488 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3093 12:38:27.892462 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3094 12:38:27.901001 [CA 0] Center 38 (8~68) winsize 61
3095 12:38:27.904580 [CA 1] Center 37 (8~67) winsize 60
3096 12:38:27.907847 [CA 2] Center 34 (4~65) winsize 62
3097 12:38:27.911728 [CA 3] Center 34 (3~65) winsize 63
3098 12:38:27.915004 [CA 4] Center 34 (4~65) winsize 62
3099 12:38:27.918023 [CA 5] Center 33 (3~64) winsize 62
3100 12:38:27.918103
3101 12:38:27.921157 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3102 12:38:27.921237
3103 12:38:27.924679 [CATrainingPosCal] consider 2 rank data
3104 12:38:27.927874 u2DelayCellTimex100 = 270/100 ps
3105 12:38:27.931289 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3106 12:38:27.934378 CA1 delay=37 (8~67),Diff = 3 PI (14 cell)
3107 12:38:27.938038 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3108 12:38:27.944538 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3109 12:38:27.948491 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3110 12:38:27.951220 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3111 12:38:27.951299
3112 12:38:27.954726 CA PerBit enable=1, Macro0, CA PI delay=34
3113 12:38:27.954807
3114 12:38:27.958561 [CBTSetCACLKResult] CA Dly = 34
3115 12:38:27.958642 CS Dly: 7 (0~40)
3116 12:38:27.958705
3117 12:38:27.961784 ----->DramcWriteLeveling(PI) begin...
3118 12:38:27.961891 ==
3119 12:38:27.964941 Dram Type= 6, Freq= 0, CH_1, rank 0
3120 12:38:27.972281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3121 12:38:27.972368 ==
3122 12:38:27.975190 Write leveling (Byte 0): 26 => 26
3123 12:38:27.978859 Write leveling (Byte 1): 29 => 29
3124 12:38:27.978948 DramcWriteLeveling(PI) end<-----
3125 12:38:27.979013
3126 12:38:27.981791 ==
3127 12:38:27.985089 Dram Type= 6, Freq= 0, CH_1, rank 0
3128 12:38:27.988535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3129 12:38:27.988619 ==
3130 12:38:27.991579 [Gating] SW mode calibration
3131 12:38:27.998786 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3132 12:38:28.001891 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3133 12:38:28.008531 0 15 0 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3134 12:38:28.012015 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (0 0) (0 0)
3135 12:38:28.015574 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 12:38:28.019265 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 12:38:28.025670 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 12:38:28.029114 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 12:38:28.032082 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 12:38:28.038581 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3141 12:38:28.042393 1 0 0 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
3142 12:38:28.045368 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 12:38:28.052357 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 12:38:28.055551 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 12:38:28.059247 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 12:38:28.065561 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 12:38:28.069095 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 12:38:28.072128 1 0 28 | B1->B0 | 2e2e 2727 | 0 0 | (0 0) (0 0)
3149 12:38:28.075573 1 1 0 | B1->B0 | 4444 3a3a | 0 0 | (0 0) (0 0)
3150 12:38:28.082592 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 12:38:28.085997 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 12:38:28.089469 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 12:38:28.095954 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 12:38:28.099170 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 12:38:28.102734 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 12:38:28.109358 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3157 12:38:28.113083 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3158 12:38:28.115966 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 12:38:28.122416 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 12:38:28.125769 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 12:38:28.129800 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 12:38:28.136203 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 12:38:28.139227 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 12:38:28.143018 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 12:38:28.146277 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 12:38:28.152741 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 12:38:28.156329 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 12:38:28.159492 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 12:38:28.165970 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 12:38:28.169759 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 12:38:28.172854 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 12:38:28.179747 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3173 12:38:28.182929 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3174 12:38:28.186753 Total UI for P1: 0, mck2ui 16
3175 12:38:28.189650 best dqsien dly found for B1: ( 1, 3, 28)
3176 12:38:28.193626 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3177 12:38:28.196158 Total UI for P1: 0, mck2ui 16
3178 12:38:28.199747 best dqsien dly found for B0: ( 1, 3, 30)
3179 12:38:28.202844 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3180 12:38:28.206725 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3181 12:38:28.206815
3182 12:38:28.209512 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3183 12:38:28.217065 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3184 12:38:28.217179 [Gating] SW calibration Done
3185 12:38:28.217268 ==
3186 12:38:28.219932 Dram Type= 6, Freq= 0, CH_1, rank 0
3187 12:38:28.226686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3188 12:38:28.226788 ==
3189 12:38:28.226885 RX Vref Scan: 0
3190 12:38:28.226950
3191 12:38:28.229924 RX Vref 0 -> 0, step: 1
3192 12:38:28.229995
3193 12:38:28.233348 RX Delay -40 -> 252, step: 8
3194 12:38:28.236304 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3195 12:38:28.240221 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3196 12:38:28.243685 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3197 12:38:28.246625 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3198 12:38:28.253715 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3199 12:38:28.256791 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3200 12:38:28.259972 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3201 12:38:28.263521 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3202 12:38:28.266619 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3203 12:38:28.270368 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3204 12:38:28.276959 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3205 12:38:28.280371 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3206 12:38:28.283785 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3207 12:38:28.287248 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3208 12:38:28.293915 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3209 12:38:28.296813 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3210 12:38:28.296909 ==
3211 12:38:28.300520 Dram Type= 6, Freq= 0, CH_1, rank 0
3212 12:38:28.304013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3213 12:38:28.304110 ==
3214 12:38:28.304205 DQS Delay:
3215 12:38:28.306795 DQS0 = 0, DQS1 = 0
3216 12:38:28.306896 DQM Delay:
3217 12:38:28.310199 DQM0 = 116, DQM1 = 109
3218 12:38:28.310294 DQ Delay:
3219 12:38:28.313610 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3220 12:38:28.317177 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3221 12:38:28.320746 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3222 12:38:28.324046 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =115
3223 12:38:28.324139
3224 12:38:28.324235
3225 12:38:28.327802 ==
3226 12:38:28.327896 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 12:38:28.333952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 12:38:28.334025 ==
3229 12:38:28.334086
3230 12:38:28.334180
3231 12:38:28.337509 TX Vref Scan disable
3232 12:38:28.337590 == TX Byte 0 ==
3233 12:38:28.341236 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3234 12:38:28.347266 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3235 12:38:28.347341 == TX Byte 1 ==
3236 12:38:28.350945 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3237 12:38:28.358129 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3238 12:38:28.358214 ==
3239 12:38:28.361244 Dram Type= 6, Freq= 0, CH_1, rank 0
3240 12:38:28.364112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3241 12:38:28.364197 ==
3242 12:38:28.375848 TX Vref=22, minBit 0, minWin=25, winSum=409
3243 12:38:28.379236 TX Vref=24, minBit 2, minWin=25, winSum=414
3244 12:38:28.382419 TX Vref=26, minBit 8, minWin=25, winSum=420
3245 12:38:28.385723 TX Vref=28, minBit 8, minWin=25, winSum=427
3246 12:38:28.389036 TX Vref=30, minBit 0, minWin=26, winSum=426
3247 12:38:28.392575 TX Vref=32, minBit 2, minWin=26, winSum=427
3248 12:38:28.399633 [TxChooseVref] Worse bit 2, Min win 26, Win sum 427, Final Vref 32
3249 12:38:28.399718
3250 12:38:28.403264 Final TX Range 1 Vref 32
3251 12:38:28.403349
3252 12:38:28.403433 ==
3253 12:38:28.406452 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 12:38:28.409525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 12:38:28.409609 ==
3256 12:38:28.409694
3257 12:38:28.409774
3258 12:38:28.412664 TX Vref Scan disable
3259 12:38:28.416558 == TX Byte 0 ==
3260 12:38:28.419600 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3261 12:38:28.422900 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3262 12:38:28.426681 == TX Byte 1 ==
3263 12:38:28.429922 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3264 12:38:28.433414 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3265 12:38:28.433497
3266 12:38:28.436819 [DATLAT]
3267 12:38:28.436975 Freq=1200, CH1 RK0
3268 12:38:28.437054
3269 12:38:28.439698 DATLAT Default: 0xd
3270 12:38:28.439777 0, 0xFFFF, sum = 0
3271 12:38:28.443615 1, 0xFFFF, sum = 0
3272 12:38:28.443713 2, 0xFFFF, sum = 0
3273 12:38:28.446126 3, 0xFFFF, sum = 0
3274 12:38:28.446207 4, 0xFFFF, sum = 0
3275 12:38:28.449544 5, 0xFFFF, sum = 0
3276 12:38:28.449642 6, 0xFFFF, sum = 0
3277 12:38:28.453171 7, 0xFFFF, sum = 0
3278 12:38:28.453253 8, 0xFFFF, sum = 0
3279 12:38:28.457387 9, 0xFFFF, sum = 0
3280 12:38:28.457472 10, 0xFFFF, sum = 0
3281 12:38:28.459773 11, 0xFFFF, sum = 0
3282 12:38:28.459857 12, 0x0, sum = 1
3283 12:38:28.463047 13, 0x0, sum = 2
3284 12:38:28.463128 14, 0x0, sum = 3
3285 12:38:28.466874 15, 0x0, sum = 4
3286 12:38:28.466982 best_step = 13
3287 12:38:28.467072
3288 12:38:28.467159 ==
3289 12:38:28.470094 Dram Type= 6, Freq= 0, CH_1, rank 0
3290 12:38:28.476645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3291 12:38:28.476752 ==
3292 12:38:28.476851 RX Vref Scan: 1
3293 12:38:28.476916
3294 12:38:28.479713 Set Vref Range= 32 -> 127
3295 12:38:28.479793
3296 12:38:28.483160 RX Vref 32 -> 127, step: 1
3297 12:38:28.483243
3298 12:38:28.483328 RX Delay -21 -> 252, step: 4
3299 12:38:28.483409
3300 12:38:28.486197 Set Vref, RX VrefLevel [Byte0]: 32
3301 12:38:28.489933 [Byte1]: 32
3302 12:38:28.493996
3303 12:38:28.494078 Set Vref, RX VrefLevel [Byte0]: 33
3304 12:38:28.497092 [Byte1]: 33
3305 12:38:28.501961
3306 12:38:28.502044 Set Vref, RX VrefLevel [Byte0]: 34
3307 12:38:28.505121 [Byte1]: 34
3308 12:38:28.510613
3309 12:38:28.510697 Set Vref, RX VrefLevel [Byte0]: 35
3310 12:38:28.512989 [Byte1]: 35
3311 12:38:28.517929
3312 12:38:28.518011 Set Vref, RX VrefLevel [Byte0]: 36
3313 12:38:28.521353 [Byte1]: 36
3314 12:38:28.525960
3315 12:38:28.526043 Set Vref, RX VrefLevel [Byte0]: 37
3316 12:38:28.529035 [Byte1]: 37
3317 12:38:28.533679
3318 12:38:28.533761 Set Vref, RX VrefLevel [Byte0]: 38
3319 12:38:28.537472 [Byte1]: 38
3320 12:38:28.541738
3321 12:38:28.541821 Set Vref, RX VrefLevel [Byte0]: 39
3322 12:38:28.544794 [Byte1]: 39
3323 12:38:28.549760
3324 12:38:28.549849 Set Vref, RX VrefLevel [Byte0]: 40
3325 12:38:28.553045 [Byte1]: 40
3326 12:38:28.557613
3327 12:38:28.557696 Set Vref, RX VrefLevel [Byte0]: 41
3328 12:38:28.560813 [Byte1]: 41
3329 12:38:28.565611
3330 12:38:28.565696 Set Vref, RX VrefLevel [Byte0]: 42
3331 12:38:28.568770 [Byte1]: 42
3332 12:38:28.573473
3333 12:38:28.573556 Set Vref, RX VrefLevel [Byte0]: 43
3334 12:38:28.576801 [Byte1]: 43
3335 12:38:28.581192
3336 12:38:28.581275 Set Vref, RX VrefLevel [Byte0]: 44
3337 12:38:28.584368 [Byte1]: 44
3338 12:38:28.589141
3339 12:38:28.589230 Set Vref, RX VrefLevel [Byte0]: 45
3340 12:38:28.595328 [Byte1]: 45
3341 12:38:28.595407
3342 12:38:28.598683 Set Vref, RX VrefLevel [Byte0]: 46
3343 12:38:28.602149 [Byte1]: 46
3344 12:38:28.602259
3345 12:38:28.605611 Set Vref, RX VrefLevel [Byte0]: 47
3346 12:38:28.608971 [Byte1]: 47
3347 12:38:28.612727
3348 12:38:28.612807 Set Vref, RX VrefLevel [Byte0]: 48
3349 12:38:28.616251 [Byte1]: 48
3350 12:38:28.620731
3351 12:38:28.620810 Set Vref, RX VrefLevel [Byte0]: 49
3352 12:38:28.624502 [Byte1]: 49
3353 12:38:28.629106
3354 12:38:28.629189 Set Vref, RX VrefLevel [Byte0]: 50
3355 12:38:28.632097 [Byte1]: 50
3356 12:38:28.636360
3357 12:38:28.636439 Set Vref, RX VrefLevel [Byte0]: 51
3358 12:38:28.639643 [Byte1]: 51
3359 12:38:28.644397
3360 12:38:28.644475 Set Vref, RX VrefLevel [Byte0]: 52
3361 12:38:28.647970 [Byte1]: 52
3362 12:38:28.652200
3363 12:38:28.652275 Set Vref, RX VrefLevel [Byte0]: 53
3364 12:38:28.655541 [Byte1]: 53
3365 12:38:28.660041
3366 12:38:28.660120 Set Vref, RX VrefLevel [Byte0]: 54
3367 12:38:28.663400 [Byte1]: 54
3368 12:38:28.668080
3369 12:38:28.668162 Set Vref, RX VrefLevel [Byte0]: 55
3370 12:38:28.671453 [Byte1]: 55
3371 12:38:28.676065
3372 12:38:28.676144 Set Vref, RX VrefLevel [Byte0]: 56
3373 12:38:28.679712 [Byte1]: 56
3374 12:38:28.684046
3375 12:38:28.684125 Set Vref, RX VrefLevel [Byte0]: 57
3376 12:38:28.687264 [Byte1]: 57
3377 12:38:28.691793
3378 12:38:28.691871 Set Vref, RX VrefLevel [Byte0]: 58
3379 12:38:28.695185 [Byte1]: 58
3380 12:38:28.700543
3381 12:38:28.700631 Set Vref, RX VrefLevel [Byte0]: 59
3382 12:38:28.702917 [Byte1]: 59
3383 12:38:28.707518
3384 12:38:28.707599 Set Vref, RX VrefLevel [Byte0]: 60
3385 12:38:28.711424 [Byte1]: 60
3386 12:38:28.715578
3387 12:38:28.715660 Set Vref, RX VrefLevel [Byte0]: 61
3388 12:38:28.719144 [Byte1]: 61
3389 12:38:28.724141
3390 12:38:28.724214 Set Vref, RX VrefLevel [Byte0]: 62
3391 12:38:28.727348 [Byte1]: 62
3392 12:38:28.731573
3393 12:38:28.731696 Set Vref, RX VrefLevel [Byte0]: 63
3394 12:38:28.734633 [Byte1]: 63
3395 12:38:28.739520
3396 12:38:28.739671 Set Vref, RX VrefLevel [Byte0]: 64
3397 12:38:28.742673 [Byte1]: 64
3398 12:38:28.747022
3399 12:38:28.747129 Set Vref, RX VrefLevel [Byte0]: 65
3400 12:38:28.750746 [Byte1]: 65
3401 12:38:28.755399
3402 12:38:28.755551 Set Vref, RX VrefLevel [Byte0]: 66
3403 12:38:28.758924 [Byte1]: 66
3404 12:38:28.762969
3405 12:38:28.763070 Set Vref, RX VrefLevel [Byte0]: 67
3406 12:38:28.766286 [Byte1]: 67
3407 12:38:28.771408
3408 12:38:28.771537 Set Vref, RX VrefLevel [Byte0]: 68
3409 12:38:28.774933 [Byte1]: 68
3410 12:38:28.779266
3411 12:38:28.779419 Set Vref, RX VrefLevel [Byte0]: 69
3412 12:38:28.782125 [Byte1]: 69
3413 12:38:28.786949
3414 12:38:28.787051 Set Vref, RX VrefLevel [Byte0]: 70
3415 12:38:28.790357 [Byte1]: 70
3416 12:38:28.794564
3417 12:38:28.794643 Final RX Vref Byte 0 = 56 to rank0
3418 12:38:28.798166 Final RX Vref Byte 1 = 51 to rank0
3419 12:38:28.801520 Final RX Vref Byte 0 = 56 to rank1
3420 12:38:28.804990 Final RX Vref Byte 1 = 51 to rank1==
3421 12:38:28.808713 Dram Type= 6, Freq= 0, CH_1, rank 0
3422 12:38:28.811666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3423 12:38:28.814811 ==
3424 12:38:28.814916 DQS Delay:
3425 12:38:28.815005 DQS0 = 0, DQS1 = 0
3426 12:38:28.818265 DQM Delay:
3427 12:38:28.818369 DQM0 = 115, DQM1 = 108
3428 12:38:28.821755 DQ Delay:
3429 12:38:28.825110 DQ0 =118, DQ1 =108, DQ2 =106, DQ3 =112
3430 12:38:28.828475 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =112
3431 12:38:28.831713 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =104
3432 12:38:28.834962 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =114
3433 12:38:28.835056
3434 12:38:28.835123
3435 12:38:28.841749 [DQSOSCAuto] RK0, (LSB)MR18= 0xe5, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
3436 12:38:28.845014 CH1 RK0: MR19=403, MR18=E5
3437 12:38:28.851766 CH1_RK0: MR19=0x403, MR18=0xE5, DQSOSC=410, MR23=63, INC=39, DEC=26
3438 12:38:28.851842
3439 12:38:28.855947 ----->DramcWriteLeveling(PI) begin...
3440 12:38:28.856024 ==
3441 12:38:28.858736 Dram Type= 6, Freq= 0, CH_1, rank 1
3442 12:38:28.861799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3443 12:38:28.861874 ==
3444 12:38:28.865701 Write leveling (Byte 0): 26 => 26
3445 12:38:28.868891 Write leveling (Byte 1): 30 => 30
3446 12:38:28.871643 DramcWriteLeveling(PI) end<-----
3447 12:38:28.871725
3448 12:38:28.871789 ==
3449 12:38:28.875429 Dram Type= 6, Freq= 0, CH_1, rank 1
3450 12:38:28.878623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3451 12:38:28.878704 ==
3452 12:38:28.882100 [Gating] SW mode calibration
3453 12:38:28.888811 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3454 12:38:28.895000 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3455 12:38:28.898249 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3456 12:38:28.901690 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3457 12:38:28.908920 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3458 12:38:28.912262 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3459 12:38:28.915309 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3460 12:38:28.921869 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3461 12:38:28.925182 0 15 24 | B1->B0 | 3333 2e2e | 1 0 | (0 0) (1 0)
3462 12:38:28.928596 0 15 28 | B1->B0 | 2a2a 2323 | 1 0 | (1 1) (1 0)
3463 12:38:28.935802 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 12:38:28.938764 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 12:38:28.942591 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3466 12:38:28.949031 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3467 12:38:28.952056 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 12:38:28.955661 1 0 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3469 12:38:28.962301 1 0 24 | B1->B0 | 2525 3a3a | 0 1 | (0 0) (0 0)
3470 12:38:28.965397 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3471 12:38:28.969504 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 12:38:28.975557 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 12:38:28.978767 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 12:38:28.982064 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 12:38:28.985562 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 12:38:28.992170 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 12:38:28.995751 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3478 12:38:28.998661 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3479 12:38:29.005814 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3480 12:38:29.008757 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 12:38:29.012584 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 12:38:29.019221 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 12:38:29.021869 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 12:38:29.025389 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 12:38:29.032539 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 12:38:29.035649 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 12:38:29.039040 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 12:38:29.045509 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 12:38:29.048609 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 12:38:29.051859 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 12:38:29.058606 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 12:38:29.062300 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 12:38:29.065513 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3494 12:38:29.072460 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3495 12:38:29.072538 Total UI for P1: 0, mck2ui 16
3496 12:38:29.075616 best dqsien dly found for B0: ( 1, 3, 24)
3497 12:38:29.082097 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3498 12:38:29.085557 Total UI for P1: 0, mck2ui 16
3499 12:38:29.088683 best dqsien dly found for B1: ( 1, 3, 28)
3500 12:38:29.092022 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3501 12:38:29.095489 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3502 12:38:29.095570
3503 12:38:29.099207 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3504 12:38:29.102238 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3505 12:38:29.105697 [Gating] SW calibration Done
3506 12:38:29.105834 ==
3507 12:38:29.109192 Dram Type= 6, Freq= 0, CH_1, rank 1
3508 12:38:29.112206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3509 12:38:29.112294 ==
3510 12:38:29.115615 RX Vref Scan: 0
3511 12:38:29.115699
3512 12:38:29.115764 RX Vref 0 -> 0, step: 1
3513 12:38:29.119108
3514 12:38:29.119191 RX Delay -40 -> 252, step: 8
3515 12:38:29.125318 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3516 12:38:29.128657 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3517 12:38:29.132198 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3518 12:38:29.135301 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3519 12:38:29.138950 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3520 12:38:29.142314 iDelay=200, Bit 5, Center 123 (56 ~ 191) 136
3521 12:38:29.148832 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3522 12:38:29.151993 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3523 12:38:29.155545 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
3524 12:38:29.158863 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3525 12:38:29.162094 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3526 12:38:29.168834 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3527 12:38:29.172187 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3528 12:38:29.175709 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3529 12:38:29.179221 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3530 12:38:29.181971 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3531 12:38:29.185736 ==
3532 12:38:29.188814 Dram Type= 6, Freq= 0, CH_1, rank 1
3533 12:38:29.192312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3534 12:38:29.192395 ==
3535 12:38:29.192461 DQS Delay:
3536 12:38:29.195563 DQS0 = 0, DQS1 = 0
3537 12:38:29.195645 DQM Delay:
3538 12:38:29.198719 DQM0 = 113, DQM1 = 110
3539 12:38:29.198802 DQ Delay:
3540 12:38:29.202781 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3541 12:38:29.205603 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =107
3542 12:38:29.209000 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3543 12:38:29.212061 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3544 12:38:29.212144
3545 12:38:29.212209
3546 12:38:29.212269 ==
3547 12:38:29.215753 Dram Type= 6, Freq= 0, CH_1, rank 1
3548 12:38:29.222687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3549 12:38:29.222768 ==
3550 12:38:29.222832
3551 12:38:29.222892
3552 12:38:29.222949 TX Vref Scan disable
3553 12:38:29.225455 == TX Byte 0 ==
3554 12:38:29.229104 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3555 12:38:29.232297 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3556 12:38:29.235744 == TX Byte 1 ==
3557 12:38:29.238974 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3558 12:38:29.242391 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3559 12:38:29.245845 ==
3560 12:38:29.245917 Dram Type= 6, Freq= 0, CH_1, rank 1
3561 12:38:29.252283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3562 12:38:29.252364 ==
3563 12:38:29.263408 TX Vref=22, minBit 1, minWin=25, winSum=416
3564 12:38:29.266992 TX Vref=24, minBit 0, minWin=25, winSum=422
3565 12:38:29.270132 TX Vref=26, minBit 0, minWin=26, winSum=432
3566 12:38:29.273267 TX Vref=28, minBit 1, minWin=26, winSum=433
3567 12:38:29.277109 TX Vref=30, minBit 4, minWin=26, winSum=439
3568 12:38:29.279904 TX Vref=32, minBit 1, minWin=26, winSum=433
3569 12:38:29.286692 [TxChooseVref] Worse bit 4, Min win 26, Win sum 439, Final Vref 30
3570 12:38:29.286767
3571 12:38:29.290028 Final TX Range 1 Vref 30
3572 12:38:29.290126
3573 12:38:29.290222 ==
3574 12:38:29.293360 Dram Type= 6, Freq= 0, CH_1, rank 1
3575 12:38:29.296970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3576 12:38:29.297075 ==
3577 12:38:29.297164
3578 12:38:29.297248
3579 12:38:29.300790 TX Vref Scan disable
3580 12:38:29.303743 == TX Byte 0 ==
3581 12:38:29.307000 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3582 12:38:29.310548 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3583 12:38:29.314353 == TX Byte 1 ==
3584 12:38:29.317031 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3585 12:38:29.320207 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3586 12:38:29.320302
3587 12:38:29.323222 [DATLAT]
3588 12:38:29.323302 Freq=1200, CH1 RK1
3589 12:38:29.323367
3590 12:38:29.326823 DATLAT Default: 0xd
3591 12:38:29.326903 0, 0xFFFF, sum = 0
3592 12:38:29.329987 1, 0xFFFF, sum = 0
3593 12:38:29.330068 2, 0xFFFF, sum = 0
3594 12:38:29.333746 3, 0xFFFF, sum = 0
3595 12:38:29.333827 4, 0xFFFF, sum = 0
3596 12:38:29.336854 5, 0xFFFF, sum = 0
3597 12:38:29.336936 6, 0xFFFF, sum = 0
3598 12:38:29.340077 7, 0xFFFF, sum = 0
3599 12:38:29.343103 8, 0xFFFF, sum = 0
3600 12:38:29.343184 9, 0xFFFF, sum = 0
3601 12:38:29.346857 10, 0xFFFF, sum = 0
3602 12:38:29.346938 11, 0xFFFF, sum = 0
3603 12:38:29.350274 12, 0x0, sum = 1
3604 12:38:29.350355 13, 0x0, sum = 2
3605 12:38:29.353120 14, 0x0, sum = 3
3606 12:38:29.353201 15, 0x0, sum = 4
3607 12:38:29.353266 best_step = 13
3608 12:38:29.353324
3609 12:38:29.356677 ==
3610 12:38:29.359742 Dram Type= 6, Freq= 0, CH_1, rank 1
3611 12:38:29.363397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3612 12:38:29.363478 ==
3613 12:38:29.363543 RX Vref Scan: 0
3614 12:38:29.363601
3615 12:38:29.366548 RX Vref 0 -> 0, step: 1
3616 12:38:29.366629
3617 12:38:29.370266 RX Delay -21 -> 252, step: 4
3618 12:38:29.373419 iDelay=191, Bit 0, Center 114 (47 ~ 182) 136
3619 12:38:29.380041 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3620 12:38:29.383564 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3621 12:38:29.386520 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3622 12:38:29.389903 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3623 12:38:29.393256 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3624 12:38:29.396694 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3625 12:38:29.403442 iDelay=191, Bit 7, Center 112 (47 ~ 178) 132
3626 12:38:29.406743 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3627 12:38:29.410214 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3628 12:38:29.413782 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3629 12:38:29.416868 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3630 12:38:29.423297 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3631 12:38:29.426814 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3632 12:38:29.430542 iDelay=191, Bit 14, Center 116 (51 ~ 182) 132
3633 12:38:29.433629 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3634 12:38:29.433709 ==
3635 12:38:29.436823 Dram Type= 6, Freq= 0, CH_1, rank 1
3636 12:38:29.443421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3637 12:38:29.443502 ==
3638 12:38:29.443566 DQS Delay:
3639 12:38:29.443624 DQS0 = 0, DQS1 = 0
3640 12:38:29.446833 DQM Delay:
3641 12:38:29.446913 DQM0 = 114, DQM1 = 109
3642 12:38:29.450316 DQ Delay:
3643 12:38:29.453282 DQ0 =114, DQ1 =110, DQ2 =104, DQ3 =112
3644 12:38:29.456752 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3645 12:38:29.459969 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3646 12:38:29.463441 DQ12 =114, DQ13 =120, DQ14 =116, DQ15 =116
3647 12:38:29.463521
3648 12:38:29.463584
3649 12:38:29.470031 [DQSOSCAuto] RK1, (LSB)MR18= 0xf901, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 412 ps
3650 12:38:29.474116 CH1 RK1: MR19=304, MR18=F901
3651 12:38:29.480281 CH1_RK1: MR19=0x304, MR18=0xF901, DQSOSC=409, MR23=63, INC=39, DEC=26
3652 12:38:29.483310 [RxdqsGatingPostProcess] freq 1200
3653 12:38:29.490256 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3654 12:38:29.493917 best DQS0 dly(2T, 0.5T) = (0, 11)
3655 12:38:29.493999 best DQS1 dly(2T, 0.5T) = (0, 11)
3656 12:38:29.496956 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3657 12:38:29.500171 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3658 12:38:29.503603 best DQS0 dly(2T, 0.5T) = (0, 11)
3659 12:38:29.506835 best DQS1 dly(2T, 0.5T) = (0, 11)
3660 12:38:29.510067 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3661 12:38:29.513454 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3662 12:38:29.516502 Pre-setting of DQS Precalculation
3663 12:38:29.523344 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3664 12:38:29.530264 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3665 12:38:29.537082 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3666 12:38:29.537163
3667 12:38:29.537226
3668 12:38:29.540461 [Calibration Summary] 2400 Mbps
3669 12:38:29.540542 CH 0, Rank 0
3670 12:38:29.543708 SW Impedance : PASS
3671 12:38:29.546784 DUTY Scan : NO K
3672 12:38:29.546865 ZQ Calibration : PASS
3673 12:38:29.550425 Jitter Meter : NO K
3674 12:38:29.550519 CBT Training : PASS
3675 12:38:29.554242 Write leveling : PASS
3676 12:38:29.556789 RX DQS gating : PASS
3677 12:38:29.556870 RX DQ/DQS(RDDQC) : PASS
3678 12:38:29.560550 TX DQ/DQS : PASS
3679 12:38:29.563580 RX DATLAT : PASS
3680 12:38:29.563660 RX DQ/DQS(Engine): PASS
3681 12:38:29.567004 TX OE : NO K
3682 12:38:29.567085 All Pass.
3683 12:38:29.567149
3684 12:38:29.570960 CH 0, Rank 1
3685 12:38:29.571039 SW Impedance : PASS
3686 12:38:29.574104 DUTY Scan : NO K
3687 12:38:29.577218 ZQ Calibration : PASS
3688 12:38:29.577298 Jitter Meter : NO K
3689 12:38:29.580838 CBT Training : PASS
3690 12:38:29.583234 Write leveling : PASS
3691 12:38:29.583314 RX DQS gating : PASS
3692 12:38:29.586937 RX DQ/DQS(RDDQC) : PASS
3693 12:38:29.590056 TX DQ/DQS : PASS
3694 12:38:29.590137 RX DATLAT : PASS
3695 12:38:29.593320 RX DQ/DQS(Engine): PASS
3696 12:38:29.593400 TX OE : NO K
3697 12:38:29.597111 All Pass.
3698 12:38:29.597191
3699 12:38:29.597254 CH 1, Rank 0
3700 12:38:29.600448 SW Impedance : PASS
3701 12:38:29.600528 DUTY Scan : NO K
3702 12:38:29.603962 ZQ Calibration : PASS
3703 12:38:29.606689 Jitter Meter : NO K
3704 12:38:29.606770 CBT Training : PASS
3705 12:38:29.610065 Write leveling : PASS
3706 12:38:29.613390 RX DQS gating : PASS
3707 12:38:29.613470 RX DQ/DQS(RDDQC) : PASS
3708 12:38:29.617137 TX DQ/DQS : PASS
3709 12:38:29.620448 RX DATLAT : PASS
3710 12:38:29.620529 RX DQ/DQS(Engine): PASS
3711 12:38:29.623653 TX OE : NO K
3712 12:38:29.623734 All Pass.
3713 12:38:29.623797
3714 12:38:29.626662 CH 1, Rank 1
3715 12:38:29.626801 SW Impedance : PASS
3716 12:38:29.630417 DUTY Scan : NO K
3717 12:38:29.633391 ZQ Calibration : PASS
3718 12:38:29.633471 Jitter Meter : NO K
3719 12:38:29.636787 CBT Training : PASS
3720 12:38:29.636867 Write leveling : PASS
3721 12:38:29.640015 RX DQS gating : PASS
3722 12:38:29.643728 RX DQ/DQS(RDDQC) : PASS
3723 12:38:29.643808 TX DQ/DQS : PASS
3724 12:38:29.646580 RX DATLAT : PASS
3725 12:38:29.650240 RX DQ/DQS(Engine): PASS
3726 12:38:29.650320 TX OE : NO K
3727 12:38:29.653408 All Pass.
3728 12:38:29.653487
3729 12:38:29.653550 DramC Write-DBI off
3730 12:38:29.656961 PER_BANK_REFRESH: Hybrid Mode
3731 12:38:29.660313 TX_TRACKING: ON
3732 12:38:29.666905 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3733 12:38:29.669943 [FAST_K] Save calibration result to emmc
3734 12:38:29.673540 dramc_set_vcore_voltage set vcore to 650000
3735 12:38:29.676599 Read voltage for 600, 5
3736 12:38:29.676679 Vio18 = 0
3737 12:38:29.680254 Vcore = 650000
3738 12:38:29.680335 Vdram = 0
3739 12:38:29.680399 Vddq = 0
3740 12:38:29.683278 Vmddr = 0
3741 12:38:29.686778 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3742 12:38:29.693307 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3743 12:38:29.693389 MEM_TYPE=3, freq_sel=19
3744 12:38:29.696651 sv_algorithm_assistance_LP4_1600
3745 12:38:29.703404 ============ PULL DRAM RESETB DOWN ============
3746 12:38:29.706620 ========== PULL DRAM RESETB DOWN end =========
3747 12:38:29.710551 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3748 12:38:29.713097 ===================================
3749 12:38:29.716688 LPDDR4 DRAM CONFIGURATION
3750 12:38:29.720266 ===================================
3751 12:38:29.720347 EX_ROW_EN[0] = 0x0
3752 12:38:29.723261 EX_ROW_EN[1] = 0x0
3753 12:38:29.726941 LP4Y_EN = 0x0
3754 12:38:29.727022 WORK_FSP = 0x0
3755 12:38:29.729798 WL = 0x2
3756 12:38:29.729889 RL = 0x2
3757 12:38:29.733641 BL = 0x2
3758 12:38:29.733721 RPST = 0x0
3759 12:38:29.737216 RD_PRE = 0x0
3760 12:38:29.737295 WR_PRE = 0x1
3761 12:38:29.740305 WR_PST = 0x0
3762 12:38:29.740384 DBI_WR = 0x0
3763 12:38:29.743143 DBI_RD = 0x0
3764 12:38:29.743225 OTF = 0x1
3765 12:38:29.746715 ===================================
3766 12:38:29.750381 ===================================
3767 12:38:29.753208 ANA top config
3768 12:38:29.757049 ===================================
3769 12:38:29.757131 DLL_ASYNC_EN = 0
3770 12:38:29.760053 ALL_SLAVE_EN = 1
3771 12:38:29.763617 NEW_RANK_MODE = 1
3772 12:38:29.766544 DLL_IDLE_MODE = 1
3773 12:38:29.766627 LP45_APHY_COMB_EN = 1
3774 12:38:29.770138 TX_ODT_DIS = 1
3775 12:38:29.773223 NEW_8X_MODE = 1
3776 12:38:29.777347 ===================================
3777 12:38:29.780165 ===================================
3778 12:38:29.783471 data_rate = 1200
3779 12:38:29.786888 CKR = 1
3780 12:38:29.789893 DQ_P2S_RATIO = 8
3781 12:38:29.794010 ===================================
3782 12:38:29.794092 CA_P2S_RATIO = 8
3783 12:38:29.796967 DQ_CA_OPEN = 0
3784 12:38:29.800162 DQ_SEMI_OPEN = 0
3785 12:38:29.803798 CA_SEMI_OPEN = 0
3786 12:38:29.806660 CA_FULL_RATE = 0
3787 12:38:29.806741 DQ_CKDIV4_EN = 1
3788 12:38:29.810572 CA_CKDIV4_EN = 1
3789 12:38:29.813630 CA_PREDIV_EN = 0
3790 12:38:29.816586 PH8_DLY = 0
3791 12:38:29.820321 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3792 12:38:29.823479 DQ_AAMCK_DIV = 4
3793 12:38:29.823581 CA_AAMCK_DIV = 4
3794 12:38:29.827377 CA_ADMCK_DIV = 4
3795 12:38:29.830885 DQ_TRACK_CA_EN = 0
3796 12:38:29.833978 CA_PICK = 600
3797 12:38:29.837110 CA_MCKIO = 600
3798 12:38:29.840146 MCKIO_SEMI = 0
3799 12:38:29.843334 PLL_FREQ = 2288
3800 12:38:29.843434 DQ_UI_PI_RATIO = 32
3801 12:38:29.846707 CA_UI_PI_RATIO = 0
3802 12:38:29.850365 ===================================
3803 12:38:29.853779 ===================================
3804 12:38:29.857010 memory_type:LPDDR4
3805 12:38:29.860415 GP_NUM : 10
3806 12:38:29.860512 SRAM_EN : 1
3807 12:38:29.863645 MD32_EN : 0
3808 12:38:29.867148 ===================================
3809 12:38:29.867247 [ANA_INIT] >>>>>>>>>>>>>>
3810 12:38:29.870346 <<<<<< [CONFIGURE PHASE]: ANA_TX
3811 12:38:29.873520 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3812 12:38:29.876849 ===================================
3813 12:38:29.880546 data_rate = 1200,PCW = 0X5800
3814 12:38:29.883805 ===================================
3815 12:38:29.886689 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3816 12:38:29.893849 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3817 12:38:29.896698 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3818 12:38:29.903709 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3819 12:38:29.907385 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3820 12:38:29.910163 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3821 12:38:29.913322 [ANA_INIT] flow start
3822 12:38:29.913425 [ANA_INIT] PLL >>>>>>>>
3823 12:38:29.916976 [ANA_INIT] PLL <<<<<<<<
3824 12:38:29.920131 [ANA_INIT] MIDPI >>>>>>>>
3825 12:38:29.920227 [ANA_INIT] MIDPI <<<<<<<<
3826 12:38:29.923883 [ANA_INIT] DLL >>>>>>>>
3827 12:38:29.926822 [ANA_INIT] flow end
3828 12:38:29.930195 ============ LP4 DIFF to SE enter ============
3829 12:38:29.933720 ============ LP4 DIFF to SE exit ============
3830 12:38:29.937179 [ANA_INIT] <<<<<<<<<<<<<
3831 12:38:29.940167 [Flow] Enable top DCM control >>>>>
3832 12:38:29.943589 [Flow] Enable top DCM control <<<<<
3833 12:38:29.946888 Enable DLL master slave shuffle
3834 12:38:29.950023 ==============================================================
3835 12:38:29.953514 Gating Mode config
3836 12:38:29.956645 ==============================================================
3837 12:38:29.960249 Config description:
3838 12:38:29.970261 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3839 12:38:29.976686 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3840 12:38:29.980457 SELPH_MODE 0: By rank 1: By Phase
3841 12:38:29.986640 ==============================================================
3842 12:38:29.990133 GAT_TRACK_EN = 1
3843 12:38:29.993864 RX_GATING_MODE = 2
3844 12:38:29.996751 RX_GATING_TRACK_MODE = 2
3845 12:38:30.000530 SELPH_MODE = 1
3846 12:38:30.003884 PICG_EARLY_EN = 1
3847 12:38:30.003982 VALID_LAT_VALUE = 1
3848 12:38:30.010665 ==============================================================
3849 12:38:30.013719 Enter into Gating configuration >>>>
3850 12:38:30.017053 Exit from Gating configuration <<<<
3851 12:38:30.019872 Enter into DVFS_PRE_config >>>>>
3852 12:38:30.030617 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3853 12:38:30.033494 Exit from DVFS_PRE_config <<<<<
3854 12:38:30.037107 Enter into PICG configuration >>>>
3855 12:38:30.040281 Exit from PICG configuration <<<<
3856 12:38:30.043806 [RX_INPUT] configuration >>>>>
3857 12:38:30.046874 [RX_INPUT] configuration <<<<<
3858 12:38:30.050300 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3859 12:38:30.056995 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3860 12:38:30.063457 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3861 12:38:30.070509 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3862 12:38:30.076899 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3863 12:38:30.080409 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3864 12:38:30.086899 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3865 12:38:30.090880 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3866 12:38:30.093683 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3867 12:38:30.097466 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3868 12:38:30.100670 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3869 12:38:30.107217 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3870 12:38:30.110747 ===================================
3871 12:38:30.113695 LPDDR4 DRAM CONFIGURATION
3872 12:38:30.117203 ===================================
3873 12:38:30.117283 EX_ROW_EN[0] = 0x0
3874 12:38:30.120233 EX_ROW_EN[1] = 0x0
3875 12:38:30.120312 LP4Y_EN = 0x0
3876 12:38:30.123427 WORK_FSP = 0x0
3877 12:38:30.123507 WL = 0x2
3878 12:38:30.126976 RL = 0x2
3879 12:38:30.127055 BL = 0x2
3880 12:38:30.130566 RPST = 0x0
3881 12:38:30.130671 RD_PRE = 0x0
3882 12:38:30.133838 WR_PRE = 0x1
3883 12:38:30.133938 WR_PST = 0x0
3884 12:38:30.136721 DBI_WR = 0x0
3885 12:38:30.136822 DBI_RD = 0x0
3886 12:38:30.140393 OTF = 0x1
3887 12:38:30.143880 ===================================
3888 12:38:30.147028 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3889 12:38:30.150345 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3890 12:38:30.157475 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3891 12:38:30.160400 ===================================
3892 12:38:30.160502 LPDDR4 DRAM CONFIGURATION
3893 12:38:30.163726 ===================================
3894 12:38:30.167014 EX_ROW_EN[0] = 0x10
3895 12:38:30.170437 EX_ROW_EN[1] = 0x0
3896 12:38:30.170515 LP4Y_EN = 0x0
3897 12:38:30.173682 WORK_FSP = 0x0
3898 12:38:30.173782 WL = 0x2
3899 12:38:30.177000 RL = 0x2
3900 12:38:30.177113 BL = 0x2
3901 12:38:30.180499 RPST = 0x0
3902 12:38:30.180583 RD_PRE = 0x0
3903 12:38:30.184174 WR_PRE = 0x1
3904 12:38:30.184276 WR_PST = 0x0
3905 12:38:30.187377 DBI_WR = 0x0
3906 12:38:30.187477 DBI_RD = 0x0
3907 12:38:30.190144 OTF = 0x1
3908 12:38:30.193951 ===================================
3909 12:38:30.200164 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3910 12:38:30.203761 nWR fixed to 30
3911 12:38:30.203870 [ModeRegInit_LP4] CH0 RK0
3912 12:38:30.207505 [ModeRegInit_LP4] CH0 RK1
3913 12:38:30.210151 [ModeRegInit_LP4] CH1 RK0
3914 12:38:30.210253 [ModeRegInit_LP4] CH1 RK1
3915 12:38:30.213557 match AC timing 17
3916 12:38:30.216697 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3917 12:38:30.223680 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3918 12:38:30.227420 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3919 12:38:30.230154 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3920 12:38:30.237064 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3921 12:38:30.237145 ==
3922 12:38:30.240213 Dram Type= 6, Freq= 0, CH_0, rank 0
3923 12:38:30.243939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3924 12:38:30.244015 ==
3925 12:38:30.250140 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3926 12:38:30.253611 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3927 12:38:30.258260 [CA 0] Center 36 (6~66) winsize 61
3928 12:38:30.261694 [CA 1] Center 36 (6~66) winsize 61
3929 12:38:30.264907 [CA 2] Center 34 (4~65) winsize 62
3930 12:38:30.267815 [CA 3] Center 34 (4~65) winsize 62
3931 12:38:30.271794 [CA 4] Center 34 (4~64) winsize 61
3932 12:38:30.274918 [CA 5] Center 33 (3~64) winsize 62
3933 12:38:30.275018
3934 12:38:30.278007 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3935 12:38:30.278099
3936 12:38:30.281632 [CATrainingPosCal] consider 1 rank data
3937 12:38:30.285179 u2DelayCellTimex100 = 270/100 ps
3938 12:38:30.287837 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3939 12:38:30.291454 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3940 12:38:30.298700 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3941 12:38:30.301700 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3942 12:38:30.305078 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3943 12:38:30.308079 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3944 12:38:30.308179
3945 12:38:30.311573 CA PerBit enable=1, Macro0, CA PI delay=33
3946 12:38:30.311668
3947 12:38:30.315214 [CBTSetCACLKResult] CA Dly = 33
3948 12:38:30.315310 CS Dly: 5 (0~36)
3949 12:38:30.315398 ==
3950 12:38:30.318142 Dram Type= 6, Freq= 0, CH_0, rank 1
3951 12:38:30.324532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3952 12:38:30.324634 ==
3953 12:38:30.328521 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3954 12:38:30.334648 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3955 12:38:30.338668 [CA 0] Center 36 (6~66) winsize 61
3956 12:38:30.342152 [CA 1] Center 36 (6~66) winsize 61
3957 12:38:30.344923 [CA 2] Center 34 (4~65) winsize 62
3958 12:38:30.348217 [CA 3] Center 34 (4~65) winsize 62
3959 12:38:30.351772 [CA 4] Center 33 (3~64) winsize 62
3960 12:38:30.354856 [CA 5] Center 33 (3~64) winsize 62
3961 12:38:30.354953
3962 12:38:30.358345 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3963 12:38:30.358446
3964 12:38:30.361780 [CATrainingPosCal] consider 2 rank data
3965 12:38:30.364976 u2DelayCellTimex100 = 270/100 ps
3966 12:38:30.368524 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3967 12:38:30.371622 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3968 12:38:30.378592 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3969 12:38:30.381524 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3970 12:38:30.384904 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3971 12:38:30.388206 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3972 12:38:30.388285
3973 12:38:30.391785 CA PerBit enable=1, Macro0, CA PI delay=33
3974 12:38:30.391864
3975 12:38:30.394751 [CBTSetCACLKResult] CA Dly = 33
3976 12:38:30.394831 CS Dly: 4 (0~35)
3977 12:38:30.394894
3978 12:38:30.398066 ----->DramcWriteLeveling(PI) begin...
3979 12:38:30.401576 ==
3980 12:38:30.401656 Dram Type= 6, Freq= 0, CH_0, rank 0
3981 12:38:30.408081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3982 12:38:30.408185 ==
3983 12:38:30.412151 Write leveling (Byte 0): 33 => 33
3984 12:38:30.414580 Write leveling (Byte 1): 32 => 32
3985 12:38:30.418001 DramcWriteLeveling(PI) end<-----
3986 12:38:30.418079
3987 12:38:30.418179 ==
3988 12:38:30.421529 Dram Type= 6, Freq= 0, CH_0, rank 0
3989 12:38:30.425136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3990 12:38:30.425233 ==
3991 12:38:30.428096 [Gating] SW mode calibration
3992 12:38:30.434596 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3993 12:38:30.438343 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3994 12:38:30.445145 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3995 12:38:30.448529 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3996 12:38:30.451366 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3997 12:38:30.458220 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
3998 12:38:30.461855 0 9 16 | B1->B0 | 3333 2e2e | 0 0 | (0 1) (1 1)
3999 12:38:30.465013 0 9 20 | B1->B0 | 2323 2323 | 1 0 | (1 0) (0 0)
4000 12:38:30.471419 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 12:38:30.475088 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 12:38:30.478130 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 12:38:30.484868 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 12:38:30.488055 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 12:38:30.491519 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4006 12:38:30.498165 0 10 16 | B1->B0 | 2f2f 3a3a | 0 0 | (0 0) (0 0)
4007 12:38:30.501524 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4008 12:38:30.504888 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 12:38:30.511595 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 12:38:30.514950 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 12:38:30.518014 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 12:38:30.521206 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 12:38:30.528820 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 12:38:30.531336 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4015 12:38:30.535096 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 12:38:30.541574 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 12:38:30.545194 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 12:38:30.548823 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 12:38:30.555296 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 12:38:30.558483 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 12:38:30.561735 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 12:38:30.568282 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 12:38:30.571921 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 12:38:30.575017 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 12:38:30.582200 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 12:38:30.585143 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 12:38:30.588285 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 12:38:30.595103 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 12:38:30.598356 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4030 12:38:30.601832 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4031 12:38:30.604930 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 12:38:30.608735 Total UI for P1: 0, mck2ui 16
4033 12:38:30.611612 best dqsien dly found for B0: ( 0, 13, 16)
4034 12:38:30.615083 Total UI for P1: 0, mck2ui 16
4035 12:38:30.618254 best dqsien dly found for B1: ( 0, 13, 18)
4036 12:38:30.621565 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4037 12:38:30.628435 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4038 12:38:30.628537
4039 12:38:30.631574 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4040 12:38:30.634833 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4041 12:38:30.638374 [Gating] SW calibration Done
4042 12:38:30.638506 ==
4043 12:38:30.641956 Dram Type= 6, Freq= 0, CH_0, rank 0
4044 12:38:30.645072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4045 12:38:30.645169 ==
4046 12:38:30.645262 RX Vref Scan: 0
4047 12:38:30.648174
4048 12:38:30.648242 RX Vref 0 -> 0, step: 1
4049 12:38:30.648303
4050 12:38:30.651776 RX Delay -230 -> 252, step: 16
4051 12:38:30.655210 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4052 12:38:30.661406 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4053 12:38:30.665074 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4054 12:38:30.668211 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4055 12:38:30.671543 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4056 12:38:30.675479 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4057 12:38:30.681919 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4058 12:38:30.685310 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4059 12:38:30.688227 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4060 12:38:30.691839 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4061 12:38:30.694983 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4062 12:38:30.701899 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4063 12:38:30.704789 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4064 12:38:30.708665 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4065 12:38:30.711713 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4066 12:38:30.718453 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4067 12:38:30.718559 ==
4068 12:38:30.721893 Dram Type= 6, Freq= 0, CH_0, rank 0
4069 12:38:30.724964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4070 12:38:30.725060 ==
4071 12:38:30.725151 DQS Delay:
4072 12:38:30.728598 DQS0 = 0, DQS1 = 0
4073 12:38:30.728699 DQM Delay:
4074 12:38:30.731655 DQM0 = 41, DQM1 = 33
4075 12:38:30.731757 DQ Delay:
4076 12:38:30.735116 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4077 12:38:30.738572 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4078 12:38:30.741770 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4079 12:38:30.745388 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4080 12:38:30.745487
4081 12:38:30.745578
4082 12:38:30.745643 ==
4083 12:38:30.748587 Dram Type= 6, Freq= 0, CH_0, rank 0
4084 12:38:30.751497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4085 12:38:30.751600 ==
4086 12:38:30.751691
4087 12:38:30.754979
4088 12:38:30.755059 TX Vref Scan disable
4089 12:38:30.758539 == TX Byte 0 ==
4090 12:38:30.761702 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4091 12:38:30.765147 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4092 12:38:30.768627 == TX Byte 1 ==
4093 12:38:30.771965 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4094 12:38:30.775410 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4095 12:38:30.775488 ==
4096 12:38:30.778534 Dram Type= 6, Freq= 0, CH_0, rank 0
4097 12:38:30.785478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4098 12:38:30.785551 ==
4099 12:38:30.785613
4100 12:38:30.785670
4101 12:38:30.785726 TX Vref Scan disable
4102 12:38:30.789750 == TX Byte 0 ==
4103 12:38:30.792929 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4104 12:38:30.800012 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4105 12:38:30.800092 == TX Byte 1 ==
4106 12:38:30.802877 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4107 12:38:30.809598 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4108 12:38:30.809677
4109 12:38:30.809741 [DATLAT]
4110 12:38:30.809801 Freq=600, CH0 RK0
4111 12:38:30.809859
4112 12:38:30.812662 DATLAT Default: 0x9
4113 12:38:30.812731 0, 0xFFFF, sum = 0
4114 12:38:30.816488 1, 0xFFFF, sum = 0
4115 12:38:30.816559 2, 0xFFFF, sum = 0
4116 12:38:30.819533 3, 0xFFFF, sum = 0
4117 12:38:30.822978 4, 0xFFFF, sum = 0
4118 12:38:30.823060 5, 0xFFFF, sum = 0
4119 12:38:30.826306 6, 0xFFFF, sum = 0
4120 12:38:30.826435 7, 0xFFFF, sum = 0
4121 12:38:30.826534 8, 0x0, sum = 1
4122 12:38:30.829665 9, 0x0, sum = 2
4123 12:38:30.829746 10, 0x0, sum = 3
4124 12:38:30.833119 11, 0x0, sum = 4
4125 12:38:30.833231 best_step = 9
4126 12:38:30.833297
4127 12:38:30.833357 ==
4128 12:38:30.836092 Dram Type= 6, Freq= 0, CH_0, rank 0
4129 12:38:30.842637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 12:38:30.842717 ==
4131 12:38:30.842783 RX Vref Scan: 1
4132 12:38:30.842843
4133 12:38:30.846247 RX Vref 0 -> 0, step: 1
4134 12:38:30.846327
4135 12:38:30.849716 RX Delay -179 -> 252, step: 8
4136 12:38:30.849797
4137 12:38:30.852730 Set Vref, RX VrefLevel [Byte0]: 53
4138 12:38:30.855993 [Byte1]: 52
4139 12:38:30.856073
4140 12:38:30.859302 Final RX Vref Byte 0 = 53 to rank0
4141 12:38:30.863127 Final RX Vref Byte 1 = 52 to rank0
4142 12:38:30.865864 Final RX Vref Byte 0 = 53 to rank1
4143 12:38:30.869508 Final RX Vref Byte 1 = 52 to rank1==
4144 12:38:30.872751 Dram Type= 6, Freq= 0, CH_0, rank 0
4145 12:38:30.876180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4146 12:38:30.876255 ==
4147 12:38:30.879179 DQS Delay:
4148 12:38:30.879246 DQS0 = 0, DQS1 = 0
4149 12:38:30.879307 DQM Delay:
4150 12:38:30.883003 DQM0 = 42, DQM1 = 33
4151 12:38:30.883082 DQ Delay:
4152 12:38:30.885863 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4153 12:38:30.889654 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4154 12:38:30.892747 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4155 12:38:30.895927 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4156 12:38:30.896007
4157 12:38:30.896070
4158 12:38:30.905870 [DQSOSCAuto] RK0, (LSB)MR18= 0x3a19, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 398 ps
4159 12:38:30.909073 CH0 RK0: MR19=808, MR18=3A19
4160 12:38:30.912484 CH0_RK0: MR19=0x808, MR18=0x3A19, DQSOSC=398, MR23=63, INC=165, DEC=110
4161 12:38:30.912564
4162 12:38:30.916297 ----->DramcWriteLeveling(PI) begin...
4163 12:38:30.919206 ==
4164 12:38:30.922883 Dram Type= 6, Freq= 0, CH_0, rank 1
4165 12:38:30.925902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4166 12:38:30.925982 ==
4167 12:38:30.929395 Write leveling (Byte 0): 33 => 33
4168 12:38:30.932516 Write leveling (Byte 1): 30 => 30
4169 12:38:30.936090 DramcWriteLeveling(PI) end<-----
4170 12:38:30.936169
4171 12:38:30.936232 ==
4172 12:38:30.939410 Dram Type= 6, Freq= 0, CH_0, rank 1
4173 12:38:30.942705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4174 12:38:30.942784 ==
4175 12:38:30.946360 [Gating] SW mode calibration
4176 12:38:30.952773 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4177 12:38:30.955905 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4178 12:38:30.962675 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4179 12:38:30.965685 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4180 12:38:30.969395 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4181 12:38:30.975650 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
4182 12:38:30.979555 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
4183 12:38:30.982309 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 12:38:30.989542 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 12:38:30.992732 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 12:38:30.995900 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 12:38:31.002432 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 12:38:31.005809 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 12:38:31.009353 0 10 12 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
4190 12:38:31.015871 0 10 16 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
4191 12:38:31.019462 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 12:38:31.022774 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 12:38:31.029405 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 12:38:31.032815 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 12:38:31.036079 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 12:38:31.039737 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 12:38:31.046025 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4198 12:38:31.049045 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4199 12:38:31.053018 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 12:38:31.059227 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 12:38:31.063076 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 12:38:31.066040 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 12:38:31.072774 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 12:38:31.075830 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 12:38:31.079854 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 12:38:31.086044 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 12:38:31.089164 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 12:38:31.092596 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 12:38:31.099283 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 12:38:31.102634 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 12:38:31.106364 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 12:38:31.112582 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4213 12:38:31.116362 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4214 12:38:31.119873 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4215 12:38:31.123092 Total UI for P1: 0, mck2ui 16
4216 12:38:31.126213 best dqsien dly found for B0: ( 0, 13, 10)
4217 12:38:31.129475 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 12:38:31.133016 Total UI for P1: 0, mck2ui 16
4219 12:38:31.136139 best dqsien dly found for B1: ( 0, 13, 14)
4220 12:38:31.139531 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4221 12:38:31.146455 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4222 12:38:31.146536
4223 12:38:31.149279 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4224 12:38:31.152619 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4225 12:38:31.156308 [Gating] SW calibration Done
4226 12:38:31.156388 ==
4227 12:38:31.159500 Dram Type= 6, Freq= 0, CH_0, rank 1
4228 12:38:31.163241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4229 12:38:31.163322 ==
4230 12:38:31.163386 RX Vref Scan: 0
4231 12:38:31.166382
4232 12:38:31.166484 RX Vref 0 -> 0, step: 1
4233 12:38:31.166548
4234 12:38:31.169654 RX Delay -230 -> 252, step: 16
4235 12:38:31.172809 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4236 12:38:31.179633 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4237 12:38:31.183131 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4238 12:38:31.186050 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4239 12:38:31.189433 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4240 12:38:31.193202 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4241 12:38:31.199577 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4242 12:38:31.202606 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4243 12:38:31.206309 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4244 12:38:31.209303 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4245 12:38:31.216001 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4246 12:38:31.219509 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4247 12:38:31.222916 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4248 12:38:31.226322 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4249 12:38:31.229381 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4250 12:38:31.236589 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4251 12:38:31.236669 ==
4252 12:38:31.239559 Dram Type= 6, Freq= 0, CH_0, rank 1
4253 12:38:31.242801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 12:38:31.242882 ==
4255 12:38:31.242946 DQS Delay:
4256 12:38:31.246276 DQS0 = 0, DQS1 = 0
4257 12:38:31.246382 DQM Delay:
4258 12:38:31.249263 DQM0 = 41, DQM1 = 33
4259 12:38:31.249343 DQ Delay:
4260 12:38:31.252799 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4261 12:38:31.256153 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4262 12:38:31.259353 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4263 12:38:31.262631 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4264 12:38:31.262736
4265 12:38:31.262825
4266 12:38:31.262890 ==
4267 12:38:31.266268 Dram Type= 6, Freq= 0, CH_0, rank 1
4268 12:38:31.269653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4269 12:38:31.269733 ==
4270 12:38:31.273153
4271 12:38:31.273233
4272 12:38:31.273297 TX Vref Scan disable
4273 12:38:31.276263 == TX Byte 0 ==
4274 12:38:31.279963 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4275 12:38:31.283228 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4276 12:38:31.286173 == TX Byte 1 ==
4277 12:38:31.289834 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4278 12:38:31.292773 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4279 12:38:31.292854 ==
4280 12:38:31.296849 Dram Type= 6, Freq= 0, CH_0, rank 1
4281 12:38:31.302832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4282 12:38:31.302913 ==
4283 12:38:31.302976
4284 12:38:31.303036
4285 12:38:31.303093 TX Vref Scan disable
4286 12:38:31.307556 == TX Byte 0 ==
4287 12:38:31.311219 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4288 12:38:31.317273 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4289 12:38:31.317364 == TX Byte 1 ==
4290 12:38:31.320957 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4291 12:38:31.324662 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4292 12:38:31.327226
4293 12:38:31.327307 [DATLAT]
4294 12:38:31.327371 Freq=600, CH0 RK1
4295 12:38:31.327430
4296 12:38:31.330697 DATLAT Default: 0x9
4297 12:38:31.330777 0, 0xFFFF, sum = 0
4298 12:38:31.334423 1, 0xFFFF, sum = 0
4299 12:38:31.334521 2, 0xFFFF, sum = 0
4300 12:38:31.337914 3, 0xFFFF, sum = 0
4301 12:38:31.337986 4, 0xFFFF, sum = 0
4302 12:38:31.340965 5, 0xFFFF, sum = 0
4303 12:38:31.344406 6, 0xFFFF, sum = 0
4304 12:38:31.344486 7, 0xFFFF, sum = 0
4305 12:38:31.344551 8, 0x0, sum = 1
4306 12:38:31.347559 9, 0x0, sum = 2
4307 12:38:31.347640 10, 0x0, sum = 3
4308 12:38:31.350587 11, 0x0, sum = 4
4309 12:38:31.350669 best_step = 9
4310 12:38:31.350732
4311 12:38:31.350790 ==
4312 12:38:31.353946 Dram Type= 6, Freq= 0, CH_0, rank 1
4313 12:38:31.361317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4314 12:38:31.361398 ==
4315 12:38:31.361463 RX Vref Scan: 0
4316 12:38:31.361522
4317 12:38:31.363922 RX Vref 0 -> 0, step: 1
4318 12:38:31.364008
4319 12:38:31.367529 RX Delay -195 -> 252, step: 8
4320 12:38:31.370855 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4321 12:38:31.377705 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4322 12:38:31.380937 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4323 12:38:31.384697 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4324 12:38:31.387397 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4325 12:38:31.391619 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4326 12:38:31.397496 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4327 12:38:31.400647 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4328 12:38:31.404358 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4329 12:38:31.407662 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4330 12:38:31.411050 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4331 12:38:31.417526 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4332 12:38:31.420986 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4333 12:38:31.424205 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4334 12:38:31.427314 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4335 12:38:31.434059 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4336 12:38:31.434144 ==
4337 12:38:31.437597 Dram Type= 6, Freq= 0, CH_0, rank 1
4338 12:38:31.441326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 12:38:31.441408 ==
4340 12:38:31.441472 DQS Delay:
4341 12:38:31.444048 DQS0 = 0, DQS1 = 0
4342 12:38:31.444128 DQM Delay:
4343 12:38:31.447490 DQM0 = 39, DQM1 = 33
4344 12:38:31.447570 DQ Delay:
4345 12:38:31.451089 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4346 12:38:31.454192 DQ4 =36, DQ5 =28, DQ6 =52, DQ7 =44
4347 12:38:31.457291 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4348 12:38:31.460513 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4349 12:38:31.460593
4350 12:38:31.460673
4351 12:38:31.470916 [DQSOSCAuto] RK1, (LSB)MR18= 0x492c, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4352 12:38:31.470998 CH0 RK1: MR19=808, MR18=492C
4353 12:38:31.477793 CH0_RK1: MR19=0x808, MR18=0x492C, DQSOSC=396, MR23=63, INC=167, DEC=111
4354 12:38:31.480693 [RxdqsGatingPostProcess] freq 600
4355 12:38:31.487658 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4356 12:38:31.490633 Pre-setting of DQS Precalculation
4357 12:38:31.494529 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4358 12:38:31.494610 ==
4359 12:38:31.497732 Dram Type= 6, Freq= 0, CH_1, rank 0
4360 12:38:31.500631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4361 12:38:31.500712 ==
4362 12:38:31.507871 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4363 12:38:31.513974 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4364 12:38:31.517679 [CA 0] Center 35 (5~66) winsize 62
4365 12:38:31.520963 [CA 1] Center 35 (5~66) winsize 62
4366 12:38:31.524674 [CA 2] Center 34 (4~64) winsize 61
4367 12:38:31.527492 [CA 3] Center 33 (3~64) winsize 62
4368 12:38:31.530657 [CA 4] Center 34 (3~65) winsize 63
4369 12:38:31.534371 [CA 5] Center 33 (2~64) winsize 63
4370 12:38:31.534499
4371 12:38:31.537633 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4372 12:38:31.537713
4373 12:38:31.540635 [CATrainingPosCal] consider 1 rank data
4374 12:38:31.544472 u2DelayCellTimex100 = 270/100 ps
4375 12:38:31.547360 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4376 12:38:31.551003 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4377 12:38:31.554415 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4378 12:38:31.557523 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4379 12:38:31.561234 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4380 12:38:31.564357 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4381 12:38:31.567736
4382 12:38:31.571091 CA PerBit enable=1, Macro0, CA PI delay=33
4383 12:38:31.571172
4384 12:38:31.574870 [CBTSetCACLKResult] CA Dly = 33
4385 12:38:31.574952 CS Dly: 5 (0~36)
4386 12:38:31.575016 ==
4387 12:38:31.577623 Dram Type= 6, Freq= 0, CH_1, rank 1
4388 12:38:31.581021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4389 12:38:31.581102 ==
4390 12:38:31.587755 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4391 12:38:31.594644 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4392 12:38:31.597686 [CA 0] Center 35 (5~66) winsize 62
4393 12:38:31.600817 [CA 1] Center 35 (5~66) winsize 62
4394 12:38:31.604092 [CA 2] Center 34 (4~65) winsize 62
4395 12:38:31.607375 [CA 3] Center 34 (3~65) winsize 63
4396 12:38:31.611066 [CA 4] Center 34 (4~65) winsize 62
4397 12:38:31.614312 [CA 5] Center 33 (3~64) winsize 62
4398 12:38:31.614418
4399 12:38:31.618113 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4400 12:38:31.618193
4401 12:38:31.621140 [CATrainingPosCal] consider 2 rank data
4402 12:38:31.624125 u2DelayCellTimex100 = 270/100 ps
4403 12:38:31.627895 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4404 12:38:31.631087 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4405 12:38:31.634383 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4406 12:38:31.638118 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4407 12:38:31.641096 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4408 12:38:31.644275 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4409 12:38:31.644354
4410 12:38:31.651004 CA PerBit enable=1, Macro0, CA PI delay=33
4411 12:38:31.651084
4412 12:38:31.654701 [CBTSetCACLKResult] CA Dly = 33
4413 12:38:31.654780 CS Dly: 6 (0~38)
4414 12:38:31.654843
4415 12:38:31.657798 ----->DramcWriteLeveling(PI) begin...
4416 12:38:31.657879 ==
4417 12:38:31.661351 Dram Type= 6, Freq= 0, CH_1, rank 0
4418 12:38:31.664526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4419 12:38:31.664606 ==
4420 12:38:31.668410 Write leveling (Byte 0): 29 => 29
4421 12:38:31.671071 Write leveling (Byte 1): 29 => 29
4422 12:38:31.674637 DramcWriteLeveling(PI) end<-----
4423 12:38:31.674717
4424 12:38:31.674779 ==
4425 12:38:31.677668 Dram Type= 6, Freq= 0, CH_1, rank 0
4426 12:38:31.681224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4427 12:38:31.684526 ==
4428 12:38:31.684605 [Gating] SW mode calibration
4429 12:38:31.694568 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4430 12:38:31.697777 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4431 12:38:31.701476 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4432 12:38:31.707975 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4433 12:38:31.711236 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4434 12:38:31.714519 0 9 12 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 1)
4435 12:38:31.721355 0 9 16 | B1->B0 | 2727 2626 | 0 0 | (0 0) (0 0)
4436 12:38:31.724570 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 12:38:31.728397 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4438 12:38:31.734700 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4439 12:38:31.737821 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 12:38:31.741713 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 12:38:31.748019 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 12:38:31.751222 0 10 12 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (0 0)
4443 12:38:31.754867 0 10 16 | B1->B0 | 3b3b 4040 | 0 0 | (0 0) (0 0)
4444 12:38:31.758099 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 12:38:31.764740 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 12:38:31.768302 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 12:38:31.771541 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 12:38:31.777797 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 12:38:31.781213 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 12:38:31.784578 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 12:38:31.791274 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 12:38:31.795199 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 12:38:31.797920 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 12:38:31.804975 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 12:38:31.808152 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 12:38:31.811334 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 12:38:31.818433 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 12:38:31.821807 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 12:38:31.824800 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 12:38:31.828633 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 12:38:31.834698 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 12:38:31.838300 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 12:38:31.841605 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 12:38:31.848771 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 12:38:31.851398 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 12:38:31.855185 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4467 12:38:31.861452 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4468 12:38:31.861533 Total UI for P1: 0, mck2ui 16
4469 12:38:31.868222 best dqsien dly found for B0: ( 0, 13, 12)
4470 12:38:31.868303 Total UI for P1: 0, mck2ui 16
4471 12:38:31.871754 best dqsien dly found for B1: ( 0, 13, 12)
4472 12:38:31.879023 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4473 12:38:31.882067 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4474 12:38:31.882162
4475 12:38:31.884940 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4476 12:38:31.888614 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4477 12:38:31.891969 [Gating] SW calibration Done
4478 12:38:31.892050 ==
4479 12:38:31.895203 Dram Type= 6, Freq= 0, CH_1, rank 0
4480 12:38:31.898289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4481 12:38:31.898369 ==
4482 12:38:31.901543 RX Vref Scan: 0
4483 12:38:31.901623
4484 12:38:31.901686 RX Vref 0 -> 0, step: 1
4485 12:38:31.901745
4486 12:38:31.904791 RX Delay -230 -> 252, step: 16
4487 12:38:31.908095 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4488 12:38:31.914907 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4489 12:38:31.918295 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4490 12:38:31.921860 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4491 12:38:31.924654 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4492 12:38:31.931666 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4493 12:38:31.934631 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4494 12:38:31.938049 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4495 12:38:31.941929 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4496 12:38:31.944924 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4497 12:38:31.951979 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4498 12:38:31.954874 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4499 12:38:31.958333 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4500 12:38:31.961789 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4501 12:38:31.968253 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4502 12:38:31.971549 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4503 12:38:31.971628 ==
4504 12:38:31.974991 Dram Type= 6, Freq= 0, CH_1, rank 0
4505 12:38:31.978312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4506 12:38:31.978422 ==
4507 12:38:31.981295 DQS Delay:
4508 12:38:31.981373 DQS0 = 0, DQS1 = 0
4509 12:38:31.984422 DQM Delay:
4510 12:38:31.984501 DQM0 = 43, DQM1 = 34
4511 12:38:31.984564 DQ Delay:
4512 12:38:31.988092 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4513 12:38:31.991255 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4514 12:38:31.994961 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4515 12:38:31.998064 DQ12 =49, DQ13 =41, DQ14 =33, DQ15 =33
4516 12:38:31.998168
4517 12:38:31.998258
4518 12:38:31.998344 ==
4519 12:38:32.001774 Dram Type= 6, Freq= 0, CH_1, rank 0
4520 12:38:32.008100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4521 12:38:32.008181 ==
4522 12:38:32.008243
4523 12:38:32.008302
4524 12:38:32.008358 TX Vref Scan disable
4525 12:38:32.011539 == TX Byte 0 ==
4526 12:38:32.015027 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4527 12:38:32.018311 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4528 12:38:32.022119 == TX Byte 1 ==
4529 12:38:32.025239 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4530 12:38:32.028778 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4531 12:38:32.032026 ==
4532 12:38:32.035249 Dram Type= 6, Freq= 0, CH_1, rank 0
4533 12:38:32.038548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4534 12:38:32.038628 ==
4535 12:38:32.038692
4536 12:38:32.038750
4537 12:38:32.042152 TX Vref Scan disable
4538 12:38:32.042231 == TX Byte 0 ==
4539 12:38:32.048507 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4540 12:38:32.051690 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4541 12:38:32.051770 == TX Byte 1 ==
4542 12:38:32.058283 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4543 12:38:32.062320 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4544 12:38:32.062446
4545 12:38:32.062513 [DATLAT]
4546 12:38:32.065120 Freq=600, CH1 RK0
4547 12:38:32.065200
4548 12:38:32.065264 DATLAT Default: 0x9
4549 12:38:32.068916 0, 0xFFFF, sum = 0
4550 12:38:32.068998 1, 0xFFFF, sum = 0
4551 12:38:32.071918 2, 0xFFFF, sum = 0
4552 12:38:32.072002 3, 0xFFFF, sum = 0
4553 12:38:32.075571 4, 0xFFFF, sum = 0
4554 12:38:32.075652 5, 0xFFFF, sum = 0
4555 12:38:32.078932 6, 0xFFFF, sum = 0
4556 12:38:32.081803 7, 0xFFFF, sum = 0
4557 12:38:32.081885 8, 0x0, sum = 1
4558 12:38:32.081950 9, 0x0, sum = 2
4559 12:38:32.085594 10, 0x0, sum = 3
4560 12:38:32.085675 11, 0x0, sum = 4
4561 12:38:32.088603 best_step = 9
4562 12:38:32.088683
4563 12:38:32.088746 ==
4564 12:38:32.091935 Dram Type= 6, Freq= 0, CH_1, rank 0
4565 12:38:32.095397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4566 12:38:32.095477 ==
4567 12:38:32.098642 RX Vref Scan: 1
4568 12:38:32.098722
4569 12:38:32.098786 RX Vref 0 -> 0, step: 1
4570 12:38:32.098845
4571 12:38:32.102217 RX Delay -179 -> 252, step: 8
4572 12:38:32.102323
4573 12:38:32.105337 Set Vref, RX VrefLevel [Byte0]: 56
4574 12:38:32.108516 [Byte1]: 51
4575 12:38:32.112027
4576 12:38:32.112107 Final RX Vref Byte 0 = 56 to rank0
4577 12:38:32.115619 Final RX Vref Byte 1 = 51 to rank0
4578 12:38:32.118943 Final RX Vref Byte 0 = 56 to rank1
4579 12:38:32.122498 Final RX Vref Byte 1 = 51 to rank1==
4580 12:38:32.125632 Dram Type= 6, Freq= 0, CH_1, rank 0
4581 12:38:32.132484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4582 12:38:32.132564 ==
4583 12:38:32.132628 DQS Delay:
4584 12:38:32.132688 DQS0 = 0, DQS1 = 0
4585 12:38:32.135639 DQM Delay:
4586 12:38:32.135718 DQM0 = 42, DQM1 = 33
4587 12:38:32.138976 DQ Delay:
4588 12:38:32.142207 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =44
4589 12:38:32.142288 DQ4 =44, DQ5 =52, DQ6 =52, DQ7 =36
4590 12:38:32.145902 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4591 12:38:32.148978 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =40
4592 12:38:32.152434
4593 12:38:32.152513
4594 12:38:32.158956 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d03, (MSB)MR19= 0x808, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
4595 12:38:32.162080 CH1 RK0: MR19=808, MR18=3D03
4596 12:38:32.169254 CH1_RK0: MR19=0x808, MR18=0x3D03, DQSOSC=398, MR23=63, INC=165, DEC=110
4597 12:38:32.169335
4598 12:38:32.172114 ----->DramcWriteLeveling(PI) begin...
4599 12:38:32.172196 ==
4600 12:38:32.175844 Dram Type= 6, Freq= 0, CH_1, rank 1
4601 12:38:32.179172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4602 12:38:32.179253 ==
4603 12:38:32.182068 Write leveling (Byte 0): 28 => 28
4604 12:38:32.185688 Write leveling (Byte 1): 30 => 30
4605 12:38:32.188760 DramcWriteLeveling(PI) end<-----
4606 12:38:32.188840
4607 12:38:32.188903 ==
4608 12:38:32.192554 Dram Type= 6, Freq= 0, CH_1, rank 1
4609 12:38:32.195449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4610 12:38:32.195529 ==
4611 12:38:32.198894 [Gating] SW mode calibration
4612 12:38:32.205607 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4613 12:38:32.212611 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4614 12:38:32.215894 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4615 12:38:32.218833 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4616 12:38:32.225734 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4617 12:38:32.229268 0 9 12 | B1->B0 | 3030 2c2c | 0 0 | (0 0) (0 0)
4618 12:38:32.232604 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4619 12:38:32.239251 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4620 12:38:32.242178 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4621 12:38:32.245764 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4622 12:38:32.252622 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 12:38:32.255660 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 12:38:32.259430 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4625 12:38:32.262570 0 10 12 | B1->B0 | 2f2f 3a3a | 0 0 | (1 1) (0 0)
4626 12:38:32.269039 0 10 16 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
4627 12:38:32.272177 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 12:38:32.275521 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 12:38:32.282221 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 12:38:32.285728 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 12:38:32.289264 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 12:38:32.295619 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4633 12:38:32.298948 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 12:38:32.302235 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 12:38:32.309028 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 12:38:32.312416 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 12:38:32.315353 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 12:38:32.322287 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 12:38:32.325881 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 12:38:32.328887 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 12:38:32.335560 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 12:38:32.338777 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 12:38:32.342662 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 12:38:32.349025 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 12:38:32.353042 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 12:38:32.355529 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 12:38:32.358910 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 12:38:32.365639 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4649 12:38:32.369212 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4650 12:38:32.372409 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4651 12:38:32.375730 Total UI for P1: 0, mck2ui 16
4652 12:38:32.379218 best dqsien dly found for B0: ( 0, 13, 10)
4653 12:38:32.382143 Total UI for P1: 0, mck2ui 16
4654 12:38:32.385846 best dqsien dly found for B1: ( 0, 13, 14)
4655 12:38:32.389352 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4656 12:38:32.395694 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4657 12:38:32.395794
4658 12:38:32.398976 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4659 12:38:32.402365 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4660 12:38:32.405480 [Gating] SW calibration Done
4661 12:38:32.405592 ==
4662 12:38:32.409373 Dram Type= 6, Freq= 0, CH_1, rank 1
4663 12:38:32.412138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4664 12:38:32.412214 ==
4665 12:38:32.412303 RX Vref Scan: 0
4666 12:38:32.415851
4667 12:38:32.415918 RX Vref 0 -> 0, step: 1
4668 12:38:32.415977
4669 12:38:32.419277 RX Delay -230 -> 252, step: 16
4670 12:38:32.422254 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4671 12:38:32.428996 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4672 12:38:32.432545 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4673 12:38:32.436035 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4674 12:38:32.438796 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4675 12:38:32.442576 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4676 12:38:32.448978 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4677 12:38:32.452097 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4678 12:38:32.455592 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4679 12:38:32.458988 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4680 12:38:32.462240 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4681 12:38:32.468909 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4682 12:38:32.472038 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4683 12:38:32.475780 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4684 12:38:32.478758 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4685 12:38:32.485657 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4686 12:38:32.485733 ==
4687 12:38:32.489130 Dram Type= 6, Freq= 0, CH_1, rank 1
4688 12:38:32.492595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4689 12:38:32.492690 ==
4690 12:38:32.492779 DQS Delay:
4691 12:38:32.495379 DQS0 = 0, DQS1 = 0
4692 12:38:32.495449 DQM Delay:
4693 12:38:32.499332 DQM0 = 40, DQM1 = 35
4694 12:38:32.499406 DQ Delay:
4695 12:38:32.502037 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4696 12:38:32.505999 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4697 12:38:32.509606 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4698 12:38:32.512597 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4699 12:38:32.512694
4700 12:38:32.512781
4701 12:38:32.512868 ==
4702 12:38:32.515958 Dram Type= 6, Freq= 0, CH_1, rank 1
4703 12:38:32.518768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4704 12:38:32.518848 ==
4705 12:38:32.522097
4706 12:38:32.522176
4707 12:38:32.522239 TX Vref Scan disable
4708 12:38:32.525772 == TX Byte 0 ==
4709 12:38:32.528877 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4710 12:38:32.532028 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4711 12:38:32.535738 == TX Byte 1 ==
4712 12:38:32.538815 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4713 12:38:32.542745 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4714 12:38:32.542824 ==
4715 12:38:32.545600 Dram Type= 6, Freq= 0, CH_1, rank 1
4716 12:38:32.552552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4717 12:38:32.552632 ==
4718 12:38:32.552696
4719 12:38:32.552754
4720 12:38:32.552810 TX Vref Scan disable
4721 12:38:32.556737 == TX Byte 0 ==
4722 12:38:32.560101 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4723 12:38:32.566994 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4724 12:38:32.567073 == TX Byte 1 ==
4725 12:38:32.570548 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4726 12:38:32.576656 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4727 12:38:32.576736
4728 12:38:32.576799 [DATLAT]
4729 12:38:32.576858 Freq=600, CH1 RK1
4730 12:38:32.576914
4731 12:38:32.579992 DATLAT Default: 0x9
4732 12:38:32.580071 0, 0xFFFF, sum = 0
4733 12:38:32.583322 1, 0xFFFF, sum = 0
4734 12:38:32.583403 2, 0xFFFF, sum = 0
4735 12:38:32.586943 3, 0xFFFF, sum = 0
4736 12:38:32.587023 4, 0xFFFF, sum = 0
4737 12:38:32.590238 5, 0xFFFF, sum = 0
4738 12:38:32.593654 6, 0xFFFF, sum = 0
4739 12:38:32.593735 7, 0xFFFF, sum = 0
4740 12:38:32.593801 8, 0x0, sum = 1
4741 12:38:32.597110 9, 0x0, sum = 2
4742 12:38:32.597190 10, 0x0, sum = 3
4743 12:38:32.600136 11, 0x0, sum = 4
4744 12:38:32.600216 best_step = 9
4745 12:38:32.600279
4746 12:38:32.600337 ==
4747 12:38:32.603129 Dram Type= 6, Freq= 0, CH_1, rank 1
4748 12:38:32.609954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4749 12:38:32.610034 ==
4750 12:38:32.610097 RX Vref Scan: 0
4751 12:38:32.610156
4752 12:38:32.613687 RX Vref 0 -> 0, step: 1
4753 12:38:32.613766
4754 12:38:32.616834 RX Delay -179 -> 252, step: 8
4755 12:38:32.620141 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4756 12:38:32.626783 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4757 12:38:32.630352 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4758 12:38:32.633519 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4759 12:38:32.637380 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4760 12:38:32.640270 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4761 12:38:32.647365 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4762 12:38:32.650166 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4763 12:38:32.653962 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4764 12:38:32.657226 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4765 12:38:32.660294 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4766 12:38:32.667231 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4767 12:38:32.669980 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4768 12:38:32.673563 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4769 12:38:32.676777 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4770 12:38:32.683340 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4771 12:38:32.683421 ==
4772 12:38:32.686612 Dram Type= 6, Freq= 0, CH_1, rank 1
4773 12:38:32.690312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4774 12:38:32.690452 ==
4775 12:38:32.690517 DQS Delay:
4776 12:38:32.693641 DQS0 = 0, DQS1 = 0
4777 12:38:32.693720 DQM Delay:
4778 12:38:32.696884 DQM0 = 38, DQM1 = 33
4779 12:38:32.696964 DQ Delay:
4780 12:38:32.700213 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =36
4781 12:38:32.703971 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4782 12:38:32.706865 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4783 12:38:32.710667 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4784 12:38:32.710746
4785 12:38:32.710809
4786 12:38:32.716859 [DQSOSCAuto] RK1, (LSB)MR18= 0x3644, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4787 12:38:32.720113 CH1 RK1: MR19=808, MR18=3644
4788 12:38:32.727283 CH1_RK1: MR19=0x808, MR18=0x3644, DQSOSC=396, MR23=63, INC=167, DEC=111
4789 12:38:32.730197 [RxdqsGatingPostProcess] freq 600
4790 12:38:32.737462 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4791 12:38:32.740401 Pre-setting of DQS Precalculation
4792 12:38:32.743900 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4793 12:38:32.750885 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4794 12:38:32.757440 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4795 12:38:32.757520
4796 12:38:32.757583
4797 12:38:32.760536 [Calibration Summary] 1200 Mbps
4798 12:38:32.764260 CH 0, Rank 0
4799 12:38:32.764339 SW Impedance : PASS
4800 12:38:32.767312 DUTY Scan : NO K
4801 12:38:32.770293 ZQ Calibration : PASS
4802 12:38:32.770420 Jitter Meter : NO K
4803 12:38:32.773661 CBT Training : PASS
4804 12:38:32.776743 Write leveling : PASS
4805 12:38:32.776848 RX DQS gating : PASS
4806 12:38:32.780740 RX DQ/DQS(RDDQC) : PASS
4807 12:38:32.780819 TX DQ/DQS : PASS
4808 12:38:32.784054 RX DATLAT : PASS
4809 12:38:32.787185 RX DQ/DQS(Engine): PASS
4810 12:38:32.787264 TX OE : NO K
4811 12:38:32.790767 All Pass.
4812 12:38:32.790846
4813 12:38:32.790909 CH 0, Rank 1
4814 12:38:32.793915 SW Impedance : PASS
4815 12:38:32.793994 DUTY Scan : NO K
4816 12:38:32.797440 ZQ Calibration : PASS
4817 12:38:32.800660 Jitter Meter : NO K
4818 12:38:32.800739 CBT Training : PASS
4819 12:38:32.803730 Write leveling : PASS
4820 12:38:32.807213 RX DQS gating : PASS
4821 12:38:32.807318 RX DQ/DQS(RDDQC) : PASS
4822 12:38:32.810705 TX DQ/DQS : PASS
4823 12:38:32.813827 RX DATLAT : PASS
4824 12:38:32.813906 RX DQ/DQS(Engine): PASS
4825 12:38:32.817004 TX OE : NO K
4826 12:38:32.817152 All Pass.
4827 12:38:32.817276
4828 12:38:32.820574 CH 1, Rank 0
4829 12:38:32.820713 SW Impedance : PASS
4830 12:38:32.824139 DUTY Scan : NO K
4831 12:38:32.824250 ZQ Calibration : PASS
4832 12:38:32.826904 Jitter Meter : NO K
4833 12:38:32.830409 CBT Training : PASS
4834 12:38:32.830565 Write leveling : PASS
4835 12:38:32.833972 RX DQS gating : PASS
4836 12:38:32.837138 RX DQ/DQS(RDDQC) : PASS
4837 12:38:32.837275 TX DQ/DQS : PASS
4838 12:38:32.840480 RX DATLAT : PASS
4839 12:38:32.844227 RX DQ/DQS(Engine): PASS
4840 12:38:32.844373 TX OE : NO K
4841 12:38:32.847120 All Pass.
4842 12:38:32.847273
4843 12:38:32.847410 CH 1, Rank 1
4844 12:38:32.850602 SW Impedance : PASS
4845 12:38:32.850709 DUTY Scan : NO K
4846 12:38:32.853476 ZQ Calibration : PASS
4847 12:38:32.857243 Jitter Meter : NO K
4848 12:38:32.857344 CBT Training : PASS
4849 12:38:32.860525 Write leveling : PASS
4850 12:38:32.863772 RX DQS gating : PASS
4851 12:38:32.863875 RX DQ/DQS(RDDQC) : PASS
4852 12:38:32.867192 TX DQ/DQS : PASS
4853 12:38:32.867292 RX DATLAT : PASS
4854 12:38:32.870578 RX DQ/DQS(Engine): PASS
4855 12:38:32.873992 TX OE : NO K
4856 12:38:32.874095 All Pass.
4857 12:38:32.874184
4858 12:38:32.877263 DramC Write-DBI off
4859 12:38:32.877368 PER_BANK_REFRESH: Hybrid Mode
4860 12:38:32.880249 TX_TRACKING: ON
4861 12:38:32.886965 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4862 12:38:32.893726 [FAST_K] Save calibration result to emmc
4863 12:38:32.897048 dramc_set_vcore_voltage set vcore to 662500
4864 12:38:32.897174 Read voltage for 933, 3
4865 12:38:32.900737 Vio18 = 0
4866 12:38:32.900855 Vcore = 662500
4867 12:38:32.900960 Vdram = 0
4868 12:38:32.903703 Vddq = 0
4869 12:38:32.903834 Vmddr = 0
4870 12:38:32.906853 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4871 12:38:32.913707 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4872 12:38:32.917328 MEM_TYPE=3, freq_sel=17
4873 12:38:32.921006 sv_algorithm_assistance_LP4_1600
4874 12:38:32.923497 ============ PULL DRAM RESETB DOWN ============
4875 12:38:32.927202 ========== PULL DRAM RESETB DOWN end =========
4876 12:38:32.930636 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4877 12:38:32.934057 ===================================
4878 12:38:32.937058 LPDDR4 DRAM CONFIGURATION
4879 12:38:32.940138 ===================================
4880 12:38:32.943793 EX_ROW_EN[0] = 0x0
4881 12:38:32.943891 EX_ROW_EN[1] = 0x0
4882 12:38:32.947143 LP4Y_EN = 0x0
4883 12:38:32.947239 WORK_FSP = 0x0
4884 12:38:32.950199 WL = 0x3
4885 12:38:32.950295 RL = 0x3
4886 12:38:32.953973 BL = 0x2
4887 12:38:32.954070 RPST = 0x0
4888 12:38:32.957449 RD_PRE = 0x0
4889 12:38:32.957545 WR_PRE = 0x1
4890 12:38:32.960716 WR_PST = 0x0
4891 12:38:32.960814 DBI_WR = 0x0
4892 12:38:32.964138 DBI_RD = 0x0
4893 12:38:32.964233 OTF = 0x1
4894 12:38:32.967039 ===================================
4895 12:38:32.970696 ===================================
4896 12:38:32.973727 ANA top config
4897 12:38:32.977287 ===================================
4898 12:38:32.980715 DLL_ASYNC_EN = 0
4899 12:38:32.980810 ALL_SLAVE_EN = 1
4900 12:38:32.984328 NEW_RANK_MODE = 1
4901 12:38:32.987206 DLL_IDLE_MODE = 1
4902 12:38:32.990692 LP45_APHY_COMB_EN = 1
4903 12:38:32.990772 TX_ODT_DIS = 1
4904 12:38:32.994065 NEW_8X_MODE = 1
4905 12:38:32.996954 ===================================
4906 12:38:33.001120 ===================================
4907 12:38:33.004230 data_rate = 1866
4908 12:38:33.007240 CKR = 1
4909 12:38:33.010462 DQ_P2S_RATIO = 8
4910 12:38:33.014168 ===================================
4911 12:38:33.017413 CA_P2S_RATIO = 8
4912 12:38:33.017535 DQ_CA_OPEN = 0
4913 12:38:33.020458 DQ_SEMI_OPEN = 0
4914 12:38:33.023953 CA_SEMI_OPEN = 0
4915 12:38:33.026848 CA_FULL_RATE = 0
4916 12:38:33.030318 DQ_CKDIV4_EN = 1
4917 12:38:33.033748 CA_CKDIV4_EN = 1
4918 12:38:33.033869 CA_PREDIV_EN = 0
4919 12:38:33.037002 PH8_DLY = 0
4920 12:38:33.040303 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4921 12:38:33.043794 DQ_AAMCK_DIV = 4
4922 12:38:33.047332 CA_AAMCK_DIV = 4
4923 12:38:33.050928 CA_ADMCK_DIV = 4
4924 12:38:33.051009 DQ_TRACK_CA_EN = 0
4925 12:38:33.053650 CA_PICK = 933
4926 12:38:33.057516 CA_MCKIO = 933
4927 12:38:33.060279 MCKIO_SEMI = 0
4928 12:38:33.063752 PLL_FREQ = 3732
4929 12:38:33.067284 DQ_UI_PI_RATIO = 32
4930 12:38:33.070296 CA_UI_PI_RATIO = 0
4931 12:38:33.074008 ===================================
4932 12:38:33.077263 ===================================
4933 12:38:33.077357 memory_type:LPDDR4
4934 12:38:33.080331 GP_NUM : 10
4935 12:38:33.080398 SRAM_EN : 1
4936 12:38:33.083760 MD32_EN : 0
4937 12:38:33.087521 ===================================
4938 12:38:33.090619 [ANA_INIT] >>>>>>>>>>>>>>
4939 12:38:33.093781 <<<<<< [CONFIGURE PHASE]: ANA_TX
4940 12:38:33.097225 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4941 12:38:33.100440 ===================================
4942 12:38:33.100536 data_rate = 1866,PCW = 0X8f00
4943 12:38:33.104100 ===================================
4944 12:38:33.110288 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4945 12:38:33.114083 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4946 12:38:33.120986 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4947 12:38:33.124297 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4948 12:38:33.127497 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4949 12:38:33.130723 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4950 12:38:33.133620 [ANA_INIT] flow start
4951 12:38:33.137180 [ANA_INIT] PLL >>>>>>>>
4952 12:38:33.137259 [ANA_INIT] PLL <<<<<<<<
4953 12:38:33.140295 [ANA_INIT] MIDPI >>>>>>>>
4954 12:38:33.143642 [ANA_INIT] MIDPI <<<<<<<<
4955 12:38:33.143722 [ANA_INIT] DLL >>>>>>>>
4956 12:38:33.147319 [ANA_INIT] flow end
4957 12:38:33.150490 ============ LP4 DIFF to SE enter ============
4958 12:38:33.153868 ============ LP4 DIFF to SE exit ============
4959 12:38:33.157438 [ANA_INIT] <<<<<<<<<<<<<
4960 12:38:33.160922 [Flow] Enable top DCM control >>>>>
4961 12:38:33.164226 [Flow] Enable top DCM control <<<<<
4962 12:38:33.167252 Enable DLL master slave shuffle
4963 12:38:33.174201 ==============================================================
4964 12:38:33.174283 Gating Mode config
4965 12:38:33.180478 ==============================================================
4966 12:38:33.180558 Config description:
4967 12:38:33.190338 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4968 12:38:33.197490 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4969 12:38:33.203953 SELPH_MODE 0: By rank 1: By Phase
4970 12:38:33.207543 ==============================================================
4971 12:38:33.210807 GAT_TRACK_EN = 1
4972 12:38:33.213899 RX_GATING_MODE = 2
4973 12:38:33.217176 RX_GATING_TRACK_MODE = 2
4974 12:38:33.220760 SELPH_MODE = 1
4975 12:38:33.223781 PICG_EARLY_EN = 1
4976 12:38:33.227518 VALID_LAT_VALUE = 1
4977 12:38:33.230585 ==============================================================
4978 12:38:33.234304 Enter into Gating configuration >>>>
4979 12:38:33.237311 Exit from Gating configuration <<<<
4980 12:38:33.240486 Enter into DVFS_PRE_config >>>>>
4981 12:38:33.254362 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4982 12:38:33.254483 Exit from DVFS_PRE_config <<<<<
4983 12:38:33.257279 Enter into PICG configuration >>>>
4984 12:38:33.260972 Exit from PICG configuration <<<<
4985 12:38:33.263977 [RX_INPUT] configuration >>>>>
4986 12:38:33.267405 [RX_INPUT] configuration <<<<<
4987 12:38:33.274466 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4988 12:38:33.277500 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4989 12:38:33.284426 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4990 12:38:33.291188 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4991 12:38:33.297714 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4992 12:38:33.304315 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4993 12:38:33.307683 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4994 12:38:33.310777 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4995 12:38:33.314465 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4996 12:38:33.320890 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4997 12:38:33.324995 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4998 12:38:33.327751 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4999 12:38:33.330858 ===================================
5000 12:38:33.334636 LPDDR4 DRAM CONFIGURATION
5001 12:38:33.337870 ===================================
5002 12:38:33.337967 EX_ROW_EN[0] = 0x0
5003 12:38:33.341365 EX_ROW_EN[1] = 0x0
5004 12:38:33.341433 LP4Y_EN = 0x0
5005 12:38:33.344177 WORK_FSP = 0x0
5006 12:38:33.344243 WL = 0x3
5007 12:38:33.348017 RL = 0x3
5008 12:38:33.348089 BL = 0x2
5009 12:38:33.351583 RPST = 0x0
5010 12:38:33.354680 RD_PRE = 0x0
5011 12:38:33.354774 WR_PRE = 0x1
5012 12:38:33.357676 WR_PST = 0x0
5013 12:38:33.357768 DBI_WR = 0x0
5014 12:38:33.361080 DBI_RD = 0x0
5015 12:38:33.361179 OTF = 0x1
5016 12:38:33.364133 ===================================
5017 12:38:33.367818 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5018 12:38:33.374611 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5019 12:38:33.377620 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5020 12:38:33.381225 ===================================
5021 12:38:33.384320 LPDDR4 DRAM CONFIGURATION
5022 12:38:33.387855 ===================================
5023 12:38:33.387922 EX_ROW_EN[0] = 0x10
5024 12:38:33.390675 EX_ROW_EN[1] = 0x0
5025 12:38:33.390742 LP4Y_EN = 0x0
5026 12:38:33.394461 WORK_FSP = 0x0
5027 12:38:33.394529 WL = 0x3
5028 12:38:33.397690 RL = 0x3
5029 12:38:33.397785 BL = 0x2
5030 12:38:33.400709 RPST = 0x0
5031 12:38:33.400781 RD_PRE = 0x0
5032 12:38:33.404531 WR_PRE = 0x1
5033 12:38:33.404627 WR_PST = 0x0
5034 12:38:33.407573 DBI_WR = 0x0
5035 12:38:33.410638 DBI_RD = 0x0
5036 12:38:33.410736 OTF = 0x1
5037 12:38:33.414111 ===================================
5038 12:38:33.420923 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5039 12:38:33.424069 nWR fixed to 30
5040 12:38:33.427705 [ModeRegInit_LP4] CH0 RK0
5041 12:38:33.427781 [ModeRegInit_LP4] CH0 RK1
5042 12:38:33.430741 [ModeRegInit_LP4] CH1 RK0
5043 12:38:33.433981 [ModeRegInit_LP4] CH1 RK1
5044 12:38:33.434054 match AC timing 9
5045 12:38:33.440925 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5046 12:38:33.443820 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5047 12:38:33.447508 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5048 12:38:33.454277 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5049 12:38:33.457567 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5050 12:38:33.457697 ==
5051 12:38:33.460662 Dram Type= 6, Freq= 0, CH_0, rank 0
5052 12:38:33.464270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5053 12:38:33.464374 ==
5054 12:38:33.470989 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5055 12:38:33.477418 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5056 12:38:33.480600 [CA 0] Center 38 (8~69) winsize 62
5057 12:38:33.483961 [CA 1] Center 38 (7~69) winsize 63
5058 12:38:33.487361 [CA 2] Center 35 (5~66) winsize 62
5059 12:38:33.491130 [CA 3] Center 35 (4~66) winsize 63
5060 12:38:33.494082 [CA 4] Center 34 (4~64) winsize 61
5061 12:38:33.497504 [CA 5] Center 34 (4~64) winsize 61
5062 12:38:33.497599
5063 12:38:33.500816 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5064 12:38:33.500917
5065 12:38:33.504103 [CATrainingPosCal] consider 1 rank data
5066 12:38:33.507665 u2DelayCellTimex100 = 270/100 ps
5067 12:38:33.511357 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5068 12:38:33.514307 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5069 12:38:33.517735 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5070 12:38:33.520691 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5071 12:38:33.524188 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5072 12:38:33.527576 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5073 12:38:33.527647
5074 12:38:33.533876 CA PerBit enable=1, Macro0, CA PI delay=34
5075 12:38:33.533974
5076 12:38:33.534062 [CBTSetCACLKResult] CA Dly = 34
5077 12:38:33.537657 CS Dly: 6 (0~37)
5078 12:38:33.537737 ==
5079 12:38:33.541048 Dram Type= 6, Freq= 0, CH_0, rank 1
5080 12:38:33.544271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5081 12:38:33.544346 ==
5082 12:38:33.551090 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5083 12:38:33.557854 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5084 12:38:33.560780 [CA 0] Center 38 (8~69) winsize 62
5085 12:38:33.564164 [CA 1] Center 38 (8~69) winsize 62
5086 12:38:33.567743 [CA 2] Center 35 (5~66) winsize 62
5087 12:38:33.571015 [CA 3] Center 35 (5~66) winsize 62
5088 12:38:33.574788 [CA 4] Center 33 (3~64) winsize 62
5089 12:38:33.577731 [CA 5] Center 33 (3~64) winsize 62
5090 12:38:33.577802
5091 12:38:33.581330 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5092 12:38:33.581400
5093 12:38:33.584502 [CATrainingPosCal] consider 2 rank data
5094 12:38:33.587467 u2DelayCellTimex100 = 270/100 ps
5095 12:38:33.591215 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5096 12:38:33.594107 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5097 12:38:33.597840 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5098 12:38:33.600991 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5099 12:38:33.604490 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5100 12:38:33.607504 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5101 12:38:33.607599
5102 12:38:33.614322 CA PerBit enable=1, Macro0, CA PI delay=34
5103 12:38:33.614453
5104 12:38:33.614515 [CBTSetCACLKResult] CA Dly = 34
5105 12:38:33.617450 CS Dly: 7 (0~39)
5106 12:38:33.617530
5107 12:38:33.621000 ----->DramcWriteLeveling(PI) begin...
5108 12:38:33.621070 ==
5109 12:38:33.624835 Dram Type= 6, Freq= 0, CH_0, rank 0
5110 12:38:33.627821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5111 12:38:33.627901 ==
5112 12:38:33.630813 Write leveling (Byte 0): 33 => 33
5113 12:38:33.634596 Write leveling (Byte 1): 26 => 26
5114 12:38:33.637680 DramcWriteLeveling(PI) end<-----
5115 12:38:33.637747
5116 12:38:33.637806 ==
5117 12:38:33.641173 Dram Type= 6, Freq= 0, CH_0, rank 0
5118 12:38:33.644546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5119 12:38:33.647459 ==
5120 12:38:33.647531 [Gating] SW mode calibration
5121 12:38:33.654174 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5122 12:38:33.661273 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5123 12:38:33.663993 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5124 12:38:33.670741 0 14 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5125 12:38:33.674558 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5126 12:38:33.677819 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5127 12:38:33.684070 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5128 12:38:33.687544 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 12:38:33.690939 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 12:38:33.697957 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 12:38:33.700914 0 15 0 | B1->B0 | 3232 2a2a | 1 0 | (1 0) (0 0)
5132 12:38:33.704486 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5133 12:38:33.707518 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5134 12:38:33.714221 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5135 12:38:33.718198 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5136 12:38:33.720638 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 12:38:33.727641 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 12:38:33.731101 0 15 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5139 12:38:33.734193 1 0 0 | B1->B0 | 3030 4242 | 0 0 | (1 1) (0 0)
5140 12:38:33.741178 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 12:38:33.744101 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 12:38:33.747855 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 12:38:33.754363 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 12:38:33.757637 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 12:38:33.760864 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 12:38:33.767583 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 12:38:33.770877 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5148 12:38:33.774203 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5149 12:38:33.780668 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5150 12:38:33.784357 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 12:38:33.788034 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 12:38:33.791097 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 12:38:33.797747 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 12:38:33.801373 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 12:38:33.804244 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 12:38:33.811486 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 12:38:33.814466 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 12:38:33.817506 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 12:38:33.824292 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 12:38:33.827537 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 12:38:33.830968 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 12:38:33.838118 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5163 12:38:33.841355 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5164 12:38:33.844483 Total UI for P1: 0, mck2ui 16
5165 12:38:33.847669 best dqsien dly found for B0: ( 1, 2, 28)
5166 12:38:33.851511 Total UI for P1: 0, mck2ui 16
5167 12:38:33.854764 best dqsien dly found for B1: ( 1, 2, 28)
5168 12:38:33.857401 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5169 12:38:33.861069 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5170 12:38:33.861171
5171 12:38:33.864529 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5172 12:38:33.867924 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5173 12:38:33.870984 [Gating] SW calibration Done
5174 12:38:33.871081 ==
5175 12:38:33.874448 Dram Type= 6, Freq= 0, CH_0, rank 0
5176 12:38:33.878040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5177 12:38:33.878134 ==
5178 12:38:33.881554 RX Vref Scan: 0
5179 12:38:33.881660
5180 12:38:33.884537 RX Vref 0 -> 0, step: 1
5181 12:38:33.884642
5182 12:38:33.884734 RX Delay -80 -> 252, step: 8
5183 12:38:33.891030 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5184 12:38:33.894283 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5185 12:38:33.897955 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200
5186 12:38:33.901113 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5187 12:38:33.904988 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5188 12:38:33.908009 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5189 12:38:33.914663 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5190 12:38:33.917948 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5191 12:38:33.921183 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5192 12:38:33.924839 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5193 12:38:33.927842 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5194 12:38:33.934816 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5195 12:38:33.937948 iDelay=200, Bit 12, Center 91 (-8 ~ 191) 200
5196 12:38:33.941239 iDelay=200, Bit 13, Center 91 (-8 ~ 191) 200
5197 12:38:33.944530 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5198 12:38:33.948514 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5199 12:38:33.948593 ==
5200 12:38:33.951161 Dram Type= 6, Freq= 0, CH_0, rank 0
5201 12:38:33.954816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5202 12:38:33.957853 ==
5203 12:38:33.957919 DQS Delay:
5204 12:38:33.957983 DQS0 = 0, DQS1 = 0
5205 12:38:33.961577 DQM Delay:
5206 12:38:33.961642 DQM0 = 97, DQM1 = 86
5207 12:38:33.964932 DQ Delay:
5208 12:38:33.964997 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5209 12:38:33.968790 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5210 12:38:33.971545 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5211 12:38:33.975129 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5212 12:38:33.978237
5213 12:38:33.978310
5214 12:38:33.978369 ==
5215 12:38:33.981265 Dram Type= 6, Freq= 0, CH_0, rank 0
5216 12:38:33.984808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5217 12:38:33.984880 ==
5218 12:38:33.984948
5219 12:38:33.985005
5220 12:38:33.988101 TX Vref Scan disable
5221 12:38:33.988170 == TX Byte 0 ==
5222 12:38:33.994830 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5223 12:38:33.998064 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5224 12:38:33.998138 == TX Byte 1 ==
5225 12:38:34.005056 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5226 12:38:34.008453 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5227 12:38:34.008522 ==
5228 12:38:34.011615 Dram Type= 6, Freq= 0, CH_0, rank 0
5229 12:38:34.014706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5230 12:38:34.014781 ==
5231 12:38:34.014842
5232 12:38:34.014898
5233 12:38:34.018277 TX Vref Scan disable
5234 12:38:34.021657 == TX Byte 0 ==
5235 12:38:34.024833 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5236 12:38:34.028449 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5237 12:38:34.031477 == TX Byte 1 ==
5238 12:38:34.035115 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5239 12:38:34.038350 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5240 12:38:34.038491
5241 12:38:34.042048 [DATLAT]
5242 12:38:34.042125 Freq=933, CH0 RK0
5243 12:38:34.042194
5244 12:38:34.044806 DATLAT Default: 0xd
5245 12:38:34.044876 0, 0xFFFF, sum = 0
5246 12:38:34.048322 1, 0xFFFF, sum = 0
5247 12:38:34.048415 2, 0xFFFF, sum = 0
5248 12:38:34.052127 3, 0xFFFF, sum = 0
5249 12:38:34.052229 4, 0xFFFF, sum = 0
5250 12:38:34.055139 5, 0xFFFF, sum = 0
5251 12:38:34.055222 6, 0xFFFF, sum = 0
5252 12:38:34.059064 7, 0xFFFF, sum = 0
5253 12:38:34.059173 8, 0xFFFF, sum = 0
5254 12:38:34.061520 9, 0xFFFF, sum = 0
5255 12:38:34.061594 10, 0x0, sum = 1
5256 12:38:34.065257 11, 0x0, sum = 2
5257 12:38:34.065332 12, 0x0, sum = 3
5258 12:38:34.068295 13, 0x0, sum = 4
5259 12:38:34.068371 best_step = 11
5260 12:38:34.068433
5261 12:38:34.068490 ==
5262 12:38:34.071592 Dram Type= 6, Freq= 0, CH_0, rank 0
5263 12:38:34.075249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5264 12:38:34.078214 ==
5265 12:38:34.078304 RX Vref Scan: 1
5266 12:38:34.078393
5267 12:38:34.081724 RX Vref 0 -> 0, step: 1
5268 12:38:34.081807
5269 12:38:34.084950 RX Delay -61 -> 252, step: 4
5270 12:38:34.085041
5271 12:38:34.085129 Set Vref, RX VrefLevel [Byte0]: 53
5272 12:38:34.088676 [Byte1]: 52
5273 12:38:34.093307
5274 12:38:34.093407 Final RX Vref Byte 0 = 53 to rank0
5275 12:38:34.097266 Final RX Vref Byte 1 = 52 to rank0
5276 12:38:34.100136 Final RX Vref Byte 0 = 53 to rank1
5277 12:38:34.103403 Final RX Vref Byte 1 = 52 to rank1==
5278 12:38:34.107054 Dram Type= 6, Freq= 0, CH_0, rank 0
5279 12:38:34.113899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5280 12:38:34.113980 ==
5281 12:38:34.114043 DQS Delay:
5282 12:38:34.114102 DQS0 = 0, DQS1 = 0
5283 12:38:34.116777 DQM Delay:
5284 12:38:34.116844 DQM0 = 96, DQM1 = 88
5285 12:38:34.119953 DQ Delay:
5286 12:38:34.123385 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =94
5287 12:38:34.127031 DQ4 =98, DQ5 =86, DQ6 =104, DQ7 =102
5288 12:38:34.129948 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =82
5289 12:38:34.133274 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =96
5290 12:38:34.133344
5291 12:38:34.133403
5292 12:38:34.140230 [DQSOSCAuto] RK0, (LSB)MR18= 0x10fb, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 416 ps
5293 12:38:34.143301 CH0 RK0: MR19=504, MR18=10FB
5294 12:38:34.150561 CH0_RK0: MR19=0x504, MR18=0x10FB, DQSOSC=416, MR23=63, INC=62, DEC=41
5295 12:38:34.150634
5296 12:38:34.153223 ----->DramcWriteLeveling(PI) begin...
5297 12:38:34.153300 ==
5298 12:38:34.156621 Dram Type= 6, Freq= 0, CH_0, rank 1
5299 12:38:34.160934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5300 12:38:34.161011 ==
5301 12:38:34.163345 Write leveling (Byte 0): 29 => 29
5302 12:38:34.166921 Write leveling (Byte 1): 29 => 29
5303 12:38:34.170051 DramcWriteLeveling(PI) end<-----
5304 12:38:34.170121
5305 12:38:34.170187 ==
5306 12:38:34.173632 Dram Type= 6, Freq= 0, CH_0, rank 1
5307 12:38:34.176854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5308 12:38:34.176926 ==
5309 12:38:34.179912 [Gating] SW mode calibration
5310 12:38:34.186650 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5311 12:38:34.193682 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5312 12:38:34.196994 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5313 12:38:34.200418 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5314 12:38:34.207166 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5315 12:38:34.209932 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5316 12:38:34.213234 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5317 12:38:34.220777 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5318 12:38:34.223342 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5319 12:38:34.226647 0 14 28 | B1->B0 | 3131 2e2e | 1 0 | (1 0) (0 0)
5320 12:38:34.233238 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5321 12:38:34.237093 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 12:38:34.240540 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5323 12:38:34.246786 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5324 12:38:34.250579 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5325 12:38:34.253799 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5326 12:38:34.257217 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 12:38:34.263942 0 15 28 | B1->B0 | 2727 3131 | 0 0 | (0 0) (0 0)
5328 12:38:34.267498 1 0 0 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
5329 12:38:34.270501 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 12:38:34.276863 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 12:38:34.280929 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 12:38:34.284244 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 12:38:34.290749 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 12:38:34.293693 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 12:38:34.297314 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5336 12:38:34.303907 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5337 12:38:34.307038 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5338 12:38:34.310799 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 12:38:34.317240 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 12:38:34.320641 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 12:38:34.324156 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 12:38:34.326959 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 12:38:34.333853 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 12:38:34.337389 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 12:38:34.340504 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 12:38:34.347256 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 12:38:34.350609 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 12:38:34.353801 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 12:38:34.360653 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 12:38:34.364423 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 12:38:34.367590 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5352 12:38:34.373908 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5353 12:38:34.373992 Total UI for P1: 0, mck2ui 16
5354 12:38:34.380976 best dqsien dly found for B0: ( 1, 2, 28)
5355 12:38:34.383833 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5356 12:38:34.387724 Total UI for P1: 0, mck2ui 16
5357 12:38:34.390728 best dqsien dly found for B1: ( 1, 3, 0)
5358 12:38:34.394328 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5359 12:38:34.397329 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5360 12:38:34.397414
5361 12:38:34.400506 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5362 12:38:34.403988 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5363 12:38:34.407458 [Gating] SW calibration Done
5364 12:38:34.407530 ==
5365 12:38:34.410653 Dram Type= 6, Freq= 0, CH_0, rank 1
5366 12:38:34.413865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5367 12:38:34.413939 ==
5368 12:38:34.417675 RX Vref Scan: 0
5369 12:38:34.417750
5370 12:38:34.420616 RX Vref 0 -> 0, step: 1
5371 12:38:34.420693
5372 12:38:34.420753 RX Delay -80 -> 252, step: 8
5373 12:38:34.427511 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5374 12:38:34.430674 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5375 12:38:34.434623 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5376 12:38:34.437361 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5377 12:38:34.440581 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5378 12:38:34.444294 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5379 12:38:34.450340 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5380 12:38:34.454079 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5381 12:38:34.457108 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5382 12:38:34.460338 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5383 12:38:34.463848 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5384 12:38:34.467117 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5385 12:38:34.474131 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5386 12:38:34.477209 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5387 12:38:34.480719 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5388 12:38:34.483585 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5389 12:38:34.483655 ==
5390 12:38:34.486906 Dram Type= 6, Freq= 0, CH_0, rank 1
5391 12:38:34.490674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5392 12:38:34.493742 ==
5393 12:38:34.493813 DQS Delay:
5394 12:38:34.493873 DQS0 = 0, DQS1 = 0
5395 12:38:34.496991 DQM Delay:
5396 12:38:34.497064 DQM0 = 97, DQM1 = 89
5397 12:38:34.497123 DQ Delay:
5398 12:38:34.500224 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5399 12:38:34.503988 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5400 12:38:34.507239 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =83
5401 12:38:34.510282 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5402 12:38:34.510359
5403 12:38:34.514048
5404 12:38:34.514122 ==
5405 12:38:34.517141 Dram Type= 6, Freq= 0, CH_0, rank 1
5406 12:38:34.520797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5407 12:38:34.520875 ==
5408 12:38:34.520936
5409 12:38:34.520997
5410 12:38:34.523798 TX Vref Scan disable
5411 12:38:34.523873 == TX Byte 0 ==
5412 12:38:34.530831 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5413 12:38:34.533668 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5414 12:38:34.533744 == TX Byte 1 ==
5415 12:38:34.537033 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5416 12:38:34.543603 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5417 12:38:34.543680 ==
5418 12:38:34.547052 Dram Type= 6, Freq= 0, CH_0, rank 1
5419 12:38:34.550526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5420 12:38:34.550604 ==
5421 12:38:34.550667
5422 12:38:34.550733
5423 12:38:34.553669 TX Vref Scan disable
5424 12:38:34.557185 == TX Byte 0 ==
5425 12:38:34.560694 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5426 12:38:34.564084 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5427 12:38:34.567215 == TX Byte 1 ==
5428 12:38:34.570529 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5429 12:38:34.573872 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5430 12:38:34.573946
5431 12:38:34.577380 [DATLAT]
5432 12:38:34.577452 Freq=933, CH0 RK1
5433 12:38:34.577512
5434 12:38:34.580419 DATLAT Default: 0xb
5435 12:38:34.580489 0, 0xFFFF, sum = 0
5436 12:38:34.583543 1, 0xFFFF, sum = 0
5437 12:38:34.583614 2, 0xFFFF, sum = 0
5438 12:38:34.587215 3, 0xFFFF, sum = 0
5439 12:38:34.587287 4, 0xFFFF, sum = 0
5440 12:38:34.590618 5, 0xFFFF, sum = 0
5441 12:38:34.590691 6, 0xFFFF, sum = 0
5442 12:38:34.593837 7, 0xFFFF, sum = 0
5443 12:38:34.593926 8, 0xFFFF, sum = 0
5444 12:38:34.597458 9, 0xFFFF, sum = 0
5445 12:38:34.597532 10, 0x0, sum = 1
5446 12:38:34.600529 11, 0x0, sum = 2
5447 12:38:34.600604 12, 0x0, sum = 3
5448 12:38:34.603817 13, 0x0, sum = 4
5449 12:38:34.603900 best_step = 11
5450 12:38:34.603959
5451 12:38:34.604020 ==
5452 12:38:34.607134 Dram Type= 6, Freq= 0, CH_0, rank 1
5453 12:38:34.610116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5454 12:38:34.613552 ==
5455 12:38:34.613627 RX Vref Scan: 0
5456 12:38:34.613689
5457 12:38:34.617153 RX Vref 0 -> 0, step: 1
5458 12:38:34.617224
5459 12:38:34.617284 RX Delay -61 -> 252, step: 4
5460 12:38:34.625356 iDelay=199, Bit 0, Center 94 (-1 ~ 190) 192
5461 12:38:34.628411 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5462 12:38:34.631617 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5463 12:38:34.634995 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5464 12:38:34.638244 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5465 12:38:34.641890 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5466 12:38:34.648466 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5467 12:38:34.651381 iDelay=199, Bit 7, Center 104 (15 ~ 194) 180
5468 12:38:34.655121 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5469 12:38:34.658276 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5470 12:38:34.661270 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5471 12:38:34.667921 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5472 12:38:34.671468 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5473 12:38:34.674984 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5474 12:38:34.677785 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5475 12:38:34.681514 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5476 12:38:34.681585 ==
5477 12:38:34.685035 Dram Type= 6, Freq= 0, CH_0, rank 1
5478 12:38:34.691263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5479 12:38:34.691345 ==
5480 12:38:34.691408 DQS Delay:
5481 12:38:34.694422 DQS0 = 0, DQS1 = 0
5482 12:38:34.694492 DQM Delay:
5483 12:38:34.694551 DQM0 = 95, DQM1 = 87
5484 12:38:34.698098 DQ Delay:
5485 12:38:34.701337 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =94
5486 12:38:34.704550 DQ4 =94, DQ5 =84, DQ6 =106, DQ7 =104
5487 12:38:34.708421 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =78
5488 12:38:34.711141 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =96
5489 12:38:34.711217
5490 12:38:34.711277
5491 12:38:34.717917 [DQSOSCAuto] RK1, (LSB)MR18= 0x1603, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 414 ps
5492 12:38:34.721490 CH0 RK1: MR19=505, MR18=1603
5493 12:38:34.728150 CH0_RK1: MR19=0x505, MR18=0x1603, DQSOSC=414, MR23=63, INC=63, DEC=42
5494 12:38:34.731790 [RxdqsGatingPostProcess] freq 933
5495 12:38:34.734681 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5496 12:38:34.737818 best DQS0 dly(2T, 0.5T) = (0, 10)
5497 12:38:34.741053 best DQS1 dly(2T, 0.5T) = (0, 10)
5498 12:38:34.744573 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5499 12:38:34.747707 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5500 12:38:34.750934 best DQS0 dly(2T, 0.5T) = (0, 10)
5501 12:38:34.754308 best DQS1 dly(2T, 0.5T) = (0, 11)
5502 12:38:34.757615 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5503 12:38:34.760793 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5504 12:38:34.764518 Pre-setting of DQS Precalculation
5505 12:38:34.767846 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5506 12:38:34.767927 ==
5507 12:38:34.771736 Dram Type= 6, Freq= 0, CH_1, rank 0
5508 12:38:34.777943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5509 12:38:34.778018 ==
5510 12:38:34.781680 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5511 12:38:34.787932 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5512 12:38:34.791050 [CA 0] Center 36 (6~67) winsize 62
5513 12:38:34.794148 [CA 1] Center 36 (6~67) winsize 62
5514 12:38:34.797720 [CA 2] Center 34 (4~64) winsize 61
5515 12:38:34.800928 [CA 3] Center 33 (3~64) winsize 62
5516 12:38:34.804170 [CA 4] Center 34 (4~65) winsize 62
5517 12:38:34.807814 [CA 5] Center 33 (3~63) winsize 61
5518 12:38:34.807886
5519 12:38:34.810804 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5520 12:38:34.810877
5521 12:38:34.814848 [CATrainingPosCal] consider 1 rank data
5522 12:38:34.817632 u2DelayCellTimex100 = 270/100 ps
5523 12:38:34.820981 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5524 12:38:34.824462 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5525 12:38:34.831108 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5526 12:38:34.834570 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5527 12:38:34.838217 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5528 12:38:34.841168 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5529 12:38:34.841240
5530 12:38:34.844294 CA PerBit enable=1, Macro0, CA PI delay=33
5531 12:38:34.844361
5532 12:38:34.847830 [CBTSetCACLKResult] CA Dly = 33
5533 12:38:34.847900 CS Dly: 4 (0~35)
5534 12:38:34.847960 ==
5535 12:38:34.850912 Dram Type= 6, Freq= 0, CH_1, rank 1
5536 12:38:34.857650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5537 12:38:34.857731 ==
5538 12:38:34.861095 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5539 12:38:34.868213 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5540 12:38:34.871395 [CA 0] Center 36 (6~67) winsize 62
5541 12:38:34.874317 [CA 1] Center 36 (6~67) winsize 62
5542 12:38:34.878248 [CA 2] Center 34 (4~64) winsize 61
5543 12:38:34.880955 [CA 3] Center 33 (3~64) winsize 62
5544 12:38:34.884823 [CA 4] Center 34 (4~64) winsize 61
5545 12:38:34.887642 [CA 5] Center 32 (2~63) winsize 62
5546 12:38:34.887710
5547 12:38:34.891069 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5548 12:38:34.891136
5549 12:38:34.894508 [CATrainingPosCal] consider 2 rank data
5550 12:38:34.898206 u2DelayCellTimex100 = 270/100 ps
5551 12:38:34.901430 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5552 12:38:34.904978 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5553 12:38:34.908002 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5554 12:38:34.914347 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5555 12:38:34.918343 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5556 12:38:34.921340 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5557 12:38:34.921408
5558 12:38:34.924424 CA PerBit enable=1, Macro0, CA PI delay=33
5559 12:38:34.924490
5560 12:38:34.927812 [CBTSetCACLKResult] CA Dly = 33
5561 12:38:34.927878 CS Dly: 5 (0~37)
5562 12:38:34.927941
5563 12:38:34.931291 ----->DramcWriteLeveling(PI) begin...
5564 12:38:34.931361 ==
5565 12:38:34.934939 Dram Type= 6, Freq= 0, CH_1, rank 0
5566 12:38:34.941962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5567 12:38:34.942037 ==
5568 12:38:34.944524 Write leveling (Byte 0): 27 => 27
5569 12:38:34.944606 Write leveling (Byte 1): 27 => 27
5570 12:38:34.948153 DramcWriteLeveling(PI) end<-----
5571 12:38:34.948230
5572 12:38:34.948291 ==
5573 12:38:34.951908 Dram Type= 6, Freq= 0, CH_1, rank 0
5574 12:38:34.958726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5575 12:38:34.958802 ==
5576 12:38:34.961920 [Gating] SW mode calibration
5577 12:38:34.968194 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5578 12:38:34.971576 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5579 12:38:34.978647 0 14 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5580 12:38:34.981997 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5581 12:38:34.985220 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5582 12:38:34.988908 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5583 12:38:34.995213 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5584 12:38:34.998343 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5585 12:38:35.001438 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 12:38:35.008409 0 14 28 | B1->B0 | 3333 3030 | 1 1 | (1 0) (1 0)
5587 12:38:35.011594 0 15 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
5588 12:38:35.015374 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5589 12:38:35.021535 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5590 12:38:35.024848 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5591 12:38:35.028219 0 15 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5592 12:38:35.034863 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5593 12:38:35.038361 0 15 24 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
5594 12:38:35.041640 0 15 28 | B1->B0 | 3232 2e2e | 0 0 | (0 0) (0 0)
5595 12:38:35.049103 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 12:38:35.051843 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 12:38:35.055242 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 12:38:35.062130 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 12:38:35.065349 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 12:38:35.068330 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 12:38:35.075102 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 12:38:35.078296 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5603 12:38:35.081718 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5604 12:38:35.085204 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 12:38:35.091354 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 12:38:35.094663 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 12:38:35.098272 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 12:38:35.104688 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 12:38:35.108592 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 12:38:35.111984 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 12:38:35.118640 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 12:38:35.121914 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 12:38:35.125210 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 12:38:35.132118 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 12:38:35.135078 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 12:38:35.138268 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 12:38:35.145313 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 12:38:35.148236 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5619 12:38:35.151955 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5620 12:38:35.158996 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5621 12:38:35.159076 Total UI for P1: 0, mck2ui 16
5622 12:38:35.162021 best dqsien dly found for B0: ( 1, 2, 30)
5623 12:38:35.165468 Total UI for P1: 0, mck2ui 16
5624 12:38:35.168569 best dqsien dly found for B1: ( 1, 2, 30)
5625 12:38:35.171874 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5626 12:38:35.175318 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5627 12:38:35.178558
5628 12:38:35.182193 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5629 12:38:35.185343 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5630 12:38:35.189109 [Gating] SW calibration Done
5631 12:38:35.189191 ==
5632 12:38:35.192109 Dram Type= 6, Freq= 0, CH_1, rank 0
5633 12:38:35.195260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5634 12:38:35.195342 ==
5635 12:38:35.195425 RX Vref Scan: 0
5636 12:38:35.195522
5637 12:38:35.198979 RX Vref 0 -> 0, step: 1
5638 12:38:35.199076
5639 12:38:35.202172 RX Delay -80 -> 252, step: 8
5640 12:38:35.205561 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5641 12:38:35.208922 iDelay=200, Bit 1, Center 95 (0 ~ 191) 192
5642 12:38:35.212257 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5643 12:38:35.218586 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5644 12:38:35.221913 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5645 12:38:35.225377 iDelay=200, Bit 5, Center 107 (16 ~ 199) 184
5646 12:38:35.228626 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5647 12:38:35.232569 iDelay=200, Bit 7, Center 95 (0 ~ 191) 192
5648 12:38:35.235643 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5649 12:38:35.241740 iDelay=200, Bit 9, Center 75 (-24 ~ 175) 200
5650 12:38:35.245164 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5651 12:38:35.248795 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5652 12:38:35.252112 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5653 12:38:35.255249 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5654 12:38:35.261768 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5655 12:38:35.265159 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5656 12:38:35.265230 ==
5657 12:38:35.269156 Dram Type= 6, Freq= 0, CH_1, rank 0
5658 12:38:35.271944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5659 12:38:35.272016 ==
5660 12:38:35.272083 DQS Delay:
5661 12:38:35.275045 DQS0 = 0, DQS1 = 0
5662 12:38:35.275113 DQM Delay:
5663 12:38:35.278282 DQM0 = 97, DQM1 = 88
5664 12:38:35.278351 DQ Delay:
5665 12:38:35.281874 DQ0 =99, DQ1 =95, DQ2 =83, DQ3 =95
5666 12:38:35.285109 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5667 12:38:35.288399 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =87
5668 12:38:35.291842 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5669 12:38:35.291918
5670 12:38:35.291978
5671 12:38:35.292034 ==
5672 12:38:35.294977 Dram Type= 6, Freq= 0, CH_1, rank 0
5673 12:38:35.298720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5674 12:38:35.298789 ==
5675 12:38:35.301845
5676 12:38:35.301913
5677 12:38:35.301971 TX Vref Scan disable
5678 12:38:35.305276 == TX Byte 0 ==
5679 12:38:35.308752 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5680 12:38:35.311728 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5681 12:38:35.315336 == TX Byte 1 ==
5682 12:38:35.318652 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5683 12:38:35.321980 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5684 12:38:35.322051 ==
5685 12:38:35.325384 Dram Type= 6, Freq= 0, CH_1, rank 0
5686 12:38:35.331990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5687 12:38:35.332064 ==
5688 12:38:35.332133
5689 12:38:35.332191
5690 12:38:35.332246 TX Vref Scan disable
5691 12:38:35.335975 == TX Byte 0 ==
5692 12:38:35.339475 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5693 12:38:35.343108 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5694 12:38:35.345975 == TX Byte 1 ==
5695 12:38:35.349624 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5696 12:38:35.352712 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5697 12:38:35.356389
5698 12:38:35.356458 [DATLAT]
5699 12:38:35.356519 Freq=933, CH1 RK0
5700 12:38:35.356584
5701 12:38:35.359522 DATLAT Default: 0xd
5702 12:38:35.359593 0, 0xFFFF, sum = 0
5703 12:38:35.363004 1, 0xFFFF, sum = 0
5704 12:38:35.363075 2, 0xFFFF, sum = 0
5705 12:38:35.366236 3, 0xFFFF, sum = 0
5706 12:38:35.366305 4, 0xFFFF, sum = 0
5707 12:38:35.369608 5, 0xFFFF, sum = 0
5708 12:38:35.372616 6, 0xFFFF, sum = 0
5709 12:38:35.372714 7, 0xFFFF, sum = 0
5710 12:38:35.375911 8, 0xFFFF, sum = 0
5711 12:38:35.376007 9, 0xFFFF, sum = 0
5712 12:38:35.379109 10, 0x0, sum = 1
5713 12:38:35.379195 11, 0x0, sum = 2
5714 12:38:35.379292 12, 0x0, sum = 3
5715 12:38:35.382902 13, 0x0, sum = 4
5716 12:38:35.382983 best_step = 11
5717 12:38:35.383045
5718 12:38:35.385874 ==
5719 12:38:35.385954 Dram Type= 6, Freq= 0, CH_1, rank 0
5720 12:38:35.392975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5721 12:38:35.393056 ==
5722 12:38:35.393120 RX Vref Scan: 1
5723 12:38:35.393178
5724 12:38:35.395757 RX Vref 0 -> 0, step: 1
5725 12:38:35.395836
5726 12:38:35.399297 RX Delay -69 -> 252, step: 4
5727 12:38:35.399381
5728 12:38:35.403491 Set Vref, RX VrefLevel [Byte0]: 56
5729 12:38:35.406180 [Byte1]: 51
5730 12:38:35.406285
5731 12:38:35.409507 Final RX Vref Byte 0 = 56 to rank0
5732 12:38:35.412750 Final RX Vref Byte 1 = 51 to rank0
5733 12:38:35.415948 Final RX Vref Byte 0 = 56 to rank1
5734 12:38:35.419038 Final RX Vref Byte 1 = 51 to rank1==
5735 12:38:35.422776 Dram Type= 6, Freq= 0, CH_1, rank 0
5736 12:38:35.426029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 12:38:35.426110 ==
5738 12:38:35.429057 DQS Delay:
5739 12:38:35.429137 DQS0 = 0, DQS1 = 0
5740 12:38:35.433014 DQM Delay:
5741 12:38:35.433094 DQM0 = 97, DQM1 = 90
5742 12:38:35.433159 DQ Delay:
5743 12:38:35.435823 DQ0 =100, DQ1 =92, DQ2 =86, DQ3 =96
5744 12:38:35.439163 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5745 12:38:35.442802 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =86
5746 12:38:35.445779 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =96
5747 12:38:35.448710
5748 12:38:35.448789
5749 12:38:35.455505 [DQSOSCAuto] RK0, (LSB)MR18= 0x13f0, (MSB)MR19= 0x504, tDQSOscB0 = 427 ps tDQSOscB1 = 415 ps
5750 12:38:35.459280 CH1 RK0: MR19=504, MR18=13F0
5751 12:38:35.465765 CH1_RK0: MR19=0x504, MR18=0x13F0, DQSOSC=415, MR23=63, INC=62, DEC=41
5752 12:38:35.465874
5753 12:38:35.469063 ----->DramcWriteLeveling(PI) begin...
5754 12:38:35.469146 ==
5755 12:38:35.472064 Dram Type= 6, Freq= 0, CH_1, rank 1
5756 12:38:35.475209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5757 12:38:35.475290 ==
5758 12:38:35.478508 Write leveling (Byte 0): 28 => 28
5759 12:38:35.481777 Write leveling (Byte 1): 25 => 25
5760 12:38:35.485362 DramcWriteLeveling(PI) end<-----
5761 12:38:35.485446
5762 12:38:35.485529 ==
5763 12:38:35.488655 Dram Type= 6, Freq= 0, CH_1, rank 1
5764 12:38:35.492568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5765 12:38:35.492652 ==
5766 12:38:35.495332 [Gating] SW mode calibration
5767 12:38:35.502004 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5768 12:38:35.508834 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5769 12:38:35.511875 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5770 12:38:35.515398 0 14 4 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
5771 12:38:35.522021 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5772 12:38:35.525245 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5773 12:38:35.528611 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5774 12:38:35.535330 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5775 12:38:35.538966 0 14 24 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
5776 12:38:35.542128 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (0 1) (0 0)
5777 12:38:35.549035 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5778 12:38:35.552103 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5779 12:38:35.555387 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5780 12:38:35.562206 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5781 12:38:35.565515 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5782 12:38:35.568892 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 12:38:35.572096 0 15 24 | B1->B0 | 2525 2f2f | 0 1 | (0 0) (0 0)
5784 12:38:35.578823 0 15 28 | B1->B0 | 3a3a 4141 | 0 0 | (0 0) (0 0)
5785 12:38:35.582451 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 12:38:35.585887 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5787 12:38:35.591917 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5788 12:38:35.595502 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 12:38:35.598949 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 12:38:35.605723 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 12:38:35.609182 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5792 12:38:35.612407 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5793 12:38:35.618794 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 12:38:35.622591 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 12:38:35.625810 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 12:38:35.632386 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 12:38:35.635597 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 12:38:35.639067 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 12:38:35.645367 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 12:38:35.649353 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 12:38:35.652350 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 12:38:35.658902 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 12:38:35.662655 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 12:38:35.665511 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 12:38:35.668753 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 12:38:35.675966 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5807 12:38:35.679606 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5808 12:38:35.682520 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5809 12:38:35.686086 Total UI for P1: 0, mck2ui 16
5810 12:38:35.689042 best dqsien dly found for B0: ( 1, 2, 22)
5811 12:38:35.695643 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 12:38:35.695725 Total UI for P1: 0, mck2ui 16
5813 12:38:35.703045 best dqsien dly found for B1: ( 1, 2, 28)
5814 12:38:35.705525 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5815 12:38:35.709216 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5816 12:38:35.709296
5817 12:38:35.712920 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5818 12:38:35.715895 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5819 12:38:35.719310 [Gating] SW calibration Done
5820 12:38:35.719391 ==
5821 12:38:35.722710 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 12:38:35.725819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 12:38:35.725900 ==
5824 12:38:35.729357 RX Vref Scan: 0
5825 12:38:35.729437
5826 12:38:35.729500 RX Vref 0 -> 0, step: 1
5827 12:38:35.729560
5828 12:38:35.732488 RX Delay -80 -> 252, step: 8
5829 12:38:35.736055 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5830 12:38:35.742359 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5831 12:38:35.746083 iDelay=200, Bit 2, Center 83 (-16 ~ 183) 200
5832 12:38:35.748946 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5833 12:38:35.752575 iDelay=200, Bit 4, Center 91 (-8 ~ 191) 200
5834 12:38:35.755643 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5835 12:38:35.759523 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5836 12:38:35.765787 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5837 12:38:35.769075 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5838 12:38:35.772602 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5839 12:38:35.776224 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5840 12:38:35.779039 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5841 12:38:35.782924 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5842 12:38:35.789603 iDelay=200, Bit 13, Center 99 (0 ~ 199) 200
5843 12:38:35.792842 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5844 12:38:35.795914 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5845 12:38:35.795996 ==
5846 12:38:35.799573 Dram Type= 6, Freq= 0, CH_1, rank 1
5847 12:38:35.802529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5848 12:38:35.802613 ==
5849 12:38:35.806236 DQS Delay:
5850 12:38:35.806341 DQS0 = 0, DQS1 = 0
5851 12:38:35.806460 DQM Delay:
5852 12:38:35.809254 DQM0 = 93, DQM1 = 88
5853 12:38:35.809337 DQ Delay:
5854 12:38:35.812547 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =95
5855 12:38:35.815759 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =87
5856 12:38:35.819450 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5857 12:38:35.822719 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5858 12:38:35.822799
5859 12:38:35.822863
5860 12:38:35.822921 ==
5861 12:38:35.826101 Dram Type= 6, Freq= 0, CH_1, rank 1
5862 12:38:35.832394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5863 12:38:35.832475 ==
5864 12:38:35.832538
5865 12:38:35.832597
5866 12:38:35.832653 TX Vref Scan disable
5867 12:38:35.836103 == TX Byte 0 ==
5868 12:38:35.839199 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5869 12:38:35.846060 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5870 12:38:35.846141 == TX Byte 1 ==
5871 12:38:35.849852 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5872 12:38:35.856369 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5873 12:38:35.856458 ==
5874 12:38:35.859597 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 12:38:35.863136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 12:38:35.863218 ==
5877 12:38:35.863301
5878 12:38:35.863378
5879 12:38:35.865814 TX Vref Scan disable
5880 12:38:35.865910 == TX Byte 0 ==
5881 12:38:35.872639 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5882 12:38:35.875952 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5883 12:38:35.876030 == TX Byte 1 ==
5884 12:38:35.882639 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5885 12:38:35.886285 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5886 12:38:35.886360
5887 12:38:35.886477 [DATLAT]
5888 12:38:35.889362 Freq=933, CH1 RK1
5889 12:38:35.889446
5890 12:38:35.889529 DATLAT Default: 0xb
5891 12:38:35.892651 0, 0xFFFF, sum = 0
5892 12:38:35.892735 1, 0xFFFF, sum = 0
5893 12:38:35.896104 2, 0xFFFF, sum = 0
5894 12:38:35.896206 3, 0xFFFF, sum = 0
5895 12:38:35.899458 4, 0xFFFF, sum = 0
5896 12:38:35.899568 5, 0xFFFF, sum = 0
5897 12:38:35.902832 6, 0xFFFF, sum = 0
5898 12:38:35.906049 7, 0xFFFF, sum = 0
5899 12:38:35.906133 8, 0xFFFF, sum = 0
5900 12:38:35.909502 9, 0xFFFF, sum = 0
5901 12:38:35.909586 10, 0x0, sum = 1
5902 12:38:35.909671 11, 0x0, sum = 2
5903 12:38:35.912553 12, 0x0, sum = 3
5904 12:38:35.912636 13, 0x0, sum = 4
5905 12:38:35.915922 best_step = 11
5906 12:38:35.916004
5907 12:38:35.916088 ==
5908 12:38:35.919551 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 12:38:35.922740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 12:38:35.922823 ==
5911 12:38:35.926535 RX Vref Scan: 0
5912 12:38:35.926618
5913 12:38:35.926702 RX Vref 0 -> 0, step: 1
5914 12:38:35.926781
5915 12:38:35.929659 RX Delay -61 -> 252, step: 4
5916 12:38:35.936913 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5917 12:38:35.939730 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5918 12:38:35.943423 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5919 12:38:35.946697 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5920 12:38:35.949944 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5921 12:38:35.953616 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5922 12:38:35.960239 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5923 12:38:35.963620 iDelay=199, Bit 7, Center 90 (-1 ~ 182) 184
5924 12:38:35.966926 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5925 12:38:35.969754 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5926 12:38:35.973421 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5927 12:38:35.979677 iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184
5928 12:38:35.983435 iDelay=199, Bit 12, Center 96 (7 ~ 186) 180
5929 12:38:35.986725 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5930 12:38:35.990292 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5931 12:38:35.993146 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
5932 12:38:35.993229 ==
5933 12:38:35.996224 Dram Type= 6, Freq= 0, CH_1, rank 1
5934 12:38:36.002855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5935 12:38:36.002940 ==
5936 12:38:36.003023 DQS Delay:
5937 12:38:36.003103 DQS0 = 0, DQS1 = 0
5938 12:38:36.006617 DQM Delay:
5939 12:38:36.006700 DQM0 = 95, DQM1 = 90
5940 12:38:36.009669 DQ Delay:
5941 12:38:36.012964 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =94
5942 12:38:36.016405 DQ4 =98, DQ5 =106, DQ6 =102, DQ7 =90
5943 12:38:36.019829 DQ8 =80, DQ9 =80, DQ10 =90, DQ11 =82
5944 12:38:36.023533 DQ12 =96, DQ13 =98, DQ14 =98, DQ15 =98
5945 12:38:36.023616
5946 12:38:36.023715
5947 12:38:36.029758 [DQSOSCAuto] RK1, (LSB)MR18= 0xe16, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
5948 12:38:36.033297 CH1 RK1: MR19=505, MR18=E16
5949 12:38:36.039751 CH1_RK1: MR19=0x505, MR18=0xE16, DQSOSC=414, MR23=63, INC=63, DEC=42
5950 12:38:36.043005 [RxdqsGatingPostProcess] freq 933
5951 12:38:36.046835 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5952 12:38:36.050051 best DQS0 dly(2T, 0.5T) = (0, 10)
5953 12:38:36.053166 best DQS1 dly(2T, 0.5T) = (0, 10)
5954 12:38:36.056630 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5955 12:38:36.059885 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5956 12:38:36.063639 best DQS0 dly(2T, 0.5T) = (0, 10)
5957 12:38:36.066457 best DQS1 dly(2T, 0.5T) = (0, 10)
5958 12:38:36.069555 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5959 12:38:36.073197 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5960 12:38:36.076200 Pre-setting of DQS Precalculation
5961 12:38:36.079417 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5962 12:38:36.086144 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5963 12:38:36.095943 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5964 12:38:36.096028
5965 12:38:36.096111
5966 12:38:36.096189 [Calibration Summary] 1866 Mbps
5967 12:38:36.099816 CH 0, Rank 0
5968 12:38:36.099898 SW Impedance : PASS
5969 12:38:36.103099 DUTY Scan : NO K
5970 12:38:36.106547 ZQ Calibration : PASS
5971 12:38:36.106630 Jitter Meter : NO K
5972 12:38:36.109571 CBT Training : PASS
5973 12:38:36.112867 Write leveling : PASS
5974 12:38:36.112949 RX DQS gating : PASS
5975 12:38:36.116197 RX DQ/DQS(RDDQC) : PASS
5976 12:38:36.120200 TX DQ/DQS : PASS
5977 12:38:36.120284 RX DATLAT : PASS
5978 12:38:36.122748 RX DQ/DQS(Engine): PASS
5979 12:38:36.126138 TX OE : NO K
5980 12:38:36.126220 All Pass.
5981 12:38:36.126319
5982 12:38:36.126435 CH 0, Rank 1
5983 12:38:36.129817 SW Impedance : PASS
5984 12:38:36.133052 DUTY Scan : NO K
5985 12:38:36.133134 ZQ Calibration : PASS
5986 12:38:36.136271 Jitter Meter : NO K
5987 12:38:36.136353 CBT Training : PASS
5988 12:38:36.139842 Write leveling : PASS
5989 12:38:36.143112 RX DQS gating : PASS
5990 12:38:36.143194 RX DQ/DQS(RDDQC) : PASS
5991 12:38:36.146137 TX DQ/DQS : PASS
5992 12:38:36.150035 RX DATLAT : PASS
5993 12:38:36.150118 RX DQ/DQS(Engine): PASS
5994 12:38:36.153188 TX OE : NO K
5995 12:38:36.153286 All Pass.
5996 12:38:36.153371
5997 12:38:36.156709 CH 1, Rank 0
5998 12:38:36.156788 SW Impedance : PASS
5999 12:38:36.159579 DUTY Scan : NO K
6000 12:38:36.162805 ZQ Calibration : PASS
6001 12:38:36.162884 Jitter Meter : NO K
6002 12:38:36.166660 CBT Training : PASS
6003 12:38:36.170010 Write leveling : PASS
6004 12:38:36.170089 RX DQS gating : PASS
6005 12:38:36.173406 RX DQ/DQS(RDDQC) : PASS
6006 12:38:36.176579 TX DQ/DQS : PASS
6007 12:38:36.176660 RX DATLAT : PASS
6008 12:38:36.179405 RX DQ/DQS(Engine): PASS
6009 12:38:36.179485 TX OE : NO K
6010 12:38:36.183332 All Pass.
6011 12:38:36.183412
6012 12:38:36.183475 CH 1, Rank 1
6013 12:38:36.186360 SW Impedance : PASS
6014 12:38:36.186481 DUTY Scan : NO K
6015 12:38:36.189436 ZQ Calibration : PASS
6016 12:38:36.193031 Jitter Meter : NO K
6017 12:38:36.193143 CBT Training : PASS
6018 12:38:36.196546 Write leveling : PASS
6019 12:38:36.199658 RX DQS gating : PASS
6020 12:38:36.199738 RX DQ/DQS(RDDQC) : PASS
6021 12:38:36.202792 TX DQ/DQS : PASS
6022 12:38:36.206356 RX DATLAT : PASS
6023 12:38:36.206474 RX DQ/DQS(Engine): PASS
6024 12:38:36.209949 TX OE : NO K
6025 12:38:36.210030 All Pass.
6026 12:38:36.210093
6027 12:38:36.212769 DramC Write-DBI off
6028 12:38:36.216853 PER_BANK_REFRESH: Hybrid Mode
6029 12:38:36.216934 TX_TRACKING: ON
6030 12:38:36.226323 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6031 12:38:36.229499 [FAST_K] Save calibration result to emmc
6032 12:38:36.233063 dramc_set_vcore_voltage set vcore to 650000
6033 12:38:36.236768 Read voltage for 400, 6
6034 12:38:36.236852 Vio18 = 0
6035 12:38:36.236952 Vcore = 650000
6036 12:38:36.239517 Vdram = 0
6037 12:38:36.239597 Vddq = 0
6038 12:38:36.239661 Vmddr = 0
6039 12:38:36.246355 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6040 12:38:36.249943 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6041 12:38:36.253365 MEM_TYPE=3, freq_sel=20
6042 12:38:36.256185 sv_algorithm_assistance_LP4_800
6043 12:38:36.260052 ============ PULL DRAM RESETB DOWN ============
6044 12:38:36.263386 ========== PULL DRAM RESETB DOWN end =========
6045 12:38:36.270594 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6046 12:38:36.273558 ===================================
6047 12:38:36.273639 LPDDR4 DRAM CONFIGURATION
6048 12:38:36.276793 ===================================
6049 12:38:36.279687 EX_ROW_EN[0] = 0x0
6050 12:38:36.279767 EX_ROW_EN[1] = 0x0
6051 12:38:36.283151 LP4Y_EN = 0x0
6052 12:38:36.283238 WORK_FSP = 0x0
6053 12:38:36.287119 WL = 0x2
6054 12:38:36.289900 RL = 0x2
6055 12:38:36.289997 BL = 0x2
6056 12:38:36.293450 RPST = 0x0
6057 12:38:36.293531 RD_PRE = 0x0
6058 12:38:36.296591 WR_PRE = 0x1
6059 12:38:36.296671 WR_PST = 0x0
6060 12:38:36.300016 DBI_WR = 0x0
6061 12:38:36.300096 DBI_RD = 0x0
6062 12:38:36.303032 OTF = 0x1
6063 12:38:36.306684 ===================================
6064 12:38:36.309866 ===================================
6065 12:38:36.309946 ANA top config
6066 12:38:36.312954 ===================================
6067 12:38:36.316481 DLL_ASYNC_EN = 0
6068 12:38:36.319902 ALL_SLAVE_EN = 1
6069 12:38:36.319982 NEW_RANK_MODE = 1
6070 12:38:36.322932 DLL_IDLE_MODE = 1
6071 12:38:36.326294 LP45_APHY_COMB_EN = 1
6072 12:38:36.329472 TX_ODT_DIS = 1
6073 12:38:36.329578 NEW_8X_MODE = 1
6074 12:38:36.333176 ===================================
6075 12:38:36.336189 ===================================
6076 12:38:36.339735 data_rate = 800
6077 12:38:36.342969 CKR = 1
6078 12:38:36.346996 DQ_P2S_RATIO = 4
6079 12:38:36.349933 ===================================
6080 12:38:36.352944 CA_P2S_RATIO = 4
6081 12:38:36.356315 DQ_CA_OPEN = 0
6082 12:38:36.356396 DQ_SEMI_OPEN = 1
6083 12:38:36.359863 CA_SEMI_OPEN = 1
6084 12:38:36.363233 CA_FULL_RATE = 0
6085 12:38:36.366555 DQ_CKDIV4_EN = 0
6086 12:38:36.369537 CA_CKDIV4_EN = 1
6087 12:38:36.373242 CA_PREDIV_EN = 0
6088 12:38:36.373354 PH8_DLY = 0
6089 12:38:36.376581 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6090 12:38:36.379729 DQ_AAMCK_DIV = 0
6091 12:38:36.382914 CA_AAMCK_DIV = 0
6092 12:38:36.386910 CA_ADMCK_DIV = 4
6093 12:38:36.389644 DQ_TRACK_CA_EN = 0
6094 12:38:36.389724 CA_PICK = 800
6095 12:38:36.393010 CA_MCKIO = 400
6096 12:38:36.396476 MCKIO_SEMI = 400
6097 12:38:36.399962 PLL_FREQ = 3016
6098 12:38:36.402697 DQ_UI_PI_RATIO = 32
6099 12:38:36.406158 CA_UI_PI_RATIO = 32
6100 12:38:36.409988 ===================================
6101 12:38:36.413253 ===================================
6102 12:38:36.416171 memory_type:LPDDR4
6103 12:38:36.416252 GP_NUM : 10
6104 12:38:36.419863 SRAM_EN : 1
6105 12:38:36.419943 MD32_EN : 0
6106 12:38:36.422778 ===================================
6107 12:38:36.426453 [ANA_INIT] >>>>>>>>>>>>>>
6108 12:38:36.429631 <<<<<< [CONFIGURE PHASE]: ANA_TX
6109 12:38:36.433301 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6110 12:38:36.436027 ===================================
6111 12:38:36.439879 data_rate = 800,PCW = 0X7400
6112 12:38:36.443265 ===================================
6113 12:38:36.446120 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6114 12:38:36.449276 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6115 12:38:36.462686 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6116 12:38:36.466306 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6117 12:38:36.469408 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6118 12:38:36.472962 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6119 12:38:36.476352 [ANA_INIT] flow start
6120 12:38:36.479512 [ANA_INIT] PLL >>>>>>>>
6121 12:38:36.479596 [ANA_INIT] PLL <<<<<<<<
6122 12:38:36.482795 [ANA_INIT] MIDPI >>>>>>>>
6123 12:38:36.486056 [ANA_INIT] MIDPI <<<<<<<<
6124 12:38:36.486136 [ANA_INIT] DLL >>>>>>>>
6125 12:38:36.489637 [ANA_INIT] flow end
6126 12:38:36.492667 ============ LP4 DIFF to SE enter ============
6127 12:38:36.496555 ============ LP4 DIFF to SE exit ============
6128 12:38:36.499853 [ANA_INIT] <<<<<<<<<<<<<
6129 12:38:36.503099 [Flow] Enable top DCM control >>>>>
6130 12:38:36.506319 [Flow] Enable top DCM control <<<<<
6131 12:38:36.510021 Enable DLL master slave shuffle
6132 12:38:36.516288 ==============================================================
6133 12:38:36.516368 Gating Mode config
6134 12:38:36.523152 ==============================================================
6135 12:38:36.523232 Config description:
6136 12:38:36.533351 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6137 12:38:36.539885 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6138 12:38:36.546350 SELPH_MODE 0: By rank 1: By Phase
6139 12:38:36.549875 ==============================================================
6140 12:38:36.554032 GAT_TRACK_EN = 0
6141 12:38:36.556739 RX_GATING_MODE = 2
6142 12:38:36.559784 RX_GATING_TRACK_MODE = 2
6143 12:38:36.563464 SELPH_MODE = 1
6144 12:38:36.566707 PICG_EARLY_EN = 1
6145 12:38:36.569962 VALID_LAT_VALUE = 1
6146 12:38:36.575358 ==============================================================
6147 12:38:36.577203 Enter into Gating configuration >>>>
6148 12:38:36.579841 Exit from Gating configuration <<<<
6149 12:38:36.583571 Enter into DVFS_PRE_config >>>>>
6150 12:38:36.596853 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6151 12:38:36.599958 Exit from DVFS_PRE_config <<<<<
6152 12:38:36.603366 Enter into PICG configuration >>>>
6153 12:38:36.603446 Exit from PICG configuration <<<<
6154 12:38:36.606283 [RX_INPUT] configuration >>>>>
6155 12:38:36.610325 [RX_INPUT] configuration <<<<<
6156 12:38:36.616657 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6157 12:38:36.619797 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6158 12:38:36.626761 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6159 12:38:36.633064 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6160 12:38:36.640044 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6161 12:38:36.646798 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6162 12:38:36.649966 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6163 12:38:36.653587 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6164 12:38:36.656431 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6165 12:38:36.663606 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6166 12:38:36.666493 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6167 12:38:36.670012 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6168 12:38:36.673220 ===================================
6169 12:38:36.676963 LPDDR4 DRAM CONFIGURATION
6170 12:38:36.680274 ===================================
6171 12:38:36.680357 EX_ROW_EN[0] = 0x0
6172 12:38:36.683641 EX_ROW_EN[1] = 0x0
6173 12:38:36.686678 LP4Y_EN = 0x0
6174 12:38:36.686759 WORK_FSP = 0x0
6175 12:38:36.689799 WL = 0x2
6176 12:38:36.689881 RL = 0x2
6177 12:38:36.693332 BL = 0x2
6178 12:38:36.693414 RPST = 0x0
6179 12:38:36.696361 RD_PRE = 0x0
6180 12:38:36.696443 WR_PRE = 0x1
6181 12:38:36.700301 WR_PST = 0x0
6182 12:38:36.700384 DBI_WR = 0x0
6183 12:38:36.703052 DBI_RD = 0x0
6184 12:38:36.703134 OTF = 0x1
6185 12:38:36.706281 ===================================
6186 12:38:36.709997 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6187 12:38:36.716672 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6188 12:38:36.720342 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6189 12:38:36.723127 ===================================
6190 12:38:36.726539 LPDDR4 DRAM CONFIGURATION
6191 12:38:36.729902 ===================================
6192 12:38:36.729985 EX_ROW_EN[0] = 0x10
6193 12:38:36.733197 EX_ROW_EN[1] = 0x0
6194 12:38:36.733278 LP4Y_EN = 0x0
6195 12:38:36.736816 WORK_FSP = 0x0
6196 12:38:36.736897 WL = 0x2
6197 12:38:36.739860 RL = 0x2
6198 12:38:36.739942 BL = 0x2
6199 12:38:36.743499 RPST = 0x0
6200 12:38:36.746591 RD_PRE = 0x0
6201 12:38:36.746674 WR_PRE = 0x1
6202 12:38:36.750387 WR_PST = 0x0
6203 12:38:36.750507 DBI_WR = 0x0
6204 12:38:36.753485 DBI_RD = 0x0
6205 12:38:36.753567 OTF = 0x1
6206 12:38:36.756431 ===================================
6207 12:38:36.763188 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6208 12:38:36.766918 nWR fixed to 30
6209 12:38:36.770291 [ModeRegInit_LP4] CH0 RK0
6210 12:38:36.770422 [ModeRegInit_LP4] CH0 RK1
6211 12:38:36.773430 [ModeRegInit_LP4] CH1 RK0
6212 12:38:36.777160 [ModeRegInit_LP4] CH1 RK1
6213 12:38:36.777243 match AC timing 19
6214 12:38:36.783848 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6215 12:38:36.786745 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6216 12:38:36.790259 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6217 12:38:36.797080 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6218 12:38:36.800565 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6219 12:38:36.800648 ==
6220 12:38:36.803771 Dram Type= 6, Freq= 0, CH_0, rank 0
6221 12:38:36.806933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6222 12:38:36.807016 ==
6223 12:38:36.813543 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6224 12:38:36.820187 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6225 12:38:36.824680 [CA 0] Center 36 (8~64) winsize 57
6226 12:38:36.827369 [CA 1] Center 36 (8~64) winsize 57
6227 12:38:36.827452 [CA 2] Center 36 (8~64) winsize 57
6228 12:38:36.830123 [CA 3] Center 36 (8~64) winsize 57
6229 12:38:36.833469 [CA 4] Center 36 (8~64) winsize 57
6230 12:38:36.837165 [CA 5] Center 36 (8~64) winsize 57
6231 12:38:36.837246
6232 12:38:36.840864 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6233 12:38:36.840965
6234 12:38:36.846975 [CATrainingPosCal] consider 1 rank data
6235 12:38:36.847055 u2DelayCellTimex100 = 270/100 ps
6236 12:38:36.853826 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 12:38:36.856609 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 12:38:36.860427 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 12:38:36.863289 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 12:38:36.866647 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 12:38:36.870213 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 12:38:36.870293
6243 12:38:36.873437 CA PerBit enable=1, Macro0, CA PI delay=36
6244 12:38:36.873516
6245 12:38:36.877116 [CBTSetCACLKResult] CA Dly = 36
6246 12:38:36.880555 CS Dly: 1 (0~32)
6247 12:38:36.880635 ==
6248 12:38:36.884259 Dram Type= 6, Freq= 0, CH_0, rank 1
6249 12:38:36.886855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6250 12:38:36.886936 ==
6251 12:38:36.893664 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6252 12:38:36.897052 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6253 12:38:36.900163 [CA 0] Center 36 (8~64) winsize 57
6254 12:38:36.903221 [CA 1] Center 36 (8~64) winsize 57
6255 12:38:36.906969 [CA 2] Center 36 (8~64) winsize 57
6256 12:38:36.910214 [CA 3] Center 36 (8~64) winsize 57
6257 12:38:36.913523 [CA 4] Center 36 (8~64) winsize 57
6258 12:38:36.916645 [CA 5] Center 36 (8~64) winsize 57
6259 12:38:36.916726
6260 12:38:36.920615 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6261 12:38:36.920696
6262 12:38:36.923658 [CATrainingPosCal] consider 2 rank data
6263 12:38:36.927205 u2DelayCellTimex100 = 270/100 ps
6264 12:38:36.930259 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 12:38:36.933784 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 12:38:36.937016 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 12:38:36.939908 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 12:38:36.946840 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 12:38:36.950372 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 12:38:36.950477
6271 12:38:36.953457 CA PerBit enable=1, Macro0, CA PI delay=36
6272 12:38:36.953541
6273 12:38:36.957097 [CBTSetCACLKResult] CA Dly = 36
6274 12:38:36.957177 CS Dly: 1 (0~32)
6275 12:38:36.957241
6276 12:38:36.959847 ----->DramcWriteLeveling(PI) begin...
6277 12:38:36.959929 ==
6278 12:38:36.963313 Dram Type= 6, Freq= 0, CH_0, rank 0
6279 12:38:36.970007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6280 12:38:36.970087 ==
6281 12:38:36.973932 Write leveling (Byte 0): 40 => 8
6282 12:38:36.974012 Write leveling (Byte 1): 32 => 0
6283 12:38:36.977330 DramcWriteLeveling(PI) end<-----
6284 12:38:36.977410
6285 12:38:36.977475 ==
6286 12:38:36.980036 Dram Type= 6, Freq= 0, CH_0, rank 0
6287 12:38:36.986584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6288 12:38:36.986664 ==
6289 12:38:36.990381 [Gating] SW mode calibration
6290 12:38:36.996915 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6291 12:38:36.999901 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6292 12:38:37.006686 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6293 12:38:37.009913 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6294 12:38:37.013152 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6295 12:38:37.019900 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6296 12:38:37.023364 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6297 12:38:37.027073 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6298 12:38:37.030277 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6299 12:38:37.036599 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6300 12:38:37.040389 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6301 12:38:37.043147 Total UI for P1: 0, mck2ui 16
6302 12:38:37.046344 best dqsien dly found for B0: ( 0, 14, 24)
6303 12:38:37.050090 Total UI for P1: 0, mck2ui 16
6304 12:38:37.053173 best dqsien dly found for B1: ( 0, 14, 24)
6305 12:38:37.056700 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6306 12:38:37.059693 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6307 12:38:37.059774
6308 12:38:37.063459 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6309 12:38:37.069660 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6310 12:38:37.069740 [Gating] SW calibration Done
6311 12:38:37.069805 ==
6312 12:38:37.073370 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 12:38:37.079842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 12:38:37.079923 ==
6315 12:38:37.079987 RX Vref Scan: 0
6316 12:38:37.080046
6317 12:38:37.083516 RX Vref 0 -> 0, step: 1
6318 12:38:37.083596
6319 12:38:37.086621 RX Delay -410 -> 252, step: 16
6320 12:38:37.090263 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6321 12:38:37.093585 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6322 12:38:37.096423 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6323 12:38:37.103603 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6324 12:38:37.106774 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6325 12:38:37.110231 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6326 12:38:37.113546 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6327 12:38:37.120075 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6328 12:38:37.123137 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6329 12:38:37.127127 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6330 12:38:37.130285 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6331 12:38:37.136708 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6332 12:38:37.140663 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6333 12:38:37.143595 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6334 12:38:37.147259 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6335 12:38:37.153086 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6336 12:38:37.153167 ==
6337 12:38:37.156578 Dram Type= 6, Freq= 0, CH_0, rank 0
6338 12:38:37.160224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 12:38:37.160306 ==
6340 12:38:37.160369 DQS Delay:
6341 12:38:37.163192 DQS0 = 35, DQS1 = 51
6342 12:38:37.163273 DQM Delay:
6343 12:38:37.167088 DQM0 = 7, DQM1 = 10
6344 12:38:37.167168 DQ Delay:
6345 12:38:37.170071 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6346 12:38:37.173667 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6347 12:38:37.176529 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6348 12:38:37.179893 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6349 12:38:37.179974
6350 12:38:37.180037
6351 12:38:37.180096 ==
6352 12:38:37.183623 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 12:38:37.186984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 12:38:37.187064 ==
6355 12:38:37.187129
6356 12:38:37.187187
6357 12:38:37.190318 TX Vref Scan disable
6358 12:38:37.190419 == TX Byte 0 ==
6359 12:38:37.196806 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6360 12:38:37.200580 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6361 12:38:37.200657 == TX Byte 1 ==
6362 12:38:37.206982 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6363 12:38:37.210432 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6364 12:38:37.210505 ==
6365 12:38:37.213590 Dram Type= 6, Freq= 0, CH_0, rank 0
6366 12:38:37.216711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6367 12:38:37.216791 ==
6368 12:38:37.216854
6369 12:38:37.216913
6370 12:38:37.220407 TX Vref Scan disable
6371 12:38:37.223570 == TX Byte 0 ==
6372 12:38:37.226718 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6373 12:38:37.230553 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6374 12:38:37.233509 == TX Byte 1 ==
6375 12:38:37.236503 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6376 12:38:37.239895 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6377 12:38:37.239975
6378 12:38:37.240038 [DATLAT]
6379 12:38:37.243715 Freq=400, CH0 RK0
6380 12:38:37.243795
6381 12:38:37.243857 DATLAT Default: 0xf
6382 12:38:37.246975 0, 0xFFFF, sum = 0
6383 12:38:37.247059 1, 0xFFFF, sum = 0
6384 12:38:37.249878 2, 0xFFFF, sum = 0
6385 12:38:37.253943 3, 0xFFFF, sum = 0
6386 12:38:37.254026 4, 0xFFFF, sum = 0
6387 12:38:37.256723 5, 0xFFFF, sum = 0
6388 12:38:37.256802 6, 0xFFFF, sum = 0
6389 12:38:37.260290 7, 0xFFFF, sum = 0
6390 12:38:37.260374 8, 0xFFFF, sum = 0
6391 12:38:37.263523 9, 0xFFFF, sum = 0
6392 12:38:37.263607 10, 0xFFFF, sum = 0
6393 12:38:37.266864 11, 0xFFFF, sum = 0
6394 12:38:37.266945 12, 0xFFFF, sum = 0
6395 12:38:37.270056 13, 0x0, sum = 1
6396 12:38:37.270138 14, 0x0, sum = 2
6397 12:38:37.273308 15, 0x0, sum = 3
6398 12:38:37.273389 16, 0x0, sum = 4
6399 12:38:37.276903 best_step = 14
6400 12:38:37.276983
6401 12:38:37.277046 ==
6402 12:38:37.279998 Dram Type= 6, Freq= 0, CH_0, rank 0
6403 12:38:37.283371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 12:38:37.283452 ==
6405 12:38:37.283515 RX Vref Scan: 1
6406 12:38:37.283573
6407 12:38:37.286838 RX Vref 0 -> 0, step: 1
6408 12:38:37.286918
6409 12:38:37.290410 RX Delay -343 -> 252, step: 8
6410 12:38:37.290506
6411 12:38:37.293525 Set Vref, RX VrefLevel [Byte0]: 53
6412 12:38:37.296725 [Byte1]: 52
6413 12:38:37.300673
6414 12:38:37.300752 Final RX Vref Byte 0 = 53 to rank0
6415 12:38:37.304334 Final RX Vref Byte 1 = 52 to rank0
6416 12:38:37.307230 Final RX Vref Byte 0 = 53 to rank1
6417 12:38:37.310652 Final RX Vref Byte 1 = 52 to rank1==
6418 12:38:37.314252 Dram Type= 6, Freq= 0, CH_0, rank 0
6419 12:38:37.320630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 12:38:37.320710 ==
6421 12:38:37.320773 DQS Delay:
6422 12:38:37.320832 DQS0 = 44, DQS1 = 60
6423 12:38:37.324288 DQM Delay:
6424 12:38:37.324367 DQM0 = 11, DQM1 = 16
6425 12:38:37.327493 DQ Delay:
6426 12:38:37.331103 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =12
6427 12:38:37.331182 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6428 12:38:37.334351 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =12
6429 12:38:37.337047 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6430 12:38:37.340840
6431 12:38:37.340920
6432 12:38:37.347604 [DQSOSCAuto] RK0, (LSB)MR18= 0x8655, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 393 ps
6433 12:38:37.350357 CH0 RK0: MR19=C0C, MR18=8655
6434 12:38:37.357393 CH0_RK0: MR19=0xC0C, MR18=0x8655, DQSOSC=393, MR23=63, INC=382, DEC=254
6435 12:38:37.357474 ==
6436 12:38:37.360968 Dram Type= 6, Freq= 0, CH_0, rank 1
6437 12:38:37.364689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6438 12:38:37.364769 ==
6439 12:38:37.367057 [Gating] SW mode calibration
6440 12:38:37.374107 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6441 12:38:37.380550 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6442 12:38:37.384077 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6443 12:38:37.387040 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6444 12:38:37.394067 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6445 12:38:37.397250 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6446 12:38:37.400149 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6447 12:38:37.406834 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6448 12:38:37.410629 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6449 12:38:37.413520 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6450 12:38:37.417118 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6451 12:38:37.420212 Total UI for P1: 0, mck2ui 16
6452 12:38:37.423455 best dqsien dly found for B0: ( 0, 14, 24)
6453 12:38:37.426914 Total UI for P1: 0, mck2ui 16
6454 12:38:37.430728 best dqsien dly found for B1: ( 0, 14, 24)
6455 12:38:37.433940 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6456 12:38:37.440558 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6457 12:38:37.440637
6458 12:38:37.443630 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6459 12:38:37.446781 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6460 12:38:37.450600 [Gating] SW calibration Done
6461 12:38:37.450680 ==
6462 12:38:37.453537 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 12:38:37.457047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 12:38:37.457127 ==
6465 12:38:37.457190 RX Vref Scan: 0
6466 12:38:37.460623
6467 12:38:37.460703 RX Vref 0 -> 0, step: 1
6468 12:38:37.460766
6469 12:38:37.463669 RX Delay -410 -> 252, step: 16
6470 12:38:37.467064 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6471 12:38:37.473664 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6472 12:38:37.477419 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6473 12:38:37.480424 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6474 12:38:37.483779 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6475 12:38:37.490248 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6476 12:38:37.493957 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6477 12:38:37.496977 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6478 12:38:37.500254 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6479 12:38:37.507819 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6480 12:38:37.510120 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6481 12:38:37.513774 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6482 12:38:37.517453 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6483 12:38:37.523714 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6484 12:38:37.527006 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6485 12:38:37.530107 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6486 12:38:37.530186 ==
6487 12:38:37.533907 Dram Type= 6, Freq= 0, CH_0, rank 1
6488 12:38:37.536795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6489 12:38:37.540378 ==
6490 12:38:37.540459 DQS Delay:
6491 12:38:37.540524 DQS0 = 43, DQS1 = 51
6492 12:38:37.543711 DQM Delay:
6493 12:38:37.543791 DQM0 = 11, DQM1 = 10
6494 12:38:37.546806 DQ Delay:
6495 12:38:37.546886 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6496 12:38:37.550668 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6497 12:38:37.553860 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6498 12:38:37.557208 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6499 12:38:37.557288
6500 12:38:37.557351
6501 12:38:37.557410 ==
6502 12:38:37.560275 Dram Type= 6, Freq= 0, CH_0, rank 1
6503 12:38:37.567187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 12:38:37.567268 ==
6505 12:38:37.567331
6506 12:38:37.567391
6507 12:38:37.567448 TX Vref Scan disable
6508 12:38:37.570961 == TX Byte 0 ==
6509 12:38:37.573878 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6510 12:38:37.577234 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6511 12:38:37.580672 == TX Byte 1 ==
6512 12:38:37.583561 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6513 12:38:37.587129 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6514 12:38:37.587210 ==
6515 12:38:37.590270 Dram Type= 6, Freq= 0, CH_0, rank 1
6516 12:38:37.596973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6517 12:38:37.597054 ==
6518 12:38:37.597118
6519 12:38:37.597178
6520 12:38:37.597233 TX Vref Scan disable
6521 12:38:37.600197 == TX Byte 0 ==
6522 12:38:37.603703 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6523 12:38:37.607297 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6524 12:38:37.610325 == TX Byte 1 ==
6525 12:38:37.613932 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6526 12:38:37.617080 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6527 12:38:37.617161
6528 12:38:37.620171 [DATLAT]
6529 12:38:37.620252 Freq=400, CH0 RK1
6530 12:38:37.620315
6531 12:38:37.624077 DATLAT Default: 0xe
6532 12:38:37.624158 0, 0xFFFF, sum = 0
6533 12:38:37.626873 1, 0xFFFF, sum = 0
6534 12:38:37.626955 2, 0xFFFF, sum = 0
6535 12:38:37.630019 3, 0xFFFF, sum = 0
6536 12:38:37.630127 4, 0xFFFF, sum = 0
6537 12:38:37.633876 5, 0xFFFF, sum = 0
6538 12:38:37.633958 6, 0xFFFF, sum = 0
6539 12:38:37.637409 7, 0xFFFF, sum = 0
6540 12:38:37.637496 8, 0xFFFF, sum = 0
6541 12:38:37.640316 9, 0xFFFF, sum = 0
6542 12:38:37.640418 10, 0xFFFF, sum = 0
6543 12:38:37.643717 11, 0xFFFF, sum = 0
6544 12:38:37.647078 12, 0xFFFF, sum = 0
6545 12:38:37.647159 13, 0x0, sum = 1
6546 12:38:37.647241 14, 0x0, sum = 2
6547 12:38:37.650097 15, 0x0, sum = 3
6548 12:38:37.650178 16, 0x0, sum = 4
6549 12:38:37.653702 best_step = 14
6550 12:38:37.653782
6551 12:38:37.653846 ==
6552 12:38:37.656764 Dram Type= 6, Freq= 0, CH_0, rank 1
6553 12:38:37.660429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6554 12:38:37.660509 ==
6555 12:38:37.663498 RX Vref Scan: 0
6556 12:38:37.663579
6557 12:38:37.663642 RX Vref 0 -> 0, step: 1
6558 12:38:37.663702
6559 12:38:37.667061 RX Delay -343 -> 252, step: 8
6560 12:38:37.674919 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6561 12:38:37.678537 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6562 12:38:37.681969 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6563 12:38:37.685341 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6564 12:38:37.692056 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6565 12:38:37.695320 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6566 12:38:37.698168 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6567 12:38:37.701779 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6568 12:38:37.708521 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6569 12:38:37.711511 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6570 12:38:37.715207 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6571 12:38:37.718340 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6572 12:38:37.725115 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6573 12:38:37.728126 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6574 12:38:37.731898 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6575 12:38:37.738221 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6576 12:38:37.738302 ==
6577 12:38:37.741396 Dram Type= 6, Freq= 0, CH_0, rank 1
6578 12:38:37.745146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6579 12:38:37.745227 ==
6580 12:38:37.745291 DQS Delay:
6581 12:38:37.748029 DQS0 = 48, DQS1 = 60
6582 12:38:37.748109 DQM Delay:
6583 12:38:37.752022 DQM0 = 13, DQM1 = 13
6584 12:38:37.752102 DQ Delay:
6585 12:38:37.754876 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6586 12:38:37.758342 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6587 12:38:37.761506 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6588 12:38:37.764691 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6589 12:38:37.764772
6590 12:38:37.764835
6591 12:38:37.772055 [DQSOSCAuto] RK1, (LSB)MR18= 0x9164, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 391 ps
6592 12:38:37.774904 CH0 RK1: MR19=C0C, MR18=9164
6593 12:38:37.781502 CH0_RK1: MR19=0xC0C, MR18=0x9164, DQSOSC=391, MR23=63, INC=386, DEC=257
6594 12:38:37.784990 [RxdqsGatingPostProcess] freq 400
6595 12:38:37.791561 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6596 12:38:37.791642 best DQS0 dly(2T, 0.5T) = (0, 10)
6597 12:38:37.794583 best DQS1 dly(2T, 0.5T) = (0, 10)
6598 12:38:37.797965 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6599 12:38:37.801475 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6600 12:38:37.804775 best DQS0 dly(2T, 0.5T) = (0, 10)
6601 12:38:37.807981 best DQS1 dly(2T, 0.5T) = (0, 10)
6602 12:38:37.811623 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6603 12:38:37.814695 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6604 12:38:37.818575 Pre-setting of DQS Precalculation
6605 12:38:37.821628 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6606 12:38:37.825090 ==
6607 12:38:37.828593 Dram Type= 6, Freq= 0, CH_1, rank 0
6608 12:38:37.831390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6609 12:38:37.831471 ==
6610 12:38:37.835335 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6611 12:38:37.841523 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6612 12:38:37.844777 [CA 0] Center 36 (8~64) winsize 57
6613 12:38:37.848222 [CA 1] Center 36 (8~64) winsize 57
6614 12:38:37.851450 [CA 2] Center 36 (8~64) winsize 57
6615 12:38:37.855053 [CA 3] Center 36 (8~64) winsize 57
6616 12:38:37.858107 [CA 4] Center 36 (8~64) winsize 57
6617 12:38:37.861795 [CA 5] Center 36 (8~64) winsize 57
6618 12:38:37.861876
6619 12:38:37.865266 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6620 12:38:37.865346
6621 12:38:37.868108 [CATrainingPosCal] consider 1 rank data
6622 12:38:37.871702 u2DelayCellTimex100 = 270/100 ps
6623 12:38:37.874892 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 12:38:37.878183 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 12:38:37.881312 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 12:38:37.884904 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 12:38:37.887910 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 12:38:37.894775 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 12:38:37.894872
6630 12:38:37.897952 CA PerBit enable=1, Macro0, CA PI delay=36
6631 12:38:37.898032
6632 12:38:37.901650 [CBTSetCACLKResult] CA Dly = 36
6633 12:38:37.901730 CS Dly: 1 (0~32)
6634 12:38:37.901794 ==
6635 12:38:37.904631 Dram Type= 6, Freq= 0, CH_1, rank 1
6636 12:38:37.908409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6637 12:38:37.911758 ==
6638 12:38:37.914620 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6639 12:38:37.921581 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6640 12:38:37.924711 [CA 0] Center 36 (8~64) winsize 57
6641 12:38:37.928301 [CA 1] Center 36 (8~64) winsize 57
6642 12:38:37.931365 [CA 2] Center 36 (8~64) winsize 57
6643 12:38:37.934968 [CA 3] Center 36 (8~64) winsize 57
6644 12:38:37.938257 [CA 4] Center 36 (8~64) winsize 57
6645 12:38:37.938337 [CA 5] Center 36 (8~64) winsize 57
6646 12:38:37.941339
6647 12:38:37.944943 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6648 12:38:37.945023
6649 12:38:37.947978 [CATrainingPosCal] consider 2 rank data
6650 12:38:37.951716 u2DelayCellTimex100 = 270/100 ps
6651 12:38:37.954814 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 12:38:37.958471 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 12:38:37.961591 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 12:38:37.964882 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 12:38:37.968480 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 12:38:37.971517 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 12:38:37.971598
6658 12:38:37.975110 CA PerBit enable=1, Macro0, CA PI delay=36
6659 12:38:37.975190
6660 12:38:37.978172 [CBTSetCACLKResult] CA Dly = 36
6661 12:38:37.981640 CS Dly: 1 (0~32)
6662 12:38:37.981747
6663 12:38:37.985308 ----->DramcWriteLeveling(PI) begin...
6664 12:38:37.985390 ==
6665 12:38:37.988067 Dram Type= 6, Freq= 0, CH_1, rank 0
6666 12:38:37.991788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 12:38:37.991874 ==
6668 12:38:37.994891 Write leveling (Byte 0): 40 => 8
6669 12:38:37.998623 Write leveling (Byte 1): 40 => 8
6670 12:38:38.001275 DramcWriteLeveling(PI) end<-----
6671 12:38:38.001358
6672 12:38:38.001441 ==
6673 12:38:38.004816 Dram Type= 6, Freq= 0, CH_1, rank 0
6674 12:38:38.008011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 12:38:38.008093 ==
6676 12:38:38.011654 [Gating] SW mode calibration
6677 12:38:38.017979 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6678 12:38:38.024668 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6679 12:38:38.027876 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6680 12:38:38.032006 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6681 12:38:38.038115 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6682 12:38:38.041692 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6683 12:38:38.044972 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6684 12:38:38.051320 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6685 12:38:38.054942 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6686 12:38:38.058594 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6687 12:38:38.064944 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6688 12:38:38.065026 Total UI for P1: 0, mck2ui 16
6689 12:38:38.071796 best dqsien dly found for B0: ( 0, 14, 24)
6690 12:38:38.071878 Total UI for P1: 0, mck2ui 16
6691 12:38:38.074962 best dqsien dly found for B1: ( 0, 14, 24)
6692 12:38:38.082149 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6693 12:38:38.084824 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6694 12:38:38.084906
6695 12:38:38.088610 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6696 12:38:38.091868 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6697 12:38:38.095336 [Gating] SW calibration Done
6698 12:38:38.095418 ==
6699 12:38:38.098552 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 12:38:38.101580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 12:38:38.101663 ==
6702 12:38:38.105135 RX Vref Scan: 0
6703 12:38:38.105216
6704 12:38:38.105299 RX Vref 0 -> 0, step: 1
6705 12:38:38.105378
6706 12:38:38.108745 RX Delay -410 -> 252, step: 16
6707 12:38:38.111798 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6708 12:38:38.118152 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6709 12:38:38.122109 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6710 12:38:38.125034 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6711 12:38:38.128884 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6712 12:38:38.135339 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6713 12:38:38.138861 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6714 12:38:38.141922 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6715 12:38:38.145577 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6716 12:38:38.152169 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6717 12:38:38.155226 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6718 12:38:38.158327 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6719 12:38:38.161611 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6720 12:38:38.168508 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6721 12:38:38.172329 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6722 12:38:38.175105 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6723 12:38:38.175188 ==
6724 12:38:38.179016 Dram Type= 6, Freq= 0, CH_1, rank 0
6725 12:38:38.182024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 12:38:38.185531 ==
6727 12:38:38.185613 DQS Delay:
6728 12:38:38.185696 DQS0 = 51, DQS1 = 59
6729 12:38:38.188935 DQM Delay:
6730 12:38:38.189017 DQM0 = 19, DQM1 = 16
6731 12:38:38.191936 DQ Delay:
6732 12:38:38.192018 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6733 12:38:38.194996 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6734 12:38:38.198659 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6735 12:38:38.202622 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6736 12:38:38.202704
6737 12:38:38.202788
6738 12:38:38.205186 ==
6739 12:38:38.208548 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 12:38:38.212521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 12:38:38.212605 ==
6742 12:38:38.212689
6743 12:38:38.212785
6744 12:38:38.215308 TX Vref Scan disable
6745 12:38:38.215440 == TX Byte 0 ==
6746 12:38:38.218625 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6747 12:38:38.225130 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6748 12:38:38.225237 == TX Byte 1 ==
6749 12:38:38.228496 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6750 12:38:38.232318 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6751 12:38:38.235248 ==
6752 12:38:38.238621 Dram Type= 6, Freq= 0, CH_1, rank 0
6753 12:38:38.242140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6754 12:38:38.242267 ==
6755 12:38:38.242361
6756 12:38:38.242444
6757 12:38:38.245185 TX Vref Scan disable
6758 12:38:38.245291 == TX Byte 0 ==
6759 12:38:38.248482 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6760 12:38:38.255441 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6761 12:38:38.255524 == TX Byte 1 ==
6762 12:38:38.258438 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6763 12:38:38.261914 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6764 12:38:38.265383
6765 12:38:38.265462 [DATLAT]
6766 12:38:38.265526 Freq=400, CH1 RK0
6767 12:38:38.265585
6768 12:38:38.268588 DATLAT Default: 0xf
6769 12:38:38.268668 0, 0xFFFF, sum = 0
6770 12:38:38.271929 1, 0xFFFF, sum = 0
6771 12:38:38.272010 2, 0xFFFF, sum = 0
6772 12:38:38.275243 3, 0xFFFF, sum = 0
6773 12:38:38.275324 4, 0xFFFF, sum = 0
6774 12:38:38.278790 5, 0xFFFF, sum = 0
6775 12:38:38.282010 6, 0xFFFF, sum = 0
6776 12:38:38.282092 7, 0xFFFF, sum = 0
6777 12:38:38.285201 8, 0xFFFF, sum = 0
6778 12:38:38.285283 9, 0xFFFF, sum = 0
6779 12:38:38.288505 10, 0xFFFF, sum = 0
6780 12:38:38.288586 11, 0xFFFF, sum = 0
6781 12:38:38.291869 12, 0xFFFF, sum = 0
6782 12:38:38.291952 13, 0x0, sum = 1
6783 12:38:38.295252 14, 0x0, sum = 2
6784 12:38:38.295333 15, 0x0, sum = 3
6785 12:38:38.298819 16, 0x0, sum = 4
6786 12:38:38.298900 best_step = 14
6787 12:38:38.298964
6788 12:38:38.299022 ==
6789 12:38:38.301831 Dram Type= 6, Freq= 0, CH_1, rank 0
6790 12:38:38.304958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 12:38:38.305039 ==
6792 12:38:38.308664 RX Vref Scan: 1
6793 12:38:38.308744
6794 12:38:38.312175 RX Vref 0 -> 0, step: 1
6795 12:38:38.312255
6796 12:38:38.312319 RX Delay -359 -> 252, step: 8
6797 12:38:38.312379
6798 12:38:38.315112 Set Vref, RX VrefLevel [Byte0]: 56
6799 12:38:38.318837 [Byte1]: 51
6800 12:38:38.324713
6801 12:38:38.324793 Final RX Vref Byte 0 = 56 to rank0
6802 12:38:38.327328 Final RX Vref Byte 1 = 51 to rank0
6803 12:38:38.330597 Final RX Vref Byte 0 = 56 to rank1
6804 12:38:38.334495 Final RX Vref Byte 1 = 51 to rank1==
6805 12:38:38.337572 Dram Type= 6, Freq= 0, CH_1, rank 0
6806 12:38:38.344288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 12:38:38.344369 ==
6808 12:38:38.344434 DQS Delay:
6809 12:38:38.344493 DQS0 = 48, DQS1 = 60
6810 12:38:38.347334 DQM Delay:
6811 12:38:38.347414 DQM0 = 13, DQM1 = 13
6812 12:38:38.350512 DQ Delay:
6813 12:38:38.354281 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6814 12:38:38.354362 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6815 12:38:38.357549 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6816 12:38:38.361115 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6817 12:38:38.361196
6818 12:38:38.361259
6819 12:38:38.370550 [DQSOSCAuto] RK0, (LSB)MR18= 0x8229, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
6820 12:38:38.374058 CH1 RK0: MR19=C0C, MR18=8229
6821 12:38:38.380562 CH1_RK0: MR19=0xC0C, MR18=0x8229, DQSOSC=393, MR23=63, INC=382, DEC=254
6822 12:38:38.380644 ==
6823 12:38:38.384230 Dram Type= 6, Freq= 0, CH_1, rank 1
6824 12:38:38.387829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6825 12:38:38.387910 ==
6826 12:38:38.391074 [Gating] SW mode calibration
6827 12:38:38.398064 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6828 12:38:38.400853 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6829 12:38:38.407394 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6830 12:38:38.411291 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6831 12:38:38.414077 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6832 12:38:38.420642 0 12 16 | B1->B0 | 4645 4646 | 1 0 | (0 0) (0 0)
6833 12:38:38.424258 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6834 12:38:38.427398 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6835 12:38:38.434078 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6836 12:38:38.437181 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6837 12:38:38.441135 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6838 12:38:38.444549 Total UI for P1: 0, mck2ui 16
6839 12:38:38.448105 best dqsien dly found for B0: ( 0, 14, 24)
6840 12:38:38.450667 Total UI for P1: 0, mck2ui 16
6841 12:38:38.454238 best dqsien dly found for B1: ( 0, 14, 24)
6842 12:38:38.457734 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6843 12:38:38.460598 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6844 12:38:38.460678
6845 12:38:38.467521 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6846 12:38:38.471198 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6847 12:38:38.471278 [Gating] SW calibration Done
6848 12:38:38.473918 ==
6849 12:38:38.477254 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 12:38:38.481120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 12:38:38.481229 ==
6852 12:38:38.481322 RX Vref Scan: 0
6853 12:38:38.481390
6854 12:38:38.484158 RX Vref 0 -> 0, step: 1
6855 12:38:38.484238
6856 12:38:38.487341 RX Delay -410 -> 252, step: 16
6857 12:38:38.490880 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6858 12:38:38.494345 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6859 12:38:38.500559 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6860 12:38:38.504186 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6861 12:38:38.507288 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6862 12:38:38.510936 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6863 12:38:38.517681 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6864 12:38:38.520524 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6865 12:38:38.524147 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6866 12:38:38.527257 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6867 12:38:38.533832 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6868 12:38:38.537591 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6869 12:38:38.540676 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6870 12:38:38.544401 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6871 12:38:38.550607 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6872 12:38:38.553972 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6873 12:38:38.554052 ==
6874 12:38:38.557486 Dram Type= 6, Freq= 0, CH_1, rank 1
6875 12:38:38.561103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6876 12:38:38.561183 ==
6877 12:38:38.563918 DQS Delay:
6878 12:38:38.563997 DQS0 = 43, DQS1 = 59
6879 12:38:38.567168 DQM Delay:
6880 12:38:38.567248 DQM0 = 9, DQM1 = 18
6881 12:38:38.567312 DQ Delay:
6882 12:38:38.570523 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6883 12:38:38.574225 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6884 12:38:38.577866 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6885 12:38:38.580540 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =32
6886 12:38:38.580620
6887 12:38:38.580684
6888 12:38:38.580742 ==
6889 12:38:38.583826 Dram Type= 6, Freq= 0, CH_1, rank 1
6890 12:38:38.587299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 12:38:38.590953 ==
6892 12:38:38.591063
6893 12:38:38.591152
6894 12:38:38.591231 TX Vref Scan disable
6895 12:38:38.593895 == TX Byte 0 ==
6896 12:38:38.597254 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6897 12:38:38.600657 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6898 12:38:38.604205 == TX Byte 1 ==
6899 12:38:38.607656 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6900 12:38:38.611012 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6901 12:38:38.611118 ==
6902 12:38:38.614209 Dram Type= 6, Freq= 0, CH_1, rank 1
6903 12:38:38.617854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6904 12:38:38.617935 ==
6905 12:38:38.620868
6906 12:38:38.620948
6907 12:38:38.621010 TX Vref Scan disable
6908 12:38:38.624130 == TX Byte 0 ==
6909 12:38:38.627463 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6910 12:38:38.630974 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6911 12:38:38.634622 == TX Byte 1 ==
6912 12:38:38.637429 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6913 12:38:38.641101 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6914 12:38:38.641183
6915 12:38:38.641254 [DATLAT]
6916 12:38:38.644205 Freq=400, CH1 RK1
6917 12:38:38.644286
6918 12:38:38.644349 DATLAT Default: 0xe
6919 12:38:38.647390 0, 0xFFFF, sum = 0
6920 12:38:38.651117 1, 0xFFFF, sum = 0
6921 12:38:38.651199 2, 0xFFFF, sum = 0
6922 12:38:38.654129 3, 0xFFFF, sum = 0
6923 12:38:38.654211 4, 0xFFFF, sum = 0
6924 12:38:38.657255 5, 0xFFFF, sum = 0
6925 12:38:38.657367 6, 0xFFFF, sum = 0
6926 12:38:38.661040 7, 0xFFFF, sum = 0
6927 12:38:38.661149 8, 0xFFFF, sum = 0
6928 12:38:38.664913 9, 0xFFFF, sum = 0
6929 12:38:38.664994 10, 0xFFFF, sum = 0
6930 12:38:38.667456 11, 0xFFFF, sum = 0
6931 12:38:38.667537 12, 0xFFFF, sum = 0
6932 12:38:38.671787 13, 0x0, sum = 1
6933 12:38:38.671868 14, 0x0, sum = 2
6934 12:38:38.674338 15, 0x0, sum = 3
6935 12:38:38.674443 16, 0x0, sum = 4
6936 12:38:38.677887 best_step = 14
6937 12:38:38.677967
6938 12:38:38.678030 ==
6939 12:38:38.681001 Dram Type= 6, Freq= 0, CH_1, rank 1
6940 12:38:38.683864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6941 12:38:38.683944 ==
6942 12:38:38.687542 RX Vref Scan: 0
6943 12:38:38.687611
6944 12:38:38.687670 RX Vref 0 -> 0, step: 1
6945 12:38:38.687727
6946 12:38:38.690656 RX Delay -359 -> 252, step: 8
6947 12:38:38.698732 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6948 12:38:38.701850 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6949 12:38:38.704711 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6950 12:38:38.708213 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6951 12:38:38.714803 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6952 12:38:38.718199 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6953 12:38:38.721642 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6954 12:38:38.725038 iDelay=217, Bit 7, Center -40 (-279 ~ 200) 480
6955 12:38:38.731783 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6956 12:38:38.735349 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6957 12:38:38.738626 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6958 12:38:38.741904 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6959 12:38:38.748141 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
6960 12:38:38.752012 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6961 12:38:38.755034 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6962 12:38:38.758784 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6963 12:38:38.761709 ==
6964 12:38:38.765381 Dram Type= 6, Freq= 0, CH_1, rank 1
6965 12:38:38.768337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6966 12:38:38.768417 ==
6967 12:38:38.768481 DQS Delay:
6968 12:38:38.771779 DQS0 = 48, DQS1 = 56
6969 12:38:38.771859 DQM Delay:
6970 12:38:38.775244 DQM0 = 10, DQM1 = 9
6971 12:38:38.775325 DQ Delay:
6972 12:38:38.778304 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6973 12:38:38.782247 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6974 12:38:38.782327 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6975 12:38:38.788537 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6976 12:38:38.788616
6977 12:38:38.788680
6978 12:38:38.795181 [DQSOSCAuto] RK1, (LSB)MR18= 0x7287, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 395 ps
6979 12:38:38.798835 CH1 RK1: MR19=C0C, MR18=7287
6980 12:38:38.805329 CH1_RK1: MR19=0xC0C, MR18=0x7287, DQSOSC=392, MR23=63, INC=384, DEC=256
6981 12:38:38.808177 [RxdqsGatingPostProcess] freq 400
6982 12:38:38.811820 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6983 12:38:38.815094 best DQS0 dly(2T, 0.5T) = (0, 10)
6984 12:38:38.818327 best DQS1 dly(2T, 0.5T) = (0, 10)
6985 12:38:38.821476 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6986 12:38:38.825225 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6987 12:38:38.828322 best DQS0 dly(2T, 0.5T) = (0, 10)
6988 12:38:38.831825 best DQS1 dly(2T, 0.5T) = (0, 10)
6989 12:38:38.834924 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6990 12:38:38.838531 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6991 12:38:38.841857 Pre-setting of DQS Precalculation
6992 12:38:38.845144 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6993 12:38:38.851984 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6994 12:38:38.861689 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6995 12:38:38.861770
6996 12:38:38.861834
6997 12:38:38.865122 [Calibration Summary] 800 Mbps
6998 12:38:38.865203 CH 0, Rank 0
6999 12:38:38.865267 SW Impedance : PASS
7000 12:38:38.869012 DUTY Scan : NO K
7001 12:38:38.872020 ZQ Calibration : PASS
7002 12:38:38.872130 Jitter Meter : NO K
7003 12:38:38.875279 CBT Training : PASS
7004 12:38:38.878970 Write leveling : PASS
7005 12:38:38.879051 RX DQS gating : PASS
7006 12:38:38.882127 RX DQ/DQS(RDDQC) : PASS
7007 12:38:38.885097 TX DQ/DQS : PASS
7008 12:38:38.885177 RX DATLAT : PASS
7009 12:38:38.888701 RX DQ/DQS(Engine): PASS
7010 12:38:38.891918 TX OE : NO K
7011 12:38:38.891999 All Pass.
7012 12:38:38.892063
7013 12:38:38.892122 CH 0, Rank 1
7014 12:38:38.895155 SW Impedance : PASS
7015 12:38:38.898690 DUTY Scan : NO K
7016 12:38:38.898770 ZQ Calibration : PASS
7017 12:38:38.902160 Jitter Meter : NO K
7018 12:38:38.905281 CBT Training : PASS
7019 12:38:38.905362 Write leveling : NO K
7020 12:38:38.908886 RX DQS gating : PASS
7021 12:38:38.908967 RX DQ/DQS(RDDQC) : PASS
7022 12:38:38.911959 TX DQ/DQS : PASS
7023 12:38:38.915320 RX DATLAT : PASS
7024 12:38:38.915400 RX DQ/DQS(Engine): PASS
7025 12:38:38.918844 TX OE : NO K
7026 12:38:38.918924 All Pass.
7027 12:38:38.918988
7028 12:38:38.922258 CH 1, Rank 0
7029 12:38:38.922373 SW Impedance : PASS
7030 12:38:38.925192 DUTY Scan : NO K
7031 12:38:38.929033 ZQ Calibration : PASS
7032 12:38:38.929114 Jitter Meter : NO K
7033 12:38:38.931971 CBT Training : PASS
7034 12:38:38.935632 Write leveling : PASS
7035 12:38:38.935712 RX DQS gating : PASS
7036 12:38:38.938837 RX DQ/DQS(RDDQC) : PASS
7037 12:38:38.941925 TX DQ/DQS : PASS
7038 12:38:38.942030 RX DATLAT : PASS
7039 12:38:38.945641 RX DQ/DQS(Engine): PASS
7040 12:38:38.945713 TX OE : NO K
7041 12:38:38.948963 All Pass.
7042 12:38:38.949043
7043 12:38:38.949107 CH 1, Rank 1
7044 12:38:38.952127 SW Impedance : PASS
7045 12:38:38.952208 DUTY Scan : NO K
7046 12:38:38.955400 ZQ Calibration : PASS
7047 12:38:38.958656 Jitter Meter : NO K
7048 12:38:38.958736 CBT Training : PASS
7049 12:38:38.962021 Write leveling : NO K
7050 12:38:38.965655 RX DQS gating : PASS
7051 12:38:38.965762 RX DQ/DQS(RDDQC) : PASS
7052 12:38:38.968958 TX DQ/DQS : PASS
7053 12:38:38.972314 RX DATLAT : PASS
7054 12:38:38.972394 RX DQ/DQS(Engine): PASS
7055 12:38:38.975530 TX OE : NO K
7056 12:38:38.975610 All Pass.
7057 12:38:38.975674
7058 12:38:38.978961 DramC Write-DBI off
7059 12:38:38.982139 PER_BANK_REFRESH: Hybrid Mode
7060 12:38:38.982245 TX_TRACKING: ON
7061 12:38:38.991986 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7062 12:38:38.995770 [FAST_K] Save calibration result to emmc
7063 12:38:38.998982 dramc_set_vcore_voltage set vcore to 725000
7064 12:38:39.001967 Read voltage for 1600, 0
7065 12:38:39.002047 Vio18 = 0
7066 12:38:39.002111 Vcore = 725000
7067 12:38:39.005279 Vdram = 0
7068 12:38:39.005359 Vddq = 0
7069 12:38:39.005422 Vmddr = 0
7070 12:38:39.012042 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7071 12:38:39.015514 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7072 12:38:39.018963 MEM_TYPE=3, freq_sel=13
7073 12:38:39.021822 sv_algorithm_assistance_LP4_3733
7074 12:38:39.025324 ============ PULL DRAM RESETB DOWN ============
7075 12:38:39.028555 ========== PULL DRAM RESETB DOWN end =========
7076 12:38:39.035325 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7077 12:38:39.038730 ===================================
7078 12:38:39.038810 LPDDR4 DRAM CONFIGURATION
7079 12:38:39.042163 ===================================
7080 12:38:39.045686 EX_ROW_EN[0] = 0x0
7081 12:38:39.048666 EX_ROW_EN[1] = 0x0
7082 12:38:39.048746 LP4Y_EN = 0x0
7083 12:38:39.052375 WORK_FSP = 0x1
7084 12:38:39.052455 WL = 0x5
7085 12:38:39.055552 RL = 0x5
7086 12:38:39.055632 BL = 0x2
7087 12:38:39.058798 RPST = 0x0
7088 12:38:39.058878 RD_PRE = 0x0
7089 12:38:39.062406 WR_PRE = 0x1
7090 12:38:39.062502 WR_PST = 0x1
7091 12:38:39.065337 DBI_WR = 0x0
7092 12:38:39.065417 DBI_RD = 0x0
7093 12:38:39.069110 OTF = 0x1
7094 12:38:39.072003 ===================================
7095 12:38:39.075305 ===================================
7096 12:38:39.075386 ANA top config
7097 12:38:39.078971 ===================================
7098 12:38:39.082236 DLL_ASYNC_EN = 0
7099 12:38:39.085486 ALL_SLAVE_EN = 0
7100 12:38:39.085566 NEW_RANK_MODE = 1
7101 12:38:39.089043 DLL_IDLE_MODE = 1
7102 12:38:39.092667 LP45_APHY_COMB_EN = 1
7103 12:38:39.095389 TX_ODT_DIS = 0
7104 12:38:39.099211 NEW_8X_MODE = 1
7105 12:38:39.102474 ===================================
7106 12:38:39.102555 ===================================
7107 12:38:39.105371 data_rate = 3200
7108 12:38:39.108975 CKR = 1
7109 12:38:39.112107 DQ_P2S_RATIO = 8
7110 12:38:39.115577 ===================================
7111 12:38:39.119131 CA_P2S_RATIO = 8
7112 12:38:39.122633 DQ_CA_OPEN = 0
7113 12:38:39.122714 DQ_SEMI_OPEN = 0
7114 12:38:39.126148 CA_SEMI_OPEN = 0
7115 12:38:39.129334 CA_FULL_RATE = 0
7116 12:38:39.132610 DQ_CKDIV4_EN = 0
7117 12:38:39.135843 CA_CKDIV4_EN = 0
7118 12:38:39.139015 CA_PREDIV_EN = 0
7119 12:38:39.139098 PH8_DLY = 12
7120 12:38:39.142125 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7121 12:38:39.145948 DQ_AAMCK_DIV = 4
7122 12:38:39.148745 CA_AAMCK_DIV = 4
7123 12:38:39.152036 CA_ADMCK_DIV = 4
7124 12:38:39.155994 DQ_TRACK_CA_EN = 0
7125 12:38:39.159228 CA_PICK = 1600
7126 12:38:39.159310 CA_MCKIO = 1600
7127 12:38:39.162263 MCKIO_SEMI = 0
7128 12:38:39.165392 PLL_FREQ = 3068
7129 12:38:39.168735 DQ_UI_PI_RATIO = 32
7130 12:38:39.172480 CA_UI_PI_RATIO = 0
7131 12:38:39.175523 ===================================
7132 12:38:39.179326 ===================================
7133 12:38:39.182369 memory_type:LPDDR4
7134 12:38:39.182475 GP_NUM : 10
7135 12:38:39.185570 SRAM_EN : 1
7136 12:38:39.185652 MD32_EN : 0
7137 12:38:39.188623 ===================================
7138 12:38:39.192174 [ANA_INIT] >>>>>>>>>>>>>>
7139 12:38:39.195481 <<<<<< [CONFIGURE PHASE]: ANA_TX
7140 12:38:39.198634 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7141 12:38:39.201943 ===================================
7142 12:38:39.205509 data_rate = 3200,PCW = 0X7600
7143 12:38:39.208595 ===================================
7144 12:38:39.211868 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7145 12:38:39.218749 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7146 12:38:39.221861 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7147 12:38:39.228471 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7148 12:38:39.231820 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7149 12:38:39.235107 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7150 12:38:39.235190 [ANA_INIT] flow start
7151 12:38:39.238821 [ANA_INIT] PLL >>>>>>>>
7152 12:38:39.242187 [ANA_INIT] PLL <<<<<<<<
7153 12:38:39.242269 [ANA_INIT] MIDPI >>>>>>>>
7154 12:38:39.245191 [ANA_INIT] MIDPI <<<<<<<<
7155 12:38:39.248615 [ANA_INIT] DLL >>>>>>>>
7156 12:38:39.248696 [ANA_INIT] DLL <<<<<<<<
7157 12:38:39.252076 [ANA_INIT] flow end
7158 12:38:39.255510 ============ LP4 DIFF to SE enter ============
7159 12:38:39.258538 ============ LP4 DIFF to SE exit ============
7160 12:38:39.261844 [ANA_INIT] <<<<<<<<<<<<<
7161 12:38:39.265496 [Flow] Enable top DCM control >>>>>
7162 12:38:39.268399 [Flow] Enable top DCM control <<<<<
7163 12:38:39.271873 Enable DLL master slave shuffle
7164 12:38:39.278706 ==============================================================
7165 12:38:39.278789 Gating Mode config
7166 12:38:39.285733 ==============================================================
7167 12:38:39.285817 Config description:
7168 12:38:39.295492 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7169 12:38:39.302019 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7170 12:38:39.308695 SELPH_MODE 0: By rank 1: By Phase
7171 12:38:39.312478 ==============================================================
7172 12:38:39.315625 GAT_TRACK_EN = 1
7173 12:38:39.318716 RX_GATING_MODE = 2
7174 12:38:39.322005 RX_GATING_TRACK_MODE = 2
7175 12:38:39.325575 SELPH_MODE = 1
7176 12:38:39.328546 PICG_EARLY_EN = 1
7177 12:38:39.332433 VALID_LAT_VALUE = 1
7178 12:38:39.335421 ==============================================================
7179 12:38:39.338388 Enter into Gating configuration >>>>
7180 12:38:39.341957 Exit from Gating configuration <<<<
7181 12:38:39.345478 Enter into DVFS_PRE_config >>>>>
7182 12:38:39.358972 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7183 12:38:39.362072 Exit from DVFS_PRE_config <<<<<
7184 12:38:39.365112 Enter into PICG configuration >>>>
7185 12:38:39.365192 Exit from PICG configuration <<<<
7186 12:38:39.368630 [RX_INPUT] configuration >>>>>
7187 12:38:39.372184 [RX_INPUT] configuration <<<<<
7188 12:38:39.378475 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7189 12:38:39.382129 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7190 12:38:39.388744 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7191 12:38:39.395502 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7192 12:38:39.402281 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7193 12:38:39.408842 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7194 12:38:39.412398 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7195 12:38:39.416146 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7196 12:38:39.419350 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7197 12:38:39.425922 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7198 12:38:39.428813 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7199 12:38:39.432489 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7200 12:38:39.435439 ===================================
7201 12:38:39.439127 LPDDR4 DRAM CONFIGURATION
7202 12:38:39.442305 ===================================
7203 12:38:39.442449 EX_ROW_EN[0] = 0x0
7204 12:38:39.445876 EX_ROW_EN[1] = 0x0
7205 12:38:39.448896 LP4Y_EN = 0x0
7206 12:38:39.448976 WORK_FSP = 0x1
7207 12:38:39.452691 WL = 0x5
7208 12:38:39.452771 RL = 0x5
7209 12:38:39.455973 BL = 0x2
7210 12:38:39.456053 RPST = 0x0
7211 12:38:39.458923 RD_PRE = 0x0
7212 12:38:39.459004 WR_PRE = 0x1
7213 12:38:39.462161 WR_PST = 0x1
7214 12:38:39.462241 DBI_WR = 0x0
7215 12:38:39.465722 DBI_RD = 0x0
7216 12:38:39.465803 OTF = 0x1
7217 12:38:39.468776 ===================================
7218 12:38:39.472306 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7219 12:38:39.478719 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7220 12:38:39.481983 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7221 12:38:39.485612 ===================================
7222 12:38:39.488659 LPDDR4 DRAM CONFIGURATION
7223 12:38:39.492160 ===================================
7224 12:38:39.492269 EX_ROW_EN[0] = 0x10
7225 12:38:39.495726 EX_ROW_EN[1] = 0x0
7226 12:38:39.495806 LP4Y_EN = 0x0
7227 12:38:39.498972 WORK_FSP = 0x1
7228 12:38:39.499053 WL = 0x5
7229 12:38:39.502109 RL = 0x5
7230 12:38:39.505508 BL = 0x2
7231 12:38:39.505639 RPST = 0x0
7232 12:38:39.508601 RD_PRE = 0x0
7233 12:38:39.508681 WR_PRE = 0x1
7234 12:38:39.511920 WR_PST = 0x1
7235 12:38:39.512000 DBI_WR = 0x0
7236 12:38:39.516014 DBI_RD = 0x0
7237 12:38:39.516095 OTF = 0x1
7238 12:38:39.519073 ===================================
7239 12:38:39.525574 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7240 12:38:39.525654 ==
7241 12:38:39.528632 Dram Type= 6, Freq= 0, CH_0, rank 0
7242 12:38:39.531900 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7243 12:38:39.531981 ==
7244 12:38:39.536299 [Duty_Offset_Calibration]
7245 12:38:39.538885 B0:2 B1:-1 CA:1
7246 12:38:39.538965
7247 12:38:39.542283 [DutyScan_Calibration_Flow] k_type=0
7248 12:38:39.549396
7249 12:38:39.549479 ==CLK 0==
7250 12:38:39.552701 Final CLK duty delay cell = -4
7251 12:38:39.556216 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7252 12:38:39.559575 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7253 12:38:39.563162 [-4] AVG Duty = 4937%(X100)
7254 12:38:39.563242
7255 12:38:39.566357 CH0 CLK Duty spec in!! Max-Min= 187%
7256 12:38:39.569467 [DutyScan_Calibration_Flow] ====Done====
7257 12:38:39.569546
7258 12:38:39.572961 [DutyScan_Calibration_Flow] k_type=1
7259 12:38:39.589141
7260 12:38:39.589220 ==DQS 0 ==
7261 12:38:39.592247 Final DQS duty delay cell = 0
7262 12:38:39.595869 [0] MAX Duty = 5125%(X100), DQS PI = 20
7263 12:38:39.599033 [0] MIN Duty = 5000%(X100), DQS PI = 14
7264 12:38:39.599114 [0] AVG Duty = 5062%(X100)
7265 12:38:39.602655
7266 12:38:39.602734 ==DQS 1 ==
7267 12:38:39.606193 Final DQS duty delay cell = -4
7268 12:38:39.609025 [-4] MAX Duty = 5124%(X100), DQS PI = 2
7269 12:38:39.612477 [-4] MIN Duty = 5031%(X100), DQS PI = 24
7270 12:38:39.615802 [-4] AVG Duty = 5077%(X100)
7271 12:38:39.615882
7272 12:38:39.618943 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7273 12:38:39.619024
7274 12:38:39.622555 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7275 12:38:39.626034 [DutyScan_Calibration_Flow] ====Done====
7276 12:38:39.626114
7277 12:38:39.629219 [DutyScan_Calibration_Flow] k_type=3
7278 12:38:39.646641
7279 12:38:39.646722 ==DQM 0 ==
7280 12:38:39.649916 Final DQM duty delay cell = 0
7281 12:38:39.653204 [0] MAX Duty = 5000%(X100), DQS PI = 18
7282 12:38:39.656592 [0] MIN Duty = 4875%(X100), DQS PI = 6
7283 12:38:39.656673 [0] AVG Duty = 4937%(X100)
7284 12:38:39.659596
7285 12:38:39.659675 ==DQM 1 ==
7286 12:38:39.662813 Final DQM duty delay cell = 0
7287 12:38:39.666691 [0] MAX Duty = 5218%(X100), DQS PI = 58
7288 12:38:39.669747 [0] MIN Duty = 4969%(X100), DQS PI = 18
7289 12:38:39.672822 [0] AVG Duty = 5093%(X100)
7290 12:38:39.672903
7291 12:38:39.676343 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7292 12:38:39.676424
7293 12:38:39.679685 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7294 12:38:39.683510 [DutyScan_Calibration_Flow] ====Done====
7295 12:38:39.683591
7296 12:38:39.686248 [DutyScan_Calibration_Flow] k_type=2
7297 12:38:39.702708
7298 12:38:39.702788 ==DQ 0 ==
7299 12:38:39.706793 Final DQ duty delay cell = -4
7300 12:38:39.709745 [-4] MAX Duty = 5031%(X100), DQS PI = 56
7301 12:38:39.712662 [-4] MIN Duty = 4844%(X100), DQS PI = 14
7302 12:38:39.716686 [-4] AVG Duty = 4937%(X100)
7303 12:38:39.716766
7304 12:38:39.716830 ==DQ 1 ==
7305 12:38:39.719385 Final DQ duty delay cell = 0
7306 12:38:39.723211 [0] MAX Duty = 5031%(X100), DQS PI = 38
7307 12:38:39.726236 [0] MIN Duty = 4907%(X100), DQS PI = 44
7308 12:38:39.729353 [0] AVG Duty = 4969%(X100)
7309 12:38:39.729434
7310 12:38:39.732627 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7311 12:38:39.732733
7312 12:38:39.736120 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7313 12:38:39.739775 [DutyScan_Calibration_Flow] ====Done====
7314 12:38:39.739856 ==
7315 12:38:39.743093 Dram Type= 6, Freq= 0, CH_1, rank 0
7316 12:38:39.746136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7317 12:38:39.746218 ==
7318 12:38:39.749902 [Duty_Offset_Calibration]
7319 12:38:39.749983 B0:1 B1:1 CA:2
7320 12:38:39.750047
7321 12:38:39.752944 [DutyScan_Calibration_Flow] k_type=0
7322 12:38:39.763207
7323 12:38:39.763287 ==CLK 0==
7324 12:38:39.767331 Final CLK duty delay cell = 0
7325 12:38:39.770610 [0] MAX Duty = 5156%(X100), DQS PI = 22
7326 12:38:39.773186 [0] MIN Duty = 4938%(X100), DQS PI = 58
7327 12:38:39.773267 [0] AVG Duty = 5047%(X100)
7328 12:38:39.776916
7329 12:38:39.780206 CH1 CLK Duty spec in!! Max-Min= 218%
7330 12:38:39.783337 [DutyScan_Calibration_Flow] ====Done====
7331 12:38:39.783418
7332 12:38:39.786902 [DutyScan_Calibration_Flow] k_type=1
7333 12:38:39.803354
7334 12:38:39.803433 ==DQS 0 ==
7335 12:38:39.806959 Final DQS duty delay cell = 0
7336 12:38:39.809832 [0] MAX Duty = 5062%(X100), DQS PI = 20
7337 12:38:39.813755 [0] MIN Duty = 4813%(X100), DQS PI = 50
7338 12:38:39.813834 [0] AVG Duty = 4937%(X100)
7339 12:38:39.816774
7340 12:38:39.816853 ==DQS 1 ==
7341 12:38:39.819887 Final DQS duty delay cell = 0
7342 12:38:39.823588 [0] MAX Duty = 5062%(X100), DQS PI = 56
7343 12:38:39.826735 [0] MIN Duty = 4938%(X100), DQS PI = 14
7344 12:38:39.826815 [0] AVG Duty = 5000%(X100)
7345 12:38:39.829772
7346 12:38:39.833665 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7347 12:38:39.833745
7348 12:38:39.836279 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7349 12:38:39.839710 [DutyScan_Calibration_Flow] ====Done====
7350 12:38:39.839789
7351 12:38:39.843009 [DutyScan_Calibration_Flow] k_type=3
7352 12:38:39.860300
7353 12:38:39.860383 ==DQM 0 ==
7354 12:38:39.863439 Final DQM duty delay cell = 0
7355 12:38:39.866994 [0] MAX Duty = 5156%(X100), DQS PI = 20
7356 12:38:39.870102 [0] MIN Duty = 4876%(X100), DQS PI = 46
7357 12:38:39.873807 [0] AVG Duty = 5016%(X100)
7358 12:38:39.873890
7359 12:38:39.873975 ==DQM 1 ==
7360 12:38:39.876766 Final DQM duty delay cell = 0
7361 12:38:39.880795 [0] MAX Duty = 5125%(X100), DQS PI = 10
7362 12:38:39.883798 [0] MIN Duty = 4875%(X100), DQS PI = 20
7363 12:38:39.883880 [0] AVG Duty = 5000%(X100)
7364 12:38:39.887051
7365 12:38:39.890036 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7366 12:38:39.890117
7367 12:38:39.893806 CH1 DQM 1 Duty spec in!! Max-Min= 250%
7368 12:38:39.896910 [DutyScan_Calibration_Flow] ====Done====
7369 12:38:39.896990
7370 12:38:39.900005 [DutyScan_Calibration_Flow] k_type=2
7371 12:38:39.917171
7372 12:38:39.917252 ==DQ 0 ==
7373 12:38:39.921235 Final DQ duty delay cell = 0
7374 12:38:39.924256 [0] MAX Duty = 5156%(X100), DQS PI = 20
7375 12:38:39.927492 [0] MIN Duty = 4938%(X100), DQS PI = 52
7376 12:38:39.927572 [0] AVG Duty = 5047%(X100)
7377 12:38:39.930565
7378 12:38:39.930644 ==DQ 1 ==
7379 12:38:39.933570 Final DQ duty delay cell = 0
7380 12:38:39.937045 [0] MAX Duty = 5093%(X100), DQS PI = 8
7381 12:38:39.940057 [0] MIN Duty = 5031%(X100), DQS PI = 0
7382 12:38:39.940138 [0] AVG Duty = 5062%(X100)
7383 12:38:39.940203
7384 12:38:39.943815 CH1 DQ 0 Duty spec in!! Max-Min= 218%
7385 12:38:39.946791
7386 12:38:39.946871 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7387 12:38:39.953314 [DutyScan_Calibration_Flow] ====Done====
7388 12:38:39.956709 nWR fixed to 30
7389 12:38:39.956790 [ModeRegInit_LP4] CH0 RK0
7390 12:38:39.960807 [ModeRegInit_LP4] CH0 RK1
7391 12:38:39.963595 [ModeRegInit_LP4] CH1 RK0
7392 12:38:39.963679 [ModeRegInit_LP4] CH1 RK1
7393 12:38:39.966571 match AC timing 5
7394 12:38:39.970296 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7395 12:38:39.973266 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7396 12:38:39.980184 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7397 12:38:39.983568 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7398 12:38:39.990519 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7399 12:38:39.990602 [MiockJmeterHQA]
7400 12:38:39.990667
7401 12:38:39.993456 [DramcMiockJmeter] u1RxGatingPI = 0
7402 12:38:39.996573 0 : 4253, 4026
7403 12:38:39.996656 4 : 4253, 4026
7404 12:38:39.996721 8 : 4255, 4029
7405 12:38:40.000128 12 : 4365, 4142
7406 12:38:40.000210 16 : 4252, 4027
7407 12:38:40.003205 20 : 4255, 4029
7408 12:38:40.003286 24 : 4252, 4027
7409 12:38:40.006925 28 : 4363, 4137
7410 12:38:40.007006 32 : 4252, 4027
7411 12:38:40.010073 36 : 4364, 4137
7412 12:38:40.010154 40 : 4252, 4027
7413 12:38:40.010219 44 : 4252, 4027
7414 12:38:40.013007 48 : 4253, 4026
7415 12:38:40.013088 52 : 4252, 4027
7416 12:38:40.016952 56 : 4364, 4137
7417 12:38:40.017033 60 : 4250, 4027
7418 12:38:40.019778 64 : 4360, 4138
7419 12:38:40.019889 68 : 4250, 4027
7420 12:38:40.019982 72 : 4253, 4029
7421 12:38:40.023364 76 : 4250, 4027
7422 12:38:40.023445 80 : 4361, 4137
7423 12:38:40.026595 84 : 4250, 4027
7424 12:38:40.026676 88 : 4360, 4137
7425 12:38:40.030087 92 : 4250, 4027
7426 12:38:40.030168 96 : 4250, 3384
7427 12:38:40.030233 100 : 4250, 0
7428 12:38:40.033934 104 : 4250, 0
7429 12:38:40.034015 108 : 4253, 0
7430 12:38:40.036879 112 : 4360, 0
7431 12:38:40.036960 116 : 4360, 0
7432 12:38:40.037024 120 : 4247, 0
7433 12:38:40.039862 124 : 4250, 0
7434 12:38:40.039999 128 : 4361, 0
7435 12:38:40.043575 132 : 4360, 0
7436 12:38:40.043654 136 : 4250, 0
7437 12:38:40.043718 140 : 4250, 0
7438 12:38:40.046615 144 : 4250, 0
7439 12:38:40.046696 148 : 4250, 0
7440 12:38:40.050253 152 : 4250, 0
7441 12:38:40.050334 156 : 4252, 0
7442 12:38:40.050406 160 : 4250, 0
7443 12:38:40.053358 164 : 4361, 0
7444 12:38:40.053438 168 : 4360, 0
7445 12:38:40.053503 172 : 4247, 0
7446 12:38:40.056643 176 : 4360, 0
7447 12:38:40.056724 180 : 4360, 0
7448 12:38:40.060139 184 : 4360, 0
7449 12:38:40.060220 188 : 4250, 0
7450 12:38:40.060286 192 : 4250, 0
7451 12:38:40.063221 196 : 4250, 0
7452 12:38:40.063302 200 : 4250, 0
7453 12:38:40.066731 204 : 4250, 0
7454 12:38:40.066840 208 : 4250, 0
7455 12:38:40.066934 212 : 4252, 326
7456 12:38:40.069935 216 : 4360, 3906
7457 12:38:40.070015 220 : 4249, 4027
7458 12:38:40.073173 224 : 4250, 4026
7459 12:38:40.073254 228 : 4250, 4027
7460 12:38:40.076485 232 : 4249, 4027
7461 12:38:40.076566 236 : 4250, 4027
7462 12:38:40.080075 240 : 4250, 4027
7463 12:38:40.080156 244 : 4250, 4027
7464 12:38:40.083254 248 : 4249, 4027
7465 12:38:40.083362 252 : 4360, 4137
7466 12:38:40.086385 256 : 4361, 4138
7467 12:38:40.086489 260 : 4247, 4025
7468 12:38:40.086554 264 : 4361, 4138
7469 12:38:40.090338 268 : 4360, 4137
7470 12:38:40.090442 272 : 4250, 4026
7471 12:38:40.093099 276 : 4250, 4027
7472 12:38:40.093180 280 : 4250, 4027
7473 12:38:40.097390 284 : 4250, 4027
7474 12:38:40.097475 288 : 4250, 4026
7475 12:38:40.100032 292 : 4250, 4027
7476 12:38:40.100113 296 : 4250, 4027
7477 12:38:40.103642 300 : 4249, 4027
7478 12:38:40.103723 304 : 4360, 4137
7479 12:38:40.106833 308 : 4361, 4137
7480 12:38:40.106913 312 : 4247, 4025
7481 12:38:40.106978 316 : 4360, 4138
7482 12:38:40.110016 320 : 4361, 4137
7483 12:38:40.110128 324 : 4250, 4027
7484 12:38:40.113223 328 : 4250, 4027
7485 12:38:40.113304 332 : 4250, 3033
7486 12:38:40.116818 336 : 4250, 98
7487 12:38:40.116899
7488 12:38:40.116963 MIOCK jitter meter ch=0
7489 12:38:40.119834
7490 12:38:40.119913 1T = (336-100) = 236 dly cells
7491 12:38:40.126710 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7492 12:38:40.126790 ==
7493 12:38:40.129688 Dram Type= 6, Freq= 0, CH_0, rank 0
7494 12:38:40.133366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7495 12:38:40.133448 ==
7496 12:38:40.140535 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7497 12:38:40.143219 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7498 12:38:40.150131 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7499 12:38:40.153798 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7500 12:38:40.163519 [CA 0] Center 44 (14~75) winsize 62
7501 12:38:40.167097 [CA 1] Center 44 (13~75) winsize 63
7502 12:38:40.170024 [CA 2] Center 40 (11~69) winsize 59
7503 12:38:40.173192 [CA 3] Center 39 (10~69) winsize 60
7504 12:38:40.176631 [CA 4] Center 38 (8~68) winsize 61
7505 12:38:40.180171 [CA 5] Center 37 (7~67) winsize 61
7506 12:38:40.180251
7507 12:38:40.183388 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7508 12:38:40.183470
7509 12:38:40.187700 [CATrainingPosCal] consider 1 rank data
7510 12:38:40.190063 u2DelayCellTimex100 = 275/100 ps
7511 12:38:40.193659 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7512 12:38:40.200388 CA1 delay=44 (13~75),Diff = 7 PI (24 cell)
7513 12:38:40.203333 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7514 12:38:40.206945 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7515 12:38:40.210012 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7516 12:38:40.213692 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7517 12:38:40.213769
7518 12:38:40.216810 CA PerBit enable=1, Macro0, CA PI delay=37
7519 12:38:40.216885
7520 12:38:40.220456 [CBTSetCACLKResult] CA Dly = 37
7521 12:38:40.223395 CS Dly: 11 (0~42)
7522 12:38:40.227204 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7523 12:38:40.230243 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7524 12:38:40.230325 ==
7525 12:38:40.233358 Dram Type= 6, Freq= 0, CH_0, rank 1
7526 12:38:40.237145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7527 12:38:40.240191 ==
7528 12:38:40.243520 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7529 12:38:40.246980 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7530 12:38:40.253756 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7531 12:38:40.256914 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7532 12:38:40.267472 [CA 0] Center 44 (14~75) winsize 62
7533 12:38:40.270575 [CA 1] Center 43 (13~74) winsize 62
7534 12:38:40.274096 [CA 2] Center 39 (10~69) winsize 60
7535 12:38:40.277839 [CA 3] Center 39 (9~69) winsize 61
7536 12:38:40.280837 [CA 4] Center 37 (7~67) winsize 61
7537 12:38:40.284361 [CA 5] Center 37 (7~67) winsize 61
7538 12:38:40.284443
7539 12:38:40.287376 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7540 12:38:40.287458
7541 12:38:40.291328 [CATrainingPosCal] consider 2 rank data
7542 12:38:40.294006 u2DelayCellTimex100 = 275/100 ps
7543 12:38:40.297562 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7544 12:38:40.303978 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7545 12:38:40.307743 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7546 12:38:40.310822 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7547 12:38:40.313914 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7548 12:38:40.317357 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7549 12:38:40.317441
7550 12:38:40.320636 CA PerBit enable=1, Macro0, CA PI delay=37
7551 12:38:40.320719
7552 12:38:40.324217 [CBTSetCACLKResult] CA Dly = 37
7553 12:38:40.327414 CS Dly: 11 (0~43)
7554 12:38:40.330653 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7555 12:38:40.334355 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7556 12:38:40.334472
7557 12:38:40.337494 ----->DramcWriteLeveling(PI) begin...
7558 12:38:40.337578 ==
7559 12:38:40.340511 Dram Type= 6, Freq= 0, CH_0, rank 0
7560 12:38:40.347543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7561 12:38:40.347626 ==
7562 12:38:40.350658 Write leveling (Byte 0): 33 => 33
7563 12:38:40.350741 Write leveling (Byte 1): 27 => 27
7564 12:38:40.353745 DramcWriteLeveling(PI) end<-----
7565 12:38:40.353826
7566 12:38:40.353909 ==
7567 12:38:40.357029 Dram Type= 6, Freq= 0, CH_0, rank 0
7568 12:38:40.363706 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7569 12:38:40.363789 ==
7570 12:38:40.367429 [Gating] SW mode calibration
7571 12:38:40.373950 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7572 12:38:40.377776 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7573 12:38:40.383812 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7574 12:38:40.387493 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7575 12:38:40.390777 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7576 12:38:40.397793 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 12:38:40.400933 1 4 16 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7578 12:38:40.403926 1 4 20 | B1->B0 | 2828 3434 | 0 1 | (1 1) (1 1)
7579 12:38:40.408016 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7580 12:38:40.413779 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7581 12:38:40.417162 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7582 12:38:40.420518 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7583 12:38:40.427365 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7584 12:38:40.430265 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7585 12:38:40.433717 1 5 16 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
7586 12:38:40.440594 1 5 20 | B1->B0 | 3434 2424 | 1 0 | (1 0) (1 0)
7587 12:38:40.443894 1 5 24 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
7588 12:38:40.447449 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 12:38:40.454107 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 12:38:40.457130 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 12:38:40.460217 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7592 12:38:40.467086 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7593 12:38:40.470268 1 6 16 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
7594 12:38:40.473835 1 6 20 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7595 12:38:40.480798 1 6 24 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
7596 12:38:40.483477 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7597 12:38:40.487379 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 12:38:40.493958 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 12:38:40.497077 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 12:38:40.500423 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7601 12:38:40.503574 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7602 12:38:40.510381 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7603 12:38:40.513812 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7604 12:38:40.517515 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 12:38:40.523791 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 12:38:40.527122 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 12:38:40.530273 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7608 12:38:40.537004 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7609 12:38:40.540345 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 12:38:40.544056 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 12:38:40.550350 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 12:38:40.554054 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 12:38:40.556838 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 12:38:40.563531 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 12:38:40.567534 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 12:38:40.570301 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7617 12:38:40.577109 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7618 12:38:40.580156 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7619 12:38:40.583833 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7620 12:38:40.587276 Total UI for P1: 0, mck2ui 16
7621 12:38:40.590366 best dqsien dly found for B0: ( 1, 9, 16)
7622 12:38:40.593602 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 12:38:40.597194 Total UI for P1: 0, mck2ui 16
7624 12:38:40.600182 best dqsien dly found for B1: ( 1, 9, 22)
7625 12:38:40.606907 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7626 12:38:40.610521 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7627 12:38:40.610602
7628 12:38:40.613517 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7629 12:38:40.616825 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7630 12:38:40.620499 [Gating] SW calibration Done
7631 12:38:40.620579 ==
7632 12:38:40.623634 Dram Type= 6, Freq= 0, CH_0, rank 0
7633 12:38:40.626704 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7634 12:38:40.626785 ==
7635 12:38:40.630190 RX Vref Scan: 0
7636 12:38:40.630270
7637 12:38:40.630380 RX Vref 0 -> 0, step: 1
7638 12:38:40.630501
7639 12:38:40.633629 RX Delay 0 -> 252, step: 8
7640 12:38:40.637365 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7641 12:38:40.640059 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7642 12:38:40.646645 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7643 12:38:40.650133 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7644 12:38:40.653446 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7645 12:38:40.656894 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7646 12:38:40.660513 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7647 12:38:40.666706 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7648 12:38:40.670280 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7649 12:38:40.673637 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7650 12:38:40.676703 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7651 12:38:40.680357 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7652 12:38:40.686912 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7653 12:38:40.689898 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7654 12:38:40.693585 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7655 12:38:40.696734 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7656 12:38:40.696815 ==
7657 12:38:40.700781 Dram Type= 6, Freq= 0, CH_0, rank 0
7658 12:38:40.706765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7659 12:38:40.706847 ==
7660 12:38:40.706911 DQS Delay:
7661 12:38:40.709885 DQS0 = 0, DQS1 = 0
7662 12:38:40.709965 DQM Delay:
7663 12:38:40.710030 DQM0 = 132, DQM1 = 124
7664 12:38:40.714028 DQ Delay:
7665 12:38:40.716889 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7666 12:38:40.720092 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7667 12:38:40.723732 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =115
7668 12:38:40.726712 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7669 12:38:40.726793
7670 12:38:40.726856
7671 12:38:40.726916 ==
7672 12:38:40.730039 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 12:38:40.733618 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7674 12:38:40.737472 ==
7675 12:38:40.737552
7676 12:38:40.737616
7677 12:38:40.737675 TX Vref Scan disable
7678 12:38:40.740321 == TX Byte 0 ==
7679 12:38:40.743477 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7680 12:38:40.746657 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7681 12:38:40.750303 == TX Byte 1 ==
7682 12:38:40.753616 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7683 12:38:40.756782 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7684 12:38:40.756862 ==
7685 12:38:40.760534 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 12:38:40.766775 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 12:38:40.766856 ==
7688 12:38:40.780989
7689 12:38:40.784023 TX Vref early break, caculate TX vref
7690 12:38:40.787000 TX Vref=16, minBit 4, minWin=20, winSum=348
7691 12:38:40.790930 TX Vref=18, minBit 0, minWin=22, winSum=364
7692 12:38:40.793706 TX Vref=20, minBit 0, minWin=22, winSum=374
7693 12:38:40.797259 TX Vref=22, minBit 4, minWin=22, winSum=383
7694 12:38:40.800521 TX Vref=24, minBit 7, minWin=23, winSum=396
7695 12:38:40.807602 TX Vref=26, minBit 4, minWin=24, winSum=407
7696 12:38:40.810929 TX Vref=28, minBit 7, minWin=24, winSum=413
7697 12:38:40.814158 TX Vref=30, minBit 4, minWin=24, winSum=415
7698 12:38:40.816890 TX Vref=32, minBit 0, minWin=24, winSum=411
7699 12:38:40.820299 TX Vref=34, minBit 4, minWin=23, winSum=397
7700 12:38:40.823982 TX Vref=36, minBit 0, minWin=23, winSum=387
7701 12:38:40.830474 [TxChooseVref] Worse bit 4, Min win 24, Win sum 415, Final Vref 30
7702 12:38:40.830556
7703 12:38:40.834074 Final TX Range 0 Vref 30
7704 12:38:40.834155
7705 12:38:40.834219 ==
7706 12:38:40.837024 Dram Type= 6, Freq= 0, CH_0, rank 0
7707 12:38:40.840587 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7708 12:38:40.840668 ==
7709 12:38:40.840733
7710 12:38:40.840792
7711 12:38:40.843592 TX Vref Scan disable
7712 12:38:40.850590 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7713 12:38:40.850671 == TX Byte 0 ==
7714 12:38:40.853617 u2DelayCellOfst[0]=14 cells (4 PI)
7715 12:38:40.857357 u2DelayCellOfst[1]=17 cells (5 PI)
7716 12:38:40.861068 u2DelayCellOfst[2]=10 cells (3 PI)
7717 12:38:40.863676 u2DelayCellOfst[3]=14 cells (4 PI)
7718 12:38:40.867280 u2DelayCellOfst[4]=10 cells (3 PI)
7719 12:38:40.870712 u2DelayCellOfst[5]=0 cells (0 PI)
7720 12:38:40.873583 u2DelayCellOfst[6]=21 cells (6 PI)
7721 12:38:40.877156 u2DelayCellOfst[7]=17 cells (5 PI)
7722 12:38:40.880796 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7723 12:38:40.884064 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7724 12:38:40.887372 == TX Byte 1 ==
7725 12:38:40.887452 u2DelayCellOfst[8]=0 cells (0 PI)
7726 12:38:40.890283 u2DelayCellOfst[9]=0 cells (0 PI)
7727 12:38:40.894553 u2DelayCellOfst[10]=7 cells (2 PI)
7728 12:38:40.897399 u2DelayCellOfst[11]=3 cells (1 PI)
7729 12:38:40.900836 u2DelayCellOfst[12]=14 cells (4 PI)
7730 12:38:40.903939 u2DelayCellOfst[13]=10 cells (3 PI)
7731 12:38:40.907085 u2DelayCellOfst[14]=17 cells (5 PI)
7732 12:38:40.911022 u2DelayCellOfst[15]=10 cells (3 PI)
7733 12:38:40.914644 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7734 12:38:40.920828 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7735 12:38:40.920909 DramC Write-DBI on
7736 12:38:40.920974 ==
7737 12:38:40.924131 Dram Type= 6, Freq= 0, CH_0, rank 0
7738 12:38:40.927501 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7739 12:38:40.930452 ==
7740 12:38:40.930533
7741 12:38:40.930597
7742 12:38:40.930656 TX Vref Scan disable
7743 12:38:40.934312 == TX Byte 0 ==
7744 12:38:40.937217 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7745 12:38:40.940645 == TX Byte 1 ==
7746 12:38:40.944002 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7747 12:38:40.947003 DramC Write-DBI off
7748 12:38:40.947097
7749 12:38:40.947191 [DATLAT]
7750 12:38:40.947267 Freq=1600, CH0 RK0
7751 12:38:40.947326
7752 12:38:40.950446 DATLAT Default: 0xf
7753 12:38:40.950526 0, 0xFFFF, sum = 0
7754 12:38:40.954200 1, 0xFFFF, sum = 0
7755 12:38:40.957425 2, 0xFFFF, sum = 0
7756 12:38:40.957537 3, 0xFFFF, sum = 0
7757 12:38:40.960767 4, 0xFFFF, sum = 0
7758 12:38:40.960849 5, 0xFFFF, sum = 0
7759 12:38:40.963908 6, 0xFFFF, sum = 0
7760 12:38:40.963990 7, 0xFFFF, sum = 0
7761 12:38:40.967365 8, 0xFFFF, sum = 0
7762 12:38:40.967447 9, 0xFFFF, sum = 0
7763 12:38:40.970835 10, 0xFFFF, sum = 0
7764 12:38:40.970917 11, 0xFFFF, sum = 0
7765 12:38:40.974334 12, 0xFFFF, sum = 0
7766 12:38:40.974439 13, 0xFFFF, sum = 0
7767 12:38:40.977251 14, 0x0, sum = 1
7768 12:38:40.977333 15, 0x0, sum = 2
7769 12:38:40.980496 16, 0x0, sum = 3
7770 12:38:40.980593 17, 0x0, sum = 4
7771 12:38:40.984006 best_step = 15
7772 12:38:40.984086
7773 12:38:40.984151 ==
7774 12:38:40.987336 Dram Type= 6, Freq= 0, CH_0, rank 0
7775 12:38:40.990564 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7776 12:38:40.990645 ==
7777 12:38:40.990709 RX Vref Scan: 1
7778 12:38:40.994065
7779 12:38:40.994160 Set Vref Range= 24 -> 127
7780 12:38:40.994255
7781 12:38:40.997428 RX Vref 24 -> 127, step: 1
7782 12:38:40.997508
7783 12:38:41.000724 RX Delay 11 -> 252, step: 4
7784 12:38:41.000805
7785 12:38:41.003962 Set Vref, RX VrefLevel [Byte0]: 24
7786 12:38:41.007300 [Byte1]: 24
7787 12:38:41.007400
7788 12:38:41.010484 Set Vref, RX VrefLevel [Byte0]: 25
7789 12:38:41.014044 [Byte1]: 25
7790 12:38:41.014125
7791 12:38:41.017148 Set Vref, RX VrefLevel [Byte0]: 26
7792 12:38:41.020442 [Byte1]: 26
7793 12:38:41.024569
7794 12:38:41.024666 Set Vref, RX VrefLevel [Byte0]: 27
7795 12:38:41.027773 [Byte1]: 27
7796 12:38:41.031968
7797 12:38:41.032050 Set Vref, RX VrefLevel [Byte0]: 28
7798 12:38:41.035756 [Byte1]: 28
7799 12:38:41.039617
7800 12:38:41.039699 Set Vref, RX VrefLevel [Byte0]: 29
7801 12:38:41.043178 [Byte1]: 29
7802 12:38:41.047449
7803 12:38:41.047531 Set Vref, RX VrefLevel [Byte0]: 30
7804 12:38:41.050596 [Byte1]: 30
7805 12:38:41.054776
7806 12:38:41.054857 Set Vref, RX VrefLevel [Byte0]: 31
7807 12:38:41.057967 [Byte1]: 31
7808 12:38:41.062371
7809 12:38:41.062476 Set Vref, RX VrefLevel [Byte0]: 32
7810 12:38:41.066231 [Byte1]: 32
7811 12:38:41.069865
7812 12:38:41.069945 Set Vref, RX VrefLevel [Byte0]: 33
7813 12:38:41.073681 [Byte1]: 33
7814 12:38:41.077804
7815 12:38:41.077884 Set Vref, RX VrefLevel [Byte0]: 34
7816 12:38:41.081155 [Byte1]: 34
7817 12:38:41.085403
7818 12:38:41.085483 Set Vref, RX VrefLevel [Byte0]: 35
7819 12:38:41.088969 [Byte1]: 35
7820 12:38:41.092845
7821 12:38:41.092982 Set Vref, RX VrefLevel [Byte0]: 36
7822 12:38:41.096500 [Byte1]: 36
7823 12:38:41.100656
7824 12:38:41.100736 Set Vref, RX VrefLevel [Byte0]: 37
7825 12:38:41.103926 [Byte1]: 37
7826 12:38:41.108004
7827 12:38:41.108085 Set Vref, RX VrefLevel [Byte0]: 38
7828 12:38:41.111865 [Byte1]: 38
7829 12:38:41.115535
7830 12:38:41.115615 Set Vref, RX VrefLevel [Byte0]: 39
7831 12:38:41.119212 [Byte1]: 39
7832 12:38:41.123771
7833 12:38:41.123851 Set Vref, RX VrefLevel [Byte0]: 40
7834 12:38:41.126498 [Byte1]: 40
7835 12:38:41.131093
7836 12:38:41.131173 Set Vref, RX VrefLevel [Byte0]: 41
7837 12:38:41.134627 [Byte1]: 41
7838 12:38:41.138843
7839 12:38:41.138924 Set Vref, RX VrefLevel [Byte0]: 42
7840 12:38:41.142111 [Byte1]: 42
7841 12:38:41.146348
7842 12:38:41.146454 Set Vref, RX VrefLevel [Byte0]: 43
7843 12:38:41.149488 [Byte1]: 43
7844 12:38:41.153981
7845 12:38:41.154061 Set Vref, RX VrefLevel [Byte0]: 44
7846 12:38:41.157486 [Byte1]: 44
7847 12:38:41.161570
7848 12:38:41.161650 Set Vref, RX VrefLevel [Byte0]: 45
7849 12:38:41.164696 [Byte1]: 45
7850 12:38:41.169243
7851 12:38:41.169324 Set Vref, RX VrefLevel [Byte0]: 46
7852 12:38:41.172389 [Byte1]: 46
7853 12:38:41.176671
7854 12:38:41.176751 Set Vref, RX VrefLevel [Byte0]: 47
7855 12:38:41.180098 [Byte1]: 47
7856 12:38:41.184008
7857 12:38:41.184087 Set Vref, RX VrefLevel [Byte0]: 48
7858 12:38:41.187509 [Byte1]: 48
7859 12:38:41.191673
7860 12:38:41.191752 Set Vref, RX VrefLevel [Byte0]: 49
7861 12:38:41.195149 [Byte1]: 49
7862 12:38:41.199886
7863 12:38:41.199994 Set Vref, RX VrefLevel [Byte0]: 50
7864 12:38:41.202942 [Byte1]: 50
7865 12:38:41.207606
7866 12:38:41.207718 Set Vref, RX VrefLevel [Byte0]: 51
7867 12:38:41.210144 [Byte1]: 51
7868 12:38:41.214451
7869 12:38:41.214531 Set Vref, RX VrefLevel [Byte0]: 52
7870 12:38:41.217742 [Byte1]: 52
7871 12:38:41.222573
7872 12:38:41.222652 Set Vref, RX VrefLevel [Byte0]: 53
7873 12:38:41.225644 [Byte1]: 53
7874 12:38:41.229946
7875 12:38:41.230026 Set Vref, RX VrefLevel [Byte0]: 54
7876 12:38:41.233603 [Byte1]: 54
7877 12:38:41.237432
7878 12:38:41.237512 Set Vref, RX VrefLevel [Byte0]: 55
7879 12:38:41.240584 [Byte1]: 55
7880 12:38:41.245172
7881 12:38:41.245251 Set Vref, RX VrefLevel [Byte0]: 56
7882 12:38:41.248316 [Byte1]: 56
7883 12:38:41.253201
7884 12:38:41.253281 Set Vref, RX VrefLevel [Byte0]: 57
7885 12:38:41.256175 [Byte1]: 57
7886 12:38:41.260584
7887 12:38:41.260703 Set Vref, RX VrefLevel [Byte0]: 58
7888 12:38:41.263468 [Byte1]: 58
7889 12:38:41.268132
7890 12:38:41.268231 Set Vref, RX VrefLevel [Byte0]: 59
7891 12:38:41.271404 [Byte1]: 59
7892 12:38:41.275446
7893 12:38:41.275520 Set Vref, RX VrefLevel [Byte0]: 60
7894 12:38:41.279194 [Byte1]: 60
7895 12:38:41.283018
7896 12:38:41.283094 Set Vref, RX VrefLevel [Byte0]: 61
7897 12:38:41.286591 [Byte1]: 61
7898 12:38:41.290921
7899 12:38:41.291018 Set Vref, RX VrefLevel [Byte0]: 62
7900 12:38:41.294535 [Byte1]: 62
7901 12:38:41.298278
7902 12:38:41.298375 Set Vref, RX VrefLevel [Byte0]: 63
7903 12:38:41.301807 [Byte1]: 63
7904 12:38:41.305812
7905 12:38:41.305910 Set Vref, RX VrefLevel [Byte0]: 64
7906 12:38:41.309132 [Byte1]: 64
7907 12:38:41.313659
7908 12:38:41.313758 Set Vref, RX VrefLevel [Byte0]: 65
7909 12:38:41.317217 [Byte1]: 65
7910 12:38:41.321460
7911 12:38:41.321555 Set Vref, RX VrefLevel [Byte0]: 66
7912 12:38:41.324855 [Byte1]: 66
7913 12:38:41.329013
7914 12:38:41.329093 Set Vref, RX VrefLevel [Byte0]: 67
7915 12:38:41.332170 [Byte1]: 67
7916 12:38:41.336468
7917 12:38:41.336548 Set Vref, RX VrefLevel [Byte0]: 68
7918 12:38:41.339527 [Byte1]: 68
7919 12:38:41.344259
7920 12:38:41.344357 Set Vref, RX VrefLevel [Byte0]: 69
7921 12:38:41.347822 [Byte1]: 69
7922 12:38:41.351670
7923 12:38:41.351750 Set Vref, RX VrefLevel [Byte0]: 70
7924 12:38:41.355327 [Byte1]: 70
7925 12:38:41.359096
7926 12:38:41.359203 Set Vref, RX VrefLevel [Byte0]: 71
7927 12:38:41.362655 [Byte1]: 71
7928 12:38:41.366777
7929 12:38:41.366858 Set Vref, RX VrefLevel [Byte0]: 72
7930 12:38:41.370345 [Byte1]: 72
7931 12:38:41.374448
7932 12:38:41.374556 Set Vref, RX VrefLevel [Byte0]: 73
7933 12:38:41.377635 [Byte1]: 73
7934 12:38:41.382532
7935 12:38:41.382629 Set Vref, RX VrefLevel [Byte0]: 74
7936 12:38:41.385551 [Byte1]: 74
7937 12:38:41.390004
7938 12:38:41.390084 Set Vref, RX VrefLevel [Byte0]: 75
7939 12:38:41.393026 [Byte1]: 75
7940 12:38:41.397675
7941 12:38:41.397756 Set Vref, RX VrefLevel [Byte0]: 76
7942 12:38:41.400817 [Byte1]: 76
7943 12:38:41.405029
7944 12:38:41.405126 Set Vref, RX VrefLevel [Byte0]: 77
7945 12:38:41.408662 [Byte1]: 77
7946 12:38:41.412741
7947 12:38:41.412821 Final RX Vref Byte 0 = 55 to rank0
7948 12:38:41.416144 Final RX Vref Byte 1 = 60 to rank0
7949 12:38:41.419511 Final RX Vref Byte 0 = 55 to rank1
7950 12:38:41.422311 Final RX Vref Byte 1 = 60 to rank1==
7951 12:38:41.425593 Dram Type= 6, Freq= 0, CH_0, rank 0
7952 12:38:41.432337 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7953 12:38:41.432418 ==
7954 12:38:41.432497 DQS Delay:
7955 12:38:41.432630 DQS0 = 0, DQS1 = 0
7956 12:38:41.436196 DQM Delay:
7957 12:38:41.436301 DQM0 = 129, DQM1 = 121
7958 12:38:41.439579 DQ Delay:
7959 12:38:41.442721 DQ0 =130, DQ1 =132, DQ2 =124, DQ3 =126
7960 12:38:41.446025 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =138
7961 12:38:41.449124 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
7962 12:38:41.452602 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
7963 12:38:41.452708
7964 12:38:41.452803
7965 12:38:41.452887
7966 12:38:41.456270 [DramC_TX_OE_Calibration] TA2
7967 12:38:41.458969 Original DQ_B0 (3 6) =30, OEN = 27
7968 12:38:41.462771 Original DQ_B1 (3 6) =30, OEN = 27
7969 12:38:41.465829 24, 0x0, End_B0=24 End_B1=24
7970 12:38:41.465910 25, 0x0, End_B0=25 End_B1=25
7971 12:38:41.469090 26, 0x0, End_B0=26 End_B1=26
7972 12:38:41.472715 27, 0x0, End_B0=27 End_B1=27
7973 12:38:41.475881 28, 0x0, End_B0=28 End_B1=28
7974 12:38:41.475962 29, 0x0, End_B0=29 End_B1=29
7975 12:38:41.479417 30, 0x0, End_B0=30 End_B1=30
7976 12:38:41.482529 31, 0x4545, End_B0=30 End_B1=30
7977 12:38:41.485924 Byte0 end_step=30 best_step=27
7978 12:38:41.489757 Byte1 end_step=30 best_step=27
7979 12:38:41.492701 Byte0 TX OE(2T, 0.5T) = (3, 3)
7980 12:38:41.492781 Byte1 TX OE(2T, 0.5T) = (3, 3)
7981 12:38:41.492845
7982 12:38:41.495661
7983 12:38:41.502599 [DQSOSCAuto] RK0, (LSB)MR18= 0x1509, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
7984 12:38:41.505633 CH0 RK0: MR19=303, MR18=1509
7985 12:38:41.512534 CH0_RK0: MR19=0x303, MR18=0x1509, DQSOSC=399, MR23=63, INC=23, DEC=15
7986 12:38:41.512622
7987 12:38:41.516135 ----->DramcWriteLeveling(PI) begin...
7988 12:38:41.516217 ==
7989 12:38:41.519436 Dram Type= 6, Freq= 0, CH_0, rank 1
7990 12:38:41.522706 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7991 12:38:41.522788 ==
7992 12:38:41.525608 Write leveling (Byte 0): 32 => 32
7993 12:38:41.529084 Write leveling (Byte 1): 27 => 27
7994 12:38:41.532431 DramcWriteLeveling(PI) end<-----
7995 12:38:41.532512
7996 12:38:41.532582 ==
7997 12:38:41.535528 Dram Type= 6, Freq= 0, CH_0, rank 1
7998 12:38:41.539258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7999 12:38:41.539339 ==
8000 12:38:41.542800 [Gating] SW mode calibration
8001 12:38:41.549738 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8002 12:38:41.556017 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8003 12:38:41.559783 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 12:38:41.562632 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 12:38:41.569140 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8006 12:38:41.572927 1 4 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8007 12:38:41.575815 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8008 12:38:41.582668 1 4 20 | B1->B0 | 2928 3434 | 1 1 | (0 0) (1 1)
8009 12:38:41.586278 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8010 12:38:41.589581 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8011 12:38:41.593210 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8012 12:38:41.599747 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8013 12:38:41.602390 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8014 12:38:41.606421 1 5 12 | B1->B0 | 3434 2727 | 1 1 | (1 1) (1 0)
8015 12:38:41.612390 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8016 12:38:41.615811 1 5 20 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
8017 12:38:41.619580 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8018 12:38:41.625938 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 12:38:41.628979 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 12:38:41.632623 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 12:38:41.639070 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8022 12:38:41.642594 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8023 12:38:41.645680 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8024 12:38:41.652525 1 6 20 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
8025 12:38:41.655880 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8026 12:38:41.659382 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8027 12:38:41.665877 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8028 12:38:41.669571 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8029 12:38:41.672123 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8030 12:38:41.678842 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8031 12:38:41.682279 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8032 12:38:41.685911 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8033 12:38:41.692242 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 12:38:41.695628 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 12:38:41.698835 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 12:38:41.705704 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 12:38:41.708993 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 12:38:41.712548 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 12:38:41.718728 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 12:38:41.722412 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 12:38:41.725302 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 12:38:41.728598 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 12:38:41.735409 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 12:38:41.738761 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8045 12:38:41.742319 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8046 12:38:41.748607 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8047 12:38:41.752482 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8048 12:38:41.755611 Total UI for P1: 0, mck2ui 16
8049 12:38:41.759324 best dqsien dly found for B0: ( 1, 9, 8)
8050 12:38:41.762466 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8051 12:38:41.769563 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8052 12:38:41.769642 Total UI for P1: 0, mck2ui 16
8053 12:38:41.775723 best dqsien dly found for B1: ( 1, 9, 20)
8054 12:38:41.779078 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8055 12:38:41.782493 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8056 12:38:41.782567
8057 12:38:41.785735 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8058 12:38:41.789259 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8059 12:38:41.792521 [Gating] SW calibration Done
8060 12:38:41.792596 ==
8061 12:38:41.795545 Dram Type= 6, Freq= 0, CH_0, rank 1
8062 12:38:41.798896 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8063 12:38:41.798972 ==
8064 12:38:41.802244 RX Vref Scan: 0
8065 12:38:41.802330
8066 12:38:41.802391 RX Vref 0 -> 0, step: 1
8067 12:38:41.802476
8068 12:38:41.805820 RX Delay 0 -> 252, step: 8
8069 12:38:41.809396 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8070 12:38:41.812505 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8071 12:38:41.818840 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8072 12:38:41.822449 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8073 12:38:41.825612 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8074 12:38:41.828745 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8075 12:38:41.832527 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8076 12:38:41.838685 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8077 12:38:41.842178 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8078 12:38:41.845600 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8079 12:38:41.848871 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8080 12:38:41.852442 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8081 12:38:41.859254 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8082 12:38:41.862291 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8083 12:38:41.865329 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8084 12:38:41.869080 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8085 12:38:41.869160 ==
8086 12:38:41.872319 Dram Type= 6, Freq= 0, CH_0, rank 1
8087 12:38:41.878636 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8088 12:38:41.878717 ==
8089 12:38:41.878781 DQS Delay:
8090 12:38:41.882208 DQS0 = 0, DQS1 = 0
8091 12:38:41.882288 DQM Delay:
8092 12:38:41.885414 DQM0 = 130, DQM1 = 125
8093 12:38:41.885494 DQ Delay:
8094 12:38:41.888708 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =131
8095 12:38:41.892042 DQ4 =131, DQ5 =115, DQ6 =139, DQ7 =139
8096 12:38:41.895204 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8097 12:38:41.898926 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8098 12:38:41.899007
8099 12:38:41.899070
8100 12:38:41.899128 ==
8101 12:38:41.902122 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 12:38:41.908540 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 12:38:41.908621 ==
8104 12:38:41.908686
8105 12:38:41.908745
8106 12:38:41.908801 TX Vref Scan disable
8107 12:38:41.912031 == TX Byte 0 ==
8108 12:38:41.915115 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8109 12:38:41.918718 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8110 12:38:41.922024 == TX Byte 1 ==
8111 12:38:41.925563 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8112 12:38:41.928815 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8113 12:38:41.932036 ==
8114 12:38:41.935075 Dram Type= 6, Freq= 0, CH_0, rank 1
8115 12:38:41.938734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8116 12:38:41.938810 ==
8117 12:38:41.952605
8118 12:38:41.955495 TX Vref early break, caculate TX vref
8119 12:38:41.959707 TX Vref=16, minBit 0, minWin=22, winSum=367
8120 12:38:41.962622 TX Vref=18, minBit 1, minWin=22, winSum=380
8121 12:38:41.965694 TX Vref=20, minBit 0, minWin=23, winSum=384
8122 12:38:41.969355 TX Vref=22, minBit 1, minWin=23, winSum=396
8123 12:38:41.972592 TX Vref=24, minBit 0, minWin=23, winSum=398
8124 12:38:41.979369 TX Vref=26, minBit 0, minWin=25, winSum=412
8125 12:38:41.982420 TX Vref=28, minBit 1, minWin=25, winSum=418
8126 12:38:41.985455 TX Vref=30, minBit 1, minWin=25, winSum=415
8127 12:38:41.989109 TX Vref=32, minBit 0, minWin=25, winSum=409
8128 12:38:41.992346 TX Vref=34, minBit 0, minWin=24, winSum=400
8129 12:38:41.996120 TX Vref=36, minBit 0, minWin=23, winSum=389
8130 12:38:42.002958 [TxChooseVref] Worse bit 1, Min win 25, Win sum 418, Final Vref 28
8131 12:38:42.003039
8132 12:38:42.005944 Final TX Range 0 Vref 28
8133 12:38:42.006049
8134 12:38:42.006143 ==
8135 12:38:42.009213 Dram Type= 6, Freq= 0, CH_0, rank 1
8136 12:38:42.012474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8137 12:38:42.012556 ==
8138 12:38:42.012653
8139 12:38:42.012712
8140 12:38:42.015654 TX Vref Scan disable
8141 12:38:42.022555 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8142 12:38:42.022636 == TX Byte 0 ==
8143 12:38:42.026020 u2DelayCellOfst[0]=14 cells (4 PI)
8144 12:38:42.029120 u2DelayCellOfst[1]=21 cells (6 PI)
8145 12:38:42.032442 u2DelayCellOfst[2]=10 cells (3 PI)
8146 12:38:42.035951 u2DelayCellOfst[3]=14 cells (4 PI)
8147 12:38:42.039828 u2DelayCellOfst[4]=10 cells (3 PI)
8148 12:38:42.042273 u2DelayCellOfst[5]=0 cells (0 PI)
8149 12:38:42.045830 u2DelayCellOfst[6]=17 cells (5 PI)
8150 12:38:42.049390 u2DelayCellOfst[7]=17 cells (5 PI)
8151 12:38:42.052263 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8152 12:38:42.056028 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8153 12:38:42.058997 == TX Byte 1 ==
8154 12:38:42.062569 u2DelayCellOfst[8]=0 cells (0 PI)
8155 12:38:42.062650 u2DelayCellOfst[9]=0 cells (0 PI)
8156 12:38:42.066067 u2DelayCellOfst[10]=7 cells (2 PI)
8157 12:38:42.069205 u2DelayCellOfst[11]=0 cells (0 PI)
8158 12:38:42.072088 u2DelayCellOfst[12]=10 cells (3 PI)
8159 12:38:42.075716 u2DelayCellOfst[13]=10 cells (3 PI)
8160 12:38:42.079550 u2DelayCellOfst[14]=14 cells (4 PI)
8161 12:38:42.082763 u2DelayCellOfst[15]=10 cells (3 PI)
8162 12:38:42.085921 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8163 12:38:42.092623 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8164 12:38:42.092704 DramC Write-DBI on
8165 12:38:42.092767 ==
8166 12:38:42.096095 Dram Type= 6, Freq= 0, CH_0, rank 1
8167 12:38:42.099354 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8168 12:38:42.102436 ==
8169 12:38:42.102531
8170 12:38:42.102594
8171 12:38:42.102653 TX Vref Scan disable
8172 12:38:42.106116 == TX Byte 0 ==
8173 12:38:42.109209 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8174 12:38:42.112836 == TX Byte 1 ==
8175 12:38:42.115968 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8176 12:38:42.116049 DramC Write-DBI off
8177 12:38:42.119467
8178 12:38:42.119548 [DATLAT]
8179 12:38:42.119613 Freq=1600, CH0 RK1
8180 12:38:42.119675
8181 12:38:42.122650 DATLAT Default: 0xf
8182 12:38:42.122730 0, 0xFFFF, sum = 0
8183 12:38:42.125917 1, 0xFFFF, sum = 0
8184 12:38:42.126025 2, 0xFFFF, sum = 0
8185 12:38:42.129243 3, 0xFFFF, sum = 0
8186 12:38:42.129322 4, 0xFFFF, sum = 0
8187 12:38:42.132377 5, 0xFFFF, sum = 0
8188 12:38:42.135899 6, 0xFFFF, sum = 0
8189 12:38:42.135995 7, 0xFFFF, sum = 0
8190 12:38:42.139417 8, 0xFFFF, sum = 0
8191 12:38:42.139491 9, 0xFFFF, sum = 0
8192 12:38:42.143110 10, 0xFFFF, sum = 0
8193 12:38:42.143192 11, 0xFFFF, sum = 0
8194 12:38:42.146084 12, 0xFFFF, sum = 0
8195 12:38:42.146165 13, 0xFFFF, sum = 0
8196 12:38:42.149240 14, 0x0, sum = 1
8197 12:38:42.149321 15, 0x0, sum = 2
8198 12:38:42.152501 16, 0x0, sum = 3
8199 12:38:42.152583 17, 0x0, sum = 4
8200 12:38:42.155768 best_step = 15
8201 12:38:42.155848
8202 12:38:42.155929 ==
8203 12:38:42.159162 Dram Type= 6, Freq= 0, CH_0, rank 1
8204 12:38:42.162964 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8205 12:38:42.163046 ==
8206 12:38:42.163110 RX Vref Scan: 0
8207 12:38:42.163169
8208 12:38:42.166836 RX Vref 0 -> 0, step: 1
8209 12:38:42.166916
8210 12:38:42.169339 RX Delay 11 -> 252, step: 4
8211 12:38:42.172886 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8212 12:38:42.179253 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8213 12:38:42.182436 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8214 12:38:42.186101 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8215 12:38:42.189154 iDelay=191, Bit 4, Center 126 (75 ~ 178) 104
8216 12:38:42.192579 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8217 12:38:42.196192 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8218 12:38:42.202580 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8219 12:38:42.206485 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
8220 12:38:42.209321 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8221 12:38:42.212862 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8222 12:38:42.216107 iDelay=191, Bit 11, Center 116 (67 ~ 166) 100
8223 12:38:42.222914 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8224 12:38:42.226087 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8225 12:38:42.229201 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8226 12:38:42.233018 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8227 12:38:42.233098 ==
8228 12:38:42.235780 Dram Type= 6, Freq= 0, CH_0, rank 1
8229 12:38:42.242383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8230 12:38:42.242505 ==
8231 12:38:42.242587 DQS Delay:
8232 12:38:42.246321 DQS0 = 0, DQS1 = 0
8233 12:38:42.246425 DQM Delay:
8234 12:38:42.246504 DQM0 = 127, DQM1 = 123
8235 12:38:42.250208 DQ Delay:
8236 12:38:42.252552 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8237 12:38:42.256541 DQ4 =126, DQ5 =114, DQ6 =136, DQ7 =136
8238 12:38:42.259315 DQ8 =114, DQ9 =110, DQ10 =122, DQ11 =116
8239 12:38:42.262836 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =132
8240 12:38:42.262916
8241 12:38:42.262980
8242 12:38:42.263039
8243 12:38:42.265957 [DramC_TX_OE_Calibration] TA2
8244 12:38:42.269248 Original DQ_B0 (3 6) =30, OEN = 27
8245 12:38:42.272634 Original DQ_B1 (3 6) =30, OEN = 27
8246 12:38:42.276155 24, 0x0, End_B0=24 End_B1=24
8247 12:38:42.276237 25, 0x0, End_B0=25 End_B1=25
8248 12:38:42.279486 26, 0x0, End_B0=26 End_B1=26
8249 12:38:42.282560 27, 0x0, End_B0=27 End_B1=27
8250 12:38:42.285934 28, 0x0, End_B0=28 End_B1=28
8251 12:38:42.289479 29, 0x0, End_B0=29 End_B1=29
8252 12:38:42.289591 30, 0x0, End_B0=30 End_B1=30
8253 12:38:42.292866 31, 0x4141, End_B0=30 End_B1=30
8254 12:38:42.295924 Byte0 end_step=30 best_step=27
8255 12:38:42.299700 Byte1 end_step=30 best_step=27
8256 12:38:42.302705 Byte0 TX OE(2T, 0.5T) = (3, 3)
8257 12:38:42.302786 Byte1 TX OE(2T, 0.5T) = (3, 3)
8258 12:38:42.306331
8259 12:38:42.306421
8260 12:38:42.312604 [DQSOSCAuto] RK1, (LSB)MR18= 0x190e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8261 12:38:42.316397 CH0 RK1: MR19=303, MR18=190E
8262 12:38:42.322542 CH0_RK1: MR19=0x303, MR18=0x190E, DQSOSC=397, MR23=63, INC=23, DEC=15
8263 12:38:42.326654 [RxdqsGatingPostProcess] freq 1600
8264 12:38:42.329360 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8265 12:38:42.332904 best DQS0 dly(2T, 0.5T) = (1, 1)
8266 12:38:42.335880 best DQS1 dly(2T, 0.5T) = (1, 1)
8267 12:38:42.339503 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8268 12:38:42.342775 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8269 12:38:42.346415 best DQS0 dly(2T, 0.5T) = (1, 1)
8270 12:38:42.349404 best DQS1 dly(2T, 0.5T) = (1, 1)
8271 12:38:42.352568 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8272 12:38:42.355857 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8273 12:38:42.359461 Pre-setting of DQS Precalculation
8274 12:38:42.362550 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8275 12:38:42.362642 ==
8276 12:38:42.365916 Dram Type= 6, Freq= 0, CH_1, rank 0
8277 12:38:42.369109 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8278 12:38:42.369191 ==
8279 12:38:42.375847 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8280 12:38:42.379380 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8281 12:38:42.385870 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8282 12:38:42.389260 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8283 12:38:42.398970 [CA 0] Center 44 (15~73) winsize 59
8284 12:38:42.402777 [CA 1] Center 44 (15~73) winsize 59
8285 12:38:42.405864 [CA 2] Center 38 (10~67) winsize 58
8286 12:38:42.409059 [CA 3] Center 37 (8~67) winsize 60
8287 12:38:42.412237 [CA 4] Center 38 (9~68) winsize 60
8288 12:38:42.415700 [CA 5] Center 38 (9~67) winsize 59
8289 12:38:42.415807
8290 12:38:42.419185 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8291 12:38:42.419267
8292 12:38:42.422317 [CATrainingPosCal] consider 1 rank data
8293 12:38:42.426038 u2DelayCellTimex100 = 275/100 ps
8294 12:38:42.429143 CA0 delay=44 (15~73),Diff = 7 PI (24 cell)
8295 12:38:42.435932 CA1 delay=44 (15~73),Diff = 7 PI (24 cell)
8296 12:38:42.439167 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8297 12:38:42.442681 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8298 12:38:42.446157 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8299 12:38:42.449341 CA5 delay=38 (9~67),Diff = 1 PI (3 cell)
8300 12:38:42.449420
8301 12:38:42.452313 CA PerBit enable=1, Macro0, CA PI delay=37
8302 12:38:42.452393
8303 12:38:42.455808 [CBTSetCACLKResult] CA Dly = 37
8304 12:38:42.458923 CS Dly: 9 (0~40)
8305 12:38:42.462586 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8306 12:38:42.465684 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8307 12:38:42.465765 ==
8308 12:38:42.468779 Dram Type= 6, Freq= 0, CH_1, rank 1
8309 12:38:42.472688 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8310 12:38:42.472769 ==
8311 12:38:42.479144 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8312 12:38:42.482629 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8313 12:38:42.488874 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8314 12:38:42.492861 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8315 12:38:42.502452 [CA 0] Center 43 (14~72) winsize 59
8316 12:38:42.505298 [CA 1] Center 43 (14~72) winsize 59
8317 12:38:42.508868 [CA 2] Center 38 (9~67) winsize 59
8318 12:38:42.512227 [CA 3] Center 37 (8~67) winsize 60
8319 12:38:42.515412 [CA 4] Center 38 (9~68) winsize 60
8320 12:38:42.519275 [CA 5] Center 37 (8~66) winsize 59
8321 12:38:42.519355
8322 12:38:42.522348 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8323 12:38:42.522449
8324 12:38:42.525747 [CATrainingPosCal] consider 2 rank data
8325 12:38:42.529055 u2DelayCellTimex100 = 275/100 ps
8326 12:38:42.532121 CA0 delay=43 (15~72),Diff = 6 PI (21 cell)
8327 12:38:42.539337 CA1 delay=43 (15~72),Diff = 6 PI (21 cell)
8328 12:38:42.542270 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8329 12:38:42.545400 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8330 12:38:42.549140 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8331 12:38:42.552191 CA5 delay=37 (9~66),Diff = 0 PI (0 cell)
8332 12:38:42.552272
8333 12:38:42.555346 CA PerBit enable=1, Macro0, CA PI delay=37
8334 12:38:42.555426
8335 12:38:42.558799 [CBTSetCACLKResult] CA Dly = 37
8336 12:38:42.562709 CS Dly: 11 (0~44)
8337 12:38:42.565724 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8338 12:38:42.569088 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8339 12:38:42.569169
8340 12:38:42.572150 ----->DramcWriteLeveling(PI) begin...
8341 12:38:42.572232 ==
8342 12:38:42.575820 Dram Type= 6, Freq= 0, CH_1, rank 0
8343 12:38:42.579309 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8344 12:38:42.582636 ==
8345 12:38:42.582716 Write leveling (Byte 0): 25 => 25
8346 12:38:42.585859 Write leveling (Byte 1): 27 => 27
8347 12:38:42.588910 DramcWriteLeveling(PI) end<-----
8348 12:38:42.588990
8349 12:38:42.589054 ==
8350 12:38:42.592324 Dram Type= 6, Freq= 0, CH_1, rank 0
8351 12:38:42.598769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8352 12:38:42.598850 ==
8353 12:38:42.598914 [Gating] SW mode calibration
8354 12:38:42.608773 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8355 12:38:42.612546 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8356 12:38:42.615409 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 12:38:42.622007 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 12:38:42.625587 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 12:38:42.628969 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 12:38:42.635272 1 4 16 | B1->B0 | 2929 2323 | 1 0 | (1 1) (0 0)
8361 12:38:42.638941 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8362 12:38:42.642772 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 12:38:42.649319 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 12:38:42.652545 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 12:38:42.655467 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 12:38:42.662507 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 12:38:42.665469 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 12:38:42.669068 1 5 16 | B1->B0 | 2f2f 3333 | 0 0 | (0 1) (0 1)
8369 12:38:42.676220 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8370 12:38:42.678922 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 12:38:42.682590 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 12:38:42.689234 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 12:38:42.692441 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 12:38:42.695495 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 12:38:42.698953 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 12:38:42.705942 1 6 16 | B1->B0 | 3737 2d2d | 0 0 | (1 1) (0 0)
8377 12:38:42.708896 1 6 20 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
8378 12:38:42.712666 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 12:38:42.719135 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 12:38:42.722018 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 12:38:42.725544 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 12:38:42.732986 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 12:38:42.735851 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 12:38:42.739304 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8385 12:38:42.745827 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 12:38:42.749018 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 12:38:42.752492 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 12:38:42.759454 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 12:38:42.762204 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 12:38:42.765773 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 12:38:42.772333 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 12:38:42.775942 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 12:38:42.779021 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 12:38:42.785701 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 12:38:42.788748 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 12:38:42.792548 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 12:38:42.795727 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 12:38:42.802018 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 12:38:42.805856 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8400 12:38:42.809110 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8401 12:38:42.815479 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8402 12:38:42.819225 Total UI for P1: 0, mck2ui 16
8403 12:38:42.822581 best dqsien dly found for B0: ( 1, 9, 14)
8404 12:38:42.825465 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 12:38:42.829371 Total UI for P1: 0, mck2ui 16
8406 12:38:42.832240 best dqsien dly found for B1: ( 1, 9, 16)
8407 12:38:42.835435 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8408 12:38:42.839005 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8409 12:38:42.839080
8410 12:38:42.842247 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8411 12:38:42.845598 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8412 12:38:42.849300 [Gating] SW calibration Done
8413 12:38:42.849375 ==
8414 12:38:42.852379 Dram Type= 6, Freq= 0, CH_1, rank 0
8415 12:38:42.855897 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8416 12:38:42.859296 ==
8417 12:38:42.859368 RX Vref Scan: 0
8418 12:38:42.859429
8419 12:38:42.862382 RX Vref 0 -> 0, step: 1
8420 12:38:42.862495
8421 12:38:42.862555 RX Delay 0 -> 252, step: 8
8422 12:38:42.869387 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8423 12:38:42.872798 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8424 12:38:42.875766 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8425 12:38:42.879703 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8426 12:38:42.882559 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8427 12:38:42.889394 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8428 12:38:42.892832 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8429 12:38:42.895602 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8430 12:38:42.899700 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8431 12:38:42.902612 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8432 12:38:42.909233 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8433 12:38:42.912420 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8434 12:38:42.915995 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8435 12:38:42.918793 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8436 12:38:42.922368 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8437 12:38:42.928903 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8438 12:38:42.928978 ==
8439 12:38:42.932383 Dram Type= 6, Freq= 0, CH_1, rank 0
8440 12:38:42.935926 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8441 12:38:42.936002 ==
8442 12:38:42.936065 DQS Delay:
8443 12:38:42.939301 DQS0 = 0, DQS1 = 0
8444 12:38:42.939368 DQM Delay:
8445 12:38:42.942647 DQM0 = 133, DQM1 = 127
8446 12:38:42.942723 DQ Delay:
8447 12:38:42.946171 DQ0 =139, DQ1 =127, DQ2 =119, DQ3 =135
8448 12:38:42.949329 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =127
8449 12:38:42.952518 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8450 12:38:42.955702 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8451 12:38:42.955769
8452 12:38:42.959259
8453 12:38:42.959324 ==
8454 12:38:42.962240 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 12:38:42.965986 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 12:38:42.966058 ==
8457 12:38:42.966119
8458 12:38:42.966179
8459 12:38:42.969048 TX Vref Scan disable
8460 12:38:42.969113 == TX Byte 0 ==
8461 12:38:42.972774 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8462 12:38:42.979088 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8463 12:38:42.979163 == TX Byte 1 ==
8464 12:38:42.982457 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8465 12:38:42.989222 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8466 12:38:42.989298 ==
8467 12:38:42.992262 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 12:38:42.995574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 12:38:42.995650 ==
8470 12:38:43.009739
8471 12:38:43.012895 TX Vref early break, caculate TX vref
8472 12:38:43.016603 TX Vref=16, minBit 8, minWin=21, winSum=367
8473 12:38:43.019739 TX Vref=18, minBit 8, minWin=21, winSum=375
8474 12:38:43.023561 TX Vref=20, minBit 0, minWin=22, winSum=385
8475 12:38:43.026466 TX Vref=22, minBit 5, minWin=23, winSum=391
8476 12:38:43.030186 TX Vref=24, minBit 5, minWin=23, winSum=401
8477 12:38:43.036609 TX Vref=26, minBit 6, minWin=25, winSum=414
8478 12:38:43.039922 TX Vref=28, minBit 8, minWin=25, winSum=419
8479 12:38:43.043755 TX Vref=30, minBit 0, minWin=25, winSum=418
8480 12:38:43.046714 TX Vref=32, minBit 0, minWin=25, winSum=414
8481 12:38:43.050215 TX Vref=34, minBit 8, minWin=24, winSum=402
8482 12:38:43.053387 TX Vref=36, minBit 11, minWin=23, winSum=394
8483 12:38:43.059863 [TxChooseVref] Worse bit 8, Min win 25, Win sum 419, Final Vref 28
8484 12:38:43.059945
8485 12:38:43.063178 Final TX Range 0 Vref 28
8486 12:38:43.063251
8487 12:38:43.063313 ==
8488 12:38:43.066248 Dram Type= 6, Freq= 0, CH_1, rank 0
8489 12:38:43.069952 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8490 12:38:43.070022 ==
8491 12:38:43.070087
8492 12:38:43.070146
8493 12:38:43.073481 TX Vref Scan disable
8494 12:38:43.079734 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8495 12:38:43.079808 == TX Byte 0 ==
8496 12:38:43.083197 u2DelayCellOfst[0]=17 cells (5 PI)
8497 12:38:43.085983 u2DelayCellOfst[1]=10 cells (3 PI)
8498 12:38:43.089922 u2DelayCellOfst[2]=0 cells (0 PI)
8499 12:38:43.093081 u2DelayCellOfst[3]=7 cells (2 PI)
8500 12:38:43.096220 u2DelayCellOfst[4]=10 cells (3 PI)
8501 12:38:43.099776 u2DelayCellOfst[5]=17 cells (5 PI)
8502 12:38:43.102782 u2DelayCellOfst[6]=17 cells (5 PI)
8503 12:38:43.105953 u2DelayCellOfst[7]=3 cells (1 PI)
8504 12:38:43.109374 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8505 12:38:43.112601 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8506 12:38:43.116230 == TX Byte 1 ==
8507 12:38:43.119237 u2DelayCellOfst[8]=0 cells (0 PI)
8508 12:38:43.122366 u2DelayCellOfst[9]=10 cells (3 PI)
8509 12:38:43.122511 u2DelayCellOfst[10]=14 cells (4 PI)
8510 12:38:43.125870 u2DelayCellOfst[11]=10 cells (3 PI)
8511 12:38:43.129171 u2DelayCellOfst[12]=17 cells (5 PI)
8512 12:38:43.132777 u2DelayCellOfst[13]=17 cells (5 PI)
8513 12:38:43.135911 u2DelayCellOfst[14]=21 cells (6 PI)
8514 12:38:43.139448 u2DelayCellOfst[15]=21 cells (6 PI)
8515 12:38:43.145859 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8516 12:38:43.149346 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8517 12:38:43.149424 DramC Write-DBI on
8518 12:38:43.149487 ==
8519 12:38:43.152613 Dram Type= 6, Freq= 0, CH_1, rank 0
8520 12:38:43.158999 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8521 12:38:43.159075 ==
8522 12:38:43.159139
8523 12:38:43.159206
8524 12:38:43.159267 TX Vref Scan disable
8525 12:38:43.163704 == TX Byte 0 ==
8526 12:38:43.166539 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8527 12:38:43.170212 == TX Byte 1 ==
8528 12:38:43.173070 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8529 12:38:43.173141 DramC Write-DBI off
8530 12:38:43.176824
8531 12:38:43.176891 [DATLAT]
8532 12:38:43.176949 Freq=1600, CH1 RK0
8533 12:38:43.177011
8534 12:38:43.179847 DATLAT Default: 0xf
8535 12:38:43.179923 0, 0xFFFF, sum = 0
8536 12:38:43.183074 1, 0xFFFF, sum = 0
8537 12:38:43.183150 2, 0xFFFF, sum = 0
8538 12:38:43.186754 3, 0xFFFF, sum = 0
8539 12:38:43.189936 4, 0xFFFF, sum = 0
8540 12:38:43.190012 5, 0xFFFF, sum = 0
8541 12:38:43.193110 6, 0xFFFF, sum = 0
8542 12:38:43.193215 7, 0xFFFF, sum = 0
8543 12:38:43.196752 8, 0xFFFF, sum = 0
8544 12:38:43.196833 9, 0xFFFF, sum = 0
8545 12:38:43.199753 10, 0xFFFF, sum = 0
8546 12:38:43.199838 11, 0xFFFF, sum = 0
8547 12:38:43.203222 12, 0xFFFF, sum = 0
8548 12:38:43.203387 13, 0xFFFF, sum = 0
8549 12:38:43.206447 14, 0x0, sum = 1
8550 12:38:43.206555 15, 0x0, sum = 2
8551 12:38:43.209949 16, 0x0, sum = 3
8552 12:38:43.210052 17, 0x0, sum = 4
8553 12:38:43.213460 best_step = 15
8554 12:38:43.213531
8555 12:38:43.213592 ==
8556 12:38:43.216953 Dram Type= 6, Freq= 0, CH_1, rank 0
8557 12:38:43.220269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8558 12:38:43.220348 ==
8559 12:38:43.220411 RX Vref Scan: 1
8560 12:38:43.220470
8561 12:38:43.223099 Set Vref Range= 24 -> 127
8562 12:38:43.223166
8563 12:38:43.226346 RX Vref 24 -> 127, step: 1
8564 12:38:43.226488
8565 12:38:43.230106 RX Delay 19 -> 252, step: 4
8566 12:38:43.230215
8567 12:38:43.233083 Set Vref, RX VrefLevel [Byte0]: 24
8568 12:38:43.236633 [Byte1]: 24
8569 12:38:43.236720
8570 12:38:43.239954 Set Vref, RX VrefLevel [Byte0]: 25
8571 12:38:43.243203 [Byte1]: 25
8572 12:38:43.243278
8573 12:38:43.246954 Set Vref, RX VrefLevel [Byte0]: 26
8574 12:38:43.249947 [Byte1]: 26
8575 12:38:43.253479
8576 12:38:43.253636 Set Vref, RX VrefLevel [Byte0]: 27
8577 12:38:43.257111 [Byte1]: 27
8578 12:38:43.260976
8579 12:38:43.261056 Set Vref, RX VrefLevel [Byte0]: 28
8580 12:38:43.264675 [Byte1]: 28
8581 12:38:43.268553
8582 12:38:43.268626 Set Vref, RX VrefLevel [Byte0]: 29
8583 12:38:43.272108 [Byte1]: 29
8584 12:38:43.276416
8585 12:38:43.276489 Set Vref, RX VrefLevel [Byte0]: 30
8586 12:38:43.279447 [Byte1]: 30
8587 12:38:43.283729
8588 12:38:43.283802 Set Vref, RX VrefLevel [Byte0]: 31
8589 12:38:43.287120 [Byte1]: 31
8590 12:38:43.291432
8591 12:38:43.291502 Set Vref, RX VrefLevel [Byte0]: 32
8592 12:38:43.294665 [Byte1]: 32
8593 12:38:43.299332
8594 12:38:43.299414 Set Vref, RX VrefLevel [Byte0]: 33
8595 12:38:43.302242 [Byte1]: 33
8596 12:38:43.306658
8597 12:38:43.306725 Set Vref, RX VrefLevel [Byte0]: 34
8598 12:38:43.310115 [Byte1]: 34
8599 12:38:43.314265
8600 12:38:43.314336 Set Vref, RX VrefLevel [Byte0]: 35
8601 12:38:43.317491 [Byte1]: 35
8602 12:38:43.321719
8603 12:38:43.321791 Set Vref, RX VrefLevel [Byte0]: 36
8604 12:38:43.325123 [Byte1]: 36
8605 12:38:43.329454
8606 12:38:43.329528 Set Vref, RX VrefLevel [Byte0]: 37
8607 12:38:43.332621 [Byte1]: 37
8608 12:38:43.336863
8609 12:38:43.336935 Set Vref, RX VrefLevel [Byte0]: 38
8610 12:38:43.340004 [Byte1]: 38
8611 12:38:43.344506
8612 12:38:43.344583 Set Vref, RX VrefLevel [Byte0]: 39
8613 12:38:43.347861 [Byte1]: 39
8614 12:38:43.352051
8615 12:38:43.352130 Set Vref, RX VrefLevel [Byte0]: 40
8616 12:38:43.355315 [Byte1]: 40
8617 12:38:43.359593
8618 12:38:43.359666 Set Vref, RX VrefLevel [Byte0]: 41
8619 12:38:43.362923 [Byte1]: 41
8620 12:38:43.367066
8621 12:38:43.367157 Set Vref, RX VrefLevel [Byte0]: 42
8622 12:38:43.370496 [Byte1]: 42
8623 12:38:43.374613
8624 12:38:43.374688 Set Vref, RX VrefLevel [Byte0]: 43
8625 12:38:43.378248 [Byte1]: 43
8626 12:38:43.382152
8627 12:38:43.382227 Set Vref, RX VrefLevel [Byte0]: 44
8628 12:38:43.385421 [Byte1]: 44
8629 12:38:43.389646
8630 12:38:43.389716 Set Vref, RX VrefLevel [Byte0]: 45
8631 12:38:43.393130 [Byte1]: 45
8632 12:38:43.397610
8633 12:38:43.397720 Set Vref, RX VrefLevel [Byte0]: 46
8634 12:38:43.401071 [Byte1]: 46
8635 12:38:43.405310
8636 12:38:43.405399 Set Vref, RX VrefLevel [Byte0]: 47
8637 12:38:43.408298 [Byte1]: 47
8638 12:38:43.412764
8639 12:38:43.412844 Set Vref, RX VrefLevel [Byte0]: 48
8640 12:38:43.416072 [Byte1]: 48
8641 12:38:43.420012
8642 12:38:43.420084 Set Vref, RX VrefLevel [Byte0]: 49
8643 12:38:43.423803 [Byte1]: 49
8644 12:38:43.427658
8645 12:38:43.427736 Set Vref, RX VrefLevel [Byte0]: 50
8646 12:38:43.430857 [Byte1]: 50
8647 12:38:43.435559
8648 12:38:43.435634 Set Vref, RX VrefLevel [Byte0]: 51
8649 12:38:43.438269 [Byte1]: 51
8650 12:38:43.442699
8651 12:38:43.442774 Set Vref, RX VrefLevel [Byte0]: 52
8652 12:38:43.446095 [Byte1]: 52
8653 12:38:43.450700
8654 12:38:43.450791 Set Vref, RX VrefLevel [Byte0]: 53
8655 12:38:43.454210 [Byte1]: 53
8656 12:38:43.458656
8657 12:38:43.458746 Set Vref, RX VrefLevel [Byte0]: 54
8658 12:38:43.461281 [Byte1]: 54
8659 12:38:43.465253
8660 12:38:43.465339 Set Vref, RX VrefLevel [Byte0]: 55
8661 12:38:43.468857 [Byte1]: 55
8662 12:38:43.472842
8663 12:38:43.472918 Set Vref, RX VrefLevel [Byte0]: 56
8664 12:38:43.476436 [Byte1]: 56
8665 12:38:43.480684
8666 12:38:43.480757 Set Vref, RX VrefLevel [Byte0]: 57
8667 12:38:43.483830 [Byte1]: 57
8668 12:38:43.488205
8669 12:38:43.488285 Set Vref, RX VrefLevel [Byte0]: 58
8670 12:38:43.491453 [Byte1]: 58
8671 12:38:43.495800
8672 12:38:43.495881 Set Vref, RX VrefLevel [Byte0]: 59
8673 12:38:43.498981 [Byte1]: 59
8674 12:38:43.503450
8675 12:38:43.503530 Set Vref, RX VrefLevel [Byte0]: 60
8676 12:38:43.507245 [Byte1]: 60
8677 12:38:43.511255
8678 12:38:43.511335 Set Vref, RX VrefLevel [Byte0]: 61
8679 12:38:43.514391 [Byte1]: 61
8680 12:38:43.519066
8681 12:38:43.519146 Set Vref, RX VrefLevel [Byte0]: 62
8682 12:38:43.521920 [Byte1]: 62
8683 12:38:43.526290
8684 12:38:43.526388 Set Vref, RX VrefLevel [Byte0]: 63
8685 12:38:43.529538 [Byte1]: 63
8686 12:38:43.533988
8687 12:38:43.534068 Set Vref, RX VrefLevel [Byte0]: 64
8688 12:38:43.536955 [Byte1]: 64
8689 12:38:43.541222
8690 12:38:43.541302 Set Vref, RX VrefLevel [Byte0]: 65
8691 12:38:43.544548 [Byte1]: 65
8692 12:38:43.549079
8693 12:38:43.549159 Set Vref, RX VrefLevel [Byte0]: 66
8694 12:38:43.552071 [Byte1]: 66
8695 12:38:43.556673
8696 12:38:43.556753 Set Vref, RX VrefLevel [Byte0]: 67
8697 12:38:43.559495 [Byte1]: 67
8698 12:38:43.564504
8699 12:38:43.564585 Set Vref, RX VrefLevel [Byte0]: 68
8700 12:38:43.567715 [Byte1]: 68
8701 12:38:43.571540
8702 12:38:43.571620 Set Vref, RX VrefLevel [Byte0]: 69
8703 12:38:43.575020 [Byte1]: 69
8704 12:38:43.579199
8705 12:38:43.579279 Set Vref, RX VrefLevel [Byte0]: 70
8706 12:38:43.582445 [Byte1]: 70
8707 12:38:43.587130
8708 12:38:43.587210 Set Vref, RX VrefLevel [Byte0]: 71
8709 12:38:43.589833 [Byte1]: 71
8710 12:38:43.593968
8711 12:38:43.594048 Set Vref, RX VrefLevel [Byte0]: 72
8712 12:38:43.597803 [Byte1]: 72
8713 12:38:43.602143
8714 12:38:43.602222 Set Vref, RX VrefLevel [Byte0]: 73
8715 12:38:43.605264 [Byte1]: 73
8716 12:38:43.609335
8717 12:38:43.609415 Set Vref, RX VrefLevel [Byte0]: 74
8718 12:38:43.612548 [Byte1]: 74
8719 12:38:43.617791
8720 12:38:43.617871 Final RX Vref Byte 0 = 62 to rank0
8721 12:38:43.620628 Final RX Vref Byte 1 = 56 to rank0
8722 12:38:43.623726 Final RX Vref Byte 0 = 62 to rank1
8723 12:38:43.627237 Final RX Vref Byte 1 = 56 to rank1==
8724 12:38:43.630409 Dram Type= 6, Freq= 0, CH_1, rank 0
8725 12:38:43.634185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8726 12:38:43.637307 ==
8727 12:38:43.637379 DQS Delay:
8728 12:38:43.637439 DQS0 = 0, DQS1 = 0
8729 12:38:43.640481 DQM Delay:
8730 12:38:43.640547 DQM0 = 131, DQM1 = 124
8731 12:38:43.643773 DQ Delay:
8732 12:38:43.647207 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =130
8733 12:38:43.650224 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8734 12:38:43.653965 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
8735 12:38:43.657070 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8736 12:38:43.657144
8737 12:38:43.657206
8738 12:38:43.657264
8739 12:38:43.660714 [DramC_TX_OE_Calibration] TA2
8740 12:38:43.663710 Original DQ_B0 (3 6) =30, OEN = 27
8741 12:38:43.667177 Original DQ_B1 (3 6) =30, OEN = 27
8742 12:38:43.667258 24, 0x0, End_B0=24 End_B1=24
8743 12:38:43.670999 25, 0x0, End_B0=25 End_B1=25
8744 12:38:43.674199 26, 0x0, End_B0=26 End_B1=26
8745 12:38:43.677225 27, 0x0, End_B0=27 End_B1=27
8746 12:38:43.680267 28, 0x0, End_B0=28 End_B1=28
8747 12:38:43.680349 29, 0x0, End_B0=29 End_B1=29
8748 12:38:43.683661 30, 0x0, End_B0=30 End_B1=30
8749 12:38:43.687148 31, 0x4141, End_B0=30 End_B1=30
8750 12:38:43.690611 Byte0 end_step=30 best_step=27
8751 12:38:43.694025 Byte1 end_step=30 best_step=27
8752 12:38:43.697258 Byte0 TX OE(2T, 0.5T) = (3, 3)
8753 12:38:43.697338 Byte1 TX OE(2T, 0.5T) = (3, 3)
8754 12:38:43.697402
8755 12:38:43.697462
8756 12:38:43.707033 [DQSOSCAuto] RK0, (LSB)MR18= 0x1601, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
8757 12:38:43.710676 CH1 RK0: MR19=303, MR18=1601
8758 12:38:43.714286 CH1_RK0: MR19=0x303, MR18=0x1601, DQSOSC=398, MR23=63, INC=23, DEC=15
8759 12:38:43.717810
8760 12:38:43.720739 ----->DramcWriteLeveling(PI) begin...
8761 12:38:43.720810 ==
8762 12:38:43.723784 Dram Type= 6, Freq= 0, CH_1, rank 1
8763 12:38:43.727326 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8764 12:38:43.727402 ==
8765 12:38:43.730964 Write leveling (Byte 0): 22 => 22
8766 12:38:43.734140 Write leveling (Byte 1): 26 => 26
8767 12:38:43.737065 DramcWriteLeveling(PI) end<-----
8768 12:38:43.737145
8769 12:38:43.737209 ==
8770 12:38:43.740338 Dram Type= 6, Freq= 0, CH_1, rank 1
8771 12:38:43.743589 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8772 12:38:43.743669 ==
8773 12:38:43.747179 [Gating] SW mode calibration
8774 12:38:43.753591 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8775 12:38:43.760284 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8776 12:38:43.763904 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 12:38:43.766981 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 12:38:43.773853 1 4 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8779 12:38:43.777325 1 4 12 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
8780 12:38:43.780377 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 12:38:43.784157 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8782 12:38:43.790321 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8783 12:38:43.794582 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 12:38:43.797553 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 12:38:43.804524 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8786 12:38:43.807846 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
8787 12:38:43.810772 1 5 12 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
8788 12:38:43.817492 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8789 12:38:43.820757 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 12:38:43.824255 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 12:38:43.830545 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 12:38:43.833582 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 12:38:43.836900 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 12:38:43.843860 1 6 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
8795 12:38:43.847122 1 6 12 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
8796 12:38:43.850366 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 12:38:43.857210 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 12:38:43.860164 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 12:38:43.864146 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 12:38:43.870098 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 12:38:43.873723 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8802 12:38:43.876753 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8803 12:38:43.883428 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8804 12:38:43.887075 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8805 12:38:43.890293 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 12:38:43.894043 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 12:38:43.900104 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 12:38:43.904507 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 12:38:43.907024 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 12:38:43.913662 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 12:38:43.917477 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 12:38:43.920169 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 12:38:43.927398 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 12:38:43.930262 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 12:38:43.933461 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 12:38:43.940697 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 12:38:43.943556 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8818 12:38:43.947108 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8819 12:38:43.953538 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8820 12:38:43.953615 Total UI for P1: 0, mck2ui 16
8821 12:38:43.960498 best dqsien dly found for B0: ( 1, 9, 6)
8822 12:38:43.963503 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 12:38:43.966950 Total UI for P1: 0, mck2ui 16
8824 12:38:43.970105 best dqsien dly found for B1: ( 1, 9, 12)
8825 12:38:43.973939 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8826 12:38:43.976944 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8827 12:38:43.977014
8828 12:38:43.980453 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8829 12:38:43.983685 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8830 12:38:43.987096 [Gating] SW calibration Done
8831 12:38:43.987165 ==
8832 12:38:43.990304 Dram Type= 6, Freq= 0, CH_1, rank 1
8833 12:38:43.993825 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8834 12:38:43.993896 ==
8835 12:38:43.997039 RX Vref Scan: 0
8836 12:38:43.997105
8837 12:38:44.000483 RX Vref 0 -> 0, step: 1
8838 12:38:44.000556
8839 12:38:44.000617 RX Delay 0 -> 252, step: 8
8840 12:38:44.006701 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8841 12:38:44.010355 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8842 12:38:44.013742 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8843 12:38:44.016793 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8844 12:38:44.020365 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8845 12:38:44.026692 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8846 12:38:44.030364 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8847 12:38:44.033927 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8848 12:38:44.036993 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8849 12:38:44.040430 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8850 12:38:44.046880 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8851 12:38:44.050335 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8852 12:38:44.053571 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8853 12:38:44.057181 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8854 12:38:44.060710 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8855 12:38:44.067030 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8856 12:38:44.067111 ==
8857 12:38:44.070526 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 12:38:44.073798 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 12:38:44.073879 ==
8860 12:38:44.073944 DQS Delay:
8861 12:38:44.076858 DQS0 = 0, DQS1 = 0
8862 12:38:44.076938 DQM Delay:
8863 12:38:44.080538 DQM0 = 132, DQM1 = 127
8864 12:38:44.080637 DQ Delay:
8865 12:38:44.083668 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8866 12:38:44.086660 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =127
8867 12:38:44.090317 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8868 12:38:44.093914 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8869 12:38:44.093995
8870 12:38:44.094059
8871 12:38:44.096953 ==
8872 12:38:44.097033 Dram Type= 6, Freq= 0, CH_1, rank 1
8873 12:38:44.103580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8874 12:38:44.103661 ==
8875 12:38:44.103725
8876 12:38:44.103785
8877 12:38:44.106691 TX Vref Scan disable
8878 12:38:44.106772 == TX Byte 0 ==
8879 12:38:44.110436 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8880 12:38:44.117129 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8881 12:38:44.117210 == TX Byte 1 ==
8882 12:38:44.120053 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8883 12:38:44.126917 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8884 12:38:44.127025 ==
8885 12:38:44.130365 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 12:38:44.134293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 12:38:44.134423 ==
8888 12:38:44.147752
8889 12:38:44.151176 TX Vref early break, caculate TX vref
8890 12:38:44.154353 TX Vref=16, minBit 8, minWin=22, winSum=379
8891 12:38:44.158332 TX Vref=18, minBit 0, minWin=23, winSum=387
8892 12:38:44.160920 TX Vref=20, minBit 0, minWin=24, winSum=398
8893 12:38:44.164744 TX Vref=22, minBit 8, minWin=24, winSum=405
8894 12:38:44.168713 TX Vref=24, minBit 0, minWin=25, winSum=413
8895 12:38:44.174133 TX Vref=26, minBit 0, minWin=26, winSum=422
8896 12:38:44.177740 TX Vref=28, minBit 0, minWin=25, winSum=427
8897 12:38:44.181149 TX Vref=30, minBit 0, minWin=26, winSum=425
8898 12:38:44.184526 TX Vref=32, minBit 0, minWin=25, winSum=421
8899 12:38:44.188035 TX Vref=34, minBit 0, minWin=24, winSum=406
8900 12:38:44.191126 TX Vref=36, minBit 0, minWin=24, winSum=396
8901 12:38:44.198008 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 30
8902 12:38:44.198089
8903 12:38:44.201315 Final TX Range 0 Vref 30
8904 12:38:44.201396
8905 12:38:44.201460 ==
8906 12:38:44.204461 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 12:38:44.207699 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 12:38:44.207780 ==
8909 12:38:44.207844
8910 12:38:44.207904
8911 12:38:44.211413 TX Vref Scan disable
8912 12:38:44.217475 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8913 12:38:44.217555 == TX Byte 0 ==
8914 12:38:44.221312 u2DelayCellOfst[0]=17 cells (5 PI)
8915 12:38:44.224684 u2DelayCellOfst[1]=10 cells (3 PI)
8916 12:38:44.227584 u2DelayCellOfst[2]=0 cells (0 PI)
8917 12:38:44.231509 u2DelayCellOfst[3]=7 cells (2 PI)
8918 12:38:44.234176 u2DelayCellOfst[4]=7 cells (2 PI)
8919 12:38:44.237875 u2DelayCellOfst[5]=17 cells (5 PI)
8920 12:38:44.240784 u2DelayCellOfst[6]=17 cells (5 PI)
8921 12:38:44.244041 u2DelayCellOfst[7]=7 cells (2 PI)
8922 12:38:44.248253 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8923 12:38:44.251418 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8924 12:38:44.254084 == TX Byte 1 ==
8925 12:38:44.254154 u2DelayCellOfst[8]=0 cells (0 PI)
8926 12:38:44.257815 u2DelayCellOfst[9]=3 cells (1 PI)
8927 12:38:44.261051 u2DelayCellOfst[10]=10 cells (3 PI)
8928 12:38:44.264413 u2DelayCellOfst[11]=3 cells (1 PI)
8929 12:38:44.267762 u2DelayCellOfst[12]=14 cells (4 PI)
8930 12:38:44.270929 u2DelayCellOfst[13]=17 cells (5 PI)
8931 12:38:44.274311 u2DelayCellOfst[14]=17 cells (5 PI)
8932 12:38:44.277237 u2DelayCellOfst[15]=17 cells (5 PI)
8933 12:38:44.280945 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8934 12:38:44.287477 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8935 12:38:44.287584 DramC Write-DBI on
8936 12:38:44.287673 ==
8937 12:38:44.290542 Dram Type= 6, Freq= 0, CH_1, rank 1
8938 12:38:44.294526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8939 12:38:44.297081 ==
8940 12:38:44.297161
8941 12:38:44.297224
8942 12:38:44.297283 TX Vref Scan disable
8943 12:38:44.300751 == TX Byte 0 ==
8944 12:38:44.304362 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8945 12:38:44.307305 == TX Byte 1 ==
8946 12:38:44.310828 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8947 12:38:44.314275 DramC Write-DBI off
8948 12:38:44.314355
8949 12:38:44.314458 [DATLAT]
8950 12:38:44.314520 Freq=1600, CH1 RK1
8951 12:38:44.314579
8952 12:38:44.317710 DATLAT Default: 0xf
8953 12:38:44.317791 0, 0xFFFF, sum = 0
8954 12:38:44.320711 1, 0xFFFF, sum = 0
8955 12:38:44.320793 2, 0xFFFF, sum = 0
8956 12:38:44.323972 3, 0xFFFF, sum = 0
8957 12:38:44.327513 4, 0xFFFF, sum = 0
8958 12:38:44.327595 5, 0xFFFF, sum = 0
8959 12:38:44.330652 6, 0xFFFF, sum = 0
8960 12:38:44.330771 7, 0xFFFF, sum = 0
8961 12:38:44.334612 8, 0xFFFF, sum = 0
8962 12:38:44.334694 9, 0xFFFF, sum = 0
8963 12:38:44.337731 10, 0xFFFF, sum = 0
8964 12:38:44.337812 11, 0xFFFF, sum = 0
8965 12:38:44.341000 12, 0xFFFF, sum = 0
8966 12:38:44.341081 13, 0xFFFF, sum = 0
8967 12:38:44.344432 14, 0x0, sum = 1
8968 12:38:44.344513 15, 0x0, sum = 2
8969 12:38:44.347473 16, 0x0, sum = 3
8970 12:38:44.347579 17, 0x0, sum = 4
8971 12:38:44.350603 best_step = 15
8972 12:38:44.350687
8973 12:38:44.350750 ==
8974 12:38:44.354213 Dram Type= 6, Freq= 0, CH_1, rank 1
8975 12:38:44.357544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8976 12:38:44.357625 ==
8977 12:38:44.357689 RX Vref Scan: 0
8978 12:38:44.360691
8979 12:38:44.360771 RX Vref 0 -> 0, step: 1
8980 12:38:44.360834
8981 12:38:44.363895 RX Delay 11 -> 252, step: 4
8982 12:38:44.367425 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8983 12:38:44.374324 iDelay=191, Bit 1, Center 126 (75 ~ 178) 104
8984 12:38:44.377631 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
8985 12:38:44.381044 iDelay=191, Bit 3, Center 130 (79 ~ 182) 104
8986 12:38:44.384048 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
8987 12:38:44.387543 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
8988 12:38:44.394176 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8989 12:38:44.397251 iDelay=191, Bit 7, Center 126 (75 ~ 178) 104
8990 12:38:44.400531 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
8991 12:38:44.403948 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8992 12:38:44.407848 iDelay=191, Bit 10, Center 126 (71 ~ 182) 112
8993 12:38:44.413986 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8994 12:38:44.417459 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8995 12:38:44.421291 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8996 12:38:44.424399 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8997 12:38:44.427818 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8998 12:38:44.427898 ==
8999 12:38:44.430950 Dram Type= 6, Freq= 0, CH_1, rank 1
9000 12:38:44.437599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9001 12:38:44.437681 ==
9002 12:38:44.437745 DQS Delay:
9003 12:38:44.440777 DQS0 = 0, DQS1 = 0
9004 12:38:44.440857 DQM Delay:
9005 12:38:44.443984 DQM0 = 130, DQM1 = 126
9006 12:38:44.444064 DQ Delay:
9007 12:38:44.447269 DQ0 =134, DQ1 =126, DQ2 =118, DQ3 =130
9008 12:38:44.451240 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =126
9009 12:38:44.454058 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =118
9010 12:38:44.457628 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =134
9011 12:38:44.457709
9012 12:38:44.457772
9013 12:38:44.457831
9014 12:38:44.460946 [DramC_TX_OE_Calibration] TA2
9015 12:38:44.464456 Original DQ_B0 (3 6) =30, OEN = 27
9016 12:38:44.467685 Original DQ_B1 (3 6) =30, OEN = 27
9017 12:38:44.471078 24, 0x0, End_B0=24 End_B1=24
9018 12:38:44.471160 25, 0x0, End_B0=25 End_B1=25
9019 12:38:44.474408 26, 0x0, End_B0=26 End_B1=26
9020 12:38:44.477691 27, 0x0, End_B0=27 End_B1=27
9021 12:38:44.481116 28, 0x0, End_B0=28 End_B1=28
9022 12:38:44.484302 29, 0x0, End_B0=29 End_B1=29
9023 12:38:44.484384 30, 0x0, End_B0=30 End_B1=30
9024 12:38:44.488043 31, 0x4545, End_B0=30 End_B1=30
9025 12:38:44.490932 Byte0 end_step=30 best_step=27
9026 12:38:44.494275 Byte1 end_step=30 best_step=27
9027 12:38:44.497648 Byte0 TX OE(2T, 0.5T) = (3, 3)
9028 12:38:44.500718 Byte1 TX OE(2T, 0.5T) = (3, 3)
9029 12:38:44.500842
9030 12:38:44.500939
9031 12:38:44.507612 [DQSOSCAuto] RK1, (LSB)MR18= 0x1116, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
9032 12:38:44.510593 CH1 RK1: MR19=303, MR18=1116
9033 12:38:44.517512 CH1_RK1: MR19=0x303, MR18=0x1116, DQSOSC=398, MR23=63, INC=23, DEC=15
9034 12:38:44.521178 [RxdqsGatingPostProcess] freq 1600
9035 12:38:44.524033 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9036 12:38:44.527957 best DQS0 dly(2T, 0.5T) = (1, 1)
9037 12:38:44.530719 best DQS1 dly(2T, 0.5T) = (1, 1)
9038 12:38:44.534602 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9039 12:38:44.537742 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9040 12:38:44.541294 best DQS0 dly(2T, 0.5T) = (1, 1)
9041 12:38:44.544420 best DQS1 dly(2T, 0.5T) = (1, 1)
9042 12:38:44.547586 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9043 12:38:44.551150 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9044 12:38:44.551231 Pre-setting of DQS Precalculation
9045 12:38:44.557694 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9046 12:38:44.564235 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9047 12:38:44.571465 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9048 12:38:44.571546
9049 12:38:44.571610
9050 12:38:44.574594 [Calibration Summary] 3200 Mbps
9051 12:38:44.578034 CH 0, Rank 0
9052 12:38:44.578114 SW Impedance : PASS
9053 12:38:44.581097 DUTY Scan : NO K
9054 12:38:44.584419 ZQ Calibration : PASS
9055 12:38:44.584500 Jitter Meter : NO K
9056 12:38:44.588233 CBT Training : PASS
9057 12:38:44.588313 Write leveling : PASS
9058 12:38:44.591449 RX DQS gating : PASS
9059 12:38:44.594241 RX DQ/DQS(RDDQC) : PASS
9060 12:38:44.594321 TX DQ/DQS : PASS
9061 12:38:44.597997 RX DATLAT : PASS
9062 12:38:44.601213 RX DQ/DQS(Engine): PASS
9063 12:38:44.601294 TX OE : PASS
9064 12:38:44.604192 All Pass.
9065 12:38:44.604273
9066 12:38:44.604337 CH 0, Rank 1
9067 12:38:44.607975 SW Impedance : PASS
9068 12:38:44.608055 DUTY Scan : NO K
9069 12:38:44.610772 ZQ Calibration : PASS
9070 12:38:44.614153 Jitter Meter : NO K
9071 12:38:44.614234 CBT Training : PASS
9072 12:38:44.617807 Write leveling : PASS
9073 12:38:44.621057 RX DQS gating : PASS
9074 12:38:44.621138 RX DQ/DQS(RDDQC) : PASS
9075 12:38:44.624342 TX DQ/DQS : PASS
9076 12:38:44.627536 RX DATLAT : PASS
9077 12:38:44.627617 RX DQ/DQS(Engine): PASS
9078 12:38:44.630890 TX OE : PASS
9079 12:38:44.630971 All Pass.
9080 12:38:44.631035
9081 12:38:44.634030 CH 1, Rank 0
9082 12:38:44.634110 SW Impedance : PASS
9083 12:38:44.637531 DUTY Scan : NO K
9084 12:38:44.640606 ZQ Calibration : PASS
9085 12:38:44.640686 Jitter Meter : NO K
9086 12:38:44.644451 CBT Training : PASS
9087 12:38:44.644533 Write leveling : PASS
9088 12:38:44.647342 RX DQS gating : PASS
9089 12:38:44.650678 RX DQ/DQS(RDDQC) : PASS
9090 12:38:44.650758 TX DQ/DQS : PASS
9091 12:38:44.654018 RX DATLAT : PASS
9092 12:38:44.657359 RX DQ/DQS(Engine): PASS
9093 12:38:44.657440 TX OE : PASS
9094 12:38:44.660788 All Pass.
9095 12:38:44.660868
9096 12:38:44.660932 CH 1, Rank 1
9097 12:38:44.663994 SW Impedance : PASS
9098 12:38:44.664074 DUTY Scan : NO K
9099 12:38:44.667828 ZQ Calibration : PASS
9100 12:38:44.670531 Jitter Meter : NO K
9101 12:38:44.670612 CBT Training : PASS
9102 12:38:44.674204 Write leveling : PASS
9103 12:38:44.677512 RX DQS gating : PASS
9104 12:38:44.677592 RX DQ/DQS(RDDQC) : PASS
9105 12:38:44.680660 TX DQ/DQS : PASS
9106 12:38:44.684579 RX DATLAT : PASS
9107 12:38:44.684659 RX DQ/DQS(Engine): PASS
9108 12:38:44.687281 TX OE : PASS
9109 12:38:44.687387 All Pass.
9110 12:38:44.687476
9111 12:38:44.690689 DramC Write-DBI on
9112 12:38:44.690770 PER_BANK_REFRESH: Hybrid Mode
9113 12:38:44.694070 TX_TRACKING: ON
9114 12:38:44.704268 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9115 12:38:44.710903 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9116 12:38:44.717711 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9117 12:38:44.721195 [FAST_K] Save calibration result to emmc
9118 12:38:44.724450 sync common calibartion params.
9119 12:38:44.727356 sync cbt_mode0:1, 1:1
9120 12:38:44.727435 dram_init: ddr_geometry: 2
9121 12:38:44.730828 dram_init: ddr_geometry: 2
9122 12:38:44.734323 dram_init: ddr_geometry: 2
9123 12:38:44.737559 0:dram_rank_size:100000000
9124 12:38:44.737641 1:dram_rank_size:100000000
9125 12:38:44.744347 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9126 12:38:44.747799 DFS_SHUFFLE_HW_MODE: ON
9127 12:38:44.751174 dramc_set_vcore_voltage set vcore to 725000
9128 12:38:44.751269 Read voltage for 1600, 0
9129 12:38:44.753956 Vio18 = 0
9130 12:38:44.754036 Vcore = 725000
9131 12:38:44.754100 Vdram = 0
9132 12:38:44.757726 Vddq = 0
9133 12:38:44.757806 Vmddr = 0
9134 12:38:44.760642 switch to 3200 Mbps bootup
9135 12:38:44.760722 [DramcRunTimeConfig]
9136 12:38:44.764491 PHYPLL
9137 12:38:44.764572 DPM_CONTROL_AFTERK: ON
9138 12:38:44.767711 PER_BANK_REFRESH: ON
9139 12:38:44.770418 REFRESH_OVERHEAD_REDUCTION: ON
9140 12:38:44.770545 CMD_PICG_NEW_MODE: OFF
9141 12:38:44.774056 XRTWTW_NEW_MODE: ON
9142 12:38:44.774136 XRTRTR_NEW_MODE: ON
9143 12:38:44.777577 TX_TRACKING: ON
9144 12:38:44.777658 RDSEL_TRACKING: OFF
9145 12:38:44.780718 DQS Precalculation for DVFS: ON
9146 12:38:44.784029 RX_TRACKING: OFF
9147 12:38:44.784109 HW_GATING DBG: ON
9148 12:38:44.787453 ZQCS_ENABLE_LP4: ON
9149 12:38:44.787534 RX_PICG_NEW_MODE: ON
9150 12:38:44.790623 TX_PICG_NEW_MODE: ON
9151 12:38:44.790704 ENABLE_RX_DCM_DPHY: ON
9152 12:38:44.793629 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9153 12:38:44.797369 DUMMY_READ_FOR_TRACKING: OFF
9154 12:38:44.800527 !!! SPM_CONTROL_AFTERK: OFF
9155 12:38:44.803645 !!! SPM could not control APHY
9156 12:38:44.803725 IMPEDANCE_TRACKING: ON
9157 12:38:44.807557 TEMP_SENSOR: ON
9158 12:38:44.807637 HW_SAVE_FOR_SR: OFF
9159 12:38:44.810429 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9160 12:38:44.814290 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9161 12:38:44.817407 Read ODT Tracking: ON
9162 12:38:44.820799 Refresh Rate DeBounce: ON
9163 12:38:44.820880 DFS_NO_QUEUE_FLUSH: ON
9164 12:38:44.824320 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9165 12:38:44.827272 ENABLE_DFS_RUNTIME_MRW: OFF
9166 12:38:44.830985 DDR_RESERVE_NEW_MODE: ON
9167 12:38:44.831065 MR_CBT_SWITCH_FREQ: ON
9168 12:38:44.833924 =========================
9169 12:38:44.852786 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9170 12:38:44.855652 dram_init: ddr_geometry: 2
9171 12:38:44.874230 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9172 12:38:44.877724 dram_init: dram init end (result: 0)
9173 12:38:44.883734 DRAM-K: Full calibration passed in 24580 msecs
9174 12:38:44.887223 MRC: failed to locate region type 0.
9175 12:38:44.887304 DRAM rank0 size:0x100000000,
9176 12:38:44.890834 DRAM rank1 size=0x100000000
9177 12:38:44.900675 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9178 12:38:44.907318 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9179 12:38:44.913676 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9180 12:38:44.920888 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9181 12:38:44.923853 DRAM rank0 size:0x100000000,
9182 12:38:44.927593 DRAM rank1 size=0x100000000
9183 12:38:44.927673 CBMEM:
9184 12:38:44.930825 IMD: root @ 0xfffff000 254 entries.
9185 12:38:44.934139 IMD: root @ 0xffffec00 62 entries.
9186 12:38:44.937072 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9187 12:38:44.940499 WARNING: RO_VPD is uninitialized or empty.
9188 12:38:44.947466 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9189 12:38:44.954251 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9190 12:38:44.967105 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9191 12:38:44.978328 BS: romstage times (exec / console): total (unknown) / 24086 ms
9192 12:38:44.978432
9193 12:38:44.978513
9194 12:38:44.988258 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9195 12:38:44.991959 ARM64: Exception handlers installed.
9196 12:38:44.995281 ARM64: Testing exception
9197 12:38:44.995361 ARM64: Done test exception
9198 12:38:44.998184 Enumerating buses...
9199 12:38:45.001876 Show all devs... Before device enumeration.
9200 12:38:45.004931 Root Device: enabled 1
9201 12:38:45.007896 CPU_CLUSTER: 0: enabled 1
9202 12:38:45.007976 CPU: 00: enabled 1
9203 12:38:45.011328 Compare with tree...
9204 12:38:45.011408 Root Device: enabled 1
9205 12:38:45.014838 CPU_CLUSTER: 0: enabled 1
9206 12:38:45.017781 CPU: 00: enabled 1
9207 12:38:45.017861 Root Device scanning...
9208 12:38:45.021608 scan_static_bus for Root Device
9209 12:38:45.024873 CPU_CLUSTER: 0 enabled
9210 12:38:45.028032 scan_static_bus for Root Device done
9211 12:38:45.031230 scan_bus: bus Root Device finished in 8 msecs
9212 12:38:45.031310 done
9213 12:38:45.038174 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9214 12:38:45.041315 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9215 12:38:45.048646 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9216 12:38:45.051466 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9217 12:38:45.055085 Allocating resources...
9218 12:38:45.058085 Reading resources...
9219 12:38:45.061169 Root Device read_resources bus 0 link: 0
9220 12:38:45.061250 DRAM rank0 size:0x100000000,
9221 12:38:45.064839 DRAM rank1 size=0x100000000
9222 12:38:45.067861 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9223 12:38:45.071266 CPU: 00 missing read_resources
9224 12:38:45.074427 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9225 12:38:45.081282 Root Device read_resources bus 0 link: 0 done
9226 12:38:45.081363 Done reading resources.
9227 12:38:45.087561 Show resources in subtree (Root Device)...After reading.
9228 12:38:45.091189 Root Device child on link 0 CPU_CLUSTER: 0
9229 12:38:45.094257 CPU_CLUSTER: 0 child on link 0 CPU: 00
9230 12:38:45.104201 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9231 12:38:45.104282 CPU: 00
9232 12:38:45.107595 Root Device assign_resources, bus 0 link: 0
9233 12:38:45.110811 CPU_CLUSTER: 0 missing set_resources
9234 12:38:45.114430 Root Device assign_resources, bus 0 link: 0 done
9235 12:38:45.117595 Done setting resources.
9236 12:38:45.124368 Show resources in subtree (Root Device)...After assigning values.
9237 12:38:45.127478 Root Device child on link 0 CPU_CLUSTER: 0
9238 12:38:45.130963 CPU_CLUSTER: 0 child on link 0 CPU: 00
9239 12:38:45.141061 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9240 12:38:45.141143 CPU: 00
9241 12:38:45.144177 Done allocating resources.
9242 12:38:45.147957 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9243 12:38:45.150966 Enabling resources...
9244 12:38:45.151047 done.
9245 12:38:45.157576 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9246 12:38:45.157657 Initializing devices...
9247 12:38:45.161018 Root Device init
9248 12:38:45.161097 init hardware done!
9249 12:38:45.164396 0x00000018: ctrlr->caps
9250 12:38:45.168147 52.000 MHz: ctrlr->f_max
9251 12:38:45.168229 0.400 MHz: ctrlr->f_min
9252 12:38:45.171241 0x40ff8080: ctrlr->voltages
9253 12:38:45.171323 sclk: 390625
9254 12:38:45.174215 Bus Width = 1
9255 12:38:45.174295 sclk: 390625
9256 12:38:45.174358 Bus Width = 1
9257 12:38:45.177957 Early init status = 3
9258 12:38:45.184938 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9259 12:38:45.187719 in-header: 03 fb 00 00 01 00 00 00
9260 12:38:45.187798 in-data: 01
9261 12:38:45.194245 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9262 12:38:45.197475 in-header: 03 fb 00 00 01 00 00 00
9263 12:38:45.197555 in-data: 01
9264 12:38:45.201119 [SSUSB] Setting up USB HOST controller...
9265 12:38:45.207534 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9266 12:38:45.207615 [SSUSB] phy power-on done.
9267 12:38:45.214177 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9268 12:38:45.217331 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9269 12:38:45.223985 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9270 12:38:45.230895 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9271 12:38:45.234385 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9272 12:38:45.241693 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9273 12:38:45.248626 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9274 12:38:45.254889 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9275 12:38:45.258595 SPM: binary array size = 0x9dc
9276 12:38:45.265563 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9277 12:38:45.268477 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9278 12:38:45.274945 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9279 12:38:45.282112 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9280 12:38:45.285364 configure_display: Starting display init
9281 12:38:45.319461 anx7625_power_on_init: Init interface.
9282 12:38:45.322572 anx7625_disable_pd_protocol: Disabled PD feature.
9283 12:38:45.326253 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9284 12:38:45.353602 anx7625_start_dp_work: Secure OCM version=00
9285 12:38:45.357062 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9286 12:38:45.372476 sp_tx_get_edid_block: EDID Block = 1
9287 12:38:45.474892 Extracted contents:
9288 12:38:45.477996 header: 00 ff ff ff ff ff ff 00
9289 12:38:45.481046 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9290 12:38:45.484505 version: 01 04
9291 12:38:45.488144 basic params: 95 1f 11 78 0a
9292 12:38:45.491031 chroma info: 76 90 94 55 54 90 27 21 50 54
9293 12:38:45.494675 established: 00 00 00
9294 12:38:45.501434 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9295 12:38:45.504313 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9296 12:38:45.511099 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9297 12:38:45.517826 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9298 12:38:45.524725 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9299 12:38:45.528578 extensions: 00
9300 12:38:45.528657 checksum: fb
9301 12:38:45.528721
9302 12:38:45.531654 Manufacturer: IVO Model 57d Serial Number 0
9303 12:38:45.534290 Made week 0 of 2020
9304 12:38:45.534370 EDID version: 1.4
9305 12:38:45.538128 Digital display
9306 12:38:45.541110 6 bits per primary color channel
9307 12:38:45.541188 DisplayPort interface
9308 12:38:45.544920 Maximum image size: 31 cm x 17 cm
9309 12:38:45.545000 Gamma: 220%
9310 12:38:45.548012 Check DPMS levels
9311 12:38:45.551575 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9312 12:38:45.554915 First detailed timing is preferred timing
9313 12:38:45.558096 Established timings supported:
9314 12:38:45.561425 Standard timings supported:
9315 12:38:45.561506 Detailed timings
9316 12:38:45.568616 Hex of detail: 383680a07038204018303c0035ae10000019
9317 12:38:45.571099 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9318 12:38:45.574967 0780 0798 07c8 0820 hborder 0
9319 12:38:45.580991 0438 043b 0447 0458 vborder 0
9320 12:38:45.581071 -hsync -vsync
9321 12:38:45.584237 Did detailed timing
9322 12:38:45.587732 Hex of detail: 000000000000000000000000000000000000
9323 12:38:45.591587 Manufacturer-specified data, tag 0
9324 12:38:45.597747 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9325 12:38:45.597827 ASCII string: InfoVision
9326 12:38:45.604189 Hex of detail: 000000fe00523134304e574635205248200a
9327 12:38:45.604272 ASCII string: R140NWF5 RH
9328 12:38:45.607354 Checksum
9329 12:38:45.607431 Checksum: 0xfb (valid)
9330 12:38:45.614284 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9331 12:38:45.617424 DSI data_rate: 832800000 bps
9332 12:38:45.621336 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9333 12:38:45.624498 anx7625_parse_edid: pixelclock(138800).
9334 12:38:45.631036 hactive(1920), hsync(48), hfp(24), hbp(88)
9335 12:38:45.634307 vactive(1080), vsync(12), vfp(3), vbp(17)
9336 12:38:45.637748 anx7625_dsi_config: config dsi.
9337 12:38:45.644481 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9338 12:38:45.657117 anx7625_dsi_config: success to config DSI
9339 12:38:45.659575 anx7625_dp_start: MIPI phy setup OK.
9340 12:38:45.663109 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9341 12:38:45.666459 mtk_ddp_mode_set invalid vrefresh 60
9342 12:38:45.669979 main_disp_path_setup
9343 12:38:45.670059 ovl_layer_smi_id_en
9344 12:38:45.673144 ovl_layer_smi_id_en
9345 12:38:45.673225 ccorr_config
9346 12:38:45.673289 aal_config
9347 12:38:45.676936 gamma_config
9348 12:38:45.677015 postmask_config
9349 12:38:45.679909 dither_config
9350 12:38:45.682974 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9351 12:38:45.689738 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9352 12:38:45.693319 Root Device init finished in 529 msecs
9353 12:38:45.693400 CPU_CLUSTER: 0 init
9354 12:38:45.703263 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9355 12:38:45.706348 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9356 12:38:45.709832 APU_MBOX 0x190000b0 = 0x10001
9357 12:38:45.713350 APU_MBOX 0x190001b0 = 0x10001
9358 12:38:45.716485 APU_MBOX 0x190005b0 = 0x10001
9359 12:38:45.720439 APU_MBOX 0x190006b0 = 0x10001
9360 12:38:45.723387 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9361 12:38:45.735804 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9362 12:38:45.748224 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9363 12:38:45.754899 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9364 12:38:45.766120 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9365 12:38:45.775216 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9366 12:38:45.779036 CPU_CLUSTER: 0 init finished in 81 msecs
9367 12:38:45.781881 Devices initialized
9368 12:38:45.785680 Show all devs... After init.
9369 12:38:45.785761 Root Device: enabled 1
9370 12:38:45.788888 CPU_CLUSTER: 0: enabled 1
9371 12:38:45.791926 CPU: 00: enabled 1
9372 12:38:45.795314 BS: BS_DEV_INIT run times (exec / console): 206 / 428 ms
9373 12:38:45.798551 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9374 12:38:45.802077 ELOG: NV offset 0x57f000 size 0x1000
9375 12:38:45.809186 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9376 12:38:45.815211 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9377 12:38:45.818880 ELOG: Event(17) added with size 13 at 2024-02-05 12:39:08 UTC
9378 12:38:45.822042 out: cmd=0x121: 03 db 21 01 00 00 00 00
9379 12:38:45.825996 in-header: 03 a9 00 00 2c 00 00 00
9380 12:38:45.839030 in-data: b6 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9381 12:38:45.845976 ELOG: Event(A1) added with size 10 at 2024-02-05 12:39:08 UTC
9382 12:38:45.852614 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9383 12:38:45.858873 ELOG: Event(A0) added with size 9 at 2024-02-05 12:39:08 UTC
9384 12:38:45.862543 elog_add_boot_reason: Logged dev mode boot
9385 12:38:45.865714 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9386 12:38:45.869170 Finalize devices...
9387 12:38:45.869251 Devices finalized
9388 12:38:45.875978 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9389 12:38:45.879257 Writing coreboot table at 0xffe64000
9390 12:38:45.882227 0. 000000000010a000-0000000000113fff: RAMSTAGE
9391 12:38:45.886065 1. 0000000040000000-00000000400fffff: RAM
9392 12:38:45.888883 2. 0000000040100000-000000004032afff: RAMSTAGE
9393 12:38:45.895804 3. 000000004032b000-00000000545fffff: RAM
9394 12:38:45.898926 4. 0000000054600000-000000005465ffff: BL31
9395 12:38:45.902676 5. 0000000054660000-00000000ffe63fff: RAM
9396 12:38:45.905552 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9397 12:38:45.912403 7. 0000000100000000-000000023fffffff: RAM
9398 12:38:45.912483 Passing 5 GPIOs to payload:
9399 12:38:45.919130 NAME | PORT | POLARITY | VALUE
9400 12:38:45.922355 EC in RW | 0x000000aa | low | undefined
9401 12:38:45.929020 EC interrupt | 0x00000005 | low | undefined
9402 12:38:45.932076 TPM interrupt | 0x000000ab | high | undefined
9403 12:38:45.935605 SD card detect | 0x00000011 | high | undefined
9404 12:38:45.942517 speaker enable | 0x00000093 | high | undefined
9405 12:38:45.945686 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9406 12:38:45.948773 in-header: 03 f9 00 00 02 00 00 00
9407 12:38:45.948852 in-data: 02 00
9408 12:38:45.952195 ADC[4]: Raw value=899114 ID=7
9409 12:38:45.955589 ADC[3]: Raw value=213336 ID=1
9410 12:38:45.955685 RAM Code: 0x71
9411 12:38:45.959009 ADC[6]: Raw value=74557 ID=0
9412 12:38:45.962131 ADC[5]: Raw value=212229 ID=1
9413 12:38:45.962210 SKU Code: 0x1
9414 12:38:45.968884 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 51b0
9415 12:38:45.972361 coreboot table: 964 bytes.
9416 12:38:45.975619 IMD ROOT 0. 0xfffff000 0x00001000
9417 12:38:45.979052 IMD SMALL 1. 0xffffe000 0x00001000
9418 12:38:45.982135 RO MCACHE 2. 0xffffc000 0x00001104
9419 12:38:45.985301 CONSOLE 3. 0xfff7c000 0x00080000
9420 12:38:45.988820 FMAP 4. 0xfff7b000 0x00000452
9421 12:38:45.992419 TIME STAMP 5. 0xfff7a000 0x00000910
9422 12:38:45.995457 VBOOT WORK 6. 0xfff66000 0x00014000
9423 12:38:45.999196 RAMOOPS 7. 0xffe66000 0x00100000
9424 12:38:46.002140 COREBOOT 8. 0xffe64000 0x00002000
9425 12:38:46.002220 IMD small region:
9426 12:38:46.005940 IMD ROOT 0. 0xffffec00 0x00000400
9427 12:38:46.008861 VPD 1. 0xffffeb80 0x0000006c
9428 12:38:46.011950 MMC STATUS 2. 0xffffeb60 0x00000004
9429 12:38:46.018793 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9430 12:38:46.018874 Probing TPM: done!
9431 12:38:46.025379 Connected to device vid:did:rid of 1ae0:0028:00
9432 12:38:46.032616 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9433 12:38:46.035637 Initialized TPM device CR50 revision 0
9434 12:38:46.040014 Checking cr50 for pending updates
9435 12:38:46.045254 Reading cr50 TPM mode
9436 12:38:46.053802 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9437 12:38:46.060637 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9438 12:38:46.100761 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9439 12:38:46.103935 Checking segment from ROM address 0x40100000
9440 12:38:46.107430 Checking segment from ROM address 0x4010001c
9441 12:38:46.114384 Loading segment from ROM address 0x40100000
9442 12:38:46.114503 code (compression=0)
9443 12:38:46.120541 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9444 12:38:46.130534 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9445 12:38:46.130615 it's not compressed!
9446 12:38:46.137564 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9447 12:38:46.140705 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9448 12:38:46.161080 Loading segment from ROM address 0x4010001c
9449 12:38:46.161163 Entry Point 0x80000000
9450 12:38:46.164805 Loaded segments
9451 12:38:46.167676 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9452 12:38:46.174359 Jumping to boot code at 0x80000000(0xffe64000)
9453 12:38:46.180804 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9454 12:38:46.187651 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9455 12:38:46.195411 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9456 12:38:46.199507 Checking segment from ROM address 0x40100000
9457 12:38:46.202004 Checking segment from ROM address 0x4010001c
9458 12:38:46.205547 Loading segment from ROM address 0x40100000
9459 12:38:46.208854 code (compression=1)
9460 12:38:46.215416 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9461 12:38:46.225424 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9462 12:38:46.225506 using LZMA
9463 12:38:46.233901 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9464 12:38:46.240737 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9465 12:38:46.243858 Loading segment from ROM address 0x4010001c
9466 12:38:46.243938 Entry Point 0x54601000
9467 12:38:46.247252 Loaded segments
9468 12:38:46.250645 NOTICE: MT8192 bl31_setup
9469 12:38:46.257373 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9470 12:38:46.260956 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9471 12:38:46.264216 WARNING: region 0:
9472 12:38:46.267159 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9473 12:38:46.267239 WARNING: region 1:
9474 12:38:46.273772 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9475 12:38:46.277514 WARNING: region 2:
9476 12:38:46.280965 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9477 12:38:46.284130 WARNING: region 3:
9478 12:38:46.287414 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9479 12:38:46.291041 WARNING: region 4:
9480 12:38:46.294366 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9481 12:38:46.297501 WARNING: region 5:
9482 12:38:46.300793 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 12:38:46.304282 WARNING: region 6:
9484 12:38:46.307810 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9485 12:38:46.307891 WARNING: region 7:
9486 12:38:46.314513 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9487 12:38:46.320723 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9488 12:38:46.324389 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9489 12:38:46.328455 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9490 12:38:46.331162 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9491 12:38:46.338053 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9492 12:38:46.341296 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9493 12:38:46.348518 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9494 12:38:46.351437 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9495 12:38:46.354614 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9496 12:38:46.361548 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9497 12:38:46.365181 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9498 12:38:46.368421 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9499 12:38:46.375271 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9500 12:38:46.378138 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9501 12:38:46.381269 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9502 12:38:46.388074 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9503 12:38:46.391697 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9504 12:38:46.398595 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9505 12:38:46.401748 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9506 12:38:46.405103 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9507 12:38:46.412031 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9508 12:38:46.415236 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9509 12:38:46.418684 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9510 12:38:46.425105 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9511 12:38:46.428226 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9512 12:38:46.435808 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9513 12:38:46.438341 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9514 12:38:46.442013 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9515 12:38:46.449041 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9516 12:38:46.451878 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9517 12:38:46.458783 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9518 12:38:46.462064 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9519 12:38:46.465597 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9520 12:38:46.468624 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9521 12:38:46.475278 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9522 12:38:46.479032 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9523 12:38:46.482674 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9524 12:38:46.485183 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9525 12:38:46.492057 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9526 12:38:46.495214 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9527 12:38:46.499221 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9528 12:38:46.502047 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9529 12:38:46.505782 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9530 12:38:46.512568 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9531 12:38:46.515870 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9532 12:38:46.519211 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9533 12:38:46.525726 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9534 12:38:46.529590 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9535 12:38:46.532959 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9536 12:38:46.539232 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9537 12:38:46.542712 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9538 12:38:46.545953 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9539 12:38:46.552445 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9540 12:38:46.555880 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9541 12:38:46.562541 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9542 12:38:46.565931 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9543 12:38:46.569985 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9544 12:38:46.576358 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9545 12:38:46.579647 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9546 12:38:46.586387 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9547 12:38:46.589612 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9548 12:38:46.596013 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9549 12:38:46.599278 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9550 12:38:46.606455 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9551 12:38:46.609958 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9552 12:38:46.613642 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9553 12:38:46.620133 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9554 12:38:46.622863 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9555 12:38:46.629866 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9556 12:38:46.633434 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9557 12:38:46.636540 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9558 12:38:46.643254 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9559 12:38:46.646949 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9560 12:38:46.653463 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9561 12:38:46.656496 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9562 12:38:46.663560 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9563 12:38:46.666760 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9564 12:38:46.670408 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9565 12:38:46.676802 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9566 12:38:46.680454 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9567 12:38:46.686883 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9568 12:38:46.689990 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9569 12:38:46.696913 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9570 12:38:46.700037 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9571 12:38:46.703928 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9572 12:38:46.710519 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9573 12:38:46.713740 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9574 12:38:46.720562 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9575 12:38:46.724100 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9576 12:38:46.726883 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9577 12:38:46.733625 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9578 12:38:46.737035 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9579 12:38:46.744293 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9580 12:38:46.747137 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9581 12:38:46.753849 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9582 12:38:46.757525 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9583 12:38:46.760870 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9584 12:38:46.764037 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9585 12:38:46.770640 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9586 12:38:46.774232 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9587 12:38:46.777331 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9588 12:38:46.784516 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9589 12:38:46.787489 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9590 12:38:46.790832 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9591 12:38:46.798298 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9592 12:38:46.800964 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9593 12:38:46.804422 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9594 12:38:46.811107 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9595 12:38:46.814636 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9596 12:38:46.821411 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9597 12:38:46.824327 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9598 12:38:46.828179 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9599 12:38:46.834245 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9600 12:38:46.837991 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9601 12:38:46.844408 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9602 12:38:46.847717 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9603 12:38:46.851378 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9604 12:38:46.857825 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9605 12:38:46.861478 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9606 12:38:46.864769 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9607 12:38:46.868004 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9608 12:38:46.874979 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9609 12:38:46.877897 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9610 12:38:46.881727 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9611 12:38:46.884649 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9612 12:38:46.891436 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9613 12:38:46.894605 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9614 12:38:46.901421 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9615 12:38:46.904858 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9616 12:38:46.908008 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9617 12:38:46.914996 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9618 12:38:46.917924 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9619 12:38:46.924543 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9620 12:38:46.927821 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9621 12:38:46.931402 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9622 12:38:46.938145 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9623 12:38:46.941268 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9624 12:38:46.944618 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9625 12:38:46.951418 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9626 12:38:46.954764 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9627 12:38:46.961513 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9628 12:38:46.965048 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9629 12:38:46.968063 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9630 12:38:46.974943 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9631 12:38:46.978419 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9632 12:38:46.981737 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9633 12:38:46.988302 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9634 12:38:46.991446 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9635 12:38:46.998254 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9636 12:38:47.001964 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9637 12:38:47.004897 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9638 12:38:47.011737 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9639 12:38:47.015463 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9640 12:38:47.022073 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9641 12:38:47.025096 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9642 12:38:47.028694 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9643 12:38:47.034882 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9644 12:38:47.038684 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9645 12:38:47.042530 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9646 12:38:47.048778 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9647 12:38:47.051847 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9648 12:38:47.058820 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9649 12:38:47.062245 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9650 12:38:47.065795 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9651 12:38:47.072190 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9652 12:38:47.075740 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9653 12:38:47.079025 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9654 12:38:47.085382 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9655 12:38:47.089159 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9656 12:38:47.096021 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9657 12:38:47.098711 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9658 12:38:47.101890 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9659 12:38:47.108634 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9660 12:38:47.112338 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9661 12:38:47.118757 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9662 12:38:47.122467 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9663 12:38:47.125656 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9664 12:38:47.132469 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9665 12:38:47.135462 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9666 12:38:47.138533 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9667 12:38:47.145218 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9668 12:38:47.148630 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9669 12:38:47.155269 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9670 12:38:47.159205 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9671 12:38:47.162079 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9672 12:38:47.168980 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9673 12:38:47.172289 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9674 12:38:47.175891 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9675 12:38:47.182180 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9676 12:38:47.185731 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9677 12:38:47.191920 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9678 12:38:47.195060 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9679 12:38:47.201826 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9680 12:38:47.205152 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9681 12:38:47.208678 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9682 12:38:47.215140 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9683 12:38:47.218806 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9684 12:38:47.225349 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9685 12:38:47.228856 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9686 12:38:47.235021 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9687 12:38:47.238854 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9688 12:38:47.241842 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9689 12:38:47.248403 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9690 12:38:47.251810 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9691 12:38:47.258663 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9692 12:38:47.261907 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9693 12:38:47.264838 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9694 12:38:47.271682 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9695 12:38:47.275386 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9696 12:38:47.282074 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9697 12:38:47.285222 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9698 12:38:47.288917 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9699 12:38:47.295131 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9700 12:38:47.299044 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9701 12:38:47.305340 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9702 12:38:47.308730 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9703 12:38:47.312613 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9704 12:38:47.318713 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9705 12:38:47.322420 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9706 12:38:47.328845 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9707 12:38:47.332022 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9708 12:38:47.335537 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9709 12:38:47.342020 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9710 12:38:47.345108 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9711 12:38:47.351924 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9712 12:38:47.355547 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9713 12:38:47.361752 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9714 12:38:47.365662 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9715 12:38:47.368596 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9716 12:38:47.375449 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9717 12:38:47.378593 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9718 12:38:47.382284 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9719 12:38:47.385435 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9720 12:38:47.388781 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9721 12:38:47.395218 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9722 12:38:47.398582 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9723 12:38:47.405181 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9724 12:38:47.408365 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9725 12:38:47.411999 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9726 12:38:47.418407 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9727 12:38:47.422066 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9728 12:38:47.425742 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9729 12:38:47.432002 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9730 12:38:47.435158 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9731 12:38:47.439049 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9732 12:38:47.445332 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9733 12:38:47.448884 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9734 12:38:47.455225 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9735 12:38:47.458951 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9736 12:38:47.461987 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9737 12:38:47.468657 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9738 12:38:47.471843 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9739 12:38:47.475441 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9740 12:38:47.482011 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9741 12:38:47.485753 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9742 12:38:47.488539 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9743 12:38:47.495049 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9744 12:38:47.498713 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9745 12:38:47.502094 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9746 12:38:47.509152 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9747 12:38:47.511976 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9748 12:38:47.518651 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9749 12:38:47.522577 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9750 12:38:47.525622 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9751 12:38:47.532304 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9752 12:38:47.535597 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9753 12:38:47.538590 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9754 12:38:47.545409 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9755 12:38:47.548750 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9756 12:38:47.552229 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9757 12:38:47.555468 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9758 12:38:47.561977 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9759 12:38:47.565706 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9760 12:38:47.568879 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9761 12:38:47.572419 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9762 12:38:47.578820 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9763 12:38:47.582311 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9764 12:38:47.585968 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9765 12:38:47.589131 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9766 12:38:47.592172 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9767 12:38:47.598849 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9768 12:38:47.602726 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9769 12:38:47.605833 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9770 12:38:47.612189 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9771 12:38:47.615871 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9772 12:38:47.622346 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9773 12:38:47.625962 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9774 12:38:47.632449 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9775 12:38:47.635661 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9776 12:38:47.639346 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9777 12:38:47.645878 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9778 12:38:47.649353 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9779 12:38:47.656245 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9780 12:38:47.658933 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9781 12:38:47.662208 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9782 12:38:47.669050 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9783 12:38:47.672197 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9784 12:38:47.675752 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9785 12:38:47.682258 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9786 12:38:47.685856 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9787 12:38:47.692172 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9788 12:38:47.695887 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9789 12:38:47.702134 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9790 12:38:47.705979 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9791 12:38:47.709122 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9792 12:38:47.715654 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9793 12:38:47.718925 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9794 12:38:47.725664 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9795 12:38:47.728925 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9796 12:38:47.732717 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9797 12:38:47.739164 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9798 12:38:47.742310 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9799 12:38:47.748849 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9800 12:38:47.752743 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9801 12:38:47.755682 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9802 12:38:47.762226 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9803 12:38:47.765675 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9804 12:38:47.772438 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9805 12:38:47.775862 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9806 12:38:47.778958 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9807 12:38:47.785906 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9808 12:38:47.789107 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9809 12:38:47.795500 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9810 12:38:47.799370 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9811 12:38:47.802203 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9812 12:38:47.808888 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9813 12:38:47.812586 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9814 12:38:47.819283 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9815 12:38:47.822807 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9816 12:38:47.825742 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9817 12:38:47.832686 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9818 12:38:47.835932 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9819 12:38:47.842474 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9820 12:38:47.845572 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9821 12:38:47.849068 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9822 12:38:47.855680 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9823 12:38:47.859609 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9824 12:38:47.865854 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9825 12:38:47.868971 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9826 12:38:47.872759 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9827 12:38:47.878730 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9828 12:38:47.882821 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9829 12:38:47.888932 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9830 12:38:47.892507 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9831 12:38:47.898998 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9832 12:38:47.902914 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9833 12:38:47.905653 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9834 12:38:47.912924 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9835 12:38:47.915530 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9836 12:38:47.919668 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9837 12:38:47.925665 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9838 12:38:47.929399 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9839 12:38:47.935656 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9840 12:38:47.939399 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9841 12:38:47.942450 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9842 12:38:47.949311 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9843 12:38:47.952845 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9844 12:38:47.958956 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9845 12:38:47.963117 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9846 12:38:47.969170 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9847 12:38:47.972205 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9848 12:38:47.975752 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9849 12:38:47.982258 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9850 12:38:47.985745 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9851 12:38:47.992705 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9852 12:38:47.996297 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9853 12:38:48.002605 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9854 12:38:48.005743 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9855 12:38:48.012231 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9856 12:38:48.015717 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9857 12:38:48.019589 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9858 12:38:48.026087 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9859 12:38:48.029069 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9860 12:38:48.035708 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9861 12:38:48.038835 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9862 12:38:48.045727 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9863 12:38:48.049357 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9864 12:38:48.052376 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9865 12:38:48.059004 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9866 12:38:48.062521 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9867 12:38:48.068923 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9868 12:38:48.072511 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9869 12:38:48.079154 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9870 12:38:48.082335 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9871 12:38:48.085830 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9872 12:38:48.092107 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9873 12:38:48.095699 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9874 12:38:48.102439 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9875 12:38:48.105645 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9876 12:38:48.112138 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9877 12:38:48.115735 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9878 12:38:48.119145 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9879 12:38:48.125760 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9880 12:38:48.129037 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9881 12:38:48.135822 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9882 12:38:48.139395 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9883 12:38:48.142294 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9884 12:38:48.148447 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9885 12:38:48.152135 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9886 12:38:48.158949 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9887 12:38:48.162048 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9888 12:38:48.168620 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9889 12:38:48.171924 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9890 12:38:48.175188 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9891 12:38:48.182105 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9892 12:38:48.185202 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9893 12:38:48.192008 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9894 12:38:48.194947 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9895 12:38:48.201704 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9896 12:38:48.205418 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9897 12:38:48.211688 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9898 12:38:48.214968 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9899 12:38:48.221686 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9900 12:38:48.225499 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9901 12:38:48.231900 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9902 12:38:48.234912 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9903 12:38:48.241693 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9904 12:38:48.245120 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9905 12:38:48.251907 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9906 12:38:48.254995 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9907 12:38:48.262165 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9908 12:38:48.265016 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9909 12:38:48.268895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9910 12:38:48.274951 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9911 12:38:48.278435 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9912 12:38:48.285058 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9913 12:38:48.288691 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9914 12:38:48.295165 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9915 12:38:48.299230 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9916 12:38:48.305406 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9917 12:38:48.308598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9918 12:38:48.315456 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9919 12:38:48.318332 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9920 12:38:48.325074 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9921 12:38:48.328794 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9922 12:38:48.332057 INFO: [APUAPC] vio 0
9923 12:38:48.335159 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9924 12:38:48.341873 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9925 12:38:48.345485 INFO: [APUAPC] D0_APC_0: 0x400510
9926 12:38:48.348559 INFO: [APUAPC] D0_APC_1: 0x0
9927 12:38:48.348641 INFO: [APUAPC] D0_APC_2: 0x1540
9928 12:38:48.351896 INFO: [APUAPC] D0_APC_3: 0x0
9929 12:38:48.355417 INFO: [APUAPC] D1_APC_0: 0xffffffff
9930 12:38:48.359083 INFO: [APUAPC] D1_APC_1: 0xffffffff
9931 12:38:48.362513 INFO: [APUAPC] D1_APC_2: 0x3fffff
9932 12:38:48.365063 INFO: [APUAPC] D1_APC_3: 0x0
9933 12:38:48.368948 INFO: [APUAPC] D2_APC_0: 0xffffffff
9934 12:38:48.372020 INFO: [APUAPC] D2_APC_1: 0xffffffff
9935 12:38:48.375439 INFO: [APUAPC] D2_APC_2: 0x3fffff
9936 12:38:48.378988 INFO: [APUAPC] D2_APC_3: 0x0
9937 12:38:48.382220 INFO: [APUAPC] D3_APC_0: 0xffffffff
9938 12:38:48.385644 INFO: [APUAPC] D3_APC_1: 0xffffffff
9939 12:38:48.389082 INFO: [APUAPC] D3_APC_2: 0x3fffff
9940 12:38:48.392328 INFO: [APUAPC] D3_APC_3: 0x0
9941 12:38:48.395582 INFO: [APUAPC] D4_APC_0: 0xffffffff
9942 12:38:48.399341 INFO: [APUAPC] D4_APC_1: 0xffffffff
9943 12:38:48.401936 INFO: [APUAPC] D4_APC_2: 0x3fffff
9944 12:38:48.405660 INFO: [APUAPC] D4_APC_3: 0x0
9945 12:38:48.408727 INFO: [APUAPC] D5_APC_0: 0xffffffff
9946 12:38:48.412192 INFO: [APUAPC] D5_APC_1: 0xffffffff
9947 12:38:48.415820 INFO: [APUAPC] D5_APC_2: 0x3fffff
9948 12:38:48.418829 INFO: [APUAPC] D5_APC_3: 0x0
9949 12:38:48.422258 INFO: [APUAPC] D6_APC_0: 0xffffffff
9950 12:38:48.426252 INFO: [APUAPC] D6_APC_1: 0xffffffff
9951 12:38:48.428919 INFO: [APUAPC] D6_APC_2: 0x3fffff
9952 12:38:48.432249 INFO: [APUAPC] D6_APC_3: 0x0
9953 12:38:48.435780 INFO: [APUAPC] D7_APC_0: 0xffffffff
9954 12:38:48.438982 INFO: [APUAPC] D7_APC_1: 0xffffffff
9955 12:38:48.442274 INFO: [APUAPC] D7_APC_2: 0x3fffff
9956 12:38:48.442354 INFO: [APUAPC] D7_APC_3: 0x0
9957 12:38:48.449046 INFO: [APUAPC] D8_APC_0: 0xffffffff
9958 12:38:48.452745 INFO: [APUAPC] D8_APC_1: 0xffffffff
9959 12:38:48.456000 INFO: [APUAPC] D8_APC_2: 0x3fffff
9960 12:38:48.456079 INFO: [APUAPC] D8_APC_3: 0x0
9961 12:38:48.458846 INFO: [APUAPC] D9_APC_0: 0xffffffff
9962 12:38:48.462587 INFO: [APUAPC] D9_APC_1: 0xffffffff
9963 12:38:48.466247 INFO: [APUAPC] D9_APC_2: 0x3fffff
9964 12:38:48.469746 INFO: [APUAPC] D9_APC_3: 0x0
9965 12:38:48.472534 INFO: [APUAPC] D10_APC_0: 0xffffffff
9966 12:38:48.476454 INFO: [APUAPC] D10_APC_1: 0xffffffff
9967 12:38:48.479389 INFO: [APUAPC] D10_APC_2: 0x3fffff
9968 12:38:48.482611 INFO: [APUAPC] D10_APC_3: 0x0
9969 12:38:48.486004 INFO: [APUAPC] D11_APC_0: 0xffffffff
9970 12:38:48.489481 INFO: [APUAPC] D11_APC_1: 0xffffffff
9971 12:38:48.492742 INFO: [APUAPC] D11_APC_2: 0x3fffff
9972 12:38:48.496362 INFO: [APUAPC] D11_APC_3: 0x0
9973 12:38:48.499261 INFO: [APUAPC] D12_APC_0: 0xffffffff
9974 12:38:48.502915 INFO: [APUAPC] D12_APC_1: 0xffffffff
9975 12:38:48.506224 INFO: [APUAPC] D12_APC_2: 0x3fffff
9976 12:38:48.509541 INFO: [APUAPC] D12_APC_3: 0x0
9977 12:38:48.512788 INFO: [APUAPC] D13_APC_0: 0xffffffff
9978 12:38:48.516456 INFO: [APUAPC] D13_APC_1: 0xffffffff
9979 12:38:48.519294 INFO: [APUAPC] D13_APC_2: 0x3fffff
9980 12:38:48.522567 INFO: [APUAPC] D13_APC_3: 0x0
9981 12:38:48.526012 INFO: [APUAPC] D14_APC_0: 0xffffffff
9982 12:38:48.529105 INFO: [APUAPC] D14_APC_1: 0xffffffff
9983 12:38:48.532608 INFO: [APUAPC] D14_APC_2: 0x3fffff
9984 12:38:48.536563 INFO: [APUAPC] D14_APC_3: 0x0
9985 12:38:48.539486 INFO: [APUAPC] D15_APC_0: 0xffffffff
9986 12:38:48.542970 INFO: [APUAPC] D15_APC_1: 0xffffffff
9987 12:38:48.546257 INFO: [APUAPC] D15_APC_2: 0x3fffff
9988 12:38:48.549338 INFO: [APUAPC] D15_APC_3: 0x0
9989 12:38:48.552478 INFO: [APUAPC] APC_CON: 0x4
9990 12:38:48.555972 INFO: [NOCDAPC] D0_APC_0: 0x0
9991 12:38:48.559637 INFO: [NOCDAPC] D0_APC_1: 0x0
9992 12:38:48.562826 INFO: [NOCDAPC] D1_APC_0: 0x0
9993 12:38:48.565938 INFO: [NOCDAPC] D1_APC_1: 0xfff
9994 12:38:48.569481 INFO: [NOCDAPC] D2_APC_0: 0x0
9995 12:38:48.569592 INFO: [NOCDAPC] D2_APC_1: 0xfff
9996 12:38:48.572535 INFO: [NOCDAPC] D3_APC_0: 0x0
9997 12:38:48.576029 INFO: [NOCDAPC] D3_APC_1: 0xfff
9998 12:38:48.579221 INFO: [NOCDAPC] D4_APC_0: 0x0
9999 12:38:48.582858 INFO: [NOCDAPC] D4_APC_1: 0xfff
10000 12:38:48.585857 INFO: [NOCDAPC] D5_APC_0: 0x0
10001 12:38:48.589029 INFO: [NOCDAPC] D5_APC_1: 0xfff
10002 12:38:48.592834 INFO: [NOCDAPC] D6_APC_0: 0x0
10003 12:38:48.595907 INFO: [NOCDAPC] D6_APC_1: 0xfff
10004 12:38:48.599594 INFO: [NOCDAPC] D7_APC_0: 0x0
10005 12:38:48.602332 INFO: [NOCDAPC] D7_APC_1: 0xfff
10006 12:38:48.602478 INFO: [NOCDAPC] D8_APC_0: 0x0
10007 12:38:48.605963 INFO: [NOCDAPC] D8_APC_1: 0xfff
10008 12:38:48.609502 INFO: [NOCDAPC] D9_APC_0: 0x0
10009 12:38:48.612535 INFO: [NOCDAPC] D9_APC_1: 0xfff
10010 12:38:48.615938 INFO: [NOCDAPC] D10_APC_0: 0x0
10011 12:38:48.619477 INFO: [NOCDAPC] D10_APC_1: 0xfff
10012 12:38:48.622376 INFO: [NOCDAPC] D11_APC_0: 0x0
10013 12:38:48.626168 INFO: [NOCDAPC] D11_APC_1: 0xfff
10014 12:38:48.629699 INFO: [NOCDAPC] D12_APC_0: 0x0
10015 12:38:48.633152 INFO: [NOCDAPC] D12_APC_1: 0xfff
10016 12:38:48.636328 INFO: [NOCDAPC] D13_APC_0: 0x0
10017 12:38:48.639080 INFO: [NOCDAPC] D13_APC_1: 0xfff
10018 12:38:48.639159 INFO: [NOCDAPC] D14_APC_0: 0x0
10019 12:38:48.642890 INFO: [NOCDAPC] D14_APC_1: 0xfff
10020 12:38:48.645745 INFO: [NOCDAPC] D15_APC_0: 0x0
10021 12:38:48.649632 INFO: [NOCDAPC] D15_APC_1: 0xfff
10022 12:38:48.652636 INFO: [NOCDAPC] APC_CON: 0x4
10023 12:38:48.656150 INFO: [APUAPC] set_apusys_apc done
10024 12:38:48.659603 INFO: [DEVAPC] devapc_init done
10025 12:38:48.662864 INFO: GICv3 without legacy support detected.
10026 12:38:48.669752 INFO: ARM GICv3 driver initialized in EL3
10027 12:38:48.672727 INFO: Maximum SPI INTID supported: 639
10028 12:38:48.675934 INFO: BL31: Initializing runtime services
10029 12:38:48.682812 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10030 12:38:48.682893 INFO: SPM: enable CPC mode
10031 12:38:48.689248 INFO: mcdi ready for mcusys-off-idle and system suspend
10032 12:38:48.692939 INFO: BL31: Preparing for EL3 exit to normal world
10033 12:38:48.696119 INFO: Entry point address = 0x80000000
10034 12:38:48.699596 INFO: SPSR = 0x8
10035 12:38:48.705238
10036 12:38:48.705317
10037 12:38:48.705381
10038 12:38:48.708574 Starting depthcharge on Spherion...
10039 12:38:48.708654
10040 12:38:48.708717 Wipe memory regions:
10041 12:38:48.708777
10042 12:38:48.709510 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10043 12:38:48.709647 start: 2.2.4 bootloader-commands (timeout 00:04:21) [common]
10044 12:38:48.709766 Setting prompt string to ['asurada:']
10045 12:38:48.709874 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:21)
10046 12:38:48.712163 [0x00000040000000, 0x00000054600000)
10047 12:38:48.834673
10048 12:38:48.834811 [0x00000054660000, 0x00000080000000)
10049 12:38:49.094658
10050 12:38:49.094798 [0x000000821a7280, 0x000000ffe64000)
10051 12:38:49.839416
10052 12:38:49.839552 [0x00000100000000, 0x00000240000000)
10053 12:38:51.730124
10054 12:38:51.733577 Initializing XHCI USB controller at 0x11200000.
10055 12:38:52.771586
10056 12:38:52.774594 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10057 12:38:52.774678
10058 12:38:52.774742
10059 12:38:52.774802
10060 12:38:52.775081 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10062 12:38:52.875443 asurada: tftpboot 192.168.201.1 12703511/tftp-deploy-446whshk/kernel/image.itb 12703511/tftp-deploy-446whshk/kernel/cmdline
10063 12:38:52.875629 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10064 12:38:52.875751 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:17)
10065 12:38:52.880016 tftpboot 192.168.201.1 12703511/tftp-deploy-446whshk/kernel/image.ittp-deploy-446whshk/kernel/cmdline
10066 12:38:52.880099
10067 12:38:52.880162 Waiting for link
10068 12:38:53.040565
10069 12:38:53.040693 R8152: Initializing
10070 12:38:53.040762
10071 12:38:53.043683 Version 6 (ocp_data = 5c30)
10072 12:38:53.043835
10073 12:38:53.047615 R8152: Done initializing
10074 12:38:53.047696
10075 12:38:53.047760 Adding net device
10076 12:38:55.091660
10077 12:38:55.091835 done.
10078 12:38:55.091904
10079 12:38:55.091965 MAC: 00:24:32:30:78:52
10080 12:38:55.092023
10081 12:38:55.095169 Sending DHCP discover... done.
10082 12:38:55.095250
10083 12:39:02.399553 Waiting for reply... done.
10084 12:39:02.399701
10085 12:39:02.399771 Sending DHCP request... done.
10086 12:39:02.402538
10087 12:39:02.407127 Waiting for reply... done.
10088 12:39:02.407207
10089 12:39:02.407271 My ip is 192.168.201.14
10090 12:39:02.407332
10091 12:39:02.410844 The DHCP server ip is 192.168.201.1
10092 12:39:02.410925
10093 12:39:02.417043 TFTP server IP predefined by user: 192.168.201.1
10094 12:39:02.417125
10095 12:39:02.424024 Bootfile predefined by user: 12703511/tftp-deploy-446whshk/kernel/image.itb
10096 12:39:02.424105
10097 12:39:02.424169 Sending tftp read request... done.
10098 12:39:02.427358
10099 12:39:02.431452 Waiting for the transfer...
10100 12:39:02.431533
10101 12:39:02.977316 00000000 ################################################################
10102 12:39:02.977483
10103 12:39:03.532578 00080000 ################################################################
10104 12:39:03.532714
10105 12:39:04.079699 00100000 ################################################################
10106 12:39:04.079846
10107 12:39:04.624140 00180000 ################################################################
10108 12:39:04.624285
10109 12:39:05.161158 00200000 ################################################################
10110 12:39:05.161289
10111 12:39:05.707916 00280000 ################################################################
10112 12:39:05.708079
10113 12:39:06.252084 00300000 ################################################################
10114 12:39:06.252221
10115 12:39:06.799992 00380000 ################################################################
10116 12:39:06.800120
10117 12:39:07.342836 00400000 ################################################################
10118 12:39:07.342978
10119 12:39:07.888147 00480000 ################################################################
10120 12:39:07.888313
10121 12:39:08.433355 00500000 ################################################################
10122 12:39:08.433504
10123 12:39:08.984709 00580000 ################################################################
10124 12:39:08.984880
10125 12:39:09.531281 00600000 ################################################################
10126 12:39:09.531446
10127 12:39:10.076304 00680000 ################################################################
10128 12:39:10.076447
10129 12:39:10.616415 00700000 ################################################################
10130 12:39:10.616599
10131 12:39:11.164752 00780000 ################################################################
10132 12:39:11.164894
10133 12:39:11.709216 00800000 ################################################################
10134 12:39:11.709360
10135 12:39:12.265973 00880000 ################################################################
10136 12:39:12.266109
10137 12:39:12.818791 00900000 ################################################################
10138 12:39:12.818935
10139 12:39:13.385205 00980000 ################################################################
10140 12:39:13.385350
10141 12:39:13.932102 00a00000 ################################################################
10142 12:39:13.932237
10143 12:39:14.482165 00a80000 ################################################################
10144 12:39:14.482336
10145 12:39:15.031955 00b00000 ################################################################
10146 12:39:15.032090
10147 12:39:15.583059 00b80000 ################################################################
10148 12:39:15.583205
10149 12:39:16.134334 00c00000 ################################################################
10150 12:39:16.134479
10151 12:39:16.686061 00c80000 ################################################################
10152 12:39:16.686223
10153 12:39:17.232844 00d00000 ################################################################
10154 12:39:17.233006
10155 12:39:17.788225 00d80000 ################################################################
10156 12:39:17.788399
10157 12:39:18.344703 00e00000 ################################################################
10158 12:39:18.344844
10159 12:39:18.897775 00e80000 ################################################################
10160 12:39:18.897923
10161 12:39:19.460388 00f00000 ################################################################
10162 12:39:19.460536
10163 12:39:20.011450 00f80000 ################################################################
10164 12:39:20.011593
10165 12:39:20.560983 01000000 ################################################################
10166 12:39:20.561130
10167 12:39:21.109868 01080000 ################################################################
10168 12:39:21.110010
10169 12:39:21.662753 01100000 ################################################################
10170 12:39:21.662897
10171 12:39:22.215133 01180000 ################################################################
10172 12:39:22.215273
10173 12:39:22.765012 01200000 ################################################################
10174 12:39:22.765153
10175 12:39:23.308858 01280000 ################################################################
10176 12:39:23.309037
10177 12:39:23.978201 01300000 ################################################################
10178 12:39:23.978840
10179 12:39:24.694714 01380000 ################################################################
10180 12:39:24.695441
10181 12:39:25.421147 01400000 ################################################################
10182 12:39:25.421657
10183 12:39:26.100128 01480000 ################################################################
10184 12:39:26.100705
10185 12:39:26.705468 01500000 ################################################################
10186 12:39:26.705623
10187 12:39:27.344202 01580000 ################################################################
10188 12:39:27.344699
10189 12:39:28.059811 01600000 ################################################################
10190 12:39:28.059957
10191 12:39:28.723403 01680000 ################################################################
10192 12:39:28.723905
10193 12:39:29.454883 01700000 ################################################################
10194 12:39:29.455371
10195 12:39:30.045720 01780000 ################################################################
10196 12:39:30.045900
10197 12:39:30.618529 01800000 ################################################################
10198 12:39:30.618694
10199 12:39:31.186620 01880000 ################################################################
10200 12:39:31.186788
10201 12:39:31.779377 01900000 ################################################################
10202 12:39:31.779516
10203 12:39:32.369798 01980000 ################################################################
10204 12:39:32.369940
10205 12:39:32.969879 01a00000 ################################################################
10206 12:39:32.970019
10207 12:39:33.550891 01a80000 ################################################################
10208 12:39:33.551038
10209 12:39:34.094987 01b00000 ################################################################
10210 12:39:34.095133
10211 12:39:34.661629 01b80000 ################################################################
10212 12:39:34.661771
10213 12:39:35.228307 01c00000 ################################################################
10214 12:39:35.228449
10215 12:39:35.771402 01c80000 ################################################################
10216 12:39:35.771553
10217 12:39:36.324761 01d00000 ################################################################
10218 12:39:36.324892
10219 12:39:36.881510 01d80000 ################################################################
10220 12:39:36.881692
10221 12:39:37.432506 01e00000 ################################################################
10222 12:39:37.432645
10223 12:39:38.045001 01e80000 ################################################################
10224 12:39:38.045141
10225 12:39:38.721436 01f00000 ################################################################
10226 12:39:38.721589
10227 12:39:39.359039 01f80000 ################################################################
10228 12:39:39.359183
10229 12:39:39.923350 02000000 ################################################################
10230 12:39:39.923488
10231 12:39:40.519263 02080000 ################################################################
10232 12:39:40.519407
10233 12:39:41.212851 02100000 ################################################################
10234 12:39:41.212999
10235 12:39:41.859850 02180000 ################################################################
10236 12:39:41.860000
10237 12:39:42.440170 02200000 ################################################################
10238 12:39:42.440601
10239 12:39:43.068511 02280000 ################################################################
10240 12:39:43.068640
10241 12:39:43.663635 02300000 ################################################################
10242 12:39:43.663770
10243 12:39:44.266910 02380000 ################################################################
10244 12:39:44.267505
10245 12:39:44.935994 02400000 ################################################################
10246 12:39:44.936302
10247 12:39:45.591172 02480000 ################################################################
10248 12:39:45.591720
10249 12:39:46.227087 02500000 ################################################################
10250 12:39:46.227237
10251 12:39:46.800462 02580000 ################################################################
10252 12:39:46.800612
10253 12:39:47.443667 02600000 ################################################################
10254 12:39:47.443955
10255 12:39:48.052564 02680000 ################################################################
10256 12:39:48.052703
10257 12:39:48.664945 02700000 ################################################################
10258 12:39:48.665111
10259 12:39:49.271004 02780000 ################################################################
10260 12:39:49.271171
10261 12:39:49.843300 02800000 ################################################################
10262 12:39:49.843429
10263 12:39:50.389733 02880000 ################################################################
10264 12:39:50.389872
10265 12:39:50.937467 02900000 ################################################################
10266 12:39:50.937602
10267 12:39:51.515811 02980000 ################################################################
10268 12:39:51.515955
10269 12:39:52.076191 02a00000 ################################################################
10270 12:39:52.076335
10271 12:39:52.612323 02a80000 ################################################################
10272 12:39:52.612473
10273 12:39:53.165300 02b00000 ################################################################
10274 12:39:53.165449
10275 12:39:53.785493 02b80000 ################################################################
10276 12:39:53.785633
10277 12:39:54.391698 02c00000 ################################################################
10278 12:39:54.391843
10279 12:39:54.981878 02c80000 ################################################################
10280 12:39:54.982021
10281 12:39:55.531099 02d00000 ################################################################
10282 12:39:55.531246
10283 12:39:56.093506 02d80000 ################################################################
10284 12:39:56.093643
10285 12:39:56.726415 02e00000 ################################################################
10286 12:39:56.726567
10287 12:39:57.285309 02e80000 ################################################################
10288 12:39:57.285454
10289 12:39:57.859921 02f00000 ################################################################
10290 12:39:57.860086
10291 12:39:58.409907 02f80000 ################################################################
10292 12:39:58.410052
10293 12:39:58.957775 03000000 ################################################################
10294 12:39:58.957911
10295 12:39:59.523124 03080000 ################################################################
10296 12:39:59.523272
10297 12:40:00.119726 03100000 ################################################################
10298 12:40:00.119884
10299 12:40:00.692280 03180000 ################################################################
10300 12:40:00.692433
10301 12:40:01.273449 03200000 ################################################################
10302 12:40:01.273614
10303 12:40:01.852391 03280000 ################################################################
10304 12:40:01.852554
10305 12:40:02.423833 03300000 ################################################################
10306 12:40:02.423983
10307 12:40:02.988848 03380000 ################################################################
10308 12:40:02.989007
10309 12:40:03.550359 03400000 ################################################################
10310 12:40:03.550551
10311 12:40:04.120449 03480000 ################################################################
10312 12:40:04.120606
10313 12:40:04.679067 03500000 ################################################################
10314 12:40:04.679226
10315 12:40:05.267404 03580000 ################################################################
10316 12:40:05.267558
10317 12:40:05.838409 03600000 ################################################################
10318 12:40:05.838596
10319 12:40:06.424277 03680000 ################################################################
10320 12:40:06.424425
10321 12:40:07.019291 03700000 ################################################################
10322 12:40:07.019445
10323 12:40:07.579656 03780000 ################################################################
10324 12:40:07.579806
10325 12:40:08.148617 03800000 ################################################################
10326 12:40:08.148802
10327 12:40:08.707602 03880000 ################################################################
10328 12:40:08.707754
10329 12:40:09.265723 03900000 ################################################################
10330 12:40:09.265919
10331 12:40:09.827802 03980000 ################################################################
10332 12:40:09.827990
10333 12:40:10.396016 03a00000 ################################################################
10334 12:40:10.396165
10335 12:40:10.956591 03a80000 ################################################################
10336 12:40:10.956782
10337 12:40:11.520542 03b00000 ################################################################
10338 12:40:11.520694
10339 12:40:12.093376 03b80000 ################################################################
10340 12:40:12.093527
10341 12:40:12.647018 03c00000 ################################################################
10342 12:40:12.647169
10343 12:40:13.292730 03c80000 ################################################################
10344 12:40:13.293213
10345 12:40:13.996608 03d00000 ################################################################
10346 12:40:13.997129
10347 12:40:14.698874 03d80000 ################################################################
10348 12:40:14.699394
10349 12:40:15.393057 03e00000 ################################################################
10350 12:40:15.393557
10351 12:40:16.097083 03e80000 ################################################################
10352 12:40:16.097587
10353 12:40:16.792797 03f00000 ################################################################
10354 12:40:16.793336
10355 12:40:17.513595 03f80000 ################################################################
10356 12:40:17.514116
10357 12:40:18.208448 04000000 ################################################################
10358 12:40:18.208587
10359 12:40:18.887060 04080000 ################################################################
10360 12:40:18.887565
10361 12:40:19.395602 04100000 ############################################### done.
10362 12:40:19.396091
10363 12:40:19.398541 The bootfile was 68536074 bytes long.
10364 12:40:19.398962
10365 12:40:19.402546 Sending tftp read request... done.
10366 12:40:19.402961
10367 12:40:19.405462 Waiting for the transfer...
10368 12:40:19.405874
10369 12:40:19.408951 00000000 # done.
10370 12:40:19.409373
10371 12:40:19.415125 Command line loaded dynamically from TFTP file: 12703511/tftp-deploy-446whshk/kernel/cmdline
10372 12:40:19.415672
10373 12:40:19.428614 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10374 12:40:19.429098
10375 12:40:19.432023 Loading FIT.
10376 12:40:19.432436
10377 12:40:19.435536 Image ramdisk-1 has 56433903 bytes.
10378 12:40:19.435950
10379 12:40:19.436278 Image fdt-1 has 47278 bytes.
10380 12:40:19.436581
10381 12:40:19.438822 Image kernel-1 has 12052857 bytes.
10382 12:40:19.439248
10383 12:40:19.448646 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10384 12:40:19.449157
10385 12:40:19.465343 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10386 12:40:19.465839
10387 12:40:19.471948 Choosing best match conf-1 for compat google,spherion-rev2.
10388 12:40:19.475772
10389 12:40:19.480695 Connected to device vid:did:rid of 1ae0:0028:00
10390 12:40:19.488569
10391 12:40:19.492292 tpm_get_response: command 0x17b, return code 0x0
10392 12:40:19.492716
10393 12:40:19.495248 ec_init: CrosEC protocol v3 supported (256, 248)
10394 12:40:19.499119
10395 12:40:19.502727 tpm_cleanup: add release locality here.
10396 12:40:19.503139
10397 12:40:19.503465 Shutting down all USB controllers.
10398 12:40:19.503770
10399 12:40:19.505561 Removing current net device
10400 12:40:19.505978
10401 12:40:19.512606 Exiting depthcharge with code 4 at timestamp: 120252599
10402 12:40:19.513085
10403 12:40:19.516158 LZMA decompressing kernel-1 to 0x821a6718
10404 12:40:19.516572
10405 12:40:19.519196 LZMA decompressing kernel-1 to 0x40000000
10406 12:40:21.019194
10407 12:40:21.019670 jumping to kernel
10408 12:40:21.021691 end: 2.2.4 bootloader-commands (duration 00:01:32) [common]
10409 12:40:21.022224 start: 2.2.5 auto-login-action (timeout 00:02:49) [common]
10410 12:40:21.022653 Setting prompt string to ['Linux version [0-9]']
10411 12:40:21.023001 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10412 12:40:21.023342 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10413 12:40:21.101006
10414 12:40:21.104727 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10415 12:40:21.108175 start: 2.2.5.1 login-action (timeout 00:02:49) [common]
10416 12:40:21.108744 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10417 12:40:21.109115 Setting prompt string to []
10418 12:40:21.109507 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10419 12:40:21.109877 Using line separator: #'\n'#
10420 12:40:21.110218 No login prompt set.
10421 12:40:21.110686 Parsing kernel messages
10422 12:40:21.110981 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10423 12:40:21.111491 [login-action] Waiting for messages, (timeout 00:02:49)
10424 12:40:21.111820 Waiting using forced prompt support (timeout 00:01:24)
10425 12:40:21.127927 [ 0.000000] Linux version 6.1.75-cip14 (KernelCI@build-j98433-arm64-gcc-10-defconfig-arm64-chromebook-89n64) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Feb 5 12:20:06 UTC 2024
10426 12:40:21.131205 [ 0.000000] random: crng init done
10427 12:40:21.134836 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10428 12:40:21.137675 [ 0.000000] efi: UEFI not found.
10429 12:40:21.148152 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10430 12:40:21.154967 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10431 12:40:21.164726 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10432 12:40:21.174653 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10433 12:40:21.181272 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10434 12:40:21.184423 [ 0.000000] printk: bootconsole [mtk8250] enabled
10435 12:40:21.193029 [ 0.000000] NUMA: No NUMA configuration found
10436 12:40:21.199261 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10437 12:40:21.206302 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10438 12:40:21.206918 [ 0.000000] Zone ranges:
10439 12:40:21.212561 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10440 12:40:21.216306 [ 0.000000] DMA32 empty
10441 12:40:21.222581 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10442 12:40:21.226333 [ 0.000000] Movable zone start for each node
10443 12:40:21.229818 [ 0.000000] Early memory node ranges
10444 12:40:21.236331 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10445 12:40:21.242834 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10446 12:40:21.249171 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10447 12:40:21.255915 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10448 12:40:21.262982 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10449 12:40:21.269128 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10450 12:40:21.325415 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10451 12:40:21.331777 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10452 12:40:21.338755 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10453 12:40:21.342239 [ 0.000000] psci: probing for conduit method from DT.
10454 12:40:21.348599 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10455 12:40:21.351954 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10456 12:40:21.358719 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10457 12:40:21.362353 [ 0.000000] psci: SMC Calling Convention v1.2
10458 12:40:21.369142 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10459 12:40:21.372100 [ 0.000000] Detected VIPT I-cache on CPU0
10460 12:40:21.378532 [ 0.000000] CPU features: detected: GIC system register CPU interface
10461 12:40:21.386292 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10462 12:40:21.392211 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10463 12:40:21.399049 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10464 12:40:21.405677 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10465 12:40:21.412101 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10466 12:40:21.418821 [ 0.000000] alternatives: applying boot alternatives
10467 12:40:21.422373 [ 0.000000] Fallback order for Node 0: 0
10468 12:40:21.428917 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10469 12:40:21.432087 [ 0.000000] Policy zone: Normal
10470 12:40:21.448628 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10471 12:40:21.458308 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10472 12:40:21.469617 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10473 12:40:21.479444 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10474 12:40:21.486543 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10475 12:40:21.489763 <6>[ 0.000000] software IO TLB: area num 8.
10476 12:40:21.546998 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10477 12:40:21.695291 <6>[ 0.000000] Memory: 7912144K/8385536K available (17984K kernel code, 4118K rwdata, 19612K rodata, 8448K init, 616K bss, 440624K reserved, 32768K cma-reserved)
10478 12:40:21.702323 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10479 12:40:21.708350 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10480 12:40:21.711903 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10481 12:40:21.718819 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10482 12:40:21.725316 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10483 12:40:21.728845 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10484 12:40:21.738069 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10485 12:40:21.744793 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10486 12:40:21.749060 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10487 12:40:21.755928 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10488 12:40:21.759675 <6>[ 0.000000] GICv3: 608 SPIs implemented
10489 12:40:21.765966 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10490 12:40:21.769242 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10491 12:40:21.772452 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10492 12:40:21.779571 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10493 12:40:21.792977 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10494 12:40:21.806792 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10495 12:40:21.813551 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10496 12:40:21.821600 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10497 12:40:21.835006 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10498 12:40:21.841684 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10499 12:40:21.848761 <6>[ 0.009183] Console: colour dummy device 80x25
10500 12:40:21.857957 <6>[ 0.013909] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10501 12:40:21.861409 <6>[ 0.024351] pid_max: default: 32768 minimum: 301
10502 12:40:21.867933 <6>[ 0.029222] LSM: Security Framework initializing
10503 12:40:21.874977 <6>[ 0.034163] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10504 12:40:21.884639 <6>[ 0.042027] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10505 12:40:21.891109 <6>[ 0.051484] cblist_init_generic: Setting adjustable number of callback queues.
10506 12:40:21.898311 <6>[ 0.058975] cblist_init_generic: Setting shift to 3 and lim to 1.
10507 12:40:21.908391 <6>[ 0.065352] cblist_init_generic: Setting adjustable number of callback queues.
10508 12:40:21.911020 <6>[ 0.072780] cblist_init_generic: Setting shift to 3 and lim to 1.
10509 12:40:21.917940 <6>[ 0.079182] rcu: Hierarchical SRCU implementation.
10510 12:40:21.924812 <6>[ 0.084228] rcu: Max phase no-delay instances is 1000.
10511 12:40:21.931754 <6>[ 0.091289] EFI services will not be available.
10512 12:40:21.934517 <6>[ 0.096271] smp: Bringing up secondary CPUs ...
10513 12:40:21.942233 <6>[ 0.101324] Detected VIPT I-cache on CPU1
10514 12:40:21.949008 <6>[ 0.101393] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10515 12:40:21.956525 <6>[ 0.101424] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10516 12:40:21.958990 <6>[ 0.101757] Detected VIPT I-cache on CPU2
10517 12:40:21.965668 <6>[ 0.101803] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10518 12:40:21.972102 <6>[ 0.101820] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10519 12:40:21.978618 <6>[ 0.102073] Detected VIPT I-cache on CPU3
10520 12:40:21.985375 <6>[ 0.102121] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10521 12:40:21.992233 <6>[ 0.102136] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10522 12:40:21.995804 <6>[ 0.102442] CPU features: detected: Spectre-v4
10523 12:40:22.002646 <6>[ 0.102449] CPU features: detected: Spectre-BHB
10524 12:40:22.005675 <6>[ 0.102454] Detected PIPT I-cache on CPU4
10525 12:40:22.011883 <6>[ 0.102511] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10526 12:40:22.019052 <6>[ 0.102527] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10527 12:40:22.026044 <6>[ 0.102823] Detected PIPT I-cache on CPU5
10528 12:40:22.032899 <6>[ 0.102886] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10529 12:40:22.039205 <6>[ 0.102903] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10530 12:40:22.041792 <6>[ 0.103183] Detected PIPT I-cache on CPU6
10531 12:40:22.049063 <6>[ 0.103247] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10532 12:40:22.056192 <6>[ 0.103263] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10533 12:40:22.062221 <6>[ 0.103561] Detected PIPT I-cache on CPU7
10534 12:40:22.068999 <6>[ 0.103625] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10535 12:40:22.075293 <6>[ 0.103641] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10536 12:40:22.078805 <6>[ 0.103688] smp: Brought up 1 node, 8 CPUs
10537 12:40:22.082598 <6>[ 0.245088] SMP: Total of 8 processors activated.
10538 12:40:22.088889 <6>[ 0.250009] CPU features: detected: 32-bit EL0 Support
10539 12:40:22.099185 <6>[ 0.255371] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10540 12:40:22.105542 <6>[ 0.264171] CPU features: detected: Common not Private translations
10541 12:40:22.109249 <6>[ 0.270647] CPU features: detected: CRC32 instructions
10542 12:40:22.115613 <6>[ 0.276032] CPU features: detected: RCpc load-acquire (LDAPR)
10543 12:40:22.122818 <6>[ 0.281991] CPU features: detected: LSE atomic instructions
10544 12:40:22.129688 <6>[ 0.287808] CPU features: detected: Privileged Access Never
10545 12:40:22.132026 <6>[ 0.293588] CPU features: detected: RAS Extension Support
10546 12:40:22.138833 <6>[ 0.299231] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10547 12:40:22.145919 <6>[ 0.306451] CPU: All CPU(s) started at EL2
10548 12:40:22.149485 <6>[ 0.310768] alternatives: applying system-wide alternatives
10549 12:40:22.160184 <6>[ 0.321459] devtmpfs: initialized
10550 12:40:22.172516 <6>[ 0.330413] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10551 12:40:22.182124 <6>[ 0.340372] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10552 12:40:22.188683 <6>[ 0.348516] pinctrl core: initialized pinctrl subsystem
10553 12:40:22.192406 <6>[ 0.355159] DMI not present or invalid.
10554 12:40:22.198675 <6>[ 0.359573] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10555 12:40:22.209225 <6>[ 0.366430] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10556 12:40:22.215263 <6>[ 0.374018] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10557 12:40:22.225377 <6>[ 0.382243] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10558 12:40:22.228455 <6>[ 0.390488] audit: initializing netlink subsys (disabled)
10559 12:40:22.239052 <5>[ 0.396180] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10560 12:40:22.245811 <6>[ 0.396883] thermal_sys: Registered thermal governor 'step_wise'
10561 12:40:22.252061 <6>[ 0.404147] thermal_sys: Registered thermal governor 'power_allocator'
10562 12:40:22.255941 <6>[ 0.410403] cpuidle: using governor menu
10563 12:40:22.258961 <6>[ 0.421363] NET: Registered PF_QIPCRTR protocol family
10564 12:40:22.268847 <6>[ 0.426835] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10565 12:40:22.271752 <6>[ 0.433938] ASID allocator initialised with 32768 entries
10566 12:40:22.279399 <6>[ 0.440508] Serial: AMBA PL011 UART driver
10567 12:40:22.288008 <4>[ 0.449318] Trying to register duplicate clock ID: 134
10568 12:40:22.344648 <6>[ 0.508942] KASLR enabled
10569 12:40:22.359237 <6>[ 0.516835] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10570 12:40:22.365741 <6>[ 0.523849] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10571 12:40:22.372282 <6>[ 0.530336] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10572 12:40:22.379382 <6>[ 0.537341] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10573 12:40:22.386054 <6>[ 0.543829] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10574 12:40:22.392041 <6>[ 0.550833] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10575 12:40:22.398652 <6>[ 0.557321] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10576 12:40:22.405571 <6>[ 0.564328] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10577 12:40:22.409030 <6>[ 0.571787] ACPI: Interpreter disabled.
10578 12:40:22.416759 <6>[ 0.578222] iommu: Default domain type: Translated
10579 12:40:22.423535 <6>[ 0.583336] iommu: DMA domain TLB invalidation policy: strict mode
10580 12:40:22.426994 <5>[ 0.590004] SCSI subsystem initialized
10581 12:40:22.433375 <6>[ 0.594174] usbcore: registered new interface driver usbfs
10582 12:40:22.440858 <6>[ 0.599908] usbcore: registered new interface driver hub
10583 12:40:22.443603 <6>[ 0.605456] usbcore: registered new device driver usb
10584 12:40:22.450094 <6>[ 0.611566] pps_core: LinuxPPS API ver. 1 registered
10585 12:40:22.459839 <6>[ 0.616763] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10586 12:40:22.463548 <6>[ 0.626112] PTP clock support registered
10587 12:40:22.466769 <6>[ 0.630358] EDAC MC: Ver: 3.0.0
10588 12:40:22.473960 <6>[ 0.635517] FPGA manager framework
10589 12:40:22.480746 <6>[ 0.639199] Advanced Linux Sound Architecture Driver Initialized.
10590 12:40:22.483654 <6>[ 0.645983] vgaarb: loaded
10591 12:40:22.490384 <6>[ 0.649128] clocksource: Switched to clocksource arch_sys_counter
10592 12:40:22.493866 <5>[ 0.655568] VFS: Disk quotas dquot_6.6.0
10593 12:40:22.500982 <6>[ 0.659751] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10594 12:40:22.503878 <6>[ 0.666940] pnp: PnP ACPI: disabled
10595 12:40:22.512066 <6>[ 0.673567] NET: Registered PF_INET protocol family
10596 12:40:22.522813 <6>[ 0.679157] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10597 12:40:22.533607 <6>[ 0.691494] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10598 12:40:22.542960 <6>[ 0.700310] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10599 12:40:22.550030 <6>[ 0.708279] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10600 12:40:22.556327 <6>[ 0.716980] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10601 12:40:22.568733 <6>[ 0.726741] TCP: Hash tables configured (established 65536 bind 65536)
10602 12:40:22.575516 <6>[ 0.733606] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10603 12:40:22.582059 <6>[ 0.740804] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10604 12:40:22.589244 <6>[ 0.748509] NET: Registered PF_UNIX/PF_LOCAL protocol family
10605 12:40:22.595115 <6>[ 0.754673] RPC: Registered named UNIX socket transport module.
10606 12:40:22.598341 <6>[ 0.760826] RPC: Registered udp transport module.
10607 12:40:22.605659 <6>[ 0.765759] RPC: Registered tcp transport module.
10608 12:40:22.611751 <6>[ 0.770692] RPC: Registered tcp NFSv4.1 backchannel transport module.
10609 12:40:22.615073 <6>[ 0.777357] PCI: CLS 0 bytes, default 64
10610 12:40:22.618179 <6>[ 0.781692] Unpacking initramfs...
10611 12:40:22.642906 <6>[ 0.801248] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10612 12:40:22.652975 <6>[ 0.809888] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10613 12:40:22.656381 <6>[ 0.818734] kvm [1]: IPA Size Limit: 40 bits
10614 12:40:22.663605 <6>[ 0.823260] kvm [1]: GICv3: no GICV resource entry
10615 12:40:22.666112 <6>[ 0.828280] kvm [1]: disabling GICv2 emulation
10616 12:40:22.672743 <6>[ 0.832969] kvm [1]: GIC system register CPU interface enabled
10617 12:40:22.677149 <6>[ 0.839127] kvm [1]: vgic interrupt IRQ18
10618 12:40:22.683344 <6>[ 0.843486] kvm [1]: VHE mode initialized successfully
10619 12:40:22.689510 <5>[ 0.849970] Initialise system trusted keyrings
10620 12:40:22.696319 <6>[ 0.854810] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10621 12:40:22.703350 <6>[ 0.864836] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10622 12:40:22.709736 <5>[ 0.871241] NFS: Registering the id_resolver key type
10623 12:40:22.713691 <5>[ 0.876542] Key type id_resolver registered
10624 12:40:22.720383 <5>[ 0.880958] Key type id_legacy registered
10625 12:40:22.726583 <6>[ 0.885237] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10626 12:40:22.733264 <6>[ 0.892160] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10627 12:40:22.739698 <6>[ 0.899874] 9p: Installing v9fs 9p2000 file system support
10628 12:40:22.776444 <5>[ 0.937795] Key type asymmetric registered
10629 12:40:22.779414 <5>[ 0.942126] Asymmetric key parser 'x509' registered
10630 12:40:22.789339 <6>[ 0.947270] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10631 12:40:22.793152 <6>[ 0.954885] io scheduler mq-deadline registered
10632 12:40:22.796894 <6>[ 0.959666] io scheduler kyber registered
10633 12:40:22.815254 <6>[ 0.976828] EINJ: ACPI disabled.
10634 12:40:22.847927 <4>[ 1.002601] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10635 12:40:22.858175 <4>[ 1.013238] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10636 12:40:22.872280 <6>[ 1.034108] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10637 12:40:22.880277 <6>[ 1.042119] printk: console [ttyS0] disabled
10638 12:40:22.908356 <6>[ 1.066745] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10639 12:40:22.914791 <6>[ 1.076218] printk: console [ttyS0] enabled
10640 12:40:22.918189 <6>[ 1.076218] printk: console [ttyS0] enabled
10641 12:40:22.925295 <6>[ 1.085110] printk: bootconsole [mtk8250] disabled
10642 12:40:22.928314 <6>[ 1.085110] printk: bootconsole [mtk8250] disabled
10643 12:40:22.934860 <6>[ 1.096324] SuperH (H)SCI(F) driver initialized
10644 12:40:22.938583 <6>[ 1.101615] msm_serial: driver initialized
10645 12:40:22.951977 <6>[ 1.110547] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10646 12:40:22.962000 <6>[ 1.119094] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10647 12:40:22.969486 <6>[ 1.127637] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10648 12:40:22.978742 <6>[ 1.136266] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10649 12:40:22.985136 <6>[ 1.144973] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10650 12:40:22.995273 <6>[ 1.153695] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10651 12:40:23.005392 <6>[ 1.162237] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10652 12:40:23.011719 <6>[ 1.171038] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10653 12:40:23.022157 <6>[ 1.179581] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10654 12:40:23.033662 <6>[ 1.195187] loop: module loaded
10655 12:40:23.040314 <6>[ 1.201176] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10656 12:40:23.063765 <4>[ 1.224501] mtk-pmic-keys: Failed to locate of_node [id: -1]
10657 12:40:23.070238 <6>[ 1.231529] megasas: 07.719.03.00-rc1
10658 12:40:23.080343 <6>[ 1.241297] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10659 12:40:23.087078 <6>[ 1.248519] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10660 12:40:23.103956 <6>[ 1.265341] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10661 12:40:23.160170 <6>[ 1.315534] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10662 12:40:25.039921 <6>[ 3.201979] Freeing initrd memory: 55108K
10663 12:40:25.051009 <6>[ 3.212499] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10664 12:40:25.061835 <6>[ 3.223378] tun: Universal TUN/TAP device driver, 1.6
10665 12:40:25.064972 <6>[ 3.229439] thunder_xcv, ver 1.0
10666 12:40:25.067673 <6>[ 3.232933] thunder_bgx, ver 1.0
10667 12:40:25.070957 <6>[ 3.236432] nicpf, ver 1.0
10668 12:40:25.081846 <6>[ 3.240456] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10669 12:40:25.084734 <6>[ 3.247932] hns3: Copyright (c) 2017 Huawei Corporation.
10670 12:40:25.088202 <6>[ 3.253520] hclge is initializing
10671 12:40:25.095092 <6>[ 3.257096] e1000: Intel(R) PRO/1000 Network Driver
10672 12:40:25.101359 <6>[ 3.262226] e1000: Copyright (c) 1999-2006 Intel Corporation.
10673 12:40:25.105286 <6>[ 3.268238] e1000e: Intel(R) PRO/1000 Network Driver
10674 12:40:25.111325 <6>[ 3.273453] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10675 12:40:25.118227 <6>[ 3.279638] igb: Intel(R) Gigabit Ethernet Network Driver
10676 12:40:25.124985 <6>[ 3.285287] igb: Copyright (c) 2007-2014 Intel Corporation.
10677 12:40:25.131620 <6>[ 3.291123] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10678 12:40:25.138349 <6>[ 3.297641] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10679 12:40:25.141265 <6>[ 3.304103] sky2: driver version 1.30
10680 12:40:25.148012 <6>[ 3.309086] VFIO - User Level meta-driver version: 0.3
10681 12:40:25.155257 <6>[ 3.317353] usbcore: registered new interface driver usb-storage
10682 12:40:25.161630 <6>[ 3.323796] usbcore: registered new device driver onboard-usb-hub
10683 12:40:25.170968 <6>[ 3.332946] mt6397-rtc mt6359-rtc: registered as rtc0
10684 12:40:25.180770 <6>[ 3.338410] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-05T12:40:47 UTC (1707136847)
10685 12:40:25.184583 <6>[ 3.347975] i2c_dev: i2c /dev entries driver
10686 12:40:25.200557 <6>[ 3.359640] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10687 12:40:25.220307 <6>[ 3.382643] cpu cpu0: EM: created perf domain
10688 12:40:25.223773 <6>[ 3.387568] cpu cpu4: EM: created perf domain
10689 12:40:25.231068 <6>[ 3.393164] sdhci: Secure Digital Host Controller Interface driver
10690 12:40:25.237272 <6>[ 3.399593] sdhci: Copyright(c) Pierre Ossman
10691 12:40:25.244197 <6>[ 3.404546] Synopsys Designware Multimedia Card Interface Driver
10692 12:40:25.250819 <6>[ 3.411182] sdhci-pltfm: SDHCI platform and OF driver helper
10693 12:40:25.254149 <6>[ 3.411239] mmc0: CQHCI version 5.10
10694 12:40:25.260804 <6>[ 3.421444] ledtrig-cpu: registered to indicate activity on CPUs
10695 12:40:25.267306 <6>[ 3.428554] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10696 12:40:25.273858 <6>[ 3.435626] usbcore: registered new interface driver usbhid
10697 12:40:25.277288 <6>[ 3.441447] usbhid: USB HID core driver
10698 12:40:25.283739 <6>[ 3.445655] spi_master spi0: will run message pump with realtime priority
10699 12:40:25.328456 <6>[ 3.484116] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10700 12:40:25.347493 <6>[ 3.499037] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10701 12:40:25.353553 <6>[ 3.514066] cros-ec-spi spi0.0: Chrome EC device registered
10702 12:40:25.362271 <6>[ 3.524372] mmc0: Command Queue Engine enabled
10703 12:40:25.369194 <6>[ 3.529128] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10704 12:40:25.375498 <6>[ 3.536573] mmcblk0: mmc0:0001 DA4128 116 GiB
10705 12:40:25.387077 <6>[ 3.549362] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10706 12:40:25.397427 <6>[ 3.549952] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10707 12:40:25.403322 <6>[ 3.556558] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10708 12:40:25.407052 <6>[ 3.565834] NET: Registered PF_PACKET protocol family
10709 12:40:25.413520 <6>[ 3.570504] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10710 12:40:25.417149 <6>[ 3.575194] 9pnet: Installing 9P2000 support
10711 12:40:25.423650 <6>[ 3.581330] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10712 12:40:25.430115 <5>[ 3.584883] Key type dns_resolver registered
10713 12:40:25.433500 <6>[ 3.596221] registered taskstats version 1
10714 12:40:25.436812 <5>[ 3.600584] Loading compiled-in X.509 certificates
10715 12:40:25.467760 <4>[ 3.623242] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10716 12:40:25.477869 <4>[ 3.633973] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10717 12:40:25.484309 <3>[ 3.644504] debugfs: File 'uA_load' in directory '/' already present!
10718 12:40:25.491160 <3>[ 3.651202] debugfs: File 'min_uV' in directory '/' already present!
10719 12:40:25.497795 <3>[ 3.657861] debugfs: File 'max_uV' in directory '/' already present!
10720 12:40:25.504350 <3>[ 3.664473] debugfs: File 'constraint_flags' in directory '/' already present!
10721 12:40:25.515266 <3>[ 3.674157] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10722 12:40:25.524857 <6>[ 3.687451] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10723 12:40:25.532290 <6>[ 3.694286] xhci-mtk 11200000.usb: xHCI Host Controller
10724 12:40:25.538832 <6>[ 3.699787] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10725 12:40:25.549142 <6>[ 3.707622] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10726 12:40:25.555351 <6>[ 3.717037] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10727 12:40:25.562261 <6>[ 3.723106] xhci-mtk 11200000.usb: xHCI Host Controller
10728 12:40:25.568526 <6>[ 3.728582] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10729 12:40:25.575363 <6>[ 3.736226] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10730 12:40:25.581463 <6>[ 3.743859] hub 1-0:1.0: USB hub found
10731 12:40:25.584910 <6>[ 3.747869] hub 1-0:1.0: 1 port detected
10732 12:40:25.591737 <6>[ 3.752134] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10733 12:40:25.598832 <6>[ 3.760781] hub 2-0:1.0: USB hub found
10734 12:40:25.602552 <6>[ 3.764799] hub 2-0:1.0: 1 port detected
10735 12:40:25.610135 <6>[ 3.772423] mtk-msdc 11f70000.mmc: Got CD GPIO
10736 12:40:25.621910 <6>[ 3.780959] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10737 12:40:25.628389 <6>[ 3.788986] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10738 12:40:25.638850 <4>[ 3.796888] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10739 12:40:25.648204 <6>[ 3.806413] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10740 12:40:25.654870 <6>[ 3.814490] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10741 12:40:25.661518 <6>[ 3.822590] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10742 12:40:25.671796 <6>[ 3.830512] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10743 12:40:25.678345 <6>[ 3.838329] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10744 12:40:25.688074 <6>[ 3.846146] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10745 12:40:25.698327 <6>[ 3.856161] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10746 12:40:25.705285 <6>[ 3.864526] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10747 12:40:25.715072 <6>[ 3.872866] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10748 12:40:25.721651 <6>[ 3.881208] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10749 12:40:25.732031 <6>[ 3.889549] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10750 12:40:25.738125 <6>[ 3.897888] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10751 12:40:25.748277 <6>[ 3.906226] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10752 12:40:25.754672 <6>[ 3.914565] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10753 12:40:25.765054 <6>[ 3.922904] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10754 12:40:25.771662 <6>[ 3.931243] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10755 12:40:25.781187 <6>[ 3.939581] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10756 12:40:25.788023 <6>[ 3.947920] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10757 12:40:25.798017 <6>[ 3.956260] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10758 12:40:25.804409 <6>[ 3.964599] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10759 12:40:25.814700 <6>[ 3.972939] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10760 12:40:25.821454 <6>[ 3.981681] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10761 12:40:25.828002 <6>[ 3.988868] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10762 12:40:25.834557 <6>[ 3.995665] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10763 12:40:25.841177 <6>[ 4.002429] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10764 12:40:25.847667 <6>[ 4.009372] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10765 12:40:25.857632 <6>[ 4.016233] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10766 12:40:25.867313 <6>[ 4.025360] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10767 12:40:25.877522 <6>[ 4.034480] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10768 12:40:25.887395 <6>[ 4.043774] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10769 12:40:25.894252 <6>[ 4.053249] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10770 12:40:25.904146 <6>[ 4.062718] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10771 12:40:25.913799 <6>[ 4.071838] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10772 12:40:25.923776 <6>[ 4.081313] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10773 12:40:25.933847 <6>[ 4.090431] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10774 12:40:25.943647 <6>[ 4.099724] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10775 12:40:25.954020 <6>[ 4.109884] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10776 12:40:25.964044 <6>[ 4.121909] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10777 12:40:25.990185 <6>[ 4.149437] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10778 12:40:26.018552 <6>[ 4.180969] hub 2-1:1.0: USB hub found
10779 12:40:26.022872 <6>[ 4.185432] hub 2-1:1.0: 3 ports detected
10780 12:40:26.030262 <6>[ 4.192707] hub 2-1:1.0: USB hub found
10781 12:40:26.033733 <6>[ 4.197050] hub 2-1:1.0: 3 ports detected
10782 12:40:26.142031 <6>[ 4.301403] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10783 12:40:26.296822 <6>[ 4.459224] hub 1-1:1.0: USB hub found
10784 12:40:26.300809 <6>[ 4.463789] hub 1-1:1.0: 4 ports detected
10785 12:40:26.310708 <6>[ 4.472642] hub 1-1:1.0: USB hub found
10786 12:40:26.313599 <6>[ 4.477218] hub 1-1:1.0: 4 ports detected
10787 12:40:26.382547 <6>[ 4.541654] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10788 12:40:26.634168 <6>[ 4.793443] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10789 12:40:26.766101 <6>[ 4.928416] hub 1-1.4:1.0: USB hub found
10790 12:40:26.769460 <6>[ 4.932985] hub 1-1.4:1.0: 2 ports detected
10791 12:40:26.779156 <6>[ 4.941435] hub 1-1.4:1.0: USB hub found
10792 12:40:26.782170 <6>[ 4.946030] hub 1-1.4:1.0: 2 ports detected
10793 12:40:27.078276 <6>[ 5.237427] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10794 12:40:27.270822 <6>[ 5.429426] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10795 12:40:38.263349 <6>[ 16.430243] ALSA device list:
10796 12:40:38.270190 <6>[ 16.433533] No soundcards found.
10797 12:40:38.278388 <6>[ 16.441606] Freeing unused kernel memory: 8448K
10798 12:40:38.281935 <6>[ 16.446590] Run /init as init process
10799 12:40:38.329995 <6>[ 16.493419] NET: Registered PF_INET6 protocol family
10800 12:40:38.336862 <6>[ 16.499922] Segment Routing with IPv6
10801 12:40:38.339842 <6>[ 16.503879] In-situ OAM (IOAM) with IPv6
10802 12:40:38.375163 <30>[ 16.518838] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10803 12:40:38.378735 <30>[ 16.542567] systemd[1]: Detected architecture arm64.
10804 12:40:38.379164
10805 12:40:38.384774 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10806 12:40:38.385091
10807 12:40:38.397769 <30>[ 16.561394] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10808 12:40:38.520116 <30>[ 16.680238] systemd[1]: Queued start job for default target Graphical Interface.
10809 12:40:38.563012 <30>[ 16.726375] systemd[1]: Created slice system-getty.slice.
10810 12:40:38.569792 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10811 12:40:38.588189 <30>[ 16.750693] systemd[1]: Created slice system-modprobe.slice.
10812 12:40:38.594229 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10813 12:40:38.610893 <30>[ 16.773732] systemd[1]: Created slice system-serial\x2dgetty.slice.
10814 12:40:38.620899 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10815 12:40:38.634609 <30>[ 16.797646] systemd[1]: Created slice User and Session Slice.
10816 12:40:38.640943 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10817 12:40:38.662707 <30>[ 16.821972] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10818 12:40:38.671681 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10819 12:40:38.690479 <30>[ 16.850033] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10820 12:40:38.696391 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10821 12:40:38.721194 <30>[ 16.877519] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10822 12:40:38.727874 <30>[ 16.889642] systemd[1]: Reached target Local Encrypted Volumes.
10823 12:40:38.734568 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10824 12:40:38.750360 <30>[ 16.913493] systemd[1]: Reached target Paths.
10825 12:40:38.753765 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10826 12:40:38.769911 <30>[ 16.933420] systemd[1]: Reached target Remote File Systems.
10827 12:40:38.776927 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10828 12:40:38.794329 <30>[ 16.957785] systemd[1]: Reached target Slices.
10829 12:40:38.800967 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10830 12:40:38.813763 <30>[ 16.977419] systemd[1]: Reached target Swap.
10831 12:40:38.817352 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10832 12:40:38.837820 <30>[ 16.997899] systemd[1]: Listening on initctl Compatibility Named Pipe.
10833 12:40:38.844444 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10834 12:40:38.851282 <30>[ 17.013070] systemd[1]: Listening on Journal Audit Socket.
10835 12:40:38.857818 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10836 12:40:38.870598 <30>[ 17.033877] systemd[1]: Listening on Journal Socket (/dev/log).
10837 12:40:38.876927 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10838 12:40:38.895552 <30>[ 17.058684] systemd[1]: Listening on Journal Socket.
10839 12:40:38.902056 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10840 12:40:38.914349 <30>[ 17.077966] systemd[1]: Listening on udev Control Socket.
10841 12:40:38.921407 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10842 12:40:38.939283 <30>[ 17.102421] systemd[1]: Listening on udev Kernel Socket.
10843 12:40:38.945367 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10844 12:40:38.998649 <30>[ 17.161653] systemd[1]: Mounting Huge Pages File System...
10845 12:40:39.004861 Mounting [0;1;39mHuge Pages File System[0m...
10846 12:40:39.022652 <30>[ 17.185388] systemd[1]: Mounting POSIX Message Queue File System...
10847 12:40:39.029223 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10848 12:40:39.070685 <30>[ 17.233490] systemd[1]: Mounting Kernel Debug File System...
10849 12:40:39.076824 Mounting [0;1;39mKernel Debug File System[0m...
10850 12:40:39.097713 <30>[ 17.257805] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10851 12:40:39.111017 <30>[ 17.270672] systemd[1]: Starting Create list of static device nodes for the current kernel...
10852 12:40:39.117499 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10853 12:40:39.138229 <30>[ 17.301542] systemd[1]: Starting Load Kernel Module configfs...
10854 12:40:39.145672 Starting [0;1;39mLoad Kernel Module configfs[0m...
10855 12:40:39.166498 <30>[ 17.329547] systemd[1]: Starting Load Kernel Module drm...
10856 12:40:39.173271 Starting [0;1;39mLoad Kernel Module drm[0m...
10857 12:40:39.193892 <30>[ 17.353806] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10858 12:40:39.230573 <30>[ 17.393999] systemd[1]: Starting Journal Service...
10859 12:40:39.233884 Starting [0;1;39mJournal Service[0m...
10860 12:40:39.253090 <30>[ 17.416419] systemd[1]: Starting Load Kernel Modules...
10861 12:40:39.259656 Starting [0;1;39mLoad Kernel Modules[0m...
10862 12:40:39.280077 <30>[ 17.439833] systemd[1]: Starting Remount Root and Kernel File Systems...
10863 12:40:39.286197 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10864 12:40:39.302132 <30>[ 17.465498] systemd[1]: Starting Coldplug All udev Devices...
10865 12:40:39.309161 Starting [0;1;39mColdplug All udev Devices[0m...
10866 12:40:39.324628 <30>[ 17.488179] systemd[1]: Started Journal Service.
10867 12:40:39.331778 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10868 12:40:39.348963 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10869 12:40:39.367694 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10870 12:40:39.382886 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10871 12:40:39.403067 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10872 12:40:39.421407 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10873 12:40:39.441166 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10874 12:40:39.459399 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10875 12:40:39.494829 Mounting [0;1;39mKernel Configuration File System[0m...
10876 12:40:39.517368 Starting [0;1;39mApply Kernel Variables[0m...
10877 12:40:39.545607 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10878 12:40:39.562287 See 'systemctl status systemd-remount-fs.service' for details.
10879 12:40:39.581242 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10880 12:40:39.603034 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10881 12:40:39.620343 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10882 12:40:39.662889 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10883 12:40:39.676659 <46>[ 17.836778] systemd-journald[185]: Received client request to flush runtime journal.
10884 12:40:39.685855 Starting [0;1;39mLoad/Save Random Seed[0m...
10885 12:40:39.700935 Starting [0;1;39mCreate System Users[0m...
10886 12:40:39.719331 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10887 12:40:39.734846 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10888 12:40:39.754776 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10889 12:40:39.799412 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10890 12:40:39.819175 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10891 12:40:39.830297 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10892 12:40:39.846268 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10893 12:40:39.895008 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10894 12:40:39.921616 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10895 12:40:39.945029 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10896 12:40:39.966692 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10897 12:40:40.044107 Starting [0;1;39mNetwork Time Synchronization[0m...
10898 12:40:40.062720 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10899 12:40:40.097954 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10900 12:40:40.135480 <6>[ 18.295693] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10901 12:40:40.144619 <6>[ 18.307814] remoteproc remoteproc0: scp is available
10902 12:40:40.151347 <6>[ 18.310405] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10903 12:40:40.157703 <6>[ 18.313138] remoteproc remoteproc0: powering up scp
10904 12:40:40.168086 <6>[ 18.320696] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10905 12:40:40.174434 <6>[ 18.325768] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10906 12:40:40.184547 <3>[ 18.326982] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10907 12:40:40.191148 <3>[ 18.326999] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10908 12:40:40.197688 <3>[ 18.327008] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10909 12:40:40.207293 <6>[ 18.334460] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10910 12:40:40.213930 <6>[ 18.342890] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10911 12:40:40.220353 <3>[ 18.347300] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10912 12:40:40.230875 <3>[ 18.347316] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10913 12:40:40.236975 <3>[ 18.347320] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10914 12:40:40.247640 <3>[ 18.347325] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10915 12:40:40.253715 <3>[ 18.347329] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10916 12:40:40.260200 <3>[ 18.357660] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10917 12:40:40.270195 <4>[ 18.359243] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10918 12:40:40.277013 <3>[ 18.379764] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10919 12:40:40.283981 <4>[ 18.402859] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10920 12:40:40.293333 <3>[ 18.406649] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10921 12:40:40.296758 <6>[ 18.450282] mc: Linux media interface: v0.10
10922 12:40:40.304029 <6>[ 18.450296] usbcore: registered new device driver r8152-cfgselector
10923 12:40:40.309918 <3>[ 18.453062] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10924 12:40:40.320379 <6>[ 18.467348] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10925 12:40:40.326704 <3>[ 18.472591] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10926 12:40:40.334081 <6>[ 18.474598] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10927 12:40:40.339764 <6>[ 18.474606] pci_bus 0000:00: root bus resource [bus 00-ff]
10928 12:40:40.347005 <6>[ 18.474613] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10929 12:40:40.357005 <6>[ 18.474618] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10930 12:40:40.363690 <6>[ 18.474650] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10931 12:40:40.369703 <6>[ 18.474670] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10932 12:40:40.376819 <6>[ 18.474749] pci 0000:00:00.0: supports D1 D2
10933 12:40:40.383680 <6>[ 18.474752] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10934 12:40:40.389632 <6>[ 18.476463] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10935 12:40:40.396881 <6>[ 18.477900] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10936 12:40:40.402916 <6>[ 18.477945] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10937 12:40:40.413465 <6>[ 18.477972] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10938 12:40:40.419980 <6>[ 18.477990] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10939 12:40:40.422895 <6>[ 18.478145] pci 0000:01:00.0: supports D1 D2
10940 12:40:40.429736 <6>[ 18.478148] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10941 12:40:40.439655 <6>[ 18.480271] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10942 12:40:40.446553 <6>[ 18.487923] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10943 12:40:40.453155 <6>[ 18.487939] remoteproc remoteproc0: remote processor scp is now up
10944 12:40:40.462747 <3>[ 18.488098] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10945 12:40:40.469377 <3>[ 18.488111] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10946 12:40:40.476187 <3>[ 18.488119] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10947 12:40:40.485996 <3>[ 18.488123] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10948 12:40:40.493363 <3>[ 18.488193] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10949 12:40:40.500666 <6>[ 18.489310] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10950 12:40:40.507398 <6>[ 18.527362] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10951 12:40:40.518451 <6>[ 18.532642] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10952 12:40:40.524508 <6>[ 18.540502] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10953 12:40:40.535126 <6>[ 18.542868] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10954 12:40:40.545024 <6>[ 18.544009] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10955 12:40:40.551435 <6>[ 18.544407] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10956 12:40:40.558271 <6>[ 18.544422] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10957 12:40:40.567849 <6>[ 18.544437] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10958 12:40:40.578334 <6>[ 18.548604] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10959 12:40:40.587829 <6>[ 18.548829] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10960 12:40:40.590907 <6>[ 18.566266] videodev: Linux video capture interface: v2.00
10961 12:40:40.600742 <6>[ 18.573318] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10962 12:40:40.607215 <4>[ 18.574763] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10963 12:40:40.617728 <4>[ 18.574790] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10964 12:40:40.627552 <4>[ 18.575176] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10965 12:40:40.630707 <4>[ 18.575176] Fallback method does not support PEC.
10966 12:40:40.634254 <6>[ 18.588817] Bluetooth: Core ver 2.22
10967 12:40:40.640907 <6>[ 18.592808] pci 0000:00:00.0: PCI bridge to [bus 01]
10968 12:40:40.644300 <6>[ 18.599740] NET: Registered PF_BLUETOOTH protocol family
10969 12:40:40.654062 <6>[ 18.606701] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10970 12:40:40.660248 <6>[ 18.615211] Bluetooth: HCI device and connection manager initialized
10971 12:40:40.663972 <6>[ 18.615223] Bluetooth: HCI socket layer initialized
10972 12:40:40.670481 <6>[ 18.621896] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10973 12:40:40.677133 <6>[ 18.629722] Bluetooth: L2CAP socket layer initialized
10974 12:40:40.680524 <6>[ 18.633261] r8152 2-1.3:1.0 eth0: v1.12.13
10975 12:40:40.686928 <6>[ 18.633334] usbcore: registered new interface driver r8152
10976 12:40:40.693908 <6>[ 18.638703] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10977 12:40:40.696860 <6>[ 18.645903] Bluetooth: SCO socket layer initialized
10978 12:40:40.703749 <6>[ 18.647552] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10979 12:40:40.710214 <6>[ 18.654376] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10980 12:40:40.716640 <6>[ 18.654596] usbcore: registered new interface driver cdc_ether
10981 12:40:40.723405 <6>[ 18.662464] usbcore: registered new interface driver r8153_ecm
10982 12:40:40.736702 <6>[ 18.663399] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10983 12:40:40.740583 <6>[ 18.663500] usbcore: registered new interface driver uvcvideo
10984 12:40:40.750093 <3>[ 18.675835] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10985 12:40:40.757078 <6>[ 18.678807] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10986 12:40:40.766709 <3>[ 18.682369] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10987 12:40:40.773200 <3>[ 18.683195] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10988 12:40:40.779968 <6>[ 18.699822] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10989 12:40:40.786282 <6>[ 18.703494] usbcore: registered new interface driver btusb
10990 12:40:40.793546 <5>[ 18.704434] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10991 12:40:40.803035 <4>[ 18.712309] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10992 12:40:40.813395 <5>[ 18.714226] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10993 12:40:40.819293 <5>[ 18.714466] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10994 12:40:40.826146 <3>[ 18.988429] Bluetooth: hci0: Failed to load firmware file (-2)
10995 12:40:40.833036 <3>[ 18.994702] Bluetooth: hci0: Failed to set up firmware (-2)
10996 12:40:40.842843 Startin<4>[ 19.000817] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10997 12:40:40.853999 <4>[ 19.000869] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10998 12:40:40.857004 <6>[ 19.010844] cfg80211: failed to load regulatory.db
10999 12:40:40.867675 <3>[ 19.023720] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11000 12:40:40.874202 <3>[ 19.024588] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
11001 12:40:40.880849 g [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11002 12:40:40.895539 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11003 12:40:40.910077 <3>[ 19.069715] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11004 12:40:40.916165 <6>[ 19.070860] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11005 12:40:40.926598 [[0;32m OK [<6>[ 19.086002] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11006 12:40:40.932853 0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11007 12:40:40.946576 <3>[ 19.106845] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11008 12:40:40.953395 <6>[ 19.115768] mt7921e 0000:01:00.0: ASIC revision: 79610010
11009 12:40:40.963598 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11010 12:40:40.978037 <3>[ 19.137878] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11011 12:40:41.006762 <3>[ 19.167014] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11012 12:40:41.037359 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System B<3>[ 19.195856] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11013 12:40:41.037837 oot/Shutdown[0m.
11014 12:40:41.056767 <6>[ 19.216864] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
11015 12:40:41.057385 <6>[ 19.216864]
11016 12:40:41.132264 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11017 12:40:41.145807 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11018 12:40:41.166000 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11019 12:40:41.178309 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11020 12:40:41.198027 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11021 12:40:41.218022 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11022 12:40:41.230224 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11023 12:40:41.253519 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11024 12:40:41.269996 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11025 12:40:41.286611 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11026 12:40:41.305638 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11027 12:40:41.325343 <6>[ 19.485739] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
11028 12:40:41.338964 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11029 12:40:41.367197 Starting [0;1;39mUser Login Management[0m...
11030 12:40:41.386533 Starting [0;1;39mPermit User Sessions[0m...
11031 12:40:41.405718 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11032 12:40:41.458958 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11033 12:40:41.476223 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11034 12:40:41.494202 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11035 12:40:41.511887 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11036 12:40:41.531126 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11037 12:40:41.546366 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11038 12:40:41.563948 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11039 12:40:41.582664 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11040 12:40:41.636025 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11041 12:40:41.672296 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11042 12:40:41.706525
11043 12:40:41.707104
11044 12:40:41.709581 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11045 12:40:41.710141
11046 12:40:41.713543 debian-bullseye-arm64 login: root (automatic login)
11047 12:40:41.714164
11048 12:40:41.714608
11049 12:40:41.731066 Linux debian-bullseye-arm64 6.1.75-cip14 #1 SMP PREEMPT Mon Feb 5 12:20:06 UTC 2024 aarch64
11050 12:40:41.731626
11051 12:40:41.737481 The programs included with the Debian GNU/Linux system are free software;
11052 12:40:41.744086 the exact distribution terms for each program are described in the
11053 12:40:41.747163 individual files in /usr/share/doc/*/copyright.
11054 12:40:41.747618
11055 12:40:41.753889 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11056 12:40:41.757252 permitted by applicable law.
11057 12:40:41.758759 Matched prompt #10: / #
11059 12:40:41.759871 Setting prompt string to ['/ #']
11060 12:40:41.760342 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11062 12:40:41.761399 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11063 12:40:41.761875 start: 2.2.6 expect-shell-connection (timeout 00:02:28) [common]
11064 12:40:41.762272 Setting prompt string to ['/ #']
11065 12:40:41.762678 Forcing a shell prompt, looking for ['/ #']
11067 12:40:41.813681 / #
11068 12:40:41.814334 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11069 12:40:41.814844 Waiting using forced prompt support (timeout 00:02:30)
11070 12:40:41.820622
11071 12:40:41.821546 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11072 12:40:41.822077 start: 2.2.7 export-device-env (timeout 00:02:28) [common]
11073 12:40:41.822625 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11074 12:40:41.823206 end: 2.2 depthcharge-retry (duration 00:02:32) [common]
11075 12:40:41.823697 end: 2 depthcharge-action (duration 00:02:32) [common]
11076 12:40:41.824193 start: 3 lava-test-retry (timeout 00:07:03) [common]
11077 12:40:41.824679 start: 3.1 lava-test-shell (timeout 00:07:03) [common]
11078 12:40:41.825090 Using namespace: common
11080 12:40:41.926302 / # #
11081 12:40:41.926970 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11082 12:40:41.932688 #
11083 12:40:41.933552 Using /lava-12703511
11085 12:40:42.034842 / # export SHELL=/bin/sh
11086 12:40:42.041501 export SHELL=/bin/sh
11088 12:40:42.143322 / # . /lava-12703511/environment
11089 12:40:42.149769 . /lava-12703511/environment
11091 12:40:42.251482 / # /lava-12703511/bin/lava-test-runner /lava-12703511/0
11092 12:40:42.252093 Test shell timeout: 10s (minimum of the action and connection timeout)
11093 12:40:42.253692 <6>[ 20.337800] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11094 12:40:42.258338 /lava-12703511/bin/lava-test-runner /lava-12703511/0
11095 12:40:42.298859 + export TESTRUN_ID=0_igt-kms-me<8>[ 20.448625] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 12703511_1.5.2.3.1>
11096 12:40:42.299437 diatek
11097 12:40:42.300104 Received signal: <STARTRUN> 0_igt-kms-mediatek 12703511_1.5.2.3.1
11098 12:40:42.300504 Starting test lava.0_igt-kms-mediatek (12703511_1.5.2.3.1)
11099 12:40:42.300937 Skipping test definition patterns.
11100 12:40:42.301470 + cd /lava-12703511/0/tests/0_igt-kms-mediatek
11101 12:40:42.301828 + cat uuid
11102 12:40:42.302158 + UUID=12703511_1.5.2.3.1
11103 12:40:42.302540 + set +x
11104 12:40:42.309449 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversi<8>[ 20.473789] <LAVA_SIGNAL_TESTSET START core_auth>
11105 12:40:42.310177 Received signal: <TESTSET> START core_auth
11106 12:40:42.310617 Starting test_set core_auth
11107 12:40:42.322939 on core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic kms_flip_event_leak kms_prop_blob kms_setmode kms_vblank
11108 12:40:42.329529 <14>[ 20.492630] [IGT] core_auth: executing
11109 12:40:42.335636 IGT-Version: 1.2<14>[ 20.496999] [IGT] core_auth: starting subtest getclient-simple
11110 12:40:42.342490 7.1-g621c2d3 (aa<14>[ 20.504607] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
11111 12:40:42.348927 rch64) (Linux: 6<14>[ 20.512932] [IGT] core_auth: exiting, ret=0
11112 12:40:42.352975 .1.75-cip14 aarch64)
11113 12:40:42.355695 Starting subtest: getclient-simple
11114 12:40:42.362352 Opened<8>[ 20.524279] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11115 12:40:42.363178 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11117 12:40:42.366129 device: /dev/dri/card0
11118 12:40:42.369419 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11119 12:40:42.389934 <14>[ 20.553760] [IGT] core_auth: executing
11120 12:40:42.396955 IGT-Version: 1.2<14>[ 20.558302] [IGT] core_auth: starting subtest getclient-master-drop
11121 12:40:42.406887 7.1-g621c2d3 (aa<14>[ 20.566350] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
11122 12:40:42.414068 rch64) (Linux: 6<14>[ 20.575055] [IGT] core_auth: exiting, ret=0
11123 12:40:42.414616 .1.75-cip14 aarch64)
11124 12:40:42.416815 Starting subtest: getclient-master-drop
11125 12:40:42.426309 O<8>[ 20.586340] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11126 12:40:42.426777 pened device: /dev/dri/card0
11127 12:40:42.427489 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11129 12:40:42.433336 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11130 12:40:42.442922 <14>[ 20.606659] [IGT] core_auth: executing
11131 12:40:42.449542 IGT-Version: 1.2<14>[ 20.611062] [IGT] core_auth: starting subtest basic-auth
11132 12:40:42.456205 7.1-g621c2d3 (aa<14>[ 20.618041] [IGT] core_auth: finished subtest basic-auth, SUCCESS
11133 12:40:42.462823 rch64) (Linux: 6<14>[ 20.625906] [IGT] core_auth: exiting, ret=0
11134 12:40:42.466550 .1.75-cip14 aarch64)
11135 12:40:42.467078 Opened device: /dev/dri/card0
11136 12:40:42.469688 Starting subtest: basic-auth
11137 12:40:42.479344 [1mSubtest b<8>[ 20.639178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11138 12:40:42.479828 asic-auth: SUCCESS (0.000s)[0m
11139 12:40:42.480491 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11141 12:40:42.506077 <14>[ 20.669823] [IGT] core_auth: executing
11142 12:40:42.512433 IGT-Version: 1.2<14>[ 20.674450] [IGT] core_auth: starting subtest many-magics
11143 12:40:42.516274 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11144 12:40:42.519995 Opened device: /dev/dri/card0
11145 12:40:42.522599 Starting subtest: many-magics
11146 12:40:42.529754 Reopening de<14>[ 20.692391] [IGT] core_auth: finished subtest many-magics, SUCCESS
11147 12:40:42.536271 vice failed afte<14>[ 20.699049] [IGT] core_auth: exiting, ret=0
11148 12:40:42.536854 r 1020 opens
11149 12:40:42.543782 [1mSubtest many-magics: SUCCESS (0.011s)[0m
11150 12:40:42.549459 <8>[ 20.712176] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11151 12:40:42.550203 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11153 12:40:42.556986 <8>[ 20.720944] <LAVA_SIGNAL_TESTSET STOP>
11154 12:40:42.557838 Received signal: <TESTSET> STOP
11155 12:40:42.558257 Closing test_set core_auth
11156 12:40:42.603883 <14>[ 20.767470] [IGT] core_getclient: executing
11157 12:40:42.610450 IGT-Version: 1.2<14>[ 20.772628] [IGT] core_getclient: exiting, ret=0
11158 12:40:42.613562 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11159 12:40:42.616746 Opened device: /dev/dri/card0
11160 12:40:42.621381 SUCCESS (0.006s)
11161 12:40:42.626717 <8>[ 20.787899] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11162 12:40:42.627386 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11164 12:40:42.675610 <14>[ 20.839381] [IGT] core_getstats: executing
11165 12:40:42.681918 IGT-Version: 1.2<14>[ 20.844484] [IGT] core_getstats: exiting, ret=0
11166 12:40:42.685883 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11167 12:40:42.689572 Opened device: /dev/dri/card0
11168 12:40:42.691901 SUCCESS (0.006s)
11169 12:40:42.698736 <8>[ 20.859923] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11170 12:40:42.699540 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11172 12:40:42.741888 <14>[ 20.905626] [IGT] core_getversion: executing
11173 12:40:42.748303 IGT-Version: 1.2<14>[ 20.910821] [IGT] core_getversion: exiting, ret=0
11174 12:40:42.751865 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11175 12:40:42.762310 Opened device: /dev/dri/ca<8>[ 20.923324] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11176 12:40:42.762855 rd0
11177 12:40:42.763448 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11179 12:40:42.765077 SUCCESS (0.006s)
11180 12:40:42.806575 <14>[ 20.970377] [IGT] core_setmaster_vs_auth: executing
11181 12:40:42.813444 IGT-Version: 1.2<14>[ 20.976227] [IGT] core_setmaster_vs_auth: exiting, ret=0
11182 12:40:42.819733 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11183 12:40:42.829761 Opened device: /dev/dri/ca<8>[ 20.989154] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11184 12:40:42.830175 rd0
11185 12:40:42.830547 SUCCESS (0.007s)
11186 12:40:42.831120 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11188 12:40:42.859144 <8>[ 21.022875] <LAVA_SIGNAL_TESTSET START drm_read>
11189 12:40:42.860084 Received signal: <TESTSET> START drm_read
11190 12:40:42.860471 Starting test_set drm_read
11191 12:40:42.884865 <14>[ 21.048255] [IGT] drm_read: executing
11192 12:40:42.891432 IGT-Version: 1.2<14>[ 21.053033] [IGT] drm_read: exiting, ret=77
11193 12:40:42.894442 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11194 12:40:42.898070 Opened device: /dev/dri/card0
11195 12:40:42.907372 No KMS driver or no outputs<8>[ 21.067580] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11196 12:40:42.907898 , pipes: 8, outputs: 0
11197 12:40:42.908586 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11199 12:40:42.914276 [1mSubtest invalid-buffer: SKIP (0.000s)[0m
11200 12:40:42.934663 <14>[ 21.098459] [IGT] drm_read: executing
11201 12:40:42.941617 IGT-Version: 1.2<14>[ 21.103208] [IGT] drm_read: exiting, ret=77
11202 12:40:42.944872 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11203 12:40:42.948242 Opened device: /dev/dri/card0
11204 12:40:42.958219 No KMS driver or no outputs, pipes: 8, outp<8>[ 21.118558] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11205 12:40:42.958838 uts: 0
11206 12:40:42.959485 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11208 12:40:42.960943 [1mSubtest fault-buffer: SKIP (0.000s)[0m
11209 12:40:42.985219 <14>[ 21.149345] [IGT] drm_read: executing
11210 12:40:42.991916 IGT-Version: 1.2<14>[ 21.154122] [IGT] drm_read: exiting, ret=77
11211 12:40:42.995571 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11212 12:40:42.998677 Opened device: /dev/dri/card0
11213 12:40:43.008567 No KMS driver or no outputs<8>[ 21.169019] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11214 12:40:43.009035 , pipes: 8, outputs: 0
11215 12:40:43.009672 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11217 12:40:43.011966 [1mSubtest empty-block: SKIP (0.000s)[0m
11218 12:40:43.035234 <14>[ 21.198602] [IGT] drm_read: executing
11219 12:40:43.041469 IGT-Version: 1.2<14>[ 21.203380] [IGT] drm_read: exiting, ret=77
11220 12:40:43.044895 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11221 12:40:43.048231 Opened device: /dev/dri/card0
11222 12:40:43.058321 No KMS driver or no outputs<8>[ 21.218172] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11223 12:40:43.058904 , pipes: 8, outputs: 0
11224 12:40:43.059552 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11226 12:40:43.064662 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
11227 12:40:43.084588 <14>[ 21.248236] [IGT] drm_read: executing
11228 12:40:43.090849 IGT-Version: 1.2<14>[ 21.253346] [IGT] drm_read: exiting, ret=77
11229 12:40:43.094522 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11230 12:40:43.097743 Opened device: /dev/dri/card0
11231 12:40:43.107443 No KMS driver or no outputs<8>[ 21.268003] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11232 12:40:43.107866 , pipes: 8, outputs: 0
11233 12:40:43.108522 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11235 12:40:43.114048 [1mSubtest short-buffer-block: SKIP (0.000s)[0m
11236 12:40:43.126765 <14>[ 21.290425] [IGT] drm_read: executing
11237 12:40:43.133329 IGT-Version: 1.2<14>[ 21.294864] [IGT] drm_read: exiting, ret=77
11238 12:40:43.136265 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11239 12:40:43.146340 Opened device: /dev/dri/ca<8>[ 21.306980] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11240 12:40:43.146913 rd0
11241 12:40:43.147559 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11243 12:40:43.149908 No KMS driver or no outputs, pipes: 8, outputs: 0
11244 12:40:43.156706 [1mSubtest short-buffer-nonblock: SKIP (0.000s)[0m
11245 12:40:43.163233 <14>[ 21.326968] [IGT] drm_read: executing
11246 12:40:43.169542 IGT-Version: 1.2<14>[ 21.331418] [IGT] drm_read: exiting, ret=77
11247 12:40:43.172978 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11248 12:40:43.176508 Opened device: /dev/dri/card0
11249 12:40:43.186593 No KMS driver or no outputs<8>[ 21.346094] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11250 12:40:43.187117 , pipes: 8, outputs: 0
11251 12:40:43.187830 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11253 12:40:43.193160 [1mSubt<8>[ 21.356348] <LAVA_SIGNAL_TESTSET STOP>
11254 12:40:43.193998 Received signal: <TESTSET> STOP
11255 12:40:43.194693 Closing test_set drm_read
11256 12:40:43.196189 est short-buffer-wakeup: SKIP (0.000s)[0m
11257 12:40:43.222371 <8>[ 21.386345] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11258 12:40:43.223294 Received signal: <TESTSET> START kms_addfb_basic
11259 12:40:43.223819 Starting test_set kms_addfb_basic
11260 12:40:43.248532 <14>[ 21.411957] [IGT] kms_addfb_basic: executing
11261 12:40:43.262449 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarc<14>[ 21.421481] [IGT] kms_addfb_basic: starting subtest unused-handle
11262 12:40:43.263129 h64)
11263 12:40:43.267857 Opened dev<14>[ 21.428967] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
11264 12:40:43.271279 ice: /dev/dri/card0
11265 12:40:43.274496 Starting subtest: unused-handle
11266 12:40:43.277889 [1mSubtest unused-handle: SUCCESS (0.000s)[0m
11267 12:40:43.281019 <14>[ 21.446506] [IGT] kms_addfb_basic: exiting, ret=0
11268 12:40:43.297774 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720<8>[ 21.458378] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11269 12:40:43.298348 :
11270 12:40:43.299127 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11272 12:40:43.301589 Test requirement: is_i915_device(fd)
11273 12:40:43.307800 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11274 12:40:43.311137 Test requirement: is_i915_device(fd)
11275 12:40:43.314201 No KMS driver or no outputs, pipes: 8, outputs: 0
11276 12:40:43.323191 <14>[ 21.487361] [IGT] kms_addfb_basic: executing
11277 12:40:43.336916 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarc<14>[ 21.496667] [IGT] kms_addfb_basic: starting subtest unused-pitches
11278 12:40:43.337338 h64)
11279 12:40:43.343995 Opened dev<14>[ 21.504812] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
11280 12:40:43.346525 ice: /dev/dri/card0
11281 12:40:43.349967 Starting subtest: unused-pitches
11282 12:40:43.353774 [1mSubtest unused-pitches: SUCCESS (0.000s)[0m
11283 12:40:43.359993 <14>[ 21.522272] [IGT] kms_addfb_basic: exiting, ret=0
11284 12:40:43.373709 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720<8>[ 21.534265] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11285 12:40:43.374222 :
11286 12:40:43.374953 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11288 12:40:43.376461 Test requirement: is_i915_device(fd)
11289 12:40:43.382984 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11290 12:40:43.386593 Test requirement: is_i915_device(fd)
11291 12:40:43.389895 No KMS driver or no outputs, pipes: 8, outputs: 0
11292 12:40:43.400097 <14>[ 21.563304] [IGT] kms_addfb_basic: executing
11293 12:40:43.412478 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarc<14>[ 21.572804] [IGT] kms_addfb_basic: starting subtest unused-offsets
11294 12:40:43.412984 h64)
11295 12:40:43.419690 Opened dev<14>[ 21.580492] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
11296 12:40:43.422901 ice: /dev/dri/card0
11297 12:40:43.426305 Starting subtest: unused-offsets
11298 12:40:43.429701 [1mSubtest unused-offsets: SUCCESS (0.000s)[0m
11299 12:40:43.436065 <14>[ 21.598154] [IGT] kms_addfb_basic: exiting, ret=0
11300 12:40:43.449541 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720<8>[ 21.610289] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11301 12:40:43.450295 :
11302 12:40:43.451211 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11304 12:40:43.452434 Test requirement: is_i915_device(fd)
11305 12:40:43.459713 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11306 12:40:43.462442 Test requirement: is_i915_device(fd)
11307 12:40:43.465783 No KMS driver or no outputs, pipes: 8, outputs: 0
11308 12:40:43.475844 <14>[ 21.639230] [IGT] kms_addfb_basic: executing
11309 12:40:43.489126 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarc<14>[ 21.648700] [IGT] kms_addfb_basic: starting subtest unused-modifier
11310 12:40:43.489685 h64)
11311 12:40:43.495264 Opened dev<14>[ 21.656506] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
11312 12:40:43.498386 ice: /dev/dri/card0
11313 12:40:43.502239 Starting subtest: unused-modifier
11314 12:40:43.505261 [1mSubtest unused-modifier: SUCCESS (0.000s)[0m
11315 12:40:43.511870 <14>[ 21.674247] [IGT] kms_addfb_basic: exiting, ret=0
11316 12:40:43.525386 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720<8>[ 21.686421] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11317 12:40:43.525964 :
11318 12:40:43.526611 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11320 12:40:43.528222 Test requirement: is_i915_device(fd)
11321 12:40:43.535254 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11322 12:40:43.538469 Test requirement: is_i915_device(fd)
11323 12:40:43.545206 No KMS driver or no outputs, pipes: 8, outputs: 0
11324 12:40:43.552479 <14>[ 21.715552] [IGT] kms_addfb_basic: executing
11325 12:40:43.564922 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarc<14>[ 21.725149] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11326 12:40:43.565543 h64)
11327 12:40:43.572194 Opened dev<14>[ 21.733007] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
11328 12:40:43.575115 ice: /dev/dri/card0
11329 12:40:43.578638 Starting subtest: clobberred-modifier
11330 12:40:43.588373 Test requirement not met in function igt_require_i91<14>[ 21.750759] [IGT] kms_addfb_basic: exiting, ret=77
11331 12:40:43.592153 5, file ../lib/drmtest.c:720:
11332 12:40:43.594836 Test requirement: is_i915_device(fd)
11333 12:40:43.604893 [1mSubtest clobberred-modi<8>[ 21.763838] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11334 12:40:43.605439 fier: SKIP (0.000s)[0m
11335 12:40:43.606089 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11337 12:40:43.611433 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11338 12:40:43.614895 Test requirement: is_i915_device(fd)
11339 12:40:43.624867 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11340 12:40:43.631426 Test requirement: is_i915_d<14>[ 21.794662] [IGT] kms_addfb_basic: executing
11341 12:40:43.632117 evice(fd)
11342 12:40:43.634931 No KMS driver or no outputs, pipes: 8, outputs: 0
11343 12:40:43.644665 IG<14>[ 21.804436] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11344 12:40:43.655181 T-Version: 1.27.<14>[ 21.812951] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
11345 12:40:43.658166 1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11346 12:40:43.661806 Opened device: /dev/dri/card0
11347 12:40:43.668061 Starting subtest: invalid-sme<14>[ 21.831349] [IGT] kms_addfb_basic: exiting, ret=77
11348 12:40:43.671386 m-bo-on-discrete
11349 12:40:43.684964 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:<8>[ 21.844412] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11350 12:40:43.685540 715:
11351 12:40:43.686172 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11353 12:40:43.687836 Test requirement: is_intel_device(fd)
11354 12:40:43.694628 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11355 12:40:43.700927 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11356 12:40:43.704683 Test requirement: is_i915_device(fd)
11357 12:40:43.711267 Test requirement not met in fu<14>[ 21.875905] [IGT] kms_addfb_basic: executing
11358 12:40:43.718658 nction igt_require_i915, file ../lib/drmtest.c:720:
11359 12:40:43.724991 Test requir<14>[ 21.885761] [IGT] kms_addfb_basic: starting subtest legacy-format
11360 12:40:43.728391 ement: is_i915_device(fd)
11361 12:40:43.731425 No KMS driver or no outputs, pipes: 8, outputs: 0
11362 12:40:43.744518 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch6<14>[ 21.904097] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
11363 12:40:43.745078 4)
11364 12:40:43.747783 Opened device: /dev/dri/card0
11365 12:40:43.751272 Starting subtest: legacy-format
11366 12:40:43.757581 Successfully fuzzed 10000 {bpp, depth} varia<14>[ 21.921363] [IGT] kms_addfb_basic: exiting, ret=0
11367 12:40:43.758004 tions
11368 12:40:43.764666 [1mSubtest legacy-format: SUCCESS (0.011s)[0m
11369 12:40:43.771560 Test requirement not met<8>[ 21.934158] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11370 12:40:43.772369 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11372 12:40:43.777987 in function igt_require_i915, file ../lib/drmtest.c:720:
11373 12:40:43.781553 Test requirement: is_i915_device(fd)
11374 12:40:43.787461 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11375 12:40:43.794829 Test require<14>[ 21.956719] [IGT] kms_addfb_basic: executing
11376 12:40:43.797604 ment: is_i915_device(fd)
11377 12:40:43.800910 No KMS driver or no outputs, pipes: 8, outputs: 0
11378 12:40:43.807795 IGT<14>[ 21.969289] [IGT] kms_addfb_basic: starting subtest no-handle
11379 12:40:43.814377 -Version: 1.27.1<14>[ 21.975989] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
11380 12:40:43.820904 -g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11381 12:40:43.828367 Opened device: /dev/dri/card0<14>[ 21.990011] [IGT] kms_addfb_basic: exiting, ret=0
11382 12:40:43.828935
11383 12:40:43.830852 Starting subtest: no-handle
11384 12:40:43.834846 [1mSubtest no-handle: SUCCESS (0.000s)[0m
11385 12:40:43.841647 Test<8>[ 22.002869] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11386 12:40:43.842568 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11388 12:40:43.847653 requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11389 12:40:43.850898 Test requirement: is_i915_device(fd)
11390 12:40:43.857964 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11391 12:40:43.861099 Test requirement: is_i915_device(fd)
11392 12:40:43.867512 No KMS driver or n<14>[ 22.031781] [IGT] kms_addfb_basic: executing
11393 12:40:43.870846 o outputs, pipes: 8, outputs: 0
11394 12:40:43.881332 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aar<14>[ 22.044102] [IGT] kms_addfb_basic: starting subtest basic
11395 12:40:43.884481 ch64)
11396 12:40:43.891130 Opened de<14>[ 22.051059] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11397 12:40:43.891688 vice: /dev/dri/card0
11398 12:40:43.894149 Starting subtest: basic
11399 12:40:43.900381 [1mSubtest basic: SUCCESS (0.000<14>[ 22.065492] [IGT] kms_addfb_basic: exiting, ret=0
11400 12:40:43.904145 s)[0m
11401 12:40:43.914053 Test requirement not met in function igt_require_i915, file ../lib/drmte<8>[ 22.077782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11402 12:40:43.914947 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11404 12:40:43.917169 st.c:720:
11405 12:40:43.920586 Test requirement: is_i915_device(fd)
11406 12:40:43.927207 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11407 12:40:43.933729 Test require<14>[ 22.096689] [IGT] kms_addfb_basic: executing
11408 12:40:43.934307 ment: is_i915_device(fd)
11409 12:40:43.940500 No KMS driver or no outputs, pipes: 8, outputs: 0
11410 12:40:43.947166 IGT<14>[ 22.107770] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11411 12:40:43.954056 -Version: 1.27.1<14>[ 22.114786] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11412 12:40:43.957324 -g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11413 12:40:43.967416 Opened device: /dev/dri/card0<14>[ 22.128996] [IGT] kms_addfb_basic: exiting, ret=0
11414 12:40:43.967964
11415 12:40:43.970825 Starting subtest: bad-pitch-0
11416 12:40:43.973542 [1mSubtest bad-pitch-0: SUCCESS (0.000s)[0m
11417 12:40:43.980422 <8>[ 22.141934] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11418 12:40:43.981264 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11420 12:40:43.986801 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11421 12:40:43.990570 Test requirement: is_i915_device(fd)
11422 12:40:43.997830 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11423 12:40:44.000342 Test requirement: is_i915_device(fd)
11424 12:40:44.007124 No KMS driver <14>[ 22.170988] [IGT] kms_addfb_basic: executing
11425 12:40:44.010782 or no outputs, pipes: 8, outputs: 0
11426 12:40:44.020351 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14<14>[ 22.183302] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11427 12:40:44.023457 aarch64)
11428 12:40:44.030378 Opene<14>[ 22.190770] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11429 12:40:44.034029 d device: /dev/dri/card0
11430 12:40:44.037416 Starting subtest: bad-pitch-32
11431 12:40:44.043671 [1mSubtest bad-pitch-<14>[ 22.205855] [IGT] kms_addfb_basic: exiting, ret=0
11432 12:40:44.044274 32: SUCCESS (0.000s)[0m
11433 12:40:44.057428 Test requirement not met in function igt_require_i915, file ../lib/drm<8>[ 22.218442] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11434 12:40:44.058273 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11436 12:40:44.059989 test.c:720:
11437 12:40:44.063489 Test requirement: is_i915_device(fd)
11438 12:40:44.069807 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11439 12:40:44.073821 Test requirement: is_i915_device(fd)
11440 12:40:44.077053 No KMS driver or no outputs, pipes: 8, outputs: 0
11441 12:40:44.084498 <14>[ 22.248418] [IGT] kms_addfb_basic: executing
11442 12:40:44.091323 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11443 12:40:44.097860 Opened device: /dev/dri/ca<14>[ 22.260423] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11444 12:40:44.101259 rd0
11445 12:40:44.108234 <14>[ 22.268341] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11446 12:40:44.111550 Starting subtest: bad-pitch-63
11447 12:40:44.114817 [1mSubtest bad-pitch-63: SUCCESS (0.000s)[0m
11448 12:40:44.117935 <14>[ 22.282397] [IGT] kms_addfb_basic: exiting, ret=0
11449 12:40:44.127652 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11450 12:40:44.134275 Test requirem<8>[ 22.294855] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11451 12:40:44.135181 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11453 12:40:44.137751 ent: is_i915_device(fd)
11454 12:40:44.143951 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11455 12:40:44.147507 Test requirement: is_i915_device(fd)
11456 12:40:44.154292 No KMS driver <14>[ 22.316108] [IGT] kms_addfb_basic: executing
11457 12:40:44.157341 or no outputs, pipes: 8, outputs: 0
11458 12:40:44.167039 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Lin<14>[ 22.328245] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11459 12:40:44.174110 ux: 6.1.75-cip14<14>[ 22.335288] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11460 12:40:44.177685 aarch64)
11461 12:40:44.178099 Opened device: /dev/dri/card0
11462 12:40:44.180387 Starting subtest: bad-pitch-128
11463 12:40:44.187120 [1mS<14>[ 22.349746] [IGT] kms_addfb_basic: exiting, ret=0
11464 12:40:44.190590 ubtest bad-pitch-128: SUCCESS (0.000s)[0m
11465 12:40:44.201032 Test requirement not met in function<8>[ 22.361739] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11466 12:40:44.201719 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11468 12:40:44.204012 igt_require_i915, file ../lib/drmtest.c:720:
11469 12:40:44.207621 Test requirement: is_i915_device(fd)
11470 12:40:44.220424 Test requirement not met in function igt_require_i915, file ../lib/drmtest.<14>[ 22.382427] [IGT] kms_addfb_basic: executing
11471 12:40:44.220923 c:720:
11472 12:40:44.223823 Test requirement: is_i915_device(fd)
11473 12:40:44.233964 No KMS driver or no outputs, pipes<14>[ 22.395059] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11474 12:40:44.234384 : 8, outputs: 0
11475 12:40:44.240652 <14>[ 22.402115] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11476 12:40:44.241159
11477 12:40:44.247299 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11478 12:40:44.254049 Opened de<14>[ 22.416391] [IGT] kms_addfb_basic: exiting, ret=0
11479 12:40:44.257414 vice: /dev/dri/card0
11480 12:40:44.257868 Starting subtest: bad-pitch-256
11481 12:40:44.267052 [1mSubtest bad-pitch-256<8>[ 22.429191] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11482 12:40:44.267947 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11484 12:40:44.270286 : SUCCESS (0.000s)[0m
11485 12:40:44.277389 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11486 12:40:44.280692 Test requirement: is_i915_device(fd)
11487 12:40:44.287303 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11488 12:40:44.290451 Test requirement: is_i915_device(fd)
11489 12:40:44.297178 No KMS<14>[ 22.458991] [IGT] kms_addfb_basic: executing
11490 12:40:44.300173 driver or no outputs, pipes: 8, outputs: 0
11491 12:40:44.310582 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.<14>[ 22.472170] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11492 12:40:44.320765 75-cip14 aarch64<14>[ 22.479981] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11493 12:40:44.321347 )
11494 12:40:44.323648 Opened device: /dev/dri/card0
11495 12:40:44.326585 Starting subtest: bad-pitch-1024
11496 12:40:44.330674 [1mSubtest <14>[ 22.495125] [IGT] kms_addfb_basic: exiting, ret=0
11497 12:40:44.334038 bad-pitch-1024: SUCCESS (0.000s)[0m
11498 12:40:44.346827 Test requirement not met in function igt_r<8>[ 22.507536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11499 12:40:44.347717 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11501 12:40:44.349965 equire_i915, file ../lib/drmtest.c:720:
11502 12:40:44.353332 Test requirement: is_i915_device(fd)
11503 12:40:44.360161 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11504 12:40:44.363352 Test requirement: is_i915_device(fd)
11505 12:40:44.366758 No KMS driver or no outputs, pipes: 8, outputs: 0
11506 12:40:44.372969 <14>[ 22.536444] [IGT] kms_addfb_basic: executing
11507 12:40:44.379941 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11508 12:40:44.386634 Opened device: /dev/dri/ca<14>[ 22.548851] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11509 12:40:44.387241 rd0
11510 12:40:44.396531 <14>[ 22.556811] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11511 12:40:44.399692 Starting subtest: bad-pitch-999
11512 12:40:44.406435 [1mSubtest bad-pitch-999: SUCCESS (0.000s)[0m<14>[ 22.571015] [IGT] kms_addfb_basic: exiting, ret=0
11513 12:40:44.406897
11514 12:40:44.416899 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11515 12:40:44.423193 Test requir<8>[ 22.583471] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11516 12:40:44.424113 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11518 12:40:44.426860 ement: is_i915_device(fd)
11519 12:40:44.433322 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11520 12:40:44.436332 Test requirement: is_i915_device(fd)
11521 12:40:44.443519 No KMS drive<14>[ 22.604920] [IGT] kms_addfb_basic: executing
11522 12:40:44.446207 r or no outputs, pipes: 8, outputs: 0
11523 12:40:44.457035 IGT-Version: 1.27.1-g621c2d3 (aarch64) (L<14>[ 22.616862] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11524 12:40:44.463425 inux: 6.1.75-cip<14>[ 22.624095] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11525 12:40:44.466764 14 aarch64)
11526 12:40:44.467321 Opened device: /dev/dri/card0
11527 12:40:44.470158 Starting subtest: bad-pitch-65536
11528 12:40:44.475984 <14>[ 22.638792] [IGT] kms_addfb_basic: exiting, ret=0
11529 12:40:44.479273 [1mSubtest bad-pitch-65536: SUCCESS (0.000s)[0m
11530 12:40:44.492890 Test requirement not met in function igt_requi<8>[ 22.651863] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11531 12:40:44.493746 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11533 12:40:44.496201 re_i915, file ../lib/drmtest.c:720:
11534 12:40:44.499552 Test requirement: is_i915_device(fd)
11535 12:40:44.506081 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11536 12:40:44.509647 Test requirement: is_i915_device(fd)
11537 12:40:44.512527 No KMS driver or no outputs, pipes: 8, outputs: 0
11538 12:40:44.519136 <14>[ 22.682327] [IGT] kms_addfb_basic: executing
11539 12:40:44.526144 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11540 12:40:44.526844 Opened device: /dev/dri/card0
11541 12:40:44.535309 <14>[ 22.696372] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11542 12:40:44.541931 Starting subtest<14>[ 22.703564] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11543 12:40:44.545882 : invalid-get-prop-any
11544 12:40:44.555835 [1mSubtest invalid-get-prop-any: SUCCES<14>[ 22.717363] [IGT] kms_addfb_basic: exiting, ret=0
11545 12:40:44.556389 S (0.000s)[0m
11546 12:40:44.568748 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720<8>[ 22.730491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11547 12:40:44.569579 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11549 12:40:44.572356 :
11550 12:40:44.575648 Test requirement: is_i915_device(fd)
11551 12:40:44.582241 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11552 12:40:44.585462 Test requirement: is_i915_device(fd)
11553 12:40:44.588569 No KMS driver or no outputs, pipes: 8, outputs: 0
11554 12:40:44.597700 <14>[ 22.761226] [IGT] kms_addfb_basic: executing
11555 12:40:44.603815 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11556 12:40:44.607313 Opened device: /dev/dri/card0
11557 12:40:44.613928 <14>[ 22.775355] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11558 12:40:44.620930 Starting subtest<14>[ 22.782192] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11559 12:40:44.624093 : invalid-get-prop
11560 12:40:44.633989 [1mSubtest invalid-get-prop: SUCCESS (0.000<14>[ 22.795546] [IGT] kms_addfb_basic: exiting, ret=0
11561 12:40:44.634582 s)[0m
11562 12:40:44.640791 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11563 12:40:44.647326 Test <8>[ 22.808799] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11564 12:40:44.648179 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11566 12:40:44.650508 requirement: is_i915_device(fd)
11567 12:40:44.657317 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11568 12:40:44.666847 Test requirement: is_i915_de<14>[ 22.829575] [IGT] kms_addfb_basic: executing
11569 12:40:44.667417 vice(fd)
11570 12:40:44.670588 No KMS driver or no outputs, pipes: 8, outputs: 0
11571 12:40:44.683909 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.<14>[ 22.843070] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11572 12:40:44.690554 75-cip14 aarch64<14>[ 22.851536] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11573 12:40:44.693739 )
11574 12:40:44.694278 Opened device: /dev/dri/card0
11575 12:40:44.700366 Starting subte<14>[ 22.864600] [IGT] kms_addfb_basic: exiting, ret=0
11576 12:40:44.703479 st: invalid-set-prop-any
11577 12:40:44.717145 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m<8>[ 22.876777] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11578 12:40:44.717705
11579 12:40:44.718348 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11581 12:40:44.723328 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11582 12:40:44.726507 Test requirement: is_i915_device(fd)
11583 12:40:44.733293 Test requirement not met in function <14>[ 22.897777] [IGT] kms_addfb_basic: executing
11584 12:40:44.737153 igt_require_i915, file ../lib/drmtest.c:720:
11585 12:40:44.740282 Test requirement: is_i915_device(fd)
11586 12:40:44.750285 No KMS driver or no outputs,<14>[ 22.911507] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11587 12:40:44.760083 pipes: 8, outpu<14>[ 22.919741] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11588 12:40:44.760745 ts: 0
11589 12:40:44.769582 IGT-Version: 1.27.1-g621c2d3 (aarch64) (L<14>[ 22.932439] [IGT] kms_addfb_basic: exiting, ret=0
11590 12:40:44.770047 inux: 6.1.75-cip14 aarch64)
11591 12:40:44.772958 Opened device: /dev/dri/card0
11592 12:40:44.776740 Starting subtest: invalid-set-prop
11593 12:40:44.783280 <8>[ 22.944840] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11594 12:40:44.784139 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11596 12:40:44.789876 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
11597 12:40:44.796615 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11598 12:40:44.802880 Test requirement: is_i915<14>[ 22.966471] [IGT] kms_addfb_basic: executing
11599 12:40:44.803291 _device(fd)
11600 12:40:44.812752 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11601 12:40:44.819654 Test requirement: is_i915_device<14>[ 22.982406] [IGT] kms_addfb_basic: starting subtest master-rmfb
11602 12:40:44.820100 (fd)
11603 12:40:44.829515 No KMS dri<14>[ 22.989747] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11604 12:40:44.836050 ver or no outputs, pipes: 8, out<14>[ 23.000030] [IGT] kms_addfb_basic: exiting, ret=0
11605 12:40:44.836494 puts: 0
11606 12:40:44.842663 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11607 12:40:44.852560 Opened device: /d<8>[ 23.012828] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11608 12:40:44.852977 ev/dri/card0
11609 12:40:44.853562 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11611 12:40:44.855801 Starting subtest: master-rmfb
11612 12:40:44.859548 [1mSubtest master-rmfb: SUCCESS (0.000s)[0m
11613 12:40:44.866269 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11614 12:40:44.869122 Test requirement: is_i915_device(fd)
11615 12:40:44.879214 Test requirement not met in function igt_re<14>[ 23.043227] [IGT] kms_addfb_basic: executing
11616 12:40:44.882338 quire_i915, file ../lib/drmtest.c:720:
11617 12:40:44.886043 Test requirement: is_i915_device(fd)
11618 12:40:44.889113 No KMS driver or no outputs, pipes: 8, outputs: 0
11619 12:40:44.899040 IGT-Version: 1.27.1-g621c2d3 (a<14>[ 23.061591] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11620 12:40:44.909088 arch64) (Linux: <14>[ 23.069411] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11621 12:40:44.915996 6.1.75-cip14 aar<14>[ 23.079142] [IGT] kms_addfb_basic: exiting, ret=0
11622 12:40:44.916421 ch64)
11623 12:40:44.919082 Opened device: /dev/dri/card0
11624 12:40:44.922592 Starting subtest: addfb25-modifier-no-flag
11625 12:40:44.932660 [1mSubtest ad<8>[ 23.092414] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11626 12:40:44.933344 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11628 12:40:44.936171 dfb25-modifier-no-flag: SUCCESS (0.000s)[0m
11629 12:40:44.942528 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11630 12:40:44.945609 Test requirement: is_i915_device(fd)
11631 12:40:44.955449 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11632 12:40:44.958866 Test r<14>[ 23.123663] [IGT] kms_addfb_basic: executing
11633 12:40:44.962219 equirement: is_i915_device(fd)
11634 12:40:44.965672 No KMS driver or no outputs, pipes: 8, outputs: 0
11635 12:40:44.972407 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11636 12:40:44.979996 Opened <14>[ 23.142287] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11637 12:40:44.982483 device: /dev/dri/card0
11638 12:40:44.985981 Starting subtest: addfb25-bad-modifier
11639 12:40:44.995253 (kms_addfb_basic:438) CRITICAL: <14>[ 23.157046] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11640 12:40:45.002513 Test assertion f<14>[ 23.165903] [IGT] kms_addfb_basic: exiting, ret=98
11641 12:40:45.009034 ailure function addfb25_tests, file ../tests/kms_addfb_basic.c:662:
11642 12:40:45.019068 (kms_addfb_basic:438) CRITI<8>[ 23.179484] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11643 12:40:45.019760 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11645 12:40:45.035505 CAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11646 12:40:45.038879 (kms_addfb_basic:438) CRITICAL: error: 0 != -1
11647 12:40:45.039338 Stack trace:
11648 12:40:45.046085 #0 ../lib/igt<14>[ 23.210380] [IGT] kms_addfb_basic: executing
11649 12:40:45.049405 _core.c:1971 __igt_fail_assert()
11650 12:40:45.051889 #1 [<unknown>+0xd37247e0]
11651 12:40:45.056185 #2 [<unknown>+0xd3726278]
11652 12:40:45.056747 #3 [<unknown>+0xd372167c]
11653 12:40:45.058945 #4 [__libc_start_main+0xe8]
11654 12:40:45.065517 #5 [<unknown>+0xd37216<14>[ 23.229057] [IGT] kms_addfb_basic: exiting, ret=77
11655 12:40:45.066074 b4]
11656 12:40:45.068575 #6 [<unknown>+0xd37216b4]
11657 12:40:45.072017 Subtest addfb25-bad-modifier failed.
11658 12:40:45.075240 **** DEBUG ****
11659 12:40:45.081759 (kms_ad<8>[ 23.242607] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11660 12:40:45.082623 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11662 12:40:45.092996 dfb_basic:438) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11663 12:40:45.102031 (kms_addfb_basic:438) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:662:
11664 12:40:45.111357 (kms_addfb_basic:438) CRITICAL: Failed assertion: i<14>[ 23.274596] [IGT] kms_addfb_basic: executing
11665 12:40:45.124944 gt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11666 12:40:45.132256 (kms_addfb_basic:438)<14>[ 23.293344] [IGT] kms_addfb_basic: exiting, ret=77
11667 12:40:45.132716 CRITICAL: error: 0 != -1
11668 12:40:45.138186 (kms_addfb_basic:438) igt_core-INFO: Stack trace:
11669 12:40:45.148271 (kms_addfb_basic:4<8>[ 23.306770] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11670 12:40:45.149110 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11672 12:40:45.152570 38) igt_core-INFO: #0 ../lib/igt_core.c:1971 __igt_fail_assert()
11673 12:40:45.158717 (kms_addfb_basic:438) igt_core-INFO: #1 [<unknown>+0xd37247e0]
11674 12:40:45.165031 (kms_addfb_basic:438) igt_<14>[ 23.328642] [IGT] kms_addfb_basic: executing
11675 12:40:45.168411 core-INFO: #2 [<unknown>+0xd3726278]
11676 12:40:45.174963 (kms_addfb_basic:438) igt_core-INFO: #3 [<unknown>+0xd372167c]
11677 12:40:45.185157 (kms_addfb_basic:438) igt_core-INFO: #4 [__libc_star<14>[ 23.347181] [IGT] kms_addfb_basic: exiting, ret=77
11678 12:40:45.185704 t_main+0xe8]
11679 12:40:45.191235 (kms_addfb_basic:438) igt_core-INFO: #5 [<unknown>+0xd37216b4]
11680 12:40:45.201089 <8>[ 23.360421] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11681 12:40:45.201830 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11683 12:40:45.204443 (kms_addfb_basic:438) igt_core-INFO: #6 [<unknown>+0xd37216b4]
11684 12:40:45.208097 **** END ****
11685 12:40:45.211306 [1mSubtest addfb25-bad-modifier: FAIL (0.007s)[0m
11686 12:40:45.218009 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11687 12:40:45.221315 Test requirement: is_i915_device(fd)
11688 12:40:45.227677 <14>[ 23.391324] [IGT] kms_addfb_basic: executing
11689 12:40:45.228186
11690 12:40:45.234473 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11691 12:40:45.237807 Test requirement: is_i915_device(fd)
11692 12:40:45.240966 No KMS driver or no outputs, pipes: 8, outputs: 0
11693 12:40:45.247803 IGT<14>[ 23.410282] [IGT] kms_addfb_basic: exiting, ret=77
11694 12:40:45.254516 -Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11695 12:40:45.264958 Opened device: /dev/dri/card0<8>[ 23.424733] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11696 12:40:45.265521
11697 12:40:45.266167 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11699 12:40:45.271092 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11700 12:40:45.275094 Test requirement: is_i915_device(fd)
11701 12:40:45.280919 [1mSubtest addfb25-x-tiled-mismatch-legacy: SKIP (0.000s)[0m
11702 12:40:45.291332 Test requirement not met in function igt_require_i915, file ../lib/dr<14>[ 23.454465] [IGT] kms_addfb_basic: executing
11703 12:40:45.291880 mtest.c:720:
11704 12:40:45.294089 Test requirement: is_i915_device(fd)
11705 12:40:45.300649 No KMS driver or no outputs, pipes: 8, outputs: 0
11706 12:40:45.304102 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11707 12:40:45.310966 Ope<14>[ 23.473642] [IGT] kms_addfb_basic: exiting, ret=77
11708 12:40:45.314806 ned device: /dev/dri/card0
11709 12:40:45.321590 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11710 12:40:45.327868 T<8>[ 23.489301] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11711 12:40:45.328732 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11713 12:40:45.330626 est requirement: is_i915_device(fd)
11714 12:40:45.337563 [1mSubtest addfb25-x-tiled-legacy: SKIP (0.000s)[0m
11715 12:40:45.344326 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11716 12:40:45.347018 Test requirement: is_i915_device(fd)
11717 12:40:45.353976 No KMS driver or no outputs, pipes: 8, outp<14>[ 23.520063] [IGT] kms_addfb_basic: executing
11718 12:40:45.357788 uts: 0
11719 12:40:45.364011 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11720 12:40:45.364573 Opened device: /dev/dri/card0
11721 12:40:45.377936 Test requirement not met in function igt_require_i915, file ../lib/<14>[ 23.538925] [IGT] kms_addfb_basic: exiting, ret=77
11722 12:40:45.378566 drmtest.c:720:
11723 12:40:45.381391 Test requirement: is_i915_device(fd)
11724 12:40:45.390819 [1mSubtest addfb25-framebuffer-vs-set-til<8>[ 23.552350] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11725 12:40:45.391552 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11727 12:40:45.393935 ing: SKIP (0.000s)[0m
11728 12:40:45.400734 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11729 12:40:45.403756 Test requirement: is_i915_device(fd)
11730 12:40:45.410106 No KMS driver or no outputs, pipes: 8, outputs: 0
11731 12:40:45.420677 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 <14>[ 23.582905] [IGT] kms_addfb_basic: executing
11732 12:40:45.421225 aarch64)
11733 12:40:45.423309 Opened device: /dev/dri/card0
11734 12:40:45.429968 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11735 12:40:45.433827 Test requirement: is_i915_device(fd)
11736 12:40:45.440115 Test requireme<14>[ 23.602121] [IGT] kms_addfb_basic: exiting, ret=77
11737 12:40:45.446841 nt not met in function igt_require_i915, file ../lib/drmtest.c:720:
11738 12:40:45.457220 Test requirement: is_i915_d<8>[ 23.615600] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11739 12:40:45.457774 evice(fd)
11740 12:40:45.458497 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11742 12:40:45.459892 [1mSubtest basic-x-tiled-legacy: SKIP (0.000s)[0m
11743 12:40:45.466642 No KMS driver or no outputs, pipes: 8, outputs: 0
11744 12:40:45.470507 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11745 12:40:45.473486 Opened device: /dev/dri/card0
11746 12:40:45.482887 Test requirement not met in function igt_require_i915, f<14>[ 23.646736] [IGT] kms_addfb_basic: executing
11747 12:40:45.486346 ile ../lib/drmtest.c:720:
11748 12:40:45.490323 Test requirement: is_i915_device(fd)
11749 12:40:45.496842 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11750 12:40:45.502885 Test requirement: is_i915_de<14>[ 23.666816] [IGT] kms_addfb_basic: exiting, ret=77
11751 12:40:45.506796 vice(fd)
11752 12:40:45.510316 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11753 12:40:45.519760 No KMS driver or no outputs,<8>[ 23.680384] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11754 12:40:45.520336 pipes: 8, outputs: 0
11755 12:40:45.520987 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11757 12:40:45.526318 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11758 12:40:45.529541 Opened device: /dev/dri/card0
11759 12:40:45.536798 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11760 12:40:45.540453 Test requirement: is_i915_device(fd)
11761 12:40:45.546830 Test requirement not met in<14>[ 23.710367] [IGT] kms_addfb_basic: executing
11762 12:40:45.553066 function igt_require_i915, file ../lib/drmtest.c:720:
11763 12:40:45.556330 Test requirement: is_i915_device(fd)
11764 12:40:45.559521 [1mSubtest tile-pitch-mismatch: SKIP (0.000s)[0m
11765 12:40:45.566683 No KMS driver or no outputs, p<14>[ 23.730564] [IGT] kms_addfb_basic: exiting, ret=77
11766 12:40:45.569517 ipes: 8, outputs: 0
11767 12:40:45.580545 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11769 12:40:45.582887 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14<8>[ 23.743606] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11770 12:40:45.583369 aarch64)
11771 12:40:45.586536 Opened device: /dev/dri/card0
11772 12:40:45.593441 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11773 12:40:45.599705 Test requirement: is_i915_device(fd<14>[ 23.762943] [IGT] kms_addfb_basic: executing
11774 12:40:45.600325 )
11775 12:40:45.606175 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11776 12:40:45.609735 Test requirement: is_i915_device(fd)
11777 12:40:45.619598 [1mSubtest basic-y-tiled-legacy: SK<14>[ 23.781607] [IGT] kms_addfb_basic: exiting, ret=77
11778 12:40:45.620165 IP (0.000s)[0m
11779 12:40:45.626730 No KMS driver or no outputs, pipes: 8, outputs: 0
11780 12:40:45.632930 IGT-Version:<8>[ 23.794631] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11781 12:40:45.633788 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11783 12:40:45.636234 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11784 12:40:45.639712 Opened device: /dev/dri/card0
11785 12:40:45.649755 Test requirement not met in function igt_require_i915, <14>[ 23.813003] [IGT] kms_addfb_basic: executing
11786 12:40:45.653047 file ../lib/drmtest.c:720:
11787 12:40:45.656863 Test requirement: is_i915_device(fd)
11788 12:40:45.666787 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:7<14>[ 23.831325] [IGT] kms_addfb_basic: exiting, ret=77
11789 12:40:45.667395 20:
11790 12:40:45.669725 Test requirement: is_i915_device(fd)
11791 12:40:45.680341 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11793 12:40:45.682978 No KMS driver or no outputs, pipes: 8<8>[ 23.843266] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11794 12:40:45.683466 , outputs: 0
11795 12:40:45.686097 [1mSubtest size-max: SKIP (0.000s)[0m
11796 12:40:45.692766 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11797 12:40:45.696736 Opened device: /dev/dri/card0
11798 12:40:45.703118 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11799 12:40:45.709137 Test requirement:<14>[ 23.872295] [IGT] kms_addfb_basic: executing
11800 12:40:45.709619 is_i915_device(fd)
11801 12:40:45.716086 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11802 12:40:45.719735 Test requirement: is_i915_device(fd)
11803 12:40:45.729998 No KMS driver or no outputs, pipes<14>[ 23.891643] [IGT] kms_addfb_basic: exiting, ret=77
11804 12:40:45.730601 : 8, outputs: 0
11805 12:40:45.732807 [1mSubtest too-wide: SKIP (0.000s)[0m
11806 12:40:45.739322 IGT-Ve<8>[ 23.903245] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11807 12:40:45.740190 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11809 12:40:45.746462 rsion: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11810 12:40:45.749232 Opened device: /dev/dri/card0
11811 12:40:45.759221 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:<14>[ 23.924922] [IGT] kms_addfb_basic: executing
11812 12:40:45.762649
11813 12:40:45.765959 Test requirement: is_i915_device(fd)
11814 12:40:45.772786 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11815 12:40:45.778988 Test requirement: is_<14>[ 23.942398] [IGT] kms_addfb_basic: exiting, ret=77
11816 12:40:45.779445 i915_device(fd)
11817 12:40:45.785886 No KMS driver or no outputs, pipes: 8, outputs: 0
11818 12:40:45.793057 [1mSubtest <8>[ 23.954194] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11819 12:40:45.793903 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11821 12:40:45.795505 too-high: SKIP (0.000s)[0m
11822 12:40:45.802274 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11823 12:40:45.805270 Opened device: /dev/dri/card0
11824 12:40:45.812454 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11825 12:40:45.815506 Test requirement: is_i915_device(fd)
11826 12:40:45.819004 Test <14>[ 23.984308] [IGT] kms_addfb_basic: executing
11827 12:40:45.828887 requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11828 12:40:45.831962 Test requirement: is_i915_device(fd)
11829 12:40:45.835009 No KMS driver or no outputs, pipes: 8, outputs: 0
11830 12:40:45.842317 [1mSubte<14>[ 24.003773] [IGT] kms_addfb_basic: exiting, ret=77
11831 12:40:45.845098 st bo-too-small: SKIP (0.000s)[0m
11832 12:40:45.855488 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11834 12:40:45.858727 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 <8>[ 24.017107] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11835 12:40:45.859165 aarch64)
11836 12:40:45.863087 Opened device: /dev/dri/card0
11837 12:40:45.868263 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11838 12:40:45.871550 Test requirement: is_i915_device(fd)
11839 12:40:45.878249 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11840 12:40:45.885307 Test requir<14>[ 24.048119] [IGT] kms_addfb_basic: executing
11841 12:40:45.885741 ement: is_i915_device(fd)
11842 12:40:45.891756 No KMS driver or no outputs, pipes: 8, outputs: 0
11843 12:40:45.894998 [1mSubtest small-bo: SKIP (0.000s)[0m
11844 12:40:45.901788 IGT-Version: 1.27.1-g621c2d3 (aarch64) (L<14>[ 24.067022] [IGT] kms_addfb_basic: exiting, ret=77
11845 12:40:45.904811 inux: 6.1.75-cip14 aarch64)
11846 12:40:45.908067 Opened device: /dev/dri/card0
11847 12:40:45.918290 Test requirement not met in function<8>[ 24.079436] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11848 12:40:45.919149 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11850 12:40:45.925813 igt_require_i915, file ../lib/drmtest.c:720:
11851 12:40:45.928397 Test requirement: is_i915_device(fd)
11852 12:40:45.938354 Test requirement not met in function igt_require_i915, file<14>[ 24.100758] [IGT] kms_addfb_basic: executing
11853 12:40:45.939078 ../lib/drmtest.c:720:
11854 12:40:45.941350 Test requirement: is_i915_device(fd)
11855 12:40:45.944998 No KMS driver or no outputs, pipes: 8, outputs: 0
11856 12:40:45.955365 [1mSubtest bo-too-small-due-to<14>[ 24.118114] [IGT] kms_addfb_basic: exiting, ret=77
11857 12:40:45.958687 -tiling: SKIP (0.000s)[0m
11858 12:40:45.968027 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.7<8>[ 24.129728] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11859 12:40:45.968871 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11861 12:40:45.971478 5-cip14 aarch64)
11862 12:40:45.975427 Opened device: /dev/dri/card0
11863 12:40:45.981552 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11864 12:40:45.985108 Test requirement: is_i915_device(fd)
11865 12:40:45.991272 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11866 12:40:45.999137 Tes<14>[ 24.160262] [IGT] kms_addfb_basic: executing
11867 12:40:45.999696 t requirement: is_i915_device(fd)
11868 12:40:46.004303 No KMS driver or no outputs, pipes: 8, outputs: 0
11869 12:40:46.007704 [1mSubtest addfb25-y-tiled-legacy: SKIP (0.000s)[0m
11870 12:40:46.018021 IGT-Version: 1.27.1-g621c2d3 (aarch<14>[ 24.179642] [IGT] kms_addfb_basic: exiting, ret=77
11871 12:40:46.021132 64) (Linux: 6.1.75-cip14 aarch64)
11872 12:40:46.021605 Opened device: /dev/dri/card0
11873 12:40:46.031181 Test requirement not met in fu<8>[ 24.192861] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11874 12:40:46.031861 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11876 12:40:46.038084 nction igt_require_i915, file ..<8>[ 24.202939] <LAVA_SIGNAL_TESTSET STOP>
11877 12:40:46.039090 Received signal: <TESTSET> STOP
11878 12:40:46.039481 Closing test_set kms_addfb_basic
11879 12:40:46.041654 /lib/drmtest.c:720:
11880 12:40:46.044497 Test requirement: is_i915_device(fd)
11881 12:40:46.051018 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11882 12:40:46.054696 Test requirement: is_i915_device(fd)
11883 12:40:46.058012 No KMS driver or no outputs, pipes: 8, outputs: 0
11884 12:40:46.064748 [1mSubtest addfb25-yf-tiled-legacy: SKIP (0.000s)[0m
11885 12:40:46.071400 IGT-Version: 1.27<8>[ 24.233778] <LAVA_SIGNAL_TESTSET START kms_atomic>
11886 12:40:46.072238 Received signal: <TESTSET> START kms_atomic
11887 12:40:46.072626 Starting test_set kms_atomic
11888 12:40:46.075227 .1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11889 12:40:46.077689 Opened device: /dev/dri/card0
11890 12:40:46.084904 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11891 12:40:46.087965 Test requirement: is_i915_device(fd)
11892 12:40:46.094120 Test requirement not met in functio<14>[ 24.260334] [IGT] kms_atomic: executing
11893 12:40:46.100760 n igt_require_i9<14>[ 24.265805] [IGT] kms_atomic: exiting, ret=77
11894 12:40:46.105005 15, file ../lib/drmtest.c:720:
11895 12:40:46.108381 Test requirement: is_i915_device(fd)
11896 12:40:46.117030 No KMS driver or no output<8>[ 24.278331] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11897 12:40:46.117769 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11899 12:40:46.121005 s, pipes: 8, outputs: 0
11900 12:40:46.123692 [1mSubtest addfb25-y-tiled-small-legacy: SKIP (0.000s)[0m
11901 12:40:46.134047 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip1<14>[ 24.299389] [IGT] kms_atomic: executing
11902 12:40:46.137041 4 aarch64)
11903 12:40:46.140471 Open<14>[ 24.304120] [IGT] kms_atomic: exiting, ret=77
11904 12:40:46.144053 ed device: /dev/dri/card0
11905 12:40:46.154262 Test requirement not met in function igt_require_i915<8>[ 24.316524] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11906 12:40:46.155178 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11908 12:40:46.157469 , file ../lib/drmtest.c:720:
11909 12:40:46.160966 Test requirement: is_i915_device(fd)
11910 12:40:46.167289 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11911 12:40:46.170872 Test requirement: is_i915_device(fd)
11912 12:40:46.177140 No KMS driver or no outputs, pipes: 8, outputs: 0
11913 12:40:46.184107 [1mSubtest addfb25-4-tiled: SKI<14>[ 24.347736] [IGT] kms_atomic: executing
11914 12:40:46.184664 P (0.000s)[0m
11915 12:40:46.191049 <14>[ 24.353080] [IGT] kms_atomic: exiting, ret=77
11916 12:40:46.193690 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11917 12:40:46.197283 Opened device: /dev/dri/card0
11918 12:40:46.207051 No KMS driv<8>[ 24.367758] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11919 12:40:46.207896 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11921 12:40:46.210276 er or no outputs, pipes: 8, outputs: 0
11922 12:40:46.217294 [1mSubtest plane-overlay-legacy: SKIP (0.000s)[0m
11923 12:40:46.223308 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11924 12:40:46.223764 Opened device: /dev/dri/card0
11925 12:40:46.230431 No KMS driver or no outputs, pipes: 8, outputs: 0
11926 12:40:46.236794 [1mSubtest plane-primary-l<14>[ 24.400059] [IGT] kms_atomic: executing
11927 12:40:46.240191 egacy: SKIP (0.0<14>[ 24.405774] [IGT] kms_atomic: exiting, ret=77
11928 12:40:46.243979 00s)[0m
11929 12:40:46.250743 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11930 12:40:46.251296 Opened device: /dev/dri/card0
11931 12:40:46.260232 N<8>[ 24.420300] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11932 12:40:46.261081 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11934 12:40:46.263152 o KMS driver or no outputs, pipes: 8, outputs: 0
11935 12:40:46.270725 [1mSubtest plane-primary-overlay-mutable-zpos: SKIP (0.000s)[0m
11936 12:40:46.276569 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Lin<14>[ 24.441457] [IGT] kms_atomic: executing
11937 12:40:46.283094 ux: 6.1.75-cip14<14>[ 24.446956] [IGT] kms_atomic: exiting, ret=77
11938 12:40:46.283544 aarch64)
11939 12:40:46.287007 Opened device: /dev/dri/card0
11940 12:40:46.297158 No KMS driver or no outputs, pipes: 8,<8>[ 24.459224] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11941 12:40:46.298237 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11943 12:40:46.300182 outputs: 0
11944 12:40:46.303426 [1mSubtest plane-immutable-zpos: SKIP (0.000s)[0m
11945 12:40:46.309912 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11946 12:40:46.313711 Opened d<14>[ 24.478349] [IGT] kms_atomic: executing
11947 12:40:46.320878 evice: /dev/dri/<14>[ 24.483588] [IGT] kms_atomic: exiting, ret=77
11948 12:40:46.321467 card0
11949 12:40:46.326668 No KMS driver or no outputs, pipes: 8, outputs: 0
11950 12:40:46.333322 [1mSubtest test-only:<8>[ 24.495764] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
11951 12:40:46.334347 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
11953 12:40:46.336534 SKIP (0.000s)[0m
11954 12:40:46.343127 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11955 12:40:46.346306 Opened device: /dev/dri/card0
11956 12:40:46.349780 No KMS driver or no outputs, pipes: 8, outputs: 0
11957 12:40:46.353155 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
11958 12:40:46.361486 <14>[ 24.525456] [IGT] kms_atomic: executing
11959 12:40:46.368135 IGT-Version: 1.2<14>[ 24.530439] [IGT] kms_atomic: exiting, ret=77
11960 12:40:46.371591 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11961 12:40:46.381018 Opened device: /dev/dri/ca<8>[ 24.542236] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
11962 12:40:46.381562 rd0
11963 12:40:46.382190 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
11965 12:40:46.388165 No KMS driver or no outputs, pipes: 8, outputs: 0
11966 12:40:46.390971 [1mSubtest plane-invalid-params: SKIP (0.000s)[0m
11967 12:40:46.408566 <14>[ 24.572577] [IGT] kms_atomic: executing
11968 12:40:46.415320 IGT-Version: 1.2<14>[ 24.577650] [IGT] kms_atomic: exiting, ret=77
11969 12:40:46.418833 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11970 12:40:46.428645 Opened dev<8>[ 24.588514] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
11971 12:40:46.429207 ice: /dev/dri/card0
11972 12:40:46.429854 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
11974 12:40:46.435072 No KMS driver or no outputs, pipes: 8, outputs: 0
11975 12:40:46.438966 [1mSubtest plane-invalid-params-fence: SKIP (0.000s)[0m
11976 12:40:46.455518 <14>[ 24.619237] [IGT] kms_atomic: executing
11977 12:40:46.462193 IGT-Version: 1.2<14>[ 24.624139] [IGT] kms_atomic: exiting, ret=77
11978 12:40:46.465068 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11979 12:40:46.475204 Opened device: /dev/dri/ca<8>[ 24.635367] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
11980 12:40:46.475752 rd0
11981 12:40:46.476385 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
11983 12:40:46.482120 No KMS driver or no outputs, pipes: 8, outputs: 0
11984 12:40:46.485640 [1mSubtest crtc-invalid-params: SKIP (0.000s)[0m
11985 12:40:46.502516 <14>[ 24.666450] [IGT] kms_atomic: executing
11986 12:40:46.509085 IGT-Version: 1.2<14>[ 24.671406] [IGT] kms_atomic: exiting, ret=77
11987 12:40:46.512526 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11988 12:40:46.522331 Opened device: /dev/dri/ca<8>[ 24.682854] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
11989 12:40:46.523111 rd0
11990 12:40:46.523766 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
11992 12:40:46.528655 No KMS driver or no outputs, pipes: 8, outputs: 0
11993 12:40:46.532452 [1mSubtest crtc-invalid-params-fence: SKIP (0.000s)[0m
11994 12:40:46.550184 <14>[ 24.713909] [IGT] kms_atomic: executing
11995 12:40:46.556137 IGT-Version: 1.2<14>[ 24.718903] [IGT] kms_atomic: exiting, ret=77
11996 12:40:46.559769 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
11997 12:40:46.569739 Opened dev<8>[ 24.730109] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
11998 12:40:46.570296 ice: /dev/dri/card0
11999 12:40:46.570983 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
12001 12:40:46.576630 No KMS driver or no outputs, pipes: 8, outputs: 0
12002 12:40:46.579851 [1mSubtest atomic-invalid-params: SKIP (0.000s)[0m
12003 12:40:46.596150 <14>[ 24.760011] [IGT] kms_atomic: executing
12004 12:40:46.603289 IGT-Version: 1.2<14>[ 24.764936] [IGT] kms_atomic: exiting, ret=77
12005 12:40:46.606028 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12006 12:40:46.615475 Opened device: /dev/dri/ca<8>[ 24.776142] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic_plane_damage RESULT=skip>
12007 12:40:46.615936 rd0
12008 12:40:46.616567 Received signal: <TESTCASE> TEST_CASE_ID=atomic_plane_damage RESULT=skip
12010 12:40:46.622655 No KMS driver or no outputs<8>[ 24.786849] <LAVA_SIGNAL_TESTSET STOP>
12011 12:40:46.623500 Received signal: <TESTSET> STOP
12012 12:40:46.623883 Closing test_set kms_atomic
12013 12:40:46.625832 , pipes: 8, outputs: 0
12014 12:40:46.629331 [1mSubtest atomic_plane_damage: SKIP (0.000s)[0m
12015 12:40:46.653592 <8>[ 24.817380] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
12016 12:40:46.654474 Received signal: <TESTSET> START kms_flip_event_leak
12017 12:40:46.654870 Starting test_set kms_flip_event_leak
12018 12:40:46.679930 <14>[ 24.844233] [IGT] kms_flip_event_leak: executing
12019 12:40:46.686958 IGT-Version: 1.2<14>[ 24.849930] [IGT] kms_flip_event_leak: exiting, ret=77
12020 12:40:46.693156 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12021 12:40:46.700088 Opened device: /dev/dri/ca<8>[ 24.862846] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12022 12:40:46.700644 rd0
12023 12:40:46.701281 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12025 12:40:46.709930 No KMS driver or no outputs, pipes: 8, outp<8>[ 24.872613] <LAVA_SIGNAL_TESTSET STOP>
12026 12:40:46.710514 uts: 0
12027 12:40:46.711155 Received signal: <TESTSET> STOP
12028 12:40:46.711521 Closing test_set kms_flip_event_leak
12029 12:40:46.712957 [1mSubtest basic: SKIP (0.000s)[0m
12030 12:40:46.730559 <8>[ 24.894452] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
12031 12:40:46.731378 Received signal: <TESTSET> START kms_prop_blob
12032 12:40:46.731849 Starting test_set kms_prop_blob
12033 12:40:46.758392 <14>[ 24.922203] [IGT] kms_prop_blob: executing
12034 12:40:46.765303 IGT-Version: 1.2<14>[ 24.927205] [IGT] kms_prop_blob: starting subtest basic
12035 12:40:46.771768 7.1-g621c2d3 (aa<14>[ 24.934020] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
12036 12:40:46.777766 rch64) (Linux: 6<14>[ 24.941786] [IGT] kms_prop_blob: exiting, ret=0
12037 12:40:46.781363 .1.75-cip14 aarch64)
12038 12:40:46.785359 Opened device: /dev/dri/card0
12039 12:40:46.785911 Starting subtest: basic
12040 12:40:46.794519 [1mSubtest basic:<8>[ 24.955075] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
12041 12:40:46.795054 SUCCESS (0.000s)[0m
12042 12:40:46.795689 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
12044 12:40:46.820112 <14>[ 24.984573] [IGT] kms_prop_blob: executing
12045 12:40:46.827771 IGT-Version: 1.2<14>[ 24.989737] [IGT] kms_prop_blob: starting subtest blob-prop-core
12046 12:40:46.837207 7.1-g621c2d3 (aa<14>[ 24.997226] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
12047 12:40:46.843942 rch64) (Linux: 6<14>[ 25.005726] [IGT] kms_prop_blob: exiting, ret=0
12048 12:40:46.844403 .1.75-cip14 aarch64)
12049 12:40:46.847182 Opened device: /dev/dri/card0
12050 12:40:46.856939 Starting subtest: blob-prop<8>[ 25.018813] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
12051 12:40:46.857647 -core
12052 12:40:46.858531 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
12054 12:40:46.860115 [1mSubtest blob-prop-core: SUCCESS (0.000s)[0m
12055 12:40:46.883873 <14>[ 25.047669] [IGT] kms_prop_blob: executing
12056 12:40:46.889967 IGT-Version: 1.2<14>[ 25.052767] [IGT] kms_prop_blob: starting subtest blob-prop-validate
12057 12:40:46.899915 7.1-g621c2d3 (aa<14>[ 25.060811] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
12058 12:40:46.906713 rch64) (Linux: 6<14>[ 25.069611] [IGT] kms_prop_blob: exiting, ret=0
12059 12:40:46.910049 .1.75-cip14 aarch64)
12060 12:40:46.910541 Opened device: /dev/dri/card0
12061 12:40:46.913792 Starting subtest: blob-prop-validate
12062 12:40:46.923277 [1mS<8>[ 25.083633] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
12063 12:40:46.923963 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12065 12:40:46.926774 ubtest blob-prop-validate: SUCCESS (0.000s)[0m
12066 12:40:46.949582 <14>[ 25.113368] [IGT] kms_prop_blob: executing
12067 12:40:46.956114 IGT-Version: 1.2<14>[ 25.118474] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12068 12:40:46.966111 7.1-g621c2d3 (aa<14>[ 25.126295] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
12069 12:40:46.973520 rch64) (Linux: 6<14>[ 25.135096] [IGT] kms_prop_blob: exiting, ret=0
12070 12:40:46.974034 .1.75-cip14 aarch64)
12071 12:40:46.976058 Opened device: /dev/dri/card0
12072 12:40:46.978951 Starting subtest: blob-prop-lifetime
12073 12:40:46.989474 [1mS<8>[ 25.148496] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12074 12:40:46.990304 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12076 12:40:46.992325 ubtest blob-prop-lifetime: SUCCESS (0.000s)[0m
12077 12:40:47.014767 <14>[ 25.179154] [IGT] kms_prop_blob: executing
12078 12:40:47.021766 IGT-Version: 1.2<14>[ 25.184524] [IGT] kms_prop_blob: starting subtest blob-multiple
12079 12:40:47.031626 7.1-g621c2d3 (aa<14>[ 25.192204] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
12080 12:40:47.038174 rch64) (Linux: 6<14>[ 25.200489] [IGT] kms_prop_blob: exiting, ret=0
12081 12:40:47.038805 .1.75-cip14 aarch64)
12082 12:40:47.041387 Opened device: /dev/dri/card0
12083 12:40:47.051821 Starting subtest: blob-mult<8>[ 25.213599] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12084 12:40:47.052379 iple
12085 12:40:47.053030 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12087 12:40:47.057850 [1mSubtest blob-multiple: SUCCESS (0.000s)[0m
12088 12:40:47.078569 <14>[ 25.242516] [IGT] kms_prop_blob: executing
12089 12:40:47.085273 IGT-Version: 1.2<14>[ 25.247549] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12090 12:40:47.095330 7.1-g621c2d3 (aa<14>[ 25.255631] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
12091 12:40:47.101766 rch64) (Linux: 6<14>[ 25.264674] [IGT] kms_prop_blob: exiting, ret=0
12092 12:40:47.105150 .1.75-cip14 aarch64)
12093 12:40:47.105616 Opened device: /dev/dri/card0
12094 12:40:47.114656 Starting subtest: invalid-g<8>[ 25.277773] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12095 12:40:47.115501 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12097 12:40:47.118265 et-prop-any
12098 12:40:47.121357 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
12099 12:40:47.143420 <14>[ 25.307467] [IGT] kms_prop_blob: executing
12100 12:40:47.149738 IGT-Version: 1.2<14>[ 25.312535] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12101 12:40:47.159592 7.1-g621c2d3 (aa<14>[ 25.320299] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
12102 12:40:47.166221 rch64) (Linux: 6<14>[ 25.328999] [IGT] kms_prop_blob: exiting, ret=0
12103 12:40:47.166809 .1.75-cip14 aarch64)
12104 12:40:47.169789 Opened device: /dev/dri/card0
12105 12:40:47.173239 Starting subtest: invalid-get-prop
12106 12:40:47.182942 [1mSub<8>[ 25.342236] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12107 12:40:47.183816 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12109 12:40:47.186115 test invalid-get-prop: SUCCESS (0.000s)[0m
12110 12:40:47.201692 <14>[ 25.365895] [IGT] kms_prop_blob: executing
12111 12:40:47.208303 IGT-Version: 1.2<14>[ 25.370657] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12112 12:40:47.218820 7.1-g621c2d3 (aa<14>[ 25.378805] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
12113 12:40:47.224931 <14>[ 25.387872] [IGT] kms_prop_blob: exiting, ret=0
12114 12:40:47.228475 rch64) (Linux: 6.1.75-cip14 aarch64)
12115 12:40:47.234980 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12117 12:40:47.238942 Opened device: /dev/dri/ca<8>[ 25.398284] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12118 12:40:47.239510 rd0
12119 12:40:47.242175 Starting subtest: invalid-set-prop-any
12120 12:40:47.245181 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
12121 12:40:47.256930 <14>[ 25.420732] [IGT] kms_prop_blob: executing
12122 12:40:47.263543 IGT-Version: 1.2<14>[ 25.425550] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12123 12:40:47.273234 7.1-g621c2d3 (aa<14>[ 25.433542] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
12124 12:40:47.280114 rch64) (Linux: 6<14>[ 25.442026] [IGT] kms_prop_blob: exiting, ret=0
12125 12:40:47.280730 .1.75-cip14 aarch64)
12126 12:40:47.283090 Opened device: /dev/dri/card0
12127 12:40:47.293085 Starting su<8>[ 25.453476] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12128 12:40:47.293922 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12130 12:40:47.296219 btest: invalid-s<8>[ 25.462435] <LAVA_SIGNAL_TESTSET STOP>
12131 12:40:47.296934 Received signal: <TESTSET> STOP
12132 12:40:47.297321 Closing test_set kms_prop_blob
12133 12:40:47.299710 et-prop
12134 12:40:47.302972 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
12135 12:40:47.327119 <8>[ 25.491740] <LAVA_SIGNAL_TESTSET START kms_setmode>
12136 12:40:47.327925 Received signal: <TESTSET> START kms_setmode
12137 12:40:47.328303 Starting test_set kms_setmode
12138 12:40:47.354526 <14>[ 25.518320] [IGT] kms_setmode: executing
12139 12:40:47.360571 IGT-Version: 1.2<14>[ 25.523586] [IGT] kms_setmode: starting subtest basic
12140 12:40:47.367340 7.1-g621c2d3 (aa<14>[ 25.530181] [IGT] kms_setmode: finished subtest basic, SKIP
12141 12:40:47.374386 rch64) (Linux: 6<14>[ 25.537497] [IGT] kms_setmode: exiting, ret=77
12142 12:40:47.377502 .1.75-cip14 aarch64)
12143 12:40:47.381187 Opened device: /dev/dri/card0
12144 12:40:47.381745 Starting subtest: basic
12145 12:40:47.390829 No dynamic tests e<8>[ 25.550839] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12146 12:40:47.391392 xecuted.
12147 12:40:47.392034 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12149 12:40:47.394432 [1mSubtest basic: SKIP (0.000s)[0m
12150 12:40:47.415697 <14>[ 25.580189] [IGT] kms_setmode: executing
12151 12:40:47.422617 IGT-Version: 1.2<14>[ 25.585199] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12152 12:40:47.432800 7.1-g621c2d3 (aa<14>[ 25.593313] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
12153 12:40:47.439340 rch64) (Linux: 6<14>[ 25.602162] [IGT] kms_setmode: exiting, ret=77
12154 12:40:47.442678 .1.75-cip14 aarch64)
12155 12:40:47.443233 Opened device: /dev/dri/card0
12156 12:40:47.452465 Starting subtest: basic-clo<8>[ 25.615072] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12157 12:40:47.453301 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12159 12:40:47.455730 ne-single-crtc
12160 12:40:47.459324 No dynamic tests executed.
12161 12:40:47.462370 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m
12162 12:40:47.481088 <14>[ 25.645449] [IGT] kms_setmode: executing
12163 12:40:47.487687 IGT-Version: 1.2<14>[ 25.650496] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12164 12:40:47.498155 7.1-g621c2d3 (aa<14>[ 25.658844] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
12165 12:40:47.504494 rch64) (Linux: 6<14>[ 25.667887] [IGT] kms_setmode: exiting, ret=77
12166 12:40:47.508398 .1.75-cip14 aarch64)
12167 12:40:47.509024 Opened device: /dev/dri/card0
12168 12:40:47.521088 Starting subtest: invalid-clone-single-crtc<8>[ 25.681266] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12169 12:40:47.521647
12170 12:40:47.522312 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12172 12:40:47.524451 No dynamic tests executed.
12173 12:40:47.527409 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)[0m
12174 12:40:47.541351 <14>[ 25.705430] [IGT] kms_setmode: executing
12175 12:40:47.547547 IGT-Version: 1.2<14>[ 25.710103] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12176 12:40:47.557842 7.1-g621c2d3 (aa<14>[ 25.718872] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
12177 12:40:47.564850 <14>[ 25.728104] [IGT] kms_setmode: exiting, ret=77
12178 12:40:47.568572 rch64) (Linux: 6.1.75-cip14 aarch64)
12179 12:40:47.577941 Opened device: /dev/dri/ca<8>[ 25.737360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12180 12:40:47.578532 rd0
12181 12:40:47.579174 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12183 12:40:47.581364 Starting subtest: invalid-clone-exclusive-crtc
12184 12:40:47.584400 No dynamic tests executed.
12185 12:40:47.591315 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0.000s)[0m
12186 12:40:47.594667 <14>[ 25.758823] [IGT] kms_setmode: executing
12187 12:40:47.601172 IGT-Version: 1.2<14>[ 25.763952] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12188 12:40:47.611066 7.1-g621c2d3 (aa<14>[ 25.771879] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
12189 12:40:47.617582 rch64) (Linux: 6<14>[ 25.780626] [IGT] kms_setmode: exiting, ret=77
12190 12:40:47.620958 .1.75-cip14 aarch64)
12191 12:40:47.621511 Opened device: /dev/dri/card0
12192 12:40:47.630494 Starting subtest: clone-exc<8>[ 25.792928] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12193 12:40:47.631302 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12195 12:40:47.634153 lusive-crtc
12196 12:40:47.634662 No dynamic tests executed.
12197 12:40:47.641642 [1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0m
12198 12:40:47.648510 <14>[ 25.812616] [IGT] kms_setmode: executing
12199 12:40:47.658869 IGT-Version: 1.2<14>[ 25.817352] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12200 12:40:47.668196 7.1-g621c2d3 (aa<14>[ 25.826482] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
12201 12:40:47.671840 rch64) (Linux: 6<14>[ 25.836350] [IGT] kms_setmode: exiting, ret=77
12202 12:40:47.674793 .1.75-cip14 aarch64)
12203 12:40:47.678796 Opened device: /dev/dri/card0
12204 12:40:47.688347 Starting subtest: invalid-c<8>[ 25.848669] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12205 12:40:47.689175 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12207 12:40:47.694879 lone-single-crtc<8>[ 25.859463] <LAVA_SIGNAL_TESTSET STOP>
12208 12:40:47.695436 -stealing
12209 12:40:47.696084 Received signal: <TESTSET> STOP
12210 12:40:47.696453 Closing test_set kms_setmode
12211 12:40:47.697767 No dynamic tests executed.
12212 12:40:47.704519 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12213 12:40:47.726288 <8>[ 25.889528] <LAVA_SIGNAL_TESTSET START kms_vblank>
12214 12:40:47.727174 Received signal: <TESTSET> START kms_vblank
12215 12:40:47.727566 Starting test_set kms_vblank
12216 12:40:47.751801 <14>[ 25.916228] [IGT] kms_vblank: executing
12217 12:40:47.758573 IGT-Version: 1.2<14>[ 25.921506] [IGT] kms_vblank: exiting, ret=77
12218 12:40:47.762338 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12219 12:40:47.771870 Opened device: /dev/dri/ca<8>[ 25.932933] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12220 12:40:47.772414 rd0
12221 12:40:47.773049 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12223 12:40:47.775342 No KMS driver or no outputs, pipes: 8, outputs: 0
12224 12:40:47.778871 [1mSubtest invalid: SKIP (0.000s)[0m
12225 12:40:47.789219 <14>[ 25.953556] [IGT] kms_vblank: executing
12226 12:40:47.796404 IGT-Version: 1.2<14>[ 25.958280] [IGT] kms_vblank: exiting, ret=77
12227 12:40:47.799270 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12228 12:40:47.809344 Opened device: /dev/dri/ca<8>[ 25.970403] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12229 12:40:47.809915 rd0
12230 12:40:47.810611 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12232 12:40:47.812768 No KMS driver or no outputs, pipes: 8, outputs: 0
12233 12:40:47.815833 [1mSubtest crtc-id: SKIP (0.000s)[0m
12234 12:40:47.824782 <14>[ 25.989055] [IGT] kms_vblank: executing
12235 12:40:47.832191 IGT-Version: 1.2<14>[ 25.993896] [IGT] kms_vblank: exiting, ret=77
12236 12:40:47.834952 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12237 12:40:47.838007 Opened device: /dev/dri/card0
12238 12:40:47.845213 No KMS driv<8>[ 26.006976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip>
12239 12:40:47.846056 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip
12241 12:40:47.851295 er or no outputs, pipes: 8, outputs: 0
12242 12:40:47.854631 [1mSubtest pipe-A-accuracy-idle: SKIP (0.000s)[0m
12243 12:40:47.864380 <14>[ 26.028449] [IGT] kms_vblank: executing
12244 12:40:47.870870 IGT-Version: 1.2<14>[ 26.033239] [IGT] kms_vblank: exiting, ret=77
12245 12:40:47.874073 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12246 12:40:47.877035 Opened device: /dev/dri/card0
12247 12:40:47.884298 No KMS driv<8>[ 26.046109] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle RESULT=skip>
12248 12:40:47.885134 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle RESULT=skip
12250 12:40:47.887707 er or no outputs, pipes: 8, outputs: 0
12251 12:40:47.894147 [1mSubtest pipe-A-query-idle: SKIP (0.000s)[0m
12252 12:40:47.902859 <14>[ 26.066869] [IGT] kms_vblank: executing
12253 12:40:47.909434 IGT-Version: 1.2<14>[ 26.071677] [IGT] kms_vblank: exiting, ret=77
12254 12:40:47.912610 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12255 12:40:47.922566 Opened device: /dev/dri/ca<8>[ 26.084105] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip>
12256 12:40:47.923038 rd0
12257 12:40:47.923672 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip
12259 12:40:47.929447 No KMS driver or no outputs, pipes: 8, outputs: 0
12260 12:40:47.932527 [1mSubtest pipe-A-query-idle-hang: SKIP (0.000s)[0m
12261 12:40:47.940701 <14>[ 26.104832] [IGT] kms_vblank: executing
12262 12:40:47.947013 IGT-Version: 1.2<14>[ 26.109673] [IGT] kms_vblank: exiting, ret=77
12263 12:40:47.950879 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12264 12:40:47.960250 Opened device: /dev/dri/ca<8>[ 26.121717] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked RESULT=skip>
12265 12:40:47.960715 rd0
12266 12:40:47.961347 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked RESULT=skip
12268 12:40:47.963365 No KMS driver or no outputs, pipes: 8, outputs: 0
12269 12:40:47.969834 [1mSubtest pipe-A-query-forked: SKIP (0.000s)[0m
12270 12:40:47.977804 <14>[ 26.141776] [IGT] kms_vblank: executing
12271 12:40:47.983920 IGT-Version: 1.2<14>[ 26.146705] [IGT] kms_vblank: exiting, ret=77
12272 12:40:47.986918 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12273 12:40:47.990605 Opened device: /dev/dri/card0
12274 12:40:48.000544 No KMS driv<8>[ 26.160075] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip>
12275 12:40:48.001005 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip
12277 12:40:48.003587 er or no outputs, pipes: 8, outputs: 0
12278 12:40:48.007351 [1mSubtest pipe-A-query-forked-hang: SKIP (0.000s)[0m
12279 12:40:48.025792 <14>[ 26.190614] [IGT] kms_vblank: executing
12280 12:40:48.032851 IGT-Version: 1.2<14>[ 26.195820] [IGT] kms_vblank: exiting, ret=77
12281 12:40:48.035611 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12282 12:40:48.045922 Opened device: /dev/dri/ca<8>[ 26.207230] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy RESULT=skip>
12283 12:40:48.046303 rd0
12284 12:40:48.046845 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy RESULT=skip
12286 12:40:48.049184 No KMS driver or no outputs, pipes: 8, outputs: 0
12287 12:40:48.055938 [1mSubtest pipe-A-query-busy: SKIP (0.000s)[0m
12288 12:40:48.063359 <14>[ 26.228011] [IGT] kms_vblank: executing
12289 12:40:48.070240 IGT-Version: 1.2<14>[ 26.232734] [IGT] kms_vblank: exiting, ret=77
12290 12:40:48.073495 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12291 12:40:48.083558 Opened device: /dev/dri/ca<8>[ 26.244753] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip>
12292 12:40:48.084057 rd0
12293 12:40:48.084646 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip
12295 12:40:48.090027 No KMS driver or no outputs, pipes: 8, outputs: 0
12296 12:40:48.093544 [1mSubtest pipe-A-query-busy-hang: SKIP (0.000s)[0m
12297 12:40:48.111089 <14>[ 26.274918] [IGT] kms_vblank: executing
12298 12:40:48.116982 IGT-Version: 1.2<14>[ 26.280094] [IGT] kms_vblank: exiting, ret=77
12299 12:40:48.120790 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12300 12:40:48.131385 Opened device: /dev/dri/ca<8>[ 26.292024] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip>
12301 12:40:48.131936 rd0
12302 12:40:48.132576 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip
12304 12:40:48.137614 No KMS driver or no outputs, pipes: 8, outputs: 0
12305 12:40:48.141007 [1mSubtest pipe-A-query-forked-busy: SKIP (0.000s)[0m
12306 12:40:48.158096 <14>[ 26.322189] [IGT] kms_vblank: executing
12307 12:40:48.164460 IGT-Version: 1.2<14>[ 26.327465] [IGT] kms_vblank: exiting, ret=77
12308 12:40:48.168315 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12309 12:40:48.178076 Opened device: /dev/dri/ca<8>[ 26.338897] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip>
12310 12:40:48.178964 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip
12312 12:40:48.180834 rd0
12313 12:40:48.184767 No KMS driver or no outputs, pipes: 8, outputs: 0
12314 12:40:48.187959 [1mSubtest pipe-A-query-forked-busy-hang: SKIP (0.000s)[0m
12315 12:40:48.205465 <14>[ 26.369699] [IGT] kms_vblank: executing
12316 12:40:48.211694 IGT-Version: 1.2<14>[ 26.374885] [IGT] kms_vblank: exiting, ret=77
12317 12:40:48.214985 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12318 12:40:48.225070 Opened device: /dev/dri/ca<8>[ 26.386183] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle RESULT=skip>
12319 12:40:48.225529 rd0
12320 12:40:48.226155 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle RESULT=skip
12322 12:40:48.228737 No KMS driver or no outputs, pipes: 8, outputs: 0
12323 12:40:48.236122 [1mSubtest pipe-A-wait-idle: SKIP (0.000s)[0m
12324 12:40:48.251135 <14>[ 26.415024] [IGT] kms_vblank: executing
12325 12:40:48.257431 IGT-Version: 1.2<14>[ 26.420147] [IGT] kms_vblank: exiting, ret=77
12326 12:40:48.261224 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12327 12:40:48.271031 Opened device: /dev/dri/ca<8>[ 26.431175] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip>
12328 12:40:48.271584 rd0
12329 12:40:48.272217 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip
12331 12:40:48.277436 No KMS driver or no outputs, pipes: 8, outputs: 0
12332 12:40:48.280832 [1mSubtest pipe-A-wait-idle-hang: SKIP (0.000s)[0m
12333 12:40:48.298793 <14>[ 26.462591] [IGT] kms_vblank: executing
12334 12:40:48.304783 IGT-Version: 1.2<14>[ 26.467747] [IGT] kms_vblank: exiting, ret=77
12335 12:40:48.308240 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12336 12:40:48.318331 Opened device: /dev/dri/ca<8>[ 26.479366] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked RESULT=skip>
12337 12:40:48.318972 rd0
12338 12:40:48.319633 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked RESULT=skip
12340 12:40:48.321877 No KMS driver or no outputs, pipes: 8, outputs: 0
12341 12:40:48.328071 [1mSubtest pipe-A-wait-forked: SKIP (0.000s)[0m
12342 12:40:48.345290 <14>[ 26.509564] [IGT] kms_vblank: executing
12343 12:40:48.352068 IGT-Version: 1.2<14>[ 26.514718] [IGT] kms_vblank: exiting, ret=77
12344 12:40:48.355394 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12345 12:40:48.365453 Opened device: /dev/dri/ca<8>[ 26.525833] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip>
12346 12:40:48.366004 rd0
12347 12:40:48.366644 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip
12349 12:40:48.372144 No KMS driver or no outputs, pipes: 8, outputs: 0
12350 12:40:48.375103 [1mSubtest pipe-A-wait-forked-hang: SKIP (0.000s)[0m
12351 12:40:48.383950 <14>[ 26.548036] [IGT] kms_vblank: executing
12352 12:40:48.390542 IGT-Version: 1.2<14>[ 26.552785] [IGT] kms_vblank: exiting, ret=77
12353 12:40:48.393402 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12354 12:40:48.396779 Opened device: /dev/dri/card0
12355 12:40:48.404174 No KMS driv<8>[ 26.566603] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy RESULT=skip>
12356 12:40:48.405005 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy RESULT=skip
12358 12:40:48.406914 er or no outputs, pipes: 8, outputs: 0
12359 12:40:48.413697 [1mSubtest pipe-A-wait-busy: SKIP (0.000s)[0m
12360 12:40:48.421466 <14>[ 26.585974] [IGT] kms_vblank: executing
12361 12:40:48.428037 IGT-Version: 1.2<14>[ 26.590686] [IGT] kms_vblank: exiting, ret=77
12362 12:40:48.431425 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12363 12:40:48.435036 Opened device: /dev/dri/card0
12364 12:40:48.441657 No KMS driv<8>[ 26.603803] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip>
12365 12:40:48.442526 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip
12367 12:40:48.448334 er or no outputs, pipes: 8, outputs: 0
12368 12:40:48.451657 [1mSubtest pipe-A-wait-busy-hang: SKIP (0.000s)[0m
12369 12:40:48.469824 <14>[ 26.634145] [IGT] kms_vblank: executing
12370 12:40:48.476574 IGT-Version: 1.2<14>[ 26.639357] [IGT] kms_vblank: exiting, ret=77
12371 12:40:48.479791 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12372 12:40:48.490216 Opened device: /dev/dri/ca<8>[ 26.650497] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip>
12373 12:40:48.490815 rd0
12374 12:40:48.491459 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip
12376 12:40:48.496862 No KMS driver or no outputs, pipes: 8, outputs: 0
12377 12:40:48.499433 [1mSubtest pipe-A-wait-forked-busy: SKIP (0.000s)[0m
12378 12:40:48.517440 <14>[ 26.681512] [IGT] kms_vblank: executing
12379 12:40:48.523755 IGT-Version: 1.2<14>[ 26.686963] [IGT] kms_vblank: exiting, ret=77
12380 12:40:48.527355 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12381 12:40:48.537528 Opened device: /dev/dri/ca<8>[ 26.698336] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip>
12382 12:40:48.538366 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip
12384 12:40:48.540777 rd0
12385 12:40:48.544059 No KMS driver or no outputs, pipes: 8, outputs: 0
12386 12:40:48.547253 [1mSubtest pipe-A-wait-forked-busy-hang: SKIP (0.000s)[0m
12387 12:40:48.556914 <14>[ 26.720057] [IGT] kms_vblank: executing
12388 12:40:48.562260 IGT-Version: 1.2<14>[ 26.724867] [IGT] kms_vblank: exiting, ret=77
12389 12:40:48.565658 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12390 12:40:48.575556 Opened device: /dev/dri/ca<8>[ 26.736738] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip>
12391 12:40:48.576242 rd0
12392 12:40:48.576879 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip
12394 12:40:48.582510 No KMS driver or no outputs, pipes: 8, outputs: 0
12395 12:40:48.586521 [1mSubtest pipe-A-ts-continuation-idle: SKIP (0.000s)[0m
12396 12:40:48.593683 <14>[ 26.757906] [IGT] kms_vblank: executing
12397 12:40:48.600837 IGT-Version: 1.2<14>[ 26.762629] [IGT] kms_vblank: exiting, ret=77
12398 12:40:48.603175 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12399 12:40:48.613199 Opened device: /dev/dri/ca<8>[ 26.774912] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip>
12400 12:40:48.613740 rd0
12401 12:40:48.614369 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip
12403 12:40:48.619846 No KMS driver or no outputs, pipes: 8, outputs: 0
12404 12:40:48.626778 [1mSubtest pipe-A-ts-continuation-idle-hang: SKIP (0.000s)[0m
12405 12:40:48.641220 <14>[ 26.805730] [IGT] kms_vblank: executing
12406 12:40:48.647995 IGT-Version: 1.2<14>[ 26.810867] [IGT] kms_vblank: exiting, ret=77
12407 12:40:48.651615 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12408 12:40:48.661412 Opened device: /dev/dri/ca<8>[ 26.822162] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip>
12409 12:40:48.662062 rd0
12410 12:40:48.662736 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip
12412 12:40:48.668465 No KMS driver or no outputs, pipes: 8, outputs: 0
12413 12:40:48.674765 [1mSubtest pipe-A-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12414 12:40:48.681419 <14>[ 26.844849] [IGT] kms_vblank: executing
12415 12:40:48.684904 IGT-Version: 1.2<14>[ 26.849727] [IGT] kms_vblank: exiting, ret=77
12416 12:40:48.691127 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12417 12:40:48.700971 Opened device: /dev/dri/ca<8>[ 26.861742] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip>
12418 12:40:48.701522 rd0
12419 12:40:48.702160 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip
12421 12:40:48.707664 No KMS driver or no outputs, pipes: 8, outputs: 0
12422 12:40:48.711174 [1mSubtest pipe-A-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12423 12:40:48.719152 <14>[ 26.883928] [IGT] kms_vblank: executing
12424 12:40:48.726620 IGT-Version: 1.2<14>[ 26.888664] [IGT] kms_vblank: exiting, ret=77
12425 12:40:48.730006 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12426 12:40:48.739665 Opened device: /dev/dri/ca<8>[ 26.900777] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip>
12427 12:40:48.740217 rd0
12428 12:40:48.740855 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip
12430 12:40:48.746211 No KMS driver or no outputs, pipes: 8, outputs: 0
12431 12:40:48.749520 [1mSubtest pipe-A-ts-continuation-suspend: SKIP (0.000s)[0m
12432 12:40:48.757881 <14>[ 26.922140] [IGT] kms_vblank: executing
12433 12:40:48.765207 IGT-Version: 1.2<14>[ 26.926874] [IGT] kms_vblank: exiting, ret=77
12434 12:40:48.767919 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12435 12:40:48.770982 Opened device: /dev/dri/card0
12436 12:40:48.781645 No KMS driv<8>[ 26.939842] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip>
12437 12:40:48.782527 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip
12439 12:40:48.784139 er or no outputs, pipes: 8, outputs: 0
12440 12:40:48.787662 [1mSubtest pipe-A-ts-continuation-modeset: SKIP (0.000s)[0m
12441 12:40:48.807051 <14>[ 26.971318] [IGT] kms_vblank: executing
12442 12:40:48.813344 IGT-Version: 1.2<14>[ 26.976508] [IGT] kms_vblank: exiting, ret=77
12443 12:40:48.817350 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12444 12:40:48.820257 Opened device: /dev/dri/card0
12445 12:40:48.830376 No KMS driver or no outputs<8>[ 26.990618] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip>
12446 12:40:48.831252 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip
12448 12:40:48.833524 , pipes: 8, outputs: 0
12449 12:40:48.840305 [1mSubtest pipe-A-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12450 12:40:48.859153 <14>[ 27.023618] [IGT] kms_vblank: executing
12451 12:40:48.866150 IGT-Version: 1.2<14>[ 27.029106] [IGT] kms_vblank: exiting, ret=77
12452 12:40:48.868998 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12453 12:40:48.873440 Opened device: /dev/dri/card0
12454 12:40:48.883196 No KMS driver or no outputs<8>[ 27.044050] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip>
12455 12:40:48.884038 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip
12457 12:40:48.885430 , pipes: 8, outputs: 0
12458 12:40:48.892767 [1mSubtest pipe-A-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12459 12:40:48.911869 <14>[ 27.075950] [IGT] kms_vblank: executing
12460 12:40:48.918276 IGT-Version: 1.2<14>[ 27.081217] [IGT] kms_vblank: exiting, ret=77
12461 12:40:48.921574 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12462 12:40:48.931717 Opened device: /dev/dri/ca<8>[ 27.092814] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip>
12463 12:40:48.932275 rd0
12464 12:40:48.932920 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip
12466 12:40:48.938500 No KMS driver or no outputs, pipes: 8, outputs: 0
12467 12:40:48.942020 [1mSubtest pipe-B-accuracy-idle: SKIP (0.000s)[0m
12468 12:40:48.950112 <14>[ 27.114145] [IGT] kms_vblank: executing
12469 12:40:48.956604 IGT-Version: 1.2<14>[ 27.118826] [IGT] kms_vblank: exiting, ret=77
12470 12:40:48.959343 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12471 12:40:48.969676 Opened device: /dev/dri/ca<8>[ 27.131057] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle RESULT=skip>
12472 12:40:48.970232 rd0
12473 12:40:48.970941 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle RESULT=skip
12475 12:40:48.972522 No KMS driver or no outputs, pipes: 8, outputs: 0
12476 12:40:48.979463 [1mSubtest pipe-B-query-idle: SKIP (0.000s)[0m
12477 12:40:48.996525 <14>[ 27.160680] [IGT] kms_vblank: executing
12478 12:40:49.003128 IGT-Version: 1.2<14>[ 27.166020] [IGT] kms_vblank: exiting, ret=77
12479 12:40:49.006523 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12480 12:40:49.016227 Opened device: /dev/dri/ca<8>[ 27.176949] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip>
12481 12:40:49.016711 rd0
12482 12:40:49.017351 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip
12484 12:40:49.023659 No KMS driver or no outputs, pipes: 8, outputs: 0
12485 12:40:49.026523 [1mSubtest pipe-B-query-idle-hang: SKIP (0.000s)[0m
12486 12:40:49.034480 <14>[ 27.198519] [IGT] kms_vblank: executing
12487 12:40:49.041044 IGT-Version: 1.2<14>[ 27.203252] [IGT] kms_vblank: exiting, ret=77
12488 12:40:49.044281 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12489 12:40:49.054207 Opened device: /dev/dri/ca<8>[ 27.215659] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked RESULT=skip>
12490 12:40:49.054856 rd0
12491 12:40:49.055507 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked RESULT=skip
12493 12:40:49.060627 No KMS driver or no outputs, pipes: 8, outputs: 0
12494 12:40:49.063760 [1mSubtest pipe-B-query-forked: SKIP (0.000s)[0m
12495 12:40:49.081202 <14>[ 27.245421] [IGT] kms_vblank: executing
12496 12:40:49.087462 IGT-Version: 1.2<14>[ 27.250636] [IGT] kms_vblank: exiting, ret=77
12497 12:40:49.090993 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12498 12:40:49.101505 Opened dev<8>[ 27.261426] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip>
12499 12:40:49.102046 ice: /dev/dri/card0
12500 12:40:49.102722 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip
12502 12:40:49.107755 No KMS driver or no outputs, pipes: 8, outputs: 0
12503 12:40:49.110445 [1mSubtest pipe-B-query-forked-hang: SKIP (0.000s)[0m
12504 12:40:49.117529 <14>[ 27.282154] [IGT] kms_vblank: executing
12505 12:40:49.124787 IGT-Version: 1.2<14>[ 27.286872] [IGT] kms_vblank: exiting, ret=77
12506 12:40:49.128012 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12507 12:40:49.130857 Opened device: /dev/dri/card0
12508 12:40:49.137836 No KMS driv<8>[ 27.300130] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy RESULT=skip>
12509 12:40:49.138723 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy RESULT=skip
12511 12:40:49.140951 er or no outputs, pipes: 8, outputs: 0
12512 12:40:49.146975 [1mSubtest pipe-B-query-busy: SKIP (0.000s)[0m
12513 12:40:49.166012 <14>[ 27.330213] [IGT] kms_vblank: executing
12514 12:40:49.172941 IGT-Version: 1.2<14>[ 27.335480] [IGT] kms_vblank: exiting, ret=77
12515 12:40:49.175851 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12516 12:40:49.185987 Opened device: /dev/dri/ca<8>[ 27.346852] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip>
12517 12:40:49.186587 rd0
12518 12:40:49.187235 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip
12520 12:40:49.192377 No KMS driver or no outputs, pipes: 8, outputs: 0
12521 12:40:49.195849 [1mSubtest pipe-B-query-busy-hang: SKIP (0.000s)[0m
12522 12:40:49.213119 <14>[ 27.377720] [IGT] kms_vblank: executing
12523 12:40:49.220366 IGT-Version: 1.2<14>[ 27.382915] [IGT] kms_vblank: exiting, ret=77
12524 12:40:49.223419 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12525 12:40:49.233348 Opened device: /dev/dri/ca<8>[ 27.394238] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip>
12526 12:40:49.233909 rd0
12527 12:40:49.234539 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip
12529 12:40:49.240168 No KMS driver or no outputs, pipes: 8, outputs: 0
12530 12:40:49.243242 [1mSubtest pipe-B-query-forked-busy: SKIP (0.000s)[0m
12531 12:40:49.252294 <14>[ 27.416077] [IGT] kms_vblank: executing
12532 12:40:49.258302 IGT-Version: 1.2<14>[ 27.420776] [IGT] kms_vblank: exiting, ret=77
12533 12:40:49.261834 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12534 12:40:49.272514 Opened device: /dev/dri/ca<8>[ 27.432896] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip>
12535 12:40:49.273088 rd0
12536 12:40:49.273731 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip
12538 12:40:49.278126 No KMS driver or no outputs, pipes: 8, outputs: 0
12539 12:40:49.281702 [1mSubtest pipe-B-query-forked-busy-hang: SKIP (0.000s)[0m
12540 12:40:49.290175 <14>[ 27.454045] [IGT] kms_vblank: executing
12541 12:40:49.296306 IGT-Version: 1.2<14>[ 27.458757] [IGT] kms_vblank: exiting, ret=77
12542 12:40:49.300372 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12543 12:40:49.309405 Opened device: /dev/dri/ca<8>[ 27.471045] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle RESULT=skip>
12544 12:40:49.309959 rd0
12545 12:40:49.310618 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle RESULT=skip
12547 12:40:49.312824 No KMS driver or no outputs, pipes: 8, outputs: 0
12548 12:40:49.319484 [1mSubtest pipe-B-wait-idle: SKIP (0.000s)[0m
12549 12:40:49.335976 <14>[ 27.500433] [IGT] kms_vblank: executing
12550 12:40:49.342965 IGT-Version: 1.2<14>[ 27.505689] [IGT] kms_vblank: exiting, ret=77
12551 12:40:49.345989 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12552 12:40:49.356353 Opened dev<8>[ 27.516399] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip>
12553 12:40:49.356899 ice: /dev/dri/card0
12554 12:40:49.357536 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip
12556 12:40:49.362613 No KMS driver or no outputs, pipes: 8, outputs: 0
12557 12:40:49.365894 [1mSubtest pipe-B-wait-idle-hang: SKIP (0.000s)[0m
12558 12:40:49.372385 <14>[ 27.537051] [IGT] kms_vblank: executing
12559 12:40:49.379783 IGT-Version: 1.2<14>[ 27.541878] [IGT] kms_vblank: exiting, ret=77
12560 12:40:49.382817 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12561 12:40:49.393149 Opened device: /dev/dri/ca<8>[ 27.553915] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked RESULT=skip>
12562 12:40:49.393704 rd0
12563 12:40:49.394340 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked RESULT=skip
12565 12:40:49.399275 No KMS driver or no outputs, pipes: 8, outputs: 0
12566 12:40:49.402113 [1mSubtest pipe-B-wait-forked: SKIP (0.000s)[0m
12567 12:40:49.418925 <14>[ 27.583701] [IGT] kms_vblank: executing
12568 12:40:49.425740 IGT-Version: 1.2<14>[ 27.588882] [IGT] kms_vblank: exiting, ret=77
12569 12:40:49.429041 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12570 12:40:49.439009 Opened device: /dev/dri/ca<8>[ 27.600469] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip>
12571 12:40:49.439551 rd0
12572 12:40:49.440182 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip
12574 12:40:49.446182 No KMS driver or no outputs, pipes: 8, outputs: 0
12575 12:40:49.448992 [1mSubtest pipe-B-wait-forked-hang: SKIP (0.000s)[0m
12576 12:40:49.466927 <14>[ 27.631100] [IGT] kms_vblank: executing
12577 12:40:49.473583 IGT-Version: 1.2<14>[ 27.636252] [IGT] kms_vblank: exiting, ret=77
12578 12:40:49.476446 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12579 12:40:49.480086 Opened device: /dev/dri/card0
12580 12:40:49.489929 No KMS driver or no outputs<8>[ 27.650426] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy RESULT=skip>
12581 12:40:49.490536 , pipes: 8, outputs: 0
12582 12:40:49.491367 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy RESULT=skip
12584 12:40:49.496722 [1mSubtest pipe-B-wait-busy: SKIP (0.000s)[0m
12585 12:40:49.507283 <14>[ 27.671595] [IGT] kms_vblank: executing
12586 12:40:49.513554 IGT-Version: 1.2<14>[ 27.676320] [IGT] kms_vblank: exiting, ret=77
12587 12:40:49.517427 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12588 12:40:49.526776 Opened device: /dev/dri/ca<8>[ 27.688717] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip>
12589 12:40:49.527323 rd0
12590 12:40:49.527958 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip
12592 12:40:49.533315 No KMS driver or no outputs, pipes: 8, outputs: 0
12593 12:40:49.537246 [1mSubtest pipe-B-wait-busy-hang: SKIP (0.000s)[0m
12594 12:40:49.554344 <14>[ 27.718512] [IGT] kms_vblank: executing
12595 12:40:49.560989 IGT-Version: 1.2<14>[ 27.723727] [IGT] kms_vblank: exiting, ret=77
12596 12:40:49.563807 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12597 12:40:49.574255 Opened device: /dev/dri/ca<8>[ 27.735379] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip>
12598 12:40:49.574850 rd0
12599 12:40:49.575495 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip
12601 12:40:49.580254 No KMS driver or no outputs, pipes: 8, outputs: 0
12602 12:40:49.583834 [1mSubtest pipe-B-wait-forked-busy: SKIP (0.000s)[0m
12603 12:40:49.601404 <14>[ 27.765779] [IGT] kms_vblank: executing
12604 12:40:49.607739 IGT-Version: 1.2<14>[ 27.771059] [IGT] kms_vblank: exiting, ret=77
12605 12:40:49.611037 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12606 12:40:49.621337 Opened device: /dev/dri/ca<8>[ 27.782864] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip>
12607 12:40:49.621902 rd0
12608 12:40:49.622551 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip
12610 12:40:49.628289 No KMS driver or no outputs, pipes: 8, outputs: 0
12611 12:40:49.631007 [1mSubtest pipe-B-wait-forked-busy-hang: SKIP (0.000s)[0m
12612 12:40:49.649768 <14>[ 27.813627] [IGT] kms_vblank: executing
12613 12:40:49.655824 IGT-Version: 1.2<14>[ 27.818748] [IGT] kms_vblank: exiting, ret=77
12614 12:40:49.659170 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12615 12:40:49.669032 Opened device: /dev/dri/ca<8>[ 27.830486] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip>
12616 12:40:49.669586 rd0
12617 12:40:49.670226 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip
12619 12:40:49.675794 No KMS driver or no outputs, pipes: 8, outputs: 0
12620 12:40:49.678681 [1mSubtest pipe-B-ts-continuation-idle: SKIP (0.000s)[0m
12621 12:40:49.687801 <14>[ 27.852237] [IGT] kms_vblank: executing
12622 12:40:49.694887 IGT-Version: 1.2<14>[ 27.856936] [IGT] kms_vblank: exiting, ret=77
12623 12:40:49.698094 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12624 12:40:49.707403 Opened device: /dev/dri/ca<8>[ 27.869414] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip>
12625 12:40:49.707985 rd0
12626 12:40:49.708632 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip
12628 12:40:49.714824 No KMS driver or no outputs, pipes: 8, outputs: 0
12629 12:40:49.717487 [1mSubtest pipe-B-ts-continuation-idle-hang: SKIP (0.000s)[0m
12630 12:40:49.735362 <14>[ 27.899903] [IGT] kms_vblank: executing
12631 12:40:49.742110 IGT-Version: 1.2<14>[ 27.905532] [IGT] kms_vblank: exiting, ret=77
12632 12:40:49.745463 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12633 12:40:49.755188 Opened device: /dev/dri/ca<8>[ 27.917011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip>
12634 12:40:49.756045 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip
12636 12:40:49.758967 rd0
12637 12:40:49.762201 No KMS driver or no outputs, pipes: 8, outputs: 0
12638 12:40:49.768696 [1mSubtest pipe-B-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12639 12:40:49.772840 <14>[ 27.939002] [IGT] kms_vblank: executing
12640 12:40:49.778377 IGT-Version: 1.2<14>[ 27.943779] [IGT] kms_vblank: exiting, ret=77
12641 12:40:49.785531 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12642 12:40:49.795954 Opened device: /dev/dri/ca<8>[ 27.956171] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip>
12643 12:40:49.796512 rd0
12644 12:40:49.797176 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip
12646 12:40:49.802575 No KMS driver or no outputs, pipes: 8, outputs: 0
12647 12:40:49.805490 [1mSubtest pipe-B-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12648 12:40:49.822755 <14>[ 27.987221] [IGT] kms_vblank: executing
12649 12:40:49.829525 IGT-Version: 1.2<14>[ 27.992307] [IGT] kms_vblank: exiting, ret=77
12650 12:40:49.832855 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12651 12:40:49.835996 Opened device: /dev/dri/card0
12652 12:40:49.849164 No KMS driver or no outputs, pipes: 8, outp<8>[ 28.007509] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip>
12653 12:40:49.849794 uts: 0
12654 12:40:49.850493 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip
12656 12:40:49.852196 [1mSubtest pipe-B-ts-continuation-suspend: SKIP (0.000s)[0m
12657 12:40:49.866101 <14>[ 28.030292] [IGT] kms_vblank: executing
12658 12:40:49.872479 IGT-Version: 1.2<14>[ 28.035000] [IGT] kms_vblank: exiting, ret=77
12659 12:40:49.876031 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12660 12:40:49.879250 Opened device: /dev/dri/card0
12661 12:40:49.889052 No KMS driv<8>[ 28.048426] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip>
12662 12:40:49.889862 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip
12664 12:40:49.892930 er or no outputs, pipes: 8, outputs: 0
12665 12:40:49.896291 [1mSubtest pipe-B-ts-continuation-modeset: SKIP (0.000s)[0m
12666 12:40:49.906497 <14>[ 28.070580] [IGT] kms_vblank: executing
12667 12:40:49.912542 IGT-Version: 1.2<14>[ 28.075309] [IGT] kms_vblank: exiting, ret=77
12668 12:40:49.915860 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12669 12:40:49.926209 Opened device: /dev/dri/ca<8>[ 28.087894] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip>
12670 12:40:49.927111 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip
12672 12:40:49.929578 rd0
12673 12:40:49.932402 No KMS driver or no outputs, pipes: 8, outputs: 0
12674 12:40:49.939454 [1mSubtest pipe-B-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12675 12:40:49.954550 <14>[ 28.119049] [IGT] kms_vblank: executing
12676 12:40:49.961656 IGT-Version: 1.2<14>[ 28.124231] [IGT] kms_vblank: exiting, ret=77
12677 12:40:49.964659 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12678 12:40:49.974084 Opened device: /dev/dri/ca<8>[ 28.135454] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip>
12679 12:40:49.974849 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip
12681 12:40:49.977606 rd0
12682 12:40:49.981126 No KMS driver or no outputs, pipes: 8, outputs: 0
12683 12:40:49.987544 [1mSubtest pipe-B-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12684 12:40:50.002759 <14>[ 28.167119] [IGT] kms_vblank: executing
12685 12:40:50.009140 IGT-Version: 1.2<14>[ 28.172314] [IGT] kms_vblank: exiting, ret=77
12686 12:40:50.012520 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12687 12:40:50.015671 Opened device: /dev/dri/card0
12688 12:40:50.022958 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip
12690 12:40:50.026150 No KMS driv<8>[ 28.185008] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip>
12691 12:40:50.030027 er or no outputs, pipes: 8, outputs: 0
12692 12:40:50.032372 [1mSubtest pipe-C-accuracy-idle: SKIP (0.000s)[0m
12693 12:40:50.042588 <14>[ 28.206823] [IGT] kms_vblank: executing
12694 12:40:50.049002 IGT-Version: 1.2<14>[ 28.211549] [IGT] kms_vblank: exiting, ret=77
12695 12:40:50.052760 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12696 12:40:50.062688 Opened device: /dev/dri/ca<8>[ 28.224104] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle RESULT=skip>
12697 12:40:50.063247 rd0
12698 12:40:50.063888 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle RESULT=skip
12700 12:40:50.065347 No KMS driver or no outputs, pipes: 8, outputs: 0
12701 12:40:50.072576 [1mSubtest pipe-C-query-idle: SKIP (0.000s)[0m
12702 12:40:50.088904 <14>[ 28.253698] [IGT] kms_vblank: executing
12703 12:40:50.096044 IGT-Version: 1.2<14>[ 28.258849] [IGT] kms_vblank: exiting, ret=77
12704 12:40:50.099135 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12705 12:40:50.108857 Opened device: /dev/dri/ca<8>[ 28.270034] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip>
12706 12:40:50.109415 rd0
12707 12:40:50.110100 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip
12709 12:40:50.115609 No KMS driver or no outputs, pipes: 8, outputs: 0
12710 12:40:50.118883 [1mSubtest pipe-C-query-idle-hang: SKIP (0.000s)[0m
12711 12:40:50.127357 <14>[ 28.291751] [IGT] kms_vblank: executing
12712 12:40:50.133900 IGT-Version: 1.2<14>[ 28.296497] [IGT] kms_vblank: exiting, ret=77
12713 12:40:50.137736 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12714 12:40:50.140964 Opened device: /dev/dri/card0
12715 12:40:50.150389 No KMS driver or no outputs<8>[ 28.311323] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked RESULT=skip>
12716 12:40:50.150904 , pipes: 8, outputs: 0
12717 12:40:50.151684 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked RESULT=skip
12719 12:40:50.156524 [1mSubtest pipe-C-query-forked: SKIP (0.000s)[0m
12720 12:40:50.167147 <14>[ 28.331603] [IGT] kms_vblank: executing
12721 12:40:50.173172 IGT-Version: 1.2<14>[ 28.336350] [IGT] kms_vblank: exiting, ret=77
12722 12:40:50.176608 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12723 12:40:50.186849 Opened device: /dev/dri/ca<8>[ 28.348685] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip>
12724 12:40:50.187267 rd0
12725 12:40:50.187880 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip
12727 12:40:50.193673 No KMS driver or no outputs, pipes: 8, outputs: 0
12728 12:40:50.197173 [1mSubtest pipe-C-query-forked-hang: SKIP (0.000s)[0m
12729 12:40:50.214129 <14>[ 28.378628] [IGT] kms_vblank: executing
12730 12:40:50.220526 IGT-Version: 1.2<14>[ 28.384012] [IGT] kms_vblank: exiting, ret=77
12731 12:40:50.224261 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12732 12:40:50.234831 Opened device: /dev/dri/ca<8>[ 28.396249] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy RESULT=skip>
12733 12:40:50.235341 rd0
12734 12:40:50.235934 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy RESULT=skip
12736 12:40:50.240326 No KMS driver or no outputs, pipes: 8, outputs: 0
12737 12:40:50.243798 [1mSubtest pipe-C-query-busy: SKIP (0.000s)[0m
12738 12:40:50.261681 <14>[ 28.425865] [IGT] kms_vblank: executing
12739 12:40:50.267993 IGT-Version: 1.2<14>[ 28.431021] [IGT] kms_vblank: exiting, ret=77
12740 12:40:50.271301 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12741 12:40:50.281454 Opened device: /dev/dri/ca<8>[ 28.442153] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip>
12742 12:40:50.282127 rd0
12743 12:40:50.282816 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip
12745 12:40:50.288165 No KMS driver or no outputs, pipes: 8, outputs: 0
12746 12:40:50.291120 [1mSubtest pipe-C-query-busy-hang: SKIP (0.000s)[0m
12747 12:40:50.308701 <14>[ 28.473107] [IGT] kms_vblank: executing
12748 12:40:50.314956 IGT-Version: 1.2<14>[ 28.478260] [IGT] kms_vblank: exiting, ret=77
12749 12:40:50.318438 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12750 12:40:50.328913 Opened device: /dev/dri/ca<8>[ 28.489651] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip>
12751 12:40:50.329471 rd0
12752 12:40:50.330118 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip
12754 12:40:50.334881 No KMS driver or no outputs, pipes: 8, outputs: 0
12755 12:40:50.338292 [1mSubtest pipe-C-query-forked-busy: SKIP (0.000s)[0m
12756 12:40:50.347396 <14>[ 28.511661] [IGT] kms_vblank: executing
12757 12:40:50.354021 IGT-Version: 1.2<14>[ 28.516404] [IGT] kms_vblank: exiting, ret=77
12758 12:40:50.357231 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12759 12:40:50.367028 Opened device: /dev/dri/ca<8>[ 28.527730] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip>
12760 12:40:50.367540 rd0
12761 12:40:50.368174 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip
12763 12:40:50.373517 No KMS driver or no outputs, pipes: 8, outputs: 0
12764 12:40:50.376782 [1mSubtest pipe-C-query-forked-busy-hang: SKIP (0.000s)[0m
12765 12:40:50.394545 <14>[ 28.559175] [IGT] kms_vblank: executing
12766 12:40:50.401415 IGT-Version: 1.2<14>[ 28.564272] [IGT] kms_vblank: exiting, ret=77
12767 12:40:50.404450 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12768 12:40:50.415042 Opened device: /dev/dri/ca<8>[ 28.575988] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle RESULT=skip>
12769 12:40:50.415589 rd0
12770 12:40:50.416219 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle RESULT=skip
12772 12:40:50.417804 No KMS driver or no outputs, pipes: 8, outputs: 0
12773 12:40:50.424516 [1mSubtest pipe-C-wait-idle: SKIP (0.000s)[0m
12774 12:40:50.441713 <14>[ 28.605858] [IGT] kms_vblank: executing
12775 12:40:50.447767 IGT-Version: 1.2<14>[ 28.611026] [IGT] kms_vblank: exiting, ret=77
12776 12:40:50.451288 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12777 12:40:50.461255 Opened device: /dev/dri/ca<8>[ 28.622767] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip>
12778 12:40:50.461812 rd0
12779 12:40:50.462541 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip
12781 12:40:50.468400 No KMS driver or no outputs, pipes: 8, outputs: 0
12782 12:40:50.471006 [1mSubtest pipe-C-wait-idle-hang: SKIP (0.000s)[0m
12783 12:40:50.479524 <14>[ 28.643948] [IGT] kms_vblank: executing
12784 12:40:50.486293 IGT-Version: 1.2<14>[ 28.648708] [IGT] kms_vblank: exiting, ret=77
12785 12:40:50.488997 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12786 12:40:50.499122 Opened device: /dev/dri/ca<8>[ 28.660878] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked RESULT=skip>
12787 12:40:50.499666 rd0
12788 12:40:50.500298 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked RESULT=skip
12790 12:40:50.502786 No KMS driver or no outputs, pipes: 8, outputs: 0
12791 12:40:50.509360 [1mSubtest pipe-C-wait-forked: SKIP (0.000s)[0m
12792 12:40:50.526637 <14>[ 28.690653] [IGT] kms_vblank: executing
12793 12:40:50.533139 IGT-Version: 1.2<14>[ 28.695849] [IGT] kms_vblank: exiting, ret=77
12794 12:40:50.535789 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12795 12:40:50.545987 Opened device: /dev/dri/ca<8>[ 28.707410] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip>
12796 12:40:50.546610 rd0
12797 12:40:50.547438 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip
12799 12:40:50.552522 No KMS driver or no outputs, pipes: 8, outputs: 0
12800 12:40:50.556127 [1mSubtest pipe-C-wait-forked-hang: SKIP (0.000s)[0m
12801 12:40:50.573321 <14>[ 28.737841] [IGT] kms_vblank: executing
12802 12:40:50.579814 IGT-Version: 1.2<14>[ 28.743092] [IGT] kms_vblank: exiting, ret=77
12803 12:40:50.583022 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12804 12:40:50.593064 Opened device: /dev/dri/ca<8>[ 28.755307] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy RESULT=skip>
12805 12:40:50.593611 rd0
12806 12:40:50.594243 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy RESULT=skip
12808 12:40:50.599376 No KMS driver or no outputs, pipes: 8, outputs: 0
12809 12:40:50.603280 [1mSubtest pipe-C-wait-busy: SKIP (0.000s)[0m
12810 12:40:50.620096 <14>[ 28.784662] [IGT] kms_vblank: executing
12811 12:40:50.626867 IGT-Version: 1.2<14>[ 28.790002] [IGT] kms_vblank: exiting, ret=77
12812 12:40:50.630104 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12813 12:40:50.633169 Opened device: /dev/dri/card0
12814 12:40:50.642952 No KMS driver or no outputs<8>[ 28.804190] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip>
12815 12:40:50.643775 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip
12817 12:40:50.646827 , pipes: 8, outputs: 0
12818 12:40:50.649519 [1mSubtest pipe-C-wait-busy-hang: SKIP (0.000s)[0m
12819 12:40:50.663782 <14>[ 28.828201] [IGT] kms_vblank: executing
12820 12:40:50.670371 IGT-Version: 1.2<14>[ 28.832940] [IGT] kms_vblank: exiting, ret=77
12821 12:40:50.673902 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12822 12:40:50.683551 Opened device: /dev/dri/ca<8>[ 28.845094] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip>
12823 12:40:50.684285 rd0
12824 12:40:50.684978 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip
12826 12:40:50.690130 No KMS driver or no outputs, pipes: 8, outputs: 0
12827 12:40:50.693594 [1mSubtest pipe-C-wait-forked-busy: SKIP (0.000s)[0m
12828 12:40:50.700489 <14>[ 28.865286] [IGT] kms_vblank: executing
12829 12:40:50.706968 IGT-Version: 1.2<14>[ 28.870036] [IGT] kms_vblank: exiting, ret=77
12830 12:40:50.710262 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12831 12:40:50.714230 Opened device: /dev/dri/card0
12832 12:40:50.723914 No KMS driv<8>[ 28.883163] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip>
12833 12:40:50.724653 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip
12835 12:40:50.726866 er or no outputs, pipes: 8, outputs: 0
12836 12:40:50.730536 [1mSubtest pipe-C-wait-forked-busy-hang: SKIP (0.000s)[0m
12837 12:40:50.740862 <14>[ 28.905437] [IGT] kms_vblank: executing
12838 12:40:50.747638 IGT-Version: 1.2<14>[ 28.910370] [IGT] kms_vblank: exiting, ret=77
12839 12:40:50.750805 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12840 12:40:50.761453 Opened device: /dev/dri/ca<8>[ 28.922305] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip>
12841 12:40:50.762018 rd0
12842 12:40:50.762663 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip
12844 12:40:50.767400 No KMS driver or no outputs, pipes: 8, outputs: 0
12845 12:40:50.770927 [1mSubtest pipe-C-ts-continuation-idle: SKIP (0.000s)[0m
12846 12:40:50.779777 <14>[ 28.943996] [IGT] kms_vblank: executing
12847 12:40:50.785900 IGT-Version: 1.2<14>[ 28.948766] [IGT] kms_vblank: exiting, ret=77
12848 12:40:50.789422 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12849 12:40:50.799260 Opened device: /dev/dri/ca<8>[ 28.960979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip>
12850 12:40:50.799937 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip
12852 12:40:50.802394 rd0
12853 12:40:50.805794 No KMS driver or no outputs, pipes: 8, outputs: 0
12854 12:40:50.811992 [1mSubtest pipe-C-ts-continuation-idle-hang: SKIP (0.000s)[0m
12855 12:40:50.815840 <14>[ 28.982102] [IGT] kms_vblank: executing
12856 12:40:50.822156 IGT-Version: 1.2<14>[ 28.986869] [IGT] kms_vblank: exiting, ret=77
12857 12:40:50.829123 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12858 12:40:50.829543 Opened device: /dev/dri/card0
12859 12:40:50.838939 No KMS driv<8>[ 29.000153] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip>
12860 12:40:50.839637 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip
12862 12:40:50.842465 er or no outputs, pipes: 8, outputs: 0
12863 12:40:50.848858 [1mSubtest pipe-C-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12864 12:40:50.858350 <14>[ 29.022802] [IGT] kms_vblank: executing
12865 12:40:50.864591 IGT-Version: 1.2<14>[ 29.027548] [IGT] kms_vblank: exiting, ret=77
12866 12:40:50.867627 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12867 12:40:50.877916 Opened dev<8>[ 29.038285] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip>
12868 12:40:50.878693 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip
12870 12:40:50.881377 ice: /dev/dri/card0
12871 12:40:50.884605 No KMS driver or no outputs, pipes: 8, outputs: 0
12872 12:40:50.891142 [1mSubtest pipe-C-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12873 12:40:50.894661 <14>[ 29.059505] [IGT] kms_vblank: executing
12874 12:40:50.901145 IGT-Version: 1.2<14>[ 29.064773] [IGT] kms_vblank: exiting, ret=77
12875 12:40:50.904555 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12876 12:40:50.914497 Opened dev<8>[ 29.075330] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip>
12877 12:40:50.915209 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip
12879 12:40:50.917690 ice: /dev/dri/card0
12880 12:40:50.921099 No KMS driver or no outputs, pipes: 8, outputs: 0
12881 12:40:50.927736 [1mSubtest pipe-C-ts-continuation-suspend: SKIP (0.000s)[0m
12882 12:40:50.931272 <14>[ 29.096561] [IGT] kms_vblank: executing
12883 12:40:50.937417 IGT-Version: 1.2<14>[ 29.101302] [IGT] kms_vblank: exiting, ret=77
12884 12:40:50.941419 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12885 12:40:50.950761 Opened dev<8>[ 29.111920] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip>
12886 12:40:50.951441 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip
12888 12:40:50.954242 ice: /dev/dri/card0
12889 12:40:50.957407 No KMS driver or no outputs, pipes: 8, outputs: 0
12890 12:40:50.963909 [1mSubtest pipe-C-ts-continuation-modeset: SKIP (0.000s)[0m
12891 12:40:50.979189 <14>[ 29.144066] [IGT] kms_vblank: executing
12892 12:40:50.986076 IGT-Version: 1.2<14>[ 29.149254] [IGT] kms_vblank: exiting, ret=77
12893 12:40:50.989124 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12894 12:40:50.998965 Opened device: /dev/dri/ca<8>[ 29.161087] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip>
12895 12:40:50.999656 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip
12897 12:40:51.002629 rd0
12898 12:40:51.005831 No KMS driver or no outputs, pipes: 8, outputs: 0
12899 12:40:51.012125 [1mSubtest pipe-C-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12900 12:40:51.027704 <14>[ 29.192496] [IGT] kms_vblank: executing
12901 12:40:51.034724 IGT-Version: 1.2<14>[ 29.197593] [IGT] kms_vblank: exiting, ret=77
12902 12:40:51.038204 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12903 12:40:51.041004 Opened device: /dev/dri/card0
12904 12:40:51.050966 No KMS driver or no outputs<8>[ 29.212087] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip>
12905 12:40:51.051821 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip
12907 12:40:51.054933 , pipes: 8, outputs: 0
12908 12:40:51.060729 [1mSubtest pipe-C-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12909 12:40:51.079343 <14>[ 29.244122] [IGT] kms_vblank: executing
12910 12:40:51.085847 IGT-Version: 1.2<14>[ 29.249240] [IGT] kms_vblank: exiting, ret=77
12911 12:40:51.089517 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12912 12:40:51.092928 Opened device: /dev/dri/card0
12913 12:40:51.103048 No KMS driver or no outputs<8>[ 29.263846] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip>
12914 12:40:51.103898 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip
12916 12:40:51.105712 , pipes: 8, outputs: 0
12917 12:40:51.109418 [1mSubtest pipe-D-accuracy-idle: SKIP (0.000s)[0m
12918 12:40:51.130332 <14>[ 29.295026] [IGT] kms_vblank: executing
12919 12:40:51.137097 IGT-Version: 1.2<14>[ 29.300197] [IGT] kms_vblank: exiting, ret=77
12920 12:40:51.140445 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12921 12:40:51.143153 Opened device: /dev/dri/card0
12922 12:40:51.150516 No KMS driv<8>[ 29.312854] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle RESULT=skip>
12923 12:40:51.151374 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle RESULT=skip
12925 12:40:51.157427 er or no outputs, pipes: 8, outputs: 0
12926 12:40:51.160444 [1mSubtest pipe-D-query-idle: SKIP (0.000s)[0m
12927 12:40:51.179876 <14>[ 29.344298] [IGT] kms_vblank: executing
12928 12:40:51.186567 IGT-Version: 1.2<14>[ 29.349430] [IGT] kms_vblank: exiting, ret=77
12929 12:40:51.190179 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12930 12:40:51.199521 Opened dev<8>[ 29.360326] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip>
12931 12:40:51.200074 ice: /dev/dri/card0
12932 12:40:51.200718 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip
12934 12:40:51.206053 No KMS driver or no outputs, pipes: 8, outputs: 0
12935 12:40:51.209514 [1mSubtest pipe-D-query-idle-hang: SKIP (0.000s)[0m
12936 12:40:51.226093 <14>[ 29.390818] [IGT] kms_vblank: executing
12937 12:40:51.232985 IGT-Version: 1.2<14>[ 29.395914] [IGT] kms_vblank: exiting, ret=77
12938 12:40:51.235914 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12939 12:40:51.239432 Opened device: /dev/dri/card0
12940 12:40:51.249411 No KMS driver or no outputs<8>[ 29.410437] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked RESULT=skip>
12941 12:40:51.250257 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked RESULT=skip
12943 12:40:51.252383 , pipes: 8, outputs: 0
12944 12:40:51.255932 [1mSubtest pipe-D-query-forked: SKIP (0.000s)[0m
12945 12:40:51.276469 <14>[ 29.440687] [IGT] kms_vblank: executing
12946 12:40:51.282263 IGT-Version: 1.2<14>[ 29.445937] [IGT] kms_vblank: exiting, ret=77
12947 12:40:51.285951 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12948 12:40:51.295645 Opened device: /dev/dri/ca<8>[ 29.457544] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip>
12949 12:40:51.296389 rd0
12950 12:40:51.297139 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip
12952 12:40:51.302528 No KMS driver or no outputs, pipes: 8, outputs: 0
12953 12:40:51.305903 [1mSubtest pipe-D-query-forked-hang: SKIP (0.000s)[0m
12954 12:40:51.316073 <14>[ 29.480988] [IGT] kms_vblank: executing
12955 12:40:51.322888 IGT-Version: 1.2<14>[ 29.485747] [IGT] kms_vblank: exiting, ret=77
12956 12:40:51.325933 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12957 12:40:51.335970 Opened device: /dev/dri/ca<8>[ 29.497941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy RESULT=skip>
12958 12:40:51.336519 rd0
12959 12:40:51.337174 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy RESULT=skip
12961 12:40:51.339856 No KMS driver or no outputs, pipes: 8, outputs: 0
12962 12:40:51.346090 [1mSubtest pipe-D-query-busy: SKIP (0.000s)[0m
12963 12:40:51.362837 <14>[ 29.527351] [IGT] kms_vblank: executing
12964 12:40:51.369318 IGT-Version: 1.2<14>[ 29.532393] [IGT] kms_vblank: exiting, ret=77
12965 12:40:51.373245 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12966 12:40:51.382861 Opened device: /dev/dri/ca<8>[ 29.544328] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip>
12967 12:40:51.383423 rd0
12968 12:40:51.384066 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip
12970 12:40:51.389871 No KMS driver or no outputs, pipes: 8, outputs: 0
12971 12:40:51.392501 [1mSubtest pipe-D-query-busy-hang: SKIP (0.000s)[0m
12972 12:40:51.409461 <14>[ 29.574482] [IGT] kms_vblank: executing
12973 12:40:51.416727 IGT-Version: 1.2<14>[ 29.579649] [IGT] kms_vblank: exiting, ret=77
12974 12:40:51.419457 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12975 12:40:51.429919 Opened device: /dev/dri/ca<8>[ 29.591086] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip>
12976 12:40:51.430532 rd0
12977 12:40:51.431185 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip
12979 12:40:51.436150 No KMS driver or no outputs, pipes: 8, outputs: 0
12980 12:40:51.440007 [1mSubtest pipe-D-query-forked-busy: SKIP (0.000s)[0m
12981 12:40:51.457891 <14>[ 29.622078] [IGT] kms_vblank: executing
12982 12:40:51.464475 IGT-Version: 1.2<14>[ 29.627377] [IGT] kms_vblank: exiting, ret=77
12983 12:40:51.467425 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12984 12:40:51.477985 Opened device: /dev/dri/ca<8>[ 29.639103] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip>
12985 12:40:51.478598 rd0
12986 12:40:51.479248 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip
12988 12:40:51.484114 No KMS driver or no outputs, pipes: 8, outputs: 0
12989 12:40:51.487618 [1mSubtest pipe-D-query-forked-busy-hang: SKIP (0.000s)[0m
12990 12:40:51.505564 <14>[ 29.669750] [IGT] kms_vblank: executing
12991 12:40:51.511615 IGT-Version: 1.2<14>[ 29.674920] [IGT] kms_vblank: exiting, ret=77
12992 12:40:51.515099 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
12993 12:40:51.524825 Opened device: /dev/dri/ca<8>[ 29.686498] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle RESULT=skip>
12994 12:40:51.525325 rd0
12995 12:40:51.525970 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle RESULT=skip
12997 12:40:51.528304 No KMS driver or no outputs, pipes: 8, outputs: 0
12998 12:40:51.535016 [1mSubtest pipe-D-wait-idle: SKIP (0.000s)[0m
12999 12:40:51.551965 <14>[ 29.716431] [IGT] kms_vblank: executing
13000 12:40:51.559201 IGT-Version: 1.2<14>[ 29.721991] [IGT] kms_vblank: exiting, ret=77
13001 12:40:51.561884 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13002 12:40:51.571989 Opened device: /dev/dri/ca<8>[ 29.733674] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip>
13003 12:40:51.572550 rd0
13004 12:40:51.573189 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip
13006 12:40:51.578366 No KMS driver or no outputs, pipes: 8, outputs: 0
13007 12:40:51.581799 [1mSubtest pipe-D-wait-idle-hang: SKIP (0.000s)[0m
13008 12:40:51.592459 <14>[ 29.757039] [IGT] kms_vblank: executing
13009 12:40:51.598916 IGT-Version: 1.2<14>[ 29.761819] [IGT] kms_vblank: exiting, ret=77
13010 12:40:51.602520 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13011 12:40:51.611832 Opened device: /dev/dri/ca<8>[ 29.773990] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked RESULT=skip>
13012 12:40:51.612385 rd0
13013 12:40:51.613012 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked RESULT=skip
13015 12:40:51.615676 No KMS driver or no outputs, pipes: 8, outputs: 0
13016 12:40:51.621978 [1mSubtest pipe-D-wait-forked: SKIP (0.000s)[0m
13017 12:40:51.632418 <14>[ 29.796914] [IGT] kms_vblank: executing
13018 12:40:51.638705 IGT-Version: 1.2<14>[ 29.801677] [IGT] kms_vblank: exiting, ret=77
13019 12:40:51.642064 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13020 12:40:51.652298 Opened device: /dev/dri/ca<8>[ 29.813917] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip>
13021 12:40:51.652910 rd0
13022 12:40:51.653557 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip
13024 12:40:51.659375 No KMS driver or no outputs, pipes: 8, outputs: 0
13025 12:40:51.662514 [1mSubtest pipe-D-wait-forked-hang: SKIP (0.000s)[0m
13026 12:40:51.679415 <14>[ 29.843928] [IGT] kms_vblank: executing
13027 12:40:51.685951 IGT-Version: 1.2<14>[ 29.849037] [IGT] kms_vblank: exiting, ret=77
13028 12:40:51.688951 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13029 12:40:51.699112 Opened device: /dev/dri/ca<8>[ 29.860889] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy RESULT=skip>
13030 12:40:51.699680 rd0
13031 12:40:51.700325 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy RESULT=skip
13033 12:40:51.702092 No KMS driver or no outputs, pipes: 8, outputs: 0
13034 12:40:51.708731 [1mSubtest pipe-D-wait-busy: SKIP (0.000s)[0m
13035 12:40:51.725986 <14>[ 29.890764] [IGT] kms_vblank: executing
13036 12:40:51.733176 IGT-Version: 1.2<14>[ 29.896009] [IGT] kms_vblank: exiting, ret=77
13037 12:40:51.736320 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13038 12:40:51.745780 Opened device: /dev/dri/ca<8>[ 29.907478] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip>
13039 12:40:51.746328 rd0
13040 12:40:51.747006 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip
13042 12:40:51.752734 No KMS driver or no outputs, pipes: 8, outputs: 0
13043 12:40:51.756191 [1mSubtest pipe-D-wait-busy-hang: SKIP (0.000s)[0m
13044 12:40:51.773691 <14>[ 29.937834] [IGT] kms_vblank: executing
13045 12:40:51.779854 IGT-Version: 1.2<14>[ 29.943051] [IGT] kms_vblank: exiting, ret=77
13046 12:40:51.783538 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13047 12:40:51.793049 Opened device: /dev/dri/ca<8>[ 29.954598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip>
13048 12:40:51.793622 rd0
13049 12:40:51.794264 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip
13051 12:40:51.799492 No KMS driver or no outputs, pipes: 8, outputs: 0
13052 12:40:51.803123 [1mSubtest pipe-D-wait-forked-busy: SKIP (0.000s)[0m
13053 12:40:51.820403 <14>[ 29.985215] [IGT] kms_vblank: executing
13054 12:40:51.826960 IGT-Version: 1.2<14>[ 29.990409] [IGT] kms_vblank: exiting, ret=77
13055 12:40:51.830525 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13056 12:40:51.840272 Opened device: /dev/dri/ca<8>[ 30.001465] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip>
13057 12:40:51.840739 rd0
13058 12:40:51.841370 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip
13060 12:40:51.846865 No KMS driver or no outputs, pipes: 8, outputs: 0
13061 12:40:51.850296 [1mSubtest pipe-D-wait-forked-busy-hang: SKIP (0.000s)[0m
13062 12:40:51.868362 <14>[ 30.032785] [IGT] kms_vblank: executing
13063 12:40:51.874965 IGT-Version: 1.2<14>[ 30.038093] [IGT] kms_vblank: exiting, ret=77
13064 12:40:51.878491 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13065 12:40:51.887583 Opened dev<8>[ 30.048665] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip>
13066 12:40:51.888231 ice: /dev/dri/card0
13067 12:40:51.888923 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip
13069 12:40:51.894566 No KMS driver or no outputs, pipes: 8, outputs: 0
13070 12:40:51.897773 [1mSubtest pipe-D-ts-continuation-idle: SKIP (0.000s)[0m
13071 12:40:51.915050 <14>[ 30.079724] [IGT] kms_vblank: executing
13072 12:40:51.921796 IGT-Version: 1.2<14>[ 30.084935] [IGT] kms_vblank: exiting, ret=77
13073 12:40:51.924923 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13074 12:40:51.935211 Opened device: /dev/dri/ca<8>[ 30.096389] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip>
13075 12:40:51.935906 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip
13077 12:40:51.938106 rd0
13078 12:40:51.941236 No KMS driver or no outputs, pipes: 8, outputs: 0
13079 12:40:51.947904 [1mSubtest pipe-D-ts-continuation-idle-hang: SKIP (0.000s)[0m
13080 12:40:51.962755 <14>[ 30.127784] [IGT] kms_vblank: executing
13081 12:40:51.969567 IGT-Version: 1.2<14>[ 30.132964] [IGT] kms_vblank: exiting, ret=77
13082 12:40:51.973953 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13083 12:40:51.983026 Opened dev<8>[ 30.143890] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip>
13084 12:40:51.983814 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip
13086 12:40:51.985973 ice: /dev/dri/card0
13087 12:40:51.989326 No KMS driver or no outputs, pipes: 8, outputs: 0
13088 12:40:51.996581 [1mSubtest pipe-D-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13089 12:40:52.010435 <14>[ 30.175410] [IGT] kms_vblank: executing
13090 12:40:52.017546 IGT-Version: 1.2<14>[ 30.180639] [IGT] kms_vblank: exiting, ret=77
13091 12:40:52.020576 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13092 12:40:52.024110 Opened device: /dev/dri/card0
13093 12:40:52.034049 No KMS driver or no outputs<8>[ 30.195676] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip>
13094 12:40:52.034946 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip
13096 12:40:52.037131 , pipes: 8, outputs: 0
13097 12:40:52.043570 [1mSubtest pipe-D-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13098 12:40:52.062997 <14>[ 30.227781] [IGT] kms_vblank: executing
13099 12:40:52.069460 IGT-Version: 1.2<14>[ 30.233012] [IGT] kms_vblank: exiting, ret=77
13100 12:40:52.072939 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13101 12:40:52.082920 Opened device: /dev/dri/ca<8>[ 30.244085] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip>
13102 12:40:52.083756 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip
13104 12:40:52.086309 rd0
13105 12:40:52.089417 No KMS driver or no outputs, pipes: 8, outputs: 0
13106 12:40:52.095764 [1mSubtest pipe-D-ts-continuation-suspend: SKIP (0.000s)[0m
13107 12:40:52.111160 <14>[ 30.275757] [IGT] kms_vblank: executing
13108 12:40:52.117949 IGT-Version: 1.2<14>[ 30.280937] [IGT] kms_vblank: exiting, ret=77
13109 12:40:52.121016 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13110 12:40:52.130611 Opened device: /dev/dri/ca<8>[ 30.292036] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip>
13111 12:40:52.131092 rd0
13112 12:40:52.131721 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip
13114 12:40:52.137629 No KMS driver or no outputs, pipes: 8, outputs: 0
13115 12:40:52.140599 [1mSubtest pipe-D-ts-continuation-modeset: SKIP (0.000s)[0m
13116 12:40:52.159381 <14>[ 30.323506] [IGT] kms_vblank: executing
13117 12:40:52.166104 IGT-Version: 1.2<14>[ 30.328641] [IGT] kms_vblank: exiting, ret=77
13118 12:40:52.168368 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13119 12:40:52.178568 Opened device: /dev/dri/ca<8>[ 30.340405] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip>
13120 12:40:52.179386 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip
13122 12:40:52.182177 rd0
13123 12:40:52.185652 No KMS driver or no outputs, pipes: 8, outputs: 0
13124 12:40:52.192266 [1mSubtest pipe-D-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13125 12:40:52.198466 <14>[ 30.362807] [IGT] kms_vblank: executing
13126 12:40:52.201941 IGT-Version: 1.2<14>[ 30.367566] [IGT] kms_vblank: exiting, ret=77
13127 12:40:52.208236 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13128 12:40:52.218009 Opened device: /dev/dri/ca<8>[ 30.380067] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip>
13129 12:40:52.218528 rd0
13130 12:40:52.219184 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip
13132 12:40:52.225187 No KMS driver or no outputs, pipes: 8, outputs: 0
13133 12:40:52.228908 [1mSubtest pipe-D-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13134 12:40:52.246616 <14>[ 30.410983] [IGT] kms_vblank: executing
13135 12:40:52.252678 IGT-Version: 1.2<14>[ 30.416137] [IGT] kms_vblank: exiting, ret=77
13136 12:40:52.256330 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13137 12:40:52.266572 Opened device: /dev/dri/ca<8>[ 30.428233] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip>
13138 12:40:52.267141 rd0
13139 12:40:52.267790 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip
13141 12:40:52.273203 No KMS driver or no outputs, pipes: 8, outputs: 0
13142 12:40:52.276442 [1mSubtest pipe-E-accuracy-idle: SKIP (0.000s)[0m
13143 12:40:52.284528 <14>[ 30.449087] [IGT] kms_vblank: executing
13144 12:40:52.291364 IGT-Version: 1.2<14>[ 30.453868] [IGT] kms_vblank: exiting, ret=77
13145 12:40:52.295049 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13146 12:40:52.304623 Opened device: /dev/dri/ca<8>[ 30.465968] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle RESULT=skip>
13147 12:40:52.305230 rd0
13148 12:40:52.306013 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle RESULT=skip
13150 12:40:52.307493 No KMS driver or no outputs, pipes: 8, outputs: 0
13151 12:40:52.313987 [1mSubtest pipe-E-query-idle: SKIP (0.000s)[0m
13152 12:40:52.331492 <14>[ 30.495509] [IGT] kms_vblank: executing
13153 12:40:52.337498 IGT-Version: 1.2<14>[ 30.500672] [IGT] kms_vblank: exiting, ret=77
13154 12:40:52.340453 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13155 12:40:52.350640 Opened device: /dev/dri/ca<8>[ 30.512431] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip>
13156 12:40:52.351229 rd0
13157 12:40:52.352053 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip
13159 12:40:52.356853 No KMS driver or no outputs, pipes: 8, outputs: 0
13160 12:40:52.360320 [1mSubtest pipe-E-query-idle-hang: SKIP (0.000s)[0m
13161 12:40:52.371005 <14>[ 30.536168] [IGT] kms_vblank: executing
13162 12:40:52.377825 IGT-Version: 1.2<14>[ 30.540904] [IGT] kms_vblank: exiting, ret=77
13163 12:40:52.381012 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13164 12:40:52.391183 Opened device: /dev/dri/ca<8>[ 30.553113] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked RESULT=skip>
13165 12:40:52.391609 rd0
13166 12:40:52.392202 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked RESULT=skip
13168 12:40:52.397379 No KMS driver or no outputs, pipes: 8, outputs: 0
13169 12:40:52.401574 [1mSubtest pipe-E-query-forked: SKIP (0.000s)[0m
13170 12:40:52.409804 <14>[ 30.574954] [IGT] kms_vblank: executing
13171 12:40:52.417263 IGT-Version: 1.2<14>[ 30.579702] [IGT] kms_vblank: exiting, ret=77
13172 12:40:52.420344 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13173 12:40:52.430014 Opened device: /dev/dri/ca<8>[ 30.591995] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip>
13174 12:40:52.430691 rd0
13175 12:40:52.431463 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip
13177 12:40:52.437191 No KMS driver or no outputs, pipes: 8, outputs: 0
13178 12:40:52.439826 [1mSubtest pipe-E-query-forked-hang: SKIP (0.000s)[0m
13179 12:40:52.457678 <14>[ 30.622114] [IGT] kms_vblank: executing
13180 12:40:52.464248 IGT-Version: 1.2<14>[ 30.627308] [IGT] kms_vblank: exiting, ret=77
13181 12:40:52.467876 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13182 12:40:52.477962 Opened device: /dev/dri/ca<8>[ 30.638993] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy RESULT=skip>
13183 12:40:52.478570 rd0
13184 12:40:52.479222 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy RESULT=skip
13186 12:40:52.484109 No KMS driver or no outputs, pipes: 8, outputs: 0
13187 12:40:52.487028 [1mSubtest pipe-E-query-busy: SKIP (0.000s)[0m
13188 12:40:52.504674 <14>[ 30.669049] [IGT] kms_vblank: executing
13189 12:40:52.511075 IGT-Version: 1.2<14>[ 30.674182] [IGT] kms_vblank: exiting, ret=77
13190 12:40:52.514648 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13191 12:40:52.523906 Opened device: /dev/dri/ca<8>[ 30.685209] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip>
13192 12:40:52.524475 rd0
13193 12:40:52.525116 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip
13195 12:40:52.530691 No KMS driver or no outputs, pipes: 8, outputs: 0
13196 12:40:52.534580 [1mSubtest pipe-E-query-busy-hang: SKIP (0.000s)[0m
13197 12:40:52.551486 <14>[ 30.716632] [IGT] kms_vblank: executing
13198 12:40:52.558557 IGT-Version: 1.2<14>[ 30.722209] [IGT] kms_vblank: exiting, ret=77
13199 12:40:52.561753 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13200 12:40:52.571715 Opened device: /dev/dri/ca<8>[ 30.733384] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip>
13201 12:40:52.572282 rd0
13202 12:40:52.572933 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip
13204 12:40:52.578255 No KMS driver or no outputs, pipes: 8, outputs: 0
13205 12:40:52.581558 [1mSubtest pipe-E-query-forked-busy: SKIP (0.000s)[0m
13206 12:40:52.599567 <14>[ 30.764360] [IGT] kms_vblank: executing
13207 12:40:52.605856 IGT-Version: 1.2<14>[ 30.769546] [IGT] kms_vblank: exiting, ret=77
13208 12:40:52.609483 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13209 12:40:52.619167 Opened device: /dev/dri/ca<8>[ 30.780477] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip>
13210 12:40:52.619726 rd0
13211 12:40:52.620368 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip
13213 12:40:52.625622 No KMS driver or no outputs, pipes: 8, outputs: 0
13214 12:40:52.629719 [1mSubtest pipe-E-query-forked-busy-hang: SKIP (0.000s)[0m
13215 12:40:52.646955 <14>[ 30.811834] [IGT] kms_vblank: executing
13216 12:40:52.654309 IGT-Version: 1.2<14>[ 30.816914] [IGT] kms_vblank: exiting, ret=77
13217 12:40:52.656857 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13218 12:40:52.666956 Opened device: /dev/dri/ca<8>[ 30.828007] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle RESULT=skip>
13219 12:40:52.667415 rd0
13220 12:40:52.668044 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle RESULT=skip
13222 12:40:52.670551 No KMS driver or no outputs, pipes: 8, outputs: 0
13223 12:40:52.677066 [1mSubtest pipe-E-wait-idle: SKIP (0.000s)[0m
13224 12:40:52.684704 <14>[ 30.849444] [IGT] kms_vblank: executing
13225 12:40:52.691322 IGT-Version: 1.2<14>[ 30.854159] [IGT] kms_vblank: exiting, ret=77
13226 12:40:52.695021 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13227 12:40:52.704830 Opened device: /dev/dri/ca<8>[ 30.866308] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip>
13228 12:40:52.705425 rd0
13229 12:40:52.706094 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip
13231 12:40:52.710988 No KMS driver or no outputs, pipes: 8, outputs: 0
13232 12:40:52.714455 [1mSubtest pipe-E-wait-idle-hang: SKIP (0.000s)[0m
13233 12:40:52.731427 <14>[ 30.896194] [IGT] kms_vblank: executing
13234 12:40:52.738136 IGT-Version: 1.2<14>[ 30.901471] [IGT] kms_vblank: exiting, ret=77
13235 12:40:52.741336 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13236 12:40:52.751151 Opened dev<8>[ 30.912323] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked RESULT=skip>
13237 12:40:52.751709 ice: /dev/dri/card0
13238 12:40:52.752355 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked RESULT=skip
13240 12:40:52.757733 No KMS driver or no outputs, pipes: 8, outputs: 0
13241 12:40:52.761021 [1mSubtest pipe-E-wait-forked: SKIP (0.000s)[0m
13242 12:40:52.777671 <14>[ 30.942483] [IGT] kms_vblank: executing
13243 12:40:52.784301 IGT-Version: 1.2<14>[ 30.947648] [IGT] kms_vblank: exiting, ret=77
13244 12:40:52.787783 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13245 12:40:52.791438 Opened device: /dev/dri/card0
13246 12:40:52.800931 No KMS driver or no outputs<8>[ 30.962446] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip>
13247 12:40:52.801831 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip
13249 12:40:52.804082 , pipes: 8, outputs: 0
13250 12:40:52.807525 [1mSubtest pipe-E-wait-forked-hang: SKIP (0.000s)[0m
13251 12:40:52.827629 <14>[ 30.992669] [IGT] kms_vblank: executing
13252 12:40:52.834506 IGT-Version: 1.2<14>[ 30.997987] [IGT] kms_vblank: exiting, ret=77
13253 12:40:52.837444 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13254 12:40:52.847935 Opened device: /dev/dri/ca<8>[ 31.009926] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy RESULT=skip>
13255 12:40:52.848536 rd0
13256 12:40:52.849311 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy RESULT=skip
13258 12:40:52.855272 No KMS driver or no outputs, pipes: 8, outputs: 0
13259 12:40:52.857741 [1mSubtest pipe-E-wait-busy: SKIP (0.000s)[0m
13260 12:40:52.874433 <14>[ 31.039610] [IGT] kms_vblank: executing
13261 12:40:52.881624 IGT-Version: 1.2<14>[ 31.044848] [IGT] kms_vblank: exiting, ret=77
13262 12:40:52.884362 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13263 12:40:52.894275 Opened device: /dev/dri/ca<8>[ 31.056293] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip>
13264 12:40:52.894765 rd0
13265 12:40:52.895601 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip
13267 12:40:52.901135 No KMS driver or no outputs, pipes: 8, outputs: 0
13268 12:40:52.904055 [1mSubtest pipe-E-wait-busy-hang: SKIP (0.000s)[0m
13269 12:40:52.921862 <14>[ 31.087276] [IGT] kms_vblank: executing
13270 12:40:52.928662 IGT-Version: 1.2<14>[ 31.092517] [IGT] kms_vblank: exiting, ret=77
13271 12:40:52.932142 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13272 12:40:52.941875 Opened device: /dev/dri/ca<8>[ 31.104252] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip>
13273 12:40:52.942112 rd0
13274 12:40:52.942514 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip
13276 12:40:52.949082 No KMS driver or no outputs, pipes: 8, outputs: 0
13277 12:40:52.951903 [1mSubtest pipe-E-wait-forked-busy: SKIP (0.000s)[0m
13278 12:40:52.960813 <14>[ 31.125943] [IGT] kms_vblank: executing
13279 12:40:52.968430 IGT-Version: 1.2<14>[ 31.130706] [IGT] kms_vblank: exiting, ret=77
13280 12:40:52.970563 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13281 12:40:52.981205 Opened device: /dev/dri/ca<8>[ 31.143221] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip>
13282 12:40:52.981720 rd0
13283 12:40:52.982323 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip
13285 12:40:52.988161 No KMS driver or no outputs, pipes: 8, outputs: 0
13286 12:40:52.990594 [1mSubtest pipe-E-wait-forked-busy-hang: SKIP (0.000s)[0m
13287 12:40:53.008856 <14>[ 31.173525] [IGT] kms_vblank: executing
13288 12:40:53.015302 IGT-Version: 1.2<14>[ 31.178715] [IGT] kms_vblank: exiting, ret=77
13289 12:40:53.018948 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13290 12:40:53.028227 Opened device: /dev/dri/ca<8>[ 31.189628] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip>
13291 12:40:53.028664 rd0
13292 12:40:53.029256 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip
13294 12:40:53.034761 No KMS driver or no outputs, pipes: 8, outputs: 0
13295 12:40:53.038682 [1mSubtest pipe-E-ts-continuation-idle: SKIP (0.000s)[0m
13296 12:40:53.056032 <14>[ 31.220720] [IGT] kms_vblank: executing
13297 12:40:53.062632 IGT-Version: 1.2<14>[ 31.226088] [IGT] kms_vblank: exiting, ret=77
13298 12:40:53.065887 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13299 12:40:53.075948 Opened dev<8>[ 31.236735] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip>
13300 12:40:53.076784 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip
13302 12:40:53.079142 ice: /dev/dri/card0
13303 12:40:53.082597 No KMS driver or no outputs, pipes: 8, outputs: 0
13304 12:40:53.089144 [1mSubtest pipe-E-ts-continuation-idle-hang: SKIP (0.000s)[0m
13305 12:40:53.102982 <14>[ 31.267713] [IGT] kms_vblank: executing
13306 12:40:53.109769 IGT-Version: 1.2<14>[ 31.272906] [IGT] kms_vblank: exiting, ret=77
13307 12:40:53.112666 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13308 12:40:53.122796 Opened device: /dev/dri/ca<8>[ 31.283999] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip>
13309 12:40:53.123536 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip
13311 12:40:53.125761 rd0
13312 12:40:53.129814 No KMS driver or no outputs, pipes: 8, outputs: 0
13313 12:40:53.135948 [1mSubtest pipe-E-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13314 12:40:53.150550 <14>[ 31.315719] [IGT] kms_vblank: executing
13315 12:40:53.157494 IGT-Version: 1.2<14>[ 31.320925] [IGT] kms_vblank: exiting, ret=77
13316 12:40:53.160737 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13317 12:40:53.170793 Opened device: /dev/dri/ca<8>[ 31.332392] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip>
13318 12:40:53.171596 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip
13320 12:40:53.173959 rd0
13321 12:40:53.177711 No KMS driver or no outputs, pipes: 8, outputs: 0
13322 12:40:53.184745 [1mSubtest pipe-E-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13323 12:40:53.198527 <14>[ 31.363794] [IGT] kms_vblank: executing
13324 12:40:53.205537 IGT-Version: 1.2<14>[ 31.368913] [IGT] kms_vblank: exiting, ret=77
13325 12:40:53.209396 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13326 12:40:53.218759 Opened device: /dev/dri/ca<8>[ 31.379924] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip>
13327 12:40:53.219318 rd0
13328 12:40:53.219959 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip
13330 12:40:53.225254 No KMS driver or no outputs, pipes: 8, outputs: 0
13331 12:40:53.228611 [1mSubtest pipe-E-ts-continuation-suspend: SKIP (0.000s)[0m
13332 12:40:53.246664 <14>[ 31.411385] [IGT] kms_vblank: executing
13333 12:40:53.253356 IGT-Version: 1.2<14>[ 31.416520] [IGT] kms_vblank: exiting, ret=77
13334 12:40:53.256133 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13335 12:40:53.266376 Opened device: /dev/dri/ca<8>[ 31.427599] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip>
13336 12:40:53.267254 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip
13338 12:40:53.269736 rd0
13339 12:40:53.272494 No KMS driver or no outputs, pipes: 8, outputs: 0
13340 12:40:53.279495 [1mSubtest pipe-E-ts-continuation-modeset: SKIP (0.000s)[0m
13341 12:40:53.294598 <14>[ 31.459147] [IGT] kms_vblank: executing
13342 12:40:53.301654 IGT-Version: 1.2<14>[ 31.464272] [IGT] kms_vblank: exiting, ret=77
13343 12:40:53.304776 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13344 12:40:53.314226 Opened device: /dev/dri/ca<8>[ 31.476151] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip>
13345 12:40:53.315100 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip
13347 12:40:53.317553 rd0
13348 12:40:53.320855 No KMS driver or no outputs, pipes: 8, outputs: 0
13349 12:40:53.327678 [1mSubtest pipe-E-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13350 12:40:53.342451 <14>[ 31.507359] [IGT] kms_vblank: executing
13351 12:40:53.348958 IGT-Version: 1.2<14>[ 31.512515] [IGT] kms_vblank: exiting, ret=77
13352 12:40:53.352504 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13353 12:40:53.362854 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip
13355 12:40:53.365393 Opened device: /dev/dri/ca<8>[ 31.524201] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip>
13356 12:40:53.365951 rd0
13357 12:40:53.368944 No KMS driver or no outputs, pipes: 8, outputs: 0
13358 12:40:53.375887 [1mSubtest pipe-E-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13359 12:40:53.391118 <14>[ 31.555597] [IGT] kms_vblank: executing
13360 12:40:53.397195 IGT-Version: 1.2<14>[ 31.560695] [IGT] kms_vblank: exiting, ret=77
13361 12:40:53.400774 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13362 12:40:53.410468 Opened device: /dev/dri/ca<8>[ 31.571862] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip>
13363 12:40:53.411098 rd0
13364 12:40:53.411997 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip
13366 12:40:53.416961 No KMS driver or no outputs, pipes: 8, outputs: 0
13367 12:40:53.420633 [1mSubtest pipe-F-accuracy-idle: SKIP (0.000s)[0m
13368 12:40:53.438524 <14>[ 31.603583] [IGT] kms_vblank: executing
13369 12:40:53.445311 IGT-Version: 1.2<14>[ 31.608783] [IGT] kms_vblank: exiting, ret=77
13370 12:40:53.449023 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13371 12:40:53.451546 Opened device: /dev/dri/card0
13372 12:40:53.461951 No KMS driver or no outputs<8>[ 31.623841] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle RESULT=skip>
13373 12:40:53.462631 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle RESULT=skip
13375 12:40:53.464823 , pipes: 8, outputs: 0
13376 12:40:53.468093 [1mSubtest pipe-F-query-idle: SKIP (0.000s)[0m
13377 12:40:53.488951 <14>[ 31.653956] [IGT] kms_vblank: executing
13378 12:40:53.495817 IGT-Version: 1.2<14>[ 31.659060] [IGT] kms_vblank: exiting, ret=77
13379 12:40:53.498885 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13380 12:40:53.502554 Opened device: /dev/dri/card0
13381 12:40:53.512036 No KMS driver or no outputs<8>[ 31.673938] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip>
13382 12:40:53.512849 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip
13384 12:40:53.515535 , pipes: 8, outputs: 0
13385 12:40:53.518999 [1mSubtest pipe-F-query-idle-hang: SKIP (0.000s)[0m
13386 12:40:53.539156 <14>[ 31.704222] [IGT] kms_vblank: executing
13387 12:40:53.546476 IGT-Version: 1.2<14>[ 31.709375] [IGT] kms_vblank: exiting, ret=77
13388 12:40:53.548886 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13389 12:40:53.559202 Opened device: /dev/dri/ca<8>[ 31.720361] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked RESULT=skip>
13390 12:40:53.559755 rd0
13391 12:40:53.560462 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked RESULT=skip
13393 12:40:53.562481 No KMS driver or no outputs, pipes: 8, outputs: 0
13394 12:40:53.569053 [1mSubtest pipe-F-query-forked: SKIP (0.000s)[0m
13395 12:40:53.577938 <14>[ 31.742229] [IGT] kms_vblank: executing
13396 12:40:53.584008 IGT-Version: 1.2<14>[ 31.746998] [IGT] kms_vblank: exiting, ret=77
13397 12:40:53.587330 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13398 12:40:53.590558 Opened device: /dev/dri/card0
13399 12:40:53.600948 No KMS driv<8>[ 31.760305] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip>
13400 12:40:53.601786 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip
13402 12:40:53.604055 er or no outputs, pipes: 8, outputs: 0
13403 12:40:53.607214 [1mSubtest pipe-F-query-forked-hang: SKIP (0.000s)[0m
13404 12:40:53.626547 <14>[ 31.791007] [IGT] kms_vblank: executing
13405 12:40:53.632950 IGT-Version: 1.2<14>[ 31.796237] [IGT] kms_vblank: exiting, ret=77
13406 12:40:53.636190 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13407 12:40:53.646514 Opened device: /dev/dri/ca<8>[ 31.808139] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy RESULT=skip>
13408 12:40:53.647072 rd0
13409 12:40:53.647710 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy RESULT=skip
13411 12:40:53.649285 No KMS driver or no outputs, pipes: 8, outputs: 0
13412 12:40:53.656094 [1mSubtest pipe-F-query-busy: SKIP (0.000s)[0m
13413 12:40:53.672988 <14>[ 31.837992] [IGT] kms_vblank: executing
13414 12:40:53.679785 IGT-Version: 1.2<14>[ 31.843420] [IGT] kms_vblank: exiting, ret=77
13415 12:40:53.683024 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13416 12:40:53.693282 Opened device: /dev/dri/ca<8>[ 31.855115] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip>
13417 12:40:53.693841 rd0
13418 12:40:53.694510 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip
13420 12:40:53.700094 No KMS driver or no outputs, pipes: 8, outputs: 0
13421 12:40:53.702759 [1mSubtest pipe-F-query-busy-hang: SKIP (0.000s)[0m
13422 12:40:53.720720 <14>[ 31.885508] [IGT] kms_vblank: executing
13423 12:40:53.727664 IGT-Version: 1.2<14>[ 31.890994] [IGT] kms_vblank: exiting, ret=77
13424 12:40:53.730383 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13425 12:40:53.740428 Opened device: /dev/dri/ca<8>[ 31.902964] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip>
13426 12:40:53.740984 rd0
13427 12:40:53.741617 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip
13429 12:40:53.747149 No KMS driver or no outputs, pipes: 8, outputs: 0
13430 12:40:53.750178 [1mSubtest pipe-F-query-forked-busy: SKIP (0.000s)[0m
13431 12:40:53.768607 <14>[ 31.933267] [IGT] kms_vblank: executing
13432 12:40:53.775087 IGT-Version: 1.2<14>[ 31.938443] [IGT] kms_vblank: exiting, ret=77
13433 12:40:53.778328 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13434 12:40:53.788199 Opened device: /dev/dri/ca<8>[ 31.949458] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip>
13435 12:40:53.788755 rd0
13436 12:40:53.789398 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip
13438 12:40:53.794956 No KMS driver or no outputs, pipes: 8, outputs: 0
13439 12:40:53.797889 [1mSubtest pipe-F-query-forked-busy-hang: SKIP (0.000s)[0m
13440 12:40:53.808102 <14>[ 31.972463] [IGT] kms_vblank: executing
13441 12:40:53.814121 IGT-Version: 1.2<14>[ 31.977260] [IGT] kms_vblank: exiting, ret=77
13442 12:40:53.817263 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13443 12:40:53.827324 Opened device: /dev/dri/ca<8>[ 31.989461] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle RESULT=skip>
13444 12:40:53.827741 rd0
13445 12:40:53.828328 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle RESULT=skip
13447 12:40:53.830530 No KMS driver or no outputs, pipes: 8, outputs: 0
13448 12:40:53.836859 [1mSubtest pipe-F-wait-idle: SKIP (0.000s)[0m
13449 12:40:53.846710 <14>[ 32.011989] [IGT] kms_vblank: executing
13450 12:40:53.853818 IGT-Version: 1.2<14>[ 32.016797] [IGT] kms_vblank: exiting, ret=77
13451 12:40:53.856491 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13452 12:40:53.866914 Opened device: /dev/dri/ca<8>[ 32.029309] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip>
13453 12:40:53.867332 rd0
13454 12:40:53.867912 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip
13456 12:40:53.873074 No KMS driver or no outputs, pipes: 8, outputs: 0
13457 12:40:53.876792 [1mSubtest pipe-F-wait-idle-hang: SKIP (0.000s)[0m
13458 12:40:53.893763 <14>[ 32.059005] [IGT] kms_vblank: executing
13459 12:40:53.900146 IGT-Version: 1.2<14>[ 32.064131] [IGT] kms_vblank: exiting, ret=77
13460 12:40:53.904042 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13461 12:40:53.907181 Opened device: /dev/dri/card0
13462 12:40:53.910104 No KMS driver or no outputs, pipes: 8, outputs: 0
13463 12:40:53.920692 [1mSubtest pipe-F-wait-<8>[ 32.082150] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked RESULT=skip>
13464 12:40:53.921468 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked RESULT=skip
13466 12:40:53.923756 forked: SKIP (0.000s)[0m
13467 12:40:53.939082 <14>[ 32.104401] [IGT] kms_vblank: executing
13468 12:40:53.945823 IGT-Version: 1.2<14>[ 32.109156] [IGT] kms_vblank: exiting, ret=77
13469 12:40:53.949412 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13470 12:40:53.959170 Opened device: /dev/dri/ca<8>[ 32.120564] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip>
13471 12:40:53.959599 rd0
13472 12:40:53.960190 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip
13474 12:40:53.966167 No KMS driver or no outputs, pipes: 8, outputs: 0
13475 12:40:53.969567 [1mSubtest pipe-F-wait-forked-hang: SKIP (0.000s)[0m
13476 12:40:53.976837 <14>[ 32.142239] [IGT] kms_vblank: executing
13477 12:40:53.984373 IGT-Version: 1.2<14>[ 32.146977] [IGT] kms_vblank: exiting, ret=77
13478 12:40:53.987119 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13479 12:40:53.994333 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy RESULT=skip
13481 12:40:53.997810 Opened dev<8>[ 32.157446] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy RESULT=skip>
13482 12:40:53.998353 ice: /dev/dri/card0
13483 12:40:54.000778 No KMS driver or no outputs, pipes: 8, outputs: 0
13484 12:40:54.006818 [1mSubtest pipe-F-wait-busy: SKIP (0.000s)[0m
13485 12:40:54.023118 <14>[ 32.188330] [IGT] kms_vblank: executing
13486 12:40:54.029755 IGT-Version: 1.2<14>[ 32.193618] [IGT] kms_vblank: exiting, ret=77
13487 12:40:54.033291 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13488 12:40:54.036625 Opened device: /dev/dri/card0
13489 12:40:54.043402 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip
13491 12:40:54.046667 No KMS driv<8>[ 32.205773] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip>
13492 12:40:54.050008 er or no outputs, pipes: 8, outputs: 0
13493 12:40:54.053359 [1mSubtest pipe-F-wait-busy-hang: SKIP (0.000s)[0m
13494 12:40:54.065496 <14>[ 32.230059] [IGT] kms_vblank: executing
13495 12:40:54.071834 IGT-Version: 1.2<14>[ 32.234891] [IGT] kms_vblank: exiting, ret=77
13496 12:40:54.074894 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13497 12:40:54.085177 Opened device: /dev/dri/ca<8>[ 32.246173] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip>
13498 12:40:54.085746 rd0
13499 12:40:54.086387 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip
13501 12:40:54.091890 No KMS driver or no outputs, pipes: 8, outputs: 0
13502 12:40:54.095486 [1mSubtest pipe-F-wait-forked-busy: SKIP (0.000s)[0m
13503 12:40:54.105200 <14>[ 32.269889] [IGT] kms_vblank: executing
13504 12:40:54.112215 IGT-Version: 1.2<14>[ 32.274746] [IGT] kms_vblank: exiting, ret=77
13505 12:40:54.114688 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13506 12:40:54.124509 Opened device: /dev/dri/ca<8>[ 32.286064] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip>
13507 12:40:54.125063 rd0
13508 12:40:54.125703 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip
13510 12:40:54.131166 No KMS driver or no outputs, pipes: 8, outputs: 0
13511 12:40:54.134665 [1mSubtest pipe-F-wait-forked-busy-hang: SKIP (0.000s)[0m
13512 12:40:54.152429 <14>[ 32.317148] [IGT] kms_vblank: executing
13513 12:40:54.158689 IGT-Version: 1.2<14>[ 32.322300] [IGT] kms_vblank: exiting, ret=77
13514 12:40:54.162554 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13515 12:40:54.172280 Opened device: /dev/dri/ca<8>[ 32.334022] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip>
13516 12:40:54.172849 rd0
13517 12:40:54.173488 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip
13519 12:40:54.178797 No KMS driver or no outputs, pipes: 8, outputs: 0
13520 12:40:54.182376 [1mSubtest pipe-F-ts-continuation-idle: SKIP (0.000s)[0m
13521 12:40:54.193972 <14>[ 32.358842] [IGT] kms_vblank: executing
13522 12:40:54.200432 IGT-Version: 1.2<14>[ 32.363605] [IGT] kms_vblank: exiting, ret=77
13523 12:40:54.204446 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13524 12:40:54.213562 Opened device: /dev/dri/ca<8>[ 32.375396] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip>
13525 12:40:54.213981 rd0
13526 12:40:54.214569 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip
13528 12:40:54.220318 No KMS driver or no outputs, pipes: 8, outputs: 0
13529 12:40:54.227059 [1mSubtest pipe-F-ts-continuation-idle-hang: SKIP (0.000s)[0m
13530 12:40:54.235236 <14>[ 32.400195] [IGT] kms_vblank: executing
13531 12:40:54.241970 IGT-Version: 1.2<14>[ 32.404927] [IGT] kms_vblank: exiting, ret=77
13532 12:40:54.244932 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13533 12:40:54.254881 Opened device: /dev/dri/ca<8>[ 32.416169] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip>
13534 12:40:54.255447 rd0
13535 12:40:54.256086 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip
13537 12:40:54.261920 No KMS driver or no outputs, pipes: 8, outputs: 0
13538 12:40:54.265325 [1mSubtest pipe-F-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13539 12:40:54.273707 <14>[ 32.438302] [IGT] kms_vblank: executing
13540 12:40:54.280214 IGT-Version: 1.2<14>[ 32.443067] [IGT] kms_vblank: exiting, ret=77
13541 12:40:54.283521 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13542 12:40:54.293139 Opened device: /dev/dri/ca<8>[ 32.455075] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip>
13543 12:40:54.294012 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip
13545 12:40:54.296378 rd0
13546 12:40:54.299643 No KMS driver or no outputs, pipes: 8, outputs: 0
13547 12:40:54.306811 [1mSubtest pipe-F-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13548 12:40:54.321805 <14>[ 32.486761] [IGT] kms_vblank: executing
13549 12:40:54.328041 IGT-Version: 1.2<14>[ 32.491885] [IGT] kms_vblank: exiting, ret=77
13550 12:40:54.331412 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13551 12:40:54.341430 Opened device: /dev/dri/ca<8>[ 32.503361] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip>
13552 12:40:54.342010 rd0
13553 12:40:54.342656 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip
13555 12:40:54.348318 No KMS driver or no outputs, pipes: 8, outputs: 0
13556 12:40:54.351365 [1mSubtest pipe-F-ts-continuation-suspend: SKIP (0.000s)[0m
13557 12:40:54.363082 <14>[ 32.527120] [IGT] kms_vblank: executing
13558 12:40:54.368616 IGT-Version: 1.2<14>[ 32.531894] [IGT] kms_vblank: exiting, ret=77
13559 12:40:54.372008 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13560 12:40:54.382066 Opened device: /dev/dri/ca<8>[ 32.544144] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip>
13561 12:40:54.382679 rd0
13562 12:40:54.383331 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip
13564 12:40:54.389057 No KMS driver or no outputs, pipes: 8, outputs: 0
13565 12:40:54.391936 [1mSubtest pipe-F-ts-continuation-modeset: SKIP (0.000s)[0m
13566 12:40:54.400309 <14>[ 32.564857] [IGT] kms_vblank: executing
13567 12:40:54.406225 IGT-Version: 1.2<14>[ 32.569752] [IGT] kms_vblank: exiting, ret=77
13568 12:40:54.409947 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13569 12:40:54.413290 Opened device: /dev/dri/card0
13570 12:40:54.422806 No KMS driv<8>[ 32.582625] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip>
13571 12:40:54.423685 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip
13573 12:40:54.426188 er or no outputs, pipes: 8, outputs: 0
13574 12:40:54.432508 [1mSubtest pipe-F-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13575 12:40:54.449103 <14>[ 32.614425] [IGT] kms_vblank: executing
13576 12:40:54.456566 IGT-Version: 1.2<14>[ 32.619535] [IGT] kms_vblank: exiting, ret=77
13577 12:40:54.459982 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13578 12:40:54.469328 Opened device: /dev/dri/ca<8>[ 32.631630] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip>
13579 12:40:54.470192 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip
13581 12:40:54.472857 rd0
13582 12:40:54.475880 No KMS driver or no outputs, pipes: 8, outputs: 0
13583 12:40:54.482750 [1mSubtest pipe-F-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13584 12:40:54.497308 <14>[ 32.662654] [IGT] kms_vblank: executing
13585 12:40:54.503674 IGT-Version: 1.2<14>[ 32.667880] [IGT] kms_vblank: exiting, ret=77
13586 12:40:54.507405 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13587 12:40:54.517136 Opened device: /dev/dri/ca<8>[ 32.679932] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip>
13588 12:40:54.517725 rd0
13589 12:40:54.518331 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip
13591 12:40:54.524512 No KMS driver or no outputs, pipes: 8, outputs: 0
13592 12:40:54.527339 [1mSubtest pipe-G-accuracy-idle: SKIP (0.000s)[0m
13593 12:40:54.544417 <14>[ 32.709809] [IGT] kms_vblank: executing
13594 12:40:54.551097 IGT-Version: 1.2<14>[ 32.714971] [IGT] kms_vblank: exiting, ret=77
13595 12:40:54.555438 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13596 12:40:54.564956 Opened device: /dev/dri/ca<8>[ 32.726842] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle RESULT=skip>
13597 12:40:54.565528 rd0
13598 12:40:54.566198 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle RESULT=skip
13600 12:40:54.571569 No KMS driver or no outputs, pipes: 8, outputs: 0
13601 12:40:54.574287 [1mSubtest pipe-G-query-idle: SKIP (0.000s)[0m
13602 12:40:54.583340 <14>[ 32.748291] [IGT] kms_vblank: executing
13603 12:40:54.589786 IGT-Version: 1.2<14>[ 32.753073] [IGT] kms_vblank: exiting, ret=77
13604 12:40:54.593314 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13605 12:40:54.596359 Opened device: /dev/dri/card0
13606 12:40:54.603321 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip
13608 12:40:54.606263 No KMS driv<8>[ 32.766381] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip>
13609 12:40:54.609722 er or no outputs, pipes: 8, outputs: 0
13610 12:40:54.613184 [1mSubtest pipe-G-query-idle-hang: SKIP (0.000s)[0m
13611 12:40:54.621823 <14>[ 32.786672] [IGT] kms_vblank: executing
13612 12:40:54.627869 IGT-Version: 1.2<14>[ 32.791426] [IGT] kms_vblank: exiting, ret=77
13613 12:40:54.631514 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13614 12:40:54.641853 Opened device: /dev/dri/ca<8>[ 32.803731] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked RESULT=skip>
13615 12:40:54.642472 rd0
13616 12:40:54.643130 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked RESULT=skip
13618 12:40:54.644949 No KMS driver or no outputs, pipes: 8, outputs: 0
13619 12:40:54.651579 [1mSubtest pipe-G-query-forked: SKIP (0.000s)[0m
13620 12:40:54.658856 <14>[ 32.824196] [IGT] kms_vblank: executing
13621 12:40:54.665968 IGT-Version: 1.2<14>[ 32.828949] [IGT] kms_vblank: exiting, ret=77
13622 12:40:54.668983 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13623 12:40:54.672592 Opened device: /dev/dri/card0
13624 12:40:54.679461 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip
13626 12:40:54.682264 No KMS driv<8>[ 32.842359] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip>
13627 12:40:54.686252 er or no outputs, pipes: 8, outputs: 0
13628 12:40:54.689352 [1mSubtest pipe-G-query-forked-hang: SKIP (0.000s)[0m
13629 12:40:54.698561 <14>[ 32.862965] [IGT] kms_vblank: executing
13630 12:40:54.704448 IGT-Version: 1.2<14>[ 32.867836] [IGT] kms_vblank: exiting, ret=77
13631 12:40:54.707457 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13632 12:40:54.718363 Opened device: /dev/dri/ca<8>[ 32.880221] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy RESULT=skip>
13633 12:40:54.718994 rd0
13634 12:40:54.719646 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy RESULT=skip
13636 12:40:54.720992 No KMS driver or no outputs, pipes: 8, outputs: 0
13637 12:40:54.727996 [1mSubtest pipe-G-query-busy: SKIP (0.000s)[0m
13638 12:40:54.735753 <14>[ 32.900850] [IGT] kms_vblank: executing
13639 12:40:54.742502 IGT-Version: 1.2<14>[ 32.905684] [IGT] kms_vblank: exiting, ret=77
13640 12:40:54.745928 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13641 12:40:54.755887 Opened device: /dev/dri/ca<8>[ 32.917656] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip>
13642 12:40:54.756509 rd0
13643 12:40:54.757165 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip
13645 12:40:54.762555 No KMS driver or no outputs, pipes: 8, outputs: 0
13646 12:40:54.766256 [1mSubtest pipe-G-query-busy-hang: SKIP (0.000s)[0m
13647 12:40:54.775800 <14>[ 32.941089] [IGT] kms_vblank: executing
13648 12:40:54.783080 IGT-Version: 1.2<14>[ 32.945846] [IGT] kms_vblank: exiting, ret=77
13649 12:40:54.786004 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13650 12:40:54.795998 Opened device: /dev/dri/ca<8>[ 32.958208] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip>
13651 12:40:54.796564 rd0
13652 12:40:54.797205 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip
13654 12:40:54.803378 No KMS driver or no outputs, pipes: 8, outputs: 0
13655 12:40:54.806077 [1mSubtest pipe-G-query-forked-busy: SKIP (0.000s)[0m
13656 12:40:54.823339 <14>[ 32.988300] [IGT] kms_vblank: executing
13657 12:40:54.829353 IGT-Version: 1.2<14>[ 32.993610] [IGT] kms_vblank: exiting, ret=77
13658 12:40:54.833012 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13659 12:40:54.836378 Opened device: /dev/dri/card0
13660 12:40:54.846669 No KMS driver or no outputs<8>[ 33.008202] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip>
13661 12:40:54.847514 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip
13663 12:40:54.849712 , pipes: 8, outputs: 0
13664 12:40:54.853090 [1mSubtest pipe-G-query-forked-busy-hang: SKIP (0.000s)[0m
13665 12:40:54.874641 <14>[ 33.040064] [IGT] kms_vblank: executing
13666 12:40:54.881387 IGT-Version: 1.2<14>[ 33.045198] [IGT] kms_vblank: exiting, ret=77
13667 12:40:54.885451 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13668 12:40:54.888068 Opened device: /dev/dri/card0
13669 12:40:54.898370 No KMS driver or no outputs<8>[ 33.059489] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle RESULT=skip>
13670 12:40:54.898860 , pipes: 8, outputs: 0
13671 12:40:54.899570 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle RESULT=skip
13673 12:40:54.904685 [1mSubtest pipe-G-wait-idle: SKIP (0.000s)[0m
13674 12:40:54.925283 <14>[ 33.090785] [IGT] kms_vblank: executing
13675 12:40:54.932434 IGT-Version: 1.2<14>[ 33.095973] [IGT] kms_vblank: exiting, ret=77
13676 12:40:54.935099 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13677 12:40:54.938328 Opened device: /dev/dri/card0
13678 12:40:54.948669 No KMS driver or no outputs<8>[ 33.111066] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip>
13679 12:40:54.949378 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip
13681 12:40:54.951693 , pipes: 8, outputs: 0
13682 12:40:54.954908 [1mSubtest pipe-G-wait-idle-hang: SKIP (0.000s)[0m
13683 12:40:54.976595 <14>[ 33.141476] [IGT] kms_vblank: executing
13684 12:40:54.983356 IGT-Version: 1.2<14>[ 33.146580] [IGT] kms_vblank: exiting, ret=77
13685 12:40:54.986955 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13686 12:40:54.990128 Opened device: /dev/dri/card0
13687 12:40:54.999397 No KMS driver or no outputs<8>[ 33.161459] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked RESULT=skip>
13688 12:40:54.999976 , pipes: 8, outputs: 0
13689 12:40:55.000749 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked RESULT=skip
13691 12:40:55.006027 [1mSubtest pipe-G-wait-forked: SKIP (0.000s)[0m
13692 12:40:55.025976 <14>[ 33.191417] [IGT] kms_vblank: executing
13693 12:40:55.032683 IGT-Version: 1.2<14>[ 33.196579] [IGT] kms_vblank: exiting, ret=77
13694 12:40:55.036190 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13695 12:40:55.045908 Opened device: /dev/dri/ca<8>[ 33.207610] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip>
13696 12:40:55.046393 rd0
13697 12:40:55.047190 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip
13699 12:40:55.052471 No KMS driver or no outputs, pipes: 8, outputs: 0
13700 12:40:55.055927 [1mSubtest pipe-G-wait-forked-hang: SKIP (0.000s)[0m
13701 12:40:55.073700 <14>[ 33.238935] [IGT] kms_vblank: executing
13702 12:40:55.080317 IGT-Version: 1.2<14>[ 33.244038] [IGT] kms_vblank: exiting, ret=77
13703 12:40:55.083477 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13704 12:40:55.093887 Opened device: /dev/dri/ca<8>[ 33.255484] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy RESULT=skip>
13705 12:40:55.094502 rd0
13706 12:40:55.095288 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy RESULT=skip
13708 12:40:55.097126 No KMS driver or no outputs, pipes: 8, outputs: 0
13709 12:40:55.103955 [1mSubtest pipe-G-wait-busy: SKIP (0.000s)[0m
13710 12:40:55.120422 <14>[ 33.285620] [IGT] kms_vblank: executing
13711 12:40:55.126981 IGT-Version: 1.2<14>[ 33.291046] [IGT] kms_vblank: exiting, ret=77
13712 12:40:55.130429 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13713 12:40:55.140713 Opened device: /dev/dri/ca<8>[ 33.302950] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip>
13714 12:40:55.141183 rd0
13715 12:40:55.141817 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip
13717 12:40:55.148049 No KMS driver or no outputs, pipes: 8, outputs: 0
13718 12:40:55.150163 [1mSubtest pipe-G-wait-busy-hang: SKIP (0.000s)[0m
13719 12:40:55.158852 <14>[ 33.324215] [IGT] kms_vblank: executing
13720 12:40:55.165903 IGT-Version: 1.2<14>[ 33.328947] [IGT] kms_vblank: exiting, ret=77
13721 12:40:55.169214 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13722 12:40:55.178969 Opened device: /dev/dri/ca<8>[ 33.341402] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip>
13723 12:40:55.179535 rd0
13724 12:40:55.180180 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip
13726 12:40:55.185865 No KMS driver or no outputs, pipes: 8, outputs: 0
13727 12:40:55.188693 [1mSubtest pipe-G-wait-forked-busy: SKIP (0.000s)[0m
13728 12:40:55.205792 <14>[ 33.371055] [IGT] kms_vblank: executing
13729 12:40:55.212574 IGT-Version: 1.2<14>[ 33.376232] [IGT] kms_vblank: exiting, ret=77
13730 12:40:55.215869 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13731 12:40:55.219502 Opened device: /dev/dri/card0
13732 12:40:55.229064 No KMS driver or no outputs<8>[ 33.390768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip>
13733 12:40:55.229892 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip
13735 12:40:55.232715 , pipes: 8, outputs: 0
13736 12:40:55.236256 [1mSubtest pipe-G-wait-forked-busy-hang: SKIP (0.000s)[0m
13737 12:40:55.258006 <14>[ 33.422991] [IGT] kms_vblank: executing
13738 12:40:55.264870 IGT-Version: 1.2<14>[ 33.428083] [IGT] kms_vblank: exiting, ret=77
13739 12:40:55.267638 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13740 12:40:55.271291 Opened device: /dev/dri/card0
13741 12:40:55.281289 No KMS driver or no outputs<8>[ 33.443137] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip>
13742 12:40:55.282131 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip
13744 12:40:55.284479 , pipes: 8, outputs: 0
13745 12:40:55.287664 [1mSubtest pipe-G-ts-continuation-idle: SKIP (0.000s)[0m
13746 12:40:55.309086 <14>[ 33.474072] [IGT] kms_vblank: executing
13747 12:40:55.315533 IGT-Version: 1.2<14>[ 33.479248] [IGT] kms_vblank: exiting, ret=77
13748 12:40:55.318667 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13749 12:40:55.322363 Opened device: /dev/dri/card0
13750 12:40:55.331920 No KMS driv<8>[ 33.492087] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip>
13751 12:40:55.332658 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip
13753 12:40:55.335413 er or no outputs, pipes: 8, outputs: 0
13754 12:40:55.342120 [1mSubtest pipe-G-ts-continuation-idle-hang: SKIP (0.000s)[0m
13755 12:40:55.358332 <14>[ 33.523725] [IGT] kms_vblank: executing
13756 12:40:55.365202 IGT-Version: 1.2<14>[ 33.528842] [IGT] kms_vblank: exiting, ret=77
13757 12:40:55.368923 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13758 12:40:55.371774 Opened device: /dev/dri/card0
13759 12:40:55.382115 No KMS driver or no outputs<8>[ 33.543795] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip>
13760 12:40:55.383026 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip
13762 12:40:55.385439 , pipes: 8, outputs: 0
13763 12:40:55.391340 [1mSubtest pipe-G-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13764 12:40:55.410760 <14>[ 33.575631] [IGT] kms_vblank: executing
13765 12:40:55.416897 IGT-Version: 1.2<14>[ 33.580798] [IGT] kms_vblank: exiting, ret=77
13766 12:40:55.420361 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13767 12:40:55.431033 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip
13769 12:40:55.433754 Opened device: /dev/dri/ca<8>[ 33.592531] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip>
13770 12:40:55.434222 rd0
13771 12:40:55.437094 No KMS driver or no outputs, pipes: 8, outputs: 0
13772 12:40:55.443366 [1mSubtest pipe-G-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13773 12:40:55.450623 <14>[ 33.614802] [IGT] kms_vblank: executing
13774 12:40:55.456774 IGT-Version: 1.2<14>[ 33.619622] [IGT] kms_vblank: exiting, ret=77
13775 12:40:55.460065 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13776 12:40:55.470162 Opened device: /dev/dri/ca<8>[ 33.631687] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip>
13777 12:40:55.470790 rd0
13778 12:40:55.471563 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip
13780 12:40:55.476839 No KMS driver or no outputs, pipes: 8, outputs: 0
13781 12:40:55.480180 [1mSubtest pipe-G-ts-continuation-suspend: SKIP (0.000s)[0m
13782 12:40:55.497543 <14>[ 33.662583] [IGT] kms_vblank: executing
13783 12:40:55.504061 IGT-Version: 1.2<14>[ 33.667775] [IGT] kms_vblank: exiting, ret=77
13784 12:40:55.507286 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13785 12:40:55.517402 Opened device: /dev/dri/ca<8>[ 33.679435] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip>
13786 12:40:55.517966 rd0
13787 12:40:55.518841 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip
13789 12:40:55.524434 No KMS driver or no outputs, pipes: 8, outputs: 0
13790 12:40:55.527642 [1mSubtest pipe-G-ts-continuation-modeset: SKIP (0.000s)[0m
13791 12:40:55.545160 <14>[ 33.710612] [IGT] kms_vblank: executing
13792 12:40:55.552065 IGT-Version: 1.2<14>[ 33.715827] [IGT] kms_vblank: exiting, ret=77
13793 12:40:55.555774 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13794 12:40:55.565367 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip
13796 12:40:55.568725 Opened device: /dev/dri/ca<8>[ 33.727820] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip>
13797 12:40:55.569386 rd0
13798 12:40:55.571516 No KMS driver or no outputs, pipes: 8, outputs: 0
13799 12:40:55.578288 [1mSubtest pipe-G-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13800 12:40:55.593633 <14>[ 33.758865] [IGT] kms_vblank: executing
13801 12:40:55.600111 IGT-Version: 1.2<14>[ 33.764035] [IGT] kms_vblank: exiting, ret=77
13802 12:40:55.603662 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13803 12:40:55.613849 Opened device: /dev/dri/ca<8>[ 33.775795] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip>
13804 12:40:55.614637 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip
13806 12:40:55.616884 rd0
13807 12:40:55.620372 No KMS driver or no outputs, pipes: 8, outputs: 0
13808 12:40:55.626543 [1mSubtest pipe-G-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13809 12:40:55.642131 <14>[ 33.807170] [IGT] kms_vblank: executing
13810 12:40:55.648895 IGT-Version: 1.2<14>[ 33.812659] [IGT] kms_vblank: exiting, ret=77
13811 12:40:55.652520 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13812 12:40:55.661993 Opened device: /dev/dri/ca<8>[ 33.823778] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip>
13813 12:40:55.662525 rd0
13814 12:40:55.663285 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip
13816 12:40:55.668140 No KMS driver or no outputs, pipes: 8, outputs: 0
13817 12:40:55.671771 [1mSubtest pipe-H-accuracy-idle: SKIP (0.000s)[0m
13818 12:40:55.689299 <14>[ 33.854432] [IGT] kms_vblank: executing
13819 12:40:55.696100 IGT-Version: 1.2<14>[ 33.859533] [IGT] kms_vblank: exiting, ret=77
13820 12:40:55.699206 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13821 12:40:55.709051 Opened device: /dev/dri/ca<8>[ 33.870711] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle RESULT=skip>
13822 12:40:55.709616 rd0
13823 12:40:55.710263 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle RESULT=skip
13825 12:40:55.712246 No KMS driver or no outputs, pipes: 8, outputs: 0
13826 12:40:55.718867 [1mSubtest pipe-H-query-idle: SKIP (0.000s)[0m
13827 12:40:55.727173 <14>[ 33.891881] [IGT] kms_vblank: executing
13828 12:40:55.733230 IGT-Version: 1.2<14>[ 33.896615] [IGT] kms_vblank: exiting, ret=77
13829 12:40:55.737255 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13830 12:40:55.747214 Opened device: /dev/dri/ca<8>[ 33.908705] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip>
13831 12:40:55.747791 rd0
13832 12:40:55.748437 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip
13834 12:40:55.753009 No KMS driver or no outputs, pipes: 8, outputs: 0
13835 12:40:55.756617 [1mSubtest pipe-H-query-idle-hang: SKIP (0.000s)[0m
13836 12:40:55.773579 <14>[ 33.938746] [IGT] kms_vblank: executing
13837 12:40:55.780474 IGT-Version: 1.2<14>[ 33.943869] [IGT] kms_vblank: exiting, ret=77
13838 12:40:55.784340 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13839 12:40:55.793440 Opened device: /dev/dri/ca<8>[ 33.955797] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked RESULT=skip>
13840 12:40:55.793999 rd0
13841 12:40:55.794640 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked RESULT=skip
13843 12:40:55.800268 No KMS driver or no outputs, pipes: 8, outputs: 0
13844 12:40:55.803206 [1mSubtest pipe-H-query-forked: SKIP (0.000s)[0m
13845 12:40:55.820249 <14>[ 33.985774] [IGT] kms_vblank: executing
13846 12:40:55.827333 IGT-Version: 1.2<14>[ 33.990901] [IGT] kms_vblank: exiting, ret=77
13847 12:40:55.830364 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13848 12:40:55.840603 Opened device: /dev/dri/ca<8>[ 34.002218] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip>
13849 12:40:55.841151 rd0
13850 12:40:55.841785 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip
13852 12:40:55.847093 No KMS driver or no outputs, pipes: 8, outputs: 0
13853 12:40:55.850045 [1mSubtest pipe-H-query-forked-hang: SKIP (0.000s)[0m
13854 12:40:55.867403 <14>[ 34.032915] [IGT] kms_vblank: executing
13855 12:40:55.874058 IGT-Version: 1.2<14>[ 34.038162] [IGT] kms_vblank: exiting, ret=77
13856 12:40:55.877765 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13857 12:40:55.887820 Opened device: /dev/dri/ca<8>[ 34.050020] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy RESULT=skip>
13858 12:40:55.888436 rd0
13859 12:40:55.889264 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy RESULT=skip
13861 12:40:55.890999 No KMS driver or no outputs, pipes: 8, outputs: 0
13862 12:40:55.897223 [1mSubtest pipe-H-query-busy: SKIP (0.000s)[0m
13863 12:40:55.914495 <14>[ 34.079657] [IGT] kms_vblank: executing
13864 12:40:55.920961 IGT-Version: 1.2<14>[ 34.084818] [IGT] kms_vblank: exiting, ret=77
13865 12:40:55.924274 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13866 12:40:55.934683 Opened device: /dev/dri/ca<8>[ 34.095869] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip>
13867 12:40:55.935100 rd0
13868 12:40:55.935685 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip
13870 12:40:55.940748 No KMS driver or no outputs, pipes: 8, outputs: 0
13871 12:40:55.944103 [1mSubtest pipe-H-query-busy-hang: SKIP (0.000s)[0m
13872 12:40:55.962066 <14>[ 34.127087] [IGT] kms_vblank: executing
13873 12:40:55.968912 IGT-Version: 1.2<14>[ 34.132172] [IGT] kms_vblank: exiting, ret=77
13874 12:40:55.972375 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13875 12:40:55.974877 Opened device: /dev/dri/card0
13876 12:40:55.985333 No KMS driver or no outputs<8>[ 34.146628] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip>
13877 12:40:55.986168 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip
13879 12:40:55.988708 , pipes: 8, outputs: 0
13880 12:40:55.991986 [1mSubtest pipe-H-query-forked-busy: SKIP (0.000s)[0m
13881 12:40:56.012936 <14>[ 34.177777] [IGT] kms_vblank: executing
13882 12:40:56.018989 IGT-Version: 1.2<14>[ 34.182900] [IGT] kms_vblank: exiting, ret=77
13883 12:40:56.022569 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13884 12:40:56.025769 Opened device: /dev/dri/card0
13885 12:40:56.036125 No KMS driver or no outputs<8>[ 34.197720] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip>
13886 12:40:56.036862 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip
13888 12:40:56.039233 , pipes: 8, outputs: 0
13889 12:40:56.042450 [1mSubtest pipe-H-query-forked-busy-hang: SKIP (0.000s)[0m
13890 12:40:56.063570 <14>[ 34.228547] [IGT] kms_vblank: executing
13891 12:40:56.069941 IGT-Version: 1.2<14>[ 34.233817] [IGT] kms_vblank: exiting, ret=77
13892 12:40:56.073678 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13893 12:40:56.082949 Opened dev<8>[ 34.244624] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle RESULT=skip>
13894 12:40:56.083497 ice: /dev/dri/card0
13895 12:40:56.084132 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle RESULT=skip
13897 12:40:56.086509 No KMS driver or no outputs, pipes: 8, outputs: 0
13898 12:40:56.093405 [1mSubtest pipe-H-wait-idle: SKIP (0.000s)[0m
13899 12:40:56.109153 <14>[ 34.274387] [IGT] kms_vblank: executing
13900 12:40:56.116099 IGT-Version: 1.2<14>[ 34.279531] [IGT] kms_vblank: exiting, ret=77
13901 12:40:56.119027 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13902 12:40:56.122522 Opened device: /dev/dri/card0
13903 12:40:56.132350 No KMS driver or no outputs<8>[ 34.294142] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip>
13904 12:40:56.133300 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip
13906 12:40:56.135224 , pipes: 8, outputs: 0
13907 12:40:56.138616 [1mSubtest pipe-H-wait-idle-hang: SKIP (0.000s)[0m
13908 12:40:56.159410 <14>[ 34.324295] [IGT] kms_vblank: executing
13909 12:40:56.165582 IGT-Version: 1.2<14>[ 34.329532] [IGT] kms_vblank: exiting, ret=77
13910 12:40:56.169461 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13911 12:40:56.178902 Opened dev<8>[ 34.340392] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked RESULT=skip>
13912 12:40:56.179469 ice: /dev/dri/card0
13913 12:40:56.180115 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked RESULT=skip
13915 12:40:56.185841 No KMS driver or no outputs, pipes: 8, outputs: 0
13916 12:40:56.188813 [1mSubtest pipe-H-wait-forked: SKIP (0.000s)[0m
13917 12:40:56.205197 <14>[ 34.370152] [IGT] kms_vblank: executing
13918 12:40:56.211985 IGT-Version: 1.2<14>[ 34.375327] [IGT] kms_vblank: exiting, ret=77
13919 12:40:56.215235 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13920 12:40:56.218007 Opened device: /dev/dri/card0
13921 12:40:56.228172 No KMS driver or no outputs<8>[ 34.390056] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip>
13922 12:40:56.228994 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip
13924 12:40:56.231416 , pipes: 8, outputs: 0
13925 12:40:56.234692 [1mSubtest pipe-H-wait-forked-hang: SKIP (0.000s)[0m
13926 12:40:56.255052 <14>[ 34.420326] [IGT] kms_vblank: executing
13927 12:40:56.261890 IGT-Version: 1.2<14>[ 34.425591] [IGT] kms_vblank: exiting, ret=77
13928 12:40:56.265475 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13929 12:40:56.275337 Opened dev<8>[ 34.436438] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy RESULT=skip>
13930 12:40:56.275892 ice: /dev/dri/card0
13931 12:40:56.276537 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy RESULT=skip
13933 12:40:56.278451 No KMS driver or no outputs, pipes: 8, outputs: 0
13934 12:40:56.284779 [1mSubtest pipe-H-wait-busy: SKIP (0.000s)[0m
13935 12:40:56.301770 <14>[ 34.466956] [IGT] kms_vblank: executing
13936 12:40:56.308273 IGT-Version: 1.2<14>[ 34.472090] [IGT] kms_vblank: exiting, ret=77
13937 12:40:56.312418 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13938 12:40:56.314948 Opened device: /dev/dri/card0
13939 12:40:56.325567 No KMS driver or no outputs<8>[ 34.487001] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip>
13940 12:40:56.326461 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip
13942 12:40:56.328212 , pipes: 8, outputs: 0
13943 12:40:56.332248 [1mSubtest pipe-H-wait-busy-hang: SKIP (0.000s)[0m
13944 12:40:56.352239 <14>[ 34.517361] [IGT] kms_vblank: executing
13945 12:40:56.358783 IGT-Version: 1.2<14>[ 34.522501] [IGT] kms_vblank: exiting, ret=77
13946 12:40:56.362004 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13947 12:40:56.365857 Opened device: /dev/dri/card0
13948 12:40:56.375418 No KMS driver or no outputs, pipes: 8, outp<8>[ 34.537731] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip>
13949 12:40:56.376258 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip
13951 12:40:56.378666 uts: 0
13952 12:40:56.382279 [1mSubtest pipe-H-wait-forked-busy: SKIP (0.000s)[0m
13953 12:40:56.410315 <14>[ 34.575504] [IGT] kms_vblank: executing
13954 12:40:56.417305 IGT-Version: 1.2<14>[ 34.580636] [IGT] kms_vblank: exiting, ret=77
13955 12:40:56.420313 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13956 12:40:56.423102 Opened device: /dev/dri/card0
13957 12:40:56.433770 No KMS driver or no outputs<8>[ 34.595641] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip>
13958 12:40:56.434678 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip
13960 12:40:56.437053 , pipes: 8, outputs: 0
13961 12:40:56.440116 [1mSubtest pipe-H-wait-forked-busy-hang: SKIP (0.000s)[0m
13962 12:40:56.461076 <14>[ 34.626388] [IGT] kms_vblank: executing
13963 12:40:56.468019 IGT-Version: 1.2<14>[ 34.631572] [IGT] kms_vblank: exiting, ret=77
13964 12:40:56.470742 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13965 12:40:56.474563 Opened device: /dev/dri/card0
13966 12:40:56.484042 No KMS driver or no outputs<8>[ 34.646153] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip>
13967 12:40:56.484874 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip
13969 12:40:56.487411 , pipes: 8, outputs: 0
13970 12:40:56.491192 [1mSubtest pipe-H-ts-continuation-idle: SKIP (0.000s)[0m
13971 12:40:56.518074 <14>[ 34.683091] [IGT] kms_vblank: executing
13972 12:40:56.524300 IGT-Version: 1.2<14>[ 34.688239] [IGT] kms_vblank: exiting, ret=77
13973 12:40:56.527530 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13974 12:40:56.531005 Opened device: /dev/dri/card0
13975 12:40:56.541114 No KMS driver or no outputs<8>[ 34.702636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip>
13976 12:40:56.541985 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip
13978 12:40:56.544130 , pipes: 8, outputs: 0
13979 12:40:56.550571 [1mSubtest pipe-H-ts-continuation-idle-hang: SKIP (0.000s)[0m
13980 12:40:56.570040 <14>[ 34.735122] [IGT] kms_vblank: executing
13981 12:40:56.576921 IGT-Version: 1.2<14>[ 34.740286] [IGT] kms_vblank: exiting, ret=77
13982 12:40:56.579396 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13983 12:40:56.583218 Opened device: /dev/dri/card0
13984 12:40:56.593386 No KMS driver or no outputs<8>[ 34.754564] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip>
13985 12:40:56.594209 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip
13987 12:40:56.597410 , pipes: 8, outputs: 0
13988 12:40:56.599924 [1mSubtest pipe-H-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13989 12:40:56.621685 <14>[ 34.787159] [IGT] kms_vblank: executing
13990 12:40:56.628105 IGT-Version: 1.2<14>[ 34.792342] [IGT] kms_vblank: exiting, ret=77
13991 12:40:56.631457 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
13992 12:40:56.641774 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip
13994 12:40:56.644985 Opened device: /dev/dri/ca<8>[ 34.803739] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip>
13995 12:40:56.645407 rd0
13996 12:40:56.648549 No KMS driver or no outputs, pipes: 8, outputs: 0
13997 12:40:56.654981 [1mSubtest pipe-H-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13998 12:40:56.661519 <14>[ 34.826492] [IGT] kms_vblank: executing
13999 12:40:56.665116 IGT-Version: 1.2<14>[ 34.831251] [IGT] kms_vblank: exiting, ret=77
14000 12:40:56.671329 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
14001 12:40:56.681243 Opened device: /dev/dri/ca<8>[ 34.843564] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip>
14002 12:40:56.681819 rd0
14003 12:40:56.682537 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip
14005 12:40:56.688295 No KMS driver or no outputs, pipes: 8, outputs: 0
14006 12:40:56.691153 [1mSubtest pipe-H-ts-continuation-suspend: SKIP (0.000s)[0m
14007 12:40:56.709001 <14>[ 34.874282] [IGT] kms_vblank: executing
14008 12:40:56.715926 IGT-Version: 1.2<14>[ 34.879422] [IGT] kms_vblank: exiting, ret=77
14009 12:40:56.719294 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
14010 12:40:56.729106 Opened device: /dev/dri/ca<8>[ 34.891196] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip>
14011 12:40:56.729653 rd0
14012 12:40:56.730291 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip
14014 12:40:56.735593 No KMS driver or no outputs, pipes: 8, outputs: 0
14015 12:40:56.739010 [1mSubtest pipe-H-ts-continuation-modeset: SKIP (0.000s)[0m
14016 12:40:56.756267 <14>[ 34.921923] [IGT] kms_vblank: executing
14017 12:40:56.763618 IGT-Version: 1.2<14>[ 34.927113] [IGT] kms_vblank: exiting, ret=77
14018 12:40:56.766881 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
14019 12:40:56.776470 Opened device: /dev/dri/ca<8>[ 34.938879] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip>
14020 12:40:56.777304 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip
14022 12:40:56.781005 rd0
14023 12:40:56.783224 No KMS driver or no outputs, pipes: 8, outputs: 0
14024 12:40:56.789817 [1mSubtest pipe-H-ts-continuation-modeset-hang: SKIP (0.000s)[0m
14025 12:40:56.805412 <14>[ 34.970380] [IGT] kms_vblank: executing
14026 12:40:56.811816 IGT-Version: 1.2<14>[ 34.975802] [IGT] kms_vblank: exiting, ret=77
14027 12:40:56.814997 7.1-g621c2d3 (aarch64) (Linux: 6.1.75-cip14 aarch64)
14028 12:40:56.825449 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip
14030 12:40:56.828470 Opened device: /dev/dri/ca<8>[ 34.987331] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip>
14031 12:40:56.828986 rd0
14032 12:40:56.835089 No KMS driver or no outputs<8>[ 34.998751] <LAVA_SIGNAL_TESTSET STOP>
14033 12:40:56.835832 Received signal: <TESTSET> STOP
14034 12:40:56.836356 Closing test_set kms_vblank
14035 12:40:56.841735 , pipes: 8, outp<8>[ 35.004690] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 12703511_1.5.2.3.1>
14036 12:40:56.842374 uts: 0
14037 12:40:56.843263 Received signal: <ENDRUN> 0_igt-kms-mediatek 12703511_1.5.2.3.1
14038 12:40:56.843817 Ending use of test pattern.
14039 12:40:56.844133 Ending test lava.0_igt-kms-mediatek (12703511_1.5.2.3.1), duration 14.54
14041 12:40:56.848436 [1mSubtest pipe-H-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
14042 12:40:56.849002 + set +x
14043 12:40:56.851830 <LAVA_TEST_RUNNER EXIT>
14044 12:40:56.852590 ok: lava_test_shell seems to have completed
14045 12:40:56.873643 addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic_plane_damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
pipe-A-accuracy-idle:
result: skip
set: kms_vblank
pipe-A-query-busy:
result: skip
set: kms_vblank
pipe-A-query-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked:
result: skip
set: kms_vblank
pipe-A-query-forked-busy:
result: skip
set: kms_vblank
pipe-A-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked-hang:
result: skip
set: kms_vblank
pipe-A-query-idle:
result: skip
set: kms_vblank
pipe-A-query-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-A-wait-busy:
result: skip
set: kms_vblank
pipe-A-wait-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked-hang:
result: skip
set: kms_vblank
pipe-A-wait-idle:
result: skip
set: kms_vblank
pipe-A-wait-idle-hang:
result: skip
set: kms_vblank
pipe-B-accuracy-idle:
result: skip
set: kms_vblank
pipe-B-query-busy:
result: skip
set: kms_vblank
pipe-B-query-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked:
result: skip
set: kms_vblank
pipe-B-query-forked-busy:
result: skip
set: kms_vblank
pipe-B-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked-hang:
result: skip
set: kms_vblank
pipe-B-query-idle:
result: skip
set: kms_vblank
pipe-B-query-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-B-wait-busy:
result: skip
set: kms_vblank
pipe-B-wait-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked-hang:
result: skip
set: kms_vblank
pipe-B-wait-idle:
result: skip
set: kms_vblank
pipe-B-wait-idle-hang:
result: skip
set: kms_vblank
pipe-C-accuracy-idle:
result: skip
set: kms_vblank
pipe-C-query-busy:
result: skip
set: kms_vblank
pipe-C-query-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked:
result: skip
set: kms_vblank
pipe-C-query-forked-busy:
result: skip
set: kms_vblank
pipe-C-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked-hang:
result: skip
set: kms_vblank
pipe-C-query-idle:
result: skip
set: kms_vblank
pipe-C-query-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-C-wait-busy:
result: skip
set: kms_vblank
pipe-C-wait-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked-hang:
result: skip
set: kms_vblank
pipe-C-wait-idle:
result: skip
set: kms_vblank
pipe-C-wait-idle-hang:
result: skip
set: kms_vblank
pipe-D-accuracy-idle:
result: skip
set: kms_vblank
pipe-D-query-busy:
result: skip
set: kms_vblank
pipe-D-query-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked:
result: skip
set: kms_vblank
pipe-D-query-forked-busy:
result: skip
set: kms_vblank
pipe-D-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked-hang:
result: skip
set: kms_vblank
pipe-D-query-idle:
result: skip
set: kms_vblank
pipe-D-query-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-D-wait-busy:
result: skip
set: kms_vblank
pipe-D-wait-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked-hang:
result: skip
set: kms_vblank
pipe-D-wait-idle:
result: skip
set: kms_vblank
pipe-D-wait-idle-hang:
result: skip
set: kms_vblank
pipe-E-accuracy-idle:
result: skip
set: kms_vblank
pipe-E-query-busy:
result: skip
set: kms_vblank
pipe-E-query-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked:
result: skip
set: kms_vblank
pipe-E-query-forked-busy:
result: skip
set: kms_vblank
pipe-E-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked-hang:
result: skip
set: kms_vblank
pipe-E-query-idle:
result: skip
set: kms_vblank
pipe-E-query-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-E-wait-busy:
result: skip
set: kms_vblank
pipe-E-wait-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked-hang:
result: skip
set: kms_vblank
pipe-E-wait-idle:
result: skip
set: kms_vblank
pipe-E-wait-idle-hang:
result: skip
set: kms_vblank
pipe-F-accuracy-idle:
result: skip
set: kms_vblank
pipe-F-query-busy:
result: skip
set: kms_vblank
pipe-F-query-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked:
result: skip
set: kms_vblank
pipe-F-query-forked-busy:
result: skip
set: kms_vblank
pipe-F-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked-hang:
result: skip
set: kms_vblank
pipe-F-query-idle:
result: skip
set: kms_vblank
pipe-F-query-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-F-wait-busy:
result: skip
set: kms_vblank
pipe-F-wait-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked-hang:
result: skip
set: kms_vblank
pipe-F-wait-idle:
result: skip
set: kms_vblank
pipe-F-wait-idle-hang:
result: skip
set: kms_vblank
pipe-G-accuracy-idle:
result: skip
set: kms_vblank
pipe-G-query-busy:
result: skip
set: kms_vblank
pipe-G-query-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked:
result: skip
set: kms_vblank
pipe-G-query-forked-busy:
result: skip
set: kms_vblank
pipe-G-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked-hang:
result: skip
set: kms_vblank
pipe-G-query-idle:
result: skip
set: kms_vblank
pipe-G-query-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-G-wait-busy:
result: skip
set: kms_vblank
pipe-G-wait-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked-hang:
result: skip
set: kms_vblank
pipe-G-wait-idle:
result: skip
set: kms_vblank
pipe-G-wait-idle-hang:
result: skip
set: kms_vblank
pipe-H-accuracy-idle:
result: skip
set: kms_vblank
pipe-H-query-busy:
result: skip
set: kms_vblank
pipe-H-query-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked:
result: skip
set: kms_vblank
pipe-H-query-forked-busy:
result: skip
set: kms_vblank
pipe-H-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked-hang:
result: skip
set: kms_vblank
pipe-H-query-idle:
result: skip
set: kms_vblank
pipe-H-query-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-H-wait-busy:
result: skip
set: kms_vblank
pipe-H-wait-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked-hang:
result: skip
set: kms_vblank
pipe-H-wait-idle:
result: skip
set: kms_vblank
pipe-H-wait-idle-hang:
result: skip
set: kms_vblank
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
14046 12:40:56.875080 end: 3.1 lava-test-shell (duration 00:00:15) [common]
14047 12:40:56.875628 end: 3 lava-test-retry (duration 00:00:15) [common]
14048 12:40:56.876121 start: 4 finalize (timeout 00:06:48) [common]
14049 12:40:56.876586 start: 4.1 power-off (timeout 00:00:30) [common]
14050 12:40:56.877370 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
14051 12:40:56.987646 >> Command sent successfully.
14052 12:40:56.995664 Returned 0 in 0 seconds
14053 12:40:57.096877 end: 4.1 power-off (duration 00:00:00) [common]
14055 12:40:57.098468 start: 4.2 read-feedback (timeout 00:06:48) [common]
14056 12:40:57.099862 Listened to connection for namespace 'common' for up to 1s
14057 12:40:58.100598 Finalising connection for namespace 'common'
14058 12:40:58.101285 Disconnecting from shell: Finalise
14059 12:40:58.101714 / #
14060 12:40:58.202827 end: 4.2 read-feedback (duration 00:00:01) [common]
14061 12:40:58.203579 end: 4 finalize (duration 00:00:01) [common]
14062 12:40:58.204221 Cleaning after the job
14063 12:40:58.204716 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703511/tftp-deploy-446whshk/ramdisk
14064 12:40:58.238090 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703511/tftp-deploy-446whshk/kernel
14065 12:40:58.255273 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703511/tftp-deploy-446whshk/dtb
14066 12:40:58.255522 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703511/tftp-deploy-446whshk/modules
14067 12:40:58.265075 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12703511
14068 12:40:58.380966 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12703511
14069 12:40:58.381144 Job finished correctly