Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 16
- Kernel Errors: 37
1 12:42:36.602427 lava-dispatcher, installed at version: 2024.01
2 12:42:36.602625 start: 0 validate
3 12:42:36.602754 Start time: 2024-02-05 12:42:36.602744+00:00 (UTC)
4 12:42:36.602914 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:42:36.603045 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20231214.0%2Farm64%2Finitrd.cpio.gz exists
6 12:42:36.873610 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:42:36.873800 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:42:37.139543 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:42:37.139704 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:42:37.405094 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:42:37.405274 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20231214.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:42:37.669030 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:42:37.669212 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:42:37.933991 validate duration: 1.33
16 12:42:37.934242 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:42:37.934336 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:42:37.934419 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:42:37.934542 Not decompressing ramdisk as can be used compressed.
20 12:42:37.934625 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20231214.0/arm64/initrd.cpio.gz
21 12:42:37.934688 saving as /var/lib/lava/dispatcher/tmp/12703562/tftp-deploy-1njj5dyf/ramdisk/initrd.cpio.gz
22 12:42:37.934751 total size: 5628325 (5 MB)
23 12:42:37.935985 progress 0 % (0 MB)
24 12:42:37.937769 progress 5 % (0 MB)
25 12:42:37.939350 progress 10 % (0 MB)
26 12:42:37.940833 progress 15 % (0 MB)
27 12:42:37.942418 progress 20 % (1 MB)
28 12:42:37.943871 progress 25 % (1 MB)
29 12:42:37.945414 progress 30 % (1 MB)
30 12:42:37.946994 progress 35 % (1 MB)
31 12:42:37.948441 progress 40 % (2 MB)
32 12:42:37.950094 progress 45 % (2 MB)
33 12:42:37.951510 progress 50 % (2 MB)
34 12:42:37.953099 progress 55 % (2 MB)
35 12:42:37.954690 progress 60 % (3 MB)
36 12:42:37.956107 progress 65 % (3 MB)
37 12:42:37.957694 progress 70 % (3 MB)
38 12:42:37.959073 progress 75 % (4 MB)
39 12:42:37.960620 progress 80 % (4 MB)
40 12:42:37.962046 progress 85 % (4 MB)
41 12:42:37.963618 progress 90 % (4 MB)
42 12:42:37.965154 progress 95 % (5 MB)
43 12:42:37.966592 progress 100 % (5 MB)
44 12:42:37.966798 5 MB downloaded in 0.03 s (167.49 MB/s)
45 12:42:37.966942 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:42:37.967184 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:42:37.967326 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:42:37.967449 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:42:37.967578 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:42:37.967646 saving as /var/lib/lava/dispatcher/tmp/12703562/tftp-deploy-1njj5dyf/kernel/Image
52 12:42:37.967706 total size: 51534336 (49 MB)
53 12:42:37.967766 No compression specified
54 12:42:37.968949 progress 0 % (0 MB)
55 12:42:37.982905 progress 5 % (2 MB)
56 12:42:37.996380 progress 10 % (4 MB)
57 12:42:38.009713 progress 15 % (7 MB)
58 12:42:38.023227 progress 20 % (9 MB)
59 12:42:38.036632 progress 25 % (12 MB)
60 12:42:38.050286 progress 30 % (14 MB)
61 12:42:38.063927 progress 35 % (17 MB)
62 12:42:38.077418 progress 40 % (19 MB)
63 12:42:38.090898 progress 45 % (22 MB)
64 12:42:38.104212 progress 50 % (24 MB)
65 12:42:38.117400 progress 55 % (27 MB)
66 12:42:38.130836 progress 60 % (29 MB)
67 12:42:38.144326 progress 65 % (31 MB)
68 12:42:38.157943 progress 70 % (34 MB)
69 12:42:38.171398 progress 75 % (36 MB)
70 12:42:38.184862 progress 80 % (39 MB)
71 12:42:38.198185 progress 85 % (41 MB)
72 12:42:38.211450 progress 90 % (44 MB)
73 12:42:38.224415 progress 95 % (46 MB)
74 12:42:38.237205 progress 100 % (49 MB)
75 12:42:38.237416 49 MB downloaded in 0.27 s (182.22 MB/s)
76 12:42:38.237636 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:42:38.237872 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:42:38.237961 start: 1.3 download-retry (timeout 00:10:00) [common]
80 12:42:38.238044 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 12:42:38.238192 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:42:38.238270 saving as /var/lib/lava/dispatcher/tmp/12703562/tftp-deploy-1njj5dyf/dtb/mt8192-asurada-spherion-r0.dtb
83 12:42:38.238331 total size: 47278 (0 MB)
84 12:42:38.238391 No compression specified
85 12:42:38.239498 progress 69 % (0 MB)
86 12:42:38.239770 progress 100 % (0 MB)
87 12:42:38.239927 0 MB downloaded in 0.00 s (28.30 MB/s)
88 12:42:38.240048 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:42:38.240266 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:42:38.240350 start: 1.4 download-retry (timeout 00:10:00) [common]
92 12:42:38.240431 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 12:42:38.240541 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20231214.0/arm64/full.rootfs.tar.xz
94 12:42:38.240612 saving as /var/lib/lava/dispatcher/tmp/12703562/tftp-deploy-1njj5dyf/nfsrootfs/full.rootfs.tar
95 12:42:38.240672 total size: 198084472 (188 MB)
96 12:42:38.240733 Using unxz to decompress xz
97 12:42:38.244873 progress 0 % (0 MB)
98 12:42:38.807925 progress 5 % (9 MB)
99 12:42:39.308691 progress 10 % (18 MB)
100 12:42:39.907849 progress 15 % (28 MB)
101 12:42:40.205091 progress 20 % (37 MB)
102 12:42:40.701731 progress 25 % (47 MB)
103 12:42:41.302419 progress 30 % (56 MB)
104 12:42:41.873447 progress 35 % (66 MB)
105 12:42:42.474654 progress 40 % (75 MB)
106 12:42:43.092629 progress 45 % (85 MB)
107 12:42:43.724468 progress 50 % (94 MB)
108 12:42:44.336117 progress 55 % (103 MB)
109 12:42:45.044643 progress 60 % (113 MB)
110 12:42:45.446391 progress 65 % (122 MB)
111 12:42:45.540257 progress 70 % (132 MB)
112 12:42:45.683006 progress 75 % (141 MB)
113 12:42:45.759593 progress 80 % (151 MB)
114 12:42:45.810247 progress 85 % (160 MB)
115 12:42:45.905446 progress 90 % (170 MB)
116 12:42:46.267439 progress 95 % (179 MB)
117 12:42:46.845323 progress 100 % (188 MB)
118 12:42:46.849991 188 MB downloaded in 8.61 s (21.94 MB/s)
119 12:42:46.850249 end: 1.4.1 http-download (duration 00:00:09) [common]
121 12:42:46.850519 end: 1.4 download-retry (duration 00:00:09) [common]
122 12:42:46.850608 start: 1.5 download-retry (timeout 00:09:51) [common]
123 12:42:46.850696 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 12:42:46.850850 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:42:46.850922 saving as /var/lib/lava/dispatcher/tmp/12703562/tftp-deploy-1njj5dyf/modules/modules.tar
126 12:42:46.850982 total size: 8639964 (8 MB)
127 12:42:46.851046 Using unxz to decompress xz
128 12:42:46.855137 progress 0 % (0 MB)
129 12:42:46.876127 progress 5 % (0 MB)
130 12:42:46.899719 progress 10 % (0 MB)
131 12:42:46.923197 progress 15 % (1 MB)
132 12:42:46.946665 progress 20 % (1 MB)
133 12:42:46.970526 progress 25 % (2 MB)
134 12:42:46.998245 progress 30 % (2 MB)
135 12:42:47.022383 progress 35 % (2 MB)
136 12:42:47.046054 progress 40 % (3 MB)
137 12:42:47.070454 progress 45 % (3 MB)
138 12:42:47.095698 progress 50 % (4 MB)
139 12:42:47.121910 progress 55 % (4 MB)
140 12:42:47.146358 progress 60 % (4 MB)
141 12:42:47.171873 progress 65 % (5 MB)
142 12:42:47.196785 progress 70 % (5 MB)
143 12:42:47.220288 progress 75 % (6 MB)
144 12:42:47.247073 progress 80 % (6 MB)
145 12:42:47.274658 progress 85 % (7 MB)
146 12:42:47.299512 progress 90 % (7 MB)
147 12:42:47.329251 progress 95 % (7 MB)
148 12:42:47.356910 progress 100 % (8 MB)
149 12:42:47.362783 8 MB downloaded in 0.51 s (16.10 MB/s)
150 12:42:47.363081 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:42:47.363407 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:42:47.363499 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 12:42:47.363594 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 12:42:51.232060 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12703562/extract-nfsrootfs-3xh3n14o
156 12:42:51.232254 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 12:42:51.232354 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 12:42:51.232533 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw
159 12:42:51.232672 makedir: /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/bin
160 12:42:51.232778 makedir: /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/tests
161 12:42:51.232880 makedir: /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/results
162 12:42:51.232985 Creating /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/bin/lava-add-keys
163 12:42:51.233137 Creating /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/bin/lava-add-sources
164 12:42:51.233271 Creating /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/bin/lava-background-process-start
165 12:42:51.233404 Creating /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/bin/lava-background-process-stop
166 12:42:51.233545 Creating /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/bin/lava-common-functions
167 12:42:51.233679 Creating /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/bin/lava-echo-ipv4
168 12:42:51.233811 Creating /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/bin/lava-install-packages
169 12:42:51.233942 Creating /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/bin/lava-installed-packages
170 12:42:51.234072 Creating /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/bin/lava-os-build
171 12:42:51.234205 Creating /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/bin/lava-probe-channel
172 12:42:51.234335 Creating /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/bin/lava-probe-ip
173 12:42:51.234464 Creating /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/bin/lava-target-ip
174 12:42:51.234594 Creating /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/bin/lava-target-mac
175 12:42:51.234725 Creating /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/bin/lava-target-storage
176 12:42:51.234932 Creating /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/bin/lava-test-case
177 12:42:51.235070 Creating /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/bin/lava-test-event
178 12:42:51.235202 Creating /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/bin/lava-test-feedback
179 12:42:51.235334 Creating /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/bin/lava-test-raise
180 12:42:51.235466 Creating /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/bin/lava-test-reference
181 12:42:51.235599 Creating /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/bin/lava-test-runner
182 12:42:51.235740 Creating /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/bin/lava-test-set
183 12:42:51.235871 Creating /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/bin/lava-test-shell
184 12:42:51.236005 Updating /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/bin/lava-add-keys (debian)
185 12:42:51.236166 Updating /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/bin/lava-add-sources (debian)
186 12:42:51.236316 Updating /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/bin/lava-install-packages (debian)
187 12:42:51.236495 Updating /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/bin/lava-installed-packages (debian)
188 12:42:51.236646 Updating /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/bin/lava-os-build (debian)
189 12:42:51.236774 Creating /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/environment
190 12:42:51.236878 LAVA metadata
191 12:42:51.236952 - LAVA_JOB_ID=12703562
192 12:42:51.237018 - LAVA_DISPATCHER_IP=192.168.201.1
193 12:42:51.237122 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 12:42:51.237190 skipped lava-vland-overlay
195 12:42:51.237268 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 12:42:51.237352 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 12:42:51.237415 skipped lava-multinode-overlay
198 12:42:51.237570 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 12:42:51.237703 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 12:42:51.237784 Loading test definitions
201 12:42:51.237877 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 12:42:51.237952 Using /lava-12703562 at stage 0
203 12:42:51.238245 uuid=12703562_1.6.2.3.1 testdef=None
204 12:42:51.238337 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 12:42:51.238422 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 12:42:51.238890 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 12:42:51.239116 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 12:42:51.239692 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 12:42:51.239927 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 12:42:51.240481 runner path: /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/0/tests/0_timesync-off test_uuid 12703562_1.6.2.3.1
213 12:42:51.240646 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 12:42:51.240876 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 12:42:51.240957 Using /lava-12703562 at stage 0
217 12:42:51.241092 Fetching tests from https://github.com/kernelci/test-definitions.git
218 12:42:51.241183 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/0/tests/1_kselftest-alsa'
219 12:42:58.398200 Running '/usr/bin/git checkout kernelci.org
220 12:42:58.550556 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 12:42:58.551328 uuid=12703562_1.6.2.3.5 testdef=None
222 12:42:58.551495 end: 1.6.2.3.5 git-repo-action (duration 00:00:07) [common]
224 12:42:58.551755 start: 1.6.2.3.6 test-overlay (timeout 00:09:39) [common]
225 12:42:58.552539 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 12:42:58.552775 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:39) [common]
228 12:42:58.553788 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 12:42:58.554031 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:39) [common]
231 12:42:58.555017 runner path: /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/0/tests/1_kselftest-alsa test_uuid 12703562_1.6.2.3.5
232 12:42:58.555116 BOARD='mt8192-asurada-spherion-r0'
233 12:42:58.555185 BRANCH='cip-gitlab'
234 12:42:58.555247 SKIPFILE='/dev/null'
235 12:42:58.555307 SKIP_INSTALL='True'
236 12:42:58.555365 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 12:42:58.555428 TST_CASENAME=''
238 12:42:58.555493 TST_CMDFILES='alsa'
239 12:42:58.555686 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 12:42:58.555944 Creating lava-test-runner.conf files
242 12:42:58.556041 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12703562/lava-overlay-mtn72asw/lava-12703562/0 for stage 0
243 12:42:58.556175 - 0_timesync-off
244 12:42:58.556282 - 1_kselftest-alsa
245 12:42:58.556416 end: 1.6.2.3 test-definition (duration 00:00:07) [common]
246 12:42:58.556547 start: 1.6.2.4 compress-overlay (timeout 00:09:39) [common]
247 12:43:06.157441 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 12:43:06.157995 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:32) [common]
249 12:43:06.158086 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 12:43:06.158185 end: 1.6.2 lava-overlay (duration 00:00:15) [common]
251 12:43:06.158278 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:32) [common]
252 12:43:06.330535 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 12:43:06.330948 start: 1.6.4 extract-modules (timeout 00:09:32) [common]
254 12:43:06.331066 extracting modules file /var/lib/lava/dispatcher/tmp/12703562/tftp-deploy-1njj5dyf/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12703562/extract-nfsrootfs-3xh3n14o
255 12:43:06.556478 extracting modules file /var/lib/lava/dispatcher/tmp/12703562/tftp-deploy-1njj5dyf/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12703562/extract-overlay-ramdisk-2e52dutx/ramdisk
256 12:43:06.784134 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 12:43:06.784309 start: 1.6.5 apply-overlay-tftp (timeout 00:09:31) [common]
258 12:43:06.784399 [common] Applying overlay to NFS
259 12:43:06.784472 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12703562/compress-overlay-282c24jc/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12703562/extract-nfsrootfs-3xh3n14o
260 12:43:07.710155 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 12:43:07.710341 start: 1.6.6 configure-preseed-file (timeout 00:09:30) [common]
262 12:43:07.710439 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 12:43:07.710529 start: 1.6.7 compress-ramdisk (timeout 00:09:30) [common]
264 12:43:07.710611 Building ramdisk /var/lib/lava/dispatcher/tmp/12703562/extract-overlay-ramdisk-2e52dutx/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12703562/extract-overlay-ramdisk-2e52dutx/ramdisk
265 12:43:08.037358 >> 130555 blocks
266 12:43:10.098166 rename /var/lib/lava/dispatcher/tmp/12703562/extract-overlay-ramdisk-2e52dutx/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12703562/tftp-deploy-1njj5dyf/ramdisk/ramdisk.cpio.gz
267 12:43:10.098643 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 12:43:10.098762 start: 1.6.8 prepare-kernel (timeout 00:09:28) [common]
269 12:43:10.098866 start: 1.6.8.1 prepare-fit (timeout 00:09:28) [common]
270 12:43:10.098975 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12703562/tftp-deploy-1njj5dyf/kernel/Image'
271 12:43:23.056591 Returned 0 in 12 seconds
272 12:43:23.157704 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12703562/tftp-deploy-1njj5dyf/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12703562/tftp-deploy-1njj5dyf/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12703562/tftp-deploy-1njj5dyf/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12703562/tftp-deploy-1njj5dyf/kernel/image.itb
273 12:43:23.557992 output: FIT description: Kernel Image image with one or more FDT blobs
274 12:43:23.558371 output: Created: Mon Feb 5 12:43:23 2024
275 12:43:23.558445 output: Image 0 (kernel-1)
276 12:43:23.558510 output: Description:
277 12:43:23.558572 output: Created: Mon Feb 5 12:43:23 2024
278 12:43:23.558632 output: Type: Kernel Image
279 12:43:23.558693 output: Compression: lzma compressed
280 12:43:23.558752 output: Data Size: 12052857 Bytes = 11770.37 KiB = 11.49 MiB
281 12:43:23.558813 output: Architecture: AArch64
282 12:43:23.558872 output: OS: Linux
283 12:43:23.558931 output: Load Address: 0x00000000
284 12:43:23.558986 output: Entry Point: 0x00000000
285 12:43:23.559038 output: Hash algo: crc32
286 12:43:23.559092 output: Hash value: 8a14336a
287 12:43:23.559148 output: Image 1 (fdt-1)
288 12:43:23.559202 output: Description: mt8192-asurada-spherion-r0
289 12:43:23.559256 output: Created: Mon Feb 5 12:43:23 2024
290 12:43:23.559338 output: Type: Flat Device Tree
291 12:43:23.559390 output: Compression: uncompressed
292 12:43:23.559458 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 12:43:23.559524 output: Architecture: AArch64
294 12:43:23.559590 output: Hash algo: crc32
295 12:43:23.559656 output: Hash value: cc4352de
296 12:43:23.559707 output: Image 2 (ramdisk-1)
297 12:43:23.559758 output: Description: unavailable
298 12:43:23.559810 output: Created: Mon Feb 5 12:43:23 2024
299 12:43:23.559878 output: Type: RAMDisk Image
300 12:43:23.559930 output: Compression: Unknown Compression
301 12:43:23.559983 output: Data Size: 18769045 Bytes = 18329.15 KiB = 17.90 MiB
302 12:43:23.560036 output: Architecture: AArch64
303 12:43:23.560089 output: OS: Linux
304 12:43:23.560141 output: Load Address: unavailable
305 12:43:23.560194 output: Entry Point: unavailable
306 12:43:23.560246 output: Hash algo: crc32
307 12:43:23.560299 output: Hash value: 9ac17f6a
308 12:43:23.560351 output: Default Configuration: 'conf-1'
309 12:43:23.560404 output: Configuration 0 (conf-1)
310 12:43:23.560456 output: Description: mt8192-asurada-spherion-r0
311 12:43:23.560509 output: Kernel: kernel-1
312 12:43:23.560562 output: Init Ramdisk: ramdisk-1
313 12:43:23.560627 output: FDT: fdt-1
314 12:43:23.560679 output: Loadables: kernel-1
315 12:43:23.560731 output:
316 12:43:23.560955 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 12:43:23.561106 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 12:43:23.561208 end: 1.6 prepare-tftp-overlay (duration 00:00:36) [common]
319 12:43:23.561299 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:14) [common]
320 12:43:23.561387 No LXC device requested
321 12:43:23.561468 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 12:43:23.561628 start: 1.8 deploy-device-env (timeout 00:09:14) [common]
323 12:43:23.561707 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 12:43:23.561778 Checking files for TFTP limit of 4294967296 bytes.
325 12:43:23.562312 end: 1 tftp-deploy (duration 00:00:46) [common]
326 12:43:23.562423 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 12:43:23.562519 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 12:43:23.562654 substitutions:
329 12:43:23.562725 - {DTB}: 12703562/tftp-deploy-1njj5dyf/dtb/mt8192-asurada-spherion-r0.dtb
330 12:43:23.562790 - {INITRD}: 12703562/tftp-deploy-1njj5dyf/ramdisk/ramdisk.cpio.gz
331 12:43:23.562851 - {KERNEL}: 12703562/tftp-deploy-1njj5dyf/kernel/Image
332 12:43:23.562910 - {LAVA_MAC}: None
333 12:43:23.562966 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12703562/extract-nfsrootfs-3xh3n14o
334 12:43:23.563023 - {NFS_SERVER_IP}: 192.168.201.1
335 12:43:23.563078 - {PRESEED_CONFIG}: None
336 12:43:23.563132 - {PRESEED_LOCAL}: None
337 12:43:23.563187 - {RAMDISK}: 12703562/tftp-deploy-1njj5dyf/ramdisk/ramdisk.cpio.gz
338 12:43:23.563242 - {ROOT_PART}: None
339 12:43:23.563297 - {ROOT}: None
340 12:43:23.563351 - {SERVER_IP}: 192.168.201.1
341 12:43:23.563406 - {TEE}: None
342 12:43:23.563460 Parsed boot commands:
343 12:43:23.563516 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 12:43:23.563741 Parsed boot commands: tftpboot 192.168.201.1 12703562/tftp-deploy-1njj5dyf/kernel/image.itb 12703562/tftp-deploy-1njj5dyf/kernel/cmdline
345 12:43:23.563875 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 12:43:23.563960 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 12:43:23.564067 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 12:43:23.564168 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 12:43:23.564239 Not connected, no need to disconnect.
350 12:43:23.564328 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 12:43:23.564419 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 12:43:23.564486 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
353 12:43:23.568867 Setting prompt string to ['lava-test: # ']
354 12:43:23.569267 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 12:43:23.569407 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 12:43:23.569523 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 12:43:23.569668 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 12:43:23.569934 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
359 12:43:28.704799 >> Command sent successfully.
360 12:43:28.714324 Returned 0 in 5 seconds
361 12:43:28.815416 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 12:43:28.817182 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 12:43:28.817746 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 12:43:28.818114 Setting prompt string to 'Starting depthcharge on Spherion...'
366 12:43:28.818375 Changing prompt to 'Starting depthcharge on Spherion...'
367 12:43:28.818630 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 12:43:28.819692 [Enter `^Ec?' for help]
369 12:43:28.981023
370 12:43:28.981289
371 12:43:28.981449 F0: 102B 0000
372 12:43:28.981625
373 12:43:28.981772 F3: 1001 0000 [0200]
374 12:43:28.981901
375 12:43:28.984473 F3: 1001 0000
376 12:43:28.984680
377 12:43:28.984843 F7: 102D 0000
378 12:43:28.984998
379 12:43:28.985146 F1: 0000 0000
380 12:43:28.988168
381 12:43:28.988507 V0: 0000 0000 [0001]
382 12:43:28.988726
383 12:43:28.988914 00: 0007 8000
384 12:43:28.989106
385 12:43:28.991875 01: 0000 0000
386 12:43:28.992128
387 12:43:28.992323 BP: 0C00 0209 [0000]
388 12:43:28.992516
389 12:43:28.995381 G0: 1182 0000
390 12:43:28.995689
391 12:43:28.995933 EC: 0000 0021 [4000]
392 12:43:28.996164
393 12:43:28.998925 S7: 0000 0000 [0000]
394 12:43:28.999617
395 12:43:28.999960 CC: 0000 0000 [0001]
396 12:43:29.000265
397 12:43:29.002360 T0: 0000 0040 [010F]
398 12:43:29.002876
399 12:43:29.003313 Jump to BL
400 12:43:29.003622
401 12:43:29.027678
402 12:43:29.027871
403 12:43:29.027962
404 12:43:29.034909 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 12:43:29.039197 ARM64: Exception handlers installed.
406 12:43:29.042770 ARM64: Testing exception
407 12:43:29.046122 ARM64: Done test exception
408 12:43:29.053142 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 12:43:29.063633 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 12:43:29.070897 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 12:43:29.080619 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 12:43:29.087436 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 12:43:29.094045 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 12:43:29.104247 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 12:43:29.111311 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 12:43:29.130981 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 12:43:29.134142 WDT: Last reset was cold boot
418 12:43:29.137359 SPI1(PAD0) initialized at 2873684 Hz
419 12:43:29.141058 SPI5(PAD0) initialized at 992727 Hz
420 12:43:29.144357 VBOOT: Loading verstage.
421 12:43:29.150885 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:43:29.154211 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 12:43:29.157385 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 12:43:29.160934 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 12:43:29.168216 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 12:43:29.175102 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 12:43:29.185946 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 12:43:29.186502
429 12:43:29.186849
430 12:43:29.195692 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 12:43:29.198921 ARM64: Exception handlers installed.
432 12:43:29.202237 ARM64: Testing exception
433 12:43:29.202663 ARM64: Done test exception
434 12:43:29.208973 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 12:43:29.212268 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 12:43:29.226277 Probing TPM: . done!
437 12:43:29.226477 TPM ready after 0 ms
438 12:43:29.233158 Connected to device vid:did:rid of 1ae0:0028:00
439 12:43:29.240328 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 12:43:29.280058 Initialized TPM device CR50 revision 0
441 12:43:29.291565 tlcl_send_startup: Startup return code is 0
442 12:43:29.291667 TPM: setup succeeded
443 12:43:29.303212 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 12:43:29.311961 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 12:43:29.323502 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 12:43:29.332764 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 12:43:29.335978 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 12:43:29.340963 in-header: 03 07 00 00 08 00 00 00
449 12:43:29.345122 in-data: aa e4 47 04 13 02 00 00
450 12:43:29.348277 Chrome EC: UHEPI supported
451 12:43:29.355270 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 12:43:29.358782 in-header: 03 9d 00 00 08 00 00 00
453 12:43:29.363084 in-data: 10 20 20 08 00 00 00 00
454 12:43:29.363582 Phase 1
455 12:43:29.369722 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 12:43:29.373413 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 12:43:29.380229 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 12:43:29.384175 Recovery requested (1009000e)
459 12:43:29.390152 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 12:43:29.396046 tlcl_extend: response is 0
461 12:43:29.405099 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 12:43:29.409111 tlcl_extend: response is 0
463 12:43:29.416436 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 12:43:29.437695 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 12:43:29.444152 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 12:43:29.444611
467 12:43:29.444949
468 12:43:29.451533 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 12:43:29.455092 ARM64: Exception handlers installed.
470 12:43:29.458836 ARM64: Testing exception
471 12:43:29.461907 ARM64: Done test exception
472 12:43:29.482570 pmic_efuse_setting: Set efuses in 11 msecs
473 12:43:29.485999 pmwrap_interface_init: Select PMIF_VLD_RDY
474 12:43:29.489555 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 12:43:29.496864 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 12:43:29.500893 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 12:43:29.504654 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 12:43:29.512737 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 12:43:29.516204 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 12:43:29.520237 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 12:43:29.523677 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 12:43:29.530723 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 12:43:29.533680 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 12:43:29.537365 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 12:43:29.543855 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 12:43:29.547642 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 12:43:29.553979 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 12:43:29.560755 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 12:43:29.564220 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 12:43:29.570856 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 12:43:29.577374 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 12:43:29.584601 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 12:43:29.588611 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 12:43:29.592078 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 12:43:29.599270 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 12:43:29.606008 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 12:43:29.609429 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 12:43:29.616376 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 12:43:29.620085 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 12:43:29.626542 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 12:43:29.630422 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 12:43:29.636682 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 12:43:29.640346 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 12:43:29.647986 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 12:43:29.651520 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 12:43:29.654904 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 12:43:29.662722 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 12:43:29.666541 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 12:43:29.670609 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 12:43:29.674433 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 12:43:29.681063 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 12:43:29.684492 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 12:43:29.691076 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 12:43:29.694269 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 12:43:29.697910 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 12:43:29.704684 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 12:43:29.707528 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 12:43:29.710882 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 12:43:29.718030 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 12:43:29.721357 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 12:43:29.724505 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 12:43:29.728045 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 12:43:29.731076 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 12:43:29.738079 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 12:43:29.744404 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 12:43:29.754151 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 12:43:29.757613 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 12:43:29.764482 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 12:43:29.774260 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 12:43:29.777800 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 12:43:29.784623 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 12:43:29.788004 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 12:43:29.794928 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
534 12:43:29.801560 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 12:43:29.804897 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 12:43:29.808176 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 12:43:29.819408 [RTC]rtc_get_frequency_meter,154: input=15, output=794
538 12:43:29.822514 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
539 12:43:29.829317 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
540 12:43:29.832898 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
541 12:43:29.835873 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
542 12:43:29.839459 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
543 12:43:29.842446 ADC[4]: Raw value=898520 ID=7
544 12:43:29.845771 ADC[3]: Raw value=213440 ID=1
545 12:43:29.849289 RAM Code: 0x71
546 12:43:29.852592 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
547 12:43:29.855831 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
548 12:43:29.865746 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
549 12:43:29.873069 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
550 12:43:29.876404 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
551 12:43:29.879268 in-header: 03 07 00 00 08 00 00 00
552 12:43:29.882701 in-data: aa e4 47 04 13 02 00 00
553 12:43:29.885988 Chrome EC: UHEPI supported
554 12:43:29.893728 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
555 12:43:29.897073 in-header: 03 d5 00 00 08 00 00 00
556 12:43:29.900672 in-data: 98 20 60 08 00 00 00 00
557 12:43:29.901237 MRC: failed to locate region type 0.
558 12:43:29.908851 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
559 12:43:29.912261 DRAM-K: Running full calibration
560 12:43:29.918366 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
561 12:43:29.921944 header.status = 0x0
562 12:43:29.922477 header.version = 0x6 (expected: 0x6)
563 12:43:29.929207 header.size = 0xd00 (expected: 0xd00)
564 12:43:29.929790 header.flags = 0x0
565 12:43:29.935528 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
566 12:43:29.952367 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
567 12:43:29.959540 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
568 12:43:29.963463 dram_init: ddr_geometry: 2
569 12:43:29.963888 [EMI] MDL number = 2
570 12:43:29.967222 [EMI] Get MDL freq = 0
571 12:43:29.967717 dram_init: ddr_type: 0
572 12:43:29.970624 is_discrete_lpddr4: 1
573 12:43:29.974520 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
574 12:43:29.975048
575 12:43:29.975385
576 12:43:29.977944 [Bian_co] ETT version 0.0.0.1
577 12:43:29.981426 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
578 12:43:29.981901
579 12:43:29.984937 dramc_set_vcore_voltage set vcore to 650000
580 12:43:29.989199 Read voltage for 800, 4
581 12:43:29.989776 Vio18 = 0
582 12:43:29.990121 Vcore = 650000
583 12:43:29.990434 Vdram = 0
584 12:43:29.992578 Vddq = 0
585 12:43:29.992996 Vmddr = 0
586 12:43:29.993330 dram_init: config_dvfs: 1
587 12:43:30.000424 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
588 12:43:30.004043 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
589 12:43:30.007468 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
590 12:43:30.011048 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
591 12:43:30.015012 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
592 12:43:30.018236 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
593 12:43:30.022206 MEM_TYPE=3, freq_sel=18
594 12:43:30.025622 sv_algorithm_assistance_LP4_1600
595 12:43:30.029302 ============ PULL DRAM RESETB DOWN ============
596 12:43:30.032314 ========== PULL DRAM RESETB DOWN end =========
597 12:43:30.039040 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
598 12:43:30.042808 ===================================
599 12:43:30.043247 LPDDR4 DRAM CONFIGURATION
600 12:43:30.045662 ===================================
601 12:43:30.049518 EX_ROW_EN[0] = 0x0
602 12:43:30.052695 EX_ROW_EN[1] = 0x0
603 12:43:30.053225 LP4Y_EN = 0x0
604 12:43:30.055977 WORK_FSP = 0x0
605 12:43:30.056402 WL = 0x2
606 12:43:30.059104 RL = 0x2
607 12:43:30.059573 BL = 0x2
608 12:43:30.062844 RPST = 0x0
609 12:43:30.063381 RD_PRE = 0x0
610 12:43:30.065617 WR_PRE = 0x1
611 12:43:30.066045 WR_PST = 0x0
612 12:43:30.068958 DBI_WR = 0x0
613 12:43:30.069382 DBI_RD = 0x0
614 12:43:30.072872 OTF = 0x1
615 12:43:30.076038 ===================================
616 12:43:30.079098 ===================================
617 12:43:30.079635 ANA top config
618 12:43:30.082424 ===================================
619 12:43:30.085781 DLL_ASYNC_EN = 0
620 12:43:30.089356 ALL_SLAVE_EN = 1
621 12:43:30.089928 NEW_RANK_MODE = 1
622 12:43:30.093044 DLL_IDLE_MODE = 1
623 12:43:30.095736 LP45_APHY_COMB_EN = 1
624 12:43:30.099454 TX_ODT_DIS = 1
625 12:43:30.102887 NEW_8X_MODE = 1
626 12:43:30.106266 ===================================
627 12:43:30.109554 ===================================
628 12:43:30.110096 data_rate = 1600
629 12:43:30.112823 CKR = 1
630 12:43:30.116155 DQ_P2S_RATIO = 8
631 12:43:30.119235 ===================================
632 12:43:30.122783 CA_P2S_RATIO = 8
633 12:43:30.125857 DQ_CA_OPEN = 0
634 12:43:30.128926 DQ_SEMI_OPEN = 0
635 12:43:30.129351 CA_SEMI_OPEN = 0
636 12:43:30.132901 CA_FULL_RATE = 0
637 12:43:30.136069 DQ_CKDIV4_EN = 1
638 12:43:30.139311 CA_CKDIV4_EN = 1
639 12:43:30.142585 CA_PREDIV_EN = 0
640 12:43:30.143010 PH8_DLY = 0
641 12:43:30.146054 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
642 12:43:30.149578 DQ_AAMCK_DIV = 4
643 12:43:30.152892 CA_AAMCK_DIV = 4
644 12:43:30.155872 CA_ADMCK_DIV = 4
645 12:43:30.159120 DQ_TRACK_CA_EN = 0
646 12:43:30.159592 CA_PICK = 800
647 12:43:30.162883 CA_MCKIO = 800
648 12:43:30.166104 MCKIO_SEMI = 0
649 12:43:30.169251 PLL_FREQ = 3068
650 12:43:30.172343 DQ_UI_PI_RATIO = 32
651 12:43:30.176201 CA_UI_PI_RATIO = 0
652 12:43:30.179505 ===================================
653 12:43:30.182729 ===================================
654 12:43:30.183167 memory_type:LPDDR4
655 12:43:30.186124 GP_NUM : 10
656 12:43:30.189442 SRAM_EN : 1
657 12:43:30.190017 MD32_EN : 0
658 12:43:30.193082 ===================================
659 12:43:30.196342 [ANA_INIT] >>>>>>>>>>>>>>
660 12:43:30.199875 <<<<<< [CONFIGURE PHASE]: ANA_TX
661 12:43:30.202932 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
662 12:43:30.206369 ===================================
663 12:43:30.209675 data_rate = 1600,PCW = 0X7600
664 12:43:30.213323 ===================================
665 12:43:30.216183 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
666 12:43:30.219654 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 12:43:30.226203 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
668 12:43:30.229256 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
669 12:43:30.233021 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
670 12:43:30.236695 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
671 12:43:30.240301 [ANA_INIT] flow start
672 12:43:30.240845 [ANA_INIT] PLL >>>>>>>>
673 12:43:30.244214 [ANA_INIT] PLL <<<<<<<<
674 12:43:30.247176 [ANA_INIT] MIDPI >>>>>>>>
675 12:43:30.247607 [ANA_INIT] MIDPI <<<<<<<<
676 12:43:30.250863 [ANA_INIT] DLL >>>>>>>>
677 12:43:30.254217 [ANA_INIT] flow end
678 12:43:30.257975 ============ LP4 DIFF to SE enter ============
679 12:43:30.262189 ============ LP4 DIFF to SE exit ============
680 12:43:30.262714 [ANA_INIT] <<<<<<<<<<<<<
681 12:43:30.265623 [Flow] Enable top DCM control >>>>>
682 12:43:30.269814 [Flow] Enable top DCM control <<<<<
683 12:43:30.273397 Enable DLL master slave shuffle
684 12:43:30.280172 ==============================================================
685 12:43:30.280693 Gating Mode config
686 12:43:30.287117 ==============================================================
687 12:43:30.287661 Config description:
688 12:43:30.298088 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
689 12:43:30.305273 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
690 12:43:30.309253 SELPH_MODE 0: By rank 1: By Phase
691 12:43:30.315808 ==============================================================
692 12:43:30.316608 GAT_TRACK_EN = 1
693 12:43:30.320353 RX_GATING_MODE = 2
694 12:43:30.323902 RX_GATING_TRACK_MODE = 2
695 12:43:30.327756 SELPH_MODE = 1
696 12:43:30.331222 PICG_EARLY_EN = 1
697 12:43:30.331773 VALID_LAT_VALUE = 1
698 12:43:30.338628 ==============================================================
699 12:43:30.342495 Enter into Gating configuration >>>>
700 12:43:30.346094 Exit from Gating configuration <<<<
701 12:43:30.349871 Enter into DVFS_PRE_config >>>>>
702 12:43:30.357341 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
703 12:43:30.360837 Exit from DVFS_PRE_config <<<<<
704 12:43:30.364295 Enter into PICG configuration >>>>
705 12:43:30.368281 Exit from PICG configuration <<<<
706 12:43:30.371665 [RX_INPUT] configuration >>>>>
707 12:43:30.375390 [RX_INPUT] configuration <<<<<
708 12:43:30.379153 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
709 12:43:30.382500 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
710 12:43:30.390196 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
711 12:43:30.397307 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
712 12:43:30.404948 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
713 12:43:30.408271 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
714 12:43:30.411961 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
715 12:43:30.415884 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
716 12:43:30.423243 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
717 12:43:30.427169 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
718 12:43:30.430509 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
719 12:43:30.434397 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
720 12:43:30.437868 ===================================
721 12:43:30.438371 LPDDR4 DRAM CONFIGURATION
722 12:43:30.442135 ===================================
723 12:43:30.445561 EX_ROW_EN[0] = 0x0
724 12:43:30.446072 EX_ROW_EN[1] = 0x0
725 12:43:30.449085 LP4Y_EN = 0x0
726 12:43:30.449596 WORK_FSP = 0x0
727 12:43:30.453032 WL = 0x2
728 12:43:30.453601 RL = 0x2
729 12:43:30.457017 BL = 0x2
730 12:43:30.457525 RPST = 0x0
731 12:43:30.460208 RD_PRE = 0x0
732 12:43:30.460714 WR_PRE = 0x1
733 12:43:30.463858 WR_PST = 0x0
734 12:43:30.464341 DBI_WR = 0x0
735 12:43:30.464745 DBI_RD = 0x0
736 12:43:30.467748 OTF = 0x1
737 12:43:30.471691 ===================================
738 12:43:30.475206 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
739 12:43:30.478933 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
740 12:43:30.482864 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
741 12:43:30.486537 ===================================
742 12:43:30.490127 LPDDR4 DRAM CONFIGURATION
743 12:43:30.493593 ===================================
744 12:43:30.494049 EX_ROW_EN[0] = 0x10
745 12:43:30.497537 EX_ROW_EN[1] = 0x0
746 12:43:30.498031 LP4Y_EN = 0x0
747 12:43:30.501103 WORK_FSP = 0x0
748 12:43:30.501582 WL = 0x2
749 12:43:30.504238 RL = 0x2
750 12:43:30.504723 BL = 0x2
751 12:43:30.508035 RPST = 0x0
752 12:43:30.508485 RD_PRE = 0x0
753 12:43:30.511480 WR_PRE = 0x1
754 12:43:30.511928 WR_PST = 0x0
755 12:43:30.515124 DBI_WR = 0x0
756 12:43:30.515570 DBI_RD = 0x0
757 12:43:30.518616 OTF = 0x1
758 12:43:30.519068 ===================================
759 12:43:30.525353 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
760 12:43:30.530962 nWR fixed to 40
761 12:43:30.534170 [ModeRegInit_LP4] CH0 RK0
762 12:43:30.534616 [ModeRegInit_LP4] CH0 RK1
763 12:43:30.538007 [ModeRegInit_LP4] CH1 RK0
764 12:43:30.538456 [ModeRegInit_LP4] CH1 RK1
765 12:43:30.541837 match AC timing 13
766 12:43:30.545548 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
767 12:43:30.549040 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
768 12:43:30.552948 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
769 12:43:30.560626 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
770 12:43:30.564082 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
771 12:43:30.564516 [EMI DOE] emi_dcm 0
772 12:43:30.568096 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
773 12:43:30.571437 ==
774 12:43:30.572002 Dram Type= 6, Freq= 0, CH_0, rank 0
775 12:43:30.578910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
776 12:43:30.579413 ==
777 12:43:30.582391 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
778 12:43:30.589818 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
779 12:43:30.597578 [CA 0] Center 38 (7~69) winsize 63
780 12:43:30.600852 [CA 1] Center 37 (7~68) winsize 62
781 12:43:30.604410 [CA 2] Center 35 (5~66) winsize 62
782 12:43:30.607490 [CA 3] Center 35 (5~66) winsize 62
783 12:43:30.611079 [CA 4] Center 34 (4~65) winsize 62
784 12:43:30.614488 [CA 5] Center 34 (4~65) winsize 62
785 12:43:30.614917
786 12:43:30.617902 [CmdBusTrainingLP45] Vref(ca) range 1: 32
787 12:43:30.618333
788 12:43:30.620767 [CATrainingPosCal] consider 1 rank data
789 12:43:30.624412 u2DelayCellTimex100 = 270/100 ps
790 12:43:30.627575 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
791 12:43:30.631012 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
792 12:43:30.637515 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
793 12:43:30.640799 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
794 12:43:30.644099 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
795 12:43:30.647632 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
796 12:43:30.648064
797 12:43:30.650953 CA PerBit enable=1, Macro0, CA PI delay=34
798 12:43:30.651386
799 12:43:30.654376 [CBTSetCACLKResult] CA Dly = 34
800 12:43:30.654808 CS Dly: 5 (0~36)
801 12:43:30.657558 ==
802 12:43:30.657994 Dram Type= 6, Freq= 0, CH_0, rank 1
803 12:43:30.664412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 12:43:30.664847 ==
805 12:43:30.667520 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
806 12:43:30.674185 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
807 12:43:30.684204 [CA 0] Center 38 (7~69) winsize 63
808 12:43:30.687251 [CA 1] Center 38 (7~69) winsize 63
809 12:43:30.690562 [CA 2] Center 35 (5~66) winsize 62
810 12:43:30.693796 [CA 3] Center 35 (5~66) winsize 62
811 12:43:30.697461 [CA 4] Center 34 (4~65) winsize 62
812 12:43:30.700694 [CA 5] Center 34 (4~65) winsize 62
813 12:43:30.701140
814 12:43:30.704100 [CmdBusTrainingLP45] Vref(ca) range 1: 32
815 12:43:30.704546
816 12:43:30.707530 [CATrainingPosCal] consider 2 rank data
817 12:43:30.710623 u2DelayCellTimex100 = 270/100 ps
818 12:43:30.714211 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
819 12:43:30.717346 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
820 12:43:30.724023 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
821 12:43:30.727582 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
822 12:43:30.730904 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
823 12:43:30.734432 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
824 12:43:30.735077
825 12:43:30.737833 CA PerBit enable=1, Macro0, CA PI delay=34
826 12:43:30.738366
827 12:43:30.741218 [CBTSetCACLKResult] CA Dly = 34
828 12:43:30.741890 CS Dly: 5 (0~37)
829 12:43:30.742386
830 12:43:30.744234 ----->DramcWriteLeveling(PI) begin...
831 12:43:30.744727 ==
832 12:43:30.747824 Dram Type= 6, Freq= 0, CH_0, rank 0
833 12:43:30.754423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
834 12:43:30.754858 ==
835 12:43:30.757548 Write leveling (Byte 0): 31 => 31
836 12:43:30.760986 Write leveling (Byte 1): 31 => 31
837 12:43:30.761581 DramcWriteLeveling(PI) end<-----
838 12:43:30.762038
839 12:43:30.764200 ==
840 12:43:30.767694 Dram Type= 6, Freq= 0, CH_0, rank 0
841 12:43:30.771057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
842 12:43:30.771656 ==
843 12:43:30.774602 [Gating] SW mode calibration
844 12:43:30.780990 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
845 12:43:30.784683 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
846 12:43:30.791100 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
847 12:43:30.794645 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
848 12:43:30.797812 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
849 12:43:30.804562 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
850 12:43:30.807784 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 12:43:30.811360 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 12:43:30.814637 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 12:43:30.821796 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 12:43:30.824997 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 12:43:30.828783 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 12:43:30.832569 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 12:43:30.839367 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 12:43:30.842929 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:43:30.846218 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:43:30.853910 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:43:30.857017 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 12:43:30.860491 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 12:43:30.863693 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 12:43:30.870450 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
865 12:43:30.873832 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
866 12:43:30.877259 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 12:43:30.883763 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 12:43:30.887044 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 12:43:30.890602 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 12:43:30.893645 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 12:43:30.900267 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 12:43:30.903609 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 12:43:30.906691 0 9 12 | B1->B0 | 2828 3333 | 0 0 | (0 0) (0 0)
874 12:43:30.913351 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 12:43:30.917021 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 12:43:30.920255 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 12:43:30.926824 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 12:43:30.930057 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 12:43:30.933469 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 12:43:30.940147 0 10 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
881 12:43:30.943603 0 10 12 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
882 12:43:30.946942 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 12:43:30.953284 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 12:43:30.956853 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 12:43:30.959962 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 12:43:30.966805 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 12:43:30.970026 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 12:43:30.973148 0 11 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
889 12:43:30.980087 0 11 12 | B1->B0 | 3636 3f3f | 0 0 | (0 0) (0 0)
890 12:43:30.983426 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 12:43:30.986571 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 12:43:30.993457 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 12:43:30.996676 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 12:43:31.000072 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 12:43:31.003718 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 12:43:31.010268 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
897 12:43:31.013695 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
898 12:43:31.016879 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 12:43:31.023346 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 12:43:31.027075 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 12:43:31.030149 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 12:43:31.036695 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 12:43:31.040134 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 12:43:31.043528 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 12:43:31.050378 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 12:43:31.053581 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 12:43:31.056619 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 12:43:31.063674 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 12:43:31.066694 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 12:43:31.070151 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 12:43:31.076928 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 12:43:31.080004 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
913 12:43:31.083603 Total UI for P1: 0, mck2ui 16
914 12:43:31.086694 best dqsien dly found for B0: ( 0, 14, 6)
915 12:43:31.089987 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
916 12:43:31.093274 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
917 12:43:31.096591 Total UI for P1: 0, mck2ui 16
918 12:43:31.099920 best dqsien dly found for B1: ( 0, 14, 12)
919 12:43:31.106608 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
920 12:43:31.110223 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
921 12:43:31.110646
922 12:43:31.113287 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
923 12:43:31.116734 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
924 12:43:31.120543 [Gating] SW calibration Done
925 12:43:31.120964 ==
926 12:43:31.123394 Dram Type= 6, Freq= 0, CH_0, rank 0
927 12:43:31.127052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 12:43:31.127480 ==
929 12:43:31.130233 RX Vref Scan: 0
930 12:43:31.130692
931 12:43:31.131028 RX Vref 0 -> 0, step: 1
932 12:43:31.131343
933 12:43:31.133427 RX Delay -130 -> 252, step: 16
934 12:43:31.136516 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
935 12:43:31.143193 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
936 12:43:31.146474 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
937 12:43:31.150135 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
938 12:43:31.153265 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
939 12:43:31.156768 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
940 12:43:31.160108 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
941 12:43:31.166753 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
942 12:43:31.169898 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
943 12:43:31.173429 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
944 12:43:31.176724 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
945 12:43:31.180045 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
946 12:43:31.186863 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
947 12:43:31.189958 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
948 12:43:31.193580 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
949 12:43:31.196682 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
950 12:43:31.197106 ==
951 12:43:31.200153 Dram Type= 6, Freq= 0, CH_0, rank 0
952 12:43:31.206809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
953 12:43:31.207237 ==
954 12:43:31.207575 DQS Delay:
955 12:43:31.207885 DQS0 = 0, DQS1 = 0
956 12:43:31.210125 DQM Delay:
957 12:43:31.210547 DQM0 = 80, DQM1 = 70
958 12:43:31.213640 DQ Delay:
959 12:43:31.216746 DQ0 =77, DQ1 =77, DQ2 =77, DQ3 =77
960 12:43:31.220146 DQ4 =77, DQ5 =69, DQ6 =93, DQ7 =93
961 12:43:31.223332 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
962 12:43:31.226920 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
963 12:43:31.227407
964 12:43:31.227840
965 12:43:31.228167 ==
966 12:43:31.230962 Dram Type= 6, Freq= 0, CH_0, rank 0
967 12:43:31.234069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 12:43:31.234543 ==
969 12:43:31.234907
970 12:43:31.235241
971 12:43:31.237358 TX Vref Scan disable
972 12:43:31.237798 == TX Byte 0 ==
973 12:43:31.240805 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
974 12:43:31.247507 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
975 12:43:31.247951 == TX Byte 1 ==
976 12:43:31.250740 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
977 12:43:31.257295 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
978 12:43:31.257897 ==
979 12:43:31.260572 Dram Type= 6, Freq= 0, CH_0, rank 0
980 12:43:31.263713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
981 12:43:31.264153 ==
982 12:43:31.276907 TX Vref=22, minBit 5, minWin=26, winSum=433
983 12:43:31.280410 TX Vref=24, minBit 0, minWin=27, winSum=439
984 12:43:31.283904 TX Vref=26, minBit 14, minWin=26, winSum=438
985 12:43:31.286863 TX Vref=28, minBit 0, minWin=27, winSum=442
986 12:43:31.290197 TX Vref=30, minBit 2, minWin=27, winSum=440
987 12:43:31.297107 TX Vref=32, minBit 12, minWin=26, winSum=439
988 12:43:31.300461 [TxChooseVref] Worse bit 0, Min win 27, Win sum 442, Final Vref 28
989 12:43:31.301008
990 12:43:31.303895 Final TX Range 1 Vref 28
991 12:43:31.304440
992 12:43:31.304809 ==
993 12:43:31.307174 Dram Type= 6, Freq= 0, CH_0, rank 0
994 12:43:31.310457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
995 12:43:31.311019 ==
996 12:43:31.313792
997 12:43:31.314231
998 12:43:31.314589 TX Vref Scan disable
999 12:43:31.317140 == TX Byte 0 ==
1000 12:43:31.320691 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1001 12:43:31.327072 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1002 12:43:31.327526 == TX Byte 1 ==
1003 12:43:31.330662 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1004 12:43:31.333871 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1005 12:43:31.334341
1006 12:43:31.337272 [DATLAT]
1007 12:43:31.337816 Freq=800, CH0 RK0
1008 12:43:31.338186
1009 12:43:31.340874 DATLAT Default: 0xa
1010 12:43:31.341505 0, 0xFFFF, sum = 0
1011 12:43:31.343962 1, 0xFFFF, sum = 0
1012 12:43:31.344435 2, 0xFFFF, sum = 0
1013 12:43:31.347321 3, 0xFFFF, sum = 0
1014 12:43:31.347886 4, 0xFFFF, sum = 0
1015 12:43:31.350871 5, 0xFFFF, sum = 0
1016 12:43:31.351450 6, 0xFFFF, sum = 0
1017 12:43:31.353952 7, 0xFFFF, sum = 0
1018 12:43:31.354387 8, 0xFFFF, sum = 0
1019 12:43:31.357386 9, 0x0, sum = 1
1020 12:43:31.357862 10, 0x0, sum = 2
1021 12:43:31.360615 11, 0x0, sum = 3
1022 12:43:31.361084 12, 0x0, sum = 4
1023 12:43:31.363910 best_step = 10
1024 12:43:31.364333
1025 12:43:31.364693 ==
1026 12:43:31.367272 Dram Type= 6, Freq= 0, CH_0, rank 0
1027 12:43:31.370430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1028 12:43:31.370847 ==
1029 12:43:31.374094 RX Vref Scan: 1
1030 12:43:31.374560
1031 12:43:31.375179 Set Vref Range= 32 -> 127
1032 12:43:31.375819
1033 12:43:31.377276 RX Vref 32 -> 127, step: 1
1034 12:43:31.377787
1035 12:43:31.380706 RX Delay -111 -> 252, step: 8
1036 12:43:31.381140
1037 12:43:31.383859 Set Vref, RX VrefLevel [Byte0]: 32
1038 12:43:31.387401 [Byte1]: 32
1039 12:43:31.387821
1040 12:43:31.390727 Set Vref, RX VrefLevel [Byte0]: 33
1041 12:43:31.393977 [Byte1]: 33
1042 12:43:31.397776
1043 12:43:31.398192 Set Vref, RX VrefLevel [Byte0]: 34
1044 12:43:31.401146 [Byte1]: 34
1045 12:43:31.405510
1046 12:43:31.405941 Set Vref, RX VrefLevel [Byte0]: 35
1047 12:43:31.408688 [Byte1]: 35
1048 12:43:31.413067
1049 12:43:31.413512 Set Vref, RX VrefLevel [Byte0]: 36
1050 12:43:31.416398 [Byte1]: 36
1051 12:43:31.420632
1052 12:43:31.421247 Set Vref, RX VrefLevel [Byte0]: 37
1053 12:43:31.424008 [Byte1]: 37
1054 12:43:31.428159
1055 12:43:31.428579 Set Vref, RX VrefLevel [Byte0]: 38
1056 12:43:31.431898 [Byte1]: 38
1057 12:43:31.436053
1058 12:43:31.436470 Set Vref, RX VrefLevel [Byte0]: 39
1059 12:43:31.439060 [Byte1]: 39
1060 12:43:31.443592
1061 12:43:31.444131 Set Vref, RX VrefLevel [Byte0]: 40
1062 12:43:31.446830 [Byte1]: 40
1063 12:43:31.451036
1064 12:43:31.451455 Set Vref, RX VrefLevel [Byte0]: 41
1065 12:43:31.454549 [Byte1]: 41
1066 12:43:31.458706
1067 12:43:31.459149 Set Vref, RX VrefLevel [Byte0]: 42
1068 12:43:31.462192 [Byte1]: 42
1069 12:43:31.466425
1070 12:43:31.466840 Set Vref, RX VrefLevel [Byte0]: 43
1071 12:43:31.469963 [Byte1]: 43
1072 12:43:31.474084
1073 12:43:31.474534 Set Vref, RX VrefLevel [Byte0]: 44
1074 12:43:31.477622 [Byte1]: 44
1075 12:43:31.481762
1076 12:43:31.482232 Set Vref, RX VrefLevel [Byte0]: 45
1077 12:43:31.485380 [Byte1]: 45
1078 12:43:31.489953
1079 12:43:31.490382 Set Vref, RX VrefLevel [Byte0]: 46
1080 12:43:31.493002 [Byte1]: 46
1081 12:43:31.497748
1082 12:43:31.498182 Set Vref, RX VrefLevel [Byte0]: 47
1083 12:43:31.501029 [Byte1]: 47
1084 12:43:31.504911
1085 12:43:31.505334 Set Vref, RX VrefLevel [Byte0]: 48
1086 12:43:31.508767 [Byte1]: 48
1087 12:43:31.512226
1088 12:43:31.512709 Set Vref, RX VrefLevel [Byte0]: 49
1089 12:43:31.515607 [Byte1]: 49
1090 12:43:31.520234
1091 12:43:31.520658 Set Vref, RX VrefLevel [Byte0]: 50
1092 12:43:31.523762 [Byte1]: 50
1093 12:43:31.527566
1094 12:43:31.528121 Set Vref, RX VrefLevel [Byte0]: 51
1095 12:43:31.530825 [Byte1]: 51
1096 12:43:31.535368
1097 12:43:31.535794 Set Vref, RX VrefLevel [Byte0]: 52
1098 12:43:31.538820 [Byte1]: 52
1099 12:43:31.543165
1100 12:43:31.543699 Set Vref, RX VrefLevel [Byte0]: 53
1101 12:43:31.546048 [Byte1]: 53
1102 12:43:31.550572
1103 12:43:31.551001 Set Vref, RX VrefLevel [Byte0]: 54
1104 12:43:31.553953 [Byte1]: 54
1105 12:43:31.558134
1106 12:43:31.558559 Set Vref, RX VrefLevel [Byte0]: 55
1107 12:43:31.561750 [Byte1]: 55
1108 12:43:31.566147
1109 12:43:31.566572 Set Vref, RX VrefLevel [Byte0]: 56
1110 12:43:31.569017 [Byte1]: 56
1111 12:43:31.573727
1112 12:43:31.574153 Set Vref, RX VrefLevel [Byte0]: 57
1113 12:43:31.576929 [Byte1]: 57
1114 12:43:31.580939
1115 12:43:31.581367 Set Vref, RX VrefLevel [Byte0]: 58
1116 12:43:31.584356 [Byte1]: 58
1117 12:43:31.588808
1118 12:43:31.589233 Set Vref, RX VrefLevel [Byte0]: 59
1119 12:43:31.591938 [Byte1]: 59
1120 12:43:31.596667
1121 12:43:31.597201 Set Vref, RX VrefLevel [Byte0]: 60
1122 12:43:31.600111 [Byte1]: 60
1123 12:43:31.604193
1124 12:43:31.604620 Set Vref, RX VrefLevel [Byte0]: 61
1125 12:43:31.607539 [Byte1]: 61
1126 12:43:31.611638
1127 12:43:31.612063 Set Vref, RX VrefLevel [Byte0]: 62
1128 12:43:31.615193 [Byte1]: 62
1129 12:43:31.619367
1130 12:43:31.619793 Set Vref, RX VrefLevel [Byte0]: 63
1131 12:43:31.622854 [Byte1]: 63
1132 12:43:31.626903
1133 12:43:31.627326 Set Vref, RX VrefLevel [Byte0]: 64
1134 12:43:31.630359 [Byte1]: 64
1135 12:43:31.634735
1136 12:43:31.635163 Set Vref, RX VrefLevel [Byte0]: 65
1137 12:43:31.637927 [Byte1]: 65
1138 12:43:31.642276
1139 12:43:31.642701 Set Vref, RX VrefLevel [Byte0]: 66
1140 12:43:31.645612 [Byte1]: 66
1141 12:43:31.649722
1142 12:43:31.650146 Set Vref, RX VrefLevel [Byte0]: 67
1143 12:43:31.653023 [Byte1]: 67
1144 12:43:31.657396
1145 12:43:31.657917 Set Vref, RX VrefLevel [Byte0]: 68
1146 12:43:31.660934 [Byte1]: 68
1147 12:43:31.665284
1148 12:43:31.665746 Set Vref, RX VrefLevel [Byte0]: 69
1149 12:43:31.668661 [Byte1]: 69
1150 12:43:31.672773
1151 12:43:31.673222 Set Vref, RX VrefLevel [Byte0]: 70
1152 12:43:31.676287 [Byte1]: 70
1153 12:43:31.680533
1154 12:43:31.680983 Set Vref, RX VrefLevel [Byte0]: 71
1155 12:43:31.683795 [Byte1]: 71
1156 12:43:31.687946
1157 12:43:31.688392 Set Vref, RX VrefLevel [Byte0]: 72
1158 12:43:31.691333 [Byte1]: 72
1159 12:43:31.695614
1160 12:43:31.696063 Set Vref, RX VrefLevel [Byte0]: 73
1161 12:43:31.698886 [Byte1]: 73
1162 12:43:31.703161
1163 12:43:31.703585 Set Vref, RX VrefLevel [Byte0]: 74
1164 12:43:31.706665 [Byte1]: 74
1165 12:43:31.710873
1166 12:43:31.711296 Set Vref, RX VrefLevel [Byte0]: 75
1167 12:43:31.714335 [Byte1]: 75
1168 12:43:31.718626
1169 12:43:31.719054 Set Vref, RX VrefLevel [Byte0]: 76
1170 12:43:31.722142 [Byte1]: 76
1171 12:43:31.726611
1172 12:43:31.727036 Set Vref, RX VrefLevel [Byte0]: 77
1173 12:43:31.729664 [Byte1]: 77
1174 12:43:31.734077
1175 12:43:31.734500 Set Vref, RX VrefLevel [Byte0]: 78
1176 12:43:31.737259 [Byte1]: 78
1177 12:43:31.741584
1178 12:43:31.742010 Set Vref, RX VrefLevel [Byte0]: 79
1179 12:43:31.744970 [Byte1]: 79
1180 12:43:31.749131
1181 12:43:31.749607 Set Vref, RX VrefLevel [Byte0]: 80
1182 12:43:31.752560 [Byte1]: 80
1183 12:43:31.756823
1184 12:43:31.757293 Final RX Vref Byte 0 = 59 to rank0
1185 12:43:31.760170 Final RX Vref Byte 1 = 62 to rank0
1186 12:43:31.763522 Final RX Vref Byte 0 = 59 to rank1
1187 12:43:31.766987 Final RX Vref Byte 1 = 62 to rank1==
1188 12:43:31.770141 Dram Type= 6, Freq= 0, CH_0, rank 0
1189 12:43:31.776764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1190 12:43:31.777252 ==
1191 12:43:31.777836 DQS Delay:
1192 12:43:31.778184 DQS0 = 0, DQS1 = 0
1193 12:43:31.780028 DQM Delay:
1194 12:43:31.780451 DQM0 = 82, DQM1 = 68
1195 12:43:31.783478 DQ Delay:
1196 12:43:31.786941 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1197 12:43:31.787368 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1198 12:43:31.789972 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1199 12:43:31.796604 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1200 12:43:31.797029
1201 12:43:31.797365
1202 12:43:31.803568 [DQSOSCAuto] RK0, (LSB)MR18= 0x2523, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1203 12:43:31.806692 CH0 RK0: MR19=606, MR18=2523
1204 12:43:31.813435 CH0_RK0: MR19=0x606, MR18=0x2523, DQSOSC=400, MR23=63, INC=92, DEC=61
1205 12:43:31.813932
1206 12:43:31.816814 ----->DramcWriteLeveling(PI) begin...
1207 12:43:31.817248 ==
1208 12:43:31.820099 Dram Type= 6, Freq= 0, CH_0, rank 1
1209 12:43:31.823549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1210 12:43:31.823978 ==
1211 12:43:31.826829 Write leveling (Byte 0): 32 => 32
1212 12:43:31.830379 Write leveling (Byte 1): 29 => 29
1213 12:43:31.833520 DramcWriteLeveling(PI) end<-----
1214 12:43:31.833946
1215 12:43:31.834279 ==
1216 12:43:31.836834 Dram Type= 6, Freq= 0, CH_0, rank 1
1217 12:43:31.840172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1218 12:43:31.840603 ==
1219 12:43:31.843528 [Gating] SW mode calibration
1220 12:43:31.850045 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1221 12:43:31.856579 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1222 12:43:31.860123 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1223 12:43:31.863221 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1224 12:43:31.869950 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1225 12:43:31.873526 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 12:43:31.876972 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 12:43:31.883351 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 12:43:31.886508 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 12:43:31.889803 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 12:43:31.896718 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 12:43:31.900182 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 12:43:31.903411 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 12:43:31.947442 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 12:43:31.947877 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 12:43:31.948561 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 12:43:31.948912 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 12:43:31.949228 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 12:43:31.949550 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 12:43:31.949849 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1240 12:43:31.950136 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1241 12:43:31.950423 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 12:43:31.950772 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 12:43:31.991781 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 12:43:31.992235 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 12:43:31.992576 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 12:43:31.992889 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 12:43:31.993189 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 12:43:31.993848 0 9 8 | B1->B0 | 2525 2e2e | 1 1 | (0 0) (0 0)
1249 12:43:31.994181 0 9 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1250 12:43:31.994480 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 12:43:31.994773 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 12:43:31.995059 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 12:43:31.997672 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 12:43:32.000961 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1255 12:43:32.004093 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1256 12:43:32.010897 0 10 8 | B1->B0 | 2f2f 2626 | 1 0 | (1 0) (0 0)
1257 12:43:32.014114 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 12:43:32.017315 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 12:43:32.024060 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 12:43:32.027253 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 12:43:32.030604 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 12:43:32.037334 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 12:43:32.040947 0 11 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
1264 12:43:32.044073 0 11 8 | B1->B0 | 2e2e 3f3f | 0 0 | (0 0) (0 0)
1265 12:43:32.050792 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1266 12:43:32.053910 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 12:43:32.057321 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 12:43:32.064009 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 12:43:32.067687 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 12:43:32.071662 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 12:43:32.075403 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1272 12:43:32.078869 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1273 12:43:32.085680 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 12:43:32.089187 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 12:43:32.093459 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 12:43:32.096735 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 12:43:32.103214 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 12:43:32.106564 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 12:43:32.109771 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 12:43:32.116669 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 12:43:32.119825 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 12:43:32.123275 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 12:43:32.129919 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 12:43:32.133253 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 12:43:32.136478 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 12:43:32.143078 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 12:43:32.146573 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 12:43:32.149739 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1289 12:43:32.153221 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1290 12:43:32.156584 Total UI for P1: 0, mck2ui 16
1291 12:43:32.159953 best dqsien dly found for B0: ( 0, 14, 8)
1292 12:43:32.162956 Total UI for P1: 0, mck2ui 16
1293 12:43:32.166602 best dqsien dly found for B1: ( 0, 14, 8)
1294 12:43:32.169695 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1295 12:43:32.173282 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1296 12:43:32.176362
1297 12:43:32.179805 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1298 12:43:32.182969 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1299 12:43:32.186457 [Gating] SW calibration Done
1300 12:43:32.186885 ==
1301 12:43:32.189889 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 12:43:32.193211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 12:43:32.193682 ==
1304 12:43:32.194025 RX Vref Scan: 0
1305 12:43:32.194343
1306 12:43:32.196306 RX Vref 0 -> 0, step: 1
1307 12:43:32.196731
1308 12:43:32.199727 RX Delay -130 -> 252, step: 16
1309 12:43:32.202869 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1310 12:43:32.206244 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1311 12:43:32.212893 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1312 12:43:32.216385 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1313 12:43:32.219839 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1314 12:43:32.223223 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1315 12:43:32.226336 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1316 12:43:32.229950 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1317 12:43:32.236689 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1318 12:43:32.239770 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1319 12:43:32.243147 iDelay=222, Bit 10, Center 61 (-66 ~ 189) 256
1320 12:43:32.246360 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1321 12:43:32.249952 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1322 12:43:32.256551 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1323 12:43:32.259962 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1324 12:43:32.263252 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1325 12:43:32.263679 ==
1326 12:43:32.266313 Dram Type= 6, Freq= 0, CH_0, rank 1
1327 12:43:32.269793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1328 12:43:32.273065 ==
1329 12:43:32.273635 DQS Delay:
1330 12:43:32.273994 DQS0 = 0, DQS1 = 0
1331 12:43:32.276486 DQM Delay:
1332 12:43:32.276909 DQM0 = 76, DQM1 = 68
1333 12:43:32.279716 DQ Delay:
1334 12:43:32.280275 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1335 12:43:32.283067 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =93
1336 12:43:32.286230 DQ8 =61, DQ9 =53, DQ10 =61, DQ11 =61
1337 12:43:32.289960 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1338 12:43:32.290472
1339 12:43:32.293049
1340 12:43:32.293614 ==
1341 12:43:32.296709 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 12:43:32.299698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 12:43:32.300168 ==
1344 12:43:32.300606
1345 12:43:32.301050
1346 12:43:32.302843 TX Vref Scan disable
1347 12:43:32.303427 == TX Byte 0 ==
1348 12:43:32.309768 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1349 12:43:32.313083 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1350 12:43:32.313541 == TX Byte 1 ==
1351 12:43:32.319605 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1352 12:43:32.323031 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1353 12:43:32.323458 ==
1354 12:43:32.326635 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 12:43:32.329578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 12:43:32.330004 ==
1357 12:43:32.343161 TX Vref=22, minBit 11, minWin=26, winSum=436
1358 12:43:32.346665 TX Vref=24, minBit 1, minWin=27, winSum=439
1359 12:43:32.350076 TX Vref=26, minBit 1, minWin=27, winSum=441
1360 12:43:32.353717 TX Vref=28, minBit 1, minWin=27, winSum=441
1361 12:43:32.356780 TX Vref=30, minBit 1, minWin=27, winSum=445
1362 12:43:32.360103 TX Vref=32, minBit 9, minWin=27, winSum=445
1363 12:43:32.366661 [TxChooseVref] Worse bit 1, Min win 27, Win sum 445, Final Vref 30
1364 12:43:32.367086
1365 12:43:32.369941 Final TX Range 1 Vref 30
1366 12:43:32.370367
1367 12:43:32.370703 ==
1368 12:43:32.373536 Dram Type= 6, Freq= 0, CH_0, rank 1
1369 12:43:32.376466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1370 12:43:32.376770 ==
1371 12:43:32.377003
1372 12:43:32.379875
1373 12:43:32.380200 TX Vref Scan disable
1374 12:43:32.383106 == TX Byte 0 ==
1375 12:43:32.386616 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1376 12:43:32.393349 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1377 12:43:32.393734 == TX Byte 1 ==
1378 12:43:32.396387 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1379 12:43:32.403089 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1380 12:43:32.403463
1381 12:43:32.403813 [DATLAT]
1382 12:43:32.404155 Freq=800, CH0 RK1
1383 12:43:32.404479
1384 12:43:32.406506 DATLAT Default: 0xa
1385 12:43:32.406760 0, 0xFFFF, sum = 0
1386 12:43:32.409897 1, 0xFFFF, sum = 0
1387 12:43:32.410175 2, 0xFFFF, sum = 0
1388 12:43:32.413076 3, 0xFFFF, sum = 0
1389 12:43:32.413330 4, 0xFFFF, sum = 0
1390 12:43:32.416310 5, 0xFFFF, sum = 0
1391 12:43:32.419836 6, 0xFFFF, sum = 0
1392 12:43:32.420232 7, 0xFFFF, sum = 0
1393 12:43:32.423124 8, 0xFFFF, sum = 0
1394 12:43:32.423627 9, 0x0, sum = 1
1395 12:43:32.423955 10, 0x0, sum = 2
1396 12:43:32.426603 11, 0x0, sum = 3
1397 12:43:32.427098 12, 0x0, sum = 4
1398 12:43:32.429988 best_step = 10
1399 12:43:32.430393
1400 12:43:32.430721 ==
1401 12:43:32.432996 Dram Type= 6, Freq= 0, CH_0, rank 1
1402 12:43:32.436317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1403 12:43:32.436721 ==
1404 12:43:32.439599 RX Vref Scan: 0
1405 12:43:32.439993
1406 12:43:32.440311 RX Vref 0 -> 0, step: 1
1407 12:43:32.440596
1408 12:43:32.442934 RX Delay -111 -> 252, step: 8
1409 12:43:32.449980 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1410 12:43:32.453405 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1411 12:43:32.456791 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1412 12:43:32.459937 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1413 12:43:32.463228 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1414 12:43:32.470019 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1415 12:43:32.473352 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1416 12:43:32.476617 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1417 12:43:32.479995 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1418 12:43:32.483432 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1419 12:43:32.490239 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1420 12:43:32.493266 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1421 12:43:32.496865 iDelay=209, Bit 12, Center 72 (-47 ~ 192) 240
1422 12:43:32.500084 iDelay=209, Bit 13, Center 72 (-47 ~ 192) 240
1423 12:43:32.503580 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1424 12:43:32.510110 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1425 12:43:32.510575 ==
1426 12:43:32.513823 Dram Type= 6, Freq= 0, CH_0, rank 1
1427 12:43:32.517099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1428 12:43:32.517835 ==
1429 12:43:32.518210 DQS Delay:
1430 12:43:32.520057 DQS0 = 0, DQS1 = 0
1431 12:43:32.520503 DQM Delay:
1432 12:43:32.523777 DQM0 = 78, DQM1 = 70
1433 12:43:32.524294 DQ Delay:
1434 12:43:32.527220 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1435 12:43:32.530190 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =88
1436 12:43:32.533889 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1437 12:43:32.537381 DQ12 =72, DQ13 =72, DQ14 =80, DQ15 =80
1438 12:43:32.537969
1439 12:43:32.538310
1440 12:43:32.543510 [DQSOSCAuto] RK1, (LSB)MR18= 0x4d28, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
1441 12:43:32.547002 CH0 RK1: MR19=606, MR18=4D28
1442 12:43:32.553361 CH0_RK1: MR19=0x606, MR18=0x4D28, DQSOSC=390, MR23=63, INC=97, DEC=64
1443 12:43:32.556685 [RxdqsGatingPostProcess] freq 800
1444 12:43:32.563450 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1445 12:43:32.566872 Pre-setting of DQS Precalculation
1446 12:43:32.570177 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1447 12:43:32.570599 ==
1448 12:43:32.573564 Dram Type= 6, Freq= 0, CH_1, rank 0
1449 12:43:32.576650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1450 12:43:32.577113 ==
1451 12:43:32.583529 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1452 12:43:32.589910 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1453 12:43:32.598476 [CA 0] Center 36 (6~66) winsize 61
1454 12:43:32.601769 [CA 1] Center 36 (6~67) winsize 62
1455 12:43:32.605342 [CA 2] Center 34 (4~64) winsize 61
1456 12:43:32.608589 [CA 3] Center 34 (4~64) winsize 61
1457 12:43:32.611942 [CA 4] Center 35 (5~65) winsize 61
1458 12:43:32.615103 [CA 5] Center 34 (4~64) winsize 61
1459 12:43:32.615546
1460 12:43:32.618483 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1461 12:43:32.618911
1462 12:43:32.621876 [CATrainingPosCal] consider 1 rank data
1463 12:43:32.625175 u2DelayCellTimex100 = 270/100 ps
1464 12:43:32.628695 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1465 12:43:32.631755 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1466 12:43:32.638368 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1467 12:43:32.641592 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1468 12:43:32.645110 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1469 12:43:32.648313 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1470 12:43:32.648862
1471 12:43:32.652031 CA PerBit enable=1, Macro0, CA PI delay=34
1472 12:43:32.652540
1473 12:43:32.655204 [CBTSetCACLKResult] CA Dly = 34
1474 12:43:32.655650 CS Dly: 5 (0~36)
1475 12:43:32.656084 ==
1476 12:43:32.658372 Dram Type= 6, Freq= 0, CH_1, rank 1
1477 12:43:32.665016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1478 12:43:32.665607 ==
1479 12:43:32.668278 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1480 12:43:32.674882 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1481 12:43:32.684569 [CA 0] Center 36 (7~66) winsize 60
1482 12:43:32.687847 [CA 1] Center 36 (6~67) winsize 62
1483 12:43:32.691395 [CA 2] Center 34 (4~65) winsize 62
1484 12:43:32.694682 [CA 3] Center 33 (3~64) winsize 62
1485 12:43:32.698007 [CA 4] Center 34 (4~65) winsize 62
1486 12:43:32.701128 [CA 5] Center 33 (3~64) winsize 62
1487 12:43:32.701720
1488 12:43:32.704635 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1489 12:43:32.705232
1490 12:43:32.707900 [CATrainingPosCal] consider 2 rank data
1491 12:43:32.711348 u2DelayCellTimex100 = 270/100 ps
1492 12:43:32.714816 CA0 delay=36 (7~66),Diff = 2 PI (14 cell)
1493 12:43:32.717897 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1494 12:43:32.724942 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1495 12:43:32.728579 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1496 12:43:32.731855 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1497 12:43:32.735503 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1498 12:43:32.736068
1499 12:43:32.739159 CA PerBit enable=1, Macro0, CA PI delay=34
1500 12:43:32.739753
1501 12:43:32.740246 [CBTSetCACLKResult] CA Dly = 34
1502 12:43:32.743239 CS Dly: 6 (0~38)
1503 12:43:32.743859
1504 12:43:32.746872 ----->DramcWriteLeveling(PI) begin...
1505 12:43:32.747457 ==
1506 12:43:32.750148 Dram Type= 6, Freq= 0, CH_1, rank 0
1507 12:43:32.753884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1508 12:43:32.754329 ==
1509 12:43:32.757309 Write leveling (Byte 0): 29 => 29
1510 12:43:32.760890 Write leveling (Byte 1): 29 => 29
1511 12:43:32.764190 DramcWriteLeveling(PI) end<-----
1512 12:43:32.764764
1513 12:43:32.765138 ==
1514 12:43:32.767539 Dram Type= 6, Freq= 0, CH_1, rank 0
1515 12:43:32.770945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1516 12:43:32.771513 ==
1517 12:43:32.774321 [Gating] SW mode calibration
1518 12:43:32.780778 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1519 12:43:32.787730 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1520 12:43:32.790837 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1521 12:43:32.794283 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1522 12:43:32.800826 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1523 12:43:32.804109 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 12:43:32.807327 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 12:43:32.810660 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 12:43:32.817354 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 12:43:32.820721 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 12:43:32.823898 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 12:43:32.830779 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 12:43:32.834032 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 12:43:32.837263 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 12:43:32.843726 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 12:43:32.847120 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 12:43:32.850632 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 12:43:32.857401 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 12:43:32.860484 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 12:43:32.863874 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1538 12:43:32.870611 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1539 12:43:32.873851 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 12:43:32.877259 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 12:43:32.883671 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 12:43:32.886944 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 12:43:32.890344 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 12:43:32.896993 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 12:43:32.900456 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 12:43:32.903845 0 9 8 | B1->B0 | 2828 2929 | 1 0 | (1 1) (0 0)
1547 12:43:32.910355 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 12:43:32.913682 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 12:43:32.917052 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 12:43:32.920409 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 12:43:32.927264 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 12:43:32.930525 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1553 12:43:32.933893 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1554 12:43:32.940584 0 10 8 | B1->B0 | 2d2d 2b2b | 1 1 | (1 0) (1 0)
1555 12:43:32.943711 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 12:43:32.947195 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 12:43:32.953648 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 12:43:32.957071 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 12:43:32.960439 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 12:43:32.966965 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 12:43:32.970427 0 11 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1562 12:43:32.973897 0 11 8 | B1->B0 | 3737 3838 | 0 0 | (0 0) (0 0)
1563 12:43:32.980271 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 12:43:32.984072 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 12:43:32.987350 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 12:43:32.994019 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 12:43:32.996842 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 12:43:33.000216 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 12:43:33.006791 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1570 12:43:33.010238 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 12:43:33.013611 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 12:43:33.016799 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 12:43:33.023445 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 12:43:33.027055 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 12:43:33.030407 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 12:43:33.036744 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 12:43:33.040255 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 12:43:33.043360 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 12:43:33.050241 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 12:43:33.053680 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 12:43:33.057120 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 12:43:33.063363 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 12:43:33.066880 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 12:43:33.070328 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 12:43:33.076863 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 12:43:33.080304 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1587 12:43:33.083459 Total UI for P1: 0, mck2ui 16
1588 12:43:33.086915 best dqsien dly found for B0: ( 0, 14, 6)
1589 12:43:33.090220 Total UI for P1: 0, mck2ui 16
1590 12:43:33.093484 best dqsien dly found for B1: ( 0, 14, 6)
1591 12:43:33.096603 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1592 12:43:33.100012 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1593 12:43:33.100083
1594 12:43:33.103454 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1595 12:43:33.106571 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1596 12:43:33.110021 [Gating] SW calibration Done
1597 12:43:33.110100 ==
1598 12:43:33.113375 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 12:43:33.116655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 12:43:33.116729 ==
1601 12:43:33.120163 RX Vref Scan: 0
1602 12:43:33.120234
1603 12:43:33.120300 RX Vref 0 -> 0, step: 1
1604 12:43:33.123611
1605 12:43:33.123686 RX Delay -130 -> 252, step: 16
1606 12:43:33.130225 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1607 12:43:33.133587 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1608 12:43:33.137046 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1609 12:43:33.140390 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1610 12:43:33.143416 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1611 12:43:33.150332 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1612 12:43:33.153623 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1613 12:43:33.156733 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1614 12:43:33.160409 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1615 12:43:33.163568 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1616 12:43:33.170035 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1617 12:43:33.173454 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1618 12:43:33.176813 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1619 12:43:33.180288 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1620 12:43:33.183421 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1621 12:43:33.190126 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1622 12:43:33.190204 ==
1623 12:43:33.193771 Dram Type= 6, Freq= 0, CH_1, rank 0
1624 12:43:33.196641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1625 12:43:33.196715 ==
1626 12:43:33.196781 DQS Delay:
1627 12:43:33.200044 DQS0 = 0, DQS1 = 0
1628 12:43:33.200113 DQM Delay:
1629 12:43:33.203562 DQM0 = 81, DQM1 = 72
1630 12:43:33.203631 DQ Delay:
1631 12:43:33.206616 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1632 12:43:33.210323 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1633 12:43:33.213602 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1634 12:43:33.217039 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1635 12:43:33.217110
1636 12:43:33.217177
1637 12:43:33.217233 ==
1638 12:43:33.220031 Dram Type= 6, Freq= 0, CH_1, rank 0
1639 12:43:33.223558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1640 12:43:33.223629 ==
1641 12:43:33.223696
1642 12:43:33.223752
1643 12:43:33.227012 TX Vref Scan disable
1644 12:43:33.230010 == TX Byte 0 ==
1645 12:43:33.233643 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1646 12:43:33.236809 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1647 12:43:33.240001 == TX Byte 1 ==
1648 12:43:33.243634 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1649 12:43:33.246874 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1650 12:43:33.246945 ==
1651 12:43:33.250262 Dram Type= 6, Freq= 0, CH_1, rank 0
1652 12:43:33.253624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1653 12:43:33.256874 ==
1654 12:43:33.268337 TX Vref=22, minBit 1, minWin=26, winSum=439
1655 12:43:33.271687 TX Vref=24, minBit 1, minWin=26, winSum=440
1656 12:43:33.274897 TX Vref=26, minBit 1, minWin=26, winSum=440
1657 12:43:33.278311 TX Vref=28, minBit 11, minWin=27, winSum=448
1658 12:43:33.281530 TX Vref=30, minBit 6, minWin=27, winSum=449
1659 12:43:33.284882 TX Vref=32, minBit 4, minWin=27, winSum=446
1660 12:43:33.291639 [TxChooseVref] Worse bit 6, Min win 27, Win sum 449, Final Vref 30
1661 12:43:33.291716
1662 12:43:33.294939 Final TX Range 1 Vref 30
1663 12:43:33.295010
1664 12:43:33.295069 ==
1665 12:43:33.298102 Dram Type= 6, Freq= 0, CH_1, rank 0
1666 12:43:33.301863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1667 12:43:33.301934 ==
1668 12:43:33.301993
1669 12:43:33.302056
1670 12:43:33.305422 TX Vref Scan disable
1671 12:43:33.308894 == TX Byte 0 ==
1672 12:43:33.312247 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1673 12:43:33.315597 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1674 12:43:33.318867 == TX Byte 1 ==
1675 12:43:33.322250 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1676 12:43:33.325591 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1677 12:43:33.325662
1678 12:43:33.328814 [DATLAT]
1679 12:43:33.328883 Freq=800, CH1 RK0
1680 12:43:33.328941
1681 12:43:33.332140 DATLAT Default: 0xa
1682 12:43:33.332208 0, 0xFFFF, sum = 0
1683 12:43:33.335416 1, 0xFFFF, sum = 0
1684 12:43:33.335486 2, 0xFFFF, sum = 0
1685 12:43:33.338745 3, 0xFFFF, sum = 0
1686 12:43:33.338815 4, 0xFFFF, sum = 0
1687 12:43:33.342187 5, 0xFFFF, sum = 0
1688 12:43:33.342257 6, 0xFFFF, sum = 0
1689 12:43:33.345308 7, 0xFFFF, sum = 0
1690 12:43:33.345413 8, 0xFFFF, sum = 0
1691 12:43:33.348915 9, 0x0, sum = 1
1692 12:43:33.348989 10, 0x0, sum = 2
1693 12:43:33.352248 11, 0x0, sum = 3
1694 12:43:33.352317 12, 0x0, sum = 4
1695 12:43:33.355412 best_step = 10
1696 12:43:33.355481
1697 12:43:33.355540 ==
1698 12:43:33.359013 Dram Type= 6, Freq= 0, CH_1, rank 0
1699 12:43:33.362403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1700 12:43:33.362475 ==
1701 12:43:33.362535 RX Vref Scan: 1
1702 12:43:33.365559
1703 12:43:33.365627 Set Vref Range= 32 -> 127
1704 12:43:33.365693
1705 12:43:33.369034 RX Vref 32 -> 127, step: 1
1706 12:43:33.369101
1707 12:43:33.372434 RX Delay -111 -> 252, step: 8
1708 12:43:33.372503
1709 12:43:33.375603 Set Vref, RX VrefLevel [Byte0]: 32
1710 12:43:33.378854 [Byte1]: 32
1711 12:43:33.378926
1712 12:43:33.382219 Set Vref, RX VrefLevel [Byte0]: 33
1713 12:43:33.385583 [Byte1]: 33
1714 12:43:33.388655
1715 12:43:33.388763 Set Vref, RX VrefLevel [Byte0]: 34
1716 12:43:33.392113 [Byte1]: 34
1717 12:43:33.396346
1718 12:43:33.396442 Set Vref, RX VrefLevel [Byte0]: 35
1719 12:43:33.399677 [Byte1]: 35
1720 12:43:33.403904
1721 12:43:33.404007 Set Vref, RX VrefLevel [Byte0]: 36
1722 12:43:33.407514 [Byte1]: 36
1723 12:43:33.411754
1724 12:43:33.411830 Set Vref, RX VrefLevel [Byte0]: 37
1725 12:43:33.415193 [Byte1]: 37
1726 12:43:33.419361
1727 12:43:33.419431 Set Vref, RX VrefLevel [Byte0]: 38
1728 12:43:33.422751 [Byte1]: 38
1729 12:43:33.426798
1730 12:43:33.426891 Set Vref, RX VrefLevel [Byte0]: 39
1731 12:43:33.430204 [Byte1]: 39
1732 12:43:33.434410
1733 12:43:33.434484 Set Vref, RX VrefLevel [Byte0]: 40
1734 12:43:33.438030 [Byte1]: 40
1735 12:43:33.442402
1736 12:43:33.442470 Set Vref, RX VrefLevel [Byte0]: 41
1737 12:43:33.445598 [Byte1]: 41
1738 12:43:33.449861
1739 12:43:33.449960 Set Vref, RX VrefLevel [Byte0]: 42
1740 12:43:33.453167 [Byte1]: 42
1741 12:43:33.457369
1742 12:43:33.457465 Set Vref, RX VrefLevel [Byte0]: 43
1743 12:43:33.460762 [Byte1]: 43
1744 12:43:33.465044
1745 12:43:33.465142 Set Vref, RX VrefLevel [Byte0]: 44
1746 12:43:33.468411 [Byte1]: 44
1747 12:43:33.472791
1748 12:43:33.472863 Set Vref, RX VrefLevel [Byte0]: 45
1749 12:43:33.476409 [Byte1]: 45
1750 12:43:33.480381
1751 12:43:33.480456 Set Vref, RX VrefLevel [Byte0]: 46
1752 12:43:33.486866 [Byte1]: 46
1753 12:43:33.486945
1754 12:43:33.490326 Set Vref, RX VrefLevel [Byte0]: 47
1755 12:43:33.493429 [Byte1]: 47
1756 12:43:33.493547
1757 12:43:33.496821 Set Vref, RX VrefLevel [Byte0]: 48
1758 12:43:33.500279 [Byte1]: 48
1759 12:43:33.500371
1760 12:43:33.503547 Set Vref, RX VrefLevel [Byte0]: 49
1761 12:43:33.507090 [Byte1]: 49
1762 12:43:33.511208
1763 12:43:33.511302 Set Vref, RX VrefLevel [Byte0]: 50
1764 12:43:33.514486 [Byte1]: 50
1765 12:43:33.518558
1766 12:43:33.518662 Set Vref, RX VrefLevel [Byte0]: 51
1767 12:43:33.522096 [Byte1]: 51
1768 12:43:33.526380
1769 12:43:33.526466 Set Vref, RX VrefLevel [Byte0]: 52
1770 12:43:33.530041 [Byte1]: 52
1771 12:43:33.533900
1772 12:43:33.533973 Set Vref, RX VrefLevel [Byte0]: 53
1773 12:43:33.537363 [Byte1]: 53
1774 12:43:33.541682
1775 12:43:33.541754 Set Vref, RX VrefLevel [Byte0]: 54
1776 12:43:33.544807 [Byte1]: 54
1777 12:43:33.549593
1778 12:43:33.549662 Set Vref, RX VrefLevel [Byte0]: 55
1779 12:43:33.552768 [Byte1]: 55
1780 12:43:33.556855
1781 12:43:33.556955 Set Vref, RX VrefLevel [Byte0]: 56
1782 12:43:33.560103 [Byte1]: 56
1783 12:43:33.564434
1784 12:43:33.564505 Set Vref, RX VrefLevel [Byte0]: 57
1785 12:43:33.567958 [Byte1]: 57
1786 12:43:33.572136
1787 12:43:33.572208 Set Vref, RX VrefLevel [Byte0]: 58
1788 12:43:33.575516 [Byte1]: 58
1789 12:43:33.579768
1790 12:43:33.579838 Set Vref, RX VrefLevel [Byte0]: 59
1791 12:43:33.583281 [Byte1]: 59
1792 12:43:33.587394
1793 12:43:33.587472 Set Vref, RX VrefLevel [Byte0]: 60
1794 12:43:33.590785 [Byte1]: 60
1795 12:43:33.595027
1796 12:43:33.595097 Set Vref, RX VrefLevel [Byte0]: 61
1797 12:43:33.598510 [Byte1]: 61
1798 12:43:33.603009
1799 12:43:33.603084 Set Vref, RX VrefLevel [Byte0]: 62
1800 12:43:33.606033 [Byte1]: 62
1801 12:43:33.610405
1802 12:43:33.610474 Set Vref, RX VrefLevel [Byte0]: 63
1803 12:43:33.613900 [Byte1]: 63
1804 12:43:33.618122
1805 12:43:33.618192 Set Vref, RX VrefLevel [Byte0]: 64
1806 12:43:33.621660 [Byte1]: 64
1807 12:43:33.625739
1808 12:43:33.625808 Set Vref, RX VrefLevel [Byte0]: 65
1809 12:43:33.629041 [Byte1]: 65
1810 12:43:33.633501
1811 12:43:33.633571 Set Vref, RX VrefLevel [Byte0]: 66
1812 12:43:33.636595 [Byte1]: 66
1813 12:43:33.641012
1814 12:43:33.641082 Set Vref, RX VrefLevel [Byte0]: 67
1815 12:43:33.644207 [Byte1]: 67
1816 12:43:33.648494
1817 12:43:33.648563 Set Vref, RX VrefLevel [Byte0]: 68
1818 12:43:33.652033 [Byte1]: 68
1819 12:43:33.656252
1820 12:43:33.656363 Set Vref, RX VrefLevel [Byte0]: 69
1821 12:43:33.659570 [Byte1]: 69
1822 12:43:33.664026
1823 12:43:33.664122 Set Vref, RX VrefLevel [Byte0]: 70
1824 12:43:33.667279 [Byte1]: 70
1825 12:43:33.671656
1826 12:43:33.671732 Set Vref, RX VrefLevel [Byte0]: 71
1827 12:43:33.674901 [Byte1]: 71
1828 12:43:33.679389
1829 12:43:33.679465 Set Vref, RX VrefLevel [Byte0]: 72
1830 12:43:33.682473 [Byte1]: 72
1831 12:43:33.687028
1832 12:43:33.687132 Set Vref, RX VrefLevel [Byte0]: 73
1833 12:43:33.690143 [Byte1]: 73
1834 12:43:33.694566
1835 12:43:33.694666 Set Vref, RX VrefLevel [Byte0]: 74
1836 12:43:33.697653 [Byte1]: 74
1837 12:43:33.702284
1838 12:43:33.702356 Set Vref, RX VrefLevel [Byte0]: 75
1839 12:43:33.705358 [Byte1]: 75
1840 12:43:33.710036
1841 12:43:33.710111 Set Vref, RX VrefLevel [Byte0]: 76
1842 12:43:33.713189 [Byte1]: 76
1843 12:43:33.717414
1844 12:43:33.717493 Set Vref, RX VrefLevel [Byte0]: 77
1845 12:43:33.720805 [Byte1]: 77
1846 12:43:33.725164
1847 12:43:33.725234 Final RX Vref Byte 0 = 58 to rank0
1848 12:43:33.728571 Final RX Vref Byte 1 = 55 to rank0
1849 12:43:33.731989 Final RX Vref Byte 0 = 58 to rank1
1850 12:43:33.735287 Final RX Vref Byte 1 = 55 to rank1==
1851 12:43:33.738485 Dram Type= 6, Freq= 0, CH_1, rank 0
1852 12:43:33.741923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1853 12:43:33.745249 ==
1854 12:43:33.745319 DQS Delay:
1855 12:43:33.745378 DQS0 = 0, DQS1 = 0
1856 12:43:33.748579 DQM Delay:
1857 12:43:33.748683 DQM0 = 81, DQM1 = 72
1858 12:43:33.751808 DQ Delay:
1859 12:43:33.755112 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =76
1860 12:43:33.755211 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =76
1861 12:43:33.758425 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1862 12:43:33.761793 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =76
1863 12:43:33.765020
1864 12:43:33.765113
1865 12:43:33.771790 [DQSOSCAuto] RK0, (LSB)MR18= 0x111c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 405 ps
1866 12:43:33.775304 CH1 RK0: MR19=606, MR18=111C
1867 12:43:33.781689 CH1_RK0: MR19=0x606, MR18=0x111C, DQSOSC=402, MR23=63, INC=91, DEC=60
1868 12:43:33.781789
1869 12:43:33.784923 ----->DramcWriteLeveling(PI) begin...
1870 12:43:33.785028 ==
1871 12:43:33.788538 Dram Type= 6, Freq= 0, CH_1, rank 1
1872 12:43:33.792012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1873 12:43:33.792114 ==
1874 12:43:33.795001 Write leveling (Byte 0): 29 => 29
1875 12:43:33.798390 Write leveling (Byte 1): 29 => 29
1876 12:43:33.801781 DramcWriteLeveling(PI) end<-----
1877 12:43:33.801853
1878 12:43:33.801945 ==
1879 12:43:33.805247 Dram Type= 6, Freq= 0, CH_1, rank 1
1880 12:43:33.808461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1881 12:43:33.808556 ==
1882 12:43:33.811724 [Gating] SW mode calibration
1883 12:43:33.818368 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1884 12:43:33.824835 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1885 12:43:33.828402 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1886 12:43:33.831819 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1887 12:43:33.838310 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1888 12:43:33.841404 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 12:43:33.844874 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 12:43:33.851583 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 12:43:33.854833 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 12:43:33.858183 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 12:43:33.864948 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 12:43:33.868118 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 12:43:33.871400 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 12:43:33.878350 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 12:43:33.881638 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 12:43:33.885097 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 12:43:33.888213 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 12:43:33.895198 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 12:43:33.898353 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1902 12:43:33.901680 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1903 12:43:33.908540 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1904 12:43:33.911601 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 12:43:33.914983 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 12:43:33.921787 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 12:43:33.925193 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 12:43:33.928649 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 12:43:33.935355 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 12:43:33.938625 0 9 4 | B1->B0 | 2323 2c2b | 1 1 | (1 1) (1 1)
1911 12:43:33.941843 0 9 8 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
1912 12:43:33.948518 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1913 12:43:33.951917 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 12:43:33.955059 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1915 12:43:33.961778 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1916 12:43:33.965087 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1917 12:43:33.968504 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1918 12:43:33.975092 0 10 4 | B1->B0 | 3131 2e2e | 1 1 | (1 0) (1 1)
1919 12:43:33.978627 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1920 12:43:33.982085 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 12:43:33.985232 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 12:43:33.991688 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 12:43:33.995387 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 12:43:33.998543 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 12:43:34.005364 0 11 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1926 12:43:34.008644 0 11 4 | B1->B0 | 2626 3c3c | 0 0 | (0 0) (0 0)
1927 12:43:34.011892 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1928 12:43:34.018465 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 12:43:34.021904 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 12:43:34.025402 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 12:43:34.031948 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 12:43:34.035451 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 12:43:34.038582 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1934 12:43:34.045266 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1935 12:43:34.048342 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1936 12:43:34.051823 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 12:43:34.058410 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 12:43:34.061837 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 12:43:34.065028 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 12:43:34.071858 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 12:43:34.075085 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 12:43:34.078446 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 12:43:34.085300 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 12:43:34.088282 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 12:43:34.091649 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 12:43:34.094887 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 12:43:34.101589 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 12:43:34.105099 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 12:43:34.108488 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1950 12:43:34.115073 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1951 12:43:34.118154 Total UI for P1: 0, mck2ui 16
1952 12:43:34.121551 best dqsien dly found for B0: ( 0, 14, 0)
1953 12:43:34.124820 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1954 12:43:34.128200 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1955 12:43:34.131698 Total UI for P1: 0, mck2ui 16
1956 12:43:34.134861 best dqsien dly found for B1: ( 0, 14, 6)
1957 12:43:34.138498 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1958 12:43:34.141414 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1959 12:43:34.141512
1960 12:43:34.148086 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1961 12:43:34.151466 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1962 12:43:34.154548 [Gating] SW calibration Done
1963 12:43:34.154618 ==
1964 12:43:34.158193 Dram Type= 6, Freq= 0, CH_1, rank 1
1965 12:43:34.161413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1966 12:43:34.161543 ==
1967 12:43:34.161605 RX Vref Scan: 0
1968 12:43:34.161669
1969 12:43:34.164812 RX Vref 0 -> 0, step: 1
1970 12:43:34.164880
1971 12:43:34.167887 RX Delay -130 -> 252, step: 16
1972 12:43:34.171329 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1973 12:43:34.174501 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1974 12:43:34.181383 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1975 12:43:34.184751 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1976 12:43:34.188297 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1977 12:43:34.191211 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1978 12:43:34.194616 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1979 12:43:34.197884 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1980 12:43:34.204717 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1981 12:43:34.207862 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1982 12:43:34.211301 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1983 12:43:34.214760 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1984 12:43:34.221449 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1985 12:43:34.224578 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1986 12:43:34.227855 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1987 12:43:34.231239 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1988 12:43:34.231312 ==
1989 12:43:34.234501 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 12:43:34.238080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 12:43:34.241111 ==
1992 12:43:34.241208 DQS Delay:
1993 12:43:34.241297 DQS0 = 0, DQS1 = 0
1994 12:43:34.244626 DQM Delay:
1995 12:43:34.244698 DQM0 = 78, DQM1 = 72
1996 12:43:34.248034 DQ Delay:
1997 12:43:34.248107 DQ0 =77, DQ1 =69, DQ2 =69, DQ3 =77
1998 12:43:34.251160 DQ4 =77, DQ5 =85, DQ6 =93, DQ7 =77
1999 12:43:34.254634 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
2000 12:43:34.257734 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
2001 12:43:34.257806
2002 12:43:34.261084
2003 12:43:34.261180 ==
2004 12:43:34.264447 Dram Type= 6, Freq= 0, CH_1, rank 1
2005 12:43:34.268026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2006 12:43:34.268102 ==
2007 12:43:34.268192
2008 12:43:34.268278
2009 12:43:34.271120 TX Vref Scan disable
2010 12:43:34.271216 == TX Byte 0 ==
2011 12:43:34.278083 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2012 12:43:34.281255 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2013 12:43:34.281325 == TX Byte 1 ==
2014 12:43:34.287921 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2015 12:43:34.291121 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2016 12:43:34.291225 ==
2017 12:43:34.294636 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 12:43:34.297843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 12:43:34.297931 ==
2020 12:43:34.311316 TX Vref=22, minBit 1, minWin=27, winSum=447
2021 12:43:34.314611 TX Vref=24, minBit 1, minWin=27, winSum=449
2022 12:43:34.317784 TX Vref=26, minBit 0, minWin=28, winSum=458
2023 12:43:34.321150 TX Vref=28, minBit 0, minWin=28, winSum=457
2024 12:43:34.324559 TX Vref=30, minBit 5, minWin=27, winSum=460
2025 12:43:34.327912 TX Vref=32, minBit 1, minWin=27, winSum=458
2026 12:43:34.334616 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 26
2027 12:43:34.334703
2028 12:43:34.338237 Final TX Range 1 Vref 26
2029 12:43:34.338319
2030 12:43:34.338388 ==
2031 12:43:34.341166 Dram Type= 6, Freq= 0, CH_1, rank 1
2032 12:43:34.344775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2033 12:43:34.344873 ==
2034 12:43:34.344956
2035 12:43:34.345034
2036 12:43:34.347866 TX Vref Scan disable
2037 12:43:34.351459 == TX Byte 0 ==
2038 12:43:34.354611 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2039 12:43:34.357739 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2040 12:43:34.361587 == TX Byte 1 ==
2041 12:43:34.364929 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2042 12:43:34.368268 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2043 12:43:34.368668
2044 12:43:34.371198 [DATLAT]
2045 12:43:34.371583 Freq=800, CH1 RK1
2046 12:43:34.371918
2047 12:43:34.375020 DATLAT Default: 0xa
2048 12:43:34.375800 0, 0xFFFF, sum = 0
2049 12:43:34.377988 1, 0xFFFF, sum = 0
2050 12:43:34.378746 2, 0xFFFF, sum = 0
2051 12:43:34.381554 3, 0xFFFF, sum = 0
2052 12:43:34.382268 4, 0xFFFF, sum = 0
2053 12:43:34.384806 5, 0xFFFF, sum = 0
2054 12:43:34.385787 6, 0xFFFF, sum = 0
2055 12:43:34.388125 7, 0xFFFF, sum = 0
2056 12:43:34.391387 8, 0xFFFF, sum = 0
2057 12:43:34.392161 9, 0x0, sum = 1
2058 12:43:34.392884 10, 0x0, sum = 2
2059 12:43:34.394894 11, 0x0, sum = 3
2060 12:43:34.395652 12, 0x0, sum = 4
2061 12:43:34.398090 best_step = 10
2062 12:43:34.398860
2063 12:43:34.399346 ==
2064 12:43:34.401741 Dram Type= 6, Freq= 0, CH_1, rank 1
2065 12:43:34.404791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2066 12:43:34.405172 ==
2067 12:43:34.408188 RX Vref Scan: 0
2068 12:43:34.408565
2069 12:43:34.408919 RX Vref 0 -> 0, step: 1
2070 12:43:34.409199
2071 12:43:34.411327 RX Delay -111 -> 252, step: 8
2072 12:43:34.418040 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2073 12:43:34.421108 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2074 12:43:34.424418 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
2075 12:43:34.427805 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2076 12:43:34.431165 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2077 12:43:34.437730 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2078 12:43:34.441261 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2079 12:43:34.444560 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2080 12:43:34.447862 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2081 12:43:34.451295 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2082 12:43:34.457949 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2083 12:43:34.461424 iDelay=209, Bit 11, Center 72 (-47 ~ 192) 240
2084 12:43:34.464559 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2085 12:43:34.468067 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2086 12:43:34.471470 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2087 12:43:34.477948 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2088 12:43:34.478021 ==
2089 12:43:34.481048 Dram Type= 6, Freq= 0, CH_1, rank 1
2090 12:43:34.484387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2091 12:43:34.484458 ==
2092 12:43:34.484519 DQS Delay:
2093 12:43:34.487807 DQS0 = 0, DQS1 = 0
2094 12:43:34.487881 DQM Delay:
2095 12:43:34.491190 DQM0 = 77, DQM1 = 74
2096 12:43:34.491260 DQ Delay:
2097 12:43:34.494317 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2098 12:43:34.497660 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2099 12:43:34.501074 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =72
2100 12:43:34.504249 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
2101 12:43:34.504317
2102 12:43:34.504382
2103 12:43:34.514295 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f38, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2104 12:43:34.514372 CH1 RK1: MR19=606, MR18=1F38
2105 12:43:34.521064 CH1_RK1: MR19=0x606, MR18=0x1F38, DQSOSC=395, MR23=63, INC=94, DEC=63
2106 12:43:34.524249 [RxdqsGatingPostProcess] freq 800
2107 12:43:34.530934 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2108 12:43:34.534271 Pre-setting of DQS Precalculation
2109 12:43:34.537779 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2110 12:43:34.544181 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2111 12:43:34.550703 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2112 12:43:34.554230
2113 12:43:34.554299
2114 12:43:34.554359 [Calibration Summary] 1600 Mbps
2115 12:43:34.557469 CH 0, Rank 0
2116 12:43:34.557556 SW Impedance : PASS
2117 12:43:34.560722 DUTY Scan : NO K
2118 12:43:34.564256 ZQ Calibration : PASS
2119 12:43:34.564329 Jitter Meter : NO K
2120 12:43:34.567343 CBT Training : PASS
2121 12:43:34.570831 Write leveling : PASS
2122 12:43:34.570899 RX DQS gating : PASS
2123 12:43:34.574150 RX DQ/DQS(RDDQC) : PASS
2124 12:43:34.577658 TX DQ/DQS : PASS
2125 12:43:34.577727 RX DATLAT : PASS
2126 12:43:34.580632 RX DQ/DQS(Engine): PASS
2127 12:43:34.584166 TX OE : NO K
2128 12:43:34.584234 All Pass.
2129 12:43:34.584294
2130 12:43:34.584349 CH 0, Rank 1
2131 12:43:34.587315 SW Impedance : PASS
2132 12:43:34.590759 DUTY Scan : NO K
2133 12:43:34.590829 ZQ Calibration : PASS
2134 12:43:34.594222 Jitter Meter : NO K
2135 12:43:34.594290 CBT Training : PASS
2136 12:43:34.597326 Write leveling : PASS
2137 12:43:34.600732 RX DQS gating : PASS
2138 12:43:34.600798 RX DQ/DQS(RDDQC) : PASS
2139 12:43:34.603891 TX DQ/DQS : PASS
2140 12:43:34.607607 RX DATLAT : PASS
2141 12:43:34.607681 RX DQ/DQS(Engine): PASS
2142 12:43:34.610618 TX OE : NO K
2143 12:43:34.610691 All Pass.
2144 12:43:34.610750
2145 12:43:34.614203 CH 1, Rank 0
2146 12:43:34.614269 SW Impedance : PASS
2147 12:43:34.617392 DUTY Scan : NO K
2148 12:43:34.620790 ZQ Calibration : PASS
2149 12:43:34.620857 Jitter Meter : NO K
2150 12:43:34.624117 CBT Training : PASS
2151 12:43:34.627300 Write leveling : PASS
2152 12:43:34.627373 RX DQS gating : PASS
2153 12:43:34.630716 RX DQ/DQS(RDDQC) : PASS
2154 12:43:34.634248 TX DQ/DQS : PASS
2155 12:43:34.634317 RX DATLAT : PASS
2156 12:43:34.637405 RX DQ/DQS(Engine): PASS
2157 12:43:34.637500 TX OE : NO K
2158 12:43:34.640746 All Pass.
2159 12:43:34.640819
2160 12:43:34.640885 CH 1, Rank 1
2161 12:43:34.644289 SW Impedance : PASS
2162 12:43:34.644357 DUTY Scan : NO K
2163 12:43:34.647415 ZQ Calibration : PASS
2164 12:43:34.650825 Jitter Meter : NO K
2165 12:43:34.650899 CBT Training : PASS
2166 12:43:34.654145 Write leveling : PASS
2167 12:43:34.657660 RX DQS gating : PASS
2168 12:43:34.657741 RX DQ/DQS(RDDQC) : PASS
2169 12:43:34.661156 TX DQ/DQS : PASS
2170 12:43:34.664332 RX DATLAT : PASS
2171 12:43:34.664413 RX DQ/DQS(Engine): PASS
2172 12:43:34.667629 TX OE : NO K
2173 12:43:34.667711 All Pass.
2174 12:43:34.667775
2175 12:43:34.670894 DramC Write-DBI off
2176 12:43:34.674256 PER_BANK_REFRESH: Hybrid Mode
2177 12:43:34.674332 TX_TRACKING: ON
2178 12:43:34.677777 [GetDramInforAfterCalByMRR] Vendor 6.
2179 12:43:34.681023 [GetDramInforAfterCalByMRR] Revision 606.
2180 12:43:34.684269 [GetDramInforAfterCalByMRR] Revision 2 0.
2181 12:43:34.687457 MR0 0x3b3b
2182 12:43:34.687537 MR8 0x5151
2183 12:43:34.690935 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2184 12:43:34.691013
2185 12:43:34.691073 MR0 0x3b3b
2186 12:43:34.694596 MR8 0x5151
2187 12:43:34.697799 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2188 12:43:34.697871
2189 12:43:34.704409 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2190 12:43:34.707539 [FAST_K] Save calibration result to emmc
2191 12:43:34.714456 [FAST_K] Save calibration result to emmc
2192 12:43:34.714530 dram_init: config_dvfs: 1
2193 12:43:34.717774 dramc_set_vcore_voltage set vcore to 662500
2194 12:43:34.720903 Read voltage for 1200, 2
2195 12:43:34.720972 Vio18 = 0
2196 12:43:34.724292 Vcore = 662500
2197 12:43:34.724366 Vdram = 0
2198 12:43:34.724435 Vddq = 0
2199 12:43:34.727934 Vmddr = 0
2200 12:43:34.730867 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2201 12:43:34.737728 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2202 12:43:34.737822 MEM_TYPE=3, freq_sel=15
2203 12:43:34.740904 sv_algorithm_assistance_LP4_1600
2204 12:43:34.747634 ============ PULL DRAM RESETB DOWN ============
2205 12:43:34.750886 ========== PULL DRAM RESETB DOWN end =========
2206 12:43:34.754411 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2207 12:43:34.757601 ===================================
2208 12:43:34.761143 LPDDR4 DRAM CONFIGURATION
2209 12:43:34.764461 ===================================
2210 12:43:34.767760 EX_ROW_EN[0] = 0x0
2211 12:43:34.767950 EX_ROW_EN[1] = 0x0
2212 12:43:34.771242 LP4Y_EN = 0x0
2213 12:43:34.771463 WORK_FSP = 0x0
2214 12:43:34.774757 WL = 0x4
2215 12:43:34.775028 RL = 0x4
2216 12:43:34.777664 BL = 0x2
2217 12:43:34.777949 RPST = 0x0
2218 12:43:34.781181 RD_PRE = 0x0
2219 12:43:34.781555 WR_PRE = 0x1
2220 12:43:34.784532 WR_PST = 0x0
2221 12:43:34.784972 DBI_WR = 0x0
2222 12:43:34.787952 DBI_RD = 0x0
2223 12:43:34.788398 OTF = 0x1
2224 12:43:34.791262 ===================================
2225 12:43:34.794495 ===================================
2226 12:43:34.798060 ANA top config
2227 12:43:34.801118 ===================================
2228 12:43:34.801587 DLL_ASYNC_EN = 0
2229 12:43:34.804590 ALL_SLAVE_EN = 0
2230 12:43:34.808018 NEW_RANK_MODE = 1
2231 12:43:34.811477 DLL_IDLE_MODE = 1
2232 12:43:34.814530 LP45_APHY_COMB_EN = 1
2233 12:43:34.814977 TX_ODT_DIS = 1
2234 12:43:34.818077 NEW_8X_MODE = 1
2235 12:43:34.821289 ===================================
2236 12:43:34.824663 ===================================
2237 12:43:34.828168 data_rate = 2400
2238 12:43:34.831156 CKR = 1
2239 12:43:34.834947 DQ_P2S_RATIO = 8
2240 12:43:34.838071 ===================================
2241 12:43:34.838535 CA_P2S_RATIO = 8
2242 12:43:34.841465 DQ_CA_OPEN = 0
2243 12:43:34.844631 DQ_SEMI_OPEN = 0
2244 12:43:34.848027 CA_SEMI_OPEN = 0
2245 12:43:34.851557 CA_FULL_RATE = 0
2246 12:43:34.854648 DQ_CKDIV4_EN = 0
2247 12:43:34.855091 CA_CKDIV4_EN = 0
2248 12:43:34.858255 CA_PREDIV_EN = 0
2249 12:43:34.861253 PH8_DLY = 17
2250 12:43:34.865032 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2251 12:43:34.868037 DQ_AAMCK_DIV = 4
2252 12:43:34.871462 CA_AAMCK_DIV = 4
2253 12:43:34.871906 CA_ADMCK_DIV = 4
2254 12:43:34.874606 DQ_TRACK_CA_EN = 0
2255 12:43:34.878235 CA_PICK = 1200
2256 12:43:34.881284 CA_MCKIO = 1200
2257 12:43:34.884643 MCKIO_SEMI = 0
2258 12:43:34.887746 PLL_FREQ = 2366
2259 12:43:34.891302 DQ_UI_PI_RATIO = 32
2260 12:43:34.891752 CA_UI_PI_RATIO = 0
2261 12:43:34.894695 ===================================
2262 12:43:34.898017 ===================================
2263 12:43:34.901712 memory_type:LPDDR4
2264 12:43:34.904735 GP_NUM : 10
2265 12:43:34.905165 SRAM_EN : 1
2266 12:43:34.908121 MD32_EN : 0
2267 12:43:34.911208 ===================================
2268 12:43:34.914622 [ANA_INIT] >>>>>>>>>>>>>>
2269 12:43:34.918064 <<<<<< [CONFIGURE PHASE]: ANA_TX
2270 12:43:34.921090 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2271 12:43:34.924653 ===================================
2272 12:43:34.925149 data_rate = 2400,PCW = 0X5b00
2273 12:43:34.927778 ===================================
2274 12:43:34.931234 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2275 12:43:34.938094 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2276 12:43:34.944548 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2277 12:43:34.948093 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2278 12:43:34.951268 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2279 12:43:34.954899 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2280 12:43:34.958146 [ANA_INIT] flow start
2281 12:43:34.958590 [ANA_INIT] PLL >>>>>>>>
2282 12:43:34.961405 [ANA_INIT] PLL <<<<<<<<
2283 12:43:34.964569 [ANA_INIT] MIDPI >>>>>>>>
2284 12:43:34.968192 [ANA_INIT] MIDPI <<<<<<<<
2285 12:43:34.968726 [ANA_INIT] DLL >>>>>>>>
2286 12:43:34.971507 [ANA_INIT] DLL <<<<<<<<
2287 12:43:34.972075 [ANA_INIT] flow end
2288 12:43:34.977908 ============ LP4 DIFF to SE enter ============
2289 12:43:34.981239 ============ LP4 DIFF to SE exit ============
2290 12:43:34.984647 [ANA_INIT] <<<<<<<<<<<<<
2291 12:43:34.988235 [Flow] Enable top DCM control >>>>>
2292 12:43:34.991445 [Flow] Enable top DCM control <<<<<
2293 12:43:34.992019 Enable DLL master slave shuffle
2294 12:43:34.997985 ==============================================================
2295 12:43:35.001449 Gating Mode config
2296 12:43:35.004675 ==============================================================
2297 12:43:35.008203 Config description:
2298 12:43:35.017898 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2299 12:43:35.024611 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2300 12:43:35.028102 SELPH_MODE 0: By rank 1: By Phase
2301 12:43:35.034516 ==============================================================
2302 12:43:35.038012 GAT_TRACK_EN = 1
2303 12:43:35.041070 RX_GATING_MODE = 2
2304 12:43:35.044653 RX_GATING_TRACK_MODE = 2
2305 12:43:35.048131 SELPH_MODE = 1
2306 12:43:35.048546 PICG_EARLY_EN = 1
2307 12:43:35.051239 VALID_LAT_VALUE = 1
2308 12:43:35.057882 ==============================================================
2309 12:43:35.061076 Enter into Gating configuration >>>>
2310 12:43:35.064766 Exit from Gating configuration <<<<
2311 12:43:35.067849 Enter into DVFS_PRE_config >>>>>
2312 12:43:35.077940 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2313 12:43:35.081210 Exit from DVFS_PRE_config <<<<<
2314 12:43:35.084565 Enter into PICG configuration >>>>
2315 12:43:35.087999 Exit from PICG configuration <<<<
2316 12:43:35.091316 [RX_INPUT] configuration >>>>>
2317 12:43:35.094609 [RX_INPUT] configuration <<<<<
2318 12:43:35.097767 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2319 12:43:35.104394 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2320 12:43:35.111071 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2321 12:43:35.117842 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2322 12:43:35.121251 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2323 12:43:35.127929 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2324 12:43:35.131430 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2325 12:43:35.137882 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2326 12:43:35.141344 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2327 12:43:35.144540 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2328 12:43:35.147765 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2329 12:43:35.154611 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2330 12:43:35.158023 ===================================
2331 12:43:35.158442 LPDDR4 DRAM CONFIGURATION
2332 12:43:35.161002 ===================================
2333 12:43:35.164563 EX_ROW_EN[0] = 0x0
2334 12:43:35.167777 EX_ROW_EN[1] = 0x0
2335 12:43:35.168264 LP4Y_EN = 0x0
2336 12:43:35.171242 WORK_FSP = 0x0
2337 12:43:35.171848 WL = 0x4
2338 12:43:35.174606 RL = 0x4
2339 12:43:35.175098 BL = 0x2
2340 12:43:35.177826 RPST = 0x0
2341 12:43:35.178304 RD_PRE = 0x0
2342 12:43:35.181386 WR_PRE = 0x1
2343 12:43:35.181921 WR_PST = 0x0
2344 12:43:35.184469 DBI_WR = 0x0
2345 12:43:35.184969 DBI_RD = 0x0
2346 12:43:35.187940 OTF = 0x1
2347 12:43:35.191396 ===================================
2348 12:43:35.194779 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2349 12:43:35.197866 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2350 12:43:35.204469 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2351 12:43:35.208153 ===================================
2352 12:43:35.208579 LPDDR4 DRAM CONFIGURATION
2353 12:43:35.211173 ===================================
2354 12:43:35.214570 EX_ROW_EN[0] = 0x10
2355 12:43:35.217887 EX_ROW_EN[1] = 0x0
2356 12:43:35.218329 LP4Y_EN = 0x0
2357 12:43:35.221217 WORK_FSP = 0x0
2358 12:43:35.221690 WL = 0x4
2359 12:43:35.224581 RL = 0x4
2360 12:43:35.225001 BL = 0x2
2361 12:43:35.227889 RPST = 0x0
2362 12:43:35.228309 RD_PRE = 0x0
2363 12:43:35.231186 WR_PRE = 0x1
2364 12:43:35.231606 WR_PST = 0x0
2365 12:43:35.234375 DBI_WR = 0x0
2366 12:43:35.234797 DBI_RD = 0x0
2367 12:43:35.237549 OTF = 0x1
2368 12:43:35.240902 ===================================
2369 12:43:35.247823 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2370 12:43:35.248243 ==
2371 12:43:35.250911 Dram Type= 6, Freq= 0, CH_0, rank 0
2372 12:43:35.254272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2373 12:43:35.254694 ==
2374 12:43:35.257834 [Duty_Offset_Calibration]
2375 12:43:35.258257 B0:2 B1:0 CA:4
2376 12:43:35.258593
2377 12:43:35.260829 [DutyScan_Calibration_Flow] k_type=0
2378 12:43:35.270936
2379 12:43:35.271353 ==CLK 0==
2380 12:43:35.274276 Final CLK duty delay cell = 0
2381 12:43:35.277359 [0] MAX Duty = 5031%(X100), DQS PI = 12
2382 12:43:35.280923 [0] MIN Duty = 4907%(X100), DQS PI = 52
2383 12:43:35.281343 [0] AVG Duty = 4969%(X100)
2384 12:43:35.284204
2385 12:43:35.287410 CH0 CLK Duty spec in!! Max-Min= 124%
2386 12:43:35.290803 [DutyScan_Calibration_Flow] ====Done====
2387 12:43:35.291229
2388 12:43:35.294127 [DutyScan_Calibration_Flow] k_type=1
2389 12:43:35.309526
2390 12:43:35.309946 ==DQS 0 ==
2391 12:43:35.312592 Final DQS duty delay cell = 0
2392 12:43:35.316122 [0] MAX Duty = 5062%(X100), DQS PI = 12
2393 12:43:35.319461 [0] MIN Duty = 4907%(X100), DQS PI = 46
2394 12:43:35.322469 [0] AVG Duty = 4984%(X100)
2395 12:43:35.322889
2396 12:43:35.323220 ==DQS 1 ==
2397 12:43:35.325799 Final DQS duty delay cell = -4
2398 12:43:35.329099 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2399 12:43:35.332544 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2400 12:43:35.335979 [-4] AVG Duty = 4922%(X100)
2401 12:43:35.336436
2402 12:43:35.339325 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2403 12:43:35.339758
2404 12:43:35.342883 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2405 12:43:35.345970 [DutyScan_Calibration_Flow] ====Done====
2406 12:43:35.346390
2407 12:43:35.349557 [DutyScan_Calibration_Flow] k_type=3
2408 12:43:35.366942
2409 12:43:35.367439 ==DQM 0 ==
2410 12:43:35.370505 Final DQM duty delay cell = 0
2411 12:43:35.373635 [0] MAX Duty = 5124%(X100), DQS PI = 28
2412 12:43:35.376677 [0] MIN Duty = 4876%(X100), DQS PI = 48
2413 12:43:35.380197 [0] AVG Duty = 5000%(X100)
2414 12:43:35.380622
2415 12:43:35.380953 ==DQM 1 ==
2416 12:43:35.384959 Final DQM duty delay cell = 4
2417 12:43:35.386955 [4] MAX Duty = 5124%(X100), DQS PI = 50
2418 12:43:35.390549 [4] MIN Duty = 5031%(X100), DQS PI = 10
2419 12:43:35.393466 [4] AVG Duty = 5077%(X100)
2420 12:43:35.393939
2421 12:43:35.396849 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2422 12:43:35.397275
2423 12:43:35.400125 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2424 12:43:35.403606 [DutyScan_Calibration_Flow] ====Done====
2425 12:43:35.404032
2426 12:43:35.406643 [DutyScan_Calibration_Flow] k_type=2
2427 12:43:35.421933
2428 12:43:35.422468 ==DQ 0 ==
2429 12:43:35.425287 Final DQ duty delay cell = -4
2430 12:43:35.428285 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2431 12:43:35.431756 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2432 12:43:35.435213 [-4] AVG Duty = 4969%(X100)
2433 12:43:35.435750
2434 12:43:35.436087 ==DQ 1 ==
2435 12:43:35.438204 Final DQ duty delay cell = -4
2436 12:43:35.441793 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2437 12:43:35.445012 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2438 12:43:35.448717 [-4] AVG Duty = 4938%(X100)
2439 12:43:35.449293
2440 12:43:35.451525 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2441 12:43:35.451994
2442 12:43:35.455057 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2443 12:43:35.458263 [DutyScan_Calibration_Flow] ====Done====
2444 12:43:35.458731 ==
2445 12:43:35.461696 Dram Type= 6, Freq= 0, CH_1, rank 0
2446 12:43:35.465294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2447 12:43:35.465804 ==
2448 12:43:35.468465 [Duty_Offset_Calibration]
2449 12:43:35.468940 B0:1 B1:-2 CA:0
2450 12:43:35.469303
2451 12:43:35.471534 [DutyScan_Calibration_Flow] k_type=0
2452 12:43:35.482480
2453 12:43:35.482942 ==CLK 0==
2454 12:43:35.485582 Final CLK duty delay cell = 0
2455 12:43:35.489039 [0] MAX Duty = 5031%(X100), DQS PI = 18
2456 12:43:35.492198 [0] MIN Duty = 4844%(X100), DQS PI = 60
2457 12:43:35.492620 [0] AVG Duty = 4937%(X100)
2458 12:43:35.495579
2459 12:43:35.498900 CH1 CLK Duty spec in!! Max-Min= 187%
2460 12:43:35.502302 [DutyScan_Calibration_Flow] ====Done====
2461 12:43:35.502718
2462 12:43:35.505698 [DutyScan_Calibration_Flow] k_type=1
2463 12:43:35.520749
2464 12:43:35.521163 ==DQS 0 ==
2465 12:43:35.524190 Final DQS duty delay cell = -4
2466 12:43:35.527916 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2467 12:43:35.530921 [-4] MIN Duty = 4876%(X100), DQS PI = 50
2468 12:43:35.534247 [-4] AVG Duty = 4953%(X100)
2469 12:43:35.534715
2470 12:43:35.535044 ==DQS 1 ==
2471 12:43:35.537566 Final DQS duty delay cell = 0
2472 12:43:35.541007 [0] MAX Duty = 5093%(X100), DQS PI = 0
2473 12:43:35.544290 [0] MIN Duty = 4844%(X100), DQS PI = 26
2474 12:43:35.547464 [0] AVG Duty = 4968%(X100)
2475 12:43:35.547884
2476 12:43:35.550914 CH1 DQS 0 Duty spec in!! Max-Min= 155%
2477 12:43:35.551331
2478 12:43:35.554136 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2479 12:43:35.557609 [DutyScan_Calibration_Flow] ====Done====
2480 12:43:35.558052
2481 12:43:35.560987 [DutyScan_Calibration_Flow] k_type=3
2482 12:43:35.577798
2483 12:43:35.578218 ==DQM 0 ==
2484 12:43:35.580792 Final DQM duty delay cell = 0
2485 12:43:35.584256 [0] MAX Duty = 5031%(X100), DQS PI = 24
2486 12:43:35.587743 [0] MIN Duty = 4876%(X100), DQS PI = 4
2487 12:43:35.588161 [0] AVG Duty = 4953%(X100)
2488 12:43:35.591052
2489 12:43:35.591594 ==DQM 1 ==
2490 12:43:35.594301 Final DQM duty delay cell = 0
2491 12:43:35.597750 [0] MAX Duty = 5031%(X100), DQS PI = 36
2492 12:43:35.600829 [0] MIN Duty = 4907%(X100), DQS PI = 0
2493 12:43:35.601270 [0] AVG Duty = 4969%(X100)
2494 12:43:35.604294
2495 12:43:35.607461 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2496 12:43:35.607897
2497 12:43:35.611063 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2498 12:43:35.614681 [DutyScan_Calibration_Flow] ====Done====
2499 12:43:35.615127
2500 12:43:35.617566 [DutyScan_Calibration_Flow] k_type=2
2501 12:43:35.634043
2502 12:43:35.634483 ==DQ 0 ==
2503 12:43:35.637170 Final DQ duty delay cell = 0
2504 12:43:35.640537 [0] MAX Duty = 5093%(X100), DQS PI = 20
2505 12:43:35.644276 [0] MIN Duty = 4938%(X100), DQS PI = 52
2506 12:43:35.644808 [0] AVG Duty = 5015%(X100)
2507 12:43:35.645169
2508 12:43:35.647142 ==DQ 1 ==
2509 12:43:35.650654 Final DQ duty delay cell = 0
2510 12:43:35.654009 [0] MAX Duty = 5125%(X100), DQS PI = 36
2511 12:43:35.657517 [0] MIN Duty = 4969%(X100), DQS PI = 26
2512 12:43:35.658054 [0] AVG Duty = 5047%(X100)
2513 12:43:35.658621
2514 12:43:35.660618 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2515 12:43:35.661218
2516 12:43:35.664108 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2517 12:43:35.670619 [DutyScan_Calibration_Flow] ====Done====
2518 12:43:35.674189 nWR fixed to 30
2519 12:43:35.674694 [ModeRegInit_LP4] CH0 RK0
2520 12:43:35.677408 [ModeRegInit_LP4] CH0 RK1
2521 12:43:35.680631 [ModeRegInit_LP4] CH1 RK0
2522 12:43:35.681117 [ModeRegInit_LP4] CH1 RK1
2523 12:43:35.684128 match AC timing 7
2524 12:43:35.687417 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2525 12:43:35.690645 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2526 12:43:35.697927 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2527 12:43:35.700915 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2528 12:43:35.707618 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2529 12:43:35.708038 ==
2530 12:43:35.711047 Dram Type= 6, Freq= 0, CH_0, rank 0
2531 12:43:35.714136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2532 12:43:35.714574 ==
2533 12:43:35.720848 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2534 12:43:35.724286 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2535 12:43:35.734103 [CA 0] Center 40 (10~71) winsize 62
2536 12:43:35.737568 [CA 1] Center 39 (9~70) winsize 62
2537 12:43:35.740451 [CA 2] Center 36 (6~66) winsize 61
2538 12:43:35.743851 [CA 3] Center 35 (5~66) winsize 62
2539 12:43:35.747308 [CA 4] Center 34 (4~65) winsize 62
2540 12:43:35.750861 [CA 5] Center 33 (3~63) winsize 61
2541 12:43:35.751343
2542 12:43:35.754126 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2543 12:43:35.754580
2544 12:43:35.757453 [CATrainingPosCal] consider 1 rank data
2545 12:43:35.760414 u2DelayCellTimex100 = 270/100 ps
2546 12:43:35.763866 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2547 12:43:35.770690 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2548 12:43:35.773752 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2549 12:43:35.777004 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2550 12:43:35.780571 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2551 12:43:35.783818 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2552 12:43:35.784251
2553 12:43:35.787461 CA PerBit enable=1, Macro0, CA PI delay=33
2554 12:43:35.787995
2555 12:43:35.790677 [CBTSetCACLKResult] CA Dly = 33
2556 12:43:35.791099 CS Dly: 7 (0~38)
2557 12:43:35.793791 ==
2558 12:43:35.797036 Dram Type= 6, Freq= 0, CH_0, rank 1
2559 12:43:35.800623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2560 12:43:35.801047 ==
2561 12:43:35.803679 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2562 12:43:35.810253 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2563 12:43:35.820054 [CA 0] Center 40 (10~70) winsize 61
2564 12:43:35.823471 [CA 1] Center 39 (9~70) winsize 62
2565 12:43:35.826743 [CA 2] Center 35 (5~66) winsize 62
2566 12:43:35.830003 [CA 3] Center 35 (5~66) winsize 62
2567 12:43:35.833274 [CA 4] Center 34 (4~65) winsize 62
2568 12:43:35.836594 [CA 5] Center 33 (3~63) winsize 61
2569 12:43:35.837011
2570 12:43:35.839930 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2571 12:43:35.840384
2572 12:43:35.843461 [CATrainingPosCal] consider 2 rank data
2573 12:43:35.846507 u2DelayCellTimex100 = 270/100 ps
2574 12:43:35.849925 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2575 12:43:35.856466 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2576 12:43:35.859961 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2577 12:43:35.863189 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2578 12:43:35.866625 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2579 12:43:35.869948 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2580 12:43:35.870366
2581 12:43:35.873543 CA PerBit enable=1, Macro0, CA PI delay=33
2582 12:43:35.873966
2583 12:43:35.876629 [CBTSetCACLKResult] CA Dly = 33
2584 12:43:35.877045 CS Dly: 7 (0~39)
2585 12:43:35.877372
2586 12:43:35.879954 ----->DramcWriteLeveling(PI) begin...
2587 12:43:35.883451 ==
2588 12:43:35.886981 Dram Type= 6, Freq= 0, CH_0, rank 0
2589 12:43:35.890172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2590 12:43:35.890594 ==
2591 12:43:35.893535 Write leveling (Byte 0): 33 => 33
2592 12:43:35.896828 Write leveling (Byte 1): 30 => 30
2593 12:43:35.900315 DramcWriteLeveling(PI) end<-----
2594 12:43:35.900737
2595 12:43:35.901063 ==
2596 12:43:35.903592 Dram Type= 6, Freq= 0, CH_0, rank 0
2597 12:43:35.906966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2598 12:43:35.907387 ==
2599 12:43:35.910310 [Gating] SW mode calibration
2600 12:43:35.916896 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2601 12:43:35.920109 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2602 12:43:35.926879 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 12:43:35.930143 0 15 4 | B1->B0 | 2a2a 3333 | 1 0 | (0 0) (0 0)
2604 12:43:35.933636 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2605 12:43:35.940135 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2606 12:43:35.943419 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2607 12:43:35.946890 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2608 12:43:35.953447 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2609 12:43:35.956838 0 15 28 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
2610 12:43:35.960145 1 0 0 | B1->B0 | 3333 2727 | 0 1 | (0 1) (1 0)
2611 12:43:35.966476 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2612 12:43:35.969994 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2613 12:43:35.973523 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2614 12:43:35.980094 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2615 12:43:35.983545 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2616 12:43:35.986640 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2617 12:43:35.993223 1 0 28 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
2618 12:43:35.996912 1 1 0 | B1->B0 | 2525 3636 | 1 0 | (0 0) (0 0)
2619 12:43:36.000162 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 12:43:36.006780 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 12:43:36.010271 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2622 12:43:36.013557 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 12:43:36.016808 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2624 12:43:36.023595 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2625 12:43:36.026782 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2626 12:43:36.030201 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2627 12:43:36.036791 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2628 12:43:36.040268 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 12:43:36.043417 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 12:43:36.050087 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 12:43:36.053531 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 12:43:36.056884 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 12:43:36.063614 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 12:43:36.066949 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 12:43:36.070100 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 12:43:36.077081 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 12:43:36.080307 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 12:43:36.083419 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 12:43:36.090477 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 12:43:36.093444 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 12:43:36.096787 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2642 12:43:36.100081 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2643 12:43:36.107162 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2644 12:43:36.109998 Total UI for P1: 0, mck2ui 16
2645 12:43:36.113358 best dqsien dly found for B0: ( 1, 3, 30)
2646 12:43:36.116755 Total UI for P1: 0, mck2ui 16
2647 12:43:36.120150 best dqsien dly found for B1: ( 1, 4, 2)
2648 12:43:36.123624 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2649 12:43:36.126960 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2650 12:43:36.127398
2651 12:43:36.130299 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2652 12:43:36.133594 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2653 12:43:36.136907 [Gating] SW calibration Done
2654 12:43:36.137338 ==
2655 12:43:36.140104 Dram Type= 6, Freq= 0, CH_0, rank 0
2656 12:43:36.143432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2657 12:43:36.143878 ==
2658 12:43:36.146747 RX Vref Scan: 0
2659 12:43:36.147250
2660 12:43:36.147600 RX Vref 0 -> 0, step: 1
2661 12:43:36.147917
2662 12:43:36.150088 RX Delay -40 -> 252, step: 8
2663 12:43:36.153534 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2664 12:43:36.160192 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2665 12:43:36.163444 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2666 12:43:36.166876 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2667 12:43:36.170105 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2668 12:43:36.173458 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2669 12:43:36.180524 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2670 12:43:36.183768 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2671 12:43:36.187281 iDelay=200, Bit 8, Center 95 (16 ~ 175) 160
2672 12:43:36.190324 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2673 12:43:36.193981 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2674 12:43:36.197228 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2675 12:43:36.203807 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2676 12:43:36.207164 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2677 12:43:36.210150 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2678 12:43:36.213607 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2679 12:43:36.214089 ==
2680 12:43:36.217208 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 12:43:36.223703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 12:43:36.224245 ==
2683 12:43:36.224613 DQS Delay:
2684 12:43:36.227301 DQS0 = 0, DQS1 = 0
2685 12:43:36.227850 DQM Delay:
2686 12:43:36.228219 DQM0 = 112, DQM1 = 103
2687 12:43:36.230625 DQ Delay:
2688 12:43:36.233659 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2689 12:43:36.237251 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2690 12:43:36.240359 DQ8 =95, DQ9 =87, DQ10 =103, DQ11 =99
2691 12:43:36.243776 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2692 12:43:36.244226
2693 12:43:36.244560
2694 12:43:36.244927 ==
2695 12:43:36.246987 Dram Type= 6, Freq= 0, CH_0, rank 0
2696 12:43:36.250382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2697 12:43:36.250805 ==
2698 12:43:36.253608
2699 12:43:36.254054
2700 12:43:36.254411 TX Vref Scan disable
2701 12:43:36.256946 == TX Byte 0 ==
2702 12:43:36.260403 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2703 12:43:36.263545 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2704 12:43:36.266905 == TX Byte 1 ==
2705 12:43:36.270454 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2706 12:43:36.273618 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2707 12:43:36.274079 ==
2708 12:43:36.276956 Dram Type= 6, Freq= 0, CH_0, rank 0
2709 12:43:36.283514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2710 12:43:36.283938 ==
2711 12:43:36.294343 TX Vref=22, minBit 1, minWin=25, winSum=416
2712 12:43:36.297727 TX Vref=24, minBit 7, minWin=25, winSum=422
2713 12:43:36.301000 TX Vref=26, minBit 4, minWin=26, winSum=426
2714 12:43:36.304301 TX Vref=28, minBit 7, minWin=26, winSum=431
2715 12:43:36.307723 TX Vref=30, minBit 7, minWin=26, winSum=431
2716 12:43:36.311236 TX Vref=32, minBit 0, minWin=26, winSum=427
2717 12:43:36.317557 [TxChooseVref] Worse bit 7, Min win 26, Win sum 431, Final Vref 28
2718 12:43:36.318014
2719 12:43:36.321042 Final TX Range 1 Vref 28
2720 12:43:36.321578
2721 12:43:36.321953 ==
2722 12:43:36.324517 Dram Type= 6, Freq= 0, CH_0, rank 0
2723 12:43:36.327750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2724 12:43:36.328297 ==
2725 12:43:36.328635
2726 12:43:36.331067
2727 12:43:36.331514 TX Vref Scan disable
2728 12:43:36.334146 == TX Byte 0 ==
2729 12:43:36.337543 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2730 12:43:36.341028 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2731 12:43:36.344215 == TX Byte 1 ==
2732 12:43:36.348163 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2733 12:43:36.351035 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2734 12:43:36.351482
2735 12:43:36.354464 [DATLAT]
2736 12:43:36.354920 Freq=1200, CH0 RK0
2737 12:43:36.355284
2738 12:43:36.357820 DATLAT Default: 0xd
2739 12:43:36.358274 0, 0xFFFF, sum = 0
2740 12:43:36.360905 1, 0xFFFF, sum = 0
2741 12:43:36.361374 2, 0xFFFF, sum = 0
2742 12:43:36.364132 3, 0xFFFF, sum = 0
2743 12:43:36.364603 4, 0xFFFF, sum = 0
2744 12:43:36.367569 5, 0xFFFF, sum = 0
2745 12:43:36.368031 6, 0xFFFF, sum = 0
2746 12:43:36.370997 7, 0xFFFF, sum = 0
2747 12:43:36.371447 8, 0xFFFF, sum = 0
2748 12:43:36.374485 9, 0xFFFF, sum = 0
2749 12:43:36.377742 10, 0xFFFF, sum = 0
2750 12:43:36.378195 11, 0xFFFF, sum = 0
2751 12:43:36.380841 12, 0x0, sum = 1
2752 12:43:36.381389 13, 0x0, sum = 2
2753 12:43:36.384130 14, 0x0, sum = 3
2754 12:43:36.384597 15, 0x0, sum = 4
2755 12:43:36.384968 best_step = 13
2756 12:43:36.385315
2757 12:43:36.387490 ==
2758 12:43:36.391007 Dram Type= 6, Freq= 0, CH_0, rank 0
2759 12:43:36.394096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2760 12:43:36.394549 ==
2761 12:43:36.394908 RX Vref Scan: 1
2762 12:43:36.395515
2763 12:43:36.397528 Set Vref Range= 32 -> 127
2764 12:43:36.397986
2765 12:43:36.400875 RX Vref 32 -> 127, step: 1
2766 12:43:36.401319
2767 12:43:36.404252 RX Delay -37 -> 252, step: 4
2768 12:43:36.404816
2769 12:43:36.407453 Set Vref, RX VrefLevel [Byte0]: 32
2770 12:43:36.410807 [Byte1]: 32
2771 12:43:36.411253
2772 12:43:36.414363 Set Vref, RX VrefLevel [Byte0]: 33
2773 12:43:36.417375 [Byte1]: 33
2774 12:43:36.420693
2775 12:43:36.421136 Set Vref, RX VrefLevel [Byte0]: 34
2776 12:43:36.424008 [Byte1]: 34
2777 12:43:36.428845
2778 12:43:36.429292 Set Vref, RX VrefLevel [Byte0]: 35
2779 12:43:36.432025 [Byte1]: 35
2780 12:43:36.436755
2781 12:43:36.437209 Set Vref, RX VrefLevel [Byte0]: 36
2782 12:43:36.439865 [Byte1]: 36
2783 12:43:36.444836
2784 12:43:36.445341 Set Vref, RX VrefLevel [Byte0]: 37
2785 12:43:36.448256 [Byte1]: 37
2786 12:43:36.452867
2787 12:43:36.453313 Set Vref, RX VrefLevel [Byte0]: 38
2788 12:43:36.455864 [Byte1]: 38
2789 12:43:36.460823
2790 12:43:36.461320 Set Vref, RX VrefLevel [Byte0]: 39
2791 12:43:36.464113 [Byte1]: 39
2792 12:43:36.468858
2793 12:43:36.469311 Set Vref, RX VrefLevel [Byte0]: 40
2794 12:43:36.472118 [Byte1]: 40
2795 12:43:36.476788
2796 12:43:36.477238 Set Vref, RX VrefLevel [Byte0]: 41
2797 12:43:36.480125 [Byte1]: 41
2798 12:43:36.484562
2799 12:43:36.485002 Set Vref, RX VrefLevel [Byte0]: 42
2800 12:43:36.491399 [Byte1]: 42
2801 12:43:36.491935
2802 12:43:36.494547 Set Vref, RX VrefLevel [Byte0]: 43
2803 12:43:36.497916 [Byte1]: 43
2804 12:43:36.498350
2805 12:43:36.501300 Set Vref, RX VrefLevel [Byte0]: 44
2806 12:43:36.504426 [Byte1]: 44
2807 12:43:36.508957
2808 12:43:36.509380 Set Vref, RX VrefLevel [Byte0]: 45
2809 12:43:36.512122 [Byte1]: 45
2810 12:43:36.516564
2811 12:43:36.516987 Set Vref, RX VrefLevel [Byte0]: 46
2812 12:43:36.520289 [Byte1]: 46
2813 12:43:36.524828
2814 12:43:36.525351 Set Vref, RX VrefLevel [Byte0]: 47
2815 12:43:36.528180 [Byte1]: 47
2816 12:43:36.532785
2817 12:43:36.533211 Set Vref, RX VrefLevel [Byte0]: 48
2818 12:43:36.536220 [Byte1]: 48
2819 12:43:36.540989
2820 12:43:36.541413 Set Vref, RX VrefLevel [Byte0]: 49
2821 12:43:36.544044 [Byte1]: 49
2822 12:43:36.548882
2823 12:43:36.549306 Set Vref, RX VrefLevel [Byte0]: 50
2824 12:43:36.551931 [Byte1]: 50
2825 12:43:36.556603
2826 12:43:36.557128 Set Vref, RX VrefLevel [Byte0]: 51
2827 12:43:36.560208 [Byte1]: 51
2828 12:43:36.565055
2829 12:43:36.565526 Set Vref, RX VrefLevel [Byte0]: 52
2830 12:43:36.567990 [Byte1]: 52
2831 12:43:36.572678
2832 12:43:36.573099 Set Vref, RX VrefLevel [Byte0]: 53
2833 12:43:36.576291 [Byte1]: 53
2834 12:43:36.580755
2835 12:43:36.581177 Set Vref, RX VrefLevel [Byte0]: 54
2836 12:43:36.584171 [Byte1]: 54
2837 12:43:36.588776
2838 12:43:36.589298 Set Vref, RX VrefLevel [Byte0]: 55
2839 12:43:36.592063 [Byte1]: 55
2840 12:43:36.596821
2841 12:43:36.597245 Set Vref, RX VrefLevel [Byte0]: 56
2842 12:43:36.599889 [Byte1]: 56
2843 12:43:36.604799
2844 12:43:36.605223 Set Vref, RX VrefLevel [Byte0]: 57
2845 12:43:36.607904 [Byte1]: 57
2846 12:43:36.612810
2847 12:43:36.613396 Set Vref, RX VrefLevel [Byte0]: 58
2848 12:43:36.615998 [Byte1]: 58
2849 12:43:36.620863
2850 12:43:36.621285 Set Vref, RX VrefLevel [Byte0]: 59
2851 12:43:36.624087 [Byte1]: 59
2852 12:43:36.628626
2853 12:43:36.629087 Set Vref, RX VrefLevel [Byte0]: 60
2854 12:43:36.632206 [Byte1]: 60
2855 12:43:36.636521
2856 12:43:36.636945 Set Vref, RX VrefLevel [Byte0]: 61
2857 12:43:36.639922 [Byte1]: 61
2858 12:43:36.644682
2859 12:43:36.645106 Set Vref, RX VrefLevel [Byte0]: 62
2860 12:43:36.648246 [Byte1]: 62
2861 12:43:36.652909
2862 12:43:36.653329 Set Vref, RX VrefLevel [Byte0]: 63
2863 12:43:36.656295 [Byte1]: 63
2864 12:43:36.660938
2865 12:43:36.661362 Set Vref, RX VrefLevel [Byte0]: 64
2866 12:43:36.663890 [Byte1]: 64
2867 12:43:36.668848
2868 12:43:36.669263 Set Vref, RX VrefLevel [Byte0]: 65
2869 12:43:36.671948 [Byte1]: 65
2870 12:43:36.676822
2871 12:43:36.677277 Set Vref, RX VrefLevel [Byte0]: 66
2872 12:43:36.680162 [Byte1]: 66
2873 12:43:36.684761
2874 12:43:36.685209 Set Vref, RX VrefLevel [Byte0]: 67
2875 12:43:36.688214 [Byte1]: 67
2876 12:43:36.692730
2877 12:43:36.693194 Set Vref, RX VrefLevel [Byte0]: 68
2878 12:43:36.695944 [Byte1]: 68
2879 12:43:36.700641
2880 12:43:36.701086 Set Vref, RX VrefLevel [Byte0]: 69
2881 12:43:36.703943 [Byte1]: 69
2882 12:43:36.708535
2883 12:43:36.708988 Set Vref, RX VrefLevel [Byte0]: 70
2884 12:43:36.712102 [Byte1]: 70
2885 12:43:36.716841
2886 12:43:36.717282 Set Vref, RX VrefLevel [Byte0]: 71
2887 12:43:36.720093 [Byte1]: 71
2888 12:43:36.724845
2889 12:43:36.725302 Set Vref, RX VrefLevel [Byte0]: 72
2890 12:43:36.727979 [Byte1]: 72
2891 12:43:36.732845
2892 12:43:36.733389 Set Vref, RX VrefLevel [Byte0]: 73
2893 12:43:36.736078 [Byte1]: 73
2894 12:43:36.740700
2895 12:43:36.741143 Set Vref, RX VrefLevel [Byte0]: 74
2896 12:43:36.744038 [Byte1]: 74
2897 12:43:36.748693
2898 12:43:36.749144 Set Vref, RX VrefLevel [Byte0]: 75
2899 12:43:36.755617 [Byte1]: 75
2900 12:43:36.756163
2901 12:43:36.758453 Final RX Vref Byte 0 = 60 to rank0
2902 12:43:36.761799 Final RX Vref Byte 1 = 52 to rank0
2903 12:43:36.765389 Final RX Vref Byte 0 = 60 to rank1
2904 12:43:36.768625 Final RX Vref Byte 1 = 52 to rank1==
2905 12:43:36.771985 Dram Type= 6, Freq= 0, CH_0, rank 0
2906 12:43:36.775252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2907 12:43:36.775671 ==
2908 12:43:36.776000 DQS Delay:
2909 12:43:36.779020 DQS0 = 0, DQS1 = 0
2910 12:43:36.779545 DQM Delay:
2911 12:43:36.781987 DQM0 = 112, DQM1 = 101
2912 12:43:36.782403 DQ Delay:
2913 12:43:36.785249 DQ0 =112, DQ1 =110, DQ2 =110, DQ3 =108
2914 12:43:36.788507 DQ4 =112, DQ5 =104, DQ6 =120, DQ7 =120
2915 12:43:36.791910 DQ8 =92, DQ9 =84, DQ10 =104, DQ11 =94
2916 12:43:36.795424 DQ12 =106, DQ13 =106, DQ14 =116, DQ15 =110
2917 12:43:36.796009
2918 12:43:36.796576
2919 12:43:36.805255 [DQSOSCAuto] RK0, (LSB)MR18= 0xfaf9, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2920 12:43:36.808523 CH0 RK0: MR19=303, MR18=FAF9
2921 12:43:36.815177 CH0_RK0: MR19=0x303, MR18=0xFAF9, DQSOSC=412, MR23=63, INC=38, DEC=25
2922 12:43:36.815648
2923 12:43:36.818483 ----->DramcWriteLeveling(PI) begin...
2924 12:43:36.818914 ==
2925 12:43:36.821948 Dram Type= 6, Freq= 0, CH_0, rank 1
2926 12:43:36.825254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2927 12:43:36.825722 ==
2928 12:43:36.828435 Write leveling (Byte 0): 35 => 35
2929 12:43:36.831874 Write leveling (Byte 1): 30 => 30
2930 12:43:36.835288 DramcWriteLeveling(PI) end<-----
2931 12:43:36.835705
2932 12:43:36.836030 ==
2933 12:43:36.838208 Dram Type= 6, Freq= 0, CH_0, rank 1
2934 12:43:36.841328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 12:43:36.841411 ==
2936 12:43:36.844661 [Gating] SW mode calibration
2937 12:43:36.851366 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2938 12:43:36.858133 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2939 12:43:36.861453 0 15 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
2940 12:43:36.864801 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2941 12:43:36.871501 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2942 12:43:36.875203 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2943 12:43:36.878172 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2944 12:43:36.881636 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2945 12:43:36.888011 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2946 12:43:36.891368 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
2947 12:43:36.894965 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2948 12:43:36.901387 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2949 12:43:36.904934 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2950 12:43:36.908406 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2951 12:43:36.915195 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2952 12:43:36.918256 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2953 12:43:36.921720 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2954 12:43:36.928170 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2955 12:43:36.931591 1 1 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2956 12:43:36.935035 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2957 12:43:36.941567 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2958 12:43:36.944912 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2959 12:43:36.948188 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2960 12:43:36.954997 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2961 12:43:36.958290 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2962 12:43:36.961572 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2963 12:43:36.968297 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 12:43:36.971782 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2965 12:43:36.974953 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2966 12:43:36.978584 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2967 12:43:36.985386 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2968 12:43:36.988441 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2969 12:43:36.991788 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2970 12:43:36.998475 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2971 12:43:37.001885 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2972 12:43:37.005115 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2973 12:43:37.012049 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2974 12:43:37.015483 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 12:43:37.018549 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 12:43:37.025241 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 12:43:37.028418 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2978 12:43:37.031933 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2979 12:43:37.038709 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2980 12:43:37.039126 Total UI for P1: 0, mck2ui 16
2981 12:43:37.045222 best dqsien dly found for B0: ( 1, 3, 26)
2982 12:43:37.045685 Total UI for P1: 0, mck2ui 16
2983 12:43:37.048498 best dqsien dly found for B1: ( 1, 3, 30)
2984 12:43:37.055196 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2985 12:43:37.058654 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2986 12:43:37.059070
2987 12:43:37.061942 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2988 12:43:37.065196 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2989 12:43:37.068575 [Gating] SW calibration Done
2990 12:43:37.069152 ==
2991 12:43:37.071755 Dram Type= 6, Freq= 0, CH_0, rank 1
2992 12:43:37.074929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2993 12:43:37.075363 ==
2994 12:43:37.078375 RX Vref Scan: 0
2995 12:43:37.078788
2996 12:43:37.079141 RX Vref 0 -> 0, step: 1
2997 12:43:37.079635
2998 12:43:37.081953 RX Delay -40 -> 252, step: 8
2999 12:43:37.085236 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
3000 12:43:37.088568 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
3001 12:43:37.095342 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3002 12:43:37.098559 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3003 12:43:37.101847 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3004 12:43:37.105219 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
3005 12:43:37.108561 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3006 12:43:37.114902 iDelay=200, Bit 7, Center 119 (40 ~ 199) 160
3007 12:43:37.118409 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3008 12:43:37.122021 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
3009 12:43:37.124872 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3010 12:43:37.128281 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
3011 12:43:37.135047 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3012 12:43:37.138617 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3013 12:43:37.141642 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3014 12:43:37.145188 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
3015 12:43:37.145645 ==
3016 12:43:37.148515 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 12:43:37.154923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 12:43:37.155353 ==
3019 12:43:37.155686 DQS Delay:
3020 12:43:37.155996 DQS0 = 0, DQS1 = 0
3021 12:43:37.158269 DQM Delay:
3022 12:43:37.158689 DQM0 = 111, DQM1 = 101
3023 12:43:37.161931 DQ Delay:
3024 12:43:37.164812 DQ0 =107, DQ1 =111, DQ2 =107, DQ3 =107
3025 12:43:37.168406 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =119
3026 12:43:37.171748 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
3027 12:43:37.174993 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =107
3028 12:43:37.175425
3029 12:43:37.175757
3030 12:43:37.176065 ==
3031 12:43:37.178269 Dram Type= 6, Freq= 0, CH_0, rank 1
3032 12:43:37.181560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3033 12:43:37.181994 ==
3034 12:43:37.182332
3035 12:43:37.185115
3036 12:43:37.185593 TX Vref Scan disable
3037 12:43:37.188399 == TX Byte 0 ==
3038 12:43:37.191710 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3039 12:43:37.194801 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3040 12:43:37.198380 == TX Byte 1 ==
3041 12:43:37.201885 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3042 12:43:37.204919 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3043 12:43:37.205409 ==
3044 12:43:37.208349 Dram Type= 6, Freq= 0, CH_0, rank 1
3045 12:43:37.214703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3046 12:43:37.215165 ==
3047 12:43:37.225789 TX Vref=22, minBit 1, minWin=26, winSum=426
3048 12:43:37.229092 TX Vref=24, minBit 2, minWin=26, winSum=428
3049 12:43:37.232421 TX Vref=26, minBit 7, minWin=26, winSum=435
3050 12:43:37.235927 TX Vref=28, minBit 0, minWin=27, winSum=438
3051 12:43:37.239380 TX Vref=30, minBit 1, minWin=26, winSum=437
3052 12:43:37.242627 TX Vref=32, minBit 0, minWin=27, winSum=440
3053 12:43:37.249181 [TxChooseVref] Worse bit 0, Min win 27, Win sum 440, Final Vref 32
3054 12:43:37.249738
3055 12:43:37.252405 Final TX Range 1 Vref 32
3056 12:43:37.252822
3057 12:43:37.253152 ==
3058 12:43:37.255707 Dram Type= 6, Freq= 0, CH_0, rank 1
3059 12:43:37.259126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3060 12:43:37.259694 ==
3061 12:43:37.260195
3062 12:43:37.262455
3063 12:43:37.262960 TX Vref Scan disable
3064 12:43:37.265672 == TX Byte 0 ==
3065 12:43:37.269256 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3066 12:43:37.272300 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3067 12:43:37.275820 == TX Byte 1 ==
3068 12:43:37.279048 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3069 12:43:37.282545 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3070 12:43:37.282974
3071 12:43:37.285924 [DATLAT]
3072 12:43:37.286341 Freq=1200, CH0 RK1
3073 12:43:37.286671
3074 12:43:37.289081 DATLAT Default: 0xd
3075 12:43:37.289608 0, 0xFFFF, sum = 0
3076 12:43:37.292852 1, 0xFFFF, sum = 0
3077 12:43:37.293272 2, 0xFFFF, sum = 0
3078 12:43:37.295655 3, 0xFFFF, sum = 0
3079 12:43:37.296074 4, 0xFFFF, sum = 0
3080 12:43:37.299181 5, 0xFFFF, sum = 0
3081 12:43:37.299935 6, 0xFFFF, sum = 0
3082 12:43:37.302531 7, 0xFFFF, sum = 0
3083 12:43:37.305869 8, 0xFFFF, sum = 0
3084 12:43:37.306292 9, 0xFFFF, sum = 0
3085 12:43:37.309035 10, 0xFFFF, sum = 0
3086 12:43:37.309615 11, 0xFFFF, sum = 0
3087 12:43:37.312507 12, 0x0, sum = 1
3088 12:43:37.312926 13, 0x0, sum = 2
3089 12:43:37.315961 14, 0x0, sum = 3
3090 12:43:37.316380 15, 0x0, sum = 4
3091 12:43:37.316717 best_step = 13
3092 12:43:37.317075
3093 12:43:37.319334 ==
3094 12:43:37.322373 Dram Type= 6, Freq= 0, CH_0, rank 1
3095 12:43:37.325855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3096 12:43:37.326271 ==
3097 12:43:37.326597 RX Vref Scan: 0
3098 12:43:37.326902
3099 12:43:37.329059 RX Vref 0 -> 0, step: 1
3100 12:43:37.329502
3101 12:43:37.332708 RX Delay -37 -> 252, step: 4
3102 12:43:37.335741 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3103 12:43:37.342275 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3104 12:43:37.345869 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3105 12:43:37.348995 iDelay=195, Bit 3, Center 110 (39 ~ 182) 144
3106 12:43:37.352476 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3107 12:43:37.355919 iDelay=195, Bit 5, Center 102 (35 ~ 170) 136
3108 12:43:37.359006 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3109 12:43:37.365975 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3110 12:43:37.369263 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3111 12:43:37.372410 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3112 12:43:37.375984 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3113 12:43:37.378939 iDelay=195, Bit 11, Center 92 (23 ~ 162) 140
3114 12:43:37.385693 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3115 12:43:37.389064 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3116 12:43:37.392524 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3117 12:43:37.395618 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3118 12:43:37.396059 ==
3119 12:43:37.398833 Dram Type= 6, Freq= 0, CH_0, rank 1
3120 12:43:37.405604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3121 12:43:37.406050 ==
3122 12:43:37.406394 DQS Delay:
3123 12:43:37.409030 DQS0 = 0, DQS1 = 0
3124 12:43:37.409525 DQM Delay:
3125 12:43:37.409890 DQM0 = 111, DQM1 = 101
3126 12:43:37.412235 DQ Delay:
3127 12:43:37.415609 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =110
3128 12:43:37.418903 DQ4 =112, DQ5 =102, DQ6 =120, DQ7 =118
3129 12:43:37.422092 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =92
3130 12:43:37.425553 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110
3131 12:43:37.426024
3132 12:43:37.426382
3133 12:43:37.435500 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3134 12:43:37.435943 CH0 RK1: MR19=403, MR18=10F7
3135 12:43:37.442315 CH0_RK1: MR19=0x403, MR18=0x10F7, DQSOSC=403, MR23=63, INC=40, DEC=26
3136 12:43:37.445315 [RxdqsGatingPostProcess] freq 1200
3137 12:43:37.452023 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3138 12:43:37.455239 best DQS0 dly(2T, 0.5T) = (0, 11)
3139 12:43:37.458906 best DQS1 dly(2T, 0.5T) = (0, 12)
3140 12:43:37.461955 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3141 12:43:37.465462 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3142 12:43:37.466012 best DQS0 dly(2T, 0.5T) = (0, 11)
3143 12:43:37.468662 best DQS1 dly(2T, 0.5T) = (0, 11)
3144 12:43:37.471947 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3145 12:43:37.475488 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3146 12:43:37.478847 Pre-setting of DQS Precalculation
3147 12:43:37.485429 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3148 12:43:37.485913 ==
3149 12:43:37.488603 Dram Type= 6, Freq= 0, CH_1, rank 0
3150 12:43:37.491970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3151 12:43:37.492405 ==
3152 12:43:37.498649 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3153 12:43:37.502185 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3154 12:43:37.511894 [CA 0] Center 37 (7~67) winsize 61
3155 12:43:37.515312 [CA 1] Center 37 (7~68) winsize 62
3156 12:43:37.518466 [CA 2] Center 34 (5~64) winsize 60
3157 12:43:37.522003 [CA 3] Center 33 (3~64) winsize 62
3158 12:43:37.525216 [CA 4] Center 34 (4~64) winsize 61
3159 12:43:37.528564 [CA 5] Center 33 (3~63) winsize 61
3160 12:43:37.528989
3161 12:43:37.532052 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3162 12:43:37.532619
3163 12:43:37.535163 [CATrainingPosCal] consider 1 rank data
3164 12:43:37.538449 u2DelayCellTimex100 = 270/100 ps
3165 12:43:37.541900 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3166 12:43:37.545203 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3167 12:43:37.551850 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3168 12:43:37.554964 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3169 12:43:37.558482 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3170 12:43:37.561869 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3171 12:43:37.562340
3172 12:43:37.564967 CA PerBit enable=1, Macro0, CA PI delay=33
3173 12:43:37.565541
3174 12:43:37.568375 [CBTSetCACLKResult] CA Dly = 33
3175 12:43:37.568813 CS Dly: 5 (0~36)
3176 12:43:37.571614 ==
3177 12:43:37.572113 Dram Type= 6, Freq= 0, CH_1, rank 1
3178 12:43:37.578413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3179 12:43:37.578903 ==
3180 12:43:37.581786 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3181 12:43:37.588252 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3182 12:43:37.597389 [CA 0] Center 37 (7~67) winsize 61
3183 12:43:37.600711 [CA 1] Center 37 (7~68) winsize 62
3184 12:43:37.604133 [CA 2] Center 34 (4~65) winsize 62
3185 12:43:37.607458 [CA 3] Center 33 (3~64) winsize 62
3186 12:43:37.610499 [CA 4] Center 34 (4~64) winsize 61
3187 12:43:37.614038 [CA 5] Center 32 (2~63) winsize 62
3188 12:43:37.614483
3189 12:43:37.617581 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3190 12:43:37.618015
3191 12:43:37.620582 [CATrainingPosCal] consider 2 rank data
3192 12:43:37.624098 u2DelayCellTimex100 = 270/100 ps
3193 12:43:37.627611 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3194 12:43:37.630764 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3195 12:43:37.637129 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3196 12:43:37.640489 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3197 12:43:37.643883 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3198 12:43:37.647534 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3199 12:43:37.647979
3200 12:43:37.651039 CA PerBit enable=1, Macro0, CA PI delay=33
3201 12:43:37.651476
3202 12:43:37.654115 [CBTSetCACLKResult] CA Dly = 33
3203 12:43:37.654549 CS Dly: 7 (0~40)
3204 12:43:37.654908
3205 12:43:37.657464 ----->DramcWriteLeveling(PI) begin...
3206 12:43:37.660743 ==
3207 12:43:37.661174 Dram Type= 6, Freq= 0, CH_1, rank 0
3208 12:43:37.667395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3209 12:43:37.667973 ==
3210 12:43:37.670855 Write leveling (Byte 0): 24 => 24
3211 12:43:37.673998 Write leveling (Byte 1): 30 => 30
3212 12:43:37.677425 DramcWriteLeveling(PI) end<-----
3213 12:43:37.677872
3214 12:43:37.678248 ==
3215 12:43:37.680523 Dram Type= 6, Freq= 0, CH_1, rank 0
3216 12:43:37.684014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3217 12:43:37.684434 ==
3218 12:43:37.687552 [Gating] SW mode calibration
3219 12:43:37.694197 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3220 12:43:37.697455 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3221 12:43:37.704360 0 15 0 | B1->B0 | 3131 2c2c | 0 0 | (0 0) (0 0)
3222 12:43:37.707385 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3223 12:43:37.710852 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3224 12:43:37.717561 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3225 12:43:37.720646 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3226 12:43:37.724138 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3227 12:43:37.730849 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3228 12:43:37.734303 0 15 28 | B1->B0 | 2d2d 2e2e | 1 0 | (1 0) (0 1)
3229 12:43:37.737395 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3230 12:43:37.744026 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3231 12:43:37.747510 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3232 12:43:37.750906 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3233 12:43:37.757289 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3234 12:43:37.760725 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3235 12:43:37.763886 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3236 12:43:37.770735 1 0 28 | B1->B0 | 3d3d 3938 | 0 1 | (0 0) (0 0)
3237 12:43:37.773993 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3238 12:43:37.777307 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3239 12:43:37.783884 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3240 12:43:37.787300 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3241 12:43:37.790953 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3242 12:43:37.793816 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3243 12:43:37.800543 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3244 12:43:37.803946 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3245 12:43:37.807189 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3246 12:43:37.813972 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3247 12:43:37.817437 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3248 12:43:37.820534 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3249 12:43:37.827463 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3250 12:43:37.830792 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3251 12:43:37.833738 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3252 12:43:37.840629 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3253 12:43:37.844153 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3254 12:43:37.847632 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3255 12:43:37.853926 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3256 12:43:37.857326 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3257 12:43:37.860690 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3258 12:43:37.867096 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3259 12:43:37.870684 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3260 12:43:37.874008 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3261 12:43:37.877557 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3262 12:43:37.880713 Total UI for P1: 0, mck2ui 16
3263 12:43:37.884229 best dqsien dly found for B0: ( 1, 3, 28)
3264 12:43:37.887643 Total UI for P1: 0, mck2ui 16
3265 12:43:37.890796 best dqsien dly found for B1: ( 1, 3, 26)
3266 12:43:37.894181 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3267 12:43:37.897820 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3268 12:43:37.900758
3269 12:43:37.904226 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3270 12:43:37.907721 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3271 12:43:37.911024 [Gating] SW calibration Done
3272 12:43:37.911469 ==
3273 12:43:37.914013 Dram Type= 6, Freq= 0, CH_1, rank 0
3274 12:43:37.917639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3275 12:43:37.918060 ==
3276 12:43:37.918386 RX Vref Scan: 0
3277 12:43:37.918690
3278 12:43:37.920646 RX Vref 0 -> 0, step: 1
3279 12:43:37.921060
3280 12:43:37.924160 RX Delay -40 -> 252, step: 8
3281 12:43:37.927520 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3282 12:43:37.930890 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3283 12:43:37.937595 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3284 12:43:37.940738 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3285 12:43:37.944165 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3286 12:43:37.947452 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3287 12:43:37.950860 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3288 12:43:37.957176 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3289 12:43:37.960640 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3290 12:43:37.964236 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3291 12:43:37.967584 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3292 12:43:37.970663 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3293 12:43:37.973942 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3294 12:43:37.980587 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3295 12:43:37.984091 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3296 12:43:37.987409 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3297 12:43:37.987828 ==
3298 12:43:37.990555 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 12:43:37.994136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 12:43:37.997596 ==
3301 12:43:37.998015 DQS Delay:
3302 12:43:37.998343 DQS0 = 0, DQS1 = 0
3303 12:43:38.000625 DQM Delay:
3304 12:43:38.001062 DQM0 = 115, DQM1 = 106
3305 12:43:38.004010 DQ Delay:
3306 12:43:38.007539 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3307 12:43:38.010886 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3308 12:43:38.014069 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =103
3309 12:43:38.017594 DQ12 =111, DQ13 =115, DQ14 =111, DQ15 =111
3310 12:43:38.018029
3311 12:43:38.018363
3312 12:43:38.018820 ==
3313 12:43:38.020678 Dram Type= 6, Freq= 0, CH_1, rank 0
3314 12:43:38.024341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3315 12:43:38.024760 ==
3316 12:43:38.025085
3317 12:43:38.025388
3318 12:43:38.027274 TX Vref Scan disable
3319 12:43:38.030865 == TX Byte 0 ==
3320 12:43:38.034273 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3321 12:43:38.037371 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3322 12:43:38.040772 == TX Byte 1 ==
3323 12:43:38.044273 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3324 12:43:38.047623 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3325 12:43:38.048041 ==
3326 12:43:38.050865 Dram Type= 6, Freq= 0, CH_1, rank 0
3327 12:43:38.054242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3328 12:43:38.057581 ==
3329 12:43:38.067798 TX Vref=22, minBit 1, minWin=25, winSum=415
3330 12:43:38.071120 TX Vref=24, minBit 8, minWin=25, winSum=420
3331 12:43:38.074452 TX Vref=26, minBit 1, minWin=26, winSum=427
3332 12:43:38.077809 TX Vref=28, minBit 8, minWin=26, winSum=433
3333 12:43:38.081544 TX Vref=30, minBit 1, minWin=26, winSum=430
3334 12:43:38.084472 TX Vref=32, minBit 3, minWin=26, winSum=429
3335 12:43:38.091360 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 28
3336 12:43:38.091777
3337 12:43:38.094575 Final TX Range 1 Vref 28
3338 12:43:38.094993
3339 12:43:38.095321 ==
3340 12:43:38.098130 Dram Type= 6, Freq= 0, CH_1, rank 0
3341 12:43:38.101529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3342 12:43:38.101990 ==
3343 12:43:38.102321
3344 12:43:38.102631
3345 12:43:38.104911 TX Vref Scan disable
3346 12:43:38.108070 == TX Byte 0 ==
3347 12:43:38.111270 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3348 12:43:38.114799 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3349 12:43:38.117918 == TX Byte 1 ==
3350 12:43:38.121588 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3351 12:43:38.124877 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3352 12:43:38.125291
3353 12:43:38.128031 [DATLAT]
3354 12:43:38.128443 Freq=1200, CH1 RK0
3355 12:43:38.128772
3356 12:43:38.131499 DATLAT Default: 0xd
3357 12:43:38.131912 0, 0xFFFF, sum = 0
3358 12:43:38.134508 1, 0xFFFF, sum = 0
3359 12:43:38.134930 2, 0xFFFF, sum = 0
3360 12:43:38.137746 3, 0xFFFF, sum = 0
3361 12:43:38.138170 4, 0xFFFF, sum = 0
3362 12:43:38.141157 5, 0xFFFF, sum = 0
3363 12:43:38.141615 6, 0xFFFF, sum = 0
3364 12:43:38.144565 7, 0xFFFF, sum = 0
3365 12:43:38.144984 8, 0xFFFF, sum = 0
3366 12:43:38.147771 9, 0xFFFF, sum = 0
3367 12:43:38.151141 10, 0xFFFF, sum = 0
3368 12:43:38.151707 11, 0xFFFF, sum = 0
3369 12:43:38.154494 12, 0x0, sum = 1
3370 12:43:38.154926 13, 0x0, sum = 2
3371 12:43:38.155261 14, 0x0, sum = 3
3372 12:43:38.157859 15, 0x0, sum = 4
3373 12:43:38.158281 best_step = 13
3374 12:43:38.158647
3375 12:43:38.159005 ==
3376 12:43:38.161230 Dram Type= 6, Freq= 0, CH_1, rank 0
3377 12:43:38.167853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3378 12:43:38.168314 ==
3379 12:43:38.168649 RX Vref Scan: 1
3380 12:43:38.168957
3381 12:43:38.171273 Set Vref Range= 32 -> 127
3382 12:43:38.171684
3383 12:43:38.174684 RX Vref 32 -> 127, step: 1
3384 12:43:38.175126
3385 12:43:38.178280 RX Delay -21 -> 252, step: 4
3386 12:43:38.178694
3387 12:43:38.179021 Set Vref, RX VrefLevel [Byte0]: 32
3388 12:43:38.181674 [Byte1]: 32
3389 12:43:38.186705
3390 12:43:38.187127 Set Vref, RX VrefLevel [Byte0]: 33
3391 12:43:38.189568 [Byte1]: 33
3392 12:43:38.193952
3393 12:43:38.194366 Set Vref, RX VrefLevel [Byte0]: 34
3394 12:43:38.197327 [Byte1]: 34
3395 12:43:38.201878
3396 12:43:38.202289 Set Vref, RX VrefLevel [Byte0]: 35
3397 12:43:38.205432 [Byte1]: 35
3398 12:43:38.209965
3399 12:43:38.210402 Set Vref, RX VrefLevel [Byte0]: 36
3400 12:43:38.213186 [Byte1]: 36
3401 12:43:38.218042
3402 12:43:38.218454 Set Vref, RX VrefLevel [Byte0]: 37
3403 12:43:38.220967 [Byte1]: 37
3404 12:43:38.225797
3405 12:43:38.226210 Set Vref, RX VrefLevel [Byte0]: 38
3406 12:43:38.228860 [Byte1]: 38
3407 12:43:38.233569
3408 12:43:38.233983 Set Vref, RX VrefLevel [Byte0]: 39
3409 12:43:38.237090 [Byte1]: 39
3410 12:43:38.241697
3411 12:43:38.242106 Set Vref, RX VrefLevel [Byte0]: 40
3412 12:43:38.244802 [Byte1]: 40
3413 12:43:38.249471
3414 12:43:38.249923 Set Vref, RX VrefLevel [Byte0]: 41
3415 12:43:38.252931 [Byte1]: 41
3416 12:43:38.257529
3417 12:43:38.257943 Set Vref, RX VrefLevel [Byte0]: 42
3418 12:43:38.260759 [Byte1]: 42
3419 12:43:38.265258
3420 12:43:38.265817 Set Vref, RX VrefLevel [Byte0]: 43
3421 12:43:38.268658 [Byte1]: 43
3422 12:43:38.273443
3423 12:43:38.273946 Set Vref, RX VrefLevel [Byte0]: 44
3424 12:43:38.276550 [Byte1]: 44
3425 12:43:38.281369
3426 12:43:38.281996 Set Vref, RX VrefLevel [Byte0]: 45
3427 12:43:38.284688 [Byte1]: 45
3428 12:43:38.289164
3429 12:43:38.289807 Set Vref, RX VrefLevel [Byte0]: 46
3430 12:43:38.292506 [Byte1]: 46
3431 12:43:38.297173
3432 12:43:38.297668 Set Vref, RX VrefLevel [Byte0]: 47
3433 12:43:38.300498 [Byte1]: 47
3434 12:43:38.304834
3435 12:43:38.305251 Set Vref, RX VrefLevel [Byte0]: 48
3436 12:43:38.308093 [Byte1]: 48
3437 12:43:38.312974
3438 12:43:38.313538 Set Vref, RX VrefLevel [Byte0]: 49
3439 12:43:38.316166 [Byte1]: 49
3440 12:43:38.320830
3441 12:43:38.321265 Set Vref, RX VrefLevel [Byte0]: 50
3442 12:43:38.324213 [Byte1]: 50
3443 12:43:38.328460
3444 12:43:38.329022 Set Vref, RX VrefLevel [Byte0]: 51
3445 12:43:38.331879 [Byte1]: 51
3446 12:43:38.336721
3447 12:43:38.337325 Set Vref, RX VrefLevel [Byte0]: 52
3448 12:43:38.339877 [Byte1]: 52
3449 12:43:38.344621
3450 12:43:38.345043 Set Vref, RX VrefLevel [Byte0]: 53
3451 12:43:38.348002 [Byte1]: 53
3452 12:43:38.352438
3453 12:43:38.352855 Set Vref, RX VrefLevel [Byte0]: 54
3454 12:43:38.355874 [Byte1]: 54
3455 12:43:38.360171
3456 12:43:38.360715 Set Vref, RX VrefLevel [Byte0]: 55
3457 12:43:38.363596 [Byte1]: 55
3458 12:43:38.368302
3459 12:43:38.368757 Set Vref, RX VrefLevel [Byte0]: 56
3460 12:43:38.371586 [Byte1]: 56
3461 12:43:38.376205
3462 12:43:38.376624 Set Vref, RX VrefLevel [Byte0]: 57
3463 12:43:38.379358 [Byte1]: 57
3464 12:43:38.384021
3465 12:43:38.384450 Set Vref, RX VrefLevel [Byte0]: 58
3466 12:43:38.387473 [Byte1]: 58
3467 12:43:38.392035
3468 12:43:38.392448 Set Vref, RX VrefLevel [Byte0]: 59
3469 12:43:38.395480 [Byte1]: 59
3470 12:43:38.400015
3471 12:43:38.400449 Set Vref, RX VrefLevel [Byte0]: 60
3472 12:43:38.403354 [Byte1]: 60
3473 12:43:38.407833
3474 12:43:38.408250 Set Vref, RX VrefLevel [Byte0]: 61
3475 12:43:38.411092 [Byte1]: 61
3476 12:43:38.415795
3477 12:43:38.416211 Set Vref, RX VrefLevel [Byte0]: 62
3478 12:43:38.418999 [Byte1]: 62
3479 12:43:38.423552
3480 12:43:38.423965 Set Vref, RX VrefLevel [Byte0]: 63
3481 12:43:38.426868 [Byte1]: 63
3482 12:43:38.431930
3483 12:43:38.432347 Set Vref, RX VrefLevel [Byte0]: 64
3484 12:43:38.435023 [Byte1]: 64
3485 12:43:38.439387
3486 12:43:38.439797 Set Vref, RX VrefLevel [Byte0]: 65
3487 12:43:38.442680 [Byte1]: 65
3488 12:43:38.447581
3489 12:43:38.447996 Set Vref, RX VrefLevel [Byte0]: 66
3490 12:43:38.450714 [Byte1]: 66
3491 12:43:38.455344
3492 12:43:38.455756 Set Vref, RX VrefLevel [Byte0]: 67
3493 12:43:38.458536 [Byte1]: 67
3494 12:43:38.463261
3495 12:43:38.463675 Set Vref, RX VrefLevel [Byte0]: 68
3496 12:43:38.466854 [Byte1]: 68
3497 12:43:38.471044
3498 12:43:38.471504 Set Vref, RX VrefLevel [Byte0]: 69
3499 12:43:38.474559 [Byte1]: 69
3500 12:43:38.479024
3501 12:43:38.479463 Set Vref, RX VrefLevel [Byte0]: 70
3502 12:43:38.482581 [Byte1]: 70
3503 12:43:38.487102
3504 12:43:38.487515 Final RX Vref Byte 0 = 54 to rank0
3505 12:43:38.490694 Final RX Vref Byte 1 = 48 to rank0
3506 12:43:38.493659 Final RX Vref Byte 0 = 54 to rank1
3507 12:43:38.497129 Final RX Vref Byte 1 = 48 to rank1==
3508 12:43:38.500523 Dram Type= 6, Freq= 0, CH_1, rank 0
3509 12:43:38.507181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3510 12:43:38.507629 ==
3511 12:43:38.507987 DQS Delay:
3512 12:43:38.508306 DQS0 = 0, DQS1 = 0
3513 12:43:38.510473 DQM Delay:
3514 12:43:38.510888 DQM0 = 115, DQM1 = 105
3515 12:43:38.513417 DQ Delay:
3516 12:43:38.516809 DQ0 =116, DQ1 =112, DQ2 =106, DQ3 =112
3517 12:43:38.520119 DQ4 =112, DQ5 =122, DQ6 =128, DQ7 =112
3518 12:43:38.523516 DQ8 =92, DQ9 =96, DQ10 =104, DQ11 =100
3519 12:43:38.527075 DQ12 =112, DQ13 =112, DQ14 =114, DQ15 =112
3520 12:43:38.527492
3521 12:43:38.527822
3522 12:43:38.533553 [DQSOSCAuto] RK0, (LSB)MR18= 0xeff6, (MSB)MR19= 0x303, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
3523 12:43:38.536916 CH1 RK0: MR19=303, MR18=EFF6
3524 12:43:38.543718 CH1_RK0: MR19=0x303, MR18=0xEFF6, DQSOSC=414, MR23=63, INC=38, DEC=25
3525 12:43:38.544175
3526 12:43:38.547104 ----->DramcWriteLeveling(PI) begin...
3527 12:43:38.547529 ==
3528 12:43:38.550614 Dram Type= 6, Freq= 0, CH_1, rank 1
3529 12:43:38.553588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3530 12:43:38.557107 ==
3531 12:43:38.557563 Write leveling (Byte 0): 24 => 24
3532 12:43:38.560434 Write leveling (Byte 1): 27 => 27
3533 12:43:38.563458 DramcWriteLeveling(PI) end<-----
3534 12:43:38.564038
3535 12:43:38.564510 ==
3536 12:43:38.566845 Dram Type= 6, Freq= 0, CH_1, rank 1
3537 12:43:38.573403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3538 12:43:38.573930 ==
3539 12:43:38.574272 [Gating] SW mode calibration
3540 12:43:38.583660 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3541 12:43:38.586754 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3542 12:43:38.590323 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3543 12:43:38.596884 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3544 12:43:38.600131 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3545 12:43:38.603482 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3546 12:43:38.610378 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3547 12:43:38.613539 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3548 12:43:38.616665 0 15 24 | B1->B0 | 3434 2727 | 0 0 | (0 0) (0 0)
3549 12:43:38.623415 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
3550 12:43:38.626875 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3551 12:43:38.630135 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3552 12:43:38.636716 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3553 12:43:38.639987 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3554 12:43:38.643381 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3555 12:43:38.649837 1 0 20 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
3556 12:43:38.653337 1 0 24 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
3557 12:43:38.656703 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3558 12:43:38.663281 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3559 12:43:38.666642 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3560 12:43:38.669893 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3561 12:43:38.676436 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3562 12:43:38.679986 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3563 12:43:38.683133 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3564 12:43:38.689930 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3565 12:43:38.693248 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3566 12:43:38.696365 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3567 12:43:38.702889 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3568 12:43:38.706364 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3569 12:43:38.709645 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3570 12:43:38.716495 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3571 12:43:38.719444 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3572 12:43:38.722736 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3573 12:43:38.729494 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3574 12:43:38.732840 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3575 12:43:38.736072 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3576 12:43:38.742676 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3577 12:43:38.746262 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3578 12:43:38.749530 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3579 12:43:38.755988 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3580 12:43:38.759513 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3581 12:43:38.762848 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3582 12:43:38.769348 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3583 12:43:38.769824 Total UI for P1: 0, mck2ui 16
3584 12:43:38.772365 best dqsien dly found for B0: ( 1, 3, 26)
3585 12:43:38.775982 Total UI for P1: 0, mck2ui 16
3586 12:43:38.779335 best dqsien dly found for B1: ( 1, 3, 28)
3587 12:43:38.782591 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3588 12:43:38.789008 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3589 12:43:38.789425
3590 12:43:38.792617 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3591 12:43:38.795912 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3592 12:43:38.799305 [Gating] SW calibration Done
3593 12:43:38.799723 ==
3594 12:43:38.802297 Dram Type= 6, Freq= 0, CH_1, rank 1
3595 12:43:38.805806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3596 12:43:38.806229 ==
3597 12:43:38.809076 RX Vref Scan: 0
3598 12:43:38.809533
3599 12:43:38.809905 RX Vref 0 -> 0, step: 1
3600 12:43:38.810257
3601 12:43:38.812494 RX Delay -40 -> 252, step: 8
3602 12:43:38.815900 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3603 12:43:38.822297 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3604 12:43:38.825468 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3605 12:43:38.828961 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3606 12:43:38.832023 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3607 12:43:38.835667 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3608 12:43:38.838887 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3609 12:43:38.845434 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3610 12:43:38.848514 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3611 12:43:38.852239 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3612 12:43:38.855276 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3613 12:43:38.858902 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
3614 12:43:38.864966 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3615 12:43:38.868446 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3616 12:43:38.871885 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3617 12:43:38.875315 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3618 12:43:38.875754 ==
3619 12:43:38.878628 Dram Type= 6, Freq= 0, CH_1, rank 1
3620 12:43:38.885227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3621 12:43:38.885693 ==
3622 12:43:38.886030 DQS Delay:
3623 12:43:38.888256 DQS0 = 0, DQS1 = 0
3624 12:43:38.888700 DQM Delay:
3625 12:43:38.891774 DQM0 = 110, DQM1 = 105
3626 12:43:38.892191 DQ Delay:
3627 12:43:38.895166 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3628 12:43:38.898333 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3629 12:43:38.901716 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =95
3630 12:43:38.905256 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3631 12:43:38.905697
3632 12:43:38.906027
3633 12:43:38.906330 ==
3634 12:43:38.908591 Dram Type= 6, Freq= 0, CH_1, rank 1
3635 12:43:38.911801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3636 12:43:38.914842 ==
3637 12:43:38.915258
3638 12:43:38.915588
3639 12:43:38.915893 TX Vref Scan disable
3640 12:43:38.918563 == TX Byte 0 ==
3641 12:43:38.921615 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3642 12:43:38.924982 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3643 12:43:38.928230 == TX Byte 1 ==
3644 12:43:38.931589 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3645 12:43:38.934858 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3646 12:43:38.938382 ==
3647 12:43:38.938799 Dram Type= 6, Freq= 0, CH_1, rank 1
3648 12:43:38.944985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3649 12:43:38.945431 ==
3650 12:43:38.956188 TX Vref=22, minBit 9, minWin=25, winSum=421
3651 12:43:38.959369 TX Vref=24, minBit 9, minWin=25, winSum=426
3652 12:43:38.962397 TX Vref=26, minBit 1, minWin=26, winSum=429
3653 12:43:38.965887 TX Vref=28, minBit 0, minWin=26, winSum=432
3654 12:43:38.968986 TX Vref=30, minBit 8, minWin=26, winSum=433
3655 12:43:38.975705 TX Vref=32, minBit 8, minWin=26, winSum=433
3656 12:43:38.979104 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 30
3657 12:43:38.979544
3658 12:43:38.982547 Final TX Range 1 Vref 30
3659 12:43:38.982965
3660 12:43:38.983295 ==
3661 12:43:38.985539 Dram Type= 6, Freq= 0, CH_1, rank 1
3662 12:43:38.988983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3663 12:43:38.989567 ==
3664 12:43:38.992283
3665 12:43:38.992697
3666 12:43:38.993024 TX Vref Scan disable
3667 12:43:38.995714 == TX Byte 0 ==
3668 12:43:38.999112 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3669 12:43:39.005548 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3670 12:43:39.005966 == TX Byte 1 ==
3671 12:43:39.009049 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3672 12:43:39.015596 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3673 12:43:39.016012
3674 12:43:39.016340 [DATLAT]
3675 12:43:39.016644 Freq=1200, CH1 RK1
3676 12:43:39.016976
3677 12:43:39.018801 DATLAT Default: 0xd
3678 12:43:39.019427 0, 0xFFFF, sum = 0
3679 12:43:39.022133 1, 0xFFFF, sum = 0
3680 12:43:39.025468 2, 0xFFFF, sum = 0
3681 12:43:39.025936 3, 0xFFFF, sum = 0
3682 12:43:39.028872 4, 0xFFFF, sum = 0
3683 12:43:39.029325 5, 0xFFFF, sum = 0
3684 12:43:39.032247 6, 0xFFFF, sum = 0
3685 12:43:39.032689 7, 0xFFFF, sum = 0
3686 12:43:39.035762 8, 0xFFFF, sum = 0
3687 12:43:39.036186 9, 0xFFFF, sum = 0
3688 12:43:39.038762 10, 0xFFFF, sum = 0
3689 12:43:39.039340 11, 0xFFFF, sum = 0
3690 12:43:39.042071 12, 0x0, sum = 1
3691 12:43:39.042494 13, 0x0, sum = 2
3692 12:43:39.045386 14, 0x0, sum = 3
3693 12:43:39.045854 15, 0x0, sum = 4
3694 12:43:39.046195 best_step = 13
3695 12:43:39.048801
3696 12:43:39.049242 ==
3697 12:43:39.052185 Dram Type= 6, Freq= 0, CH_1, rank 1
3698 12:43:39.055358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3699 12:43:39.055774 ==
3700 12:43:39.056303 RX Vref Scan: 0
3701 12:43:39.056643
3702 12:43:39.058714 RX Vref 0 -> 0, step: 1
3703 12:43:39.059132
3704 12:43:39.061990 RX Delay -21 -> 252, step: 4
3705 12:43:39.065546 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3706 12:43:39.071961 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3707 12:43:39.075303 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3708 12:43:39.078693 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3709 12:43:39.082062 iDelay=195, Bit 4, Center 110 (39 ~ 182) 144
3710 12:43:39.085260 iDelay=195, Bit 5, Center 118 (47 ~ 190) 144
3711 12:43:39.091871 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3712 12:43:39.095415 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3713 12:43:39.098494 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3714 12:43:39.101919 iDelay=195, Bit 9, Center 100 (31 ~ 170) 140
3715 12:43:39.105350 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3716 12:43:39.111767 iDelay=195, Bit 11, Center 100 (31 ~ 170) 140
3717 12:43:39.115212 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3718 12:43:39.118282 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3719 12:43:39.121656 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3720 12:43:39.128112 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3721 12:43:39.128530 ==
3722 12:43:39.131622 Dram Type= 6, Freq= 0, CH_1, rank 1
3723 12:43:39.134821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3724 12:43:39.135238 ==
3725 12:43:39.135611 DQS Delay:
3726 12:43:39.138375 DQS0 = 0, DQS1 = 0
3727 12:43:39.138792 DQM Delay:
3728 12:43:39.141287 DQM0 = 111, DQM1 = 109
3729 12:43:39.141844 DQ Delay:
3730 12:43:39.144795 DQ0 =114, DQ1 =110, DQ2 =100, DQ3 =108
3731 12:43:39.148231 DQ4 =110, DQ5 =118, DQ6 =120, DQ7 =110
3732 12:43:39.151375 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =100
3733 12:43:39.154800 DQ12 =118, DQ13 =114, DQ14 =116, DQ15 =118
3734 12:43:39.155216
3735 12:43:39.155554
3736 12:43:39.164646 [DQSOSCAuto] RK1, (LSB)MR18= 0xf706, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 413 ps
3737 12:43:39.167852 CH1 RK1: MR19=304, MR18=F706
3738 12:43:39.174645 CH1_RK1: MR19=0x304, MR18=0xF706, DQSOSC=407, MR23=63, INC=39, DEC=26
3739 12:43:39.175078 [RxdqsGatingPostProcess] freq 1200
3740 12:43:39.181252 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3741 12:43:39.184544 best DQS0 dly(2T, 0.5T) = (0, 11)
3742 12:43:39.187715 best DQS1 dly(2T, 0.5T) = (0, 11)
3743 12:43:39.191225 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3744 12:43:39.194550 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3745 12:43:39.197974 best DQS0 dly(2T, 0.5T) = (0, 11)
3746 12:43:39.201431 best DQS1 dly(2T, 0.5T) = (0, 11)
3747 12:43:39.204518 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3748 12:43:39.207758 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3749 12:43:39.211211 Pre-setting of DQS Precalculation
3750 12:43:39.214594 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3751 12:43:39.221001 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3752 12:43:39.227733 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3753 12:43:39.230954
3754 12:43:39.231368
3755 12:43:39.231699 [Calibration Summary] 2400 Mbps
3756 12:43:39.234050 CH 0, Rank 0
3757 12:43:39.234469 SW Impedance : PASS
3758 12:43:39.237459 DUTY Scan : NO K
3759 12:43:39.241014 ZQ Calibration : PASS
3760 12:43:39.241594 Jitter Meter : NO K
3761 12:43:39.244108 CBT Training : PASS
3762 12:43:39.247557 Write leveling : PASS
3763 12:43:39.248018 RX DQS gating : PASS
3764 12:43:39.251109 RX DQ/DQS(RDDQC) : PASS
3765 12:43:39.254220 TX DQ/DQS : PASS
3766 12:43:39.254640 RX DATLAT : PASS
3767 12:43:39.257266 RX DQ/DQS(Engine): PASS
3768 12:43:39.260869 TX OE : NO K
3769 12:43:39.261286 All Pass.
3770 12:43:39.261660
3771 12:43:39.261974 CH 0, Rank 1
3772 12:43:39.263918 SW Impedance : PASS
3773 12:43:39.267228 DUTY Scan : NO K
3774 12:43:39.267641 ZQ Calibration : PASS
3775 12:43:39.270589 Jitter Meter : NO K
3776 12:43:39.274015 CBT Training : PASS
3777 12:43:39.274447 Write leveling : PASS
3778 12:43:39.277211 RX DQS gating : PASS
3779 12:43:39.280697 RX DQ/DQS(RDDQC) : PASS
3780 12:43:39.281278 TX DQ/DQS : PASS
3781 12:43:39.283951 RX DATLAT : PASS
3782 12:43:39.284428 RX DQ/DQS(Engine): PASS
3783 12:43:39.287232 TX OE : NO K
3784 12:43:39.287650 All Pass.
3785 12:43:39.287977
3786 12:43:39.290499 CH 1, Rank 0
3787 12:43:39.290916 SW Impedance : PASS
3788 12:43:39.293898 DUTY Scan : NO K
3789 12:43:39.297163 ZQ Calibration : PASS
3790 12:43:39.297619 Jitter Meter : NO K
3791 12:43:39.300401 CBT Training : PASS
3792 12:43:39.303950 Write leveling : PASS
3793 12:43:39.304595 RX DQS gating : PASS
3794 12:43:39.307164 RX DQ/DQS(RDDQC) : PASS
3795 12:43:39.310317 TX DQ/DQS : PASS
3796 12:43:39.310762 RX DATLAT : PASS
3797 12:43:39.313787 RX DQ/DQS(Engine): PASS
3798 12:43:39.316925 TX OE : NO K
3799 12:43:39.317344 All Pass.
3800 12:43:39.317728
3801 12:43:39.318039 CH 1, Rank 1
3802 12:43:39.320217 SW Impedance : PASS
3803 12:43:39.323853 DUTY Scan : NO K
3804 12:43:39.324348 ZQ Calibration : PASS
3805 12:43:39.327008 Jitter Meter : NO K
3806 12:43:39.330484 CBT Training : PASS
3807 12:43:39.330967 Write leveling : PASS
3808 12:43:39.333570 RX DQS gating : PASS
3809 12:43:39.337037 RX DQ/DQS(RDDQC) : PASS
3810 12:43:39.337598 TX DQ/DQS : PASS
3811 12:43:39.340570 RX DATLAT : PASS
3812 12:43:39.343718 RX DQ/DQS(Engine): PASS
3813 12:43:39.344215 TX OE : NO K
3814 12:43:39.344555 All Pass.
3815 12:43:39.344864
3816 12:43:39.347055 DramC Write-DBI off
3817 12:43:39.350232 PER_BANK_REFRESH: Hybrid Mode
3818 12:43:39.350648 TX_TRACKING: ON
3819 12:43:39.360169 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3820 12:43:39.363617 [FAST_K] Save calibration result to emmc
3821 12:43:39.366669 dramc_set_vcore_voltage set vcore to 650000
3822 12:43:39.369791 Read voltage for 600, 5
3823 12:43:39.370208 Vio18 = 0
3824 12:43:39.373088 Vcore = 650000
3825 12:43:39.373547 Vdram = 0
3826 12:43:39.373889 Vddq = 0
3827 12:43:39.374199 Vmddr = 0
3828 12:43:39.380056 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3829 12:43:39.386558 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3830 12:43:39.387092 MEM_TYPE=3, freq_sel=19
3831 12:43:39.390113 sv_algorithm_assistance_LP4_1600
3832 12:43:39.393306 ============ PULL DRAM RESETB DOWN ============
3833 12:43:39.399846 ========== PULL DRAM RESETB DOWN end =========
3834 12:43:39.403213 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3835 12:43:39.406412 ===================================
3836 12:43:39.409701 LPDDR4 DRAM CONFIGURATION
3837 12:43:39.413038 ===================================
3838 12:43:39.413524 EX_ROW_EN[0] = 0x0
3839 12:43:39.416341 EX_ROW_EN[1] = 0x0
3840 12:43:39.416796 LP4Y_EN = 0x0
3841 12:43:39.419734 WORK_FSP = 0x0
3842 12:43:39.420167 WL = 0x2
3843 12:43:39.423399 RL = 0x2
3844 12:43:39.423816 BL = 0x2
3845 12:43:39.426461 RPST = 0x0
3846 12:43:39.429559 RD_PRE = 0x0
3847 12:43:39.429977 WR_PRE = 0x1
3848 12:43:39.433272 WR_PST = 0x0
3849 12:43:39.433735 DBI_WR = 0x0
3850 12:43:39.436345 DBI_RD = 0x0
3851 12:43:39.436762 OTF = 0x1
3852 12:43:39.439708 ===================================
3853 12:43:39.443146 ===================================
3854 12:43:39.446317 ANA top config
3855 12:43:39.449681 ===================================
3856 12:43:39.450122 DLL_ASYNC_EN = 0
3857 12:43:39.452792 ALL_SLAVE_EN = 1
3858 12:43:39.456303 NEW_RANK_MODE = 1
3859 12:43:39.459461 DLL_IDLE_MODE = 1
3860 12:43:39.459898 LP45_APHY_COMB_EN = 1
3861 12:43:39.462870 TX_ODT_DIS = 1
3862 12:43:39.466262 NEW_8X_MODE = 1
3863 12:43:39.469458 ===================================
3864 12:43:39.473011 ===================================
3865 12:43:39.476003 data_rate = 1200
3866 12:43:39.479539 CKR = 1
3867 12:43:39.482984 DQ_P2S_RATIO = 8
3868 12:43:39.483437 ===================================
3869 12:43:39.486122 CA_P2S_RATIO = 8
3870 12:43:39.489507 DQ_CA_OPEN = 0
3871 12:43:39.492796 DQ_SEMI_OPEN = 0
3872 12:43:39.495973 CA_SEMI_OPEN = 0
3873 12:43:39.499254 CA_FULL_RATE = 0
3874 12:43:39.502589 DQ_CKDIV4_EN = 1
3875 12:43:39.503003 CA_CKDIV4_EN = 1
3876 12:43:39.505809 CA_PREDIV_EN = 0
3877 12:43:39.509309 PH8_DLY = 0
3878 12:43:39.512778 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3879 12:43:39.516001 DQ_AAMCK_DIV = 4
3880 12:43:39.516445 CA_AAMCK_DIV = 4
3881 12:43:39.519440 CA_ADMCK_DIV = 4
3882 12:43:39.522583 DQ_TRACK_CA_EN = 0
3883 12:43:39.525959 CA_PICK = 600
3884 12:43:39.529229 CA_MCKIO = 600
3885 12:43:39.532208 MCKIO_SEMI = 0
3886 12:43:39.536096 PLL_FREQ = 2288
3887 12:43:39.538897 DQ_UI_PI_RATIO = 32
3888 12:43:39.539339 CA_UI_PI_RATIO = 0
3889 12:43:39.542485 ===================================
3890 12:43:39.545893 ===================================
3891 12:43:39.548837 memory_type:LPDDR4
3892 12:43:39.552210 GP_NUM : 10
3893 12:43:39.552831 SRAM_EN : 1
3894 12:43:39.555713 MD32_EN : 0
3895 12:43:39.558819 ===================================
3896 12:43:39.562265 [ANA_INIT] >>>>>>>>>>>>>>
3897 12:43:39.565456 <<<<<< [CONFIGURE PHASE]: ANA_TX
3898 12:43:39.568839 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3899 12:43:39.572262 ===================================
3900 12:43:39.572787 data_rate = 1200,PCW = 0X5800
3901 12:43:39.575344 ===================================
3902 12:43:39.578798 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3903 12:43:39.585110 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3904 12:43:39.591750 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3905 12:43:39.595287 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3906 12:43:39.598366 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3907 12:43:39.601827 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3908 12:43:39.605079 [ANA_INIT] flow start
3909 12:43:39.608571 [ANA_INIT] PLL >>>>>>>>
3910 12:43:39.608996 [ANA_INIT] PLL <<<<<<<<
3911 12:43:39.611618 [ANA_INIT] MIDPI >>>>>>>>
3912 12:43:39.615113 [ANA_INIT] MIDPI <<<<<<<<
3913 12:43:39.615523 [ANA_INIT] DLL >>>>>>>>
3914 12:43:39.618401 [ANA_INIT] flow end
3915 12:43:39.621802 ============ LP4 DIFF to SE enter ============
3916 12:43:39.625246 ============ LP4 DIFF to SE exit ============
3917 12:43:39.628517 [ANA_INIT] <<<<<<<<<<<<<
3918 12:43:39.631516 [Flow] Enable top DCM control >>>>>
3919 12:43:39.635150 [Flow] Enable top DCM control <<<<<
3920 12:43:39.638264 Enable DLL master slave shuffle
3921 12:43:39.645106 ==============================================================
3922 12:43:39.645590 Gating Mode config
3923 12:43:39.651390 ==============================================================
3924 12:43:39.651806 Config description:
3925 12:43:39.661590 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3926 12:43:39.668225 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3927 12:43:39.674874 SELPH_MODE 0: By rank 1: By Phase
3928 12:43:39.678123 ==============================================================
3929 12:43:39.681465 GAT_TRACK_EN = 1
3930 12:43:39.684494 RX_GATING_MODE = 2
3931 12:43:39.687910 RX_GATING_TRACK_MODE = 2
3932 12:43:39.691253 SELPH_MODE = 1
3933 12:43:39.694750 PICG_EARLY_EN = 1
3934 12:43:39.697946 VALID_LAT_VALUE = 1
3935 12:43:39.704393 ==============================================================
3936 12:43:39.707753 Enter into Gating configuration >>>>
3937 12:43:39.711207 Exit from Gating configuration <<<<
3938 12:43:39.714231 Enter into DVFS_PRE_config >>>>>
3939 12:43:39.724081 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3940 12:43:39.727548 Exit from DVFS_PRE_config <<<<<
3941 12:43:39.730812 Enter into PICG configuration >>>>
3942 12:43:39.734113 Exit from PICG configuration <<<<
3943 12:43:39.737167 [RX_INPUT] configuration >>>>>
3944 12:43:39.737251 [RX_INPUT] configuration <<<<<
3945 12:43:39.743849 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3946 12:43:39.750412 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3947 12:43:39.753975 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3948 12:43:39.760555 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3949 12:43:39.766956 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3950 12:43:39.773662 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3951 12:43:39.776984 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3952 12:43:39.780339 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3953 12:43:39.787028 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3954 12:43:39.790299 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3955 12:43:39.793713 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3956 12:43:39.800291 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3957 12:43:39.803519 ===================================
3958 12:43:39.803604 LPDDR4 DRAM CONFIGURATION
3959 12:43:39.807041 ===================================
3960 12:43:39.810182 EX_ROW_EN[0] = 0x0
3961 12:43:39.810266 EX_ROW_EN[1] = 0x0
3962 12:43:39.813434 LP4Y_EN = 0x0
3963 12:43:39.813561 WORK_FSP = 0x0
3964 12:43:39.816592 WL = 0x2
3965 12:43:39.819981 RL = 0x2
3966 12:43:39.820063 BL = 0x2
3967 12:43:39.823509 RPST = 0x0
3968 12:43:39.823592 RD_PRE = 0x0
3969 12:43:39.826881 WR_PRE = 0x1
3970 12:43:39.826990 WR_PST = 0x0
3971 12:43:39.830002 DBI_WR = 0x0
3972 12:43:39.830084 DBI_RD = 0x0
3973 12:43:39.833439 OTF = 0x1
3974 12:43:39.836494 ===================================
3975 12:43:39.840093 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3976 12:43:39.843453 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3977 12:43:39.846745 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3978 12:43:39.849899 ===================================
3979 12:43:39.853418 LPDDR4 DRAM CONFIGURATION
3980 12:43:39.856567 ===================================
3981 12:43:39.860166 EX_ROW_EN[0] = 0x10
3982 12:43:39.860252 EX_ROW_EN[1] = 0x0
3983 12:43:39.863433 LP4Y_EN = 0x0
3984 12:43:39.863519 WORK_FSP = 0x0
3985 12:43:39.866870 WL = 0x2
3986 12:43:39.866957 RL = 0x2
3987 12:43:39.869999 BL = 0x2
3988 12:43:39.870085 RPST = 0x0
3989 12:43:39.873152 RD_PRE = 0x0
3990 12:43:39.873237 WR_PRE = 0x1
3991 12:43:39.876511 WR_PST = 0x0
3992 12:43:39.879828 DBI_WR = 0x0
3993 12:43:39.879913 DBI_RD = 0x0
3994 12:43:39.883230 OTF = 0x1
3995 12:43:39.886798 ===================================
3996 12:43:39.889913 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3997 12:43:39.895592 nWR fixed to 30
3998 12:43:39.898861 [ModeRegInit_LP4] CH0 RK0
3999 12:43:39.899302 [ModeRegInit_LP4] CH0 RK1
4000 12:43:39.902055 [ModeRegInit_LP4] CH1 RK0
4001 12:43:39.905432 [ModeRegInit_LP4] CH1 RK1
4002 12:43:39.905948 match AC timing 17
4003 12:43:39.912205 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4004 12:43:39.915379 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4005 12:43:39.918837 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4006 12:43:39.925586 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4007 12:43:39.928818 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4008 12:43:39.929242 ==
4009 12:43:39.931929 Dram Type= 6, Freq= 0, CH_0, rank 0
4010 12:43:39.935431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4011 12:43:39.935862 ==
4012 12:43:39.941987 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4013 12:43:39.948754 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4014 12:43:39.951848 [CA 0] Center 37 (7~67) winsize 61
4015 12:43:39.955230 [CA 1] Center 37 (7~67) winsize 61
4016 12:43:39.958408 [CA 2] Center 35 (5~65) winsize 61
4017 12:43:39.962098 [CA 3] Center 35 (5~65) winsize 61
4018 12:43:39.965179 [CA 4] Center 34 (4~65) winsize 62
4019 12:43:39.968390 [CA 5] Center 34 (4~64) winsize 61
4020 12:43:39.968815
4021 12:43:39.971519 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4022 12:43:39.971964
4023 12:43:39.975071 [CATrainingPosCal] consider 1 rank data
4024 12:43:39.978369 u2DelayCellTimex100 = 270/100 ps
4025 12:43:39.981505 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4026 12:43:39.984855 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4027 12:43:39.988376 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4028 12:43:39.991640 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4029 12:43:39.994799 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4030 12:43:40.001471 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4031 12:43:40.001942
4032 12:43:40.005096 CA PerBit enable=1, Macro0, CA PI delay=34
4033 12:43:40.005709
4034 12:43:40.008215 [CBTSetCACLKResult] CA Dly = 34
4035 12:43:40.008638 CS Dly: 6 (0~37)
4036 12:43:40.008976 ==
4037 12:43:40.011451 Dram Type= 6, Freq= 0, CH_0, rank 1
4038 12:43:40.014729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4039 12:43:40.018033 ==
4040 12:43:40.021369 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4041 12:43:40.028021 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4042 12:43:40.031238 [CA 0] Center 37 (7~67) winsize 61
4043 12:43:40.034648 [CA 1] Center 37 (7~67) winsize 61
4044 12:43:40.038084 [CA 2] Center 35 (5~65) winsize 61
4045 12:43:40.041261 [CA 3] Center 35 (5~65) winsize 61
4046 12:43:40.044545 [CA 4] Center 34 (4~65) winsize 62
4047 12:43:40.048283 [CA 5] Center 34 (3~65) winsize 63
4048 12:43:40.048782
4049 12:43:40.051175 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4050 12:43:40.051647
4051 12:43:40.054623 [CATrainingPosCal] consider 2 rank data
4052 12:43:40.057776 u2DelayCellTimex100 = 270/100 ps
4053 12:43:40.061162 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4054 12:43:40.064533 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4055 12:43:40.067937 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4056 12:43:40.074421 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4057 12:43:40.077630 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4058 12:43:40.081064 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4059 12:43:40.081686
4060 12:43:40.084289 CA PerBit enable=1, Macro0, CA PI delay=34
4061 12:43:40.084762
4062 12:43:40.087806 [CBTSetCACLKResult] CA Dly = 34
4063 12:43:40.088273 CS Dly: 6 (0~37)
4064 12:43:40.088685
4065 12:43:40.090911 ----->DramcWriteLeveling(PI) begin...
4066 12:43:40.094323 ==
4067 12:43:40.094828 Dram Type= 6, Freq= 0, CH_0, rank 0
4068 12:43:40.100765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4069 12:43:40.101268 ==
4070 12:43:40.104020 Write leveling (Byte 0): 32 => 32
4071 12:43:40.107400 Write leveling (Byte 1): 32 => 32
4072 12:43:40.110784 DramcWriteLeveling(PI) end<-----
4073 12:43:40.111227
4074 12:43:40.111565 ==
4075 12:43:40.114370 Dram Type= 6, Freq= 0, CH_0, rank 0
4076 12:43:40.117635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4077 12:43:40.118066 ==
4078 12:43:40.120941 [Gating] SW mode calibration
4079 12:43:40.127766 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4080 12:43:40.130777 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4081 12:43:40.137399 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4082 12:43:40.140793 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4083 12:43:40.144148 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4084 12:43:40.150826 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
4085 12:43:40.154187 0 9 16 | B1->B0 | 3030 2828 | 0 0 | (0 0) (1 1)
4086 12:43:40.157652 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
4087 12:43:40.164116 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4088 12:43:40.167415 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4089 12:43:40.170600 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4090 12:43:40.177521 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4091 12:43:40.180616 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4092 12:43:40.184196 0 10 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4093 12:43:40.190509 0 10 16 | B1->B0 | 3636 3b3b | 0 1 | (0 0) (0 0)
4094 12:43:40.194087 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4095 12:43:40.197403 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4096 12:43:40.203905 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4097 12:43:40.207301 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4098 12:43:40.210381 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4099 12:43:40.216970 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4100 12:43:40.220385 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4101 12:43:40.223407 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4102 12:43:40.230335 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4103 12:43:40.233411 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4104 12:43:40.236963 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4105 12:43:40.243458 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4106 12:43:40.246893 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4107 12:43:40.249961 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4108 12:43:40.256499 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4109 12:43:40.259851 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4110 12:43:40.263229 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4111 12:43:40.269893 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4112 12:43:40.273121 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4113 12:43:40.276358 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4114 12:43:40.283312 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4115 12:43:40.286514 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4116 12:43:40.289977 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4117 12:43:40.296361 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4118 12:43:40.296889 Total UI for P1: 0, mck2ui 16
4119 12:43:40.303313 best dqsien dly found for B0: ( 0, 13, 14)
4120 12:43:40.306609 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4121 12:43:40.309561 Total UI for P1: 0, mck2ui 16
4122 12:43:40.312981 best dqsien dly found for B1: ( 0, 13, 16)
4123 12:43:40.316383 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4124 12:43:40.319454 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4125 12:43:40.319924
4126 12:43:40.322748 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4127 12:43:40.326064 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4128 12:43:40.329420 [Gating] SW calibration Done
4129 12:43:40.329925 ==
4130 12:43:40.332782 Dram Type= 6, Freq= 0, CH_0, rank 0
4131 12:43:40.336243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 12:43:40.339344 ==
4133 12:43:40.339769 RX Vref Scan: 0
4134 12:43:40.340106
4135 12:43:40.342769 RX Vref 0 -> 0, step: 1
4136 12:43:40.343191
4137 12:43:40.345825 RX Delay -230 -> 252, step: 16
4138 12:43:40.349236 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4139 12:43:40.352716 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4140 12:43:40.356137 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4141 12:43:40.362287 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4142 12:43:40.365660 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4143 12:43:40.369061 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4144 12:43:40.372447 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4145 12:43:40.375538 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4146 12:43:40.382230 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4147 12:43:40.385521 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4148 12:43:40.388765 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4149 12:43:40.392172 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4150 12:43:40.398623 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4151 12:43:40.401962 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4152 12:43:40.405280 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4153 12:43:40.408732 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4154 12:43:40.409257 ==
4155 12:43:40.411962 Dram Type= 6, Freq= 0, CH_0, rank 0
4156 12:43:40.418745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4157 12:43:40.419174 ==
4158 12:43:40.419512 DQS Delay:
4159 12:43:40.422017 DQS0 = 0, DQS1 = 0
4160 12:43:40.422441 DQM Delay:
4161 12:43:40.425221 DQM0 = 37, DQM1 = 27
4162 12:43:40.425679 DQ Delay:
4163 12:43:40.428615 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4164 12:43:40.431881 DQ4 =41, DQ5 =17, DQ6 =49, DQ7 =49
4165 12:43:40.435213 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4166 12:43:40.438460 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4167 12:43:40.438885
4168 12:43:40.439220
4169 12:43:40.439532 ==
4170 12:43:40.441616 Dram Type= 6, Freq= 0, CH_0, rank 0
4171 12:43:40.445207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4172 12:43:40.445664 ==
4173 12:43:40.446004
4174 12:43:40.446314
4175 12:43:40.448831 TX Vref Scan disable
4176 12:43:40.451824 == TX Byte 0 ==
4177 12:43:40.455117 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4178 12:43:40.458547 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4179 12:43:40.461747 == TX Byte 1 ==
4180 12:43:40.464823 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4181 12:43:40.468238 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4182 12:43:40.468674 ==
4183 12:43:40.471686 Dram Type= 6, Freq= 0, CH_0, rank 0
4184 12:43:40.475222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4185 12:43:40.478127 ==
4186 12:43:40.478551
4187 12:43:40.478886
4188 12:43:40.479194 TX Vref Scan disable
4189 12:43:40.482304 == TX Byte 0 ==
4190 12:43:40.485559 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4191 12:43:40.492187 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4192 12:43:40.492634 == TX Byte 1 ==
4193 12:43:40.495499 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4194 12:43:40.501852 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4195 12:43:40.502435
4196 12:43:40.502960 [DATLAT]
4197 12:43:40.503445 Freq=600, CH0 RK0
4198 12:43:40.503786
4199 12:43:40.505468 DATLAT Default: 0x9
4200 12:43:40.505937 0, 0xFFFF, sum = 0
4201 12:43:40.508729 1, 0xFFFF, sum = 0
4202 12:43:40.509161 2, 0xFFFF, sum = 0
4203 12:43:40.511983 3, 0xFFFF, sum = 0
4204 12:43:40.515236 4, 0xFFFF, sum = 0
4205 12:43:40.515681 5, 0xFFFF, sum = 0
4206 12:43:40.518416 6, 0xFFFF, sum = 0
4207 12:43:40.518878 7, 0xFFFF, sum = 0
4208 12:43:40.521949 8, 0x0, sum = 1
4209 12:43:40.522417 9, 0x0, sum = 2
4210 12:43:40.522890 10, 0x0, sum = 3
4211 12:43:40.525180 11, 0x0, sum = 4
4212 12:43:40.525654 best_step = 9
4213 12:43:40.525999
4214 12:43:40.526313 ==
4215 12:43:40.528528 Dram Type= 6, Freq= 0, CH_0, rank 0
4216 12:43:40.535113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4217 12:43:40.535543 ==
4218 12:43:40.535880 RX Vref Scan: 1
4219 12:43:40.536198
4220 12:43:40.538296 RX Vref 0 -> 0, step: 1
4221 12:43:40.538982
4222 12:43:40.541530 RX Delay -195 -> 252, step: 8
4223 12:43:40.541960
4224 12:43:40.545154 Set Vref, RX VrefLevel [Byte0]: 60
4225 12:43:40.548224 [Byte1]: 52
4226 12:43:40.548647
4227 12:43:40.551655 Final RX Vref Byte 0 = 60 to rank0
4228 12:43:40.555212 Final RX Vref Byte 1 = 52 to rank0
4229 12:43:40.558713 Final RX Vref Byte 0 = 60 to rank1
4230 12:43:40.561974 Final RX Vref Byte 1 = 52 to rank1==
4231 12:43:40.564830 Dram Type= 6, Freq= 0, CH_0, rank 0
4232 12:43:40.568265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4233 12:43:40.568693 ==
4234 12:43:40.571427 DQS Delay:
4235 12:43:40.572004 DQS0 = 0, DQS1 = 0
4236 12:43:40.574766 DQM Delay:
4237 12:43:40.575239 DQM0 = 34, DQM1 = 28
4238 12:43:40.575586 DQ Delay:
4239 12:43:40.578430 DQ0 =32, DQ1 =36, DQ2 =36, DQ3 =32
4240 12:43:40.581600 DQ4 =32, DQ5 =24, DQ6 =40, DQ7 =44
4241 12:43:40.584853 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4242 12:43:40.588174 DQ12 =32, DQ13 =36, DQ14 =40, DQ15 =36
4243 12:43:40.588598
4244 12:43:40.588936
4245 12:43:40.598170 [DQSOSCAuto] RK0, (LSB)MR18= 0x4140, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4246 12:43:40.601246 CH0 RK0: MR19=808, MR18=4140
4247 12:43:40.608033 CH0_RK0: MR19=0x808, MR18=0x4140, DQSOSC=397, MR23=63, INC=166, DEC=110
4248 12:43:40.608492
4249 12:43:40.611525 ----->DramcWriteLeveling(PI) begin...
4250 12:43:40.611911 ==
4251 12:43:40.614703 Dram Type= 6, Freq= 0, CH_0, rank 1
4252 12:43:40.617926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4253 12:43:40.618332 ==
4254 12:43:40.621266 Write leveling (Byte 0): 33 => 33
4255 12:43:40.624842 Write leveling (Byte 1): 33 => 33
4256 12:43:40.628049 DramcWriteLeveling(PI) end<-----
4257 12:43:40.628436
4258 12:43:40.628777 ==
4259 12:43:40.631051 Dram Type= 6, Freq= 0, CH_0, rank 1
4260 12:43:40.634596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4261 12:43:40.635038 ==
4262 12:43:40.638087 [Gating] SW mode calibration
4263 12:43:40.644626 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4264 12:43:40.651073 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4265 12:43:40.654572 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4266 12:43:40.657633 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4267 12:43:40.664504 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4268 12:43:40.667811 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 1)
4269 12:43:40.670999 0 9 16 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
4270 12:43:40.677585 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4271 12:43:40.681031 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4272 12:43:40.684499 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4273 12:43:40.691067 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4274 12:43:40.694377 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4275 12:43:40.697597 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4276 12:43:40.704389 0 10 12 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
4277 12:43:40.707382 0 10 16 | B1->B0 | 3f3f 4444 | 0 0 | (0 0) (0 0)
4278 12:43:40.710762 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4279 12:43:40.717313 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4280 12:43:40.720765 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4281 12:43:40.724251 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4282 12:43:40.730807 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4283 12:43:40.734096 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4284 12:43:40.737126 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4285 12:43:40.743780 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4286 12:43:40.747284 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 12:43:40.750469 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 12:43:40.753820 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 12:43:40.760521 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 12:43:40.764039 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 12:43:40.767476 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 12:43:40.774056 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 12:43:40.777200 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 12:43:40.780653 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 12:43:40.787219 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4296 12:43:40.790718 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4297 12:43:40.793833 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4298 12:43:40.800364 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 12:43:40.803966 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4300 12:43:40.807377 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 12:43:40.813803 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4302 12:43:40.817424 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4303 12:43:40.820617 Total UI for P1: 0, mck2ui 16
4304 12:43:40.823923 best dqsien dly found for B0: ( 0, 13, 16)
4305 12:43:40.827426 Total UI for P1: 0, mck2ui 16
4306 12:43:40.830644 best dqsien dly found for B1: ( 0, 13, 18)
4307 12:43:40.833991 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4308 12:43:40.836968 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4309 12:43:40.837405
4310 12:43:40.840128 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4311 12:43:40.843616 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4312 12:43:40.847069 [Gating] SW calibration Done
4313 12:43:40.847491 ==
4314 12:43:40.850234 Dram Type= 6, Freq= 0, CH_0, rank 1
4315 12:43:40.857045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4316 12:43:40.857656 ==
4317 12:43:40.858153 RX Vref Scan: 0
4318 12:43:40.858589
4319 12:43:40.860243 RX Vref 0 -> 0, step: 1
4320 12:43:40.860838
4321 12:43:40.863420 RX Delay -230 -> 252, step: 16
4322 12:43:40.867016 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4323 12:43:40.870381 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4324 12:43:40.873301 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4325 12:43:40.880538 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4326 12:43:40.883536 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4327 12:43:40.887004 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4328 12:43:40.890182 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4329 12:43:40.893683 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4330 12:43:40.900282 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4331 12:43:40.903301 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4332 12:43:40.906780 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4333 12:43:40.910040 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4334 12:43:40.916762 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4335 12:43:40.920004 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4336 12:43:40.923472 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4337 12:43:40.926554 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4338 12:43:40.927013 ==
4339 12:43:40.930015 Dram Type= 6, Freq= 0, CH_0, rank 1
4340 12:43:40.936524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4341 12:43:40.937019 ==
4342 12:43:40.937450 DQS Delay:
4343 12:43:40.939982 DQS0 = 0, DQS1 = 0
4344 12:43:40.940465 DQM Delay:
4345 12:43:40.940855 DQM0 = 36, DQM1 = 29
4346 12:43:40.943296 DQ Delay:
4347 12:43:40.946792 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4348 12:43:40.949834 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4349 12:43:40.952970 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4350 12:43:40.956489 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4351 12:43:40.957006
4352 12:43:40.957429
4353 12:43:40.957881 ==
4354 12:43:40.959793 Dram Type= 6, Freq= 0, CH_0, rank 1
4355 12:43:40.962847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4356 12:43:40.963269 ==
4357 12:43:40.963602
4358 12:43:40.963908
4359 12:43:40.966106 TX Vref Scan disable
4360 12:43:40.969597 == TX Byte 0 ==
4361 12:43:40.972907 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4362 12:43:40.976025 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4363 12:43:40.979359 == TX Byte 1 ==
4364 12:43:40.982540 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4365 12:43:40.986086 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4366 12:43:40.986560 ==
4367 12:43:40.989197 Dram Type= 6, Freq= 0, CH_0, rank 1
4368 12:43:40.992435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4369 12:43:40.995743 ==
4370 12:43:40.995996
4371 12:43:40.996182
4372 12:43:40.996382 TX Vref Scan disable
4373 12:43:40.999885 == TX Byte 0 ==
4374 12:43:41.003033 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4375 12:43:41.009621 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4376 12:43:41.009856 == TX Byte 1 ==
4377 12:43:41.013243 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4378 12:43:41.019644 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4379 12:43:41.019913
4380 12:43:41.020096 [DATLAT]
4381 12:43:41.020310 Freq=600, CH0 RK1
4382 12:43:41.020477
4383 12:43:41.022992 DATLAT Default: 0x9
4384 12:43:41.023258 0, 0xFFFF, sum = 0
4385 12:43:41.026366 1, 0xFFFF, sum = 0
4386 12:43:41.026638 2, 0xFFFF, sum = 0
4387 12:43:41.029710 3, 0xFFFF, sum = 0
4388 12:43:41.032752 4, 0xFFFF, sum = 0
4389 12:43:41.032977 5, 0xFFFF, sum = 0
4390 12:43:41.036184 6, 0xFFFF, sum = 0
4391 12:43:41.036440 7, 0xFFFF, sum = 0
4392 12:43:41.039512 8, 0x0, sum = 1
4393 12:43:41.039743 9, 0x0, sum = 2
4394 12:43:41.039971 10, 0x0, sum = 3
4395 12:43:41.042957 11, 0x0, sum = 4
4396 12:43:41.043289 best_step = 9
4397 12:43:41.043478
4398 12:43:41.043647 ==
4399 12:43:41.046109 Dram Type= 6, Freq= 0, CH_0, rank 1
4400 12:43:41.052724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 12:43:41.052953 ==
4402 12:43:41.053130 RX Vref Scan: 0
4403 12:43:41.053299
4404 12:43:41.055965 RX Vref 0 -> 0, step: 1
4405 12:43:41.056242
4406 12:43:41.059557 RX Delay -195 -> 252, step: 8
4407 12:43:41.066269 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4408 12:43:41.069522 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4409 12:43:41.072849 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4410 12:43:41.075954 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4411 12:43:41.079571 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4412 12:43:41.086056 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4413 12:43:41.089103 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4414 12:43:41.092562 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4415 12:43:41.095890 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4416 12:43:41.102568 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4417 12:43:41.105845 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4418 12:43:41.109181 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4419 12:43:41.112582 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4420 12:43:41.119173 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4421 12:43:41.122562 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4422 12:43:41.125830 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4423 12:43:41.126306 ==
4424 12:43:41.128989 Dram Type= 6, Freq= 0, CH_0, rank 1
4425 12:43:41.132205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4426 12:43:41.132677 ==
4427 12:43:41.135703 DQS Delay:
4428 12:43:41.136208 DQS0 = 0, DQS1 = 0
4429 12:43:41.138992 DQM Delay:
4430 12:43:41.139460 DQM0 = 34, DQM1 = 27
4431 12:43:41.139857 DQ Delay:
4432 12:43:41.142258 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4433 12:43:41.145728 DQ4 =36, DQ5 =20, DQ6 =44, DQ7 =44
4434 12:43:41.148975 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4435 12:43:41.152052 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4436 12:43:41.152564
4437 12:43:41.152914
4438 12:43:41.162100 [DQSOSCAuto] RK1, (LSB)MR18= 0x6937, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4439 12:43:41.165665 CH0 RK1: MR19=808, MR18=6937
4440 12:43:41.172089 CH0_RK1: MR19=0x808, MR18=0x6937, DQSOSC=390, MR23=63, INC=172, DEC=114
4441 12:43:41.172580 [RxdqsGatingPostProcess] freq 600
4442 12:43:41.178791 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4443 12:43:41.182373 Pre-setting of DQS Precalculation
4444 12:43:41.185694 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4445 12:43:41.186257 ==
4446 12:43:41.188900 Dram Type= 6, Freq= 0, CH_1, rank 0
4447 12:43:41.195390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4448 12:43:41.195817 ==
4449 12:43:41.198885 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4450 12:43:41.205365 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4451 12:43:41.209227 [CA 0] Center 35 (5~66) winsize 62
4452 12:43:41.212238 [CA 1] Center 36 (6~66) winsize 61
4453 12:43:41.215772 [CA 2] Center 34 (4~65) winsize 62
4454 12:43:41.218933 [CA 3] Center 34 (3~65) winsize 63
4455 12:43:41.222288 [CA 4] Center 34 (4~65) winsize 62
4456 12:43:41.225628 [CA 5] Center 33 (3~64) winsize 62
4457 12:43:41.226069
4458 12:43:41.228994 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4459 12:43:41.229656
4460 12:43:41.232101 [CATrainingPosCal] consider 1 rank data
4461 12:43:41.235484 u2DelayCellTimex100 = 270/100 ps
4462 12:43:41.239100 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4463 12:43:41.245425 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4464 12:43:41.248895 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4465 12:43:41.252209 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4466 12:43:41.255580 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4467 12:43:41.259021 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4468 12:43:41.259446
4469 12:43:41.262285 CA PerBit enable=1, Macro0, CA PI delay=33
4470 12:43:41.262707
4471 12:43:41.265610 [CBTSetCACLKResult] CA Dly = 33
4472 12:43:41.266059 CS Dly: 4 (0~35)
4473 12:43:41.268988 ==
4474 12:43:41.269410 Dram Type= 6, Freq= 0, CH_1, rank 1
4475 12:43:41.275522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4476 12:43:41.275989 ==
4477 12:43:41.278690 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4478 12:43:41.285164 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4479 12:43:41.289219 [CA 0] Center 36 (6~66) winsize 61
4480 12:43:41.292496 [CA 1] Center 36 (6~66) winsize 61
4481 12:43:41.295763 [CA 2] Center 34 (4~65) winsize 62
4482 12:43:41.299150 [CA 3] Center 34 (3~65) winsize 63
4483 12:43:41.302432 [CA 4] Center 34 (4~65) winsize 62
4484 12:43:41.305517 [CA 5] Center 33 (3~64) winsize 62
4485 12:43:41.305996
4486 12:43:41.308888 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4487 12:43:41.309376
4488 12:43:41.312300 [CATrainingPosCal] consider 2 rank data
4489 12:43:41.315579 u2DelayCellTimex100 = 270/100 ps
4490 12:43:41.318766 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4491 12:43:41.325687 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4492 12:43:41.328609 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4493 12:43:41.332446 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4494 12:43:41.335682 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4495 12:43:41.338709 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4496 12:43:41.339184
4497 12:43:41.342125 CA PerBit enable=1, Macro0, CA PI delay=33
4498 12:43:41.342576
4499 12:43:41.345726 [CBTSetCACLKResult] CA Dly = 33
4500 12:43:41.346182 CS Dly: 4 (0~36)
4501 12:43:41.348915
4502 12:43:41.352294 ----->DramcWriteLeveling(PI) begin...
4503 12:43:41.352758 ==
4504 12:43:41.355363 Dram Type= 6, Freq= 0, CH_1, rank 0
4505 12:43:41.358919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4506 12:43:41.359368 ==
4507 12:43:41.362047 Write leveling (Byte 0): 30 => 30
4508 12:43:41.365465 Write leveling (Byte 1): 30 => 30
4509 12:43:41.368754 DramcWriteLeveling(PI) end<-----
4510 12:43:41.369217
4511 12:43:41.369839 ==
4512 12:43:41.371988 Dram Type= 6, Freq= 0, CH_1, rank 0
4513 12:43:41.375538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4514 12:43:41.375997 ==
4515 12:43:41.378838 [Gating] SW mode calibration
4516 12:43:41.385065 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4517 12:43:41.392008 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4518 12:43:41.395289 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4519 12:43:41.398377 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4520 12:43:41.404887 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4521 12:43:41.408235 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 0)
4522 12:43:41.411599 0 9 16 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
4523 12:43:41.418139 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4524 12:43:41.421360 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4525 12:43:41.424751 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4526 12:43:41.431685 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4527 12:43:41.435049 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4528 12:43:41.437918 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4529 12:43:41.444514 0 10 12 | B1->B0 | 2929 302f | 0 1 | (0 0) (0 0)
4530 12:43:41.448048 0 10 16 | B1->B0 | 3f3f 3e3e | 0 0 | (0 0) (0 0)
4531 12:43:41.451560 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4532 12:43:41.457980 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4533 12:43:41.461058 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4534 12:43:41.464396 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4535 12:43:41.470954 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4536 12:43:41.474283 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4537 12:43:41.477620 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4538 12:43:41.484283 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4539 12:43:41.487679 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4540 12:43:41.490947 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4541 12:43:41.494576 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4542 12:43:41.500931 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4543 12:43:41.504157 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4544 12:43:41.510855 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4545 12:43:41.513963 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4546 12:43:41.517588 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4547 12:43:41.520811 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4548 12:43:41.527332 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4549 12:43:41.530429 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4550 12:43:41.533865 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4551 12:43:41.540668 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4552 12:43:41.543852 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4553 12:43:41.550420 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4554 12:43:41.553556 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4555 12:43:41.556817 Total UI for P1: 0, mck2ui 16
4556 12:43:41.560236 best dqsien dly found for B0: ( 0, 13, 14)
4557 12:43:41.563509 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4558 12:43:41.566944 Total UI for P1: 0, mck2ui 16
4559 12:43:41.570189 best dqsien dly found for B1: ( 0, 13, 14)
4560 12:43:41.573378 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4561 12:43:41.576805 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4562 12:43:41.577340
4563 12:43:41.580367 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4564 12:43:41.586612 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4565 12:43:41.587124 [Gating] SW calibration Done
4566 12:43:41.590041 ==
4567 12:43:41.590541 Dram Type= 6, Freq= 0, CH_1, rank 0
4568 12:43:41.596374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 12:43:41.596895 ==
4570 12:43:41.597302 RX Vref Scan: 0
4571 12:43:41.597788
4572 12:43:41.599752 RX Vref 0 -> 0, step: 1
4573 12:43:41.600238
4574 12:43:41.603248 RX Delay -230 -> 252, step: 16
4575 12:43:41.606335 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4576 12:43:41.609915 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4577 12:43:41.616406 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4578 12:43:41.619586 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4579 12:43:41.622824 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4580 12:43:41.626214 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4581 12:43:41.629472 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4582 12:43:41.636372 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4583 12:43:41.639665 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4584 12:43:41.643107 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4585 12:43:41.646304 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4586 12:43:41.652853 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4587 12:43:41.655960 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4588 12:43:41.659323 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4589 12:43:41.662510 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4590 12:43:41.669463 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4591 12:43:41.669931 ==
4592 12:43:41.672892 Dram Type= 6, Freq= 0, CH_1, rank 0
4593 12:43:41.676173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4594 12:43:41.676657 ==
4595 12:43:41.677095 DQS Delay:
4596 12:43:41.679225 DQS0 = 0, DQS1 = 0
4597 12:43:41.679708 DQM Delay:
4598 12:43:41.682710 DQM0 = 38, DQM1 = 32
4599 12:43:41.683135 DQ Delay:
4600 12:43:41.686179 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4601 12:43:41.689182 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4602 12:43:41.692416 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4603 12:43:41.695583 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4604 12:43:41.696011
4605 12:43:41.696347
4606 12:43:41.696778 ==
4607 12:43:41.699131 Dram Type= 6, Freq= 0, CH_1, rank 0
4608 12:43:41.702243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4609 12:43:41.705576 ==
4610 12:43:41.706001
4611 12:43:41.706333
4612 12:43:41.706642 TX Vref Scan disable
4613 12:43:41.708817 == TX Byte 0 ==
4614 12:43:41.712374 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4615 12:43:41.715529 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4616 12:43:41.718927 == TX Byte 1 ==
4617 12:43:41.722251 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4618 12:43:41.725676 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4619 12:43:41.728906 ==
4620 12:43:41.729340 Dram Type= 6, Freq= 0, CH_1, rank 0
4621 12:43:41.735838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4622 12:43:41.736265 ==
4623 12:43:41.736739
4624 12:43:41.737089
4625 12:43:41.739002 TX Vref Scan disable
4626 12:43:41.739438 == TX Byte 0 ==
4627 12:43:41.745612 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4628 12:43:41.748761 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4629 12:43:41.749198 == TX Byte 1 ==
4630 12:43:41.755211 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4631 12:43:41.758544 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4632 12:43:41.758974
4633 12:43:41.759310 [DATLAT]
4634 12:43:41.761933 Freq=600, CH1 RK0
4635 12:43:41.762365
4636 12:43:41.762721 DATLAT Default: 0x9
4637 12:43:41.765318 0, 0xFFFF, sum = 0
4638 12:43:41.765838 1, 0xFFFF, sum = 0
4639 12:43:41.768460 2, 0xFFFF, sum = 0
4640 12:43:41.772273 3, 0xFFFF, sum = 0
4641 12:43:41.772842 4, 0xFFFF, sum = 0
4642 12:43:41.775113 5, 0xFFFF, sum = 0
4643 12:43:41.775604 6, 0xFFFF, sum = 0
4644 12:43:41.778598 7, 0xFFFF, sum = 0
4645 12:43:41.779048 8, 0x0, sum = 1
4646 12:43:41.779404 9, 0x0, sum = 2
4647 12:43:41.781591 10, 0x0, sum = 3
4648 12:43:41.782031 11, 0x0, sum = 4
4649 12:43:41.784994 best_step = 9
4650 12:43:41.785432
4651 12:43:41.785847 ==
4652 12:43:41.788328 Dram Type= 6, Freq= 0, CH_1, rank 0
4653 12:43:41.791594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4654 12:43:41.792044 ==
4655 12:43:41.795152 RX Vref Scan: 1
4656 12:43:41.795602
4657 12:43:41.796079 RX Vref 0 -> 0, step: 1
4658 12:43:41.796431
4659 12:43:41.798303 RX Delay -179 -> 252, step: 8
4660 12:43:41.798736
4661 12:43:41.801778 Set Vref, RX VrefLevel [Byte0]: 54
4662 12:43:41.804853 [Byte1]: 48
4663 12:43:41.809080
4664 12:43:41.809541 Final RX Vref Byte 0 = 54 to rank0
4665 12:43:41.812457 Final RX Vref Byte 1 = 48 to rank0
4666 12:43:41.815845 Final RX Vref Byte 0 = 54 to rank1
4667 12:43:41.819203 Final RX Vref Byte 1 = 48 to rank1==
4668 12:43:41.822398 Dram Type= 6, Freq= 0, CH_1, rank 0
4669 12:43:41.829148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4670 12:43:41.829725 ==
4671 12:43:41.830069 DQS Delay:
4672 12:43:41.830402 DQS0 = 0, DQS1 = 0
4673 12:43:41.832277 DQM Delay:
4674 12:43:41.832708 DQM0 = 39, DQM1 = 28
4675 12:43:41.835829 DQ Delay:
4676 12:43:41.838845 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4677 12:43:41.842300 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4678 12:43:41.845650 DQ8 =12, DQ9 =16, DQ10 =32, DQ11 =20
4679 12:43:41.848943 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4680 12:43:41.849411
4681 12:43:41.849825
4682 12:43:41.855490 [DQSOSCAuto] RK0, (LSB)MR18= 0x202d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 403 ps
4683 12:43:41.858871 CH1 RK0: MR19=808, MR18=202D
4684 12:43:41.865701 CH1_RK0: MR19=0x808, MR18=0x202D, DQSOSC=401, MR23=63, INC=163, DEC=108
4685 12:43:41.866136
4686 12:43:41.868969 ----->DramcWriteLeveling(PI) begin...
4687 12:43:41.869416 ==
4688 12:43:41.872161 Dram Type= 6, Freq= 0, CH_1, rank 1
4689 12:43:41.875432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4690 12:43:41.875869 ==
4691 12:43:41.878775 Write leveling (Byte 0): 29 => 29
4692 12:43:41.882105 Write leveling (Byte 1): 29 => 29
4693 12:43:41.885170 DramcWriteLeveling(PI) end<-----
4694 12:43:41.885748
4695 12:43:41.886091 ==
4696 12:43:41.888742 Dram Type= 6, Freq= 0, CH_1, rank 1
4697 12:43:41.891999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4698 12:43:41.892473 ==
4699 12:43:41.894854 [Gating] SW mode calibration
4700 12:43:41.901552 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4701 12:43:41.908010 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4702 12:43:41.911298 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4703 12:43:41.918143 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4704 12:43:41.921453 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4705 12:43:41.924862 0 9 12 | B1->B0 | 2f2f 2929 | 1 0 | (1 1) (1 0)
4706 12:43:41.931387 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4707 12:43:41.934607 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4708 12:43:41.937781 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4709 12:43:41.944830 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4710 12:43:41.948161 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4711 12:43:41.951238 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4712 12:43:41.954715 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4713 12:43:41.961173 0 10 12 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
4714 12:43:41.964688 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4715 12:43:41.967988 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4716 12:43:41.974946 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4717 12:43:41.977790 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4718 12:43:41.981267 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4719 12:43:41.987803 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4720 12:43:41.991128 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4721 12:43:41.994707 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4722 12:43:42.001074 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4723 12:43:42.004658 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4724 12:43:42.008049 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4725 12:43:42.014738 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4726 12:43:42.018002 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4727 12:43:42.021282 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4728 12:43:42.027887 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4729 12:43:42.031507 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4730 12:43:42.034414 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4731 12:43:42.041122 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4732 12:43:42.044599 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4733 12:43:42.047981 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4734 12:43:42.054801 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4735 12:43:42.057801 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4736 12:43:42.061354 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4737 12:43:42.067735 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4738 12:43:42.070935 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4739 12:43:42.074514 Total UI for P1: 0, mck2ui 16
4740 12:43:42.077925 best dqsien dly found for B0: ( 0, 13, 10)
4741 12:43:42.081012 Total UI for P1: 0, mck2ui 16
4742 12:43:42.084561 best dqsien dly found for B1: ( 0, 13, 12)
4743 12:43:42.087649 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4744 12:43:42.091191 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4745 12:43:42.091635
4746 12:43:42.094254 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4747 12:43:42.097843 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4748 12:43:42.101151 [Gating] SW calibration Done
4749 12:43:42.101751 ==
4750 12:43:42.104553 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 12:43:42.107668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 12:43:42.111086 ==
4753 12:43:42.111517 RX Vref Scan: 0
4754 12:43:42.111867
4755 12:43:42.114306 RX Vref 0 -> 0, step: 1
4756 12:43:42.114740
4757 12:43:42.117844 RX Delay -230 -> 252, step: 16
4758 12:43:42.120869 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4759 12:43:42.124249 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4760 12:43:42.127667 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4761 12:43:42.130927 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4762 12:43:42.137679 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4763 12:43:42.140873 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4764 12:43:42.144218 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4765 12:43:42.147751 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4766 12:43:42.154247 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4767 12:43:42.157382 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4768 12:43:42.160732 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4769 12:43:42.164193 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4770 12:43:42.171039 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4771 12:43:42.174175 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4772 12:43:42.177422 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4773 12:43:42.181016 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4774 12:43:42.181452 ==
4775 12:43:42.184284 Dram Type= 6, Freq= 0, CH_1, rank 1
4776 12:43:42.190770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4777 12:43:42.191207 ==
4778 12:43:42.191546 DQS Delay:
4779 12:43:42.191873 DQS0 = 0, DQS1 = 0
4780 12:43:42.194126 DQM Delay:
4781 12:43:42.194683 DQM0 = 38, DQM1 = 31
4782 12:43:42.197225 DQ Delay:
4783 12:43:42.200602 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4784 12:43:42.204124 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4785 12:43:42.207177 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4786 12:43:42.210710 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =41
4787 12:43:42.211145
4788 12:43:42.211495
4789 12:43:42.211822 ==
4790 12:43:42.213833 Dram Type= 6, Freq= 0, CH_1, rank 1
4791 12:43:42.217427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4792 12:43:42.218016 ==
4793 12:43:42.218382
4794 12:43:42.218699
4795 12:43:42.220537 TX Vref Scan disable
4796 12:43:42.221046 == TX Byte 0 ==
4797 12:43:42.227084 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4798 12:43:42.230566 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4799 12:43:42.230995 == TX Byte 1 ==
4800 12:43:42.237010 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4801 12:43:42.240231 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4802 12:43:42.240682 ==
4803 12:43:42.243667 Dram Type= 6, Freq= 0, CH_1, rank 1
4804 12:43:42.246832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4805 12:43:42.247282 ==
4806 12:43:42.249991
4807 12:43:42.250552
4808 12:43:42.250902 TX Vref Scan disable
4809 12:43:42.253870 == TX Byte 0 ==
4810 12:43:42.256976 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4811 12:43:42.263584 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4812 12:43:42.264025 == TX Byte 1 ==
4813 12:43:42.267110 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4814 12:43:42.273895 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4815 12:43:42.274356
4816 12:43:42.274882 [DATLAT]
4817 12:43:42.275334 Freq=600, CH1 RK1
4818 12:43:42.275649
4819 12:43:42.276843 DATLAT Default: 0x9
4820 12:43:42.277273 0, 0xFFFF, sum = 0
4821 12:43:42.280346 1, 0xFFFF, sum = 0
4822 12:43:42.280907 2, 0xFFFF, sum = 0
4823 12:43:42.283515 3, 0xFFFF, sum = 0
4824 12:43:42.286699 4, 0xFFFF, sum = 0
4825 12:43:42.287124 5, 0xFFFF, sum = 0
4826 12:43:42.290429 6, 0xFFFF, sum = 0
4827 12:43:42.290856 7, 0xFFFF, sum = 0
4828 12:43:42.293633 8, 0x0, sum = 1
4829 12:43:42.294089 9, 0x0, sum = 2
4830 12:43:42.294433 10, 0x0, sum = 3
4831 12:43:42.297162 11, 0x0, sum = 4
4832 12:43:42.297641 best_step = 9
4833 12:43:42.297995
4834 12:43:42.298320 ==
4835 12:43:42.300228 Dram Type= 6, Freq= 0, CH_1, rank 1
4836 12:43:42.307006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4837 12:43:42.307451 ==
4838 12:43:42.307805 RX Vref Scan: 0
4839 12:43:42.308135
4840 12:43:42.310142 RX Vref 0 -> 0, step: 1
4841 12:43:42.310563
4842 12:43:42.313547 RX Delay -195 -> 252, step: 8
4843 12:43:42.317039 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4844 12:43:42.323417 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4845 12:43:42.326900 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4846 12:43:42.330054 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4847 12:43:42.333468 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4848 12:43:42.340066 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4849 12:43:42.343630 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4850 12:43:42.346606 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4851 12:43:42.350124 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4852 12:43:42.353344 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4853 12:43:42.360120 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4854 12:43:42.363470 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4855 12:43:42.366613 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4856 12:43:42.369913 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4857 12:43:42.376498 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4858 12:43:42.379965 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4859 12:43:42.380386 ==
4860 12:43:42.383202 Dram Type= 6, Freq= 0, CH_1, rank 1
4861 12:43:42.386553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4862 12:43:42.386977 ==
4863 12:43:42.389841 DQS Delay:
4864 12:43:42.390263 DQS0 = 0, DQS1 = 0
4865 12:43:42.390603 DQM Delay:
4866 12:43:42.393216 DQM0 = 36, DQM1 = 30
4867 12:43:42.393676 DQ Delay:
4868 12:43:42.396657 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4869 12:43:42.399896 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4870 12:43:42.402948 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4871 12:43:42.406238 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4872 12:43:42.406787
4873 12:43:42.407131
4874 12:43:42.416470 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b5a, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4875 12:43:42.419767 CH1 RK1: MR19=808, MR18=3B5A
4876 12:43:42.422943 CH1_RK1: MR19=0x808, MR18=0x3B5A, DQSOSC=392, MR23=63, INC=170, DEC=113
4877 12:43:42.426395 [RxdqsGatingPostProcess] freq 600
4878 12:43:42.432737 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4879 12:43:42.436270 Pre-setting of DQS Precalculation
4880 12:43:42.439475 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4881 12:43:42.449404 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4882 12:43:42.455998 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4883 12:43:42.456439
4884 12:43:42.456887
4885 12:43:42.459264 [Calibration Summary] 1200 Mbps
4886 12:43:42.459699 CH 0, Rank 0
4887 12:43:42.462513 SW Impedance : PASS
4888 12:43:42.462951 DUTY Scan : NO K
4889 12:43:42.465954 ZQ Calibration : PASS
4890 12:43:42.469505 Jitter Meter : NO K
4891 12:43:42.469954 CBT Training : PASS
4892 12:43:42.472568 Write leveling : PASS
4893 12:43:42.476030 RX DQS gating : PASS
4894 12:43:42.476469 RX DQ/DQS(RDDQC) : PASS
4895 12:43:42.479205 TX DQ/DQS : PASS
4896 12:43:42.482375 RX DATLAT : PASS
4897 12:43:42.482815 RX DQ/DQS(Engine): PASS
4898 12:43:42.485937 TX OE : NO K
4899 12:43:42.486377 All Pass.
4900 12:43:42.486827
4901 12:43:42.488958 CH 0, Rank 1
4902 12:43:42.489412 SW Impedance : PASS
4903 12:43:42.492518 DUTY Scan : NO K
4904 12:43:42.495892 ZQ Calibration : PASS
4905 12:43:42.496329 Jitter Meter : NO K
4906 12:43:42.498959 CBT Training : PASS
4907 12:43:42.499399 Write leveling : PASS
4908 12:43:42.502399 RX DQS gating : PASS
4909 12:43:42.505556 RX DQ/DQS(RDDQC) : PASS
4910 12:43:42.505998 TX DQ/DQS : PASS
4911 12:43:42.509009 RX DATLAT : PASS
4912 12:43:42.512444 RX DQ/DQS(Engine): PASS
4913 12:43:42.512883 TX OE : NO K
4914 12:43:42.515603 All Pass.
4915 12:43:42.516037
4916 12:43:42.516481 CH 1, Rank 0
4917 12:43:42.518800 SW Impedance : PASS
4918 12:43:42.519240 DUTY Scan : NO K
4919 12:43:42.522454 ZQ Calibration : PASS
4920 12:43:42.525546 Jitter Meter : NO K
4921 12:43:42.525988 CBT Training : PASS
4922 12:43:42.528841 Write leveling : PASS
4923 12:43:42.532225 RX DQS gating : PASS
4924 12:43:42.532672 RX DQ/DQS(RDDQC) : PASS
4925 12:43:42.535591 TX DQ/DQS : PASS
4926 12:43:42.538935 RX DATLAT : PASS
4927 12:43:42.539374 RX DQ/DQS(Engine): PASS
4928 12:43:42.542282 TX OE : NO K
4929 12:43:42.542740 All Pass.
4930 12:43:42.543188
4931 12:43:42.545279 CH 1, Rank 1
4932 12:43:42.545784 SW Impedance : PASS
4933 12:43:42.548760 DUTY Scan : NO K
4934 12:43:42.552104 ZQ Calibration : PASS
4935 12:43:42.552543 Jitter Meter : NO K
4936 12:43:42.555175 CBT Training : PASS
4937 12:43:42.555768 Write leveling : PASS
4938 12:43:42.558796 RX DQS gating : PASS
4939 12:43:42.562049 RX DQ/DQS(RDDQC) : PASS
4940 12:43:42.562487 TX DQ/DQS : PASS
4941 12:43:42.565323 RX DATLAT : PASS
4942 12:43:42.568506 RX DQ/DQS(Engine): PASS
4943 12:43:42.568944 TX OE : NO K
4944 12:43:42.571875 All Pass.
4945 12:43:42.572326
4946 12:43:42.572853 DramC Write-DBI off
4947 12:43:42.575079 PER_BANK_REFRESH: Hybrid Mode
4948 12:43:42.578488 TX_TRACKING: ON
4949 12:43:42.585150 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4950 12:43:42.588566 [FAST_K] Save calibration result to emmc
4951 12:43:42.591679 dramc_set_vcore_voltage set vcore to 662500
4952 12:43:42.594886 Read voltage for 933, 3
4953 12:43:42.595319 Vio18 = 0
4954 12:43:42.598394 Vcore = 662500
4955 12:43:42.598814 Vdram = 0
4956 12:43:42.599148 Vddq = 0
4957 12:43:42.601707 Vmddr = 0
4958 12:43:42.604855 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4959 12:43:42.611571 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4960 12:43:42.611995 MEM_TYPE=3, freq_sel=17
4961 12:43:42.614790 sv_algorithm_assistance_LP4_1600
4962 12:43:42.621411 ============ PULL DRAM RESETB DOWN ============
4963 12:43:42.624859 ========== PULL DRAM RESETB DOWN end =========
4964 12:43:42.627979 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4965 12:43:42.631503 ===================================
4966 12:43:42.634847 LPDDR4 DRAM CONFIGURATION
4967 12:43:42.637980 ===================================
4968 12:43:42.641427 EX_ROW_EN[0] = 0x0
4969 12:43:42.641900 EX_ROW_EN[1] = 0x0
4970 12:43:42.644673 LP4Y_EN = 0x0
4971 12:43:42.645105 WORK_FSP = 0x0
4972 12:43:42.647807 WL = 0x3
4973 12:43:42.648245 RL = 0x3
4974 12:43:42.651265 BL = 0x2
4975 12:43:42.651701 RPST = 0x0
4976 12:43:42.654577 RD_PRE = 0x0
4977 12:43:42.655013 WR_PRE = 0x1
4978 12:43:42.657921 WR_PST = 0x0
4979 12:43:42.658354 DBI_WR = 0x0
4980 12:43:42.661047 DBI_RD = 0x0
4981 12:43:42.661628 OTF = 0x1
4982 12:43:42.664334 ===================================
4983 12:43:42.667851 ===================================
4984 12:43:42.670945 ANA top config
4985 12:43:42.674413 ===================================
4986 12:43:42.677501 DLL_ASYNC_EN = 0
4987 12:43:42.677938 ALL_SLAVE_EN = 1
4988 12:43:42.680837 NEW_RANK_MODE = 1
4989 12:43:42.684168 DLL_IDLE_MODE = 1
4990 12:43:42.687405 LP45_APHY_COMB_EN = 1
4991 12:43:42.687823 TX_ODT_DIS = 1
4992 12:43:42.690861 NEW_8X_MODE = 1
4993 12:43:42.694350 ===================================
4994 12:43:42.697377 ===================================
4995 12:43:42.700767 data_rate = 1866
4996 12:43:42.703924 CKR = 1
4997 12:43:42.707388 DQ_P2S_RATIO = 8
4998 12:43:42.710878 ===================================
4999 12:43:42.714011 CA_P2S_RATIO = 8
5000 12:43:42.714432 DQ_CA_OPEN = 0
5001 12:43:42.717424 DQ_SEMI_OPEN = 0
5002 12:43:42.720482 CA_SEMI_OPEN = 0
5003 12:43:42.724051 CA_FULL_RATE = 0
5004 12:43:42.727174 DQ_CKDIV4_EN = 1
5005 12:43:42.730780 CA_CKDIV4_EN = 1
5006 12:43:42.731202 CA_PREDIV_EN = 0
5007 12:43:42.733949 PH8_DLY = 0
5008 12:43:42.737244 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5009 12:43:42.740787 DQ_AAMCK_DIV = 4
5010 12:43:42.743811 CA_AAMCK_DIV = 4
5011 12:43:42.747351 CA_ADMCK_DIV = 4
5012 12:43:42.747769 DQ_TRACK_CA_EN = 0
5013 12:43:42.750459 CA_PICK = 933
5014 12:43:42.753943 CA_MCKIO = 933
5015 12:43:42.756988 MCKIO_SEMI = 0
5016 12:43:42.760556 PLL_FREQ = 3732
5017 12:43:42.763929 DQ_UI_PI_RATIO = 32
5018 12:43:42.767382 CA_UI_PI_RATIO = 0
5019 12:43:42.770435 ===================================
5020 12:43:42.773557 ===================================
5021 12:43:42.773979 memory_type:LPDDR4
5022 12:43:42.776841 GP_NUM : 10
5023 12:43:42.780178 SRAM_EN : 1
5024 12:43:42.780696 MD32_EN : 0
5025 12:43:42.783748 ===================================
5026 12:43:42.786989 [ANA_INIT] >>>>>>>>>>>>>>
5027 12:43:42.790111 <<<<<< [CONFIGURE PHASE]: ANA_TX
5028 12:43:42.793407 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5029 12:43:42.796694 ===================================
5030 12:43:42.800223 data_rate = 1866,PCW = 0X8f00
5031 12:43:42.803423 ===================================
5032 12:43:42.806887 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5033 12:43:42.810216 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5034 12:43:42.816701 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5035 12:43:42.820196 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5036 12:43:42.823546 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5037 12:43:42.826738 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5038 12:43:42.830213 [ANA_INIT] flow start
5039 12:43:42.833429 [ANA_INIT] PLL >>>>>>>>
5040 12:43:42.833888 [ANA_INIT] PLL <<<<<<<<
5041 12:43:42.836910 [ANA_INIT] MIDPI >>>>>>>>
5042 12:43:42.840435 [ANA_INIT] MIDPI <<<<<<<<
5043 12:43:42.843595 [ANA_INIT] DLL >>>>>>>>
5044 12:43:42.844016 [ANA_INIT] flow end
5045 12:43:42.846643 ============ LP4 DIFF to SE enter ============
5046 12:43:42.853541 ============ LP4 DIFF to SE exit ============
5047 12:43:42.853967 [ANA_INIT] <<<<<<<<<<<<<
5048 12:43:42.856716 [Flow] Enable top DCM control >>>>>
5049 12:43:42.860263 [Flow] Enable top DCM control <<<<<
5050 12:43:42.863465 Enable DLL master slave shuffle
5051 12:43:42.870153 ==============================================================
5052 12:43:42.870574 Gating Mode config
5053 12:43:42.876822 ==============================================================
5054 12:43:42.879887 Config description:
5055 12:43:42.889842 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5056 12:43:42.896461 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5057 12:43:42.899584 SELPH_MODE 0: By rank 1: By Phase
5058 12:43:42.906381 ==============================================================
5059 12:43:42.909538 GAT_TRACK_EN = 1
5060 12:43:42.909968 RX_GATING_MODE = 2
5061 12:43:42.912935 RX_GATING_TRACK_MODE = 2
5062 12:43:42.915983 SELPH_MODE = 1
5063 12:43:42.919591 PICG_EARLY_EN = 1
5064 12:43:42.922670 VALID_LAT_VALUE = 1
5065 12:43:42.929539 ==============================================================
5066 12:43:42.932758 Enter into Gating configuration >>>>
5067 12:43:42.936080 Exit from Gating configuration <<<<
5068 12:43:42.939355 Enter into DVFS_PRE_config >>>>>
5069 12:43:42.949419 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5070 12:43:42.952863 Exit from DVFS_PRE_config <<<<<
5071 12:43:42.956421 Enter into PICG configuration >>>>
5072 12:43:42.959515 Exit from PICG configuration <<<<
5073 12:43:42.962917 [RX_INPUT] configuration >>>>>
5074 12:43:42.965986 [RX_INPUT] configuration <<<<<
5075 12:43:42.969542 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5076 12:43:42.976211 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5077 12:43:42.982553 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5078 12:43:42.986159 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5079 12:43:42.992752 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5080 12:43:42.999211 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5081 12:43:43.002618 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5082 12:43:43.009453 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5083 12:43:43.012542 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5084 12:43:43.016007 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5085 12:43:43.019341 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5086 12:43:43.025745 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5087 12:43:43.029132 ===================================
5088 12:43:43.029600 LPDDR4 DRAM CONFIGURATION
5089 12:43:43.032445 ===================================
5090 12:43:43.035676 EX_ROW_EN[0] = 0x0
5091 12:43:43.039100 EX_ROW_EN[1] = 0x0
5092 12:43:43.039542 LP4Y_EN = 0x0
5093 12:43:43.042533 WORK_FSP = 0x0
5094 12:43:43.042956 WL = 0x3
5095 12:43:43.045628 RL = 0x3
5096 12:43:43.046198 BL = 0x2
5097 12:43:43.048821 RPST = 0x0
5098 12:43:43.049240 RD_PRE = 0x0
5099 12:43:43.052555 WR_PRE = 0x1
5100 12:43:43.052975 WR_PST = 0x0
5101 12:43:43.055495 DBI_WR = 0x0
5102 12:43:43.056081 DBI_RD = 0x0
5103 12:43:43.059023 OTF = 0x1
5104 12:43:43.062249 ===================================
5105 12:43:43.065405 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5106 12:43:43.068823 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5107 12:43:43.075451 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5108 12:43:43.078847 ===================================
5109 12:43:43.079292 LPDDR4 DRAM CONFIGURATION
5110 12:43:43.081909 ===================================
5111 12:43:43.085286 EX_ROW_EN[0] = 0x10
5112 12:43:43.088814 EX_ROW_EN[1] = 0x0
5113 12:43:43.089237 LP4Y_EN = 0x0
5114 12:43:43.091932 WORK_FSP = 0x0
5115 12:43:43.092356 WL = 0x3
5116 12:43:43.095652 RL = 0x3
5117 12:43:43.096076 BL = 0x2
5118 12:43:43.098499 RPST = 0x0
5119 12:43:43.098925 RD_PRE = 0x0
5120 12:43:43.101994 WR_PRE = 0x1
5121 12:43:43.102422 WR_PST = 0x0
5122 12:43:43.105457 DBI_WR = 0x0
5123 12:43:43.105918 DBI_RD = 0x0
5124 12:43:43.108750 OTF = 0x1
5125 12:43:43.111873 ===================================
5126 12:43:43.118597 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5127 12:43:43.121841 nWR fixed to 30
5128 12:43:43.122264 [ModeRegInit_LP4] CH0 RK0
5129 12:43:43.125258 [ModeRegInit_LP4] CH0 RK1
5130 12:43:43.128411 [ModeRegInit_LP4] CH1 RK0
5131 12:43:43.131946 [ModeRegInit_LP4] CH1 RK1
5132 12:43:43.132367 match AC timing 9
5133 12:43:43.135319 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5134 12:43:43.141854 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5135 12:43:43.145272 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5136 12:43:43.154865 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5137 12:43:43.155292 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5138 12:43:43.155628 ==
5139 12:43:43.158412 Dram Type= 6, Freq= 0, CH_0, rank 0
5140 12:43:43.161732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5141 12:43:43.162157 ==
5142 12:43:43.168340 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5143 12:43:43.175134 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5144 12:43:43.178307 [CA 0] Center 38 (8~69) winsize 62
5145 12:43:43.181425 [CA 1] Center 38 (7~69) winsize 63
5146 12:43:43.184719 [CA 2] Center 36 (6~66) winsize 61
5147 12:43:43.188153 [CA 3] Center 35 (5~65) winsize 61
5148 12:43:43.191537 [CA 4] Center 34 (4~65) winsize 62
5149 12:43:43.195033 [CA 5] Center 33 (3~64) winsize 62
5150 12:43:43.195547
5151 12:43:43.198023 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5152 12:43:43.198498
5153 12:43:43.201430 [CATrainingPosCal] consider 1 rank data
5154 12:43:43.205012 u2DelayCellTimex100 = 270/100 ps
5155 12:43:43.208222 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5156 12:43:43.211586 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5157 12:43:43.214687 CA2 delay=36 (6~66),Diff = 3 PI (18 cell)
5158 12:43:43.217856 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5159 12:43:43.221493 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5160 12:43:43.224582 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5161 12:43:43.225083
5162 12:43:43.231236 CA PerBit enable=1, Macro0, CA PI delay=33
5163 12:43:43.231751
5164 12:43:43.232106 [CBTSetCACLKResult] CA Dly = 33
5165 12:43:43.234616 CS Dly: 7 (0~38)
5166 12:43:43.235129 ==
5167 12:43:43.238011 Dram Type= 6, Freq= 0, CH_0, rank 1
5168 12:43:43.241092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5169 12:43:43.241548 ==
5170 12:43:43.247902 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5171 12:43:43.254590 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5172 12:43:43.257927 [CA 0] Center 38 (8~69) winsize 62
5173 12:43:43.260980 [CA 1] Center 38 (7~69) winsize 63
5174 12:43:43.264509 [CA 2] Center 35 (5~66) winsize 62
5175 12:43:43.267715 [CA 3] Center 35 (5~66) winsize 62
5176 12:43:43.271125 [CA 4] Center 34 (4~65) winsize 62
5177 12:43:43.274356 [CA 5] Center 34 (4~64) winsize 61
5178 12:43:43.274797
5179 12:43:43.278019 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5180 12:43:43.278462
5181 12:43:43.281269 [CATrainingPosCal] consider 2 rank data
5182 12:43:43.284458 u2DelayCellTimex100 = 270/100 ps
5183 12:43:43.287730 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5184 12:43:43.291163 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5185 12:43:43.294042 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5186 12:43:43.297579 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5187 12:43:43.300955 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5188 12:43:43.304390 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5189 12:43:43.307519
5190 12:43:43.310963 CA PerBit enable=1, Macro0, CA PI delay=34
5191 12:43:43.311349
5192 12:43:43.314270 [CBTSetCACLKResult] CA Dly = 34
5193 12:43:43.314626 CS Dly: 7 (0~39)
5194 12:43:43.314960
5195 12:43:43.317549 ----->DramcWriteLeveling(PI) begin...
5196 12:43:43.317928 ==
5197 12:43:43.320668 Dram Type= 6, Freq= 0, CH_0, rank 0
5198 12:43:43.324020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5199 12:43:43.327403 ==
5200 12:43:43.327983 Write leveling (Byte 0): 30 => 30
5201 12:43:43.330649 Write leveling (Byte 1): 30 => 30
5202 12:43:43.334064 DramcWriteLeveling(PI) end<-----
5203 12:43:43.334486
5204 12:43:43.334819 ==
5205 12:43:43.337244 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 12:43:43.344001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 12:43:43.344430 ==
5208 12:43:43.347433 [Gating] SW mode calibration
5209 12:43:43.353811 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5210 12:43:43.357173 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5211 12:43:43.363726 0 14 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5212 12:43:43.367132 0 14 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5213 12:43:43.370513 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5214 12:43:43.377195 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5215 12:43:43.380563 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5216 12:43:43.383678 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5217 12:43:43.390365 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5218 12:43:43.393553 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5219 12:43:43.397169 0 15 0 | B1->B0 | 3434 2b2b | 0 0 | (0 0) (0 0)
5220 12:43:43.403583 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5221 12:43:43.407032 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5222 12:43:43.410082 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5223 12:43:43.413582 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5224 12:43:43.420109 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5225 12:43:43.423484 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5226 12:43:43.426748 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5227 12:43:43.433559 1 0 0 | B1->B0 | 2b2b 3b3b | 0 0 | (0 0) (0 0)
5228 12:43:43.436963 1 0 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5229 12:43:43.440161 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5230 12:43:43.446186 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5231 12:43:43.449859 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5232 12:43:43.453069 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5233 12:43:43.459675 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5234 12:43:43.462725 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5235 12:43:43.466512 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5236 12:43:43.472772 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5237 12:43:43.476321 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5238 12:43:43.479952 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5239 12:43:43.486068 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5240 12:43:43.489430 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5241 12:43:43.492608 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5242 12:43:43.499333 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5243 12:43:43.502667 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5244 12:43:43.506056 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5245 12:43:43.512824 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5246 12:43:43.516036 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5247 12:43:43.519615 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5248 12:43:43.525876 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5249 12:43:43.529305 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5250 12:43:43.532515 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5251 12:43:43.539054 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5252 12:43:43.539137 Total UI for P1: 0, mck2ui 16
5253 12:43:43.545800 best dqsien dly found for B0: ( 1, 2, 30)
5254 12:43:43.549172 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5255 12:43:43.552512 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5256 12:43:43.555830 Total UI for P1: 0, mck2ui 16
5257 12:43:43.558932 best dqsien dly found for B1: ( 1, 3, 2)
5258 12:43:43.562296 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5259 12:43:43.565637 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5260 12:43:43.565720
5261 12:43:43.569129 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5262 12:43:43.575653 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5263 12:43:43.575739 [Gating] SW calibration Done
5264 12:43:43.575805 ==
5265 12:43:43.579052 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 12:43:43.585602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 12:43:43.585685 ==
5268 12:43:43.585751 RX Vref Scan: 0
5269 12:43:43.585812
5270 12:43:43.589403 RX Vref 0 -> 0, step: 1
5271 12:43:43.589505
5272 12:43:43.592459 RX Delay -80 -> 252, step: 8
5273 12:43:43.595620 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5274 12:43:43.599052 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5275 12:43:43.602204 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5276 12:43:43.605471 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5277 12:43:43.612040 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5278 12:43:43.615601 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5279 12:43:43.618653 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5280 12:43:43.622203 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5281 12:43:43.625457 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5282 12:43:43.628793 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5283 12:43:43.635528 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5284 12:43:43.638975 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5285 12:43:43.642115 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5286 12:43:43.645576 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5287 12:43:43.651893 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5288 12:43:43.655272 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5289 12:43:43.655355 ==
5290 12:43:43.658528 Dram Type= 6, Freq= 0, CH_0, rank 0
5291 12:43:43.661941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 12:43:43.662024 ==
5293 12:43:43.665193 DQS Delay:
5294 12:43:43.665274 DQS0 = 0, DQS1 = 0
5295 12:43:43.665339 DQM Delay:
5296 12:43:43.668441 DQM0 = 94, DQM1 = 84
5297 12:43:43.668524 DQ Delay:
5298 12:43:43.671940 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5299 12:43:43.675096 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5300 12:43:43.678587 DQ8 =79, DQ9 =75, DQ10 =83, DQ11 =79
5301 12:43:43.682004 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5302 12:43:43.682086
5303 12:43:43.682150
5304 12:43:43.682209 ==
5305 12:43:43.685328 Dram Type= 6, Freq= 0, CH_0, rank 0
5306 12:43:43.691677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5307 12:43:43.691759 ==
5308 12:43:43.691825
5309 12:43:43.691884
5310 12:43:43.691942 TX Vref Scan disable
5311 12:43:43.694897 == TX Byte 0 ==
5312 12:43:43.698454 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5313 12:43:43.705000 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5314 12:43:43.705082 == TX Byte 1 ==
5315 12:43:43.708468 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5316 12:43:43.714825 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5317 12:43:43.714912 ==
5318 12:43:43.718240 Dram Type= 6, Freq= 0, CH_0, rank 0
5319 12:43:43.721584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5320 12:43:43.721657 ==
5321 12:43:43.721723
5322 12:43:43.721783
5323 12:43:43.725037 TX Vref Scan disable
5324 12:43:43.725129 == TX Byte 0 ==
5325 12:43:43.731351 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5326 12:43:43.734882 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5327 12:43:43.734955 == TX Byte 1 ==
5328 12:43:43.741634 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5329 12:43:43.745046 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5330 12:43:43.745138
5331 12:43:43.745227 [DATLAT]
5332 12:43:43.748166 Freq=933, CH0 RK0
5333 12:43:43.748265
5334 12:43:43.748355 DATLAT Default: 0xd
5335 12:43:43.751467 0, 0xFFFF, sum = 0
5336 12:43:43.751562 1, 0xFFFF, sum = 0
5337 12:43:43.754927 2, 0xFFFF, sum = 0
5338 12:43:43.755031 3, 0xFFFF, sum = 0
5339 12:43:43.758218 4, 0xFFFF, sum = 0
5340 12:43:43.758289 5, 0xFFFF, sum = 0
5341 12:43:43.761326 6, 0xFFFF, sum = 0
5342 12:43:43.764600 7, 0xFFFF, sum = 0
5343 12:43:43.764683 8, 0xFFFF, sum = 0
5344 12:43:43.767976 9, 0xFFFF, sum = 0
5345 12:43:43.768085 10, 0x0, sum = 1
5346 12:43:43.771328 11, 0x0, sum = 2
5347 12:43:43.771526 12, 0x0, sum = 3
5348 12:43:43.771651 13, 0x0, sum = 4
5349 12:43:43.774384 best_step = 11
5350 12:43:43.774524
5351 12:43:43.774624 ==
5352 12:43:43.777902 Dram Type= 6, Freq= 0, CH_0, rank 0
5353 12:43:43.781111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5354 12:43:43.781201 ==
5355 12:43:43.784529 RX Vref Scan: 1
5356 12:43:43.784611
5357 12:43:43.784675 RX Vref 0 -> 0, step: 1
5358 12:43:43.787854
5359 12:43:43.787936 RX Delay -69 -> 252, step: 4
5360 12:43:43.788002
5361 12:43:43.791052 Set Vref, RX VrefLevel [Byte0]: 60
5362 12:43:43.794572 [Byte1]: 52
5363 12:43:43.799288
5364 12:43:43.799370 Final RX Vref Byte 0 = 60 to rank0
5365 12:43:43.802399 Final RX Vref Byte 1 = 52 to rank0
5366 12:43:43.805607 Final RX Vref Byte 0 = 60 to rank1
5367 12:43:43.808860 Final RX Vref Byte 1 = 52 to rank1==
5368 12:43:43.812177 Dram Type= 6, Freq= 0, CH_0, rank 0
5369 12:43:43.818796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 12:43:43.818878 ==
5371 12:43:43.818943 DQS Delay:
5372 12:43:43.819004 DQS0 = 0, DQS1 = 0
5373 12:43:43.822272 DQM Delay:
5374 12:43:43.822378 DQM0 = 95, DQM1 = 83
5375 12:43:43.825397 DQ Delay:
5376 12:43:43.828720 DQ0 =94, DQ1 =98, DQ2 =92, DQ3 =94
5377 12:43:43.832177 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106
5378 12:43:43.835358 DQ8 =76, DQ9 =70, DQ10 =82, DQ11 =78
5379 12:43:43.838854 DQ12 =86, DQ13 =88, DQ14 =94, DQ15 =90
5380 12:43:43.838935
5381 12:43:43.839000
5382 12:43:43.845643 [DQSOSCAuto] RK0, (LSB)MR18= 0x100f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 416 ps
5383 12:43:43.848639 CH0 RK0: MR19=505, MR18=100F
5384 12:43:43.855642 CH0_RK0: MR19=0x505, MR18=0x100F, DQSOSC=416, MR23=63, INC=62, DEC=41
5385 12:43:43.855724
5386 12:43:43.858800 ----->DramcWriteLeveling(PI) begin...
5387 12:43:43.858884 ==
5388 12:43:43.862244 Dram Type= 6, Freq= 0, CH_0, rank 1
5389 12:43:43.865336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5390 12:43:43.865444 ==
5391 12:43:43.868801 Write leveling (Byte 0): 31 => 31
5392 12:43:43.872283 Write leveling (Byte 1): 29 => 29
5393 12:43:43.875507 DramcWriteLeveling(PI) end<-----
5394 12:43:43.875589
5395 12:43:43.875653 ==
5396 12:43:43.878759 Dram Type= 6, Freq= 0, CH_0, rank 1
5397 12:43:43.882016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5398 12:43:43.882099 ==
5399 12:43:43.885394 [Gating] SW mode calibration
5400 12:43:43.892258 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5401 12:43:43.898600 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5402 12:43:43.901913 0 14 0 | B1->B0 | 2323 3434 | 1 1 | (0 0) (1 1)
5403 12:43:43.908576 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5404 12:43:43.911684 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5405 12:43:43.915158 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5406 12:43:43.921439 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5407 12:43:43.925021 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5408 12:43:43.928099 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5409 12:43:43.934801 0 14 28 | B1->B0 | 3333 2626 | 1 0 | (1 1) (1 0)
5410 12:43:43.938349 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5411 12:43:43.941461 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5412 12:43:43.947999 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5413 12:43:43.951381 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5414 12:43:43.954529 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5415 12:43:43.961357 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5416 12:43:43.964402 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5417 12:43:43.968014 0 15 28 | B1->B0 | 2525 3535 | 0 0 | (0 0) (0 0)
5418 12:43:43.974436 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5419 12:43:43.978092 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5420 12:43:43.981077 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5421 12:43:43.987602 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5422 12:43:43.991149 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5423 12:43:43.994370 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5424 12:43:43.997639 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5425 12:43:44.004469 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5426 12:43:44.007477 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5427 12:43:44.010805 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 12:43:44.017368 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 12:43:44.020581 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 12:43:44.024039 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 12:43:44.030748 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 12:43:44.034330 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 12:43:44.037126 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 12:43:44.043830 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 12:43:44.047103 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 12:43:44.050440 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5437 12:43:44.057225 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 12:43:44.060420 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 12:43:44.063850 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 12:43:44.070504 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5441 12:43:44.073668 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5442 12:43:44.076998 Total UI for P1: 0, mck2ui 16
5443 12:43:44.080475 best dqsien dly found for B0: ( 1, 2, 24)
5444 12:43:44.083524 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5445 12:43:44.090144 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5446 12:43:44.090227 Total UI for P1: 0, mck2ui 16
5447 12:43:44.096902 best dqsien dly found for B1: ( 1, 2, 30)
5448 12:43:44.100150 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5449 12:43:44.103607 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5450 12:43:44.103690
5451 12:43:44.106905 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5452 12:43:44.110081 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5453 12:43:44.113378 [Gating] SW calibration Done
5454 12:43:44.113507 ==
5455 12:43:44.116697 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 12:43:44.120072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 12:43:44.120155 ==
5458 12:43:44.123503 RX Vref Scan: 0
5459 12:43:44.123586
5460 12:43:44.123651 RX Vref 0 -> 0, step: 1
5461 12:43:44.123712
5462 12:43:44.126775 RX Delay -80 -> 252, step: 8
5463 12:43:44.133190 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5464 12:43:44.136778 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5465 12:43:44.139923 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5466 12:43:44.143512 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5467 12:43:44.146708 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5468 12:43:44.149759 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5469 12:43:44.156470 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5470 12:43:44.159916 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5471 12:43:44.163017 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5472 12:43:44.166442 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5473 12:43:44.169775 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5474 12:43:44.176292 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5475 12:43:44.179627 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5476 12:43:44.183024 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5477 12:43:44.186164 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5478 12:43:44.189610 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5479 12:43:44.192755 ==
5480 12:43:44.196244 Dram Type= 6, Freq= 0, CH_0, rank 1
5481 12:43:44.199463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 12:43:44.199546 ==
5483 12:43:44.199611 DQS Delay:
5484 12:43:44.202703 DQS0 = 0, DQS1 = 0
5485 12:43:44.202785 DQM Delay:
5486 12:43:44.206108 DQM0 = 92, DQM1 = 82
5487 12:43:44.206190 DQ Delay:
5488 12:43:44.209508 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5489 12:43:44.212974 DQ4 =91, DQ5 =75, DQ6 =107, DQ7 =107
5490 12:43:44.216180 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5491 12:43:44.219225 DQ12 =91, DQ13 =87, DQ14 =91, DQ15 =87
5492 12:43:44.219308
5493 12:43:44.219372
5494 12:43:44.219432 ==
5495 12:43:44.222890 Dram Type= 6, Freq= 0, CH_0, rank 1
5496 12:43:44.225861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5497 12:43:44.225944 ==
5498 12:43:44.226009
5499 12:43:44.226068
5500 12:43:44.229200 TX Vref Scan disable
5501 12:43:44.232759 == TX Byte 0 ==
5502 12:43:44.235880 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5503 12:43:44.239183 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5504 12:43:44.242604 == TX Byte 1 ==
5505 12:43:44.245807 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5506 12:43:44.249101 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5507 12:43:44.249183 ==
5508 12:43:44.252621 Dram Type= 6, Freq= 0, CH_0, rank 1
5509 12:43:44.259240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5510 12:43:44.259323 ==
5511 12:43:44.259389
5512 12:43:44.259449
5513 12:43:44.259505 TX Vref Scan disable
5514 12:43:44.262824 == TX Byte 0 ==
5515 12:43:44.266191 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5516 12:43:44.273094 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5517 12:43:44.273194 == TX Byte 1 ==
5518 12:43:44.276101 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5519 12:43:44.283196 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5520 12:43:44.283275
5521 12:43:44.283341 [DATLAT]
5522 12:43:44.283400 Freq=933, CH0 RK1
5523 12:43:44.283456
5524 12:43:44.286318 DATLAT Default: 0xb
5525 12:43:44.286384 0, 0xFFFF, sum = 0
5526 12:43:44.289444 1, 0xFFFF, sum = 0
5527 12:43:44.289537 2, 0xFFFF, sum = 0
5528 12:43:44.293064 3, 0xFFFF, sum = 0
5529 12:43:44.296218 4, 0xFFFF, sum = 0
5530 12:43:44.296317 5, 0xFFFF, sum = 0
5531 12:43:44.299660 6, 0xFFFF, sum = 0
5532 12:43:44.299754 7, 0xFFFF, sum = 0
5533 12:43:44.302675 8, 0xFFFF, sum = 0
5534 12:43:44.302744 9, 0xFFFF, sum = 0
5535 12:43:44.306117 10, 0x0, sum = 1
5536 12:43:44.306184 11, 0x0, sum = 2
5537 12:43:44.309347 12, 0x0, sum = 3
5538 12:43:44.309446 13, 0x0, sum = 4
5539 12:43:44.309526 best_step = 11
5540 12:43:44.309585
5541 12:43:44.312520 ==
5542 12:43:44.315988 Dram Type= 6, Freq= 0, CH_0, rank 1
5543 12:43:44.319374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5544 12:43:44.319472 ==
5545 12:43:44.319566 RX Vref Scan: 0
5546 12:43:44.319655
5547 12:43:44.322674 RX Vref 0 -> 0, step: 1
5548 12:43:44.322743
5549 12:43:44.326095 RX Delay -69 -> 252, step: 4
5550 12:43:44.329362 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5551 12:43:44.335891 iDelay=199, Bit 1, Center 92 (-1 ~ 186) 188
5552 12:43:44.339561 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5553 12:43:44.342555 iDelay=199, Bit 3, Center 86 (-9 ~ 182) 192
5554 12:43:44.345820 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5555 12:43:44.349092 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5556 12:43:44.356063 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5557 12:43:44.359054 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5558 12:43:44.362562 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5559 12:43:44.365649 iDelay=199, Bit 9, Center 70 (-17 ~ 158) 176
5560 12:43:44.369037 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5561 12:43:44.375576 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5562 12:43:44.379202 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5563 12:43:44.382347 iDelay=199, Bit 13, Center 88 (-5 ~ 182) 188
5564 12:43:44.385705 iDelay=199, Bit 14, Center 92 (-1 ~ 186) 188
5565 12:43:44.388827 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5566 12:43:44.388924 ==
5567 12:43:44.392216 Dram Type= 6, Freq= 0, CH_0, rank 1
5568 12:43:44.399016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5569 12:43:44.399089 ==
5570 12:43:44.399152 DQS Delay:
5571 12:43:44.402166 DQS0 = 0, DQS1 = 0
5572 12:43:44.402235 DQM Delay:
5573 12:43:44.402294 DQM0 = 92, DQM1 = 83
5574 12:43:44.405644 DQ Delay:
5575 12:43:44.408722 DQ0 =90, DQ1 =92, DQ2 =88, DQ3 =86
5576 12:43:44.412247 DQ4 =92, DQ5 =80, DQ6 =106, DQ7 =102
5577 12:43:44.415496 DQ8 =76, DQ9 =70, DQ10 =86, DQ11 =76
5578 12:43:44.418689 DQ12 =90, DQ13 =88, DQ14 =92, DQ15 =92
5579 12:43:44.418799
5580 12:43:44.418880
5581 12:43:44.425363 [DQSOSCAuto] RK1, (LSB)MR18= 0x3214, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 406 ps
5582 12:43:44.428510 CH0 RK1: MR19=505, MR18=3214
5583 12:43:44.435452 CH0_RK1: MR19=0x505, MR18=0x3214, DQSOSC=406, MR23=63, INC=65, DEC=43
5584 12:43:44.438378 [RxdqsGatingPostProcess] freq 933
5585 12:43:44.445398 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5586 12:43:44.445602 best DQS0 dly(2T, 0.5T) = (0, 10)
5587 12:43:44.448589 best DQS1 dly(2T, 0.5T) = (0, 11)
5588 12:43:44.451717 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5589 12:43:44.454904 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5590 12:43:44.458380 best DQS0 dly(2T, 0.5T) = (0, 10)
5591 12:43:44.461843 best DQS1 dly(2T, 0.5T) = (0, 10)
5592 12:43:44.465371 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5593 12:43:44.468578 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5594 12:43:44.471699 Pre-setting of DQS Precalculation
5595 12:43:44.478399 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5596 12:43:44.478952 ==
5597 12:43:44.481892 Dram Type= 6, Freq= 0, CH_1, rank 0
5598 12:43:44.485249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 12:43:44.485793 ==
5600 12:43:44.491653 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5601 12:43:44.494888 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5602 12:43:44.499172 [CA 0] Center 37 (7~67) winsize 61
5603 12:43:44.502230 [CA 1] Center 37 (7~68) winsize 62
5604 12:43:44.505635 [CA 2] Center 34 (5~64) winsize 60
5605 12:43:44.509119 [CA 3] Center 34 (4~64) winsize 61
5606 12:43:44.512612 [CA 4] Center 34 (5~64) winsize 60
5607 12:43:44.515668 [CA 5] Center 34 (4~64) winsize 61
5608 12:43:44.516093
5609 12:43:44.519168 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5610 12:43:44.519591
5611 12:43:44.522475 [CATrainingPosCal] consider 1 rank data
5612 12:43:44.525538 u2DelayCellTimex100 = 270/100 ps
5613 12:43:44.528830 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5614 12:43:44.535556 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5615 12:43:44.538889 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5616 12:43:44.542327 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5617 12:43:44.545394 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5618 12:43:44.548823 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5619 12:43:44.549314
5620 12:43:44.552089 CA PerBit enable=1, Macro0, CA PI delay=34
5621 12:43:44.552551
5622 12:43:44.555635 [CBTSetCACLKResult] CA Dly = 34
5623 12:43:44.556154 CS Dly: 6 (0~37)
5624 12:43:44.558864 ==
5625 12:43:44.562039 Dram Type= 6, Freq= 0, CH_1, rank 1
5626 12:43:44.565462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5627 12:43:44.565919 ==
5628 12:43:44.568633 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5629 12:43:44.575323 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5630 12:43:44.578956 [CA 0] Center 37 (7~68) winsize 62
5631 12:43:44.582315 [CA 1] Center 37 (7~68) winsize 62
5632 12:43:44.585840 [CA 2] Center 35 (5~65) winsize 61
5633 12:43:44.589143 [CA 3] Center 34 (4~64) winsize 61
5634 12:43:44.592290 [CA 4] Center 34 (4~65) winsize 62
5635 12:43:44.595846 [CA 5] Center 33 (3~64) winsize 62
5636 12:43:44.596335
5637 12:43:44.598952 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5638 12:43:44.599377
5639 12:43:44.602518 [CATrainingPosCal] consider 2 rank data
5640 12:43:44.605773 u2DelayCellTimex100 = 270/100 ps
5641 12:43:44.609089 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5642 12:43:44.612216 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5643 12:43:44.619034 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5644 12:43:44.622077 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5645 12:43:44.625635 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5646 12:43:44.628971 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5647 12:43:44.629399
5648 12:43:44.632145 CA PerBit enable=1, Macro0, CA PI delay=34
5649 12:43:44.632569
5650 12:43:44.635678 [CBTSetCACLKResult] CA Dly = 34
5651 12:43:44.636103 CS Dly: 6 (0~38)
5652 12:43:44.636439
5653 12:43:44.638764 ----->DramcWriteLeveling(PI) begin...
5654 12:43:44.642201 ==
5655 12:43:44.645616 Dram Type= 6, Freq= 0, CH_1, rank 0
5656 12:43:44.648650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5657 12:43:44.649077 ==
5658 12:43:44.652012 Write leveling (Byte 0): 24 => 24
5659 12:43:44.655563 Write leveling (Byte 1): 27 => 27
5660 12:43:44.658634 DramcWriteLeveling(PI) end<-----
5661 12:43:44.659059
5662 12:43:44.659392 ==
5663 12:43:44.662193 Dram Type= 6, Freq= 0, CH_1, rank 0
5664 12:43:44.665404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5665 12:43:44.665862 ==
5666 12:43:44.668464 [Gating] SW mode calibration
5667 12:43:44.675201 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5668 12:43:44.681725 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5669 12:43:44.685104 0 14 0 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 0)
5670 12:43:44.688366 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5671 12:43:44.694850 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5672 12:43:44.697999 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5673 12:43:44.701233 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5674 12:43:44.708101 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5675 12:43:44.711424 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5676 12:43:44.714827 0 14 28 | B1->B0 | 2f2f 3030 | 0 0 | (0 1) (0 1)
5677 12:43:44.721237 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5678 12:43:44.724609 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5679 12:43:44.728038 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5680 12:43:44.731379 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5681 12:43:44.738015 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5682 12:43:44.741155 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5683 12:43:44.744617 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5684 12:43:44.750996 0 15 28 | B1->B0 | 3232 3131 | 0 0 | (0 0) (0 0)
5685 12:43:44.754485 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5686 12:43:44.757793 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5687 12:43:44.764433 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5688 12:43:44.767911 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5689 12:43:44.771111 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5690 12:43:44.777803 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5691 12:43:44.780985 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5692 12:43:44.784430 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5693 12:43:44.790873 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5694 12:43:44.794285 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5695 12:43:44.797611 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 12:43:44.804347 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5697 12:43:44.807430 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5698 12:43:44.810876 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 12:43:44.817552 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5700 12:43:44.820684 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5701 12:43:44.824100 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5702 12:43:44.830717 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5703 12:43:44.833910 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5704 12:43:44.837716 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5705 12:43:44.844140 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5706 12:43:44.847169 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5707 12:43:44.850665 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5708 12:43:44.857234 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5709 12:43:44.860722 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5710 12:43:44.864485 Total UI for P1: 0, mck2ui 16
5711 12:43:44.867857 best dqsien dly found for B1: ( 1, 2, 28)
5712 12:43:44.871133 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5713 12:43:44.873980 Total UI for P1: 0, mck2ui 16
5714 12:43:44.877696 best dqsien dly found for B0: ( 1, 2, 30)
5715 12:43:44.880975 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5716 12:43:44.884195 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5717 12:43:44.884622
5718 12:43:44.887686 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5719 12:43:44.894237 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5720 12:43:44.894679 [Gating] SW calibration Done
5721 12:43:44.895016 ==
5722 12:43:44.897540 Dram Type= 6, Freq= 0, CH_1, rank 0
5723 12:43:44.903986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5724 12:43:44.904417 ==
5725 12:43:44.904756 RX Vref Scan: 0
5726 12:43:44.905071
5727 12:43:44.907315 RX Vref 0 -> 0, step: 1
5728 12:43:44.907788
5729 12:43:44.910471 RX Delay -80 -> 252, step: 8
5730 12:43:44.913887 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5731 12:43:44.917597 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5732 12:43:44.920677 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5733 12:43:44.927274 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5734 12:43:44.930798 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5735 12:43:44.933852 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5736 12:43:44.937115 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5737 12:43:44.940769 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5738 12:43:44.943890 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5739 12:43:44.950535 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5740 12:43:44.953630 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5741 12:43:44.957231 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5742 12:43:44.960419 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5743 12:43:44.963709 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5744 12:43:44.970257 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5745 12:43:44.973946 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5746 12:43:44.974373 ==
5747 12:43:44.976972 Dram Type= 6, Freq= 0, CH_1, rank 0
5748 12:43:44.980355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 12:43:44.980799 ==
5750 12:43:44.983912 DQS Delay:
5751 12:43:44.984334 DQS0 = 0, DQS1 = 0
5752 12:43:44.984667 DQM Delay:
5753 12:43:44.987143 DQM0 = 95, DQM1 = 86
5754 12:43:44.987568 DQ Delay:
5755 12:43:44.990088 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5756 12:43:44.993466 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5757 12:43:44.996939 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5758 12:43:45.000389 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5759 12:43:45.000815
5760 12:43:45.001150
5761 12:43:45.001464 ==
5762 12:43:45.003498 Dram Type= 6, Freq= 0, CH_1, rank 0
5763 12:43:45.009934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5764 12:43:45.010361 ==
5765 12:43:45.010696
5766 12:43:45.011004
5767 12:43:45.011302 TX Vref Scan disable
5768 12:43:45.013772 == TX Byte 0 ==
5769 12:43:45.017094 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5770 12:43:45.023668 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5771 12:43:45.024095 == TX Byte 1 ==
5772 12:43:45.026855 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5773 12:43:45.033455 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5774 12:43:45.033915 ==
5775 12:43:45.036890 Dram Type= 6, Freq= 0, CH_1, rank 0
5776 12:43:45.040016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5777 12:43:45.040444 ==
5778 12:43:45.040785
5779 12:43:45.041093
5780 12:43:45.043405 TX Vref Scan disable
5781 12:43:45.043831 == TX Byte 0 ==
5782 12:43:45.050110 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5783 12:43:45.053459 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5784 12:43:45.053930 == TX Byte 1 ==
5785 12:43:45.060106 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5786 12:43:45.063205 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5787 12:43:45.063632
5788 12:43:45.063970 [DATLAT]
5789 12:43:45.066550 Freq=933, CH1 RK0
5790 12:43:45.066978
5791 12:43:45.067312 DATLAT Default: 0xd
5792 12:43:45.069786 0, 0xFFFF, sum = 0
5793 12:43:45.070218 1, 0xFFFF, sum = 0
5794 12:43:45.073190 2, 0xFFFF, sum = 0
5795 12:43:45.073663 3, 0xFFFF, sum = 0
5796 12:43:45.076621 4, 0xFFFF, sum = 0
5797 12:43:45.080011 5, 0xFFFF, sum = 0
5798 12:43:45.080444 6, 0xFFFF, sum = 0
5799 12:43:45.083211 7, 0xFFFF, sum = 0
5800 12:43:45.083642 8, 0xFFFF, sum = 0
5801 12:43:45.086515 9, 0xFFFF, sum = 0
5802 12:43:45.086946 10, 0x0, sum = 1
5803 12:43:45.089816 11, 0x0, sum = 2
5804 12:43:45.090246 12, 0x0, sum = 3
5805 12:43:45.090586 13, 0x0, sum = 4
5806 12:43:45.093250 best_step = 11
5807 12:43:45.093698
5808 12:43:45.094037 ==
5809 12:43:45.096598 Dram Type= 6, Freq= 0, CH_1, rank 0
5810 12:43:45.100229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5811 12:43:45.100657 ==
5812 12:43:45.103011 RX Vref Scan: 1
5813 12:43:45.103434
5814 12:43:45.106358 RX Vref 0 -> 0, step: 1
5815 12:43:45.106783
5816 12:43:45.107118 RX Delay -61 -> 252, step: 4
5817 12:43:45.107432
5818 12:43:45.109915 Set Vref, RX VrefLevel [Byte0]: 54
5819 12:43:45.113089 [Byte1]: 48
5820 12:43:45.117826
5821 12:43:45.118267 Final RX Vref Byte 0 = 54 to rank0
5822 12:43:45.120674 Final RX Vref Byte 1 = 48 to rank0
5823 12:43:45.124414 Final RX Vref Byte 0 = 54 to rank1
5824 12:43:45.127274 Final RX Vref Byte 1 = 48 to rank1==
5825 12:43:45.130806 Dram Type= 6, Freq= 0, CH_1, rank 0
5826 12:43:45.137509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5827 12:43:45.137935 ==
5828 12:43:45.138285 DQS Delay:
5829 12:43:45.138606 DQS0 = 0, DQS1 = 0
5830 12:43:45.140953 DQM Delay:
5831 12:43:45.141367 DQM0 = 95, DQM1 = 87
5832 12:43:45.143967 DQ Delay:
5833 12:43:45.147485 DQ0 =100, DQ1 =90, DQ2 =84, DQ3 =92
5834 12:43:45.150560 DQ4 =92, DQ5 =106, DQ6 =106, DQ7 =92
5835 12:43:45.153950 DQ8 =74, DQ9 =82, DQ10 =86, DQ11 =82
5836 12:43:45.157406 DQ12 =94, DQ13 =94, DQ14 =92, DQ15 =94
5837 12:43:45.157833
5838 12:43:45.158177
5839 12:43:45.163999 [DQSOSCAuto] RK0, (LSB)MR18= 0x8, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5840 12:43:45.167232 CH1 RK0: MR19=505, MR18=8
5841 12:43:45.174044 CH1_RK0: MR19=0x505, MR18=0x8, DQSOSC=419, MR23=63, INC=61, DEC=41
5842 12:43:45.174447
5843 12:43:45.177116 ----->DramcWriteLeveling(PI) begin...
5844 12:43:45.177642 ==
5845 12:43:45.180545 Dram Type= 6, Freq= 0, CH_1, rank 1
5846 12:43:45.184015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5847 12:43:45.184503 ==
5848 12:43:45.187276 Write leveling (Byte 0): 22 => 22
5849 12:43:45.190352 Write leveling (Byte 1): 27 => 27
5850 12:43:45.193953 DramcWriteLeveling(PI) end<-----
5851 12:43:45.194379
5852 12:43:45.194735 ==
5853 12:43:45.196840 Dram Type= 6, Freq= 0, CH_1, rank 1
5854 12:43:45.200255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5855 12:43:45.200687 ==
5856 12:43:45.203618 [Gating] SW mode calibration
5857 12:43:45.209981 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5858 12:43:45.216880 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5859 12:43:45.220106 0 14 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5860 12:43:45.223557 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5861 12:43:45.229948 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5862 12:43:45.233381 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5863 12:43:45.236625 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5864 12:43:45.243136 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5865 12:43:45.246709 0 14 24 | B1->B0 | 3434 3030 | 0 1 | (0 0) (1 1)
5866 12:43:45.249809 0 14 28 | B1->B0 | 2b2b 2525 | 1 0 | (1 0) (1 0)
5867 12:43:45.256359 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5868 12:43:45.259693 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5869 12:43:45.263208 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5870 12:43:45.269504 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5871 12:43:45.272900 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5872 12:43:45.276180 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5873 12:43:45.283127 0 15 24 | B1->B0 | 2929 3232 | 0 0 | (0 0) (0 0)
5874 12:43:45.286183 0 15 28 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5875 12:43:45.289643 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5876 12:43:45.296226 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5877 12:43:45.299584 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5878 12:43:45.302752 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5879 12:43:45.309391 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5880 12:43:45.312784 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5881 12:43:45.316236 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5882 12:43:45.322816 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5883 12:43:45.326111 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5884 12:43:45.329549 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5885 12:43:45.335967 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5886 12:43:45.339432 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5887 12:43:45.342707 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5888 12:43:45.349284 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5889 12:43:45.352677 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5890 12:43:45.355760 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5891 12:43:45.362635 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5892 12:43:45.365895 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5893 12:43:45.369416 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5894 12:43:45.372794 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5895 12:43:45.379395 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5896 12:43:45.382780 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5897 12:43:45.385911 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5898 12:43:45.392373 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5899 12:43:45.395776 Total UI for P1: 0, mck2ui 16
5900 12:43:45.399327 best dqsien dly found for B0: ( 1, 2, 22)
5901 12:43:45.402421 Total UI for P1: 0, mck2ui 16
5902 12:43:45.406007 best dqsien dly found for B1: ( 1, 2, 26)
5903 12:43:45.409054 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5904 12:43:45.412291 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5905 12:43:45.412717
5906 12:43:45.415582 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5907 12:43:45.418899 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5908 12:43:45.422514 [Gating] SW calibration Done
5909 12:43:45.422938 ==
5910 12:43:45.425753 Dram Type= 6, Freq= 0, CH_1, rank 1
5911 12:43:45.429116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5912 12:43:45.429637 ==
5913 12:43:45.432299 RX Vref Scan: 0
5914 12:43:45.432720
5915 12:43:45.435445 RX Vref 0 -> 0, step: 1
5916 12:43:45.435870
5917 12:43:45.436206 RX Delay -80 -> 252, step: 8
5918 12:43:45.442396 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5919 12:43:45.445414 iDelay=208, Bit 1, Center 87 (-16 ~ 191) 208
5920 12:43:45.448744 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5921 12:43:45.452186 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5922 12:43:45.455331 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5923 12:43:45.458976 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5924 12:43:45.465469 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5925 12:43:45.468846 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5926 12:43:45.471897 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5927 12:43:45.475341 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5928 12:43:45.478528 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5929 12:43:45.485547 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5930 12:43:45.488512 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5931 12:43:45.491874 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5932 12:43:45.495492 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5933 12:43:45.498723 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5934 12:43:45.499105 ==
5935 12:43:45.502056 Dram Type= 6, Freq= 0, CH_1, rank 1
5936 12:43:45.508477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5937 12:43:45.508946 ==
5938 12:43:45.509282 DQS Delay:
5939 12:43:45.511866 DQS0 = 0, DQS1 = 0
5940 12:43:45.512405 DQM Delay:
5941 12:43:45.512762 DQM0 = 93, DQM1 = 88
5942 12:43:45.515231 DQ Delay:
5943 12:43:45.518767 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =91
5944 12:43:45.521833 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5945 12:43:45.525323 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =87
5946 12:43:45.528701 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5947 12:43:45.529139
5948 12:43:45.529613
5949 12:43:45.529964 ==
5950 12:43:45.531849 Dram Type= 6, Freq= 0, CH_1, rank 1
5951 12:43:45.535037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5952 12:43:45.535531 ==
5953 12:43:45.536028
5954 12:43:45.536490
5955 12:43:45.538504 TX Vref Scan disable
5956 12:43:45.538945 == TX Byte 0 ==
5957 12:43:45.545273 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5958 12:43:45.548489 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5959 12:43:45.551515 == TX Byte 1 ==
5960 12:43:45.555115 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5961 12:43:45.558349 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5962 12:43:45.558879 ==
5963 12:43:45.561581 Dram Type= 6, Freq= 0, CH_1, rank 1
5964 12:43:45.564848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5965 12:43:45.568241 ==
5966 12:43:45.568804
5967 12:43:45.569284
5968 12:43:45.569735 TX Vref Scan disable
5969 12:43:45.571875 == TX Byte 0 ==
5970 12:43:45.574883 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5971 12:43:45.581647 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5972 12:43:45.582096 == TX Byte 1 ==
5973 12:43:45.585110 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5974 12:43:45.591506 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5975 12:43:45.591935
5976 12:43:45.592274 [DATLAT]
5977 12:43:45.592588 Freq=933, CH1 RK1
5978 12:43:45.592891
5979 12:43:45.594852 DATLAT Default: 0xb
5980 12:43:45.595278 0, 0xFFFF, sum = 0
5981 12:43:45.598369 1, 0xFFFF, sum = 0
5982 12:43:45.598805 2, 0xFFFF, sum = 0
5983 12:43:45.601456 3, 0xFFFF, sum = 0
5984 12:43:45.604838 4, 0xFFFF, sum = 0
5985 12:43:45.605270 5, 0xFFFF, sum = 0
5986 12:43:45.608251 6, 0xFFFF, sum = 0
5987 12:43:45.608681 7, 0xFFFF, sum = 0
5988 12:43:45.611629 8, 0xFFFF, sum = 0
5989 12:43:45.612064 9, 0xFFFF, sum = 0
5990 12:43:45.614718 10, 0x0, sum = 1
5991 12:43:45.615164 11, 0x0, sum = 2
5992 12:43:45.618008 12, 0x0, sum = 3
5993 12:43:45.618440 13, 0x0, sum = 4
5994 12:43:45.618783 best_step = 11
5995 12:43:45.619095
5996 12:43:45.621340 ==
5997 12:43:45.624614 Dram Type= 6, Freq= 0, CH_1, rank 1
5998 12:43:45.627975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5999 12:43:45.628403 ==
6000 12:43:45.628739 RX Vref Scan: 0
6001 12:43:45.629049
6002 12:43:45.631348 RX Vref 0 -> 0, step: 1
6003 12:43:45.631773
6004 12:43:45.634505 RX Delay -69 -> 252, step: 4
6005 12:43:45.638055 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
6006 12:43:45.644717 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
6007 12:43:45.647855 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
6008 12:43:45.651226 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
6009 12:43:45.654512 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
6010 12:43:45.657968 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
6011 12:43:45.661355 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
6012 12:43:45.668115 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
6013 12:43:45.671450 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
6014 12:43:45.674599 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
6015 12:43:45.677942 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
6016 12:43:45.681551 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
6017 12:43:45.688004 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
6018 12:43:45.691463 iDelay=203, Bit 13, Center 96 (3 ~ 190) 188
6019 12:43:45.694572 iDelay=203, Bit 14, Center 100 (11 ~ 190) 180
6020 12:43:45.697722 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
6021 12:43:45.698149 ==
6022 12:43:45.701068 Dram Type= 6, Freq= 0, CH_1, rank 1
6023 12:43:45.704377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6024 12:43:45.707815 ==
6025 12:43:45.708213 DQS Delay:
6026 12:43:45.708553 DQS0 = 0, DQS1 = 0
6027 12:43:45.711105 DQM Delay:
6028 12:43:45.711560 DQM0 = 91, DQM1 = 90
6029 12:43:45.714410 DQ Delay:
6030 12:43:45.717751 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
6031 12:43:45.721148 DQ4 =90, DQ5 =102, DQ6 =102, DQ7 =88
6032 12:43:45.724372 DQ8 =78, DQ9 =82, DQ10 =90, DQ11 =84
6033 12:43:45.727664 DQ12 =96, DQ13 =96, DQ14 =100, DQ15 =96
6034 12:43:45.728090
6035 12:43:45.728427
6036 12:43:45.734130 [DQSOSCAuto] RK1, (LSB)MR18= 0x1125, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
6037 12:43:45.737747 CH1 RK1: MR19=505, MR18=1125
6038 12:43:45.744140 CH1_RK1: MR19=0x505, MR18=0x1125, DQSOSC=410, MR23=63, INC=64, DEC=42
6039 12:43:45.747398 [RxdqsGatingPostProcess] freq 933
6040 12:43:45.750506 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6041 12:43:45.753734 best DQS0 dly(2T, 0.5T) = (0, 10)
6042 12:43:45.757324 best DQS1 dly(2T, 0.5T) = (0, 10)
6043 12:43:45.760409 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6044 12:43:45.763674 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6045 12:43:45.767014 best DQS0 dly(2T, 0.5T) = (0, 10)
6046 12:43:45.770334 best DQS1 dly(2T, 0.5T) = (0, 10)
6047 12:43:45.773748 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6048 12:43:45.776967 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6049 12:43:45.780290 Pre-setting of DQS Precalculation
6050 12:43:45.783651 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6051 12:43:45.793681 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6052 12:43:45.800315 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6053 12:43:45.800742
6054 12:43:45.801075
6055 12:43:45.803529 [Calibration Summary] 1866 Mbps
6056 12:43:45.803951 CH 0, Rank 0
6057 12:43:45.806938 SW Impedance : PASS
6058 12:43:45.807408 DUTY Scan : NO K
6059 12:43:45.810023 ZQ Calibration : PASS
6060 12:43:45.813422 Jitter Meter : NO K
6061 12:43:45.813889 CBT Training : PASS
6062 12:43:45.816817 Write leveling : PASS
6063 12:43:45.820006 RX DQS gating : PASS
6064 12:43:45.820433 RX DQ/DQS(RDDQC) : PASS
6065 12:43:45.823460 TX DQ/DQS : PASS
6066 12:43:45.826738 RX DATLAT : PASS
6067 12:43:45.827166 RX DQ/DQS(Engine): PASS
6068 12:43:45.829861 TX OE : NO K
6069 12:43:45.830301 All Pass.
6070 12:43:45.830633
6071 12:43:45.833391 CH 0, Rank 1
6072 12:43:45.833857 SW Impedance : PASS
6073 12:43:45.836586 DUTY Scan : NO K
6074 12:43:45.839809 ZQ Calibration : PASS
6075 12:43:45.840231 Jitter Meter : NO K
6076 12:43:45.843227 CBT Training : PASS
6077 12:43:45.846645 Write leveling : PASS
6078 12:43:45.847069 RX DQS gating : PASS
6079 12:43:45.849581 RX DQ/DQS(RDDQC) : PASS
6080 12:43:45.853081 TX DQ/DQS : PASS
6081 12:43:45.853539 RX DATLAT : PASS
6082 12:43:45.856437 RX DQ/DQS(Engine): PASS
6083 12:43:45.856859 TX OE : NO K
6084 12:43:45.859750 All Pass.
6085 12:43:45.860172
6086 12:43:45.860507 CH 1, Rank 0
6087 12:43:45.862834 SW Impedance : PASS
6088 12:43:45.863257 DUTY Scan : NO K
6089 12:43:45.866243 ZQ Calibration : PASS
6090 12:43:45.869584 Jitter Meter : NO K
6091 12:43:45.870010 CBT Training : PASS
6092 12:43:45.872840 Write leveling : PASS
6093 12:43:45.876370 RX DQS gating : PASS
6094 12:43:45.876792 RX DQ/DQS(RDDQC) : PASS
6095 12:43:45.879719 TX DQ/DQS : PASS
6096 12:43:45.882832 RX DATLAT : PASS
6097 12:43:45.883259 RX DQ/DQS(Engine): PASS
6098 12:43:45.886224 TX OE : NO K
6099 12:43:45.886651 All Pass.
6100 12:43:45.886988
6101 12:43:45.889329 CH 1, Rank 1
6102 12:43:45.889795 SW Impedance : PASS
6103 12:43:45.892798 DUTY Scan : NO K
6104 12:43:45.895829 ZQ Calibration : PASS
6105 12:43:45.896292 Jitter Meter : NO K
6106 12:43:45.899322 CBT Training : PASS
6107 12:43:45.902842 Write leveling : PASS
6108 12:43:45.903266 RX DQS gating : PASS
6109 12:43:45.905781 RX DQ/DQS(RDDQC) : PASS
6110 12:43:45.909239 TX DQ/DQS : PASS
6111 12:43:45.909735 RX DATLAT : PASS
6112 12:43:45.912327 RX DQ/DQS(Engine): PASS
6113 12:43:45.915835 TX OE : NO K
6114 12:43:45.916262 All Pass.
6115 12:43:45.916598
6116 12:43:45.916908 DramC Write-DBI off
6117 12:43:45.918885 PER_BANK_REFRESH: Hybrid Mode
6118 12:43:45.922398 TX_TRACKING: ON
6119 12:43:45.928855 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6120 12:43:45.931979 [FAST_K] Save calibration result to emmc
6121 12:43:45.938692 dramc_set_vcore_voltage set vcore to 650000
6122 12:43:45.939214 Read voltage for 400, 6
6123 12:43:45.941953 Vio18 = 0
6124 12:43:45.942377 Vcore = 650000
6125 12:43:45.942710 Vdram = 0
6126 12:43:45.945343 Vddq = 0
6127 12:43:45.945815 Vmddr = 0
6128 12:43:45.948951 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6129 12:43:45.955706 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6130 12:43:45.958585 MEM_TYPE=3, freq_sel=20
6131 12:43:45.961984 sv_algorithm_assistance_LP4_800
6132 12:43:45.965085 ============ PULL DRAM RESETB DOWN ============
6133 12:43:45.968292 ========== PULL DRAM RESETB DOWN end =========
6134 12:43:45.975271 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6135 12:43:45.978318 ===================================
6136 12:43:45.978894 LPDDR4 DRAM CONFIGURATION
6137 12:43:45.981768 ===================================
6138 12:43:45.985359 EX_ROW_EN[0] = 0x0
6139 12:43:45.985832 EX_ROW_EN[1] = 0x0
6140 12:43:45.988273 LP4Y_EN = 0x0
6141 12:43:45.988697 WORK_FSP = 0x0
6142 12:43:45.991821 WL = 0x2
6143 12:43:45.992521 RL = 0x2
6144 12:43:45.995104 BL = 0x2
6145 12:43:45.995528 RPST = 0x0
6146 12:43:45.998583 RD_PRE = 0x0
6147 12:43:46.001412 WR_PRE = 0x1
6148 12:43:46.001882 WR_PST = 0x0
6149 12:43:46.004944 DBI_WR = 0x0
6150 12:43:46.005367 DBI_RD = 0x0
6151 12:43:46.008157 OTF = 0x1
6152 12:43:46.011520 ===================================
6153 12:43:46.014757 ===================================
6154 12:43:46.015181 ANA top config
6155 12:43:46.018104 ===================================
6156 12:43:46.021602 DLL_ASYNC_EN = 0
6157 12:43:46.024617 ALL_SLAVE_EN = 1
6158 12:43:46.025043 NEW_RANK_MODE = 1
6159 12:43:46.028001 DLL_IDLE_MODE = 1
6160 12:43:46.031329 LP45_APHY_COMB_EN = 1
6161 12:43:46.034634 TX_ODT_DIS = 1
6162 12:43:46.037919 NEW_8X_MODE = 1
6163 12:43:46.038353 ===================================
6164 12:43:46.041241 ===================================
6165 12:43:46.044451 data_rate = 800
6166 12:43:46.047806 CKR = 1
6167 12:43:46.051135 DQ_P2S_RATIO = 4
6168 12:43:46.054597 ===================================
6169 12:43:46.057949 CA_P2S_RATIO = 4
6170 12:43:46.060942 DQ_CA_OPEN = 0
6171 12:43:46.064432 DQ_SEMI_OPEN = 1
6172 12:43:46.065129 CA_SEMI_OPEN = 1
6173 12:43:46.067889 CA_FULL_RATE = 0
6174 12:43:46.071314 DQ_CKDIV4_EN = 0
6175 12:43:46.074544 CA_CKDIV4_EN = 1
6176 12:43:46.077790 CA_PREDIV_EN = 0
6177 12:43:46.081172 PH8_DLY = 0
6178 12:43:46.081831 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6179 12:43:46.084177 DQ_AAMCK_DIV = 0
6180 12:43:46.087324 CA_AAMCK_DIV = 0
6181 12:43:46.090834 CA_ADMCK_DIV = 4
6182 12:43:46.094387 DQ_TRACK_CA_EN = 0
6183 12:43:46.097384 CA_PICK = 800
6184 12:43:46.100786 CA_MCKIO = 400
6185 12:43:46.101237 MCKIO_SEMI = 400
6186 12:43:46.104028 PLL_FREQ = 3016
6187 12:43:46.107417 DQ_UI_PI_RATIO = 32
6188 12:43:46.110745 CA_UI_PI_RATIO = 32
6189 12:43:46.113977 ===================================
6190 12:43:46.117453 ===================================
6191 12:43:46.120768 memory_type:LPDDR4
6192 12:43:46.121208 GP_NUM : 10
6193 12:43:46.123861 SRAM_EN : 1
6194 12:43:46.127459 MD32_EN : 0
6195 12:43:46.130808 ===================================
6196 12:43:46.131215 [ANA_INIT] >>>>>>>>>>>>>>
6197 12:43:46.133841 <<<<<< [CONFIGURE PHASE]: ANA_TX
6198 12:43:46.137280 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6199 12:43:46.140686 ===================================
6200 12:43:46.143817 data_rate = 800,PCW = 0X7400
6201 12:43:46.147202 ===================================
6202 12:43:46.150433 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6203 12:43:46.157330 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6204 12:43:46.167000 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6205 12:43:46.173683 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6206 12:43:46.176962 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6207 12:43:46.180351 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6208 12:43:46.180797 [ANA_INIT] flow start
6209 12:43:46.183587 [ANA_INIT] PLL >>>>>>>>
6210 12:43:46.186994 [ANA_INIT] PLL <<<<<<<<
6211 12:43:46.187418 [ANA_INIT] MIDPI >>>>>>>>
6212 12:43:46.190085 [ANA_INIT] MIDPI <<<<<<<<
6213 12:43:46.193393 [ANA_INIT] DLL >>>>>>>>
6214 12:43:46.193886 [ANA_INIT] flow end
6215 12:43:46.199932 ============ LP4 DIFF to SE enter ============
6216 12:43:46.203426 ============ LP4 DIFF to SE exit ============
6217 12:43:46.203856 [ANA_INIT] <<<<<<<<<<<<<
6218 12:43:46.206554 [Flow] Enable top DCM control >>>>>
6219 12:43:46.210086 [Flow] Enable top DCM control <<<<<
6220 12:43:46.213218 Enable DLL master slave shuffle
6221 12:43:46.219988 ==============================================================
6222 12:43:46.223017 Gating Mode config
6223 12:43:46.226429 ==============================================================
6224 12:43:46.229815 Config description:
6225 12:43:46.239633 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6226 12:43:46.246131 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6227 12:43:46.249614 SELPH_MODE 0: By rank 1: By Phase
6228 12:43:46.256446 ==============================================================
6229 12:43:46.259495 GAT_TRACK_EN = 0
6230 12:43:46.262917 RX_GATING_MODE = 2
6231 12:43:46.265872 RX_GATING_TRACK_MODE = 2
6232 12:43:46.269241 SELPH_MODE = 1
6233 12:43:46.269739 PICG_EARLY_EN = 1
6234 12:43:46.272389 VALID_LAT_VALUE = 1
6235 12:43:46.279293 ==============================================================
6236 12:43:46.282882 Enter into Gating configuration >>>>
6237 12:43:46.285719 Exit from Gating configuration <<<<
6238 12:43:46.289414 Enter into DVFS_PRE_config >>>>>
6239 12:43:46.299434 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6240 12:43:46.302354 Exit from DVFS_PRE_config <<<<<
6241 12:43:46.305909 Enter into PICG configuration >>>>
6242 12:43:46.309450 Exit from PICG configuration <<<<
6243 12:43:46.312220 [RX_INPUT] configuration >>>>>
6244 12:43:46.315692 [RX_INPUT] configuration <<<<<
6245 12:43:46.318951 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6246 12:43:46.325630 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6247 12:43:46.332162 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6248 12:43:46.338772 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6249 12:43:46.345068 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6250 12:43:46.351766 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6251 12:43:46.355277 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6252 12:43:46.358523 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6253 12:43:46.361657 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6254 12:43:46.368239 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6255 12:43:46.371829 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6256 12:43:46.375020 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6257 12:43:46.378465 ===================================
6258 12:43:46.381865 LPDDR4 DRAM CONFIGURATION
6259 12:43:46.385001 ===================================
6260 12:43:46.385461 EX_ROW_EN[0] = 0x0
6261 12:43:46.388395 EX_ROW_EN[1] = 0x0
6262 12:43:46.391439 LP4Y_EN = 0x0
6263 12:43:46.391861 WORK_FSP = 0x0
6264 12:43:46.394925 WL = 0x2
6265 12:43:46.395345 RL = 0x2
6266 12:43:46.398070 BL = 0x2
6267 12:43:46.398512 RPST = 0x0
6268 12:43:46.401604 RD_PRE = 0x0
6269 12:43:46.402041 WR_PRE = 0x1
6270 12:43:46.404629 WR_PST = 0x0
6271 12:43:46.405096 DBI_WR = 0x0
6272 12:43:46.408156 DBI_RD = 0x0
6273 12:43:46.408601 OTF = 0x1
6274 12:43:46.411616 ===================================
6275 12:43:46.414737 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6276 12:43:46.421698 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6277 12:43:46.424580 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6278 12:43:46.427795 ===================================
6279 12:43:46.431297 LPDDR4 DRAM CONFIGURATION
6280 12:43:46.434666 ===================================
6281 12:43:46.435120 EX_ROW_EN[0] = 0x10
6282 12:43:46.437760 EX_ROW_EN[1] = 0x0
6283 12:43:46.441089 LP4Y_EN = 0x0
6284 12:43:46.441604 WORK_FSP = 0x0
6285 12:43:46.444400 WL = 0x2
6286 12:43:46.444828 RL = 0x2
6287 12:43:46.447978 BL = 0x2
6288 12:43:46.448508 RPST = 0x0
6289 12:43:46.451162 RD_PRE = 0x0
6290 12:43:46.451586 WR_PRE = 0x1
6291 12:43:46.454405 WR_PST = 0x0
6292 12:43:46.454826 DBI_WR = 0x0
6293 12:43:46.457605 DBI_RD = 0x0
6294 12:43:46.458029 OTF = 0x1
6295 12:43:46.461081 ===================================
6296 12:43:46.467469 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6297 12:43:46.471825 nWR fixed to 30
6298 12:43:46.475389 [ModeRegInit_LP4] CH0 RK0
6299 12:43:46.475809 [ModeRegInit_LP4] CH0 RK1
6300 12:43:46.478507 [ModeRegInit_LP4] CH1 RK0
6301 12:43:46.481965 [ModeRegInit_LP4] CH1 RK1
6302 12:43:46.482388 match AC timing 19
6303 12:43:46.488053 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6304 12:43:46.491294 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6305 12:43:46.494619 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6306 12:43:46.501144 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6307 12:43:46.504485 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6308 12:43:46.504567 ==
6309 12:43:46.507983 Dram Type= 6, Freq= 0, CH_0, rank 0
6310 12:43:46.511383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6311 12:43:46.511465 ==
6312 12:43:46.517758 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6313 12:43:46.524505 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6314 12:43:46.527751 [CA 0] Center 36 (8~64) winsize 57
6315 12:43:46.531129 [CA 1] Center 36 (8~64) winsize 57
6316 12:43:46.534503 [CA 2] Center 36 (8~64) winsize 57
6317 12:43:46.537593 [CA 3] Center 36 (8~64) winsize 57
6318 12:43:46.537675 [CA 4] Center 36 (8~64) winsize 57
6319 12:43:46.541270 [CA 5] Center 36 (8~64) winsize 57
6320 12:43:46.541353
6321 12:43:46.547847 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6322 12:43:46.547929
6323 12:43:46.551091 [CATrainingPosCal] consider 1 rank data
6324 12:43:46.554388 u2DelayCellTimex100 = 270/100 ps
6325 12:43:46.557700 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 12:43:46.561070 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 12:43:46.564249 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 12:43:46.567501 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 12:43:46.570874 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 12:43:46.574119 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 12:43:46.574223
6332 12:43:46.577456 CA PerBit enable=1, Macro0, CA PI delay=36
6333 12:43:46.577549
6334 12:43:46.581035 [CBTSetCACLKResult] CA Dly = 36
6335 12:43:46.584190 CS Dly: 1 (0~32)
6336 12:43:46.584302 ==
6337 12:43:46.587530 Dram Type= 6, Freq= 0, CH_0, rank 1
6338 12:43:46.590783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 12:43:46.590866 ==
6340 12:43:46.597615 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6341 12:43:46.603822 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6342 12:43:46.603928 [CA 0] Center 36 (8~64) winsize 57
6343 12:43:46.607167 [CA 1] Center 36 (8~64) winsize 57
6344 12:43:46.610632 [CA 2] Center 36 (8~64) winsize 57
6345 12:43:46.614077 [CA 3] Center 36 (8~64) winsize 57
6346 12:43:46.617210 [CA 4] Center 36 (8~64) winsize 57
6347 12:43:46.620633 [CA 5] Center 36 (8~64) winsize 57
6348 12:43:46.620715
6349 12:43:46.623765 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6350 12:43:46.623847
6351 12:43:46.627290 [CATrainingPosCal] consider 2 rank data
6352 12:43:46.630505 u2DelayCellTimex100 = 270/100 ps
6353 12:43:46.633792 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6354 12:43:46.640432 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6355 12:43:46.643629 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6356 12:43:46.647012 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6357 12:43:46.650413 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6358 12:43:46.653820 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6359 12:43:46.653902
6360 12:43:46.656930 CA PerBit enable=1, Macro0, CA PI delay=36
6361 12:43:46.657012
6362 12:43:46.660416 [CBTSetCACLKResult] CA Dly = 36
6363 12:43:46.660503 CS Dly: 1 (0~32)
6364 12:43:46.663912
6365 12:43:46.667028 ----->DramcWriteLeveling(PI) begin...
6366 12:43:46.667123 ==
6367 12:43:46.670392 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 12:43:46.673719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 12:43:46.673841 ==
6370 12:43:46.676774 Write leveling (Byte 0): 40 => 8
6371 12:43:46.680144 Write leveling (Byte 1): 40 => 8
6372 12:43:46.683597 DramcWriteLeveling(PI) end<-----
6373 12:43:46.683718
6374 12:43:46.683834 ==
6375 12:43:46.687236 Dram Type= 6, Freq= 0, CH_0, rank 0
6376 12:43:46.690138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6377 12:43:46.690326 ==
6378 12:43:46.693455 [Gating] SW mode calibration
6379 12:43:46.700193 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6380 12:43:46.706428 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6381 12:43:46.709883 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6382 12:43:46.713116 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6383 12:43:46.720142 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6384 12:43:46.723197 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6385 12:43:46.726365 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6386 12:43:46.732994 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6387 12:43:46.736525 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6388 12:43:46.739871 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6389 12:43:46.746724 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6390 12:43:46.746811 Total UI for P1: 0, mck2ui 16
6391 12:43:46.749741 best dqsien dly found for B0: ( 0, 14, 24)
6392 12:43:46.753109 Total UI for P1: 0, mck2ui 16
6393 12:43:46.756501 best dqsien dly found for B1: ( 0, 14, 24)
6394 12:43:46.763100 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6395 12:43:46.766104 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6396 12:43:46.766190
6397 12:43:46.769485 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6398 12:43:46.773201 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6399 12:43:46.776364 [Gating] SW calibration Done
6400 12:43:46.776464 ==
6401 12:43:46.779577 Dram Type= 6, Freq= 0, CH_0, rank 0
6402 12:43:46.782856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6403 12:43:46.782945 ==
6404 12:43:46.786342 RX Vref Scan: 0
6405 12:43:46.786415
6406 12:43:46.786475 RX Vref 0 -> 0, step: 1
6407 12:43:46.786532
6408 12:43:46.789404 RX Delay -410 -> 252, step: 16
6409 12:43:46.796183 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6410 12:43:46.799405 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6411 12:43:46.802622 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6412 12:43:46.806134 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6413 12:43:46.812538 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6414 12:43:46.815856 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6415 12:43:46.819203 iDelay=230, Bit 6, Center -35 (-282 ~ 213) 496
6416 12:43:46.822629 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6417 12:43:46.829094 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6418 12:43:46.832594 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6419 12:43:46.835837 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6420 12:43:46.839037 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6421 12:43:46.845623 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6422 12:43:46.849062 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6423 12:43:46.852229 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6424 12:43:46.855603 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6425 12:43:46.858951 ==
6426 12:43:46.859028 Dram Type= 6, Freq= 0, CH_0, rank 0
6427 12:43:46.865728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6428 12:43:46.865815 ==
6429 12:43:46.865880 DQS Delay:
6430 12:43:46.869038 DQS0 = 59, DQS1 = 59
6431 12:43:46.869134 DQM Delay:
6432 12:43:46.872549 DQM0 = 17, DQM1 = 10
6433 12:43:46.872645 DQ Delay:
6434 12:43:46.875429 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6435 12:43:46.879104 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6436 12:43:46.882390 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6437 12:43:46.885785 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6438 12:43:46.885859
6439 12:43:46.885919
6440 12:43:46.885976 ==
6441 12:43:46.889043 Dram Type= 6, Freq= 0, CH_0, rank 0
6442 12:43:46.892379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6443 12:43:46.892452 ==
6444 12:43:46.892513
6445 12:43:46.892575
6446 12:43:46.895796 TX Vref Scan disable
6447 12:43:46.895865 == TX Byte 0 ==
6448 12:43:46.902408 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6449 12:43:46.905712 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6450 12:43:46.905783 == TX Byte 1 ==
6451 12:43:46.912170 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6452 12:43:46.915592 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6453 12:43:46.915668 ==
6454 12:43:46.918629 Dram Type= 6, Freq= 0, CH_0, rank 0
6455 12:43:46.922178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6456 12:43:46.922250 ==
6457 12:43:46.922317
6458 12:43:46.922376
6459 12:43:46.925221 TX Vref Scan disable
6460 12:43:46.925295 == TX Byte 0 ==
6461 12:43:46.932027 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6462 12:43:46.935187 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6463 12:43:46.935259 == TX Byte 1 ==
6464 12:43:46.941810 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6465 12:43:46.945098 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6466 12:43:46.945175
6467 12:43:46.945237 [DATLAT]
6468 12:43:46.948760 Freq=400, CH0 RK0
6469 12:43:46.948832
6470 12:43:46.948892 DATLAT Default: 0xf
6471 12:43:46.951725 0, 0xFFFF, sum = 0
6472 12:43:46.951796 1, 0xFFFF, sum = 0
6473 12:43:46.955127 2, 0xFFFF, sum = 0
6474 12:43:46.955204 3, 0xFFFF, sum = 0
6475 12:43:46.958553 4, 0xFFFF, sum = 0
6476 12:43:46.958626 5, 0xFFFF, sum = 0
6477 12:43:46.961912 6, 0xFFFF, sum = 0
6478 12:43:46.961987 7, 0xFFFF, sum = 0
6479 12:43:46.965387 8, 0xFFFF, sum = 0
6480 12:43:46.965491 9, 0xFFFF, sum = 0
6481 12:43:46.968418 10, 0xFFFF, sum = 0
6482 12:43:46.971785 11, 0xFFFF, sum = 0
6483 12:43:46.971857 12, 0xFFFF, sum = 0
6484 12:43:46.975263 13, 0x0, sum = 1
6485 12:43:46.975334 14, 0x0, sum = 2
6486 12:43:46.978421 15, 0x0, sum = 3
6487 12:43:46.978492 16, 0x0, sum = 4
6488 12:43:46.978553 best_step = 14
6489 12:43:46.978610
6490 12:43:46.981503 ==
6491 12:43:46.984813 Dram Type= 6, Freq= 0, CH_0, rank 0
6492 12:43:46.987995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 12:43:46.988071 ==
6494 12:43:46.988135 RX Vref Scan: 1
6495 12:43:46.988194
6496 12:43:46.991381 RX Vref 0 -> 0, step: 1
6497 12:43:46.991454
6498 12:43:46.994772 RX Delay -359 -> 252, step: 8
6499 12:43:46.994844
6500 12:43:46.998185 Set Vref, RX VrefLevel [Byte0]: 60
6501 12:43:47.001218 [Byte1]: 52
6502 12:43:47.005351
6503 12:43:47.005448 Final RX Vref Byte 0 = 60 to rank0
6504 12:43:47.008637 Final RX Vref Byte 1 = 52 to rank0
6505 12:43:47.011864 Final RX Vref Byte 0 = 60 to rank1
6506 12:43:47.015050 Final RX Vref Byte 1 = 52 to rank1==
6507 12:43:47.018449 Dram Type= 6, Freq= 0, CH_0, rank 0
6508 12:43:47.025024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6509 12:43:47.025125 ==
6510 12:43:47.025214 DQS Delay:
6511 12:43:47.028557 DQS0 = 60, DQS1 = 68
6512 12:43:47.028628 DQM Delay:
6513 12:43:47.028687 DQM0 = 15, DQM1 = 14
6514 12:43:47.031752 DQ Delay:
6515 12:43:47.035180 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =16
6516 12:43:47.038285 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6517 12:43:47.038356 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6518 12:43:47.044877 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6519 12:43:47.044951
6520 12:43:47.045013
6521 12:43:47.051389 [DQSOSCAuto] RK0, (LSB)MR18= 0x8887, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
6522 12:43:47.054846 CH0 RK0: MR19=C0C, MR18=8887
6523 12:43:47.061415 CH0_RK0: MR19=0xC0C, MR18=0x8887, DQSOSC=392, MR23=63, INC=384, DEC=256
6524 12:43:47.061516 ==
6525 12:43:47.064680 Dram Type= 6, Freq= 0, CH_0, rank 1
6526 12:43:47.067866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6527 12:43:47.067963 ==
6528 12:43:47.071398 [Gating] SW mode calibration
6529 12:43:47.078153 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6530 12:43:47.084697 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6531 12:43:47.088025 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6532 12:43:47.091219 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6533 12:43:47.098239 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6534 12:43:47.101362 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6535 12:43:47.104710 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6536 12:43:47.111346 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6537 12:43:47.114585 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6538 12:43:47.117879 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6539 12:43:47.124515 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6540 12:43:47.124626 Total UI for P1: 0, mck2ui 16
6541 12:43:47.131206 best dqsien dly found for B0: ( 0, 14, 24)
6542 12:43:47.131289 Total UI for P1: 0, mck2ui 16
6543 12:43:47.137791 best dqsien dly found for B1: ( 0, 14, 24)
6544 12:43:47.140979 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6545 12:43:47.144177 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6546 12:43:47.144269
6547 12:43:47.147821 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6548 12:43:47.151015 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6549 12:43:47.154351 [Gating] SW calibration Done
6550 12:43:47.154424 ==
6551 12:43:47.157389 Dram Type= 6, Freq= 0, CH_0, rank 1
6552 12:43:47.161000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6553 12:43:47.161111 ==
6554 12:43:47.164131 RX Vref Scan: 0
6555 12:43:47.164227
6556 12:43:47.164301 RX Vref 0 -> 0, step: 1
6557 12:43:47.164370
6558 12:43:47.167459 RX Delay -410 -> 252, step: 16
6559 12:43:47.174163 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6560 12:43:47.177485 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6561 12:43:47.180523 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6562 12:43:47.184027 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6563 12:43:47.190706 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6564 12:43:47.194053 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6565 12:43:47.197262 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6566 12:43:47.200591 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6567 12:43:47.207376 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6568 12:43:47.210767 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6569 12:43:47.214192 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6570 12:43:47.217392 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6571 12:43:47.224141 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6572 12:43:47.227561 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6573 12:43:47.230661 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6574 12:43:47.234144 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6575 12:43:47.237361 ==
6576 12:43:47.240856 Dram Type= 6, Freq= 0, CH_0, rank 1
6577 12:43:47.244081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6578 12:43:47.244649 ==
6579 12:43:47.245099 DQS Delay:
6580 12:43:47.247672 DQS0 = 59, DQS1 = 59
6581 12:43:47.248125 DQM Delay:
6582 12:43:47.251010 DQM0 = 16, DQM1 = 10
6583 12:43:47.251440 DQ Delay:
6584 12:43:47.254070 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6585 12:43:47.257393 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6586 12:43:47.260621 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6587 12:43:47.264216 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6588 12:43:47.264632
6589 12:43:47.264981
6590 12:43:47.265346 ==
6591 12:43:47.267212 Dram Type= 6, Freq= 0, CH_0, rank 1
6592 12:43:47.270576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6593 12:43:47.271024 ==
6594 12:43:47.271377
6595 12:43:47.271706
6596 12:43:47.273710 TX Vref Scan disable
6597 12:43:47.274157 == TX Byte 0 ==
6598 12:43:47.280375 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6599 12:43:47.283750 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6600 12:43:47.284381 == TX Byte 1 ==
6601 12:43:47.290329 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6602 12:43:47.293843 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6603 12:43:47.294474 ==
6604 12:43:47.296881 Dram Type= 6, Freq= 0, CH_0, rank 1
6605 12:43:47.300400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6606 12:43:47.300917 ==
6607 12:43:47.301368
6608 12:43:47.303652
6609 12:43:47.304173 TX Vref Scan disable
6610 12:43:47.307265 == TX Byte 0 ==
6611 12:43:47.310452 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6612 12:43:47.313578 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6613 12:43:47.317103 == TX Byte 1 ==
6614 12:43:47.320455 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6615 12:43:47.323704 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6616 12:43:47.324240
6617 12:43:47.326844 [DATLAT]
6618 12:43:47.327350 Freq=400, CH0 RK1
6619 12:43:47.327794
6620 12:43:47.330374 DATLAT Default: 0xe
6621 12:43:47.330884 0, 0xFFFF, sum = 0
6622 12:43:47.333612 1, 0xFFFF, sum = 0
6623 12:43:47.334078 2, 0xFFFF, sum = 0
6624 12:43:47.336733 3, 0xFFFF, sum = 0
6625 12:43:47.337181 4, 0xFFFF, sum = 0
6626 12:43:47.340194 5, 0xFFFF, sum = 0
6627 12:43:47.340689 6, 0xFFFF, sum = 0
6628 12:43:47.343431 7, 0xFFFF, sum = 0
6629 12:43:47.343961 8, 0xFFFF, sum = 0
6630 12:43:47.346654 9, 0xFFFF, sum = 0
6631 12:43:47.347091 10, 0xFFFF, sum = 0
6632 12:43:47.349914 11, 0xFFFF, sum = 0
6633 12:43:47.350450 12, 0xFFFF, sum = 0
6634 12:43:47.353456 13, 0x0, sum = 1
6635 12:43:47.353976 14, 0x0, sum = 2
6636 12:43:47.356657 15, 0x0, sum = 3
6637 12:43:47.357292 16, 0x0, sum = 4
6638 12:43:47.360029 best_step = 14
6639 12:43:47.360593
6640 12:43:47.361120 ==
6641 12:43:47.363435 Dram Type= 6, Freq= 0, CH_0, rank 1
6642 12:43:47.366621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 12:43:47.367132 ==
6644 12:43:47.369926 RX Vref Scan: 0
6645 12:43:47.370385
6646 12:43:47.370724 RX Vref 0 -> 0, step: 1
6647 12:43:47.371040
6648 12:43:47.373106 RX Delay -359 -> 252, step: 8
6649 12:43:47.381238 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6650 12:43:47.384688 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6651 12:43:47.387997 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6652 12:43:47.391438 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6653 12:43:47.398050 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6654 12:43:47.401202 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6655 12:43:47.404417 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6656 12:43:47.407919 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6657 12:43:47.414459 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6658 12:43:47.417863 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6659 12:43:47.420947 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6660 12:43:47.427938 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6661 12:43:47.431092 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6662 12:43:47.434313 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6663 12:43:47.437537 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6664 12:43:47.444049 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6665 12:43:47.444541 ==
6666 12:43:47.447413 Dram Type= 6, Freq= 0, CH_0, rank 1
6667 12:43:47.450840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6668 12:43:47.451278 ==
6669 12:43:47.451639 DQS Delay:
6670 12:43:47.453790 DQS0 = 60, DQS1 = 72
6671 12:43:47.454252 DQM Delay:
6672 12:43:47.457315 DQM0 = 11, DQM1 = 17
6673 12:43:47.457825 DQ Delay:
6674 12:43:47.460486 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6675 12:43:47.463686 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6676 12:43:47.467531 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6677 12:43:47.470625 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6678 12:43:47.471241
6679 12:43:47.471595
6680 12:43:47.476899 [DQSOSCAuto] RK1, (LSB)MR18= 0xce84, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6681 12:43:47.480363 CH0 RK1: MR19=C0C, MR18=CE84
6682 12:43:47.487034 CH0_RK1: MR19=0xC0C, MR18=0xCE84, DQSOSC=384, MR23=63, INC=400, DEC=267
6683 12:43:47.490269 [RxdqsGatingPostProcess] freq 400
6684 12:43:47.496900 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6685 12:43:47.500403 best DQS0 dly(2T, 0.5T) = (0, 10)
6686 12:43:47.503392 best DQS1 dly(2T, 0.5T) = (0, 10)
6687 12:43:47.506880 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6688 12:43:47.510120 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6689 12:43:47.510560 best DQS0 dly(2T, 0.5T) = (0, 10)
6690 12:43:47.513391 best DQS1 dly(2T, 0.5T) = (0, 10)
6691 12:43:47.516895 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6692 12:43:47.520050 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6693 12:43:47.523454 Pre-setting of DQS Precalculation
6694 12:43:47.529919 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6695 12:43:47.530356 ==
6696 12:43:47.533444 Dram Type= 6, Freq= 0, CH_1, rank 0
6697 12:43:47.536484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6698 12:43:47.536931 ==
6699 12:43:47.543252 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6700 12:43:47.549862 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6701 12:43:47.553087 [CA 0] Center 36 (8~64) winsize 57
6702 12:43:47.553549 [CA 1] Center 36 (8~64) winsize 57
6703 12:43:47.556449 [CA 2] Center 36 (8~64) winsize 57
6704 12:43:47.559569 [CA 3] Center 36 (8~64) winsize 57
6705 12:43:47.562860 [CA 4] Center 36 (8~64) winsize 57
6706 12:43:47.566264 [CA 5] Center 36 (8~64) winsize 57
6707 12:43:47.566851
6708 12:43:47.569413 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6709 12:43:47.569878
6710 12:43:47.576120 [CATrainingPosCal] consider 1 rank data
6711 12:43:47.576737 u2DelayCellTimex100 = 270/100 ps
6712 12:43:47.582867 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 12:43:47.585812 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 12:43:47.589166 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 12:43:47.592658 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 12:43:47.595745 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 12:43:47.599129 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 12:43:47.599499
6719 12:43:47.602504 CA PerBit enable=1, Macro0, CA PI delay=36
6720 12:43:47.602888
6721 12:43:47.606101 [CBTSetCACLKResult] CA Dly = 36
6722 12:43:47.609725 CS Dly: 1 (0~32)
6723 12:43:47.610411 ==
6724 12:43:47.612668 Dram Type= 6, Freq= 0, CH_1, rank 1
6725 12:43:47.615870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 12:43:47.616311 ==
6727 12:43:47.622674 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6728 12:43:47.625883 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6729 12:43:47.629128 [CA 0] Center 36 (8~64) winsize 57
6730 12:43:47.632558 [CA 1] Center 36 (8~64) winsize 57
6731 12:43:47.635641 [CA 2] Center 36 (8~64) winsize 57
6732 12:43:47.639187 [CA 3] Center 36 (8~64) winsize 57
6733 12:43:47.642166 [CA 4] Center 36 (8~64) winsize 57
6734 12:43:47.645654 [CA 5] Center 36 (8~64) winsize 57
6735 12:43:47.646092
6736 12:43:47.649097 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6737 12:43:47.649589
6738 12:43:47.652424 [CATrainingPosCal] consider 2 rank data
6739 12:43:47.655469 u2DelayCellTimex100 = 270/100 ps
6740 12:43:47.658839 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6741 12:43:47.662226 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6742 12:43:47.665584 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6743 12:43:47.672251 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6744 12:43:47.675490 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6745 12:43:47.678521 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6746 12:43:47.678945
6747 12:43:47.682391 CA PerBit enable=1, Macro0, CA PI delay=36
6748 12:43:47.682838
6749 12:43:47.685059 [CBTSetCACLKResult] CA Dly = 36
6750 12:43:47.685579 CS Dly: 1 (0~32)
6751 12:43:47.685948
6752 12:43:47.688360 ----->DramcWriteLeveling(PI) begin...
6753 12:43:47.691870 ==
6754 12:43:47.695536 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 12:43:47.698610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 12:43:47.699055 ==
6757 12:43:47.701815 Write leveling (Byte 0): 40 => 8
6758 12:43:47.705272 Write leveling (Byte 1): 40 => 8
6759 12:43:47.708319 DramcWriteLeveling(PI) end<-----
6760 12:43:47.708754
6761 12:43:47.709101 ==
6762 12:43:47.711543 Dram Type= 6, Freq= 0, CH_1, rank 0
6763 12:43:47.715063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6764 12:43:47.715510 ==
6765 12:43:47.718263 [Gating] SW mode calibration
6766 12:43:47.725014 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6767 12:43:47.731516 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6768 12:43:47.735014 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6769 12:43:47.738048 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6770 12:43:47.744828 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6771 12:43:47.747897 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6772 12:43:47.751468 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6773 12:43:47.757851 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6774 12:43:47.761235 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6775 12:43:47.764535 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6776 12:43:47.771010 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6777 12:43:47.771451 Total UI for P1: 0, mck2ui 16
6778 12:43:47.777628 best dqsien dly found for B0: ( 0, 14, 24)
6779 12:43:47.778242 Total UI for P1: 0, mck2ui 16
6780 12:43:47.780979 best dqsien dly found for B1: ( 0, 14, 24)
6781 12:43:47.787481 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6782 12:43:47.790889 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6783 12:43:47.791329
6784 12:43:47.794227 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6785 12:43:47.797649 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6786 12:43:47.800736 [Gating] SW calibration Done
6787 12:43:47.801353 ==
6788 12:43:47.804486 Dram Type= 6, Freq= 0, CH_1, rank 0
6789 12:43:47.807669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6790 12:43:47.808242 ==
6791 12:43:47.810852 RX Vref Scan: 0
6792 12:43:47.811286
6793 12:43:47.811623 RX Vref 0 -> 0, step: 1
6794 12:43:47.811956
6795 12:43:47.814065 RX Delay -410 -> 252, step: 16
6796 12:43:47.820877 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6797 12:43:47.824190 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6798 12:43:47.827261 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6799 12:43:47.830530 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6800 12:43:47.837302 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6801 12:43:47.840242 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6802 12:43:47.843641 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6803 12:43:47.847124 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6804 12:43:47.853592 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6805 12:43:47.856866 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6806 12:43:47.860359 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6807 12:43:47.863556 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6808 12:43:47.870049 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6809 12:43:47.873422 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6810 12:43:47.876637 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6811 12:43:47.880127 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6812 12:43:47.883516 ==
6813 12:43:47.886580 Dram Type= 6, Freq= 0, CH_1, rank 0
6814 12:43:47.890076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6815 12:43:47.890524 ==
6816 12:43:47.890861 DQS Delay:
6817 12:43:47.893132 DQS0 = 51, DQS1 = 67
6818 12:43:47.893616 DQM Delay:
6819 12:43:47.896587 DQM0 = 12, DQM1 = 18
6820 12:43:47.897004 DQ Delay:
6821 12:43:47.899694 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6822 12:43:47.903075 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6823 12:43:47.906468 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6824 12:43:47.909743 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =32
6825 12:43:47.910161
6826 12:43:47.910529
6827 12:43:47.910842 ==
6828 12:43:47.912898 Dram Type= 6, Freq= 0, CH_1, rank 0
6829 12:43:47.916413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6830 12:43:47.916832 ==
6831 12:43:47.917163
6832 12:43:47.917466
6833 12:43:47.919558 TX Vref Scan disable
6834 12:43:47.920038 == TX Byte 0 ==
6835 12:43:47.926544 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6836 12:43:47.929821 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6837 12:43:47.930239 == TX Byte 1 ==
6838 12:43:47.936306 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6839 12:43:47.939816 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6840 12:43:47.940233 ==
6841 12:43:47.942787 Dram Type= 6, Freq= 0, CH_1, rank 0
6842 12:43:47.946137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6843 12:43:47.946558 ==
6844 12:43:47.947001
6845 12:43:47.947315
6846 12:43:47.949546 TX Vref Scan disable
6847 12:43:47.952800 == TX Byte 0 ==
6848 12:43:47.956156 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6849 12:43:47.959526 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6850 12:43:47.959942 == TX Byte 1 ==
6851 12:43:47.965987 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6852 12:43:47.969337 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6853 12:43:47.969748
6854 12:43:47.970098 [DATLAT]
6855 12:43:47.972905 Freq=400, CH1 RK0
6856 12:43:47.973270
6857 12:43:47.973607 DATLAT Default: 0xf
6858 12:43:47.976138 0, 0xFFFF, sum = 0
6859 12:43:47.976506 1, 0xFFFF, sum = 0
6860 12:43:47.979245 2, 0xFFFF, sum = 0
6861 12:43:47.979599 3, 0xFFFF, sum = 0
6862 12:43:47.982808 4, 0xFFFF, sum = 0
6863 12:43:47.983258 5, 0xFFFF, sum = 0
6864 12:43:47.985937 6, 0xFFFF, sum = 0
6865 12:43:47.989161 7, 0xFFFF, sum = 0
6866 12:43:47.989698 8, 0xFFFF, sum = 0
6867 12:43:47.992636 9, 0xFFFF, sum = 0
6868 12:43:47.993038 10, 0xFFFF, sum = 0
6869 12:43:47.996003 11, 0xFFFF, sum = 0
6870 12:43:47.996417 12, 0xFFFF, sum = 0
6871 12:43:47.999471 13, 0x0, sum = 1
6872 12:43:47.999900 14, 0x0, sum = 2
6873 12:43:48.002635 15, 0x0, sum = 3
6874 12:43:48.003060 16, 0x0, sum = 4
6875 12:43:48.003394 best_step = 14
6876 12:43:48.005979
6877 12:43:48.006395 ==
6878 12:43:48.009167 Dram Type= 6, Freq= 0, CH_1, rank 0
6879 12:43:48.012073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 12:43:48.012155 ==
6881 12:43:48.012219 RX Vref Scan: 1
6882 12:43:48.012278
6883 12:43:48.015473 RX Vref 0 -> 0, step: 1
6884 12:43:48.015554
6885 12:43:48.018602 RX Delay -375 -> 252, step: 8
6886 12:43:48.018682
6887 12:43:48.021983 Set Vref, RX VrefLevel [Byte0]: 54
6888 12:43:48.025349 [Byte1]: 48
6889 12:43:48.029242
6890 12:43:48.029349 Final RX Vref Byte 0 = 54 to rank0
6891 12:43:48.032809 Final RX Vref Byte 1 = 48 to rank0
6892 12:43:48.036244 Final RX Vref Byte 0 = 54 to rank1
6893 12:43:48.039408 Final RX Vref Byte 1 = 48 to rank1==
6894 12:43:48.042582 Dram Type= 6, Freq= 0, CH_1, rank 0
6895 12:43:48.049304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6896 12:43:48.049412 ==
6897 12:43:48.049537 DQS Delay:
6898 12:43:48.052438 DQS0 = 56, DQS1 = 68
6899 12:43:48.052519 DQM Delay:
6900 12:43:48.052583 DQM0 = 12, DQM1 = 14
6901 12:43:48.055842 DQ Delay:
6902 12:43:48.059104 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6903 12:43:48.059185 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6904 12:43:48.062591 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6905 12:43:48.065991 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6906 12:43:48.066072
6907 12:43:48.066135
6908 12:43:48.075700 [DQSOSCAuto] RK0, (LSB)MR18= 0x576a, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6909 12:43:48.079093 CH1 RK0: MR19=C0C, MR18=576A
6910 12:43:48.085798 CH1_RK0: MR19=0xC0C, MR18=0x576A, DQSOSC=396, MR23=63, INC=376, DEC=251
6911 12:43:48.085879 ==
6912 12:43:48.088983 Dram Type= 6, Freq= 0, CH_1, rank 1
6913 12:43:48.092620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6914 12:43:48.092702 ==
6915 12:43:48.095812 [Gating] SW mode calibration
6916 12:43:48.102305 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6917 12:43:48.109107 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6918 12:43:48.112202 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6919 12:43:48.115689 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6920 12:43:48.122051 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6921 12:43:48.125462 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6922 12:43:48.129006 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6923 12:43:48.132030 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6924 12:43:48.138747 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6925 12:43:48.142348 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6926 12:43:48.145355 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6927 12:43:48.148841 Total UI for P1: 0, mck2ui 16
6928 12:43:48.152195 best dqsien dly found for B0: ( 0, 14, 24)
6929 12:43:48.155544 Total UI for P1: 0, mck2ui 16
6930 12:43:48.158769 best dqsien dly found for B1: ( 0, 14, 24)
6931 12:43:48.162001 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6932 12:43:48.165386 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6933 12:43:48.168907
6934 12:43:48.171993 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6935 12:43:48.175230 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6936 12:43:48.178949 [Gating] SW calibration Done
6937 12:43:48.179030 ==
6938 12:43:48.181963 Dram Type= 6, Freq= 0, CH_1, rank 1
6939 12:43:48.185342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6940 12:43:48.185423 ==
6941 12:43:48.185511 RX Vref Scan: 0
6942 12:43:48.188754
6943 12:43:48.188844 RX Vref 0 -> 0, step: 1
6944 12:43:48.188909
6945 12:43:48.191905 RX Delay -410 -> 252, step: 16
6946 12:43:48.195330 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6947 12:43:48.201743 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6948 12:43:48.205153 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6949 12:43:48.208577 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6950 12:43:48.211941 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6951 12:43:48.218542 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6952 12:43:48.221834 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6953 12:43:48.225014 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6954 12:43:48.228415 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6955 12:43:48.234889 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6956 12:43:48.238462 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6957 12:43:48.241613 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6958 12:43:48.245241 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6959 12:43:48.251763 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6960 12:43:48.254984 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6961 12:43:48.258427 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6962 12:43:48.258508 ==
6963 12:43:48.261453 Dram Type= 6, Freq= 0, CH_1, rank 1
6964 12:43:48.268369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6965 12:43:48.268518 ==
6966 12:43:48.268583 DQS Delay:
6967 12:43:48.271563 DQS0 = 59, DQS1 = 59
6968 12:43:48.271643 DQM Delay:
6969 12:43:48.271707 DQM0 = 19, DQM1 = 13
6970 12:43:48.274986 DQ Delay:
6971 12:43:48.278160 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6972 12:43:48.281668 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6973 12:43:48.281749 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6974 12:43:48.288231 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =16
6975 12:43:48.288318
6976 12:43:48.288385
6977 12:43:48.288448 ==
6978 12:43:48.291682 Dram Type= 6, Freq= 0, CH_1, rank 1
6979 12:43:48.294877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6980 12:43:48.294979 ==
6981 12:43:48.295059
6982 12:43:48.295132
6983 12:43:48.298273 TX Vref Scan disable
6984 12:43:48.298374 == TX Byte 0 ==
6985 12:43:48.304727 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6986 12:43:48.307955 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6987 12:43:48.308077 == TX Byte 1 ==
6988 12:43:48.314910 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6989 12:43:48.317945 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6990 12:43:48.318095 ==
6991 12:43:48.321258 Dram Type= 6, Freq= 0, CH_1, rank 1
6992 12:43:48.324627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6993 12:43:48.324828 ==
6994 12:43:48.324986
6995 12:43:48.325132
6996 12:43:48.327983 TX Vref Scan disable
6997 12:43:48.328182 == TX Byte 0 ==
6998 12:43:48.334639 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6999 12:43:48.338101 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
7000 12:43:48.338407 == TX Byte 1 ==
7001 12:43:48.344701 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
7002 12:43:48.348079 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
7003 12:43:48.348495
7004 12:43:48.348824 [DATLAT]
7005 12:43:48.351547 Freq=400, CH1 RK1
7006 12:43:48.352122
7007 12:43:48.352464 DATLAT Default: 0xe
7008 12:43:48.354529 0, 0xFFFF, sum = 0
7009 12:43:48.354951 1, 0xFFFF, sum = 0
7010 12:43:48.358008 2, 0xFFFF, sum = 0
7011 12:43:48.358431 3, 0xFFFF, sum = 0
7012 12:43:48.361343 4, 0xFFFF, sum = 0
7013 12:43:48.364457 5, 0xFFFF, sum = 0
7014 12:43:48.364879 6, 0xFFFF, sum = 0
7015 12:43:48.368272 7, 0xFFFF, sum = 0
7016 12:43:48.368709 8, 0xFFFF, sum = 0
7017 12:43:48.371276 9, 0xFFFF, sum = 0
7018 12:43:48.371696 10, 0xFFFF, sum = 0
7019 12:43:48.374757 11, 0xFFFF, sum = 0
7020 12:43:48.375178 12, 0xFFFF, sum = 0
7021 12:43:48.378147 13, 0x0, sum = 1
7022 12:43:48.378567 14, 0x0, sum = 2
7023 12:43:48.381185 15, 0x0, sum = 3
7024 12:43:48.381677 16, 0x0, sum = 4
7025 12:43:48.382050 best_step = 14
7026 12:43:48.384762
7027 12:43:48.385193 ==
7028 12:43:48.387752 Dram Type= 6, Freq= 0, CH_1, rank 1
7029 12:43:48.391242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7030 12:43:48.391732 ==
7031 12:43:48.392106 RX Vref Scan: 0
7032 12:43:48.392440
7033 12:43:48.394370 RX Vref 0 -> 0, step: 1
7034 12:43:48.394857
7035 12:43:48.397880 RX Delay -359 -> 252, step: 8
7036 12:43:48.404944 iDelay=217, Bit 0, Center -40 (-287 ~ 208) 496
7037 12:43:48.408344 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7038 12:43:48.411695 iDelay=217, Bit 2, Center -56 (-303 ~ 192) 496
7039 12:43:48.418332 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7040 12:43:48.421632 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
7041 12:43:48.424838 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7042 12:43:48.428035 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7043 12:43:48.434525 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7044 12:43:48.437784 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7045 12:43:48.441463 iDelay=217, Bit 9, Center -60 (-319 ~ 200) 520
7046 12:43:48.444796 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7047 12:43:48.451206 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
7048 12:43:48.454624 iDelay=217, Bit 12, Center -44 (-295 ~ 208) 504
7049 12:43:48.457989 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7050 12:43:48.461048 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7051 12:43:48.467811 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7052 12:43:48.468315 ==
7053 12:43:48.471274 Dram Type= 6, Freq= 0, CH_1, rank 1
7054 12:43:48.474300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7055 12:43:48.474814 ==
7056 12:43:48.475233 DQS Delay:
7057 12:43:48.477587 DQS0 = 56, DQS1 = 64
7058 12:43:48.478242 DQM Delay:
7059 12:43:48.480728 DQM0 = 9, DQM1 = 11
7060 12:43:48.481256 DQ Delay:
7061 12:43:48.484276 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
7062 12:43:48.487643 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
7063 12:43:48.490812 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
7064 12:43:48.494404 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
7065 12:43:48.494901
7066 12:43:48.495343
7067 12:43:48.500873 [DQSOSCAuto] RK1, (LSB)MR18= 0x7cab, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
7068 12:43:48.503853 CH1 RK1: MR19=C0C, MR18=7CAB
7069 12:43:48.510825 CH1_RK1: MR19=0xC0C, MR18=0x7CAB, DQSOSC=388, MR23=63, INC=392, DEC=261
7070 12:43:48.513812 [RxdqsGatingPostProcess] freq 400
7071 12:43:48.520802 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7072 12:43:48.524011 best DQS0 dly(2T, 0.5T) = (0, 10)
7073 12:43:48.527250 best DQS1 dly(2T, 0.5T) = (0, 10)
7074 12:43:48.530644 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7075 12:43:48.533979 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7076 12:43:48.534406 best DQS0 dly(2T, 0.5T) = (0, 10)
7077 12:43:48.537372 best DQS1 dly(2T, 0.5T) = (0, 10)
7078 12:43:48.540440 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7079 12:43:48.543815 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7080 12:43:48.547594 Pre-setting of DQS Precalculation
7081 12:43:48.553866 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7082 12:43:48.560347 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7083 12:43:48.566860 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7084 12:43:48.567287
7085 12:43:48.567619
7086 12:43:48.570296 [Calibration Summary] 800 Mbps
7087 12:43:48.570767 CH 0, Rank 0
7088 12:43:48.573668 SW Impedance : PASS
7089 12:43:48.576873 DUTY Scan : NO K
7090 12:43:48.577449 ZQ Calibration : PASS
7091 12:43:48.580051 Jitter Meter : NO K
7092 12:43:48.583390 CBT Training : PASS
7093 12:43:48.583912 Write leveling : PASS
7094 12:43:48.586785 RX DQS gating : PASS
7095 12:43:48.590322 RX DQ/DQS(RDDQC) : PASS
7096 12:43:48.590746 TX DQ/DQS : PASS
7097 12:43:48.593327 RX DATLAT : PASS
7098 12:43:48.596745 RX DQ/DQS(Engine): PASS
7099 12:43:48.597171 TX OE : NO K
7100 12:43:48.597543 All Pass.
7101 12:43:48.600403
7102 12:43:48.600939 CH 0, Rank 1
7103 12:43:48.603667 SW Impedance : PASS
7104 12:43:48.604094 DUTY Scan : NO K
7105 12:43:48.606764 ZQ Calibration : PASS
7106 12:43:48.607202 Jitter Meter : NO K
7107 12:43:48.610286 CBT Training : PASS
7108 12:43:48.613407 Write leveling : NO K
7109 12:43:48.613853 RX DQS gating : PASS
7110 12:43:48.616930 RX DQ/DQS(RDDQC) : PASS
7111 12:43:48.620094 TX DQ/DQS : PASS
7112 12:43:48.620519 RX DATLAT : PASS
7113 12:43:48.623194 RX DQ/DQS(Engine): PASS
7114 12:43:48.626709 TX OE : NO K
7115 12:43:48.627137 All Pass.
7116 12:43:48.627476
7117 12:43:48.627790 CH 1, Rank 0
7118 12:43:48.630112 SW Impedance : PASS
7119 12:43:48.633331 DUTY Scan : NO K
7120 12:43:48.633776 ZQ Calibration : PASS
7121 12:43:48.636579 Jitter Meter : NO K
7122 12:43:48.639873 CBT Training : PASS
7123 12:43:48.640296 Write leveling : PASS
7124 12:43:48.643296 RX DQS gating : PASS
7125 12:43:48.646393 RX DQ/DQS(RDDQC) : PASS
7126 12:43:48.647000 TX DQ/DQS : PASS
7127 12:43:48.649927 RX DATLAT : PASS
7128 12:43:48.653302 RX DQ/DQS(Engine): PASS
7129 12:43:48.653762 TX OE : NO K
7130 12:43:48.654104 All Pass.
7131 12:43:48.656303
7132 12:43:48.656725 CH 1, Rank 1
7133 12:43:48.659715 SW Impedance : PASS
7134 12:43:48.660139 DUTY Scan : NO K
7135 12:43:48.663210 ZQ Calibration : PASS
7136 12:43:48.663635 Jitter Meter : NO K
7137 12:43:48.666578 CBT Training : PASS
7138 12:43:48.669950 Write leveling : NO K
7139 12:43:48.670401 RX DQS gating : PASS
7140 12:43:48.672978 RX DQ/DQS(RDDQC) : PASS
7141 12:43:48.676281 TX DQ/DQS : PASS
7142 12:43:48.676732 RX DATLAT : PASS
7143 12:43:48.679573 RX DQ/DQS(Engine): PASS
7144 12:43:48.682991 TX OE : NO K
7145 12:43:48.683468 All Pass.
7146 12:43:48.683924
7147 12:43:48.686113 DramC Write-DBI off
7148 12:43:48.686579 PER_BANK_REFRESH: Hybrid Mode
7149 12:43:48.690048 TX_TRACKING: ON
7150 12:43:48.699429 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7151 12:43:48.702919 [FAST_K] Save calibration result to emmc
7152 12:43:48.706044 dramc_set_vcore_voltage set vcore to 725000
7153 12:43:48.706493 Read voltage for 1600, 0
7154 12:43:48.709536 Vio18 = 0
7155 12:43:48.709990 Vcore = 725000
7156 12:43:48.710446 Vdram = 0
7157 12:43:48.712582 Vddq = 0
7158 12:43:48.713031 Vmddr = 0
7159 12:43:48.716011 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7160 12:43:48.722920 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7161 12:43:48.725969 MEM_TYPE=3, freq_sel=13
7162 12:43:48.729373 sv_algorithm_assistance_LP4_3733
7163 12:43:48.733080 ============ PULL DRAM RESETB DOWN ============
7164 12:43:48.735892 ========== PULL DRAM RESETB DOWN end =========
7165 12:43:48.742755 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7166 12:43:48.746034 ===================================
7167 12:43:48.746474 LPDDR4 DRAM CONFIGURATION
7168 12:43:48.749357 ===================================
7169 12:43:48.752731 EX_ROW_EN[0] = 0x0
7170 12:43:48.753156 EX_ROW_EN[1] = 0x0
7171 12:43:48.755870 LP4Y_EN = 0x0
7172 12:43:48.756294 WORK_FSP = 0x1
7173 12:43:48.759372 WL = 0x5
7174 12:43:48.762660 RL = 0x5
7175 12:43:48.763084 BL = 0x2
7176 12:43:48.766171 RPST = 0x0
7177 12:43:48.766613 RD_PRE = 0x0
7178 12:43:48.769100 WR_PRE = 0x1
7179 12:43:48.769575 WR_PST = 0x1
7180 12:43:48.772697 DBI_WR = 0x0
7181 12:43:48.773124 DBI_RD = 0x0
7182 12:43:48.775852 OTF = 0x1
7183 12:43:48.779207 ===================================
7184 12:43:48.782212 ===================================
7185 12:43:48.782667 ANA top config
7186 12:43:48.785717 ===================================
7187 12:43:48.789001 DLL_ASYNC_EN = 0
7188 12:43:48.792426 ALL_SLAVE_EN = 0
7189 12:43:48.792917 NEW_RANK_MODE = 1
7190 12:43:48.795679 DLL_IDLE_MODE = 1
7191 12:43:48.798751 LP45_APHY_COMB_EN = 1
7192 12:43:48.802297 TX_ODT_DIS = 0
7193 12:43:48.805813 NEW_8X_MODE = 1
7194 12:43:48.808629 ===================================
7195 12:43:48.812422 ===================================
7196 12:43:48.812994 data_rate = 3200
7197 12:43:48.815448 CKR = 1
7198 12:43:48.818624 DQ_P2S_RATIO = 8
7199 12:43:48.821987 ===================================
7200 12:43:48.825321 CA_P2S_RATIO = 8
7201 12:43:48.828617 DQ_CA_OPEN = 0
7202 12:43:48.831951 DQ_SEMI_OPEN = 0
7203 12:43:48.832393 CA_SEMI_OPEN = 0
7204 12:43:48.835441 CA_FULL_RATE = 0
7205 12:43:48.838488 DQ_CKDIV4_EN = 0
7206 12:43:48.841817 CA_CKDIV4_EN = 0
7207 12:43:48.845198 CA_PREDIV_EN = 0
7208 12:43:48.848579 PH8_DLY = 12
7209 12:43:48.849024 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7210 12:43:48.851863 DQ_AAMCK_DIV = 4
7211 12:43:48.855247 CA_AAMCK_DIV = 4
7212 12:43:48.858615 CA_ADMCK_DIV = 4
7213 12:43:48.862172 DQ_TRACK_CA_EN = 0
7214 12:43:48.865246 CA_PICK = 1600
7215 12:43:48.868520 CA_MCKIO = 1600
7216 12:43:48.868965 MCKIO_SEMI = 0
7217 12:43:48.871552 PLL_FREQ = 3068
7218 12:43:48.875020 DQ_UI_PI_RATIO = 32
7219 12:43:48.878573 CA_UI_PI_RATIO = 0
7220 12:43:48.881540 ===================================
7221 12:43:48.884853 ===================================
7222 12:43:48.888193 memory_type:LPDDR4
7223 12:43:48.888684 GP_NUM : 10
7224 12:43:48.891491 SRAM_EN : 1
7225 12:43:48.894829 MD32_EN : 0
7226 12:43:48.898135 ===================================
7227 12:43:48.898609 [ANA_INIT] >>>>>>>>>>>>>>
7228 12:43:48.901609 <<<<<< [CONFIGURE PHASE]: ANA_TX
7229 12:43:48.904980 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7230 12:43:48.908429 ===================================
7231 12:43:48.911515 data_rate = 3200,PCW = 0X7600
7232 12:43:48.914965 ===================================
7233 12:43:48.917973 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7234 12:43:48.924810 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7235 12:43:48.928265 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7236 12:43:48.934608 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7237 12:43:48.938031 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7238 12:43:48.941257 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7239 12:43:48.941871 [ANA_INIT] flow start
7240 12:43:48.944488 [ANA_INIT] PLL >>>>>>>>
7241 12:43:48.947832 [ANA_INIT] PLL <<<<<<<<
7242 12:43:48.951443 [ANA_INIT] MIDPI >>>>>>>>
7243 12:43:48.951884 [ANA_INIT] MIDPI <<<<<<<<
7244 12:43:48.954572 [ANA_INIT] DLL >>>>>>>>
7245 12:43:48.957969 [ANA_INIT] DLL <<<<<<<<
7246 12:43:48.958418 [ANA_INIT] flow end
7247 12:43:48.961186 ============ LP4 DIFF to SE enter ============
7248 12:43:48.967862 ============ LP4 DIFF to SE exit ============
7249 12:43:48.968307 [ANA_INIT] <<<<<<<<<<<<<
7250 12:43:48.971336 [Flow] Enable top DCM control >>>>>
7251 12:43:48.974446 [Flow] Enable top DCM control <<<<<
7252 12:43:48.977981 Enable DLL master slave shuffle
7253 12:43:48.984443 ==============================================================
7254 12:43:48.984887 Gating Mode config
7255 12:43:48.991154 ==============================================================
7256 12:43:48.994558 Config description:
7257 12:43:49.004288 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7258 12:43:49.011206 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7259 12:43:49.014302 SELPH_MODE 0: By rank 1: By Phase
7260 12:43:49.020844 ==============================================================
7261 12:43:49.024136 GAT_TRACK_EN = 1
7262 12:43:49.027486 RX_GATING_MODE = 2
7263 12:43:49.027938 RX_GATING_TRACK_MODE = 2
7264 12:43:49.030977 SELPH_MODE = 1
7265 12:43:49.034528 PICG_EARLY_EN = 1
7266 12:43:49.037830 VALID_LAT_VALUE = 1
7267 12:43:49.044197 ==============================================================
7268 12:43:49.047220 Enter into Gating configuration >>>>
7269 12:43:49.050963 Exit from Gating configuration <<<<
7270 12:43:49.054129 Enter into DVFS_PRE_config >>>>>
7271 12:43:49.064288 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7272 12:43:49.067578 Exit from DVFS_PRE_config <<<<<
7273 12:43:49.070788 Enter into PICG configuration >>>>
7274 12:43:49.074114 Exit from PICG configuration <<<<
7275 12:43:49.077551 [RX_INPUT] configuration >>>>>
7276 12:43:49.080901 [RX_INPUT] configuration <<<<<
7277 12:43:49.084136 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7278 12:43:49.090526 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7279 12:43:49.097115 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7280 12:43:49.103787 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7281 12:43:49.107165 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7282 12:43:49.113969 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7283 12:43:49.117172 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7284 12:43:49.123831 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7285 12:43:49.127300 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7286 12:43:49.130654 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7287 12:43:49.133794 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7288 12:43:49.140644 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7289 12:43:49.144033 ===================================
7290 12:43:49.144544 LPDDR4 DRAM CONFIGURATION
7291 12:43:49.147106 ===================================
7292 12:43:49.150540 EX_ROW_EN[0] = 0x0
7293 12:43:49.153911 EX_ROW_EN[1] = 0x0
7294 12:43:49.154349 LP4Y_EN = 0x0
7295 12:43:49.156940 WORK_FSP = 0x1
7296 12:43:49.157379 WL = 0x5
7297 12:43:49.160162 RL = 0x5
7298 12:43:49.160602 BL = 0x2
7299 12:43:49.163482 RPST = 0x0
7300 12:43:49.163923 RD_PRE = 0x0
7301 12:43:49.167148 WR_PRE = 0x1
7302 12:43:49.167691 WR_PST = 0x1
7303 12:43:49.170420 DBI_WR = 0x0
7304 12:43:49.170856 DBI_RD = 0x0
7305 12:43:49.173543 OTF = 0x1
7306 12:43:49.176710 ===================================
7307 12:43:49.180237 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7308 12:43:49.183528 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7309 12:43:49.189928 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7310 12:43:49.193333 ===================================
7311 12:43:49.193835 LPDDR4 DRAM CONFIGURATION
7312 12:43:49.196835 ===================================
7313 12:43:49.200011 EX_ROW_EN[0] = 0x10
7314 12:43:49.203212 EX_ROW_EN[1] = 0x0
7315 12:43:49.203652 LP4Y_EN = 0x0
7316 12:43:49.206691 WORK_FSP = 0x1
7317 12:43:49.207115 WL = 0x5
7318 12:43:49.210023 RL = 0x5
7319 12:43:49.210464 BL = 0x2
7320 12:43:49.213141 RPST = 0x0
7321 12:43:49.213630 RD_PRE = 0x0
7322 12:43:49.216556 WR_PRE = 0x1
7323 12:43:49.216988 WR_PST = 0x1
7324 12:43:49.219927 DBI_WR = 0x0
7325 12:43:49.220377 DBI_RD = 0x0
7326 12:43:49.223267 OTF = 0x1
7327 12:43:49.226419 ===================================
7328 12:43:49.232812 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7329 12:43:49.233251 ==
7330 12:43:49.236091 Dram Type= 6, Freq= 0, CH_0, rank 0
7331 12:43:49.239383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7332 12:43:49.239824 ==
7333 12:43:49.242965 [Duty_Offset_Calibration]
7334 12:43:49.243386 B0:2 B1:0 CA:3
7335 12:43:49.243736
7336 12:43:49.246109 [DutyScan_Calibration_Flow] k_type=0
7337 12:43:49.257007
7338 12:43:49.257448 ==CLK 0==
7339 12:43:49.260535 Final CLK duty delay cell = 0
7340 12:43:49.263819 [0] MAX Duty = 5031%(X100), DQS PI = 12
7341 12:43:49.267191 [0] MIN Duty = 4907%(X100), DQS PI = 6
7342 12:43:49.267629 [0] AVG Duty = 4969%(X100)
7343 12:43:49.270483
7344 12:43:49.270917 CH0 CLK Duty spec in!! Max-Min= 124%
7345 12:43:49.277106 [DutyScan_Calibration_Flow] ====Done====
7346 12:43:49.277581
7347 12:43:49.280417 [DutyScan_Calibration_Flow] k_type=1
7348 12:43:49.297186
7349 12:43:49.297682 ==DQS 0 ==
7350 12:43:49.300541 Final DQS duty delay cell = 0
7351 12:43:49.303642 [0] MAX Duty = 5125%(X100), DQS PI = 30
7352 12:43:49.307027 [0] MIN Duty = 4875%(X100), DQS PI = 48
7353 12:43:49.310580 [0] AVG Duty = 5000%(X100)
7354 12:43:49.311037
7355 12:43:49.311490 ==DQS 1 ==
7356 12:43:49.313556 Final DQS duty delay cell = 0
7357 12:43:49.316724 [0] MAX Duty = 5156%(X100), DQS PI = 32
7358 12:43:49.320337 [0] MIN Duty = 5062%(X100), DQS PI = 10
7359 12:43:49.323306 [0] AVG Duty = 5109%(X100)
7360 12:43:49.323917
7361 12:43:49.327036 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7362 12:43:49.327626
7363 12:43:49.330170 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7364 12:43:49.333392 [DutyScan_Calibration_Flow] ====Done====
7365 12:43:49.334025
7366 12:43:49.336742 [DutyScan_Calibration_Flow] k_type=3
7367 12:43:49.353882
7368 12:43:49.354057 ==DQM 0 ==
7369 12:43:49.357161 Final DQM duty delay cell = 0
7370 12:43:49.360533 [0] MAX Duty = 5156%(X100), DQS PI = 30
7371 12:43:49.363927 [0] MIN Duty = 4875%(X100), DQS PI = 0
7372 12:43:49.364078 [0] AVG Duty = 5015%(X100)
7373 12:43:49.367470
7374 12:43:49.367627 ==DQM 1 ==
7375 12:43:49.370543 Final DQM duty delay cell = 0
7376 12:43:49.373967 [0] MAX Duty = 4938%(X100), DQS PI = 60
7377 12:43:49.377297 [0] MIN Duty = 4813%(X100), DQS PI = 18
7378 12:43:49.377440 [0] AVG Duty = 4875%(X100)
7379 12:43:49.380635
7380 12:43:49.384081 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7381 12:43:49.384229
7382 12:43:49.387137 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7383 12:43:49.390536 [DutyScan_Calibration_Flow] ====Done====
7384 12:43:49.390670
7385 12:43:49.394159 [DutyScan_Calibration_Flow] k_type=2
7386 12:43:49.410503
7387 12:43:49.410803 ==DQ 0 ==
7388 12:43:49.413634 Final DQ duty delay cell = -4
7389 12:43:49.416969 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7390 12:43:49.420584 [-4] MIN Duty = 4876%(X100), DQS PI = 46
7391 12:43:49.423741 [-4] AVG Duty = 4938%(X100)
7392 12:43:49.424121
7393 12:43:49.424430 ==DQ 1 ==
7394 12:43:49.427118 Final DQ duty delay cell = 0
7395 12:43:49.430568 [0] MAX Duty = 5156%(X100), DQS PI = 58
7396 12:43:49.433738 [0] MIN Duty = 5000%(X100), DQS PI = 14
7397 12:43:49.437277 [0] AVG Duty = 5078%(X100)
7398 12:43:49.437745
7399 12:43:49.440221 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7400 12:43:49.440608
7401 12:43:49.443642 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7402 12:43:49.447175 [DutyScan_Calibration_Flow] ====Done====
7403 12:43:49.447610 ==
7404 12:43:49.450235 Dram Type= 6, Freq= 0, CH_1, rank 0
7405 12:43:49.453597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7406 12:43:49.454023 ==
7407 12:43:49.457076 [Duty_Offset_Calibration]
7408 12:43:49.457595 B0:1 B1:-2 CA:0
7409 12:43:49.457932
7410 12:43:49.460277 [DutyScan_Calibration_Flow] k_type=0
7411 12:43:49.471134
7412 12:43:49.471551 ==CLK 0==
7413 12:43:49.474406 Final CLK duty delay cell = 0
7414 12:43:49.477745 [0] MAX Duty = 5062%(X100), DQS PI = 20
7415 12:43:49.481259 [0] MIN Duty = 4844%(X100), DQS PI = 60
7416 12:43:49.481718 [0] AVG Duty = 4953%(X100)
7417 12:43:49.484361
7418 12:43:49.487820 CH1 CLK Duty spec in!! Max-Min= 218%
7419 12:43:49.490865 [DutyScan_Calibration_Flow] ====Done====
7420 12:43:49.491305
7421 12:43:49.494173 [DutyScan_Calibration_Flow] k_type=1
7422 12:43:49.510120
7423 12:43:49.510606 ==DQS 0 ==
7424 12:43:49.513614 Final DQS duty delay cell = -4
7425 12:43:49.516730 [-4] MAX Duty = 5000%(X100), DQS PI = 26
7426 12:43:49.520039 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7427 12:43:49.523261 [-4] AVG Duty = 4922%(X100)
7428 12:43:49.523698
7429 12:43:49.524039 ==DQS 1 ==
7430 12:43:49.526412 Final DQS duty delay cell = 0
7431 12:43:49.529980 [0] MAX Duty = 5124%(X100), DQS PI = 62
7432 12:43:49.533396 [0] MIN Duty = 4844%(X100), DQS PI = 26
7433 12:43:49.536677 [0] AVG Duty = 4984%(X100)
7434 12:43:49.537113
7435 12:43:49.540015 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7436 12:43:49.540449
7437 12:43:49.543457 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7438 12:43:49.546705 [DutyScan_Calibration_Flow] ====Done====
7439 12:43:49.547137
7440 12:43:49.549994 [DutyScan_Calibration_Flow] k_type=3
7441 12:43:49.567681
7442 12:43:49.568141 ==DQM 0 ==
7443 12:43:49.570539 Final DQM duty delay cell = 0
7444 12:43:49.574061 [0] MAX Duty = 5031%(X100), DQS PI = 24
7445 12:43:49.577548 [0] MIN Duty = 4813%(X100), DQS PI = 56
7446 12:43:49.580512 [0] AVG Duty = 4922%(X100)
7447 12:43:49.580932
7448 12:43:49.581263 ==DQM 1 ==
7449 12:43:49.583951 Final DQM duty delay cell = 0
7450 12:43:49.587218 [0] MAX Duty = 5093%(X100), DQS PI = 36
7451 12:43:49.590614 [0] MIN Duty = 4875%(X100), DQS PI = 26
7452 12:43:49.593822 [0] AVG Duty = 4984%(X100)
7453 12:43:49.594245
7454 12:43:49.597258 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7455 12:43:49.597730
7456 12:43:49.600673 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7457 12:43:49.603832 [DutyScan_Calibration_Flow] ====Done====
7458 12:43:49.604256
7459 12:43:49.606833 [DutyScan_Calibration_Flow] k_type=2
7460 12:43:49.624246
7461 12:43:49.624993 ==DQ 0 ==
7462 12:43:49.627944 Final DQ duty delay cell = 0
7463 12:43:49.630888 [0] MAX Duty = 5093%(X100), DQS PI = 20
7464 12:43:49.634342 [0] MIN Duty = 4907%(X100), DQS PI = 62
7465 12:43:49.634810 [0] AVG Duty = 5000%(X100)
7466 12:43:49.637515
7467 12:43:49.637982 ==DQ 1 ==
7468 12:43:49.640770 Final DQ duty delay cell = 0
7469 12:43:49.644175 [0] MAX Duty = 5156%(X100), DQS PI = 36
7470 12:43:49.647380 [0] MIN Duty = 4969%(X100), DQS PI = 24
7471 12:43:49.647837 [0] AVG Duty = 5062%(X100)
7472 12:43:49.650783
7473 12:43:49.653972 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7474 12:43:49.654425
7475 12:43:49.657522 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7476 12:43:49.660630 [DutyScan_Calibration_Flow] ====Done====
7477 12:43:49.663958 nWR fixed to 30
7478 12:43:49.664415 [ModeRegInit_LP4] CH0 RK0
7479 12:43:49.667338 [ModeRegInit_LP4] CH0 RK1
7480 12:43:49.670615 [ModeRegInit_LP4] CH1 RK0
7481 12:43:49.673943 [ModeRegInit_LP4] CH1 RK1
7482 12:43:49.674391 match AC timing 5
7483 12:43:49.680218 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7484 12:43:49.683763 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7485 12:43:49.687119 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7486 12:43:49.693793 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7487 12:43:49.697029 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7488 12:43:49.697499 [MiockJmeterHQA]
7489 12:43:49.697969
7490 12:43:49.700493 [DramcMiockJmeter] u1RxGatingPI = 0
7491 12:43:49.703621 0 : 4255, 4027
7492 12:43:49.704082 4 : 4253, 4027
7493 12:43:49.707081 8 : 4365, 4140
7494 12:43:49.707662 12 : 4368, 4140
7495 12:43:49.708130 16 : 4363, 4137
7496 12:43:49.710443 20 : 4258, 4027
7497 12:43:49.710905 24 : 4252, 4027
7498 12:43:49.713438 28 : 4255, 4027
7499 12:43:49.713927 32 : 4255, 4027
7500 12:43:49.716825 36 : 4252, 4027
7501 12:43:49.717290 40 : 4364, 4137
7502 12:43:49.720269 44 : 4257, 4029
7503 12:43:49.720732 48 : 4365, 4137
7504 12:43:49.721199 52 : 4255, 4027
7505 12:43:49.723572 56 : 4254, 4026
7506 12:43:49.724043 60 : 4255, 4027
7507 12:43:49.726884 64 : 4368, 4140
7508 12:43:49.727347 68 : 4363, 4137
7509 12:43:49.730216 72 : 4258, 4029
7510 12:43:49.730670 76 : 4257, 4029
7511 12:43:49.733392 80 : 4253, 4027
7512 12:43:49.733889 84 : 4258, 4030
7513 12:43:49.734358 88 : 4255, 4029
7514 12:43:49.736795 92 : 4363, 4138
7515 12:43:49.737253 96 : 4257, 4029
7516 12:43:49.740394 100 : 4363, 4137
7517 12:43:49.740851 104 : 4363, 3979
7518 12:43:49.743401 108 : 4255, 2
7519 12:43:49.743859 112 : 4252, 0
7520 12:43:49.744328 116 : 4258, 0
7521 12:43:49.746635 120 : 4254, 0
7522 12:43:49.747089 124 : 4363, 0
7523 12:43:49.750027 128 : 4249, 0
7524 12:43:49.750501 132 : 4252, 0
7525 12:43:49.750970 136 : 4252, 0
7526 12:43:49.753343 140 : 4250, 0
7527 12:43:49.753835 144 : 4253, 0
7528 12:43:49.756760 148 : 4250, 0
7529 12:43:49.757224 152 : 4250, 0
7530 12:43:49.757789 156 : 4252, 0
7531 12:43:49.760288 160 : 4361, 0
7532 12:43:49.760745 164 : 4250, 0
7533 12:43:49.761216 168 : 4250, 0
7534 12:43:49.763426 172 : 4360, 0
7535 12:43:49.763882 176 : 4250, 0
7536 12:43:49.766576 180 : 4250, 0
7537 12:43:49.767054 184 : 4250, 0
7538 12:43:49.767512 188 : 4361, 0
7539 12:43:49.769986 192 : 4361, 0
7540 12:43:49.770425 196 : 4250, 0
7541 12:43:49.773372 200 : 4250, 0
7542 12:43:49.773846 204 : 4250, 0
7543 12:43:49.774202 208 : 4253, 0
7544 12:43:49.776775 212 : 4250, 0
7545 12:43:49.777221 216 : 4250, 0
7546 12:43:49.779892 220 : 4252, 0
7547 12:43:49.780333 224 : 4360, 0
7548 12:43:49.780689 228 : 4250, 0
7549 12:43:49.783238 232 : 4250, 1
7550 12:43:49.783752 236 : 4250, 1037
7551 12:43:49.786487 240 : 4250, 4027
7552 12:43:49.787010 244 : 4250, 4027
7553 12:43:49.789663 248 : 4250, 4027
7554 12:43:49.790182 252 : 4361, 4138
7555 12:43:49.793159 256 : 4250, 4027
7556 12:43:49.793634 260 : 4250, 4027
7557 12:43:49.794139 264 : 4361, 4137
7558 12:43:49.796233 268 : 4250, 4027
7559 12:43:49.796674 272 : 4250, 4027
7560 12:43:49.799591 276 : 4360, 4138
7561 12:43:49.800051 280 : 4249, 4027
7562 12:43:49.803082 284 : 4250, 4027
7563 12:43:49.803526 288 : 4250, 4027
7564 12:43:49.806119 292 : 4250, 4027
7565 12:43:49.806569 296 : 4250, 4027
7566 12:43:49.809585 300 : 4252, 4027
7567 12:43:49.810042 304 : 4361, 4138
7568 12:43:49.812968 308 : 4250, 4027
7569 12:43:49.813415 312 : 4250, 4027
7570 12:43:49.816159 316 : 4361, 4137
7571 12:43:49.816604 320 : 4250, 4027
7572 12:43:49.819290 324 : 4360, 4138
7573 12:43:49.819733 328 : 4360, 4138
7574 12:43:49.820221 332 : 4250, 4027
7575 12:43:49.822643 336 : 4250, 4027
7576 12:43:49.823086 340 : 4250, 4027
7577 12:43:49.825945 344 : 4250, 4027
7578 12:43:49.826391 348 : 4250, 4027
7579 12:43:49.829398 352 : 4250, 4025
7580 12:43:49.829874 356 : 4361, 3134
7581 12:43:49.832543 360 : 4250, 1
7582 12:43:49.832991
7583 12:43:49.833505 MIOCK jitter meter ch=0
7584 12:43:49.833858
7585 12:43:49.836022 1T = (360-108) = 252 dly cells
7586 12:43:49.842719 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7587 12:43:49.843179 ==
7588 12:43:49.845960 Dram Type= 6, Freq= 0, CH_0, rank 0
7589 12:43:49.849371 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7590 12:43:49.849856 ==
7591 12:43:49.855881 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7592 12:43:49.859371 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7593 12:43:49.865464 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7594 12:43:49.868791 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7595 12:43:49.879200 [CA 0] Center 44 (14~75) winsize 62
7596 12:43:49.882606 [CA 1] Center 43 (13~74) winsize 62
7597 12:43:49.885554 [CA 2] Center 40 (11~69) winsize 59
7598 12:43:49.889290 [CA 3] Center 39 (10~68) winsize 59
7599 12:43:49.892307 [CA 4] Center 37 (8~67) winsize 60
7600 12:43:49.895798 [CA 5] Center 37 (7~67) winsize 61
7601 12:43:49.896251
7602 12:43:49.899125 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7603 12:43:49.899577
7604 12:43:49.905766 [CATrainingPosCal] consider 1 rank data
7605 12:43:49.906229 u2DelayCellTimex100 = 258/100 ps
7606 12:43:49.912141 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7607 12:43:49.915610 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7608 12:43:49.918848 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7609 12:43:49.922385 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7610 12:43:49.925576 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7611 12:43:49.928842 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7612 12:43:49.929300
7613 12:43:49.932070 CA PerBit enable=1, Macro0, CA PI delay=37
7614 12:43:49.932520
7615 12:43:49.935317 [CBTSetCACLKResult] CA Dly = 37
7616 12:43:49.938782 CS Dly: 11 (0~42)
7617 12:43:49.942014 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7618 12:43:49.945451 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7619 12:43:49.945958 ==
7620 12:43:49.948678 Dram Type= 6, Freq= 0, CH_0, rank 1
7621 12:43:49.955418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7622 12:43:49.955872 ==
7623 12:43:49.958682 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7624 12:43:49.965202 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7625 12:43:49.968331 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7626 12:43:49.975068 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7627 12:43:49.983125 [CA 0] Center 44 (13~75) winsize 63
7628 12:43:49.986618 [CA 1] Center 43 (13~74) winsize 62
7629 12:43:49.989812 [CA 2] Center 39 (10~69) winsize 60
7630 12:43:49.993140 [CA 3] Center 39 (10~68) winsize 59
7631 12:43:49.996547 [CA 4] Center 37 (8~67) winsize 60
7632 12:43:49.999873 [CA 5] Center 36 (7~66) winsize 60
7633 12:43:50.000325
7634 12:43:50.003058 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7635 12:43:50.003522
7636 12:43:50.006212 [CATrainingPosCal] consider 2 rank data
7637 12:43:50.010002 u2DelayCellTimex100 = 258/100 ps
7638 12:43:50.016301 CA0 delay=44 (14~75),Diff = 8 PI (30 cell)
7639 12:43:50.019841 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7640 12:43:50.022903 CA2 delay=40 (11~69),Diff = 4 PI (15 cell)
7641 12:43:50.026581 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7642 12:43:50.029602 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
7643 12:43:50.033184 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7644 12:43:50.033714
7645 12:43:50.036378 CA PerBit enable=1, Macro0, CA PI delay=36
7646 12:43:50.036826
7647 12:43:50.039572 [CBTSetCACLKResult] CA Dly = 36
7648 12:43:50.043119 CS Dly: 11 (0~43)
7649 12:43:50.046183 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7650 12:43:50.049456 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7651 12:43:50.050052
7652 12:43:50.052759 ----->DramcWriteLeveling(PI) begin...
7653 12:43:50.053196 ==
7654 12:43:50.056381 Dram Type= 6, Freq= 0, CH_0, rank 0
7655 12:43:50.062885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7656 12:43:50.063323 ==
7657 12:43:50.066277 Write leveling (Byte 0): 36 => 36
7658 12:43:50.069470 Write leveling (Byte 1): 29 => 29
7659 12:43:50.069969 DramcWriteLeveling(PI) end<-----
7660 12:43:50.072669
7661 12:43:50.073120 ==
7662 12:43:50.076217 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 12:43:50.079189 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 12:43:50.079645 ==
7665 12:43:50.082405 [Gating] SW mode calibration
7666 12:43:50.089167 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7667 12:43:50.092381 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7668 12:43:50.099108 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7669 12:43:50.102405 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7670 12:43:50.105525 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7671 12:43:50.112368 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7672 12:43:50.115424 1 4 16 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
7673 12:43:50.119084 1 4 20 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
7674 12:43:50.125384 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7675 12:43:50.128765 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7676 12:43:50.132198 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7677 12:43:50.138863 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7678 12:43:50.142327 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7679 12:43:50.145440 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7680 12:43:50.152085 1 5 16 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
7681 12:43:50.155500 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
7682 12:43:50.158691 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
7683 12:43:50.165454 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7684 12:43:50.168772 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7685 12:43:50.172130 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7686 12:43:50.178811 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7687 12:43:50.181986 1 6 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7688 12:43:50.185315 1 6 16 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
7689 12:43:50.191971 1 6 20 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7690 12:43:50.195346 1 6 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
7691 12:43:50.198348 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7692 12:43:50.205231 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7693 12:43:50.208554 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7694 12:43:50.211665 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7695 12:43:50.218561 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7696 12:43:50.221627 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7697 12:43:50.225278 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7698 12:43:50.231803 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7699 12:43:50.235070 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7700 12:43:50.238311 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7701 12:43:50.244812 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7702 12:43:50.248436 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7703 12:43:50.251992 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7704 12:43:50.255167 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7705 12:43:50.261966 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7706 12:43:50.265084 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7707 12:43:50.268368 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7708 12:43:50.274833 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7709 12:43:50.278263 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7710 12:43:50.281532 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7711 12:43:50.288246 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7712 12:43:50.291452 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7713 12:43:50.294682 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7714 12:43:50.298008 Total UI for P1: 0, mck2ui 16
7715 12:43:50.301775 best dqsien dly found for B0: ( 1, 9, 14)
7716 12:43:50.308349 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7717 12:43:50.311334 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7718 12:43:50.314536 Total UI for P1: 0, mck2ui 16
7719 12:43:50.317819 best dqsien dly found for B1: ( 1, 9, 22)
7720 12:43:50.321121 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7721 12:43:50.324513 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7722 12:43:50.324962
7723 12:43:50.328203 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7724 12:43:50.334246 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7725 12:43:50.334708 [Gating] SW calibration Done
7726 12:43:50.335163 ==
7727 12:43:50.337553 Dram Type= 6, Freq= 0, CH_0, rank 0
7728 12:43:50.344383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7729 12:43:50.344842 ==
7730 12:43:50.345303 RX Vref Scan: 0
7731 12:43:50.345772
7732 12:43:50.347471 RX Vref 0 -> 0, step: 1
7733 12:43:50.347859
7734 12:43:50.350742 RX Delay 0 -> 252, step: 8
7735 12:43:50.353947 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7736 12:43:50.357446 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7737 12:43:50.360841 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7738 12:43:50.367383 iDelay=192, Bit 3, Center 119 (64 ~ 175) 112
7739 12:43:50.370551 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7740 12:43:50.374094 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7741 12:43:50.377336 iDelay=192, Bit 6, Center 135 (80 ~ 191) 112
7742 12:43:50.380486 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7743 12:43:50.387100 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7744 12:43:50.390394 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7745 12:43:50.393921 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7746 12:43:50.397191 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7747 12:43:50.400431 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7748 12:43:50.407155 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7749 12:43:50.410279 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7750 12:43:50.413446 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7751 12:43:50.413922 ==
7752 12:43:50.416991 Dram Type= 6, Freq= 0, CH_0, rank 0
7753 12:43:50.420043 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7754 12:43:50.423703 ==
7755 12:43:50.424140 DQS Delay:
7756 12:43:50.424478 DQS0 = 0, DQS1 = 0
7757 12:43:50.426837 DQM Delay:
7758 12:43:50.427373 DQM0 = 126, DQM1 = 123
7759 12:43:50.430082 DQ Delay:
7760 12:43:50.433640 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7761 12:43:50.436661 DQ4 =127, DQ5 =111, DQ6 =135, DQ7 =135
7762 12:43:50.439938 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7763 12:43:50.443547 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7764 12:43:50.444001
7765 12:43:50.444546
7766 12:43:50.444879 ==
7767 12:43:50.446519 Dram Type= 6, Freq= 0, CH_0, rank 0
7768 12:43:50.449914 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7769 12:43:50.450470 ==
7770 12:43:50.450976
7771 12:43:50.453153
7772 12:43:50.453593 TX Vref Scan disable
7773 12:43:50.456436 == TX Byte 0 ==
7774 12:43:50.459737 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7775 12:43:50.463051 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7776 12:43:50.466427 == TX Byte 1 ==
7777 12:43:50.469530 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7778 12:43:50.473407 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7779 12:43:50.473899 ==
7780 12:43:50.476407 Dram Type= 6, Freq= 0, CH_0, rank 0
7781 12:43:50.482849 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7782 12:43:50.483297 ==
7783 12:43:50.495506
7784 12:43:50.498836 TX Vref early break, caculate TX vref
7785 12:43:50.502100 TX Vref=16, minBit 8, minWin=21, winSum=364
7786 12:43:50.505246 TX Vref=18, minBit 8, minWin=22, winSum=373
7787 12:43:50.508739 TX Vref=20, minBit 8, minWin=22, winSum=383
7788 12:43:50.512219 TX Vref=22, minBit 8, minWin=23, winSum=396
7789 12:43:50.515317 TX Vref=24, minBit 8, minWin=24, winSum=406
7790 12:43:50.522158 TX Vref=26, minBit 11, minWin=24, winSum=406
7791 12:43:50.525265 TX Vref=28, minBit 9, minWin=24, winSum=412
7792 12:43:50.528797 TX Vref=30, minBit 4, minWin=24, winSum=400
7793 12:43:50.531943 TX Vref=32, minBit 8, minWin=22, winSum=395
7794 12:43:50.535351 TX Vref=34, minBit 15, minWin=22, winSum=384
7795 12:43:50.542025 [TxChooseVref] Worse bit 9, Min win 24, Win sum 412, Final Vref 28
7796 12:43:50.542458
7797 12:43:50.545252 Final TX Range 0 Vref 28
7798 12:43:50.545778
7799 12:43:50.546126 ==
7800 12:43:50.548512 Dram Type= 6, Freq= 0, CH_0, rank 0
7801 12:43:50.551620 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7802 12:43:50.552044 ==
7803 12:43:50.552388
7804 12:43:50.552711
7805 12:43:50.555007 TX Vref Scan disable
7806 12:43:50.561739 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7807 12:43:50.562175 == TX Byte 0 ==
7808 12:43:50.565069 u2DelayCellOfst[0]=15 cells (4 PI)
7809 12:43:50.568482 u2DelayCellOfst[1]=18 cells (5 PI)
7810 12:43:50.571540 u2DelayCellOfst[2]=11 cells (3 PI)
7811 12:43:50.574863 u2DelayCellOfst[3]=15 cells (4 PI)
7812 12:43:50.578506 u2DelayCellOfst[4]=11 cells (3 PI)
7813 12:43:50.581580 u2DelayCellOfst[5]=0 cells (0 PI)
7814 12:43:50.584978 u2DelayCellOfst[6]=18 cells (5 PI)
7815 12:43:50.588408 u2DelayCellOfst[7]=18 cells (5 PI)
7816 12:43:50.591608 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7817 12:43:50.594784 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7818 12:43:50.598336 == TX Byte 1 ==
7819 12:43:50.601502 u2DelayCellOfst[8]=0 cells (0 PI)
7820 12:43:50.601948 u2DelayCellOfst[9]=3 cells (1 PI)
7821 12:43:50.604767 u2DelayCellOfst[10]=7 cells (2 PI)
7822 12:43:50.608092 u2DelayCellOfst[11]=3 cells (1 PI)
7823 12:43:50.611420 u2DelayCellOfst[12]=15 cells (4 PI)
7824 12:43:50.614769 u2DelayCellOfst[13]=11 cells (3 PI)
7825 12:43:50.618107 u2DelayCellOfst[14]=15 cells (4 PI)
7826 12:43:50.621181 u2DelayCellOfst[15]=11 cells (3 PI)
7827 12:43:50.624658 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7828 12:43:50.631243 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7829 12:43:50.631666 DramC Write-DBI on
7830 12:43:50.632013 ==
7831 12:43:50.634753 Dram Type= 6, Freq= 0, CH_0, rank 0
7832 12:43:50.641180 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7833 12:43:50.641788 ==
7834 12:43:50.642275
7835 12:43:50.642712
7836 12:43:50.643019 TX Vref Scan disable
7837 12:43:50.645061 == TX Byte 0 ==
7838 12:43:50.648397 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7839 12:43:50.652018 == TX Byte 1 ==
7840 12:43:50.655132 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7841 12:43:50.658335 DramC Write-DBI off
7842 12:43:50.658765
7843 12:43:50.659118 [DATLAT]
7844 12:43:50.659439 Freq=1600, CH0 RK0
7845 12:43:50.659743
7846 12:43:50.661883 DATLAT Default: 0xf
7847 12:43:50.662316 0, 0xFFFF, sum = 0
7848 12:43:50.665026 1, 0xFFFF, sum = 0
7849 12:43:50.668328 2, 0xFFFF, sum = 0
7850 12:43:50.668854 3, 0xFFFF, sum = 0
7851 12:43:50.671764 4, 0xFFFF, sum = 0
7852 12:43:50.672338 5, 0xFFFF, sum = 0
7853 12:43:50.674859 6, 0xFFFF, sum = 0
7854 12:43:50.675335 7, 0xFFFF, sum = 0
7855 12:43:50.678406 8, 0xFFFF, sum = 0
7856 12:43:50.678846 9, 0xFFFF, sum = 0
7857 12:43:50.681658 10, 0xFFFF, sum = 0
7858 12:43:50.682097 11, 0xFFFF, sum = 0
7859 12:43:50.684863 12, 0xFFFF, sum = 0
7860 12:43:50.685439 13, 0xFFFF, sum = 0
7861 12:43:50.688343 14, 0x0, sum = 1
7862 12:43:50.688782 15, 0x0, sum = 2
7863 12:43:50.691585 16, 0x0, sum = 3
7864 12:43:50.692184 17, 0x0, sum = 4
7865 12:43:50.694745 best_step = 15
7866 12:43:50.695182
7867 12:43:50.695528 ==
7868 12:43:50.698023 Dram Type= 6, Freq= 0, CH_0, rank 0
7869 12:43:50.701375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7870 12:43:50.701866 ==
7871 12:43:50.704549 RX Vref Scan: 1
7872 12:43:50.705087
7873 12:43:50.705652 Set Vref Range= 24 -> 127
7874 12:43:50.706006
7875 12:43:50.708237 RX Vref 24 -> 127, step: 1
7876 12:43:50.708794
7877 12:43:50.711572 RX Delay 11 -> 252, step: 4
7878 12:43:50.712013
7879 12:43:50.714492 Set Vref, RX VrefLevel [Byte0]: 24
7880 12:43:50.718098 [Byte1]: 24
7881 12:43:50.718521
7882 12:43:50.721439 Set Vref, RX VrefLevel [Byte0]: 25
7883 12:43:50.724555 [Byte1]: 25
7884 12:43:50.728001
7885 12:43:50.728425 Set Vref, RX VrefLevel [Byte0]: 26
7886 12:43:50.731406 [Byte1]: 26
7887 12:43:50.735757
7888 12:43:50.736200 Set Vref, RX VrefLevel [Byte0]: 27
7889 12:43:50.738916 [Byte1]: 27
7890 12:43:50.743414
7891 12:43:50.743877 Set Vref, RX VrefLevel [Byte0]: 28
7892 12:43:50.746728 [Byte1]: 28
7893 12:43:50.750763
7894 12:43:50.751194 Set Vref, RX VrefLevel [Byte0]: 29
7895 12:43:50.753980 [Byte1]: 29
7896 12:43:50.758385
7897 12:43:50.758816 Set Vref, RX VrefLevel [Byte0]: 30
7898 12:43:50.761933 [Byte1]: 30
7899 12:43:50.766254
7900 12:43:50.766684 Set Vref, RX VrefLevel [Byte0]: 31
7901 12:43:50.769398 [Byte1]: 31
7902 12:43:50.773811
7903 12:43:50.774243 Set Vref, RX VrefLevel [Byte0]: 32
7904 12:43:50.776896 [Byte1]: 32
7905 12:43:50.781210
7906 12:43:50.781725 Set Vref, RX VrefLevel [Byte0]: 33
7907 12:43:50.784666 [Byte1]: 33
7908 12:43:50.788803
7909 12:43:50.789233 Set Vref, RX VrefLevel [Byte0]: 34
7910 12:43:50.792238 [Byte1]: 34
7911 12:43:50.796397
7912 12:43:50.796827 Set Vref, RX VrefLevel [Byte0]: 35
7913 12:43:50.799934 [Byte1]: 35
7914 12:43:50.804215
7915 12:43:50.804646 Set Vref, RX VrefLevel [Byte0]: 36
7916 12:43:50.807593 [Byte1]: 36
7917 12:43:50.811618
7918 12:43:50.812059 Set Vref, RX VrefLevel [Byte0]: 37
7919 12:43:50.814897 [Byte1]: 37
7920 12:43:50.819574
7921 12:43:50.820137 Set Vref, RX VrefLevel [Byte0]: 38
7922 12:43:50.822718 [Byte1]: 38
7923 12:43:50.826883
7924 12:43:50.827312 Set Vref, RX VrefLevel [Byte0]: 39
7925 12:43:50.830327 [Byte1]: 39
7926 12:43:50.834497
7927 12:43:50.834927 Set Vref, RX VrefLevel [Byte0]: 40
7928 12:43:50.837968 [Byte1]: 40
7929 12:43:50.842066
7930 12:43:50.842602 Set Vref, RX VrefLevel [Byte0]: 41
7931 12:43:50.845514 [Byte1]: 41
7932 12:43:50.850002
7933 12:43:50.850438 Set Vref, RX VrefLevel [Byte0]: 42
7934 12:43:50.853064 [Byte1]: 42
7935 12:43:50.857303
7936 12:43:50.857795 Set Vref, RX VrefLevel [Byte0]: 43
7937 12:43:50.860700 [Byte1]: 43
7938 12:43:50.865375
7939 12:43:50.865843 Set Vref, RX VrefLevel [Byte0]: 44
7940 12:43:50.868361 [Byte1]: 44
7941 12:43:50.872555
7942 12:43:50.872981 Set Vref, RX VrefLevel [Byte0]: 45
7943 12:43:50.875753 [Byte1]: 45
7944 12:43:50.880168
7945 12:43:50.880592 Set Vref, RX VrefLevel [Byte0]: 46
7946 12:43:50.883580 [Byte1]: 46
7947 12:43:50.887762
7948 12:43:50.888195 Set Vref, RX VrefLevel [Byte0]: 47
7949 12:43:50.891206 [Byte1]: 47
7950 12:43:50.895256
7951 12:43:50.895829 Set Vref, RX VrefLevel [Byte0]: 48
7952 12:43:50.898765 [Byte1]: 48
7953 12:43:50.903014
7954 12:43:50.903567 Set Vref, RX VrefLevel [Byte0]: 49
7955 12:43:50.906511 [Byte1]: 49
7956 12:43:50.910856
7957 12:43:50.911278 Set Vref, RX VrefLevel [Byte0]: 50
7958 12:43:50.913889 [Byte1]: 50
7959 12:43:50.918321
7960 12:43:50.918831 Set Vref, RX VrefLevel [Byte0]: 51
7961 12:43:50.921398 [Byte1]: 51
7962 12:43:50.925990
7963 12:43:50.926435 Set Vref, RX VrefLevel [Byte0]: 52
7964 12:43:50.929383 [Byte1]: 52
7965 12:43:50.933355
7966 12:43:50.933830 Set Vref, RX VrefLevel [Byte0]: 53
7967 12:43:50.937042 [Byte1]: 53
7968 12:43:50.941305
7969 12:43:50.941793 Set Vref, RX VrefLevel [Byte0]: 54
7970 12:43:50.944565 [Byte1]: 54
7971 12:43:50.948715
7972 12:43:50.949192 Set Vref, RX VrefLevel [Byte0]: 55
7973 12:43:50.951914 [Byte1]: 55
7974 12:43:50.956465
7975 12:43:50.956943 Set Vref, RX VrefLevel [Byte0]: 56
7976 12:43:50.959633 [Byte1]: 56
7977 12:43:50.963801
7978 12:43:50.964227 Set Vref, RX VrefLevel [Byte0]: 57
7979 12:43:50.967175 [Byte1]: 57
7980 12:43:50.971535
7981 12:43:50.971959 Set Vref, RX VrefLevel [Byte0]: 58
7982 12:43:50.974686 [Byte1]: 58
7983 12:43:50.979349
7984 12:43:50.979768 Set Vref, RX VrefLevel [Byte0]: 59
7985 12:43:50.982339 [Byte1]: 59
7986 12:43:50.986942
7987 12:43:50.987369 Set Vref, RX VrefLevel [Byte0]: 60
7988 12:43:50.990037 [Byte1]: 60
7989 12:43:50.994504
7990 12:43:50.994924 Set Vref, RX VrefLevel [Byte0]: 61
7991 12:43:50.997558 [Byte1]: 61
7992 12:43:51.002096
7993 12:43:51.002519 Set Vref, RX VrefLevel [Byte0]: 62
7994 12:43:51.005443 [Byte1]: 62
7995 12:43:51.009678
7996 12:43:51.010105 Set Vref, RX VrefLevel [Byte0]: 63
7997 12:43:51.012887 [Byte1]: 63
7998 12:43:51.017333
7999 12:43:51.017799 Set Vref, RX VrefLevel [Byte0]: 64
8000 12:43:51.020348 [Byte1]: 64
8001 12:43:51.024660
8002 12:43:51.025084 Set Vref, RX VrefLevel [Byte0]: 65
8003 12:43:51.028086 [Byte1]: 65
8004 12:43:51.032595
8005 12:43:51.033016 Set Vref, RX VrefLevel [Byte0]: 66
8006 12:43:51.035607 [Byte1]: 66
8007 12:43:51.040187
8008 12:43:51.040610 Set Vref, RX VrefLevel [Byte0]: 67
8009 12:43:51.043364 [Byte1]: 67
8010 12:43:51.047539
8011 12:43:51.047961 Set Vref, RX VrefLevel [Byte0]: 68
8012 12:43:51.050832 [Byte1]: 68
8013 12:43:51.055352
8014 12:43:51.055792 Set Vref, RX VrefLevel [Byte0]: 69
8015 12:43:51.058383 [Byte1]: 69
8016 12:43:51.062930
8017 12:43:51.063351 Set Vref, RX VrefLevel [Byte0]: 70
8018 12:43:51.066293 [Byte1]: 70
8019 12:43:51.070415
8020 12:43:51.070888 Set Vref, RX VrefLevel [Byte0]: 71
8021 12:43:51.073821 [Byte1]: 71
8022 12:43:51.078230
8023 12:43:51.078725 Set Vref, RX VrefLevel [Byte0]: 72
8024 12:43:51.081446 [Byte1]: 72
8025 12:43:51.085594
8026 12:43:51.086070 Set Vref, RX VrefLevel [Byte0]: 73
8027 12:43:51.089069 [Byte1]: 73
8028 12:43:51.093317
8029 12:43:51.093936 Set Vref, RX VrefLevel [Byte0]: 74
8030 12:43:51.096745 [Byte1]: 74
8031 12:43:51.101057
8032 12:43:51.101676 Set Vref, RX VrefLevel [Byte0]: 75
8033 12:43:51.104111 [Byte1]: 75
8034 12:43:51.108717
8035 12:43:51.109193 Set Vref, RX VrefLevel [Byte0]: 76
8036 12:43:51.111864 [Byte1]: 76
8037 12:43:51.116160
8038 12:43:51.116638 Final RX Vref Byte 0 = 63 to rank0
8039 12:43:51.119374 Final RX Vref Byte 1 = 58 to rank0
8040 12:43:51.122967 Final RX Vref Byte 0 = 63 to rank1
8041 12:43:51.126337 Final RX Vref Byte 1 = 58 to rank1==
8042 12:43:51.129572 Dram Type= 6, Freq= 0, CH_0, rank 0
8043 12:43:51.136163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8044 12:43:51.136648 ==
8045 12:43:51.137006 DQS Delay:
8046 12:43:51.137399 DQS0 = 0, DQS1 = 0
8047 12:43:51.139615 DQM Delay:
8048 12:43:51.140092 DQM0 = 126, DQM1 = 119
8049 12:43:51.142897 DQ Delay:
8050 12:43:51.146099 DQ0 =126, DQ1 =126, DQ2 =126, DQ3 =122
8051 12:43:51.149372 DQ4 =126, DQ5 =114, DQ6 =132, DQ7 =138
8052 12:43:51.152824 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8053 12:43:51.156282 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
8054 12:43:51.156764
8055 12:43:51.157171
8056 12:43:51.157623
8057 12:43:51.159606 [DramC_TX_OE_Calibration] TA2
8058 12:43:51.162806 Original DQ_B0 (3 6) =30, OEN = 27
8059 12:43:51.166181 Original DQ_B1 (3 6) =30, OEN = 27
8060 12:43:51.169553 24, 0x0, End_B0=24 End_B1=24
8061 12:43:51.170052 25, 0x0, End_B0=25 End_B1=25
8062 12:43:51.172967 26, 0x0, End_B0=26 End_B1=26
8063 12:43:51.175823 27, 0x0, End_B0=27 End_B1=27
8064 12:43:51.179333 28, 0x0, End_B0=28 End_B1=28
8065 12:43:51.182758 29, 0x0, End_B0=29 End_B1=29
8066 12:43:51.183247 30, 0x0, End_B0=30 End_B1=30
8067 12:43:51.185790 31, 0x4141, End_B0=30 End_B1=30
8068 12:43:51.189050 Byte0 end_step=30 best_step=27
8069 12:43:51.192260 Byte1 end_step=30 best_step=27
8070 12:43:51.195729 Byte0 TX OE(2T, 0.5T) = (3, 3)
8071 12:43:51.199002 Byte1 TX OE(2T, 0.5T) = (3, 3)
8072 12:43:51.199521
8073 12:43:51.199945
8074 12:43:51.205568 [DQSOSCAuto] RK0, (LSB)MR18= 0x1211, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
8075 12:43:51.208897 CH0 RK0: MR19=303, MR18=1211
8076 12:43:51.215646 CH0_RK0: MR19=0x303, MR18=0x1211, DQSOSC=400, MR23=63, INC=23, DEC=15
8077 12:43:51.216122
8078 12:43:51.218802 ----->DramcWriteLeveling(PI) begin...
8079 12:43:51.219314 ==
8080 12:43:51.222213 Dram Type= 6, Freq= 0, CH_0, rank 1
8081 12:43:51.225304 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8082 12:43:51.225919 ==
8083 12:43:51.228775 Write leveling (Byte 0): 35 => 35
8084 12:43:51.231888 Write leveling (Byte 1): 27 => 27
8085 12:43:51.235238 DramcWriteLeveling(PI) end<-----
8086 12:43:51.235751
8087 12:43:51.236153 ==
8088 12:43:51.238590 Dram Type= 6, Freq= 0, CH_0, rank 1
8089 12:43:51.241866 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8090 12:43:51.242353 ==
8091 12:43:51.245221 [Gating] SW mode calibration
8092 12:43:51.251856 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8093 12:43:51.258544 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8094 12:43:51.261788 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8095 12:43:51.268400 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8096 12:43:51.271590 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8097 12:43:51.275134 1 4 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8098 12:43:51.281586 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8099 12:43:51.284865 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8100 12:43:51.288176 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8101 12:43:51.294775 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8102 12:43:51.298197 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8103 12:43:51.301407 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8104 12:43:51.307927 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8105 12:43:51.311436 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
8106 12:43:51.314483 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8107 12:43:51.321348 1 5 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8108 12:43:51.324379 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8109 12:43:51.327783 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8110 12:43:51.334430 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8111 12:43:51.337601 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8112 12:43:51.341035 1 6 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
8113 12:43:51.347506 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8114 12:43:51.350957 1 6 16 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
8115 12:43:51.353939 1 6 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8116 12:43:51.360803 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8117 12:43:51.364013 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8118 12:43:51.367392 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8119 12:43:51.373944 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8120 12:43:51.377317 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8121 12:43:51.380656 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8122 12:43:51.387116 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8123 12:43:51.390619 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8124 12:43:51.393690 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8125 12:43:51.400547 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8126 12:43:51.403581 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8127 12:43:51.406785 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8128 12:43:51.413397 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8129 12:43:51.416688 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8130 12:43:51.420165 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8131 12:43:51.426602 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8132 12:43:51.430004 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8133 12:43:51.433465 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8134 12:43:51.439790 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8135 12:43:51.443420 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8136 12:43:51.446409 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8137 12:43:51.453148 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8138 12:43:51.456419 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8139 12:43:51.459919 Total UI for P1: 0, mck2ui 16
8140 12:43:51.463372 best dqsien dly found for B0: ( 1, 9, 10)
8141 12:43:51.466494 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8142 12:43:51.469848 Total UI for P1: 0, mck2ui 16
8143 12:43:51.472950 best dqsien dly found for B1: ( 1, 9, 16)
8144 12:43:51.476332 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8145 12:43:51.479652 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8146 12:43:51.480111
8147 12:43:51.483051 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8148 12:43:51.489459 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8149 12:43:51.489928 [Gating] SW calibration Done
8150 12:43:51.492918 ==
8151 12:43:51.493357 Dram Type= 6, Freq= 0, CH_0, rank 1
8152 12:43:51.499445 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8153 12:43:51.499870 ==
8154 12:43:51.500200 RX Vref Scan: 0
8155 12:43:51.500505
8156 12:43:51.502849 RX Vref 0 -> 0, step: 1
8157 12:43:51.503323
8158 12:43:51.506133 RX Delay 0 -> 252, step: 8
8159 12:43:51.509376 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8160 12:43:51.512627 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8161 12:43:51.515863 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8162 12:43:51.522854 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8163 12:43:51.526122 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8164 12:43:51.529425 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8165 12:43:51.532782 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8166 12:43:51.535774 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8167 12:43:51.542341 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8168 12:43:51.545954 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8169 12:43:51.549373 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8170 12:43:51.552538 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8171 12:43:51.555709 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8172 12:43:51.562593 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8173 12:43:51.566007 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8174 12:43:51.569091 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8175 12:43:51.569602 ==
8176 12:43:51.572606 Dram Type= 6, Freq= 0, CH_0, rank 1
8177 12:43:51.575955 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8178 12:43:51.576435 ==
8179 12:43:51.579244 DQS Delay:
8180 12:43:51.579764 DQS0 = 0, DQS1 = 0
8181 12:43:51.582648 DQM Delay:
8182 12:43:51.583178 DQM0 = 128, DQM1 = 121
8183 12:43:51.585957 DQ Delay:
8184 12:43:51.589276 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8185 12:43:51.592274 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8186 12:43:51.595746 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8187 12:43:51.599238 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8188 12:43:51.599789
8189 12:43:51.600127
8190 12:43:51.600436 ==
8191 12:43:51.602649 Dram Type= 6, Freq= 0, CH_0, rank 1
8192 12:43:51.605761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8193 12:43:51.606180 ==
8194 12:43:51.606571
8195 12:43:51.606888
8196 12:43:51.609240 TX Vref Scan disable
8197 12:43:51.612262 == TX Byte 0 ==
8198 12:43:51.615900 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8199 12:43:51.619001 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8200 12:43:51.622076 == TX Byte 1 ==
8201 12:43:51.625397 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8202 12:43:51.628953 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8203 12:43:51.629378 ==
8204 12:43:51.632216 Dram Type= 6, Freq= 0, CH_0, rank 1
8205 12:43:51.638569 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8206 12:43:51.638987 ==
8207 12:43:51.651204
8208 12:43:51.654358 TX Vref early break, caculate TX vref
8209 12:43:51.657794 TX Vref=16, minBit 8, minWin=21, winSum=366
8210 12:43:51.660842 TX Vref=18, minBit 8, minWin=22, winSum=377
8211 12:43:51.664334 TX Vref=20, minBit 8, minWin=22, winSum=380
8212 12:43:51.667610 TX Vref=22, minBit 9, minWin=22, winSum=387
8213 12:43:51.670962 TX Vref=24, minBit 8, minWin=23, winSum=399
8214 12:43:51.677565 TX Vref=26, minBit 8, minWin=24, winSum=412
8215 12:43:51.681147 TX Vref=28, minBit 8, minWin=24, winSum=408
8216 12:43:51.684165 TX Vref=30, minBit 8, minWin=23, winSum=406
8217 12:43:51.687510 TX Vref=32, minBit 8, minWin=23, winSum=398
8218 12:43:51.690819 TX Vref=34, minBit 8, minWin=22, winSum=389
8219 12:43:51.697548 [TxChooseVref] Worse bit 8, Min win 24, Win sum 412, Final Vref 26
8220 12:43:51.697981
8221 12:43:51.700705 Final TX Range 0 Vref 26
8222 12:43:51.701131
8223 12:43:51.701464 ==
8224 12:43:51.704209 Dram Type= 6, Freq= 0, CH_0, rank 1
8225 12:43:51.707760 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8226 12:43:51.708185 ==
8227 12:43:51.708519
8228 12:43:51.708827
8229 12:43:51.710730 TX Vref Scan disable
8230 12:43:51.717361 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8231 12:43:51.717948 == TX Byte 0 ==
8232 12:43:51.720775 u2DelayCellOfst[0]=15 cells (4 PI)
8233 12:43:51.723923 u2DelayCellOfst[1]=22 cells (6 PI)
8234 12:43:51.727531 u2DelayCellOfst[2]=15 cells (4 PI)
8235 12:43:51.730818 u2DelayCellOfst[3]=11 cells (3 PI)
8236 12:43:51.733882 u2DelayCellOfst[4]=11 cells (3 PI)
8237 12:43:51.737218 u2DelayCellOfst[5]=0 cells (0 PI)
8238 12:43:51.740490 u2DelayCellOfst[6]=22 cells (6 PI)
8239 12:43:51.743849 u2DelayCellOfst[7]=18 cells (5 PI)
8240 12:43:51.746950 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8241 12:43:51.750281 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8242 12:43:51.753904 == TX Byte 1 ==
8243 12:43:51.757161 u2DelayCellOfst[8]=0 cells (0 PI)
8244 12:43:51.757617 u2DelayCellOfst[9]=0 cells (0 PI)
8245 12:43:51.760325 u2DelayCellOfst[10]=7 cells (2 PI)
8246 12:43:51.763722 u2DelayCellOfst[11]=3 cells (1 PI)
8247 12:43:51.767128 u2DelayCellOfst[12]=15 cells (4 PI)
8248 12:43:51.770194 u2DelayCellOfst[13]=15 cells (4 PI)
8249 12:43:51.773795 u2DelayCellOfst[14]=15 cells (4 PI)
8250 12:43:51.776789 u2DelayCellOfst[15]=11 cells (3 PI)
8251 12:43:51.780334 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8252 12:43:51.786902 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8253 12:43:51.787321 DramC Write-DBI on
8254 12:43:51.787673 ==
8255 12:43:51.790556 Dram Type= 6, Freq= 0, CH_0, rank 1
8256 12:43:51.794023 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8257 12:43:51.797133 ==
8258 12:43:51.797580
8259 12:43:51.797923
8260 12:43:51.798256 TX Vref Scan disable
8261 12:43:51.800633 == TX Byte 0 ==
8262 12:43:51.803985 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8263 12:43:51.807437 == TX Byte 1 ==
8264 12:43:51.810566 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8265 12:43:51.814078 DramC Write-DBI off
8266 12:43:51.814495
8267 12:43:51.814823 [DATLAT]
8268 12:43:51.815125 Freq=1600, CH0 RK1
8269 12:43:51.815424
8270 12:43:51.817180 DATLAT Default: 0xf
8271 12:43:51.817625 0, 0xFFFF, sum = 0
8272 12:43:51.820751 1, 0xFFFF, sum = 0
8273 12:43:51.824024 2, 0xFFFF, sum = 0
8274 12:43:51.824501 3, 0xFFFF, sum = 0
8275 12:43:51.827249 4, 0xFFFF, sum = 0
8276 12:43:51.827681 5, 0xFFFF, sum = 0
8277 12:43:51.830593 6, 0xFFFF, sum = 0
8278 12:43:51.831025 7, 0xFFFF, sum = 0
8279 12:43:51.833868 8, 0xFFFF, sum = 0
8280 12:43:51.834299 9, 0xFFFF, sum = 0
8281 12:43:51.837005 10, 0xFFFF, sum = 0
8282 12:43:51.837437 11, 0xFFFF, sum = 0
8283 12:43:51.840607 12, 0xFFFF, sum = 0
8284 12:43:51.841036 13, 0xCFFF, sum = 0
8285 12:43:51.843653 14, 0x0, sum = 1
8286 12:43:51.844085 15, 0x0, sum = 2
8287 12:43:51.847018 16, 0x0, sum = 3
8288 12:43:51.847448 17, 0x0, sum = 4
8289 12:43:51.850428 best_step = 15
8290 12:43:51.850851
8291 12:43:51.851183 ==
8292 12:43:51.853565 Dram Type= 6, Freq= 0, CH_0, rank 1
8293 12:43:51.856798 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8294 12:43:51.857270 ==
8295 12:43:51.860137 RX Vref Scan: 0
8296 12:43:51.860559
8297 12:43:51.860896 RX Vref 0 -> 0, step: 1
8298 12:43:51.861273
8299 12:43:51.863596 RX Delay 3 -> 252, step: 4
8300 12:43:51.869845 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8301 12:43:51.873014 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8302 12:43:51.876374 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8303 12:43:51.879794 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8304 12:43:51.883016 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8305 12:43:51.886523 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8306 12:43:51.893113 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8307 12:43:51.896108 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8308 12:43:51.899546 iDelay=191, Bit 8, Center 112 (55 ~ 170) 116
8309 12:43:51.902931 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8310 12:43:51.906090 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8311 12:43:51.913003 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8312 12:43:51.916269 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8313 12:43:51.919461 iDelay=191, Bit 13, Center 124 (67 ~ 182) 116
8314 12:43:51.922871 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8315 12:43:51.929559 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8316 12:43:51.929642 ==
8317 12:43:51.932741 Dram Type= 6, Freq= 0, CH_0, rank 1
8318 12:43:51.936099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8319 12:43:51.936182 ==
8320 12:43:51.936248 DQS Delay:
8321 12:43:51.939300 DQS0 = 0, DQS1 = 0
8322 12:43:51.939382 DQM Delay:
8323 12:43:51.942567 DQM0 = 124, DQM1 = 118
8324 12:43:51.942649 DQ Delay:
8325 12:43:51.945968 DQ0 =124, DQ1 =126, DQ2 =122, DQ3 =122
8326 12:43:51.949172 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8327 12:43:51.952753 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
8328 12:43:51.956020 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8329 12:43:51.956103
8330 12:43:51.956167
8331 12:43:51.959339
8332 12:43:51.959420 [DramC_TX_OE_Calibration] TA2
8333 12:43:51.962549 Original DQ_B0 (3 6) =30, OEN = 27
8334 12:43:51.965956 Original DQ_B1 (3 6) =30, OEN = 27
8335 12:43:51.969035 24, 0x0, End_B0=24 End_B1=24
8336 12:43:51.972723 25, 0x0, End_B0=25 End_B1=25
8337 12:43:51.975641 26, 0x0, End_B0=26 End_B1=26
8338 12:43:51.975725 27, 0x0, End_B0=27 End_B1=27
8339 12:43:51.979093 28, 0x0, End_B0=28 End_B1=28
8340 12:43:51.982155 29, 0x0, End_B0=29 End_B1=29
8341 12:43:51.985765 30, 0x0, End_B0=30 End_B1=30
8342 12:43:51.989132 31, 0x4141, End_B0=30 End_B1=30
8343 12:43:51.989243 Byte0 end_step=30 best_step=27
8344 12:43:51.992271 Byte1 end_step=30 best_step=27
8345 12:43:51.995750 Byte0 TX OE(2T, 0.5T) = (3, 3)
8346 12:43:51.999119 Byte1 TX OE(2T, 0.5T) = (3, 3)
8347 12:43:51.999202
8348 12:43:51.999268
8349 12:43:52.005366 [DQSOSCAuto] RK1, (LSB)MR18= 0x210f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8350 12:43:52.008853 CH0 RK1: MR19=303, MR18=210F
8351 12:43:52.015519 CH0_RK1: MR19=0x303, MR18=0x210F, DQSOSC=393, MR23=63, INC=23, DEC=15
8352 12:43:52.018780 [RxdqsGatingPostProcess] freq 1600
8353 12:43:52.025285 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8354 12:43:52.028770 best DQS0 dly(2T, 0.5T) = (1, 1)
8355 12:43:52.031904 best DQS1 dly(2T, 0.5T) = (1, 1)
8356 12:43:52.031987 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8357 12:43:52.035146 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8358 12:43:52.038792 best DQS0 dly(2T, 0.5T) = (1, 1)
8359 12:43:52.041770 best DQS1 dly(2T, 0.5T) = (1, 1)
8360 12:43:52.045098 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8361 12:43:52.048661 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8362 12:43:52.051718 Pre-setting of DQS Precalculation
8363 12:43:52.058624 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8364 12:43:52.058729 ==
8365 12:43:52.061769 Dram Type= 6, Freq= 0, CH_1, rank 0
8366 12:43:52.065271 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8367 12:43:52.065406 ==
8368 12:43:52.071546 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8369 12:43:52.075144 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8370 12:43:52.078435 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8371 12:43:52.084960 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8372 12:43:52.093393 [CA 0] Center 41 (12~71) winsize 60
8373 12:43:52.097180 [CA 1] Center 42 (13~72) winsize 60
8374 12:43:52.100047 [CA 2] Center 37 (9~66) winsize 58
8375 12:43:52.103582 [CA 3] Center 37 (8~66) winsize 59
8376 12:43:52.106955 [CA 4] Center 37 (8~67) winsize 60
8377 12:43:52.110122 [CA 5] Center 36 (7~66) winsize 60
8378 12:43:52.110204
8379 12:43:52.113355 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8380 12:43:52.113462
8381 12:43:52.116558 [CATrainingPosCal] consider 1 rank data
8382 12:43:52.119953 u2DelayCellTimex100 = 258/100 ps
8383 12:43:52.123713 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8384 12:43:52.130127 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8385 12:43:52.133482 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8386 12:43:52.136930 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8387 12:43:52.140003 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8388 12:43:52.143189 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8389 12:43:52.143271
8390 12:43:52.146610 CA PerBit enable=1, Macro0, CA PI delay=36
8391 12:43:52.146692
8392 12:43:52.149888 [CBTSetCACLKResult] CA Dly = 36
8393 12:43:52.153114 CS Dly: 9 (0~40)
8394 12:43:52.156467 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8395 12:43:52.160305 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8396 12:43:52.160386 ==
8397 12:43:52.163197 Dram Type= 6, Freq= 0, CH_1, rank 1
8398 12:43:52.166317 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8399 12:43:52.169592 ==
8400 12:43:52.172822 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8401 12:43:52.176247 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8402 12:43:52.182741 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8403 12:43:52.186212 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8404 12:43:52.196719 [CA 0] Center 42 (13~71) winsize 59
8405 12:43:52.200077 [CA 1] Center 42 (13~72) winsize 60
8406 12:43:52.202999 [CA 2] Center 37 (8~67) winsize 60
8407 12:43:52.206393 [CA 3] Center 36 (7~66) winsize 60
8408 12:43:52.209811 [CA 4] Center 38 (8~68) winsize 61
8409 12:43:52.213129 [CA 5] Center 37 (7~67) winsize 61
8410 12:43:52.213211
8411 12:43:52.216519 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8412 12:43:52.216623
8413 12:43:52.219782 [CATrainingPosCal] consider 2 rank data
8414 12:43:52.223274 u2DelayCellTimex100 = 258/100 ps
8415 12:43:52.226244 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8416 12:43:52.233041 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8417 12:43:52.236507 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8418 12:43:52.239779 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8419 12:43:52.242878 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8420 12:43:52.246317 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8421 12:43:52.246400
8422 12:43:52.249414 CA PerBit enable=1, Macro0, CA PI delay=36
8423 12:43:52.249554
8424 12:43:52.252806 [CBTSetCACLKResult] CA Dly = 36
8425 12:43:52.256123 CS Dly: 10 (0~43)
8426 12:43:52.259393 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8427 12:43:52.262794 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8428 12:43:52.262878
8429 12:43:52.266260 ----->DramcWriteLeveling(PI) begin...
8430 12:43:52.266343 ==
8431 12:43:52.269360 Dram Type= 6, Freq= 0, CH_1, rank 0
8432 12:43:52.275968 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8433 12:43:52.276052 ==
8434 12:43:52.279522 Write leveling (Byte 0): 24 => 24
8435 12:43:52.279604 Write leveling (Byte 1): 28 => 28
8436 12:43:52.282798 DramcWriteLeveling(PI) end<-----
8437 12:43:52.282881
8438 12:43:52.282946 ==
8439 12:43:52.286283 Dram Type= 6, Freq= 0, CH_1, rank 0
8440 12:43:52.292607 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8441 12:43:52.292691 ==
8442 12:43:52.295746 [Gating] SW mode calibration
8443 12:43:52.302399 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8444 12:43:52.305853 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8445 12:43:52.312358 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8446 12:43:52.315922 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8447 12:43:52.319170 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8448 12:43:52.325654 1 4 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8449 12:43:52.328982 1 4 16 | B1->B0 | 3434 3433 | 1 1 | (1 1) (0 0)
8450 12:43:52.332516 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8451 12:43:52.339163 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8452 12:43:52.342351 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8453 12:43:52.345795 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8454 12:43:52.352502 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8455 12:43:52.355671 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8456 12:43:52.359020 1 5 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8457 12:43:52.365601 1 5 16 | B1->B0 | 2525 2424 | 0 0 | (1 0) (1 0)
8458 12:43:52.368789 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8459 12:43:52.372161 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8460 12:43:52.378801 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8461 12:43:52.382171 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8462 12:43:52.385649 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8463 12:43:52.391986 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8464 12:43:52.395373 1 6 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8465 12:43:52.398612 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8466 12:43:52.401984 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8467 12:43:52.408799 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8468 12:43:52.412224 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8469 12:43:52.415368 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8470 12:43:52.422104 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8471 12:43:52.425378 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8472 12:43:52.428570 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8473 12:43:52.435194 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8474 12:43:52.438389 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8475 12:43:52.441819 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8476 12:43:52.448681 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8477 12:43:52.452005 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8478 12:43:52.454992 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8479 12:43:52.461676 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8480 12:43:52.465238 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8481 12:43:52.468525 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8482 12:43:52.475045 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8483 12:43:52.478072 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8484 12:43:52.481678 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8485 12:43:52.488248 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8486 12:43:52.491314 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8487 12:43:52.494619 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8488 12:43:52.501417 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8489 12:43:52.504598 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8490 12:43:52.507764 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8491 12:43:52.511201 Total UI for P1: 0, mck2ui 16
8492 12:43:52.514772 best dqsien dly found for B0: ( 1, 9, 16)
8493 12:43:52.517994 Total UI for P1: 0, mck2ui 16
8494 12:43:52.521146 best dqsien dly found for B1: ( 1, 9, 16)
8495 12:43:52.524451 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8496 12:43:52.527681 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8497 12:43:52.527764
8498 12:43:52.534552 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8499 12:43:52.537795 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8500 12:43:52.541222 [Gating] SW calibration Done
8501 12:43:52.541305 ==
8502 12:43:52.544299 Dram Type= 6, Freq= 0, CH_1, rank 0
8503 12:43:52.547599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8504 12:43:52.547683 ==
8505 12:43:52.547748 RX Vref Scan: 0
8506 12:43:52.547810
8507 12:43:52.550859 RX Vref 0 -> 0, step: 1
8508 12:43:52.550941
8509 12:43:52.554171 RX Delay 0 -> 252, step: 8
8510 12:43:52.557378 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8511 12:43:52.560744 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8512 12:43:52.567390 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8513 12:43:52.570963 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8514 12:43:52.573990 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8515 12:43:52.577415 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8516 12:43:52.580744 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8517 12:43:52.587481 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8518 12:43:52.590678 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8519 12:43:52.594204 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8520 12:43:52.597360 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8521 12:43:52.600842 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8522 12:43:52.607241 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8523 12:43:52.610697 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8524 12:43:52.614203 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8525 12:43:52.617261 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8526 12:43:52.617343 ==
8527 12:43:52.620717 Dram Type= 6, Freq= 0, CH_1, rank 0
8528 12:43:52.624181 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8529 12:43:52.627228 ==
8530 12:43:52.627310 DQS Delay:
8531 12:43:52.627376 DQS0 = 0, DQS1 = 0
8532 12:43:52.630739 DQM Delay:
8533 12:43:52.630825 DQM0 = 132, DQM1 = 126
8534 12:43:52.633818 DQ Delay:
8535 12:43:52.637223 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8536 12:43:52.640710 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8537 12:43:52.643828 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8538 12:43:52.647140 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8539 12:43:52.647254
8540 12:43:52.647318
8541 12:43:52.647378 ==
8542 12:43:52.650572 Dram Type= 6, Freq= 0, CH_1, rank 0
8543 12:43:52.653820 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8544 12:43:52.653903 ==
8545 12:43:52.657206
8546 12:43:52.657292
8547 12:43:52.657397 TX Vref Scan disable
8548 12:43:52.660372 == TX Byte 0 ==
8549 12:43:52.663820 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8550 12:43:52.667134 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8551 12:43:52.670301 == TX Byte 1 ==
8552 12:43:52.673760 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8553 12:43:52.677069 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8554 12:43:52.677152 ==
8555 12:43:52.680541 Dram Type= 6, Freq= 0, CH_1, rank 0
8556 12:43:52.686951 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8557 12:43:52.687034 ==
8558 12:43:52.698729
8559 12:43:52.702018 TX Vref early break, caculate TX vref
8560 12:43:52.705460 TX Vref=16, minBit 1, minWin=22, winSum=364
8561 12:43:52.708761 TX Vref=18, minBit 0, minWin=23, winSum=373
8562 12:43:52.712117 TX Vref=20, minBit 5, minWin=23, winSum=383
8563 12:43:52.715375 TX Vref=22, minBit 11, minWin=23, winSum=391
8564 12:43:52.718464 TX Vref=24, minBit 1, minWin=24, winSum=401
8565 12:43:52.725258 TX Vref=26, minBit 0, minWin=25, winSum=413
8566 12:43:52.728617 TX Vref=28, minBit 0, minWin=25, winSum=420
8567 12:43:52.731997 TX Vref=30, minBit 6, minWin=24, winSum=412
8568 12:43:52.735201 TX Vref=32, minBit 0, minWin=24, winSum=403
8569 12:43:52.738277 TX Vref=34, minBit 0, minWin=23, winSum=395
8570 12:43:52.745196 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 28
8571 12:43:52.745279
8572 12:43:52.748574 Final TX Range 0 Vref 28
8573 12:43:52.748657
8574 12:43:52.748722 ==
8575 12:43:52.751730 Dram Type= 6, Freq= 0, CH_1, rank 0
8576 12:43:52.755192 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8577 12:43:52.755275 ==
8578 12:43:52.755340
8579 12:43:52.755400
8580 12:43:52.758201 TX Vref Scan disable
8581 12:43:52.764742 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8582 12:43:52.764825 == TX Byte 0 ==
8583 12:43:52.768258 u2DelayCellOfst[0]=22 cells (6 PI)
8584 12:43:52.771370 u2DelayCellOfst[1]=15 cells (4 PI)
8585 12:43:52.774672 u2DelayCellOfst[2]=0 cells (0 PI)
8586 12:43:52.778317 u2DelayCellOfst[3]=7 cells (2 PI)
8587 12:43:52.781431 u2DelayCellOfst[4]=11 cells (3 PI)
8588 12:43:52.784681 u2DelayCellOfst[5]=22 cells (6 PI)
8589 12:43:52.788049 u2DelayCellOfst[6]=26 cells (7 PI)
8590 12:43:52.791346 u2DelayCellOfst[7]=7 cells (2 PI)
8591 12:43:52.794675 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8592 12:43:52.798151 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8593 12:43:52.801427 == TX Byte 1 ==
8594 12:43:52.804580 u2DelayCellOfst[8]=0 cells (0 PI)
8595 12:43:52.804663 u2DelayCellOfst[9]=7 cells (2 PI)
8596 12:43:52.807982 u2DelayCellOfst[10]=15 cells (4 PI)
8597 12:43:52.811689 u2DelayCellOfst[11]=7 cells (2 PI)
8598 12:43:52.814621 u2DelayCellOfst[12]=18 cells (5 PI)
8599 12:43:52.818113 u2DelayCellOfst[13]=22 cells (6 PI)
8600 12:43:52.821410 u2DelayCellOfst[14]=22 cells (6 PI)
8601 12:43:52.824711 u2DelayCellOfst[15]=22 cells (6 PI)
8602 12:43:52.828034 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8603 12:43:52.834537 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8604 12:43:52.834620 DramC Write-DBI on
8605 12:43:52.834686 ==
8606 12:43:52.837880 Dram Type= 6, Freq= 0, CH_1, rank 0
8607 12:43:52.844434 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8608 12:43:52.844517 ==
8609 12:43:52.844583
8610 12:43:52.844642
8611 12:43:52.844699 TX Vref Scan disable
8612 12:43:52.848127 == TX Byte 0 ==
8613 12:43:52.851595 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8614 12:43:52.854878 == TX Byte 1 ==
8615 12:43:52.857978 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8616 12:43:52.861441 DramC Write-DBI off
8617 12:43:52.861571
8618 12:43:52.861637 [DATLAT]
8619 12:43:52.861697 Freq=1600, CH1 RK0
8620 12:43:52.861756
8621 12:43:52.864936 DATLAT Default: 0xf
8622 12:43:52.865018 0, 0xFFFF, sum = 0
8623 12:43:52.867973 1, 0xFFFF, sum = 0
8624 12:43:52.871440 2, 0xFFFF, sum = 0
8625 12:43:52.871523 3, 0xFFFF, sum = 0
8626 12:43:52.874505 4, 0xFFFF, sum = 0
8627 12:43:52.874590 5, 0xFFFF, sum = 0
8628 12:43:52.877991 6, 0xFFFF, sum = 0
8629 12:43:52.878074 7, 0xFFFF, sum = 0
8630 12:43:52.881324 8, 0xFFFF, sum = 0
8631 12:43:52.881434 9, 0xFFFF, sum = 0
8632 12:43:52.884592 10, 0xFFFF, sum = 0
8633 12:43:52.884676 11, 0xFFFF, sum = 0
8634 12:43:52.887882 12, 0xFFFF, sum = 0
8635 12:43:52.887966 13, 0x8FFF, sum = 0
8636 12:43:52.891181 14, 0x0, sum = 1
8637 12:43:52.891288 15, 0x0, sum = 2
8638 12:43:52.894452 16, 0x0, sum = 3
8639 12:43:52.894563 17, 0x0, sum = 4
8640 12:43:52.897857 best_step = 15
8641 12:43:52.897938
8642 12:43:52.898001 ==
8643 12:43:52.901079 Dram Type= 6, Freq= 0, CH_1, rank 0
8644 12:43:52.904359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8645 12:43:52.904440 ==
8646 12:43:52.907746 RX Vref Scan: 1
8647 12:43:52.907827
8648 12:43:52.907890 Set Vref Range= 24 -> 127
8649 12:43:52.907949
8650 12:43:52.911233 RX Vref 24 -> 127, step: 1
8651 12:43:52.911314
8652 12:43:52.914392 RX Delay 11 -> 252, step: 4
8653 12:43:52.914473
8654 12:43:52.917882 Set Vref, RX VrefLevel [Byte0]: 24
8655 12:43:52.920986 [Byte1]: 24
8656 12:43:52.921066
8657 12:43:52.924410 Set Vref, RX VrefLevel [Byte0]: 25
8658 12:43:52.927565 [Byte1]: 25
8659 12:43:52.931087
8660 12:43:52.931168 Set Vref, RX VrefLevel [Byte0]: 26
8661 12:43:52.934166 [Byte1]: 26
8662 12:43:52.938664
8663 12:43:52.938747 Set Vref, RX VrefLevel [Byte0]: 27
8664 12:43:52.941911 [Byte1]: 27
8665 12:43:52.946227
8666 12:43:52.946306 Set Vref, RX VrefLevel [Byte0]: 28
8667 12:43:52.949472 [Byte1]: 28
8668 12:43:52.953721
8669 12:43:52.953801 Set Vref, RX VrefLevel [Byte0]: 29
8670 12:43:52.957053 [Byte1]: 29
8671 12:43:52.961437
8672 12:43:52.961564 Set Vref, RX VrefLevel [Byte0]: 30
8673 12:43:52.964748 [Byte1]: 30
8674 12:43:52.969032
8675 12:43:52.969138 Set Vref, RX VrefLevel [Byte0]: 31
8676 12:43:52.972461 [Byte1]: 31
8677 12:43:52.976538
8678 12:43:52.976618 Set Vref, RX VrefLevel [Byte0]: 32
8679 12:43:52.979902 [Byte1]: 32
8680 12:43:52.984250
8681 12:43:52.984331 Set Vref, RX VrefLevel [Byte0]: 33
8682 12:43:52.987467 [Byte1]: 33
8683 12:43:52.991797
8684 12:43:52.991877 Set Vref, RX VrefLevel [Byte0]: 34
8685 12:43:52.995078 [Byte1]: 34
8686 12:43:52.999474
8687 12:43:52.999555 Set Vref, RX VrefLevel [Byte0]: 35
8688 12:43:53.002740 [Byte1]: 35
8689 12:43:53.007140
8690 12:43:53.007221 Set Vref, RX VrefLevel [Byte0]: 36
8691 12:43:53.010632 [Byte1]: 36
8692 12:43:53.014761
8693 12:43:53.014843 Set Vref, RX VrefLevel [Byte0]: 37
8694 12:43:53.018108 [Byte1]: 37
8695 12:43:53.022501
8696 12:43:53.022608 Set Vref, RX VrefLevel [Byte0]: 38
8697 12:43:53.025602 [Byte1]: 38
8698 12:43:53.029864
8699 12:43:53.029967 Set Vref, RX VrefLevel [Byte0]: 39
8700 12:43:53.033059 [Byte1]: 39
8701 12:43:53.037556
8702 12:43:53.037630 Set Vref, RX VrefLevel [Byte0]: 40
8703 12:43:53.040857 [Byte1]: 40
8704 12:43:53.045106
8705 12:43:53.045179 Set Vref, RX VrefLevel [Byte0]: 41
8706 12:43:53.048828 [Byte1]: 41
8707 12:43:53.052754
8708 12:43:53.052826 Set Vref, RX VrefLevel [Byte0]: 42
8709 12:43:53.056054 [Byte1]: 42
8710 12:43:53.060483
8711 12:43:53.060565 Set Vref, RX VrefLevel [Byte0]: 43
8712 12:43:53.063523 [Byte1]: 43
8713 12:43:53.067972
8714 12:43:53.068054 Set Vref, RX VrefLevel [Byte0]: 44
8715 12:43:53.071396 [Byte1]: 44
8716 12:43:53.075550
8717 12:43:53.075632 Set Vref, RX VrefLevel [Byte0]: 45
8718 12:43:53.079019 [Byte1]: 45
8719 12:43:53.083187
8720 12:43:53.083269 Set Vref, RX VrefLevel [Byte0]: 46
8721 12:43:53.086663 [Byte1]: 46
8722 12:43:53.090855
8723 12:43:53.090942 Set Vref, RX VrefLevel [Byte0]: 47
8724 12:43:53.093974 [Byte1]: 47
8725 12:43:53.098564
8726 12:43:53.098646 Set Vref, RX VrefLevel [Byte0]: 48
8727 12:43:53.101556 [Byte1]: 48
8728 12:43:53.106113
8729 12:43:53.106190 Set Vref, RX VrefLevel [Byte0]: 49
8730 12:43:53.109675 [Byte1]: 49
8731 12:43:53.113774
8732 12:43:53.113846 Set Vref, RX VrefLevel [Byte0]: 50
8733 12:43:53.116834 [Byte1]: 50
8734 12:43:53.121428
8735 12:43:53.121526 Set Vref, RX VrefLevel [Byte0]: 51
8736 12:43:53.124407 [Byte1]: 51
8737 12:43:53.128971
8738 12:43:53.129069 Set Vref, RX VrefLevel [Byte0]: 52
8739 12:43:53.132113 [Byte1]: 52
8740 12:43:53.136335
8741 12:43:53.136432 Set Vref, RX VrefLevel [Byte0]: 53
8742 12:43:53.139991 [Byte1]: 53
8743 12:43:53.144181
8744 12:43:53.144252 Set Vref, RX VrefLevel [Byte0]: 54
8745 12:43:53.147573 [Byte1]: 54
8746 12:43:53.151732
8747 12:43:53.151829 Set Vref, RX VrefLevel [Byte0]: 55
8748 12:43:53.155382 [Byte1]: 55
8749 12:43:53.159185
8750 12:43:53.159266 Set Vref, RX VrefLevel [Byte0]: 56
8751 12:43:53.162703 [Byte1]: 56
8752 12:43:53.166949
8753 12:43:53.167025 Set Vref, RX VrefLevel [Byte0]: 57
8754 12:43:53.170353 [Byte1]: 57
8755 12:43:53.174541
8756 12:43:53.174622 Set Vref, RX VrefLevel [Byte0]: 58
8757 12:43:53.177762 [Byte1]: 58
8758 12:43:53.182101
8759 12:43:53.182183 Set Vref, RX VrefLevel [Byte0]: 59
8760 12:43:53.185528 [Byte1]: 59
8761 12:43:53.189875
8762 12:43:53.189956 Set Vref, RX VrefLevel [Byte0]: 60
8763 12:43:53.192981 [Byte1]: 60
8764 12:43:53.197397
8765 12:43:53.197538 Set Vref, RX VrefLevel [Byte0]: 61
8766 12:43:53.200509 [Byte1]: 61
8767 12:43:53.205111
8768 12:43:53.205206 Set Vref, RX VrefLevel [Byte0]: 62
8769 12:43:53.208662 [Byte1]: 62
8770 12:43:53.212861
8771 12:43:53.212943 Set Vref, RX VrefLevel [Byte0]: 63
8772 12:43:53.216143 [Byte1]: 63
8773 12:43:53.220410
8774 12:43:53.220491 Set Vref, RX VrefLevel [Byte0]: 64
8775 12:43:53.223481 [Byte1]: 64
8776 12:43:53.228136
8777 12:43:53.228217 Set Vref, RX VrefLevel [Byte0]: 65
8778 12:43:53.231267 [Byte1]: 65
8779 12:43:53.235532
8780 12:43:53.235614 Set Vref, RX VrefLevel [Byte0]: 66
8781 12:43:53.239028 [Byte1]: 66
8782 12:43:53.243198
8783 12:43:53.243280 Set Vref, RX VrefLevel [Byte0]: 67
8784 12:43:53.246244 [Byte1]: 67
8785 12:43:53.250811
8786 12:43:53.250896 Set Vref, RX VrefLevel [Byte0]: 68
8787 12:43:53.253875 [Byte1]: 68
8788 12:43:53.258232
8789 12:43:53.258313 Set Vref, RX VrefLevel [Byte0]: 69
8790 12:43:53.262047 [Byte1]: 69
8791 12:43:53.266036
8792 12:43:53.266119 Set Vref, RX VrefLevel [Byte0]: 70
8793 12:43:53.269096 [Byte1]: 70
8794 12:43:53.273670
8795 12:43:53.273752 Final RX Vref Byte 0 = 58 to rank0
8796 12:43:53.277003 Final RX Vref Byte 1 = 54 to rank0
8797 12:43:53.280069 Final RX Vref Byte 0 = 58 to rank1
8798 12:43:53.283521 Final RX Vref Byte 1 = 54 to rank1==
8799 12:43:53.286717 Dram Type= 6, Freq= 0, CH_1, rank 0
8800 12:43:53.293387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8801 12:43:53.293518 ==
8802 12:43:53.293602 DQS Delay:
8803 12:43:53.296811 DQS0 = 0, DQS1 = 0
8804 12:43:53.296893 DQM Delay:
8805 12:43:53.296958 DQM0 = 130, DQM1 = 123
8806 12:43:53.300008 DQ Delay:
8807 12:43:53.303205 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =126
8808 12:43:53.306553 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =128
8809 12:43:53.310135 DQ8 =110, DQ9 =114, DQ10 =122, DQ11 =116
8810 12:43:53.313321 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8811 12:43:53.313456
8812 12:43:53.313554
8813 12:43:53.313616
8814 12:43:53.316682 [DramC_TX_OE_Calibration] TA2
8815 12:43:53.319714 Original DQ_B0 (3 6) =30, OEN = 27
8816 12:43:53.323276 Original DQ_B1 (3 6) =30, OEN = 27
8817 12:43:53.326717 24, 0x0, End_B0=24 End_B1=24
8818 12:43:53.326801 25, 0x0, End_B0=25 End_B1=25
8819 12:43:53.330002 26, 0x0, End_B0=26 End_B1=26
8820 12:43:53.333036 27, 0x0, End_B0=27 End_B1=27
8821 12:43:53.336321 28, 0x0, End_B0=28 End_B1=28
8822 12:43:53.339671 29, 0x0, End_B0=29 End_B1=29
8823 12:43:53.339754 30, 0x0, End_B0=30 End_B1=30
8824 12:43:53.342968 31, 0x4141, End_B0=30 End_B1=30
8825 12:43:53.346684 Byte0 end_step=30 best_step=27
8826 12:43:53.349630 Byte1 end_step=30 best_step=27
8827 12:43:53.352982 Byte0 TX OE(2T, 0.5T) = (3, 3)
8828 12:43:53.356581 Byte1 TX OE(2T, 0.5T) = (3, 3)
8829 12:43:53.356663
8830 12:43:53.356727
8831 12:43:53.362837 [DQSOSCAuto] RK0, (LSB)MR18= 0x90d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
8832 12:43:53.366193 CH1 RK0: MR19=303, MR18=90D
8833 12:43:53.373024 CH1_RK0: MR19=0x303, MR18=0x90D, DQSOSC=403, MR23=63, INC=22, DEC=15
8834 12:43:53.373107
8835 12:43:53.376316 ----->DramcWriteLeveling(PI) begin...
8836 12:43:53.376400 ==
8837 12:43:53.379664 Dram Type= 6, Freq= 0, CH_1, rank 1
8838 12:43:53.382816 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8839 12:43:53.382899 ==
8840 12:43:53.386508 Write leveling (Byte 0): 25 => 25
8841 12:43:53.389744 Write leveling (Byte 1): 28 => 28
8842 12:43:53.392805 DramcWriteLeveling(PI) end<-----
8843 12:43:53.392912
8844 12:43:53.393015 ==
8845 12:43:53.396201 Dram Type= 6, Freq= 0, CH_1, rank 1
8846 12:43:53.399656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8847 12:43:53.399733 ==
8848 12:43:53.403090 [Gating] SW mode calibration
8849 12:43:53.409402 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8850 12:43:53.416006 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8851 12:43:53.419473 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8852 12:43:53.422687 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8853 12:43:53.429373 1 4 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8854 12:43:53.432490 1 4 12 | B1->B0 | 2d2c 3434 | 1 1 | (0 0) (1 1)
8855 12:43:53.435928 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8856 12:43:53.442851 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8857 12:43:53.446175 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8858 12:43:53.449188 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8859 12:43:53.456237 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8860 12:43:53.459436 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8861 12:43:53.462519 1 5 8 | B1->B0 | 3333 2929 | 1 1 | (1 0) (1 0)
8862 12:43:53.469259 1 5 12 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
8863 12:43:53.472370 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8864 12:43:53.475881 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8865 12:43:53.482490 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8866 12:43:53.486012 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8867 12:43:53.488976 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8868 12:43:53.495702 1 6 4 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
8869 12:43:53.498793 1 6 8 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
8870 12:43:53.502167 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8871 12:43:53.509037 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8872 12:43:53.512511 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8873 12:43:53.515646 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8874 12:43:53.521952 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8875 12:43:53.525427 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8876 12:43:53.528538 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8877 12:43:53.535112 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8878 12:43:53.538416 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8879 12:43:53.541900 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8880 12:43:53.548699 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 12:43:53.551819 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8882 12:43:53.555347 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8883 12:43:53.561983 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8884 12:43:53.565372 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8885 12:43:53.568587 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8886 12:43:53.572014 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8887 12:43:53.578642 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8888 12:43:53.581984 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8889 12:43:53.585126 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8890 12:43:53.591852 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8891 12:43:53.595236 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8892 12:43:53.598218 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8893 12:43:53.605137 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8894 12:43:53.608487 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8895 12:43:53.611601 Total UI for P1: 0, mck2ui 16
8896 12:43:53.615010 best dqsien dly found for B0: ( 1, 9, 8)
8897 12:43:53.618337 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8898 12:43:53.621733 Total UI for P1: 0, mck2ui 16
8899 12:43:53.625051 best dqsien dly found for B1: ( 1, 9, 10)
8900 12:43:53.628187 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8901 12:43:53.631616 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8902 12:43:53.634654
8903 12:43:53.638110 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8904 12:43:53.641175 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8905 12:43:53.644597 [Gating] SW calibration Done
8906 12:43:53.644678 ==
8907 12:43:53.648026 Dram Type= 6, Freq= 0, CH_1, rank 1
8908 12:43:53.651147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8909 12:43:53.651229 ==
8910 12:43:53.654458 RX Vref Scan: 0
8911 12:43:53.654538
8912 12:43:53.654601 RX Vref 0 -> 0, step: 1
8913 12:43:53.654663
8914 12:43:53.657796 RX Delay 0 -> 252, step: 8
8915 12:43:53.661030 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8916 12:43:53.664480 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8917 12:43:53.671004 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8918 12:43:53.674313 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8919 12:43:53.678031 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8920 12:43:53.681023 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8921 12:43:53.684296 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8922 12:43:53.691061 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8923 12:43:53.694405 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8924 12:43:53.697505 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8925 12:43:53.700843 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8926 12:43:53.704319 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8927 12:43:53.710804 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8928 12:43:53.714123 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8929 12:43:53.717197 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8930 12:43:53.720626 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8931 12:43:53.720700 ==
8932 12:43:53.723963 Dram Type= 6, Freq= 0, CH_1, rank 1
8933 12:43:53.730707 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8934 12:43:53.730789 ==
8935 12:43:53.730853 DQS Delay:
8936 12:43:53.733930 DQS0 = 0, DQS1 = 0
8937 12:43:53.734011 DQM Delay:
8938 12:43:53.737393 DQM0 = 133, DQM1 = 128
8939 12:43:53.737501 DQ Delay:
8940 12:43:53.740526 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8941 12:43:53.744081 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =131
8942 12:43:53.747009 DQ8 =115, DQ9 =115, DQ10 =135, DQ11 =123
8943 12:43:53.750428 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8944 12:43:53.750509
8945 12:43:53.750572
8946 12:43:53.750630 ==
8947 12:43:53.753610 Dram Type= 6, Freq= 0, CH_1, rank 1
8948 12:43:53.760046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8949 12:43:53.760127 ==
8950 12:43:53.760190
8951 12:43:53.760249
8952 12:43:53.760306 TX Vref Scan disable
8953 12:43:53.763665 == TX Byte 0 ==
8954 12:43:53.767051 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8955 12:43:53.773931 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8956 12:43:53.774012 == TX Byte 1 ==
8957 12:43:53.777081 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8958 12:43:53.783560 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8959 12:43:53.783642 ==
8960 12:43:53.787063 Dram Type= 6, Freq= 0, CH_1, rank 1
8961 12:43:53.790750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8962 12:43:53.790832 ==
8963 12:43:53.802847
8964 12:43:53.805904 TX Vref early break, caculate TX vref
8965 12:43:53.809229 TX Vref=16, minBit 0, minWin=23, winSum=385
8966 12:43:53.812580 TX Vref=18, minBit 0, minWin=23, winSum=389
8967 12:43:53.815970 TX Vref=20, minBit 0, minWin=23, winSum=399
8968 12:43:53.819361 TX Vref=22, minBit 0, minWin=24, winSum=406
8969 12:43:53.822731 TX Vref=24, minBit 5, minWin=24, winSum=418
8970 12:43:53.829656 TX Vref=26, minBit 0, minWin=25, winSum=421
8971 12:43:53.832343 TX Vref=28, minBit 0, minWin=26, winSum=428
8972 12:43:53.835866 TX Vref=30, minBit 1, minWin=25, winSum=423
8973 12:43:53.839390 TX Vref=32, minBit 1, minWin=24, winSum=412
8974 12:43:53.842597 TX Vref=34, minBit 0, minWin=24, winSum=403
8975 12:43:53.849108 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 28
8976 12:43:53.849189
8977 12:43:53.852205 Final TX Range 0 Vref 28
8978 12:43:53.852286
8979 12:43:53.852348 ==
8980 12:43:53.855631 Dram Type= 6, Freq= 0, CH_1, rank 1
8981 12:43:53.859019 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8982 12:43:53.859100 ==
8983 12:43:53.859163
8984 12:43:53.859222
8985 12:43:53.862080 TX Vref Scan disable
8986 12:43:53.869020 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8987 12:43:53.869103 == TX Byte 0 ==
8988 12:43:53.872077 u2DelayCellOfst[0]=15 cells (4 PI)
8989 12:43:53.875562 u2DelayCellOfst[1]=11 cells (3 PI)
8990 12:43:53.878553 u2DelayCellOfst[2]=0 cells (0 PI)
8991 12:43:53.882062 u2DelayCellOfst[3]=3 cells (1 PI)
8992 12:43:53.885353 u2DelayCellOfst[4]=7 cells (2 PI)
8993 12:43:53.888882 u2DelayCellOfst[5]=22 cells (6 PI)
8994 12:43:53.891866 u2DelayCellOfst[6]=18 cells (5 PI)
8995 12:43:53.895417 u2DelayCellOfst[7]=3 cells (1 PI)
8996 12:43:53.898490 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8997 12:43:53.901785 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8998 12:43:53.905081 == TX Byte 1 ==
8999 12:43:53.908658 u2DelayCellOfst[8]=0 cells (0 PI)
9000 12:43:53.908739 u2DelayCellOfst[9]=7 cells (2 PI)
9001 12:43:53.911678 u2DelayCellOfst[10]=15 cells (4 PI)
9002 12:43:53.915168 u2DelayCellOfst[11]=7 cells (2 PI)
9003 12:43:53.918211 u2DelayCellOfst[12]=18 cells (5 PI)
9004 12:43:53.921430 u2DelayCellOfst[13]=18 cells (5 PI)
9005 12:43:53.925006 u2DelayCellOfst[14]=22 cells (6 PI)
9006 12:43:53.928306 u2DelayCellOfst[15]=18 cells (5 PI)
9007 12:43:53.931893 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
9008 12:43:53.938392 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
9009 12:43:53.938500 DramC Write-DBI on
9010 12:43:53.938591 ==
9011 12:43:53.941585 Dram Type= 6, Freq= 0, CH_1, rank 1
9012 12:43:53.948153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9013 12:43:53.948234 ==
9014 12:43:53.948298
9015 12:43:53.948356
9016 12:43:53.948424 TX Vref Scan disable
9017 12:43:53.952223 == TX Byte 0 ==
9018 12:43:53.955586 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9019 12:43:53.958732 == TX Byte 1 ==
9020 12:43:53.961859 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
9021 12:43:53.965305 DramC Write-DBI off
9022 12:43:53.965416
9023 12:43:53.965554 [DATLAT]
9024 12:43:53.965618 Freq=1600, CH1 RK1
9025 12:43:53.965677
9026 12:43:53.968562 DATLAT Default: 0xf
9027 12:43:53.968650 0, 0xFFFF, sum = 0
9028 12:43:53.971707 1, 0xFFFF, sum = 0
9029 12:43:53.975077 2, 0xFFFF, sum = 0
9030 12:43:53.975159 3, 0xFFFF, sum = 0
9031 12:43:53.978439 4, 0xFFFF, sum = 0
9032 12:43:53.978521 5, 0xFFFF, sum = 0
9033 12:43:53.981631 6, 0xFFFF, sum = 0
9034 12:43:53.981714 7, 0xFFFF, sum = 0
9035 12:43:53.985192 8, 0xFFFF, sum = 0
9036 12:43:53.985315 9, 0xFFFF, sum = 0
9037 12:43:53.988454 10, 0xFFFF, sum = 0
9038 12:43:53.988547 11, 0xFFFF, sum = 0
9039 12:43:53.991423 12, 0xFFFF, sum = 0
9040 12:43:53.991505 13, 0x8FFF, sum = 0
9041 12:43:53.994774 14, 0x0, sum = 1
9042 12:43:53.994856 15, 0x0, sum = 2
9043 12:43:53.998343 16, 0x0, sum = 3
9044 12:43:53.998452 17, 0x0, sum = 4
9045 12:43:54.001393 best_step = 15
9046 12:43:54.001505
9047 12:43:54.001571 ==
9048 12:43:54.004799 Dram Type= 6, Freq= 0, CH_1, rank 1
9049 12:43:54.008091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9050 12:43:54.008197 ==
9051 12:43:54.011311 RX Vref Scan: 0
9052 12:43:54.011401
9053 12:43:54.011465 RX Vref 0 -> 0, step: 1
9054 12:43:54.011525
9055 12:43:54.014751 RX Delay 11 -> 252, step: 4
9056 12:43:54.021349 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
9057 12:43:54.024856 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9058 12:43:54.028101 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9059 12:43:54.031199 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9060 12:43:54.034533 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
9061 12:43:54.037773 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
9062 12:43:54.044673 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
9063 12:43:54.047980 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
9064 12:43:54.051000 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
9065 12:43:54.054509 iDelay=195, Bit 9, Center 114 (63 ~ 166) 104
9066 12:43:54.061099 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9067 12:43:54.064295 iDelay=195, Bit 11, Center 118 (63 ~ 174) 112
9068 12:43:54.067819 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9069 12:43:54.070968 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9070 12:43:54.074572 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
9071 12:43:54.081126 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9072 12:43:54.081207 ==
9073 12:43:54.084411 Dram Type= 6, Freq= 0, CH_1, rank 1
9074 12:43:54.087800 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9075 12:43:54.087882 ==
9076 12:43:54.087946 DQS Delay:
9077 12:43:54.090938 DQS0 = 0, DQS1 = 0
9078 12:43:54.091023 DQM Delay:
9079 12:43:54.094462 DQM0 = 130, DQM1 = 125
9080 12:43:54.094542 DQ Delay:
9081 12:43:54.097696 DQ0 =134, DQ1 =130, DQ2 =118, DQ3 =126
9082 12:43:54.101044 DQ4 =126, DQ5 =140, DQ6 =142, DQ7 =128
9083 12:43:54.104220 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =118
9084 12:43:54.107593 DQ12 =132, DQ13 =134, DQ14 =132, DQ15 =136
9085 12:43:54.107674
9086 12:43:54.107737
9087 12:43:54.111260
9088 12:43:54.111340 [DramC_TX_OE_Calibration] TA2
9089 12:43:54.114023 Original DQ_B0 (3 6) =30, OEN = 27
9090 12:43:54.117395 Original DQ_B1 (3 6) =30, OEN = 27
9091 12:43:54.121118 24, 0x0, End_B0=24 End_B1=24
9092 12:43:54.124172 25, 0x0, End_B0=25 End_B1=25
9093 12:43:54.127563 26, 0x0, End_B0=26 End_B1=26
9094 12:43:54.127672 27, 0x0, End_B0=27 End_B1=27
9095 12:43:54.130846 28, 0x0, End_B0=28 End_B1=28
9096 12:43:54.134238 29, 0x0, End_B0=29 End_B1=29
9097 12:43:54.137469 30, 0x0, End_B0=30 End_B1=30
9098 12:43:54.140995 31, 0x4141, End_B0=30 End_B1=30
9099 12:43:54.141076 Byte0 end_step=30 best_step=27
9100 12:43:54.144126 Byte1 end_step=30 best_step=27
9101 12:43:54.147546 Byte0 TX OE(2T, 0.5T) = (3, 3)
9102 12:43:54.150519 Byte1 TX OE(2T, 0.5T) = (3, 3)
9103 12:43:54.150603
9104 12:43:54.150666
9105 12:43:54.157112 [DQSOSCAuto] RK1, (LSB)MR18= 0x101c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
9106 12:43:54.160620 CH1 RK1: MR19=303, MR18=101C
9107 12:43:54.167059 CH1_RK1: MR19=0x303, MR18=0x101C, DQSOSC=395, MR23=63, INC=23, DEC=15
9108 12:43:54.170546 [RxdqsGatingPostProcess] freq 1600
9109 12:43:54.176940 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9110 12:43:54.180500 best DQS0 dly(2T, 0.5T) = (1, 1)
9111 12:43:54.180581 best DQS1 dly(2T, 0.5T) = (1, 1)
9112 12:43:54.183899 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9113 12:43:54.187050 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9114 12:43:54.190461 best DQS0 dly(2T, 0.5T) = (1, 1)
9115 12:43:54.193878 best DQS1 dly(2T, 0.5T) = (1, 1)
9116 12:43:54.197070 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9117 12:43:54.200381 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9118 12:43:54.203827 Pre-setting of DQS Precalculation
9119 12:43:54.207455 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9120 12:43:54.216815 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9121 12:43:54.223423 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9122 12:43:54.223505
9123 12:43:54.223568
9124 12:43:54.226828 [Calibration Summary] 3200 Mbps
9125 12:43:54.226909 CH 0, Rank 0
9126 12:43:54.229971 SW Impedance : PASS
9127 12:43:54.233464 DUTY Scan : NO K
9128 12:43:54.233553 ZQ Calibration : PASS
9129 12:43:54.236748 Jitter Meter : NO K
9130 12:43:54.236828 CBT Training : PASS
9131 12:43:54.240177 Write leveling : PASS
9132 12:43:54.243485 RX DQS gating : PASS
9133 12:43:54.243567 RX DQ/DQS(RDDQC) : PASS
9134 12:43:54.246567 TX DQ/DQS : PASS
9135 12:43:54.249974 RX DATLAT : PASS
9136 12:43:54.250055 RX DQ/DQS(Engine): PASS
9137 12:43:54.253363 TX OE : PASS
9138 12:43:54.253470 All Pass.
9139 12:43:54.253545
9140 12:43:54.256833 CH 0, Rank 1
9141 12:43:54.256913 SW Impedance : PASS
9142 12:43:54.260027 DUTY Scan : NO K
9143 12:43:54.263425 ZQ Calibration : PASS
9144 12:43:54.263505 Jitter Meter : NO K
9145 12:43:54.266941 CBT Training : PASS
9146 12:43:54.270230 Write leveling : PASS
9147 12:43:54.270311 RX DQS gating : PASS
9148 12:43:54.273381 RX DQ/DQS(RDDQC) : PASS
9149 12:43:54.276533 TX DQ/DQS : PASS
9150 12:43:54.276613 RX DATLAT : PASS
9151 12:43:54.279982 RX DQ/DQS(Engine): PASS
9152 12:43:54.280063 TX OE : PASS
9153 12:43:54.283343 All Pass.
9154 12:43:54.283423
9155 12:43:54.283486 CH 1, Rank 0
9156 12:43:54.286698 SW Impedance : PASS
9157 12:43:54.286778 DUTY Scan : NO K
9158 12:43:54.289831 ZQ Calibration : PASS
9159 12:43:54.293365 Jitter Meter : NO K
9160 12:43:54.293472 CBT Training : PASS
9161 12:43:54.296716 Write leveling : PASS
9162 12:43:54.300094 RX DQS gating : PASS
9163 12:43:54.300174 RX DQ/DQS(RDDQC) : PASS
9164 12:43:54.303415 TX DQ/DQS : PASS
9165 12:43:54.306638 RX DATLAT : PASS
9166 12:43:54.306720 RX DQ/DQS(Engine): PASS
9167 12:43:54.309718 TX OE : PASS
9168 12:43:54.309800 All Pass.
9169 12:43:54.309864
9170 12:43:54.313211 CH 1, Rank 1
9171 12:43:54.313293 SW Impedance : PASS
9172 12:43:54.316479 DUTY Scan : NO K
9173 12:43:54.319854 ZQ Calibration : PASS
9174 12:43:54.319937 Jitter Meter : NO K
9175 12:43:54.322793 CBT Training : PASS
9176 12:43:54.326357 Write leveling : PASS
9177 12:43:54.326439 RX DQS gating : PASS
9178 12:43:54.329725 RX DQ/DQS(RDDQC) : PASS
9179 12:43:54.333162 TX DQ/DQS : PASS
9180 12:43:54.333244 RX DATLAT : PASS
9181 12:43:54.336369 RX DQ/DQS(Engine): PASS
9182 12:43:54.336451 TX OE : PASS
9183 12:43:54.339742 All Pass.
9184 12:43:54.339824
9185 12:43:54.339889 DramC Write-DBI on
9186 12:43:54.342958 PER_BANK_REFRESH: Hybrid Mode
9187 12:43:54.346099 TX_TRACKING: ON
9188 12:43:54.352882 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9189 12:43:54.362755 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9190 12:43:54.369204 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9191 12:43:54.372808 [FAST_K] Save calibration result to emmc
9192 12:43:54.376091 sync common calibartion params.
9193 12:43:54.376173 sync cbt_mode0:1, 1:1
9194 12:43:54.379331 dram_init: ddr_geometry: 2
9195 12:43:54.382763 dram_init: ddr_geometry: 2
9196 12:43:54.385978 dram_init: ddr_geometry: 2
9197 12:43:54.386064 0:dram_rank_size:100000000
9198 12:43:54.389385 1:dram_rank_size:100000000
9199 12:43:54.395992 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9200 12:43:54.396075 DFS_SHUFFLE_HW_MODE: ON
9201 12:43:54.402578 dramc_set_vcore_voltage set vcore to 725000
9202 12:43:54.402660 Read voltage for 1600, 0
9203 12:43:54.406049 Vio18 = 0
9204 12:43:54.406131 Vcore = 725000
9205 12:43:54.406196 Vdram = 0
9206 12:43:54.409191 Vddq = 0
9207 12:43:54.409273 Vmddr = 0
9208 12:43:54.412613 switch to 3200 Mbps bootup
9209 12:43:54.412695 [DramcRunTimeConfig]
9210 12:43:54.412760 PHYPLL
9211 12:43:54.415704 DPM_CONTROL_AFTERK: ON
9212 12:43:54.419225 PER_BANK_REFRESH: ON
9213 12:43:54.419308 REFRESH_OVERHEAD_REDUCTION: ON
9214 12:43:54.422611 CMD_PICG_NEW_MODE: OFF
9215 12:43:54.425824 XRTWTW_NEW_MODE: ON
9216 12:43:54.425906 XRTRTR_NEW_MODE: ON
9217 12:43:54.429100 TX_TRACKING: ON
9218 12:43:54.429182 RDSEL_TRACKING: OFF
9219 12:43:54.432246 DQS Precalculation for DVFS: ON
9220 12:43:54.432328 RX_TRACKING: OFF
9221 12:43:54.435875 HW_GATING DBG: ON
9222 12:43:54.435957 ZQCS_ENABLE_LP4: ON
9223 12:43:54.439227 RX_PICG_NEW_MODE: ON
9224 12:43:54.442353 TX_PICG_NEW_MODE: ON
9225 12:43:54.442435 ENABLE_RX_DCM_DPHY: ON
9226 12:43:54.445707 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9227 12:43:54.448741 DUMMY_READ_FOR_TRACKING: OFF
9228 12:43:54.452515 !!! SPM_CONTROL_AFTERK: OFF
9229 12:43:54.452606 !!! SPM could not control APHY
9230 12:43:54.455750 IMPEDANCE_TRACKING: ON
9231 12:43:54.458862 TEMP_SENSOR: ON
9232 12:43:54.458944 HW_SAVE_FOR_SR: OFF
9233 12:43:54.462111 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9234 12:43:54.465494 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9235 12:43:54.468818 Read ODT Tracking: ON
9236 12:43:54.468899 Refresh Rate DeBounce: ON
9237 12:43:54.472196 DFS_NO_QUEUE_FLUSH: ON
9238 12:43:54.475512 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9239 12:43:54.478988 ENABLE_DFS_RUNTIME_MRW: OFF
9240 12:43:54.479071 DDR_RESERVE_NEW_MODE: ON
9241 12:43:54.482126 MR_CBT_SWITCH_FREQ: ON
9242 12:43:54.485404 =========================
9243 12:43:54.503583 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9244 12:43:54.506497 dram_init: ddr_geometry: 2
9245 12:43:54.525117 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9246 12:43:54.528221 dram_init: dram init end (result: 0)
9247 12:43:54.535072 DRAM-K: Full calibration passed in 24611 msecs
9248 12:43:54.537994 MRC: failed to locate region type 0.
9249 12:43:54.538077 DRAM rank0 size:0x100000000,
9250 12:43:54.541574 DRAM rank1 size=0x100000000
9251 12:43:54.551440 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9252 12:43:54.558103 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9253 12:43:54.564544 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9254 12:43:54.571256 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9255 12:43:54.574561 DRAM rank0 size:0x100000000,
9256 12:43:54.577975 DRAM rank1 size=0x100000000
9257 12:43:54.578058 CBMEM:
9258 12:43:54.581352 IMD: root @ 0xfffff000 254 entries.
9259 12:43:54.584724 IMD: root @ 0xffffec00 62 entries.
9260 12:43:54.587839 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9261 12:43:54.591144 WARNING: RO_VPD is uninitialized or empty.
9262 12:43:54.597839 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9263 12:43:54.604878 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9264 12:43:54.617570 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9265 12:43:54.629091 BS: romstage times (exec / console): total (unknown) / 24069 ms
9266 12:43:54.629174
9267 12:43:54.629238
9268 12:43:54.638870 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9269 12:43:54.642155 ARM64: Exception handlers installed.
9270 12:43:54.645639 ARM64: Testing exception
9271 12:43:54.648803 ARM64: Done test exception
9272 12:43:54.648885 Enumerating buses...
9273 12:43:54.652245 Show all devs... Before device enumeration.
9274 12:43:54.655600 Root Device: enabled 1
9275 12:43:54.658743 CPU_CLUSTER: 0: enabled 1
9276 12:43:54.658825 CPU: 00: enabled 1
9277 12:43:54.662208 Compare with tree...
9278 12:43:54.662290 Root Device: enabled 1
9279 12:43:54.665320 CPU_CLUSTER: 0: enabled 1
9280 12:43:54.668973 CPU: 00: enabled 1
9281 12:43:54.669052 Root Device scanning...
9282 12:43:54.672225 scan_static_bus for Root Device
9283 12:43:54.675576 CPU_CLUSTER: 0 enabled
9284 12:43:54.678674 scan_static_bus for Root Device done
9285 12:43:54.682082 scan_bus: bus Root Device finished in 8 msecs
9286 12:43:54.682155 done
9287 12:43:54.688615 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9288 12:43:54.692174 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9289 12:43:54.698725 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9290 12:43:54.702001 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9291 12:43:54.705433 Allocating resources...
9292 12:43:54.708762 Reading resources...
9293 12:43:54.712076 Root Device read_resources bus 0 link: 0
9294 12:43:54.712153 DRAM rank0 size:0x100000000,
9295 12:43:54.715256 DRAM rank1 size=0x100000000
9296 12:43:54.718825 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9297 12:43:54.721893 CPU: 00 missing read_resources
9298 12:43:54.725203 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9299 12:43:54.732015 Root Device read_resources bus 0 link: 0 done
9300 12:43:54.732090 Done reading resources.
9301 12:43:54.738726 Show resources in subtree (Root Device)...After reading.
9302 12:43:54.742062 Root Device child on link 0 CPU_CLUSTER: 0
9303 12:43:54.745397 CPU_CLUSTER: 0 child on link 0 CPU: 00
9304 12:43:54.755188 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9305 12:43:54.755265 CPU: 00
9306 12:43:54.758529 Root Device assign_resources, bus 0 link: 0
9307 12:43:54.761886 CPU_CLUSTER: 0 missing set_resources
9308 12:43:54.768448 Root Device assign_resources, bus 0 link: 0 done
9309 12:43:54.768552 Done setting resources.
9310 12:43:54.775304 Show resources in subtree (Root Device)...After assigning values.
9311 12:43:54.778623 Root Device child on link 0 CPU_CLUSTER: 0
9312 12:43:54.781929 CPU_CLUSTER: 0 child on link 0 CPU: 00
9313 12:43:54.791725 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9314 12:43:54.791835 CPU: 00
9315 12:43:54.794978 Done allocating resources.
9316 12:43:54.798506 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9317 12:43:54.801613 Enabling resources...
9318 12:43:54.801694 done.
9319 12:43:54.808112 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9320 12:43:54.808194 Initializing devices...
9321 12:43:54.811531 Root Device init
9322 12:43:54.811612 init hardware done!
9323 12:43:54.814960 0x00000018: ctrlr->caps
9324 12:43:54.818026 52.000 MHz: ctrlr->f_max
9325 12:43:54.818099 0.400 MHz: ctrlr->f_min
9326 12:43:54.821467 0x40ff8080: ctrlr->voltages
9327 12:43:54.821587 sclk: 390625
9328 12:43:54.824652 Bus Width = 1
9329 12:43:54.824722 sclk: 390625
9330 12:43:54.827975 Bus Width = 1
9331 12:43:54.828056 Early init status = 3
9332 12:43:54.834819 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9333 12:43:54.837790 in-header: 03 fc 00 00 01 00 00 00
9334 12:43:54.837897 in-data: 00
9335 12:43:54.844341 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9336 12:43:54.847737 in-header: 03 fd 00 00 00 00 00 00
9337 12:43:54.850952 in-data:
9338 12:43:54.854232 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9339 12:43:54.857968 in-header: 03 fc 00 00 01 00 00 00
9340 12:43:54.861274 in-data: 00
9341 12:43:54.864308 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9342 12:43:54.869117 in-header: 03 fd 00 00 00 00 00 00
9343 12:43:54.872334 in-data:
9344 12:43:54.875715 [SSUSB] Setting up USB HOST controller...
9345 12:43:54.879158 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9346 12:43:54.882221 [SSUSB] phy power-on done.
9347 12:43:54.885877 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9348 12:43:54.892240 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9349 12:43:54.895617 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9350 12:43:54.902012 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9351 12:43:54.908952 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9352 12:43:54.915795 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9353 12:43:54.921926 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9354 12:43:54.928830 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9355 12:43:54.931933 SPM: binary array size = 0x9dc
9356 12:43:54.935343 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9357 12:43:54.941936 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9358 12:43:54.948509 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9359 12:43:54.954781 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9360 12:43:54.958320 configure_display: Starting display init
9361 12:43:54.992646 anx7625_power_on_init: Init interface.
9362 12:43:54.996004 anx7625_disable_pd_protocol: Disabled PD feature.
9363 12:43:54.998904 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9364 12:43:55.026862 anx7625_start_dp_work: Secure OCM version=00
9365 12:43:55.030406 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9366 12:43:55.045308 sp_tx_get_edid_block: EDID Block = 1
9367 12:43:55.147852 Extracted contents:
9368 12:43:55.151171 header: 00 ff ff ff ff ff ff 00
9369 12:43:55.154219 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9370 12:43:55.157723 version: 01 04
9371 12:43:55.160861 basic params: 95 1f 11 78 0a
9372 12:43:55.164360 chroma info: 76 90 94 55 54 90 27 21 50 54
9373 12:43:55.167473 established: 00 00 00
9374 12:43:55.174265 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9375 12:43:55.177376 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9376 12:43:55.184456 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9377 12:43:55.190958 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9378 12:43:55.197570 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9379 12:43:55.200975 extensions: 00
9380 12:43:55.201609 checksum: fb
9381 12:43:55.202087
9382 12:43:55.204153 Manufacturer: IVO Model 57d Serial Number 0
9383 12:43:55.207398 Made week 0 of 2020
9384 12:43:55.207811 EDID version: 1.4
9385 12:43:55.211040 Digital display
9386 12:43:55.214076 6 bits per primary color channel
9387 12:43:55.214499 DisplayPort interface
9388 12:43:55.217555 Maximum image size: 31 cm x 17 cm
9389 12:43:55.221199 Gamma: 220%
9390 12:43:55.221654 Check DPMS levels
9391 12:43:55.223958 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9392 12:43:55.227365 First detailed timing is preferred timing
9393 12:43:55.230740 Established timings supported:
9394 12:43:55.233783 Standard timings supported:
9395 12:43:55.237331 Detailed timings
9396 12:43:55.240530 Hex of detail: 383680a07038204018303c0035ae10000019
9397 12:43:55.244046 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9398 12:43:55.250531 0780 0798 07c8 0820 hborder 0
9399 12:43:55.254110 0438 043b 0447 0458 vborder 0
9400 12:43:55.257598 -hsync -vsync
9401 12:43:55.258061 Did detailed timing
9402 12:43:55.264058 Hex of detail: 000000000000000000000000000000000000
9403 12:43:55.264531 Manufacturer-specified data, tag 0
9404 12:43:55.270447 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9405 12:43:55.273919 ASCII string: InfoVision
9406 12:43:55.276904 Hex of detail: 000000fe00523134304e574635205248200a
9407 12:43:55.280427 ASCII string: R140NWF5 RH
9408 12:43:55.280891 Checksum
9409 12:43:55.283799 Checksum: 0xfb (valid)
9410 12:43:55.287046 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9411 12:43:55.290400 DSI data_rate: 832800000 bps
9412 12:43:55.297353 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9413 12:43:55.300548 anx7625_parse_edid: pixelclock(138800).
9414 12:43:55.303865 hactive(1920), hsync(48), hfp(24), hbp(88)
9415 12:43:55.307081 vactive(1080), vsync(12), vfp(3), vbp(17)
9416 12:43:55.310280 anx7625_dsi_config: config dsi.
9417 12:43:55.317022 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9418 12:43:55.329859 anx7625_dsi_config: success to config DSI
9419 12:43:55.332903 anx7625_dp_start: MIPI phy setup OK.
9420 12:43:55.336190 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9421 12:43:55.339531 mtk_ddp_mode_set invalid vrefresh 60
9422 12:43:55.342531 main_disp_path_setup
9423 12:43:55.342913 ovl_layer_smi_id_en
9424 12:43:55.345927 ovl_layer_smi_id_en
9425 12:43:55.346108 ccorr_config
9426 12:43:55.346262 aal_config
9427 12:43:55.349457 gamma_config
9428 12:43:55.349633 postmask_config
9429 12:43:55.352825 dither_config
9430 12:43:55.356064 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9431 12:43:55.362623 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9432 12:43:55.365893 Root Device init finished in 551 msecs
9433 12:43:55.369063 CPU_CLUSTER: 0 init
9434 12:43:55.375536 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9435 12:43:55.382452 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9436 12:43:55.382577 APU_MBOX 0x190000b0 = 0x10001
9437 12:43:55.385582 APU_MBOX 0x190001b0 = 0x10001
9438 12:43:55.388789 APU_MBOX 0x190005b0 = 0x10001
9439 12:43:55.392045 APU_MBOX 0x190006b0 = 0x10001
9440 12:43:55.398803 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9441 12:43:55.408591 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9442 12:43:55.421133 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9443 12:43:55.427797 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9444 12:43:55.439428 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9445 12:43:55.448849 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9446 12:43:55.452227 CPU_CLUSTER: 0 init finished in 81 msecs
9447 12:43:55.455350 Devices initialized
9448 12:43:55.458983 Show all devs... After init.
9449 12:43:55.459424 Root Device: enabled 1
9450 12:43:55.461879 CPU_CLUSTER: 0: enabled 1
9451 12:43:55.465206 CPU: 00: enabled 1
9452 12:43:55.468682 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9453 12:43:55.471780 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9454 12:43:55.475172 ELOG: NV offset 0x57f000 size 0x1000
9455 12:43:55.481912 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9456 12:43:55.488262 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9457 12:43:55.491786 ELOG: Event(17) added with size 13 at 2024-02-05 12:43:55 UTC
9458 12:43:55.495034 out: cmd=0x121: 03 db 21 01 00 00 00 00
9459 12:43:55.498868 in-header: 03 38 00 00 2c 00 00 00
9460 12:43:55.512222 in-data: 26 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9461 12:43:55.518685 ELOG: Event(A1) added with size 10 at 2024-02-05 12:43:55 UTC
9462 12:43:55.525543 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9463 12:43:55.532090 ELOG: Event(A0) added with size 9 at 2024-02-05 12:43:55 UTC
9464 12:43:55.535221 elog_add_boot_reason: Logged dev mode boot
9465 12:43:55.538903 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9466 12:43:55.541880 Finalize devices...
9467 12:43:55.542307 Devices finalized
9468 12:43:55.548488 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9469 12:43:55.551718 Writing coreboot table at 0xffe64000
9470 12:43:55.555154 0. 000000000010a000-0000000000113fff: RAMSTAGE
9471 12:43:55.558453 1. 0000000040000000-00000000400fffff: RAM
9472 12:43:55.565221 2. 0000000040100000-000000004032afff: RAMSTAGE
9473 12:43:55.568700 3. 000000004032b000-00000000545fffff: RAM
9474 12:43:55.571813 4. 0000000054600000-000000005465ffff: BL31
9475 12:43:55.575214 5. 0000000054660000-00000000ffe63fff: RAM
9476 12:43:55.581869 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9477 12:43:55.585082 7. 0000000100000000-000000023fffffff: RAM
9478 12:43:55.585734 Passing 5 GPIOs to payload:
9479 12:43:55.591812 NAME | PORT | POLARITY | VALUE
9480 12:43:55.595106 EC in RW | 0x000000aa | low | undefined
9481 12:43:55.601464 EC interrupt | 0x00000005 | low | undefined
9482 12:43:55.604949 TPM interrupt | 0x000000ab | high | undefined
9483 12:43:55.611570 SD card detect | 0x00000011 | high | undefined
9484 12:43:55.615144 speaker enable | 0x00000093 | high | undefined
9485 12:43:55.618040 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9486 12:43:55.621545 in-header: 03 f9 00 00 02 00 00 00
9487 12:43:55.621984 in-data: 02 00
9488 12:43:55.624705 ADC[4]: Raw value=896670 ID=7
9489 12:43:55.628289 ADC[3]: Raw value=212700 ID=1
9490 12:43:55.631589 RAM Code: 0x71
9491 12:43:55.632023 ADC[6]: Raw value=74722 ID=0
9492 12:43:55.634674 ADC[5]: Raw value=212330 ID=1
9493 12:43:55.637971 SKU Code: 0x1
9494 12:43:55.641207 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 21e3
9495 12:43:55.644713 coreboot table: 964 bytes.
9496 12:43:55.648121 IMD ROOT 0. 0xfffff000 0x00001000
9497 12:43:55.651489 IMD SMALL 1. 0xffffe000 0x00001000
9498 12:43:55.654455 RO MCACHE 2. 0xffffc000 0x00001104
9499 12:43:55.657986 CONSOLE 3. 0xfff7c000 0x00080000
9500 12:43:55.661334 FMAP 4. 0xfff7b000 0x00000452
9501 12:43:55.664512 TIME STAMP 5. 0xfff7a000 0x00000910
9502 12:43:55.667977 VBOOT WORK 6. 0xfff66000 0x00014000
9503 12:43:55.671076 RAMOOPS 7. 0xffe66000 0x00100000
9504 12:43:55.674520 COREBOOT 8. 0xffe64000 0x00002000
9505 12:43:55.674957 IMD small region:
9506 12:43:55.677989 IMD ROOT 0. 0xffffec00 0x00000400
9507 12:43:55.681341 VPD 1. 0xffffeb80 0x0000006c
9508 12:43:55.684391 MMC STATUS 2. 0xffffeb60 0x00000004
9509 12:43:55.691103 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9510 12:43:55.694486 Probing TPM: done!
9511 12:43:55.698269 Connected to device vid:did:rid of 1ae0:0028:00
9512 12:43:55.707982 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9513 12:43:55.711216 Initialized TPM device CR50 revision 0
9514 12:43:55.715127 Checking cr50 for pending updates
9515 12:43:55.718486 Reading cr50 TPM mode
9516 12:43:55.727064 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9517 12:43:55.733472 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9518 12:43:55.773771 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9519 12:43:55.777102 Checking segment from ROM address 0x40100000
9520 12:43:55.780305 Checking segment from ROM address 0x4010001c
9521 12:43:55.786862 Loading segment from ROM address 0x40100000
9522 12:43:55.787341 code (compression=0)
9523 12:43:55.796936 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9524 12:43:55.803577 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9525 12:43:55.804019 it's not compressed!
9526 12:43:55.810427 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9527 12:43:55.813784 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9528 12:43:55.834141 Loading segment from ROM address 0x4010001c
9529 12:43:55.834721 Entry Point 0x80000000
9530 12:43:55.837282 Loaded segments
9531 12:43:55.840828 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9532 12:43:55.847213 Jumping to boot code at 0x80000000(0xffe64000)
9533 12:43:55.854197 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9534 12:43:55.860341 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9535 12:43:55.868413 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9536 12:43:55.871910 Checking segment from ROM address 0x40100000
9537 12:43:55.874977 Checking segment from ROM address 0x4010001c
9538 12:43:55.881639 Loading segment from ROM address 0x40100000
9539 12:43:55.882057 code (compression=1)
9540 12:43:55.888424 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9541 12:43:55.898430 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9542 12:43:55.898979 using LZMA
9543 12:43:55.906942 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9544 12:43:55.913585 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9545 12:43:55.916877 Loading segment from ROM address 0x4010001c
9546 12:43:55.917325 Entry Point 0x54601000
9547 12:43:55.920163 Loaded segments
9548 12:43:55.923475 NOTICE: MT8192 bl31_setup
9549 12:43:55.930327 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9550 12:43:55.933791 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9551 12:43:55.937229 WARNING: region 0:
9552 12:43:55.940334 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9553 12:43:55.940718 WARNING: region 1:
9554 12:43:55.946910 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9555 12:43:55.950433 WARNING: region 2:
9556 12:43:55.953938 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9557 12:43:55.957023 WARNING: region 3:
9558 12:43:55.960582 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9559 12:43:55.963709 WARNING: region 4:
9560 12:43:55.970427 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9561 12:43:55.970884 WARNING: region 5:
9562 12:43:55.973638 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9563 12:43:55.977084 WARNING: region 6:
9564 12:43:55.980348 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9565 12:43:55.983711 WARNING: region 7:
9566 12:43:55.986886 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9567 12:43:55.993822 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9568 12:43:55.996868 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9569 12:43:56.000298 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9570 12:43:56.006914 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9571 12:43:56.010069 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9572 12:43:56.013345 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9573 12:43:56.020169 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9574 12:43:56.023544 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9575 12:43:56.030317 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9576 12:43:56.033723 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9577 12:43:56.037085 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9578 12:43:56.043699 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9579 12:43:56.047176 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9580 12:43:56.050242 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9581 12:43:56.057067 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9582 12:43:56.060535 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9583 12:43:56.067092 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9584 12:43:56.070500 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9585 12:43:56.073603 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9586 12:43:56.080568 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9587 12:43:56.083590 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9588 12:43:56.087066 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9589 12:43:56.093811 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9590 12:43:56.097010 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9591 12:43:56.103734 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9592 12:43:56.107015 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9593 12:43:56.110445 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9594 12:43:56.117032 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9595 12:43:56.120424 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9596 12:43:56.123983 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9597 12:43:56.130478 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9598 12:43:56.133833 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9599 12:43:56.137457 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9600 12:43:56.144178 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9601 12:43:56.147426 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9602 12:43:56.150488 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9603 12:43:56.153440 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9604 12:43:56.160308 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9605 12:43:56.163581 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9606 12:43:56.167046 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9607 12:43:56.170084 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9608 12:43:56.176663 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9609 12:43:56.180124 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9610 12:43:56.183321 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9611 12:43:56.186982 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9612 12:43:56.193181 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9613 12:43:56.196610 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9614 12:43:56.199934 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9615 12:43:56.206801 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9616 12:43:56.210083 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9617 12:43:56.216561 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9618 12:43:56.220085 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9619 12:43:56.223312 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9620 12:43:56.230139 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9621 12:43:56.233316 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9622 12:43:56.240185 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9623 12:43:56.243316 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9624 12:43:56.250053 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9625 12:43:56.253473 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9626 12:43:56.256591 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9627 12:43:56.263664 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9628 12:43:56.266714 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9629 12:43:56.273462 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9630 12:43:56.276712 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9631 12:43:56.283407 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9632 12:43:56.286441 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9633 12:43:56.293241 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9634 12:43:56.296540 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9635 12:43:56.300059 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9636 12:43:56.306607 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9637 12:43:56.309886 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9638 12:43:56.316679 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9639 12:43:56.320169 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9640 12:43:56.323317 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9641 12:43:56.329971 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9642 12:43:56.333396 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9643 12:43:56.340072 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9644 12:43:56.343199 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9645 12:43:56.349745 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9646 12:43:56.353289 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9647 12:43:56.359789 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9648 12:43:56.363153 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9649 12:43:56.366550 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9650 12:43:56.373317 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9651 12:43:56.376727 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9652 12:43:56.383211 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9653 12:43:56.386643 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9654 12:43:56.393341 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9655 12:43:56.396722 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9656 12:43:56.399769 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9657 12:43:56.406458 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9658 12:43:56.409807 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9659 12:43:56.416546 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9660 12:43:56.420025 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9661 12:43:56.426390 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9662 12:43:56.429700 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9663 12:43:56.433220 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9664 12:43:56.439749 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9665 12:43:56.443281 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9666 12:43:56.446487 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9667 12:43:56.450007 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9668 12:43:56.456532 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9669 12:43:56.459726 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9670 12:43:56.466634 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9671 12:43:56.469819 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9672 12:43:56.473254 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9673 12:43:56.479856 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9674 12:43:56.483139 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9675 12:43:56.489792 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9676 12:43:56.493223 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9677 12:43:56.496587 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9678 12:43:56.503201 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9679 12:43:56.506352 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9680 12:43:56.513079 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9681 12:43:56.516510 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9682 12:43:56.520001 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9683 12:43:56.523180 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9684 12:43:56.529665 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9685 12:43:56.533096 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9686 12:43:56.536279 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9687 12:43:56.543177 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9688 12:43:56.546427 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9689 12:43:56.549511 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9690 12:43:56.553172 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9691 12:43:56.559966 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9692 12:43:56.563040 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9693 12:43:56.569601 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9694 12:43:56.572990 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9695 12:43:56.576143 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9696 12:43:56.583285 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9697 12:43:56.586415 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9698 12:43:56.589516 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9699 12:43:56.596530 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9700 12:43:56.599813 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9701 12:43:56.606368 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9702 12:43:56.609727 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9703 12:43:56.612983 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9704 12:43:56.619457 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9705 12:43:56.622908 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9706 12:43:56.629688 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9707 12:43:56.633082 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9708 12:43:56.636319 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9709 12:43:56.642964 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9710 12:43:56.646437 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9711 12:43:56.649762 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9712 12:43:56.656855 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9713 12:43:56.660018 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9714 12:43:56.666631 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9715 12:43:56.670019 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9716 12:43:56.673115 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9717 12:43:56.679829 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9718 12:43:56.683106 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9719 12:43:56.689840 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9720 12:43:56.693338 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9721 12:43:56.696600 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9722 12:43:56.702980 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9723 12:43:56.706470 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9724 12:43:56.709762 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9725 12:43:56.716594 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9726 12:43:56.719743 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9727 12:43:56.726557 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9728 12:43:56.729493 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9729 12:43:56.733219 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9730 12:43:56.739744 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9731 12:43:56.743132 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9732 12:43:56.749598 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9733 12:43:56.752942 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9734 12:43:56.756375 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9735 12:43:56.763080 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9736 12:43:56.766381 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9737 12:43:56.772887 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9738 12:43:56.776565 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9739 12:43:56.779717 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9740 12:43:56.786120 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9741 12:43:56.789684 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9742 12:43:56.796166 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9743 12:43:56.799353 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9744 12:43:56.802693 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9745 12:43:56.809527 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9746 12:43:56.812875 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9747 12:43:56.819053 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9748 12:43:56.822850 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9749 12:43:56.825899 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9750 12:43:56.832525 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9751 12:43:56.836012 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9752 12:43:56.842612 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9753 12:43:56.845766 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9754 12:43:56.849078 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9755 12:43:56.855483 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9756 12:43:56.859092 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9757 12:43:56.865422 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9758 12:43:56.868840 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9759 12:43:56.875211 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9760 12:43:56.878995 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9761 12:43:56.881803 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9762 12:43:56.888685 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9763 12:43:56.891891 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9764 12:43:56.898390 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9765 12:43:56.901610 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9766 12:43:56.905099 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9767 12:43:56.911782 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9768 12:43:56.915057 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9769 12:43:56.921523 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9770 12:43:56.925165 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9771 12:43:56.931826 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9772 12:43:56.935162 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9773 12:43:56.938273 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9774 12:43:56.945140 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9775 12:43:56.948231 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9776 12:43:56.954825 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9777 12:43:56.957896 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9778 12:43:56.964543 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9779 12:43:56.967767 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9780 12:43:56.971450 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9781 12:43:56.977894 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9782 12:43:56.981231 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9783 12:43:56.987843 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9784 12:43:56.991042 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9785 12:43:56.994333 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9786 12:43:57.000761 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9787 12:43:57.004130 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9788 12:43:57.011021 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9789 12:43:57.013919 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9790 12:43:57.020783 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9791 12:43:57.024169 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9792 12:43:57.027143 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9793 12:43:57.034280 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9794 12:43:57.037010 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9795 12:43:57.044105 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9796 12:43:57.047183 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9797 12:43:57.050704 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9798 12:43:57.053403 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9799 12:43:57.060115 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9800 12:43:57.063490 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9801 12:43:57.066588 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9802 12:43:57.073455 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9803 12:43:57.076811 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9804 12:43:57.080086 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9805 12:43:57.086956 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9806 12:43:57.090131 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9807 12:43:57.093356 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9808 12:43:57.099654 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9809 12:43:57.103137 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9810 12:43:57.106590 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9811 12:43:57.113235 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9812 12:43:57.116553 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9813 12:43:57.123223 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9814 12:43:57.126465 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9815 12:43:57.129905 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9816 12:43:57.136330 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9817 12:43:57.139933 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9818 12:43:57.146232 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9819 12:43:57.149710 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9820 12:43:57.152855 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9821 12:43:57.159424 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9822 12:43:57.162954 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9823 12:43:57.166210 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9824 12:43:57.173214 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9825 12:43:57.176379 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9826 12:43:57.179450 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9827 12:43:57.186365 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9828 12:43:57.189852 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9829 12:43:57.196106 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9830 12:43:57.199370 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9831 12:43:57.202977 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9832 12:43:57.209356 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9833 12:43:57.212999 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9834 12:43:57.216122 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9835 12:43:57.222764 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9836 12:43:57.226062 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9837 12:43:57.229048 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9838 12:43:57.232735 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9839 12:43:57.239199 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9840 12:43:57.242427 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9841 12:43:57.245671 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9842 12:43:57.249334 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9843 12:43:57.252483 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9844 12:43:57.259092 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9845 12:43:57.262637 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9846 12:43:57.265822 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9847 12:43:57.272486 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9848 12:43:57.275998 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9849 12:43:57.279133 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9850 12:43:57.285807 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9851 12:43:57.289296 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9852 12:43:57.296050 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9853 12:43:57.299029 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9854 12:43:57.302560 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9855 12:43:57.309033 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9856 12:43:57.312372 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9857 12:43:57.319010 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9858 12:43:57.322431 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9859 12:43:57.325873 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9860 12:43:57.332097 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9861 12:43:57.335605 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9862 12:43:57.342068 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9863 12:43:57.345421 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9864 12:43:57.348811 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9865 12:43:57.355343 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9866 12:43:57.358541 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9867 12:43:57.365040 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9868 12:43:57.368533 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9869 12:43:57.375414 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9870 12:43:57.378646 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9871 12:43:57.382054 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9872 12:43:57.388653 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9873 12:43:57.392034 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9874 12:43:57.398576 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9875 12:43:57.402035 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9876 12:43:57.405386 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9877 12:43:57.411731 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9878 12:43:57.415081 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9879 12:43:57.421616 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9880 12:43:57.424810 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9881 12:43:57.428415 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9882 12:43:57.434839 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9883 12:43:57.438119 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9884 12:43:57.444855 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9885 12:43:57.447923 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9886 12:43:57.454810 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9887 12:43:57.457828 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9888 12:43:57.461515 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9889 12:43:57.467890 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9890 12:43:57.471504 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9891 12:43:57.478028 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9892 12:43:57.481146 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9893 12:43:57.487596 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9894 12:43:57.491130 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9895 12:43:57.494305 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9896 12:43:57.501106 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9897 12:43:57.504198 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9898 12:43:57.510921 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9899 12:43:57.514362 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9900 12:43:57.517509 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9901 12:43:57.524284 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9902 12:43:57.527448 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9903 12:43:57.533895 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9904 12:43:57.537511 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9905 12:43:57.540595 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9906 12:43:57.547288 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9907 12:43:57.550676 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9908 12:43:57.557362 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9909 12:43:57.560322 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9910 12:43:57.567063 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9911 12:43:57.570433 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9912 12:43:57.573945 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9913 12:43:57.580507 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9914 12:43:57.583773 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9915 12:43:57.590319 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9916 12:43:57.593736 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9917 12:43:57.597123 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9918 12:43:57.603500 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9919 12:43:57.607132 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9920 12:43:57.613601 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9921 12:43:57.617137 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9922 12:43:57.620306 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9923 12:43:57.626888 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9924 12:43:57.630332 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9925 12:43:57.637014 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9926 12:43:57.639951 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9927 12:43:57.646652 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9928 12:43:57.650382 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9929 12:43:57.653436 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9930 12:43:57.660464 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9931 12:43:57.663677 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9932 12:43:57.670142 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9933 12:43:57.673588 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9934 12:43:57.680167 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9935 12:43:57.683826 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9936 12:43:57.687122 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9937 12:43:57.693643 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9938 12:43:57.696828 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9939 12:43:57.703365 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9940 12:43:57.706752 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9941 12:43:57.713217 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9942 12:43:57.716634 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9943 12:43:57.723371 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9944 12:43:57.726533 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9945 12:43:57.729646 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9946 12:43:57.736595 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9947 12:43:57.739957 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9948 12:43:57.746370 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9949 12:43:57.749694 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9950 12:43:57.756150 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9951 12:43:57.759372 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9952 12:43:57.766231 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9953 12:43:57.769471 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9954 12:43:57.772598 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9955 12:43:57.779270 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9956 12:43:57.782844 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9957 12:43:57.789055 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9958 12:43:57.792784 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9959 12:43:57.799134 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9960 12:43:57.802511 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9961 12:43:57.805785 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9962 12:43:57.812244 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9963 12:43:57.816049 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9964 12:43:57.822446 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9965 12:43:57.825888 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9966 12:43:57.832178 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9967 12:43:57.835591 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9968 12:43:57.842185 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9969 12:43:57.845877 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9970 12:43:57.849047 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9971 12:43:57.855556 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9972 12:43:57.858643 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9973 12:43:57.865467 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9974 12:43:57.868712 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9975 12:43:57.875508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9976 12:43:57.878669 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9977 12:43:57.885229 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9978 12:43:57.888386 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9979 12:43:57.895324 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9980 12:43:57.898424 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9981 12:43:57.905137 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9982 12:43:57.908299 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9983 12:43:57.914718 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9984 12:43:57.918438 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9985 12:43:57.924872 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9986 12:43:57.927934 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9987 12:43:57.934756 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9988 12:43:57.938059 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9989 12:43:57.944586 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9990 12:43:57.948288 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9991 12:43:57.954995 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9992 12:43:57.958092 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9993 12:43:57.964874 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9994 12:43:57.967738 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9995 12:43:57.974595 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9996 12:43:57.977877 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9997 12:43:57.984422 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9998 12:43:57.987603 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9999 12:43:57.994151 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10000 12:43:57.997582 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10001 12:43:58.000706 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10002 12:43:58.004256 INFO: [APUAPC] vio 0
10003 12:43:58.010858 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10004 12:43:58.014367 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10005 12:43:58.017430 INFO: [APUAPC] D0_APC_0: 0x400510
10006 12:43:58.020638 INFO: [APUAPC] D0_APC_1: 0x0
10007 12:43:58.024062 INFO: [APUAPC] D0_APC_2: 0x1540
10008 12:43:58.027419 INFO: [APUAPC] D0_APC_3: 0x0
10009 12:43:58.030478 INFO: [APUAPC] D1_APC_0: 0xffffffff
10010 12:43:58.033830 INFO: [APUAPC] D1_APC_1: 0xffffffff
10011 12:43:58.037570 INFO: [APUAPC] D1_APC_2: 0x3fffff
10012 12:43:58.040856 INFO: [APUAPC] D1_APC_3: 0x0
10013 12:43:58.043968 INFO: [APUAPC] D2_APC_0: 0xffffffff
10014 12:43:58.047609 INFO: [APUAPC] D2_APC_1: 0xffffffff
10015 12:43:58.050361 INFO: [APUAPC] D2_APC_2: 0x3fffff
10016 12:43:58.050713 INFO: [APUAPC] D2_APC_3: 0x0
10017 12:43:58.053818 INFO: [APUAPC] D3_APC_0: 0xffffffff
10018 12:43:58.060265 INFO: [APUAPC] D3_APC_1: 0xffffffff
10019 12:43:58.060448 INFO: [APUAPC] D3_APC_2: 0x3fffff
10020 12:43:58.063794 INFO: [APUAPC] D3_APC_3: 0x0
10021 12:43:58.067034 INFO: [APUAPC] D4_APC_0: 0xffffffff
10022 12:43:58.070187 INFO: [APUAPC] D4_APC_1: 0xffffffff
10023 12:43:58.073644 INFO: [APUAPC] D4_APC_2: 0x3fffff
10024 12:43:58.076745 INFO: [APUAPC] D4_APC_3: 0x0
10025 12:43:58.080067 INFO: [APUAPC] D5_APC_0: 0xffffffff
10026 12:43:58.083588 INFO: [APUAPC] D5_APC_1: 0xffffffff
10027 12:43:58.086965 INFO: [APUAPC] D5_APC_2: 0x3fffff
10028 12:43:58.089960 INFO: [APUAPC] D5_APC_3: 0x0
10029 12:43:58.093256 INFO: [APUAPC] D6_APC_0: 0xffffffff
10030 12:43:58.096661 INFO: [APUAPC] D6_APC_1: 0xffffffff
10031 12:43:58.100037 INFO: [APUAPC] D6_APC_2: 0x3fffff
10032 12:43:58.103424 INFO: [APUAPC] D6_APC_3: 0x0
10033 12:43:58.106514 INFO: [APUAPC] D7_APC_0: 0xffffffff
10034 12:43:58.110016 INFO: [APUAPC] D7_APC_1: 0xffffffff
10035 12:43:58.113061 INFO: [APUAPC] D7_APC_2: 0x3fffff
10036 12:43:58.116733 INFO: [APUAPC] D7_APC_3: 0x0
10037 12:43:58.120112 INFO: [APUAPC] D8_APC_0: 0xffffffff
10038 12:43:58.123237 INFO: [APUAPC] D8_APC_1: 0xffffffff
10039 12:43:58.126796 INFO: [APUAPC] D8_APC_2: 0x3fffff
10040 12:43:58.130047 INFO: [APUAPC] D8_APC_3: 0x0
10041 12:43:58.133154 INFO: [APUAPC] D9_APC_0: 0xffffffff
10042 12:43:58.136678 INFO: [APUAPC] D9_APC_1: 0xffffffff
10043 12:43:58.139684 INFO: [APUAPC] D9_APC_2: 0x3fffff
10044 12:43:58.143135 INFO: [APUAPC] D9_APC_3: 0x0
10045 12:43:58.146605 INFO: [APUAPC] D10_APC_0: 0xffffffff
10046 12:43:58.149506 INFO: [APUAPC] D10_APC_1: 0xffffffff
10047 12:43:58.152899 INFO: [APUAPC] D10_APC_2: 0x3fffff
10048 12:43:58.156265 INFO: [APUAPC] D10_APC_3: 0x0
10049 12:43:58.159673 INFO: [APUAPC] D11_APC_0: 0xffffffff
10050 12:43:58.163127 INFO: [APUAPC] D11_APC_1: 0xffffffff
10051 12:43:58.166327 INFO: [APUAPC] D11_APC_2: 0x3fffff
10052 12:43:58.169663 INFO: [APUAPC] D11_APC_3: 0x0
10053 12:43:58.172816 INFO: [APUAPC] D12_APC_0: 0xffffffff
10054 12:43:58.176308 INFO: [APUAPC] D12_APC_1: 0xffffffff
10055 12:43:58.179327 INFO: [APUAPC] D12_APC_2: 0x3fffff
10056 12:43:58.182816 INFO: [APUAPC] D12_APC_3: 0x0
10057 12:43:58.186297 INFO: [APUAPC] D13_APC_0: 0xffffffff
10058 12:43:58.189428 INFO: [APUAPC] D13_APC_1: 0xffffffff
10059 12:43:58.192676 INFO: [APUAPC] D13_APC_2: 0x3fffff
10060 12:43:58.196142 INFO: [APUAPC] D13_APC_3: 0x0
10061 12:43:58.199569 INFO: [APUAPC] D14_APC_0: 0xffffffff
10062 12:43:58.202475 INFO: [APUAPC] D14_APC_1: 0xffffffff
10063 12:43:58.206088 INFO: [APUAPC] D14_APC_2: 0x3fffff
10064 12:43:58.209141 INFO: [APUAPC] D14_APC_3: 0x0
10065 12:43:58.212661 INFO: [APUAPC] D15_APC_0: 0xffffffff
10066 12:43:58.216049 INFO: [APUAPC] D15_APC_1: 0xffffffff
10067 12:43:58.219329 INFO: [APUAPC] D15_APC_2: 0x3fffff
10068 12:43:58.222649 INFO: [APUAPC] D15_APC_3: 0x0
10069 12:43:58.225814 INFO: [APUAPC] APC_CON: 0x4
10070 12:43:58.229293 INFO: [NOCDAPC] D0_APC_0: 0x0
10071 12:43:58.232532 INFO: [NOCDAPC] D0_APC_1: 0x0
10072 12:43:58.235887 INFO: [NOCDAPC] D1_APC_0: 0x0
10073 12:43:58.239115 INFO: [NOCDAPC] D1_APC_1: 0xfff
10074 12:43:58.239200 INFO: [NOCDAPC] D2_APC_0: 0x0
10075 12:43:58.242469 INFO: [NOCDAPC] D2_APC_1: 0xfff
10076 12:43:58.245787 INFO: [NOCDAPC] D3_APC_0: 0x0
10077 12:43:58.248859 INFO: [NOCDAPC] D3_APC_1: 0xfff
10078 12:43:58.252408 INFO: [NOCDAPC] D4_APC_0: 0x0
10079 12:43:58.255511 INFO: [NOCDAPC] D4_APC_1: 0xfff
10080 12:43:58.258955 INFO: [NOCDAPC] D5_APC_0: 0x0
10081 12:43:58.262297 INFO: [NOCDAPC] D5_APC_1: 0xfff
10082 12:43:58.265370 INFO: [NOCDAPC] D6_APC_0: 0x0
10083 12:43:58.268676 INFO: [NOCDAPC] D6_APC_1: 0xfff
10084 12:43:58.272187 INFO: [NOCDAPC] D7_APC_0: 0x0
10085 12:43:58.275213 INFO: [NOCDAPC] D7_APC_1: 0xfff
10086 12:43:58.275296 INFO: [NOCDAPC] D8_APC_0: 0x0
10087 12:43:58.278655 INFO: [NOCDAPC] D8_APC_1: 0xfff
10088 12:43:58.282039 INFO: [NOCDAPC] D9_APC_0: 0x0
10089 12:43:58.285161 INFO: [NOCDAPC] D9_APC_1: 0xfff
10090 12:43:58.288353 INFO: [NOCDAPC] D10_APC_0: 0x0
10091 12:43:58.291783 INFO: [NOCDAPC] D10_APC_1: 0xfff
10092 12:43:58.295205 INFO: [NOCDAPC] D11_APC_0: 0x0
10093 12:43:58.298598 INFO: [NOCDAPC] D11_APC_1: 0xfff
10094 12:43:58.301981 INFO: [NOCDAPC] D12_APC_0: 0x0
10095 12:43:58.304979 INFO: [NOCDAPC] D12_APC_1: 0xfff
10096 12:43:58.308422 INFO: [NOCDAPC] D13_APC_0: 0x0
10097 12:43:58.311655 INFO: [NOCDAPC] D13_APC_1: 0xfff
10098 12:43:58.314855 INFO: [NOCDAPC] D14_APC_0: 0x0
10099 12:43:58.318372 INFO: [NOCDAPC] D14_APC_1: 0xfff
10100 12:43:58.318455 INFO: [NOCDAPC] D15_APC_0: 0x0
10101 12:43:58.321629 INFO: [NOCDAPC] D15_APC_1: 0xfff
10102 12:43:58.325101 INFO: [NOCDAPC] APC_CON: 0x4
10103 12:43:58.328505 INFO: [APUAPC] set_apusys_apc done
10104 12:43:58.331504 INFO: [DEVAPC] devapc_init done
10105 12:43:58.334898 INFO: GICv3 without legacy support detected.
10106 12:43:58.341456 INFO: ARM GICv3 driver initialized in EL3
10107 12:43:58.345113 INFO: Maximum SPI INTID supported: 639
10108 12:43:58.348337 INFO: BL31: Initializing runtime services
10109 12:43:58.354889 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10110 12:43:58.358366 INFO: SPM: enable CPC mode
10111 12:43:58.361356 INFO: mcdi ready for mcusys-off-idle and system suspend
10112 12:43:58.367971 INFO: BL31: Preparing for EL3 exit to normal world
10113 12:43:58.371344 INFO: Entry point address = 0x80000000
10114 12:43:58.371506 INFO: SPSR = 0x8
10115 12:43:58.378012
10116 12:43:58.378127
10117 12:43:58.378230
10118 12:43:58.381248 Starting depthcharge on Spherion...
10119 12:43:58.381364
10120 12:43:58.381466 Wipe memory regions:
10121 12:43:58.381632
10122 12:43:58.382503 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10123 12:43:58.382673 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10124 12:43:58.382797 Setting prompt string to ['asurada:']
10125 12:43:58.382926 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10126 12:43:58.384625 [0x00000040000000, 0x00000054600000)
10127 12:43:58.507113
10128 12:43:58.507302 [0x00000054660000, 0x00000080000000)
10129 12:43:58.767570
10130 12:43:58.767721 [0x000000821a7280, 0x000000ffe64000)
10131 12:43:59.512432
10132 12:43:59.512601 [0x00000100000000, 0x00000240000000)
10133 12:44:01.402928
10134 12:44:01.406017 Initializing XHCI USB controller at 0x11200000.
10135 12:44:02.443931
10136 12:44:02.447008 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10137 12:44:02.447096
10138 12:44:02.447162
10139 12:44:02.447222
10140 12:44:02.447507 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10142 12:44:02.547848 asurada: tftpboot 192.168.201.1 12703562/tftp-deploy-1njj5dyf/kernel/image.itb 12703562/tftp-deploy-1njj5dyf/kernel/cmdline
10143 12:44:02.548039 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10144 12:44:02.548149 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10145 12:44:02.552114 tftpboot 192.168.201.1 12703562/tftp-deploy-1njj5dyf/kernel/image.ittp-deploy-1njj5dyf/kernel/cmdline
10146 12:44:02.552228
10147 12:44:02.552322 Waiting for link
10148 12:44:02.712726
10149 12:44:02.712887 R8152: Initializing
10150 12:44:02.712987
10151 12:44:02.715857 Version 6 (ocp_data = 5c30)
10152 12:44:02.715939
10153 12:44:02.719031 R8152: Done initializing
10154 12:44:02.719113
10155 12:44:02.719178 Adding net device
10156 12:44:04.623088
10157 12:44:04.623246 done.
10158 12:44:04.623348
10159 12:44:04.623445 MAC: 00:24:32:30:78:ff
10160 12:44:04.623511
10161 12:44:04.626416 Sending DHCP discover... done.
10162 12:44:04.626500
10163 12:44:04.629765 Waiting for reply... done.
10164 12:44:04.629849
10165 12:44:04.633038 Sending DHCP request... done.
10166 12:44:04.633121
10167 12:44:04.637431 Waiting for reply... done.
10168 12:44:04.637552
10169 12:44:04.637659 My ip is 192.168.201.21
10170 12:44:04.637723
10171 12:44:04.640981 The DHCP server ip is 192.168.201.1
10172 12:44:04.641053
10173 12:44:04.647411 TFTP server IP predefined by user: 192.168.201.1
10174 12:44:04.647502
10175 12:44:04.654182 Bootfile predefined by user: 12703562/tftp-deploy-1njj5dyf/kernel/image.itb
10176 12:44:04.654270
10177 12:44:04.654337 Sending tftp read request... done.
10178 12:44:04.657392
10179 12:44:04.661339 Waiting for the transfer...
10180 12:44:04.661450
10181 12:44:05.187845 00000000 ################################################################
10182 12:44:05.188042
10183 12:44:05.709354 00080000 ################################################################
10184 12:44:05.709540
10185 12:44:06.228334 00100000 ################################################################
10186 12:44:06.228507
10187 12:44:06.749325 00180000 ################################################################
10188 12:44:06.749567
10189 12:44:07.297058 00200000 ################################################################
10190 12:44:07.297298
10191 12:44:07.839590 00280000 ################################################################
10192 12:44:07.839812
10193 12:44:08.360198 00300000 ################################################################
10194 12:44:08.360350
10195 12:44:08.886278 00380000 ################################################################
10196 12:44:08.886415
10197 12:44:09.422966 00400000 ################################################################
10198 12:44:09.423117
10199 12:44:09.946008 00480000 ################################################################
10200 12:44:09.946185
10201 12:44:10.480431 00500000 ################################################################
10202 12:44:10.480584
10203 12:44:11.007783 00580000 ################################################################
10204 12:44:11.007923
10205 12:44:11.532579 00600000 ################################################################
10206 12:44:11.532740
10207 12:44:12.066781 00680000 ################################################################
10208 12:44:12.066930
10209 12:44:12.595535 00700000 ################################################################
10210 12:44:12.595685
10211 12:44:13.127121 00780000 ################################################################
10212 12:44:13.127274
10213 12:44:13.656832 00800000 ################################################################
10214 12:44:13.657016
10215 12:44:14.183448 00880000 ################################################################
10216 12:44:14.183601
10217 12:44:14.711005 00900000 ################################################################
10218 12:44:14.711157
10219 12:44:15.242737 00980000 ################################################################
10220 12:44:15.242897
10221 12:44:15.759747 00a00000 ################################################################
10222 12:44:15.759890
10223 12:44:16.279910 00a80000 ################################################################
10224 12:44:16.280057
10225 12:44:16.837459 00b00000 ################################################################
10226 12:44:16.837645
10227 12:44:17.354661 00b80000 ################################################################
10228 12:44:17.354809
10229 12:44:17.878898 00c00000 ################################################################
10230 12:44:17.879043
10231 12:44:18.406908 00c80000 ################################################################
10232 12:44:18.407050
10233 12:44:18.928214 00d00000 ################################################################
10234 12:44:18.928387
10235 12:44:19.451357 00d80000 ################################################################
10236 12:44:19.451556
10237 12:44:19.969821 00e00000 ################################################################
10238 12:44:19.969963
10239 12:44:20.489141 00e80000 ################################################################
10240 12:44:20.489296
10241 12:44:21.027335 00f00000 ################################################################
10242 12:44:21.027501
10243 12:44:21.570000 00f80000 ################################################################
10244 12:44:21.570139
10245 12:44:22.095201 01000000 ################################################################
10246 12:44:22.095340
10247 12:44:22.642941 01080000 ################################################################
10248 12:44:22.643096
10249 12:44:23.197499 01100000 ################################################################
10250 12:44:23.197646
10251 12:44:23.759724 01180000 ################################################################
10252 12:44:23.759860
10253 12:44:24.314222 01200000 ################################################################
10254 12:44:24.314364
10255 12:44:24.859960 01280000 ################################################################
10256 12:44:24.860093
10257 12:44:25.411862 01300000 ################################################################
10258 12:44:25.412011
10259 12:44:25.938252 01380000 ################################################################
10260 12:44:25.938408
10261 12:44:26.469928 01400000 ################################################################
10262 12:44:26.470084
10263 12:44:27.001688 01480000 ################################################################
10264 12:44:27.001847
10265 12:44:27.528234 01500000 ################################################################
10266 12:44:27.528390
10267 12:44:28.064216 01580000 ################################################################
10268 12:44:28.064416
10269 12:44:28.623492 01600000 ################################################################
10270 12:44:28.623651
10271 12:44:29.163385 01680000 ################################################################
10272 12:44:29.163543
10273 12:44:29.706798 01700000 ################################################################
10274 12:44:29.706958
10275 12:44:30.259860 01780000 ################################################################
10276 12:44:30.260018
10277 12:44:30.791934 01800000 ################################################################
10278 12:44:30.792089
10279 12:44:31.327306 01880000 ################################################################
10280 12:44:31.327475
10281 12:44:31.875601 01900000 ################################################################
10282 12:44:31.875760
10283 12:44:32.431137 01980000 ################################################################
10284 12:44:32.431304
10285 12:44:32.977621 01a00000 ################################################################
10286 12:44:32.977777
10287 12:44:33.520729 01a80000 ################################################################
10288 12:44:33.520885
10289 12:44:34.050494 01b00000 ################################################################
10290 12:44:34.050659
10291 12:44:34.597100 01b80000 ################################################################
10292 12:44:34.597257
10293 12:44:35.150453 01c00000 ################################################################
10294 12:44:35.150607
10295 12:44:35.714264 01c80000 ################################################################
10296 12:44:35.714415
10297 12:44:36.207618 01d00000 ######################################################### done.
10298 12:44:36.207771
10299 12:44:36.211262 The bootfile was 30871218 bytes long.
10300 12:44:36.211349
10301 12:44:36.214454 Sending tftp read request... done.
10302 12:44:36.214536
10303 12:44:36.214601 Waiting for the transfer...
10304 12:44:36.214661
10305 12:44:36.217667 00000000 # done.
10306 12:44:36.217751
10307 12:44:36.224375 Command line loaded dynamically from TFTP file: 12703562/tftp-deploy-1njj5dyf/kernel/cmdline
10308 12:44:36.224460
10309 12:44:36.247456 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12703562/extract-nfsrootfs-3xh3n14o,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10310 12:44:36.247584
10311 12:44:36.247653 Loading FIT.
10312 12:44:36.247714
10313 12:44:36.250829 Image ramdisk-1 has 18769045 bytes.
10314 12:44:36.250912
10315 12:44:36.254266 Image fdt-1 has 47278 bytes.
10316 12:44:36.254349
10317 12:44:36.257400 Image kernel-1 has 12052857 bytes.
10318 12:44:36.257514
10319 12:44:36.267418 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10320 12:44:36.267504
10321 12:44:36.284027 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10322 12:44:36.284127
10323 12:44:36.290327 Choosing best match conf-1 for compat google,spherion-rev2.
10324 12:44:36.290431
10325 12:44:36.297834 Connected to device vid:did:rid of 1ae0:0028:00
10326 12:44:36.305098
10327 12:44:36.308400 tpm_get_response: command 0x17b, return code 0x0
10328 12:44:36.308482
10329 12:44:36.311477 ec_init: CrosEC protocol v3 supported (256, 248)
10330 12:44:36.316798
10331 12:44:36.320050 tpm_cleanup: add release locality here.
10332 12:44:36.320133
10333 12:44:36.320199 Shutting down all USB controllers.
10334 12:44:36.323179
10335 12:44:36.323261 Removing current net device
10336 12:44:36.323325
10337 12:44:36.330108 Exiting depthcharge with code 4 at timestamp: 67298909
10338 12:44:36.330190
10339 12:44:36.333293 LZMA decompressing kernel-1 to 0x821a6718
10340 12:44:36.333375
10341 12:44:36.336645 LZMA decompressing kernel-1 to 0x40000000
10342 12:44:37.836474
10343 12:44:37.836931 jumping to kernel
10344 12:44:37.838291 end: 2.2.4 bootloader-commands (duration 00:00:39) [common]
10345 12:44:37.838699 start: 2.2.5 auto-login-action (timeout 00:03:46) [common]
10346 12:44:37.839012 Setting prompt string to ['Linux version [0-9]']
10347 12:44:37.839311 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10348 12:44:37.839604 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10349 12:44:37.919547
10350 12:44:37.922632 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10351 12:44:37.925875 start: 2.2.5.1 login-action (timeout 00:03:46) [common]
10352 12:44:37.925970 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10353 12:44:37.926042 Setting prompt string to []
10354 12:44:37.926118 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10355 12:44:37.926191 Using line separator: #'\n'#
10356 12:44:37.926249 No login prompt set.
10357 12:44:37.926307 Parsing kernel messages
10358 12:44:37.926361 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10359 12:44:37.926463 [login-action] Waiting for messages, (timeout 00:03:46)
10360 12:44:37.926526 Waiting using forced prompt support (timeout 00:01:53)
10361 12:44:37.945548 [ 0.000000] Linux version 6.1.75-cip14 (KernelCI@build-j98433-arm64-gcc-10-defconfig-arm64-chromebook-89n64) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Feb 5 12:20:06 UTC 2024
10362 12:44:37.948878 [ 0.000000] random: crng init done
10363 12:44:37.955346 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10364 12:44:37.958750 [ 0.000000] efi: UEFI not found.
10365 12:44:37.965532 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10366 12:44:37.975211 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10367 12:44:37.982083 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10368 12:44:37.991857 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10369 12:44:37.998325 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10370 12:44:38.005032 [ 0.000000] printk: bootconsole [mtk8250] enabled
10371 12:44:38.011718 [ 0.000000] NUMA: No NUMA configuration found
10372 12:44:38.018214 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10373 12:44:38.021659 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10374 12:44:38.025030 [ 0.000000] Zone ranges:
10375 12:44:38.031660 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10376 12:44:38.035022 [ 0.000000] DMA32 empty
10377 12:44:38.041410 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10378 12:44:38.044950 [ 0.000000] Movable zone start for each node
10379 12:44:38.048123 [ 0.000000] Early memory node ranges
10380 12:44:38.055000 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10381 12:44:38.061457 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10382 12:44:38.068110 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10383 12:44:38.074767 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10384 12:44:38.081458 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10385 12:44:38.088103 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10386 12:44:38.143345 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10387 12:44:38.150120 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10388 12:44:38.156599 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10389 12:44:38.160151 [ 0.000000] psci: probing for conduit method from DT.
10390 12:44:38.166492 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10391 12:44:38.169598 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10392 12:44:38.176295 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10393 12:44:38.179650 [ 0.000000] psci: SMC Calling Convention v1.2
10394 12:44:38.186393 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10395 12:44:38.189857 [ 0.000000] Detected VIPT I-cache on CPU0
10396 12:44:38.196325 [ 0.000000] CPU features: detected: GIC system register CPU interface
10397 12:44:38.203030 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10398 12:44:38.209510 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10399 12:44:38.216094 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10400 12:44:38.223045 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10401 12:44:38.232578 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10402 12:44:38.235890 [ 0.000000] alternatives: applying boot alternatives
10403 12:44:38.242821 [ 0.000000] Fallback order for Node 0: 0
10404 12:44:38.249286 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10405 12:44:38.252464 [ 0.000000] Policy zone: Normal
10406 12:44:38.276042 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12703562/extract-nfsrootfs-3xh3n14o,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10407 12:44:38.285626 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10408 12:44:38.296362 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10409 12:44:38.306332 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10410 12:44:38.313244 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10411 12:44:38.316297 <6>[ 0.000000] software IO TLB: area num 8.
10412 12:44:38.372983 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10413 12:44:38.522159 <6>[ 0.000000] Memory: 7948928K/8385536K available (17984K kernel code, 4118K rwdata, 19612K rodata, 8448K init, 616K bss, 403840K reserved, 32768K cma-reserved)
10414 12:44:38.528590 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10415 12:44:38.535513 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10416 12:44:38.538390 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10417 12:44:38.545310 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10418 12:44:38.551636 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10419 12:44:38.555087 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10420 12:44:38.564815 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10421 12:44:38.571145 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10422 12:44:38.578015 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10423 12:44:38.585056 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10424 12:44:38.587896 <6>[ 0.000000] GICv3: 608 SPIs implemented
10425 12:44:38.591568 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10426 12:44:38.597840 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10427 12:44:38.601058 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10428 12:44:38.608056 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10429 12:44:38.621428 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10430 12:44:38.634634 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10431 12:44:38.641270 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10432 12:44:38.648345 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10433 12:44:38.661833 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10434 12:44:38.668560 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10435 12:44:38.675403 <6>[ 0.009183] Console: colour dummy device 80x25
10436 12:44:38.685256 <6>[ 0.013909] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10437 12:44:38.691928 <6>[ 0.024350] pid_max: default: 32768 minimum: 301
10438 12:44:38.694843 <6>[ 0.029252] LSM: Security Framework initializing
10439 12:44:38.701665 <6>[ 0.034192] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10440 12:44:38.711452 <6>[ 0.042005] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10441 12:44:38.718250 <6>[ 0.051469] cblist_init_generic: Setting adjustable number of callback queues.
10442 12:44:38.724683 <6>[ 0.058960] cblist_init_generic: Setting shift to 3 and lim to 1.
10443 12:44:38.734776 <6>[ 0.065299] cblist_init_generic: Setting adjustable number of callback queues.
10444 12:44:38.741330 <6>[ 0.072773] cblist_init_generic: Setting shift to 3 and lim to 1.
10445 12:44:38.744793 <6>[ 0.079174] rcu: Hierarchical SRCU implementation.
10446 12:44:38.751128 <6>[ 0.084190] rcu: Max phase no-delay instances is 1000.
10447 12:44:38.757641 <6>[ 0.091224] EFI services will not be available.
10448 12:44:38.761132 <6>[ 0.096187] smp: Bringing up secondary CPUs ...
10449 12:44:38.769622 <6>[ 0.101238] Detected VIPT I-cache on CPU1
10450 12:44:38.775997 <6>[ 0.101307] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10451 12:44:38.782610 <6>[ 0.101339] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10452 12:44:38.786160 <6>[ 0.101683] Detected VIPT I-cache on CPU2
10453 12:44:38.793009 <6>[ 0.101736] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10454 12:44:38.799069 <6>[ 0.101753] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10455 12:44:38.806110 <6>[ 0.102016] Detected VIPT I-cache on CPU3
10456 12:44:38.812680 <6>[ 0.102063] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10457 12:44:38.819290 <6>[ 0.102078] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10458 12:44:38.822788 <6>[ 0.102384] CPU features: detected: Spectre-v4
10459 12:44:38.829157 <6>[ 0.102390] CPU features: detected: Spectre-BHB
10460 12:44:38.832433 <6>[ 0.102395] Detected PIPT I-cache on CPU4
10461 12:44:38.839351 <6>[ 0.102453] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10462 12:44:38.845995 <6>[ 0.102470] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10463 12:44:38.852331 <6>[ 0.102763] Detected PIPT I-cache on CPU5
10464 12:44:38.858664 <6>[ 0.102824] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10465 12:44:38.865237 <6>[ 0.102841] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10466 12:44:38.868744 <6>[ 0.103124] Detected PIPT I-cache on CPU6
10467 12:44:38.875199 <6>[ 0.103188] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10468 12:44:38.882248 <6>[ 0.103204] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10469 12:44:38.888252 <6>[ 0.103504] Detected PIPT I-cache on CPU7
10470 12:44:38.895038 <6>[ 0.103569] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10471 12:44:38.901665 <6>[ 0.103586] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10472 12:44:38.905043 <6>[ 0.103634] smp: Brought up 1 node, 8 CPUs
10473 12:44:38.911671 <6>[ 0.244999] SMP: Total of 8 processors activated.
10474 12:44:38.914820 <6>[ 0.249920] CPU features: detected: 32-bit EL0 Support
10475 12:44:38.925114 <6>[ 0.255283] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10476 12:44:38.931586 <6>[ 0.264137] CPU features: detected: Common not Private translations
10477 12:44:38.937856 <6>[ 0.270653] CPU features: detected: CRC32 instructions
10478 12:44:38.941159 <6>[ 0.276005] CPU features: detected: RCpc load-acquire (LDAPR)
10479 12:44:38.948306 <6>[ 0.281965] CPU features: detected: LSE atomic instructions
10480 12:44:38.954825 <6>[ 0.287782] CPU features: detected: Privileged Access Never
10481 12:44:38.961223 <6>[ 0.293561] CPU features: detected: RAS Extension Support
10482 12:44:38.967958 <6>[ 0.299170] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10483 12:44:38.971120 <6>[ 0.306389] CPU: All CPU(s) started at EL2
10484 12:44:38.978126 <6>[ 0.310706] alternatives: applying system-wide alternatives
10485 12:44:38.987180 <6>[ 0.321420] devtmpfs: initialized
10486 12:44:39.002907 <6>[ 0.330472] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10487 12:44:39.009336 <6>[ 0.340431] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10488 12:44:39.016199 <6>[ 0.348455] pinctrl core: initialized pinctrl subsystem
10489 12:44:39.019837 <6>[ 0.355083] DMI not present or invalid.
10490 12:44:39.026377 <6>[ 0.359493] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10491 12:44:39.036153 <6>[ 0.366372] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10492 12:44:39.042508 <6>[ 0.373961] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10493 12:44:39.052335 <6>[ 0.382171] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10494 12:44:39.056015 <6>[ 0.390416] audit: initializing netlink subsys (disabled)
10495 12:44:39.065618 <5>[ 0.396105] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10496 12:44:39.072276 <6>[ 0.396804] thermal_sys: Registered thermal governor 'step_wise'
10497 12:44:39.078725 <6>[ 0.404075] thermal_sys: Registered thermal governor 'power_allocator'
10498 12:44:39.082349 <6>[ 0.410329] cpuidle: using governor menu
10499 12:44:39.089311 <6>[ 0.421288] NET: Registered PF_QIPCRTR protocol family
10500 12:44:39.095410 <6>[ 0.426768] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10501 12:44:39.098676 <6>[ 0.433873] ASID allocator initialised with 32768 entries
10502 12:44:39.106165 <6>[ 0.440424] Serial: AMBA PL011 UART driver
10503 12:44:39.114845 <4>[ 0.449157] Trying to register duplicate clock ID: 134
10504 12:44:39.169264 <6>[ 0.506531] KASLR enabled
10505 12:44:39.183549 <6>[ 0.514269] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10506 12:44:39.189993 <6>[ 0.521284] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10507 12:44:39.196624 <6>[ 0.527773] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10508 12:44:39.203521 <6>[ 0.534780] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10509 12:44:39.210075 <6>[ 0.541267] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10510 12:44:39.216685 <6>[ 0.548271] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10511 12:44:39.223542 <6>[ 0.554757] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10512 12:44:39.229641 <6>[ 0.561761] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10513 12:44:39.232792 <6>[ 0.569297] ACPI: Interpreter disabled.
10514 12:44:39.241589 <6>[ 0.575726] iommu: Default domain type: Translated
10515 12:44:39.247948 <6>[ 0.580837] iommu: DMA domain TLB invalidation policy: strict mode
10516 12:44:39.251403 <5>[ 0.587504] SCSI subsystem initialized
10517 12:44:39.257816 <6>[ 0.591675] usbcore: registered new interface driver usbfs
10518 12:44:39.264572 <6>[ 0.597409] usbcore: registered new interface driver hub
10519 12:44:39.268071 <6>[ 0.602960] usbcore: registered new device driver usb
10520 12:44:39.274494 <6>[ 0.609059] pps_core: LinuxPPS API ver. 1 registered
10521 12:44:39.285105 <6>[ 0.614255] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10522 12:44:39.288619 <6>[ 0.623602] PTP clock support registered
10523 12:44:39.291659 <6>[ 0.627847] EDAC MC: Ver: 3.0.0
10524 12:44:39.299152 <6>[ 0.633005] FPGA manager framework
10525 12:44:39.305384 <6>[ 0.636687] Advanced Linux Sound Architecture Driver Initialized.
10526 12:44:39.308808 <6>[ 0.643469] vgaarb: loaded
10527 12:44:39.315284 <6>[ 0.646627] clocksource: Switched to clocksource arch_sys_counter
10528 12:44:39.318734 <5>[ 0.653069] VFS: Disk quotas dquot_6.6.0
10529 12:44:39.325292 <6>[ 0.657255] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10530 12:44:39.328519 <6>[ 0.664446] pnp: PnP ACPI: disabled
10531 12:44:39.337135 <6>[ 0.671117] NET: Registered PF_INET protocol family
10532 12:44:39.346581 <6>[ 0.676711] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10533 12:44:39.358072 <6>[ 0.689046] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10534 12:44:39.368300 <6>[ 0.697865] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10535 12:44:39.374205 <6>[ 0.705836] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10536 12:44:39.384767 <6>[ 0.714535] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10537 12:44:39.391345 <6>[ 0.724293] TCP: Hash tables configured (established 65536 bind 65536)
10538 12:44:39.397882 <6>[ 0.731158] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10539 12:44:39.407736 <6>[ 0.738358] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10540 12:44:39.410984 <6>[ 0.746065] NET: Registered PF_UNIX/PF_LOCAL protocol family
10541 12:44:39.418364 <6>[ 0.752221] RPC: Registered named UNIX socket transport module.
10542 12:44:39.424436 <6>[ 0.758376] RPC: Registered udp transport module.
10543 12:44:39.428331 <6>[ 0.763306] RPC: Registered tcp transport module.
10544 12:44:39.434808 <6>[ 0.768240] RPC: Registered tcp NFSv4.1 backchannel transport module.
10545 12:44:39.441467 <6>[ 0.774908] PCI: CLS 0 bytes, default 64
10546 12:44:39.444303 <6>[ 0.779239] Unpacking initramfs...
10547 12:44:39.467661 <6>[ 0.798733] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10548 12:44:39.478274 <6>[ 0.807380] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10549 12:44:39.481319 <6>[ 0.816231] kvm [1]: IPA Size Limit: 40 bits
10550 12:44:39.487704 <6>[ 0.820761] kvm [1]: GICv3: no GICV resource entry
10551 12:44:39.490988 <6>[ 0.825783] kvm [1]: disabling GICv2 emulation
10552 12:44:39.497620 <6>[ 0.830471] kvm [1]: GIC system register CPU interface enabled
10553 12:44:39.501079 <6>[ 0.836628] kvm [1]: vgic interrupt IRQ18
10554 12:44:39.507921 <6>[ 0.840988] kvm [1]: VHE mode initialized successfully
10555 12:44:39.514423 <5>[ 0.847462] Initialise system trusted keyrings
10556 12:44:39.521073 <6>[ 0.852315] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10557 12:44:39.528178 <6>[ 0.862339] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10558 12:44:39.534622 <5>[ 0.868734] NFS: Registering the id_resolver key type
10559 12:44:39.538174 <5>[ 0.874036] Key type id_resolver registered
10560 12:44:39.544537 <5>[ 0.878451] Key type id_legacy registered
10561 12:44:39.551073 <6>[ 0.882732] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10562 12:44:39.557888 <6>[ 0.889653] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10563 12:44:39.563940 <6>[ 0.897353] 9p: Installing v9fs 9p2000 file system support
10564 12:44:39.601361 <5>[ 0.935076] Key type asymmetric registered
10565 12:44:39.604546 <5>[ 0.939406] Asymmetric key parser 'x509' registered
10566 12:44:39.614407 <6>[ 0.944541] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10567 12:44:39.617253 <6>[ 0.952156] io scheduler mq-deadline registered
10568 12:44:39.620972 <6>[ 0.956933] io scheduler kyber registered
10569 12:44:39.639129 <6>[ 0.973810] EINJ: ACPI disabled.
10570 12:44:39.671412 <4>[ 0.999200] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10571 12:44:39.681052 <4>[ 1.009840] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10572 12:44:39.696421 <6>[ 1.030411] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10573 12:44:39.704272 <6>[ 1.038393] printk: console [ttyS0] disabled
10574 12:44:39.732228 <6>[ 1.063018] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10575 12:44:39.738541 <6>[ 1.072503] printk: console [ttyS0] enabled
10576 12:44:39.742366 <6>[ 1.072503] printk: console [ttyS0] enabled
10577 12:44:39.748664 <6>[ 1.081398] printk: bootconsole [mtk8250] disabled
10578 12:44:39.752123 <6>[ 1.081398] printk: bootconsole [mtk8250] disabled
10579 12:44:39.758363 <6>[ 1.092394] SuperH (H)SCI(F) driver initialized
10580 12:44:39.761775 <6>[ 1.097674] msm_serial: driver initialized
10581 12:44:39.775626 <6>[ 1.106552] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10582 12:44:39.785719 <6>[ 1.115098] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10583 12:44:39.792222 <6>[ 1.123640] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10584 12:44:39.802456 <6>[ 1.132269] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10585 12:44:39.808970 <6>[ 1.140977] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10586 12:44:39.818927 <6>[ 1.149696] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10587 12:44:39.828817 <6>[ 1.158237] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10588 12:44:39.835400 <6>[ 1.167051] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10589 12:44:39.845183 <6>[ 1.175593] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10590 12:44:39.856781 <6>[ 1.190964] loop: module loaded
10591 12:44:39.863585 <6>[ 1.197006] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10592 12:44:39.885791 <4>[ 1.220008] mtk-pmic-keys: Failed to locate of_node [id: -1]
10593 12:44:39.892496 <6>[ 1.226753] megasas: 07.719.03.00-rc1
10594 12:44:39.901600 <6>[ 1.236297] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10595 12:44:39.916016 <6>[ 1.250002] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10596 12:44:39.932461 <6>[ 1.266725] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10597 12:44:39.988974 <6>[ 1.316763] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10598 12:44:40.237080 <6>[ 1.571877] Freeing initrd memory: 18324K
10599 12:44:40.248858 <6>[ 1.583578] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10600 12:44:40.259818 <6>[ 1.594472] tun: Universal TUN/TAP device driver, 1.6
10601 12:44:40.263309 <6>[ 1.600532] thunder_xcv, ver 1.0
10602 12:44:40.266648 <6>[ 1.604036] thunder_bgx, ver 1.0
10603 12:44:40.269950 <6>[ 1.607529] nicpf, ver 1.0
10604 12:44:40.280769 <6>[ 1.611539] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10605 12:44:40.283763 <6>[ 1.619016] hns3: Copyright (c) 2017 Huawei Corporation.
10606 12:44:40.287404 <6>[ 1.624602] hclge is initializing
10607 12:44:40.293583 <6>[ 1.628183] e1000: Intel(R) PRO/1000 Network Driver
10608 12:44:40.300549 <6>[ 1.633313] e1000: Copyright (c) 1999-2006 Intel Corporation.
10609 12:44:40.304031 <6>[ 1.639325] e1000e: Intel(R) PRO/1000 Network Driver
10610 12:44:40.310201 <6>[ 1.644540] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10611 12:44:40.316847 <6>[ 1.650728] igb: Intel(R) Gigabit Ethernet Network Driver
10612 12:44:40.323649 <6>[ 1.656378] igb: Copyright (c) 2007-2014 Intel Corporation.
10613 12:44:40.330532 <6>[ 1.662214] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10614 12:44:40.337219 <6>[ 1.668731] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10615 12:44:40.340445 <6>[ 1.675192] sky2: driver version 1.30
10616 12:44:40.346572 <6>[ 1.680167] VFIO - User Level meta-driver version: 0.3
10617 12:44:40.353989 <6>[ 1.688387] usbcore: registered new interface driver usb-storage
10618 12:44:40.360751 <6>[ 1.694834] usbcore: registered new device driver onboard-usb-hub
10619 12:44:40.369472 <6>[ 1.703962] mt6397-rtc mt6359-rtc: registered as rtc0
10620 12:44:40.379569 <6>[ 1.709427] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-05T12:44:40 UTC (1707137080)
10621 12:44:40.382900 <6>[ 1.718995] i2c_dev: i2c /dev entries driver
10622 12:44:40.399538 <6>[ 1.730587] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10623 12:44:40.419440 <6>[ 1.753565] cpu cpu0: EM: created perf domain
10624 12:44:40.422439 <6>[ 1.758501] cpu cpu4: EM: created perf domain
10625 12:44:40.429916 <6>[ 1.764084] sdhci: Secure Digital Host Controller Interface driver
10626 12:44:40.436392 <6>[ 1.770519] sdhci: Copyright(c) Pierre Ossman
10627 12:44:40.442928 <6>[ 1.775477] Synopsys Designware Multimedia Card Interface Driver
10628 12:44:40.449781 <6>[ 1.782111] sdhci-pltfm: SDHCI platform and OF driver helper
10629 12:44:40.452936 <6>[ 1.782231] mmc0: CQHCI version 5.10
10630 12:44:40.459313 <6>[ 1.792129] ledtrig-cpu: registered to indicate activity on CPUs
10631 12:44:40.466238 <6>[ 1.799096] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10632 12:44:40.472948 <6>[ 1.806145] usbcore: registered new interface driver usbhid
10633 12:44:40.476550 <6>[ 1.811965] usbhid: USB HID core driver
10634 12:44:40.482815 <6>[ 1.816153] spi_master spi0: will run message pump with realtime priority
10635 12:44:40.527519 <6>[ 1.854788] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10636 12:44:40.546311 <6>[ 1.870613] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10637 12:44:40.550140 <6>[ 1.884261] mmc0: Command Queue Engine enabled
10638 12:44:40.556298 <6>[ 1.889047] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10639 12:44:40.562927 <6>[ 1.895984] cros-ec-spi spi0.0: Chrome EC device registered
10640 12:44:40.566692 <6>[ 1.896365] mmcblk0: mmc0:0001 DA4128 116 GiB
10641 12:44:40.576270 <6>[ 1.911051] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10642 12:44:40.583766 <6>[ 1.918486] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10643 12:44:40.590773 <6>[ 1.924403] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10644 12:44:40.597459 <6>[ 1.930320] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10645 12:44:40.612656 <6>[ 1.943429] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10646 12:44:40.619783 <6>[ 1.954129] NET: Registered PF_PACKET protocol family
10647 12:44:40.623344 <6>[ 1.959536] 9pnet: Installing 9P2000 support
10648 12:44:40.629659 <5>[ 1.964099] Key type dns_resolver registered
10649 12:44:40.632923 <6>[ 1.969104] registered taskstats version 1
10650 12:44:40.639418 <5>[ 1.973490] Loading compiled-in X.509 certificates
10651 12:44:40.670337 <4>[ 1.998094] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10652 12:44:40.680039 <4>[ 2.009035] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10653 12:44:40.686555 <3>[ 2.019583] debugfs: File 'uA_load' in directory '/' already present!
10654 12:44:40.693457 <3>[ 2.026288] debugfs: File 'min_uV' in directory '/' already present!
10655 12:44:40.699934 <3>[ 2.032902] debugfs: File 'max_uV' in directory '/' already present!
10656 12:44:40.706566 <3>[ 2.039512] debugfs: File 'constraint_flags' in directory '/' already present!
10657 12:44:40.718413 <3>[ 2.049668] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10658 12:44:40.731653 <6>[ 2.065891] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10659 12:44:40.738443 <6>[ 2.072689] xhci-mtk 11200000.usb: xHCI Host Controller
10660 12:44:40.745132 <6>[ 2.078194] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10661 12:44:40.754961 <6>[ 2.086047] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10662 12:44:40.761587 <6>[ 2.095475] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10663 12:44:40.768394 <6>[ 2.101559] xhci-mtk 11200000.usb: xHCI Host Controller
10664 12:44:40.774690 <6>[ 2.107048] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10665 12:44:40.781936 <6>[ 2.114699] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10666 12:44:40.788112 <6>[ 2.122363] hub 1-0:1.0: USB hub found
10667 12:44:40.791464 <6>[ 2.126392] hub 1-0:1.0: 1 port detected
10668 12:44:40.798259 <6>[ 2.130692] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10669 12:44:40.805102 <6>[ 2.139258] hub 2-0:1.0: USB hub found
10670 12:44:40.808726 <6>[ 2.143267] hub 2-0:1.0: 1 port detected
10671 12:44:40.815603 <6>[ 2.150224] mtk-msdc 11f70000.mmc: Got CD GPIO
10672 12:44:40.830464 <6>[ 2.161339] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10673 12:44:40.837208 <6>[ 2.169363] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10674 12:44:40.847210 <4>[ 2.177294] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10675 12:44:40.857162 <6>[ 2.186836] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10676 12:44:40.864087 <6>[ 2.194913] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10677 12:44:40.870453 <6>[ 2.202958] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10678 12:44:40.880836 <6>[ 2.210881] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10679 12:44:40.887055 <6>[ 2.218700] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10680 12:44:40.897097 <6>[ 2.226520] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10681 12:44:40.906675 <6>[ 2.236792] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10682 12:44:40.913418 <6>[ 2.245153] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10683 12:44:40.923643 <6>[ 2.253502] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10684 12:44:40.929965 <6>[ 2.261842] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10685 12:44:40.940106 <6>[ 2.270181] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10686 12:44:40.946814 <6>[ 2.278520] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10687 12:44:40.956478 <6>[ 2.286861] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10688 12:44:40.963183 <6>[ 2.295201] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10689 12:44:40.973422 <6>[ 2.303540] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10690 12:44:40.980128 <6>[ 2.311879] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10691 12:44:40.989772 <6>[ 2.320218] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10692 12:44:40.996305 <6>[ 2.328556] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10693 12:44:41.006349 <6>[ 2.336895] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10694 12:44:41.013358 <6>[ 2.345233] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10695 12:44:41.023280 <6>[ 2.353571] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10696 12:44:41.029587 <6>[ 2.362319] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10697 12:44:41.036198 <6>[ 2.369542] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10698 12:44:41.042391 <6>[ 2.376311] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10699 12:44:41.049158 <6>[ 2.383154] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10700 12:44:41.055833 <6>[ 2.390152] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10701 12:44:41.065772 <6>[ 2.397017] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10702 12:44:41.075838 <6>[ 2.406155] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10703 12:44:41.085388 <6>[ 2.415274] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10704 12:44:41.095916 <6>[ 2.424568] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10705 12:44:41.105663 <6>[ 2.434035] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10706 12:44:41.112068 <6>[ 2.443501] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10707 12:44:41.122093 <6>[ 2.452621] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10708 12:44:41.131872 <6>[ 2.462086] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10709 12:44:41.141917 <6>[ 2.471204] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10710 12:44:41.151747 <6>[ 2.480499] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10711 12:44:41.161415 <6>[ 2.490659] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10712 12:44:41.171301 <6>[ 2.502100] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10713 12:44:41.178075 <6>[ 2.511667] Trying to probe devices needed for running init ...
10714 12:44:41.215964 <6>[ 2.546902] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10715 12:44:41.370193 <6>[ 2.704965] hub 1-1:1.0: USB hub found
10716 12:44:41.373702 <6>[ 2.709490] hub 1-1:1.0: 4 ports detected
10717 12:44:41.383926 <6>[ 2.718177] hub 1-1:1.0: USB hub found
10718 12:44:41.387529 <6>[ 2.722553] hub 1-1:1.0: 4 ports detected
10719 12:44:41.495842 <6>[ 2.827107] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10720 12:44:41.522053 <6>[ 2.856544] hub 2-1:1.0: USB hub found
10721 12:44:41.525606 <6>[ 2.861065] hub 2-1:1.0: 3 ports detected
10722 12:44:41.534545 <6>[ 2.869071] hub 2-1:1.0: USB hub found
10723 12:44:41.537882 <6>[ 2.873530] hub 2-1:1.0: 3 ports detected
10724 12:44:41.707580 <6>[ 3.038944] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10725 12:44:41.840671 <6>[ 3.174801] hub 1-1.4:1.0: USB hub found
10726 12:44:41.843235 <6>[ 3.179435] hub 1-1.4:1.0: 2 ports detected
10727 12:44:41.852172 <6>[ 3.186806] hub 1-1.4:1.0: USB hub found
10728 12:44:41.855756 <6>[ 3.191402] hub 1-1.4:1.0: 2 ports detected
10729 12:44:41.919275 <6>[ 3.251097] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10730 12:44:42.150883 <6>[ 3.482937] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10731 12:44:42.343205 <6>[ 3.674939] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10732 12:44:53.460181 <6>[ 14.799910] ALSA device list:
10733 12:44:53.466608 <6>[ 14.803200] No soundcards found.
10734 12:44:53.474720 <6>[ 14.811183] Freeing unused kernel memory: 8448K
10735 12:44:53.477811 <6>[ 14.816177] Run /init as init process
10736 12:44:53.489340 Loading, please wait...
10737 12:44:53.514110 Starting systemd-udevd version 252.19-1~deb12u1
10738 12:44:53.746936 <3>[ 15.079622] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10739 12:44:53.753010 <6>[ 15.080214] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10740 12:44:53.763138 <3>[ 15.089731] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10741 12:44:53.766269 <6>[ 15.104104] remoteproc remoteproc0: scp is available
10742 12:44:53.776462 <3>[ 15.104389] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10743 12:44:53.782849 <6>[ 15.108294] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10744 12:44:53.789676 <6>[ 15.109750] remoteproc remoteproc0: powering up scp
10745 12:44:53.796373 <3>[ 15.117915] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10746 12:44:53.803192 <6>[ 15.120194] usbcore: registered new device driver r8152-cfgselector
10747 12:44:53.813433 <6>[ 15.125484] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10748 12:44:53.819882 <3>[ 15.130406] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10749 12:44:53.826321 <6>[ 15.131323] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10750 12:44:53.836570 <6>[ 15.131352] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10751 12:44:53.846543 <6>[ 15.131362] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10752 12:44:53.853372 <4>[ 15.132243] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10753 12:44:53.859547 <4>[ 15.132243] Fallback method does not support PEC.
10754 12:44:53.863069 <6>[ 15.138418] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10755 12:44:53.872784 <4>[ 15.144003] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10756 12:44:53.879475 <3>[ 15.144923] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10757 12:44:53.886090 <3>[ 15.144931] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10758 12:44:53.896420 <3>[ 15.144935] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10759 12:44:53.906277 <3>[ 15.149243] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10760 12:44:53.912796 <3>[ 15.157079] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10761 12:44:53.919515 <4>[ 15.157242] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10762 12:44:53.925652 <6>[ 15.179460] mc: Linux media interface: v0.10
10763 12:44:53.932535 <3>[ 15.183611] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10764 12:44:53.942178 <3>[ 15.188987] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10765 12:44:53.949198 <6>[ 15.251914] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10766 12:44:53.955680 <3>[ 15.254233] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10767 12:44:53.962158 <6>[ 15.261526] pci_bus 0000:00: root bus resource [bus 00-ff]
10768 12:44:53.968994 <3>[ 15.266040] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10769 12:44:53.978454 <6>[ 15.267052] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10770 12:44:53.988689 <6>[ 15.271657] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10771 12:44:53.995179 <6>[ 15.274811] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10772 12:44:54.001734 <6>[ 15.279204] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10773 12:44:54.011881 <6>[ 15.282907] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10774 12:44:54.018209 <3>[ 15.286781] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10775 12:44:54.028126 <3>[ 15.286786] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10776 12:44:54.034819 <3>[ 15.286789] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10777 12:44:54.041645 <3>[ 15.286794] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10778 12:44:54.051387 <3>[ 15.286796] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10779 12:44:54.057938 <3>[ 15.286813] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10780 12:44:54.067838 <6>[ 15.289748] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10781 12:44:54.074460 <6>[ 15.289790] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10782 12:44:54.084515 <4>[ 15.290300] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10783 12:44:54.090738 <4>[ 15.290309] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10784 12:44:54.101029 <6>[ 15.291065] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10785 12:44:54.107366 <6>[ 15.292703] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10786 12:44:54.113841 <6>[ 15.297874] remoteproc remoteproc0: remote processor scp is now up
10787 12:44:54.123872 <6>[ 15.303583] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10788 12:44:54.133790 <6>[ 15.307024] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10789 12:44:54.140582 <6>[ 15.307471] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10790 12:44:54.147442 <6>[ 15.320806] videodev: Linux video capture interface: v2.00
10791 12:44:54.153628 <6>[ 15.329359] pci 0000:00:00.0: supports D1 D2
10792 12:44:54.157012 <6>[ 15.343994] Bluetooth: Core ver 2.22
10793 12:44:54.163570 <6>[ 15.352000] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10794 12:44:54.170123 <6>[ 15.353107] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10795 12:44:54.176925 <6>[ 15.354948] r8152 2-1.3:1.0 eth0: v1.12.13
10796 12:44:54.180168 <6>[ 15.355004] usbcore: registered new interface driver r8152
10797 12:44:54.186813 <6>[ 15.360150] NET: Registered PF_BLUETOOTH protocol family
10798 12:44:54.193487 <6>[ 15.368284] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10799 12:44:54.200119 <6>[ 15.376247] Bluetooth: HCI device and connection manager initialized
10800 12:44:54.203417 <6>[ 15.376269] Bluetooth: HCI socket layer initialized
10801 12:44:54.213400 <6>[ 15.384351] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10802 12:44:54.216670 <6>[ 15.384551] usbcore: registered new interface driver cdc_ether
10803 12:44:54.223065 <6>[ 15.392406] Bluetooth: L2CAP socket layer initialized
10804 12:44:54.229618 <6>[ 15.400494] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10805 12:44:54.236446 <6>[ 15.400835] usbcore: registered new interface driver r8153_ecm
10806 12:44:54.242993 <6>[ 15.402475] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10807 12:44:54.256270 <6>[ 15.403670] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10808 12:44:54.262821 <6>[ 15.403835] usbcore: registered new interface driver uvcvideo
10809 12:44:54.266240 <6>[ 15.410392] Bluetooth: SCO socket layer initialized
10810 12:44:54.276210 <6>[ 15.416793] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10811 12:44:54.282536 <6>[ 15.427337] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10812 12:44:54.285843 <6>[ 15.433878] pci 0000:01:00.0: supports D1 D2
10813 12:44:54.292664 <6>[ 15.434663] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10814 12:44:54.299140 <6>[ 15.483820] usbcore: registered new interface driver btusb
10815 12:44:54.308891 <4>[ 15.485059] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10816 12:44:54.315539 <3>[ 15.485066] Bluetooth: hci0: Failed to load firmware file (-2)
10817 12:44:54.318848 <3>[ 15.485068] Bluetooth: hci0: Failed to set up firmware (-2)
10818 12:44:54.332243 <4>[ 15.485070] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10819 12:44:54.338688 <6>[ 15.489199] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10820 12:44:54.361693 <6>[ 15.694971] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10821 12:44:54.368310 <6>[ 15.701886] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10822 12:44:54.374857 <6>[ 15.709967] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10823 12:44:54.384865 <6>[ 15.717968] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10824 12:44:54.391622 <6>[ 15.725970] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10825 12:44:54.401375 <6>[ 15.733970] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10826 12:44:54.404859 <6>[ 15.741970] pci 0000:00:00.0: PCI bridge to [bus 01]
10827 12:44:54.414901 <6>[ 15.747187] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10828 12:44:54.421392 <6>[ 15.755325] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10829 12:44:54.427649 <6>[ 15.762169] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10830 12:44:54.434402 <6>[ 15.768921] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10831 12:44:54.456045 <5>[ 15.789354] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10832 12:44:54.478099 <5>[ 15.811223] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10833 12:44:54.484728 <5>[ 15.819194] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10834 12:44:54.494503 <4>[ 15.827699] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10835 12:44:54.501268 <6>[ 15.836605] cfg80211: failed to load regulatory.db
10836 12:44:54.553058 <6>[ 15.886193] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10837 12:44:54.559420 <6>[ 15.893737] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10838 12:44:54.584034 <6>[ 15.920727] mt7921e 0000:01:00.0: ASIC revision: 79610010
10839 12:44:54.685570 <6>[ 16.019060] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10840 12:44:54.688743 <6>[ 16.019060]
10841 12:44:54.711094 Begin: Loading essential drivers ... done.
10842 12:44:54.714146 Begin: Running /scripts/init-premount ... done.
10843 12:44:54.720819 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10844 12:44:54.730784 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10845 12:44:54.734229 Device /sys/class/net/enx0024323078ff found
10846 12:44:54.734312 done.
10847 12:44:54.740719 Begin: Waiting up to 180 secs for any network device to become available ... done.
10848 12:44:54.789471 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10849 12:44:54.954271 <6>[ 16.287470] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10850 12:44:55.588429 <6>[ 16.925351] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10851 12:44:55.826242 <6>[ 17.162802] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10852 12:44:55.872610 IP-Config: no response after 2 secs - giving up
10853 12:44:55.913197 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10854 12:44:55.946077 IP-Config: wlp1s0 hardware address d8:f3:bc:78:28:07 mtu 1500 DHCP
10855 12:44:56.655634 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10856 12:44:56.662050 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10857 12:44:56.668540 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10858 12:44:56.675072 host : mt8192-asurada-spherion-r0-cbg-8
10859 12:44:56.681816 domain : lava-rack
10860 12:44:56.685158 rootserver: 192.168.201.1 rootpath:
10861 12:44:56.688588 filename :
10862 12:44:56.789171 done.
10863 12:44:56.796695 Begin: Running /scripts/nfs-bottom ... done.
10864 12:44:56.809811 Begin: Running /scripts/init-bottom ... done.
10865 12:44:58.154029 <6>[ 19.490987] NET: Registered PF_INET6 protocol family
10866 12:44:58.163368 <6>[ 19.500227] Segment Routing with IPv6
10867 12:44:58.166658 <6>[ 19.504194] In-situ OAM (IOAM) with IPv6
10868 12:44:58.371062 <30>[ 19.681465] systemd[1]: systemd 252.19-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10869 12:44:58.377511 <30>[ 19.714611] systemd[1]: Detected architecture arm64.
10870 12:44:58.393737
10871 12:44:58.397310 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10872 12:44:58.397416
10873 12:44:58.419444 <30>[ 19.756632] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10874 12:44:59.537663 <30>[ 20.871630] systemd[1]: Queued start job for default target graphical.target.
10875 12:44:59.573955 <30>[ 20.908048] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10876 12:44:59.580598 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10877 12:44:59.602962 <30>[ 20.936774] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10878 12:44:59.612631 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10879 12:44:59.630802 <30>[ 20.964655] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10880 12:44:59.640509 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10881 12:44:59.658618 <30>[ 20.992294] systemd[1]: Created slice user.slice - User and Session Slice.
10882 12:44:59.664654 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10883 12:44:59.689340 <30>[ 21.019794] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10884 12:44:59.695939 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10885 12:44:59.716818 <30>[ 21.047157] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10886 12:44:59.723012 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10887 12:44:59.751546 <30>[ 21.075578] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10888 12:44:59.761881 <30>[ 21.095581] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10889 12:44:59.768216 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10890 12:44:59.789662 <30>[ 21.123423] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10891 12:44:59.799270 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10892 12:44:59.814116 <30>[ 21.151404] systemd[1]: Reached target paths.target - Path Units.
10893 12:44:59.821083 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10894 12:44:59.841433 <30>[ 21.175385] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10895 12:44:59.848086 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10896 12:44:59.861806 <30>[ 21.198910] systemd[1]: Reached target slices.target - Slice Units.
10897 12:44:59.871787 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10898 12:44:59.886387 <30>[ 21.223411] systemd[1]: Reached target swap.target - Swaps.
10899 12:44:59.892871 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10900 12:44:59.913616 <30>[ 21.247361] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10901 12:44:59.923184 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10902 12:44:59.941677 <30>[ 21.275386] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10903 12:44:59.951277 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10904 12:44:59.972915 <30>[ 21.306601] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10905 12:44:59.982606 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10906 12:44:59.998592 <30>[ 21.332439] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10907 12:45:00.008669 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10908 12:45:00.026067 <30>[ 21.359680] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10909 12:45:00.032897 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10910 12:45:00.051357 <30>[ 21.384616] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10911 12:45:00.061011 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10912 12:45:00.080696 <30>[ 21.414159] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10913 12:45:00.090432 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10914 12:45:00.105893 <30>[ 21.439403] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10915 12:45:00.115831 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10916 12:45:00.157362 <30>[ 21.491013] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10917 12:45:00.163896 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10918 12:45:00.186285 <30>[ 21.519841] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10919 12:45:00.192844 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10920 12:45:00.218631 <30>[ 21.552300] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10921 12:45:00.224961 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10922 12:45:00.251819 <30>[ 21.579133] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10923 12:45:00.297694 <30>[ 21.631730] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10924 12:45:00.307556 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10925 12:45:00.330235 <30>[ 21.664318] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10926 12:45:00.336709 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10927 12:45:00.362305 <30>[ 21.696305] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10928 12:45:00.368906 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10929 12:45:00.406974 <6>[ 21.741110] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10930 12:45:00.417769 <30>[ 21.751432] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10931 12:45:00.424028 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10932 12:45:00.447237 <30>[ 21.781133] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10933 12:45:00.457061 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10934 12:45:00.497346 <30>[ 21.831495] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10935 12:45:00.504081 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10936 12:45:00.531090 <30>[ 21.864743] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10937 12:45:00.537322 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10938 12:45:00.559798 <6>[ 21.896971] fuse: init (API version 7.37)
10939 12:45:00.566169 <30>[ 21.899316] systemd[1]: Starting systemd-journald.service - Journal Service...
10940 12:45:00.572816 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10941 12:45:00.606918 <30>[ 21.940782] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10942 12:45:00.613398 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10943 12:45:00.672926 <30>[ 22.003627] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10944 12:45:00.679653 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10945 12:45:00.700692 <30>[ 22.034550] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10946 12:45:00.710165 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10947 12:45:00.733832 <30>[ 22.067421] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10948 12:45:00.744034 <3>[ 22.070671] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10949 12:45:00.750756 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10950 12:45:00.771834 <3>[ 22.105655] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10951 12:45:00.778477 <30>[ 22.106982] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10952 12:45:00.788330 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10953 12:45:00.805425 <30>[ 22.139356] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10954 12:45:00.812244 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10955 12:45:00.823667 <3>[ 22.157489] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 12:45:00.833260 <30>[ 22.166772] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10957 12:45:00.840266 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10958 12:45:00.852257 <3>[ 22.186459] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 12:45:00.862220 <30>[ 22.196141] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10960 12:45:00.873022 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10961 12:45:00.883540 <3>[ 22.217527] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 12:45:00.893555 <30>[ 22.227454] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10963 12:45:00.900710 <30>[ 22.235225] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10964 12:45:00.914615 [[0;32m OK [0m] Finished [0;1;39mmodprobe@c<3>[ 22.246782] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10965 12:45:00.917819 onfigfs…[0m - Load Kernel Module configfs.
10966 12:45:00.941788 <30>[ 22.275946] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10967 12:45:00.951733 <3>[ 22.283769] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10968 12:45:00.958404 <30>[ 22.283843] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10969 12:45:00.968145 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10970 12:45:00.982528 <30>[ 22.319674] systemd[1]: modprobe@drm.service: Deactivated successfully.
10971 12:45:00.992888 <3>[ 22.320830] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10972 12:45:00.999161 <30>[ 22.327110] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10973 12:45:01.009458 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10974 12:45:01.026119 <30>[ 22.360129] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10975 12:45:01.032775 <3>[ 22.362950] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10976 12:45:01.042509 <30>[ 22.368572] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10977 12:45:01.052824 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10978 12:45:01.063551 <3>[ 22.397649] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10979 12:45:01.074582 <30>[ 22.408697] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10980 12:45:01.081395 <30>[ 22.416276] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10981 12:45:01.088708 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10982 12:45:01.107703 <30>[ 22.444343] systemd[1]: modprobe@loop.service: Deactivated successfully.
10983 12:45:01.118830 <30>[ 22.452447] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10984 12:45:01.124892 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10985 12:45:01.146318 <30>[ 22.479526] systemd[1]: Started systemd-journald.service - Journal Service.
10986 12:45:01.166368 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0<4>[ 22.492058] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10987 12:45:01.173147 <3>[ 22.508395] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10988 12:45:01.176381 m - Journal Service.
10989 12:45:01.198645 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10990 12:45:01.219174 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10991 12:45:01.238396 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10992 12:45:01.258502 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10993 12:45:01.279928 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10994 12:45:01.337909 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10995 12:45:01.359501 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10996 12:45:01.384217 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10997 12:45:01.410735 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10998 12:45:01.435516 <46>[ 22.769655] systemd-journald[310]: Received client request to flush runtime journal.
10999 12:45:01.442200 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11000 12:45:01.474462 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11001 12:45:01.772326 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11002 12:45:01.789790 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11003 12:45:01.810897 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11004 12:45:02.220798 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11005 12:45:02.577991 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11006 12:45:02.625942 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11007 12:45:02.868897 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11008 12:45:02.983357 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11009 12:45:03.001187 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11010 12:45:03.017074 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11011 12:45:03.057123 Starting [0;1;39msystemd-binfmt.se…et Up Additional Binary Formats...
11012 12:45:03.077398 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11013 12:45:03.098587 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11014 12:45:03.124680 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-bi… Set Up Additional Binary Formats.
11015 12:45:03.137760 See 'systemctl status systemd-binfmt.service' for details.
11016 12:45:03.385422 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11017 12:45:03.460645 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11018 12:45:03.526951 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11019 12:45:03.821975 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11020 12:45:03.874776 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11021 12:45:03.895829 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11022 12:45:03.941400 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11023 12:45:04.029801 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11024 12:45:04.053400 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11025 12:45:04.074545 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11026 12:45:04.094639 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11027 12:45:04.185462 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11028 12:45:04.205865 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11029 12:45:04.226462 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11030 12:45:04.294021 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11031 12:45:04.313720 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11032 12:45:04.333344 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11033 12:45:04.353175 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11034 12:45:04.368723 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11035 12:45:04.392223 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11036 12:45:04.430478 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11037 12:45:04.449060 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11038 12:45:04.468434 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11039 12:45:04.488734 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11040 12:45:04.504438 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11041 12:45:04.523120 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11042 12:45:04.540697 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11043 12:45:04.557110 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11044 12:45:04.602389 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11045 12:45:04.636468 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11046 12:45:04.701318 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11047 12:45:04.727063 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11048 12:45:04.745529 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11049 12:45:04.907832 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11050 12:45:04.960266 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11051 12:45:05.024018 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11052 12:45:05.043960 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11053 12:45:05.062782 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11054 12:45:05.095925 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11055 12:45:05.115400 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11056 12:45:05.144656 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11057 12:45:05.162452 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11058 12:45:05.236812 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11059 12:45:05.262103 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11060 12:45:05.312699 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11061 12:45:05.382398 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11062 12:45:05.463457
11063 12:45:05.463572
11064 12:45:05.466466 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11065 12:45:05.466550
11066 12:45:05.469885 debian-bookworm-arm64 login: root (automatic login)
11067 12:45:05.469968
11068 12:45:05.470034
11069 12:45:05.766033 Linux debian-bookworm-arm64 6.1.75-cip14 #1 SMP PREEMPT Mon Feb 5 12:20:06 UTC 2024 aarch64
11070 12:45:05.766174
11071 12:45:05.772480 The programs included with the Debian GNU/Linux system are free software;
11072 12:45:05.778988 the exact distribution terms for each program are described in the
11073 12:45:05.782457 individual files in /usr/share/doc/*/copyright.
11074 12:45:05.782566
11075 12:45:05.789040 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11076 12:45:05.792330 permitted by applicable law.
11077 12:45:06.855358 Matched prompt #10: / #
11079 12:45:06.855627 Setting prompt string to ['/ #']
11080 12:45:06.855721 end: 2.2.5.1 login-action (duration 00:00:29) [common]
11082 12:45:06.855915 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
11083 12:45:06.856000 start: 2.2.6 expect-shell-connection (timeout 00:03:17) [common]
11084 12:45:06.856070 Setting prompt string to ['/ #']
11085 12:45:06.856131 Forcing a shell prompt, looking for ['/ #']
11087 12:45:06.906432 / #
11088 12:45:06.906644 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11089 12:45:06.906756 Waiting using forced prompt support (timeout 00:02:30)
11090 12:45:06.912038
11091 12:45:06.912458 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11092 12:45:06.912607 start: 2.2.7 export-device-env (timeout 00:03:17) [common]
11094 12:45:07.013385 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12703562/extract-nfsrootfs-3xh3n14o'
11095 12:45:07.019889 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12703562/extract-nfsrootfs-3xh3n14o'
11097 12:45:07.121736 / # export NFS_SERVER_IP='192.168.201.1'
11098 12:45:07.127037 export NFS_SERVER_IP='192.168.201.1'
11099 12:45:07.127485 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11100 12:45:07.127667 end: 2.2 depthcharge-retry (duration 00:01:44) [common]
11101 12:45:07.127829 end: 2 depthcharge-action (duration 00:01:44) [common]
11102 12:45:07.127986 start: 3 lava-test-retry (timeout 00:07:31) [common]
11103 12:45:07.128135 start: 3.1 lava-test-shell (timeout 00:07:31) [common]
11104 12:45:07.128262 Using namespace: common
11106 12:45:07.229085 / # #
11107 12:45:07.229774 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11108 12:45:07.235140 #
11109 12:45:07.236074 Using /lava-12703562
11111 12:45:07.337410 / # export SHELL=/bin/bash
11112 12:45:07.344476 export SHELL=/bin/bash
11114 12:45:07.446234 / # . /lava-12703562/environment
11115 12:45:07.452670 . /lava-12703562/environment
11117 12:45:07.561615 / # /lava-12703562/bin/lava-test-runner /lava-12703562/0
11118 12:45:07.562269 Test shell timeout: 10s (minimum of the action and connection timeout)
11119 12:45:07.568034 /lava-12703562/bin/lava-test-runner /lava-12703562/0
11120 12:45:07.905963 + export TESTRUN_ID=0_timesync-off
11121 12:45:07.908941 + TESTRUN_ID=0_timesync-off
11122 12:45:07.912312 + cd /lava-12703562/0/tests/0_timesync-off
11123 12:45:07.915491 ++ cat uuid
11124 12:45:07.925699 + UUID=12703562_1.6.2.3.1
11125 12:45:07.926089 + set +x
11126 12:45:07.932399 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12703562_1.6.2.3.1>
11127 12:45:07.933054 Received signal: <STARTRUN> 0_timesync-off 12703562_1.6.2.3.1
11128 12:45:07.933462 Starting test lava.0_timesync-off (12703562_1.6.2.3.1)
11129 12:45:07.934028 Skipping test definition patterns.
11130 12:45:07.935542 + systemctl stop systemd-timesyncd
11131 12:45:08.033649 + set +x
11132 12:45:08.037212 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12703562_1.6.2.3.1>
11133 12:45:08.037927 Received signal: <ENDRUN> 0_timesync-off 12703562_1.6.2.3.1
11134 12:45:08.038442 Ending use of test pattern.
11135 12:45:08.038768 Ending test lava.0_timesync-off (12703562_1.6.2.3.1), duration 0.11
11137 12:45:08.144995 + export TESTRUN_ID=1_kselftest-alsa
11138 12:45:08.148105 + TESTRUN_ID=1_kselftest-alsa
11139 12:45:08.154999 + cd /lava-12703562/0/tests/1_kselftest-alsa
11140 12:45:08.155541 ++ cat uuid
11141 12:45:08.164931 + UUID=12703562_1.6.2.3.5
11142 12:45:08.165389 + set +x
11143 12:45:08.171496 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 12703562_1.6.2.3.5>
11144 12:45:08.172291 Received signal: <STARTRUN> 1_kselftest-alsa 12703562_1.6.2.3.5
11145 12:45:08.172674 Starting test lava.1_kselftest-alsa (12703562_1.6.2.3.5)
11146 12:45:08.173126 Skipping test definition patterns.
11147 12:45:08.174909 + cd ./automated/linux/kselftest/
11148 12:45:08.201406 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11149 12:45:08.262912 INFO: install_deps skipped
11150 12:45:08.798893 --2024-02-05 12:45:08-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11151 12:45:08.805924 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11152 12:45:08.940355 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11153 12:45:09.072079 HTTP request sent, awaiting response... 200 OK
11154 12:45:09.075537 Length: 2966020 (2.8M) [application/octet-stream]
11155 12:45:09.078644 Saving to: 'kselftest.tar.xz'
11156 12:45:09.078724
11157 12:45:09.078810
11158 12:45:09.338159 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11159 12:45:09.602887 kselftest.tar.xz 1%[ ] 47.81K 183KB/s
11160 12:45:09.867391 kselftest.tar.xz 7%[> ] 217.50K 415KB/s
11161 12:45:10.069116 kselftest.tar.xz 30%[=====> ] 892.00K 1.11MB/s
11162 12:45:10.195505 kselftest.tar.xz 52%[=========> ] 1.50M 1.52MB/s
11163 12:45:10.202129 kselftest.tar.xz 100%[===================>] 2.83M 2.55MB/s in 1.1s
11164 12:45:10.202237
11165 12:45:10.460403 2024-02-05 12:45:10 (2.55 MB/s) - 'kselftest.tar.xz' saved [2966020/2966020]
11166 12:45:10.460539
11167 12:45:17.935484 skiplist:
11168 12:45:17.939057 ========================================
11169 12:45:17.942012 ========================================
11170 12:45:18.007877 alsa:mixer-test
11171 12:45:18.033200 ============== Tests to run ===============
11172 12:45:18.036878 alsa:mixer-test
11173 12:45:18.039966 ===========End Tests to run ===============
11174 12:45:18.045715 shardfile-alsa pass
11175 12:45:18.173295 <12>[ 39.512392] kselftest: Running tests in alsa
11176 12:45:18.186683 TAP version 13
11177 12:45:18.203918 1..1
11178 12:45:18.224138 # selftests: alsa: mixer-test
11179 12:45:18.783565 # TAP version 13
11180 12:45:18.784123 # 1..0
11181 12:45:18.790046 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11182 12:45:18.793448 ok 1 selftests: alsa: mixer-test
11183 12:45:19.568688 alsa_mixer-test pass
11184 12:45:19.613953 + ../../utils/send-to-lava.sh ./output/result.txt
11185 12:45:19.715751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
11186 12:45:19.716553 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
11188 12:45:19.785893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11189 12:45:19.786405 + set +x
11190 12:45:19.787021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11192 12:45:19.792558 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 12703562_1.6.2.3.5>
11193 12:45:19.793351 Received signal: <ENDRUN> 1_kselftest-alsa 12703562_1.6.2.3.5
11194 12:45:19.793818 Ending use of test pattern.
11195 12:45:19.794153 Ending test lava.1_kselftest-alsa (12703562_1.6.2.3.5), duration 11.62
11197 12:45:19.795741 <LAVA_TEST_RUNNER EXIT>
11198 12:45:19.796415 ok: lava_test_shell seems to have completed
11199 12:45:19.796930 alsa_mixer-test: pass
shardfile-alsa: pass
11200 12:45:19.797343 end: 3.1 lava-test-shell (duration 00:00:13) [common]
11201 12:45:19.797842 end: 3 lava-test-retry (duration 00:00:13) [common]
11202 12:45:19.798290 start: 4 finalize (timeout 00:07:18) [common]
11203 12:45:19.798747 start: 4.1 power-off (timeout 00:00:30) [common]
11204 12:45:19.799501 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11205 12:45:19.891529 >> Command sent successfully.
11206 12:45:19.897147 Returned 0 in 0 seconds
11207 12:45:19.998196 end: 4.1 power-off (duration 00:00:00) [common]
11209 12:45:19.999968 start: 4.2 read-feedback (timeout 00:07:18) [common]
11210 12:45:20.001645 Listened to connection for namespace 'common' for up to 1s
11211 12:45:21.001715 Finalising connection for namespace 'common'
11212 12:45:21.002374 Disconnecting from shell: Finalise
11213 12:45:21.002775 / #
11214 12:45:21.103689 end: 4.2 read-feedback (duration 00:00:01) [common]
11215 12:45:21.104310 end: 4 finalize (duration 00:00:01) [common]
11216 12:45:21.104884 Cleaning after the job
11217 12:45:21.105348 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703562/tftp-deploy-1njj5dyf/ramdisk
11218 12:45:21.119694 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703562/tftp-deploy-1njj5dyf/kernel
11219 12:45:21.146911 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703562/tftp-deploy-1njj5dyf/dtb
11220 12:45:21.147164 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703562/tftp-deploy-1njj5dyf/nfsrootfs
11221 12:45:21.246143 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703562/tftp-deploy-1njj5dyf/modules
11222 12:45:21.252988 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12703562
11223 12:45:21.894961 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12703562
11224 12:45:21.895140 Job finished correctly