Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 17
- Kernel Errors: 38
1 12:45:07.511002 lava-dispatcher, installed at version: 2024.01
2 12:45:07.511239 start: 0 validate
3 12:45:07.511387 Start time: 2024-02-05 12:45:07.511378+00:00 (UTC)
4 12:45:07.511524 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:45:07.511660 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 12:45:07.777315 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:45:07.777489 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:45:08.041359 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:45:08.041536 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:45:08.333400 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:45:08.333584 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:45:08.596168 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:45:08.596367 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:45:08.861706 validate duration: 1.35
16 12:45:08.862014 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:45:08.862115 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:45:08.862248 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:45:08.862422 Not decompressing ramdisk as can be used compressed.
20 12:45:08.862541 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 12:45:08.862644 saving as /var/lib/lava/dispatcher/tmp/12703557/tftp-deploy-4emrxmv5/ramdisk/initrd.cpio.gz
22 12:45:08.862744 total size: 4665395 (4 MB)
23 12:45:08.864460 progress 0 % (0 MB)
24 12:45:08.866171 progress 5 % (0 MB)
25 12:45:08.867456 progress 10 % (0 MB)
26 12:45:08.868735 progress 15 % (0 MB)
27 12:45:08.870036 progress 20 % (0 MB)
28 12:45:08.871297 progress 25 % (1 MB)
29 12:45:08.872619 progress 30 % (1 MB)
30 12:45:08.873912 progress 35 % (1 MB)
31 12:45:08.875193 progress 40 % (1 MB)
32 12:45:08.876654 progress 45 % (2 MB)
33 12:45:08.877970 progress 50 % (2 MB)
34 12:45:08.879250 progress 55 % (2 MB)
35 12:45:08.880603 progress 60 % (2 MB)
36 12:45:08.881982 progress 65 % (2 MB)
37 12:45:08.883343 progress 70 % (3 MB)
38 12:45:08.884770 progress 75 % (3 MB)
39 12:45:08.886111 progress 80 % (3 MB)
40 12:45:08.887682 progress 85 % (3 MB)
41 12:45:08.889077 progress 90 % (4 MB)
42 12:45:08.890348 progress 95 % (4 MB)
43 12:45:08.891623 progress 100 % (4 MB)
44 12:45:08.891785 4 MB downloaded in 0.03 s (153.21 MB/s)
45 12:45:08.891947 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:45:08.892195 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:45:08.892283 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:45:08.892382 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:45:08.892521 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:45:08.892590 saving as /var/lib/lava/dispatcher/tmp/12703557/tftp-deploy-4emrxmv5/kernel/Image
52 12:45:08.892665 total size: 51534336 (49 MB)
53 12:45:08.892741 No compression specified
54 12:45:08.893870 progress 0 % (0 MB)
55 12:45:08.907573 progress 5 % (2 MB)
56 12:45:08.921521 progress 10 % (4 MB)
57 12:45:08.935185 progress 15 % (7 MB)
58 12:45:08.949123 progress 20 % (9 MB)
59 12:45:08.963014 progress 25 % (12 MB)
60 12:45:08.976662 progress 30 % (14 MB)
61 12:45:08.990433 progress 35 % (17 MB)
62 12:45:09.004252 progress 40 % (19 MB)
63 12:45:09.017902 progress 45 % (22 MB)
64 12:45:09.031836 progress 50 % (24 MB)
65 12:45:09.045528 progress 55 % (27 MB)
66 12:45:09.059426 progress 60 % (29 MB)
67 12:45:09.073455 progress 65 % (31 MB)
68 12:45:09.087085 progress 70 % (34 MB)
69 12:45:09.100846 progress 75 % (36 MB)
70 12:45:09.114626 progress 80 % (39 MB)
71 12:45:09.128235 progress 85 % (41 MB)
72 12:45:09.142050 progress 90 % (44 MB)
73 12:45:09.156011 progress 95 % (46 MB)
74 12:45:09.169372 progress 100 % (49 MB)
75 12:45:09.169636 49 MB downloaded in 0.28 s (177.45 MB/s)
76 12:45:09.169795 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:45:09.170036 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:45:09.170128 start: 1.3 download-retry (timeout 00:10:00) [common]
80 12:45:09.170214 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 12:45:09.170360 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:45:09.170436 saving as /var/lib/lava/dispatcher/tmp/12703557/tftp-deploy-4emrxmv5/dtb/mt8192-asurada-spherion-r0.dtb
83 12:45:09.170498 total size: 47278 (0 MB)
84 12:45:09.170558 No compression specified
85 12:45:09.171732 progress 69 % (0 MB)
86 12:45:09.172016 progress 100 % (0 MB)
87 12:45:09.172175 0 MB downloaded in 0.00 s (26.93 MB/s)
88 12:45:09.172311 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:45:09.172538 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:45:09.172624 start: 1.4 download-retry (timeout 00:10:00) [common]
92 12:45:09.172746 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 12:45:09.172868 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 12:45:09.172940 saving as /var/lib/lava/dispatcher/tmp/12703557/tftp-deploy-4emrxmv5/nfsrootfs/full.rootfs.tar
95 12:45:09.173001 total size: 200813988 (191 MB)
96 12:45:09.173062 Using unxz to decompress xz
97 12:45:09.177274 progress 0 % (0 MB)
98 12:45:09.762243 progress 5 % (9 MB)
99 12:45:10.333217 progress 10 % (19 MB)
100 12:45:10.949089 progress 15 % (28 MB)
101 12:45:11.354831 progress 20 % (38 MB)
102 12:45:11.704196 progress 25 % (47 MB)
103 12:45:12.308595 progress 30 % (57 MB)
104 12:45:12.880844 progress 35 % (67 MB)
105 12:45:13.508176 progress 40 % (76 MB)
106 12:45:14.108384 progress 45 % (86 MB)
107 12:45:14.728779 progress 50 % (95 MB)
108 12:45:15.397987 progress 55 % (105 MB)
109 12:45:16.112856 progress 60 % (114 MB)
110 12:45:16.244103 progress 65 % (124 MB)
111 12:45:16.398146 progress 70 % (134 MB)
112 12:45:16.505319 progress 75 % (143 MB)
113 12:45:16.583926 progress 80 % (153 MB)
114 12:45:16.659555 progress 85 % (162 MB)
115 12:45:16.769236 progress 90 % (172 MB)
116 12:45:17.068353 progress 95 % (181 MB)
117 12:45:17.684674 progress 100 % (191 MB)
118 12:45:17.690315 191 MB downloaded in 8.52 s (22.48 MB/s)
119 12:45:17.690624 end: 1.4.1 http-download (duration 00:00:09) [common]
121 12:45:17.691037 end: 1.4 download-retry (duration 00:00:09) [common]
122 12:45:17.691163 start: 1.5 download-retry (timeout 00:09:51) [common]
123 12:45:17.691288 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 12:45:17.691481 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:45:17.691582 saving as /var/lib/lava/dispatcher/tmp/12703557/tftp-deploy-4emrxmv5/modules/modules.tar
126 12:45:17.691678 total size: 8639964 (8 MB)
127 12:45:17.691774 Using unxz to decompress xz
128 12:45:17.696457 progress 0 % (0 MB)
129 12:45:17.718068 progress 5 % (0 MB)
130 12:45:17.742886 progress 10 % (0 MB)
131 12:45:17.768695 progress 15 % (1 MB)
132 12:45:17.794135 progress 20 % (1 MB)
133 12:45:17.819652 progress 25 % (2 MB)
134 12:45:17.849323 progress 30 % (2 MB)
135 12:45:17.876231 progress 35 % (2 MB)
136 12:45:17.901753 progress 40 % (3 MB)
137 12:45:17.928058 progress 45 % (3 MB)
138 12:45:17.955759 progress 50 % (4 MB)
139 12:45:17.984642 progress 55 % (4 MB)
140 12:45:18.011764 progress 60 % (4 MB)
141 12:45:18.040001 progress 65 % (5 MB)
142 12:45:18.066669 progress 70 % (5 MB)
143 12:45:18.091354 progress 75 % (6 MB)
144 12:45:18.120271 progress 80 % (6 MB)
145 12:45:18.150846 progress 85 % (7 MB)
146 12:45:18.178360 progress 90 % (7 MB)
147 12:45:18.210604 progress 95 % (7 MB)
148 12:45:18.240183 progress 100 % (8 MB)
149 12:45:18.246494 8 MB downloaded in 0.55 s (14.85 MB/s)
150 12:45:18.246757 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:45:18.247026 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:45:18.247120 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 12:45:18.247217 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 12:45:22.319359 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12703557/extract-nfsrootfs-4y1kaca8
156 12:45:22.319559 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 12:45:22.319660 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 12:45:22.319837 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf
159 12:45:22.319967 makedir: /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/bin
160 12:45:22.320070 makedir: /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/tests
161 12:45:22.320165 makedir: /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/results
162 12:45:22.320265 Creating /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/bin/lava-add-keys
163 12:45:22.320576 Creating /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/bin/lava-add-sources
164 12:45:22.320741 Creating /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/bin/lava-background-process-start
165 12:45:22.320872 Creating /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/bin/lava-background-process-stop
166 12:45:22.321030 Creating /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/bin/lava-common-functions
167 12:45:22.321159 Creating /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/bin/lava-echo-ipv4
168 12:45:22.321283 Creating /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/bin/lava-install-packages
169 12:45:22.321410 Creating /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/bin/lava-installed-packages
170 12:45:22.321532 Creating /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/bin/lava-os-build
171 12:45:22.321660 Creating /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/bin/lava-probe-channel
172 12:45:22.321782 Creating /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/bin/lava-probe-ip
173 12:45:22.321908 Creating /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/bin/lava-target-ip
174 12:45:22.322030 Creating /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/bin/lava-target-mac
175 12:45:22.322156 Creating /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/bin/lava-target-storage
176 12:45:22.322283 Creating /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/bin/lava-test-case
177 12:45:22.322428 Creating /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/bin/lava-test-event
178 12:45:22.322551 Creating /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/bin/lava-test-feedback
179 12:45:22.322677 Creating /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/bin/lava-test-raise
180 12:45:22.322803 Creating /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/bin/lava-test-reference
181 12:45:22.322926 Creating /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/bin/lava-test-runner
182 12:45:22.323049 Creating /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/bin/lava-test-set
183 12:45:22.323174 Creating /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/bin/lava-test-shell
184 12:45:22.323297 Updating /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/bin/lava-add-keys (debian)
185 12:45:22.323447 Updating /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/bin/lava-add-sources (debian)
186 12:45:22.323602 Updating /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/bin/lava-install-packages (debian)
187 12:45:22.323749 Updating /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/bin/lava-installed-packages (debian)
188 12:45:22.323898 Updating /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/bin/lava-os-build (debian)
189 12:45:22.324028 Creating /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/environment
190 12:45:22.324134 LAVA metadata
191 12:45:22.324203 - LAVA_JOB_ID=12703557
192 12:45:22.324264 - LAVA_DISPATCHER_IP=192.168.201.1
193 12:45:22.324414 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 12:45:22.324478 skipped lava-vland-overlay
195 12:45:22.324549 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 12:45:22.324637 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 12:45:22.324735 skipped lava-multinode-overlay
198 12:45:22.324810 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 12:45:22.324886 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 12:45:22.324955 Loading test definitions
201 12:45:22.325038 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 12:45:22.325110 Using /lava-12703557 at stage 0
203 12:45:22.325390 uuid=12703557_1.6.2.3.1 testdef=None
204 12:45:22.325476 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 12:45:22.325561 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 12:45:22.326018 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 12:45:22.326239 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 12:45:22.326831 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 12:45:22.327058 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 12:45:22.327611 runner path: /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/0/tests/0_timesync-off test_uuid 12703557_1.6.2.3.1
213 12:45:22.327767 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 12:45:22.327989 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 12:45:22.328061 Using /lava-12703557 at stage 0
217 12:45:22.328154 Fetching tests from https://github.com/kernelci/test-definitions.git
218 12:45:22.328237 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/0/tests/1_kselftest-arm64'
219 12:45:24.882702 Running '/usr/bin/git checkout kernelci.org
220 12:45:25.129412 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 12:45:25.130343 uuid=12703557_1.6.2.3.5 testdef=None
222 12:45:25.130567 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 12:45:25.130955 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 12:45:25.132369 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 12:45:25.132607 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 12:45:25.133646 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 12:45:25.134069 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 12:45:25.142639 runner path: /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/0/tests/1_kselftest-arm64 test_uuid 12703557_1.6.2.3.5
232 12:45:25.142761 BOARD='mt8192-asurada-spherion-r0'
233 12:45:25.142832 BRANCH='cip-gitlab'
234 12:45:25.142894 SKIPFILE='/dev/null'
235 12:45:25.142952 SKIP_INSTALL='True'
236 12:45:25.143007 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 12:45:25.143064 TST_CASENAME=''
238 12:45:25.143148 TST_CMDFILES='arm64'
239 12:45:25.143309 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 12:45:25.143522 Creating lava-test-runner.conf files
242 12:45:25.143589 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12703557/lava-overlay-x9mwxbyf/lava-12703557/0 for stage 0
243 12:45:25.143685 - 0_timesync-off
244 12:45:25.143754 - 1_kselftest-arm64
245 12:45:25.143853 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 12:45:25.143973 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 12:45:32.899099 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 12:45:32.899256 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:36) [common]
249 12:45:32.899368 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 12:45:32.899473 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 12:45:32.899578 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:36) [common]
252 12:45:33.029217 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 12:45:33.029610 start: 1.6.4 extract-modules (timeout 00:09:36) [common]
254 12:45:33.029760 extracting modules file /var/lib/lava/dispatcher/tmp/12703557/tftp-deploy-4emrxmv5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12703557/extract-nfsrootfs-4y1kaca8
255 12:45:33.263876 extracting modules file /var/lib/lava/dispatcher/tmp/12703557/tftp-deploy-4emrxmv5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12703557/extract-overlay-ramdisk-tjtgifhc/ramdisk
256 12:45:33.503346 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 12:45:33.503507 start: 1.6.5 apply-overlay-tftp (timeout 00:09:35) [common]
258 12:45:33.503600 [common] Applying overlay to NFS
259 12:45:33.503672 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12703557/compress-overlay-f9n98ypw/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12703557/extract-nfsrootfs-4y1kaca8
260 12:45:34.448558 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 12:45:34.448729 start: 1.6.6 configure-preseed-file (timeout 00:09:34) [common]
262 12:45:34.448831 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 12:45:34.448925 start: 1.6.7 compress-ramdisk (timeout 00:09:34) [common]
264 12:45:34.449005 Building ramdisk /var/lib/lava/dispatcher/tmp/12703557/extract-overlay-ramdisk-tjtgifhc/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12703557/extract-overlay-ramdisk-tjtgifhc/ramdisk
265 12:45:34.769975 >> 119430 blocks
266 12:45:36.768504 rename /var/lib/lava/dispatcher/tmp/12703557/extract-overlay-ramdisk-tjtgifhc/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12703557/tftp-deploy-4emrxmv5/ramdisk/ramdisk.cpio.gz
267 12:45:36.768951 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 12:45:36.769082 start: 1.6.8 prepare-kernel (timeout 00:09:32) [common]
269 12:45:36.769230 start: 1.6.8.1 prepare-fit (timeout 00:09:32) [common]
270 12:45:36.769354 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12703557/tftp-deploy-4emrxmv5/kernel/Image'
271 12:45:49.809738 Returned 0 in 13 seconds
272 12:45:49.910628 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12703557/tftp-deploy-4emrxmv5/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12703557/tftp-deploy-4emrxmv5/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12703557/tftp-deploy-4emrxmv5/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12703557/tftp-deploy-4emrxmv5/kernel/image.itb
273 12:45:50.301521 output: FIT description: Kernel Image image with one or more FDT blobs
274 12:45:50.301917 output: Created: Mon Feb 5 12:45:50 2024
275 12:45:50.302003 output: Image 0 (kernel-1)
276 12:45:50.302079 output: Description:
277 12:45:50.302152 output: Created: Mon Feb 5 12:45:50 2024
278 12:45:50.302219 output: Type: Kernel Image
279 12:45:50.302283 output: Compression: lzma compressed
280 12:45:50.302344 output: Data Size: 12052857 Bytes = 11770.37 KiB = 11.49 MiB
281 12:45:50.302401 output: Architecture: AArch64
282 12:45:50.302457 output: OS: Linux
283 12:45:50.302513 output: Load Address: 0x00000000
284 12:45:50.302569 output: Entry Point: 0x00000000
285 12:45:50.302626 output: Hash algo: crc32
286 12:45:50.302693 output: Hash value: 8a14336a
287 12:45:50.302750 output: Image 1 (fdt-1)
288 12:45:50.302805 output: Description: mt8192-asurada-spherion-r0
289 12:45:50.302858 output: Created: Mon Feb 5 12:45:50 2024
290 12:45:50.302911 output: Type: Flat Device Tree
291 12:45:50.302963 output: Compression: uncompressed
292 12:45:50.303016 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 12:45:50.303068 output: Architecture: AArch64
294 12:45:50.303120 output: Hash algo: crc32
295 12:45:50.303171 output: Hash value: cc4352de
296 12:45:50.303223 output: Image 2 (ramdisk-1)
297 12:45:50.303303 output: Description: unavailable
298 12:45:50.303386 output: Created: Mon Feb 5 12:45:50 2024
299 12:45:50.303467 output: Type: RAMDisk Image
300 12:45:50.303551 output: Compression: Unknown Compression
301 12:45:50.303607 output: Data Size: 17801754 Bytes = 17384.53 KiB = 16.98 MiB
302 12:45:50.303660 output: Architecture: AArch64
303 12:45:50.303713 output: OS: Linux
304 12:45:50.303765 output: Load Address: unavailable
305 12:45:50.303817 output: Entry Point: unavailable
306 12:45:50.303869 output: Hash algo: crc32
307 12:45:50.303921 output: Hash value: 03b45b27
308 12:45:50.303982 output: Default Configuration: 'conf-1'
309 12:45:50.304068 output: Configuration 0 (conf-1)
310 12:45:50.304163 output: Description: mt8192-asurada-spherion-r0
311 12:45:50.304254 output: Kernel: kernel-1
312 12:45:50.304364 output: Init Ramdisk: ramdisk-1
313 12:45:50.304420 output: FDT: fdt-1
314 12:45:50.304489 output: Loadables: kernel-1
315 12:45:50.304543 output:
316 12:45:50.304756 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 12:45:50.304869 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 12:45:50.304974 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 12:45:50.305077 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
320 12:45:50.305162 No LXC device requested
321 12:45:50.305241 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 12:45:50.305327 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
323 12:45:50.305404 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 12:45:50.305476 Checking files for TFTP limit of 4294967296 bytes.
325 12:45:50.306269 end: 1 tftp-deploy (duration 00:00:41) [common]
326 12:45:50.306417 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 12:45:50.306552 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 12:45:50.306735 substitutions:
329 12:45:50.306833 - {DTB}: 12703557/tftp-deploy-4emrxmv5/dtb/mt8192-asurada-spherion-r0.dtb
330 12:45:50.306925 - {INITRD}: 12703557/tftp-deploy-4emrxmv5/ramdisk/ramdisk.cpio.gz
331 12:45:50.307022 - {KERNEL}: 12703557/tftp-deploy-4emrxmv5/kernel/Image
332 12:45:50.307109 - {LAVA_MAC}: None
333 12:45:50.307195 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12703557/extract-nfsrootfs-4y1kaca8
334 12:45:50.307280 - {NFS_SERVER_IP}: 192.168.201.1
335 12:45:50.307364 - {PRESEED_CONFIG}: None
336 12:45:50.307447 - {PRESEED_LOCAL}: None
337 12:45:50.307530 - {RAMDISK}: 12703557/tftp-deploy-4emrxmv5/ramdisk/ramdisk.cpio.gz
338 12:45:50.307613 - {ROOT_PART}: None
339 12:45:50.307695 - {ROOT}: None
340 12:45:50.307752 - {SERVER_IP}: 192.168.201.1
341 12:45:50.307807 - {TEE}: None
342 12:45:50.307861 Parsed boot commands:
343 12:45:50.307932 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 12:45:50.308218 Parsed boot commands: tftpboot 192.168.201.1 12703557/tftp-deploy-4emrxmv5/kernel/image.itb 12703557/tftp-deploy-4emrxmv5/kernel/cmdline
345 12:45:50.308382 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 12:45:50.308475 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 12:45:50.308582 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 12:45:50.308716 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 12:45:50.308826 Not connected, no need to disconnect.
350 12:45:50.308934 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 12:45:50.309139 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 12:45:50.309267 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
353 12:45:50.313482 Setting prompt string to ['lava-test: # ']
354 12:45:50.313891 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 12:45:50.314007 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 12:45:50.314108 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 12:45:50.314205 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 12:45:50.314442 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
359 12:45:55.456917 >> Command sent successfully.
360 12:45:55.467161 Returned 0 in 5 seconds
361 12:45:55.568523 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 12:45:55.570040 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 12:45:55.570541 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 12:45:55.570972 Setting prompt string to 'Starting depthcharge on Spherion...'
366 12:45:55.571324 Changing prompt to 'Starting depthcharge on Spherion...'
367 12:45:55.571676 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 12:45:55.573036 [Enter `^Ec?' for help]
369 12:45:55.735573
370 12:45:55.736129
371 12:45:55.736559 F0: 102B 0000
372 12:45:55.736904
373 12:45:55.737217 F3: 1001 0000 [0200]
374 12:45:55.739021
375 12:45:55.739447 F3: 1001 0000
376 12:45:55.739787
377 12:45:55.740102 F7: 102D 0000
378 12:45:55.740440
379 12:45:55.742157 F1: 0000 0000
380 12:45:55.742585
381 12:45:55.742924 V0: 0000 0000 [0001]
382 12:45:55.743252
383 12:45:55.745566 00: 0007 8000
384 12:45:55.746014
385 12:45:55.746352 01: 0000 0000
386 12:45:55.746672
387 12:45:55.748656 BP: 0C00 0209 [0000]
388 12:45:55.749083
389 12:45:55.749416 G0: 1182 0000
390 12:45:55.749727
391 12:45:55.752450 EC: 0000 0021 [4000]
392 12:45:55.752879
393 12:45:55.753216 S7: 0000 0000 [0000]
394 12:45:55.753530
395 12:45:55.756485 CC: 0000 0000 [0001]
396 12:45:55.756912
397 12:45:55.757249 T0: 0000 0040 [010F]
398 12:45:55.757563
399 12:45:55.757861 Jump to BL
400 12:45:55.758151
401 12:45:55.783093
402 12:45:55.783650
403 12:45:55.783990
404 12:45:55.789986 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 12:45:55.793964 ARM64: Exception handlers installed.
406 12:45:55.797984 ARM64: Testing exception
407 12:45:55.801171 ARM64: Done test exception
408 12:45:55.807817 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 12:45:55.817927 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 12:45:55.824846 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 12:45:55.834553 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 12:45:55.842015 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 12:45:55.848053 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 12:45:55.859931 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 12:45:55.866559 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 12:45:55.885872 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 12:45:55.888992 WDT: Last reset was cold boot
418 12:45:55.892118 SPI1(PAD0) initialized at 2873684 Hz
419 12:45:55.895963 SPI5(PAD0) initialized at 992727 Hz
420 12:45:55.899217 VBOOT: Loading verstage.
421 12:45:55.906300 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:45:55.909495 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 12:45:55.912707 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 12:45:55.915878 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 12:45:55.922977 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 12:45:55.929821 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 12:45:55.941342 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 12:45:55.941769
429 12:45:55.942098
430 12:45:55.951382 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 12:45:55.954733 ARM64: Exception handlers installed.
432 12:45:55.955270 ARM64: Testing exception
433 12:45:55.957813 ARM64: Done test exception
434 12:45:55.961223 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 12:45:55.968551 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 12:45:55.981923 Probing TPM: . done!
437 12:45:55.982555 TPM ready after 0 ms
438 12:45:55.988978 Connected to device vid:did:rid of 1ae0:0028:00
439 12:45:55.996198 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 12:45:56.054586 Initialized TPM device CR50 revision 0
441 12:45:56.066612 tlcl_send_startup: Startup return code is 0
442 12:45:56.067164 TPM: setup succeeded
443 12:45:56.077931 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 12:45:56.086890 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 12:45:56.098757 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 12:45:56.109333 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 12:45:56.112465 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 12:45:56.116467 in-header: 03 07 00 00 08 00 00 00
449 12:45:56.120365 in-data: aa e4 47 04 13 02 00 00
450 12:45:56.120842 Chrome EC: UHEPI supported
451 12:45:56.127945 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 12:45:56.131910 in-header: 03 95 00 00 08 00 00 00
453 12:45:56.135270 in-data: 18 20 20 08 00 00 00 00
454 12:45:56.135869 Phase 1
455 12:45:56.139612 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 12:45:56.146276 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 12:45:56.149935 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 12:45:56.153968 Recovery requested (1009000e)
459 12:45:56.163745 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 12:45:56.168921 tlcl_extend: response is 0
461 12:45:56.178398 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 12:45:56.184862 tlcl_extend: response is 0
463 12:45:56.191430 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 12:45:56.210911 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 12:45:56.217068 BS: bootblock times (exec / console): total (unknown) / 149 ms
466 12:45:56.217542
467 12:45:56.217912
468 12:45:56.227081 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 12:45:56.230795 ARM64: Exception handlers installed.
470 12:45:56.233495 ARM64: Testing exception
471 12:45:56.233925 ARM64: Done test exception
472 12:45:56.256470 pmic_efuse_setting: Set efuses in 11 msecs
473 12:45:56.259842 pmwrap_interface_init: Select PMIF_VLD_RDY
474 12:45:56.266719 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 12:45:56.269977 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 12:45:56.276753 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 12:45:56.280894 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 12:45:56.284475 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 12:45:56.288030 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 12:45:56.296193 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 12:45:56.300084 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 12:45:56.303220 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 12:45:56.307123 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 12:45:56.314470 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 12:45:56.318374 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 12:45:56.321514 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 12:45:56.329357 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 12:45:56.333170 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 12:45:56.340218 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 12:45:56.347539 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 12:45:56.350774 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 12:45:56.358544 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 12:45:56.361737 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 12:45:56.370118 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 12:45:56.373805 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 12:45:56.381276 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 12:45:56.384887 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 12:45:56.388585 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 12:45:56.395745 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 12:45:56.399484 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 12:45:56.407074 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 12:45:56.410233 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 12:45:56.414360 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 12:45:56.421513 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 12:45:56.424872 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 12:45:56.428726 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 12:45:56.436224 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 12:45:56.439710 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 12:45:56.446971 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 12:45:56.450387 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 12:45:56.454702 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 12:45:56.458006 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 12:45:56.465397 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 12:45:56.468849 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 12:45:56.472724 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 12:45:56.476727 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 12:45:56.480123 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 12:45:56.488014 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 12:45:56.490967 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 12:45:56.495280 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 12:45:56.498807 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 12:45:56.502485 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 12:45:56.505863 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 12:45:56.509861 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 12:45:56.517552 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 12:45:56.528804 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 12:45:56.532078 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 12:45:56.540133 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 12:45:56.547331 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 12:45:56.554898 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 12:45:56.558511 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 12:45:56.562031 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 12:45:56.569414 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x38
534 12:45:56.573398 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 12:45:56.581459 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 12:45:56.584969 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 12:45:56.594090 [RTC]rtc_get_frequency_meter,154: input=15, output=759
538 12:45:56.603500 [RTC]rtc_get_frequency_meter,154: input=23, output=942
539 12:45:56.612811 [RTC]rtc_get_frequency_meter,154: input=19, output=849
540 12:45:56.622428 [RTC]rtc_get_frequency_meter,154: input=17, output=804
541 12:45:56.631600 [RTC]rtc_get_frequency_meter,154: input=16, output=782
542 12:45:56.641224 [RTC]rtc_get_frequency_meter,154: input=16, output=781
543 12:45:56.650838 [RTC]rtc_get_frequency_meter,154: input=17, output=805
544 12:45:56.654184 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 12:45:56.661688 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 12:45:56.665336 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 12:45:56.669139 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 12:45:56.672575 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 12:45:56.676357 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 12:45:56.680227 ADC[4]: Raw value=906573 ID=7
551 12:45:56.684225 ADC[3]: Raw value=213810 ID=1
552 12:45:56.684354 RAM Code: 0x71
553 12:45:56.687582 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 12:45:56.694766 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 12:45:56.703015 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 12:45:56.709524 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 12:45:56.713505 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 12:45:56.717182 in-header: 03 07 00 00 08 00 00 00
559 12:45:56.721567 in-data: aa e4 47 04 13 02 00 00
560 12:45:56.722008 Chrome EC: UHEPI supported
561 12:45:56.728962 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 12:45:56.732862 in-header: 03 95 00 00 08 00 00 00
563 12:45:56.736583 in-data: 18 20 20 08 00 00 00 00
564 12:45:56.740386 MRC: failed to locate region type 0.
565 12:45:56.743757 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 12:45:56.747583 DRAM-K: Running full calibration
567 12:45:56.755210 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 12:45:56.755398 header.status = 0x0
569 12:45:56.758502 header.version = 0x6 (expected: 0x6)
570 12:45:56.762356 header.size = 0xd00 (expected: 0xd00)
571 12:45:56.766355 header.flags = 0x0
572 12:45:56.769466 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 12:45:56.788690 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
574 12:45:56.796345 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 12:45:56.796462 dram_init: ddr_geometry: 2
576 12:45:56.800422 [EMI] MDL number = 2
577 12:45:56.804087 [EMI] Get MDL freq = 0
578 12:45:56.804171 dram_init: ddr_type: 0
579 12:45:56.808101 is_discrete_lpddr4: 1
580 12:45:56.808185 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 12:45:56.811360
582 12:45:56.811443
583 12:45:56.811508 [Bian_co] ETT version 0.0.0.1
584 12:45:56.819051 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 12:45:56.819477
586 12:45:56.823061 dramc_set_vcore_voltage set vcore to 650000
587 12:45:56.823558 Read voltage for 800, 4
588 12:45:56.824105 Vio18 = 0
589 12:45:56.826419 Vcore = 650000
590 12:45:56.826849 Vdram = 0
591 12:45:56.827189 Vddq = 0
592 12:45:56.830397 Vmddr = 0
593 12:45:56.830826 dram_init: config_dvfs: 1
594 12:45:56.834613 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 12:45:56.841803 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 12:45:56.845918 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
597 12:45:56.849140 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
598 12:45:56.853652 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 12:45:56.856893 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 12:45:56.857323 MEM_TYPE=3, freq_sel=18
601 12:45:56.860810 sv_algorithm_assistance_LP4_1600
602 12:45:56.867814 ============ PULL DRAM RESETB DOWN ============
603 12:45:56.870806 ========== PULL DRAM RESETB DOWN end =========
604 12:45:56.874234 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 12:45:56.877508 ===================================
606 12:45:56.880931 LPDDR4 DRAM CONFIGURATION
607 12:45:56.884598 ===================================
608 12:45:56.885030 EX_ROW_EN[0] = 0x0
609 12:45:56.888209 EX_ROW_EN[1] = 0x0
610 12:45:56.888714 LP4Y_EN = 0x0
611 12:45:56.892213 WORK_FSP = 0x0
612 12:45:56.892684 WL = 0x2
613 12:45:56.896151 RL = 0x2
614 12:45:56.896665 BL = 0x2
615 12:45:56.899349 RPST = 0x0
616 12:45:56.899787 RD_PRE = 0x0
617 12:45:56.903245 WR_PRE = 0x1
618 12:45:56.903683 WR_PST = 0x0
619 12:45:56.904132 DBI_WR = 0x0
620 12:45:56.906363 DBI_RD = 0x0
621 12:45:56.909353 OTF = 0x1
622 12:45:56.912720 ===================================
623 12:45:56.915932 ===================================
624 12:45:56.916118 ANA top config
625 12:45:56.920093 ===================================
626 12:45:56.922921 DLL_ASYNC_EN = 0
627 12:45:56.923134 ALL_SLAVE_EN = 1
628 12:45:56.926109 NEW_RANK_MODE = 1
629 12:45:56.929370 DLL_IDLE_MODE = 1
630 12:45:56.932667 LP45_APHY_COMB_EN = 1
631 12:45:56.935949 TX_ODT_DIS = 1
632 12:45:56.936055 NEW_8X_MODE = 1
633 12:45:56.940270 ===================================
634 12:45:56.943355 ===================================
635 12:45:56.946478 data_rate = 1600
636 12:45:56.950277 CKR = 1
637 12:45:56.953318 DQ_P2S_RATIO = 8
638 12:45:56.956763 ===================================
639 12:45:56.956852 CA_P2S_RATIO = 8
640 12:45:56.960052 DQ_CA_OPEN = 0
641 12:45:56.963514 DQ_SEMI_OPEN = 0
642 12:45:56.967172 CA_SEMI_OPEN = 0
643 12:45:56.970522 CA_FULL_RATE = 0
644 12:45:56.973770 DQ_CKDIV4_EN = 1
645 12:45:56.973872 CA_CKDIV4_EN = 1
646 12:45:56.977185 CA_PREDIV_EN = 0
647 12:45:56.980358 PH8_DLY = 0
648 12:45:56.983760 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 12:45:56.987265 DQ_AAMCK_DIV = 4
650 12:45:56.990296 CA_AAMCK_DIV = 4
651 12:45:56.990387 CA_ADMCK_DIV = 4
652 12:45:56.993499 DQ_TRACK_CA_EN = 0
653 12:45:56.997135 CA_PICK = 800
654 12:45:56.999881 CA_MCKIO = 800
655 12:45:57.004153 MCKIO_SEMI = 0
656 12:45:57.007768 PLL_FREQ = 3068
657 12:45:57.007852 DQ_UI_PI_RATIO = 32
658 12:45:57.011695 CA_UI_PI_RATIO = 0
659 12:45:57.015087 ===================================
660 12:45:57.019170 ===================================
661 12:45:57.019253 memory_type:LPDDR4
662 12:45:57.022406 GP_NUM : 10
663 12:45:57.026496 SRAM_EN : 1
664 12:45:57.026594 MD32_EN : 0
665 12:45:57.030175 ===================================
666 12:45:57.033769 [ANA_INIT] >>>>>>>>>>>>>>
667 12:45:57.033874 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 12:45:57.037952 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 12:45:57.041094 ===================================
670 12:45:57.044715 data_rate = 1600,PCW = 0X7600
671 12:45:57.047770 ===================================
672 12:45:57.051145 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 12:45:57.057893 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 12:45:57.060897 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 12:45:57.067693 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 12:45:57.071504 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 12:45:57.074527 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 12:45:57.074953 [ANA_INIT] flow start
679 12:45:57.077917 [ANA_INIT] PLL >>>>>>>>
680 12:45:57.081595 [ANA_INIT] PLL <<<<<<<<
681 12:45:57.084838 [ANA_INIT] MIDPI >>>>>>>>
682 12:45:57.085370 [ANA_INIT] MIDPI <<<<<<<<
683 12:45:57.088153 [ANA_INIT] DLL >>>>>>>>
684 12:45:57.091386 [ANA_INIT] flow end
685 12:45:57.094772 ============ LP4 DIFF to SE enter ============
686 12:45:57.097854 ============ LP4 DIFF to SE exit ============
687 12:45:57.101181 [ANA_INIT] <<<<<<<<<<<<<
688 12:45:57.104420 [Flow] Enable top DCM control >>>>>
689 12:45:57.108002 [Flow] Enable top DCM control <<<<<
690 12:45:57.111656 Enable DLL master slave shuffle
691 12:45:57.114646 ==============================================================
692 12:45:57.118107 Gating Mode config
693 12:45:57.120910 ==============================================================
694 12:45:57.124886 Config description:
695 12:45:57.134935 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 12:45:57.141399 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 12:45:57.144568 SELPH_MODE 0: By rank 1: By Phase
698 12:45:57.150889 ==============================================================
699 12:45:57.155069 GAT_TRACK_EN = 1
700 12:45:57.157752 RX_GATING_MODE = 2
701 12:45:57.161476 RX_GATING_TRACK_MODE = 2
702 12:45:57.164684 SELPH_MODE = 1
703 12:45:57.165234 PICG_EARLY_EN = 1
704 12:45:57.168461 VALID_LAT_VALUE = 1
705 12:45:57.174440 ==============================================================
706 12:45:57.178012 Enter into Gating configuration >>>>
707 12:45:57.181396 Exit from Gating configuration <<<<
708 12:45:57.184800 Enter into DVFS_PRE_config >>>>>
709 12:45:57.195184 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 12:45:57.198354 Exit from DVFS_PRE_config <<<<<
711 12:45:57.201804 Enter into PICG configuration >>>>
712 12:45:57.204998 Exit from PICG configuration <<<<
713 12:45:57.208220 [RX_INPUT] configuration >>>>>
714 12:45:57.211752 [RX_INPUT] configuration <<<<<
715 12:45:57.214942 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 12:45:57.221573 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 12:45:57.227996 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 12:45:57.234896 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 12:45:57.238004 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 12:45:57.244988 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 12:45:57.248617 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 12:45:57.255236 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 12:45:57.258563 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 12:45:57.261597 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 12:45:57.264863 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 12:45:57.271839 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 12:45:57.275368 ===================================
728 12:45:57.275935 LPDDR4 DRAM CONFIGURATION
729 12:45:57.278344 ===================================
730 12:45:57.281625 EX_ROW_EN[0] = 0x0
731 12:45:57.284856 EX_ROW_EN[1] = 0x0
732 12:45:57.285322 LP4Y_EN = 0x0
733 12:45:57.288583 WORK_FSP = 0x0
734 12:45:57.289165 WL = 0x2
735 12:45:57.291423 RL = 0x2
736 12:45:57.291888 BL = 0x2
737 12:45:57.295324 RPST = 0x0
738 12:45:57.295910 RD_PRE = 0x0
739 12:45:57.298246 WR_PRE = 0x1
740 12:45:57.298710 WR_PST = 0x0
741 12:45:57.302544 DBI_WR = 0x0
742 12:45:57.303115 DBI_RD = 0x0
743 12:45:57.305347 OTF = 0x1
744 12:45:57.308281 ===================================
745 12:45:57.311963 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 12:45:57.315242 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 12:45:57.321496 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 12:45:57.325037 ===================================
749 12:45:57.325529 LPDDR4 DRAM CONFIGURATION
750 12:45:57.328219 ===================================
751 12:45:57.332088 EX_ROW_EN[0] = 0x10
752 12:45:57.332722 EX_ROW_EN[1] = 0x0
753 12:45:57.335122 LP4Y_EN = 0x0
754 12:45:57.335585 WORK_FSP = 0x0
755 12:45:57.338778 WL = 0x2
756 12:45:57.339343 RL = 0x2
757 12:45:57.341785 BL = 0x2
758 12:45:57.342246 RPST = 0x0
759 12:45:57.345138 RD_PRE = 0x0
760 12:45:57.345557 WR_PRE = 0x1
761 12:45:57.348282 WR_PST = 0x0
762 12:45:57.351650 DBI_WR = 0x0
763 12:45:57.352068 DBI_RD = 0x0
764 12:45:57.355286 OTF = 0x1
765 12:45:57.358993 ===================================
766 12:45:57.362292 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 12:45:57.367086 nWR fixed to 40
768 12:45:57.370770 [ModeRegInit_LP4] CH0 RK0
769 12:45:57.371288 [ModeRegInit_LP4] CH0 RK1
770 12:45:57.373519 [ModeRegInit_LP4] CH1 RK0
771 12:45:57.377204 [ModeRegInit_LP4] CH1 RK1
772 12:45:57.377832 match AC timing 13
773 12:45:57.383763 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 12:45:57.387593 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 12:45:57.390594 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 12:45:57.397232 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 12:45:57.400255 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 12:45:57.400716 [EMI DOE] emi_dcm 0
779 12:45:57.407009 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 12:45:57.407554 ==
781 12:45:57.410516 Dram Type= 6, Freq= 0, CH_0, rank 0
782 12:45:57.413732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 12:45:57.414311 ==
784 12:45:57.420510 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 12:45:57.426592 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 12:45:57.434346 [CA 0] Center 36 (6~67) winsize 62
787 12:45:57.437682 [CA 1] Center 36 (6~67) winsize 62
788 12:45:57.440936 [CA 2] Center 34 (4~65) winsize 62
789 12:45:57.444374 [CA 3] Center 34 (4~64) winsize 61
790 12:45:57.447670 [CA 4] Center 33 (3~63) winsize 61
791 12:45:57.451433 [CA 5] Center 32 (2~62) winsize 61
792 12:45:57.451857
793 12:45:57.454698 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 12:45:57.455116
795 12:45:57.457987 [CATrainingPosCal] consider 1 rank data
796 12:45:57.461091 u2DelayCellTimex100 = 270/100 ps
797 12:45:57.464559 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
798 12:45:57.468455 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
799 12:45:57.471888 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
800 12:45:57.477927 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
801 12:45:57.481246 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
802 12:45:57.484894 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
803 12:45:57.485382
804 12:45:57.488446 CA PerBit enable=1, Macro0, CA PI delay=32
805 12:45:57.489036
806 12:45:57.491615 [CBTSetCACLKResult] CA Dly = 32
807 12:45:57.492210 CS Dly: 4 (0~35)
808 12:45:57.492760 ==
809 12:45:57.494811 Dram Type= 6, Freq= 0, CH_0, rank 1
810 12:45:57.501479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 12:45:57.502067 ==
812 12:45:57.504971 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 12:45:57.511822 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 12:45:57.520941 [CA 0] Center 36 (6~67) winsize 62
815 12:45:57.524116 [CA 1] Center 36 (6~67) winsize 62
816 12:45:57.527416 [CA 2] Center 34 (4~65) winsize 62
817 12:45:57.530999 [CA 3] Center 33 (3~64) winsize 62
818 12:45:57.534288 [CA 4] Center 33 (2~64) winsize 63
819 12:45:57.537298 [CA 5] Center 32 (2~63) winsize 62
820 12:45:57.537790
821 12:45:57.540912 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 12:45:57.541506
823 12:45:57.543841 [CATrainingPosCal] consider 2 rank data
824 12:45:57.547485 u2DelayCellTimex100 = 270/100 ps
825 12:45:57.550775 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
826 12:45:57.554403 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
827 12:45:57.560647 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
828 12:45:57.564627 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
829 12:45:57.567900 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
830 12:45:57.570997 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
831 12:45:57.571443
832 12:45:57.574843 CA PerBit enable=1, Macro0, CA PI delay=32
833 12:45:57.575395
834 12:45:57.577394 [CBTSetCACLKResult] CA Dly = 32
835 12:45:57.577839 CS Dly: 5 (0~37)
836 12:45:57.578296
837 12:45:57.581888 ----->DramcWriteLeveling(PI) begin...
838 12:45:57.582457 ==
839 12:45:57.584907 Dram Type= 6, Freq= 0, CH_0, rank 0
840 12:45:57.588823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 12:45:57.592086 ==
842 12:45:57.592684 Write leveling (Byte 0): 32 => 32
843 12:45:57.596061 Write leveling (Byte 1): 28 => 28
844 12:45:57.599194 DramcWriteLeveling(PI) end<-----
845 12:45:57.599641
846 12:45:57.600099 ==
847 12:45:57.602725 Dram Type= 6, Freq= 0, CH_0, rank 0
848 12:45:57.606361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 12:45:57.606921 ==
850 12:45:57.609361 [Gating] SW mode calibration
851 12:45:57.616721 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 12:45:57.623263 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 12:45:57.626316 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 12:45:57.629719 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 12:45:57.636705 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
856 12:45:57.639915 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 12:45:57.643068 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 12:45:57.649592 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:45:57.652928 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:45:57.656483 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:45:57.663221 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 12:45:57.666348 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 12:45:57.670019 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 12:45:57.676704 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 12:45:57.679694 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 12:45:57.683666 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 12:45:57.689958 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 12:45:57.693525 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 12:45:57.696474 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 12:45:57.699448 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
871 12:45:57.706445 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
872 12:45:57.709669 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 12:45:57.713267 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 12:45:57.719492 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 12:45:57.724082 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 12:45:57.726012 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 12:45:57.732865 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 12:45:57.736477 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 12:45:57.739758 0 9 8 | B1->B0 | 2323 3030 | 1 0 | (1 1) (0 0)
880 12:45:57.746113 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
881 12:45:57.749593 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 12:45:57.752750 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 12:45:57.759318 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 12:45:57.762575 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 12:45:57.766097 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 12:45:57.772769 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 0)
887 12:45:57.776221 0 10 8 | B1->B0 | 3030 2b2b | 0 1 | (0 0) (1 0)
888 12:45:57.779436 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 12:45:57.786589 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 12:45:57.790018 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 12:45:57.793455 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 12:45:57.796473 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 12:45:57.802880 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 12:45:57.806388 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
895 12:45:57.809262 0 11 8 | B1->B0 | 2a2a 3d3d | 0 0 | (0 0) (0 0)
896 12:45:57.815992 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
897 12:45:57.819442 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 12:45:57.822888 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 12:45:57.829443 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 12:45:57.832905 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 12:45:57.836501 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 12:45:57.842997 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 12:45:57.846332 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
904 12:45:57.849586 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 12:45:57.856224 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 12:45:57.860201 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 12:45:57.863489 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 12:45:57.870172 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 12:45:57.873417 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 12:45:57.876503 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 12:45:57.879662 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 12:45:57.886831 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 12:45:57.890032 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 12:45:57.893129 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 12:45:57.899862 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 12:45:57.903644 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 12:45:57.906911 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 12:45:57.913049 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 12:45:57.917311 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
920 12:45:57.920477 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 12:45:57.923624 Total UI for P1: 0, mck2ui 16
922 12:45:57.927198 best dqsien dly found for B0: ( 0, 14, 6)
923 12:45:57.930252 Total UI for P1: 0, mck2ui 16
924 12:45:57.933680 best dqsien dly found for B1: ( 0, 14, 10)
925 12:45:57.937079 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
926 12:45:57.940831 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
927 12:45:57.941334
928 12:45:57.943917 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
929 12:45:57.947320 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
930 12:45:57.950655 [Gating] SW calibration Done
931 12:45:57.951117 ==
932 12:45:57.953474 Dram Type= 6, Freq= 0, CH_0, rank 0
933 12:45:57.960852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 12:45:57.961382 ==
935 12:45:57.961752 RX Vref Scan: 0
936 12:45:57.962092
937 12:45:57.963659 RX Vref 0 -> 0, step: 1
938 12:45:57.964093
939 12:45:57.966919 RX Delay -130 -> 252, step: 16
940 12:45:57.970797 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
941 12:45:57.973921 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
942 12:45:57.977051 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 12:45:57.980314 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 12:45:57.987155 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
945 12:45:57.991146 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 12:45:57.994221 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
947 12:45:57.997143 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
948 12:45:58.000528 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
949 12:45:58.007675 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
950 12:45:58.010808 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
951 12:45:58.013802 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
952 12:45:58.017724 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
953 12:45:58.020841 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
954 12:45:58.027627 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
955 12:45:58.030707 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 12:45:58.031190 ==
957 12:45:58.034023 Dram Type= 6, Freq= 0, CH_0, rank 0
958 12:45:58.037338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 12:45:58.037813 ==
960 12:45:58.040601 DQS Delay:
961 12:45:58.041027 DQS0 = 0, DQS1 = 0
962 12:45:58.041363 DQM Delay:
963 12:45:58.044182 DQM0 = 90, DQM1 = 84
964 12:45:58.044754 DQ Delay:
965 12:45:58.048224 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
966 12:45:58.051593 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
967 12:45:58.054505 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
968 12:45:58.057751 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85
969 12:45:58.058334
970 12:45:58.058820
971 12:45:58.059271 ==
972 12:45:58.061039 Dram Type= 6, Freq= 0, CH_0, rank 0
973 12:45:58.064464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 12:45:58.067737 ==
975 12:45:58.068351
976 12:45:58.068840
977 12:45:58.069309 TX Vref Scan disable
978 12:45:58.071368 == TX Byte 0 ==
979 12:45:58.074180 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
980 12:45:58.077560 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
981 12:45:58.081147 == TX Byte 1 ==
982 12:45:58.084365 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
983 12:45:58.087560 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
984 12:45:58.091041 ==
985 12:45:58.094167 Dram Type= 6, Freq= 0, CH_0, rank 0
986 12:45:58.097651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 12:45:58.098243 ==
988 12:45:58.110354 TX Vref=22, minBit 8, minWin=27, winSum=447
989 12:45:58.113694 TX Vref=24, minBit 10, minWin=27, winSum=452
990 12:45:58.117281 TX Vref=26, minBit 14, minWin=27, winSum=455
991 12:45:58.120242 TX Vref=28, minBit 0, minWin=28, winSum=458
992 12:45:58.123653 TX Vref=30, minBit 5, minWin=28, winSum=459
993 12:45:58.130304 TX Vref=32, minBit 8, minWin=27, winSum=455
994 12:45:58.134019 [TxChooseVref] Worse bit 5, Min win 28, Win sum 459, Final Vref 30
995 12:45:58.134494
996 12:45:58.137310 Final TX Range 1 Vref 30
997 12:45:58.137738
998 12:45:58.138092 ==
999 12:45:58.140594 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 12:45:58.143901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 12:45:58.144485 ==
1002 12:45:58.144947
1003 12:45:58.147296
1004 12:45:58.147840 TX Vref Scan disable
1005 12:45:58.150579 == TX Byte 0 ==
1006 12:45:58.153652 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1007 12:45:58.156938 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1008 12:45:58.160580 == TX Byte 1 ==
1009 12:45:58.164199 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1010 12:45:58.167621 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1011 12:45:58.170807
1012 12:45:58.171350 [DATLAT]
1013 12:45:58.171805 Freq=800, CH0 RK0
1014 12:45:58.172230
1015 12:45:58.173924 DATLAT Default: 0xa
1016 12:45:58.174362 0, 0xFFFF, sum = 0
1017 12:45:58.177104 1, 0xFFFF, sum = 0
1018 12:45:58.177549 2, 0xFFFF, sum = 0
1019 12:45:58.180996 3, 0xFFFF, sum = 0
1020 12:45:58.181548 4, 0xFFFF, sum = 0
1021 12:45:58.184334 5, 0xFFFF, sum = 0
1022 12:45:58.184896 6, 0xFFFF, sum = 0
1023 12:45:58.187136 7, 0xFFFF, sum = 0
1024 12:45:58.187583 8, 0xFFFF, sum = 0
1025 12:45:58.190516 9, 0x0, sum = 1
1026 12:45:58.190967 10, 0x0, sum = 2
1027 12:45:58.194011 11, 0x0, sum = 3
1028 12:45:58.194555 12, 0x0, sum = 4
1029 12:45:58.197208 best_step = 10
1030 12:45:58.197746
1031 12:45:58.198200 ==
1032 12:45:58.200514 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 12:45:58.204555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 12:45:58.205096 ==
1035 12:45:58.207711 RX Vref Scan: 1
1036 12:45:58.208249
1037 12:45:58.208738 Set Vref Range= 32 -> 127
1038 12:45:58.209153
1039 12:45:58.211111 RX Vref 32 -> 127, step: 1
1040 12:45:58.211650
1041 12:45:58.213958 RX Delay -79 -> 252, step: 8
1042 12:45:58.214391
1043 12:45:58.217353 Set Vref, RX VrefLevel [Byte0]: 32
1044 12:45:58.220718 [Byte1]: 32
1045 12:45:58.221149
1046 12:45:58.223823 Set Vref, RX VrefLevel [Byte0]: 33
1047 12:45:58.227109 [Byte1]: 33
1048 12:45:58.230692
1049 12:45:58.231299 Set Vref, RX VrefLevel [Byte0]: 34
1050 12:45:58.234506 [Byte1]: 34
1051 12:45:58.237977
1052 12:45:58.238554 Set Vref, RX VrefLevel [Byte0]: 35
1053 12:45:58.241788 [Byte1]: 35
1054 12:45:58.245920
1055 12:45:58.246441 Set Vref, RX VrefLevel [Byte0]: 36
1056 12:45:58.249518 [Byte1]: 36
1057 12:45:58.253584
1058 12:45:58.253990 Set Vref, RX VrefLevel [Byte0]: 37
1059 12:45:58.256851 [Byte1]: 37
1060 12:45:58.261103
1061 12:45:58.261514 Set Vref, RX VrefLevel [Byte0]: 38
1062 12:45:58.264361 [Byte1]: 38
1063 12:45:58.269127
1064 12:45:58.269582 Set Vref, RX VrefLevel [Byte0]: 39
1065 12:45:58.271610 [Byte1]: 39
1066 12:45:58.276195
1067 12:45:58.276723 Set Vref, RX VrefLevel [Byte0]: 40
1068 12:45:58.279569 [Byte1]: 40
1069 12:45:58.283683
1070 12:45:58.284219 Set Vref, RX VrefLevel [Byte0]: 41
1071 12:45:58.287088 [Byte1]: 41
1072 12:45:58.291355
1073 12:45:58.291881 Set Vref, RX VrefLevel [Byte0]: 42
1074 12:45:58.294599 [Byte1]: 42
1075 12:45:58.298800
1076 12:45:58.299353 Set Vref, RX VrefLevel [Byte0]: 43
1077 12:45:58.301802 [Byte1]: 43
1078 12:45:58.306747
1079 12:45:58.307269 Set Vref, RX VrefLevel [Byte0]: 44
1080 12:45:58.309957 [Byte1]: 44
1081 12:45:58.313457
1082 12:45:58.313919 Set Vref, RX VrefLevel [Byte0]: 45
1083 12:45:58.317584 [Byte1]: 45
1084 12:45:58.321361
1085 12:45:58.321934 Set Vref, RX VrefLevel [Byte0]: 46
1086 12:45:58.324501 [Byte1]: 46
1087 12:45:58.328926
1088 12:45:58.329538 Set Vref, RX VrefLevel [Byte0]: 47
1089 12:45:58.331971 [Byte1]: 47
1090 12:45:58.336837
1091 12:45:58.337402 Set Vref, RX VrefLevel [Byte0]: 48
1092 12:45:58.339885 [Byte1]: 48
1093 12:45:58.344155
1094 12:45:58.344799 Set Vref, RX VrefLevel [Byte0]: 49
1095 12:45:58.347257 [Byte1]: 49
1096 12:45:58.351897
1097 12:45:58.352511 Set Vref, RX VrefLevel [Byte0]: 50
1098 12:45:58.355116 [Byte1]: 50
1099 12:45:58.359564
1100 12:45:58.360123 Set Vref, RX VrefLevel [Byte0]: 51
1101 12:45:58.362408 [Byte1]: 51
1102 12:45:58.366456
1103 12:45:58.367026 Set Vref, RX VrefLevel [Byte0]: 52
1104 12:45:58.369798 [Byte1]: 52
1105 12:45:58.374666
1106 12:45:58.375228 Set Vref, RX VrefLevel [Byte0]: 53
1107 12:45:58.377375 [Byte1]: 53
1108 12:45:58.382331
1109 12:45:58.382950 Set Vref, RX VrefLevel [Byte0]: 54
1110 12:45:58.384875 [Byte1]: 54
1111 12:45:58.389275
1112 12:45:58.389838 Set Vref, RX VrefLevel [Byte0]: 55
1113 12:45:58.392466 [Byte1]: 55
1114 12:45:58.396624
1115 12:45:58.397085 Set Vref, RX VrefLevel [Byte0]: 56
1116 12:45:58.399868 [Byte1]: 56
1117 12:45:58.404527
1118 12:45:58.405053 Set Vref, RX VrefLevel [Byte0]: 57
1119 12:45:58.407461 [Byte1]: 57
1120 12:45:58.411945
1121 12:45:58.412526 Set Vref, RX VrefLevel [Byte0]: 58
1122 12:45:58.415429 [Byte1]: 58
1123 12:45:58.419233
1124 12:45:58.419698 Set Vref, RX VrefLevel [Byte0]: 59
1125 12:45:58.422330 [Byte1]: 59
1126 12:45:58.426934
1127 12:45:58.427401 Set Vref, RX VrefLevel [Byte0]: 60
1128 12:45:58.430247 [Byte1]: 60
1129 12:45:58.434280
1130 12:45:58.434718 Set Vref, RX VrefLevel [Byte0]: 61
1131 12:45:58.437547 [Byte1]: 61
1132 12:45:58.442391
1133 12:45:58.442933 Set Vref, RX VrefLevel [Byte0]: 62
1134 12:45:58.445516 [Byte1]: 62
1135 12:45:58.449384
1136 12:45:58.449806 Set Vref, RX VrefLevel [Byte0]: 63
1137 12:45:58.452669 [Byte1]: 63
1138 12:45:58.457357
1139 12:45:58.457875 Set Vref, RX VrefLevel [Byte0]: 64
1140 12:45:58.460599 [Byte1]: 64
1141 12:45:58.464482
1142 12:45:58.464900 Set Vref, RX VrefLevel [Byte0]: 65
1143 12:45:58.467634 [Byte1]: 65
1144 12:45:58.472174
1145 12:45:58.472623 Set Vref, RX VrefLevel [Byte0]: 66
1146 12:45:58.475423 [Byte1]: 66
1147 12:45:58.479523
1148 12:45:58.479947 Set Vref, RX VrefLevel [Byte0]: 67
1149 12:45:58.482778 [Byte1]: 67
1150 12:45:58.487264
1151 12:45:58.487683 Set Vref, RX VrefLevel [Byte0]: 68
1152 12:45:58.490311 [Byte1]: 68
1153 12:45:58.494564
1154 12:45:58.494980 Set Vref, RX VrefLevel [Byte0]: 69
1155 12:45:58.498412 [Byte1]: 69
1156 12:45:58.502433
1157 12:45:58.502854 Set Vref, RX VrefLevel [Byte0]: 70
1158 12:45:58.505778 [Byte1]: 70
1159 12:45:58.509692
1160 12:45:58.510113 Set Vref, RX VrefLevel [Byte0]: 71
1161 12:45:58.513173 [Byte1]: 71
1162 12:45:58.517166
1163 12:45:58.517583 Set Vref, RX VrefLevel [Byte0]: 72
1164 12:45:58.520802 [Byte1]: 72
1165 12:45:58.525302
1166 12:45:58.525719 Set Vref, RX VrefLevel [Byte0]: 73
1167 12:45:58.528793 [Byte1]: 73
1168 12:45:58.532417
1169 12:45:58.532860 Set Vref, RX VrefLevel [Byte0]: 74
1170 12:45:58.536105 [Byte1]: 74
1171 12:45:58.539819
1172 12:45:58.540271 Set Vref, RX VrefLevel [Byte0]: 75
1173 12:45:58.543394 [Byte1]: 75
1174 12:45:58.547959
1175 12:45:58.548543 Final RX Vref Byte 0 = 60 to rank0
1176 12:45:58.551043 Final RX Vref Byte 1 = 62 to rank0
1177 12:45:58.554515 Final RX Vref Byte 0 = 60 to rank1
1178 12:45:58.557763 Final RX Vref Byte 1 = 62 to rank1==
1179 12:45:58.560919 Dram Type= 6, Freq= 0, CH_0, rank 0
1180 12:45:58.567830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1181 12:45:58.568415 ==
1182 12:45:58.568854 DQS Delay:
1183 12:45:58.569263 DQS0 = 0, DQS1 = 0
1184 12:45:58.570909 DQM Delay:
1185 12:45:58.571334 DQM0 = 92, DQM1 = 86
1186 12:45:58.574923 DQ Delay:
1187 12:45:58.577767 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1188 12:45:58.581149 DQ4 =96, DQ5 =80, DQ6 =96, DQ7 =100
1189 12:45:58.581682 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1190 12:45:58.587911 DQ12 =92, DQ13 =96, DQ14 =96, DQ15 =92
1191 12:45:58.588490
1192 12:45:58.588925
1193 12:45:58.594239 [DQSOSCAuto] RK0, (LSB)MR18= 0x493f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1194 12:45:58.597764 CH0 RK0: MR19=606, MR18=493F
1195 12:45:58.604451 CH0_RK0: MR19=0x606, MR18=0x493F, DQSOSC=391, MR23=63, INC=96, DEC=64
1196 12:45:58.604986
1197 12:45:58.607888 ----->DramcWriteLeveling(PI) begin...
1198 12:45:58.608462 ==
1199 12:45:58.611188 Dram Type= 6, Freq= 0, CH_0, rank 1
1200 12:45:58.614800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1201 12:45:58.615357 ==
1202 12:45:58.617617 Write leveling (Byte 0): 32 => 32
1203 12:45:58.621389 Write leveling (Byte 1): 30 => 30
1204 12:45:58.624530 DramcWriteLeveling(PI) end<-----
1205 12:45:58.624969
1206 12:45:58.625410 ==
1207 12:45:58.628219 Dram Type= 6, Freq= 0, CH_0, rank 1
1208 12:45:58.631290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1209 12:45:58.631719 ==
1210 12:45:58.634393 [Gating] SW mode calibration
1211 12:45:58.641017 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1212 12:45:58.648093 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1213 12:45:58.650951 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1214 12:45:58.654621 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1215 12:45:58.698924 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1216 12:45:58.699932 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 12:45:58.700402 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 12:45:58.700861 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 12:45:58.701297 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 12:45:58.701727 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 12:45:58.702148 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 12:45:58.702566 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 12:45:58.703073 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 12:45:58.703462 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 12:45:58.743063 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 12:45:58.744032 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 12:45:58.744510 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 12:45:58.744976 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 12:45:58.745419 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 12:45:58.745938 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1231 12:45:58.746352 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1232 12:45:58.746777 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 12:45:58.747196 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 12:45:58.747616 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 12:45:58.786631 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 12:45:58.787267 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 12:45:58.787834 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 12:45:58.788556 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 12:45:58.788936 0 9 8 | B1->B0 | 3232 2c2c | 0 0 | (0 0) (0 0)
1240 12:45:58.789263 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 12:45:58.789573 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 12:45:58.789877 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 12:45:58.790181 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 12:45:58.790481 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 12:45:58.806376 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 12:45:58.807485 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 12:45:58.807923 0 10 8 | B1->B0 | 2727 2626 | 0 0 | (0 0) (1 0)
1248 12:45:58.808497 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 12:45:58.810037 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 12:45:58.813288 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 12:45:58.816678 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 12:45:58.823303 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 12:45:58.826685 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 12:45:58.830560 0 11 4 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
1255 12:45:58.834337 0 11 8 | B1->B0 | 3e3e 3b3b | 0 0 | (0 0) (0 0)
1256 12:45:58.842172 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 12:45:58.845224 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 12:45:58.848607 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 12:45:58.851565 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 12:45:58.859651 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 12:45:58.862764 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 12:45:58.866260 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 12:45:58.869427 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1264 12:45:58.876056 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1265 12:45:58.879358 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 12:45:58.883345 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 12:45:58.889964 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 12:45:58.893289 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 12:45:58.896572 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 12:45:58.903101 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 12:45:58.906216 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 12:45:58.909223 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 12:45:58.916046 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 12:45:58.919242 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 12:45:58.923085 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 12:45:58.929418 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 12:45:58.933039 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 12:45:58.935879 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 12:45:58.939738 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1280 12:45:58.946293 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1281 12:45:58.949606 Total UI for P1: 0, mck2ui 16
1282 12:45:58.953146 best dqsien dly found for B1: ( 0, 14, 8)
1283 12:45:58.955980 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1284 12:45:58.959395 Total UI for P1: 0, mck2ui 16
1285 12:45:58.962932 best dqsien dly found for B0: ( 0, 14, 10)
1286 12:45:58.966128 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
1287 12:45:58.969138 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1288 12:45:58.969574
1289 12:45:58.972796 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
1290 12:45:58.975762 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1291 12:45:58.979841 [Gating] SW calibration Done
1292 12:45:58.980420 ==
1293 12:45:58.982576 Dram Type= 6, Freq= 0, CH_0, rank 1
1294 12:45:58.986412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1295 12:45:58.989850 ==
1296 12:45:58.990280 RX Vref Scan: 0
1297 12:45:58.990715
1298 12:45:58.993347 RX Vref 0 -> 0, step: 1
1299 12:45:58.993879
1300 12:45:58.996116 RX Delay -130 -> 252, step: 16
1301 12:45:58.999669 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1302 12:45:59.002545 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1303 12:45:59.005886 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1304 12:45:59.009294 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1305 12:45:59.016020 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1306 12:45:59.020000 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1307 12:45:59.023020 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1308 12:45:59.026220 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1309 12:45:59.029887 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1310 12:45:59.036187 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1311 12:45:59.039770 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1312 12:45:59.043140 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1313 12:45:59.046236 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1314 12:45:59.050198 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1315 12:45:59.056498 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1316 12:45:59.060021 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1317 12:45:59.060631 ==
1318 12:45:59.063310 Dram Type= 6, Freq= 0, CH_0, rank 1
1319 12:45:59.066270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1320 12:45:59.066710 ==
1321 12:45:59.069747 DQS Delay:
1322 12:45:59.070276 DQS0 = 0, DQS1 = 0
1323 12:45:59.070728 DQM Delay:
1324 12:45:59.073037 DQM0 = 92, DQM1 = 84
1325 12:45:59.073471 DQ Delay:
1326 12:45:59.076357 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1327 12:45:59.079710 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1328 12:45:59.083095 DQ8 =69, DQ9 =77, DQ10 =77, DQ11 =77
1329 12:45:59.086559 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1330 12:45:59.087106
1331 12:45:59.087551
1332 12:45:59.087995 ==
1333 12:45:59.089732 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 12:45:59.096654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 12:45:59.097194 ==
1336 12:45:59.097639
1337 12:45:59.098057
1338 12:45:59.098462 TX Vref Scan disable
1339 12:45:59.099711 == TX Byte 0 ==
1340 12:45:59.102879 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1341 12:45:59.106184 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1342 12:45:59.109429 == TX Byte 1 ==
1343 12:45:59.112830 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1344 12:45:59.116921 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1345 12:45:59.120118 ==
1346 12:45:59.123039 Dram Type= 6, Freq= 0, CH_0, rank 1
1347 12:45:59.126391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1348 12:45:59.126803 ==
1349 12:45:59.139374 TX Vref=22, minBit 12, minWin=27, winSum=450
1350 12:45:59.142433 TX Vref=24, minBit 1, minWin=28, winSum=452
1351 12:45:59.145710 TX Vref=26, minBit 1, minWin=28, winSum=456
1352 12:45:59.149077 TX Vref=28, minBit 2, minWin=28, winSum=453
1353 12:45:59.152603 TX Vref=30, minBit 7, minWin=28, winSum=459
1354 12:45:59.155542 TX Vref=32, minBit 2, minWin=28, winSum=456
1355 12:45:59.162384 [TxChooseVref] Worse bit 7, Min win 28, Win sum 459, Final Vref 30
1356 12:45:59.162966
1357 12:45:59.165647 Final TX Range 1 Vref 30
1358 12:45:59.166123
1359 12:45:59.166604 ==
1360 12:45:59.168798 Dram Type= 6, Freq= 0, CH_0, rank 1
1361 12:45:59.172585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1362 12:45:59.173175 ==
1363 12:45:59.173693
1364 12:45:59.174187
1365 12:45:59.175812 TX Vref Scan disable
1366 12:45:59.179134 == TX Byte 0 ==
1367 12:45:59.182164 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1368 12:45:59.185872 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1369 12:45:59.188932 == TX Byte 1 ==
1370 12:45:59.192201 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1371 12:45:59.195544 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1372 12:45:59.195761
1373 12:45:59.199258 [DATLAT]
1374 12:45:59.199577 Freq=800, CH0 RK1
1375 12:45:59.199726
1376 12:45:59.202231 DATLAT Default: 0xa
1377 12:45:59.202498 0, 0xFFFF, sum = 0
1378 12:45:59.205445 1, 0xFFFF, sum = 0
1379 12:45:59.205637 2, 0xFFFF, sum = 0
1380 12:45:59.208499 3, 0xFFFF, sum = 0
1381 12:45:59.208680 4, 0xFFFF, sum = 0
1382 12:45:59.212027 5, 0xFFFF, sum = 0
1383 12:45:59.212317 6, 0xFFFF, sum = 0
1384 12:45:59.215602 7, 0xFFFF, sum = 0
1385 12:45:59.218692 8, 0xFFFF, sum = 0
1386 12:45:59.218898 9, 0x0, sum = 1
1387 12:45:59.219043 10, 0x0, sum = 2
1388 12:45:59.222054 11, 0x0, sum = 3
1389 12:45:59.222236 12, 0x0, sum = 4
1390 12:45:59.225084 best_step = 10
1391 12:45:59.225264
1392 12:45:59.225403 ==
1393 12:45:59.228898 Dram Type= 6, Freq= 0, CH_0, rank 1
1394 12:45:59.231924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1395 12:45:59.232104 ==
1396 12:45:59.235045 RX Vref Scan: 0
1397 12:45:59.235224
1398 12:45:59.235364 RX Vref 0 -> 0, step: 1
1399 12:45:59.235494
1400 12:45:59.238489 RX Delay -95 -> 252, step: 8
1401 12:45:59.245496 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1402 12:45:59.248670 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1403 12:45:59.252398 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1404 12:45:59.255688 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1405 12:45:59.258949 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1406 12:45:59.265738 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1407 12:45:59.268884 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1408 12:45:59.272342 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1409 12:45:59.275738 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1410 12:45:59.278903 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1411 12:45:59.285784 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1412 12:45:59.288847 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1413 12:45:59.292662 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1414 12:45:59.295840 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1415 12:45:59.299343 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1416 12:45:59.305417 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1417 12:45:59.305960 ==
1418 12:45:59.308838 Dram Type= 6, Freq= 0, CH_0, rank 1
1419 12:45:59.312095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1420 12:45:59.312688 ==
1421 12:45:59.313048 DQS Delay:
1422 12:45:59.315572 DQS0 = 0, DQS1 = 0
1423 12:45:59.316127 DQM Delay:
1424 12:45:59.318972 DQM0 = 93, DQM1 = 84
1425 12:45:59.319520 DQ Delay:
1426 12:45:59.322019 DQ0 =92, DQ1 =96, DQ2 =92, DQ3 =88
1427 12:45:59.325251 DQ4 =92, DQ5 =88, DQ6 =100, DQ7 =100
1428 12:45:59.328908 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1429 12:45:59.332093 DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =92
1430 12:45:59.332680
1431 12:45:59.333037
1432 12:45:59.339154 [DQSOSCAuto] RK1, (LSB)MR18= 0x4010, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1433 12:45:59.342379 CH0 RK1: MR19=606, MR18=4010
1434 12:45:59.348959 CH0_RK1: MR19=0x606, MR18=0x4010, DQSOSC=393, MR23=63, INC=95, DEC=63
1435 12:45:59.352566 [RxdqsGatingPostProcess] freq 800
1436 12:45:59.358659 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1437 12:45:59.362657 Pre-setting of DQS Precalculation
1438 12:45:59.365890 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1439 12:45:59.366346 ==
1440 12:45:59.369117 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 12:45:59.372373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 12:45:59.372930 ==
1443 12:45:59.379077 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1444 12:45:59.385578 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1445 12:45:59.394556 [CA 0] Center 36 (6~67) winsize 62
1446 12:45:59.397462 [CA 1] Center 36 (6~67) winsize 62
1447 12:45:59.400870 [CA 2] Center 35 (5~65) winsize 61
1448 12:45:59.404258 [CA 3] Center 35 (5~65) winsize 61
1449 12:45:59.407121 [CA 4] Center 34 (4~65) winsize 62
1450 12:45:59.410686 [CA 5] Center 34 (4~65) winsize 62
1451 12:45:59.411263
1452 12:45:59.414677 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1453 12:45:59.415250
1454 12:45:59.417603 [CATrainingPosCal] consider 1 rank data
1455 12:45:59.421042 u2DelayCellTimex100 = 270/100 ps
1456 12:45:59.424499 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1457 12:45:59.427511 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1458 12:45:59.430649 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1459 12:45:59.437315 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1460 12:45:59.440624 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1461 12:45:59.444830 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1462 12:45:59.445395
1463 12:45:59.447881 CA PerBit enable=1, Macro0, CA PI delay=34
1464 12:45:59.448535
1465 12:45:59.450878 [CBTSetCACLKResult] CA Dly = 34
1466 12:45:59.451464 CS Dly: 5 (0~36)
1467 12:45:59.451835 ==
1468 12:45:59.454581 Dram Type= 6, Freq= 0, CH_1, rank 1
1469 12:45:59.461020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1470 12:45:59.461479 ==
1471 12:45:59.464208 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1472 12:45:59.470776 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1473 12:45:59.480244 [CA 0] Center 36 (6~67) winsize 62
1474 12:45:59.483384 [CA 1] Center 36 (6~67) winsize 62
1475 12:45:59.486898 [CA 2] Center 34 (4~65) winsize 62
1476 12:45:59.490779 [CA 3] Center 34 (4~65) winsize 62
1477 12:45:59.494065 [CA 4] Center 35 (5~65) winsize 61
1478 12:45:59.497561 [CA 5] Center 34 (4~65) winsize 62
1479 12:45:59.498043
1480 12:45:59.501030 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1481 12:45:59.501508
1482 12:45:59.505162 [CATrainingPosCal] consider 2 rank data
1483 12:45:59.508584 u2DelayCellTimex100 = 270/100 ps
1484 12:45:59.511867 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1485 12:45:59.515950 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1486 12:45:59.520095 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1487 12:45:59.523443 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1488 12:45:59.526840 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1489 12:45:59.530611 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1490 12:45:59.531030
1491 12:45:59.534177 CA PerBit enable=1, Macro0, CA PI delay=34
1492 12:45:59.534713
1493 12:45:59.536863 [CBTSetCACLKResult] CA Dly = 34
1494 12:45:59.537357 CS Dly: 6 (0~38)
1495 12:45:59.537852
1496 12:45:59.540325 ----->DramcWriteLeveling(PI) begin...
1497 12:45:59.540753 ==
1498 12:45:59.543603 Dram Type= 6, Freq= 0, CH_1, rank 0
1499 12:45:59.550609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1500 12:45:59.551198 ==
1501 12:45:59.553637 Write leveling (Byte 0): 27 => 27
1502 12:45:59.557276 Write leveling (Byte 1): 27 => 27
1503 12:45:59.557770 DramcWriteLeveling(PI) end<-----
1504 12:45:59.558101
1505 12:45:59.560569 ==
1506 12:45:59.560987 Dram Type= 6, Freq= 0, CH_1, rank 0
1507 12:45:59.567194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1508 12:45:59.567615 ==
1509 12:45:59.571021 [Gating] SW mode calibration
1510 12:45:59.577405 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1511 12:45:59.580590 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1512 12:45:59.587576 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1513 12:45:59.590988 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1514 12:45:59.594296 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 12:45:59.600995 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 12:45:59.604234 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 12:45:59.607646 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 12:45:59.614130 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 12:45:59.617039 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 12:45:59.620448 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 12:45:59.624042 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 12:45:59.630594 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 12:45:59.633951 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 12:45:59.637139 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 12:45:59.643788 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 12:45:59.647829 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 12:45:59.651049 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 12:45:59.657807 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1529 12:45:59.661091 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1530 12:45:59.664507 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 12:45:59.670934 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 12:45:59.674369 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 12:45:59.677546 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 12:45:59.684260 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 12:45:59.687618 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 12:45:59.690846 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 12:45:59.694819 0 9 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1538 12:45:59.701045 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1539 12:45:59.704460 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 12:45:59.707330 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 12:45:59.714115 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 12:45:59.717385 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 12:45:59.721265 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 12:45:59.727469 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1545 12:45:59.730751 0 10 4 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (0 0)
1546 12:45:59.734571 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (1 0)
1547 12:45:59.741264 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 12:45:59.744231 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 12:45:59.747745 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 12:45:59.754580 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 12:45:59.758066 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 12:45:59.761068 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 12:45:59.764270 0 11 4 | B1->B0 | 2c2c 3636 | 0 1 | (0 0) (0 0)
1554 12:45:59.771473 0 11 8 | B1->B0 | 3f3f 4646 | 1 0 | (1 1) (0 0)
1555 12:45:59.774803 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 12:45:59.777616 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 12:45:59.784260 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 12:45:59.787687 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 12:45:59.790943 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 12:45:59.797677 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 12:45:59.801316 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1562 12:45:59.804717 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 12:45:59.810929 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 12:45:59.814252 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 12:45:59.817669 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 12:45:59.825019 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 12:45:59.828152 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 12:45:59.831254 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 12:45:59.838189 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 12:45:59.841336 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 12:45:59.844759 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 12:45:59.848111 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 12:45:59.854604 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 12:45:59.857893 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 12:45:59.862033 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 12:45:59.867923 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1577 12:45:59.871616 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1578 12:45:59.875328 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1579 12:45:59.878499 Total UI for P1: 0, mck2ui 16
1580 12:45:59.881705 best dqsien dly found for B1: ( 0, 14, 4)
1581 12:45:59.888511 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1582 12:45:59.889088 Total UI for P1: 0, mck2ui 16
1583 12:45:59.894846 best dqsien dly found for B0: ( 0, 14, 8)
1584 12:45:59.897793 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1585 12:45:59.901405 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1586 12:45:59.901970
1587 12:45:59.904684 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1588 12:45:59.908276 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1589 12:45:59.911361 [Gating] SW calibration Done
1590 12:45:59.911927 ==
1591 12:45:59.914856 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 12:45:59.918181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 12:45:59.918756 ==
1594 12:45:59.921297 RX Vref Scan: 0
1595 12:45:59.921756
1596 12:45:59.922113 RX Vref 0 -> 0, step: 1
1597 12:45:59.922449
1598 12:45:59.924512 RX Delay -130 -> 252, step: 16
1599 12:45:59.927914 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1600 12:45:59.934453 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1601 12:45:59.937608 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1602 12:45:59.941461 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1603 12:45:59.944237 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1604 12:45:59.948338 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1605 12:45:59.954563 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1606 12:45:59.957877 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1607 12:45:59.961367 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1608 12:45:59.964767 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1609 12:45:59.967742 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1610 12:45:59.975745 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1611 12:45:59.978076 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1612 12:45:59.981411 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1613 12:45:59.984889 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1614 12:45:59.988031 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1615 12:45:59.988642 ==
1616 12:45:59.991230 Dram Type= 6, Freq= 0, CH_1, rank 0
1617 12:45:59.998511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1618 12:45:59.998953 ==
1619 12:45:59.999287 DQS Delay:
1620 12:46:00.001048 DQS0 = 0, DQS1 = 0
1621 12:46:00.001465 DQM Delay:
1622 12:46:00.001796 DQM0 = 93, DQM1 = 86
1623 12:46:00.004940 DQ Delay:
1624 12:46:00.008441 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1625 12:46:00.011814 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1626 12:46:00.015101 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1627 12:46:00.018135 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1628 12:46:00.018700
1629 12:46:00.019065
1630 12:46:00.019404 ==
1631 12:46:00.021087 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 12:46:00.024359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 12:46:00.024784 ==
1634 12:46:00.025111
1635 12:46:00.025414
1636 12:46:00.027609 TX Vref Scan disable
1637 12:46:00.031003 == TX Byte 0 ==
1638 12:46:00.034862 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1639 12:46:00.038029 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1640 12:46:00.041510 == TX Byte 1 ==
1641 12:46:00.044525 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1642 12:46:00.048502 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1643 12:46:00.049010 ==
1644 12:46:00.051257 Dram Type= 6, Freq= 0, CH_1, rank 0
1645 12:46:00.054747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1646 12:46:00.055170 ==
1647 12:46:00.068683 TX Vref=22, minBit 0, minWin=26, winSum=431
1648 12:46:00.072843 TX Vref=24, minBit 1, minWin=27, winSum=444
1649 12:46:00.076237 TX Vref=26, minBit 1, minWin=27, winSum=445
1650 12:46:00.079567 TX Vref=28, minBit 0, minWin=27, winSum=450
1651 12:46:00.083128 TX Vref=30, minBit 1, minWin=27, winSum=450
1652 12:46:00.086260 TX Vref=32, minBit 0, minWin=27, winSum=445
1653 12:46:00.093231 [TxChooseVref] Worse bit 0, Min win 27, Win sum 450, Final Vref 28
1654 12:46:00.093755
1655 12:46:00.096371 Final TX Range 1 Vref 28
1656 12:46:00.096904
1657 12:46:00.097235 ==
1658 12:46:00.099818 Dram Type= 6, Freq= 0, CH_1, rank 0
1659 12:46:00.103232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1660 12:46:00.103754 ==
1661 12:46:00.104088
1662 12:46:00.104445
1663 12:46:00.106377 TX Vref Scan disable
1664 12:46:00.109836 == TX Byte 0 ==
1665 12:46:00.113632 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1666 12:46:00.116718 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1667 12:46:00.120008 == TX Byte 1 ==
1668 12:46:00.123011 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1669 12:46:00.126288 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1670 12:46:00.126711
1671 12:46:00.127039 [DATLAT]
1672 12:46:00.130524 Freq=800, CH1 RK0
1673 12:46:00.131042
1674 12:46:00.131376 DATLAT Default: 0xa
1675 12:46:00.132969 0, 0xFFFF, sum = 0
1676 12:46:00.137013 1, 0xFFFF, sum = 0
1677 12:46:00.137542 2, 0xFFFF, sum = 0
1678 12:46:00.139638 3, 0xFFFF, sum = 0
1679 12:46:00.140075 4, 0xFFFF, sum = 0
1680 12:46:00.142962 5, 0xFFFF, sum = 0
1681 12:46:00.143386 6, 0xFFFF, sum = 0
1682 12:46:00.147175 7, 0xFFFF, sum = 0
1683 12:46:00.147709 8, 0xFFFF, sum = 0
1684 12:46:00.150479 9, 0x0, sum = 1
1685 12:46:00.151009 10, 0x0, sum = 2
1686 12:46:00.153480 11, 0x0, sum = 3
1687 12:46:00.153902 12, 0x0, sum = 4
1688 12:46:00.154234 best_step = 10
1689 12:46:00.154554
1690 12:46:00.157247 ==
1691 12:46:00.160179 Dram Type= 6, Freq= 0, CH_1, rank 0
1692 12:46:00.163807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1693 12:46:00.164376 ==
1694 12:46:00.164720 RX Vref Scan: 1
1695 12:46:00.165030
1696 12:46:00.166331 Set Vref Range= 32 -> 127
1697 12:46:00.166747
1698 12:46:00.170310 RX Vref 32 -> 127, step: 1
1699 12:46:00.170838
1700 12:46:00.173415 RX Delay -79 -> 252, step: 8
1701 12:46:00.173944
1702 12:46:00.176710 Set Vref, RX VrefLevel [Byte0]: 32
1703 12:46:00.180212 [Byte1]: 32
1704 12:46:00.180780
1705 12:46:00.183305 Set Vref, RX VrefLevel [Byte0]: 33
1706 12:46:00.186746 [Byte1]: 33
1707 12:46:00.187269
1708 12:46:00.189656 Set Vref, RX VrefLevel [Byte0]: 34
1709 12:46:00.193175 [Byte1]: 34
1710 12:46:00.196358
1711 12:46:00.196776 Set Vref, RX VrefLevel [Byte0]: 35
1712 12:46:00.200118 [Byte1]: 35
1713 12:46:00.204152
1714 12:46:00.204729 Set Vref, RX VrefLevel [Byte0]: 36
1715 12:46:00.207316 [Byte1]: 36
1716 12:46:00.211347
1717 12:46:00.211762 Set Vref, RX VrefLevel [Byte0]: 37
1718 12:46:00.214844 [Byte1]: 37
1719 12:46:00.219189
1720 12:46:00.219758 Set Vref, RX VrefLevel [Byte0]: 38
1721 12:46:00.222364 [Byte1]: 38
1722 12:46:00.226629
1723 12:46:00.227091 Set Vref, RX VrefLevel [Byte0]: 39
1724 12:46:00.230014 [Byte1]: 39
1725 12:46:00.234391
1726 12:46:00.234967 Set Vref, RX VrefLevel [Byte0]: 40
1727 12:46:00.237454 [Byte1]: 40
1728 12:46:00.241948
1729 12:46:00.242367 Set Vref, RX VrefLevel [Byte0]: 41
1730 12:46:00.244670 [Byte1]: 41
1731 12:46:00.249525
1732 12:46:00.250052 Set Vref, RX VrefLevel [Byte0]: 42
1733 12:46:00.252840 [Byte1]: 42
1734 12:46:00.256848
1735 12:46:00.257372 Set Vref, RX VrefLevel [Byte0]: 43
1736 12:46:00.259991 [Byte1]: 43
1737 12:46:00.264843
1738 12:46:00.265370 Set Vref, RX VrefLevel [Byte0]: 44
1739 12:46:00.267949 [Byte1]: 44
1740 12:46:00.271566
1741 12:46:00.271985 Set Vref, RX VrefLevel [Byte0]: 45
1742 12:46:00.275170 [Byte1]: 45
1743 12:46:00.279793
1744 12:46:00.280340 Set Vref, RX VrefLevel [Byte0]: 46
1745 12:46:00.283169 [Byte1]: 46
1746 12:46:00.287051
1747 12:46:00.287570 Set Vref, RX VrefLevel [Byte0]: 47
1748 12:46:00.290326 [Byte1]: 47
1749 12:46:00.294497
1750 12:46:00.295019 Set Vref, RX VrefLevel [Byte0]: 48
1751 12:46:00.297754 [Byte1]: 48
1752 12:46:00.302175
1753 12:46:00.302779 Set Vref, RX VrefLevel [Byte0]: 49
1754 12:46:00.305627 [Byte1]: 49
1755 12:46:00.309865
1756 12:46:00.310278 Set Vref, RX VrefLevel [Byte0]: 50
1757 12:46:00.312872 [Byte1]: 50
1758 12:46:00.317358
1759 12:46:00.317890 Set Vref, RX VrefLevel [Byte0]: 51
1760 12:46:00.320169 [Byte1]: 51
1761 12:46:00.324427
1762 12:46:00.324852 Set Vref, RX VrefLevel [Byte0]: 52
1763 12:46:00.327849 [Byte1]: 52
1764 12:46:00.332093
1765 12:46:00.332558 Set Vref, RX VrefLevel [Byte0]: 53
1766 12:46:00.335515 [Byte1]: 53
1767 12:46:00.339591
1768 12:46:00.340107 Set Vref, RX VrefLevel [Byte0]: 54
1769 12:46:00.343156 [Byte1]: 54
1770 12:46:00.347388
1771 12:46:00.350970 Set Vref, RX VrefLevel [Byte0]: 55
1772 12:46:00.351495 [Byte1]: 55
1773 12:46:00.355193
1774 12:46:00.355609 Set Vref, RX VrefLevel [Byte0]: 56
1775 12:46:00.358064 [Byte1]: 56
1776 12:46:00.362485
1777 12:46:00.363141 Set Vref, RX VrefLevel [Byte0]: 57
1778 12:46:00.365703 [Byte1]: 57
1779 12:46:00.370459
1780 12:46:00.370985 Set Vref, RX VrefLevel [Byte0]: 58
1781 12:46:00.373416 [Byte1]: 58
1782 12:46:00.377370
1783 12:46:00.377808 Set Vref, RX VrefLevel [Byte0]: 59
1784 12:46:00.380964 [Byte1]: 59
1785 12:46:00.385304
1786 12:46:00.385825 Set Vref, RX VrefLevel [Byte0]: 60
1787 12:46:00.388582 [Byte1]: 60
1788 12:46:00.392844
1789 12:46:00.393377 Set Vref, RX VrefLevel [Byte0]: 61
1790 12:46:00.395955 [Byte1]: 61
1791 12:46:00.400146
1792 12:46:00.400724 Set Vref, RX VrefLevel [Byte0]: 62
1793 12:46:00.403226 [Byte1]: 62
1794 12:46:00.407693
1795 12:46:00.408108 Set Vref, RX VrefLevel [Byte0]: 63
1796 12:46:00.410829 [Byte1]: 63
1797 12:46:00.415403
1798 12:46:00.415923 Set Vref, RX VrefLevel [Byte0]: 64
1799 12:46:00.418791 [Byte1]: 64
1800 12:46:00.422649
1801 12:46:00.423171 Set Vref, RX VrefLevel [Byte0]: 65
1802 12:46:00.426091 [Byte1]: 65
1803 12:46:00.430683
1804 12:46:00.431099 Set Vref, RX VrefLevel [Byte0]: 66
1805 12:46:00.433972 [Byte1]: 66
1806 12:46:00.437953
1807 12:46:00.438367 Set Vref, RX VrefLevel [Byte0]: 67
1808 12:46:00.441367 [Byte1]: 67
1809 12:46:00.445304
1810 12:46:00.445723 Set Vref, RX VrefLevel [Byte0]: 68
1811 12:46:00.448450 [Byte1]: 68
1812 12:46:00.453104
1813 12:46:00.453622 Set Vref, RX VrefLevel [Byte0]: 69
1814 12:46:00.455962 [Byte1]: 69
1815 12:46:00.460565
1816 12:46:00.460981 Set Vref, RX VrefLevel [Byte0]: 70
1817 12:46:00.464015 [Byte1]: 70
1818 12:46:00.468020
1819 12:46:00.468588 Set Vref, RX VrefLevel [Byte0]: 71
1820 12:46:00.471542 [Byte1]: 71
1821 12:46:00.475596
1822 12:46:00.476014 Set Vref, RX VrefLevel [Byte0]: 72
1823 12:46:00.478629 [Byte1]: 72
1824 12:46:00.483314
1825 12:46:00.483840 Set Vref, RX VrefLevel [Byte0]: 73
1826 12:46:00.486350 [Byte1]: 73
1827 12:46:00.490804
1828 12:46:00.491314 Final RX Vref Byte 0 = 58 to rank0
1829 12:46:00.493947 Final RX Vref Byte 1 = 54 to rank0
1830 12:46:00.497593 Final RX Vref Byte 0 = 58 to rank1
1831 12:46:00.500905 Final RX Vref Byte 1 = 54 to rank1==
1832 12:46:00.504435 Dram Type= 6, Freq= 0, CH_1, rank 0
1833 12:46:00.507568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1834 12:46:00.510970 ==
1835 12:46:00.511402 DQS Delay:
1836 12:46:00.511730 DQS0 = 0, DQS1 = 0
1837 12:46:00.514199 DQM Delay:
1838 12:46:00.514614 DQM0 = 96, DQM1 = 90
1839 12:46:00.517401 DQ Delay:
1840 12:46:00.521027 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =92
1841 12:46:00.524424 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1842 12:46:00.527634 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1843 12:46:00.530688 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1844 12:46:00.531125
1845 12:46:00.531519
1846 12:46:00.537692 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a46, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
1847 12:46:00.540974 CH1 RK0: MR19=606, MR18=2A46
1848 12:46:00.547235 CH1_RK0: MR19=0x606, MR18=0x2A46, DQSOSC=392, MR23=63, INC=96, DEC=64
1849 12:46:00.547772
1850 12:46:00.550597 ----->DramcWriteLeveling(PI) begin...
1851 12:46:00.551194 ==
1852 12:46:00.553914 Dram Type= 6, Freq= 0, CH_1, rank 1
1853 12:46:00.557099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1854 12:46:00.557618 ==
1855 12:46:00.560574 Write leveling (Byte 0): 28 => 28
1856 12:46:00.564452 Write leveling (Byte 1): 30 => 30
1857 12:46:00.567408 DramcWriteLeveling(PI) end<-----
1858 12:46:00.568013
1859 12:46:00.568409 ==
1860 12:46:00.570850 Dram Type= 6, Freq= 0, CH_1, rank 1
1861 12:46:00.574594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1862 12:46:00.575018 ==
1863 12:46:00.577977 [Gating] SW mode calibration
1864 12:46:00.584410 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1865 12:46:00.591207 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1866 12:46:00.594149 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1867 12:46:00.597694 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1868 12:46:00.604638 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 12:46:00.607636 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 12:46:00.610796 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 12:46:00.617847 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 12:46:00.621176 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 12:46:00.624537 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 12:46:00.631005 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 12:46:00.634065 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 12:46:00.637525 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 12:46:00.641239 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 12:46:00.647737 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 12:46:00.651063 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 12:46:00.654991 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 12:46:00.661698 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 12:46:00.665181 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1883 12:46:00.668030 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1884 12:46:00.674366 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 12:46:00.677886 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 12:46:00.681243 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 12:46:00.688061 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 12:46:00.691159 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 12:46:00.695070 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 12:46:00.701792 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 12:46:00.705192 0 9 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (1 1)
1892 12:46:00.708117 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1893 12:46:00.715124 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 12:46:00.718307 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1895 12:46:00.721155 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 12:46:00.724697 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 12:46:00.731630 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 12:46:00.734553 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1899 12:46:00.738281 0 10 4 | B1->B0 | 2a2a 3131 | 0 0 | (0 0) (0 0)
1900 12:46:00.744834 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1901 12:46:00.747821 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 12:46:00.751361 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 12:46:00.757881 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 12:46:00.761291 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 12:46:00.764830 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 12:46:00.771385 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 12:46:00.774394 0 11 4 | B1->B0 | 3a3a 2a2a | 0 0 | (0 0) (0 0)
1908 12:46:00.777968 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 12:46:00.784695 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 12:46:00.788158 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 12:46:00.791264 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 12:46:00.798378 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 12:46:00.801877 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 12:46:00.804640 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1915 12:46:00.807975 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1916 12:46:00.814872 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 12:46:00.818214 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 12:46:00.821474 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 12:46:00.827863 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 12:46:00.831536 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 12:46:00.834559 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 12:46:00.841730 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 12:46:00.845035 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 12:46:00.848595 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 12:46:00.855210 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 12:46:00.858252 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 12:46:00.861415 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 12:46:00.868468 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 12:46:00.871973 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 12:46:00.874814 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1931 12:46:00.881516 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1932 12:46:00.885264 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 12:46:00.888155 Total UI for P1: 0, mck2ui 16
1934 12:46:00.891886 best dqsien dly found for B0: ( 0, 14, 4)
1935 12:46:00.894966 Total UI for P1: 0, mck2ui 16
1936 12:46:00.898097 best dqsien dly found for B1: ( 0, 14, 2)
1937 12:46:00.901805 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1938 12:46:00.904844 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1939 12:46:00.905306
1940 12:46:00.908107 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1941 12:46:00.912005 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1942 12:46:00.914914 [Gating] SW calibration Done
1943 12:46:00.915377 ==
1944 12:46:00.918491 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 12:46:00.921615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 12:46:00.922080 ==
1947 12:46:00.924956 RX Vref Scan: 0
1948 12:46:00.925374
1949 12:46:00.925703 RX Vref 0 -> 0, step: 1
1950 12:46:00.926011
1951 12:46:00.928345 RX Delay -130 -> 252, step: 16
1952 12:46:00.931466 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1953 12:46:00.938135 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1954 12:46:00.942154 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1955 12:46:00.944905 iDelay=222, Bit 3, Center 93 (-2 ~ 189) 192
1956 12:46:00.948211 iDelay=222, Bit 4, Center 93 (-2 ~ 189) 192
1957 12:46:00.951547 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1958 12:46:00.958926 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1959 12:46:00.962036 iDelay=222, Bit 7, Center 101 (-2 ~ 205) 208
1960 12:46:00.965662 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1961 12:46:00.968134 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1962 12:46:00.971701 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1963 12:46:00.978737 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1964 12:46:00.981855 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1965 12:46:00.984819 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1966 12:46:00.988850 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1967 12:46:00.992148 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1968 12:46:00.995199 ==
1969 12:46:00.995659 Dram Type= 6, Freq= 0, CH_1, rank 1
1970 12:46:01.001503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1971 12:46:01.002138 ==
1972 12:46:01.002515 DQS Delay:
1973 12:46:01.005041 DQS0 = 0, DQS1 = 0
1974 12:46:01.005498 DQM Delay:
1975 12:46:01.008615 DQM0 = 95, DQM1 = 91
1976 12:46:01.009074 DQ Delay:
1977 12:46:01.011563 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1978 12:46:01.014912 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =101
1979 12:46:01.018693 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1980 12:46:01.021311 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1981 12:46:01.021733
1982 12:46:01.022065
1983 12:46:01.022371 ==
1984 12:46:01.025082 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 12:46:01.028376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 12:46:01.028794 ==
1987 12:46:01.029122
1988 12:46:01.029428
1989 12:46:01.031613 TX Vref Scan disable
1990 12:46:01.034773 == TX Byte 0 ==
1991 12:46:01.038572 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1992 12:46:01.041433 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1993 12:46:01.045314 == TX Byte 1 ==
1994 12:46:01.048679 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1995 12:46:01.052077 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1996 12:46:01.052728 ==
1997 12:46:01.055522 Dram Type= 6, Freq= 0, CH_1, rank 1
1998 12:46:01.061506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1999 12:46:01.062013 ==
2000 12:46:01.073363 TX Vref=22, minBit 1, minWin=26, winSum=437
2001 12:46:01.076917 TX Vref=24, minBit 1, minWin=26, winSum=444
2002 12:46:01.080070 TX Vref=26, minBit 2, minWin=27, winSum=449
2003 12:46:01.083286 TX Vref=28, minBit 2, minWin=27, winSum=450
2004 12:46:01.086356 TX Vref=30, minBit 2, minWin=27, winSum=453
2005 12:46:01.090553 TX Vref=32, minBit 2, minWin=27, winSum=450
2006 12:46:01.096974 [TxChooseVref] Worse bit 2, Min win 27, Win sum 453, Final Vref 30
2007 12:46:01.097516
2008 12:46:01.099932 Final TX Range 1 Vref 30
2009 12:46:01.100399
2010 12:46:01.100738 ==
2011 12:46:01.103178 Dram Type= 6, Freq= 0, CH_1, rank 1
2012 12:46:01.106935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2013 12:46:01.107507 ==
2014 12:46:01.107838
2015 12:46:01.108142
2016 12:46:01.109933 TX Vref Scan disable
2017 12:46:01.113368 == TX Byte 0 ==
2018 12:46:01.117010 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2019 12:46:01.120267 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2020 12:46:01.123414 == TX Byte 1 ==
2021 12:46:01.126876 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2022 12:46:01.129809 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2023 12:46:01.130269
2024 12:46:01.133217 [DATLAT]
2025 12:46:01.133633 Freq=800, CH1 RK1
2026 12:46:01.133963
2027 12:46:01.137081 DATLAT Default: 0xa
2028 12:46:01.137495 0, 0xFFFF, sum = 0
2029 12:46:01.140392 1, 0xFFFF, sum = 0
2030 12:46:01.141013 2, 0xFFFF, sum = 0
2031 12:46:01.143677 3, 0xFFFF, sum = 0
2032 12:46:01.144105 4, 0xFFFF, sum = 0
2033 12:46:01.146493 5, 0xFFFF, sum = 0
2034 12:46:01.146912 6, 0xFFFF, sum = 0
2035 12:46:01.150460 7, 0xFFFF, sum = 0
2036 12:46:01.150902 8, 0xFFFF, sum = 0
2037 12:46:01.153314 9, 0x0, sum = 1
2038 12:46:01.153834 10, 0x0, sum = 2
2039 12:46:01.156780 11, 0x0, sum = 3
2040 12:46:01.157205 12, 0x0, sum = 4
2041 12:46:01.159886 best_step = 10
2042 12:46:01.160335
2043 12:46:01.160706 ==
2044 12:46:01.163476 Dram Type= 6, Freq= 0, CH_1, rank 1
2045 12:46:01.167064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2046 12:46:01.167592 ==
2047 12:46:01.170566 RX Vref Scan: 0
2048 12:46:01.171095
2049 12:46:01.171429 RX Vref 0 -> 0, step: 1
2050 12:46:01.171736
2051 12:46:01.173616 RX Delay -79 -> 252, step: 8
2052 12:46:01.180157 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2053 12:46:01.183522 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2054 12:46:01.186870 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2055 12:46:01.190213 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2056 12:46:01.193492 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2057 12:46:01.197021 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2058 12:46:01.200824 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2059 12:46:01.207262 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2060 12:46:01.210804 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2061 12:46:01.214037 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2062 12:46:01.217255 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
2063 12:46:01.220457 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2064 12:46:01.226991 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2065 12:46:01.230673 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2066 12:46:01.234330 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2067 12:46:01.237647 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2068 12:46:01.238173 ==
2069 12:46:01.240801 Dram Type= 6, Freq= 0, CH_1, rank 1
2070 12:46:01.244085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2071 12:46:01.247145 ==
2072 12:46:01.247571 DQS Delay:
2073 12:46:01.247899 DQS0 = 0, DQS1 = 0
2074 12:46:01.250357 DQM Delay:
2075 12:46:01.250775 DQM0 = 97, DQM1 = 91
2076 12:46:01.253927 DQ Delay:
2077 12:46:01.256983 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2078 12:46:01.257407 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
2079 12:46:01.260333 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =84
2080 12:46:01.267673 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2081 12:46:01.268209
2082 12:46:01.268606
2083 12:46:01.274438 [DQSOSCAuto] RK1, (LSB)MR18= 0x4711, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
2084 12:46:01.277403 CH1 RK1: MR19=606, MR18=4711
2085 12:46:01.283950 CH1_RK1: MR19=0x606, MR18=0x4711, DQSOSC=392, MR23=63, INC=96, DEC=64
2086 12:46:01.287228 [RxdqsGatingPostProcess] freq 800
2087 12:46:01.290676 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2088 12:46:01.293823 Pre-setting of DQS Precalculation
2089 12:46:01.300554 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2090 12:46:01.307219 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2091 12:46:01.314313 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2092 12:46:01.314841
2093 12:46:01.315176
2094 12:46:01.317074 [Calibration Summary] 1600 Mbps
2095 12:46:01.317493 CH 0, Rank 0
2096 12:46:01.320533 SW Impedance : PASS
2097 12:46:01.323904 DUTY Scan : NO K
2098 12:46:01.324344 ZQ Calibration : PASS
2099 12:46:01.327590 Jitter Meter : NO K
2100 12:46:01.328008 CBT Training : PASS
2101 12:46:01.330977 Write leveling : PASS
2102 12:46:01.334246 RX DQS gating : PASS
2103 12:46:01.334665 RX DQ/DQS(RDDQC) : PASS
2104 12:46:01.337261 TX DQ/DQS : PASS
2105 12:46:01.340682 RX DATLAT : PASS
2106 12:46:01.341098 RX DQ/DQS(Engine): PASS
2107 12:46:01.344322 TX OE : NO K
2108 12:46:01.344857 All Pass.
2109 12:46:01.345187
2110 12:46:01.347302 CH 0, Rank 1
2111 12:46:01.347715 SW Impedance : PASS
2112 12:46:01.350644 DUTY Scan : NO K
2113 12:46:01.354212 ZQ Calibration : PASS
2114 12:46:01.354735 Jitter Meter : NO K
2115 12:46:01.357382 CBT Training : PASS
2116 12:46:01.357804 Write leveling : PASS
2117 12:46:01.361183 RX DQS gating : PASS
2118 12:46:01.364750 RX DQ/DQS(RDDQC) : PASS
2119 12:46:01.365275 TX DQ/DQS : PASS
2120 12:46:01.367960 RX DATLAT : PASS
2121 12:46:01.371074 RX DQ/DQS(Engine): PASS
2122 12:46:01.371598 TX OE : NO K
2123 12:46:01.374390 All Pass.
2124 12:46:01.374917
2125 12:46:01.375253 CH 1, Rank 0
2126 12:46:01.378024 SW Impedance : PASS
2127 12:46:01.378546 DUTY Scan : NO K
2128 12:46:01.380973 ZQ Calibration : PASS
2129 12:46:01.384418 Jitter Meter : NO K
2130 12:46:01.384948 CBT Training : PASS
2131 12:46:01.387500 Write leveling : PASS
2132 12:46:01.391096 RX DQS gating : PASS
2133 12:46:01.391621 RX DQ/DQS(RDDQC) : PASS
2134 12:46:01.394294 TX DQ/DQS : PASS
2135 12:46:01.394823 RX DATLAT : PASS
2136 12:46:01.397578 RX DQ/DQS(Engine): PASS
2137 12:46:01.401094 TX OE : NO K
2138 12:46:01.401513 All Pass.
2139 12:46:01.401842
2140 12:46:01.402151 CH 1, Rank 1
2141 12:46:01.404661 SW Impedance : PASS
2142 12:46:01.407940 DUTY Scan : NO K
2143 12:46:01.408515 ZQ Calibration : PASS
2144 12:46:01.411261 Jitter Meter : NO K
2145 12:46:01.414292 CBT Training : PASS
2146 12:46:01.414711 Write leveling : PASS
2147 12:46:01.418250 RX DQS gating : PASS
2148 12:46:01.421123 RX DQ/DQS(RDDQC) : PASS
2149 12:46:01.421545 TX DQ/DQS : PASS
2150 12:46:01.424983 RX DATLAT : PASS
2151 12:46:01.428061 RX DQ/DQS(Engine): PASS
2152 12:46:01.428577 TX OE : NO K
2153 12:46:01.428915 All Pass.
2154 12:46:01.431007
2155 12:46:01.431422 DramC Write-DBI off
2156 12:46:01.434627 PER_BANK_REFRESH: Hybrid Mode
2157 12:46:01.435044 TX_TRACKING: ON
2158 12:46:01.437717 [GetDramInforAfterCalByMRR] Vendor 6.
2159 12:46:01.441328 [GetDramInforAfterCalByMRR] Revision 606.
2160 12:46:01.447970 [GetDramInforAfterCalByMRR] Revision 2 0.
2161 12:46:01.448568 MR0 0x3b3b
2162 12:46:01.448909 MR8 0x5151
2163 12:46:01.451225 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2164 12:46:01.451643
2165 12:46:01.454272 MR0 0x3b3b
2166 12:46:01.454691 MR8 0x5151
2167 12:46:01.457795 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2168 12:46:01.458214
2169 12:46:01.467932 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2170 12:46:01.471000 [FAST_K] Save calibration result to emmc
2171 12:46:01.474371 [FAST_K] Save calibration result to emmc
2172 12:46:01.477769 dram_init: config_dvfs: 1
2173 12:46:01.481428 dramc_set_vcore_voltage set vcore to 662500
2174 12:46:01.481845 Read voltage for 1200, 2
2175 12:46:01.484595 Vio18 = 0
2176 12:46:01.485045 Vcore = 662500
2177 12:46:01.485375 Vdram = 0
2178 12:46:01.487662 Vddq = 0
2179 12:46:01.488078 Vmddr = 0
2180 12:46:01.491256 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2181 12:46:01.498292 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2182 12:46:01.500938 MEM_TYPE=3, freq_sel=15
2183 12:46:01.504446 sv_algorithm_assistance_LP4_1600
2184 12:46:01.508221 ============ PULL DRAM RESETB DOWN ============
2185 12:46:01.511329 ========== PULL DRAM RESETB DOWN end =========
2186 12:46:01.518024 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2187 12:46:01.521208 ===================================
2188 12:46:01.521792 LPDDR4 DRAM CONFIGURATION
2189 12:46:01.524670 ===================================
2190 12:46:01.527957 EX_ROW_EN[0] = 0x0
2191 12:46:01.528552 EX_ROW_EN[1] = 0x0
2192 12:46:01.531071 LP4Y_EN = 0x0
2193 12:46:01.531534 WORK_FSP = 0x0
2194 12:46:01.534418 WL = 0x4
2195 12:46:01.534898 RL = 0x4
2196 12:46:01.538119 BL = 0x2
2197 12:46:01.538537 RPST = 0x0
2198 12:46:01.541585 RD_PRE = 0x0
2199 12:46:01.545249 WR_PRE = 0x1
2200 12:46:01.545772 WR_PST = 0x0
2201 12:46:01.548178 DBI_WR = 0x0
2202 12:46:01.548632 DBI_RD = 0x0
2203 12:46:01.551521 OTF = 0x1
2204 12:46:01.555095 ===================================
2205 12:46:01.558106 ===================================
2206 12:46:01.558525 ANA top config
2207 12:46:01.561153 ===================================
2208 12:46:01.564709 DLL_ASYNC_EN = 0
2209 12:46:01.565125 ALL_SLAVE_EN = 0
2210 12:46:01.568156 NEW_RANK_MODE = 1
2211 12:46:01.571338 DLL_IDLE_MODE = 1
2212 12:46:01.574863 LP45_APHY_COMB_EN = 1
2213 12:46:01.578418 TX_ODT_DIS = 1
2214 12:46:01.578837 NEW_8X_MODE = 1
2215 12:46:01.581351 ===================================
2216 12:46:01.584670 ===================================
2217 12:46:01.587799 data_rate = 2400
2218 12:46:01.591278 CKR = 1
2219 12:46:01.595280 DQ_P2S_RATIO = 8
2220 12:46:01.598490 ===================================
2221 12:46:01.601175 CA_P2S_RATIO = 8
2222 12:46:01.601594 DQ_CA_OPEN = 0
2223 12:46:01.604806 DQ_SEMI_OPEN = 0
2224 12:46:01.608009 CA_SEMI_OPEN = 0
2225 12:46:01.611358 CA_FULL_RATE = 0
2226 12:46:01.614845 DQ_CKDIV4_EN = 0
2227 12:46:01.618075 CA_CKDIV4_EN = 0
2228 12:46:01.618597 CA_PREDIV_EN = 0
2229 12:46:01.621554 PH8_DLY = 17
2230 12:46:01.624522 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2231 12:46:01.628131 DQ_AAMCK_DIV = 4
2232 12:46:01.632080 CA_AAMCK_DIV = 4
2233 12:46:01.634454 CA_ADMCK_DIV = 4
2234 12:46:01.634874 DQ_TRACK_CA_EN = 0
2235 12:46:01.638069 CA_PICK = 1200
2236 12:46:01.640982 CA_MCKIO = 1200
2237 12:46:01.644665 MCKIO_SEMI = 0
2238 12:46:01.647657 PLL_FREQ = 2366
2239 12:46:01.650943 DQ_UI_PI_RATIO = 32
2240 12:46:01.654561 CA_UI_PI_RATIO = 0
2241 12:46:01.657635 ===================================
2242 12:46:01.661683 ===================================
2243 12:46:01.662211 memory_type:LPDDR4
2244 12:46:01.664253 GP_NUM : 10
2245 12:46:01.668421 SRAM_EN : 1
2246 12:46:01.668952 MD32_EN : 0
2247 12:46:01.671595 ===================================
2248 12:46:01.675272 [ANA_INIT] >>>>>>>>>>>>>>
2249 12:46:01.678485 <<<<<< [CONFIGURE PHASE]: ANA_TX
2250 12:46:01.681388 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2251 12:46:01.684604 ===================================
2252 12:46:01.687791 data_rate = 2400,PCW = 0X5b00
2253 12:46:01.691893 ===================================
2254 12:46:01.694770 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2255 12:46:01.698466 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2256 12:46:01.704957 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2257 12:46:01.708014 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2258 12:46:01.711774 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2259 12:46:01.715195 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2260 12:46:01.718490 [ANA_INIT] flow start
2261 12:46:01.721326 [ANA_INIT] PLL >>>>>>>>
2262 12:46:01.721747 [ANA_INIT] PLL <<<<<<<<
2263 12:46:01.724962 [ANA_INIT] MIDPI >>>>>>>>
2264 12:46:01.728152 [ANA_INIT] MIDPI <<<<<<<<
2265 12:46:01.728617 [ANA_INIT] DLL >>>>>>>>
2266 12:46:01.731560 [ANA_INIT] DLL <<<<<<<<
2267 12:46:01.734585 [ANA_INIT] flow end
2268 12:46:01.738214 ============ LP4 DIFF to SE enter ============
2269 12:46:01.741500 ============ LP4 DIFF to SE exit ============
2270 12:46:01.745036 [ANA_INIT] <<<<<<<<<<<<<
2271 12:46:01.748058 [Flow] Enable top DCM control >>>>>
2272 12:46:01.751345 [Flow] Enable top DCM control <<<<<
2273 12:46:01.755052 Enable DLL master slave shuffle
2274 12:46:01.758248 ==============================================================
2275 12:46:01.761531 Gating Mode config
2276 12:46:01.764865 ==============================================================
2277 12:46:01.768707 Config description:
2278 12:46:01.778588 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2279 12:46:01.785045 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2280 12:46:01.788332 SELPH_MODE 0: By rank 1: By Phase
2281 12:46:01.795468 ==============================================================
2282 12:46:01.798814 GAT_TRACK_EN = 1
2283 12:46:01.801740 RX_GATING_MODE = 2
2284 12:46:01.804950 RX_GATING_TRACK_MODE = 2
2285 12:46:01.808567 SELPH_MODE = 1
2286 12:46:01.812099 PICG_EARLY_EN = 1
2287 12:46:01.812673 VALID_LAT_VALUE = 1
2288 12:46:01.818397 ==============================================================
2289 12:46:01.821566 Enter into Gating configuration >>>>
2290 12:46:01.824954 Exit from Gating configuration <<<<
2291 12:46:01.827904 Enter into DVFS_PRE_config >>>>>
2292 12:46:01.838794 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2293 12:46:01.841708 Exit from DVFS_PRE_config <<<<<
2294 12:46:01.845237 Enter into PICG configuration >>>>
2295 12:46:01.848683 Exit from PICG configuration <<<<
2296 12:46:01.851772 [RX_INPUT] configuration >>>>>
2297 12:46:01.855737 [RX_INPUT] configuration <<<<<
2298 12:46:01.859005 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2299 12:46:01.865132 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2300 12:46:01.871645 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2301 12:46:01.878888 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2302 12:46:01.885106 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2303 12:46:01.888912 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2304 12:46:01.895115 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2305 12:46:01.899162 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2306 12:46:01.902237 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2307 12:46:01.905807 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2308 12:46:01.908980 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2309 12:46:01.915708 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2310 12:46:01.919383 ===================================
2311 12:46:01.922287 LPDDR4 DRAM CONFIGURATION
2312 12:46:01.925240 ===================================
2313 12:46:01.925758 EX_ROW_EN[0] = 0x0
2314 12:46:01.928430 EX_ROW_EN[1] = 0x0
2315 12:46:01.928910 LP4Y_EN = 0x0
2316 12:46:01.932073 WORK_FSP = 0x0
2317 12:46:01.932546 WL = 0x4
2318 12:46:01.935184 RL = 0x4
2319 12:46:01.935699 BL = 0x2
2320 12:46:01.938842 RPST = 0x0
2321 12:46:01.939374 RD_PRE = 0x0
2322 12:46:01.941883 WR_PRE = 0x1
2323 12:46:01.942301 WR_PST = 0x0
2324 12:46:01.945220 DBI_WR = 0x0
2325 12:46:01.945751 DBI_RD = 0x0
2326 12:46:01.948638 OTF = 0x1
2327 12:46:01.951953 ===================================
2328 12:46:01.955508 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2329 12:46:01.958802 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2330 12:46:01.965778 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2331 12:46:01.968836 ===================================
2332 12:46:01.969260 LPDDR4 DRAM CONFIGURATION
2333 12:46:01.972403 ===================================
2334 12:46:01.975500 EX_ROW_EN[0] = 0x10
2335 12:46:01.975917 EX_ROW_EN[1] = 0x0
2336 12:46:01.978859 LP4Y_EN = 0x0
2337 12:46:01.982267 WORK_FSP = 0x0
2338 12:46:01.982683 WL = 0x4
2339 12:46:01.985594 RL = 0x4
2340 12:46:01.986017 BL = 0x2
2341 12:46:01.989003 RPST = 0x0
2342 12:46:01.989516 RD_PRE = 0x0
2343 12:46:01.992616 WR_PRE = 0x1
2344 12:46:01.993133 WR_PST = 0x0
2345 12:46:01.995755 DBI_WR = 0x0
2346 12:46:01.996263 DBI_RD = 0x0
2347 12:46:01.998874 OTF = 0x1
2348 12:46:02.002259 ===================================
2349 12:46:02.005919 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2350 12:46:02.009357 ==
2351 12:46:02.012886 Dram Type= 6, Freq= 0, CH_0, rank 0
2352 12:46:02.016037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2353 12:46:02.016613 ==
2354 12:46:02.019354 [Duty_Offset_Calibration]
2355 12:46:02.019868 B0:2 B1:1 CA:1
2356 12:46:02.020196
2357 12:46:02.022232 [DutyScan_Calibration_Flow] k_type=0
2358 12:46:02.031826
2359 12:46:02.032376 ==CLK 0==
2360 12:46:02.034857 Final CLK duty delay cell = 0
2361 12:46:02.038331 [0] MAX Duty = 5187%(X100), DQS PI = 24
2362 12:46:02.041699 [0] MIN Duty = 4875%(X100), DQS PI = 0
2363 12:46:02.042115 [0] AVG Duty = 5031%(X100)
2364 12:46:02.042439
2365 12:46:02.045302 CH0 CLK Duty spec in!! Max-Min= 312%
2366 12:46:02.051820 [DutyScan_Calibration_Flow] ====Done====
2367 12:46:02.052261
2368 12:46:02.054874 [DutyScan_Calibration_Flow] k_type=1
2369 12:46:02.069566
2370 12:46:02.070080 ==DQS 0 ==
2371 12:46:02.073178 Final DQS duty delay cell = -4
2372 12:46:02.076777 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2373 12:46:02.080195 [-4] MIN Duty = 4751%(X100), DQS PI = 62
2374 12:46:02.082596 [-4] AVG Duty = 4937%(X100)
2375 12:46:02.083013
2376 12:46:02.083333 ==DQS 1 ==
2377 12:46:02.086635 Final DQS duty delay cell = -4
2378 12:46:02.089383 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2379 12:46:02.092966 [-4] MIN Duty = 4844%(X100), DQS PI = 32
2380 12:46:02.096318 [-4] AVG Duty = 4906%(X100)
2381 12:46:02.096831
2382 12:46:02.100008 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2383 12:46:02.100455
2384 12:46:02.103436 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2385 12:46:02.106905 [DutyScan_Calibration_Flow] ====Done====
2386 12:46:02.107413
2387 12:46:02.109745 [DutyScan_Calibration_Flow] k_type=3
2388 12:46:02.126913
2389 12:46:02.127463 ==DQM 0 ==
2390 12:46:02.129886 Final DQM duty delay cell = 0
2391 12:46:02.133617 [0] MAX Duty = 5156%(X100), DQS PI = 30
2392 12:46:02.137032 [0] MIN Duty = 4875%(X100), DQS PI = 58
2393 12:46:02.137559 [0] AVG Duty = 5015%(X100)
2394 12:46:02.140701
2395 12:46:02.141246 ==DQM 1 ==
2396 12:46:02.143748 Final DQM duty delay cell = 0
2397 12:46:02.147124 [0] MAX Duty = 5093%(X100), DQS PI = 0
2398 12:46:02.149921 [0] MIN Duty = 5000%(X100), DQS PI = 18
2399 12:46:02.150361 [0] AVG Duty = 5046%(X100)
2400 12:46:02.153495
2401 12:46:02.156848 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2402 12:46:02.157268
2403 12:46:02.160388 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2404 12:46:02.163514 [DutyScan_Calibration_Flow] ====Done====
2405 12:46:02.163928
2406 12:46:02.166734 [DutyScan_Calibration_Flow] k_type=2
2407 12:46:02.183084
2408 12:46:02.183584 ==DQ 0 ==
2409 12:46:02.186278 Final DQ duty delay cell = 0
2410 12:46:02.189489 [0] MAX Duty = 5031%(X100), DQS PI = 24
2411 12:46:02.193234 [0] MIN Duty = 4906%(X100), DQS PI = 0
2412 12:46:02.193752 [0] AVG Duty = 4968%(X100)
2413 12:46:02.194078
2414 12:46:02.196335 ==DQ 1 ==
2415 12:46:02.199619 Final DQ duty delay cell = 0
2416 12:46:02.203325 [0] MAX Duty = 5093%(X100), DQS PI = 46
2417 12:46:02.206549 [0] MIN Duty = 4907%(X100), DQS PI = 36
2418 12:46:02.207060 [0] AVG Duty = 5000%(X100)
2419 12:46:02.207387
2420 12:46:02.209856 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2421 12:46:02.210270
2422 12:46:02.213255 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2423 12:46:02.219865 [DutyScan_Calibration_Flow] ====Done====
2424 12:46:02.220398 ==
2425 12:46:02.223124 Dram Type= 6, Freq= 0, CH_1, rank 0
2426 12:46:02.226243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2427 12:46:02.226664 ==
2428 12:46:02.229652 [Duty_Offset_Calibration]
2429 12:46:02.230070 B0:1 B1:0 CA:0
2430 12:46:02.230401
2431 12:46:02.233040 [DutyScan_Calibration_Flow] k_type=0
2432 12:46:02.242773
2433 12:46:02.243305 ==CLK 0==
2434 12:46:02.246170 Final CLK duty delay cell = -4
2435 12:46:02.249219 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2436 12:46:02.252425 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2437 12:46:02.256120 [-4] AVG Duty = 4953%(X100)
2438 12:46:02.256694
2439 12:46:02.259393 CH1 CLK Duty spec in!! Max-Min= 93%
2440 12:46:02.262661 [DutyScan_Calibration_Flow] ====Done====
2441 12:46:02.263231
2442 12:46:02.265941 [DutyScan_Calibration_Flow] k_type=1
2443 12:46:02.282015
2444 12:46:02.282580 ==DQS 0 ==
2445 12:46:02.285482 Final DQS duty delay cell = 0
2446 12:46:02.288531 [0] MAX Duty = 5094%(X100), DQS PI = 26
2447 12:46:02.291993 [0] MIN Duty = 4875%(X100), DQS PI = 0
2448 12:46:02.292497 [0] AVG Duty = 4984%(X100)
2449 12:46:02.295657
2450 12:46:02.296204 ==DQS 1 ==
2451 12:46:02.298530 Final DQS duty delay cell = 0
2452 12:46:02.302206 [0] MAX Duty = 5187%(X100), DQS PI = 20
2453 12:46:02.305541 [0] MIN Duty = 4969%(X100), DQS PI = 10
2454 12:46:02.306100 [0] AVG Duty = 5078%(X100)
2455 12:46:02.308787
2456 12:46:02.311793 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2457 12:46:02.312404
2458 12:46:02.315427 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2459 12:46:02.318494 [DutyScan_Calibration_Flow] ====Done====
2460 12:46:02.319050
2461 12:46:02.321696 [DutyScan_Calibration_Flow] k_type=3
2462 12:46:02.338894
2463 12:46:02.339439 ==DQM 0 ==
2464 12:46:02.341947 Final DQM duty delay cell = 0
2465 12:46:02.345244 [0] MAX Duty = 5156%(X100), DQS PI = 6
2466 12:46:02.348330 [0] MIN Duty = 5031%(X100), DQS PI = 0
2467 12:46:02.348794 [0] AVG Duty = 5093%(X100)
2468 12:46:02.351378
2469 12:46:02.351836 ==DQM 1 ==
2470 12:46:02.354918 Final DQM duty delay cell = 0
2471 12:46:02.358508 [0] MAX Duty = 5031%(X100), DQS PI = 16
2472 12:46:02.361609 [0] MIN Duty = 4907%(X100), DQS PI = 36
2473 12:46:02.362074 [0] AVG Duty = 4969%(X100)
2474 12:46:02.364987
2475 12:46:02.368495 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2476 12:46:02.369006
2477 12:46:02.371540 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2478 12:46:02.375687 [DutyScan_Calibration_Flow] ====Done====
2479 12:46:02.376200
2480 12:46:02.378814 [DutyScan_Calibration_Flow] k_type=2
2481 12:46:02.394483
2482 12:46:02.395040 ==DQ 0 ==
2483 12:46:02.398017 Final DQ duty delay cell = -4
2484 12:46:02.401048 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2485 12:46:02.404451 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2486 12:46:02.407868 [-4] AVG Duty = 4984%(X100)
2487 12:46:02.408461
2488 12:46:02.408827 ==DQ 1 ==
2489 12:46:02.410835 Final DQ duty delay cell = 0
2490 12:46:02.414368 [0] MAX Duty = 5125%(X100), DQS PI = 20
2491 12:46:02.417436 [0] MIN Duty = 4969%(X100), DQS PI = 10
2492 12:46:02.417903 [0] AVG Duty = 5047%(X100)
2493 12:46:02.421315
2494 12:46:02.424537 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2495 12:46:02.425098
2496 12:46:02.427920 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2497 12:46:02.431070 [DutyScan_Calibration_Flow] ====Done====
2498 12:46:02.434319 nWR fixed to 30
2499 12:46:02.434784 [ModeRegInit_LP4] CH0 RK0
2500 12:46:02.437461 [ModeRegInit_LP4] CH0 RK1
2501 12:46:02.441183 [ModeRegInit_LP4] CH1 RK0
2502 12:46:02.441738 [ModeRegInit_LP4] CH1 RK1
2503 12:46:02.444352 match AC timing 7
2504 12:46:02.447720 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2505 12:46:02.450964 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2506 12:46:02.458029 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2507 12:46:02.461332 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2508 12:46:02.467638 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2509 12:46:02.468194 ==
2510 12:46:02.471194 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 12:46:02.474547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 12:46:02.475063 ==
2513 12:46:02.480796 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2514 12:46:02.487170 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2515 12:46:02.494579 [CA 0] Center 39 (8~70) winsize 63
2516 12:46:02.498447 [CA 1] Center 39 (8~70) winsize 63
2517 12:46:02.501906 [CA 2] Center 35 (5~66) winsize 62
2518 12:46:02.504367 [CA 3] Center 34 (4~65) winsize 62
2519 12:46:02.508657 [CA 4] Center 33 (3~64) winsize 62
2520 12:46:02.511820 [CA 5] Center 32 (3~62) winsize 60
2521 12:46:02.512388
2522 12:46:02.515003 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2523 12:46:02.515421
2524 12:46:02.518400 [CATrainingPosCal] consider 1 rank data
2525 12:46:02.521565 u2DelayCellTimex100 = 270/100 ps
2526 12:46:02.524935 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2527 12:46:02.528064 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2528 12:46:02.535240 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2529 12:46:02.537954 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2530 12:46:02.541328 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2531 12:46:02.544477 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2532 12:46:02.544893
2533 12:46:02.548479 CA PerBit enable=1, Macro0, CA PI delay=32
2534 12:46:02.548889
2535 12:46:02.551093 [CBTSetCACLKResult] CA Dly = 32
2536 12:46:02.551505 CS Dly: 6 (0~37)
2537 12:46:02.551830 ==
2538 12:46:02.554712 Dram Type= 6, Freq= 0, CH_0, rank 1
2539 12:46:02.561780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2540 12:46:02.562295 ==
2541 12:46:02.564851 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2542 12:46:02.571051 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2543 12:46:02.579916 [CA 0] Center 38 (8~69) winsize 62
2544 12:46:02.583584 [CA 1] Center 38 (8~69) winsize 62
2545 12:46:02.587202 [CA 2] Center 35 (4~66) winsize 63
2546 12:46:02.590181 [CA 3] Center 34 (4~65) winsize 62
2547 12:46:02.593341 [CA 4] Center 33 (3~64) winsize 62
2548 12:46:02.596988 [CA 5] Center 32 (3~62) winsize 60
2549 12:46:02.597475
2550 12:46:02.600118 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2551 12:46:02.600852
2552 12:46:02.603894 [CATrainingPosCal] consider 2 rank data
2553 12:46:02.606903 u2DelayCellTimex100 = 270/100 ps
2554 12:46:02.610005 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2555 12:46:02.613743 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2556 12:46:02.620332 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2557 12:46:02.623596 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2558 12:46:02.626852 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2559 12:46:02.630097 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2560 12:46:02.630518
2561 12:46:02.633477 CA PerBit enable=1, Macro0, CA PI delay=32
2562 12:46:02.633898
2563 12:46:02.636611 [CBTSetCACLKResult] CA Dly = 32
2564 12:46:02.637030 CS Dly: 6 (0~38)
2565 12:46:02.640184
2566 12:46:02.643123 ----->DramcWriteLeveling(PI) begin...
2567 12:46:02.643584 ==
2568 12:46:02.646790 Dram Type= 6, Freq= 0, CH_0, rank 0
2569 12:46:02.649857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2570 12:46:02.650290 ==
2571 12:46:02.653348 Write leveling (Byte 0): 33 => 33
2572 12:46:02.656643 Write leveling (Byte 1): 29 => 29
2573 12:46:02.659925 DramcWriteLeveling(PI) end<-----
2574 12:46:02.660411
2575 12:46:02.660748 ==
2576 12:46:02.663189 Dram Type= 6, Freq= 0, CH_0, rank 0
2577 12:46:02.666375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2578 12:46:02.666795 ==
2579 12:46:02.670058 [Gating] SW mode calibration
2580 12:46:02.676456 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2581 12:46:02.682896 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2582 12:46:02.686615 0 15 0 | B1->B0 | 2323 3332 | 0 1 | (0 0) (1 1)
2583 12:46:02.689855 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2584 12:46:02.696794 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2585 12:46:02.699743 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2586 12:46:02.703535 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 12:46:02.706811 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 12:46:02.712945 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 12:46:02.716835 0 15 28 | B1->B0 | 3333 2424 | 1 0 | (0 0) (0 0)
2590 12:46:02.720011 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2591 12:46:02.726638 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 12:46:02.730000 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2593 12:46:02.733535 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 12:46:02.739959 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 12:46:02.743855 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 12:46:02.746500 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2597 12:46:02.753631 1 0 28 | B1->B0 | 2d2d 4646 | 0 0 | (1 1) (0 0)
2598 12:46:02.756675 1 1 0 | B1->B0 | 3636 4545 | 0 0 | (0 0) (0 0)
2599 12:46:02.759831 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 12:46:02.766928 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 12:46:02.770493 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 12:46:02.773477 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 12:46:02.776843 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 12:46:02.783443 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2605 12:46:02.786861 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2606 12:46:02.790750 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2607 12:46:02.797030 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 12:46:02.800570 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 12:46:02.803932 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 12:46:02.810251 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 12:46:02.814137 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 12:46:02.817050 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 12:46:02.823591 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 12:46:02.827157 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 12:46:02.830031 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 12:46:02.837213 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 12:46:02.840664 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 12:46:02.844068 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 12:46:02.850336 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 12:46:02.853589 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2621 12:46:02.856823 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2622 12:46:02.860187 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2623 12:46:02.864219 Total UI for P1: 0, mck2ui 16
2624 12:46:02.867534 best dqsien dly found for B0: ( 1, 3, 26)
2625 12:46:02.873751 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2626 12:46:02.874255 Total UI for P1: 0, mck2ui 16
2627 12:46:02.880167 best dqsien dly found for B1: ( 1, 4, 0)
2628 12:46:02.883765 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2629 12:46:02.887131 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2630 12:46:02.887704
2631 12:46:02.891078 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2632 12:46:02.894562 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2633 12:46:02.897812 [Gating] SW calibration Done
2634 12:46:02.898325 ==
2635 12:46:02.900944 Dram Type= 6, Freq= 0, CH_0, rank 0
2636 12:46:02.904178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2637 12:46:02.904785 ==
2638 12:46:02.907928 RX Vref Scan: 0
2639 12:46:02.908494
2640 12:46:02.908828 RX Vref 0 -> 0, step: 1
2641 12:46:02.909128
2642 12:46:02.910954 RX Delay -40 -> 252, step: 8
2643 12:46:02.914303 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
2644 12:46:02.920917 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2645 12:46:02.924165 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2646 12:46:02.927226 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2647 12:46:02.930778 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2648 12:46:02.933826 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2649 12:46:02.937149 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2650 12:46:02.943971 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2651 12:46:02.947300 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2652 12:46:02.950384 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2653 12:46:02.953622 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2654 12:46:02.957549 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2655 12:46:02.964017 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2656 12:46:02.967428 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2657 12:46:02.970905 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2658 12:46:02.973817 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2659 12:46:02.974262 ==
2660 12:46:02.977679 Dram Type= 6, Freq= 0, CH_0, rank 0
2661 12:46:02.984230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2662 12:46:02.984812 ==
2663 12:46:02.985139 DQS Delay:
2664 12:46:02.987324 DQS0 = 0, DQS1 = 0
2665 12:46:02.987835 DQM Delay:
2666 12:46:02.988332 DQM0 = 121, DQM1 = 113
2667 12:46:02.990935 DQ Delay:
2668 12:46:02.994374 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2669 12:46:02.997204 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2670 12:46:03.000911 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2671 12:46:03.004373 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2672 12:46:03.005009
2673 12:46:03.005340
2674 12:46:03.005637 ==
2675 12:46:03.007404 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 12:46:03.010984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 12:46:03.014443 ==
2678 12:46:03.014861
2679 12:46:03.015179
2680 12:46:03.015476 TX Vref Scan disable
2681 12:46:03.017251 == TX Byte 0 ==
2682 12:46:03.020545 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2683 12:46:03.023902 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2684 12:46:03.027278 == TX Byte 1 ==
2685 12:46:03.031067 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2686 12:46:03.034185 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2687 12:46:03.034597 ==
2688 12:46:03.037751 Dram Type= 6, Freq= 0, CH_0, rank 0
2689 12:46:03.044539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2690 12:46:03.045051 ==
2691 12:46:03.054881 TX Vref=22, minBit 0, minWin=25, winSum=408
2692 12:46:03.058148 TX Vref=24, minBit 0, minWin=25, winSum=415
2693 12:46:03.061460 TX Vref=26, minBit 0, minWin=26, winSum=420
2694 12:46:03.065292 TX Vref=28, minBit 0, minWin=26, winSum=424
2695 12:46:03.068757 TX Vref=30, minBit 3, minWin=26, winSum=424
2696 12:46:03.072216 TX Vref=32, minBit 0, minWin=26, winSum=425
2697 12:46:03.078857 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 32
2698 12:46:03.079375
2699 12:46:03.082233 Final TX Range 1 Vref 32
2700 12:46:03.082780
2701 12:46:03.083154 ==
2702 12:46:03.085416 Dram Type= 6, Freq= 0, CH_0, rank 0
2703 12:46:03.088723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2704 12:46:03.089236 ==
2705 12:46:03.089561
2706 12:46:03.089857
2707 12:46:03.092079 TX Vref Scan disable
2708 12:46:03.094974 == TX Byte 0 ==
2709 12:46:03.098872 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2710 12:46:03.102237 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2711 12:46:03.105097 == TX Byte 1 ==
2712 12:46:03.108809 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2713 12:46:03.112047 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2714 12:46:03.112505
2715 12:46:03.115404 [DATLAT]
2716 12:46:03.115809 Freq=1200, CH0 RK0
2717 12:46:03.116126
2718 12:46:03.118701 DATLAT Default: 0xd
2719 12:46:03.119221 0, 0xFFFF, sum = 0
2720 12:46:03.122205 1, 0xFFFF, sum = 0
2721 12:46:03.122726 2, 0xFFFF, sum = 0
2722 12:46:03.125176 3, 0xFFFF, sum = 0
2723 12:46:03.125593 4, 0xFFFF, sum = 0
2724 12:46:03.128800 5, 0xFFFF, sum = 0
2725 12:46:03.129351 6, 0xFFFF, sum = 0
2726 12:46:03.132022 7, 0xFFFF, sum = 0
2727 12:46:03.132542 8, 0xFFFF, sum = 0
2728 12:46:03.135271 9, 0xFFFF, sum = 0
2729 12:46:03.135683 10, 0xFFFF, sum = 0
2730 12:46:03.138670 11, 0xFFFF, sum = 0
2731 12:46:03.139231 12, 0x0, sum = 1
2732 12:46:03.141852 13, 0x0, sum = 2
2733 12:46:03.142484 14, 0x0, sum = 3
2734 12:46:03.145005 15, 0x0, sum = 4
2735 12:46:03.145438 best_step = 13
2736 12:46:03.145862
2737 12:46:03.146266 ==
2738 12:46:03.148488 Dram Type= 6, Freq= 0, CH_0, rank 0
2739 12:46:03.155310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2740 12:46:03.155874 ==
2741 12:46:03.156208 RX Vref Scan: 1
2742 12:46:03.156573
2743 12:46:03.158653 Set Vref Range= 32 -> 127
2744 12:46:03.159229
2745 12:46:03.161895 RX Vref 32 -> 127, step: 1
2746 12:46:03.162364
2747 12:46:03.165106 RX Delay -13 -> 252, step: 4
2748 12:46:03.165533
2749 12:46:03.165885 Set Vref, RX VrefLevel [Byte0]: 32
2750 12:46:03.168591 [Byte1]: 32
2751 12:46:03.173043
2752 12:46:03.173571 Set Vref, RX VrefLevel [Byte0]: 33
2753 12:46:03.176262 [Byte1]: 33
2754 12:46:03.180880
2755 12:46:03.181286 Set Vref, RX VrefLevel [Byte0]: 34
2756 12:46:03.184138 [Byte1]: 34
2757 12:46:03.189179
2758 12:46:03.189693 Set Vref, RX VrefLevel [Byte0]: 35
2759 12:46:03.192447 [Byte1]: 35
2760 12:46:03.197064
2761 12:46:03.197471 Set Vref, RX VrefLevel [Byte0]: 36
2762 12:46:03.200552 [Byte1]: 36
2763 12:46:03.205050
2764 12:46:03.205559 Set Vref, RX VrefLevel [Byte0]: 37
2765 12:46:03.208129 [Byte1]: 37
2766 12:46:03.212393
2767 12:46:03.212805 Set Vref, RX VrefLevel [Byte0]: 38
2768 12:46:03.215909 [Byte1]: 38
2769 12:46:03.220730
2770 12:46:03.221240 Set Vref, RX VrefLevel [Byte0]: 39
2771 12:46:03.227078 [Byte1]: 39
2772 12:46:03.227579
2773 12:46:03.230318 Set Vref, RX VrefLevel [Byte0]: 40
2774 12:46:03.233359 [Byte1]: 40
2775 12:46:03.233962
2776 12:46:03.237136 Set Vref, RX VrefLevel [Byte0]: 41
2777 12:46:03.240562 [Byte1]: 41
2778 12:46:03.244267
2779 12:46:03.244718 Set Vref, RX VrefLevel [Byte0]: 42
2780 12:46:03.247435 [Byte1]: 42
2781 12:46:03.251813
2782 12:46:03.252221 Set Vref, RX VrefLevel [Byte0]: 43
2783 12:46:03.255253 [Byte1]: 43
2784 12:46:03.260329
2785 12:46:03.260839 Set Vref, RX VrefLevel [Byte0]: 44
2786 12:46:03.263022 [Byte1]: 44
2787 12:46:03.267610
2788 12:46:03.268016 Set Vref, RX VrefLevel [Byte0]: 45
2789 12:46:03.271188 [Byte1]: 45
2790 12:46:03.275764
2791 12:46:03.276169 Set Vref, RX VrefLevel [Byte0]: 46
2792 12:46:03.278924 [Byte1]: 46
2793 12:46:03.283519
2794 12:46:03.283927 Set Vref, RX VrefLevel [Byte0]: 47
2795 12:46:03.286982 [Byte1]: 47
2796 12:46:03.291821
2797 12:46:03.292231 Set Vref, RX VrefLevel [Byte0]: 48
2798 12:46:03.294536 [Byte1]: 48
2799 12:46:03.299883
2800 12:46:03.300445 Set Vref, RX VrefLevel [Byte0]: 49
2801 12:46:03.302601 [Byte1]: 49
2802 12:46:03.307343
2803 12:46:03.307847 Set Vref, RX VrefLevel [Byte0]: 50
2804 12:46:03.310646 [Byte1]: 50
2805 12:46:03.315316
2806 12:46:03.315841 Set Vref, RX VrefLevel [Byte0]: 51
2807 12:46:03.318209 [Byte1]: 51
2808 12:46:03.322889
2809 12:46:03.323294 Set Vref, RX VrefLevel [Byte0]: 52
2810 12:46:03.326856 [Byte1]: 52
2811 12:46:03.330968
2812 12:46:03.331502 Set Vref, RX VrefLevel [Byte0]: 53
2813 12:46:03.333998 [Byte1]: 53
2814 12:46:03.338735
2815 12:46:03.339143 Set Vref, RX VrefLevel [Byte0]: 54
2816 12:46:03.342237 [Byte1]: 54
2817 12:46:03.346852
2818 12:46:03.347363 Set Vref, RX VrefLevel [Byte0]: 55
2819 12:46:03.349800 [Byte1]: 55
2820 12:46:03.354357
2821 12:46:03.354778 Set Vref, RX VrefLevel [Byte0]: 56
2822 12:46:03.357405 [Byte1]: 56
2823 12:46:03.362436
2824 12:46:03.363000 Set Vref, RX VrefLevel [Byte0]: 57
2825 12:46:03.365601 [Byte1]: 57
2826 12:46:03.370316
2827 12:46:03.370921 Set Vref, RX VrefLevel [Byte0]: 58
2828 12:46:03.373460 [Byte1]: 58
2829 12:46:03.377911
2830 12:46:03.378381 Set Vref, RX VrefLevel [Byte0]: 59
2831 12:46:03.381420 [Byte1]: 59
2832 12:46:03.385989
2833 12:46:03.386533 Set Vref, RX VrefLevel [Byte0]: 60
2834 12:46:03.389597 [Byte1]: 60
2835 12:46:03.394251
2836 12:46:03.394758 Set Vref, RX VrefLevel [Byte0]: 61
2837 12:46:03.397750 [Byte1]: 61
2838 12:46:03.402171
2839 12:46:03.402584 Set Vref, RX VrefLevel [Byte0]: 62
2840 12:46:03.405432 [Byte1]: 62
2841 12:46:03.409797
2842 12:46:03.410464 Set Vref, RX VrefLevel [Byte0]: 63
2843 12:46:03.413014 [Byte1]: 63
2844 12:46:03.417750
2845 12:46:03.418191 Set Vref, RX VrefLevel [Byte0]: 64
2846 12:46:03.420982 [Byte1]: 64
2847 12:46:03.425505
2848 12:46:03.425954 Set Vref, RX VrefLevel [Byte0]: 65
2849 12:46:03.429236 [Byte1]: 65
2850 12:46:03.433929
2851 12:46:03.434496 Set Vref, RX VrefLevel [Byte0]: 66
2852 12:46:03.436931 [Byte1]: 66
2853 12:46:03.441243
2854 12:46:03.441675 Set Vref, RX VrefLevel [Byte0]: 67
2855 12:46:03.444496 [Byte1]: 67
2856 12:46:03.449172
2857 12:46:03.449631 Set Vref, RX VrefLevel [Byte0]: 68
2858 12:46:03.452590 [Byte1]: 68
2859 12:46:03.457200
2860 12:46:03.457730 Set Vref, RX VrefLevel [Byte0]: 69
2861 12:46:03.460557 [Byte1]: 69
2862 12:46:03.464596
2863 12:46:03.465040 Set Vref, RX VrefLevel [Byte0]: 70
2864 12:46:03.468552 [Byte1]: 70
2865 12:46:03.473098
2866 12:46:03.473641 Final RX Vref Byte 0 = 58 to rank0
2867 12:46:03.476440 Final RX Vref Byte 1 = 53 to rank0
2868 12:46:03.479794 Final RX Vref Byte 0 = 58 to rank1
2869 12:46:03.483004 Final RX Vref Byte 1 = 53 to rank1==
2870 12:46:03.486275 Dram Type= 6, Freq= 0, CH_0, rank 0
2871 12:46:03.489599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2872 12:46:03.493444 ==
2873 12:46:03.493855 DQS Delay:
2874 12:46:03.494176 DQS0 = 0, DQS1 = 0
2875 12:46:03.496490 DQM Delay:
2876 12:46:03.496946 DQM0 = 120, DQM1 = 113
2877 12:46:03.499906 DQ Delay:
2878 12:46:03.503599 DQ0 =120, DQ1 =122, DQ2 =120, DQ3 =118
2879 12:46:03.506410 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2880 12:46:03.509905 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2881 12:46:03.512844 DQ12 =120, DQ13 =116, DQ14 =126, DQ15 =122
2882 12:46:03.513261
2883 12:46:03.513582
2884 12:46:03.520105 [DQSOSCAuto] RK0, (LSB)MR18= 0x140d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2885 12:46:03.523440 CH0 RK0: MR19=404, MR18=140D
2886 12:46:03.529644 CH0_RK0: MR19=0x404, MR18=0x140D, DQSOSC=402, MR23=63, INC=40, DEC=27
2887 12:46:03.530165
2888 12:46:03.533518 ----->DramcWriteLeveling(PI) begin...
2889 12:46:03.533942 ==
2890 12:46:03.536364 Dram Type= 6, Freq= 0, CH_0, rank 1
2891 12:46:03.539535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2892 12:46:03.543492 ==
2893 12:46:03.544045 Write leveling (Byte 0): 34 => 34
2894 12:46:03.546488 Write leveling (Byte 1): 30 => 30
2895 12:46:03.550012 DramcWriteLeveling(PI) end<-----
2896 12:46:03.550526
2897 12:46:03.550898 ==
2898 12:46:03.553005 Dram Type= 6, Freq= 0, CH_0, rank 1
2899 12:46:03.559756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2900 12:46:03.560345 ==
2901 12:46:03.560952 [Gating] SW mode calibration
2902 12:46:03.569525 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2903 12:46:03.573197 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2904 12:46:03.576437 0 15 0 | B1->B0 | 3131 2d2d | 0 1 | (0 0) (0 0)
2905 12:46:03.583487 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 12:46:03.586818 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 12:46:03.589891 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 12:46:03.596840 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 12:46:03.600248 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2910 12:46:03.603481 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2911 12:46:03.609824 0 15 28 | B1->B0 | 2e2e 2c2c | 1 1 | (1 1) (1 0)
2912 12:46:03.613201 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2913 12:46:03.616550 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 12:46:03.623038 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 12:46:03.626485 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 12:46:03.630021 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 12:46:03.636558 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2918 12:46:03.639941 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2919 12:46:03.643035 1 0 28 | B1->B0 | 3e3e 3f3f | 0 0 | (1 1) (0 0)
2920 12:46:03.649707 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 12:46:03.653045 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 12:46:03.656482 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 12:46:03.663035 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 12:46:03.666332 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 12:46:03.669804 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 12:46:03.672795 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2927 12:46:03.680065 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2928 12:46:03.683433 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2929 12:46:03.686620 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 12:46:03.693157 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 12:46:03.696576 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 12:46:03.700207 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 12:46:03.706725 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 12:46:03.709974 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 12:46:03.713220 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 12:46:03.719829 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 12:46:03.723607 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 12:46:03.726772 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 12:46:03.733138 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 12:46:03.737018 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 12:46:03.740090 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 12:46:03.743400 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2943 12:46:03.749925 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2944 12:46:03.753293 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2945 12:46:03.756647 Total UI for P1: 0, mck2ui 16
2946 12:46:03.759817 best dqsien dly found for B0: ( 1, 3, 26)
2947 12:46:03.763076 Total UI for P1: 0, mck2ui 16
2948 12:46:03.766868 best dqsien dly found for B1: ( 1, 3, 26)
2949 12:46:03.770071 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2950 12:46:03.773542 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
2951 12:46:03.773958
2952 12:46:03.776476 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2953 12:46:03.780115 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
2954 12:46:03.783457 [Gating] SW calibration Done
2955 12:46:03.783876 ==
2956 12:46:03.786987 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 12:46:03.790188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 12:46:03.793558 ==
2959 12:46:03.793968 RX Vref Scan: 0
2960 12:46:03.794291
2961 12:46:03.796879 RX Vref 0 -> 0, step: 1
2962 12:46:03.797290
2963 12:46:03.800736 RX Delay -40 -> 252, step: 8
2964 12:46:03.803756 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2965 12:46:03.806967 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2966 12:46:03.810601 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2967 12:46:03.813699 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2968 12:46:03.820558 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2969 12:46:03.824012 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2970 12:46:03.827031 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2971 12:46:03.830170 iDelay=200, Bit 7, Center 131 (64 ~ 199) 136
2972 12:46:03.833408 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2973 12:46:03.836932 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2974 12:46:03.843287 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2975 12:46:03.846764 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2976 12:46:03.850281 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2977 12:46:03.853228 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2978 12:46:03.860029 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2979 12:46:03.863095 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2980 12:46:03.863550 ==
2981 12:46:03.866617 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 12:46:03.869683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 12:46:03.870058 ==
2984 12:46:03.870369 DQS Delay:
2985 12:46:03.873552 DQS0 = 0, DQS1 = 0
2986 12:46:03.874130 DQM Delay:
2987 12:46:03.876611 DQM0 = 122, DQM1 = 113
2988 12:46:03.877023 DQ Delay:
2989 12:46:03.879968 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2990 12:46:03.883788 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =131
2991 12:46:03.886641 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
2992 12:46:03.890132 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2993 12:46:03.890690
2994 12:46:03.893462
2995 12:46:03.894015 ==
2996 12:46:03.897046 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 12:46:03.900828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 12:46:03.901400 ==
2999 12:46:03.901776
3000 12:46:03.902105
3001 12:46:03.903823 TX Vref Scan disable
3002 12:46:03.904379 == TX Byte 0 ==
3003 12:46:03.910631 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3004 12:46:03.913589 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3005 12:46:03.914046 == TX Byte 1 ==
3006 12:46:03.920103 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3007 12:46:03.923790 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3008 12:46:03.924392 ==
3009 12:46:03.926994 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 12:46:03.930046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 12:46:03.930541 ==
3012 12:46:03.943165 TX Vref=22, minBit 1, minWin=25, winSum=416
3013 12:46:03.946129 TX Vref=24, minBit 3, minWin=25, winSum=419
3014 12:46:03.949502 TX Vref=26, minBit 3, minWin=25, winSum=425
3015 12:46:03.952650 TX Vref=28, minBit 1, minWin=26, winSum=430
3016 12:46:03.955908 TX Vref=30, minBit 0, minWin=26, winSum=425
3017 12:46:03.960092 TX Vref=32, minBit 5, minWin=25, winSum=426
3018 12:46:03.966328 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 28
3019 12:46:03.966865
3020 12:46:03.969582 Final TX Range 1 Vref 28
3021 12:46:03.970161
3022 12:46:03.970526 ==
3023 12:46:03.972943 Dram Type= 6, Freq= 0, CH_0, rank 1
3024 12:46:03.976607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3025 12:46:03.977191 ==
3026 12:46:03.977555
3027 12:46:03.977966
3028 12:46:03.979361 TX Vref Scan disable
3029 12:46:03.982834 == TX Byte 0 ==
3030 12:46:03.986123 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3031 12:46:03.989771 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3032 12:46:03.992720 == TX Byte 1 ==
3033 12:46:03.996368 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3034 12:46:03.999260 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3035 12:46:03.999708
3036 12:46:04.002992 [DATLAT]
3037 12:46:04.003501 Freq=1200, CH0 RK1
3038 12:46:04.003876
3039 12:46:04.006212 DATLAT Default: 0xd
3040 12:46:04.006775 0, 0xFFFF, sum = 0
3041 12:46:04.009667 1, 0xFFFF, sum = 0
3042 12:46:04.010237 2, 0xFFFF, sum = 0
3043 12:46:04.012699 3, 0xFFFF, sum = 0
3044 12:46:04.013159 4, 0xFFFF, sum = 0
3045 12:46:04.016490 5, 0xFFFF, sum = 0
3046 12:46:04.016951 6, 0xFFFF, sum = 0
3047 12:46:04.019971 7, 0xFFFF, sum = 0
3048 12:46:04.020540 8, 0xFFFF, sum = 0
3049 12:46:04.022980 9, 0xFFFF, sum = 0
3050 12:46:04.023402 10, 0xFFFF, sum = 0
3051 12:46:04.026103 11, 0xFFFF, sum = 0
3052 12:46:04.026521 12, 0x0, sum = 1
3053 12:46:04.029707 13, 0x0, sum = 2
3054 12:46:04.030123 14, 0x0, sum = 3
3055 12:46:04.032837 15, 0x0, sum = 4
3056 12:46:04.033254 best_step = 13
3057 12:46:04.033580
3058 12:46:04.033879 ==
3059 12:46:04.036485 Dram Type= 6, Freq= 0, CH_0, rank 1
3060 12:46:04.043282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3061 12:46:04.043698 ==
3062 12:46:04.044026 RX Vref Scan: 0
3063 12:46:04.044374
3064 12:46:04.046573 RX Vref 0 -> 0, step: 1
3065 12:46:04.046983
3066 12:46:04.049946 RX Delay -13 -> 252, step: 4
3067 12:46:04.053214 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3068 12:46:04.056532 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3069 12:46:04.060258 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3070 12:46:04.066977 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3071 12:46:04.070553 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3072 12:46:04.073370 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3073 12:46:04.076775 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3074 12:46:04.080572 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3075 12:46:04.086821 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3076 12:46:04.090473 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3077 12:46:04.093462 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3078 12:46:04.097175 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3079 12:46:04.100226 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3080 12:46:04.107152 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3081 12:46:04.110872 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3082 12:46:04.113317 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3083 12:46:04.113734 ==
3084 12:46:04.116517 Dram Type= 6, Freq= 0, CH_0, rank 1
3085 12:46:04.120069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3086 12:46:04.120642 ==
3087 12:46:04.123807 DQS Delay:
3088 12:46:04.124370 DQS0 = 0, DQS1 = 0
3089 12:46:04.127084 DQM Delay:
3090 12:46:04.127593 DQM0 = 120, DQM1 = 111
3091 12:46:04.127923 DQ Delay:
3092 12:46:04.133305 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3093 12:46:04.136513 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3094 12:46:04.139922 DQ8 =100, DQ9 =98, DQ10 =112, DQ11 =104
3095 12:46:04.143246 DQ12 =116, DQ13 =118, DQ14 =122, DQ15 =120
3096 12:46:04.143734
3097 12:46:04.144061
3098 12:46:04.150385 [DQSOSCAuto] RK1, (LSB)MR18= 0xced, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3099 12:46:04.153554 CH0 RK1: MR19=403, MR18=CED
3100 12:46:04.160135 CH0_RK1: MR19=0x403, MR18=0xCED, DQSOSC=405, MR23=63, INC=39, DEC=26
3101 12:46:04.163427 [RxdqsGatingPostProcess] freq 1200
3102 12:46:04.167426 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3103 12:46:04.170596 best DQS0 dly(2T, 0.5T) = (0, 11)
3104 12:46:04.173321 best DQS1 dly(2T, 0.5T) = (0, 12)
3105 12:46:04.176685 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3106 12:46:04.180051 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3107 12:46:04.183396 best DQS0 dly(2T, 0.5T) = (0, 11)
3108 12:46:04.186884 best DQS1 dly(2T, 0.5T) = (0, 11)
3109 12:46:04.190343 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3110 12:46:04.193424 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3111 12:46:04.197317 Pre-setting of DQS Precalculation
3112 12:46:04.200281 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3113 12:46:04.200723 ==
3114 12:46:04.203956 Dram Type= 6, Freq= 0, CH_1, rank 0
3115 12:46:04.210526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3116 12:46:04.210941 ==
3117 12:46:04.213921 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3118 12:46:04.220006 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3119 12:46:04.228574 [CA 0] Center 37 (7~68) winsize 62
3120 12:46:04.232115 [CA 1] Center 37 (7~68) winsize 62
3121 12:46:04.235667 [CA 2] Center 35 (5~65) winsize 61
3122 12:46:04.238891 [CA 3] Center 34 (4~64) winsize 61
3123 12:46:04.242225 [CA 4] Center 34 (5~64) winsize 60
3124 12:46:04.245525 [CA 5] Center 33 (3~63) winsize 61
3125 12:46:04.246098
3126 12:46:04.248928 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3127 12:46:04.249591
3128 12:46:04.252067 [CATrainingPosCal] consider 1 rank data
3129 12:46:04.255533 u2DelayCellTimex100 = 270/100 ps
3130 12:46:04.258659 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3131 12:46:04.262197 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3132 12:46:04.268782 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3133 12:46:04.272179 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3134 12:46:04.275356 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3135 12:46:04.278671 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3136 12:46:04.279083
3137 12:46:04.282399 CA PerBit enable=1, Macro0, CA PI delay=33
3138 12:46:04.282811
3139 12:46:04.285608 [CBTSetCACLKResult] CA Dly = 33
3140 12:46:04.286025 CS Dly: 7 (0~38)
3141 12:46:04.286346 ==
3142 12:46:04.288822 Dram Type= 6, Freq= 0, CH_1, rank 1
3143 12:46:04.295832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3144 12:46:04.296368 ==
3145 12:46:04.298699 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3146 12:46:04.305707 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3147 12:46:04.314475 [CA 0] Center 37 (7~68) winsize 62
3148 12:46:04.318087 [CA 1] Center 37 (7~68) winsize 62
3149 12:46:04.321223 [CA 2] Center 35 (5~65) winsize 61
3150 12:46:04.324236 [CA 3] Center 35 (5~65) winsize 61
3151 12:46:04.327716 [CA 4] Center 34 (4~65) winsize 62
3152 12:46:04.331247 [CA 5] Center 34 (4~64) winsize 61
3153 12:46:04.331661
3154 12:46:04.334223 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3155 12:46:04.334636
3156 12:46:04.337545 [CATrainingPosCal] consider 2 rank data
3157 12:46:04.340847 u2DelayCellTimex100 = 270/100 ps
3158 12:46:04.344811 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3159 12:46:04.347626 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3160 12:46:04.354209 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3161 12:46:04.357918 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3162 12:46:04.361145 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3163 12:46:04.364632 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3164 12:46:04.365095
3165 12:46:04.367899 CA PerBit enable=1, Macro0, CA PI delay=33
3166 12:46:04.368346
3167 12:46:04.370572 [CBTSetCACLKResult] CA Dly = 33
3168 12:46:04.370985 CS Dly: 8 (0~41)
3169 12:46:04.371309
3170 12:46:04.373997 ----->DramcWriteLeveling(PI) begin...
3171 12:46:04.377901 ==
3172 12:46:04.381149 Dram Type= 6, Freq= 0, CH_1, rank 0
3173 12:46:04.384243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3174 12:46:04.384799 ==
3175 12:46:04.387363 Write leveling (Byte 0): 25 => 25
3176 12:46:04.391037 Write leveling (Byte 1): 28 => 28
3177 12:46:04.394105 DramcWriteLeveling(PI) end<-----
3178 12:46:04.394537
3179 12:46:04.394914 ==
3180 12:46:04.397345 Dram Type= 6, Freq= 0, CH_1, rank 0
3181 12:46:04.400747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3182 12:46:04.401168 ==
3183 12:46:04.404409 [Gating] SW mode calibration
3184 12:46:04.410830 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3185 12:46:04.414222 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3186 12:46:04.421154 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
3187 12:46:04.423997 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 12:46:04.427544 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 12:46:04.433986 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 12:46:04.438008 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 12:46:04.441138 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 12:46:04.447967 0 15 24 | B1->B0 | 3333 2e2e | 0 0 | (0 1) (0 1)
3193 12:46:04.451251 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
3194 12:46:04.454378 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 12:46:04.460953 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 12:46:04.464384 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 12:46:04.467524 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 12:46:04.474481 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 12:46:04.477625 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 12:46:04.480866 1 0 24 | B1->B0 | 2f2f 3c3c | 0 0 | (1 1) (0 0)
3201 12:46:04.484872 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 12:46:04.491405 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 12:46:04.494458 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 12:46:04.498082 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 12:46:04.504556 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 12:46:04.507825 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 12:46:04.511245 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 12:46:04.518296 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3209 12:46:04.521278 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3210 12:46:04.524915 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 12:46:04.531244 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 12:46:04.535006 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 12:46:04.538289 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 12:46:04.544728 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 12:46:04.547755 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 12:46:04.551166 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 12:46:04.558144 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 12:46:04.561334 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 12:46:04.564526 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 12:46:04.571304 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 12:46:04.574651 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 12:46:04.578057 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 12:46:04.581297 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 12:46:04.587719 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3225 12:46:04.591244 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3226 12:46:04.594551 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 12:46:04.597723 Total UI for P1: 0, mck2ui 16
3228 12:46:04.601568 best dqsien dly found for B0: ( 1, 3, 26)
3229 12:46:04.604983 Total UI for P1: 0, mck2ui 16
3230 12:46:04.607534 best dqsien dly found for B1: ( 1, 3, 26)
3231 12:46:04.611238 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3232 12:46:04.614857 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3233 12:46:04.615276
3234 12:46:04.621657 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3235 12:46:04.624523 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3236 12:46:04.627757 [Gating] SW calibration Done
3237 12:46:04.628274 ==
3238 12:46:04.630946 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 12:46:04.634835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 12:46:04.635257 ==
3241 12:46:04.635582 RX Vref Scan: 0
3242 12:46:04.635891
3243 12:46:04.637971 RX Vref 0 -> 0, step: 1
3244 12:46:04.638382
3245 12:46:04.641780 RX Delay -40 -> 252, step: 8
3246 12:46:04.644639 iDelay=200, Bit 0, Center 127 (56 ~ 199) 144
3247 12:46:04.648452 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3248 12:46:04.651194 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3249 12:46:04.658214 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3250 12:46:04.661230 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3251 12:46:04.664843 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3252 12:46:04.668113 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3253 12:46:04.671383 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3254 12:46:04.677763 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3255 12:46:04.681634 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3256 12:46:04.684871 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3257 12:46:04.688232 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3258 12:46:04.691594 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3259 12:46:04.697853 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3260 12:46:04.701276 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3261 12:46:04.704983 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3262 12:46:04.705428 ==
3263 12:46:04.708224 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 12:46:04.711757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 12:46:04.712178 ==
3266 12:46:04.714614 DQS Delay:
3267 12:46:04.715199 DQS0 = 0, DQS1 = 0
3268 12:46:04.718149 DQM Delay:
3269 12:46:04.718658 DQM0 = 121, DQM1 = 116
3270 12:46:04.718990 DQ Delay:
3271 12:46:04.721953 DQ0 =127, DQ1 =115, DQ2 =107, DQ3 =119
3272 12:46:04.728537 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =123
3273 12:46:04.731852 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3274 12:46:04.735182 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3275 12:46:04.735590
3276 12:46:04.735903
3277 12:46:04.736211 ==
3278 12:46:04.738532 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 12:46:04.741276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 12:46:04.741689 ==
3281 12:46:04.742010
3282 12:46:04.742306
3283 12:46:04.745383 TX Vref Scan disable
3284 12:46:04.747684 == TX Byte 0 ==
3285 12:46:04.751621 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3286 12:46:04.754724 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3287 12:46:04.757965 == TX Byte 1 ==
3288 12:46:04.761229 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3289 12:46:04.764915 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3290 12:46:04.765355 ==
3291 12:46:04.767870 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 12:46:04.771273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 12:46:04.771808 ==
3294 12:46:04.784825 TX Vref=22, minBit 1, minWin=24, winSum=408
3295 12:46:04.788134 TX Vref=24, minBit 9, minWin=25, winSum=418
3296 12:46:04.790894 TX Vref=26, minBit 9, minWin=25, winSum=424
3297 12:46:04.794839 TX Vref=28, minBit 1, minWin=26, winSum=428
3298 12:46:04.798073 TX Vref=30, minBit 10, minWin=25, winSum=427
3299 12:46:04.801336 TX Vref=32, minBit 2, minWin=26, winSum=432
3300 12:46:04.807945 [TxChooseVref] Worse bit 2, Min win 26, Win sum 432, Final Vref 32
3301 12:46:04.808095
3302 12:46:04.810994 Final TX Range 1 Vref 32
3303 12:46:04.811124
3304 12:46:04.811224 ==
3305 12:46:04.814554 Dram Type= 6, Freq= 0, CH_1, rank 0
3306 12:46:04.817547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3307 12:46:04.817660 ==
3308 12:46:04.817747
3309 12:46:04.821153
3310 12:46:04.821253 TX Vref Scan disable
3311 12:46:04.824199 == TX Byte 0 ==
3312 12:46:04.827873 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3313 12:46:04.830939 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3314 12:46:04.834774 == TX Byte 1 ==
3315 12:46:04.837520 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3316 12:46:04.841454 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3317 12:46:04.841571
3318 12:46:04.844839 [DATLAT]
3319 12:46:04.844920 Freq=1200, CH1 RK0
3320 12:46:04.844983
3321 12:46:04.847582 DATLAT Default: 0xd
3322 12:46:04.847662 0, 0xFFFF, sum = 0
3323 12:46:04.851523 1, 0xFFFF, sum = 0
3324 12:46:04.851608 2, 0xFFFF, sum = 0
3325 12:46:04.854802 3, 0xFFFF, sum = 0
3326 12:46:04.854884 4, 0xFFFF, sum = 0
3327 12:46:04.858035 5, 0xFFFF, sum = 0
3328 12:46:04.858116 6, 0xFFFF, sum = 0
3329 12:46:04.861169 7, 0xFFFF, sum = 0
3330 12:46:04.861282 8, 0xFFFF, sum = 0
3331 12:46:04.865016 9, 0xFFFF, sum = 0
3332 12:46:04.865120 10, 0xFFFF, sum = 0
3333 12:46:04.868188 11, 0xFFFF, sum = 0
3334 12:46:04.868332 12, 0x0, sum = 1
3335 12:46:04.871277 13, 0x0, sum = 2
3336 12:46:04.871377 14, 0x0, sum = 3
3337 12:46:04.874967 15, 0x0, sum = 4
3338 12:46:04.875049 best_step = 13
3339 12:46:04.875112
3340 12:46:04.875171 ==
3341 12:46:04.877776 Dram Type= 6, Freq= 0, CH_1, rank 0
3342 12:46:04.884756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3343 12:46:04.884838 ==
3344 12:46:04.884901 RX Vref Scan: 1
3345 12:46:04.884960
3346 12:46:04.888032 Set Vref Range= 32 -> 127
3347 12:46:04.888112
3348 12:46:04.891431 RX Vref 32 -> 127, step: 1
3349 12:46:04.891511
3350 12:46:04.891574 RX Delay -5 -> 252, step: 4
3351 12:46:04.891632
3352 12:46:04.895120 Set Vref, RX VrefLevel [Byte0]: 32
3353 12:46:04.898225 [Byte1]: 32
3354 12:46:04.902968
3355 12:46:04.903123 Set Vref, RX VrefLevel [Byte0]: 33
3356 12:46:04.906173 [Byte1]: 33
3357 12:46:04.910892
3358 12:46:04.911047 Set Vref, RX VrefLevel [Byte0]: 34
3359 12:46:04.913434 [Byte1]: 34
3360 12:46:04.918410
3361 12:46:04.918491 Set Vref, RX VrefLevel [Byte0]: 35
3362 12:46:04.921730 [Byte1]: 35
3363 12:46:04.926098
3364 12:46:04.926178 Set Vref, RX VrefLevel [Byte0]: 36
3365 12:46:04.929314 [Byte1]: 36
3366 12:46:04.933943
3367 12:46:04.934022 Set Vref, RX VrefLevel [Byte0]: 37
3368 12:46:04.940199 [Byte1]: 37
3369 12:46:04.940320
3370 12:46:04.943781 Set Vref, RX VrefLevel [Byte0]: 38
3371 12:46:04.947222 [Byte1]: 38
3372 12:46:04.947314
3373 12:46:04.950853 Set Vref, RX VrefLevel [Byte0]: 39
3374 12:46:04.954023 [Byte1]: 39
3375 12:46:04.958025
3376 12:46:04.958463 Set Vref, RX VrefLevel [Byte0]: 40
3377 12:46:04.961205 [Byte1]: 40
3378 12:46:04.965807
3379 12:46:04.966346 Set Vref, RX VrefLevel [Byte0]: 41
3380 12:46:04.968849 [Byte1]: 41
3381 12:46:04.974021
3382 12:46:04.974446 Set Vref, RX VrefLevel [Byte0]: 42
3383 12:46:04.977026 [Byte1]: 42
3384 12:46:04.981370
3385 12:46:04.981776 Set Vref, RX VrefLevel [Byte0]: 43
3386 12:46:04.984732 [Byte1]: 43
3387 12:46:04.989315
3388 12:46:04.989750 Set Vref, RX VrefLevel [Byte0]: 44
3389 12:46:04.992574 [Byte1]: 44
3390 12:46:04.997274
3391 12:46:04.997788 Set Vref, RX VrefLevel [Byte0]: 45
3392 12:46:05.000533 [Byte1]: 45
3393 12:46:05.005350
3394 12:46:05.005857 Set Vref, RX VrefLevel [Byte0]: 46
3395 12:46:05.008564 [Byte1]: 46
3396 12:46:05.013420
3397 12:46:05.013984 Set Vref, RX VrefLevel [Byte0]: 47
3398 12:46:05.016791 [Byte1]: 47
3399 12:46:05.020490
3400 12:46:05.020963 Set Vref, RX VrefLevel [Byte0]: 48
3401 12:46:05.024186 [Byte1]: 48
3402 12:46:05.028779
3403 12:46:05.029236 Set Vref, RX VrefLevel [Byte0]: 49
3404 12:46:05.031760 [Byte1]: 49
3405 12:46:05.036005
3406 12:46:05.036525 Set Vref, RX VrefLevel [Byte0]: 50
3407 12:46:05.040128 [Byte1]: 50
3408 12:46:05.044852
3409 12:46:05.045402 Set Vref, RX VrefLevel [Byte0]: 51
3410 12:46:05.047426 [Byte1]: 51
3411 12:46:05.052411
3412 12:46:05.052865 Set Vref, RX VrefLevel [Byte0]: 52
3413 12:46:05.055502 [Byte1]: 52
3414 12:46:05.059868
3415 12:46:05.060364 Set Vref, RX VrefLevel [Byte0]: 53
3416 12:46:05.063532 [Byte1]: 53
3417 12:46:05.068005
3418 12:46:05.068541 Set Vref, RX VrefLevel [Byte0]: 54
3419 12:46:05.071080 [Byte1]: 54
3420 12:46:05.075486
3421 12:46:05.075989 Set Vref, RX VrefLevel [Byte0]: 55
3422 12:46:05.078809 [Byte1]: 55
3423 12:46:05.083353
3424 12:46:05.083764 Set Vref, RX VrefLevel [Byte0]: 56
3425 12:46:05.086570 [Byte1]: 56
3426 12:46:05.091456
3427 12:46:05.091987 Set Vref, RX VrefLevel [Byte0]: 57
3428 12:46:05.094594 [Byte1]: 57
3429 12:46:05.099004
3430 12:46:05.099415 Set Vref, RX VrefLevel [Byte0]: 58
3431 12:46:05.102318 [Byte1]: 58
3432 12:46:05.106827
3433 12:46:05.107241 Set Vref, RX VrefLevel [Byte0]: 59
3434 12:46:05.110028 [Byte1]: 59
3435 12:46:05.114541
3436 12:46:05.114989 Set Vref, RX VrefLevel [Byte0]: 60
3437 12:46:05.117915 [Byte1]: 60
3438 12:46:05.122621
3439 12:46:05.123044 Set Vref, RX VrefLevel [Byte0]: 61
3440 12:46:05.125990 [Byte1]: 61
3441 12:46:05.130435
3442 12:46:05.130844 Set Vref, RX VrefLevel [Byte0]: 62
3443 12:46:05.133621 [Byte1]: 62
3444 12:46:05.138653
3445 12:46:05.139059 Set Vref, RX VrefLevel [Byte0]: 63
3446 12:46:05.141767 [Byte1]: 63
3447 12:46:05.146006
3448 12:46:05.146412 Set Vref, RX VrefLevel [Byte0]: 64
3449 12:46:05.149282 [Byte1]: 64
3450 12:46:05.154422
3451 12:46:05.154847 Set Vref, RX VrefLevel [Byte0]: 65
3452 12:46:05.157675 [Byte1]: 65
3453 12:46:05.162291
3454 12:46:05.162697 Set Vref, RX VrefLevel [Byte0]: 66
3455 12:46:05.164882 [Byte1]: 66
3456 12:46:05.169679
3457 12:46:05.170088 Set Vref, RX VrefLevel [Byte0]: 67
3458 12:46:05.172956 [Byte1]: 67
3459 12:46:05.177855
3460 12:46:05.178263 Set Vref, RX VrefLevel [Byte0]: 68
3461 12:46:05.180698 [Byte1]: 68
3462 12:46:05.185551
3463 12:46:05.186023 Final RX Vref Byte 0 = 52 to rank0
3464 12:46:05.188776 Final RX Vref Byte 1 = 52 to rank0
3465 12:46:05.191734 Final RX Vref Byte 0 = 52 to rank1
3466 12:46:05.195264 Final RX Vref Byte 1 = 52 to rank1==
3467 12:46:05.199046 Dram Type= 6, Freq= 0, CH_1, rank 0
3468 12:46:05.205484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3469 12:46:05.205902 ==
3470 12:46:05.206229 DQS Delay:
3471 12:46:05.206529 DQS0 = 0, DQS1 = 0
3472 12:46:05.208639 DQM Delay:
3473 12:46:05.209053 DQM0 = 120, DQM1 = 117
3474 12:46:05.212361 DQ Delay:
3475 12:46:05.215673 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3476 12:46:05.218980 DQ4 =120, DQ5 =128, DQ6 =130, DQ7 =120
3477 12:46:05.222394 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =110
3478 12:46:05.225683 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3479 12:46:05.226180
3480 12:46:05.226563
3481 12:46:05.232368 [DQSOSCAuto] RK0, (LSB)MR18= 0xfe11, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3482 12:46:05.235609 CH1 RK0: MR19=304, MR18=FE11
3483 12:46:05.242021 CH1_RK0: MR19=0x304, MR18=0xFE11, DQSOSC=403, MR23=63, INC=40, DEC=26
3484 12:46:05.242434
3485 12:46:05.245283 ----->DramcWriteLeveling(PI) begin...
3486 12:46:05.245721 ==
3487 12:46:05.248924 Dram Type= 6, Freq= 0, CH_1, rank 1
3488 12:46:05.251885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3489 12:46:05.255500 ==
3490 12:46:05.255916 Write leveling (Byte 0): 27 => 27
3491 12:46:05.258798 Write leveling (Byte 1): 27 => 27
3492 12:46:05.262114 DramcWriteLeveling(PI) end<-----
3493 12:46:05.262530
3494 12:46:05.262851 ==
3495 12:46:05.265357 Dram Type= 6, Freq= 0, CH_1, rank 1
3496 12:46:05.272771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3497 12:46:05.273187 ==
3498 12:46:05.273507 [Gating] SW mode calibration
3499 12:46:05.282561 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3500 12:46:05.285918 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3501 12:46:05.289070 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3502 12:46:05.295904 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3503 12:46:05.298835 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3504 12:46:05.302593 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3505 12:46:05.308909 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3506 12:46:05.311977 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3507 12:46:05.315286 0 15 24 | B1->B0 | 2b2b 3434 | 0 0 | (1 0) (0 1)
3508 12:46:05.322252 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 0)
3509 12:46:05.325285 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3510 12:46:05.328926 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3511 12:46:05.335415 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3512 12:46:05.338690 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3513 12:46:05.342638 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3514 12:46:05.349259 1 0 20 | B1->B0 | 2827 2323 | 1 0 | (0 0) (0 0)
3515 12:46:05.352551 1 0 24 | B1->B0 | 4343 2c2c | 0 0 | (0 0) (0 0)
3516 12:46:05.355680 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3517 12:46:05.362539 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 12:46:05.365434 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 12:46:05.368824 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 12:46:05.375390 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3521 12:46:05.378640 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 12:46:05.381917 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3523 12:46:05.385844 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3524 12:46:05.391851 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3525 12:46:05.395788 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 12:46:05.399102 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 12:46:05.405037 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 12:46:05.408610 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 12:46:05.411733 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 12:46:05.418719 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 12:46:05.421848 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 12:46:05.425420 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 12:46:05.432279 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 12:46:05.435150 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 12:46:05.438676 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 12:46:05.445626 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 12:46:05.448537 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3538 12:46:05.451853 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3539 12:46:05.458442 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3540 12:46:05.458974 Total UI for P1: 0, mck2ui 16
3541 12:46:05.465413 best dqsien dly found for B1: ( 1, 3, 18)
3542 12:46:05.468427 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3543 12:46:05.471548 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3544 12:46:05.475331 Total UI for P1: 0, mck2ui 16
3545 12:46:05.478784 best dqsien dly found for B0: ( 1, 3, 26)
3546 12:46:05.482019 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3547 12:46:05.485303 best DQS1 dly(MCK, UI, PI) = (1, 3, 18)
3548 12:46:05.485723
3549 12:46:05.488618 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3550 12:46:05.495253 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 18)
3551 12:46:05.495792 [Gating] SW calibration Done
3552 12:46:05.498533 ==
3553 12:46:05.498946 Dram Type= 6, Freq= 0, CH_1, rank 1
3554 12:46:05.505050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3555 12:46:05.505468 ==
3556 12:46:05.505792 RX Vref Scan: 0
3557 12:46:05.506094
3558 12:46:05.508441 RX Vref 0 -> 0, step: 1
3559 12:46:05.508852
3560 12:46:05.511771 RX Delay -40 -> 252, step: 8
3561 12:46:05.515298 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3562 12:46:05.518615 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3563 12:46:05.521927 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3564 12:46:05.528352 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3565 12:46:05.531708 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3566 12:46:05.534803 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3567 12:46:05.538329 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3568 12:46:05.541860 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3569 12:46:05.548421 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3570 12:46:05.551866 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3571 12:46:05.555107 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3572 12:46:05.558295 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3573 12:46:05.561601 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3574 12:46:05.568076 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3575 12:46:05.571812 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3576 12:46:05.575156 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3577 12:46:05.575586 ==
3578 12:46:05.578009 Dram Type= 6, Freq= 0, CH_1, rank 1
3579 12:46:05.581348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3580 12:46:05.581781 ==
3581 12:46:05.584776 DQS Delay:
3582 12:46:05.585286 DQS0 = 0, DQS1 = 0
3583 12:46:05.588358 DQM Delay:
3584 12:46:05.588903 DQM0 = 121, DQM1 = 117
3585 12:46:05.591249 DQ Delay:
3586 12:46:05.594664 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3587 12:46:05.597909 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3588 12:46:05.601692 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =115
3589 12:46:05.604944 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3590 12:46:05.605358
3591 12:46:05.605680
3592 12:46:05.605978 ==
3593 12:46:05.608333 Dram Type= 6, Freq= 0, CH_1, rank 1
3594 12:46:05.611647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3595 12:46:05.612062 ==
3596 12:46:05.612439
3597 12:46:05.612752
3598 12:46:05.614935 TX Vref Scan disable
3599 12:46:05.618263 == TX Byte 0 ==
3600 12:46:05.621466 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3601 12:46:05.624825 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3602 12:46:05.628062 == TX Byte 1 ==
3603 12:46:05.631448 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3604 12:46:05.634741 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3605 12:46:05.635155 ==
3606 12:46:05.638728 Dram Type= 6, Freq= 0, CH_1, rank 1
3607 12:46:05.641375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3608 12:46:05.645068 ==
3609 12:46:05.654849 TX Vref=22, minBit 10, minWin=25, winSum=417
3610 12:46:05.657976 TX Vref=24, minBit 0, minWin=26, winSum=424
3611 12:46:05.661584 TX Vref=26, minBit 1, minWin=26, winSum=428
3612 12:46:05.664576 TX Vref=28, minBit 2, minWin=26, winSum=430
3613 12:46:05.668072 TX Vref=30, minBit 9, minWin=26, winSum=433
3614 12:46:05.671353 TX Vref=32, minBit 9, minWin=26, winSum=431
3615 12:46:05.678102 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 30
3616 12:46:05.678516
3617 12:46:05.681368 Final TX Range 1 Vref 30
3618 12:46:05.681783
3619 12:46:05.682105 ==
3620 12:46:05.684542 Dram Type= 6, Freq= 0, CH_1, rank 1
3621 12:46:05.688246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3622 12:46:05.688707 ==
3623 12:46:05.689036
3624 12:46:05.691645
3625 12:46:05.692177 TX Vref Scan disable
3626 12:46:05.694716 == TX Byte 0 ==
3627 12:46:05.698086 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3628 12:46:05.701775 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3629 12:46:05.705125 == TX Byte 1 ==
3630 12:46:05.708529 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3631 12:46:05.711416 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3632 12:46:05.711832
3633 12:46:05.714745 [DATLAT]
3634 12:46:05.715155 Freq=1200, CH1 RK1
3635 12:46:05.715482
3636 12:46:05.717901 DATLAT Default: 0xd
3637 12:46:05.718351 0, 0xFFFF, sum = 0
3638 12:46:05.721342 1, 0xFFFF, sum = 0
3639 12:46:05.721761 2, 0xFFFF, sum = 0
3640 12:46:05.724809 3, 0xFFFF, sum = 0
3641 12:46:05.725230 4, 0xFFFF, sum = 0
3642 12:46:05.727849 5, 0xFFFF, sum = 0
3643 12:46:05.728495 6, 0xFFFF, sum = 0
3644 12:46:05.731219 7, 0xFFFF, sum = 0
3645 12:46:05.731781 8, 0xFFFF, sum = 0
3646 12:46:05.734496 9, 0xFFFF, sum = 0
3647 12:46:05.738337 10, 0xFFFF, sum = 0
3648 12:46:05.738842 11, 0xFFFF, sum = 0
3649 12:46:05.741494 12, 0x0, sum = 1
3650 12:46:05.742053 13, 0x0, sum = 2
3651 12:46:05.745013 14, 0x0, sum = 3
3652 12:46:05.745537 15, 0x0, sum = 4
3653 12:46:05.745874 best_step = 13
3654 12:46:05.746281
3655 12:46:05.748119 ==
3656 12:46:05.751386 Dram Type= 6, Freq= 0, CH_1, rank 1
3657 12:46:05.754622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3658 12:46:05.755032 ==
3659 12:46:05.755354 RX Vref Scan: 0
3660 12:46:05.755655
3661 12:46:05.757928 RX Vref 0 -> 0, step: 1
3662 12:46:05.758338
3663 12:46:05.761500 RX Delay -5 -> 252, step: 4
3664 12:46:05.764746 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3665 12:46:05.767831 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3666 12:46:05.774392 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3667 12:46:05.778068 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3668 12:46:05.781345 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3669 12:46:05.784619 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3670 12:46:05.787908 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3671 12:46:05.794790 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3672 12:46:05.797941 iDelay=195, Bit 8, Center 108 (47 ~ 170) 124
3673 12:46:05.800919 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3674 12:46:05.804310 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3675 12:46:05.807584 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3676 12:46:05.814236 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3677 12:46:05.817924 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3678 12:46:05.821073 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3679 12:46:05.824791 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3680 12:46:05.825228 ==
3681 12:46:05.827780 Dram Type= 6, Freq= 0, CH_1, rank 1
3682 12:46:05.834381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3683 12:46:05.834882 ==
3684 12:46:05.835298 DQS Delay:
3685 12:46:05.837974 DQS0 = 0, DQS1 = 0
3686 12:46:05.838464 DQM Delay:
3687 12:46:05.841132 DQM0 = 120, DQM1 = 118
3688 12:46:05.841542 DQ Delay:
3689 12:46:05.844457 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3690 12:46:05.848046 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3691 12:46:05.850872 DQ8 =108, DQ9 =108, DQ10 =116, DQ11 =112
3692 12:46:05.854058 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3693 12:46:05.854469
3694 12:46:05.854789
3695 12:46:05.864581 [DQSOSCAuto] RK1, (LSB)MR18= 0x11ef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3696 12:46:05.865000 CH1 RK1: MR19=403, MR18=11EF
3697 12:46:05.870985 CH1_RK1: MR19=0x403, MR18=0x11EF, DQSOSC=403, MR23=63, INC=40, DEC=26
3698 12:46:05.874140 [RxdqsGatingPostProcess] freq 1200
3699 12:46:05.881036 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3700 12:46:05.884224 best DQS0 dly(2T, 0.5T) = (0, 11)
3701 12:46:05.887371 best DQS1 dly(2T, 0.5T) = (0, 11)
3702 12:46:05.890635 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3703 12:46:05.894535 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3704 12:46:05.897865 best DQS0 dly(2T, 0.5T) = (0, 11)
3705 12:46:05.900970 best DQS1 dly(2T, 0.5T) = (0, 11)
3706 12:46:05.901384 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3707 12:46:05.904105 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3708 12:46:05.907660 Pre-setting of DQS Precalculation
3709 12:46:05.914059 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3710 12:46:05.920484 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3711 12:46:05.927646 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3712 12:46:05.927727
3713 12:46:05.927789
3714 12:46:05.930406 [Calibration Summary] 2400 Mbps
3715 12:46:05.933804 CH 0, Rank 0
3716 12:46:05.933889 SW Impedance : PASS
3717 12:46:05.937178 DUTY Scan : NO K
3718 12:46:05.937270 ZQ Calibration : PASS
3719 12:46:05.940206 Jitter Meter : NO K
3720 12:46:05.943976 CBT Training : PASS
3721 12:46:05.944075 Write leveling : PASS
3722 12:46:05.947033 RX DQS gating : PASS
3723 12:46:05.950322 RX DQ/DQS(RDDQC) : PASS
3724 12:46:05.950402 TX DQ/DQS : PASS
3725 12:46:05.953449 RX DATLAT : PASS
3726 12:46:05.956980 RX DQ/DQS(Engine): PASS
3727 12:46:05.957061 TX OE : NO K
3728 12:46:05.959958 All Pass.
3729 12:46:05.960038
3730 12:46:05.960101 CH 0, Rank 1
3731 12:46:05.963428 SW Impedance : PASS
3732 12:46:05.963509 DUTY Scan : NO K
3733 12:46:05.967115 ZQ Calibration : PASS
3734 12:46:05.970443 Jitter Meter : NO K
3735 12:46:05.970524 CBT Training : PASS
3736 12:46:05.973746 Write leveling : PASS
3737 12:46:05.976867 RX DQS gating : PASS
3738 12:46:05.976947 RX DQ/DQS(RDDQC) : PASS
3739 12:46:05.980148 TX DQ/DQS : PASS
3740 12:46:05.983445 RX DATLAT : PASS
3741 12:46:05.983526 RX DQ/DQS(Engine): PASS
3742 12:46:05.986526 TX OE : NO K
3743 12:46:05.986606 All Pass.
3744 12:46:05.986669
3745 12:46:05.990340 CH 1, Rank 0
3746 12:46:05.990420 SW Impedance : PASS
3747 12:46:05.993461 DUTY Scan : NO K
3748 12:46:05.993541 ZQ Calibration : PASS
3749 12:46:05.996699 Jitter Meter : NO K
3750 12:46:06.000013 CBT Training : PASS
3751 12:46:06.000092 Write leveling : PASS
3752 12:46:06.003320 RX DQS gating : PASS
3753 12:46:06.006797 RX DQ/DQS(RDDQC) : PASS
3754 12:46:06.006877 TX DQ/DQS : PASS
3755 12:46:06.009958 RX DATLAT : PASS
3756 12:46:06.013162 RX DQ/DQS(Engine): PASS
3757 12:46:06.013241 TX OE : NO K
3758 12:46:06.016365 All Pass.
3759 12:46:06.016445
3760 12:46:06.016509 CH 1, Rank 1
3761 12:46:06.019653 SW Impedance : PASS
3762 12:46:06.019733 DUTY Scan : NO K
3763 12:46:06.023052 ZQ Calibration : PASS
3764 12:46:06.026921 Jitter Meter : NO K
3765 12:46:06.027001 CBT Training : PASS
3766 12:46:06.029985 Write leveling : PASS
3767 12:46:06.033361 RX DQS gating : PASS
3768 12:46:06.033441 RX DQ/DQS(RDDQC) : PASS
3769 12:46:06.036617 TX DQ/DQS : PASS
3770 12:46:06.039970 RX DATLAT : PASS
3771 12:46:06.040051 RX DQ/DQS(Engine): PASS
3772 12:46:06.043261 TX OE : NO K
3773 12:46:06.043342 All Pass.
3774 12:46:06.043405
3775 12:46:06.046517 DramC Write-DBI off
3776 12:46:06.049513 PER_BANK_REFRESH: Hybrid Mode
3777 12:46:06.049593 TX_TRACKING: ON
3778 12:46:06.059824 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3779 12:46:06.062986 [FAST_K] Save calibration result to emmc
3780 12:46:06.066346 dramc_set_vcore_voltage set vcore to 650000
3781 12:46:06.066426 Read voltage for 600, 5
3782 12:46:06.069995 Vio18 = 0
3783 12:46:06.070075 Vcore = 650000
3784 12:46:06.070137 Vdram = 0
3785 12:46:06.072978 Vddq = 0
3786 12:46:06.073058 Vmddr = 0
3787 12:46:06.079721 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3788 12:46:06.083279 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3789 12:46:06.086555 MEM_TYPE=3, freq_sel=19
3790 12:46:06.090060 sv_algorithm_assistance_LP4_1600
3791 12:46:06.093136 ============ PULL DRAM RESETB DOWN ============
3792 12:46:06.096550 ========== PULL DRAM RESETB DOWN end =========
3793 12:46:06.103391 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3794 12:46:06.106742 ===================================
3795 12:46:06.106875 LPDDR4 DRAM CONFIGURATION
3796 12:46:06.109929 ===================================
3797 12:46:06.113180 EX_ROW_EN[0] = 0x0
3798 12:46:06.113329 EX_ROW_EN[1] = 0x0
3799 12:46:06.116460 LP4Y_EN = 0x0
3800 12:46:06.119570 WORK_FSP = 0x0
3801 12:46:06.119769 WL = 0x2
3802 12:46:06.122720 RL = 0x2
3803 12:46:06.122799 BL = 0x2
3804 12:46:06.126163 RPST = 0x0
3805 12:46:06.126249 RD_PRE = 0x0
3806 12:46:06.129511 WR_PRE = 0x1
3807 12:46:06.129615 WR_PST = 0x0
3808 12:46:06.132711 DBI_WR = 0x0
3809 12:46:06.132803 DBI_RD = 0x0
3810 12:46:06.136303 OTF = 0x1
3811 12:46:06.139594 ===================================
3812 12:46:06.142930 ===================================
3813 12:46:06.143039 ANA top config
3814 12:46:06.146176 ===================================
3815 12:46:06.149542 DLL_ASYNC_EN = 0
3816 12:46:06.152636 ALL_SLAVE_EN = 1
3817 12:46:06.152768 NEW_RANK_MODE = 1
3818 12:46:06.155957 DLL_IDLE_MODE = 1
3819 12:46:06.159658 LP45_APHY_COMB_EN = 1
3820 12:46:06.162564 TX_ODT_DIS = 1
3821 12:46:06.165887 NEW_8X_MODE = 1
3822 12:46:06.169730 ===================================
3823 12:46:06.173084 ===================================
3824 12:46:06.173325 data_rate = 1200
3825 12:46:06.176350 CKR = 1
3826 12:46:06.179812 DQ_P2S_RATIO = 8
3827 12:46:06.183176 ===================================
3828 12:46:06.186397 CA_P2S_RATIO = 8
3829 12:46:06.189437 DQ_CA_OPEN = 0
3830 12:46:06.192925 DQ_SEMI_OPEN = 0
3831 12:46:06.193350 CA_SEMI_OPEN = 0
3832 12:46:06.196428 CA_FULL_RATE = 0
3833 12:46:06.199626 DQ_CKDIV4_EN = 1
3834 12:46:06.202925 CA_CKDIV4_EN = 1
3835 12:46:06.206162 CA_PREDIV_EN = 0
3836 12:46:06.209584 PH8_DLY = 0
3837 12:46:06.210008 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3838 12:46:06.212985 DQ_AAMCK_DIV = 4
3839 12:46:06.216180 CA_AAMCK_DIV = 4
3840 12:46:06.219432 CA_ADMCK_DIV = 4
3841 12:46:06.223388 DQ_TRACK_CA_EN = 0
3842 12:46:06.226588 CA_PICK = 600
3843 12:46:06.227113 CA_MCKIO = 600
3844 12:46:06.229899 MCKIO_SEMI = 0
3845 12:46:06.233049 PLL_FREQ = 2288
3846 12:46:06.236427 DQ_UI_PI_RATIO = 32
3847 12:46:06.239823 CA_UI_PI_RATIO = 0
3848 12:46:06.243073 ===================================
3849 12:46:06.246068 ===================================
3850 12:46:06.249538 memory_type:LPDDR4
3851 12:46:06.249951 GP_NUM : 10
3852 12:46:06.252830 SRAM_EN : 1
3853 12:46:06.253243 MD32_EN : 0
3854 12:46:06.256004 ===================================
3855 12:46:06.259279 [ANA_INIT] >>>>>>>>>>>>>>
3856 12:46:06.263168 <<<<<< [CONFIGURE PHASE]: ANA_TX
3857 12:46:06.266270 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3858 12:46:06.269251 ===================================
3859 12:46:06.272850 data_rate = 1200,PCW = 0X5800
3860 12:46:06.276053 ===================================
3861 12:46:06.279455 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3862 12:46:06.285750 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3863 12:46:06.289009 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3864 12:46:06.295731 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3865 12:46:06.299417 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3866 12:46:06.302429 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3867 12:46:06.302530 [ANA_INIT] flow start
3868 12:46:06.305901 [ANA_INIT] PLL >>>>>>>>
3869 12:46:06.308953 [ANA_INIT] PLL <<<<<<<<
3870 12:46:06.309061 [ANA_INIT] MIDPI >>>>>>>>
3871 12:46:06.312565 [ANA_INIT] MIDPI <<<<<<<<
3872 12:46:06.315810 [ANA_INIT] DLL >>>>>>>>
3873 12:46:06.315971 [ANA_INIT] flow end
3874 12:46:06.319090 ============ LP4 DIFF to SE enter ============
3875 12:46:06.326047 ============ LP4 DIFF to SE exit ============
3876 12:46:06.326229 [ANA_INIT] <<<<<<<<<<<<<
3877 12:46:06.329458 [Flow] Enable top DCM control >>>>>
3878 12:46:06.332714 [Flow] Enable top DCM control <<<<<
3879 12:46:06.335701 Enable DLL master slave shuffle
3880 12:46:06.342713 ==============================================================
3881 12:46:06.343120 Gating Mode config
3882 12:46:06.349136 ==============================================================
3883 12:46:06.352789 Config description:
3884 12:46:06.363273 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3885 12:46:06.369325 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3886 12:46:06.372801 SELPH_MODE 0: By rank 1: By Phase
3887 12:46:06.379496 ==============================================================
3888 12:46:06.382588 GAT_TRACK_EN = 1
3889 12:46:06.386364 RX_GATING_MODE = 2
3890 12:46:06.386849 RX_GATING_TRACK_MODE = 2
3891 12:46:06.389613 SELPH_MODE = 1
3892 12:46:06.393086 PICG_EARLY_EN = 1
3893 12:46:06.395646 VALID_LAT_VALUE = 1
3894 12:46:06.402214 ==============================================================
3895 12:46:06.405619 Enter into Gating configuration >>>>
3896 12:46:06.408959 Exit from Gating configuration <<<<
3897 12:46:06.413033 Enter into DVFS_PRE_config >>>>>
3898 12:46:06.422904 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3899 12:46:06.426118 Exit from DVFS_PRE_config <<<<<
3900 12:46:06.429216 Enter into PICG configuration >>>>
3901 12:46:06.432215 Exit from PICG configuration <<<<
3902 12:46:06.436035 [RX_INPUT] configuration >>>>>
3903 12:46:06.439118 [RX_INPUT] configuration <<<<<
3904 12:46:06.442401 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3905 12:46:06.449090 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3906 12:46:06.455531 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3907 12:46:06.462297 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3908 12:46:06.465676 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3909 12:46:06.472060 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3910 12:46:06.475441 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3911 12:46:06.482512 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3912 12:46:06.485613 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3913 12:46:06.489006 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3914 12:46:06.492535 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3915 12:46:06.499242 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3916 12:46:06.502280 ===================================
3917 12:46:06.502703 LPDDR4 DRAM CONFIGURATION
3918 12:46:06.505690 ===================================
3919 12:46:06.509046 EX_ROW_EN[0] = 0x0
3920 12:46:06.512035 EX_ROW_EN[1] = 0x0
3921 12:46:06.512579 LP4Y_EN = 0x0
3922 12:46:06.515222 WORK_FSP = 0x0
3923 12:46:06.515675 WL = 0x2
3924 12:46:06.519060 RL = 0x2
3925 12:46:06.519680 BL = 0x2
3926 12:46:06.521850 RPST = 0x0
3927 12:46:06.522405 RD_PRE = 0x0
3928 12:46:06.525843 WR_PRE = 0x1
3929 12:46:06.526396 WR_PST = 0x0
3930 12:46:06.528513 DBI_WR = 0x0
3931 12:46:06.528593 DBI_RD = 0x0
3932 12:46:06.531456 OTF = 0x1
3933 12:46:06.535291 ===================================
3934 12:46:06.538541 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3935 12:46:06.541912 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3936 12:46:06.548460 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3937 12:46:06.551716 ===================================
3938 12:46:06.551829 LPDDR4 DRAM CONFIGURATION
3939 12:46:06.554881 ===================================
3940 12:46:06.558306 EX_ROW_EN[0] = 0x10
3941 12:46:06.561666 EX_ROW_EN[1] = 0x0
3942 12:46:06.561762 LP4Y_EN = 0x0
3943 12:46:06.564735 WORK_FSP = 0x0
3944 12:46:06.564845 WL = 0x2
3945 12:46:06.568631 RL = 0x2
3946 12:46:06.568729 BL = 0x2
3947 12:46:06.571602 RPST = 0x0
3948 12:46:06.571741 RD_PRE = 0x0
3949 12:46:06.574699 WR_PRE = 0x1
3950 12:46:06.574799 WR_PST = 0x0
3951 12:46:06.578764 DBI_WR = 0x0
3952 12:46:06.578872 DBI_RD = 0x0
3953 12:46:06.581960 OTF = 0x1
3954 12:46:06.584921 ===================================
3955 12:46:06.591457 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3956 12:46:06.595163 nWR fixed to 30
3957 12:46:06.595317 [ModeRegInit_LP4] CH0 RK0
3958 12:46:06.598364 [ModeRegInit_LP4] CH0 RK1
3959 12:46:06.601639 [ModeRegInit_LP4] CH1 RK0
3960 12:46:06.601834 [ModeRegInit_LP4] CH1 RK1
3961 12:46:06.605045 match AC timing 17
3962 12:46:06.608748 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3963 12:46:06.612134 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3964 12:46:06.618748 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3965 12:46:06.621998 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3966 12:46:06.628844 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3967 12:46:06.629261 ==
3968 12:46:06.632182 Dram Type= 6, Freq= 0, CH_0, rank 0
3969 12:46:06.635481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3970 12:46:06.635906 ==
3971 12:46:06.642139 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3972 12:46:06.645650 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3973 12:46:06.649597 [CA 0] Center 35 (5~66) winsize 62
3974 12:46:06.652917 [CA 1] Center 35 (5~66) winsize 62
3975 12:46:06.656739 [CA 2] Center 33 (3~64) winsize 62
3976 12:46:06.659918 [CA 3] Center 33 (2~64) winsize 63
3977 12:46:06.663350 [CA 4] Center 33 (2~64) winsize 63
3978 12:46:06.666517 [CA 5] Center 32 (2~63) winsize 62
3979 12:46:06.666936
3980 12:46:06.669885 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3981 12:46:06.670296
3982 12:46:06.673170 [CATrainingPosCal] consider 1 rank data
3983 12:46:06.676566 u2DelayCellTimex100 = 270/100 ps
3984 12:46:06.679875 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3985 12:46:06.683151 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3986 12:46:06.689836 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3987 12:46:06.693126 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3988 12:46:06.696354 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3989 12:46:06.699459 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3990 12:46:06.699888
3991 12:46:06.703119 CA PerBit enable=1, Macro0, CA PI delay=32
3992 12:46:06.703548
3993 12:46:06.706407 [CBTSetCACLKResult] CA Dly = 32
3994 12:46:06.706833 CS Dly: 4 (0~35)
3995 12:46:06.707263 ==
3996 12:46:06.709911 Dram Type= 6, Freq= 0, CH_0, rank 1
3997 12:46:06.716165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3998 12:46:06.716622 ==
3999 12:46:06.719886 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4000 12:46:06.726286 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4001 12:46:06.729583 [CA 0] Center 35 (5~66) winsize 62
4002 12:46:06.733325 [CA 1] Center 35 (5~66) winsize 62
4003 12:46:06.736616 [CA 2] Center 34 (3~65) winsize 63
4004 12:46:06.739777 [CA 3] Center 33 (3~64) winsize 62
4005 12:46:06.742914 [CA 4] Center 33 (2~64) winsize 63
4006 12:46:06.746940 [CA 5] Center 32 (2~63) winsize 62
4007 12:46:06.747453
4008 12:46:06.749941 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4009 12:46:06.750354
4010 12:46:06.752872 [CATrainingPosCal] consider 2 rank data
4011 12:46:06.756708 u2DelayCellTimex100 = 270/100 ps
4012 12:46:06.760070 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4013 12:46:06.763181 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4014 12:46:06.769696 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4015 12:46:06.773113 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4016 12:46:06.776373 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4017 12:46:06.779870 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4018 12:46:06.780281
4019 12:46:06.783190 CA PerBit enable=1, Macro0, CA PI delay=32
4020 12:46:06.783604
4021 12:46:06.786304 [CBTSetCACLKResult] CA Dly = 32
4022 12:46:06.786737 CS Dly: 4 (0~36)
4023 12:46:06.787164
4024 12:46:06.789812 ----->DramcWriteLeveling(PI) begin...
4025 12:46:06.792878 ==
4026 12:46:06.796363 Dram Type= 6, Freq= 0, CH_0, rank 0
4027 12:46:06.799869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4028 12:46:06.800450 ==
4029 12:46:06.802934 Write leveling (Byte 0): 33 => 33
4030 12:46:06.806374 Write leveling (Byte 1): 32 => 32
4031 12:46:06.809547 DramcWriteLeveling(PI) end<-----
4032 12:46:06.809983
4033 12:46:06.810416 ==
4034 12:46:06.813118 Dram Type= 6, Freq= 0, CH_0, rank 0
4035 12:46:06.816113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4036 12:46:06.816578 ==
4037 12:46:06.819514 [Gating] SW mode calibration
4038 12:46:06.826001 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4039 12:46:06.829321 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4040 12:46:06.836424 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4041 12:46:06.839779 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4042 12:46:06.842706 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4043 12:46:06.849395 0 9 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
4044 12:46:06.853023 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (1 0)
4045 12:46:06.856006 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 12:46:06.862664 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 12:46:06.866389 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 12:46:06.869521 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 12:46:06.876126 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 12:46:06.879802 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 12:46:06.882951 0 10 12 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
4052 12:46:06.889613 0 10 16 | B1->B0 | 2e2e 4646 | 1 0 | (0 0) (0 0)
4053 12:46:06.892899 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 12:46:06.896339 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 12:46:06.902869 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 12:46:06.906074 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 12:46:06.909343 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 12:46:06.916654 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 12:46:06.920031 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 12:46:06.923146 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4061 12:46:06.929542 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 12:46:06.932561 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 12:46:06.936475 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 12:46:06.939812 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 12:46:06.946540 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 12:46:06.950111 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 12:46:06.953036 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 12:46:06.959546 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 12:46:06.963364 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 12:46:06.966283 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 12:46:06.973041 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 12:46:06.976157 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 12:46:06.979443 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 12:46:06.986418 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 12:46:06.989711 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4076 12:46:06.992945 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4077 12:46:06.996698 Total UI for P1: 0, mck2ui 16
4078 12:46:06.999570 best dqsien dly found for B0: ( 0, 13, 12)
4079 12:46:07.006196 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4080 12:46:07.006713 Total UI for P1: 0, mck2ui 16
4081 12:46:07.009545 best dqsien dly found for B1: ( 0, 13, 16)
4082 12:46:07.015991 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4083 12:46:07.019325 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4084 12:46:07.019741
4085 12:46:07.022589 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4086 12:46:07.026503 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4087 12:46:07.029198 [Gating] SW calibration Done
4088 12:46:07.029614 ==
4089 12:46:07.032595 Dram Type= 6, Freq= 0, CH_0, rank 0
4090 12:46:07.036329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4091 12:46:07.036755 ==
4092 12:46:07.039435 RX Vref Scan: 0
4093 12:46:07.039853
4094 12:46:07.040217 RX Vref 0 -> 0, step: 1
4095 12:46:07.040612
4096 12:46:07.042694 RX Delay -230 -> 252, step: 16
4097 12:46:07.046066 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4098 12:46:07.052793 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4099 12:46:07.056061 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4100 12:46:07.059656 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4101 12:46:07.062549 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4102 12:46:07.069605 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4103 12:46:07.072518 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4104 12:46:07.075892 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4105 12:46:07.079217 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4106 12:46:07.086381 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4107 12:46:07.089009 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4108 12:46:07.092231 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4109 12:46:07.096052 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4110 12:46:07.099581 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4111 12:46:07.105932 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4112 12:46:07.109295 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4113 12:46:07.109717 ==
4114 12:46:07.112349 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 12:46:07.115539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 12:46:07.115979 ==
4117 12:46:07.119103 DQS Delay:
4118 12:46:07.119520 DQS0 = 0, DQS1 = 0
4119 12:46:07.121923 DQM Delay:
4120 12:46:07.122345 DQM0 = 48, DQM1 = 44
4121 12:46:07.122672 DQ Delay:
4122 12:46:07.125164 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4123 12:46:07.128443 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4124 12:46:07.131864 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4125 12:46:07.135678 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4126 12:46:07.136209
4127 12:46:07.136646
4128 12:46:07.138511 ==
4129 12:46:07.138929 Dram Type= 6, Freq= 0, CH_0, rank 0
4130 12:46:07.145013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4131 12:46:07.145405 ==
4132 12:46:07.145713
4133 12:46:07.145962
4134 12:46:07.148106 TX Vref Scan disable
4135 12:46:07.148353 == TX Byte 0 ==
4136 12:46:07.151600 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4137 12:46:07.158241 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4138 12:46:07.158394 == TX Byte 1 ==
4139 12:46:07.161623 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4140 12:46:07.168209 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4141 12:46:07.168356 ==
4142 12:46:07.171441 Dram Type= 6, Freq= 0, CH_0, rank 0
4143 12:46:07.174839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4144 12:46:07.174961 ==
4145 12:46:07.175078
4146 12:46:07.175186
4147 12:46:07.177973 TX Vref Scan disable
4148 12:46:07.181490 == TX Byte 0 ==
4149 12:46:07.184974 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4150 12:46:07.187903 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4151 12:46:07.191727 == TX Byte 1 ==
4152 12:46:07.194838 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4153 12:46:07.198456 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4154 12:46:07.198539
4155 12:46:07.201610 [DATLAT]
4156 12:46:07.201693 Freq=600, CH0 RK0
4157 12:46:07.201776
4158 12:46:07.204433 DATLAT Default: 0x9
4159 12:46:07.204516 0, 0xFFFF, sum = 0
4160 12:46:07.208241 1, 0xFFFF, sum = 0
4161 12:46:07.208366 2, 0xFFFF, sum = 0
4162 12:46:07.211024 3, 0xFFFF, sum = 0
4163 12:46:07.211108 4, 0xFFFF, sum = 0
4164 12:46:07.214248 5, 0xFFFF, sum = 0
4165 12:46:07.214332 6, 0xFFFF, sum = 0
4166 12:46:07.217642 7, 0xFFFF, sum = 0
4167 12:46:07.217725 8, 0x0, sum = 1
4168 12:46:07.220927 9, 0x0, sum = 2
4169 12:46:07.221017 10, 0x0, sum = 3
4170 12:46:07.224741 11, 0x0, sum = 4
4171 12:46:07.224831 best_step = 9
4172 12:46:07.224920
4173 12:46:07.225004 ==
4174 12:46:07.228048 Dram Type= 6, Freq= 0, CH_0, rank 0
4175 12:46:07.230931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4176 12:46:07.234828 ==
4177 12:46:07.234930 RX Vref Scan: 1
4178 12:46:07.235034
4179 12:46:07.237631 RX Vref 0 -> 0, step: 1
4180 12:46:07.237743
4181 12:46:07.241333 RX Delay -163 -> 252, step: 8
4182 12:46:07.241445
4183 12:46:07.244263 Set Vref, RX VrefLevel [Byte0]: 58
4184 12:46:07.247795 [Byte1]: 53
4185 12:46:07.247907
4186 12:46:07.251371 Final RX Vref Byte 0 = 58 to rank0
4187 12:46:07.254515 Final RX Vref Byte 1 = 53 to rank0
4188 12:46:07.257417 Final RX Vref Byte 0 = 58 to rank1
4189 12:46:07.260838 Final RX Vref Byte 1 = 53 to rank1==
4190 12:46:07.264110 Dram Type= 6, Freq= 0, CH_0, rank 0
4191 12:46:07.267450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4192 12:46:07.267539 ==
4193 12:46:07.267629 DQS Delay:
4194 12:46:07.270580 DQS0 = 0, DQS1 = 0
4195 12:46:07.270674 DQM Delay:
4196 12:46:07.274140 DQM0 = 52, DQM1 = 46
4197 12:46:07.274240 DQ Delay:
4198 12:46:07.281030 DQ0 =52, DQ1 =52, DQ2 =48, DQ3 =48
4199 12:46:07.281157 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4200 12:46:07.284033 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4201 12:46:07.288324 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4202 12:46:07.288449
4203 12:46:07.288572
4204 12:46:07.297826 [DQSOSCAuto] RK0, (LSB)MR18= 0x7063, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 388 ps
4205 12:46:07.297989 CH0 RK0: MR19=808, MR18=7063
4206 12:46:07.304480 CH0_RK0: MR19=0x808, MR18=0x7063, DQSOSC=388, MR23=63, INC=174, DEC=116
4207 12:46:07.304656
4208 12:46:07.307510 ----->DramcWriteLeveling(PI) begin...
4209 12:46:07.307798 ==
4210 12:46:07.311392 Dram Type= 6, Freq= 0, CH_0, rank 1
4211 12:46:07.317961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4212 12:46:07.318391 ==
4213 12:46:07.321256 Write leveling (Byte 0): 34 => 34
4214 12:46:07.324786 Write leveling (Byte 1): 31 => 31
4215 12:46:07.325211 DramcWriteLeveling(PI) end<-----
4216 12:46:07.325638
4217 12:46:07.328049 ==
4218 12:46:07.331140 Dram Type= 6, Freq= 0, CH_0, rank 1
4219 12:46:07.334490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4220 12:46:07.334916 ==
4221 12:46:07.337883 [Gating] SW mode calibration
4222 12:46:07.344475 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4223 12:46:07.347738 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4224 12:46:07.354413 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4225 12:46:07.357927 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4226 12:46:07.361075 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4227 12:46:07.367780 0 9 12 | B1->B0 | 3333 3333 | 1 1 | (1 0) (1 0)
4228 12:46:07.370972 0 9 16 | B1->B0 | 2727 2828 | 0 0 | (1 1) (0 0)
4229 12:46:07.374185 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 12:46:07.381032 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 12:46:07.384271 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 12:46:07.387676 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 12:46:07.394254 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 12:46:07.397705 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 12:46:07.400623 0 10 12 | B1->B0 | 2525 2b2b | 0 0 | (0 0) (0 0)
4236 12:46:07.407106 0 10 16 | B1->B0 | 4040 4040 | 0 1 | (1 1) (0 0)
4237 12:46:07.410810 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 12:46:07.413796 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 12:46:07.420397 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 12:46:07.424012 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 12:46:07.427229 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 12:46:07.434071 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 12:46:07.437167 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4244 12:46:07.440478 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4245 12:46:07.444188 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 12:46:07.450835 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 12:46:07.454015 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 12:46:07.457048 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 12:46:07.463928 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 12:46:07.467311 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 12:46:07.470554 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 12:46:07.477309 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 12:46:07.480522 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 12:46:07.483761 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 12:46:07.490518 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 12:46:07.493872 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 12:46:07.497157 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 12:46:07.503887 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 12:46:07.506762 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 12:46:07.510383 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4261 12:46:07.513556 Total UI for P1: 0, mck2ui 16
4262 12:46:07.516571 best dqsien dly found for B0: ( 0, 13, 14)
4263 12:46:07.523388 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 12:46:07.523537 Total UI for P1: 0, mck2ui 16
4265 12:46:07.530090 best dqsien dly found for B1: ( 0, 13, 16)
4266 12:46:07.533531 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4267 12:46:07.536637 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4268 12:46:07.536736
4269 12:46:07.540098 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4270 12:46:07.543405 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4271 12:46:07.546887 [Gating] SW calibration Done
4272 12:46:07.546968 ==
4273 12:46:07.550057 Dram Type= 6, Freq= 0, CH_0, rank 1
4274 12:46:07.553419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4275 12:46:07.553500 ==
4276 12:46:07.556673 RX Vref Scan: 0
4277 12:46:07.556752
4278 12:46:07.556815 RX Vref 0 -> 0, step: 1
4279 12:46:07.556873
4280 12:46:07.559865 RX Delay -230 -> 252, step: 16
4281 12:46:07.563091 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4282 12:46:07.569871 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4283 12:46:07.573099 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4284 12:46:07.576555 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4285 12:46:07.579773 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4286 12:46:07.586498 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4287 12:46:07.589860 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4288 12:46:07.593056 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4289 12:46:07.596616 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4290 12:46:07.599984 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4291 12:46:07.606136 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4292 12:46:07.609529 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4293 12:46:07.612876 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4294 12:46:07.616083 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4295 12:46:07.622947 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4296 12:46:07.626049 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4297 12:46:07.626154 ==
4298 12:46:07.629739 Dram Type= 6, Freq= 0, CH_0, rank 1
4299 12:46:07.632996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4300 12:46:07.633076 ==
4301 12:46:07.636141 DQS Delay:
4302 12:46:07.636246 DQS0 = 0, DQS1 = 0
4303 12:46:07.639769 DQM Delay:
4304 12:46:07.639847 DQM0 = 50, DQM1 = 42
4305 12:46:07.639909 DQ Delay:
4306 12:46:07.642689 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4307 12:46:07.646056 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4308 12:46:07.649498 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4309 12:46:07.652541 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4310 12:46:07.652621
4311 12:46:07.652683
4312 12:46:07.652740 ==
4313 12:46:07.656317 Dram Type= 6, Freq= 0, CH_0, rank 1
4314 12:46:07.662768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4315 12:46:07.662849 ==
4316 12:46:07.662911
4317 12:46:07.662969
4318 12:46:07.663023 TX Vref Scan disable
4319 12:46:07.666654 == TX Byte 0 ==
4320 12:46:07.669811 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4321 12:46:07.676314 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4322 12:46:07.676407 == TX Byte 1 ==
4323 12:46:07.679818 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4324 12:46:07.686848 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4325 12:46:07.686950 ==
4326 12:46:07.690120 Dram Type= 6, Freq= 0, CH_0, rank 1
4327 12:46:07.693527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4328 12:46:07.693649 ==
4329 12:46:07.693743
4330 12:46:07.693824
4331 12:46:07.696841 TX Vref Scan disable
4332 12:46:07.699541 == TX Byte 0 ==
4333 12:46:07.702884 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4334 12:46:07.706916 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4335 12:46:07.710183 == TX Byte 1 ==
4336 12:46:07.712907 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4337 12:46:07.716764 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4338 12:46:07.716936
4339 12:46:07.717084 [DATLAT]
4340 12:46:07.719990 Freq=600, CH0 RK1
4341 12:46:07.720165
4342 12:46:07.720341 DATLAT Default: 0x9
4343 12:46:07.723560 0, 0xFFFF, sum = 0
4344 12:46:07.723694 1, 0xFFFF, sum = 0
4345 12:46:07.726928 2, 0xFFFF, sum = 0
4346 12:46:07.730130 3, 0xFFFF, sum = 0
4347 12:46:07.730264 4, 0xFFFF, sum = 0
4348 12:46:07.733490 5, 0xFFFF, sum = 0
4349 12:46:07.733642 6, 0xFFFF, sum = 0
4350 12:46:07.736762 7, 0xFFFF, sum = 0
4351 12:46:07.736896 8, 0x0, sum = 1
4352 12:46:07.737001 9, 0x0, sum = 2
4353 12:46:07.739875 10, 0x0, sum = 3
4354 12:46:07.740055 11, 0x0, sum = 4
4355 12:46:07.743607 best_step = 9
4356 12:46:07.743738
4357 12:46:07.743841 ==
4358 12:46:07.747010 Dram Type= 6, Freq= 0, CH_0, rank 1
4359 12:46:07.749507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4360 12:46:07.749644 ==
4361 12:46:07.753348 RX Vref Scan: 0
4362 12:46:07.753478
4363 12:46:07.753580 RX Vref 0 -> 0, step: 1
4364 12:46:07.753695
4365 12:46:07.756551 RX Delay -163 -> 252, step: 8
4366 12:46:07.763519 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4367 12:46:07.766775 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4368 12:46:07.770766 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4369 12:46:07.773327 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4370 12:46:07.779983 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4371 12:46:07.783556 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4372 12:46:07.786673 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4373 12:46:07.790176 iDelay=205, Bit 7, Center 60 (-83 ~ 204) 288
4374 12:46:07.793126 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4375 12:46:07.799883 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4376 12:46:07.803521 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4377 12:46:07.806836 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4378 12:46:07.809818 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4379 12:46:07.812925 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4380 12:46:07.819973 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4381 12:46:07.823257 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4382 12:46:07.823498 ==
4383 12:46:07.826626 Dram Type= 6, Freq= 0, CH_0, rank 1
4384 12:46:07.830046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4385 12:46:07.830369 ==
4386 12:46:07.833412 DQS Delay:
4387 12:46:07.833716 DQS0 = 0, DQS1 = 0
4388 12:46:07.834009 DQM Delay:
4389 12:46:07.836549 DQM0 = 53, DQM1 = 46
4390 12:46:07.836784 DQ Delay:
4391 12:46:07.840090 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4392 12:46:07.843377 DQ4 =52, DQ5 =44, DQ6 =56, DQ7 =60
4393 12:46:07.846471 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =36
4394 12:46:07.849763 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4395 12:46:07.849999
4396 12:46:07.850183
4397 12:46:07.859914 [DQSOSCAuto] RK1, (LSB)MR18= 0x6424, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4398 12:46:07.860023 CH0 RK1: MR19=808, MR18=6424
4399 12:46:07.866170 CH0_RK1: MR19=0x808, MR18=0x6424, DQSOSC=391, MR23=63, INC=171, DEC=114
4400 12:46:07.869364 [RxdqsGatingPostProcess] freq 600
4401 12:46:07.875854 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4402 12:46:07.879346 Pre-setting of DQS Precalculation
4403 12:46:07.882729 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4404 12:46:07.882810 ==
4405 12:46:07.885916 Dram Type= 6, Freq= 0, CH_1, rank 0
4406 12:46:07.892664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4407 12:46:07.892776 ==
4408 12:46:07.896049 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4409 12:46:07.902804 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4410 12:46:07.906128 [CA 0] Center 36 (5~67) winsize 63
4411 12:46:07.909397 [CA 1] Center 36 (5~67) winsize 63
4412 12:46:07.912575 [CA 2] Center 34 (4~65) winsize 62
4413 12:46:07.915878 [CA 3] Center 34 (4~65) winsize 62
4414 12:46:07.919560 [CA 4] Center 34 (4~65) winsize 62
4415 12:46:07.922577 [CA 5] Center 33 (3~64) winsize 62
4416 12:46:07.922658
4417 12:46:07.925966 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4418 12:46:07.926046
4419 12:46:07.929169 [CATrainingPosCal] consider 1 rank data
4420 12:46:07.932558 u2DelayCellTimex100 = 270/100 ps
4421 12:46:07.936007 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4422 12:46:07.942619 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4423 12:46:07.946153 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4424 12:46:07.949425 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4425 12:46:07.952734 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4426 12:46:07.956100 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4427 12:46:07.956181
4428 12:46:07.959325 CA PerBit enable=1, Macro0, CA PI delay=33
4429 12:46:07.959436
4430 12:46:07.962015 [CBTSetCACLKResult] CA Dly = 33
4431 12:46:07.962131 CS Dly: 6 (0~37)
4432 12:46:07.965820 ==
4433 12:46:07.969298 Dram Type= 6, Freq= 0, CH_1, rank 1
4434 12:46:07.972151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4435 12:46:07.972235 ==
4436 12:46:07.975486 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4437 12:46:07.982570 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4438 12:46:07.986405 [CA 0] Center 36 (5~67) winsize 63
4439 12:46:07.989830 [CA 1] Center 36 (5~67) winsize 63
4440 12:46:07.992989 [CA 2] Center 34 (4~65) winsize 62
4441 12:46:07.996481 [CA 3] Center 34 (4~65) winsize 62
4442 12:46:07.999795 [CA 4] Center 34 (4~65) winsize 62
4443 12:46:08.003098 [CA 5] Center 34 (3~65) winsize 63
4444 12:46:08.003205
4445 12:46:08.005860 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4446 12:46:08.005966
4447 12:46:08.009252 [CATrainingPosCal] consider 2 rank data
4448 12:46:08.013279 u2DelayCellTimex100 = 270/100 ps
4449 12:46:08.015816 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4450 12:46:08.019395 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4451 12:46:08.026123 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4452 12:46:08.029422 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4453 12:46:08.032648 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4454 12:46:08.035965 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4455 12:46:08.036070
4456 12:46:08.039618 CA PerBit enable=1, Macro0, CA PI delay=33
4457 12:46:08.039720
4458 12:46:08.042715 [CBTSetCACLKResult] CA Dly = 33
4459 12:46:08.042796 CS Dly: 6 (0~37)
4460 12:46:08.042860
4461 12:46:08.045829 ----->DramcWriteLeveling(PI) begin...
4462 12:46:08.049368 ==
4463 12:46:08.052690 Dram Type= 6, Freq= 0, CH_1, rank 0
4464 12:46:08.056127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4465 12:46:08.056230 ==
4466 12:46:08.059205 Write leveling (Byte 0): 33 => 33
4467 12:46:08.062404 Write leveling (Byte 1): 33 => 33
4468 12:46:08.066366 DramcWriteLeveling(PI) end<-----
4469 12:46:08.066474
4470 12:46:08.066571 ==
4471 12:46:08.068978 Dram Type= 6, Freq= 0, CH_1, rank 0
4472 12:46:08.072326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4473 12:46:08.072421 ==
4474 12:46:08.075759 [Gating] SW mode calibration
4475 12:46:08.082829 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4476 12:46:08.089108 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4477 12:46:08.092501 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4478 12:46:08.095768 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4479 12:46:08.098966 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4480 12:46:08.106183 0 9 12 | B1->B0 | 2f2f 2d2d | 0 0 | (1 1) (0 0)
4481 12:46:08.108962 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4482 12:46:08.112917 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 12:46:08.119553 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 12:46:08.122809 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 12:46:08.125997 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 12:46:08.132418 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 12:46:08.135642 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4488 12:46:08.139095 0 10 12 | B1->B0 | 3737 3c3c | 0 0 | (1 1) (1 1)
4489 12:46:08.145708 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 12:46:08.149069 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 12:46:08.152407 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 12:46:08.158992 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 12:46:08.162030 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 12:46:08.165596 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 12:46:08.172184 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 12:46:08.175464 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4497 12:46:08.179150 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 12:46:08.185829 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 12:46:08.189041 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 12:46:08.192538 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 12:46:08.198881 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 12:46:08.202128 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 12:46:08.205358 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 12:46:08.212423 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 12:46:08.215322 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 12:46:08.218583 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 12:46:08.225195 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 12:46:08.228992 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 12:46:08.232080 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 12:46:08.235353 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 12:46:08.242146 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4512 12:46:08.245438 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4513 12:46:08.248666 Total UI for P1: 0, mck2ui 16
4514 12:46:08.252060 best dqsien dly found for B0: ( 0, 13, 8)
4515 12:46:08.255308 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4516 12:46:08.258615 Total UI for P1: 0, mck2ui 16
4517 12:46:08.262060 best dqsien dly found for B1: ( 0, 13, 12)
4518 12:46:08.265370 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4519 12:46:08.271886 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4520 12:46:08.271990
4521 12:46:08.275366 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4522 12:46:08.278546 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4523 12:46:08.281738 [Gating] SW calibration Done
4524 12:46:08.281834 ==
4525 12:46:08.284926 Dram Type= 6, Freq= 0, CH_1, rank 0
4526 12:46:08.288516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4527 12:46:08.288586 ==
4528 12:46:08.288653 RX Vref Scan: 0
4529 12:46:08.291899
4530 12:46:08.291984 RX Vref 0 -> 0, step: 1
4531 12:46:08.292044
4532 12:46:08.295194 RX Delay -230 -> 252, step: 16
4533 12:46:08.298570 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4534 12:46:08.304874 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4535 12:46:08.308146 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4536 12:46:08.311324 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4537 12:46:08.314749 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4538 12:46:08.318097 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4539 12:46:08.325074 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4540 12:46:08.328020 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4541 12:46:08.331577 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4542 12:46:08.334528 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4543 12:46:08.341581 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4544 12:46:08.344603 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4545 12:46:08.347909 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4546 12:46:08.351440 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4547 12:46:08.354576 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4548 12:46:08.360990 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4549 12:46:08.361062 ==
4550 12:46:08.364324 Dram Type= 6, Freq= 0, CH_1, rank 0
4551 12:46:08.367653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4552 12:46:08.367722 ==
4553 12:46:08.367783 DQS Delay:
4554 12:46:08.370848 DQS0 = 0, DQS1 = 0
4555 12:46:08.370914 DQM Delay:
4556 12:46:08.374763 DQM0 = 52, DQM1 = 49
4557 12:46:08.374843 DQ Delay:
4558 12:46:08.377978 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4559 12:46:08.381212 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4560 12:46:08.384397 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4561 12:46:08.387709 DQ12 =65, DQ13 =57, DQ14 =49, DQ15 =65
4562 12:46:08.387794
4563 12:46:08.387860
4564 12:46:08.387918 ==
4565 12:46:08.391135 Dram Type= 6, Freq= 0, CH_1, rank 0
4566 12:46:08.394542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4567 12:46:08.397971 ==
4568 12:46:08.398051
4569 12:46:08.398113
4570 12:46:08.398171 TX Vref Scan disable
4571 12:46:08.400880 == TX Byte 0 ==
4572 12:46:08.404209 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4573 12:46:08.407696 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4574 12:46:08.411174 == TX Byte 1 ==
4575 12:46:08.414378 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4576 12:46:08.417596 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4577 12:46:08.421162 ==
4578 12:46:08.421237 Dram Type= 6, Freq= 0, CH_1, rank 0
4579 12:46:08.427798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 12:46:08.427869 ==
4581 12:46:08.427929
4582 12:46:08.427985
4583 12:46:08.430930 TX Vref Scan disable
4584 12:46:08.430997 == TX Byte 0 ==
4585 12:46:08.437493 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4586 12:46:08.440843 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4587 12:46:08.440918 == TX Byte 1 ==
4588 12:46:08.447580 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4589 12:46:08.450739 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4590 12:46:08.450837
4591 12:46:08.450930 [DATLAT]
4592 12:46:08.454511 Freq=600, CH1 RK0
4593 12:46:08.454609
4594 12:46:08.454705 DATLAT Default: 0x9
4595 12:46:08.457488 0, 0xFFFF, sum = 0
4596 12:46:08.457561 1, 0xFFFF, sum = 0
4597 12:46:08.460984 2, 0xFFFF, sum = 0
4598 12:46:08.461067 3, 0xFFFF, sum = 0
4599 12:46:08.464138 4, 0xFFFF, sum = 0
4600 12:46:08.464242 5, 0xFFFF, sum = 0
4601 12:46:08.467513 6, 0xFFFF, sum = 0
4602 12:46:08.470589 7, 0xFFFF, sum = 0
4603 12:46:08.470668 8, 0x0, sum = 1
4604 12:46:08.470729 9, 0x0, sum = 2
4605 12:46:08.473992 10, 0x0, sum = 3
4606 12:46:08.474069 11, 0x0, sum = 4
4607 12:46:08.477392 best_step = 9
4608 12:46:08.477506
4609 12:46:08.477683 ==
4610 12:46:08.480638 Dram Type= 6, Freq= 0, CH_1, rank 0
4611 12:46:08.484139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4612 12:46:08.484249 ==
4613 12:46:08.487435 RX Vref Scan: 1
4614 12:46:08.487511
4615 12:46:08.487573 RX Vref 0 -> 0, step: 1
4616 12:46:08.487640
4617 12:46:08.490787 RX Delay -163 -> 252, step: 8
4618 12:46:08.490874
4619 12:46:08.494124 Set Vref, RX VrefLevel [Byte0]: 52
4620 12:46:08.497519 [Byte1]: 52
4621 12:46:08.501457
4622 12:46:08.501529 Final RX Vref Byte 0 = 52 to rank0
4623 12:46:08.504098 Final RX Vref Byte 1 = 52 to rank0
4624 12:46:08.508077 Final RX Vref Byte 0 = 52 to rank1
4625 12:46:08.511248 Final RX Vref Byte 1 = 52 to rank1==
4626 12:46:08.514661 Dram Type= 6, Freq= 0, CH_1, rank 0
4627 12:46:08.520810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4628 12:46:08.520887 ==
4629 12:46:08.520949 DQS Delay:
4630 12:46:08.521007 DQS0 = 0, DQS1 = 0
4631 12:46:08.524451 DQM Delay:
4632 12:46:08.524522 DQM0 = 48, DQM1 = 45
4633 12:46:08.527448 DQ Delay:
4634 12:46:08.530894 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4635 12:46:08.534179 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4636 12:46:08.537479 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4637 12:46:08.540617 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4638 12:46:08.540689
4639 12:46:08.540749
4640 12:46:08.547229 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a6f, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
4641 12:46:08.551126 CH1 RK0: MR19=808, MR18=4A6F
4642 12:46:08.557620 CH1_RK0: MR19=0x808, MR18=0x4A6F, DQSOSC=389, MR23=63, INC=173, DEC=115
4643 12:46:08.557706
4644 12:46:08.560503 ----->DramcWriteLeveling(PI) begin...
4645 12:46:08.560580 ==
4646 12:46:08.563728 Dram Type= 6, Freq= 0, CH_1, rank 1
4647 12:46:08.567165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4648 12:46:08.567246 ==
4649 12:46:08.570510 Write leveling (Byte 0): 30 => 30
4650 12:46:08.574500 Write leveling (Byte 1): 31 => 31
4651 12:46:08.577544 DramcWriteLeveling(PI) end<-----
4652 12:46:08.577620
4653 12:46:08.577683 ==
4654 12:46:08.580842 Dram Type= 6, Freq= 0, CH_1, rank 1
4655 12:46:08.584170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4656 12:46:08.584245 ==
4657 12:46:08.587469 [Gating] SW mode calibration
4658 12:46:08.593759 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4659 12:46:08.600722 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4660 12:46:08.603715 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4661 12:46:08.610677 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4662 12:46:08.613976 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4663 12:46:08.617392 0 9 12 | B1->B0 | 2e2e 2f2f | 1 0 | (1 0) (0 1)
4664 12:46:08.624154 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 12:46:08.627471 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4666 12:46:08.630914 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4667 12:46:08.634169 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4668 12:46:08.640673 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4669 12:46:08.643881 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4670 12:46:08.647056 0 10 8 | B1->B0 | 2424 2424 | 1 0 | (0 0) (0 0)
4671 12:46:08.653609 0 10 12 | B1->B0 | 3939 3535 | 1 0 | (0 0) (0 0)
4672 12:46:08.656934 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 12:46:08.660723 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 12:46:08.666887 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 12:46:08.669954 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 12:46:08.673300 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 12:46:08.680032 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 12:46:08.683262 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 12:46:08.686580 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 12:46:08.693430 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 12:46:08.696785 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 12:46:08.700114 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 12:46:08.706477 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 12:46:08.710002 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 12:46:08.713351 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 12:46:08.720091 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 12:46:08.723376 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 12:46:08.726519 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 12:46:08.733061 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 12:46:08.736481 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 12:46:08.739865 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 12:46:08.746376 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 12:46:08.749619 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 12:46:08.752843 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4695 12:46:08.759685 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4696 12:46:08.763268 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4697 12:46:08.766234 Total UI for P1: 0, mck2ui 16
4698 12:46:08.769305 best dqsien dly found for B0: ( 0, 13, 12)
4699 12:46:08.772927 Total UI for P1: 0, mck2ui 16
4700 12:46:08.776399 best dqsien dly found for B1: ( 0, 13, 10)
4701 12:46:08.779544 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4702 12:46:08.782654 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4703 12:46:08.782727
4704 12:46:08.785856 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4705 12:46:08.789364 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4706 12:46:08.793057 [Gating] SW calibration Done
4707 12:46:08.793133 ==
4708 12:46:08.796130 Dram Type= 6, Freq= 0, CH_1, rank 1
4709 12:46:08.799377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4710 12:46:08.802722 ==
4711 12:46:08.802791 RX Vref Scan: 0
4712 12:46:08.802852
4713 12:46:08.806001 RX Vref 0 -> 0, step: 1
4714 12:46:08.806084
4715 12:46:08.809465 RX Delay -230 -> 252, step: 16
4716 12:46:08.812689 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4717 12:46:08.816078 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4718 12:46:08.819335 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4719 12:46:08.825659 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4720 12:46:08.829404 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4721 12:46:08.832543 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4722 12:46:08.835960 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4723 12:46:08.839463 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4724 12:46:08.846189 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4725 12:46:08.849311 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4726 12:46:08.852634 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4727 12:46:08.855829 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4728 12:46:08.862431 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4729 12:46:08.866366 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4730 12:46:08.869109 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4731 12:46:08.872476 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4732 12:46:08.872561 ==
4733 12:46:08.875744 Dram Type= 6, Freq= 0, CH_1, rank 1
4734 12:46:08.882354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4735 12:46:08.882460 ==
4736 12:46:08.882560 DQS Delay:
4737 12:46:08.885701 DQS0 = 0, DQS1 = 0
4738 12:46:08.885781 DQM Delay:
4739 12:46:08.885845 DQM0 = 50, DQM1 = 48
4740 12:46:08.889324 DQ Delay:
4741 12:46:08.892230 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4742 12:46:08.895974 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4743 12:46:08.899243 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4744 12:46:08.902257 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4745 12:46:08.902338
4746 12:46:08.902401
4747 12:46:08.902459 ==
4748 12:46:08.905451 Dram Type= 6, Freq= 0, CH_1, rank 1
4749 12:46:08.908779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4750 12:46:08.908864 ==
4751 12:46:08.908933
4752 12:46:08.908993
4753 12:46:08.912575 TX Vref Scan disable
4754 12:46:08.912656 == TX Byte 0 ==
4755 12:46:08.918784 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4756 12:46:08.922090 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4757 12:46:08.922195 == TX Byte 1 ==
4758 12:46:08.928898 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4759 12:46:08.932332 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4760 12:46:08.932428 ==
4761 12:46:08.935284 Dram Type= 6, Freq= 0, CH_1, rank 1
4762 12:46:08.939140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4763 12:46:08.939221 ==
4764 12:46:08.939285
4765 12:46:08.941993
4766 12:46:08.942074 TX Vref Scan disable
4767 12:46:08.945817 == TX Byte 0 ==
4768 12:46:08.949013 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4769 12:46:08.955239 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4770 12:46:08.955320 == TX Byte 1 ==
4771 12:46:08.958745 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4772 12:46:08.965435 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4773 12:46:08.965517
4774 12:46:08.965581 [DATLAT]
4775 12:46:08.965640 Freq=600, CH1 RK1
4776 12:46:08.965702
4777 12:46:08.968706 DATLAT Default: 0x9
4778 12:46:08.968773 0, 0xFFFF, sum = 0
4779 12:46:08.972272 1, 0xFFFF, sum = 0
4780 12:46:08.975549 2, 0xFFFF, sum = 0
4781 12:46:08.975687 3, 0xFFFF, sum = 0
4782 12:46:08.978949 4, 0xFFFF, sum = 0
4783 12:46:08.979052 5, 0xFFFF, sum = 0
4784 12:46:08.982386 6, 0xFFFF, sum = 0
4785 12:46:08.982459 7, 0xFFFF, sum = 0
4786 12:46:08.985565 8, 0x0, sum = 1
4787 12:46:08.985661 9, 0x0, sum = 2
4788 12:46:08.985734 10, 0x0, sum = 3
4789 12:46:08.988793 11, 0x0, sum = 4
4790 12:46:08.988863 best_step = 9
4791 12:46:08.988934
4792 12:46:08.988992 ==
4793 12:46:08.992131 Dram Type= 6, Freq= 0, CH_1, rank 1
4794 12:46:08.998823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4795 12:46:08.998934 ==
4796 12:46:08.999024 RX Vref Scan: 0
4797 12:46:08.999119
4798 12:46:09.002075 RX Vref 0 -> 0, step: 1
4799 12:46:09.002143
4800 12:46:09.005347 RX Delay -163 -> 252, step: 8
4801 12:46:09.008474 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4802 12:46:09.015463 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4803 12:46:09.018460 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4804 12:46:09.021613 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4805 12:46:09.025133 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4806 12:46:09.028833 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4807 12:46:09.034938 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4808 12:46:09.038440 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4809 12:46:09.041621 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4810 12:46:09.044872 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4811 12:46:09.048615 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4812 12:46:09.054906 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4813 12:46:09.058175 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4814 12:46:09.061379 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4815 12:46:09.065343 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4816 12:46:09.071296 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4817 12:46:09.071382 ==
4818 12:46:09.075018 Dram Type= 6, Freq= 0, CH_1, rank 1
4819 12:46:09.078036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4820 12:46:09.078144 ==
4821 12:46:09.078232 DQS Delay:
4822 12:46:09.081570 DQS0 = 0, DQS1 = 0
4823 12:46:09.081655 DQM Delay:
4824 12:46:09.084583 DQM0 = 48, DQM1 = 45
4825 12:46:09.084666 DQ Delay:
4826 12:46:09.088199 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4827 12:46:09.091535 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4828 12:46:09.094896 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4829 12:46:09.098116 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4830 12:46:09.098196
4831 12:46:09.098258
4832 12:46:09.104753 [DQSOSCAuto] RK1, (LSB)MR18= 0x671e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4833 12:46:09.108101 CH1 RK1: MR19=808, MR18=671E
4834 12:46:09.114731 CH1_RK1: MR19=0x808, MR18=0x671E, DQSOSC=390, MR23=63, INC=172, DEC=114
4835 12:46:09.117964 [RxdqsGatingPostProcess] freq 600
4836 12:46:09.124403 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4837 12:46:09.127675 Pre-setting of DQS Precalculation
4838 12:46:09.131400 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4839 12:46:09.137923 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4840 12:46:09.144521 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4841 12:46:09.144603
4842 12:46:09.144707
4843 12:46:09.148054 [Calibration Summary] 1200 Mbps
4844 12:46:09.151470 CH 0, Rank 0
4845 12:46:09.151555 SW Impedance : PASS
4846 12:46:09.154718 DUTY Scan : NO K
4847 12:46:09.158215 ZQ Calibration : PASS
4848 12:46:09.158296 Jitter Meter : NO K
4849 12:46:09.161909 CBT Training : PASS
4850 12:46:09.164455 Write leveling : PASS
4851 12:46:09.164545 RX DQS gating : PASS
4852 12:46:09.167848 RX DQ/DQS(RDDQC) : PASS
4853 12:46:09.167958 TX DQ/DQS : PASS
4854 12:46:09.171492 RX DATLAT : PASS
4855 12:46:09.174723 RX DQ/DQS(Engine): PASS
4856 12:46:09.174799 TX OE : NO K
4857 12:46:09.177964 All Pass.
4858 12:46:09.178036
4859 12:46:09.178098 CH 0, Rank 1
4860 12:46:09.181240 SW Impedance : PASS
4861 12:46:09.181314 DUTY Scan : NO K
4862 12:46:09.185085 ZQ Calibration : PASS
4863 12:46:09.187766 Jitter Meter : NO K
4864 12:46:09.187864 CBT Training : PASS
4865 12:46:09.191049 Write leveling : PASS
4866 12:46:09.194702 RX DQS gating : PASS
4867 12:46:09.194776 RX DQ/DQS(RDDQC) : PASS
4868 12:46:09.198461 TX DQ/DQS : PASS
4869 12:46:09.201461 RX DATLAT : PASS
4870 12:46:09.201542 RX DQ/DQS(Engine): PASS
4871 12:46:09.204800 TX OE : NO K
4872 12:46:09.204885 All Pass.
4873 12:46:09.204946
4874 12:46:09.208142 CH 1, Rank 0
4875 12:46:09.208238 SW Impedance : PASS
4876 12:46:09.211397 DUTY Scan : NO K
4877 12:46:09.214602 ZQ Calibration : PASS
4878 12:46:09.214674 Jitter Meter : NO K
4879 12:46:09.217807 CBT Training : PASS
4880 12:46:09.217906 Write leveling : PASS
4881 12:46:09.221004 RX DQS gating : PASS
4882 12:46:09.224243 RX DQ/DQS(RDDQC) : PASS
4883 12:46:09.224353 TX DQ/DQS : PASS
4884 12:46:09.227551 RX DATLAT : PASS
4885 12:46:09.230891 RX DQ/DQS(Engine): PASS
4886 12:46:09.230963 TX OE : NO K
4887 12:46:09.234160 All Pass.
4888 12:46:09.234233
4889 12:46:09.234301 CH 1, Rank 1
4890 12:46:09.237918 SW Impedance : PASS
4891 12:46:09.238023 DUTY Scan : NO K
4892 12:46:09.241270 ZQ Calibration : PASS
4893 12:46:09.244607 Jitter Meter : NO K
4894 12:46:09.244681 CBT Training : PASS
4895 12:46:09.247804 Write leveling : PASS
4896 12:46:09.250967 RX DQS gating : PASS
4897 12:46:09.251042 RX DQ/DQS(RDDQC) : PASS
4898 12:46:09.254103 TX DQ/DQS : PASS
4899 12:46:09.257370 RX DATLAT : PASS
4900 12:46:09.257454 RX DQ/DQS(Engine): PASS
4901 12:46:09.260679 TX OE : NO K
4902 12:46:09.260757 All Pass.
4903 12:46:09.260820
4904 12:46:09.264664 DramC Write-DBI off
4905 12:46:09.267885 PER_BANK_REFRESH: Hybrid Mode
4906 12:46:09.267993 TX_TRACKING: ON
4907 12:46:09.277855 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4908 12:46:09.280745 [FAST_K] Save calibration result to emmc
4909 12:46:09.284403 dramc_set_vcore_voltage set vcore to 662500
4910 12:46:09.287413 Read voltage for 933, 3
4911 12:46:09.287494 Vio18 = 0
4912 12:46:09.287569 Vcore = 662500
4913 12:46:09.290427 Vdram = 0
4914 12:46:09.290501 Vddq = 0
4915 12:46:09.290562 Vmddr = 0
4916 12:46:09.297282 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4917 12:46:09.300609 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4918 12:46:09.304113 MEM_TYPE=3, freq_sel=17
4919 12:46:09.307389 sv_algorithm_assistance_LP4_1600
4920 12:46:09.310918 ============ PULL DRAM RESETB DOWN ============
4921 12:46:09.313946 ========== PULL DRAM RESETB DOWN end =========
4922 12:46:09.320694 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4923 12:46:09.324044 ===================================
4924 12:46:09.324126 LPDDR4 DRAM CONFIGURATION
4925 12:46:09.327126 ===================================
4926 12:46:09.330440 EX_ROW_EN[0] = 0x0
4927 12:46:09.334473 EX_ROW_EN[1] = 0x0
4928 12:46:09.334553 LP4Y_EN = 0x0
4929 12:46:09.337665 WORK_FSP = 0x0
4930 12:46:09.337746 WL = 0x3
4931 12:46:09.340927 RL = 0x3
4932 12:46:09.341008 BL = 0x2
4933 12:46:09.344027 RPST = 0x0
4934 12:46:09.344116 RD_PRE = 0x0
4935 12:46:09.347366 WR_PRE = 0x1
4936 12:46:09.347447 WR_PST = 0x0
4937 12:46:09.350584 DBI_WR = 0x0
4938 12:46:09.350664 DBI_RD = 0x0
4939 12:46:09.353830 OTF = 0x1
4940 12:46:09.357065 ===================================
4941 12:46:09.360441 ===================================
4942 12:46:09.360523 ANA top config
4943 12:46:09.364229 ===================================
4944 12:46:09.367593 DLL_ASYNC_EN = 0
4945 12:46:09.370918 ALL_SLAVE_EN = 1
4946 12:46:09.370999 NEW_RANK_MODE = 1
4947 12:46:09.374226 DLL_IDLE_MODE = 1
4948 12:46:09.377500 LP45_APHY_COMB_EN = 1
4949 12:46:09.380812 TX_ODT_DIS = 1
4950 12:46:09.384162 NEW_8X_MODE = 1
4951 12:46:09.386915 ===================================
4952 12:46:09.390307 ===================================
4953 12:46:09.394085 data_rate = 1866
4954 12:46:09.394166 CKR = 1
4955 12:46:09.397352 DQ_P2S_RATIO = 8
4956 12:46:09.400695 ===================================
4957 12:46:09.403483 CA_P2S_RATIO = 8
4958 12:46:09.406932 DQ_CA_OPEN = 0
4959 12:46:09.409998 DQ_SEMI_OPEN = 0
4960 12:46:09.413311 CA_SEMI_OPEN = 0
4961 12:46:09.413382 CA_FULL_RATE = 0
4962 12:46:09.417034 DQ_CKDIV4_EN = 1
4963 12:46:09.420377 CA_CKDIV4_EN = 1
4964 12:46:09.423566 CA_PREDIV_EN = 0
4965 12:46:09.426542 PH8_DLY = 0
4966 12:46:09.426618 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4967 12:46:09.430345 DQ_AAMCK_DIV = 4
4968 12:46:09.433406 CA_AAMCK_DIV = 4
4969 12:46:09.436596 CA_ADMCK_DIV = 4
4970 12:46:09.439807 DQ_TRACK_CA_EN = 0
4971 12:46:09.443464 CA_PICK = 933
4972 12:46:09.446911 CA_MCKIO = 933
4973 12:46:09.446987 MCKIO_SEMI = 0
4974 12:46:09.450189 PLL_FREQ = 3732
4975 12:46:09.453528 DQ_UI_PI_RATIO = 32
4976 12:46:09.456695 CA_UI_PI_RATIO = 0
4977 12:46:09.460032 ===================================
4978 12:46:09.463396 ===================================
4979 12:46:09.466586 memory_type:LPDDR4
4980 12:46:09.466718 GP_NUM : 10
4981 12:46:09.469790 SRAM_EN : 1
4982 12:46:09.473095 MD32_EN : 0
4983 12:46:09.476447 ===================================
4984 12:46:09.476558 [ANA_INIT] >>>>>>>>>>>>>>
4985 12:46:09.479662 <<<<<< [CONFIGURE PHASE]: ANA_TX
4986 12:46:09.482907 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4987 12:46:09.486868 ===================================
4988 12:46:09.489643 data_rate = 1866,PCW = 0X8f00
4989 12:46:09.493031 ===================================
4990 12:46:09.496346 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4991 12:46:09.503556 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4992 12:46:09.506697 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4993 12:46:09.513355 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4994 12:46:09.516723 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4995 12:46:09.520033 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4996 12:46:09.520130 [ANA_INIT] flow start
4997 12:46:09.523129 [ANA_INIT] PLL >>>>>>>>
4998 12:46:09.526743 [ANA_INIT] PLL <<<<<<<<
4999 12:46:09.526836 [ANA_INIT] MIDPI >>>>>>>>
5000 12:46:09.530134 [ANA_INIT] MIDPI <<<<<<<<
5001 12:46:09.533110 [ANA_INIT] DLL >>>>>>>>
5002 12:46:09.533192 [ANA_INIT] flow end
5003 12:46:09.539697 ============ LP4 DIFF to SE enter ============
5004 12:46:09.543050 ============ LP4 DIFF to SE exit ============
5005 12:46:09.546234 [ANA_INIT] <<<<<<<<<<<<<
5006 12:46:09.550132 [Flow] Enable top DCM control >>>>>
5007 12:46:09.553291 [Flow] Enable top DCM control <<<<<
5008 12:46:09.553363 Enable DLL master slave shuffle
5009 12:46:09.559493 ==============================================================
5010 12:46:09.563106 Gating Mode config
5011 12:46:09.566158 ==============================================================
5012 12:46:09.569526 Config description:
5013 12:46:09.579896 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5014 12:46:09.586807 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5015 12:46:09.590141 SELPH_MODE 0: By rank 1: By Phase
5016 12:46:09.596834 ==============================================================
5017 12:46:09.600016 GAT_TRACK_EN = 1
5018 12:46:09.603356 RX_GATING_MODE = 2
5019 12:46:09.606668 RX_GATING_TRACK_MODE = 2
5020 12:46:09.606747 SELPH_MODE = 1
5021 12:46:09.609768 PICG_EARLY_EN = 1
5022 12:46:09.613011 VALID_LAT_VALUE = 1
5023 12:46:09.619560 ==============================================================
5024 12:46:09.622909 Enter into Gating configuration >>>>
5025 12:46:09.626237 Exit from Gating configuration <<<<
5026 12:46:09.629489 Enter into DVFS_PRE_config >>>>>
5027 12:46:09.639662 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5028 12:46:09.643118 Exit from DVFS_PRE_config <<<<<
5029 12:46:09.646167 Enter into PICG configuration >>>>
5030 12:46:09.649769 Exit from PICG configuration <<<<
5031 12:46:09.652966 [RX_INPUT] configuration >>>>>
5032 12:46:09.656427 [RX_INPUT] configuration <<<<<
5033 12:46:09.659600 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5034 12:46:09.666234 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5035 12:46:09.672939 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5036 12:46:09.679518 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5037 12:46:09.683001 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5038 12:46:09.689739 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5039 12:46:09.692870 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5040 12:46:09.699758 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5041 12:46:09.703020 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5042 12:46:09.706180 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5043 12:46:09.709788 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5044 12:46:09.716727 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5045 12:46:09.720051 ===================================
5046 12:46:09.720133 LPDDR4 DRAM CONFIGURATION
5047 12:46:09.723486 ===================================
5048 12:46:09.726147 EX_ROW_EN[0] = 0x0
5049 12:46:09.730258 EX_ROW_EN[1] = 0x0
5050 12:46:09.730352 LP4Y_EN = 0x0
5051 12:46:09.732943 WORK_FSP = 0x0
5052 12:46:09.733045 WL = 0x3
5053 12:46:09.736332 RL = 0x3
5054 12:46:09.736446 BL = 0x2
5055 12:46:09.739977 RPST = 0x0
5056 12:46:09.740087 RD_PRE = 0x0
5057 12:46:09.742954 WR_PRE = 0x1
5058 12:46:09.743074 WR_PST = 0x0
5059 12:46:09.746327 DBI_WR = 0x0
5060 12:46:09.746462 DBI_RD = 0x0
5061 12:46:09.749682 OTF = 0x1
5062 12:46:09.753141 ===================================
5063 12:46:09.756831 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5064 12:46:09.759608 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5065 12:46:09.766708 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5066 12:46:09.770117 ===================================
5067 12:46:09.770189 LPDDR4 DRAM CONFIGURATION
5068 12:46:09.773261 ===================================
5069 12:46:09.776510 EX_ROW_EN[0] = 0x10
5070 12:46:09.776582 EX_ROW_EN[1] = 0x0
5071 12:46:09.779753 LP4Y_EN = 0x0
5072 12:46:09.783099 WORK_FSP = 0x0
5073 12:46:09.783177 WL = 0x3
5074 12:46:09.786205 RL = 0x3
5075 12:46:09.786276 BL = 0x2
5076 12:46:09.789984 RPST = 0x0
5077 12:46:09.790071 RD_PRE = 0x0
5078 12:46:09.792972 WR_PRE = 0x1
5079 12:46:09.793045 WR_PST = 0x0
5080 12:46:09.796195 DBI_WR = 0x0
5081 12:46:09.796282 DBI_RD = 0x0
5082 12:46:09.799363 OTF = 0x1
5083 12:46:09.803276 ===================================
5084 12:46:09.809414 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5085 12:46:09.812973 nWR fixed to 30
5086 12:46:09.813045 [ModeRegInit_LP4] CH0 RK0
5087 12:46:09.816061 [ModeRegInit_LP4] CH0 RK1
5088 12:46:09.819384 [ModeRegInit_LP4] CH1 RK0
5089 12:46:09.819454 [ModeRegInit_LP4] CH1 RK1
5090 12:46:09.822764 match AC timing 9
5091 12:46:09.826369 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5092 12:46:09.829281 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5093 12:46:09.836111 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5094 12:46:09.839395 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5095 12:46:09.845911 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5096 12:46:09.846019 ==
5097 12:46:09.849045 Dram Type= 6, Freq= 0, CH_0, rank 0
5098 12:46:09.852791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5099 12:46:09.852877 ==
5100 12:46:09.859375 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5101 12:46:09.862505 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5102 12:46:09.867127 [CA 0] Center 37 (6~68) winsize 63
5103 12:46:09.870457 [CA 1] Center 37 (6~68) winsize 63
5104 12:46:09.873562 [CA 2] Center 34 (4~65) winsize 62
5105 12:46:09.876863 [CA 3] Center 33 (3~64) winsize 62
5106 12:46:09.880167 [CA 4] Center 33 (3~64) winsize 62
5107 12:46:09.883539 [CA 5] Center 32 (2~62) winsize 61
5108 12:46:09.883613
5109 12:46:09.886859 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5110 12:46:09.886930
5111 12:46:09.890164 [CATrainingPosCal] consider 1 rank data
5112 12:46:09.893500 u2DelayCellTimex100 = 270/100 ps
5113 12:46:09.896643 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5114 12:46:09.903476 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5115 12:46:09.906616 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5116 12:46:09.910419 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5117 12:46:09.913737 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5118 12:46:09.916935 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5119 12:46:09.917020
5120 12:46:09.920417 CA PerBit enable=1, Macro0, CA PI delay=32
5121 12:46:09.920499
5122 12:46:09.923638 [CBTSetCACLKResult] CA Dly = 32
5123 12:46:09.923720 CS Dly: 5 (0~36)
5124 12:46:09.926758 ==
5125 12:46:09.929877 Dram Type= 6, Freq= 0, CH_0, rank 1
5126 12:46:09.933187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5127 12:46:09.933271 ==
5128 12:46:09.936645 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5129 12:46:09.943208 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5130 12:46:09.947534 [CA 0] Center 37 (6~68) winsize 63
5131 12:46:09.950721 [CA 1] Center 37 (6~68) winsize 63
5132 12:46:09.953701 [CA 2] Center 34 (4~65) winsize 62
5133 12:46:09.957210 [CA 3] Center 34 (3~65) winsize 63
5134 12:46:09.960187 [CA 4] Center 33 (3~63) winsize 61
5135 12:46:09.963903 [CA 5] Center 32 (2~62) winsize 61
5136 12:46:09.963984
5137 12:46:09.967346 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5138 12:46:09.967427
5139 12:46:09.970459 [CATrainingPosCal] consider 2 rank data
5140 12:46:09.973699 u2DelayCellTimex100 = 270/100 ps
5141 12:46:09.976817 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5142 12:46:09.980465 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5143 12:46:09.987324 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5144 12:46:09.990607 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5145 12:46:09.993972 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5146 12:46:09.997447 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5147 12:46:09.997527
5148 12:46:10.000480 CA PerBit enable=1, Macro0, CA PI delay=32
5149 12:46:10.000560
5150 12:46:10.003583 [CBTSetCACLKResult] CA Dly = 32
5151 12:46:10.003664 CS Dly: 6 (0~38)
5152 12:46:10.003728
5153 12:46:10.006820 ----->DramcWriteLeveling(PI) begin...
5154 12:46:10.010590 ==
5155 12:46:10.013662 Dram Type= 6, Freq= 0, CH_0, rank 0
5156 12:46:10.016871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5157 12:46:10.016958 ==
5158 12:46:10.020136 Write leveling (Byte 0): 32 => 32
5159 12:46:10.023505 Write leveling (Byte 1): 30 => 30
5160 12:46:10.026828 DramcWriteLeveling(PI) end<-----
5161 12:46:10.026908
5162 12:46:10.026972 ==
5163 12:46:10.030095 Dram Type= 6, Freq= 0, CH_0, rank 0
5164 12:46:10.033432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5165 12:46:10.033513 ==
5166 12:46:10.037232 [Gating] SW mode calibration
5167 12:46:10.043815 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5168 12:46:10.050505 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5169 12:46:10.053747 0 14 0 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
5170 12:46:10.057343 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 12:46:10.059990 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5172 12:46:10.066613 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5173 12:46:10.069804 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5174 12:46:10.073954 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5175 12:46:10.079855 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
5176 12:46:10.083521 0 14 28 | B1->B0 | 3333 2424 | 1 0 | (1 0) (0 0)
5177 12:46:10.086806 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (0 0) (0 0)
5178 12:46:10.093162 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 12:46:10.096813 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 12:46:10.100235 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5181 12:46:10.106493 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5182 12:46:10.110159 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5183 12:46:10.113286 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5184 12:46:10.119782 0 15 28 | B1->B0 | 2727 4040 | 0 0 | (0 0) (0 0)
5185 12:46:10.123396 1 0 0 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
5186 12:46:10.126653 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 12:46:10.133241 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 12:46:10.136518 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 12:46:10.139726 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 12:46:10.146073 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 12:46:10.149347 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 12:46:10.152736 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5193 12:46:10.159454 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 12:46:10.162687 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 12:46:10.166033 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 12:46:10.173270 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 12:46:10.176276 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 12:46:10.179638 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 12:46:10.186173 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 12:46:10.189636 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 12:46:10.192645 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 12:46:10.199122 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 12:46:10.202842 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 12:46:10.206069 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 12:46:10.209458 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 12:46:10.216788 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 12:46:10.219505 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5208 12:46:10.223098 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5209 12:46:10.226325 Total UI for P1: 0, mck2ui 16
5210 12:46:10.229467 best dqsien dly found for B0: ( 1, 2, 24)
5211 12:46:10.236142 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5212 12:46:10.239292 Total UI for P1: 0, mck2ui 16
5213 12:46:10.242602 best dqsien dly found for B1: ( 1, 2, 28)
5214 12:46:10.245907 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5215 12:46:10.249219 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5216 12:46:10.249300
5217 12:46:10.252467 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5218 12:46:10.256242 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5219 12:46:10.259491 [Gating] SW calibration Done
5220 12:46:10.259567 ==
5221 12:46:10.262774 Dram Type= 6, Freq= 0, CH_0, rank 0
5222 12:46:10.266102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5223 12:46:10.266173 ==
5224 12:46:10.269328 RX Vref Scan: 0
5225 12:46:10.269396
5226 12:46:10.269456 RX Vref 0 -> 0, step: 1
5227 12:46:10.272657
5228 12:46:10.272723 RX Delay -80 -> 252, step: 8
5229 12:46:10.279067 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5230 12:46:10.282413 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5231 12:46:10.285581 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5232 12:46:10.288975 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5233 12:46:10.292166 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5234 12:46:10.295413 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5235 12:46:10.302661 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5236 12:46:10.305870 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5237 12:46:10.308937 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5238 12:46:10.311876 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5239 12:46:10.315202 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5240 12:46:10.319079 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5241 12:46:10.325366 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5242 12:46:10.328603 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5243 12:46:10.332438 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5244 12:46:10.335524 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5245 12:46:10.335604 ==
5246 12:46:10.339062 Dram Type= 6, Freq= 0, CH_0, rank 0
5247 12:46:10.345534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5248 12:46:10.345618 ==
5249 12:46:10.345683 DQS Delay:
5250 12:46:10.345742 DQS0 = 0, DQS1 = 0
5251 12:46:10.348543 DQM Delay:
5252 12:46:10.348613 DQM0 = 104, DQM1 = 95
5253 12:46:10.351881 DQ Delay:
5254 12:46:10.355469 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5255 12:46:10.358546 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =115
5256 12:46:10.362318 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =91
5257 12:46:10.365112 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5258 12:46:10.365225
5259 12:46:10.365316
5260 12:46:10.365381 ==
5261 12:46:10.368549 Dram Type= 6, Freq= 0, CH_0, rank 0
5262 12:46:10.372092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5263 12:46:10.372616 ==
5264 12:46:10.372954
5265 12:46:10.373260
5266 12:46:10.375392 TX Vref Scan disable
5267 12:46:10.378829 == TX Byte 0 ==
5268 12:46:10.381984 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5269 12:46:10.385416 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5270 12:46:10.388751 == TX Byte 1 ==
5271 12:46:10.392137 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5272 12:46:10.395586 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5273 12:46:10.396003 ==
5274 12:46:10.398970 Dram Type= 6, Freq= 0, CH_0, rank 0
5275 12:46:10.402332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5276 12:46:10.405515 ==
5277 12:46:10.405925
5278 12:46:10.406247
5279 12:46:10.406545 TX Vref Scan disable
5280 12:46:10.409609 == TX Byte 0 ==
5281 12:46:10.412954 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5282 12:46:10.419598 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5283 12:46:10.420107 == TX Byte 1 ==
5284 12:46:10.422415 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5285 12:46:10.428986 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5286 12:46:10.429414
5287 12:46:10.429738 [DATLAT]
5288 12:46:10.430039 Freq=933, CH0 RK0
5289 12:46:10.430334
5290 12:46:10.432789 DATLAT Default: 0xd
5291 12:46:10.433270 0, 0xFFFF, sum = 0
5292 12:46:10.435932 1, 0xFFFF, sum = 0
5293 12:46:10.436384 2, 0xFFFF, sum = 0
5294 12:46:10.438984 3, 0xFFFF, sum = 0
5295 12:46:10.442405 4, 0xFFFF, sum = 0
5296 12:46:10.442851 5, 0xFFFF, sum = 0
5297 12:46:10.445964 6, 0xFFFF, sum = 0
5298 12:46:10.446384 7, 0xFFFF, sum = 0
5299 12:46:10.449611 8, 0xFFFF, sum = 0
5300 12:46:10.450033 9, 0xFFFF, sum = 0
5301 12:46:10.452754 10, 0x0, sum = 1
5302 12:46:10.453176 11, 0x0, sum = 2
5303 12:46:10.453508 12, 0x0, sum = 3
5304 12:46:10.455908 13, 0x0, sum = 4
5305 12:46:10.456370 best_step = 11
5306 12:46:10.456708
5307 12:46:10.458834 ==
5308 12:46:10.459272 Dram Type= 6, Freq= 0, CH_0, rank 0
5309 12:46:10.465723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5310 12:46:10.466145 ==
5311 12:46:10.466473 RX Vref Scan: 1
5312 12:46:10.466781
5313 12:46:10.469357 RX Vref 0 -> 0, step: 1
5314 12:46:10.469788
5315 12:46:10.472206 RX Delay -53 -> 252, step: 4
5316 12:46:10.472653
5317 12:46:10.475572 Set Vref, RX VrefLevel [Byte0]: 58
5318 12:46:10.479018 [Byte1]: 53
5319 12:46:10.479430
5320 12:46:10.482417 Final RX Vref Byte 0 = 58 to rank0
5321 12:46:10.486242 Final RX Vref Byte 1 = 53 to rank0
5322 12:46:10.488965 Final RX Vref Byte 0 = 58 to rank1
5323 12:46:10.492324 Final RX Vref Byte 1 = 53 to rank1==
5324 12:46:10.495963 Dram Type= 6, Freq= 0, CH_0, rank 0
5325 12:46:10.498912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5326 12:46:10.499364 ==
5327 12:46:10.502226 DQS Delay:
5328 12:46:10.502611 DQS0 = 0, DQS1 = 0
5329 12:46:10.505487 DQM Delay:
5330 12:46:10.505920 DQM0 = 105, DQM1 = 97
5331 12:46:10.506245 DQ Delay:
5332 12:46:10.512211 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5333 12:46:10.515526 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =110
5334 12:46:10.518852 DQ8 =86, DQ9 =88, DQ10 =96, DQ11 =92
5335 12:46:10.522156 DQ12 =102, DQ13 =102, DQ14 =106, DQ15 =104
5336 12:46:10.522566
5337 12:46:10.522890
5338 12:46:10.528786 [DQSOSCAuto] RK0, (LSB)MR18= 0x342c, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 405 ps
5339 12:46:10.531982 CH0 RK0: MR19=505, MR18=342C
5340 12:46:10.538669 CH0_RK0: MR19=0x505, MR18=0x342C, DQSOSC=405, MR23=63, INC=66, DEC=44
5341 12:46:10.539219
5342 12:46:10.542426 ----->DramcWriteLeveling(PI) begin...
5343 12:46:10.542988 ==
5344 12:46:10.545662 Dram Type= 6, Freq= 0, CH_0, rank 1
5345 12:46:10.548809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5346 12:46:10.549265 ==
5347 12:46:10.552169 Write leveling (Byte 0): 32 => 32
5348 12:46:10.555771 Write leveling (Byte 1): 30 => 30
5349 12:46:10.558892 DramcWriteLeveling(PI) end<-----
5350 12:46:10.559495
5351 12:46:10.560025 ==
5352 12:46:10.562152 Dram Type= 6, Freq= 0, CH_0, rank 1
5353 12:46:10.565448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5354 12:46:10.565941 ==
5355 12:46:10.568431 [Gating] SW mode calibration
5356 12:46:10.575547 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5357 12:46:10.582130 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5358 12:46:10.585153 0 14 0 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
5359 12:46:10.591594 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 12:46:10.594972 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 12:46:10.598851 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 12:46:10.605510 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 12:46:10.608253 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 12:46:10.611791 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5365 12:46:10.618527 0 14 28 | B1->B0 | 2828 2929 | 1 0 | (1 1) (0 0)
5366 12:46:10.621885 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5367 12:46:10.625175 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 12:46:10.631831 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 12:46:10.635102 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 12:46:10.638510 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 12:46:10.642166 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 12:46:10.648094 0 15 24 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
5373 12:46:10.652280 0 15 28 | B1->B0 | 3b3b 3333 | 0 0 | (0 0) (0 0)
5374 12:46:10.655539 1 0 0 | B1->B0 | 4646 4342 | 0 1 | (0 0) (0 0)
5375 12:46:10.662235 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 12:46:10.664655 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 12:46:10.668396 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 12:46:10.675108 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 12:46:10.677941 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 12:46:10.681311 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 12:46:10.688570 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5382 12:46:10.691657 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5383 12:46:10.694869 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 12:46:10.701047 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 12:46:10.704369 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 12:46:10.707630 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 12:46:10.714085 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 12:46:10.717407 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 12:46:10.721061 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 12:46:10.727591 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 12:46:10.731083 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 12:46:10.734308 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 12:46:10.740690 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 12:46:10.744443 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 12:46:10.747591 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 12:46:10.754095 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5397 12:46:10.757189 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5398 12:46:10.761162 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5399 12:46:10.763787 Total UI for P1: 0, mck2ui 16
5400 12:46:10.767812 best dqsien dly found for B1: ( 1, 2, 30)
5401 12:46:10.773710 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5402 12:46:10.774121 Total UI for P1: 0, mck2ui 16
5403 12:46:10.780851 best dqsien dly found for B0: ( 1, 2, 28)
5404 12:46:10.784264 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5405 12:46:10.787150 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5406 12:46:10.787733
5407 12:46:10.790289 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5408 12:46:10.793798 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5409 12:46:10.797447 [Gating] SW calibration Done
5410 12:46:10.797894 ==
5411 12:46:10.800786 Dram Type= 6, Freq= 0, CH_0, rank 1
5412 12:46:10.804109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5413 12:46:10.804678 ==
5414 12:46:10.807366 RX Vref Scan: 0
5415 12:46:10.807882
5416 12:46:10.808414 RX Vref 0 -> 0, step: 1
5417 12:46:10.808824
5418 12:46:10.810307 RX Delay -80 -> 252, step: 8
5419 12:46:10.813708 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5420 12:46:10.820559 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5421 12:46:10.823779 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5422 12:46:10.827727 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5423 12:46:10.831029 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5424 12:46:10.833858 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5425 12:46:10.836957 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5426 12:46:10.843838 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5427 12:46:10.847106 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5428 12:46:10.850360 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5429 12:46:10.853618 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5430 12:46:10.856781 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5431 12:46:10.860170 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5432 12:46:10.866551 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5433 12:46:10.869917 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5434 12:46:10.873539 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5435 12:46:10.873620 ==
5436 12:46:10.876775 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 12:46:10.880159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 12:46:10.880261 ==
5439 12:46:10.883291 DQS Delay:
5440 12:46:10.883399 DQS0 = 0, DQS1 = 0
5441 12:46:10.886632 DQM Delay:
5442 12:46:10.886740 DQM0 = 105, DQM1 = 93
5443 12:46:10.886835 DQ Delay:
5444 12:46:10.893499 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =103
5445 12:46:10.896760 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =115
5446 12:46:10.899972 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =87
5447 12:46:10.903444 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5448 12:46:10.903525
5449 12:46:10.903588
5450 12:46:10.903648 ==
5451 12:46:10.906453 Dram Type= 6, Freq= 0, CH_0, rank 1
5452 12:46:10.910181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5453 12:46:10.910263 ==
5454 12:46:10.910326
5455 12:46:10.910387
5456 12:46:10.913132 TX Vref Scan disable
5457 12:46:10.913277 == TX Byte 0 ==
5458 12:46:10.920207 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5459 12:46:10.923658 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5460 12:46:10.923740 == TX Byte 1 ==
5461 12:46:10.930151 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5462 12:46:10.933492 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5463 12:46:10.933573 ==
5464 12:46:10.936637 Dram Type= 6, Freq= 0, CH_0, rank 1
5465 12:46:10.939704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5466 12:46:10.939785 ==
5467 12:46:10.939848
5468 12:46:10.939906
5469 12:46:10.943089 TX Vref Scan disable
5470 12:46:10.947015 == TX Byte 0 ==
5471 12:46:10.950233 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5472 12:46:10.953464 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5473 12:46:10.956421 == TX Byte 1 ==
5474 12:46:10.960070 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5475 12:46:10.963121 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5476 12:46:10.963201
5477 12:46:10.966678 [DATLAT]
5478 12:46:10.966758 Freq=933, CH0 RK1
5479 12:46:10.966821
5480 12:46:10.969610 DATLAT Default: 0xb
5481 12:46:10.969690 0, 0xFFFF, sum = 0
5482 12:46:10.973192 1, 0xFFFF, sum = 0
5483 12:46:10.973273 2, 0xFFFF, sum = 0
5484 12:46:10.976954 3, 0xFFFF, sum = 0
5485 12:46:10.977043 4, 0xFFFF, sum = 0
5486 12:46:10.980152 5, 0xFFFF, sum = 0
5487 12:46:10.980233 6, 0xFFFF, sum = 0
5488 12:46:10.983590 7, 0xFFFF, sum = 0
5489 12:46:10.983672 8, 0xFFFF, sum = 0
5490 12:46:10.986757 9, 0xFFFF, sum = 0
5491 12:46:10.986839 10, 0x0, sum = 1
5492 12:46:10.989994 11, 0x0, sum = 2
5493 12:46:10.990092 12, 0x0, sum = 3
5494 12:46:10.993475 13, 0x0, sum = 4
5495 12:46:10.993560 best_step = 11
5496 12:46:10.993622
5497 12:46:10.993716 ==
5498 12:46:10.996886 Dram Type= 6, Freq= 0, CH_0, rank 1
5499 12:46:11.003368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5500 12:46:11.003449 ==
5501 12:46:11.003513 RX Vref Scan: 0
5502 12:46:11.003572
5503 12:46:11.006603 RX Vref 0 -> 0, step: 1
5504 12:46:11.006683
5505 12:46:11.009809 RX Delay -53 -> 252, step: 4
5506 12:46:11.013109 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5507 12:46:11.019587 iDelay=199, Bit 1, Center 104 (19 ~ 190) 172
5508 12:46:11.023163 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5509 12:46:11.026322 iDelay=199, Bit 3, Center 100 (11 ~ 190) 180
5510 12:46:11.029409 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5511 12:46:11.032634 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5512 12:46:11.035998 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5513 12:46:11.042969 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5514 12:46:11.045995 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5515 12:46:11.049625 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5516 12:46:11.052606 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5517 12:46:11.056403 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5518 12:46:11.063165 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5519 12:46:11.066558 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5520 12:46:11.069743 iDelay=199, Bit 14, Center 106 (23 ~ 190) 168
5521 12:46:11.072476 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5522 12:46:11.072565 ==
5523 12:46:11.076152 Dram Type= 6, Freq= 0, CH_0, rank 1
5524 12:46:11.079190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5525 12:46:11.083126 ==
5526 12:46:11.083235 DQS Delay:
5527 12:46:11.083302 DQS0 = 0, DQS1 = 0
5528 12:46:11.086086 DQM Delay:
5529 12:46:11.086188 DQM0 = 104, DQM1 = 95
5530 12:46:11.089413 DQ Delay:
5531 12:46:11.092545 DQ0 =102, DQ1 =104, DQ2 =102, DQ3 =100
5532 12:46:11.095972 DQ4 =106, DQ5 =98, DQ6 =112, DQ7 =112
5533 12:46:11.099135 DQ8 =86, DQ9 =86, DQ10 =94, DQ11 =88
5534 12:46:11.102612 DQ12 =100, DQ13 =98, DQ14 =106, DQ15 =102
5535 12:46:11.102723
5536 12:46:11.102817
5537 12:46:11.109456 [DQSOSCAuto] RK1, (LSB)MR18= 0x2902, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5538 12:46:11.112714 CH0 RK1: MR19=505, MR18=2902
5539 12:46:11.119465 CH0_RK1: MR19=0x505, MR18=0x2902, DQSOSC=408, MR23=63, INC=65, DEC=43
5540 12:46:11.122723 [RxdqsGatingPostProcess] freq 933
5541 12:46:11.125889 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5542 12:46:11.129088 best DQS0 dly(2T, 0.5T) = (0, 10)
5543 12:46:11.132844 best DQS1 dly(2T, 0.5T) = (0, 10)
5544 12:46:11.136397 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5545 12:46:11.139452 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5546 12:46:11.142789 best DQS0 dly(2T, 0.5T) = (0, 10)
5547 12:46:11.146089 best DQS1 dly(2T, 0.5T) = (0, 10)
5548 12:46:11.149233 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5549 12:46:11.152566 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5550 12:46:11.156051 Pre-setting of DQS Precalculation
5551 12:46:11.159686 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5552 12:46:11.159773 ==
5553 12:46:11.163033 Dram Type= 6, Freq= 0, CH_1, rank 0
5554 12:46:11.169330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5555 12:46:11.169432 ==
5556 12:46:11.172710 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5557 12:46:11.179333 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5558 12:46:11.182724 [CA 0] Center 36 (6~67) winsize 62
5559 12:46:11.186081 [CA 1] Center 37 (6~68) winsize 63
5560 12:46:11.189348 [CA 2] Center 34 (4~65) winsize 62
5561 12:46:11.192630 [CA 3] Center 34 (4~65) winsize 62
5562 12:46:11.195983 [CA 4] Center 34 (4~65) winsize 62
5563 12:46:11.199138 [CA 5] Center 33 (3~64) winsize 62
5564 12:46:11.199217
5565 12:46:11.202550 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5566 12:46:11.202631
5567 12:46:11.206011 [CATrainingPosCal] consider 1 rank data
5568 12:46:11.209301 u2DelayCellTimex100 = 270/100 ps
5569 12:46:11.212315 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5570 12:46:11.219236 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5571 12:46:11.222159 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5572 12:46:11.225484 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5573 12:46:11.228627 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5574 12:46:11.231894 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5575 12:46:11.231974
5576 12:46:11.235230 CA PerBit enable=1, Macro0, CA PI delay=33
5577 12:46:11.235311
5578 12:46:11.238631 [CBTSetCACLKResult] CA Dly = 33
5579 12:46:11.241858 CS Dly: 7 (0~38)
5580 12:46:11.241939 ==
5581 12:46:11.245505 Dram Type= 6, Freq= 0, CH_1, rank 1
5582 12:46:11.248543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5583 12:46:11.248624 ==
5584 12:46:11.255061 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5585 12:46:11.258441 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5586 12:46:11.262497 [CA 0] Center 36 (6~67) winsize 62
5587 12:46:11.265738 [CA 1] Center 37 (6~68) winsize 63
5588 12:46:11.269044 [CA 2] Center 35 (4~66) winsize 63
5589 12:46:11.272866 [CA 3] Center 34 (4~65) winsize 62
5590 12:46:11.276006 [CA 4] Center 34 (4~65) winsize 62
5591 12:46:11.279413 [CA 5] Center 34 (4~64) winsize 61
5592 12:46:11.279497
5593 12:46:11.282406 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5594 12:46:11.282511
5595 12:46:11.286128 [CATrainingPosCal] consider 2 rank data
5596 12:46:11.289275 u2DelayCellTimex100 = 270/100 ps
5597 12:46:11.292589 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5598 12:46:11.299217 CA1 delay=37 (6~68),Diff = 3 PI (18 cell)
5599 12:46:11.302540 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
5600 12:46:11.306030 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5601 12:46:11.309218 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5602 12:46:11.312546 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5603 12:46:11.312627
5604 12:46:11.315870 CA PerBit enable=1, Macro0, CA PI delay=34
5605 12:46:11.315951
5606 12:46:11.319063 [CBTSetCACLKResult] CA Dly = 34
5607 12:46:11.319143 CS Dly: 8 (0~40)
5608 12:46:11.322256
5609 12:46:11.325639 ----->DramcWriteLeveling(PI) begin...
5610 12:46:11.325721 ==
5611 12:46:11.328696 Dram Type= 6, Freq= 0, CH_1, rank 0
5612 12:46:11.332094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5613 12:46:11.332175 ==
5614 12:46:11.335352 Write leveling (Byte 0): 26 => 26
5615 12:46:11.338927 Write leveling (Byte 1): 26 => 26
5616 12:46:11.341892 DramcWriteLeveling(PI) end<-----
5617 12:46:11.342033
5618 12:46:11.342116 ==
5619 12:46:11.345846 Dram Type= 6, Freq= 0, CH_1, rank 0
5620 12:46:11.348873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5621 12:46:11.348955 ==
5622 12:46:11.352056 [Gating] SW mode calibration
5623 12:46:11.358845 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5624 12:46:11.365355 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5625 12:46:11.369044 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 12:46:11.372439 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 12:46:11.378908 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 12:46:11.382206 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5629 12:46:11.385462 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5630 12:46:11.391965 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5631 12:46:11.395512 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
5632 12:46:11.398865 0 14 28 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
5633 12:46:11.405318 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 12:46:11.408683 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5635 12:46:11.412119 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 12:46:11.415396 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 12:46:11.421909 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5638 12:46:11.425294 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5639 12:46:11.428682 0 15 24 | B1->B0 | 2929 3030 | 0 0 | (0 0) (0 0)
5640 12:46:11.435187 0 15 28 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
5641 12:46:11.438531 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 12:46:11.441930 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 12:46:11.448238 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 12:46:11.451882 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 12:46:11.455261 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 12:46:11.461670 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5647 12:46:11.464882 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5648 12:46:11.468485 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5649 12:46:11.475238 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5650 12:46:11.478418 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 12:46:11.481897 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 12:46:11.488492 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 12:46:11.491760 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 12:46:11.494841 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 12:46:11.501437 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 12:46:11.505138 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 12:46:11.508106 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 12:46:11.515062 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 12:46:11.518449 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 12:46:11.521853 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 12:46:11.528445 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 12:46:11.531707 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 12:46:11.534968 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5664 12:46:11.538253 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5665 12:46:11.541514 Total UI for P1: 0, mck2ui 16
5666 12:46:11.544867 best dqsien dly found for B0: ( 1, 2, 24)
5667 12:46:11.548186 Total UI for P1: 0, mck2ui 16
5668 12:46:11.551487 best dqsien dly found for B1: ( 1, 2, 24)
5669 12:46:11.554819 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5670 12:46:11.558047 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5671 12:46:11.561399
5672 12:46:11.564529 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5673 12:46:11.568222 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5674 12:46:11.571309 [Gating] SW calibration Done
5675 12:46:11.571407 ==
5676 12:46:11.574987 Dram Type= 6, Freq= 0, CH_1, rank 0
5677 12:46:11.578119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5678 12:46:11.578192 ==
5679 12:46:11.578256 RX Vref Scan: 0
5680 12:46:11.581385
5681 12:46:11.581455 RX Vref 0 -> 0, step: 1
5682 12:46:11.581513
5683 12:46:11.584774 RX Delay -80 -> 252, step: 8
5684 12:46:11.588008 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5685 12:46:11.591055 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5686 12:46:11.597889 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5687 12:46:11.601702 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5688 12:46:11.604254 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5689 12:46:11.608045 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5690 12:46:11.611438 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5691 12:46:11.614892 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5692 12:46:11.621379 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5693 12:46:11.624628 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5694 12:46:11.627474 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5695 12:46:11.630887 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5696 12:46:11.634483 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5697 12:46:11.640852 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5698 12:46:11.644077 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5699 12:46:11.647557 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5700 12:46:11.647643 ==
5701 12:46:11.650830 Dram Type= 6, Freq= 0, CH_1, rank 0
5702 12:46:11.654178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5703 12:46:11.654254 ==
5704 12:46:11.657503 DQS Delay:
5705 12:46:11.657577 DQS0 = 0, DQS1 = 0
5706 12:46:11.660845 DQM Delay:
5707 12:46:11.660924 DQM0 = 102, DQM1 = 99
5708 12:46:11.660985 DQ Delay:
5709 12:46:11.664132 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5710 12:46:11.667684 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5711 12:46:11.670928 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5712 12:46:11.674080 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5713 12:46:11.677230
5714 12:46:11.677312
5715 12:46:11.677376 ==
5716 12:46:11.680943 Dram Type= 6, Freq= 0, CH_1, rank 0
5717 12:46:11.684390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5718 12:46:11.684472 ==
5719 12:46:11.684569
5720 12:46:11.684628
5721 12:46:11.687586 TX Vref Scan disable
5722 12:46:11.687668 == TX Byte 0 ==
5723 12:46:11.694186 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5724 12:46:11.697480 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5725 12:46:11.697588 == TX Byte 1 ==
5726 12:46:11.704099 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5727 12:46:11.707433 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5728 12:46:11.707514 ==
5729 12:46:11.710745 Dram Type= 6, Freq= 0, CH_1, rank 0
5730 12:46:11.713948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 12:46:11.714022 ==
5732 12:46:11.714082
5733 12:46:11.714140
5734 12:46:11.717240 TX Vref Scan disable
5735 12:46:11.720390 == TX Byte 0 ==
5736 12:46:11.723671 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5737 12:46:11.727489 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5738 12:46:11.730585 == TX Byte 1 ==
5739 12:46:11.733884 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5740 12:46:11.737187 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5741 12:46:11.737260
5742 12:46:11.740278 [DATLAT]
5743 12:46:11.740387 Freq=933, CH1 RK0
5744 12:46:11.740495
5745 12:46:11.744320 DATLAT Default: 0xd
5746 12:46:11.744403 0, 0xFFFF, sum = 0
5747 12:46:11.747098 1, 0xFFFF, sum = 0
5748 12:46:11.747180 2, 0xFFFF, sum = 0
5749 12:46:11.750654 3, 0xFFFF, sum = 0
5750 12:46:11.750736 4, 0xFFFF, sum = 0
5751 12:46:11.754304 5, 0xFFFF, sum = 0
5752 12:46:11.754387 6, 0xFFFF, sum = 0
5753 12:46:11.757305 7, 0xFFFF, sum = 0
5754 12:46:11.757387 8, 0xFFFF, sum = 0
5755 12:46:11.760229 9, 0xFFFF, sum = 0
5756 12:46:11.760378 10, 0x0, sum = 1
5757 12:46:11.764023 11, 0x0, sum = 2
5758 12:46:11.764132 12, 0x0, sum = 3
5759 12:46:11.766915 13, 0x0, sum = 4
5760 12:46:11.767009 best_step = 11
5761 12:46:11.767128
5762 12:46:11.767194 ==
5763 12:46:11.770314 Dram Type= 6, Freq= 0, CH_1, rank 0
5764 12:46:11.776957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5765 12:46:11.777040 ==
5766 12:46:11.777135 RX Vref Scan: 1
5767 12:46:11.777227
5768 12:46:11.780176 RX Vref 0 -> 0, step: 1
5769 12:46:11.780273
5770 12:46:11.783665 RX Delay -45 -> 252, step: 4
5771 12:46:11.783789
5772 12:46:11.787492 Set Vref, RX VrefLevel [Byte0]: 52
5773 12:46:11.790492 [Byte1]: 52
5774 12:46:11.790657
5775 12:46:11.793367 Final RX Vref Byte 0 = 52 to rank0
5776 12:46:11.796804 Final RX Vref Byte 1 = 52 to rank0
5777 12:46:11.800035 Final RX Vref Byte 0 = 52 to rank1
5778 12:46:11.803541 Final RX Vref Byte 1 = 52 to rank1==
5779 12:46:11.806967 Dram Type= 6, Freq= 0, CH_1, rank 0
5780 12:46:11.810255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5781 12:46:11.810337 ==
5782 12:46:11.813589 DQS Delay:
5783 12:46:11.813670 DQS0 = 0, DQS1 = 0
5784 12:46:11.813733 DQM Delay:
5785 12:46:11.816854 DQM0 = 102, DQM1 = 99
5786 12:46:11.816941 DQ Delay:
5787 12:46:11.820133 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5788 12:46:11.823343 DQ4 =104, DQ5 =112, DQ6 =110, DQ7 =102
5789 12:46:11.827233 DQ8 =90, DQ9 =92, DQ10 =98, DQ11 =92
5790 12:46:11.830534 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =106
5791 12:46:11.830608
5792 12:46:11.833783
5793 12:46:11.840217 [DQSOSCAuto] RK0, (LSB)MR18= 0x152c, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
5794 12:46:11.843536 CH1 RK0: MR19=505, MR18=152C
5795 12:46:11.850065 CH1_RK0: MR19=0x505, MR18=0x152C, DQSOSC=408, MR23=63, INC=65, DEC=43
5796 12:46:11.850150
5797 12:46:11.853320 ----->DramcWriteLeveling(PI) begin...
5798 12:46:11.853394 ==
5799 12:46:11.856529 Dram Type= 6, Freq= 0, CH_1, rank 1
5800 12:46:11.859761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5801 12:46:11.859846 ==
5802 12:46:11.863650 Write leveling (Byte 0): 25 => 25
5803 12:46:11.866727 Write leveling (Byte 1): 26 => 26
5804 12:46:11.869738 DramcWriteLeveling(PI) end<-----
5805 12:46:11.869819
5806 12:46:11.869882 ==
5807 12:46:11.873278 Dram Type= 6, Freq= 0, CH_1, rank 1
5808 12:46:11.876631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5809 12:46:11.876712 ==
5810 12:46:11.880090 [Gating] SW mode calibration
5811 12:46:11.886455 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5812 12:46:11.893243 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5813 12:46:11.896451 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 12:46:11.899890 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5815 12:46:11.906767 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5816 12:46:11.909702 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5817 12:46:11.913691 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5818 12:46:11.919791 0 14 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5819 12:46:11.923203 0 14 24 | B1->B0 | 2a2a 3131 | 1 1 | (1 0) (1 1)
5820 12:46:11.926641 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5821 12:46:11.932917 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5822 12:46:11.936257 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5823 12:46:11.939522 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 12:46:11.946943 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5825 12:46:11.949978 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5826 12:46:11.953304 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5827 12:46:11.959970 0 15 24 | B1->B0 | 3939 2a2a | 0 1 | (0 0) (0 0)
5828 12:46:11.963336 0 15 28 | B1->B0 | 4646 3c3c | 0 0 | (0 0) (0 0)
5829 12:46:11.966386 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 12:46:11.972668 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 12:46:11.975958 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 12:46:11.979412 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 12:46:11.986545 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 12:46:11.989538 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5835 12:46:11.992722 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5836 12:46:11.996372 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5837 12:46:12.003178 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 12:46:12.006276 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 12:46:12.009730 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 12:46:12.016411 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 12:46:12.020062 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 12:46:12.023305 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 12:46:12.029945 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 12:46:12.033281 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 12:46:12.036548 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 12:46:12.043312 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 12:46:12.046782 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 12:46:12.050076 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 12:46:12.056460 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 12:46:12.059837 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 12:46:12.063089 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5852 12:46:12.069636 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5853 12:46:12.070075 Total UI for P1: 0, mck2ui 16
5854 12:46:12.076743 best dqsien dly found for B0: ( 1, 2, 26)
5855 12:46:12.077180 Total UI for P1: 0, mck2ui 16
5856 12:46:12.079964 best dqsien dly found for B1: ( 1, 2, 24)
5857 12:46:12.086254 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5858 12:46:12.090140 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5859 12:46:12.090680
5860 12:46:12.093519 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5861 12:46:12.096773 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5862 12:46:12.099866 [Gating] SW calibration Done
5863 12:46:12.100320 ==
5864 12:46:12.102853 Dram Type= 6, Freq= 0, CH_1, rank 1
5865 12:46:12.106990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5866 12:46:12.107426 ==
5867 12:46:12.109851 RX Vref Scan: 0
5868 12:46:12.110282
5869 12:46:12.110722 RX Vref 0 -> 0, step: 1
5870 12:46:12.111141
5871 12:46:12.113195 RX Delay -80 -> 252, step: 8
5872 12:46:12.116365 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5873 12:46:12.122871 iDelay=208, Bit 1, Center 103 (16 ~ 191) 176
5874 12:46:12.126146 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5875 12:46:12.129467 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5876 12:46:12.133283 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5877 12:46:12.136029 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5878 12:46:12.139757 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5879 12:46:12.146166 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5880 12:46:12.149578 iDelay=208, Bit 8, Center 91 (0 ~ 183) 184
5881 12:46:12.153082 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5882 12:46:12.155929 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5883 12:46:12.159533 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5884 12:46:12.163055 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5885 12:46:12.169703 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5886 12:46:12.173057 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5887 12:46:12.176317 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5888 12:46:12.176736 ==
5889 12:46:12.179533 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 12:46:12.182901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 12:46:12.186059 ==
5892 12:46:12.186570 DQS Delay:
5893 12:46:12.187020 DQS0 = 0, DQS1 = 0
5894 12:46:12.189363 DQM Delay:
5895 12:46:12.189799 DQM0 = 104, DQM1 = 99
5896 12:46:12.190241 DQ Delay:
5897 12:46:12.195865 DQ0 =107, DQ1 =103, DQ2 =91, DQ3 =103
5898 12:46:12.199075 DQ4 =95, DQ5 =119, DQ6 =115, DQ7 =103
5899 12:46:12.202811 DQ8 =91, DQ9 =91, DQ10 =99, DQ11 =91
5900 12:46:12.206224 DQ12 =107, DQ13 =107, DQ14 =99, DQ15 =107
5901 12:46:12.206658
5902 12:46:12.207103
5903 12:46:12.207519 ==
5904 12:46:12.209416 Dram Type= 6, Freq= 0, CH_1, rank 1
5905 12:46:12.212631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5906 12:46:12.213065 ==
5907 12:46:12.213506
5908 12:46:12.213926
5909 12:46:12.216371 TX Vref Scan disable
5910 12:46:12.216808 == TX Byte 0 ==
5911 12:46:12.222674 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5912 12:46:12.225920 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5913 12:46:12.226354 == TX Byte 1 ==
5914 12:46:12.232400 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5915 12:46:12.235355 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5916 12:46:12.235438 ==
5917 12:46:12.238817 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 12:46:12.242064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 12:46:12.242149 ==
5920 12:46:12.242234
5921 12:46:12.245357
5922 12:46:12.245442 TX Vref Scan disable
5923 12:46:12.248613 == TX Byte 0 ==
5924 12:46:12.252051 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5925 12:46:12.255464 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5926 12:46:12.258783 == TX Byte 1 ==
5927 12:46:12.262415 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5928 12:46:12.265423 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5929 12:46:12.265510
5930 12:46:12.268637 [DATLAT]
5931 12:46:12.268721 Freq=933, CH1 RK1
5932 12:46:12.268806
5933 12:46:12.272048 DATLAT Default: 0xb
5934 12:46:12.272155 0, 0xFFFF, sum = 0
5935 12:46:12.275303 1, 0xFFFF, sum = 0
5936 12:46:12.275388 2, 0xFFFF, sum = 0
5937 12:46:12.278836 3, 0xFFFF, sum = 0
5938 12:46:12.278922 4, 0xFFFF, sum = 0
5939 12:46:12.282021 5, 0xFFFF, sum = 0
5940 12:46:12.282107 6, 0xFFFF, sum = 0
5941 12:46:12.285494 7, 0xFFFF, sum = 0
5942 12:46:12.285583 8, 0xFFFF, sum = 0
5943 12:46:12.288840 9, 0xFFFF, sum = 0
5944 12:46:12.288949 10, 0x0, sum = 1
5945 12:46:12.292488 11, 0x0, sum = 2
5946 12:46:12.292570 12, 0x0, sum = 3
5947 12:46:12.295616 13, 0x0, sum = 4
5948 12:46:12.295715 best_step = 11
5949 12:46:12.295806
5950 12:46:12.295928 ==
5951 12:46:12.298941 Dram Type= 6, Freq= 0, CH_1, rank 1
5952 12:46:12.305387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5953 12:46:12.305469 ==
5954 12:46:12.305533 RX Vref Scan: 0
5955 12:46:12.305592
5956 12:46:12.309068 RX Vref 0 -> 0, step: 1
5957 12:46:12.309176
5958 12:46:12.312626 RX Delay -45 -> 252, step: 4
5959 12:46:12.315622 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5960 12:46:12.319224 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5961 12:46:12.325318 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5962 12:46:12.328824 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5963 12:46:12.331868 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5964 12:46:12.335135 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5965 12:46:12.338540 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5966 12:46:12.345120 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5967 12:46:12.348524 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5968 12:46:12.352390 iDelay=203, Bit 9, Center 88 (-1 ~ 178) 180
5969 12:46:12.354997 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5970 12:46:12.358889 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5971 12:46:12.365565 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5972 12:46:12.368813 iDelay=203, Bit 13, Center 104 (19 ~ 190) 172
5973 12:46:12.372150 iDelay=203, Bit 14, Center 102 (19 ~ 186) 168
5974 12:46:12.375372 iDelay=203, Bit 15, Center 106 (19 ~ 194) 176
5975 12:46:12.375469 ==
5976 12:46:12.378738 Dram Type= 6, Freq= 0, CH_1, rank 1
5977 12:46:12.385377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5978 12:46:12.385489 ==
5979 12:46:12.385590 DQS Delay:
5980 12:46:12.385677 DQS0 = 0, DQS1 = 0
5981 12:46:12.388256 DQM Delay:
5982 12:46:12.388378 DQM0 = 104, DQM1 = 98
5983 12:46:12.392039 DQ Delay:
5984 12:46:12.395014 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5985 12:46:12.398309 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =102
5986 12:46:12.401654 DQ8 =88, DQ9 =88, DQ10 =100, DQ11 =92
5987 12:46:12.405248 DQ12 =108, DQ13 =104, DQ14 =102, DQ15 =106
5988 12:46:12.405344
5989 12:46:12.405434
5990 12:46:12.411768 [DQSOSCAuto] RK1, (LSB)MR18= 0x3003, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 406 ps
5991 12:46:12.415134 CH1 RK1: MR19=505, MR18=3003
5992 12:46:12.421491 CH1_RK1: MR19=0x505, MR18=0x3003, DQSOSC=406, MR23=63, INC=65, DEC=43
5993 12:46:12.425184 [RxdqsGatingPostProcess] freq 933
5994 12:46:12.431749 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5995 12:46:12.435070 best DQS0 dly(2T, 0.5T) = (0, 10)
5996 12:46:12.435172 best DQS1 dly(2T, 0.5T) = (0, 10)
5997 12:46:12.438550 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5998 12:46:12.441557 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5999 12:46:12.445001 best DQS0 dly(2T, 0.5T) = (0, 10)
6000 12:46:12.448410 best DQS1 dly(2T, 0.5T) = (0, 10)
6001 12:46:12.452070 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6002 12:46:12.455185 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6003 12:46:12.458411 Pre-setting of DQS Precalculation
6004 12:46:12.465084 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6005 12:46:12.471925 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6006 12:46:12.477788 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6007 12:46:12.477894
6008 12:46:12.477985
6009 12:46:12.481862 [Calibration Summary] 1866 Mbps
6010 12:46:12.481965 CH 0, Rank 0
6011 12:46:12.485159 SW Impedance : PASS
6012 12:46:12.488546 DUTY Scan : NO K
6013 12:46:12.488652 ZQ Calibration : PASS
6014 12:46:12.491674 Jitter Meter : NO K
6015 12:46:12.495033 CBT Training : PASS
6016 12:46:12.495136 Write leveling : PASS
6017 12:46:12.498291 RX DQS gating : PASS
6018 12:46:12.498402 RX DQ/DQS(RDDQC) : PASS
6019 12:46:12.501744 TX DQ/DQS : PASS
6020 12:46:12.504949 RX DATLAT : PASS
6021 12:46:12.505046 RX DQ/DQS(Engine): PASS
6022 12:46:12.507889 TX OE : NO K
6023 12:46:12.507983 All Pass.
6024 12:46:12.508100
6025 12:46:12.511648 CH 0, Rank 1
6026 12:46:12.511743 SW Impedance : PASS
6027 12:46:12.514734 DUTY Scan : NO K
6028 12:46:12.518048 ZQ Calibration : PASS
6029 12:46:12.518152 Jitter Meter : NO K
6030 12:46:12.521279 CBT Training : PASS
6031 12:46:12.524649 Write leveling : PASS
6032 12:46:12.524753 RX DQS gating : PASS
6033 12:46:12.527973 RX DQ/DQS(RDDQC) : PASS
6034 12:46:12.531178 TX DQ/DQS : PASS
6035 12:46:12.531272 RX DATLAT : PASS
6036 12:46:12.534458 RX DQ/DQS(Engine): PASS
6037 12:46:12.534554 TX OE : NO K
6038 12:46:12.538150 All Pass.
6039 12:46:12.538244
6040 12:46:12.538332 CH 1, Rank 0
6041 12:46:12.541405 SW Impedance : PASS
6042 12:46:12.544516 DUTY Scan : NO K
6043 12:46:12.544614 ZQ Calibration : PASS
6044 12:46:12.547735 Jitter Meter : NO K
6045 12:46:12.547807 CBT Training : PASS
6046 12:46:12.551397 Write leveling : PASS
6047 12:46:12.554323 RX DQS gating : PASS
6048 12:46:12.554469 RX DQ/DQS(RDDQC) : PASS
6049 12:46:12.557775 TX DQ/DQS : PASS
6050 12:46:12.561029 RX DATLAT : PASS
6051 12:46:12.561126 RX DQ/DQS(Engine): PASS
6052 12:46:12.564658 TX OE : NO K
6053 12:46:12.564755 All Pass.
6054 12:46:12.564842
6055 12:46:12.567758 CH 1, Rank 1
6056 12:46:12.567849 SW Impedance : PASS
6057 12:46:12.571306 DUTY Scan : NO K
6058 12:46:12.574940 ZQ Calibration : PASS
6059 12:46:12.575044 Jitter Meter : NO K
6060 12:46:12.578044 CBT Training : PASS
6061 12:46:12.581419 Write leveling : PASS
6062 12:46:12.581508 RX DQS gating : PASS
6063 12:46:12.584110 RX DQ/DQS(RDDQC) : PASS
6064 12:46:12.588055 TX DQ/DQS : PASS
6065 12:46:12.588163 RX DATLAT : PASS
6066 12:46:12.591370 RX DQ/DQS(Engine): PASS
6067 12:46:12.594665 TX OE : NO K
6068 12:46:12.594762 All Pass.
6069 12:46:12.594850
6070 12:46:12.594937 DramC Write-DBI off
6071 12:46:12.597975 PER_BANK_REFRESH: Hybrid Mode
6072 12:46:12.601396 TX_TRACKING: ON
6073 12:46:12.607999 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6074 12:46:12.611228 [FAST_K] Save calibration result to emmc
6075 12:46:12.617349 dramc_set_vcore_voltage set vcore to 650000
6076 12:46:12.617459 Read voltage for 400, 6
6077 12:46:12.617612 Vio18 = 0
6078 12:46:12.621211 Vcore = 650000
6079 12:46:12.621308 Vdram = 0
6080 12:46:12.621395 Vddq = 0
6081 12:46:12.624138 Vmddr = 0
6082 12:46:12.627315 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6083 12:46:12.633999 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6084 12:46:12.637809 MEM_TYPE=3, freq_sel=20
6085 12:46:12.637909 sv_algorithm_assistance_LP4_800
6086 12:46:12.644314 ============ PULL DRAM RESETB DOWN ============
6087 12:46:12.647458 ========== PULL DRAM RESETB DOWN end =========
6088 12:46:12.651110 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6089 12:46:12.654338 ===================================
6090 12:46:12.657649 LPDDR4 DRAM CONFIGURATION
6091 12:46:12.661021 ===================================
6092 12:46:12.664212 EX_ROW_EN[0] = 0x0
6093 12:46:12.664345 EX_ROW_EN[1] = 0x0
6094 12:46:12.667504 LP4Y_EN = 0x0
6095 12:46:12.667602 WORK_FSP = 0x0
6096 12:46:12.670743 WL = 0x2
6097 12:46:12.670868 RL = 0x2
6098 12:46:12.674062 BL = 0x2
6099 12:46:12.674158 RPST = 0x0
6100 12:46:12.677180 RD_PRE = 0x0
6101 12:46:12.677281 WR_PRE = 0x1
6102 12:46:12.680779 WR_PST = 0x0
6103 12:46:12.680880 DBI_WR = 0x0
6104 12:46:12.683751 DBI_RD = 0x0
6105 12:46:12.683851 OTF = 0x1
6106 12:46:12.687668 ===================================
6107 12:46:12.691006 ===================================
6108 12:46:12.694212 ANA top config
6109 12:46:12.697452 ===================================
6110 12:46:12.701023 DLL_ASYNC_EN = 0
6111 12:46:12.701107 ALL_SLAVE_EN = 1
6112 12:46:12.704455 NEW_RANK_MODE = 1
6113 12:46:12.707665 DLL_IDLE_MODE = 1
6114 12:46:12.711006 LP45_APHY_COMB_EN = 1
6115 12:46:12.711090 TX_ODT_DIS = 1
6116 12:46:12.714363 NEW_8X_MODE = 1
6117 12:46:12.717584 ===================================
6118 12:46:12.720685 ===================================
6119 12:46:12.724280 data_rate = 800
6120 12:46:12.727492 CKR = 1
6121 12:46:12.730577 DQ_P2S_RATIO = 4
6122 12:46:12.734077 ===================================
6123 12:46:12.737211 CA_P2S_RATIO = 4
6124 12:46:12.737295 DQ_CA_OPEN = 0
6125 12:46:12.740525 DQ_SEMI_OPEN = 1
6126 12:46:12.744154 CA_SEMI_OPEN = 1
6127 12:46:12.747574 CA_FULL_RATE = 0
6128 12:46:12.750771 DQ_CKDIV4_EN = 0
6129 12:46:12.754281 CA_CKDIV4_EN = 1
6130 12:46:12.754402 CA_PREDIV_EN = 0
6131 12:46:12.757499 PH8_DLY = 0
6132 12:46:12.760446 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6133 12:46:12.764231 DQ_AAMCK_DIV = 0
6134 12:46:12.766980 CA_AAMCK_DIV = 0
6135 12:46:12.770862 CA_ADMCK_DIV = 4
6136 12:46:12.770947 DQ_TRACK_CA_EN = 0
6137 12:46:12.774103 CA_PICK = 800
6138 12:46:12.777135 CA_MCKIO = 400
6139 12:46:12.780526 MCKIO_SEMI = 400
6140 12:46:12.783784 PLL_FREQ = 3016
6141 12:46:12.787148 DQ_UI_PI_RATIO = 32
6142 12:46:12.790448 CA_UI_PI_RATIO = 32
6143 12:46:12.793579 ===================================
6144 12:46:12.796866 ===================================
6145 12:46:12.796966 memory_type:LPDDR4
6146 12:46:12.800653 GP_NUM : 10
6147 12:46:12.803825 SRAM_EN : 1
6148 12:46:12.803909 MD32_EN : 0
6149 12:46:12.807239 ===================================
6150 12:46:12.810455 [ANA_INIT] >>>>>>>>>>>>>>
6151 12:46:12.814009 <<<<<< [CONFIGURE PHASE]: ANA_TX
6152 12:46:12.817039 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6153 12:46:12.820345 ===================================
6154 12:46:12.823591 data_rate = 800,PCW = 0X7400
6155 12:46:12.823676 ===================================
6156 12:46:12.830469 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6157 12:46:12.833798 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6158 12:46:12.847246 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6159 12:46:12.850592 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6160 12:46:12.853407 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6161 12:46:12.856670 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6162 12:46:12.860578 [ANA_INIT] flow start
6163 12:46:12.860662 [ANA_INIT] PLL >>>>>>>>
6164 12:46:12.863693 [ANA_INIT] PLL <<<<<<<<
6165 12:46:12.866849 [ANA_INIT] MIDPI >>>>>>>>
6166 12:46:12.869982 [ANA_INIT] MIDPI <<<<<<<<
6167 12:46:12.870066 [ANA_INIT] DLL >>>>>>>>
6168 12:46:12.873594 [ANA_INIT] flow end
6169 12:46:12.876840 ============ LP4 DIFF to SE enter ============
6170 12:46:12.880095 ============ LP4 DIFF to SE exit ============
6171 12:46:12.883828 [ANA_INIT] <<<<<<<<<<<<<
6172 12:46:12.887078 [Flow] Enable top DCM control >>>>>
6173 12:46:12.890427 [Flow] Enable top DCM control <<<<<
6174 12:46:12.893306 Enable DLL master slave shuffle
6175 12:46:12.897004 ==============================================================
6176 12:46:12.900327 Gating Mode config
6177 12:46:12.906984 ==============================================================
6178 12:46:12.907069 Config description:
6179 12:46:12.916553 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6180 12:46:12.923504 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6181 12:46:12.929900 SELPH_MODE 0: By rank 1: By Phase
6182 12:46:12.932996 ==============================================================
6183 12:46:12.936824 GAT_TRACK_EN = 0
6184 12:46:12.939919 RX_GATING_MODE = 2
6185 12:46:12.943210 RX_GATING_TRACK_MODE = 2
6186 12:46:12.946452 SELPH_MODE = 1
6187 12:46:12.949976 PICG_EARLY_EN = 1
6188 12:46:12.953132 VALID_LAT_VALUE = 1
6189 12:46:12.956299 ==============================================================
6190 12:46:12.959573 Enter into Gating configuration >>>>
6191 12:46:12.962998 Exit from Gating configuration <<<<
6192 12:46:12.966309 Enter into DVFS_PRE_config >>>>>
6193 12:46:12.979795 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6194 12:46:12.982901 Exit from DVFS_PRE_config <<<<<
6195 12:46:12.985972 Enter into PICG configuration >>>>
6196 12:46:12.989719 Exit from PICG configuration <<<<
6197 12:46:12.989805 [RX_INPUT] configuration >>>>>
6198 12:46:12.992936 [RX_INPUT] configuration <<<<<
6199 12:46:12.999424 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6200 12:46:13.002497 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6201 12:46:13.009606 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6202 12:46:13.015894 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6203 12:46:13.022530 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6204 12:46:13.029063 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6205 12:46:13.032448 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6206 12:46:13.036398 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6207 12:46:13.042690 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6208 12:46:13.045974 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6209 12:46:13.049363 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6210 12:46:13.052322 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6211 12:46:13.055704 ===================================
6212 12:46:13.059107 LPDDR4 DRAM CONFIGURATION
6213 12:46:13.062301 ===================================
6214 12:46:13.066299 EX_ROW_EN[0] = 0x0
6215 12:46:13.066380 EX_ROW_EN[1] = 0x0
6216 12:46:13.069607 LP4Y_EN = 0x0
6217 12:46:13.069689 WORK_FSP = 0x0
6218 12:46:13.072814 WL = 0x2
6219 12:46:13.072895 RL = 0x2
6220 12:46:13.076041 BL = 0x2
6221 12:46:13.076123 RPST = 0x0
6222 12:46:13.079370 RD_PRE = 0x0
6223 12:46:13.079451 WR_PRE = 0x1
6224 12:46:13.082817 WR_PST = 0x0
6225 12:46:13.082897 DBI_WR = 0x0
6226 12:46:13.086032 DBI_RD = 0x0
6227 12:46:13.086113 OTF = 0x1
6228 12:46:13.089326 ===================================
6229 12:46:13.095744 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6230 12:46:13.099119 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6231 12:46:13.102163 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6232 12:46:13.105900 ===================================
6233 12:46:13.109123 LPDDR4 DRAM CONFIGURATION
6234 12:46:13.112481 ===================================
6235 12:46:13.115654 EX_ROW_EN[0] = 0x10
6236 12:46:13.115735 EX_ROW_EN[1] = 0x0
6237 12:46:13.118778 LP4Y_EN = 0x0
6238 12:46:13.118859 WORK_FSP = 0x0
6239 12:46:13.122642 WL = 0x2
6240 12:46:13.122723 RL = 0x2
6241 12:46:13.125875 BL = 0x2
6242 12:46:13.125958 RPST = 0x0
6243 12:46:13.129224 RD_PRE = 0x0
6244 12:46:13.129306 WR_PRE = 0x1
6245 12:46:13.132414 WR_PST = 0x0
6246 12:46:13.132495 DBI_WR = 0x0
6247 12:46:13.135776 DBI_RD = 0x0
6248 12:46:13.135857 OTF = 0x1
6249 12:46:13.139357 ===================================
6250 12:46:13.145281 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6251 12:46:13.150568 nWR fixed to 30
6252 12:46:13.153550 [ModeRegInit_LP4] CH0 RK0
6253 12:46:13.153631 [ModeRegInit_LP4] CH0 RK1
6254 12:46:13.156572 [ModeRegInit_LP4] CH1 RK0
6255 12:46:13.160014 [ModeRegInit_LP4] CH1 RK1
6256 12:46:13.160095 match AC timing 19
6257 12:46:13.166720 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6258 12:46:13.169893 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6259 12:46:13.173523 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6260 12:46:13.179974 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6261 12:46:13.183395 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6262 12:46:13.183479 ==
6263 12:46:13.186623 Dram Type= 6, Freq= 0, CH_0, rank 0
6264 12:46:13.190012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6265 12:46:13.190097 ==
6266 12:46:13.196853 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6267 12:46:13.203317 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6268 12:46:13.206538 [CA 0] Center 36 (8~64) winsize 57
6269 12:46:13.209957 [CA 1] Center 36 (8~64) winsize 57
6270 12:46:13.213266 [CA 2] Center 36 (8~64) winsize 57
6271 12:46:13.216361 [CA 3] Center 36 (8~64) winsize 57
6272 12:46:13.216468 [CA 4] Center 36 (8~64) winsize 57
6273 12:46:13.219918 [CA 5] Center 36 (8~64) winsize 57
6274 12:46:13.220016
6275 12:46:13.226538 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6276 12:46:13.226625
6277 12:46:13.229850 [CATrainingPosCal] consider 1 rank data
6278 12:46:13.233163 u2DelayCellTimex100 = 270/100 ps
6279 12:46:13.237034 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 12:46:13.239886 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 12:46:13.243618 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 12:46:13.246954 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 12:46:13.250339 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 12:46:13.253596 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 12:46:13.253673
6286 12:46:13.256949 CA PerBit enable=1, Macro0, CA PI delay=36
6287 12:46:13.257044
6288 12:46:13.260340 [CBTSetCACLKResult] CA Dly = 36
6289 12:46:13.263119 CS Dly: 1 (0~32)
6290 12:46:13.263190 ==
6291 12:46:13.266993 Dram Type= 6, Freq= 0, CH_0, rank 1
6292 12:46:13.270086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6293 12:46:13.270153 ==
6294 12:46:13.276793 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6295 12:46:13.279720 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6296 12:46:13.283191 [CA 0] Center 36 (8~64) winsize 57
6297 12:46:13.286526 [CA 1] Center 36 (8~64) winsize 57
6298 12:46:13.289903 [CA 2] Center 36 (8~64) winsize 57
6299 12:46:13.293262 [CA 3] Center 36 (8~64) winsize 57
6300 12:46:13.296849 [CA 4] Center 36 (8~64) winsize 57
6301 12:46:13.299532 [CA 5] Center 36 (8~64) winsize 57
6302 12:46:13.299607
6303 12:46:13.302931 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6304 12:46:13.303025
6305 12:46:13.306296 [CATrainingPosCal] consider 2 rank data
6306 12:46:13.309663 u2DelayCellTimex100 = 270/100 ps
6307 12:46:13.313020 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 12:46:13.316746 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 12:46:13.319933 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 12:46:13.326424 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 12:46:13.329572 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 12:46:13.333117 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 12:46:13.333210
6314 12:46:13.336542 CA PerBit enable=1, Macro0, CA PI delay=36
6315 12:46:13.336637
6316 12:46:13.339405 [CBTSetCACLKResult] CA Dly = 36
6317 12:46:13.339472 CS Dly: 1 (0~32)
6318 12:46:13.339536
6319 12:46:13.343319 ----->DramcWriteLeveling(PI) begin...
6320 12:46:13.343414 ==
6321 12:46:13.346508 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 12:46:13.353164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 12:46:13.353240 ==
6324 12:46:13.356017 Write leveling (Byte 0): 40 => 8
6325 12:46:13.359862 Write leveling (Byte 1): 40 => 8
6326 12:46:13.359957 DramcWriteLeveling(PI) end<-----
6327 12:46:13.360043
6328 12:46:13.363163 ==
6329 12:46:13.366538 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 12:46:13.369776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 12:46:13.369870 ==
6332 12:46:13.373172 [Gating] SW mode calibration
6333 12:46:13.379744 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6334 12:46:13.382919 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6335 12:46:13.389395 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6336 12:46:13.393165 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6337 12:46:13.396236 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6338 12:46:13.403031 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6339 12:46:13.406186 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6340 12:46:13.409192 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6341 12:46:13.415847 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6342 12:46:13.419036 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6343 12:46:13.422757 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6344 12:46:13.426159 Total UI for P1: 0, mck2ui 16
6345 12:46:13.429349 best dqsien dly found for B0: ( 0, 14, 24)
6346 12:46:13.432487 Total UI for P1: 0, mck2ui 16
6347 12:46:13.435696 best dqsien dly found for B1: ( 0, 14, 24)
6348 12:46:13.438874 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6349 12:46:13.442164 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6350 12:46:13.442271
6351 12:46:13.449146 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6352 12:46:13.452650 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6353 12:46:13.455718 [Gating] SW calibration Done
6354 12:46:13.455818 ==
6355 12:46:13.459015 Dram Type= 6, Freq= 0, CH_0, rank 0
6356 12:46:13.462275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6357 12:46:13.462374 ==
6358 12:46:13.462499 RX Vref Scan: 0
6359 12:46:13.462589
6360 12:46:13.465542 RX Vref 0 -> 0, step: 1
6361 12:46:13.465650
6362 12:46:13.468883 RX Delay -410 -> 252, step: 16
6363 12:46:13.472220 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6364 12:46:13.478780 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6365 12:46:13.481983 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6366 12:46:13.485911 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6367 12:46:13.489210 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6368 12:46:13.492349 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6369 12:46:13.499005 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6370 12:46:13.502060 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6371 12:46:13.505351 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6372 12:46:13.509387 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6373 12:46:13.515944 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6374 12:46:13.518992 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6375 12:46:13.522642 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6376 12:46:13.528675 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6377 12:46:13.532329 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6378 12:46:13.535451 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6379 12:46:13.535575 ==
6380 12:46:13.539144 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 12:46:13.542272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 12:46:13.542376 ==
6383 12:46:13.545949 DQS Delay:
6384 12:46:13.546052 DQS0 = 27, DQS1 = 35
6385 12:46:13.549022 DQM Delay:
6386 12:46:13.549123 DQM0 = 10, DQM1 = 11
6387 12:46:13.552481 DQ Delay:
6388 12:46:13.552589 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6389 12:46:13.555686 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6390 12:46:13.559099 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6391 12:46:13.562148 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6392 12:46:13.562229
6393 12:46:13.562293
6394 12:46:13.562351 ==
6395 12:46:13.565884 Dram Type= 6, Freq= 0, CH_0, rank 0
6396 12:46:13.572492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 12:46:13.572573 ==
6398 12:46:13.572637
6399 12:46:13.572696
6400 12:46:13.572754 TX Vref Scan disable
6401 12:46:13.575818 == TX Byte 0 ==
6402 12:46:13.578955 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6403 12:46:13.582182 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6404 12:46:13.585393 == TX Byte 1 ==
6405 12:46:13.588766 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6406 12:46:13.592013 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6407 12:46:13.592094 ==
6408 12:46:13.595712 Dram Type= 6, Freq= 0, CH_0, rank 0
6409 12:46:13.602051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 12:46:13.602173 ==
6411 12:46:13.602278
6412 12:46:13.602364
6413 12:46:13.602442 TX Vref Scan disable
6414 12:46:13.605369 == TX Byte 0 ==
6415 12:46:13.608566 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6416 12:46:13.612274 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6417 12:46:13.615573 == TX Byte 1 ==
6418 12:46:13.618953 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6419 12:46:13.621811 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6420 12:46:13.621911
6421 12:46:13.625184 [DATLAT]
6422 12:46:13.625329 Freq=400, CH0 RK0
6423 12:46:13.625414
6424 12:46:13.628432 DATLAT Default: 0xf
6425 12:46:13.628516 0, 0xFFFF, sum = 0
6426 12:46:13.632203 1, 0xFFFF, sum = 0
6427 12:46:13.632296 2, 0xFFFF, sum = 0
6428 12:46:13.635546 3, 0xFFFF, sum = 0
6429 12:46:13.635631 4, 0xFFFF, sum = 0
6430 12:46:13.638861 5, 0xFFFF, sum = 0
6431 12:46:13.638946 6, 0xFFFF, sum = 0
6432 12:46:13.641905 7, 0xFFFF, sum = 0
6433 12:46:13.641991 8, 0xFFFF, sum = 0
6434 12:46:13.645698 9, 0xFFFF, sum = 0
6435 12:46:13.648413 10, 0xFFFF, sum = 0
6436 12:46:13.648554 11, 0xFFFF, sum = 0
6437 12:46:13.652244 12, 0xFFFF, sum = 0
6438 12:46:13.652354 13, 0x0, sum = 1
6439 12:46:13.655860 14, 0x0, sum = 2
6440 12:46:13.655974 15, 0x0, sum = 3
6441 12:46:13.656060 16, 0x0, sum = 4
6442 12:46:13.658614 best_step = 14
6443 12:46:13.658698
6444 12:46:13.658783 ==
6445 12:46:13.661731 Dram Type= 6, Freq= 0, CH_0, rank 0
6446 12:46:13.665204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 12:46:13.665288 ==
6448 12:46:13.668733 RX Vref Scan: 1
6449 12:46:13.668820
6450 12:46:13.668906 RX Vref 0 -> 0, step: 1
6451 12:46:13.672097
6452 12:46:13.672181 RX Delay -311 -> 252, step: 8
6453 12:46:13.672281
6454 12:46:13.675011 Set Vref, RX VrefLevel [Byte0]: 58
6455 12:46:13.678620 [Byte1]: 53
6456 12:46:13.683565
6457 12:46:13.683648 Final RX Vref Byte 0 = 58 to rank0
6458 12:46:13.686811 Final RX Vref Byte 1 = 53 to rank0
6459 12:46:13.690222 Final RX Vref Byte 0 = 58 to rank1
6460 12:46:13.693567 Final RX Vref Byte 1 = 53 to rank1==
6461 12:46:13.696815 Dram Type= 6, Freq= 0, CH_0, rank 0
6462 12:46:13.703921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6463 12:46:13.704006 ==
6464 12:46:13.704092 DQS Delay:
6465 12:46:13.707070 DQS0 = 28, DQS1 = 36
6466 12:46:13.707154 DQM Delay:
6467 12:46:13.707240 DQM0 = 10, DQM1 = 12
6468 12:46:13.710504 DQ Delay:
6469 12:46:13.713698 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6470 12:46:13.713782 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6471 12:46:13.716683 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6472 12:46:13.719793 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6473 12:46:13.719896
6474 12:46:13.723209
6475 12:46:13.730394 [DQSOSCAuto] RK0, (LSB)MR18= 0xd0bc, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6476 12:46:13.733155 CH0 RK0: MR19=C0C, MR18=D0BC
6477 12:46:13.740613 CH0_RK0: MR19=0xC0C, MR18=0xD0BC, DQSOSC=384, MR23=63, INC=400, DEC=267
6478 12:46:13.740797 ==
6479 12:46:13.743862 Dram Type= 6, Freq= 0, CH_0, rank 1
6480 12:46:13.747262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 12:46:13.747465 ==
6482 12:46:13.750330 [Gating] SW mode calibration
6483 12:46:13.757083 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6484 12:46:13.764046 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6485 12:46:13.766782 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6486 12:46:13.770222 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6487 12:46:13.773299 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6488 12:46:13.780391 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6489 12:46:13.783661 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6490 12:46:13.786941 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6491 12:46:13.793757 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6492 12:46:13.796956 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6493 12:46:13.800325 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6494 12:46:13.803532 Total UI for P1: 0, mck2ui 16
6495 12:46:13.806712 best dqsien dly found for B0: ( 0, 14, 24)
6496 12:46:13.810325 Total UI for P1: 0, mck2ui 16
6497 12:46:13.813471 best dqsien dly found for B1: ( 0, 14, 24)
6498 12:46:13.816846 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6499 12:46:13.820034 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6500 12:46:13.823118
6501 12:46:13.826974 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6502 12:46:13.830374 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6503 12:46:13.833578 [Gating] SW calibration Done
6504 12:46:13.833983 ==
6505 12:46:13.836930 Dram Type= 6, Freq= 0, CH_0, rank 1
6506 12:46:13.840585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6507 12:46:13.841101 ==
6508 12:46:13.841428 RX Vref Scan: 0
6509 12:46:13.841733
6510 12:46:13.843366 RX Vref 0 -> 0, step: 1
6511 12:46:13.843822
6512 12:46:13.847589 RX Delay -410 -> 252, step: 16
6513 12:46:13.850537 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6514 12:46:13.856916 iDelay=230, Bit 1, Center -11 (-234 ~ 213) 448
6515 12:46:13.860559 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6516 12:46:13.863864 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6517 12:46:13.867320 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6518 12:46:13.873683 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6519 12:46:13.876767 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6520 12:46:13.880196 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6521 12:46:13.883391 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6522 12:46:13.889933 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6523 12:46:13.893113 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6524 12:46:13.896820 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6525 12:46:13.900372 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6526 12:46:13.906958 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6527 12:46:13.910229 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6528 12:46:13.913380 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6529 12:46:13.913797 ==
6530 12:46:13.916722 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 12:46:13.919916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 12:46:13.923202 ==
6533 12:46:13.923617 DQS Delay:
6534 12:46:13.923957 DQS0 = 27, DQS1 = 35
6535 12:46:13.926290 DQM Delay:
6536 12:46:13.926718 DQM0 = 13, DQM1 = 11
6537 12:46:13.929638 DQ Delay:
6538 12:46:13.930141 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =8
6539 12:46:13.933252 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6540 12:46:13.936265 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6541 12:46:13.939961 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6542 12:46:13.940422
6543 12:46:13.940757
6544 12:46:13.943644 ==
6545 12:46:13.944057 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 12:46:13.949990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 12:46:13.950528 ==
6548 12:46:13.951027
6549 12:46:13.951454
6550 12:46:13.953107 TX Vref Scan disable
6551 12:46:13.953517 == TX Byte 0 ==
6552 12:46:13.956623 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6553 12:46:13.959940 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6554 12:46:13.963144 == TX Byte 1 ==
6555 12:46:13.966345 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6556 12:46:13.969682 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6557 12:46:13.972794 ==
6558 12:46:13.976119 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 12:46:13.979448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 12:46:13.979868 ==
6561 12:46:13.980322
6562 12:46:13.980662
6563 12:46:13.982706 TX Vref Scan disable
6564 12:46:13.983121 == TX Byte 0 ==
6565 12:46:13.986089 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6566 12:46:13.992626 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6567 12:46:13.993047 == TX Byte 1 ==
6568 12:46:13.995967 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6569 12:46:13.999662 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6570 12:46:14.003503
6571 12:46:14.004028 [DATLAT]
6572 12:46:14.004419 Freq=400, CH0 RK1
6573 12:46:14.004740
6574 12:46:14.006867 DATLAT Default: 0xe
6575 12:46:14.007388 0, 0xFFFF, sum = 0
6576 12:46:14.009381 1, 0xFFFF, sum = 0
6577 12:46:14.009804 2, 0xFFFF, sum = 0
6578 12:46:14.012576 3, 0xFFFF, sum = 0
6579 12:46:14.013004 4, 0xFFFF, sum = 0
6580 12:46:14.016354 5, 0xFFFF, sum = 0
6581 12:46:14.020148 6, 0xFFFF, sum = 0
6582 12:46:14.020738 7, 0xFFFF, sum = 0
6583 12:46:14.023144 8, 0xFFFF, sum = 0
6584 12:46:14.023714 9, 0xFFFF, sum = 0
6585 12:46:14.026281 10, 0xFFFF, sum = 0
6586 12:46:14.026714 11, 0xFFFF, sum = 0
6587 12:46:14.029302 12, 0xFFFF, sum = 0
6588 12:46:14.029745 13, 0x0, sum = 1
6589 12:46:14.032904 14, 0x0, sum = 2
6590 12:46:14.033456 15, 0x0, sum = 3
6591 12:46:14.035812 16, 0x0, sum = 4
6592 12:46:14.036461 best_step = 14
6593 12:46:14.036976
6594 12:46:14.037331 ==
6595 12:46:14.039515 Dram Type= 6, Freq= 0, CH_0, rank 1
6596 12:46:14.042297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6597 12:46:14.042722 ==
6598 12:46:14.045925 RX Vref Scan: 0
6599 12:46:14.046345
6600 12:46:14.049032 RX Vref 0 -> 0, step: 1
6601 12:46:14.049611
6602 12:46:14.050070 RX Delay -311 -> 252, step: 8
6603 12:46:14.057792 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6604 12:46:14.061283 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6605 12:46:14.064711 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6606 12:46:14.067765 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6607 12:46:14.074405 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6608 12:46:14.077500 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6609 12:46:14.081006 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6610 12:46:14.084332 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6611 12:46:14.090938 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6612 12:46:14.094259 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6613 12:46:14.098082 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6614 12:46:14.101361 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6615 12:46:14.107990 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6616 12:46:14.111265 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6617 12:46:14.114519 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6618 12:46:14.121026 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6619 12:46:14.121513 ==
6620 12:46:14.124228 Dram Type= 6, Freq= 0, CH_0, rank 1
6621 12:46:14.127570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6622 12:46:14.128009 ==
6623 12:46:14.128599 DQS Delay:
6624 12:46:14.131448 DQS0 = 24, DQS1 = 32
6625 12:46:14.131943 DQM Delay:
6626 12:46:14.134564 DQM0 = 8, DQM1 = 10
6627 12:46:14.135155 DQ Delay:
6628 12:46:14.137812 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6629 12:46:14.141045 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6630 12:46:14.144374 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6631 12:46:14.147357 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6632 12:46:14.147820
6633 12:46:14.148439
6634 12:46:14.154052 [DQSOSCAuto] RK1, (LSB)MR18= 0xb556, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 387 ps
6635 12:46:14.157882 CH0 RK1: MR19=C0C, MR18=B556
6636 12:46:14.164395 CH0_RK1: MR19=0xC0C, MR18=0xB556, DQSOSC=387, MR23=63, INC=394, DEC=262
6637 12:46:14.167468 [RxdqsGatingPostProcess] freq 400
6638 12:46:14.171057 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6639 12:46:14.173927 best DQS0 dly(2T, 0.5T) = (0, 10)
6640 12:46:14.177184 best DQS1 dly(2T, 0.5T) = (0, 10)
6641 12:46:14.180879 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6642 12:46:14.184282 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6643 12:46:14.187687 best DQS0 dly(2T, 0.5T) = (0, 10)
6644 12:46:14.190485 best DQS1 dly(2T, 0.5T) = (0, 10)
6645 12:46:14.194232 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6646 12:46:14.197972 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6647 12:46:14.201139 Pre-setting of DQS Precalculation
6648 12:46:14.204352 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6649 12:46:14.207454 ==
6650 12:46:14.207875 Dram Type= 6, Freq= 0, CH_1, rank 0
6651 12:46:14.214106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 12:46:14.214531 ==
6653 12:46:14.217444 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6654 12:46:14.224040 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6655 12:46:14.227801 [CA 0] Center 36 (8~64) winsize 57
6656 12:46:14.231156 [CA 1] Center 36 (8~64) winsize 57
6657 12:46:14.234460 [CA 2] Center 36 (8~64) winsize 57
6658 12:46:14.237679 [CA 3] Center 36 (8~64) winsize 57
6659 12:46:14.240824 [CA 4] Center 36 (8~64) winsize 57
6660 12:46:14.243799 [CA 5] Center 36 (8~64) winsize 57
6661 12:46:14.244217
6662 12:46:14.247028 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6663 12:46:14.247458
6664 12:46:14.250596 [CATrainingPosCal] consider 1 rank data
6665 12:46:14.253850 u2DelayCellTimex100 = 270/100 ps
6666 12:46:14.257145 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 12:46:14.260959 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 12:46:14.263697 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 12:46:14.267114 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 12:46:14.270351 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 12:46:14.277276 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 12:46:14.277692
6673 12:46:14.280816 CA PerBit enable=1, Macro0, CA PI delay=36
6674 12:46:14.281325
6675 12:46:14.283938 [CBTSetCACLKResult] CA Dly = 36
6676 12:46:14.284393 CS Dly: 1 (0~32)
6677 12:46:14.284725 ==
6678 12:46:14.287628 Dram Type= 6, Freq= 0, CH_1, rank 1
6679 12:46:14.290527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6680 12:46:14.291024 ==
6681 12:46:14.297509 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6682 12:46:14.304096 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6683 12:46:14.307292 [CA 0] Center 36 (8~64) winsize 57
6684 12:46:14.310830 [CA 1] Center 36 (8~64) winsize 57
6685 12:46:14.313913 [CA 2] Center 36 (8~64) winsize 57
6686 12:46:14.317473 [CA 3] Center 36 (8~64) winsize 57
6687 12:46:14.320485 [CA 4] Center 36 (8~64) winsize 57
6688 12:46:14.320924 [CA 5] Center 36 (8~64) winsize 57
6689 12:46:14.323908
6690 12:46:14.327121 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6691 12:46:14.327595
6692 12:46:14.330994 [CATrainingPosCal] consider 2 rank data
6693 12:46:14.334237 u2DelayCellTimex100 = 270/100 ps
6694 12:46:14.337620 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 12:46:14.340898 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 12:46:14.344046 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 12:46:14.347255 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 12:46:14.350825 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 12:46:14.354119 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 12:46:14.354536
6701 12:46:14.357414 CA PerBit enable=1, Macro0, CA PI delay=36
6702 12:46:14.357885
6703 12:46:14.360787 [CBTSetCACLKResult] CA Dly = 36
6704 12:46:14.364164 CS Dly: 1 (0~32)
6705 12:46:14.364632
6706 12:46:14.367170 ----->DramcWriteLeveling(PI) begin...
6707 12:46:14.367622 ==
6708 12:46:14.370492 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 12:46:14.373547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 12:46:14.373971 ==
6711 12:46:14.377325 Write leveling (Byte 0): 40 => 8
6712 12:46:14.380216 Write leveling (Byte 1): 40 => 8
6713 12:46:14.384004 DramcWriteLeveling(PI) end<-----
6714 12:46:14.384468
6715 12:46:14.384807 ==
6716 12:46:14.387406 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 12:46:14.390083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 12:46:14.390506 ==
6719 12:46:14.393742 [Gating] SW mode calibration
6720 12:46:14.400087 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6721 12:46:14.407006 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6722 12:46:14.410143 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6723 12:46:14.413536 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6724 12:46:14.420091 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6725 12:46:14.423438 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6726 12:46:14.426790 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6727 12:46:14.433261 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6728 12:46:14.436969 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6729 12:46:14.440180 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6730 12:46:14.447051 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6731 12:46:14.447218 Total UI for P1: 0, mck2ui 16
6732 12:46:14.453471 best dqsien dly found for B0: ( 0, 14, 24)
6733 12:46:14.453686 Total UI for P1: 0, mck2ui 16
6734 12:46:14.460184 best dqsien dly found for B1: ( 0, 14, 24)
6735 12:46:14.463065 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6736 12:46:14.466442 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6737 12:46:14.466524
6738 12:46:14.469794 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6739 12:46:14.473077 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6740 12:46:14.476428 [Gating] SW calibration Done
6741 12:46:14.476509 ==
6742 12:46:14.479821 Dram Type= 6, Freq= 0, CH_1, rank 0
6743 12:46:14.483047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6744 12:46:14.483145 ==
6745 12:46:14.486234 RX Vref Scan: 0
6746 12:46:14.486333
6747 12:46:14.486428 RX Vref 0 -> 0, step: 1
6748 12:46:14.489781
6749 12:46:14.489861 RX Delay -410 -> 252, step: 16
6750 12:46:14.496077 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6751 12:46:14.499369 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6752 12:46:14.502452 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6753 12:46:14.509298 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6754 12:46:14.512770 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6755 12:46:14.515922 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6756 12:46:14.519098 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6757 12:46:14.522296 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6758 12:46:14.529054 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6759 12:46:14.532458 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6760 12:46:14.535720 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6761 12:46:14.542432 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6762 12:46:14.545734 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6763 12:46:14.549091 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6764 12:46:14.552468 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6765 12:46:14.559254 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6766 12:46:14.559338 ==
6767 12:46:14.562196 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 12:46:14.565836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 12:46:14.565918 ==
6770 12:46:14.565983 DQS Delay:
6771 12:46:14.568908 DQS0 = 27, DQS1 = 35
6772 12:46:14.569014 DQM Delay:
6773 12:46:14.572632 DQM0 = 10, DQM1 = 13
6774 12:46:14.572753 DQ Delay:
6775 12:46:14.575866 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =8
6776 12:46:14.578994 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6777 12:46:14.582538 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6778 12:46:14.586279 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6779 12:46:14.586358
6780 12:46:14.586421
6781 12:46:14.586480 ==
6782 12:46:14.589315 Dram Type= 6, Freq= 0, CH_1, rank 0
6783 12:46:14.592626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 12:46:14.592726 ==
6785 12:46:14.592815
6786 12:46:14.592900
6787 12:46:14.595376 TX Vref Scan disable
6788 12:46:14.595456 == TX Byte 0 ==
6789 12:46:14.602269 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6790 12:46:14.605424 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6791 12:46:14.605532 == TX Byte 1 ==
6792 12:46:14.612060 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6793 12:46:14.615434 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6794 12:46:14.615535 ==
6795 12:46:14.619105 Dram Type= 6, Freq= 0, CH_1, rank 0
6796 12:46:14.622100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 12:46:14.622187 ==
6798 12:46:14.622290
6799 12:46:14.622395
6800 12:46:14.625612 TX Vref Scan disable
6801 12:46:14.625708 == TX Byte 0 ==
6802 12:46:14.632465 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6803 12:46:14.635853 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6804 12:46:14.635994 == TX Byte 1 ==
6805 12:46:14.642773 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6806 12:46:14.645526 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6807 12:46:14.645610
6808 12:46:14.645697 [DATLAT]
6809 12:46:14.648830 Freq=400, CH1 RK0
6810 12:46:14.648930
6811 12:46:14.649019 DATLAT Default: 0xf
6812 12:46:14.652155 0, 0xFFFF, sum = 0
6813 12:46:14.652281 1, 0xFFFF, sum = 0
6814 12:46:14.655594 2, 0xFFFF, sum = 0
6815 12:46:14.655707 3, 0xFFFF, sum = 0
6816 12:46:14.659068 4, 0xFFFF, sum = 0
6817 12:46:14.659184 5, 0xFFFF, sum = 0
6818 12:46:14.662358 6, 0xFFFF, sum = 0
6819 12:46:14.662468 7, 0xFFFF, sum = 0
6820 12:46:14.665867 8, 0xFFFF, sum = 0
6821 12:46:14.665978 9, 0xFFFF, sum = 0
6822 12:46:14.668681 10, 0xFFFF, sum = 0
6823 12:46:14.672084 11, 0xFFFF, sum = 0
6824 12:46:14.672194 12, 0xFFFF, sum = 0
6825 12:46:14.675631 13, 0x0, sum = 1
6826 12:46:14.675715 14, 0x0, sum = 2
6827 12:46:14.679085 15, 0x0, sum = 3
6828 12:46:14.679168 16, 0x0, sum = 4
6829 12:46:14.679234 best_step = 14
6830 12:46:14.679295
6831 12:46:14.682328 ==
6832 12:46:14.682427 Dram Type= 6, Freq= 0, CH_1, rank 0
6833 12:46:14.688735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 12:46:14.688813 ==
6835 12:46:14.688876 RX Vref Scan: 1
6836 12:46:14.688935
6837 12:46:14.692244 RX Vref 0 -> 0, step: 1
6838 12:46:14.692363
6839 12:46:14.695698 RX Delay -311 -> 252, step: 8
6840 12:46:14.695811
6841 12:46:14.698688 Set Vref, RX VrefLevel [Byte0]: 52
6842 12:46:14.702022 [Byte1]: 52
6843 12:46:14.705513
6844 12:46:14.705604 Final RX Vref Byte 0 = 52 to rank0
6845 12:46:14.708782 Final RX Vref Byte 1 = 52 to rank0
6846 12:46:14.711788 Final RX Vref Byte 0 = 52 to rank1
6847 12:46:14.715441 Final RX Vref Byte 1 = 52 to rank1==
6848 12:46:14.718404 Dram Type= 6, Freq= 0, CH_1, rank 0
6849 12:46:14.725508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6850 12:46:14.725640 ==
6851 12:46:14.725754 DQS Delay:
6852 12:46:14.728737 DQS0 = 32, DQS1 = 32
6853 12:46:14.728819 DQM Delay:
6854 12:46:14.728885 DQM0 = 13, DQM1 = 10
6855 12:46:14.731727 DQ Delay:
6856 12:46:14.735409 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6857 12:46:14.735508 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
6858 12:46:14.738855 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6859 12:46:14.741682 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6860 12:46:14.741784
6861 12:46:14.745081
6862 12:46:14.752149 [DQSOSCAuto] RK0, (LSB)MR18= 0x8cc5, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6863 12:46:14.755585 CH1 RK0: MR19=C0C, MR18=8CC5
6864 12:46:14.762106 CH1_RK0: MR19=0xC0C, MR18=0x8CC5, DQSOSC=385, MR23=63, INC=398, DEC=265
6865 12:46:14.762210 ==
6866 12:46:14.765343 Dram Type= 6, Freq= 0, CH_1, rank 1
6867 12:46:14.768754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 12:46:14.768834 ==
6869 12:46:14.772151 [Gating] SW mode calibration
6870 12:46:14.778420 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6871 12:46:14.785360 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6872 12:46:14.788733 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6873 12:46:14.792046 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6874 12:46:14.795010 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6875 12:46:14.801700 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6876 12:46:14.805061 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6877 12:46:14.808305 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6878 12:46:14.815150 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6879 12:46:14.818634 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6880 12:46:14.822031 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6881 12:46:14.825387 Total UI for P1: 0, mck2ui 16
6882 12:46:14.828958 best dqsien dly found for B0: ( 0, 14, 24)
6883 12:46:14.831911 Total UI for P1: 0, mck2ui 16
6884 12:46:14.835021 best dqsien dly found for B1: ( 0, 14, 24)
6885 12:46:14.838245 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6886 12:46:14.841637 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6887 12:46:14.845246
6888 12:46:14.848401 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6889 12:46:14.851567 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6890 12:46:14.855287 [Gating] SW calibration Done
6891 12:46:14.855367 ==
6892 12:46:14.858377 Dram Type= 6, Freq= 0, CH_1, rank 1
6893 12:46:14.862007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6894 12:46:14.862115 ==
6895 12:46:14.862215 RX Vref Scan: 0
6896 12:46:14.862327
6897 12:46:14.864780 RX Vref 0 -> 0, step: 1
6898 12:46:14.864872
6899 12:46:14.868035 RX Delay -410 -> 252, step: 16
6900 12:46:14.871643 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6901 12:46:14.878027 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6902 12:46:14.881729 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6903 12:46:14.884954 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6904 12:46:14.888275 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6905 12:46:14.895107 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6906 12:46:14.898464 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6907 12:46:14.901353 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6908 12:46:14.904847 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6909 12:46:14.908267 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6910 12:46:14.914957 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6911 12:46:14.918412 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6912 12:46:14.921768 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6913 12:46:14.928483 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6914 12:46:14.931138 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6915 12:46:14.934675 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6916 12:46:14.934757 ==
6917 12:46:14.938119 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 12:46:14.941291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 12:46:14.944509 ==
6920 12:46:14.944592 DQS Delay:
6921 12:46:14.944660 DQS0 = 35, DQS1 = 35
6922 12:46:14.947734 DQM Delay:
6923 12:46:14.947837 DQM0 = 18, DQM1 = 15
6924 12:46:14.951785 DQ Delay:
6925 12:46:14.951875 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6926 12:46:14.954470 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6927 12:46:14.957858 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6928 12:46:14.961102 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6929 12:46:14.961184
6930 12:46:14.961249
6931 12:46:14.964276 ==
6932 12:46:14.968028 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 12:46:14.971326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 12:46:14.971439 ==
6935 12:46:14.971545
6936 12:46:14.971644
6937 12:46:14.974726 TX Vref Scan disable
6938 12:46:14.974860 == TX Byte 0 ==
6939 12:46:14.978448 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6940 12:46:14.984679 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6941 12:46:14.984761 == TX Byte 1 ==
6942 12:46:14.987747 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6943 12:46:14.991062 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6944 12:46:14.994378 ==
6945 12:46:14.998205 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 12:46:15.001477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 12:46:15.001599 ==
6948 12:46:15.001702
6949 12:46:15.001803
6950 12:46:15.004632 TX Vref Scan disable
6951 12:46:15.004718 == TX Byte 0 ==
6952 12:46:15.007788 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6953 12:46:15.014558 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6954 12:46:15.014674 == TX Byte 1 ==
6955 12:46:15.017784 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6956 12:46:15.021902 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6957 12:46:15.022004
6958 12:46:15.025193 [DATLAT]
6959 12:46:15.025294 Freq=400, CH1 RK1
6960 12:46:15.025390
6961 12:46:15.027780 DATLAT Default: 0xe
6962 12:46:15.027881 0, 0xFFFF, sum = 0
6963 12:46:15.031219 1, 0xFFFF, sum = 0
6964 12:46:15.031331 2, 0xFFFF, sum = 0
6965 12:46:15.034625 3, 0xFFFF, sum = 0
6966 12:46:15.034726 4, 0xFFFF, sum = 0
6967 12:46:15.038130 5, 0xFFFF, sum = 0
6968 12:46:15.038233 6, 0xFFFF, sum = 0
6969 12:46:15.041553 7, 0xFFFF, sum = 0
6970 12:46:15.044418 8, 0xFFFF, sum = 0
6971 12:46:15.044519 9, 0xFFFF, sum = 0
6972 12:46:15.047749 10, 0xFFFF, sum = 0
6973 12:46:15.047863 11, 0xFFFF, sum = 0
6974 12:46:15.051633 12, 0xFFFF, sum = 0
6975 12:46:15.051759 13, 0x0, sum = 1
6976 12:46:15.054342 14, 0x0, sum = 2
6977 12:46:15.054446 15, 0x0, sum = 3
6978 12:46:15.057745 16, 0x0, sum = 4
6979 12:46:15.057834 best_step = 14
6980 12:46:15.057899
6981 12:46:15.057958 ==
6982 12:46:15.061037 Dram Type= 6, Freq= 0, CH_1, rank 1
6983 12:46:15.064592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6984 12:46:15.064675 ==
6985 12:46:15.067899 RX Vref Scan: 0
6986 12:46:15.067980
6987 12:46:15.071149 RX Vref 0 -> 0, step: 1
6988 12:46:15.071231
6989 12:46:15.071295 RX Delay -311 -> 252, step: 8
6990 12:46:15.080051 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6991 12:46:15.082904 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6992 12:46:15.086320 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6993 12:46:15.093192 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6994 12:46:15.096434 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6995 12:46:15.099480 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6996 12:46:15.102832 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6997 12:46:15.106415 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6998 12:46:15.112998 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6999 12:46:15.116307 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
7000 12:46:15.119243 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
7001 12:46:15.122953 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
7002 12:46:15.129546 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
7003 12:46:15.133066 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7004 12:46:15.135970 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
7005 12:46:15.142888 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7006 12:46:15.142967 ==
7007 12:46:15.146270 Dram Type= 6, Freq= 0, CH_1, rank 1
7008 12:46:15.149791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7009 12:46:15.149875 ==
7010 12:46:15.149940 DQS Delay:
7011 12:46:15.152563 DQS0 = 28, DQS1 = 32
7012 12:46:15.152646 DQM Delay:
7013 12:46:15.156174 DQM0 = 11, DQM1 = 11
7014 12:46:15.156282 DQ Delay:
7015 12:46:15.159524 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7016 12:46:15.162691 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
7017 12:46:15.165977 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
7018 12:46:15.169405 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7019 12:46:15.169487
7020 12:46:15.169551
7021 12:46:15.176223 [DQSOSCAuto] RK1, (LSB)MR18= 0xc455, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
7022 12:46:15.179725 CH1 RK1: MR19=C0C, MR18=C455
7023 12:46:15.185906 CH1_RK1: MR19=0xC0C, MR18=0xC455, DQSOSC=385, MR23=63, INC=398, DEC=265
7024 12:46:15.189361 [RxdqsGatingPostProcess] freq 400
7025 12:46:15.196009 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7026 12:46:15.196120 best DQS0 dly(2T, 0.5T) = (0, 10)
7027 12:46:15.199468 best DQS1 dly(2T, 0.5T) = (0, 10)
7028 12:46:15.202418 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7029 12:46:15.205789 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7030 12:46:15.209350 best DQS0 dly(2T, 0.5T) = (0, 10)
7031 12:46:15.212102 best DQS1 dly(2T, 0.5T) = (0, 10)
7032 12:46:15.215674 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7033 12:46:15.218990 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7034 12:46:15.222110 Pre-setting of DQS Precalculation
7035 12:46:15.228978 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7036 12:46:15.235435 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7037 12:46:15.242142 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7038 12:46:15.242232
7039 12:46:15.242297
7040 12:46:15.245785 [Calibration Summary] 800 Mbps
7041 12:46:15.245862 CH 0, Rank 0
7042 12:46:15.248910 SW Impedance : PASS
7043 12:46:15.249014 DUTY Scan : NO K
7044 12:46:15.251975 ZQ Calibration : PASS
7045 12:46:15.255555 Jitter Meter : NO K
7046 12:46:15.255636 CBT Training : PASS
7047 12:46:15.258844 Write leveling : PASS
7048 12:46:15.261908 RX DQS gating : PASS
7049 12:46:15.261981 RX DQ/DQS(RDDQC) : PASS
7050 12:46:15.265286 TX DQ/DQS : PASS
7051 12:46:15.268847 RX DATLAT : PASS
7052 12:46:15.268954 RX DQ/DQS(Engine): PASS
7053 12:46:15.271972 TX OE : NO K
7054 12:46:15.272086 All Pass.
7055 12:46:15.272213
7056 12:46:15.275465 CH 0, Rank 1
7057 12:46:15.275567 SW Impedance : PASS
7058 12:46:15.278646 DUTY Scan : NO K
7059 12:46:15.282354 ZQ Calibration : PASS
7060 12:46:15.282471 Jitter Meter : NO K
7061 12:46:15.285561 CBT Training : PASS
7062 12:46:15.289009 Write leveling : NO K
7063 12:46:15.289134 RX DQS gating : PASS
7064 12:46:15.292400 RX DQ/DQS(RDDQC) : PASS
7065 12:46:15.292495 TX DQ/DQS : PASS
7066 12:46:15.295308 RX DATLAT : PASS
7067 12:46:15.298623 RX DQ/DQS(Engine): PASS
7068 12:46:15.298706 TX OE : NO K
7069 12:46:15.302022 All Pass.
7070 12:46:15.302102
7071 12:46:15.302170 CH 1, Rank 0
7072 12:46:15.305388 SW Impedance : PASS
7073 12:46:15.305490 DUTY Scan : NO K
7074 12:46:15.308789 ZQ Calibration : PASS
7075 12:46:15.312205 Jitter Meter : NO K
7076 12:46:15.312313 CBT Training : PASS
7077 12:46:15.315632 Write leveling : PASS
7078 12:46:15.318316 RX DQS gating : PASS
7079 12:46:15.318387 RX DQ/DQS(RDDQC) : PASS
7080 12:46:15.322427 TX DQ/DQS : PASS
7081 12:46:15.325621 RX DATLAT : PASS
7082 12:46:15.325703 RX DQ/DQS(Engine): PASS
7083 12:46:15.328991 TX OE : NO K
7084 12:46:15.329073 All Pass.
7085 12:46:15.329137
7086 12:46:15.331525 CH 1, Rank 1
7087 12:46:15.331606 SW Impedance : PASS
7088 12:46:15.335455 DUTY Scan : NO K
7089 12:46:15.338818 ZQ Calibration : PASS
7090 12:46:15.338900 Jitter Meter : NO K
7091 12:46:15.342118 CBT Training : PASS
7092 12:46:15.345184 Write leveling : NO K
7093 12:46:15.345266 RX DQS gating : PASS
7094 12:46:15.348100 RX DQ/DQS(RDDQC) : PASS
7095 12:46:15.351790 TX DQ/DQS : PASS
7096 12:46:15.351888 RX DATLAT : PASS
7097 12:46:15.355479 RX DQ/DQS(Engine): PASS
7098 12:46:15.355564 TX OE : NO K
7099 12:46:15.358701 All Pass.
7100 12:46:15.358782
7101 12:46:15.358846 DramC Write-DBI off
7102 12:46:15.361953 PER_BANK_REFRESH: Hybrid Mode
7103 12:46:15.365229 TX_TRACKING: ON
7104 12:46:15.371667 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7105 12:46:15.375121 [FAST_K] Save calibration result to emmc
7106 12:46:15.378451 dramc_set_vcore_voltage set vcore to 725000
7107 12:46:15.381988 Read voltage for 1600, 0
7108 12:46:15.382063 Vio18 = 0
7109 12:46:15.385105 Vcore = 725000
7110 12:46:15.385181 Vdram = 0
7111 12:46:15.385274 Vddq = 0
7112 12:46:15.388704 Vmddr = 0
7113 12:46:15.391632 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7114 12:46:15.398830 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7115 12:46:15.398915 MEM_TYPE=3, freq_sel=13
7116 12:46:15.402112 sv_algorithm_assistance_LP4_3733
7117 12:46:15.408714 ============ PULL DRAM RESETB DOWN ============
7118 12:46:15.411993 ========== PULL DRAM RESETB DOWN end =========
7119 12:46:15.415319 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7120 12:46:15.418677 ===================================
7121 12:46:15.422146 LPDDR4 DRAM CONFIGURATION
7122 12:46:15.425373 ===================================
7123 12:46:15.428017 EX_ROW_EN[0] = 0x0
7124 12:46:15.428095 EX_ROW_EN[1] = 0x0
7125 12:46:15.431339 LP4Y_EN = 0x0
7126 12:46:15.431414 WORK_FSP = 0x1
7127 12:46:15.434636 WL = 0x5
7128 12:46:15.434713 RL = 0x5
7129 12:46:15.438293 BL = 0x2
7130 12:46:15.438422 RPST = 0x0
7131 12:46:15.441553 RD_PRE = 0x0
7132 12:46:15.441657 WR_PRE = 0x1
7133 12:46:15.444789 WR_PST = 0x1
7134 12:46:15.444908 DBI_WR = 0x0
7135 12:46:15.448296 DBI_RD = 0x0
7136 12:46:15.448405 OTF = 0x1
7137 12:46:15.451658 ===================================
7138 12:46:15.454873 ===================================
7139 12:46:15.458296 ANA top config
7140 12:46:15.461256 ===================================
7141 12:46:15.465119 DLL_ASYNC_EN = 0
7142 12:46:15.465207 ALL_SLAVE_EN = 0
7143 12:46:15.468376 NEW_RANK_MODE = 1
7144 12:46:15.471714 DLL_IDLE_MODE = 1
7145 12:46:15.475017 LP45_APHY_COMB_EN = 1
7146 12:46:15.475137 TX_ODT_DIS = 0
7147 12:46:15.478398 NEW_8X_MODE = 1
7148 12:46:15.481869 ===================================
7149 12:46:15.484485 ===================================
7150 12:46:15.487930 data_rate = 3200
7151 12:46:15.491368 CKR = 1
7152 12:46:15.494770 DQ_P2S_RATIO = 8
7153 12:46:15.498219 ===================================
7154 12:46:15.501493 CA_P2S_RATIO = 8
7155 12:46:15.501599 DQ_CA_OPEN = 0
7156 12:46:15.504771 DQ_SEMI_OPEN = 0
7157 12:46:15.507927 CA_SEMI_OPEN = 0
7158 12:46:15.511602 CA_FULL_RATE = 0
7159 12:46:15.514755 DQ_CKDIV4_EN = 0
7160 12:46:15.514851 CA_CKDIV4_EN = 0
7161 12:46:15.518329 CA_PREDIV_EN = 0
7162 12:46:15.521237 PH8_DLY = 12
7163 12:46:15.524986 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7164 12:46:15.527965 DQ_AAMCK_DIV = 4
7165 12:46:15.531504 CA_AAMCK_DIV = 4
7166 12:46:15.531615 CA_ADMCK_DIV = 4
7167 12:46:15.534687 DQ_TRACK_CA_EN = 0
7168 12:46:15.538369 CA_PICK = 1600
7169 12:46:15.541588 CA_MCKIO = 1600
7170 12:46:15.545131 MCKIO_SEMI = 0
7171 12:46:15.548384 PLL_FREQ = 3068
7172 12:46:15.551614 DQ_UI_PI_RATIO = 32
7173 12:46:15.554910 CA_UI_PI_RATIO = 0
7174 12:46:15.558380 ===================================
7175 12:46:15.558480 ===================================
7176 12:46:15.561426 memory_type:LPDDR4
7177 12:46:15.564712 GP_NUM : 10
7178 12:46:15.564813 SRAM_EN : 1
7179 12:46:15.567739 MD32_EN : 0
7180 12:46:15.571389 ===================================
7181 12:46:15.574501 [ANA_INIT] >>>>>>>>>>>>>>
7182 12:46:15.578477 <<<<<< [CONFIGURE PHASE]: ANA_TX
7183 12:46:15.581724 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7184 12:46:15.584307 ===================================
7185 12:46:15.584443 data_rate = 3200,PCW = 0X7600
7186 12:46:15.587836 ===================================
7187 12:46:15.591194 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7188 12:46:15.598002 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7189 12:46:15.604814 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7190 12:46:15.608150 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7191 12:46:15.611462 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7192 12:46:15.614777 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7193 12:46:15.618143 [ANA_INIT] flow start
7194 12:46:15.620910 [ANA_INIT] PLL >>>>>>>>
7195 12:46:15.620991 [ANA_INIT] PLL <<<<<<<<
7196 12:46:15.624528 [ANA_INIT] MIDPI >>>>>>>>
7197 12:46:15.627829 [ANA_INIT] MIDPI <<<<<<<<
7198 12:46:15.627947 [ANA_INIT] DLL >>>>>>>>
7199 12:46:15.631317 [ANA_INIT] DLL <<<<<<<<
7200 12:46:15.634423 [ANA_INIT] flow end
7201 12:46:15.637932 ============ LP4 DIFF to SE enter ============
7202 12:46:15.641325 ============ LP4 DIFF to SE exit ============
7203 12:46:15.644743 [ANA_INIT] <<<<<<<<<<<<<
7204 12:46:15.647878 [Flow] Enable top DCM control >>>>>
7205 12:46:15.650756 [Flow] Enable top DCM control <<<<<
7206 12:46:15.654220 Enable DLL master slave shuffle
7207 12:46:15.657540 ==============================================================
7208 12:46:15.661298 Gating Mode config
7209 12:46:15.667820 ==============================================================
7210 12:46:15.667903 Config description:
7211 12:46:15.677759 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7212 12:46:15.684529 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7213 12:46:15.687499 SELPH_MODE 0: By rank 1: By Phase
7214 12:46:15.694097 ==============================================================
7215 12:46:15.697910 GAT_TRACK_EN = 1
7216 12:46:15.700760 RX_GATING_MODE = 2
7217 12:46:15.704160 RX_GATING_TRACK_MODE = 2
7218 12:46:15.707766 SELPH_MODE = 1
7219 12:46:15.711053 PICG_EARLY_EN = 1
7220 12:46:15.713829 VALID_LAT_VALUE = 1
7221 12:46:15.717395 ==============================================================
7222 12:46:15.720750 Enter into Gating configuration >>>>
7223 12:46:15.724066 Exit from Gating configuration <<<<
7224 12:46:15.727437 Enter into DVFS_PRE_config >>>>>
7225 12:46:15.740695 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7226 12:46:15.740780 Exit from DVFS_PRE_config <<<<<
7227 12:46:15.744113 Enter into PICG configuration >>>>
7228 12:46:15.747151 Exit from PICG configuration <<<<
7229 12:46:15.750457 [RX_INPUT] configuration >>>>>
7230 12:46:15.753854 [RX_INPUT] configuration <<<<<
7231 12:46:15.760516 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7232 12:46:15.763528 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7233 12:46:15.770309 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7234 12:46:15.777329 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7235 12:46:15.783875 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7236 12:46:15.790464 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7237 12:46:15.793608 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7238 12:46:15.796936 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7239 12:46:15.800190 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7240 12:46:15.807256 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7241 12:46:15.810589 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7242 12:46:15.813523 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7243 12:46:15.816843 ===================================
7244 12:46:15.820598 LPDDR4 DRAM CONFIGURATION
7245 12:46:15.823975 ===================================
7246 12:46:15.824057 EX_ROW_EN[0] = 0x0
7247 12:46:15.827215 EX_ROW_EN[1] = 0x0
7248 12:46:15.830535 LP4Y_EN = 0x0
7249 12:46:15.830644 WORK_FSP = 0x1
7250 12:46:15.833791 WL = 0x5
7251 12:46:15.833874 RL = 0x5
7252 12:46:15.837055 BL = 0x2
7253 12:46:15.837137 RPST = 0x0
7254 12:46:15.840393 RD_PRE = 0x0
7255 12:46:15.840475 WR_PRE = 0x1
7256 12:46:15.843818 WR_PST = 0x1
7257 12:46:15.843900 DBI_WR = 0x0
7258 12:46:15.846570 DBI_RD = 0x0
7259 12:46:15.846653 OTF = 0x1
7260 12:46:15.849913 ===================================
7261 12:46:15.853600 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7262 12:46:15.860192 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7263 12:46:15.863576 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7264 12:46:15.866834 ===================================
7265 12:46:15.870177 LPDDR4 DRAM CONFIGURATION
7266 12:46:15.873342 ===================================
7267 12:46:15.873450 EX_ROW_EN[0] = 0x10
7268 12:46:15.876627 EX_ROW_EN[1] = 0x0
7269 12:46:15.876703 LP4Y_EN = 0x0
7270 12:46:15.879904 WORK_FSP = 0x1
7271 12:46:15.883054 WL = 0x5
7272 12:46:15.883170 RL = 0x5
7273 12:46:15.886606 BL = 0x2
7274 12:46:15.886708 RPST = 0x0
7275 12:46:15.889767 RD_PRE = 0x0
7276 12:46:15.889874 WR_PRE = 0x1
7277 12:46:15.893473 WR_PST = 0x1
7278 12:46:15.893602 DBI_WR = 0x0
7279 12:46:15.896645 DBI_RD = 0x0
7280 12:46:15.896742 OTF = 0x1
7281 12:46:15.900109 ===================================
7282 12:46:15.906408 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7283 12:46:15.906491 ==
7284 12:46:15.910197 Dram Type= 6, Freq= 0, CH_0, rank 0
7285 12:46:15.913847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7286 12:46:15.913929 ==
7287 12:46:15.916422 [Duty_Offset_Calibration]
7288 12:46:15.920402 B0:2 B1:1 CA:1
7289 12:46:15.920484
7290 12:46:15.923500 [DutyScan_Calibration_Flow] k_type=0
7291 12:46:15.931612
7292 12:46:15.931687 ==CLK 0==
7293 12:46:15.934918 Final CLK duty delay cell = 0
7294 12:46:15.938448 [0] MAX Duty = 5187%(X100), DQS PI = 22
7295 12:46:15.941654 [0] MIN Duty = 4876%(X100), DQS PI = 48
7296 12:46:15.944802 [0] AVG Duty = 5031%(X100)
7297 12:46:15.944875
7298 12:46:15.948510 CH0 CLK Duty spec in!! Max-Min= 311%
7299 12:46:15.951349 [DutyScan_Calibration_Flow] ====Done====
7300 12:46:15.951511
7301 12:46:15.954498 [DutyScan_Calibration_Flow] k_type=1
7302 12:46:15.970918
7303 12:46:15.971037 ==DQS 0 ==
7304 12:46:15.974455 Final DQS duty delay cell = -4
7305 12:46:15.977152 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7306 12:46:15.980726 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7307 12:46:15.983988 [-4] AVG Duty = 4891%(X100)
7308 12:46:15.984058
7309 12:46:15.984118 ==DQS 1 ==
7310 12:46:15.987776 Final DQS duty delay cell = 0
7311 12:46:15.990879 [0] MAX Duty = 5187%(X100), DQS PI = 10
7312 12:46:15.994012 [0] MIN Duty = 5062%(X100), DQS PI = 30
7313 12:46:15.997851 [0] AVG Duty = 5124%(X100)
7314 12:46:15.997930
7315 12:46:16.001097 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7316 12:46:16.001187
7317 12:46:16.004246 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7318 12:46:16.007461 [DutyScan_Calibration_Flow] ====Done====
7319 12:46:16.007534
7320 12:46:16.010642 [DutyScan_Calibration_Flow] k_type=3
7321 12:46:16.028347
7322 12:46:16.028435 ==DQM 0 ==
7323 12:46:16.031663 Final DQM duty delay cell = 0
7324 12:46:16.034933 [0] MAX Duty = 5218%(X100), DQS PI = 34
7325 12:46:16.038190 [0] MIN Duty = 4907%(X100), DQS PI = 58
7326 12:46:16.041461 [0] AVG Duty = 5062%(X100)
7327 12:46:16.041545
7328 12:46:16.041612 ==DQM 1 ==
7329 12:46:16.045080 Final DQM duty delay cell = 0
7330 12:46:16.048068 [0] MAX Duty = 5187%(X100), DQS PI = 4
7331 12:46:16.051760 [0] MIN Duty = 5062%(X100), DQS PI = 14
7332 12:46:16.054864 [0] AVG Duty = 5124%(X100)
7333 12:46:16.054981
7334 12:46:16.058111 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7335 12:46:16.058215
7336 12:46:16.061619 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7337 12:46:16.064762 [DutyScan_Calibration_Flow] ====Done====
7338 12:46:16.064843
7339 12:46:16.068044 [DutyScan_Calibration_Flow] k_type=2
7340 12:46:16.085835
7341 12:46:16.085925 ==DQ 0 ==
7342 12:46:16.089140 Final DQ duty delay cell = 0
7343 12:46:16.092490 [0] MAX Duty = 5062%(X100), DQS PI = 24
7344 12:46:16.095217 [0] MIN Duty = 4907%(X100), DQS PI = 0
7345 12:46:16.095326 [0] AVG Duty = 4984%(X100)
7346 12:46:16.095418
7347 12:46:16.099133 ==DQ 1 ==
7348 12:46:16.102225 Final DQ duty delay cell = 0
7349 12:46:16.105295 [0] MAX Duty = 5125%(X100), DQS PI = 6
7350 12:46:16.109186 [0] MIN Duty = 4938%(X100), DQS PI = 34
7351 12:46:16.109258 [0] AVG Duty = 5031%(X100)
7352 12:46:16.109320
7353 12:46:16.112279 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7354 12:46:16.112393
7355 12:46:16.118906 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7356 12:46:16.122076 [DutyScan_Calibration_Flow] ====Done====
7357 12:46:16.122147 ==
7358 12:46:16.125511 Dram Type= 6, Freq= 0, CH_1, rank 0
7359 12:46:16.128933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7360 12:46:16.129013 ==
7361 12:46:16.131639 [Duty_Offset_Calibration]
7362 12:46:16.131717 B0:1 B1:0 CA:0
7363 12:46:16.131780
7364 12:46:16.135056 [DutyScan_Calibration_Flow] k_type=0
7365 12:46:16.145103
7366 12:46:16.145183 ==CLK 0==
7367 12:46:16.148456 Final CLK duty delay cell = -4
7368 12:46:16.151535 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7369 12:46:16.154695 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7370 12:46:16.158257 [-4] AVG Duty = 4922%(X100)
7371 12:46:16.158332
7372 12:46:16.161505 CH1 CLK Duty spec in!! Max-Min= 156%
7373 12:46:16.164795 [DutyScan_Calibration_Flow] ====Done====
7374 12:46:16.164870
7375 12:46:16.167939 [DutyScan_Calibration_Flow] k_type=1
7376 12:46:16.184455
7377 12:46:16.184532 ==DQS 0 ==
7378 12:46:16.188015 Final DQS duty delay cell = 0
7379 12:46:16.191589 [0] MAX Duty = 5094%(X100), DQS PI = 12
7380 12:46:16.194442 [0] MIN Duty = 4844%(X100), DQS PI = 48
7381 12:46:16.197918 [0] AVG Duty = 4969%(X100)
7382 12:46:16.197996
7383 12:46:16.198058 ==DQS 1 ==
7384 12:46:16.201114 Final DQS duty delay cell = 0
7385 12:46:16.204822 [0] MAX Duty = 5249%(X100), DQS PI = 18
7386 12:46:16.207933 [0] MIN Duty = 4969%(X100), DQS PI = 8
7387 12:46:16.208009 [0] AVG Duty = 5109%(X100)
7388 12:46:16.211075
7389 12:46:16.214956 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7390 12:46:16.215037
7391 12:46:16.218000 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7392 12:46:16.221354 [DutyScan_Calibration_Flow] ====Done====
7393 12:46:16.221435
7394 12:46:16.224526 [DutyScan_Calibration_Flow] k_type=3
7395 12:46:16.241548
7396 12:46:16.241630 ==DQM 0 ==
7397 12:46:16.244881 Final DQM duty delay cell = 0
7398 12:46:16.248121 [0] MAX Duty = 5187%(X100), DQS PI = 8
7399 12:46:16.251484 [0] MIN Duty = 4969%(X100), DQS PI = 48
7400 12:46:16.254784 [0] AVG Duty = 5078%(X100)
7401 12:46:16.254866
7402 12:46:16.254933 ==DQM 1 ==
7403 12:46:16.258120 Final DQM duty delay cell = 0
7404 12:46:16.261255 [0] MAX Duty = 5093%(X100), DQS PI = 16
7405 12:46:16.264925 [0] MIN Duty = 4907%(X100), DQS PI = 34
7406 12:46:16.268146 [0] AVG Duty = 5000%(X100)
7407 12:46:16.268256
7408 12:46:16.271564 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7409 12:46:16.271645
7410 12:46:16.274758 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7411 12:46:16.278201 [DutyScan_Calibration_Flow] ====Done====
7412 12:46:16.278283
7413 12:46:16.281443 [DutyScan_Calibration_Flow] k_type=2
7414 12:46:16.297491
7415 12:46:16.297589 ==DQ 0 ==
7416 12:46:16.301573 Final DQ duty delay cell = -4
7417 12:46:16.304220 [-4] MAX Duty = 5062%(X100), DQS PI = 10
7418 12:46:16.307511 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7419 12:46:16.311344 [-4] AVG Duty = 4968%(X100)
7420 12:46:16.311443
7421 12:46:16.311520 ==DQ 1 ==
7422 12:46:16.314621 Final DQ duty delay cell = 0
7423 12:46:16.317667 [0] MAX Duty = 5125%(X100), DQS PI = 18
7424 12:46:16.321035 [0] MIN Duty = 4938%(X100), DQS PI = 8
7425 12:46:16.321127 [0] AVG Duty = 5031%(X100)
7426 12:46:16.324216
7427 12:46:16.327838 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7428 12:46:16.327947
7429 12:46:16.331362 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7430 12:46:16.334151 [DutyScan_Calibration_Flow] ====Done====
7431 12:46:16.337648 nWR fixed to 30
7432 12:46:16.337726 [ModeRegInit_LP4] CH0 RK0
7433 12:46:16.341236 [ModeRegInit_LP4] CH0 RK1
7434 12:46:16.344278 [ModeRegInit_LP4] CH1 RK0
7435 12:46:16.347569 [ModeRegInit_LP4] CH1 RK1
7436 12:46:16.347647 match AC timing 5
7437 12:46:16.351084 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7438 12:46:16.357861 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7439 12:46:16.361090 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7440 12:46:16.367624 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7441 12:46:16.370820 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7442 12:46:16.370902 [MiockJmeterHQA]
7443 12:46:16.370966
7444 12:46:16.374225 [DramcMiockJmeter] u1RxGatingPI = 0
7445 12:46:16.377453 0 : 4253, 4026
7446 12:46:16.377535 4 : 4252, 4027
7447 12:46:16.380819 8 : 4252, 4027
7448 12:46:16.380902 12 : 4255, 4029
7449 12:46:16.380967 16 : 4253, 4027
7450 12:46:16.384105 20 : 4363, 4137
7451 12:46:16.384207 24 : 4363, 4138
7452 12:46:16.387487 28 : 4363, 4138
7453 12:46:16.387585 32 : 4253, 4027
7454 12:46:16.390763 36 : 4252, 4027
7455 12:46:16.390847 40 : 4252, 4027
7456 12:46:16.390930 44 : 4255, 4030
7457 12:46:16.394228 48 : 4363, 4137
7458 12:46:16.394435 52 : 4250, 4027
7459 12:46:16.397519 56 : 4250, 4027
7460 12:46:16.397644 60 : 4255, 4029
7461 12:46:16.400406 64 : 4250, 4027
7462 12:46:16.400497 68 : 4250, 4026
7463 12:46:16.403932 72 : 4361, 4137
7464 12:46:16.404039 76 : 4360, 4138
7465 12:46:16.404130 80 : 4361, 4138
7466 12:46:16.407392 84 : 4252, 4029
7467 12:46:16.407471 88 : 4250, 83
7468 12:46:16.410822 92 : 4250, 0
7469 12:46:16.410926 96 : 4360, 0
7470 12:46:16.411023 100 : 4252, 0
7471 12:46:16.414130 104 : 4360, 0
7472 12:46:16.414232 108 : 4249, 0
7473 12:46:16.417503 112 : 4250, 0
7474 12:46:16.417597 116 : 4250, 0
7475 12:46:16.417734 120 : 4252, 0
7476 12:46:16.420243 124 : 4360, 0
7477 12:46:16.420379 128 : 4361, 0
7478 12:46:16.423724 132 : 4363, 0
7479 12:46:16.423837 136 : 4250, 0
7480 12:46:16.423931 140 : 4250, 0
7481 12:46:16.427187 144 : 4250, 0
7482 12:46:16.427298 148 : 4250, 0
7483 12:46:16.430653 152 : 4252, 0
7484 12:46:16.430761 156 : 4250, 0
7485 12:46:16.430888 160 : 4252, 0
7486 12:46:16.433499 164 : 4250, 0
7487 12:46:16.433572 168 : 4250, 0
7488 12:46:16.433650 172 : 4253, 0
7489 12:46:16.437056 176 : 4360, 0
7490 12:46:16.437179 180 : 4250, 0
7491 12:46:16.440383 184 : 4361, 0
7492 12:46:16.440497 188 : 4250, 0
7493 12:46:16.440592 192 : 4255, 0
7494 12:46:16.443490 196 : 4249, 0
7495 12:46:16.443604 200 : 4250, 0
7496 12:46:16.447425 204 : 4253, 1317
7497 12:46:16.447523 208 : 4250, 4013
7498 12:46:16.450463 212 : 4363, 4140
7499 12:46:16.450558 216 : 4250, 4027
7500 12:46:16.453532 220 : 4250, 4027
7501 12:46:16.453610 224 : 4250, 4027
7502 12:46:16.453673 228 : 4252, 4030
7503 12:46:16.456698 232 : 4249, 4027
7504 12:46:16.456815 236 : 4360, 4137
7505 12:46:16.460228 240 : 4361, 4137
7506 12:46:16.460348 244 : 4250, 4027
7507 12:46:16.463743 248 : 4250, 4027
7508 12:46:16.463845 252 : 4252, 4029
7509 12:46:16.467479 256 : 4250, 4026
7510 12:46:16.467577 260 : 4250, 4027
7511 12:46:16.470095 264 : 4363, 4140
7512 12:46:16.470211 268 : 4250, 4027
7513 12:46:16.473477 272 : 4250, 4026
7514 12:46:16.473600 276 : 4360, 4138
7515 12:46:16.476900 280 : 4250, 4027
7516 12:46:16.477005 284 : 4250, 4027
7517 12:46:16.477114 288 : 4363, 4140
7518 12:46:16.480149 292 : 4361, 4137
7519 12:46:16.480268 296 : 4250, 4026
7520 12:46:16.483892 300 : 4250, 4027
7521 12:46:16.484023 304 : 4250, 4027
7522 12:46:16.486784 308 : 4252, 3935
7523 12:46:16.486898 312 : 4250, 2165
7524 12:46:16.490302 316 : 4363, 3
7525 12:46:16.490425
7526 12:46:16.490520 MIOCK jitter meter ch=0
7527 12:46:16.490607
7528 12:46:16.493422 1T = (316-88) = 228 dly cells
7529 12:46:16.500173 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7530 12:46:16.500293 ==
7531 12:46:16.503415 Dram Type= 6, Freq= 0, CH_0, rank 0
7532 12:46:16.506892 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7533 12:46:16.507006 ==
7534 12:46:16.513644 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7535 12:46:16.517045 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7536 12:46:16.520345 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7537 12:46:16.526826 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7538 12:46:16.536237 [CA 0] Center 42 (12~73) winsize 62
7539 12:46:16.539713 [CA 1] Center 42 (12~73) winsize 62
7540 12:46:16.543155 [CA 2] Center 37 (7~67) winsize 61
7541 12:46:16.546406 [CA 3] Center 37 (7~67) winsize 61
7542 12:46:16.550318 [CA 4] Center 36 (6~66) winsize 61
7543 12:46:16.553700 [CA 5] Center 35 (6~64) winsize 59
7544 12:46:16.553782
7545 12:46:16.556600 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7546 12:46:16.556682
7547 12:46:16.560377 [CATrainingPosCal] consider 1 rank data
7548 12:46:16.563679 u2DelayCellTimex100 = 285/100 ps
7549 12:46:16.566955 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7550 12:46:16.573256 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7551 12:46:16.576368 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7552 12:46:16.579784 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7553 12:46:16.582941 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7554 12:46:16.586316 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7555 12:46:16.586398
7556 12:46:16.589491 CA PerBit enable=1, Macro0, CA PI delay=35
7557 12:46:16.589576
7558 12:46:16.593382 [CBTSetCACLKResult] CA Dly = 35
7559 12:46:16.593480 CS Dly: 9 (0~40)
7560 12:46:16.599907 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7561 12:46:16.603248 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7562 12:46:16.603358 ==
7563 12:46:16.606464 Dram Type= 6, Freq= 0, CH_0, rank 1
7564 12:46:16.609736 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7565 12:46:16.609843 ==
7566 12:46:16.616375 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7567 12:46:16.619749 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7568 12:46:16.626149 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7569 12:46:16.629575 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7570 12:46:16.639682 [CA 0] Center 42 (12~73) winsize 62
7571 12:46:16.642920 [CA 1] Center 42 (12~73) winsize 62
7572 12:46:16.646415 [CA 2] Center 38 (8~68) winsize 61
7573 12:46:16.649624 [CA 3] Center 37 (7~67) winsize 61
7574 12:46:16.652845 [CA 4] Center 36 (6~66) winsize 61
7575 12:46:16.656131 [CA 5] Center 35 (5~65) winsize 61
7576 12:46:16.656206
7577 12:46:16.659608 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7578 12:46:16.659678
7579 12:46:16.663187 [CATrainingPosCal] consider 2 rank data
7580 12:46:16.666500 u2DelayCellTimex100 = 285/100 ps
7581 12:46:16.669790 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7582 12:46:16.676421 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7583 12:46:16.679660 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7584 12:46:16.683182 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7585 12:46:16.686389 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7586 12:46:16.689751 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7587 12:46:16.689827
7588 12:46:16.693090 CA PerBit enable=1, Macro0, CA PI delay=35
7589 12:46:16.693186
7590 12:46:16.696481 [CBTSetCACLKResult] CA Dly = 35
7591 12:46:16.699933 CS Dly: 10 (0~42)
7592 12:46:16.702722 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7593 12:46:16.705997 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7594 12:46:16.706109
7595 12:46:16.709318 ----->DramcWriteLeveling(PI) begin...
7596 12:46:16.709396 ==
7597 12:46:16.712680 Dram Type= 6, Freq= 0, CH_0, rank 0
7598 12:46:16.716042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7599 12:46:16.719514 ==
7600 12:46:16.719619 Write leveling (Byte 0): 35 => 35
7601 12:46:16.722827 Write leveling (Byte 1): 29 => 29
7602 12:46:16.726167 DramcWriteLeveling(PI) end<-----
7603 12:46:16.726283
7604 12:46:16.726355 ==
7605 12:46:16.729450 Dram Type= 6, Freq= 0, CH_0, rank 0
7606 12:46:16.735807 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7607 12:46:16.735914 ==
7608 12:46:16.739551 [Gating] SW mode calibration
7609 12:46:16.745940 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7610 12:46:16.749495 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7611 12:46:16.755788 1 4 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7612 12:46:16.759083 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7613 12:46:16.762546 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7614 12:46:16.769124 1 4 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
7615 12:46:16.772364 1 4 16 | B1->B0 | 2424 3636 | 1 0 | (1 1) (0 0)
7616 12:46:16.776115 1 4 20 | B1->B0 | 3333 3c3b | 0 1 | (1 1) (0 0)
7617 12:46:16.779375 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7618 12:46:16.786159 1 4 28 | B1->B0 | 3434 3939 | 1 0 | (1 1) (0 0)
7619 12:46:16.789440 1 5 0 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7620 12:46:16.792892 1 5 4 | B1->B0 | 3434 3837 | 1 1 | (1 1) (0 0)
7621 12:46:16.798980 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 1)
7622 12:46:16.802391 1 5 12 | B1->B0 | 3434 2625 | 1 1 | (1 1) (1 0)
7623 12:46:16.805673 1 5 16 | B1->B0 | 3333 2424 | 1 0 | (1 1) (1 0)
7624 12:46:16.812331 1 5 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7625 12:46:16.816214 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7626 12:46:16.818969 1 5 28 | B1->B0 | 2323 2928 | 0 1 | (0 0) (1 1)
7627 12:46:16.826214 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7628 12:46:16.829385 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7629 12:46:16.832780 1 6 8 | B1->B0 | 2323 3130 | 0 1 | (0 0) (0 0)
7630 12:46:16.839491 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7631 12:46:16.842132 1 6 16 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7632 12:46:16.845520 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7633 12:46:16.852325 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 12:46:16.855596 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 12:46:16.859002 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7636 12:46:16.865694 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7637 12:46:16.869363 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7638 12:46:16.872516 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7639 12:46:16.875721 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7640 12:46:16.882534 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7641 12:46:16.885875 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 12:46:16.889118 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 12:46:16.895654 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 12:46:16.899237 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 12:46:16.902637 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 12:46:16.908798 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 12:46:16.912407 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 12:46:16.915715 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 12:46:16.922313 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 12:46:16.925519 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 12:46:16.928854 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 12:46:16.936145 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 12:46:16.939391 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7654 12:46:16.942768 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7655 12:46:16.949420 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7656 12:46:16.949510 Total UI for P1: 0, mck2ui 16
7657 12:46:16.956123 best dqsien dly found for B0: ( 1, 9, 10)
7658 12:46:16.959265 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7659 12:46:16.962630 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7660 12:46:16.966054 Total UI for P1: 0, mck2ui 16
7661 12:46:16.969289 best dqsien dly found for B1: ( 1, 9, 18)
7662 12:46:16.972556 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7663 12:46:16.975660 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7664 12:46:16.975737
7665 12:46:16.979087 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7666 12:46:16.986127 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7667 12:46:16.986231 [Gating] SW calibration Done
7668 12:46:16.986339 ==
7669 12:46:16.989493 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 12:46:16.996053 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7671 12:46:16.996167 ==
7672 12:46:16.996269 RX Vref Scan: 0
7673 12:46:16.996345
7674 12:46:16.999077 RX Vref 0 -> 0, step: 1
7675 12:46:16.999151
7676 12:46:17.002600 RX Delay 0 -> 252, step: 8
7677 12:46:17.005641 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7678 12:46:17.008982 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7679 12:46:17.012494 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7680 12:46:17.019362 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7681 12:46:17.022099 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7682 12:46:17.025506 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7683 12:46:17.028940 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7684 12:46:17.032366 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7685 12:46:17.035619 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7686 12:46:17.042163 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7687 12:46:17.045599 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7688 12:46:17.048707 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7689 12:46:17.052099 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7690 12:46:17.055385 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7691 12:46:17.062044 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7692 12:46:17.065389 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7693 12:46:17.065472 ==
7694 12:46:17.068694 Dram Type= 6, Freq= 0, CH_0, rank 0
7695 12:46:17.072069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7696 12:46:17.072201 ==
7697 12:46:17.075910 DQS Delay:
7698 12:46:17.076008 DQS0 = 0, DQS1 = 0
7699 12:46:17.076119 DQM Delay:
7700 12:46:17.078574 DQM0 = 137, DQM1 = 131
7701 12:46:17.078669 DQ Delay:
7702 12:46:17.082477 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =135
7703 12:46:17.085783 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7704 12:46:17.089182 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7705 12:46:17.095709 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =135
7706 12:46:17.095841
7707 12:46:17.095967
7708 12:46:17.096091 ==
7709 12:46:17.099200 Dram Type= 6, Freq= 0, CH_0, rank 0
7710 12:46:17.102389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7711 12:46:17.102491 ==
7712 12:46:17.102589
7713 12:46:17.102683
7714 12:46:17.105674 TX Vref Scan disable
7715 12:46:17.105762 == TX Byte 0 ==
7716 12:46:17.112276 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7717 12:46:17.115381 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7718 12:46:17.115450 == TX Byte 1 ==
7719 12:46:17.121960 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7720 12:46:17.125458 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7721 12:46:17.125579 ==
7722 12:46:17.128805 Dram Type= 6, Freq= 0, CH_0, rank 0
7723 12:46:17.132212 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7724 12:46:17.132357 ==
7725 12:46:17.146796
7726 12:46:17.150239 TX Vref early break, caculate TX vref
7727 12:46:17.153202 TX Vref=16, minBit 4, minWin=22, winSum=381
7728 12:46:17.156667 TX Vref=18, minBit 3, minWin=23, winSum=388
7729 12:46:17.160015 TX Vref=20, minBit 7, minWin=23, winSum=398
7730 12:46:17.163117 TX Vref=22, minBit 1, minWin=24, winSum=408
7731 12:46:17.166553 TX Vref=24, minBit 2, minWin=25, winSum=416
7732 12:46:17.173261 TX Vref=26, minBit 3, minWin=25, winSum=424
7733 12:46:17.176928 TX Vref=28, minBit 6, minWin=25, winSum=425
7734 12:46:17.180156 TX Vref=30, minBit 7, minWin=24, winSum=413
7735 12:46:17.183596 TX Vref=32, minBit 6, minWin=23, winSum=403
7736 12:46:17.186537 TX Vref=34, minBit 1, minWin=23, winSum=391
7737 12:46:17.192942 [TxChooseVref] Worse bit 6, Min win 25, Win sum 425, Final Vref 28
7738 12:46:17.193029
7739 12:46:17.197158 Final TX Range 0 Vref 28
7740 12:46:17.197240
7741 12:46:17.197306 ==
7742 12:46:17.199646 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 12:46:17.203063 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7744 12:46:17.203145 ==
7745 12:46:17.203209
7746 12:46:17.203268
7747 12:46:17.206342 TX Vref Scan disable
7748 12:46:17.213108 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7749 12:46:17.213189 == TX Byte 0 ==
7750 12:46:17.216462 u2DelayCellOfst[0]=13 cells (4 PI)
7751 12:46:17.219973 u2DelayCellOfst[1]=13 cells (4 PI)
7752 12:46:17.223068 u2DelayCellOfst[2]=10 cells (3 PI)
7753 12:46:17.226275 u2DelayCellOfst[3]=10 cells (3 PI)
7754 12:46:17.229575 u2DelayCellOfst[4]=6 cells (2 PI)
7755 12:46:17.232765 u2DelayCellOfst[5]=0 cells (0 PI)
7756 12:46:17.236484 u2DelayCellOfst[6]=17 cells (5 PI)
7757 12:46:17.239793 u2DelayCellOfst[7]=13 cells (4 PI)
7758 12:46:17.242583 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7759 12:46:17.246035 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7760 12:46:17.249407 == TX Byte 1 ==
7761 12:46:17.249540 u2DelayCellOfst[8]=0 cells (0 PI)
7762 12:46:17.252952 u2DelayCellOfst[9]=0 cells (0 PI)
7763 12:46:17.256164 u2DelayCellOfst[10]=10 cells (3 PI)
7764 12:46:17.259519 u2DelayCellOfst[11]=3 cells (1 PI)
7765 12:46:17.263040 u2DelayCellOfst[12]=10 cells (3 PI)
7766 12:46:17.266424 u2DelayCellOfst[13]=10 cells (3 PI)
7767 12:46:17.269843 u2DelayCellOfst[14]=13 cells (4 PI)
7768 12:46:17.272571 u2DelayCellOfst[15]=10 cells (3 PI)
7769 12:46:17.276248 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7770 12:46:17.282708 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7771 12:46:17.282871 DramC Write-DBI on
7772 12:46:17.283003 ==
7773 12:46:17.285723 Dram Type= 6, Freq= 0, CH_0, rank 0
7774 12:46:17.289409 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7775 12:46:17.292710 ==
7776 12:46:17.292791
7777 12:46:17.292854
7778 12:46:17.292913 TX Vref Scan disable
7779 12:46:17.296111 == TX Byte 0 ==
7780 12:46:17.299484 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7781 12:46:17.302897 == TX Byte 1 ==
7782 12:46:17.305953 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7783 12:46:17.309372 DramC Write-DBI off
7784 12:46:17.309449
7785 12:46:17.309512 [DATLAT]
7786 12:46:17.309570 Freq=1600, CH0 RK0
7787 12:46:17.309627
7788 12:46:17.312918 DATLAT Default: 0xf
7789 12:46:17.313036 0, 0xFFFF, sum = 0
7790 12:46:17.316174 1, 0xFFFF, sum = 0
7791 12:46:17.316275 2, 0xFFFF, sum = 0
7792 12:46:17.319649 3, 0xFFFF, sum = 0
7793 12:46:17.323032 4, 0xFFFF, sum = 0
7794 12:46:17.323131 5, 0xFFFF, sum = 0
7795 12:46:17.326303 6, 0xFFFF, sum = 0
7796 12:46:17.326379 7, 0xFFFF, sum = 0
7797 12:46:17.329720 8, 0xFFFF, sum = 0
7798 12:46:17.329822 9, 0xFFFF, sum = 0
7799 12:46:17.332569 10, 0xFFFF, sum = 0
7800 12:46:17.332642 11, 0xFFFF, sum = 0
7801 12:46:17.336006 12, 0xFFFF, sum = 0
7802 12:46:17.336105 13, 0xFFFF, sum = 0
7803 12:46:17.339597 14, 0x0, sum = 1
7804 12:46:17.339678 15, 0x0, sum = 2
7805 12:46:17.342775 16, 0x0, sum = 3
7806 12:46:17.342870 17, 0x0, sum = 4
7807 12:46:17.346425 best_step = 15
7808 12:46:17.346551
7809 12:46:17.346643 ==
7810 12:46:17.349787 Dram Type= 6, Freq= 0, CH_0, rank 0
7811 12:46:17.353443 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7812 12:46:17.353527 ==
7813 12:46:17.353592 RX Vref Scan: 1
7814 12:46:17.353654
7815 12:46:17.355946 Set Vref Range= 24 -> 127
7816 12:46:17.356029
7817 12:46:17.359413 RX Vref 24 -> 127, step: 1
7818 12:46:17.359495
7819 12:46:17.362635 RX Delay 27 -> 252, step: 4
7820 12:46:17.362719
7821 12:46:17.366704 Set Vref, RX VrefLevel [Byte0]: 24
7822 12:46:17.369383 [Byte1]: 24
7823 12:46:17.369465
7824 12:46:17.372795 Set Vref, RX VrefLevel [Byte0]: 25
7825 12:46:17.376359 [Byte1]: 25
7826 12:46:17.376442
7827 12:46:17.379823 Set Vref, RX VrefLevel [Byte0]: 26
7828 12:46:17.382602 [Byte1]: 26
7829 12:46:17.386570
7830 12:46:17.386689 Set Vref, RX VrefLevel [Byte0]: 27
7831 12:46:17.389855 [Byte1]: 27
7832 12:46:17.393611
7833 12:46:17.393688 Set Vref, RX VrefLevel [Byte0]: 28
7834 12:46:17.397145 [Byte1]: 28
7835 12:46:17.401519
7836 12:46:17.401597 Set Vref, RX VrefLevel [Byte0]: 29
7837 12:46:17.404837 [Byte1]: 29
7838 12:46:17.408717
7839 12:46:17.408802 Set Vref, RX VrefLevel [Byte0]: 30
7840 12:46:17.412283 [Byte1]: 30
7841 12:46:17.416443
7842 12:46:17.416528 Set Vref, RX VrefLevel [Byte0]: 31
7843 12:46:17.419902 [Byte1]: 31
7844 12:46:17.423899
7845 12:46:17.423982 Set Vref, RX VrefLevel [Byte0]: 32
7846 12:46:17.427532 [Byte1]: 32
7847 12:46:17.431490
7848 12:46:17.431572 Set Vref, RX VrefLevel [Byte0]: 33
7849 12:46:17.434642 [Byte1]: 33
7850 12:46:17.438964
7851 12:46:17.439049 Set Vref, RX VrefLevel [Byte0]: 34
7852 12:46:17.442611 [Byte1]: 34
7853 12:46:17.446465
7854 12:46:17.446547 Set Vref, RX VrefLevel [Byte0]: 35
7855 12:46:17.449803 [Byte1]: 35
7856 12:46:17.454282
7857 12:46:17.454362 Set Vref, RX VrefLevel [Byte0]: 36
7858 12:46:17.457450 [Byte1]: 36
7859 12:46:17.461527
7860 12:46:17.461607 Set Vref, RX VrefLevel [Byte0]: 37
7861 12:46:17.464738 [Byte1]: 37
7862 12:46:17.469167
7863 12:46:17.469244 Set Vref, RX VrefLevel [Byte0]: 38
7864 12:46:17.472629 [Byte1]: 38
7865 12:46:17.476625
7866 12:46:17.476699 Set Vref, RX VrefLevel [Byte0]: 39
7867 12:46:17.479801 [Byte1]: 39
7868 12:46:17.484524
7869 12:46:17.484606 Set Vref, RX VrefLevel [Byte0]: 40
7870 12:46:17.487828 [Byte1]: 40
7871 12:46:17.491632
7872 12:46:17.491708 Set Vref, RX VrefLevel [Byte0]: 41
7873 12:46:17.494944 [Byte1]: 41
7874 12:46:17.499497
7875 12:46:17.499574 Set Vref, RX VrefLevel [Byte0]: 42
7876 12:46:17.502857 [Byte1]: 42
7877 12:46:17.506702
7878 12:46:17.506776 Set Vref, RX VrefLevel [Byte0]: 43
7879 12:46:17.510121 [Byte1]: 43
7880 12:46:17.514176
7881 12:46:17.514256 Set Vref, RX VrefLevel [Byte0]: 44
7882 12:46:17.517573 [Byte1]: 44
7883 12:46:17.522131
7884 12:46:17.522211 Set Vref, RX VrefLevel [Byte0]: 45
7885 12:46:17.525565 [Byte1]: 45
7886 12:46:17.529410
7887 12:46:17.529490 Set Vref, RX VrefLevel [Byte0]: 46
7888 12:46:17.532622 [Byte1]: 46
7889 12:46:17.537346
7890 12:46:17.537426 Set Vref, RX VrefLevel [Byte0]: 47
7891 12:46:17.540076 [Byte1]: 47
7892 12:46:17.544486
7893 12:46:17.544626 Set Vref, RX VrefLevel [Byte0]: 48
7894 12:46:17.548106 [Byte1]: 48
7895 12:46:17.551861
7896 12:46:17.551977 Set Vref, RX VrefLevel [Byte0]: 49
7897 12:46:17.555084 [Byte1]: 49
7898 12:46:17.559670
7899 12:46:17.559760 Set Vref, RX VrefLevel [Byte0]: 50
7900 12:46:17.562963 [Byte1]: 50
7901 12:46:17.567016
7902 12:46:17.567101 Set Vref, RX VrefLevel [Byte0]: 51
7903 12:46:17.570358 [Byte1]: 51
7904 12:46:17.574668
7905 12:46:17.574770 Set Vref, RX VrefLevel [Byte0]: 52
7906 12:46:17.577981 [Byte1]: 52
7907 12:46:17.582099
7908 12:46:17.582167 Set Vref, RX VrefLevel [Byte0]: 53
7909 12:46:17.585481 [Byte1]: 53
7910 12:46:17.589453
7911 12:46:17.589533 Set Vref, RX VrefLevel [Byte0]: 54
7912 12:46:17.592812 [Byte1]: 54
7913 12:46:17.597538
7914 12:46:17.597621 Set Vref, RX VrefLevel [Byte0]: 55
7915 12:46:17.600710 [Byte1]: 55
7916 12:46:17.605087
7917 12:46:17.605167 Set Vref, RX VrefLevel [Byte0]: 56
7918 12:46:17.608350 [Byte1]: 56
7919 12:46:17.612322
7920 12:46:17.612416 Set Vref, RX VrefLevel [Byte0]: 57
7921 12:46:17.615562 [Byte1]: 57
7922 12:46:17.619763
7923 12:46:17.619842 Set Vref, RX VrefLevel [Byte0]: 58
7924 12:46:17.623213 [Byte1]: 58
7925 12:46:17.627585
7926 12:46:17.627664 Set Vref, RX VrefLevel [Byte0]: 59
7927 12:46:17.630885 [Byte1]: 59
7928 12:46:17.635015
7929 12:46:17.635094 Set Vref, RX VrefLevel [Byte0]: 60
7930 12:46:17.638426 [Byte1]: 60
7931 12:46:17.642547
7932 12:46:17.642627 Set Vref, RX VrefLevel [Byte0]: 61
7933 12:46:17.645894 [Byte1]: 61
7934 12:46:17.649885
7935 12:46:17.649966 Set Vref, RX VrefLevel [Byte0]: 62
7936 12:46:17.653268 [Byte1]: 62
7937 12:46:17.658094
7938 12:46:17.658173 Set Vref, RX VrefLevel [Byte0]: 63
7939 12:46:17.660599 [Byte1]: 63
7940 12:46:17.664806
7941 12:46:17.664906 Set Vref, RX VrefLevel [Byte0]: 64
7942 12:46:17.668312 [Byte1]: 64
7943 12:46:17.672921
7944 12:46:17.673000 Set Vref, RX VrefLevel [Byte0]: 65
7945 12:46:17.675637 [Byte1]: 65
7946 12:46:17.680008
7947 12:46:17.680112 Set Vref, RX VrefLevel [Byte0]: 66
7948 12:46:17.683266 [Byte1]: 66
7949 12:46:17.687847
7950 12:46:17.687924 Set Vref, RX VrefLevel [Byte0]: 67
7951 12:46:17.691079 [Byte1]: 67
7952 12:46:17.695303
7953 12:46:17.695382 Set Vref, RX VrefLevel [Byte0]: 68
7954 12:46:17.698637 [Byte1]: 68
7955 12:46:17.702596
7956 12:46:17.702701 Set Vref, RX VrefLevel [Byte0]: 69
7957 12:46:17.705840 [Byte1]: 69
7958 12:46:17.710534
7959 12:46:17.710613 Set Vref, RX VrefLevel [Byte0]: 70
7960 12:46:17.713889 [Byte1]: 70
7961 12:46:17.718498
7962 12:46:17.719036 Set Vref, RX VrefLevel [Byte0]: 71
7963 12:46:17.721886 [Byte1]: 71
7964 12:46:17.725585
7965 12:46:17.725994 Set Vref, RX VrefLevel [Byte0]: 72
7966 12:46:17.728871 [Byte1]: 72
7967 12:46:17.733897
7968 12:46:17.734406 Set Vref, RX VrefLevel [Byte0]: 73
7969 12:46:17.737292 [Byte1]: 73
7970 12:46:17.741145
7971 12:46:17.741660 Final RX Vref Byte 0 = 56 to rank0
7972 12:46:17.744380 Final RX Vref Byte 1 = 62 to rank0
7973 12:46:17.747698 Final RX Vref Byte 0 = 56 to rank1
7974 12:46:17.751172 Final RX Vref Byte 1 = 62 to rank1==
7975 12:46:17.754182 Dram Type= 6, Freq= 0, CH_0, rank 0
7976 12:46:17.761281 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7977 12:46:17.761844 ==
7978 12:46:17.762204 DQS Delay:
7979 12:46:17.762538 DQS0 = 0, DQS1 = 0
7980 12:46:17.764498 DQM Delay:
7981 12:46:17.765055 DQM0 = 133, DQM1 = 127
7982 12:46:17.767232 DQ Delay:
7983 12:46:17.770520 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130
7984 12:46:17.773917 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138
7985 12:46:17.777111 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7986 12:46:17.780492 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7987 12:46:17.781004
7988 12:46:17.781329
7989 12:46:17.781630
7990 12:46:17.783492 [DramC_TX_OE_Calibration] TA2
7991 12:46:17.787498 Original DQ_B0 (3 6) =30, OEN = 27
7992 12:46:17.790621 Original DQ_B1 (3 6) =30, OEN = 27
7993 12:46:17.794007 24, 0x0, End_B0=24 End_B1=24
7994 12:46:17.794519 25, 0x0, End_B0=25 End_B1=25
7995 12:46:17.797198 26, 0x0, End_B0=26 End_B1=26
7996 12:46:17.800433 27, 0x0, End_B0=27 End_B1=27
7997 12:46:17.803689 28, 0x0, End_B0=28 End_B1=28
7998 12:46:17.804103 29, 0x0, End_B0=29 End_B1=29
7999 12:46:17.807431 30, 0x0, End_B0=30 End_B1=30
8000 12:46:17.810440 31, 0x4141, End_B0=30 End_B1=30
8001 12:46:17.814072 Byte0 end_step=30 best_step=27
8002 12:46:17.816949 Byte1 end_step=30 best_step=27
8003 12:46:17.820603 Byte0 TX OE(2T, 0.5T) = (3, 3)
8004 12:46:17.821016 Byte1 TX OE(2T, 0.5T) = (3, 3)
8005 12:46:17.823753
8006 12:46:17.824157
8007 12:46:17.830680 [DQSOSCAuto] RK0, (LSB)MR18= 0x231e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 392 ps
8008 12:46:17.834017 CH0 RK0: MR19=303, MR18=231E
8009 12:46:17.840313 CH0_RK0: MR19=0x303, MR18=0x231E, DQSOSC=392, MR23=63, INC=24, DEC=16
8010 12:46:17.840730
8011 12:46:17.844068 ----->DramcWriteLeveling(PI) begin...
8012 12:46:17.844586 ==
8013 12:46:17.847360 Dram Type= 6, Freq= 0, CH_0, rank 1
8014 12:46:17.850673 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8015 12:46:17.851123 ==
8016 12:46:17.853862 Write leveling (Byte 0): 36 => 36
8017 12:46:17.857437 Write leveling (Byte 1): 26 => 26
8018 12:46:17.860120 DramcWriteLeveling(PI) end<-----
8019 12:46:17.860577
8020 12:46:17.860904 ==
8021 12:46:17.863445 Dram Type= 6, Freq= 0, CH_0, rank 1
8022 12:46:17.866918 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8023 12:46:17.867356 ==
8024 12:46:17.870209 [Gating] SW mode calibration
8025 12:46:17.876881 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8026 12:46:17.883465 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8027 12:46:17.886770 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8028 12:46:17.890018 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8029 12:46:17.896370 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 12:46:17.899911 1 4 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
8031 12:46:17.903248 1 4 16 | B1->B0 | 2929 3535 | 0 0 | (0 0) (1 1)
8032 12:46:17.910518 1 4 20 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
8033 12:46:17.913699 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
8034 12:46:17.917002 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8035 12:46:17.923220 1 5 0 | B1->B0 | 3434 3635 | 1 1 | (1 1) (1 1)
8036 12:46:17.926575 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8037 12:46:17.930144 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8038 12:46:17.936826 1 5 12 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
8039 12:46:17.939844 1 5 16 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (1 0)
8040 12:46:17.943536 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8041 12:46:17.949713 1 5 24 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
8042 12:46:17.953004 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8043 12:46:17.956405 1 6 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8044 12:46:17.963036 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8045 12:46:17.966838 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8046 12:46:17.970157 1 6 12 | B1->B0 | 2525 3838 | 0 1 | (0 0) (0 0)
8047 12:46:17.976857 1 6 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
8048 12:46:17.979628 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8049 12:46:17.982813 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8050 12:46:17.986690 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8051 12:46:17.993131 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8052 12:46:17.996669 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 12:46:17.999856 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8054 12:46:18.006511 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8055 12:46:18.009841 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8056 12:46:18.013042 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8057 12:46:18.019689 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 12:46:18.023545 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 12:46:18.026306 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 12:46:18.033191 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 12:46:18.036973 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 12:46:18.039960 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 12:46:18.046673 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 12:46:18.049915 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 12:46:18.053209 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 12:46:18.059778 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 12:46:18.063489 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 12:46:18.066970 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 12:46:18.073376 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 12:46:18.076596 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8071 12:46:18.079922 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8072 12:46:18.083362 Total UI for P1: 0, mck2ui 16
8073 12:46:18.086634 best dqsien dly found for B0: ( 1, 9, 12)
8074 12:46:18.090437 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8075 12:46:18.093527 Total UI for P1: 0, mck2ui 16
8076 12:46:18.096666 best dqsien dly found for B1: ( 1, 9, 14)
8077 12:46:18.099927 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8078 12:46:18.103548 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8079 12:46:18.106946
8080 12:46:18.110041 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8081 12:46:18.113484 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8082 12:46:18.116711 [Gating] SW calibration Done
8083 12:46:18.117135 ==
8084 12:46:18.119909 Dram Type= 6, Freq= 0, CH_0, rank 1
8085 12:46:18.123059 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8086 12:46:18.123505 ==
8087 12:46:18.126404 RX Vref Scan: 0
8088 12:46:18.126824
8089 12:46:18.127189 RX Vref 0 -> 0, step: 1
8090 12:46:18.127537
8091 12:46:18.129881 RX Delay 0 -> 252, step: 8
8092 12:46:18.133200 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8093 12:46:18.136762 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8094 12:46:18.143207 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8095 12:46:18.146542 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8096 12:46:18.149709 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8097 12:46:18.152882 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8098 12:46:18.156152 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8099 12:46:18.162858 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8100 12:46:18.166246 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8101 12:46:18.169508 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8102 12:46:18.172998 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8103 12:46:18.176548 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8104 12:46:18.182614 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8105 12:46:18.186254 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8106 12:46:18.189675 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8107 12:46:18.192884 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8108 12:46:18.193111 ==
8109 12:46:18.195920 Dram Type= 6, Freq= 0, CH_0, rank 1
8110 12:46:18.202854 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8111 12:46:18.203014 ==
8112 12:46:18.203134 DQS Delay:
8113 12:46:18.206178 DQS0 = 0, DQS1 = 0
8114 12:46:18.206329 DQM Delay:
8115 12:46:18.209053 DQM0 = 136, DQM1 = 129
8116 12:46:18.209205 DQ Delay:
8117 12:46:18.212643 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8118 12:46:18.216100 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8119 12:46:18.219526 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =123
8120 12:46:18.222607 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8121 12:46:18.222801
8122 12:46:18.222932
8123 12:46:18.223052 ==
8124 12:46:18.225744 Dram Type= 6, Freq= 0, CH_0, rank 1
8125 12:46:18.232801 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8126 12:46:18.233041 ==
8127 12:46:18.233175
8128 12:46:18.233290
8129 12:46:18.233400 TX Vref Scan disable
8130 12:46:18.236017 == TX Byte 0 ==
8131 12:46:18.239359 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8132 12:46:18.246191 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8133 12:46:18.246483 == TX Byte 1 ==
8134 12:46:18.249348 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8135 12:46:18.256004 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8136 12:46:18.256350 ==
8137 12:46:18.258830 Dram Type= 6, Freq= 0, CH_0, rank 1
8138 12:46:18.262163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8139 12:46:18.262549 ==
8140 12:46:18.276114
8141 12:46:18.279708 TX Vref early break, caculate TX vref
8142 12:46:18.282983 TX Vref=16, minBit 1, minWin=23, winSum=387
8143 12:46:18.286311 TX Vref=18, minBit 1, minWin=22, winSum=393
8144 12:46:18.289140 TX Vref=20, minBit 1, minWin=24, winSum=405
8145 12:46:18.292710 TX Vref=22, minBit 1, minWin=24, winSum=411
8146 12:46:18.296175 TX Vref=24, minBit 4, minWin=24, winSum=414
8147 12:46:18.303517 TX Vref=26, minBit 3, minWin=25, winSum=426
8148 12:46:18.306351 TX Vref=28, minBit 3, minWin=25, winSum=425
8149 12:46:18.309193 TX Vref=30, minBit 0, minWin=25, winSum=416
8150 12:46:18.312890 TX Vref=32, minBit 0, minWin=24, winSum=408
8151 12:46:18.316138 TX Vref=34, minBit 0, minWin=24, winSum=401
8152 12:46:18.322954 [TxChooseVref] Worse bit 3, Min win 25, Win sum 426, Final Vref 26
8153 12:46:18.323418
8154 12:46:18.325905 Final TX Range 0 Vref 26
8155 12:46:18.326473
8156 12:46:18.326844 ==
8157 12:46:18.329080 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 12:46:18.333222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 12:46:18.333783 ==
8160 12:46:18.334149
8161 12:46:18.334482
8162 12:46:18.336172 TX Vref Scan disable
8163 12:46:18.342561 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8164 12:46:18.343022 == TX Byte 0 ==
8165 12:46:18.346061 u2DelayCellOfst[0]=10 cells (3 PI)
8166 12:46:18.349289 u2DelayCellOfst[1]=13 cells (4 PI)
8167 12:46:18.353239 u2DelayCellOfst[2]=10 cells (3 PI)
8168 12:46:18.356478 u2DelayCellOfst[3]=10 cells (3 PI)
8169 12:46:18.359578 u2DelayCellOfst[4]=6 cells (2 PI)
8170 12:46:18.362886 u2DelayCellOfst[5]=0 cells (0 PI)
8171 12:46:18.365895 u2DelayCellOfst[6]=13 cells (4 PI)
8172 12:46:18.366377 u2DelayCellOfst[7]=13 cells (4 PI)
8173 12:46:18.372590 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8174 12:46:18.375960 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8175 12:46:18.376578 == TX Byte 1 ==
8176 12:46:18.379490 u2DelayCellOfst[8]=0 cells (0 PI)
8177 12:46:18.382610 u2DelayCellOfst[9]=0 cells (0 PI)
8178 12:46:18.386355 u2DelayCellOfst[10]=6 cells (2 PI)
8179 12:46:18.389037 u2DelayCellOfst[11]=3 cells (1 PI)
8180 12:46:18.392275 u2DelayCellOfst[12]=10 cells (3 PI)
8181 12:46:18.396025 u2DelayCellOfst[13]=13 cells (4 PI)
8182 12:46:18.399538 u2DelayCellOfst[14]=13 cells (4 PI)
8183 12:46:18.402774 u2DelayCellOfst[15]=10 cells (3 PI)
8184 12:46:18.405645 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8185 12:46:18.412441 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8186 12:46:18.412860 DramC Write-DBI on
8187 12:46:18.413186 ==
8188 12:46:18.415470 Dram Type= 6, Freq= 0, CH_0, rank 1
8189 12:46:18.419216 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8190 12:46:18.419641 ==
8191 12:46:18.422517
8192 12:46:18.422939
8193 12:46:18.423468 TX Vref Scan disable
8194 12:46:18.426042 == TX Byte 0 ==
8195 12:46:18.429132 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8196 12:46:18.432548 == TX Byte 1 ==
8197 12:46:18.436394 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8198 12:46:18.439166 DramC Write-DBI off
8199 12:46:18.439688
8200 12:46:18.440021 [DATLAT]
8201 12:46:18.440379 Freq=1600, CH0 RK1
8202 12:46:18.440694
8203 12:46:18.442136 DATLAT Default: 0xf
8204 12:46:18.442555 0, 0xFFFF, sum = 0
8205 12:46:18.446077 1, 0xFFFF, sum = 0
8206 12:46:18.449075 2, 0xFFFF, sum = 0
8207 12:46:18.449508 3, 0xFFFF, sum = 0
8208 12:46:18.452117 4, 0xFFFF, sum = 0
8209 12:46:18.452595 5, 0xFFFF, sum = 0
8210 12:46:18.455408 6, 0xFFFF, sum = 0
8211 12:46:18.455832 7, 0xFFFF, sum = 0
8212 12:46:18.458674 8, 0xFFFF, sum = 0
8213 12:46:18.459103 9, 0xFFFF, sum = 0
8214 12:46:18.462135 10, 0xFFFF, sum = 0
8215 12:46:18.462560 11, 0xFFFF, sum = 0
8216 12:46:18.465464 12, 0xFFFF, sum = 0
8217 12:46:18.465982 13, 0xFFFF, sum = 0
8218 12:46:18.469005 14, 0x0, sum = 1
8219 12:46:18.469431 15, 0x0, sum = 2
8220 12:46:18.472188 16, 0x0, sum = 3
8221 12:46:18.472696 17, 0x0, sum = 4
8222 12:46:18.475640 best_step = 15
8223 12:46:18.476057
8224 12:46:18.476431 ==
8225 12:46:18.479271 Dram Type= 6, Freq= 0, CH_0, rank 1
8226 12:46:18.482567 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8227 12:46:18.483086 ==
8228 12:46:18.485850 RX Vref Scan: 0
8229 12:46:18.486273
8230 12:46:18.486601 RX Vref 0 -> 0, step: 1
8231 12:46:18.486906
8232 12:46:18.488859 RX Delay 19 -> 252, step: 4
8233 12:46:18.492408 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8234 12:46:18.498844 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8235 12:46:18.502108 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8236 12:46:18.505245 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8237 12:46:18.508388 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8238 12:46:18.512165 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8239 12:46:18.518345 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8240 12:46:18.522208 iDelay=191, Bit 7, Center 142 (95 ~ 190) 96
8241 12:46:18.524980 iDelay=191, Bit 8, Center 120 (71 ~ 170) 100
8242 12:46:18.528034 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8243 12:46:18.531915 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8244 12:46:18.537992 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8245 12:46:18.541357 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8246 12:46:18.545151 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8247 12:46:18.548402 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8248 12:46:18.554951 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8249 12:46:18.555418 ==
8250 12:46:18.557951 Dram Type= 6, Freq= 0, CH_0, rank 1
8251 12:46:18.561689 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8252 12:46:18.562251 ==
8253 12:46:18.562596 DQS Delay:
8254 12:46:18.564713 DQS0 = 0, DQS1 = 0
8255 12:46:18.565241 DQM Delay:
8256 12:46:18.567645 DQM0 = 134, DQM1 = 127
8257 12:46:18.568068 DQ Delay:
8258 12:46:18.571257 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =132
8259 12:46:18.574882 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =142
8260 12:46:18.577616 DQ8 =120, DQ9 =116, DQ10 =128, DQ11 =118
8261 12:46:18.581273 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8262 12:46:18.581726
8263 12:46:18.582054
8264 12:46:18.584642
8265 12:46:18.585054 [DramC_TX_OE_Calibration] TA2
8266 12:46:18.588182 Original DQ_B0 (3 6) =30, OEN = 27
8267 12:46:18.591398 Original DQ_B1 (3 6) =30, OEN = 27
8268 12:46:18.594538 24, 0x0, End_B0=24 End_B1=24
8269 12:46:18.597832 25, 0x0, End_B0=25 End_B1=25
8270 12:46:18.601053 26, 0x0, End_B0=26 End_B1=26
8271 12:46:18.601521 27, 0x0, End_B0=27 End_B1=27
8272 12:46:18.604062 28, 0x0, End_B0=28 End_B1=28
8273 12:46:18.607863 29, 0x0, End_B0=29 End_B1=29
8274 12:46:18.611084 30, 0x0, End_B0=30 End_B1=30
8275 12:46:18.614458 31, 0x4545, End_B0=30 End_B1=30
8276 12:46:18.614878 Byte0 end_step=30 best_step=27
8277 12:46:18.617890 Byte1 end_step=30 best_step=27
8278 12:46:18.621049 Byte0 TX OE(2T, 0.5T) = (3, 3)
8279 12:46:18.624327 Byte1 TX OE(2T, 0.5T) = (3, 3)
8280 12:46:18.624873
8281 12:46:18.625238
8282 12:46:18.630703 [DQSOSCAuto] RK1, (LSB)MR18= 0x230b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8283 12:46:18.634762 CH0 RK1: MR19=303, MR18=230B
8284 12:46:18.640672 CH0_RK1: MR19=0x303, MR18=0x230B, DQSOSC=392, MR23=63, INC=24, DEC=16
8285 12:46:18.643783 [RxdqsGatingPostProcess] freq 1600
8286 12:46:18.650585 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8287 12:46:18.653999 best DQS0 dly(2T, 0.5T) = (1, 1)
8288 12:46:18.657186 best DQS1 dly(2T, 0.5T) = (1, 1)
8289 12:46:18.657604 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8290 12:46:18.660690 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8291 12:46:18.664119 best DQS0 dly(2T, 0.5T) = (1, 1)
8292 12:46:18.666992 best DQS1 dly(2T, 0.5T) = (1, 1)
8293 12:46:18.670594 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8294 12:46:18.673919 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8295 12:46:18.677208 Pre-setting of DQS Precalculation
8296 12:46:18.684039 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8297 12:46:18.684525 ==
8298 12:46:18.687542 Dram Type= 6, Freq= 0, CH_1, rank 0
8299 12:46:18.690431 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8300 12:46:18.690852 ==
8301 12:46:18.694229 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8302 12:46:18.700629 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8303 12:46:18.704008 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8304 12:46:18.710363 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8305 12:46:18.718890 [CA 0] Center 42 (12~72) winsize 61
8306 12:46:18.722093 [CA 1] Center 42 (13~72) winsize 60
8307 12:46:18.725487 [CA 2] Center 38 (9~68) winsize 60
8308 12:46:18.728167 [CA 3] Center 38 (9~67) winsize 59
8309 12:46:18.731565 [CA 4] Center 38 (9~68) winsize 60
8310 12:46:18.734741 [CA 5] Center 37 (8~67) winsize 60
8311 12:46:18.735163
8312 12:46:18.738434 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8313 12:46:18.738854
8314 12:46:18.741746 [CATrainingPosCal] consider 1 rank data
8315 12:46:18.744884 u2DelayCellTimex100 = 285/100 ps
8316 12:46:18.748030 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8317 12:46:18.755140 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8318 12:46:18.758619 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8319 12:46:18.761949 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8320 12:46:18.765298 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8321 12:46:18.768901 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8322 12:46:18.769422
8323 12:46:18.771846 CA PerBit enable=1, Macro0, CA PI delay=37
8324 12:46:18.772267
8325 12:46:18.775246 [CBTSetCACLKResult] CA Dly = 37
8326 12:46:18.778082 CS Dly: 10 (0~41)
8327 12:46:18.781600 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8328 12:46:18.784806 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8329 12:46:18.785229 ==
8330 12:46:18.788141 Dram Type= 6, Freq= 0, CH_1, rank 1
8331 12:46:18.791803 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8332 12:46:18.795158 ==
8333 12:46:18.798056 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8334 12:46:18.801583 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8335 12:46:18.808358 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8336 12:46:18.811753 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8337 12:46:18.821734 [CA 0] Center 41 (12~71) winsize 60
8338 12:46:18.825408 [CA 1] Center 42 (12~72) winsize 61
8339 12:46:18.828507 [CA 2] Center 38 (9~68) winsize 60
8340 12:46:18.831761 [CA 3] Center 37 (8~67) winsize 60
8341 12:46:18.835409 [CA 4] Center 38 (8~68) winsize 61
8342 12:46:18.838518 [CA 5] Center 37 (7~67) winsize 61
8343 12:46:18.838969
8344 12:46:18.841812 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8345 12:46:18.842337
8346 12:46:18.844943 [CATrainingPosCal] consider 2 rank data
8347 12:46:18.848775 u2DelayCellTimex100 = 285/100 ps
8348 12:46:18.851816 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8349 12:46:18.858193 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8350 12:46:18.861928 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8351 12:46:18.865147 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8352 12:46:18.868108 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8353 12:46:18.871470 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8354 12:46:18.871927
8355 12:46:18.874784 CA PerBit enable=1, Macro0, CA PI delay=37
8356 12:46:18.875351
8357 12:46:18.878130 [CBTSetCACLKResult] CA Dly = 37
8358 12:46:18.881998 CS Dly: 12 (0~45)
8359 12:46:18.885201 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8360 12:46:18.888256 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8361 12:46:18.888750
8362 12:46:18.891487 ----->DramcWriteLeveling(PI) begin...
8363 12:46:18.891910 ==
8364 12:46:18.895338 Dram Type= 6, Freq= 0, CH_1, rank 0
8365 12:46:18.898578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8366 12:46:18.901389 ==
8367 12:46:18.901650 Write leveling (Byte 0): 26 => 26
8368 12:46:18.904587 Write leveling (Byte 1): 28 => 28
8369 12:46:18.908181 DramcWriteLeveling(PI) end<-----
8370 12:46:18.908486
8371 12:46:18.908635 ==
8372 12:46:18.911412 Dram Type= 6, Freq= 0, CH_1, rank 0
8373 12:46:18.917935 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8374 12:46:18.918120 ==
8375 12:46:18.918260 [Gating] SW mode calibration
8376 12:46:18.927982 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8377 12:46:18.931600 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8378 12:46:18.934482 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 12:46:18.941645 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 12:46:18.944371 1 4 8 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
8381 12:46:18.948310 1 4 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
8382 12:46:18.954883 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8383 12:46:18.958193 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8384 12:46:18.961462 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8385 12:46:18.967964 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8386 12:46:18.971326 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 12:46:18.974681 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8388 12:46:18.981207 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8389 12:46:18.984454 1 5 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (1 0)
8390 12:46:18.988342 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 12:46:18.994759 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 12:46:18.998095 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 12:46:19.001567 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 12:46:19.007915 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 12:46:19.011217 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8396 12:46:19.014435 1 6 8 | B1->B0 | 2626 3c3c | 0 1 | (0 0) (0 0)
8397 12:46:19.021293 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 12:46:19.024523 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 12:46:19.027875 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 12:46:19.034782 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8401 12:46:19.038093 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 12:46:19.040780 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 12:46:19.048047 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 12:46:19.050983 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8405 12:46:19.054229 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8406 12:46:19.060950 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8407 12:46:19.064273 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 12:46:19.067513 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 12:46:19.071042 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 12:46:19.078013 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 12:46:19.080797 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 12:46:19.084201 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 12:46:19.090847 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 12:46:19.094346 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 12:46:19.097853 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 12:46:19.104050 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 12:46:19.107492 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 12:46:19.110524 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 12:46:19.117318 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 12:46:19.120807 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8421 12:46:19.123964 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8422 12:46:19.130619 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8423 12:46:19.133880 Total UI for P1: 0, mck2ui 16
8424 12:46:19.137750 best dqsien dly found for B1: ( 1, 9, 10)
8425 12:46:19.140845 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8426 12:46:19.144365 Total UI for P1: 0, mck2ui 16
8427 12:46:19.147699 best dqsien dly found for B0: ( 1, 9, 12)
8428 12:46:19.150382 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8429 12:46:19.153768 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8430 12:46:19.154350
8431 12:46:19.157727 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8432 12:46:19.160481 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8433 12:46:19.163788 [Gating] SW calibration Done
8434 12:46:19.164448 ==
8435 12:46:19.167150 Dram Type= 6, Freq= 0, CH_1, rank 0
8436 12:46:19.173850 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8437 12:46:19.174273 ==
8438 12:46:19.174601 RX Vref Scan: 0
8439 12:46:19.174912
8440 12:46:19.177227 RX Vref 0 -> 0, step: 1
8441 12:46:19.177648
8442 12:46:19.180476 RX Delay 0 -> 252, step: 8
8443 12:46:19.183822 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8444 12:46:19.187129 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8445 12:46:19.190934 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8446 12:46:19.194142 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8447 12:46:19.200828 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8448 12:46:19.203808 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8449 12:46:19.207425 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8450 12:46:19.210203 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8451 12:46:19.214091 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
8452 12:46:19.220495 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8453 12:46:19.223380 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8454 12:46:19.226792 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8455 12:46:19.230114 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8456 12:46:19.234018 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8457 12:46:19.239939 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8458 12:46:19.243413 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8459 12:46:19.243494 ==
8460 12:46:19.246754 Dram Type= 6, Freq= 0, CH_1, rank 0
8461 12:46:19.249667 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8462 12:46:19.249750 ==
8463 12:46:19.253246 DQS Delay:
8464 12:46:19.253327 DQS0 = 0, DQS1 = 0
8465 12:46:19.253391 DQM Delay:
8466 12:46:19.256756 DQM0 = 136, DQM1 = 133
8467 12:46:19.256835 DQ Delay:
8468 12:46:19.259741 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8469 12:46:19.263288 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8470 12:46:19.266571 DQ8 =123, DQ9 =123, DQ10 =131, DQ11 =127
8471 12:46:19.273284 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8472 12:46:19.273377
8473 12:46:19.273455
8474 12:46:19.273555 ==
8475 12:46:19.276601 Dram Type= 6, Freq= 0, CH_1, rank 0
8476 12:46:19.279969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8477 12:46:19.280095 ==
8478 12:46:19.280207
8479 12:46:19.280316
8480 12:46:19.283554 TX Vref Scan disable
8481 12:46:19.283686 == TX Byte 0 ==
8482 12:46:19.290217 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8483 12:46:19.292853 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8484 12:46:19.292981 == TX Byte 1 ==
8485 12:46:19.299703 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8486 12:46:19.303620 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8487 12:46:19.303847 ==
8488 12:46:19.306324 Dram Type= 6, Freq= 0, CH_1, rank 0
8489 12:46:19.309655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8490 12:46:19.309829 ==
8491 12:46:19.323572
8492 12:46:19.326879 TX Vref early break, caculate TX vref
8493 12:46:19.330101 TX Vref=16, minBit 1, minWin=21, winSum=374
8494 12:46:19.333448 TX Vref=18, minBit 1, minWin=22, winSum=383
8495 12:46:19.336823 TX Vref=20, minBit 0, minWin=23, winSum=393
8496 12:46:19.340056 TX Vref=22, minBit 1, minWin=23, winSum=402
8497 12:46:19.343352 TX Vref=24, minBit 1, minWin=24, winSum=411
8498 12:46:19.350179 TX Vref=26, minBit 1, minWin=24, winSum=420
8499 12:46:19.353261 TX Vref=28, minBit 0, minWin=24, winSum=424
8500 12:46:19.356851 TX Vref=30, minBit 1, minWin=24, winSum=419
8501 12:46:19.360388 TX Vref=32, minBit 0, minWin=24, winSum=415
8502 12:46:19.363687 TX Vref=34, minBit 0, minWin=23, winSum=398
8503 12:46:19.370366 [TxChooseVref] Worse bit 0, Min win 24, Win sum 424, Final Vref 28
8504 12:46:19.370786
8505 12:46:19.373607 Final TX Range 0 Vref 28
8506 12:46:19.374058
8507 12:46:19.374466 ==
8508 12:46:19.376518 Dram Type= 6, Freq= 0, CH_1, rank 0
8509 12:46:19.379944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8510 12:46:19.380416 ==
8511 12:46:19.380750
8512 12:46:19.381059
8513 12:46:19.383333 TX Vref Scan disable
8514 12:46:19.389948 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8515 12:46:19.390371 == TX Byte 0 ==
8516 12:46:19.393383 u2DelayCellOfst[0]=20 cells (6 PI)
8517 12:46:19.396575 u2DelayCellOfst[1]=10 cells (3 PI)
8518 12:46:19.400267 u2DelayCellOfst[2]=0 cells (0 PI)
8519 12:46:19.403495 u2DelayCellOfst[3]=6 cells (2 PI)
8520 12:46:19.407091 u2DelayCellOfst[4]=6 cells (2 PI)
8521 12:46:19.410387 u2DelayCellOfst[5]=20 cells (6 PI)
8522 12:46:19.413811 u2DelayCellOfst[6]=20 cells (6 PI)
8523 12:46:19.414231 u2DelayCellOfst[7]=6 cells (2 PI)
8524 12:46:19.419875 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8525 12:46:19.423677 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8526 12:46:19.424101 == TX Byte 1 ==
8527 12:46:19.426816 u2DelayCellOfst[8]=0 cells (0 PI)
8528 12:46:19.430050 u2DelayCellOfst[9]=3 cells (1 PI)
8529 12:46:19.432979 u2DelayCellOfst[10]=10 cells (3 PI)
8530 12:46:19.436160 u2DelayCellOfst[11]=6 cells (2 PI)
8531 12:46:19.439731 u2DelayCellOfst[12]=13 cells (4 PI)
8532 12:46:19.443466 u2DelayCellOfst[13]=17 cells (5 PI)
8533 12:46:19.446763 u2DelayCellOfst[14]=17 cells (5 PI)
8534 12:46:19.449998 u2DelayCellOfst[15]=17 cells (5 PI)
8535 12:46:19.453320 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8536 12:46:19.459688 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8537 12:46:19.460118 DramC Write-DBI on
8538 12:46:19.460498 ==
8539 12:46:19.463076 Dram Type= 6, Freq= 0, CH_1, rank 0
8540 12:46:19.466322 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8541 12:46:19.466790 ==
8542 12:46:19.469480
8543 12:46:19.469895
8544 12:46:19.470217 TX Vref Scan disable
8545 12:46:19.473253 == TX Byte 0 ==
8546 12:46:19.476586 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8547 12:46:19.479852 == TX Byte 1 ==
8548 12:46:19.483129 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8549 12:46:19.483546 DramC Write-DBI off
8550 12:46:19.483969
8551 12:46:19.486301 [DATLAT]
8552 12:46:19.486717 Freq=1600, CH1 RK0
8553 12:46:19.487047
8554 12:46:19.489549 DATLAT Default: 0xf
8555 12:46:19.489979 0, 0xFFFF, sum = 0
8556 12:46:19.493120 1, 0xFFFF, sum = 0
8557 12:46:19.493539 2, 0xFFFF, sum = 0
8558 12:46:19.496416 3, 0xFFFF, sum = 0
8559 12:46:19.496907 4, 0xFFFF, sum = 0
8560 12:46:19.500044 5, 0xFFFF, sum = 0
8561 12:46:19.500514 6, 0xFFFF, sum = 0
8562 12:46:19.502947 7, 0xFFFF, sum = 0
8563 12:46:19.506158 8, 0xFFFF, sum = 0
8564 12:46:19.506638 9, 0xFFFF, sum = 0
8565 12:46:19.509741 10, 0xFFFF, sum = 0
8566 12:46:19.510160 11, 0xFFFF, sum = 0
8567 12:46:19.513019 12, 0xFFFF, sum = 0
8568 12:46:19.513439 13, 0xFFFF, sum = 0
8569 12:46:19.516210 14, 0x0, sum = 1
8570 12:46:19.516686 15, 0x0, sum = 2
8571 12:46:19.519679 16, 0x0, sum = 3
8572 12:46:19.520161 17, 0x0, sum = 4
8573 12:46:19.522999 best_step = 15
8574 12:46:19.523446
8575 12:46:19.523771 ==
8576 12:46:19.526268 Dram Type= 6, Freq= 0, CH_1, rank 0
8577 12:46:19.529407 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8578 12:46:19.529867 ==
8579 12:46:19.530200 RX Vref Scan: 1
8580 12:46:19.530509
8581 12:46:19.532654 Set Vref Range= 24 -> 127
8582 12:46:19.533082
8583 12:46:19.536630 RX Vref 24 -> 127, step: 1
8584 12:46:19.537045
8585 12:46:19.539796 RX Delay 27 -> 252, step: 4
8586 12:46:19.540210
8587 12:46:19.542888 Set Vref, RX VrefLevel [Byte0]: 24
8588 12:46:19.546149 [Byte1]: 24
8589 12:46:19.546578
8590 12:46:19.549565 Set Vref, RX VrefLevel [Byte0]: 25
8591 12:46:19.552903 [Byte1]: 25
8592 12:46:19.553321
8593 12:46:19.556207 Set Vref, RX VrefLevel [Byte0]: 26
8594 12:46:19.559555 [Byte1]: 26
8595 12:46:19.562927
8596 12:46:19.563339 Set Vref, RX VrefLevel [Byte0]: 27
8597 12:46:19.566632 [Byte1]: 27
8598 12:46:19.570738
8599 12:46:19.571195 Set Vref, RX VrefLevel [Byte0]: 28
8600 12:46:19.573939 [Byte1]: 28
8601 12:46:19.578175
8602 12:46:19.578643 Set Vref, RX VrefLevel [Byte0]: 29
8603 12:46:19.581478 [Byte1]: 29
8604 12:46:19.585881
8605 12:46:19.586295 Set Vref, RX VrefLevel [Byte0]: 30
8606 12:46:19.589045 [Byte1]: 30
8607 12:46:19.593004
8608 12:46:19.593426 Set Vref, RX VrefLevel [Byte0]: 31
8609 12:46:19.596198 [Byte1]: 31
8610 12:46:19.600490
8611 12:46:19.600905 Set Vref, RX VrefLevel [Byte0]: 32
8612 12:46:19.603795 [Byte1]: 32
8613 12:46:19.607956
8614 12:46:19.608413 Set Vref, RX VrefLevel [Byte0]: 33
8615 12:46:19.611296 [Byte1]: 33
8616 12:46:19.615832
8617 12:46:19.616329 Set Vref, RX VrefLevel [Byte0]: 34
8618 12:46:19.618988 [Byte1]: 34
8619 12:46:19.623489
8620 12:46:19.623902 Set Vref, RX VrefLevel [Byte0]: 35
8621 12:46:19.626603 [Byte1]: 35
8622 12:46:19.630477
8623 12:46:19.630893 Set Vref, RX VrefLevel [Byte0]: 36
8624 12:46:19.633859 [Byte1]: 36
8625 12:46:19.638117
8626 12:46:19.638203 Set Vref, RX VrefLevel [Byte0]: 37
8627 12:46:19.641576 [Byte1]: 37
8628 12:46:19.645248
8629 12:46:19.645325 Set Vref, RX VrefLevel [Byte0]: 38
8630 12:46:19.648413 [Byte1]: 38
8631 12:46:19.652856
8632 12:46:19.652963 Set Vref, RX VrefLevel [Byte0]: 39
8633 12:46:19.656040 [Byte1]: 39
8634 12:46:19.660179
8635 12:46:19.660276 Set Vref, RX VrefLevel [Byte0]: 40
8636 12:46:19.663983 [Byte1]: 40
8637 12:46:19.667973
8638 12:46:19.668054 Set Vref, RX VrefLevel [Byte0]: 41
8639 12:46:19.671301 [Byte1]: 41
8640 12:46:19.675313
8641 12:46:19.675386 Set Vref, RX VrefLevel [Byte0]: 42
8642 12:46:19.679099 [Byte1]: 42
8643 12:46:19.682855
8644 12:46:19.682930 Set Vref, RX VrefLevel [Byte0]: 43
8645 12:46:19.686678 [Byte1]: 43
8646 12:46:19.690720
8647 12:46:19.690805 Set Vref, RX VrefLevel [Byte0]: 44
8648 12:46:19.694049 [Byte1]: 44
8649 12:46:19.698001
8650 12:46:19.698073 Set Vref, RX VrefLevel [Byte0]: 45
8651 12:46:19.701821 [Byte1]: 45
8652 12:46:19.705577
8653 12:46:19.705683 Set Vref, RX VrefLevel [Byte0]: 46
8654 12:46:19.708880 [Byte1]: 46
8655 12:46:19.713557
8656 12:46:19.713637 Set Vref, RX VrefLevel [Byte0]: 47
8657 12:46:19.716903 [Byte1]: 47
8658 12:46:19.720751
8659 12:46:19.720831 Set Vref, RX VrefLevel [Byte0]: 48
8660 12:46:19.724065 [Byte1]: 48
8661 12:46:19.728481
8662 12:46:19.728556 Set Vref, RX VrefLevel [Byte0]: 49
8663 12:46:19.731762 [Byte1]: 49
8664 12:46:19.735710
8665 12:46:19.735790 Set Vref, RX VrefLevel [Byte0]: 50
8666 12:46:19.739064 [Byte1]: 50
8667 12:46:19.743713
8668 12:46:19.743782 Set Vref, RX VrefLevel [Byte0]: 51
8669 12:46:19.746875 [Byte1]: 51
8670 12:46:19.750620
8671 12:46:19.750695 Set Vref, RX VrefLevel [Byte0]: 52
8672 12:46:19.754380 [Byte1]: 52
8673 12:46:19.758675
8674 12:46:19.758749 Set Vref, RX VrefLevel [Byte0]: 53
8675 12:46:19.761760 [Byte1]: 53
8676 12:46:19.766090
8677 12:46:19.766158 Set Vref, RX VrefLevel [Byte0]: 54
8678 12:46:19.769213 [Byte1]: 54
8679 12:46:19.773487
8680 12:46:19.773567 Set Vref, RX VrefLevel [Byte0]: 55
8681 12:46:19.776886 [Byte1]: 55
8682 12:46:19.780949
8683 12:46:19.781030 Set Vref, RX VrefLevel [Byte0]: 56
8684 12:46:19.784468 [Byte1]: 56
8685 12:46:19.788726
8686 12:46:19.788800 Set Vref, RX VrefLevel [Byte0]: 57
8687 12:46:19.791745 [Byte1]: 57
8688 12:46:19.796041
8689 12:46:19.796122 Set Vref, RX VrefLevel [Byte0]: 58
8690 12:46:19.799169 [Byte1]: 58
8691 12:46:19.803769
8692 12:46:19.803851 Set Vref, RX VrefLevel [Byte0]: 59
8693 12:46:19.807065 [Byte1]: 59
8694 12:46:19.811448
8695 12:46:19.811530 Set Vref, RX VrefLevel [Byte0]: 60
8696 12:46:19.814835 [Byte1]: 60
8697 12:46:19.818757
8698 12:46:19.818838 Set Vref, RX VrefLevel [Byte0]: 61
8699 12:46:19.822040 [Byte1]: 61
8700 12:46:19.826018
8701 12:46:19.826099 Set Vref, RX VrefLevel [Byte0]: 62
8702 12:46:19.829282 [Byte1]: 62
8703 12:46:19.833624
8704 12:46:19.833705 Set Vref, RX VrefLevel [Byte0]: 63
8705 12:46:19.836890 [Byte1]: 63
8706 12:46:19.841511
8707 12:46:19.841592 Set Vref, RX VrefLevel [Byte0]: 64
8708 12:46:19.844795 [Byte1]: 64
8709 12:46:19.848713
8710 12:46:19.848797 Set Vref, RX VrefLevel [Byte0]: 65
8711 12:46:19.851884 [Byte1]: 65
8712 12:46:19.856689
8713 12:46:19.856771 Set Vref, RX VrefLevel [Byte0]: 66
8714 12:46:19.859939 [Byte1]: 66
8715 12:46:19.863966
8716 12:46:19.864047 Set Vref, RX VrefLevel [Byte0]: 67
8717 12:46:19.867231 [Byte1]: 67
8718 12:46:19.871270
8719 12:46:19.871351 Set Vref, RX VrefLevel [Byte0]: 68
8720 12:46:19.874494 [Byte1]: 68
8721 12:46:19.879067
8722 12:46:19.879149 Set Vref, RX VrefLevel [Byte0]: 69
8723 12:46:19.882467 [Byte1]: 69
8724 12:46:19.886248
8725 12:46:19.886329 Set Vref, RX VrefLevel [Byte0]: 70
8726 12:46:19.890313 [Byte1]: 70
8727 12:46:19.893798
8728 12:46:19.893879 Set Vref, RX VrefLevel [Byte0]: 71
8729 12:46:19.897196 [Byte1]: 71
8730 12:46:19.901447
8731 12:46:19.901528 Set Vref, RX VrefLevel [Byte0]: 72
8732 12:46:19.904886 [Byte1]: 72
8733 12:46:19.909125
8734 12:46:19.909206 Set Vref, RX VrefLevel [Byte0]: 73
8735 12:46:19.912189 [Byte1]: 73
8736 12:46:19.916855
8737 12:46:19.916936 Final RX Vref Byte 0 = 58 to rank0
8738 12:46:19.919872 Final RX Vref Byte 1 = 57 to rank0
8739 12:46:19.923293 Final RX Vref Byte 0 = 58 to rank1
8740 12:46:19.926568 Final RX Vref Byte 1 = 57 to rank1==
8741 12:46:19.929884 Dram Type= 6, Freq= 0, CH_1, rank 0
8742 12:46:19.936540 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8743 12:46:19.936624 ==
8744 12:46:19.936688 DQS Delay:
8745 12:46:19.936746 DQS0 = 0, DQS1 = 0
8746 12:46:19.940133 DQM Delay:
8747 12:46:19.940214 DQM0 = 134, DQM1 = 131
8748 12:46:19.943391 DQ Delay:
8749 12:46:19.946582 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8750 12:46:19.950008 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8751 12:46:19.953405 DQ8 =118, DQ9 =122, DQ10 =132, DQ11 =122
8752 12:46:19.956698 DQ12 =140, DQ13 =140, DQ14 =138, DQ15 =140
8753 12:46:19.956890
8754 12:46:19.957044
8755 12:46:19.957177
8756 12:46:19.959804 [DramC_TX_OE_Calibration] TA2
8757 12:46:19.963679 Original DQ_B0 (3 6) =30, OEN = 27
8758 12:46:19.966664 Original DQ_B1 (3 6) =30, OEN = 27
8759 12:46:19.969800 24, 0x0, End_B0=24 End_B1=24
8760 12:46:19.969940 25, 0x0, End_B0=25 End_B1=25
8761 12:46:19.973183 26, 0x0, End_B0=26 End_B1=26
8762 12:46:19.976483 27, 0x0, End_B0=27 End_B1=27
8763 12:46:19.979879 28, 0x0, End_B0=28 End_B1=28
8764 12:46:19.980033 29, 0x0, End_B0=29 End_B1=29
8765 12:46:19.983452 30, 0x0, End_B0=30 End_B1=30
8766 12:46:19.986570 31, 0x5151, End_B0=30 End_B1=30
8767 12:46:19.989916 Byte0 end_step=30 best_step=27
8768 12:46:19.993424 Byte1 end_step=30 best_step=27
8769 12:46:19.996727 Byte0 TX OE(2T, 0.5T) = (3, 3)
8770 12:46:19.997122 Byte1 TX OE(2T, 0.5T) = (3, 3)
8771 12:46:20.000628
8772 12:46:20.001018
8773 12:46:20.006654 [DQSOSCAuto] RK0, (LSB)MR18= 0x1623, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
8774 12:46:20.010244 CH1 RK0: MR19=303, MR18=1623
8775 12:46:20.016468 CH1_RK0: MR19=0x303, MR18=0x1623, DQSOSC=392, MR23=63, INC=24, DEC=16
8776 12:46:20.017218
8777 12:46:20.020646 ----->DramcWriteLeveling(PI) begin...
8778 12:46:20.021209 ==
8779 12:46:20.023204 Dram Type= 6, Freq= 0, CH_1, rank 1
8780 12:46:20.026531 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8781 12:46:20.026996 ==
8782 12:46:20.030019 Write leveling (Byte 0): 25 => 25
8783 12:46:20.033086 Write leveling (Byte 1): 28 => 28
8784 12:46:20.036670 DramcWriteLeveling(PI) end<-----
8785 12:46:20.037127
8786 12:46:20.037479 ==
8787 12:46:20.039873 Dram Type= 6, Freq= 0, CH_1, rank 1
8788 12:46:20.043575 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8789 12:46:20.044133 ==
8790 12:46:20.046683 [Gating] SW mode calibration
8791 12:46:20.053061 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8792 12:46:20.059712 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8793 12:46:20.063418 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 12:46:20.066778 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 12:46:20.073007 1 4 8 | B1->B0 | 3131 2323 | 1 0 | (0 0) (0 0)
8796 12:46:20.076402 1 4 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
8797 12:46:20.079599 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8798 12:46:20.086887 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8799 12:46:20.090018 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8800 12:46:20.093227 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8801 12:46:20.100343 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8802 12:46:20.103662 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8803 12:46:20.106583 1 5 8 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 0)
8804 12:46:20.113408 1 5 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 1)
8805 12:46:20.116880 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8806 12:46:20.119961 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 12:46:20.126458 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8808 12:46:20.129528 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 12:46:20.132874 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8810 12:46:20.139768 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8811 12:46:20.143000 1 6 8 | B1->B0 | 4646 2323 | 0 0 | (0 0) (0 0)
8812 12:46:20.146277 1 6 12 | B1->B0 | 4646 3e3e | 0 0 | (0 0) (0 0)
8813 12:46:20.153251 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8814 12:46:20.156379 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 12:46:20.159509 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 12:46:20.166000 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 12:46:20.169605 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 12:46:20.172953 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 12:46:20.179172 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8820 12:46:20.182905 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8821 12:46:20.186221 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8822 12:46:20.192372 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 12:46:20.196034 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 12:46:20.199356 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 12:46:20.205617 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 12:46:20.209616 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 12:46:20.212774 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 12:46:20.216252 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 12:46:20.223024 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 12:46:20.226233 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 12:46:20.229419 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 12:46:20.235867 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 12:46:20.239774 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 12:46:20.242399 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8835 12:46:20.249309 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8836 12:46:20.253092 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8837 12:46:20.255934 Total UI for P1: 0, mck2ui 16
8838 12:46:20.259249 best dqsien dly found for B1: ( 1, 9, 6)
8839 12:46:20.262485 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8840 12:46:20.269493 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8841 12:46:20.270003 Total UI for P1: 0, mck2ui 16
8842 12:46:20.272810 best dqsien dly found for B0: ( 1, 9, 12)
8843 12:46:20.279281 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8844 12:46:20.282711 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8845 12:46:20.283238
8846 12:46:20.285948 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8847 12:46:20.289087 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8848 12:46:20.292374 [Gating] SW calibration Done
8849 12:46:20.292903 ==
8850 12:46:20.295655 Dram Type= 6, Freq= 0, CH_1, rank 1
8851 12:46:20.299400 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8852 12:46:20.299820 ==
8853 12:46:20.302845 RX Vref Scan: 0
8854 12:46:20.303360
8855 12:46:20.303690 RX Vref 0 -> 0, step: 1
8856 12:46:20.303996
8857 12:46:20.305894 RX Delay 0 -> 252, step: 8
8858 12:46:20.309052 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8859 12:46:20.316042 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8860 12:46:20.319090 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8861 12:46:20.322551 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8862 12:46:20.325640 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8863 12:46:20.329399 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8864 12:46:20.332406 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8865 12:46:20.339239 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8866 12:46:20.342744 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8867 12:46:20.345784 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8868 12:46:20.348999 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8869 12:46:20.352523 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8870 12:46:20.359075 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8871 12:46:20.362402 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8872 12:46:20.365790 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8873 12:46:20.368979 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8874 12:46:20.369437 ==
8875 12:46:20.372407 Dram Type= 6, Freq= 0, CH_1, rank 1
8876 12:46:20.378669 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8877 12:46:20.379127 ==
8878 12:46:20.379487 DQS Delay:
8879 12:46:20.382646 DQS0 = 0, DQS1 = 0
8880 12:46:20.383205 DQM Delay:
8881 12:46:20.385435 DQM0 = 136, DQM1 = 133
8882 12:46:20.386224 DQ Delay:
8883 12:46:20.388807 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8884 12:46:20.391812 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8885 12:46:20.395736 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8886 12:46:20.399198 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8887 12:46:20.399609
8888 12:46:20.399930
8889 12:46:20.400227 ==
8890 12:46:20.402019 Dram Type= 6, Freq= 0, CH_1, rank 1
8891 12:46:20.408742 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8892 12:46:20.409179 ==
8893 12:46:20.409507
8894 12:46:20.409807
8895 12:46:20.410097 TX Vref Scan disable
8896 12:46:20.412042 == TX Byte 0 ==
8897 12:46:20.415320 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8898 12:46:20.422159 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8899 12:46:20.422677 == TX Byte 1 ==
8900 12:46:20.424964 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8901 12:46:20.432144 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8902 12:46:20.432590 ==
8903 12:46:20.435673 Dram Type= 6, Freq= 0, CH_1, rank 1
8904 12:46:20.438641 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8905 12:46:20.439160 ==
8906 12:46:20.451967
8907 12:46:20.455289 TX Vref early break, caculate TX vref
8908 12:46:20.458572 TX Vref=16, minBit 0, minWin=23, winSum=384
8909 12:46:20.462020 TX Vref=18, minBit 0, minWin=23, winSum=390
8910 12:46:20.465514 TX Vref=20, minBit 2, minWin=23, winSum=400
8911 12:46:20.468683 TX Vref=22, minBit 1, minWin=23, winSum=404
8912 12:46:20.472142 TX Vref=24, minBit 0, minWin=24, winSum=415
8913 12:46:20.478614 TX Vref=26, minBit 0, minWin=25, winSum=425
8914 12:46:20.482231 TX Vref=28, minBit 0, minWin=25, winSum=424
8915 12:46:20.485134 TX Vref=30, minBit 6, minWin=24, winSum=418
8916 12:46:20.489229 TX Vref=32, minBit 0, minWin=25, winSum=417
8917 12:46:20.492037 TX Vref=34, minBit 0, minWin=24, winSum=407
8918 12:46:20.495240 TX Vref=36, minBit 0, minWin=23, winSum=396
8919 12:46:20.502001 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 26
8920 12:46:20.502559
8921 12:46:20.504909 Final TX Range 0 Vref 26
8922 12:46:20.505412
8923 12:46:20.505772 ==
8924 12:46:20.508141 Dram Type= 6, Freq= 0, CH_1, rank 1
8925 12:46:20.512101 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8926 12:46:20.512611 ==
8927 12:46:20.512974
8928 12:46:20.513302
8929 12:46:20.515392 TX Vref Scan disable
8930 12:46:20.521815 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8931 12:46:20.522272 == TX Byte 0 ==
8932 12:46:20.525164 u2DelayCellOfst[0]=17 cells (5 PI)
8933 12:46:20.528744 u2DelayCellOfst[1]=10 cells (3 PI)
8934 12:46:20.531935 u2DelayCellOfst[2]=0 cells (0 PI)
8935 12:46:20.535852 u2DelayCellOfst[3]=6 cells (2 PI)
8936 12:46:20.539052 u2DelayCellOfst[4]=10 cells (3 PI)
8937 12:46:20.542206 u2DelayCellOfst[5]=20 cells (6 PI)
8938 12:46:20.545155 u2DelayCellOfst[6]=20 cells (6 PI)
8939 12:46:20.548414 u2DelayCellOfst[7]=6 cells (2 PI)
8940 12:46:20.552126 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8941 12:46:20.555214 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8942 12:46:20.558234 == TX Byte 1 ==
8943 12:46:20.561577 u2DelayCellOfst[8]=0 cells (0 PI)
8944 12:46:20.562053 u2DelayCellOfst[9]=0 cells (0 PI)
8945 12:46:20.565259 u2DelayCellOfst[10]=10 cells (3 PI)
8946 12:46:20.568434 u2DelayCellOfst[11]=3 cells (1 PI)
8947 12:46:20.571662 u2DelayCellOfst[12]=13 cells (4 PI)
8948 12:46:20.575257 u2DelayCellOfst[13]=13 cells (4 PI)
8949 12:46:20.578895 u2DelayCellOfst[14]=17 cells (5 PI)
8950 12:46:20.582135 u2DelayCellOfst[15]=17 cells (5 PI)
8951 12:46:20.585260 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8952 12:46:20.591743 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8953 12:46:20.592259 DramC Write-DBI on
8954 12:46:20.592626 ==
8955 12:46:20.594995 Dram Type= 6, Freq= 0, CH_1, rank 1
8956 12:46:20.598391 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8957 12:46:20.601851 ==
8958 12:46:20.602267
8959 12:46:20.602589
8960 12:46:20.602887 TX Vref Scan disable
8961 12:46:20.605293 == TX Byte 0 ==
8962 12:46:20.608478 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8963 12:46:20.612125 == TX Byte 1 ==
8964 12:46:20.615471 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8965 12:46:20.616002 DramC Write-DBI off
8966 12:46:20.618427
8967 12:46:20.618830 [DATLAT]
8968 12:46:20.619149 Freq=1600, CH1 RK1
8969 12:46:20.619453
8970 12:46:20.621714 DATLAT Default: 0xf
8971 12:46:20.622344 0, 0xFFFF, sum = 0
8972 12:46:20.625219 1, 0xFFFF, sum = 0
8973 12:46:20.625770 2, 0xFFFF, sum = 0
8974 12:46:20.628234 3, 0xFFFF, sum = 0
8975 12:46:20.631495 4, 0xFFFF, sum = 0
8976 12:46:20.632001 5, 0xFFFF, sum = 0
8977 12:46:20.634942 6, 0xFFFF, sum = 0
8978 12:46:20.635355 7, 0xFFFF, sum = 0
8979 12:46:20.638287 8, 0xFFFF, sum = 0
8980 12:46:20.638703 9, 0xFFFF, sum = 0
8981 12:46:20.641723 10, 0xFFFF, sum = 0
8982 12:46:20.642233 11, 0xFFFF, sum = 0
8983 12:46:20.644978 12, 0xFFFF, sum = 0
8984 12:46:20.645396 13, 0xFFFF, sum = 0
8985 12:46:20.648664 14, 0x0, sum = 1
8986 12:46:20.649077 15, 0x0, sum = 2
8987 12:46:20.651732 16, 0x0, sum = 3
8988 12:46:20.652264 17, 0x0, sum = 4
8989 12:46:20.654849 best_step = 15
8990 12:46:20.655257
8991 12:46:20.655578 ==
8992 12:46:20.658260 Dram Type= 6, Freq= 0, CH_1, rank 1
8993 12:46:20.661561 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8994 12:46:20.662008 ==
8995 12:46:20.662341 RX Vref Scan: 0
8996 12:46:20.665027
8997 12:46:20.665435 RX Vref 0 -> 0, step: 1
8998 12:46:20.665758
8999 12:46:20.668466 RX Delay 19 -> 252, step: 4
9000 12:46:20.671653 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9001 12:46:20.678349 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9002 12:46:20.681365 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9003 12:46:20.684655 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9004 12:46:20.688224 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9005 12:46:20.691708 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9006 12:46:20.695453 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9007 12:46:20.702080 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9008 12:46:20.705002 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
9009 12:46:20.708064 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9010 12:46:20.711639 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9011 12:46:20.715340 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9012 12:46:20.721869 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9013 12:46:20.724506 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9014 12:46:20.727949 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9015 12:46:20.731651 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
9016 12:46:20.732165 ==
9017 12:46:20.734762 Dram Type= 6, Freq= 0, CH_1, rank 1
9018 12:46:20.741566 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9019 12:46:20.741998 ==
9020 12:46:20.742330 DQS Delay:
9021 12:46:20.744454 DQS0 = 0, DQS1 = 0
9022 12:46:20.744867 DQM Delay:
9023 12:46:20.748007 DQM0 = 134, DQM1 = 130
9024 12:46:20.748460 DQ Delay:
9025 12:46:20.751362 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9026 12:46:20.754452 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9027 12:46:20.757937 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
9028 12:46:20.761225 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =138
9029 12:46:20.761796
9030 12:46:20.762339
9031 12:46:20.762827
9032 12:46:20.764718 [DramC_TX_OE_Calibration] TA2
9033 12:46:20.767825 Original DQ_B0 (3 6) =30, OEN = 27
9034 12:46:20.770988 Original DQ_B1 (3 6) =30, OEN = 27
9035 12:46:20.774558 24, 0x0, End_B0=24 End_B1=24
9036 12:46:20.777611 25, 0x0, End_B0=25 End_B1=25
9037 12:46:20.778047 26, 0x0, End_B0=26 End_B1=26
9038 12:46:20.781261 27, 0x0, End_B0=27 End_B1=27
9039 12:46:20.784632 28, 0x0, End_B0=28 End_B1=28
9040 12:46:20.787998 29, 0x0, End_B0=29 End_B1=29
9041 12:46:20.788558 30, 0x0, End_B0=30 End_B1=30
9042 12:46:20.791494 31, 0x4141, End_B0=30 End_B1=30
9043 12:46:20.794396 Byte0 end_step=30 best_step=27
9044 12:46:20.797979 Byte1 end_step=30 best_step=27
9045 12:46:20.801202 Byte0 TX OE(2T, 0.5T) = (3, 3)
9046 12:46:20.804693 Byte1 TX OE(2T, 0.5T) = (3, 3)
9047 12:46:20.805204
9048 12:46:20.805530
9049 12:46:20.810991 [DQSOSCAuto] RK1, (LSB)MR18= 0x2206, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
9050 12:46:20.814486 CH1 RK1: MR19=303, MR18=2206
9051 12:46:20.821346 CH1_RK1: MR19=0x303, MR18=0x2206, DQSOSC=392, MR23=63, INC=24, DEC=16
9052 12:46:20.824529 [RxdqsGatingPostProcess] freq 1600
9053 12:46:20.828083 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9054 12:46:20.831046 best DQS0 dly(2T, 0.5T) = (1, 1)
9055 12:46:20.833812 best DQS1 dly(2T, 0.5T) = (1, 1)
9056 12:46:20.838044 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9057 12:46:20.841245 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9058 12:46:20.844368 best DQS0 dly(2T, 0.5T) = (1, 1)
9059 12:46:20.847215 best DQS1 dly(2T, 0.5T) = (1, 1)
9060 12:46:20.850765 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9061 12:46:20.854207 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9062 12:46:20.857428 Pre-setting of DQS Precalculation
9063 12:46:20.860543 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9064 12:46:20.867310 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9065 12:46:20.877530 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9066 12:46:20.878052
9067 12:46:20.878377
9068 12:46:20.880925 [Calibration Summary] 3200 Mbps
9069 12:46:20.881442 CH 0, Rank 0
9070 12:46:20.884426 SW Impedance : PASS
9071 12:46:20.885041 DUTY Scan : NO K
9072 12:46:20.887301 ZQ Calibration : PASS
9073 12:46:20.890263 Jitter Meter : NO K
9074 12:46:20.890821 CBT Training : PASS
9075 12:46:20.893727 Write leveling : PASS
9076 12:46:20.897356 RX DQS gating : PASS
9077 12:46:20.897941 RX DQ/DQS(RDDQC) : PASS
9078 12:46:20.900906 TX DQ/DQS : PASS
9079 12:46:20.901484 RX DATLAT : PASS
9080 12:46:20.903552 RX DQ/DQS(Engine): PASS
9081 12:46:20.906951 TX OE : PASS
9082 12:46:20.907482 All Pass.
9083 12:46:20.907963
9084 12:46:20.908468 CH 0, Rank 1
9085 12:46:20.910235 SW Impedance : PASS
9086 12:46:20.913807 DUTY Scan : NO K
9087 12:46:20.914465 ZQ Calibration : PASS
9088 12:46:20.917326 Jitter Meter : NO K
9089 12:46:20.920223 CBT Training : PASS
9090 12:46:20.920666 Write leveling : PASS
9091 12:46:20.923674 RX DQS gating : PASS
9092 12:46:20.927166 RX DQ/DQS(RDDQC) : PASS
9093 12:46:20.927523 TX DQ/DQS : PASS
9094 12:46:20.930100 RX DATLAT : PASS
9095 12:46:20.933678 RX DQ/DQS(Engine): PASS
9096 12:46:20.934088 TX OE : PASS
9097 12:46:20.934482 All Pass.
9098 12:46:20.936952
9099 12:46:20.937360 CH 1, Rank 0
9100 12:46:20.940570 SW Impedance : PASS
9101 12:46:20.941077 DUTY Scan : NO K
9102 12:46:20.943786 ZQ Calibration : PASS
9103 12:46:20.946916 Jitter Meter : NO K
9104 12:46:20.947327 CBT Training : PASS
9105 12:46:20.950308 Write leveling : PASS
9106 12:46:20.950811 RX DQS gating : PASS
9107 12:46:20.954146 RX DQ/DQS(RDDQC) : PASS
9108 12:46:20.957298 TX DQ/DQS : PASS
9109 12:46:20.957813 RX DATLAT : PASS
9110 12:46:20.960478 RX DQ/DQS(Engine): PASS
9111 12:46:20.963287 TX OE : PASS
9112 12:46:20.963743 All Pass.
9113 12:46:20.964082
9114 12:46:20.964416 CH 1, Rank 1
9115 12:46:20.966572 SW Impedance : PASS
9116 12:46:20.970755 DUTY Scan : NO K
9117 12:46:20.971282 ZQ Calibration : PASS
9118 12:46:20.974101 Jitter Meter : NO K
9119 12:46:20.977313 CBT Training : PASS
9120 12:46:20.977821 Write leveling : PASS
9121 12:46:20.980475 RX DQS gating : PASS
9122 12:46:20.984037 RX DQ/DQS(RDDQC) : PASS
9123 12:46:20.984586 TX DQ/DQS : PASS
9124 12:46:20.987314 RX DATLAT : PASS
9125 12:46:20.990388 RX DQ/DQS(Engine): PASS
9126 12:46:20.990897 TX OE : PASS
9127 12:46:20.991234 All Pass.
9128 12:46:20.991535
9129 12:46:20.993827 DramC Write-DBI on
9130 12:46:20.996918 PER_BANK_REFRESH: Hybrid Mode
9131 12:46:20.997339 TX_TRACKING: ON
9132 12:46:21.006752 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9133 12:46:21.013417 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9134 12:46:21.023395 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9135 12:46:21.026451 [FAST_K] Save calibration result to emmc
9136 12:46:21.026861 sync common calibartion params.
9137 12:46:21.030142 sync cbt_mode0:1, 1:1
9138 12:46:21.033423 dram_init: ddr_geometry: 2
9139 12:46:21.036866 dram_init: ddr_geometry: 2
9140 12:46:21.037348 dram_init: ddr_geometry: 2
9141 12:46:21.040153 0:dram_rank_size:100000000
9142 12:46:21.043451 1:dram_rank_size:100000000
9143 12:46:21.046846 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9144 12:46:21.049898 DFS_SHUFFLE_HW_MODE: ON
9145 12:46:21.053448 dramc_set_vcore_voltage set vcore to 725000
9146 12:46:21.056907 Read voltage for 1600, 0
9147 12:46:21.057319 Vio18 = 0
9148 12:46:21.059849 Vcore = 725000
9149 12:46:21.060257 Vdram = 0
9150 12:46:21.060697 Vddq = 0
9151 12:46:21.061061 Vmddr = 0
9152 12:46:21.063306 switch to 3200 Mbps bootup
9153 12:46:21.066729 [DramcRunTimeConfig]
9154 12:46:21.067147 PHYPLL
9155 12:46:21.070208 DPM_CONTROL_AFTERK: ON
9156 12:46:21.070722 PER_BANK_REFRESH: ON
9157 12:46:21.073249 REFRESH_OVERHEAD_REDUCTION: ON
9158 12:46:21.076593 CMD_PICG_NEW_MODE: OFF
9159 12:46:21.077012 XRTWTW_NEW_MODE: ON
9160 12:46:21.079931 XRTRTR_NEW_MODE: ON
9161 12:46:21.080386 TX_TRACKING: ON
9162 12:46:21.083457 RDSEL_TRACKING: OFF
9163 12:46:21.083971 DQS Precalculation for DVFS: ON
9164 12:46:21.086595 RX_TRACKING: OFF
9165 12:46:21.087014 HW_GATING DBG: ON
9166 12:46:21.090076 ZQCS_ENABLE_LP4: ON
9167 12:46:21.093354 RX_PICG_NEW_MODE: ON
9168 12:46:21.093774 TX_PICG_NEW_MODE: ON
9169 12:46:21.096634 ENABLE_RX_DCM_DPHY: ON
9170 12:46:21.100152 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9171 12:46:21.100712 DUMMY_READ_FOR_TRACKING: OFF
9172 12:46:21.103120 !!! SPM_CONTROL_AFTERK: OFF
9173 12:46:21.106932 !!! SPM could not control APHY
9174 12:46:21.109812 IMPEDANCE_TRACKING: ON
9175 12:46:21.110323 TEMP_SENSOR: ON
9176 12:46:21.113505 HW_SAVE_FOR_SR: OFF
9177 12:46:21.116751 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9178 12:46:21.120190 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9179 12:46:21.120741 Read ODT Tracking: ON
9180 12:46:21.123245 Refresh Rate DeBounce: ON
9181 12:46:21.126621 DFS_NO_QUEUE_FLUSH: ON
9182 12:46:21.129896 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9183 12:46:21.130426 ENABLE_DFS_RUNTIME_MRW: OFF
9184 12:46:21.132985 DDR_RESERVE_NEW_MODE: ON
9185 12:46:21.136386 MR_CBT_SWITCH_FREQ: ON
9186 12:46:21.136806 =========================
9187 12:46:21.156140 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9188 12:46:21.159227 dram_init: ddr_geometry: 2
9189 12:46:21.177081 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9190 12:46:21.180906 dram_init: dram init end (result: 0)
9191 12:46:21.187104 DRAM-K: Full calibration passed in 24427 msecs
9192 12:46:21.190713 MRC: failed to locate region type 0.
9193 12:46:21.190795 DRAM rank0 size:0x100000000,
9194 12:46:21.194404 DRAM rank1 size=0x100000000
9195 12:46:21.204085 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9196 12:46:21.210680 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9197 12:46:21.217375 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9198 12:46:21.224133 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9199 12:46:21.227505 DRAM rank0 size:0x100000000,
9200 12:46:21.230909 DRAM rank1 size=0x100000000
9201 12:46:21.231088 CBMEM:
9202 12:46:21.234554 IMD: root @ 0xfffff000 254 entries.
9203 12:46:21.237975 IMD: root @ 0xffffec00 62 entries.
9204 12:46:21.241265 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9205 12:46:21.244547 WARNING: RO_VPD is uninitialized or empty.
9206 12:46:21.250970 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9207 12:46:21.257559 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9208 12:46:21.270463 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9209 12:46:21.282336 BS: romstage times (exec / console): total (unknown) / 23968 ms
9210 12:46:21.282884
9211 12:46:21.283360
9212 12:46:21.292244 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9213 12:46:21.295419 ARM64: Exception handlers installed.
9214 12:46:21.298591 ARM64: Testing exception
9215 12:46:21.301942 ARM64: Done test exception
9216 12:46:21.302548 Enumerating buses...
9217 12:46:21.305214 Show all devs... Before device enumeration.
9218 12:46:21.308503 Root Device: enabled 1
9219 12:46:21.311999 CPU_CLUSTER: 0: enabled 1
9220 12:46:21.312686 CPU: 00: enabled 1
9221 12:46:21.315162 Compare with tree...
9222 12:46:21.315749 Root Device: enabled 1
9223 12:46:21.318626 CPU_CLUSTER: 0: enabled 1
9224 12:46:21.321893 CPU: 00: enabled 1
9225 12:46:21.322434 Root Device scanning...
9226 12:46:21.324846 scan_static_bus for Root Device
9227 12:46:21.328249 CPU_CLUSTER: 0 enabled
9228 12:46:21.331511 scan_static_bus for Root Device done
9229 12:46:21.334677 scan_bus: bus Root Device finished in 8 msecs
9230 12:46:21.335107 done
9231 12:46:21.341634 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9232 12:46:21.344940 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9233 12:46:21.351646 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9234 12:46:21.355092 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9235 12:46:21.358663 Allocating resources...
9236 12:46:21.361793 Reading resources...
9237 12:46:21.365151 Root Device read_resources bus 0 link: 0
9238 12:46:21.365573 DRAM rank0 size:0x100000000,
9239 12:46:21.368492 DRAM rank1 size=0x100000000
9240 12:46:21.372045 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9241 12:46:21.375181 CPU: 00 missing read_resources
9242 12:46:21.378636 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9243 12:46:21.385204 Root Device read_resources bus 0 link: 0 done
9244 12:46:21.385752 Done reading resources.
9245 12:46:21.391711 Show resources in subtree (Root Device)...After reading.
9246 12:46:21.394986 Root Device child on link 0 CPU_CLUSTER: 0
9247 12:46:21.398498 CPU_CLUSTER: 0 child on link 0 CPU: 00
9248 12:46:21.408417 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9249 12:46:21.408984 CPU: 00
9250 12:46:21.411593 Root Device assign_resources, bus 0 link: 0
9251 12:46:21.414732 CPU_CLUSTER: 0 missing set_resources
9252 12:46:21.420953 Root Device assign_resources, bus 0 link: 0 done
9253 12:46:21.421376 Done setting resources.
9254 12:46:21.427448 Show resources in subtree (Root Device)...After assigning values.
9255 12:46:21.430804 Root Device child on link 0 CPU_CLUSTER: 0
9256 12:46:21.434473 CPU_CLUSTER: 0 child on link 0 CPU: 00
9257 12:46:21.444112 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9258 12:46:21.444654 CPU: 00
9259 12:46:21.447354 Done allocating resources.
9260 12:46:21.450847 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9261 12:46:21.454096 Enabling resources...
9262 12:46:21.454508 done.
9263 12:46:21.461211 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9264 12:46:21.461637 Initializing devices...
9265 12:46:21.464429 Root Device init
9266 12:46:21.464855 init hardware done!
9267 12:46:21.467642 0x00000018: ctrlr->caps
9268 12:46:21.470895 52.000 MHz: ctrlr->f_max
9269 12:46:21.471317 0.400 MHz: ctrlr->f_min
9270 12:46:21.474131 0x40ff8080: ctrlr->voltages
9271 12:46:21.477405 sclk: 390625
9272 12:46:21.477813 Bus Width = 1
9273 12:46:21.478133 sclk: 390625
9274 12:46:21.480804 Bus Width = 1
9275 12:46:21.481215 Early init status = 3
9276 12:46:21.487215 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9277 12:46:21.490508 in-header: 03 fc 00 00 01 00 00 00
9278 12:46:21.494243 in-data: 00
9279 12:46:21.497300 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9280 12:46:21.502718 in-header: 03 fd 00 00 00 00 00 00
9281 12:46:21.506110 in-data:
9282 12:46:21.509438 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9283 12:46:21.513456 in-header: 03 fc 00 00 01 00 00 00
9284 12:46:21.516718 in-data: 00
9285 12:46:21.519845 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9286 12:46:21.525674 in-header: 03 fd 00 00 00 00 00 00
9287 12:46:21.528924 in-data:
9288 12:46:21.532199 [SSUSB] Setting up USB HOST controller...
9289 12:46:21.535554 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9290 12:46:21.538651 [SSUSB] phy power-on done.
9291 12:46:21.542414 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9292 12:46:21.548738 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9293 12:46:21.552388 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9294 12:46:21.559027 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9295 12:46:21.565594 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9296 12:46:21.572224 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9297 12:46:21.578903 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9298 12:46:21.585056 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9299 12:46:21.588435 SPM: binary array size = 0x9dc
9300 12:46:21.591573 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9301 12:46:21.598250 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9302 12:46:21.605362 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9303 12:46:21.608366 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9304 12:46:21.614803 configure_display: Starting display init
9305 12:46:21.648499 anx7625_power_on_init: Init interface.
9306 12:46:21.651744 anx7625_disable_pd_protocol: Disabled PD feature.
9307 12:46:21.655021 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9308 12:46:21.682987 anx7625_start_dp_work: Secure OCM version=00
9309 12:46:21.686595 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9310 12:46:21.700909 sp_tx_get_edid_block: EDID Block = 1
9311 12:46:21.803807 Extracted contents:
9312 12:46:21.807176 header: 00 ff ff ff ff ff ff 00
9313 12:46:21.810348 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9314 12:46:21.813971 version: 01 04
9315 12:46:21.816996 basic params: 95 1f 11 78 0a
9316 12:46:21.820752 chroma info: 76 90 94 55 54 90 27 21 50 54
9317 12:46:21.823489 established: 00 00 00
9318 12:46:21.830094 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9319 12:46:21.833686 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9320 12:46:21.840100 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9321 12:46:21.846808 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9322 12:46:21.853470 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9323 12:46:21.856600 extensions: 00
9324 12:46:21.856693 checksum: fb
9325 12:46:21.856766
9326 12:46:21.860004 Manufacturer: IVO Model 57d Serial Number 0
9327 12:46:21.863265 Made week 0 of 2020
9328 12:46:21.863375 EDID version: 1.4
9329 12:46:21.867048 Digital display
9330 12:46:21.870073 6 bits per primary color channel
9331 12:46:21.870156 DisplayPort interface
9332 12:46:21.873543 Maximum image size: 31 cm x 17 cm
9333 12:46:21.876758 Gamma: 220%
9334 12:46:21.876839 Check DPMS levels
9335 12:46:21.880560 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9336 12:46:21.883441 First detailed timing is preferred timing
9337 12:46:21.887197 Established timings supported:
9338 12:46:21.890483 Standard timings supported:
9339 12:46:21.890564 Detailed timings
9340 12:46:21.896431 Hex of detail: 383680a07038204018303c0035ae10000019
9341 12:46:21.899847 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9342 12:46:21.906909 0780 0798 07c8 0820 hborder 0
9343 12:46:21.910152 0438 043b 0447 0458 vborder 0
9344 12:46:21.913620 -hsync -vsync
9345 12:46:21.913701 Did detailed timing
9346 12:46:21.916936 Hex of detail: 000000000000000000000000000000000000
9347 12:46:21.920104 Manufacturer-specified data, tag 0
9348 12:46:21.926873 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9349 12:46:21.926958 ASCII string: InfoVision
9350 12:46:21.933439 Hex of detail: 000000fe00523134304e574635205248200a
9351 12:46:21.936639 ASCII string: R140NWF5 RH
9352 12:46:21.936721 Checksum
9353 12:46:21.936785 Checksum: 0xfb (valid)
9354 12:46:21.943409 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9355 12:46:21.946487 DSI data_rate: 832800000 bps
9356 12:46:21.949752 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9357 12:46:21.956333 anx7625_parse_edid: pixelclock(138800).
9358 12:46:21.960113 hactive(1920), hsync(48), hfp(24), hbp(88)
9359 12:46:21.962985 vactive(1080), vsync(12), vfp(3), vbp(17)
9360 12:46:21.966493 anx7625_dsi_config: config dsi.
9361 12:46:21.973014 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9362 12:46:21.985582 anx7625_dsi_config: success to config DSI
9363 12:46:21.989376 anx7625_dp_start: MIPI phy setup OK.
9364 12:46:21.992478 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9365 12:46:21.996037 mtk_ddp_mode_set invalid vrefresh 60
9366 12:46:21.999360 main_disp_path_setup
9367 12:46:21.999440 ovl_layer_smi_id_en
9368 12:46:22.002797 ovl_layer_smi_id_en
9369 12:46:22.002883 ccorr_config
9370 12:46:22.002950 aal_config
9371 12:46:22.006415 gamma_config
9372 12:46:22.006580 postmask_config
9373 12:46:22.009367 dither_config
9374 12:46:22.012525 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9375 12:46:22.019425 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9376 12:46:22.022816 Root Device init finished in 555 msecs
9377 12:46:22.022938 CPU_CLUSTER: 0 init
9378 12:46:22.032655 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9379 12:46:22.036110 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9380 12:46:22.039298 APU_MBOX 0x190000b0 = 0x10001
9381 12:46:22.042655 APU_MBOX 0x190001b0 = 0x10001
9382 12:46:22.045443 APU_MBOX 0x190005b0 = 0x10001
9383 12:46:22.048872 APU_MBOX 0x190006b0 = 0x10001
9384 12:46:22.052640 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9385 12:46:22.064905 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9386 12:46:22.077892 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9387 12:46:22.084375 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9388 12:46:22.095845 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9389 12:46:22.105211 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9390 12:46:22.108613 CPU_CLUSTER: 0 init finished in 81 msecs
9391 12:46:22.111460 Devices initialized
9392 12:46:22.114789 Show all devs... After init.
9393 12:46:22.115243 Root Device: enabled 1
9394 12:46:22.118123 CPU_CLUSTER: 0: enabled 1
9395 12:46:22.121656 CPU: 00: enabled 1
9396 12:46:22.125112 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9397 12:46:22.128260 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9398 12:46:22.132139 ELOG: NV offset 0x57f000 size 0x1000
9399 12:46:22.138087 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9400 12:46:22.144490 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9401 12:46:22.147747 ELOG: Event(17) added with size 13 at 2024-02-05 12:43:38 UTC
9402 12:46:22.154344 out: cmd=0x121: 03 db 21 01 00 00 00 00
9403 12:46:22.158178 in-header: 03 f6 00 00 2c 00 00 00
9404 12:46:22.167711 in-data: 69 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9405 12:46:22.174930 ELOG: Event(A1) added with size 10 at 2024-02-05 12:43:38 UTC
9406 12:46:22.181546 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9407 12:46:22.187788 ELOG: Event(A0) added with size 9 at 2024-02-05 12:43:38 UTC
9408 12:46:22.191489 elog_add_boot_reason: Logged dev mode boot
9409 12:46:22.194741 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9410 12:46:22.198104 Finalize devices...
9411 12:46:22.198517 Devices finalized
9412 12:46:22.204476 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9413 12:46:22.207950 Writing coreboot table at 0xffe64000
9414 12:46:22.211511 0. 000000000010a000-0000000000113fff: RAMSTAGE
9415 12:46:22.214461 1. 0000000040000000-00000000400fffff: RAM
9416 12:46:22.221384 2. 0000000040100000-000000004032afff: RAMSTAGE
9417 12:46:22.224461 3. 000000004032b000-00000000545fffff: RAM
9418 12:46:22.227580 4. 0000000054600000-000000005465ffff: BL31
9419 12:46:22.231011 5. 0000000054660000-00000000ffe63fff: RAM
9420 12:46:22.237182 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9421 12:46:22.240881 7. 0000000100000000-000000023fffffff: RAM
9422 12:46:22.244092 Passing 5 GPIOs to payload:
9423 12:46:22.247451 NAME | PORT | POLARITY | VALUE
9424 12:46:22.250852 EC in RW | 0x000000aa | low | undefined
9425 12:46:22.257510 EC interrupt | 0x00000005 | low | undefined
9426 12:46:22.260675 TPM interrupt | 0x000000ab | high | undefined
9427 12:46:22.267125 SD card detect | 0x00000011 | high | undefined
9428 12:46:22.270418 speaker enable | 0x00000093 | high | undefined
9429 12:46:22.274117 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9430 12:46:22.277322 in-header: 03 f9 00 00 02 00 00 00
9431 12:46:22.280595 in-data: 02 00
9432 12:46:22.280676 ADC[4]: Raw value=904357 ID=7
9433 12:46:22.283928 ADC[3]: Raw value=213441 ID=1
9434 12:46:22.287371 RAM Code: 0x71
9435 12:46:22.287453 ADC[6]: Raw value=75701 ID=0
9436 12:46:22.290618 ADC[5]: Raw value=213072 ID=1
9437 12:46:22.294206 SKU Code: 0x1
9438 12:46:22.297313 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 6c95
9439 12:46:22.300345 coreboot table: 964 bytes.
9440 12:46:22.303668 IMD ROOT 0. 0xfffff000 0x00001000
9441 12:46:22.307123 IMD SMALL 1. 0xffffe000 0x00001000
9442 12:46:22.310397 RO MCACHE 2. 0xffffc000 0x00001104
9443 12:46:22.314002 CONSOLE 3. 0xfff7c000 0x00080000
9444 12:46:22.317404 FMAP 4. 0xfff7b000 0x00000452
9445 12:46:22.320722 TIME STAMP 5. 0xfff7a000 0x00000910
9446 12:46:22.323937 VBOOT WORK 6. 0xfff66000 0x00014000
9447 12:46:22.327049 RAMOOPS 7. 0xffe66000 0x00100000
9448 12:46:22.330587 COREBOOT 8. 0xffe64000 0x00002000
9449 12:46:22.330655 IMD small region:
9450 12:46:22.334115 IMD ROOT 0. 0xffffec00 0x00000400
9451 12:46:22.336998 VPD 1. 0xffffeb80 0x0000006c
9452 12:46:22.340217 MMC STATUS 2. 0xffffeb60 0x00000004
9453 12:46:22.347532 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9454 12:46:22.350796 Probing TPM: done!
9455 12:46:22.353936 Connected to device vid:did:rid of 1ae0:0028:00
9456 12:46:22.364224 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9457 12:46:22.367600 Initialized TPM device CR50 revision 0
9458 12:46:22.371335 Checking cr50 for pending updates
9459 12:46:22.375426 Reading cr50 TPM mode
9460 12:46:22.383038 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9461 12:46:22.389643 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9462 12:46:22.429979 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9463 12:46:22.433418 Checking segment from ROM address 0x40100000
9464 12:46:22.436663 Checking segment from ROM address 0x4010001c
9465 12:46:22.442861 Loading segment from ROM address 0x40100000
9466 12:46:22.442937 code (compression=0)
9467 12:46:22.450127 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9468 12:46:22.459802 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9469 12:46:22.459880 it's not compressed!
9470 12:46:22.466771 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9471 12:46:22.469846 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9472 12:46:22.489879 Loading segment from ROM address 0x4010001c
9473 12:46:22.489958 Entry Point 0x80000000
9474 12:46:22.493853 Loaded segments
9475 12:46:22.497027 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9476 12:46:22.503627 Jumping to boot code at 0x80000000(0xffe64000)
9477 12:46:22.510758 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9478 12:46:22.517075 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9479 12:46:22.524435 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9480 12:46:22.528113 Checking segment from ROM address 0x40100000
9481 12:46:22.531375 Checking segment from ROM address 0x4010001c
9482 12:46:22.538120 Loading segment from ROM address 0x40100000
9483 12:46:22.538193 code (compression=1)
9484 12:46:22.544671 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9485 12:46:22.554330 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9486 12:46:22.554405 using LZMA
9487 12:46:22.563033 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9488 12:46:22.569543 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9489 12:46:22.572945 Loading segment from ROM address 0x4010001c
9490 12:46:22.573016 Entry Point 0x54601000
9491 12:46:22.576208 Loaded segments
9492 12:46:22.579387 NOTICE: MT8192 bl31_setup
9493 12:46:22.586409 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9494 12:46:22.589814 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9495 12:46:22.593284 WARNING: region 0:
9496 12:46:22.596666 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9497 12:46:22.596740 WARNING: region 1:
9498 12:46:22.603128 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9499 12:46:22.606593 WARNING: region 2:
9500 12:46:22.609833 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9501 12:46:22.612896 WARNING: region 3:
9502 12:46:22.616478 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9503 12:46:22.620175 WARNING: region 4:
9504 12:46:22.626853 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9505 12:46:22.626927 WARNING: region 5:
9506 12:46:22.630002 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9507 12:46:22.633028 WARNING: region 6:
9508 12:46:22.636377 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9509 12:46:22.639663 WARNING: region 7:
9510 12:46:22.642880 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9511 12:46:22.649623 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9512 12:46:22.652827 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9513 12:46:22.656659 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9514 12:46:22.663591 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9515 12:46:22.666721 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9516 12:46:22.669867 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9517 12:46:22.676395 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9518 12:46:22.679684 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9519 12:46:22.686703 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9520 12:46:22.690091 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9521 12:46:22.693374 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9522 12:46:22.699838 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9523 12:46:22.703095 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9524 12:46:22.706490 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9525 12:46:22.712994 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9526 12:46:22.716658 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9527 12:46:22.723304 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9528 12:46:22.726379 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9529 12:46:22.729776 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9530 12:46:22.736466 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9531 12:46:22.739561 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9532 12:46:22.743312 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9533 12:46:22.749643 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9534 12:46:22.752986 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9535 12:46:22.759585 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9536 12:46:22.762903 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9537 12:46:22.766248 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9538 12:46:22.773631 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9539 12:46:22.776810 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9540 12:46:22.783335 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9541 12:46:22.786542 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9542 12:46:22.790070 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9543 12:46:22.796779 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9544 12:46:22.800021 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9545 12:46:22.803089 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9546 12:46:22.806814 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9547 12:46:22.810057 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9548 12:46:22.816733 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9549 12:46:22.820107 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9550 12:46:22.823529 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9551 12:46:22.826971 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9552 12:46:22.833424 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9553 12:46:22.836600 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9554 12:46:22.840577 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9555 12:46:22.843500 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9556 12:46:22.850115 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9557 12:46:22.853591 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9558 12:46:22.856832 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9559 12:46:22.863608 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9560 12:46:22.867245 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9561 12:46:22.870657 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9562 12:46:22.877009 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9563 12:46:22.880401 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9564 12:46:22.887108 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9565 12:46:22.890449 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9566 12:46:22.893758 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9567 12:46:22.900790 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9568 12:46:22.903718 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9569 12:46:22.910742 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9570 12:46:22.913663 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9571 12:46:22.920630 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9572 12:46:22.923922 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9573 12:46:22.930534 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9574 12:46:22.933836 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9575 12:46:22.936887 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9576 12:46:22.944105 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9577 12:46:22.947328 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9578 12:46:22.954021 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9579 12:46:22.957402 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9580 12:46:22.963991 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9581 12:46:22.967073 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9582 12:46:22.970574 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9583 12:46:22.977306 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9584 12:46:22.980957 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9585 12:46:22.987255 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9586 12:46:22.990795 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9587 12:46:22.997616 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9588 12:46:23.000819 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9589 12:46:23.004256 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9590 12:46:23.010621 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9591 12:46:23.013901 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9592 12:46:23.020442 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9593 12:46:23.024283 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9594 12:46:23.030388 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9595 12:46:23.033964 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9596 12:46:23.037444 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9597 12:46:23.044293 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9598 12:46:23.047196 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9599 12:46:23.053733 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9600 12:46:23.057616 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9601 12:46:23.064207 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9602 12:46:23.067507 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9603 12:46:23.070802 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9604 12:46:23.077771 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9605 12:46:23.081011 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9606 12:46:23.087431 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9607 12:46:23.090813 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9608 12:46:23.093910 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9609 12:46:23.097640 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9610 12:46:23.104052 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9611 12:46:23.107745 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9612 12:46:23.111219 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9613 12:46:23.117778 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9614 12:46:23.121016 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9615 12:46:23.127563 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9616 12:46:23.130606 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9617 12:46:23.134037 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9618 12:46:23.141028 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9619 12:46:23.144091 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9620 12:46:23.150639 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9621 12:46:23.154298 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9622 12:46:23.157347 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9623 12:46:23.164208 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9624 12:46:23.167481 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9625 12:46:23.174088 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9626 12:46:23.177323 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9627 12:46:23.180666 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9628 12:46:23.183831 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9629 12:46:23.190759 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9630 12:46:23.194050 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9631 12:46:23.197409 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9632 12:46:23.200668 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9633 12:46:23.207379 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9634 12:46:23.210781 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9635 12:46:23.214531 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9636 12:46:23.220849 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9637 12:46:23.224193 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9638 12:46:23.230536 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9639 12:46:23.234024 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9640 12:46:23.237683 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9641 12:46:23.244071 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9642 12:46:23.247389 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9643 12:46:23.250515 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9644 12:46:23.257707 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9645 12:46:23.261033 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9646 12:46:23.267444 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9647 12:46:23.271108 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9648 12:46:23.274138 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9649 12:46:23.280750 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9650 12:46:23.284411 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9651 12:46:23.287843 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9652 12:46:23.294376 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9653 12:46:23.297560 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9654 12:46:23.304163 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9655 12:46:23.307527 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9656 12:46:23.310844 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9657 12:46:23.317498 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9658 12:46:23.320921 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9659 12:46:23.328073 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9660 12:46:23.330793 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9661 12:46:23.334510 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9662 12:46:23.340980 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9663 12:46:23.344235 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9664 12:46:23.347881 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9665 12:46:23.354289 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9666 12:46:23.357550 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9667 12:46:23.364157 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9668 12:46:23.367356 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9669 12:46:23.370589 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9670 12:46:23.377459 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9671 12:46:23.380778 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9672 12:46:23.387367 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9673 12:46:23.391229 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9674 12:46:23.394178 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9675 12:46:23.400492 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9676 12:46:23.404222 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9677 12:46:23.410887 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9678 12:46:23.413816 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9679 12:46:23.417570 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9680 12:46:23.424058 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9681 12:46:23.427325 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9682 12:46:23.434007 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9683 12:46:23.437300 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9684 12:46:23.440787 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9685 12:46:23.447261 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9686 12:46:23.450433 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9687 12:46:23.454254 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9688 12:46:23.461024 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9689 12:46:23.464015 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9690 12:46:23.470638 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9691 12:46:23.473957 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9692 12:46:23.477439 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9693 12:46:23.483952 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9694 12:46:23.486968 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9695 12:46:23.494085 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9696 12:46:23.497297 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9697 12:46:23.500661 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9698 12:46:23.507246 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9699 12:46:23.510410 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9700 12:46:23.517253 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9701 12:46:23.520469 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9702 12:46:23.523953 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9703 12:46:23.530724 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9704 12:46:23.533970 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9705 12:46:23.540523 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9706 12:46:23.543824 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9707 12:46:23.547177 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9708 12:46:23.553759 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9709 12:46:23.557110 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9710 12:46:23.563529 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9711 12:46:23.566678 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9712 12:46:23.573259 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9713 12:46:23.577071 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9714 12:46:23.580205 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9715 12:46:23.586753 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9716 12:46:23.590503 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9717 12:46:23.597024 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9718 12:46:23.600414 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9719 12:46:23.603721 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9720 12:46:23.610568 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9721 12:46:23.613858 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9722 12:46:23.620254 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9723 12:46:23.623538 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9724 12:46:23.630020 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9725 12:46:23.633841 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9726 12:46:23.636828 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9727 12:46:23.643396 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9728 12:46:23.646721 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9729 12:46:23.653351 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9730 12:46:23.656647 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9731 12:46:23.659966 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9732 12:46:23.666629 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9733 12:46:23.669918 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9734 12:46:23.676451 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9735 12:46:23.679746 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9736 12:46:23.686983 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9737 12:46:23.689967 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9738 12:46:23.693274 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9739 12:46:23.700369 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9740 12:46:23.703738 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9741 12:46:23.706367 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9742 12:46:23.710084 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9743 12:46:23.716845 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9744 12:46:23.720185 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9745 12:46:23.723476 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9746 12:46:23.730249 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9747 12:46:23.733380 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9748 12:46:23.736802 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9749 12:46:23.743531 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9750 12:46:23.746666 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9751 12:46:23.750169 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9752 12:46:23.756301 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9753 12:46:23.759531 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9754 12:46:23.762904 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9755 12:46:23.769481 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9756 12:46:23.772718 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9757 12:46:23.779872 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9758 12:46:23.783298 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9759 12:46:23.786526 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9760 12:46:23.792584 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9761 12:46:23.796278 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9762 12:46:23.802955 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9763 12:46:23.806231 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9764 12:46:23.809373 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9765 12:46:23.815991 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9766 12:46:23.819305 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9767 12:46:23.822489 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9768 12:46:23.829316 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9769 12:46:23.832610 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9770 12:46:23.835810 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9771 12:46:23.842742 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9772 12:46:23.845616 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9773 12:46:23.852485 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9774 12:46:23.855833 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9775 12:46:23.858738 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9776 12:46:23.865723 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9777 12:46:23.868835 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9778 12:46:23.872147 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9779 12:46:23.879107 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9780 12:46:23.882155 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9781 12:46:23.885908 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9782 12:46:23.889239 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9783 12:46:23.895853 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9784 12:46:23.898573 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9785 12:46:23.901863 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9786 12:46:23.905541 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9787 12:46:23.912196 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9788 12:46:23.915519 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9789 12:46:23.918844 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9790 12:46:23.922409 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9791 12:46:23.928395 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9792 12:46:23.931988 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9793 12:46:23.935227 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9794 12:46:23.941962 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9795 12:46:23.945769 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9796 12:46:23.951785 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9797 12:46:23.955723 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9798 12:46:23.958402 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9799 12:46:23.965122 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9800 12:46:23.968366 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9801 12:46:23.975517 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9802 12:46:23.978472 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9803 12:46:23.981795 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9804 12:46:23.988703 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9805 12:46:23.992632 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9806 12:46:23.998952 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9807 12:46:24.002304 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9808 12:46:24.004944 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9809 12:46:24.011695 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9810 12:46:24.014995 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9811 12:46:24.021686 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9812 12:46:24.025374 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9813 12:46:24.032083 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9814 12:46:24.035150 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9815 12:46:24.038500 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9816 12:46:24.044841 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9817 12:46:24.048135 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9818 12:46:24.054737 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9819 12:46:24.057987 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9820 12:46:24.061217 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9821 12:46:24.067955 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9822 12:46:24.071726 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9823 12:46:24.078374 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9824 12:46:24.081645 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9825 12:46:24.084988 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9826 12:46:24.091653 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9827 12:46:24.094787 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9828 12:46:24.101828 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9829 12:46:24.105094 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9830 12:46:24.108273 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9831 12:46:24.114525 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9832 12:46:24.118324 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9833 12:46:24.124646 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9834 12:46:24.128503 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9835 12:46:24.131558 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9836 12:46:24.138038 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9837 12:46:24.141567 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9838 12:46:24.148648 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9839 12:46:24.151643 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9840 12:46:24.154801 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9841 12:46:24.161395 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9842 12:46:24.164552 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9843 12:46:24.171189 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9844 12:46:24.174304 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9845 12:46:24.181026 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9846 12:46:24.184524 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9847 12:46:24.187981 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9848 12:46:24.194830 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9849 12:46:24.198169 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9850 12:46:24.204670 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9851 12:46:24.208231 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9852 12:46:24.211198 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9853 12:46:24.217906 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9854 12:46:24.221298 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9855 12:46:24.228080 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9856 12:46:24.230815 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9857 12:46:24.234736 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9858 12:46:24.241134 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9859 12:46:24.244317 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9860 12:46:24.251073 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9861 12:46:24.254288 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9862 12:46:24.257618 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9863 12:46:24.264404 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9864 12:46:24.267735 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9865 12:46:24.274539 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9866 12:46:24.277610 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9867 12:46:24.284933 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9868 12:46:24.287467 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9869 12:46:24.290659 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9870 12:46:24.297461 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9871 12:46:24.300809 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9872 12:46:24.307437 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9873 12:46:24.310757 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9874 12:46:24.317335 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9875 12:46:24.320646 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9876 12:46:24.323837 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9877 12:46:24.330554 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9878 12:46:24.333781 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9879 12:46:24.340903 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9880 12:46:24.344229 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9881 12:46:24.350903 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9882 12:46:24.354316 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9883 12:46:24.360954 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9884 12:46:24.364222 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9885 12:46:24.367718 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9886 12:46:24.374699 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9887 12:46:24.377663 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9888 12:46:24.384216 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9889 12:46:24.387392 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9890 12:46:24.394221 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9891 12:46:24.397403 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9892 12:46:24.400692 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9893 12:46:24.407306 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9894 12:46:24.411124 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9895 12:46:24.417732 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9896 12:46:24.421286 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9897 12:46:24.424380 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9898 12:46:24.431365 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9899 12:46:24.434536 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9900 12:46:24.440786 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9901 12:46:24.444500 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9902 12:46:24.450855 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9903 12:46:24.454224 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9904 12:46:24.457508 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9905 12:46:24.464115 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9906 12:46:24.467260 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9907 12:46:24.473830 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9908 12:46:24.477782 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9909 12:46:24.483658 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9910 12:46:24.487388 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9911 12:46:24.493892 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9912 12:46:24.497046 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9913 12:46:24.500203 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9914 12:46:24.507109 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9915 12:46:24.510709 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9916 12:46:24.516725 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9917 12:46:24.520069 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9918 12:46:24.526716 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9919 12:46:24.530151 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9920 12:46:24.536807 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9921 12:46:24.540511 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9922 12:46:24.546992 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9923 12:46:24.550723 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9924 12:46:24.553385 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9925 12:46:24.560038 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9926 12:46:24.563321 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9927 12:46:24.569879 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9928 12:46:24.573422 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9929 12:46:24.580034 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9930 12:46:24.583534 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9931 12:46:24.589949 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9932 12:46:24.593638 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9933 12:46:24.600137 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9934 12:46:24.603544 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9935 12:46:24.610025 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9936 12:46:24.613202 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9937 12:46:24.619926 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9938 12:46:24.623067 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9939 12:46:24.629950 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9940 12:46:24.632974 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9941 12:46:24.639825 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9942 12:46:24.643007 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9943 12:46:24.649842 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9944 12:46:24.653149 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9945 12:46:24.659702 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9946 12:46:24.659907 INFO: [APUAPC] vio 0
9947 12:46:24.666312 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9948 12:46:24.670064 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9949 12:46:24.673158 INFO: [APUAPC] D0_APC_0: 0x400510
9950 12:46:24.676466 INFO: [APUAPC] D0_APC_1: 0x0
9951 12:46:24.679675 INFO: [APUAPC] D0_APC_2: 0x1540
9952 12:46:24.682987 INFO: [APUAPC] D0_APC_3: 0x0
9953 12:46:24.686328 INFO: [APUAPC] D1_APC_0: 0xffffffff
9954 12:46:24.689736 INFO: [APUAPC] D1_APC_1: 0xffffffff
9955 12:46:24.693129 INFO: [APUAPC] D1_APC_2: 0x3fffff
9956 12:46:24.696246 INFO: [APUAPC] D1_APC_3: 0x0
9957 12:46:24.699672 INFO: [APUAPC] D2_APC_0: 0xffffffff
9958 12:46:24.703021 INFO: [APUAPC] D2_APC_1: 0xffffffff
9959 12:46:24.706114 INFO: [APUAPC] D2_APC_2: 0x3fffff
9960 12:46:24.709973 INFO: [APUAPC] D2_APC_3: 0x0
9961 12:46:24.713490 INFO: [APUAPC] D3_APC_0: 0xffffffff
9962 12:46:24.716843 INFO: [APUAPC] D3_APC_1: 0xffffffff
9963 12:46:24.720181 INFO: [APUAPC] D3_APC_2: 0x3fffff
9964 12:46:24.723563 INFO: [APUAPC] D3_APC_3: 0x0
9965 12:46:24.726930 INFO: [APUAPC] D4_APC_0: 0xffffffff
9966 12:46:24.730025 INFO: [APUAPC] D4_APC_1: 0xffffffff
9967 12:46:24.733185 INFO: [APUAPC] D4_APC_2: 0x3fffff
9968 12:46:24.733603 INFO: [APUAPC] D4_APC_3: 0x0
9969 12:46:24.736324 INFO: [APUAPC] D5_APC_0: 0xffffffff
9970 12:46:24.739659 INFO: [APUAPC] D5_APC_1: 0xffffffff
9971 12:46:24.743455 INFO: [APUAPC] D5_APC_2: 0x3fffff
9972 12:46:24.746466 INFO: [APUAPC] D5_APC_3: 0x0
9973 12:46:24.750015 INFO: [APUAPC] D6_APC_0: 0xffffffff
9974 12:46:24.753046 INFO: [APUAPC] D6_APC_1: 0xffffffff
9975 12:46:24.756626 INFO: [APUAPC] D6_APC_2: 0x3fffff
9976 12:46:24.759615 INFO: [APUAPC] D6_APC_3: 0x0
9977 12:46:24.763415 INFO: [APUAPC] D7_APC_0: 0xffffffff
9978 12:46:24.766479 INFO: [APUAPC] D7_APC_1: 0xffffffff
9979 12:46:24.769550 INFO: [APUAPC] D7_APC_2: 0x3fffff
9980 12:46:24.772982 INFO: [APUAPC] D7_APC_3: 0x0
9981 12:46:24.776199 INFO: [APUAPC] D8_APC_0: 0xffffffff
9982 12:46:24.779895 INFO: [APUAPC] D8_APC_1: 0xffffffff
9983 12:46:24.782698 INFO: [APUAPC] D8_APC_2: 0x3fffff
9984 12:46:24.786214 INFO: [APUAPC] D8_APC_3: 0x0
9985 12:46:24.789571 INFO: [APUAPC] D9_APC_0: 0xffffffff
9986 12:46:24.792840 INFO: [APUAPC] D9_APC_1: 0xffffffff
9987 12:46:24.796994 INFO: [APUAPC] D9_APC_2: 0x3fffff
9988 12:46:24.799971 INFO: [APUAPC] D9_APC_3: 0x0
9989 12:46:24.803105 INFO: [APUAPC] D10_APC_0: 0xffffffff
9990 12:46:24.806337 INFO: [APUAPC] D10_APC_1: 0xffffffff
9991 12:46:24.809640 INFO: [APUAPC] D10_APC_2: 0x3fffff
9992 12:46:24.812759 INFO: [APUAPC] D10_APC_3: 0x0
9993 12:46:24.816025 INFO: [APUAPC] D11_APC_0: 0xffffffff
9994 12:46:24.819700 INFO: [APUAPC] D11_APC_1: 0xffffffff
9995 12:46:24.822817 INFO: [APUAPC] D11_APC_2: 0x3fffff
9996 12:46:24.825887 INFO: [APUAPC] D11_APC_3: 0x0
9997 12:46:24.829225 INFO: [APUAPC] D12_APC_0: 0xffffffff
9998 12:46:24.832540 INFO: [APUAPC] D12_APC_1: 0xffffffff
9999 12:46:24.836366 INFO: [APUAPC] D12_APC_2: 0x3fffff
10000 12:46:24.839417 INFO: [APUAPC] D12_APC_3: 0x0
10001 12:46:24.842684 INFO: [APUAPC] D13_APC_0: 0xffffffff
10002 12:46:24.846005 INFO: [APUAPC] D13_APC_1: 0xffffffff
10003 12:46:24.849344 INFO: [APUAPC] D13_APC_2: 0x3fffff
10004 12:46:24.852678 INFO: [APUAPC] D13_APC_3: 0x0
10005 12:46:24.856319 INFO: [APUAPC] D14_APC_0: 0xffffffff
10006 12:46:24.859358 INFO: [APUAPC] D14_APC_1: 0xffffffff
10007 12:46:24.862681 INFO: [APUAPC] D14_APC_2: 0x3fffff
10008 12:46:24.866170 INFO: [APUAPC] D14_APC_3: 0x0
10009 12:46:24.869275 INFO: [APUAPC] D15_APC_0: 0xffffffff
10010 12:46:24.873242 INFO: [APUAPC] D15_APC_1: 0xffffffff
10011 12:46:24.875878 INFO: [APUAPC] D15_APC_2: 0x3fffff
10012 12:46:24.879787 INFO: [APUAPC] D15_APC_3: 0x0
10013 12:46:24.882943 INFO: [APUAPC] APC_CON: 0x4
10014 12:46:24.886210 INFO: [NOCDAPC] D0_APC_0: 0x0
10015 12:46:24.889617 INFO: [NOCDAPC] D0_APC_1: 0x0
10016 12:46:24.892748 INFO: [NOCDAPC] D1_APC_0: 0x0
10017 12:46:24.896041 INFO: [NOCDAPC] D1_APC_1: 0xfff
10018 12:46:24.896496 INFO: [NOCDAPC] D2_APC_0: 0x0
10019 12:46:24.899105 INFO: [NOCDAPC] D2_APC_1: 0xfff
10020 12:46:24.902637 INFO: [NOCDAPC] D3_APC_0: 0x0
10021 12:46:24.906007 INFO: [NOCDAPC] D3_APC_1: 0xfff
10022 12:46:24.909292 INFO: [NOCDAPC] D4_APC_0: 0x0
10023 12:46:24.912430 INFO: [NOCDAPC] D4_APC_1: 0xfff
10024 12:46:24.916094 INFO: [NOCDAPC] D5_APC_0: 0x0
10025 12:46:24.919490 INFO: [NOCDAPC] D5_APC_1: 0xfff
10026 12:46:24.922704 INFO: [NOCDAPC] D6_APC_0: 0x0
10027 12:46:24.925971 INFO: [NOCDAPC] D6_APC_1: 0xfff
10028 12:46:24.929301 INFO: [NOCDAPC] D7_APC_0: 0x0
10029 12:46:24.929724 INFO: [NOCDAPC] D7_APC_1: 0xfff
10030 12:46:24.932348 INFO: [NOCDAPC] D8_APC_0: 0x0
10031 12:46:24.935895 INFO: [NOCDAPC] D8_APC_1: 0xfff
10032 12:46:24.939143 INFO: [NOCDAPC] D9_APC_0: 0x0
10033 12:46:24.942389 INFO: [NOCDAPC] D9_APC_1: 0xfff
10034 12:46:24.945550 INFO: [NOCDAPC] D10_APC_0: 0x0
10035 12:46:24.948815 INFO: [NOCDAPC] D10_APC_1: 0xfff
10036 12:46:24.952139 INFO: [NOCDAPC] D11_APC_0: 0x0
10037 12:46:24.955452 INFO: [NOCDAPC] D11_APC_1: 0xfff
10038 12:46:24.958826 INFO: [NOCDAPC] D12_APC_0: 0x0
10039 12:46:24.961847 INFO: [NOCDAPC] D12_APC_1: 0xfff
10040 12:46:24.965003 INFO: [NOCDAPC] D13_APC_0: 0x0
10041 12:46:24.968367 INFO: [NOCDAPC] D13_APC_1: 0xfff
10042 12:46:24.971702 INFO: [NOCDAPC] D14_APC_0: 0x0
10043 12:46:24.974627 INFO: [NOCDAPC] D14_APC_1: 0xfff
10044 12:46:24.974708 INFO: [NOCDAPC] D15_APC_0: 0x0
10045 12:46:24.978567 INFO: [NOCDAPC] D15_APC_1: 0xfff
10046 12:46:24.981463 INFO: [NOCDAPC] APC_CON: 0x4
10047 12:46:24.984538 INFO: [APUAPC] set_apusys_apc done
10048 12:46:24.988227 INFO: [DEVAPC] devapc_init done
10049 12:46:24.994875 INFO: GICv3 without legacy support detected.
10050 12:46:24.998278 INFO: ARM GICv3 driver initialized in EL3
10051 12:46:25.001681 INFO: Maximum SPI INTID supported: 639
10052 12:46:25.004987 INFO: BL31: Initializing runtime services
10053 12:46:25.011510 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10054 12:46:25.015206 INFO: SPM: enable CPC mode
10055 12:46:25.017929 INFO: mcdi ready for mcusys-off-idle and system suspend
10056 12:46:25.024741 INFO: BL31: Preparing for EL3 exit to normal world
10057 12:46:25.027817 INFO: Entry point address = 0x80000000
10058 12:46:25.027948 INFO: SPSR = 0x8
10059 12:46:25.034455
10060 12:46:25.034624
10061 12:46:25.034765
10062 12:46:25.038198 Starting depthcharge on Spherion...
10063 12:46:25.038382
10064 12:46:25.038588 Wipe memory regions:
10065 12:46:25.038784
10066 12:46:25.040370 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10067 12:46:25.040617 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10068 12:46:25.040820 Setting prompt string to ['asurada:']
10069 12:46:25.041012 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10070 12:46:25.041369 [0x00000040000000, 0x00000054600000)
10071 12:46:25.164162
10072 12:46:25.164399 [0x00000054660000, 0x00000080000000)
10073 12:46:25.424171
10074 12:46:25.424347 [0x000000821a7280, 0x000000ffe64000)
10075 12:46:26.169207
10076 12:46:26.169345 [0x00000100000000, 0x00000240000000)
10077 12:46:28.059521
10078 12:46:28.062540 Initializing XHCI USB controller at 0x11200000.
10079 12:46:29.101401
10080 12:46:29.104234 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10081 12:46:29.104700
10082 12:46:29.105133
10083 12:46:29.105539
10084 12:46:29.106408 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10086 12:46:29.207669 asurada: tftpboot 192.168.201.1 12703557/tftp-deploy-4emrxmv5/kernel/image.itb 12703557/tftp-deploy-4emrxmv5/kernel/cmdline
10087 12:46:29.208327 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10088 12:46:29.208808 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10089 12:46:29.213707 tftpboot 192.168.201.1 12703557/tftp-deploy-4emrxmv5/kernel/image.ittp-deploy-4emrxmv5/kernel/cmdline
10090 12:46:29.214142
10091 12:46:29.214577 Waiting for link
10092 12:46:29.374284
10093 12:46:29.374787 R8152: Initializing
10094 12:46:29.375231
10095 12:46:29.377518 Version 9 (ocp_data = 6010)
10096 12:46:29.377948
10097 12:46:29.380709 R8152: Done initializing
10098 12:46:29.381140
10099 12:46:29.381576 Adding net device
10100 12:46:31.249638
10101 12:46:31.250188 done.
10102 12:46:31.250672
10103 12:46:31.251129 MAC: 00:e0:4c:78:7a:aa
10104 12:46:31.251570
10105 12:46:31.252723 Sending DHCP discover... done.
10106 12:46:31.253199
10107 12:46:31.255767 Waiting for reply... done.
10108 12:46:31.256411
10109 12:46:31.259181 Sending DHCP request... done.
10110 12:46:31.259645
10111 12:46:31.263012 Waiting for reply... done.
10112 12:46:31.263492
10113 12:46:31.263818 My ip is 192.168.201.12
10114 12:46:31.264128
10115 12:46:31.266675 The DHCP server ip is 192.168.201.1
10116 12:46:31.267097
10117 12:46:31.273020 TFTP server IP predefined by user: 192.168.201.1
10118 12:46:31.273451
10119 12:46:31.279806 Bootfile predefined by user: 12703557/tftp-deploy-4emrxmv5/kernel/image.itb
10120 12:46:31.280394
10121 12:46:31.282844 Sending tftp read request... done.
10122 12:46:31.283370
10123 12:46:31.289220 Waiting for the transfer...
10124 12:46:31.289675
10125 12:46:31.664465 00000000 ################################################################
10126 12:46:31.664669
10127 12:46:31.916858 00080000 ################################################################
10128 12:46:31.916992
10129 12:46:32.176222 00100000 ################################################################
10130 12:46:32.176402
10131 12:46:32.447178 00180000 ################################################################
10132 12:46:32.447310
10133 12:46:32.712268 00200000 ################################################################
10134 12:46:32.712424
10135 12:46:32.996854 00280000 ################################################################
10136 12:46:32.996982
10137 12:46:33.284321 00300000 ################################################################
10138 12:46:33.284466
10139 12:46:33.569391 00380000 ################################################################
10140 12:46:33.569562
10141 12:46:33.857916 00400000 ################################################################
10142 12:46:33.858050
10143 12:46:34.128858 00480000 ################################################################
10144 12:46:34.128990
10145 12:46:34.408566 00500000 ################################################################
10146 12:46:34.408697
10147 12:46:34.677646 00580000 ################################################################
10148 12:46:34.677778
10149 12:46:34.944882 00600000 ################################################################
10150 12:46:34.945037
10151 12:46:35.196561 00680000 ################################################################
10152 12:46:35.196689
10153 12:46:35.446018 00700000 ################################################################
10154 12:46:35.446180
10155 12:46:35.711170 00780000 ################################################################
10156 12:46:35.711306
10157 12:46:35.994286 00800000 ################################################################
10158 12:46:35.994420
10159 12:46:36.279147 00880000 ################################################################
10160 12:46:36.279286
10161 12:46:36.539693 00900000 ################################################################
10162 12:46:36.539822
10163 12:46:36.813400 00980000 ################################################################
10164 12:46:36.813555
10165 12:46:37.096786 00a00000 ################################################################
10166 12:46:37.096918
10167 12:46:37.380777 00a80000 ################################################################
10168 12:46:37.380926
10169 12:46:37.666282 00b00000 ################################################################
10170 12:46:37.666417
10171 12:46:37.930447 00b80000 ################################################################
10172 12:46:37.930611
10173 12:46:38.202091 00c00000 ################################################################
10174 12:46:38.202226
10175 12:46:38.467407 00c80000 ################################################################
10176 12:46:38.467540
10177 12:46:38.730349 00d00000 ################################################################
10178 12:46:38.730483
10179 12:46:38.997407 00d80000 ################################################################
10180 12:46:38.997541
10181 12:46:39.259992 00e00000 ################################################################
10182 12:46:39.260119
10183 12:46:39.532861 00e80000 ################################################################
10184 12:46:39.532995
10185 12:46:39.802569 00f00000 ################################################################
10186 12:46:39.802703
10187 12:46:40.076082 00f80000 ################################################################
10188 12:46:40.076211
10189 12:46:40.356075 01000000 ################################################################
10190 12:46:40.356214
10191 12:46:40.625689 01080000 ################################################################
10192 12:46:40.625823
10193 12:46:40.895229 01100000 ################################################################
10194 12:46:40.895367
10195 12:46:41.165698 01180000 ################################################################
10196 12:46:41.165836
10197 12:46:41.446832 01200000 ################################################################
10198 12:46:41.446967
10199 12:46:41.729656 01280000 ################################################################
10200 12:46:41.729789
10201 12:46:42.019850 01300000 ################################################################
10202 12:46:42.019987
10203 12:46:42.291844 01380000 ################################################################
10204 12:46:42.291981
10205 12:46:42.557448 01400000 ################################################################
10206 12:46:42.557610
10207 12:46:42.813594 01480000 ################################################################
10208 12:46:42.813731
10209 12:46:43.070976 01500000 ################################################################
10210 12:46:43.071110
10211 12:46:43.340131 01580000 ################################################################
10212 12:46:43.340293
10213 12:46:43.607881 01600000 ################################################################
10214 12:46:43.608016
10215 12:46:43.889412 01680000 ################################################################
10216 12:46:43.889567
10217 12:46:44.170757 01700000 ################################################################
10218 12:46:44.170887
10219 12:46:44.449294 01780000 ################################################################
10220 12:46:44.449481
10221 12:46:44.699182 01800000 ################################################################
10222 12:46:44.699319
10223 12:46:44.959447 01880000 ################################################################
10224 12:46:44.959582
10225 12:46:45.239808 01900000 ################################################################
10226 12:46:45.239943
10227 12:46:45.505056 01980000 ################################################################
10228 12:46:45.505192
10229 12:46:45.772098 01a00000 ################################################################
10230 12:46:45.772253
10231 12:46:46.040325 01a80000 ################################################################
10232 12:46:46.040498
10233 12:46:46.309967 01b00000 ################################################################
10234 12:46:46.310095
10235 12:46:46.562536 01b80000 ################################################################
10236 12:46:46.562691
10237 12:46:46.833141 01c00000 ################################################################
10238 12:46:46.833272
10239 12:46:46.841483 01c80000 ### done.
10240 12:46:46.841590
10241 12:46:46.845137 The bootfile was 29903926 bytes long.
10242 12:46:46.845219
10243 12:46:46.848601 Sending tftp read request... done.
10244 12:46:46.848690
10245 12:46:46.852099 Waiting for the transfer...
10246 12:46:46.852203
10247 12:46:46.852302 00000000 # done.
10248 12:46:46.852403
10249 12:46:46.861472 Command line loaded dynamically from TFTP file: 12703557/tftp-deploy-4emrxmv5/kernel/cmdline
10250 12:46:46.861567
10251 12:46:46.881523 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12703557/extract-nfsrootfs-4y1kaca8,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10252 12:46:46.881655
10253 12:46:46.885199 Loading FIT.
10254 12:46:46.885292
10255 12:46:46.888282 Image ramdisk-1 has 17801754 bytes.
10256 12:46:46.888392
10257 12:46:46.891351 Image fdt-1 has 47278 bytes.
10258 12:46:46.891486
10259 12:46:46.891606 Image kernel-1 has 12052857 bytes.
10260 12:46:46.891706
10261 12:46:46.901767 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10262 12:46:46.901894
10263 12:46:46.918234 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10264 12:46:46.918482
10265 12:46:46.925374 Choosing best match conf-1 for compat google,spherion-rev2.
10266 12:46:46.929212
10267 12:46:46.934206 Connected to device vid:did:rid of 1ae0:0028:00
10268 12:46:46.942075
10269 12:46:46.945573 tpm_get_response: command 0x17b, return code 0x0
10270 12:46:46.945875
10271 12:46:46.949027 ec_init: CrosEC protocol v3 supported (256, 248)
10272 12:46:46.952775
10273 12:46:46.955854 tpm_cleanup: add release locality here.
10274 12:46:46.956154
10275 12:46:46.956450 Shutting down all USB controllers.
10276 12:46:46.959351
10277 12:46:46.959654 Removing current net device
10278 12:46:46.959890
10279 12:46:46.966144 Exiting depthcharge with code 4 at timestamp: 51179564
10280 12:46:46.966446
10281 12:46:46.969001 LZMA decompressing kernel-1 to 0x821a6718
10282 12:46:46.969435
10283 12:46:46.972536 LZMA decompressing kernel-1 to 0x40000000
10284 12:46:48.472101
10285 12:46:48.472630 jumping to kernel
10286 12:46:48.474183 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
10287 12:46:48.474681 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10288 12:46:48.475064 Setting prompt string to ['Linux version [0-9]']
10289 12:46:48.475409 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10290 12:46:48.475757 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10291 12:46:48.555289
10292 12:46:48.558798 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10293 12:46:48.562513 start: 2.2.5.1 login-action (timeout 00:04:02) [common]
10294 12:46:48.562971 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10295 12:46:48.563327 Setting prompt string to []
10296 12:46:48.563703 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10297 12:46:48.564063 Using line separator: #'\n'#
10298 12:46:48.564384 No login prompt set.
10299 12:46:48.564685 Parsing kernel messages
10300 12:46:48.564961 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10301 12:46:48.565534 [login-action] Waiting for messages, (timeout 00:04:02)
10302 12:46:48.565899 Waiting using forced prompt support (timeout 00:02:01)
10303 12:46:48.582082 [ 0.000000] Linux version 6.1.75-cip14 (KernelCI@build-j98433-arm64-gcc-10-defconfig-arm64-chromebook-89n64) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Feb 5 12:20:06 UTC 2024
10304 12:46:48.585003 [ 0.000000] random: crng init done
10305 12:46:48.591706 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10306 12:46:48.595370 [ 0.000000] efi: UEFI not found.
10307 12:46:48.601586 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10308 12:46:48.608424 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10309 12:46:48.618196 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10310 12:46:48.628578 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10311 12:46:48.634974 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10312 12:46:48.641427 [ 0.000000] printk: bootconsole [mtk8250] enabled
10313 12:46:48.648372 [ 0.000000] NUMA: No NUMA configuration found
10314 12:46:48.654722 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10315 12:46:48.658445 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10316 12:46:48.661538 [ 0.000000] Zone ranges:
10317 12:46:48.668582 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10318 12:46:48.671742 [ 0.000000] DMA32 empty
10319 12:46:48.678061 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10320 12:46:48.681315 [ 0.000000] Movable zone start for each node
10321 12:46:48.684464 [ 0.000000] Early memory node ranges
10322 12:46:48.691583 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10323 12:46:48.698283 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10324 12:46:48.704593 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10325 12:46:48.708378 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10326 12:46:48.714523 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10327 12:46:48.721413 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10328 12:46:48.779927 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10329 12:46:48.786176 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10330 12:46:48.793182 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10331 12:46:48.796621 [ 0.000000] psci: probing for conduit method from DT.
10332 12:46:48.802869 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10333 12:46:48.806121 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10334 12:46:48.813020 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10335 12:46:48.816613 [ 0.000000] psci: SMC Calling Convention v1.2
10336 12:46:48.823098 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10337 12:46:48.826273 [ 0.000000] Detected VIPT I-cache on CPU0
10338 12:46:48.832925 [ 0.000000] CPU features: detected: GIC system register CPU interface
10339 12:46:48.839710 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10340 12:46:48.846419 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10341 12:46:48.853363 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10342 12:46:48.859740 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10343 12:46:48.866066 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10344 12:46:48.872539 [ 0.000000] alternatives: applying boot alternatives
10345 12:46:48.876262 [ 0.000000] Fallback order for Node 0: 0
10346 12:46:48.882833 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10347 12:46:48.886194 [ 0.000000] Policy zone: Normal
10348 12:46:48.909554 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12703557/extract-nfsrootfs-4y1kaca8,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10349 12:46:48.922683 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10350 12:46:48.932369 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10351 12:46:48.942381 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10352 12:46:48.949061 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10353 12:46:48.952250 <6>[ 0.000000] software IO TLB: area num 8.
10354 12:46:49.008739 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10355 12:46:49.158310 <6>[ 0.000000] Memory: 7949872K/8385536K available (17984K kernel code, 4118K rwdata, 19612K rodata, 8448K init, 616K bss, 402896K reserved, 32768K cma-reserved)
10356 12:46:49.164696 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10357 12:46:49.171342 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10358 12:46:49.174695 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10359 12:46:49.181652 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10360 12:46:49.187864 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10361 12:46:49.191658 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10362 12:46:49.201116 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10363 12:46:49.207583 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10364 12:46:49.211102 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10365 12:46:49.219227 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10366 12:46:49.222742 <6>[ 0.000000] GICv3: 608 SPIs implemented
10367 12:46:49.228742 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10368 12:46:49.232172 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10369 12:46:49.235601 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10370 12:46:49.244955 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10371 12:46:49.255054 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10372 12:46:49.268600 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10373 12:46:49.275105 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10374 12:46:49.284003 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10375 12:46:49.297501 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10376 12:46:49.304250 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10377 12:46:49.310999 <6>[ 0.009183] Console: colour dummy device 80x25
10378 12:46:49.320682 <6>[ 0.013899] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10379 12:46:49.323952 <6>[ 0.024340] pid_max: default: 32768 minimum: 301
10380 12:46:49.330755 <6>[ 0.029211] LSM: Security Framework initializing
10381 12:46:49.337484 <6>[ 0.034180] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10382 12:46:49.347513 <6>[ 0.041995] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10383 12:46:49.353972 <6>[ 0.051409] cblist_init_generic: Setting adjustable number of callback queues.
10384 12:46:49.360488 <6>[ 0.058853] cblist_init_generic: Setting shift to 3 and lim to 1.
10385 12:46:49.370370 <6>[ 0.065191] cblist_init_generic: Setting adjustable number of callback queues.
10386 12:46:49.373822 <6>[ 0.072664] cblist_init_generic: Setting shift to 3 and lim to 1.
10387 12:46:49.381084 <6>[ 0.079103] rcu: Hierarchical SRCU implementation.
10388 12:46:49.387429 <6>[ 0.084119] rcu: Max phase no-delay instances is 1000.
10389 12:46:49.394015 <6>[ 0.091178] EFI services will not be available.
10390 12:46:49.397043 <6>[ 0.096162] smp: Bringing up secondary CPUs ...
10391 12:46:49.405178 <6>[ 0.101215] Detected VIPT I-cache on CPU1
10392 12:46:49.411510 <6>[ 0.101285] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10393 12:46:49.418331 <6>[ 0.101316] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10394 12:46:49.421686 <6>[ 0.101658] Detected VIPT I-cache on CPU2
10395 12:46:49.428397 <6>[ 0.101709] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10396 12:46:49.434790 <6>[ 0.101728] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10397 12:46:49.442001 <6>[ 0.101991] Detected VIPT I-cache on CPU3
10398 12:46:49.448020 <6>[ 0.102038] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10399 12:46:49.454952 <6>[ 0.102052] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10400 12:46:49.457952 <6>[ 0.102355] CPU features: detected: Spectre-v4
10401 12:46:49.464458 <6>[ 0.102360] CPU features: detected: Spectre-BHB
10402 12:46:49.468125 <6>[ 0.102366] Detected PIPT I-cache on CPU4
10403 12:46:49.474630 <6>[ 0.102423] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10404 12:46:49.481627 <6>[ 0.102439] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10405 12:46:49.488089 <6>[ 0.102730] Detected PIPT I-cache on CPU5
10406 12:46:49.494755 <6>[ 0.102792] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10407 12:46:49.501311 <6>[ 0.102809] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10408 12:46:49.504463 <6>[ 0.103092] Detected PIPT I-cache on CPU6
10409 12:46:49.511103 <6>[ 0.103156] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10410 12:46:49.517480 <6>[ 0.103172] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10411 12:46:49.524217 <6>[ 0.103469] Detected PIPT I-cache on CPU7
10412 12:46:49.530606 <6>[ 0.103533] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10413 12:46:49.537242 <6>[ 0.103549] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10414 12:46:49.541194 <6>[ 0.103595] smp: Brought up 1 node, 8 CPUs
10415 12:46:49.547308 <6>[ 0.244919] SMP: Total of 8 processors activated.
10416 12:46:49.550541 <6>[ 0.249840] CPU features: detected: 32-bit EL0 Support
10417 12:46:49.560888 <6>[ 0.255202] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10418 12:46:49.567437 <6>[ 0.264002] CPU features: detected: Common not Private translations
10419 12:46:49.573944 <6>[ 0.270477] CPU features: detected: CRC32 instructions
10420 12:46:49.577136 <6>[ 0.275828] CPU features: detected: RCpc load-acquire (LDAPR)
10421 12:46:49.583621 <6>[ 0.281788] CPU features: detected: LSE atomic instructions
10422 12:46:49.590204 <6>[ 0.287569] CPU features: detected: Privileged Access Never
10423 12:46:49.596920 <6>[ 0.293349] CPU features: detected: RAS Extension Support
10424 12:46:49.604032 <6>[ 0.298957] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10425 12:46:49.607203 <6>[ 0.306177] CPU: All CPU(s) started at EL2
10426 12:46:49.613327 <6>[ 0.310521] alternatives: applying system-wide alternatives
10427 12:46:49.622430 <6>[ 0.321244] devtmpfs: initialized
10428 12:46:49.635277 <6>[ 0.330117] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10429 12:46:49.645111 <6>[ 0.340080] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10430 12:46:49.651361 <6>[ 0.348298] pinctrl core: initialized pinctrl subsystem
10431 12:46:49.654704 <6>[ 0.354929] DMI not present or invalid.
10432 12:46:49.661891 <6>[ 0.359340] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10433 12:46:49.671268 <6>[ 0.366140] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10434 12:46:49.678345 <6>[ 0.373728] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10435 12:46:49.688071 <6>[ 0.381954] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10436 12:46:49.691280 <6>[ 0.390201] audit: initializing netlink subsys (disabled)
10437 12:46:49.700770 <5>[ 0.395893] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10438 12:46:49.707850 <6>[ 0.396583] thermal_sys: Registered thermal governor 'step_wise'
10439 12:46:49.714082 <6>[ 0.403864] thermal_sys: Registered thermal governor 'power_allocator'
10440 12:46:49.717610 <6>[ 0.410118] cpuidle: using governor menu
10441 12:46:49.724235 <6>[ 0.421076] NET: Registered PF_QIPCRTR protocol family
10442 12:46:49.731089 <6>[ 0.426557] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10443 12:46:49.737491 <6>[ 0.433660] ASID allocator initialised with 32768 entries
10444 12:46:49.740819 <6>[ 0.440205] Serial: AMBA PL011 UART driver
10445 12:46:49.750152 <4>[ 0.448946] Trying to register duplicate clock ID: 134
10446 12:46:49.804345 <6>[ 0.506329] KASLR enabled
10447 12:46:49.819057 <6>[ 0.513965] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10448 12:46:49.825527 <6>[ 0.520979] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10449 12:46:49.832439 <6>[ 0.527467] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10450 12:46:49.839877 <6>[ 0.534472] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10451 12:46:49.845556 <6>[ 0.540956] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10452 12:46:49.852122 <6>[ 0.547960] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10453 12:46:49.858927 <6>[ 0.554447] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10454 12:46:49.865450 <6>[ 0.561449] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10455 12:46:49.868381 <6>[ 0.568903] ACPI: Interpreter disabled.
10456 12:46:49.876856 <6>[ 0.575332] iommu: Default domain type: Translated
10457 12:46:49.883670 <6>[ 0.580444] iommu: DMA domain TLB invalidation policy: strict mode
10458 12:46:49.887089 <5>[ 0.587106] SCSI subsystem initialized
10459 12:46:49.893718 <6>[ 0.591354] usbcore: registered new interface driver usbfs
10460 12:46:49.900173 <6>[ 0.597085] usbcore: registered new interface driver hub
10461 12:46:49.903425 <6>[ 0.602638] usbcore: registered new device driver usb
10462 12:46:49.910177 <6>[ 0.608756] pps_core: LinuxPPS API ver. 1 registered
10463 12:46:49.920005 <6>[ 0.613951] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10464 12:46:49.923514 <6>[ 0.623299] PTP clock support registered
10465 12:46:49.926939 <6>[ 0.627541] EDAC MC: Ver: 3.0.0
10466 12:46:49.934423 <6>[ 0.632716] FPGA manager framework
10467 12:46:49.941034 <6>[ 0.636391] Advanced Linux Sound Architecture Driver Initialized.
10468 12:46:49.944007 <6>[ 0.643157] vgaarb: loaded
10469 12:46:49.950731 <6>[ 0.646306] clocksource: Switched to clocksource arch_sys_counter
10470 12:46:49.954433 <5>[ 0.652748] VFS: Disk quotas dquot_6.6.0
10471 12:46:49.960782 <6>[ 0.656936] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10472 12:46:49.963983 <6>[ 0.664127] pnp: PnP ACPI: disabled
10473 12:46:49.972161 <6>[ 0.670737] NET: Registered PF_INET protocol family
10474 12:46:49.982026 <6>[ 0.676326] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10475 12:46:49.993358 <6>[ 0.688646] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10476 12:46:50.003302 <6>[ 0.697464] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10477 12:46:50.010005 <6>[ 0.705438] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10478 12:46:50.016802 <6>[ 0.714136] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10479 12:46:50.028456 <6>[ 0.723888] TCP: Hash tables configured (established 65536 bind 65536)
10480 12:46:50.035392 <6>[ 0.730761] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10481 12:46:50.041894 <6>[ 0.737965] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10482 12:46:50.048424 <6>[ 0.745670] NET: Registered PF_UNIX/PF_LOCAL protocol family
10483 12:46:50.055431 <6>[ 0.751816] RPC: Registered named UNIX socket transport module.
10484 12:46:50.058471 <6>[ 0.757970] RPC: Registered udp transport module.
10485 12:46:50.065449 <6>[ 0.762905] RPC: Registered tcp transport module.
10486 12:46:50.071874 <6>[ 0.767838] RPC: Registered tcp NFSv4.1 backchannel transport module.
10487 12:46:50.074964 <6>[ 0.774501] PCI: CLS 0 bytes, default 64
10488 12:46:50.078660 <6>[ 0.778834] Unpacking initramfs...
10489 12:46:50.103498 <6>[ 0.798425] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10490 12:46:50.112927 <6>[ 0.807068] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10491 12:46:50.116237 <6>[ 0.815915] kvm [1]: IPA Size Limit: 40 bits
10492 12:46:50.122924 <6>[ 0.820444] kvm [1]: GICv3: no GICV resource entry
10493 12:46:50.126717 <6>[ 0.825466] kvm [1]: disabling GICv2 emulation
10494 12:46:50.133411 <6>[ 0.830152] kvm [1]: GIC system register CPU interface enabled
10495 12:46:50.136163 <6>[ 0.836312] kvm [1]: vgic interrupt IRQ18
10496 12:46:50.143274 <6>[ 0.840664] kvm [1]: VHE mode initialized successfully
10497 12:46:50.149615 <5>[ 0.847080] Initialise system trusted keyrings
10498 12:46:50.156023 <6>[ 0.851870] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10499 12:46:50.163210 <6>[ 0.861900] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10500 12:46:50.169965 <5>[ 0.868317] NFS: Registering the id_resolver key type
10501 12:46:50.173267 <5>[ 0.873616] Key type id_resolver registered
10502 12:46:50.179681 <5>[ 0.878031] Key type id_legacy registered
10503 12:46:50.186608 <6>[ 0.882319] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10504 12:46:50.193043 <6>[ 0.889241] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10505 12:46:50.199412 <6>[ 0.896982] 9p: Installing v9fs 9p2000 file system support
10506 12:46:50.236049 <5>[ 0.934814] Key type asymmetric registered
10507 12:46:50.239559 <5>[ 0.939144] Asymmetric key parser 'x509' registered
10508 12:46:50.249467 <6>[ 0.944280] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10509 12:46:50.252603 <6>[ 0.951895] io scheduler mq-deadline registered
10510 12:46:50.256222 <6>[ 0.956657] io scheduler kyber registered
10511 12:46:50.275166 <6>[ 0.973566] EINJ: ACPI disabled.
10512 12:46:50.306659 <4>[ 0.998695] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10513 12:46:50.317123 <4>[ 1.009333] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10514 12:46:50.331526 <6>[ 1.029778] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10515 12:46:50.339401 <6>[ 1.037612] printk: console [ttyS0] disabled
10516 12:46:50.366846 <6>[ 1.062241] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10517 12:46:50.373741 <6>[ 1.071736] printk: console [ttyS0] enabled
10518 12:46:50.377309 <6>[ 1.071736] printk: console [ttyS0] enabled
10519 12:46:50.383588 <6>[ 1.080630] printk: bootconsole [mtk8250] disabled
10520 12:46:50.386973 <6>[ 1.080630] printk: bootconsole [mtk8250] disabled
10521 12:46:50.393483 <6>[ 1.091653] SuperH (H)SCI(F) driver initialized
10522 12:46:50.396836 <6>[ 1.096923] msm_serial: driver initialized
10523 12:46:50.410866 <6>[ 1.105843] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10524 12:46:50.420996 <6>[ 1.114388] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10525 12:46:50.427246 <6>[ 1.122930] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10526 12:46:50.437341 <6>[ 1.131559] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10527 12:46:50.443850 <6>[ 1.140265] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10528 12:46:50.453990 <6>[ 1.148986] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10529 12:46:50.463781 <6>[ 1.157526] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10530 12:46:50.470273 <6>[ 1.166328] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10531 12:46:50.480605 <6>[ 1.174870] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10532 12:46:50.491931 <6>[ 1.190257] loop: module loaded
10533 12:46:50.498356 <6>[ 1.196212] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10534 12:46:50.521385 <4>[ 1.219600] mtk-pmic-keys: Failed to locate of_node [id: -1]
10535 12:46:50.527781 <6>[ 1.226511] megasas: 07.719.03.00-rc1
10536 12:46:50.537789 <6>[ 1.236190] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10537 12:46:50.551597 <6>[ 1.249686] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10538 12:46:50.568046 <6>[ 1.266203] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10539 12:46:50.624805 <6>[ 1.316463] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10540 12:46:50.825253 <6>[ 1.524001] Freeing initrd memory: 17380K
10541 12:46:50.835915 <6>[ 1.534554] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10542 12:46:50.846880 <6>[ 1.545586] tun: Universal TUN/TAP device driver, 1.6
10543 12:46:50.850754 <6>[ 1.551661] thunder_xcv, ver 1.0
10544 12:46:50.854029 <6>[ 1.555171] thunder_bgx, ver 1.0
10545 12:46:50.856803 <6>[ 1.558666] nicpf, ver 1.0
10546 12:46:50.867514 <6>[ 1.562697] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10547 12:46:50.870759 <6>[ 1.570172] hns3: Copyright (c) 2017 Huawei Corporation.
10548 12:46:50.874014 <6>[ 1.575760] hclge is initializing
10549 12:46:50.881061 <6>[ 1.579342] e1000: Intel(R) PRO/1000 Network Driver
10550 12:46:50.887428 <6>[ 1.584471] e1000: Copyright (c) 1999-2006 Intel Corporation.
10551 12:46:50.890554 <6>[ 1.590487] e1000e: Intel(R) PRO/1000 Network Driver
10552 12:46:50.897566 <6>[ 1.595703] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10553 12:46:50.904250 <6>[ 1.601888] igb: Intel(R) Gigabit Ethernet Network Driver
10554 12:46:50.910772 <6>[ 1.607538] igb: Copyright (c) 2007-2014 Intel Corporation.
10555 12:46:50.917413 <6>[ 1.613374] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10556 12:46:50.924069 <6>[ 1.619891] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10557 12:46:50.927468 <6>[ 1.626363] sky2: driver version 1.30
10558 12:46:50.933895 <6>[ 1.631343] VFIO - User Level meta-driver version: 0.3
10559 12:46:50.941102 <6>[ 1.639549] usbcore: registered new interface driver usb-storage
10560 12:46:50.947886 <6>[ 1.645997] usbcore: registered new device driver onboard-usb-hub
10561 12:46:50.956407 <6>[ 1.655178] mt6397-rtc mt6359-rtc: registered as rtc0
10562 12:46:50.967110 <6>[ 1.660649] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-05T12:44:07 UTC (1707137047)
10563 12:46:50.970299 <6>[ 1.670249] i2c_dev: i2c /dev entries driver
10564 12:46:50.986830 <6>[ 1.681881] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10565 12:46:51.007187 <6>[ 1.705874] cpu cpu0: EM: created perf domain
10566 12:46:51.010293 <6>[ 1.710791] cpu cpu4: EM: created perf domain
10567 12:46:51.017840 <6>[ 1.716356] sdhci: Secure Digital Host Controller Interface driver
10568 12:46:51.024619 <6>[ 1.722789] sdhci: Copyright(c) Pierre Ossman
10569 12:46:51.030918 <6>[ 1.727748] Synopsys Designware Multimedia Card Interface Driver
10570 12:46:51.037816 <6>[ 1.734384] sdhci-pltfm: SDHCI platform and OF driver helper
10571 12:46:51.040748 <6>[ 1.734532] mmc0: CQHCI version 5.10
10572 12:46:51.047819 <6>[ 1.744361] ledtrig-cpu: registered to indicate activity on CPUs
10573 12:46:51.054119 <6>[ 1.751308] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10574 12:46:51.060498 <6>[ 1.758373] usbcore: registered new interface driver usbhid
10575 12:46:51.063935 <6>[ 1.764194] usbhid: USB HID core driver
10576 12:46:51.070850 <6>[ 1.768400] spi_master spi0: will run message pump with realtime priority
10577 12:46:51.115358 <6>[ 1.806928] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10578 12:46:51.130963 <6>[ 1.822761] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10579 12:46:51.138044 <6>[ 1.836366] mmc0: Command Queue Engine enabled
10580 12:46:51.145105 <6>[ 1.841147] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10581 12:46:51.151724 <6>[ 1.848082] cros-ec-spi spi0.0: Chrome EC device registered
10582 12:46:51.154957 <6>[ 1.848451] mmcblk0: mmc0:0001 DA4128 116 GiB
10583 12:46:51.164401 <6>[ 1.863215] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10584 12:46:51.172188 <6>[ 1.870660] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10585 12:46:51.178536 <6>[ 1.876550] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10586 12:46:51.185410 <6>[ 1.882470] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10587 12:46:51.200635 <6>[ 1.895827] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10588 12:46:51.208479 <6>[ 1.906698] NET: Registered PF_PACKET protocol family
10589 12:46:51.211291 <6>[ 1.912093] 9pnet: Installing 9P2000 support
10590 12:46:51.218155 <5>[ 1.916659] Key type dns_resolver registered
10591 12:46:51.221957 <6>[ 1.921675] registered taskstats version 1
10592 12:46:51.228363 <5>[ 1.926061] Loading compiled-in X.509 certificates
10593 12:46:51.259743 <4>[ 1.951372] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10594 12:46:51.269711 <4>[ 1.962198] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10595 12:46:51.276072 <3>[ 1.972775] debugfs: File 'uA_load' in directory '/' already present!
10596 12:46:51.283337 <3>[ 1.979492] debugfs: File 'min_uV' in directory '/' already present!
10597 12:46:51.289672 <3>[ 1.986106] debugfs: File 'max_uV' in directory '/' already present!
10598 12:46:51.296597 <3>[ 1.992720] debugfs: File 'constraint_flags' in directory '/' already present!
10599 12:46:51.307141 <3>[ 2.002394] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10600 12:46:51.321648 <6>[ 2.020324] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10601 12:46:51.328829 <6>[ 2.027258] xhci-mtk 11200000.usb: xHCI Host Controller
10602 12:46:51.335225 <6>[ 2.032762] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10603 12:46:51.345360 <6>[ 2.040640] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10604 12:46:51.352527 <6>[ 2.050084] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10605 12:46:51.359156 <6>[ 2.056192] xhci-mtk 11200000.usb: xHCI Host Controller
10606 12:46:51.365657 <6>[ 2.061690] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10607 12:46:51.372457 <6>[ 2.069363] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10608 12:46:51.378620 <6>[ 2.077277] hub 1-0:1.0: USB hub found
10609 12:46:51.382341 <6>[ 2.081307] hub 1-0:1.0: 1 port detected
10610 12:46:51.388591 <6>[ 2.085614] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10611 12:46:51.395707 <6>[ 2.094472] hub 2-0:1.0: USB hub found
10612 12:46:51.398918 <6>[ 2.098504] hub 2-0:1.0: 1 port detected
10613 12:46:51.407644 <6>[ 2.106093] mtk-msdc 11f70000.mmc: Got CD GPIO
10614 12:46:51.419914 <6>[ 2.115242] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10615 12:46:51.426860 <6>[ 2.123276] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10616 12:46:51.436655 <4>[ 2.131209] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10617 12:46:51.446494 <6>[ 2.140795] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10618 12:46:51.453504 <6>[ 2.148873] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10619 12:46:51.459889 <6>[ 2.157011] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10620 12:46:51.470027 <6>[ 2.164944] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10621 12:46:51.476867 <6>[ 2.172765] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10622 12:46:51.486748 <6>[ 2.180583] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10623 12:46:51.496831 <6>[ 2.191066] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10624 12:46:51.503873 <6>[ 2.199457] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10625 12:46:51.513614 <6>[ 2.207800] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10626 12:46:51.520581 <6>[ 2.216141] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10627 12:46:51.530076 <6>[ 2.224480] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10628 12:46:51.537063 <6>[ 2.232818] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10629 12:46:51.547072 <6>[ 2.241157] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10630 12:46:51.553620 <6>[ 2.249496] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10631 12:46:51.563549 <6>[ 2.257845] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10632 12:46:51.570405 <6>[ 2.266186] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10633 12:46:51.580316 <6>[ 2.274525] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10634 12:46:51.587323 <6>[ 2.282864] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10635 12:46:51.597421 <6>[ 2.291204] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10636 12:46:51.603919 <6>[ 2.299542] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10637 12:46:51.613725 <6>[ 2.307883] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10638 12:46:51.620308 <6>[ 2.316666] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10639 12:46:51.627059 <6>[ 2.323951] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10640 12:46:51.634050 <6>[ 2.330866] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10641 12:46:51.640473 <6>[ 2.337758] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10642 12:46:51.647055 <6>[ 2.344793] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10643 12:46:51.657367 <6>[ 2.351665] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10644 12:46:51.666962 <6>[ 2.360796] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10645 12:46:51.676625 <6>[ 2.369915] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10646 12:46:51.683283 <6>[ 2.379209] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10647 12:46:51.693499 <6>[ 2.388676] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10648 12:46:51.703646 <6>[ 2.398142] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10649 12:46:51.713069 <6>[ 2.407261] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10650 12:46:51.723296 <6>[ 2.416726] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10651 12:46:51.733132 <6>[ 2.425844] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10652 12:46:51.743296 <6>[ 2.435138] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10653 12:46:51.753239 <6>[ 2.445299] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10654 12:46:51.762843 <6>[ 2.456501] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10655 12:46:51.769306 <6>[ 2.466257] Trying to probe devices needed for running init ...
10656 12:46:51.798854 <6>[ 2.494521] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10657 12:46:51.953992 <6>[ 2.652447] hub 1-1:1.0: USB hub found
10658 12:46:51.956989 <6>[ 2.656947] hub 1-1:1.0: 4 ports detected
10659 12:46:51.966572 <6>[ 2.665451] hub 1-1:1.0: USB hub found
10660 12:46:51.969910 <6>[ 2.669929] hub 1-1:1.0: 4 ports detected
10661 12:46:52.079403 <6>[ 2.774930] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10662 12:46:52.105703 <6>[ 2.804207] hub 2-1:1.0: USB hub found
10663 12:46:52.108915 <6>[ 2.808696] hub 2-1:1.0: 3 ports detected
10664 12:46:52.118378 <6>[ 2.816833] hub 2-1:1.0: USB hub found
10665 12:46:52.121375 <6>[ 2.821319] hub 2-1:1.0: 3 ports detected
10666 12:46:52.295062 <6>[ 2.990584] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10667 12:46:52.427802 <6>[ 3.126420] hub 1-1.4:1.0: USB hub found
10668 12:46:52.430974 <6>[ 3.131084] hub 1-1.4:1.0: 2 ports detected
10669 12:46:52.440523 <6>[ 3.139035] hub 1-1.4:1.0: USB hub found
10670 12:46:52.443765 <6>[ 3.143638] hub 1-1.4:1.0: 2 ports detected
10671 12:46:52.507358 <6>[ 3.202806] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10672 12:46:52.738891 <6>[ 3.434621] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10673 12:46:52.931301 <6>[ 3.626619] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10674 12:47:04.064170 <6>[ 14.767600] ALSA device list:
10675 12:47:04.070844 <6>[ 14.770898] No soundcards found.
10676 12:47:04.078920 <6>[ 14.778927] Freeing unused kernel memory: 8448K
10677 12:47:04.082106 <6>[ 14.783921] Run /init as init process
10678 12:47:04.093667 Loading, please wait...
10679 12:47:04.118535 Starting version 247.3-7+deb11u2
10680 12:47:04.317700 <6>[ 15.014211] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10681 12:47:04.327973 <3>[ 15.024810] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10682 12:47:04.331987 <6>[ 15.025016] remoteproc remoteproc0: scp is available
10683 12:47:04.341334 <3>[ 15.032953] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10684 12:47:04.344802 <6>[ 15.038411] remoteproc remoteproc0: powering up scp
10685 12:47:04.351841 <6>[ 15.039046] usbcore: registered new device driver r8152-cfgselector
10686 12:47:04.361363 <6>[ 15.044943] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10687 12:47:04.367821 <6>[ 15.044967] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10688 12:47:04.378013 <6>[ 15.044976] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10689 12:47:04.381673 <6>[ 15.046721] mc: Linux media interface: v0.10
10690 12:47:04.391606 <3>[ 15.047390] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10691 12:47:04.398125 <3>[ 15.047461] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10692 12:47:04.408076 <3>[ 15.047464] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10693 12:47:04.414669 <3>[ 15.047467] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10694 12:47:04.420933 <3>[ 15.047472] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10695 12:47:04.430874 <3>[ 15.047476] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10696 12:47:04.437338 <3>[ 15.047499] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10697 12:47:04.447805 <3>[ 15.047525] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10698 12:47:04.454386 <3>[ 15.047527] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10699 12:47:04.464118 <3>[ 15.047530] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10700 12:47:04.470495 <3>[ 15.047544] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10701 12:47:04.480947 <3>[ 15.047546] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10702 12:47:04.487726 <3>[ 15.047549] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10703 12:47:04.493947 <3>[ 15.047551] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10704 12:47:04.504412 <3>[ 15.047554] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10705 12:47:04.510369 <3>[ 15.047567] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10706 12:47:04.520531 <6>[ 15.051790] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10707 12:47:04.527048 <4>[ 15.067722] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10708 12:47:04.533509 <6>[ 15.074149] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10709 12:47:04.540397 <6>[ 15.167751] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10710 12:47:04.547136 <4>[ 15.170582] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10711 12:47:04.554372 <6>[ 15.170603] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10712 12:47:04.564203 <6>[ 15.175258] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10713 12:47:04.571077 <6>[ 15.176313] pci_bus 0000:00: root bus resource [bus 00-ff]
10714 12:47:04.581111 <6>[ 15.190927] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10715 12:47:04.587863 <6>[ 15.192461] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10716 12:47:04.594403 <6>[ 15.199676] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10717 12:47:04.600729 <6>[ 15.200556] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10718 12:47:04.607652 <6>[ 15.201358] videodev: Linux video capture interface: v2.00
10719 12:47:04.617043 <6>[ 15.208608] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10720 12:47:04.623966 <6>[ 15.216777] remoteproc remoteproc0: remote processor scp is now up
10721 12:47:04.631366 <6>[ 15.225151] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10722 12:47:04.640997 <4>[ 15.236669] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10723 12:47:04.644583 <4>[ 15.236669] Fallback method does not support PEC.
10724 12:47:04.651319 <6>[ 15.238075] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10725 12:47:04.661244 <6>[ 15.239237] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10726 12:47:04.667921 <6>[ 15.241476] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10727 12:47:04.678194 <3>[ 15.261510] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10728 12:47:04.681212 <6>[ 15.270000] pci 0000:00:00.0: supports D1 D2
10729 12:47:04.691320 <6>[ 15.278593] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10730 12:47:04.698027 <6>[ 15.284705] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10731 12:47:04.704987 <6>[ 15.285781] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10732 12:47:04.714589 <6>[ 15.296174] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10733 12:47:04.721247 <6>[ 15.299088] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10734 12:47:04.731523 <4>[ 15.322156] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10735 12:47:04.737884 <6>[ 15.323128] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10736 12:47:04.745063 <6>[ 15.323151] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10737 12:47:04.748077 <6>[ 15.323745] Bluetooth: Core ver 2.22
10738 12:47:04.754655 <6>[ 15.323798] NET: Registered PF_BLUETOOTH protocol family
10739 12:47:04.760883 <6>[ 15.323800] Bluetooth: HCI device and connection manager initialized
10740 12:47:04.764342 <6>[ 15.323814] Bluetooth: HCI socket layer initialized
10741 12:47:04.771078 <6>[ 15.323818] Bluetooth: L2CAP socket layer initialized
10742 12:47:04.777897 <6>[ 15.323824] Bluetooth: SCO socket layer initialized
10743 12:47:04.784145 <4>[ 15.329621] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10744 12:47:04.790815 <6>[ 15.335853] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10745 12:47:04.797426 <6>[ 15.335973] pci 0000:01:00.0: supports D1 D2
10746 12:47:04.804024 <3>[ 15.354198] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10747 12:47:04.811002 <6>[ 15.356959] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10748 12:47:04.817322 <6>[ 15.366417] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10749 12:47:04.827256 <6>[ 15.388480] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10750 12:47:04.834001 <6>[ 15.395143] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10751 12:47:04.840280 <6>[ 15.395942] usbcore: registered new interface driver btusb
10752 12:47:04.850542 <4>[ 15.397017] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10753 12:47:04.857133 <3>[ 15.397027] Bluetooth: hci0: Failed to load firmware file (-2)
10754 12:47:04.863989 <3>[ 15.397031] Bluetooth: hci0: Failed to set up firmware (-2)
10755 12:47:04.873547 <4>[ 15.397035] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10756 12:47:04.883580 <6>[ 15.403542] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10757 12:47:04.893486 <6>[ 15.410227] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10758 12:47:04.900141 <6>[ 15.410241] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10759 12:47:04.906986 <6>[ 15.410825] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10760 12:47:04.913610 <6>[ 15.419685] usbcore: registered new interface driver uvcvideo
10761 12:47:04.916456 <6>[ 15.422511] r8152 2-1.3:1.0 eth0: v1.12.13
10762 12:47:04.923923 <6>[ 15.422565] usbcore: registered new interface driver r8152
10763 12:47:04.929754 <6>[ 15.425787] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10764 12:47:04.936641 <6>[ 15.450139] usbcore: registered new interface driver cdc_ether
10765 12:47:04.946159 <6>[ 15.453580] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10766 12:47:04.949888 <6>[ 15.453592] pci 0000:00:00.0: PCI bridge to [bus 01]
10767 12:47:04.956212 <6>[ 15.471049] usbcore: registered new interface driver r8153_ecm
10768 12:47:04.966516 <6>[ 15.476171] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10769 12:47:04.969525 <6>[ 15.476312] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10770 12:47:04.976126 <6>[ 15.489530] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10771 12:47:04.983090 <6>[ 15.497359] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10772 12:47:04.989817 <6>[ 15.688985] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10773 12:47:05.014814 <5>[ 15.711360] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10774 12:47:05.037056 <5>[ 15.733873] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10775 12:47:05.044492 <5>[ 15.741271] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10776 12:47:05.053792 <4>[ 15.749714] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10777 12:47:05.057471 <6>[ 15.758614] cfg80211: failed to load regulatory.db
10778 12:47:05.113540 <6>[ 15.809963] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10779 12:47:05.120151 <6>[ 15.817585] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10780 12:47:05.144493 <6>[ 15.844360] mt7921e 0000:01:00.0: ASIC revision: 79610010
10781 12:47:05.246136 <6>[ 15.942617] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10782 12:47:05.249136 <6>[ 15.942617]
10783 12:47:05.264131 Begin: Loading essential drivers ... done.
10784 12:47:05.267549 Begin: Running /scripts/init-premount ... done.
10785 12:47:05.273775 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10786 12:47:05.284262 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10787 12:47:05.287241 Device /sys/class/net/enx00e04c787aaa found
10788 12:47:05.287321 done.
10789 12:47:05.361520 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10790 12:47:05.516532 <6>[ 16.212887] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10791 12:47:06.357839 <6>[ 17.058205] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10792 12:47:06.366452 <6>[ 17.066992] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10793 12:47:06.460883 IP-Config: no response after 2 secs - giving up
10794 12:47:06.498164 IP-Config: wlp1s0 hardware address d8:f3:bc:78:17:6f mtu 1500 DHCP
10795 12:47:07.213684 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10796 12:47:07.216733 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10797 12:47:07.223525 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10798 12:47:07.230297 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10799 12:47:07.236552 host : mt8192-asurada-spherion-r0-cbg-0
10800 12:47:07.243054 domain : lava-rack
10801 12:47:07.249469 rootserver: 192.168.201.1 rootpath:
10802 12:47:07.249550 filename :
10803 12:47:07.380566 done.
10804 12:47:07.387028 Begin: Running /scripts/nfs-bottom ... done.
10805 12:47:07.407064 Begin: Running /scripts/init-bottom ... done.
10806 12:47:08.546366 <6>[ 19.246954] NET: Registered PF_INET6 protocol family
10807 12:47:08.556147 <6>[ 19.256541] Segment Routing with IPv6
10808 12:47:08.559324 <6>[ 19.260528] In-situ OAM (IOAM) with IPv6
10809 12:47:08.701491 <30>[ 19.385021] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10810 12:47:08.708928 <30>[ 19.409356] systemd[1]: Detected architecture arm64.
10811 12:47:08.728502
10812 12:47:08.731526 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10813 12:47:08.731608
10814 12:47:08.748107 <30>[ 19.448621] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10815 12:47:09.522488 <30>[ 20.219892] systemd[1]: Queued start job for default target Graphical Interface.
10816 12:47:09.556252 <30>[ 20.257018] systemd[1]: Created slice system-getty.slice.
10817 12:47:09.563063 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10818 12:47:09.579354 <30>[ 20.280014] systemd[1]: Created slice system-modprobe.slice.
10819 12:47:09.585858 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10820 12:47:09.603076 <30>[ 20.303808] systemd[1]: Created slice system-serial\x2dgetty.slice.
10821 12:47:09.613156 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10822 12:47:09.627436 <30>[ 20.327649] systemd[1]: Created slice User and Session Slice.
10823 12:47:09.633653 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10824 12:47:09.654597 <30>[ 20.351448] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10825 12:47:09.664142 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10826 12:47:09.682090 <30>[ 20.379352] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10827 12:47:09.688892 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10828 12:47:09.712763 <30>[ 20.406739] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10829 12:47:09.719345 <30>[ 20.418887] systemd[1]: Reached target Local Encrypted Volumes.
10830 12:47:09.725968 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10831 12:47:09.742502 <30>[ 20.443168] systemd[1]: Reached target Paths.
10832 12:47:09.745895 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10833 12:47:09.762409 <30>[ 20.462654] systemd[1]: Reached target Remote File Systems.
10834 12:47:09.768676 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10835 12:47:09.786359 <30>[ 20.486958] systemd[1]: Reached target Slices.
10836 12:47:09.792507 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10837 12:47:09.805835 <30>[ 20.506638] systemd[1]: Reached target Swap.
10838 12:47:09.809648 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10839 12:47:09.830009 <30>[ 20.527088] systemd[1]: Listening on initctl Compatibility Named Pipe.
10840 12:47:09.836636 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10841 12:47:09.843143 <30>[ 20.543064] systemd[1]: Listening on Journal Audit Socket.
10842 12:47:09.849610 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10843 12:47:09.867255 <30>[ 20.567723] systemd[1]: Listening on Journal Socket (/dev/log).
10844 12:47:09.874015 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10845 12:47:09.890662 <30>[ 20.591155] systemd[1]: Listening on Journal Socket.
10846 12:47:09.897361 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10847 12:47:09.914550 <30>[ 20.611946] systemd[1]: Listening on Network Service Netlink Socket.
10848 12:47:09.921551 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10849 12:47:09.936258 <30>[ 20.637052] systemd[1]: Listening on udev Control Socket.
10850 12:47:09.942850 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10851 12:47:09.958168 <30>[ 20.659037] systemd[1]: Listening on udev Kernel Socket.
10852 12:47:09.964776 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10853 12:47:10.014334 <30>[ 20.715120] systemd[1]: Mounting Huge Pages File System...
10854 12:47:10.021310 Mounting [0;1;39mHuge Pages File System[0m...
10855 12:47:10.036124 <30>[ 20.736799] systemd[1]: Mounting POSIX Message Queue File System...
10856 12:47:10.043295 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10857 12:47:10.060825 <30>[ 20.761474] systemd[1]: Mounting Kernel Debug File System...
10858 12:47:10.067501 Mounting [0;1;39mKernel Debug File System[0m...
10859 12:47:10.085586 <30>[ 20.783084] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10860 12:47:10.110450 <30>[ 20.807679] systemd[1]: Starting Create list of static device nodes for the current kernel...
10861 12:47:10.117193 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10862 12:47:10.138355 <30>[ 20.839206] systemd[1]: Starting Load Kernel Module configfs...
10863 12:47:10.145383 Starting [0;1;39mLoad Kernel Module configfs[0m...
10864 12:47:10.166397 <30>[ 20.866932] systemd[1]: Starting Load Kernel Module drm...
10865 12:47:10.172610 Starting [0;1;39mLoad Kernel Module drm[0m...
10866 12:47:10.190865 <30>[ 20.891290] systemd[1]: Starting Load Kernel Module fuse...
10867 12:47:10.197328 Starting [0;1;39mLoad Kernel Module fuse[0m...
10868 12:47:10.224353 <6>[ 20.925161] fuse: init (API version 7.37)
10869 12:47:10.234398 <30>[ 20.926239] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10870 12:47:10.246743 <30>[ 20.947397] systemd[1]: Starting Journal Service...
10871 12:47:10.253123 Starting [0;1;39mJournal Service[0m...
10872 12:47:10.274925 <30>[ 20.975451] systemd[1]: Starting Load Kernel Modules...
10873 12:47:10.281151 Starting [0;1;39mLoad Kernel Modules[0m...
10874 12:47:10.303648 <30>[ 21.001061] systemd[1]: Starting Remount Root and Kernel File Systems...
10875 12:47:10.310160 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10876 12:47:10.326426 <30>[ 21.026777] systemd[1]: Starting Coldplug All udev Devices...
10877 12:47:10.332965 Starting [0;1;39mColdplug All udev Devices[0m...
10878 12:47:10.352237 <30>[ 21.053050] systemd[1]: Mounted Huge Pages File System.
10879 12:47:10.360157 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10880 12:47:10.370079 <3>[ 21.065512] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10881 12:47:10.376567 <30>[ 21.075523] systemd[1]: Mounted POSIX Message Queue File System.
10882 12:47:10.383385 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10883 12:47:10.400456 <3>[ 21.097894] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10884 12:47:10.407426 <30>[ 21.107218] systemd[1]: Mounted Kernel Debug File System.
10885 12:47:10.413488 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10886 12:47:10.434442 <30>[ 21.131516] systemd[1]: Finished Create list of static device nodes for the current kernel.
10887 12:47:10.444916 <3>[ 21.136546] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10888 12:47:10.451052 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10889 12:47:10.466946 <30>[ 21.167767] systemd[1]: modprobe@configfs.service: Succeeded.
10890 12:47:10.477053 <3>[ 21.172573] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10891 12:47:10.484184 <30>[ 21.174832] systemd[1]: Finished Load Kernel Module configfs.
10892 12:47:10.490743 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10893 12:47:10.506544 <3>[ 21.203882] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10894 12:47:10.513627 <30>[ 21.214391] systemd[1]: modprobe@drm.service: Succeeded.
10895 12:47:10.521035 <30>[ 21.221164] systemd[1]: Finished Load Kernel Module drm.
10896 12:47:10.527395 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10897 12:47:10.538235 <3>[ 21.235969] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10898 12:47:10.545828 <30>[ 21.246505] systemd[1]: modprobe@fuse.service: Succeeded.
10899 12:47:10.552734 <30>[ 21.253698] systemd[1]: Finished Load Kernel Module fuse.
10900 12:47:10.560274 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10901 12:47:10.569925 <3>[ 21.267596] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 12:47:10.577601 <30>[ 21.278387] systemd[1]: Finished Load Kernel Modules.
10903 12:47:10.584159 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10904 12:47:10.603064 <30>[ 21.300367] systemd[1]: Finished Remount Root and Kernel File Systems.
10905 12:47:10.609204 <3>[ 21.300439] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 12:47:10.616442 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10907 12:47:10.641097 <3>[ 21.338286] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10908 12:47:10.670830 <3>[ 21.368328] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 12:47:10.680959 <30>[ 21.381614] systemd[1]: Mounting FUSE Control File System...
10910 12:47:10.687544 Mounting [0;1;39mFUSE Control File System[0m...
10911 12:47:10.708250 <30>[ 21.405227] systemd[1]: Mounting Kernel Configuration File System...
10912 12:47:10.711431 Mounting [0;1;39mKernel Configuration File System[0m...
10913 12:47:10.732155 <30>[ 21.429801] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10914 12:47:10.742558 <30>[ 21.438864] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10915 12:47:10.751673 <30>[ 21.452232] systemd[1]: Starting Load/Save Random Seed...
10916 12:47:10.758129 Starting [0;1;39mLoad/Save Random Seed[0m...
10917 12:47:10.782135 <30>[ 21.482836] systemd[1]: Starting Apply Kernel Variables...
10918 12:47:10.789005 Starting [0;1;39mApply Kernel Variables[0m...
10919 12:47:10.806823 <30>[ 21.507286] systemd[1]: Starting Create System Users...
10920 12:47:10.814228 Starting [0;1;39mCreate System Users[0m...
10921 12:47:10.830276 <4>[ 21.519384] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10922 12:47:10.836873 <3>[ 21.535124] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10923 12:47:10.844665 <30>[ 21.545650] systemd[1]: Started Journal Service.
10924 12:47:10.851752 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10925 12:47:10.875203 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10926 12:47:10.886008 See 'systemctl status systemd-udev-trigger.service' for details.
10927 12:47:10.903795 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10928 12:47:10.922861 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10929 12:47:10.939930 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10930 12:47:10.955741 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10931 12:47:10.971709 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10932 12:47:11.015609 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10933 12:47:11.032645 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10934 12:47:11.060807 <46>[ 21.757786] systemd-journald[289]: Received client request to flush runtime journal.
10935 12:47:11.100071 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10936 12:47:11.119105 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10937 12:47:11.138527 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10938 12:47:11.190719 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10939 12:47:12.472255 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10940 12:47:12.510675 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10941 12:47:12.530256 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10942 12:47:12.612308 Starting [0;1;39mNetwork Service[0m...
10943 12:47:12.895045 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10944 12:47:12.916672 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10945 12:47:12.962002 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10946 12:47:13.282785 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10947 12:47:13.301556 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10948 12:47:13.338780 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10949 12:47:13.359966 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10950 12:47:13.378378 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10951 12:47:13.398358 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10952 12:47:13.422586 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10953 12:47:13.510326 Starting [0;1;39mNetwork Name Resolution[0m...
10954 12:47:13.539293 Starting [0;1;39mNetwork Time Synchronization[0m...
10955 12:47:13.556742 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10956 12:47:13.590019 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10957 12:47:13.709771 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10958 12:47:13.727440 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10959 12:47:13.744991 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10960 12:47:13.758027 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10961 12:47:13.774088 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10962 12:47:13.808686 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10963 12:47:13.885576 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10964 12:47:13.927883 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10965 12:47:13.984650 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10966 12:47:13.997951 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10967 12:47:14.023801 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10968 12:47:14.037659 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10969 12:47:14.053616 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10970 12:47:14.094305 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10971 12:47:14.193817 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10972 12:47:14.254126 Starting [0;1;39mUser Login Management[0m...
10973 12:47:14.271060 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10974 12:47:14.286015 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10975 12:47:14.305585 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10976 12:47:14.363094 Starting [0;1;39mPermit User Sessions[0m...
10977 12:47:14.459034 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10978 12:47:14.503022 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10979 12:47:14.540166 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10980 12:47:14.554569 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10981 12:47:14.577730 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10982 12:47:14.593375 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10983 12:47:14.612989 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10984 12:47:14.631938 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10985 12:47:14.692896 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10986 12:47:14.726665 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10987 12:47:14.825485
10988 12:47:14.825616
10989 12:47:14.828564 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10990 12:47:14.828647
10991 12:47:14.832303 debian-bullseye-arm64 login: root (automatic login)
10992 12:47:14.832400
10993 12:47:14.832464
10994 12:47:15.157996 Linux debian-bullseye-arm64 6.1.75-cip14 #1 SMP PREEMPT Mon Feb 5 12:20:06 UTC 2024 aarch64
10995 12:47:15.158145
10996 12:47:15.164741 The programs included with the Debian GNU/Linux system are free software;
10997 12:47:15.170955 the exact distribution terms for each program are described in the
10998 12:47:15.174446 individual files in /usr/share/doc/*/copyright.
10999 12:47:15.174528
11000 12:47:15.180953 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11001 12:47:15.183991 permitted by applicable law.
11002 12:47:15.977987 Matched prompt #10: / #
11004 12:47:15.978418 Setting prompt string to ['/ #']
11005 12:47:15.978553 end: 2.2.5.1 login-action (duration 00:00:27) [common]
11007 12:47:15.978850 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11008 12:47:15.978978 start: 2.2.6 expect-shell-connection (timeout 00:03:34) [common]
11009 12:47:15.979081 Setting prompt string to ['/ #']
11010 12:47:15.979174 Forcing a shell prompt, looking for ['/ #']
11012 12:47:16.029454 / #
11013 12:47:16.029718 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11014 12:47:16.029837 Waiting using forced prompt support (timeout 00:02:30)
11015 12:47:16.035208
11016 12:47:16.035576 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11017 12:47:16.035721 start: 2.2.7 export-device-env (timeout 00:03:34) [common]
11019 12:47:16.136171 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12703557/extract-nfsrootfs-4y1kaca8'
11020 12:47:16.141809 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12703557/extract-nfsrootfs-4y1kaca8'
11022 12:47:16.242472 / # export NFS_SERVER_IP='192.168.201.1'
11023 12:47:16.248223 export NFS_SERVER_IP='192.168.201.1'
11024 12:47:16.248631 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11025 12:47:16.248777 end: 2.2 depthcharge-retry (duration 00:01:26) [common]
11026 12:47:16.248908 end: 2 depthcharge-action (duration 00:01:26) [common]
11027 12:47:16.249040 start: 3 lava-test-retry (timeout 00:07:53) [common]
11028 12:47:16.249167 start: 3.1 lava-test-shell (timeout 00:07:53) [common]
11029 12:47:16.249276 Using namespace: common
11031 12:47:16.349668 / # #
11032 12:47:16.349899 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11033 12:47:16.354913 #
11034 12:47:16.355231 Using /lava-12703557
11036 12:47:16.455624 / # export SHELL=/bin/bash
11037 12:47:16.460989 export SHELL=/bin/bash
11039 12:47:16.561606 / # . /lava-12703557/environment
11040 12:47:16.567603 . /lava-12703557/environment
11042 12:47:16.673198 / # /lava-12703557/bin/lava-test-runner /lava-12703557/0
11043 12:47:16.673421 Test shell timeout: 10s (minimum of the action and connection timeout)
11044 12:47:16.678880 /lava-12703557/bin/lava-test-runner /lava-12703557/0
11045 12:47:16.928336 + export TESTRUN_ID=0_timesync-off
11046 12:47:16.931886 + TESTRUN_ID=0_timesync-off
11047 12:47:16.935044 + cd /lava-12703557/0/tests/0_timesync-off
11048 12:47:16.938808 ++ cat uuid
11049 12:47:16.938933 + UUID=12703557_1.6.2.3.1
11050 12:47:16.941540 + set +x
11051 12:47:16.945126 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12703557_1.6.2.3.1>
11052 12:47:16.945408 Received signal: <STARTRUN> 0_timesync-off 12703557_1.6.2.3.1
11053 12:47:16.945481 Starting test lava.0_timesync-off (12703557_1.6.2.3.1)
11054 12:47:16.945566 Skipping test definition patterns.
11055 12:47:16.948279 + systemctl stop systemd-timesyncd
11056 12:47:17.006881 + set +x
11057 12:47:17.010298 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12703557_1.6.2.3.1>
11058 12:47:17.010574 Received signal: <ENDRUN> 0_timesync-off 12703557_1.6.2.3.1
11059 12:47:17.010654 Ending use of test pattern.
11060 12:47:17.010716 Ending test lava.0_timesync-off (12703557_1.6.2.3.1), duration 0.07
11062 12:47:17.071153 + export TESTRUN_ID=1_kselftest-arm64
11063 12:47:17.071311 + TESTRUN_ID=1_kselftest-arm64
11064 12:47:17.077898 + cd /lava-12703557/0/tests/1_kselftest-arm64
11065 12:47:17.078009 ++ cat uuid
11066 12:47:17.081747 + UUID=12703557_1.6.2.3.5
11067 12:47:17.081835 + set +x
11068 12:47:17.088151 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 12703557_1.6.2.3.5>
11069 12:47:17.088429 Received signal: <STARTRUN> 1_kselftest-arm64 12703557_1.6.2.3.5
11070 12:47:17.088503 Starting test lava.1_kselftest-arm64 (12703557_1.6.2.3.5)
11071 12:47:17.088585 Skipping test definition patterns.
11072 12:47:17.091231 + cd ./automated/linux/kselftest/
11073 12:47:17.118097 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11074 12:47:17.147665 INFO: install_deps skipped
11075 12:47:17.262443 --2024-02-05 12:44:33-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11076 12:47:17.283763 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11077 12:47:17.420133 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11078 12:47:17.556514 HTTP request sent, awaiting response... 200 OK
11079 12:47:17.559983 Length: 2966020 (2.8M) [application/octet-stream]
11080 12:47:17.562882 Saving to: 'kselftest.tar.xz'
11081 12:47:17.562994
11082 12:47:17.563089
11083 12:47:17.829628 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11084 12:47:18.103229 kselftest.tar.xz 1%[ ] 47.81K 177KB/s
11085 12:47:18.561059 kselftest.tar.xz 7%[> ] 217.50K 402KB/s
11086 12:47:18.845417 kselftest.tar.xz 28%[====> ] 815.64K 818KB/s
11087 12:47:18.852138 kselftest.tar.xz 84%[===============> ] 2.40M 1.87MB/s
11088 12:47:18.858313 kselftest.tar.xz 100%[===================>] 2.83M 2.20MB/s in 1.3s
11089 12:47:18.858461
11090 12:47:19.120274 2024-02-05 12:44:35 (2.20 MB/s) - 'kselftest.tar.xz' saved [2966020/2966020]
11091 12:47:19.120474
11092 12:47:24.569165 skiplist:
11093 12:47:24.572308 ========================================
11094 12:47:24.575787 ========================================
11095 12:47:24.617337 arm64:tags_test
11096 12:47:24.620461 arm64:run_tags_test.sh
11097 12:47:24.620553 arm64:fake_sigreturn_bad_magic
11098 12:47:24.623762 arm64:fake_sigreturn_bad_size
11099 12:47:24.627538 arm64:fake_sigreturn_bad_size_for_magic0
11100 12:47:24.630632 arm64:fake_sigreturn_duplicated_fpsimd
11101 12:47:24.633883 arm64:fake_sigreturn_misaligned_sp
11102 12:47:24.637610 arm64:fake_sigreturn_missing_fpsimd
11103 12:47:24.640768 arm64:fake_sigreturn_sme_change_vl
11104 12:47:24.644022 arm64:fake_sigreturn_sve_change_vl
11105 12:47:24.647332 arm64:mangle_pstate_invalid_compat_toggle
11106 12:47:24.650442 arm64:mangle_pstate_invalid_daif_bits
11107 12:47:24.654072 arm64:mangle_pstate_invalid_mode_el1h
11108 12:47:24.657233 arm64:mangle_pstate_invalid_mode_el1t
11109 12:47:24.660132 arm64:mangle_pstate_invalid_mode_el2h
11110 12:47:24.663793 arm64:mangle_pstate_invalid_mode_el2t
11111 12:47:24.666782 arm64:mangle_pstate_invalid_mode_el3h
11112 12:47:24.670518 arm64:mangle_pstate_invalid_mode_el3t
11113 12:47:24.673539 arm64:sme_trap_no_sm
11114 12:47:24.676922 arm64:sme_trap_non_streaming
11115 12:47:24.677028 arm64:sme_trap_za
11116 12:47:24.680061 arm64:sme_vl
11117 12:47:24.680176 arm64:ssve_regs
11118 12:47:24.683733 arm64:sve_regs
11119 12:47:24.683846 arm64:sve_vl
11120 12:47:24.683939 arm64:za_no_regs
11121 12:47:24.686970 arm64:za_regs
11122 12:47:24.687079 arm64:pac
11123 12:47:24.690311 arm64:fp-stress
11124 12:47:24.690420 arm64:sve-ptrace
11125 12:47:24.693252 arm64:sve-probe-vls
11126 12:47:24.693361 arm64:vec-syscfg
11127 12:47:24.693453 arm64:za-fork
11128 12:47:24.696476 arm64:za-ptrace
11129 12:47:24.700391 arm64:check_buffer_fill
11130 12:47:24.700503 arm64:check_child_memory
11131 12:47:24.703542 arm64:check_gcr_el1_cswitch
11132 12:47:24.706717 arm64:check_ksm_options
11133 12:47:24.706825 arm64:check_mmap_options
11134 12:47:24.709904 arm64:check_prctl
11135 12:47:24.713384 arm64:check_tags_inclusion
11136 12:47:24.713492 arm64:check_user_mem
11137 12:47:24.716413 arm64:btitest
11138 12:47:24.716519 arm64:nobtitest
11139 12:47:24.716612 arm64:hwcap
11140 12:47:24.719913 arm64:ptrace
11141 12:47:24.720021 arm64:syscall-abi
11142 12:47:24.723447 arm64:tpidr2
11143 12:47:24.726368 ============== Tests to run ===============
11144 12:47:24.726481 arm64:tags_test
11145 12:47:24.730123 arm64:run_tags_test.sh
11146 12:47:24.732953 arm64:fake_sigreturn_bad_magic
11147 12:47:24.733063 arm64:fake_sigreturn_bad_size
11148 12:47:24.740023 arm64:fake_sigreturn_bad_size_for_magic0
11149 12:47:24.743011 arm64:fake_sigreturn_duplicated_fpsimd
11150 12:47:24.746239 arm64:fake_sigreturn_misaligned_sp
11151 12:47:24.749507 arm64:fake_sigreturn_missing_fpsimd
11152 12:47:24.749622 arm64:fake_sigreturn_sme_change_vl
11153 12:47:24.752843 arm64:fake_sigreturn_sve_change_vl
11154 12:47:24.759774 arm64:mangle_pstate_invalid_compat_toggle
11155 12:47:24.762784 arm64:mangle_pstate_invalid_daif_bits
11156 12:47:24.766431 arm64:mangle_pstate_invalid_mode_el1h
11157 12:47:24.769503 arm64:mangle_pstate_invalid_mode_el1t
11158 12:47:24.772718 arm64:mangle_pstate_invalid_mode_el2h
11159 12:47:24.776051 arm64:mangle_pstate_invalid_mode_el2t
11160 12:47:24.779412 arm64:mangle_pstate_invalid_mode_el3h
11161 12:47:24.783266 arm64:mangle_pstate_invalid_mode_el3t
11162 12:47:24.783372 arm64:sme_trap_no_sm
11163 12:47:24.786236 arm64:sme_trap_non_streaming
11164 12:47:24.789759 arm64:sme_trap_za
11165 12:47:24.789863 arm64:sme_vl
11166 12:47:24.789953 arm64:ssve_regs
11167 12:47:24.792559 arm64:sve_regs
11168 12:47:24.792661 arm64:sve_vl
11169 12:47:24.795823 arm64:za_no_regs
11170 12:47:24.795925 arm64:za_regs
11171 12:47:24.796016 arm64:pac
11172 12:47:24.799636 arm64:fp-stress
11173 12:47:24.799741 arm64:sve-ptrace
11174 12:47:24.802819 arm64:sve-probe-vls
11175 12:47:24.802923 arm64:vec-syscfg
11176 12:47:24.805889 arm64:za-fork
11177 12:47:24.805992 arm64:za-ptrace
11178 12:47:24.809422 arm64:check_buffer_fill
11179 12:47:24.809525 arm64:check_child_memory
11180 12:47:24.812644 arm64:check_gcr_el1_cswitch
11181 12:47:24.815822 arm64:check_ksm_options
11182 12:47:24.815926 arm64:check_mmap_options
11183 12:47:24.819579 arm64:check_prctl
11184 12:47:24.822748 arm64:check_tags_inclusion
11185 12:47:24.822853 arm64:check_user_mem
11186 12:47:24.825981 arm64:btitest
11187 12:47:24.826088 arm64:nobtitest
11188 12:47:24.826181 arm64:hwcap
11189 12:47:24.829444 arm64:ptrace
11190 12:47:24.829552 arm64:syscall-abi
11191 12:47:24.832677 arm64:tpidr2
11192 12:47:24.835787 ===========End Tests to run ===============
11193 12:47:24.835894 shardfile-arm64 pass
11194 12:47:25.024457 <12>[ 35.727089] kselftest: Running tests in arm64
11195 12:47:25.035576 TAP version 13
11196 12:47:25.046444 1..48
11197 12:47:25.060994 # selftests: arm64: tags_test
11198 12:47:25.481382 ok 1 selftests: arm64: tags_test
11199 12:47:25.495695 # selftests: arm64: run_tags_test.sh
11200 12:47:25.542800 # --------------------
11201 12:47:25.545772 # running tags test
11202 12:47:25.545861 # --------------------
11203 12:47:25.549273 # [PASS]
11204 12:47:25.552595 ok 2 selftests: arm64: run_tags_test.sh
11205 12:47:25.564387 # selftests: arm64: fake_sigreturn_bad_magic
11206 12:47:25.613235 # Registered handlers for all signals.
11207 12:47:25.613372 # Detected MINSTKSIGSZ:4720
11208 12:47:25.616175 # Testcase initialized.
11209 12:47:25.619981 # uc context validated.
11210 12:47:25.623093 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11211 12:47:25.626388 # Handled SIG_COPYCTX
11212 12:47:25.626493 # Available space:3568
11213 12:47:25.632703 # Using badly built context - ERR: BAD MAGIC !
11214 12:47:25.639839 # SIG_OK -- SP:0xFFFFFF243AC0 si_addr@:0xffffff243ac0 si_code:2 token@:0xffffff242860 offset:-4704
11215 12:47:25.642965 # ==>> completed. PASS(1)
11216 12:47:25.649761 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11217 12:47:25.656014 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFF242860
11218 12:47:25.659729 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11219 12:47:25.665872 # selftests: arm64: fake_sigreturn_bad_size
11220 12:47:25.677761 # Registered handlers for all signals.
11221 12:47:25.677872 # Detected MINSTKSIGSZ:4720
11222 12:47:25.681541 # Testcase initialized.
11223 12:47:25.684673 # uc context validated.
11224 12:47:25.687791 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11225 12:47:25.691508 # Handled SIG_COPYCTX
11226 12:47:25.691625 # Available space:3568
11227 12:47:25.694445 # uc context validated.
11228 12:47:25.700905 # Using badly built context - ERR: Bad size for esr_context
11229 12:47:25.708165 # SIG_OK -- SP:0xFFFFDB9F00B0 si_addr@:0xffffdb9f00b0 si_code:2 token@:0xffffdb9eee50 offset:-4704
11230 12:47:25.711318 # ==>> completed. PASS(1)
11231 12:47:25.717711 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11232 12:47:25.724514 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDB9EEE50
11233 12:47:25.727741 ok 4 selftests: arm64: fake_sigreturn_bad_size
11234 12:47:25.734212 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11235 12:47:25.743823 # Registered handlers for all signals.
11236 12:47:25.743935 # Detected MINSTKSIGSZ:4720
11237 12:47:25.747242 # Testcase initialized.
11238 12:47:25.750650 # uc context validated.
11239 12:47:25.753925 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11240 12:47:25.757361 # Handled SIG_COPYCTX
11241 12:47:25.757470 # Available space:3568
11242 12:47:25.764142 # Using badly built context - ERR: Bad size for terminator
11243 12:47:25.773951 # SIG_OK -- SP:0xFFFFF9CD3CA0 si_addr@:0xfffff9cd3ca0 si_code:2 token@:0xfffff9cd2a40 offset:-4704
11244 12:47:25.774066 # ==>> completed. PASS(1)
11245 12:47:25.783873 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11246 12:47:25.790112 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF9CD2A40
11247 12:47:25.793872 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11248 12:47:25.799969 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11249 12:47:25.816207 # Registered handlers for all signals.
11250 12:47:25.816358 # Detected MINSTKSIGSZ:4720
11251 12:47:25.819664 # Testcase initialized.
11252 12:47:25.822812 # uc context validated.
11253 12:47:25.826075 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11254 12:47:25.829150 # Handled SIG_COPYCTX
11255 12:47:25.829257 # Available space:3568
11256 12:47:25.835916 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11257 12:47:25.845921 # SIG_OK -- SP:0xFFFFC5A085F0 si_addr@:0xffffc5a085f0 si_code:2 token@:0xffffc5a07390 offset:-4704
11258 12:47:25.846031 # ==>> completed. PASS(1)
11259 12:47:25.856338 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11260 12:47:25.862421 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC5A07390
11261 12:47:25.865734 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11262 12:47:25.869001 # selftests: arm64: fake_sigreturn_misaligned_sp
11263 12:47:25.888243 # Registered handlers for all signals.
11264 12:47:25.888401 # Detected MINSTKSIGSZ:4720
11265 12:47:25.891566 # Testcase initialized.
11266 12:47:25.894839 # uc context validated.
11267 12:47:25.897940 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11268 12:47:25.901674 # Handled SIG_COPYCTX
11269 12:47:25.908045 # SIG_OK -- SP:0xFFFFE81CA653 si_addr@:0xffffe81ca653 si_code:2 token@:0xffffe81ca653 offset:0
11270 12:47:25.911537 # ==>> completed. PASS(1)
11271 12:47:25.918374 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11272 12:47:25.924627 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE81CA653
11273 12:47:25.931152 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11274 12:47:25.934495 # selftests: arm64: fake_sigreturn_missing_fpsimd
11275 12:47:25.959462 # Registered handlers for all signals.
11276 12:47:25.959610 # Detected MINSTKSIGSZ:4720
11277 12:47:25.962657 # Testcase initialized.
11278 12:47:25.965841 # uc context validated.
11279 12:47:25.969493 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11280 12:47:25.972792 # Handled SIG_COPYCTX
11281 12:47:25.976223 # Mangling template header. Spare space:4096
11282 12:47:25.979514 # Using badly built context - ERR: Missing FPSIMD
11283 12:47:25.989118 # SIG_OK -- SP:0xFFFFDB9DA800 si_addr@:0xffffdb9da800 si_code:2 token@:0xffffdb9d95a0 offset:-4704
11284 12:47:25.992579 # ==>> completed. PASS(1)
11285 12:47:25.999016 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11286 12:47:26.005601 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDB9D95A0
11287 12:47:26.008966 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11288 12:47:26.015542 # selftests: arm64: fake_sigreturn_sme_change_vl
11289 12:47:26.032423 # Registered handlers for all signals.
11290 12:47:26.032544 # Detected MINSTKSIGSZ:4720
11291 12:47:26.035581 # ==>> completed. SKIP.
11292 12:47:26.042080 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11293 12:47:26.045888 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11294 12:47:26.052271 # selftests: arm64: fake_sigreturn_sve_change_vl
11295 12:47:26.103114 # Registered handlers for all signals.
11296 12:47:26.103261 # Detected MINSTKSIGSZ:4720
11297 12:47:26.106628 # ==>> completed. SKIP.
11298 12:47:26.113364 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11299 12:47:26.116914 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11300 12:47:26.122994 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11301 12:47:26.177124 # Registered handlers for all signals.
11302 12:47:26.177275 # Detected MINSTKSIGSZ:4720
11303 12:47:26.181017 # Testcase initialized.
11304 12:47:26.184239 # uc context validated.
11305 12:47:26.184384 # Handled SIG_TRIG
11306 12:47:26.194267 # SIG_OK -- SP:0xFFFFE0C8D870 si_addr@:0xffffe0c8d870 si_code:2 token@:(nil) offset:-281474453002352
11307 12:47:26.197334 # ==>> completed. PASS(1)
11308 12:47:26.204282 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11309 12:47:26.210222 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11310 12:47:26.213927 # selftests: arm64: mangle_pstate_invalid_daif_bits
11311 12:47:26.255391 # Registered handlers for all signals.
11312 12:47:26.255533 # Detected MINSTKSIGSZ:4720
11313 12:47:26.258462 # Testcase initialized.
11314 12:47:26.261547 # uc context validated.
11315 12:47:26.261653 # Handled SIG_TRIG
11316 12:47:26.271514 # SIG_OK -- SP:0xFFFFF777EAB0 si_addr@:0xfffff777eab0 si_code:2 token@:(nil) offset:-281474833574576
11317 12:47:26.274743 # ==>> completed. PASS(1)
11318 12:47:26.281320 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11319 12:47:26.284993 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11320 12:47:26.291561 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11321 12:47:26.322458 # Registered handlers for all signals.
11322 12:47:26.322620 # Detected MINSTKSIGSZ:4720
11323 12:47:26.325643 # Testcase initialized.
11324 12:47:26.329334 # uc context validated.
11325 12:47:26.329440 # Handled SIG_TRIG
11326 12:47:26.339320 # SIG_OK -- SP:0xFFFFD9BE06D0 si_addr@:0xffffd9be06d0 si_code:2 token@:(nil) offset:-281474334852816
11327 12:47:26.342419 # ==>> completed. PASS(1)
11328 12:47:26.349232 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11329 12:47:26.352232 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11330 12:47:26.359341 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11331 12:47:26.393074 # Registered handlers for all signals.
11332 12:47:26.393248 # Detected MINSTKSIGSZ:4720
11333 12:47:26.396804 # Testcase initialized.
11334 12:47:26.400018 # uc context validated.
11335 12:47:26.400125 # Handled SIG_TRIG
11336 12:47:26.410090 # SIG_OK -- SP:0xFFFFF205D560 si_addr@:0xfffff205d560 si_code:2 token@:(nil) offset:-281474742211936
11337 12:47:26.413233 # ==>> completed. PASS(1)
11338 12:47:26.420127 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11339 12:47:26.423007 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11340 12:47:26.429917 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11341 12:47:26.483959 # Registered handlers for all signals.
11342 12:47:26.484142 # Detected MINSTKSIGSZ:4720
11343 12:47:26.487228 # Testcase initialized.
11344 12:47:26.491068 # uc context validated.
11345 12:47:26.491176 # Handled SIG_TRIG
11346 12:47:26.500450 # SIG_OK -- SP:0xFFFFEB73E4F0 si_addr@:0xffffeb73e4f0 si_code:2 token@:(nil) offset:-281474631984368
11347 12:47:26.504059 # ==>> completed. PASS(1)
11348 12:47:26.510893 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11349 12:47:26.513844 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11350 12:47:26.520504 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11351 12:47:26.557353 # Registered handlers for all signals.
11352 12:47:26.557523 # Detected MINSTKSIGSZ:4720
11353 12:47:26.560821 # Testcase initialized.
11354 12:47:26.564055 # uc context validated.
11355 12:47:26.564160 # Handled SIG_TRIG
11356 12:47:26.573868 # SIG_OK -- SP:0xFFFFFE8CDE30 si_addr@:0xfffffe8cde30 si_code:2 token@:(nil) offset:-281474952388144
11357 12:47:26.577139 # ==>> completed. PASS(1)
11358 12:47:26.583758 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11359 12:47:26.587439 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11360 12:47:26.593740 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11361 12:47:26.635532 # Registered handlers for all signals.
11362 12:47:26.635710 # Detected MINSTKSIGSZ:4720
11363 12:47:26.638805 # Testcase initialized.
11364 12:47:26.642049 # uc context validated.
11365 12:47:26.642158 # Handled SIG_TRIG
11366 12:47:26.651734 # SIG_OK -- SP:0xFFFFCC7C6580 si_addr@:0xffffcc7c6580 si_code:2 token@:(nil) offset:-281474112447872
11367 12:47:26.655043 # ==>> completed. PASS(1)
11368 12:47:26.661901 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11369 12:47:26.665112 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11370 12:47:26.671823 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11371 12:47:26.705255 # Registered handlers for all signals.
11372 12:47:26.705415 # Detected MINSTKSIGSZ:4720
11373 12:47:26.708686 # Testcase initialized.
11374 12:47:26.711850 # uc context validated.
11375 12:47:26.711957 # Handled SIG_TRIG
11376 12:47:26.721974 # SIG_OK -- SP:0xFFFFCF6CB1D0 si_addr@:0xffffcf6cb1d0 si_code:2 token@:(nil) offset:-281474161750480
11377 12:47:26.725185 # ==>> completed. PASS(1)
11378 12:47:26.732058 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11379 12:47:26.735089 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11380 12:47:26.738603 # selftests: arm64: sme_trap_no_sm
11381 12:47:26.785327 # Registered handlers for all signals.
11382 12:47:26.785513 # Detected MINSTKSIGSZ:4720
11383 12:47:26.788965 # ==>> completed. SKIP.
11384 12:47:26.798630 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11385 12:47:26.802169 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11386 12:47:26.805401 # selftests: arm64: sme_trap_non_streaming
11387 12:47:26.865859 # Registered handlers for all signals.
11388 12:47:26.866048 # Detected MINSTKSIGSZ:4720
11389 12:47:26.868744 # ==>> completed. SKIP.
11390 12:47:26.879171 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11391 12:47:26.885328 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11392 12:47:26.888817 # selftests: arm64: sme_trap_za
11393 12:47:26.939038 # Registered handlers for all signals.
11394 12:47:26.939219 # Detected MINSTKSIGSZ:4720
11395 12:47:26.941868 # Testcase initialized.
11396 12:47:26.951704 # SIG_OK -- SP:0xFFFFC4299ED0 si_addr@:0xaaaac1562510 si_code:1 token@:(nil) offset:-187650364810512
11397 12:47:26.951820 # ==>> completed. PASS(1)
11398 12:47:26.961398 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11399 12:47:26.964897 ok 21 selftests: arm64: sme_trap_za
11400 12:47:26.965005 # selftests: arm64: sme_vl
11401 12:47:26.994578 # Registered handlers for all signals.
11402 12:47:26.994727 # Detected MINSTKSIGSZ:4720
11403 12:47:26.997399 # ==>> completed. SKIP.
11404 12:47:27.001096 # # SME VL :: Check that we get the right SME VL reported
11405 12:47:27.004174 ok 22 selftests: arm64: sme_vl # SKIP
11406 12:47:27.009895 # selftests: arm64: ssve_regs
11407 12:47:27.083647 # Registered handlers for all signals.
11408 12:47:27.083831 # Detected MINSTKSIGSZ:4720
11409 12:47:27.086752 # ==>> completed. SKIP.
11410 12:47:27.093349 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11411 12:47:27.096729 ok 23 selftests: arm64: ssve_regs # SKIP
11412 12:47:27.102923 # selftests: arm64: sve_regs
11413 12:47:27.171148 # Registered handlers for all signals.
11414 12:47:27.171331 # Detected MINSTKSIGSZ:4720
11415 12:47:27.174210 # ==>> completed. SKIP.
11416 12:47:27.180593 # # SVE registers :: Check that we get the right SVE registers reported
11417 12:47:27.184193 ok 24 selftests: arm64: sve_regs # SKIP
11418 12:47:27.187363 # selftests: arm64: sve_vl
11419 12:47:27.248605 # Registered handlers for all signals.
11420 12:47:27.248742 # Detected MINSTKSIGSZ:4720
11421 12:47:27.252143 # ==>> completed. SKIP.
11422 12:47:27.255453 # # SVE VL :: Check that we get the right SVE VL reported
11423 12:47:27.258513 ok 25 selftests: arm64: sve_vl # SKIP
11424 12:47:27.266190 # selftests: arm64: za_no_regs
11425 12:47:27.326020 # Registered handlers for all signals.
11426 12:47:27.326186 # Detected MINSTKSIGSZ:4720
11427 12:47:27.329332 # ==>> completed. SKIP.
11428 12:47:27.335837 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11429 12:47:27.339464 ok 26 selftests: arm64: za_no_regs # SKIP
11430 12:47:27.342308 # selftests: arm64: za_regs
11431 12:47:27.390096 # Registered handlers for all signals.
11432 12:47:27.390274 # Detected MINSTKSIGSZ:4720
11433 12:47:27.393150 # ==>> completed. SKIP.
11434 12:47:27.399696 # # ZA register :: Check that we get the right ZA registers reported
11435 12:47:27.402973 ok 27 selftests: arm64: za_regs # SKIP
11436 12:47:27.407361 # selftests: arm64: pac
11437 12:47:27.452639 # TAP version 13
11438 12:47:27.452741 # 1..7
11439 12:47:27.456030 # # Starting 7 tests from 1 test cases.
11440 12:47:27.458914 # # RUN global.corrupt_pac ...
11441 12:47:27.462339 # # SKIP PAUTH not enabled
11442 12:47:27.466176 # # OK global.corrupt_pac
11443 12:47:27.469341 # ok 1 # SKIP PAUTH not enabled
11444 12:47:27.475619 # # RUN global.pac_instructions_not_nop ...
11445 12:47:27.479289 # # SKIP PAUTH not enabled
11446 12:47:27.482428 # # OK global.pac_instructions_not_nop
11447 12:47:27.485674 # ok 2 # SKIP PAUTH not enabled
11448 12:47:27.492083 # # RUN global.pac_instructions_not_nop_generic ...
11449 12:47:27.495743 # # SKIP Generic PAUTH not enabled
11450 12:47:27.498824 # # OK global.pac_instructions_not_nop_generic
11451 12:47:27.502051 # ok 3 # SKIP Generic PAUTH not enabled
11452 12:47:27.508823 # # RUN global.single_thread_different_keys ...
11453 12:47:27.511806 # # SKIP PAUTH not enabled
11454 12:47:27.518630 # # OK global.single_thread_different_keys
11455 12:47:27.518709 # ok 4 # SKIP PAUTH not enabled
11456 12:47:27.525794 # # RUN global.exec_changed_keys ...
11457 12:47:27.528528 # # SKIP PAUTH not enabled
11458 12:47:27.531751 # # OK global.exec_changed_keys
11459 12:47:27.535177 # ok 5 # SKIP PAUTH not enabled
11460 12:47:27.538565 # # RUN global.context_switch_keep_keys ...
11461 12:47:27.541872 # # SKIP PAUTH not enabled
11462 12:47:27.545230 # # OK global.context_switch_keep_keys
11463 12:47:27.548893 # ok 6 # SKIP PAUTH not enabled
11464 12:47:27.555277 # # RUN global.context_switch_keep_keys_generic ...
11465 12:47:27.558441 # # SKIP Generic PAUTH not enabled
11466 12:47:27.565444 # # OK global.context_switch_keep_keys_generic
11467 12:47:27.568694 # ok 7 # SKIP Generic PAUTH not enabled
11468 12:47:27.571974 # # PASSED: 7 / 7 tests passed.
11469 12:47:27.575095 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11470 12:47:27.578678 ok 28 selftests: arm64: pac
11471 12:47:27.581727 # selftests: arm64: fp-stress
11472 12:47:35.519259 <6>[ 46.225714] vpu: disabling
11473 12:47:35.522463 <6>[ 46.228764] vproc2: disabling
11474 12:47:35.525509 <6>[ 46.232360] vproc1: disabling
11475 12:47:35.529339 <6>[ 46.236082] vaud18: disabling
11476 12:47:35.536482 <6>[ 46.239588] vsram_others: disabling
11477 12:47:35.539302 <6>[ 46.243581] va09: disabling
11478 12:47:35.542792 <6>[ 46.246777] vsram_md: disabling
11479 12:47:35.546464 <6>[ 46.250366] Vgpu: disabling
11480 12:47:37.529516 # TAP version 13
11481 12:47:37.530077 # 1..16
11482 12:47:37.532090 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11483 12:47:37.536792 # # Will run for 10s
11484 12:47:37.537263 # # Started FPSIMD-0-0
11485 12:47:37.539349 # # Started FPSIMD-0-1
11486 12:47:37.542442 # # Started FPSIMD-1-0
11487 12:47:37.543078 # # Started FPSIMD-1-1
11488 12:47:37.545562 # # Started FPSIMD-2-0
11489 12:47:37.546092 # # Started FPSIMD-2-1
11490 12:47:37.548929 # # Started FPSIMD-3-0
11491 12:47:37.552633 # # Started FPSIMD-3-1
11492 12:47:37.553046 # # Started FPSIMD-4-0
11493 12:47:37.555524 # # Started FPSIMD-4-1
11494 12:47:37.558966 # # Started FPSIMD-5-0
11495 12:47:37.559525 # # Started FPSIMD-5-1
11496 12:47:37.562550 # # Started FPSIMD-6-0
11497 12:47:37.565552 # # Started FPSIMD-6-1
11498 12:47:37.566060 # # Started FPSIMD-7-0
11499 12:47:37.568886 # # Started FPSIMD-7-1
11500 12:47:37.572725 # # FPSIMD-1-1: Vector length: 128 bits
11501 12:47:37.575361 # # FPSIMD-1-1: PID: 1155
11502 12:47:37.578862 # # FPSIMD-2-1: Vector length: 128 bits
11503 12:47:37.579386 # # FPSIMD-2-1: PID: 1157
11504 12:47:37.582070 # # FPSIMD-0-0: Vector length: 128 bits
11505 12:47:37.585473 # # FPSIMD-0-0: PID: 1152
11506 12:47:37.588806 # # FPSIMD-0-1: Vector length: 128 bits
11507 12:47:37.592124 # # FPSIMD-0-1: PID: 1153
11508 12:47:37.595820 # # FPSIMD-2-0: Vector length: 128 bits
11509 12:47:37.598870 # # FPSIMD-2-0: PID: 1156
11510 12:47:37.601936 # # FPSIMD-3-1: Vector length: 128 bits
11511 12:47:37.602496 # # FPSIMD-3-1: PID: 1159
11512 12:47:37.608816 # # FPSIMD-5-0: Vector length: 128 bits
11513 12:47:37.609252 # # FPSIMD-5-0: PID: 1162
11514 12:47:37.612371 # # FPSIMD-4-1: Vector length: 128 bits
11515 12:47:37.615278 # # FPSIMD-1-0: Vector length: 128 bits
11516 12:47:37.618648 # # FPSIMD-1-0: PID: 1154
11517 12:47:37.621877 # # FPSIMD-4-1: PID: 1161
11518 12:47:37.625137 # # FPSIMD-3-0: Vector length: 128 bits
11519 12:47:37.628282 # # FPSIMD-3-0: PID: 1158
11520 12:47:37.631479 # # FPSIMD-7-0: Vector length: 128 bits
11521 12:47:37.631924 # # FPSIMD-7-0: PID: 1166
11522 12:47:37.635211 # # FPSIMD-7-1: Vector length: 128 bits
11523 12:47:37.638643 # # FPSIMD-7-1: PID: 1167
11524 12:47:37.641946 # # FPSIMD-5-1: Vector length: 128 bits
11525 12:47:37.644904 # # FPSIMD-5-1: PID: 1163
11526 12:47:37.648256 # # FPSIMD-6-0: Vector length: 128 bits
11527 12:47:37.651501 # # FPSIMD-6-0: PID: 1164
11528 12:47:37.654740 # # FPSIMD-6-1: Vector length: 128 bits
11529 12:47:37.658508 # # FPSIMD-6-1: PID: 1165
11530 12:47:37.661683 # # FPSIMD-4-0: Vector length: 128 bits
11531 12:47:37.662314 # # FPSIMD-4-0: PID: 1160
11532 12:47:37.665286 # # Finishing up...
11533 12:47:37.671656 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=1030319, signals=10
11534 12:47:37.678092 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=993503, signals=10
11535 12:47:37.684861 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=1022427, signals=10
11536 12:47:37.694958 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=1091915, signals=10
11537 12:47:37.701418 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=1484561, signals=10
11538 12:47:37.708000 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1577073, signals=10
11539 12:47:37.714360 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=1760304, signals=10
11540 12:47:37.717789 # ok 1 FPSIMD-0-0
11541 12:47:37.718210 # ok 2 FPSIMD-0-1
11542 12:47:37.721325 # ok 3 FPSIMD-1-0
11543 12:47:37.721738 # ok 4 FPSIMD-1-1
11544 12:47:37.724347 # ok 5 FPSIMD-2-0
11545 12:47:37.724865 # ok 6 FPSIMD-2-1
11546 12:47:37.727729 # ok 7 FPSIMD-3-0
11547 12:47:37.728272 # ok 8 FPSIMD-3-1
11548 12:47:37.731350 # ok 9 FPSIMD-4-0
11549 12:47:37.731755 # ok 10 FPSIMD-4-1
11550 12:47:37.734847 # ok 11 FPSIMD-5-0
11551 12:47:37.735256 # ok 12 FPSIMD-5-1
11552 12:47:37.737790 # ok 13 FPSIMD-6-0
11553 12:47:37.738199 # ok 14 FPSIMD-6-1
11554 12:47:37.741445 # ok 15 FPSIMD-7-0
11555 12:47:37.741880 # ok 16 FPSIMD-7-1
11556 12:47:37.748177 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=1351061, signals=9
11557 12:47:37.754659 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=982973, signals=10
11558 12:47:37.764478 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=1708317, signals=10
11559 12:47:37.770961 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=1542929, signals=10
11560 12:47:37.777583 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=1989083, signals=10
11561 12:47:37.784619 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=986391, signals=9
11562 12:47:37.791040 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=962934, signals=10
11563 12:47:37.797635 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=995524, signals=10
11564 12:47:37.804545 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=977773, signals=9
11565 12:47:37.810746 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11566 12:47:37.814127 ok 29 selftests: arm64: fp-stress
11567 12:47:37.817389 # selftests: arm64: sve-ptrace
11568 12:47:37.817796 # TAP version 13
11569 12:47:37.820967 # 1..4104
11570 12:47:37.821361 # ok 2 # SKIP SVE not available
11571 12:47:37.827555 # # Planned tests != run tests (4104 != 1)
11572 12:47:37.830484 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11573 12:47:37.834250 ok 30 selftests: arm64: sve-ptrace # SKIP
11574 12:47:37.837090 # selftests: arm64: sve-probe-vls
11575 12:47:37.840674 # TAP version 13
11576 12:47:37.841104 # 1..2
11577 12:47:37.843775 # ok 2 # SKIP SVE not available
11578 12:47:37.847170 # # Planned tests != run tests (2 != 1)
11579 12:47:37.850403 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11580 12:47:37.857275 ok 31 selftests: arm64: sve-probe-vls # SKIP
11581 12:47:37.857896 # selftests: arm64: vec-syscfg
11582 12:47:37.860354 # TAP version 13
11583 12:47:37.860791 # 1..20
11584 12:47:37.863267 # ok 1 # SKIP SVE not supported
11585 12:47:37.866979 # ok 2 # SKIP SVE not supported
11586 12:47:37.870228 # ok 3 # SKIP SVE not supported
11587 12:47:37.874006 # ok 4 # SKIP SVE not supported
11588 12:47:37.874445 # ok 5 # SKIP SVE not supported
11589 12:47:37.876750 # ok 6 # SKIP SVE not supported
11590 12:47:37.880562 # ok 7 # SKIP SVE not supported
11591 12:47:37.883877 # ok 8 # SKIP SVE not supported
11592 12:47:37.886847 # ok 9 # SKIP SVE not supported
11593 12:47:37.890034 # ok 10 # SKIP SVE not supported
11594 12:47:37.893726 # ok 11 # SKIP SME not supported
11595 12:47:37.894162 # ok 12 # SKIP SME not supported
11596 12:47:37.896885 # ok 13 # SKIP SME not supported
11597 12:47:37.900137 # ok 14 # SKIP SME not supported
11598 12:47:37.903585 # ok 15 # SKIP SME not supported
11599 12:47:37.906788 # ok 16 # SKIP SME not supported
11600 12:47:37.909965 # ok 17 # SKIP SME not supported
11601 12:47:37.913526 # ok 18 # SKIP SME not supported
11602 12:47:37.916987 # ok 19 # SKIP SME not supported
11603 12:47:37.920352 # ok 20 # SKIP SME not supported
11604 12:47:37.923358 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11605 12:47:37.926927 ok 32 selftests: arm64: vec-syscfg
11606 12:47:37.929596 # selftests: arm64: za-fork
11607 12:47:37.930156 # TAP version 13
11608 12:47:37.933321 # 1..1
11609 12:47:37.933732 # # PID: 1242
11610 12:47:37.936425 # # SME support not present
11611 12:47:37.936833 # ok 0 skipped
11612 12:47:37.943492 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11613 12:47:37.946459 ok 33 selftests: arm64: za-fork
11614 12:47:37.947051 # selftests: arm64: za-ptrace
11615 12:47:37.949798 # TAP version 13
11616 12:47:37.950190 # 1..1
11617 12:47:37.952903 # ok 2 # SKIP SME not available
11618 12:47:37.956359 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11619 12:47:37.959522 ok 34 selftests: arm64: za-ptrace # SKIP
11620 12:47:37.966101 # selftests: arm64: check_buffer_fill
11621 12:47:38.018875 # # SKIP: MTE features unavailable
11622 12:47:38.026270 ok 35 selftests: arm64: check_buffer_fill # SKIP
11623 12:47:38.040470 # selftests: arm64: check_child_memory
11624 12:47:38.092154 # # SKIP: MTE features unavailable
11625 12:47:38.098791 ok 36 selftests: arm64: check_child_memory # SKIP
11626 12:47:38.113828 # selftests: arm64: check_gcr_el1_cswitch
11627 12:47:38.145635 # # SKIP: MTE features unavailable
11628 12:47:38.152512 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11629 12:47:38.166919 # selftests: arm64: check_ksm_options
11630 12:47:38.224397 # # SKIP: MTE features unavailable
11631 12:47:38.231984 ok 38 selftests: arm64: check_ksm_options # SKIP
11632 12:47:38.247484 # selftests: arm64: check_mmap_options
11633 12:47:38.305596 # # SKIP: MTE features unavailable
11634 12:47:38.312772 ok 39 selftests: arm64: check_mmap_options # SKIP
11635 12:47:38.324740 # selftests: arm64: check_prctl
11636 12:47:38.381544 # TAP version 13
11637 12:47:38.381669 # 1..5
11638 12:47:38.384772 # ok 1 check_basic_read
11639 12:47:38.384851 # ok 2 NONE
11640 12:47:38.388319 # ok 3 # SKIP SYNC
11641 12:47:38.388429 # ok 4 # SKIP ASYNC
11642 12:47:38.391436 # ok 5 # SKIP SYNC+ASYNC
11643 12:47:38.394819 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11644 12:47:38.398385 ok 40 selftests: arm64: check_prctl
11645 12:47:38.404769 # selftests: arm64: check_tags_inclusion
11646 12:47:38.453066 # # SKIP: MTE features unavailable
11647 12:47:38.460864 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11648 12:47:38.472540 # selftests: arm64: check_user_mem
11649 12:47:38.526340 # # SKIP: MTE features unavailable
11650 12:47:38.533456 ok 42 selftests: arm64: check_user_mem # SKIP
11651 12:47:38.543645 # selftests: arm64: btitest
11652 12:47:38.593331 # TAP version 13
11653 12:47:38.593419 # 1..18
11654 12:47:38.596734 # # HWCAP_PACA not present
11655 12:47:38.600142 # # HWCAP2_BTI not present
11656 12:47:38.600247 # # Test binary built for BTI
11657 12:47:38.606627 # ok 1 nohint_func/call_using_br_x0 # SKIP
11658 12:47:38.609758 # ok 1 nohint_func/call_using_br_x16 # SKIP
11659 12:47:38.613595 # ok 1 nohint_func/call_using_blr # SKIP
11660 12:47:38.616522 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11661 12:47:38.619922 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11662 12:47:38.626697 # ok 1 bti_none_func/call_using_blr # SKIP
11663 12:47:38.629933 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11664 12:47:38.633375 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11665 12:47:38.636793 # ok 1 bti_c_func/call_using_blr # SKIP
11666 12:47:38.639738 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11667 12:47:38.643276 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11668 12:47:38.646615 # ok 1 bti_j_func/call_using_blr # SKIP
11669 12:47:38.649814 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11670 12:47:38.656244 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11671 12:47:38.659862 # ok 1 bti_jc_func/call_using_blr # SKIP
11672 12:47:38.662819 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11673 12:47:38.666043 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11674 12:47:38.669963 # ok 1 paciasp_func/call_using_blr # SKIP
11675 12:47:38.675867 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11676 12:47:38.679168 # # WARNING - EXPECTED TEST COUNT WRONG
11677 12:47:38.682949 ok 43 selftests: arm64: btitest
11678 12:47:38.683049 # selftests: arm64: nobtitest
11679 12:47:38.686023 # TAP version 13
11680 12:47:38.686120 # 1..18
11681 12:47:38.689759 # # HWCAP_PACA not present
11682 12:47:38.692902 # # HWCAP2_BTI not present
11683 12:47:38.696191 # # Test binary not built for BTI
11684 12:47:38.699402 # ok 1 nohint_func/call_using_br_x0 # SKIP
11685 12:47:38.702546 # ok 1 nohint_func/call_using_br_x16 # SKIP
11686 12:47:38.706108 # ok 1 nohint_func/call_using_blr # SKIP
11687 12:47:38.709053 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11688 12:47:38.712415 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11689 12:47:38.719283 # ok 1 bti_none_func/call_using_blr # SKIP
11690 12:47:38.722299 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11691 12:47:38.725756 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11692 12:47:38.729669 # ok 1 bti_c_func/call_using_blr # SKIP
11693 12:47:38.732256 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11694 12:47:38.736111 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11695 12:47:38.739276 # ok 1 bti_j_func/call_using_blr # SKIP
11696 12:47:38.742869 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11697 12:47:38.749225 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11698 12:47:38.752268 # ok 1 bti_jc_func/call_using_blr # SKIP
11699 12:47:38.755722 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11700 12:47:38.758919 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11701 12:47:38.762499 # ok 1 paciasp_func/call_using_blr # SKIP
11702 12:47:38.769387 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11703 12:47:38.772220 # # WARNING - EXPECTED TEST COUNT WRONG
11704 12:47:38.775804 ok 44 selftests: arm64: nobtitest
11705 12:47:38.775907 # selftests: arm64: hwcap
11706 12:47:38.779033 # TAP version 13
11707 12:47:38.779131 # 1..28
11708 12:47:38.782304 # ok 1 cpuinfo_match_RNG
11709 12:47:38.785606 # # SIGILL reported for RNG
11710 12:47:38.785678 # ok 2 # SKIP sigill_RNG
11711 12:47:38.788736 # ok 3 cpuinfo_match_SME
11712 12:47:38.788809 # ok 4 sigill_SME
11713 12:47:38.792479 # ok 5 cpuinfo_match_SVE
11714 12:47:38.795758 # ok 6 sigill_SVE
11715 12:47:38.795826 # ok 7 cpuinfo_match_SVE 2
11716 12:47:38.799102 # # SIGILL reported for SVE 2
11717 12:47:38.802363 # ok 8 # SKIP sigill_SVE 2
11718 12:47:38.805714 # ok 9 cpuinfo_match_SVE AES
11719 12:47:38.808860 # # SIGILL reported for SVE AES
11720 12:47:38.808939 # ok 10 # SKIP sigill_SVE AES
11721 12:47:38.811931 # ok 11 cpuinfo_match_SVE2 PMULL
11722 12:47:38.815799 # # SIGILL reported for SVE2 PMULL
11723 12:47:38.819017 # ok 12 # SKIP sigill_SVE2 PMULL
11724 12:47:38.821841 # ok 13 cpuinfo_match_SVE2 BITPERM
11725 12:47:38.825691 # # SIGILL reported for SVE2 BITPERM
11726 12:47:38.828390 # ok 14 # SKIP sigill_SVE2 BITPERM
11727 12:47:38.831803 # ok 15 cpuinfo_match_SVE2 SHA3
11728 12:47:38.835055 # # SIGILL reported for SVE2 SHA3
11729 12:47:38.838584 # ok 16 # SKIP sigill_SVE2 SHA3
11730 12:47:38.838658 # ok 17 cpuinfo_match_SVE2 SM4
11731 12:47:38.841841 # # SIGILL reported for SVE2 SM4
11732 12:47:38.845119 # ok 18 # SKIP sigill_SVE2 SM4
11733 12:47:38.848667 # ok 19 cpuinfo_match_SVE2 I8MM
11734 12:47:38.851711 # # SIGILL reported for SVE2 I8MM
11735 12:47:38.855012 # ok 20 # SKIP sigill_SVE2 I8MM
11736 12:47:38.858827 # ok 21 cpuinfo_match_SVE2 F32MM
11737 12:47:38.861755 # # SIGILL reported for SVE2 F32MM
11738 12:47:38.864802 # ok 22 # SKIP sigill_SVE2 F32MM
11739 12:47:38.864898 # ok 23 cpuinfo_match_SVE2 F64MM
11740 12:47:38.868526 # # SIGILL reported for SVE2 F64MM
11741 12:47:38.871764 # ok 24 # SKIP sigill_SVE2 F64MM
11742 12:47:38.874972 # ok 25 cpuinfo_match_SVE2 BF16
11743 12:47:38.878062 # # SIGILL reported for SVE2 BF16
11744 12:47:38.881841 # ok 26 # SKIP sigill_SVE2 BF16
11745 12:47:38.884659 # ok 27 cpuinfo_match_SVE2 EBF16
11746 12:47:38.888065 # ok 28 # SKIP sigill_SVE2 EBF16
11747 12:47:38.891409 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11748 12:47:38.894818 ok 45 selftests: arm64: hwcap
11749 12:47:38.898285 # selftests: arm64: ptrace
11750 12:47:38.898358 # TAP version 13
11751 12:47:38.901342 # 1..7
11752 12:47:38.904771 # # Parent is 1484, child is 1485
11753 12:47:38.904873 # ok 1 read_tpidr_one
11754 12:47:38.907889 # ok 2 write_tpidr_one
11755 12:47:38.907991 # ok 3 verify_tpidr_one
11756 12:47:38.911144 # ok 4 count_tpidrs
11757 12:47:38.911240 # ok 5 tpidr2_write
11758 12:47:38.914304 # ok 6 tpidr2_read
11759 12:47:38.918015 # ok 7 write_tpidr_only
11760 12:47:38.921305 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11761 12:47:38.924869 ok 46 selftests: arm64: ptrace
11762 12:47:38.927770 # selftests: arm64: syscall-abi
11763 12:47:38.927864 # TAP version 13
11764 12:47:38.931066 # 1..2
11765 12:47:38.931162 # ok 1 getpid() FPSIMD
11766 12:47:38.934764 # ok 2 sched_yield() FPSIMD
11767 12:47:38.937991 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11768 12:47:38.941419 ok 47 selftests: arm64: syscall-abi
11769 12:47:38.944483 # selftests: arm64: tpidr2
11770 12:47:38.966324 # TAP version 13
11771 12:47:38.966427 # 1..5
11772 12:47:38.969714 # # PID: 1521
11773 12:47:38.969787 # # SME support not present
11774 12:47:38.973262 # ok 0 skipped, TPIDR2 not supported
11775 12:47:38.976303 # ok 1 skipped, TPIDR2 not supported
11776 12:47:38.979630 # ok 2 skipped, TPIDR2 not supported
11777 12:47:38.983014 # ok 3 skipped, TPIDR2 not supported
11778 12:47:38.986079 # ok 4 skipped, TPIDR2 not supported
11779 12:47:38.992512 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11780 12:47:38.996366 ok 48 selftests: arm64: tpidr2
11781 12:47:39.596174 arm64_tags_test pass
11782 12:47:39.599390 arm64_run_tags_test_sh pass
11783 12:47:39.602675 arm64_fake_sigreturn_bad_magic pass
11784 12:47:39.605781 arm64_fake_sigreturn_bad_size pass
11785 12:47:39.609004 arm64_fake_sigreturn_bad_size_for_magic0 pass
11786 12:47:39.612726 arm64_fake_sigreturn_duplicated_fpsimd pass
11787 12:47:39.616002 arm64_fake_sigreturn_misaligned_sp pass
11788 12:47:39.619165 arm64_fake_sigreturn_missing_fpsimd pass
11789 12:47:39.622495 arm64_fake_sigreturn_sme_change_vl skip
11790 12:47:39.625571 arm64_fake_sigreturn_sve_change_vl skip
11791 12:47:39.632198 arm64_mangle_pstate_invalid_compat_toggle pass
11792 12:47:39.635849 arm64_mangle_pstate_invalid_daif_bits pass
11793 12:47:39.638804 arm64_mangle_pstate_invalid_mode_el1h pass
11794 12:47:39.642465 arm64_mangle_pstate_invalid_mode_el1t pass
11795 12:47:39.645811 arm64_mangle_pstate_invalid_mode_el2h pass
11796 12:47:39.651981 arm64_mangle_pstate_invalid_mode_el2t pass
11797 12:47:39.655548 arm64_mangle_pstate_invalid_mode_el3h pass
11798 12:47:39.658988 arm64_mangle_pstate_invalid_mode_el3t pass
11799 12:47:39.659081 arm64_sme_trap_no_sm skip
11800 12:47:39.662135 arm64_sme_trap_non_streaming skip
11801 12:47:39.665682 arm64_sme_trap_za pass
11802 12:47:39.668734 arm64_sme_vl skip
11803 12:47:39.668830 arm64_ssve_regs skip
11804 12:47:39.671966 arm64_sve_regs skip
11805 12:47:39.672061 arm64_sve_vl skip
11806 12:47:39.675438 arm64_za_no_regs skip
11807 12:47:39.675534 arm64_za_regs skip
11808 12:47:39.678960 arm64_pac_pauth_not_enabled skip
11809 12:47:39.682321 arm64_pac_pauth_not_enabled skip
11810 12:47:39.685336 arm64_pac_generic_pauth_not_enabled skip
11811 12:47:39.689127 arm64_pac_pauth_not_enabled skip
11812 12:47:39.692149 arm64_pac_pauth_not_enabled skip
11813 12:47:39.695372 arm64_pac_pauth_not_enabled skip
11814 12:47:39.698517 arm64_pac_generic_pauth_not_enabled skip
11815 12:47:39.698588 arm64_pac pass
11816 12:47:39.702333 arm64_fp-stress_FPSIMD-0-0 pass
11817 12:47:39.705561 arm64_fp-stress_FPSIMD-0-1 pass
11818 12:47:39.708709 arm64_fp-stress_FPSIMD-1-0 pass
11819 12:47:39.711949 arm64_fp-stress_FPSIMD-1-1 pass
11820 12:47:39.715016 arm64_fp-stress_FPSIMD-2-0 pass
11821 12:47:39.718220 arm64_fp-stress_FPSIMD-2-1 pass
11822 12:47:39.718320 arm64_fp-stress_FPSIMD-3-0 pass
11823 12:47:39.721536 arm64_fp-stress_FPSIMD-3-1 pass
11824 12:47:39.724748 arm64_fp-stress_FPSIMD-4-0 pass
11825 12:47:39.728652 arm64_fp-stress_FPSIMD-4-1 pass
11826 12:47:39.731627 arm64_fp-stress_FPSIMD-5-0 pass
11827 12:47:39.734694 arm64_fp-stress_FPSIMD-5-1 pass
11828 12:47:39.738107 arm64_fp-stress_FPSIMD-6-0 pass
11829 12:47:39.738183 arm64_fp-stress_FPSIMD-6-1 pass
11830 12:47:39.741694 arm64_fp-stress_FPSIMD-7-0 pass
11831 12:47:39.744852 arm64_fp-stress_FPSIMD-7-1 pass
11832 12:47:39.748156 arm64_fp-stress pass
11833 12:47:39.751163 arm64_sve-ptrace_sve_not_available skip
11834 12:47:39.751260 arm64_sve-ptrace skip
11835 12:47:39.758459 arm64_sve-probe-vls_sve_not_available skip
11836 12:47:39.758557 arm64_sve-probe-vls skip
11837 12:47:39.761476 arm64_vec-syscfg_sve_not_supported skip
11838 12:47:39.764738 arm64_vec-syscfg_sve_not_supported skip
11839 12:47:39.771355 arm64_vec-syscfg_sve_not_supported skip
11840 12:47:39.774798 arm64_vec-syscfg_sve_not_supported skip
11841 12:47:39.777933 arm64_vec-syscfg_sve_not_supported skip
11842 12:47:39.781440 arm64_vec-syscfg_sve_not_supported skip
11843 12:47:39.784821 arm64_vec-syscfg_sve_not_supported skip
11844 12:47:39.788380 arm64_vec-syscfg_sve_not_supported skip
11845 12:47:39.791249 arm64_vec-syscfg_sve_not_supported skip
11846 12:47:39.794679 arm64_vec-syscfg_sve_not_supported skip
11847 12:47:39.798120 arm64_vec-syscfg_sme_not_supported skip
11848 12:47:39.801288 arm64_vec-syscfg_sme_not_supported skip
11849 12:47:39.804595 arm64_vec-syscfg_sme_not_supported skip
11850 12:47:39.807818 arm64_vec-syscfg_sme_not_supported skip
11851 12:47:39.811117 arm64_vec-syscfg_sme_not_supported skip
11852 12:47:39.814797 arm64_vec-syscfg_sme_not_supported skip
11853 12:47:39.821052 arm64_vec-syscfg_sme_not_supported skip
11854 12:47:39.824851 arm64_vec-syscfg_sme_not_supported skip
11855 12:47:39.827986 arm64_vec-syscfg_sme_not_supported skip
11856 12:47:39.831129 arm64_vec-syscfg_sme_not_supported skip
11857 12:47:39.831228 arm64_vec-syscfg pass
11858 12:47:39.834458 arm64_za-fork_skipped pass
11859 12:47:39.838124 arm64_za-fork pass
11860 12:47:39.841361 arm64_za-ptrace_sme_not_available skip
11861 12:47:39.841446 arm64_za-ptrace skip
11862 12:47:39.844471 arm64_check_buffer_fill skip
11863 12:47:39.847576 arm64_check_child_memory skip
11864 12:47:39.851416 arm64_check_gcr_el1_cswitch skip
11865 12:47:39.851515 arm64_check_ksm_options skip
11866 12:47:39.854764 arm64_check_mmap_options skip
11867 12:47:39.858004 arm64_check_prctl_check_basic_read pass
11868 12:47:39.861243 arm64_check_prctl_NONE pass
11869 12:47:39.864400 arm64_check_prctl_sync skip
11870 12:47:39.867588 arm64_check_prctl_async skip
11871 12:47:39.871032 arm64_check_prctl_sync_async skip
11872 12:47:39.871131 arm64_check_prctl pass
11873 12:47:39.874425 arm64_check_tags_inclusion skip
11874 12:47:39.878037 arm64_check_user_mem skip
11875 12:47:39.881116 arm64_btitest_nohint_func_call_using_br_x0 skip
11876 12:47:39.884586 arm64_btitest_nohint_func_call_using_br_x16 skip
11877 12:47:39.890972 arm64_btitest_nohint_func_call_using_blr skip
11878 12:47:39.894505 arm64_btitest_bti_none_func_call_using_br_x0 skip
11879 12:47:39.897271 arm64_btitest_bti_none_func_call_using_br_x16 skip
11880 12:47:39.903984 arm64_btitest_bti_none_func_call_using_blr skip
11881 12:47:39.907477 arm64_btitest_bti_c_func_call_using_br_x0 skip
11882 12:47:39.910773 arm64_btitest_bti_c_func_call_using_br_x16 skip
11883 12:47:39.914150 arm64_btitest_bti_c_func_call_using_blr skip
11884 12:47:39.920451 arm64_btitest_bti_j_func_call_using_br_x0 skip
11885 12:47:39.924273 arm64_btitest_bti_j_func_call_using_br_x16 skip
11886 12:47:39.927435 arm64_btitest_bti_j_func_call_using_blr skip
11887 12:47:39.930838 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11888 12:47:39.937224 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11889 12:47:39.940278 arm64_btitest_bti_jc_func_call_using_blr skip
11890 12:47:39.944118 arm64_btitest_paciasp_func_call_using_br_x0 skip
11891 12:47:39.950530 arm64_btitest_paciasp_func_call_using_br_x16 skip
11892 12:47:39.953737 arm64_btitest_paciasp_func_call_using_blr skip
11893 12:47:39.953839 arm64_btitest pass
11894 12:47:39.960708 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11895 12:47:39.963903 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11896 12:47:39.967165 arm64_nobtitest_nohint_func_call_using_blr skip
11897 12:47:39.974006 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11898 12:47:39.977379 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11899 12:47:39.980584 arm64_nobtitest_bti_none_func_call_using_blr skip
11900 12:47:39.987521 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11901 12:47:39.990162 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11902 12:47:39.993729 arm64_nobtitest_bti_c_func_call_using_blr skip
11903 12:47:40.000675 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11904 12:47:40.003609 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11905 12:47:40.006900 arm64_nobtitest_bti_j_func_call_using_blr skip
11906 12:47:40.010532 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11907 12:47:40.017135 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11908 12:47:40.020507 arm64_nobtitest_bti_jc_func_call_using_blr skip
11909 12:47:40.023635 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11910 12:47:40.030556 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11911 12:47:40.033817 arm64_nobtitest_paciasp_func_call_using_blr skip
11912 12:47:40.036718 arm64_nobtitest pass
11913 12:47:40.040575 arm64_hwcap_cpuinfo_match_RNG pass
11914 12:47:40.040647 arm64_hwcap_sigill_rng skip
11915 12:47:40.043775 arm64_hwcap_cpuinfo_match_SME pass
11916 12:47:40.046905 arm64_hwcap_sigill_SME pass
11917 12:47:40.050072 arm64_hwcap_cpuinfo_match_SVE pass
11918 12:47:40.053317 arm64_hwcap_sigill_SVE pass
11919 12:47:40.057201 arm64_hwcap_cpuinfo_match_SVE_2 pass
11920 12:47:40.060361 arm64_hwcap_sigill_sve_2 skip
11921 12:47:40.063661 arm64_hwcap_cpuinfo_match_SVE_AES pass
11922 12:47:40.066900 arm64_hwcap_sigill_sve_aes skip
11923 12:47:40.070283 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11924 12:47:40.073512 arm64_hwcap_sigill_sve2_pmull skip
11925 12:47:40.076521 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11926 12:47:40.079786 arm64_hwcap_sigill_sve2_bitperm skip
11927 12:47:40.083730 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11928 12:47:40.086352 arm64_hwcap_sigill_sve2_sha3 skip
11929 12:47:40.089966 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11930 12:47:40.092965 arm64_hwcap_sigill_sve2_sm4 skip
11931 12:47:40.096471 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11932 12:47:40.099743 arm64_hwcap_sigill_sve2_i8mm skip
11933 12:47:40.102926 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11934 12:47:40.106705 arm64_hwcap_sigill_sve2_f32mm skip
11935 12:47:40.109831 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11936 12:47:40.112931 arm64_hwcap_sigill_sve2_f64mm skip
11937 12:47:40.116174 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11938 12:47:40.119394 arm64_hwcap_sigill_sve2_bf16 skip
11939 12:47:40.122959 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11940 12:47:40.126411 arm64_hwcap_sigill_sve2_ebf16 skip
11941 12:47:40.129785 arm64_hwcap pass
11942 12:47:40.129882 arm64_ptrace_read_tpidr_one pass
11943 12:47:40.132628 arm64_ptrace_write_tpidr_one pass
11944 12:47:40.135979 arm64_ptrace_verify_tpidr_one pass
11945 12:47:40.139204 arm64_ptrace_count_tpidrs pass
11946 12:47:40.142673 arm64_ptrace_tpidr2_write pass
11947 12:47:40.146120 arm64_ptrace_tpidr2_read pass
11948 12:47:40.149370 arm64_ptrace_write_tpidr_only pass
11949 12:47:40.149475 arm64_ptrace pass
11950 12:47:40.152837 arm64_syscall-abi_getpid_FPSIMD pass
11951 12:47:40.156201 arm64_syscall-abi_sched_yield_FPSIMD pass
11952 12:47:40.159383 arm64_syscall-abi pass
11953 12:47:40.162636 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11954 12:47:40.169337 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11955 12:47:40.172588 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11956 12:47:40.175926 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11957 12:47:40.179514 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11958 12:47:40.182781 arm64_tpidr2 pass
11959 12:47:40.185979 + ../../utils/send-to-lava.sh ./output/result.txt
11960 12:47:40.192603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
11961 12:47:40.192895 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
11963 12:47:40.199383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
11964 12:47:40.199668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
11966 12:47:40.202099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
11967 12:47:40.202342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
11969 12:47:40.212648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
11970 12:47:40.212909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
11972 12:47:40.219052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
11973 12:47:40.219326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
11975 12:47:40.225771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
11976 12:47:40.226029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
11978 12:47:40.246020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
11979 12:47:40.246278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
11981 12:47:40.280449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
11982 12:47:40.280719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
11984 12:47:40.317861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
11985 12:47:40.318117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
11987 12:47:40.355343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
11988 12:47:40.355637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
11990 12:47:40.394070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
11991 12:47:40.394356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
11993 12:47:40.432977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
11994 12:47:40.433308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
11996 12:47:40.474695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
11997 12:47:40.474976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
11999 12:47:40.517323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
12000 12:47:40.517631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
12002 12:47:40.559657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
12003 12:47:40.559935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
12005 12:47:40.602834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
12006 12:47:40.603117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
12008 12:47:40.641006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12009 12:47:40.641272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12011 12:47:40.678102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12012 12:47:40.678356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12014 12:47:40.716829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12015 12:47:40.717121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12017 12:47:40.750730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12018 12:47:40.751015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12020 12:47:40.794371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12022 12:47:40.797241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12023 12:47:40.832200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12024 12:47:40.832515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12026 12:47:40.864224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12027 12:47:40.864524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12029 12:47:40.899888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12030 12:47:40.900170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12032 12:47:40.939203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12033 12:47:40.939490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12035 12:47:40.976240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12036 12:47:40.976554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12038 12:47:41.017978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12039 12:47:41.018237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12041 12:47:41.054670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12042 12:47:41.054953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12044 12:47:41.093080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12046 12:47:41.096545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12047 12:47:41.137747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12049 12:47:41.140791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12050 12:47:41.178728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
12051 12:47:41.179018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
12053 12:47:41.211875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12055 12:47:41.215387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12056 12:47:41.249156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12058 12:47:41.252176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12059 12:47:41.280942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12061 12:47:41.283951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12062 12:47:41.317741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
12063 12:47:41.318003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
12065 12:47:41.348215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12066 12:47:41.348529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12068 12:47:41.380406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12069 12:47:41.380670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12071 12:47:41.414217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12072 12:47:41.414497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12074 12:47:41.445552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12075 12:47:41.445810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12077 12:47:41.479410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12078 12:47:41.479741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12080 12:47:41.519280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12081 12:47:41.519543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12083 12:47:41.556946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12084 12:47:41.557199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12086 12:47:41.597462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12087 12:47:41.597732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12089 12:47:41.636738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12090 12:47:41.637006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12092 12:47:41.670990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12093 12:47:41.671280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12095 12:47:41.705327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12096 12:47:41.705579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12098 12:47:41.744090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12099 12:47:41.744377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12101 12:47:41.780211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12102 12:47:41.780497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12104 12:47:41.817650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12105 12:47:41.817937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12107 12:47:41.853829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12108 12:47:41.854088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12110 12:47:41.897439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12111 12:47:41.897718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12113 12:47:41.933545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12114 12:47:41.933808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12116 12:47:41.970050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12117 12:47:41.970311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12119 12:47:42.014466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip>
12120 12:47:42.014752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip
12122 12:47:42.049403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12123 12:47:42.049689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12125 12:47:42.097619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip>
12126 12:47:42.097891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip
12128 12:47:42.135889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12129 12:47:42.136173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12131 12:47:42.182251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12132 12:47:42.182542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12134 12:47:42.219204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12135 12:47:42.219491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12137 12:47:42.257587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12138 12:47:42.257869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12140 12:47:42.300202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12141 12:47:42.300529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12143 12:47:42.339887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12144 12:47:42.340175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12146 12:47:42.376382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12147 12:47:42.376640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12149 12:47:42.417724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12150 12:47:42.418012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12152 12:47:42.458881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12153 12:47:42.459167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12155 12:47:42.497139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12156 12:47:42.497408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12158 12:47:42.531334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12159 12:47:42.531598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12161 12:47:42.567904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12162 12:47:42.568190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12164 12:47:42.604022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12165 12:47:42.604307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12167 12:47:42.649405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12168 12:47:42.649682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12170 12:47:42.691734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12171 12:47:42.692051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12173 12:47:42.736260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12174 12:47:42.736557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12176 12:47:42.774008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12177 12:47:42.774261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12179 12:47:42.811662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12180 12:47:42.811942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12182 12:47:42.850594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12183 12:47:42.850883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12185 12:47:42.888424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12186 12:47:42.888675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12188 12:47:42.921908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12189 12:47:42.922194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12191 12:47:42.951214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12192 12:47:42.951468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12194 12:47:42.990676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12195 12:47:42.990931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12197 12:47:43.035676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12198 12:47:43.035935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12200 12:47:43.083479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip>
12201 12:47:43.083740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip
12203 12:47:43.119195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12204 12:47:43.119457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12206 12:47:43.154497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12207 12:47:43.154752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12209 12:47:43.195760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12210 12:47:43.196017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12212 12:47:43.240332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12213 12:47:43.240599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12215 12:47:43.273211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12216 12:47:43.273470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12218 12:47:43.308891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12219 12:47:43.309149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12221 12:47:43.348811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12222 12:47:43.349081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12224 12:47:43.379446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12225 12:47:43.379698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12227 12:47:43.411249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip>
12228 12:47:43.411528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip
12230 12:47:43.440942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_async RESULT=skip>
12231 12:47:43.441224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_async RESULT=skip
12233 12:47:43.482551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip
12235 12:47:43.485687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip>
12236 12:47:43.525265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12237 12:47:43.525564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12239 12:47:43.562746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12240 12:47:43.563064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12242 12:47:43.597267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12243 12:47:43.597547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12245 12:47:43.636613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12246 12:47:43.636881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12248 12:47:43.679024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12249 12:47:43.679282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12251 12:47:43.714337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12252 12:47:43.714593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12254 12:47:43.753726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12255 12:47:43.754020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12257 12:47:43.787869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12258 12:47:43.788152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12260 12:47:43.826781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12261 12:47:43.827039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12263 12:47:43.860836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12264 12:47:43.861119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12266 12:47:43.900223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12267 12:47:43.900508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12269 12:47:43.943592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12270 12:47:43.943871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12272 12:47:43.982611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12273 12:47:43.982891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12275 12:47:44.021821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12276 12:47:44.022110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12278 12:47:44.058880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12279 12:47:44.059131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12281 12:47:44.096521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12282 12:47:44.096778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12284 12:47:44.137170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12285 12:47:44.137434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12287 12:47:44.171807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12288 12:47:44.172084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12290 12:47:44.212349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12291 12:47:44.212653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12293 12:47:44.253147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12294 12:47:44.253431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12296 12:47:44.284257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12297 12:47:44.284534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12299 12:47:44.315516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12300 12:47:44.315777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12302 12:47:44.352938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12303 12:47:44.353197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12305 12:47:44.386181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12306 12:47:44.386436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12308 12:47:44.419351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12309 12:47:44.419611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12311 12:47:44.452501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12312 12:47:44.452756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12314 12:47:44.486159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12315 12:47:44.486414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12317 12:47:44.520198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12318 12:47:44.520485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12320 12:47:44.552437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12321 12:47:44.552699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12323 12:47:44.583380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12324 12:47:44.583636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12326 12:47:44.614551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12327 12:47:44.614806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12329 12:47:44.645857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12330 12:47:44.646119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12332 12:47:44.682090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12333 12:47:44.682341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12335 12:47:44.714827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12336 12:47:44.715089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12338 12:47:44.746473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12339 12:47:44.746732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12341 12:47:44.784450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12342 12:47:44.784733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12344 12:47:44.817482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12345 12:47:44.817751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12347 12:47:44.850187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12348 12:47:44.850439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12350 12:47:44.886190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12351 12:47:44.886446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12353 12:47:44.921545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12354 12:47:44.921808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12356 12:47:44.956123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12357 12:47:44.956402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12359 12:47:44.994714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12360 12:47:44.994965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12362 12:47:45.020196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip>
12363 12:47:45.020510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip
12365 12:47:45.062684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12366 12:47:45.062978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12368 12:47:45.096411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12369 12:47:45.096680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12371 12:47:45.138747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12372 12:47:45.139011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12374 12:47:45.171805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12375 12:47:45.172063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12377 12:47:45.217124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12378 12:47:45.217414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12380 12:47:45.255162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip>
12381 12:47:45.255437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip
12383 12:47:45.295976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12384 12:47:45.296239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12386 12:47:45.328236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip>
12387 12:47:45.328527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip
12389 12:47:45.375117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12390 12:47:45.375373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12392 12:47:45.417470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip>
12393 12:47:45.417743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip
12395 12:47:45.459646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12396 12:47:45.459903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12398 12:47:45.494577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip>
12399 12:47:45.494870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip
12401 12:47:45.532163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12402 12:47:45.532449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12404 12:47:45.564793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip
12406 12:47:45.568023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip>
12407 12:47:45.604709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12408 12:47:45.605000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12410 12:47:45.641774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip
12412 12:47:45.645241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip>
12413 12:47:45.689307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12414 12:47:45.689596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12416 12:47:45.723935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip
12418 12:47:45.727051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip>
12419 12:47:45.767357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12420 12:47:45.767638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12422 12:47:45.811686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip>
12423 12:47:45.811973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip
12425 12:47:45.850601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12426 12:47:45.850891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12428 12:47:45.885961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip>
12429 12:47:45.886242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip
12431 12:47:45.925024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12432 12:47:45.925313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12434 12:47:45.959552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip>
12435 12:47:45.959810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip
12437 12:47:45.999774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12438 12:47:46.000057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12440 12:47:46.035603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip
12442 12:47:46.038358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip>
12443 12:47:46.072939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12444 12:47:46.073199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12446 12:47:46.110350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12448 12:47:46.113332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12449 12:47:46.148417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12451 12:47:46.151432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12452 12:47:46.189205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12453 12:47:46.189486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12455 12:47:46.223191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12456 12:47:46.223476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12458 12:47:46.259515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12459 12:47:46.259796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12461 12:47:46.291843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12462 12:47:46.292121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12464 12:47:46.332199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12465 12:47:46.332494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12467 12:47:46.362904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12468 12:47:46.363156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12470 12:47:46.398841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12471 12:47:46.399120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12473 12:47:46.430116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12474 12:47:46.430396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12476 12:47:46.462903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12477 12:47:46.463163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12479 12:47:46.503984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12480 12:47:46.504246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12482 12:47:46.541777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12483 12:47:46.542038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12485 12:47:46.580611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12486 12:47:46.580869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12488 12:47:46.618745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12489 12:47:46.619065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12491 12:47:46.657296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12492 12:47:46.657560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12494 12:47:46.690972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12495 12:47:46.691066 + set +x
12496 12:47:46.691304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12498 12:47:46.697467 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 12703557_1.6.2.3.5>
12499 12:47:46.697730 Received signal: <ENDRUN> 1_kselftest-arm64 12703557_1.6.2.3.5
12500 12:47:46.697803 Ending use of test pattern.
12501 12:47:46.697864 Ending test lava.1_kselftest-arm64 (12703557_1.6.2.3.5), duration 29.61
12503 12:47:46.700572 <LAVA_TEST_RUNNER EXIT>
12504 12:47:46.700831 ok: lava_test_shell seems to have completed
12505 12:47:46.701851 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_async: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_prctl_sync: skip
arm64_check_prctl_sync_async: skip
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_rng: skip
arm64_hwcap_sigill_sve2_bf16: skip
arm64_hwcap_sigill_sve2_bitperm: skip
arm64_hwcap_sigill_sve2_ebf16: skip
arm64_hwcap_sigill_sve2_f32mm: skip
arm64_hwcap_sigill_sve2_f64mm: skip
arm64_hwcap_sigill_sve2_i8mm: skip
arm64_hwcap_sigill_sve2_pmull: skip
arm64_hwcap_sigill_sve2_sha3: skip
arm64_hwcap_sigill_sve2_sm4: skip
arm64_hwcap_sigill_sve_2: skip
arm64_hwcap_sigill_sve_aes: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_generic_pauth_not_enabled: skip
arm64_pac_pauth_not_enabled: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_sve_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_sve_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_sme_not_supported: skip
arm64_vec-syscfg_sve_not_supported: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_sme_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12506 12:47:46.701999 end: 3.1 lava-test-shell (duration 00:00:30) [common]
12507 12:47:46.702087 end: 3 lava-test-retry (duration 00:00:30) [common]
12508 12:47:46.702174 start: 4 finalize (timeout 00:07:22) [common]
12509 12:47:46.702265 start: 4.1 power-off (timeout 00:00:30) [common]
12510 12:47:46.702421 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
12511 12:47:46.779647 >> Command sent successfully.
12512 12:47:46.782102 Returned 0 in 0 seconds
12513 12:47:46.882483 end: 4.1 power-off (duration 00:00:00) [common]
12515 12:47:46.882807 start: 4.2 read-feedback (timeout 00:07:22) [common]
12516 12:47:46.883079 Listened to connection for namespace 'common' for up to 1s
12517 12:47:47.883991 Finalising connection for namespace 'common'
12518 12:47:47.884169 Disconnecting from shell: Finalise
12519 12:47:47.884254 / #
12520 12:47:47.984595 end: 4.2 read-feedback (duration 00:00:01) [common]
12521 12:47:47.984753 end: 4 finalize (duration 00:00:01) [common]
12522 12:47:47.984871 Cleaning after the job
12523 12:47:47.984967 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703557/tftp-deploy-4emrxmv5/ramdisk
12524 12:47:47.987484 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703557/tftp-deploy-4emrxmv5/kernel
12525 12:47:48.000496 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703557/tftp-deploy-4emrxmv5/dtb
12526 12:47:48.000721 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703557/tftp-deploy-4emrxmv5/nfsrootfs
12527 12:47:48.091542 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703557/tftp-deploy-4emrxmv5/modules
12528 12:47:48.098647 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12703557
12529 12:47:48.762853 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12703557
12530 12:47:48.763034 Job finished correctly