Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 17
- Kernel Errors: 38
1 12:36:56.729895 lava-dispatcher, installed at version: 2024.01
2 12:36:56.730110 start: 0 validate
3 12:36:56.730273 Start time: 2024-02-05 12:36:56.730258+00:00 (UTC)
4 12:36:56.730425 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:36:56.730571 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 12:36:57.004182 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:36:57.004349 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:37:50.781375 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:37:50.781577 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:37:51.045989 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:37:51.046155 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:37:51.314045 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:37:51.314800 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:37:54.820671 validate duration: 58.09
16 12:37:54.821035 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:37:54.821197 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:37:54.821312 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:37:54.821441 Not decompressing ramdisk as can be used compressed.
20 12:37:54.821540 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 12:37:54.821619 saving as /var/lib/lava/dispatcher/tmp/12703533/tftp-deploy-0ti03h9j/ramdisk/initrd.cpio.gz
22 12:37:54.821686 total size: 4665395 (4 MB)
23 12:37:54.822837 progress 0 % (0 MB)
24 12:37:54.824293 progress 5 % (0 MB)
25 12:37:54.825725 progress 10 % (0 MB)
26 12:37:54.827274 progress 15 % (0 MB)
27 12:37:54.828648 progress 20 % (0 MB)
28 12:37:54.830006 progress 25 % (1 MB)
29 12:37:54.831303 progress 30 % (1 MB)
30 12:37:54.832612 progress 35 % (1 MB)
31 12:37:54.833898 progress 40 % (1 MB)
32 12:37:54.835310 progress 45 % (2 MB)
33 12:37:54.836667 progress 50 % (2 MB)
34 12:37:54.838011 progress 55 % (2 MB)
35 12:37:54.839244 progress 60 % (2 MB)
36 12:37:54.840543 progress 65 % (2 MB)
37 12:37:54.841830 progress 70 % (3 MB)
38 12:37:54.843117 progress 75 % (3 MB)
39 12:37:54.844408 progress 80 % (3 MB)
40 12:37:54.845895 progress 85 % (3 MB)
41 12:37:54.847153 progress 90 % (4 MB)
42 12:37:54.848383 progress 95 % (4 MB)
43 12:37:54.849746 progress 100 % (4 MB)
44 12:37:54.849911 4 MB downloaded in 0.03 s (157.64 MB/s)
45 12:37:54.850062 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:37:54.850309 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:37:54.850414 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:37:54.850501 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:37:54.850643 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:37:54.850712 saving as /var/lib/lava/dispatcher/tmp/12703533/tftp-deploy-0ti03h9j/kernel/Image
52 12:37:54.850774 total size: 51534336 (49 MB)
53 12:37:54.850836 No compression specified
54 12:37:54.851935 progress 0 % (0 MB)
55 12:37:54.865876 progress 5 % (2 MB)
56 12:37:54.879668 progress 10 % (4 MB)
57 12:37:54.893232 progress 15 % (7 MB)
58 12:37:54.906860 progress 20 % (9 MB)
59 12:37:54.921058 progress 25 % (12 MB)
60 12:37:54.935623 progress 30 % (14 MB)
61 12:37:54.950465 progress 35 % (17 MB)
62 12:37:54.965349 progress 40 % (19 MB)
63 12:37:54.979536 progress 45 % (22 MB)
64 12:37:54.994342 progress 50 % (24 MB)
65 12:37:55.007677 progress 55 % (27 MB)
66 12:37:55.022150 progress 60 % (29 MB)
67 12:37:55.036178 progress 65 % (31 MB)
68 12:37:55.049572 progress 70 % (34 MB)
69 12:37:55.063002 progress 75 % (36 MB)
70 12:37:55.077809 progress 80 % (39 MB)
71 12:37:55.092593 progress 85 % (41 MB)
72 12:37:55.107658 progress 90 % (44 MB)
73 12:37:55.122734 progress 95 % (46 MB)
74 12:37:55.136469 progress 100 % (49 MB)
75 12:37:55.136736 49 MB downloaded in 0.29 s (171.87 MB/s)
76 12:37:55.136896 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:37:55.137136 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:37:55.137229 start: 1.3 download-retry (timeout 00:10:00) [common]
80 12:37:55.137315 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 12:37:55.137458 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:37:55.137577 saving as /var/lib/lava/dispatcher/tmp/12703533/tftp-deploy-0ti03h9j/dtb/mt8192-asurada-spherion-r0.dtb
83 12:37:55.137641 total size: 47278 (0 MB)
84 12:37:55.137704 No compression specified
85 12:37:55.138812 progress 69 % (0 MB)
86 12:37:55.139084 progress 100 % (0 MB)
87 12:37:55.139239 0 MB downloaded in 0.00 s (28.25 MB/s)
88 12:37:55.139360 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:37:55.139584 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:37:55.139669 start: 1.4 download-retry (timeout 00:10:00) [common]
92 12:37:55.139752 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 12:37:55.139865 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 12:37:55.139936 saving as /var/lib/lava/dispatcher/tmp/12703533/tftp-deploy-0ti03h9j/nfsrootfs/full.rootfs.tar
95 12:37:55.139996 total size: 200813988 (191 MB)
96 12:37:55.140057 Using unxz to decompress xz
97 12:37:55.144279 progress 0 % (0 MB)
98 12:37:55.698724 progress 5 % (9 MB)
99 12:37:56.244710 progress 10 % (19 MB)
100 12:37:56.849310 progress 15 % (28 MB)
101 12:37:57.227408 progress 20 % (38 MB)
102 12:37:57.557697 progress 25 % (47 MB)
103 12:37:58.158768 progress 30 % (57 MB)
104 12:37:58.715656 progress 35 % (67 MB)
105 12:37:59.320152 progress 40 % (76 MB)
106 12:37:59.886486 progress 45 % (86 MB)
107 12:38:00.477471 progress 50 % (95 MB)
108 12:38:01.129807 progress 55 % (105 MB)
109 12:38:01.815162 progress 60 % (114 MB)
110 12:38:01.940706 progress 65 % (124 MB)
111 12:38:02.091521 progress 70 % (134 MB)
112 12:38:02.205689 progress 75 % (143 MB)
113 12:38:02.277486 progress 80 % (153 MB)
114 12:38:02.352475 progress 85 % (162 MB)
115 12:38:02.464742 progress 90 % (172 MB)
116 12:38:02.765376 progress 95 % (181 MB)
117 12:38:03.389311 progress 100 % (191 MB)
118 12:38:03.394854 191 MB downloaded in 8.25 s (23.20 MB/s)
119 12:38:03.395140 end: 1.4.1 http-download (duration 00:00:08) [common]
121 12:38:03.395416 end: 1.4 download-retry (duration 00:00:08) [common]
122 12:38:03.395511 start: 1.5 download-retry (timeout 00:09:51) [common]
123 12:38:03.395601 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 12:38:03.395755 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:38:03.395902 saving as /var/lib/lava/dispatcher/tmp/12703533/tftp-deploy-0ti03h9j/modules/modules.tar
126 12:38:03.396039 total size: 8639964 (8 MB)
127 12:38:03.396135 Using unxz to decompress xz
128 12:38:03.400389 progress 0 % (0 MB)
129 12:38:03.423322 progress 5 % (0 MB)
130 12:38:03.448647 progress 10 % (0 MB)
131 12:38:03.472934 progress 15 % (1 MB)
132 12:38:03.496914 progress 20 % (1 MB)
133 12:38:03.521933 progress 25 % (2 MB)
134 12:38:03.550270 progress 30 % (2 MB)
135 12:38:03.575225 progress 35 % (2 MB)
136 12:38:03.599562 progress 40 % (3 MB)
137 12:38:03.625336 progress 45 % (3 MB)
138 12:38:03.653106 progress 50 % (4 MB)
139 12:38:03.681962 progress 55 % (4 MB)
140 12:38:03.710220 progress 60 % (4 MB)
141 12:38:03.738595 progress 65 % (5 MB)
142 12:38:03.765769 progress 70 % (5 MB)
143 12:38:03.792290 progress 75 % (6 MB)
144 12:38:03.834410 progress 80 % (6 MB)
145 12:38:03.864949 progress 85 % (7 MB)
146 12:38:03.890760 progress 90 % (7 MB)
147 12:38:03.921865 progress 95 % (7 MB)
148 12:38:03.950678 progress 100 % (8 MB)
149 12:38:03.956816 8 MB downloaded in 0.56 s (14.69 MB/s)
150 12:38:03.957071 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:38:03.957373 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:38:03.957517 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 12:38:03.957651 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 12:38:07.761508 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12703533/extract-nfsrootfs-ijr2jn3z
156 12:38:07.761720 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 12:38:07.761832 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 12:38:07.762007 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy
159 12:38:07.762141 makedir: /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/bin
160 12:38:07.762245 makedir: /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/tests
161 12:38:07.762346 makedir: /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/results
162 12:38:07.762447 Creating /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/bin/lava-add-keys
163 12:38:07.762591 Creating /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/bin/lava-add-sources
164 12:38:07.762724 Creating /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/bin/lava-background-process-start
165 12:38:07.762854 Creating /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/bin/lava-background-process-stop
166 12:38:07.762995 Creating /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/bin/lava-common-functions
167 12:38:07.763132 Creating /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/bin/lava-echo-ipv4
168 12:38:07.763266 Creating /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/bin/lava-install-packages
169 12:38:07.763394 Creating /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/bin/lava-installed-packages
170 12:38:07.763522 Creating /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/bin/lava-os-build
171 12:38:07.763650 Creating /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/bin/lava-probe-channel
172 12:38:07.763783 Creating /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/bin/lava-probe-ip
173 12:38:07.763922 Creating /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/bin/lava-target-ip
174 12:38:07.764050 Creating /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/bin/lava-target-mac
175 12:38:07.764183 Creating /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/bin/lava-target-storage
176 12:38:07.764311 Creating /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/bin/lava-test-case
177 12:38:07.764452 Creating /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/bin/lava-test-event
178 12:38:07.764588 Creating /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/bin/lava-test-feedback
179 12:38:07.764714 Creating /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/bin/lava-test-raise
180 12:38:07.764851 Creating /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/bin/lava-test-reference
181 12:38:07.764993 Creating /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/bin/lava-test-runner
182 12:38:07.765121 Creating /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/bin/lava-test-set
183 12:38:07.765247 Creating /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/bin/lava-test-shell
184 12:38:07.765374 Updating /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/bin/lava-add-keys (debian)
185 12:38:07.765579 Updating /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/bin/lava-add-sources (debian)
186 12:38:07.765772 Updating /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/bin/lava-install-packages (debian)
187 12:38:07.765914 Updating /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/bin/lava-installed-packages (debian)
188 12:38:07.766054 Updating /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/bin/lava-os-build (debian)
189 12:38:07.766176 Creating /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/environment
190 12:38:07.766273 LAVA metadata
191 12:38:07.766344 - LAVA_JOB_ID=12703533
192 12:38:07.766408 - LAVA_DISPATCHER_IP=192.168.201.1
193 12:38:07.766509 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 12:38:07.766576 skipped lava-vland-overlay
195 12:38:07.766649 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 12:38:07.766727 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 12:38:07.766786 skipped lava-multinode-overlay
198 12:38:07.766870 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 12:38:07.766948 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 12:38:07.767021 Loading test definitions
201 12:38:07.767121 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 12:38:07.767191 Using /lava-12703533 at stage 0
203 12:38:07.767497 uuid=12703533_1.6.2.3.1 testdef=None
204 12:38:07.767586 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 12:38:07.767673 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 12:38:07.768136 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 12:38:07.768361 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 12:38:07.768927 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 12:38:07.769159 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 12:38:07.769746 runner path: /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/0/tests/0_timesync-off test_uuid 12703533_1.6.2.3.1
213 12:38:07.769914 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 12:38:07.770164 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 12:38:07.770237 Using /lava-12703533 at stage 0
217 12:38:07.770333 Fetching tests from https://github.com/kernelci/test-definitions.git
218 12:38:07.770422 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/0/tests/1_kselftest-rtc'
219 12:38:15.616188 Running '/usr/bin/git checkout kernelci.org
220 12:38:15.770095 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 12:38:15.770878 uuid=12703533_1.6.2.3.5 testdef=None
222 12:38:15.771054 end: 1.6.2.3.5 git-repo-action (duration 00:00:08) [common]
224 12:38:15.771353 start: 1.6.2.3.6 test-overlay (timeout 00:09:39) [common]
225 12:38:15.772129 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 12:38:15.772362 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:39) [common]
228 12:38:15.773338 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 12:38:15.773631 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:39) [common]
231 12:38:15.794701 runner path: /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/0/tests/1_kselftest-rtc test_uuid 12703533_1.6.2.3.5
232 12:38:15.794828 BOARD='mt8192-asurada-spherion-r0'
233 12:38:15.794900 BRANCH='cip-gitlab'
234 12:38:15.794965 SKIPFILE='/dev/null'
235 12:38:15.795027 SKIP_INSTALL='True'
236 12:38:15.795084 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 12:38:15.795143 TST_CASENAME=''
238 12:38:15.795199 TST_CMDFILES='rtc'
239 12:38:15.795364 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 12:38:15.795577 Creating lava-test-runner.conf files
242 12:38:15.795643 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12703533/lava-overlay-mnomsjxy/lava-12703533/0 for stage 0
243 12:38:15.795738 - 0_timesync-off
244 12:38:15.795809 - 1_kselftest-rtc
245 12:38:15.795903 end: 1.6.2.3 test-definition (duration 00:00:08) [common]
246 12:38:15.796005 start: 1.6.2.4 compress-overlay (timeout 00:09:39) [common]
247 12:38:23.687187 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 12:38:23.687412 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:31) [common]
249 12:38:23.687535 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 12:38:23.687666 end: 1.6.2 lava-overlay (duration 00:00:16) [common]
251 12:38:23.687789 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:31) [common]
252 12:38:23.812067 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 12:38:23.812505 start: 1.6.4 extract-modules (timeout 00:09:31) [common]
254 12:38:23.812658 extracting modules file /var/lib/lava/dispatcher/tmp/12703533/tftp-deploy-0ti03h9j/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12703533/extract-nfsrootfs-ijr2jn3z
255 12:38:24.095466 extracting modules file /var/lib/lava/dispatcher/tmp/12703533/tftp-deploy-0ti03h9j/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12703533/extract-overlay-ramdisk-4leotcx9/ramdisk
256 12:38:24.336392 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 12:38:24.336575 start: 1.6.5 apply-overlay-tftp (timeout 00:09:30) [common]
258 12:38:24.336669 [common] Applying overlay to NFS
259 12:38:24.336750 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12703533/compress-overlay-33nmmxnb/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12703533/extract-nfsrootfs-ijr2jn3z
260 12:38:25.321211 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 12:38:25.321414 start: 1.6.6 configure-preseed-file (timeout 00:09:29) [common]
262 12:38:25.321588 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 12:38:25.321696 start: 1.6.7 compress-ramdisk (timeout 00:09:29) [common]
264 12:38:25.321817 Building ramdisk /var/lib/lava/dispatcher/tmp/12703533/extract-overlay-ramdisk-4leotcx9/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12703533/extract-overlay-ramdisk-4leotcx9/ramdisk
265 12:38:25.626245 >> 119430 blocks
266 12:38:27.601411 rename /var/lib/lava/dispatcher/tmp/12703533/extract-overlay-ramdisk-4leotcx9/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12703533/tftp-deploy-0ti03h9j/ramdisk/ramdisk.cpio.gz
267 12:38:27.601927 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 12:38:27.602054 start: 1.6.8 prepare-kernel (timeout 00:09:27) [common]
269 12:38:27.602163 start: 1.6.8.1 prepare-fit (timeout 00:09:27) [common]
270 12:38:27.602283 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12703533/tftp-deploy-0ti03h9j/kernel/Image'
271 12:38:41.074123 Returned 0 in 13 seconds
272 12:38:41.174819 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12703533/tftp-deploy-0ti03h9j/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12703533/tftp-deploy-0ti03h9j/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12703533/tftp-deploy-0ti03h9j/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12703533/tftp-deploy-0ti03h9j/kernel/image.itb
273 12:38:41.535206 output: FIT description: Kernel Image image with one or more FDT blobs
274 12:38:41.535606 output: Created: Mon Feb 5 12:38:41 2024
275 12:38:41.535683 output: Image 0 (kernel-1)
276 12:38:41.535750 output: Description:
277 12:38:41.535811 output: Created: Mon Feb 5 12:38:41 2024
278 12:38:41.535875 output: Type: Kernel Image
279 12:38:41.535938 output: Compression: lzma compressed
280 12:38:41.535997 output: Data Size: 12052857 Bytes = 11770.37 KiB = 11.49 MiB
281 12:38:41.536057 output: Architecture: AArch64
282 12:38:41.536114 output: OS: Linux
283 12:38:41.536173 output: Load Address: 0x00000000
284 12:38:41.536234 output: Entry Point: 0x00000000
285 12:38:41.536288 output: Hash algo: crc32
286 12:38:41.536346 output: Hash value: 8a14336a
287 12:38:41.536402 output: Image 1 (fdt-1)
288 12:38:41.536455 output: Description: mt8192-asurada-spherion-r0
289 12:38:41.536511 output: Created: Mon Feb 5 12:38:41 2024
290 12:38:41.536564 output: Type: Flat Device Tree
291 12:38:41.536618 output: Compression: uncompressed
292 12:38:41.536671 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 12:38:41.536724 output: Architecture: AArch64
294 12:38:41.536777 output: Hash algo: crc32
295 12:38:41.536830 output: Hash value: cc4352de
296 12:38:41.536883 output: Image 2 (ramdisk-1)
297 12:38:41.536936 output: Description: unavailable
298 12:38:41.536988 output: Created: Mon Feb 5 12:38:41 2024
299 12:38:41.537042 output: Type: RAMDisk Image
300 12:38:41.537095 output: Compression: Unknown Compression
301 12:38:41.537147 output: Data Size: 17802498 Bytes = 17385.25 KiB = 16.98 MiB
302 12:38:41.537200 output: Architecture: AArch64
303 12:38:41.537253 output: OS: Linux
304 12:38:41.537306 output: Load Address: unavailable
305 12:38:41.537359 output: Entry Point: unavailable
306 12:38:41.537411 output: Hash algo: crc32
307 12:38:41.537463 output: Hash value: 881117fc
308 12:38:41.537527 output: Default Configuration: 'conf-1'
309 12:38:41.537581 output: Configuration 0 (conf-1)
310 12:38:41.537634 output: Description: mt8192-asurada-spherion-r0
311 12:38:41.537687 output: Kernel: kernel-1
312 12:38:41.537740 output: Init Ramdisk: ramdisk-1
313 12:38:41.537793 output: FDT: fdt-1
314 12:38:41.537846 output: Loadables: kernel-1
315 12:38:41.537898 output:
316 12:38:41.538135 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 12:38:41.538235 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 12:38:41.538336 end: 1.6 prepare-tftp-overlay (duration 00:00:38) [common]
319 12:38:41.538428 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:13) [common]
320 12:38:41.538509 No LXC device requested
321 12:38:41.538590 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 12:38:41.538679 start: 1.8 deploy-device-env (timeout 00:09:13) [common]
323 12:38:41.538756 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 12:38:41.538827 Checking files for TFTP limit of 4294967296 bytes.
325 12:38:41.539320 end: 1 tftp-deploy (duration 00:00:47) [common]
326 12:38:41.539429 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 12:38:41.539523 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 12:38:41.539652 substitutions:
329 12:38:41.539720 - {DTB}: 12703533/tftp-deploy-0ti03h9j/dtb/mt8192-asurada-spherion-r0.dtb
330 12:38:41.539785 - {INITRD}: 12703533/tftp-deploy-0ti03h9j/ramdisk/ramdisk.cpio.gz
331 12:38:41.539847 - {KERNEL}: 12703533/tftp-deploy-0ti03h9j/kernel/Image
332 12:38:41.539905 - {LAVA_MAC}: None
333 12:38:41.539986 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12703533/extract-nfsrootfs-ijr2jn3z
334 12:38:41.540045 - {NFS_SERVER_IP}: 192.168.201.1
335 12:38:41.540101 - {PRESEED_CONFIG}: None
336 12:38:41.540157 - {PRESEED_LOCAL}: None
337 12:38:41.540212 - {RAMDISK}: 12703533/tftp-deploy-0ti03h9j/ramdisk/ramdisk.cpio.gz
338 12:38:41.540266 - {ROOT_PART}: None
339 12:38:41.540321 - {ROOT}: None
340 12:38:41.540375 - {SERVER_IP}: 192.168.201.1
341 12:38:41.540429 - {TEE}: None
342 12:38:41.540482 Parsed boot commands:
343 12:38:41.540536 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 12:38:41.540720 Parsed boot commands: tftpboot 192.168.201.1 12703533/tftp-deploy-0ti03h9j/kernel/image.itb 12703533/tftp-deploy-0ti03h9j/kernel/cmdline
345 12:38:41.540810 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 12:38:41.540897 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 12:38:41.540990 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 12:38:41.541072 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 12:38:41.541148 Not connected, no need to disconnect.
350 12:38:41.541223 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 12:38:41.541306 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 12:38:41.541378 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
353 12:38:41.545375 Setting prompt string to ['lava-test: # ']
354 12:38:41.545801 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 12:38:41.545911 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 12:38:41.546008 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 12:38:41.546101 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 12:38:41.546341 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
359 12:38:46.684694 >> Command sent successfully.
360 12:38:46.695312 Returned 0 in 5 seconds
361 12:38:46.796648 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 12:38:46.798126 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 12:38:46.798642 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 12:38:46.799104 Setting prompt string to 'Starting depthcharge on Spherion...'
366 12:38:46.799454 Changing prompt to 'Starting depthcharge on Spherion...'
367 12:38:46.799955 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 12:38:46.801296 [Enter `^Ec?' for help]
369 12:38:46.963789
370 12:38:46.964353
371 12:38:46.964701 F0: 102B 0000
372 12:38:46.965044
373 12:38:46.965364 F3: 1001 0000 [0200]
374 12:38:46.965845
375 12:38:46.967324 F3: 1001 0000
376 12:38:46.967755
377 12:38:46.968163 F7: 102D 0000
378 12:38:46.968490
379 12:38:46.968799 F1: 0000 0000
380 12:38:46.969100
381 12:38:46.970808 V0: 0000 0000 [0001]
382 12:38:46.971333
383 12:38:46.971758 00: 0007 8000
384 12:38:46.972253
385 12:38:46.974703 01: 0000 0000
386 12:38:46.975299
387 12:38:46.975954 BP: 0C00 0209 [0000]
388 12:38:46.976564
389 12:38:46.978024 G0: 1182 0000
390 12:38:46.978521
391 12:38:46.978863 EC: 0000 0021 [4000]
392 12:38:46.979179
393 12:38:46.981370 S7: 0000 0000 [0000]
394 12:38:46.981890
395 12:38:46.982242 CC: 0000 0000 [0001]
396 12:38:46.982568
397 12:38:46.984741 T0: 0000 0040 [010F]
398 12:38:46.985177
399 12:38:46.985565 Jump to BL
400 12:38:46.985919
401 12:38:47.010401
402 12:38:47.010823
403 12:38:47.011136
404 12:38:47.018066 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 12:38:47.021377 ARM64: Exception handlers installed.
406 12:38:47.025036 ARM64: Testing exception
407 12:38:47.029064 ARM64: Done test exception
408 12:38:47.032818 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 12:38:47.044712 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 12:38:47.051918 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 12:38:47.061704 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 12:38:47.068214 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 12:38:47.074929 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 12:38:47.087485 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 12:38:47.094125 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 12:38:47.113117 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 12:38:47.116679 WDT: Last reset was cold boot
418 12:38:47.120117 SPI1(PAD0) initialized at 2873684 Hz
419 12:38:47.123138 SPI5(PAD0) initialized at 992727 Hz
420 12:38:47.126488 VBOOT: Loading verstage.
421 12:38:47.133330 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:38:47.136519 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 12:38:47.140055 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 12:38:47.143349 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 12:38:47.150763 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 12:38:47.157762 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 12:38:47.168018 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 12:38:47.168458
429 12:38:47.168802
430 12:38:47.178185 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 12:38:47.181430 ARM64: Exception handlers installed.
432 12:38:47.184763 ARM64: Testing exception
433 12:38:47.185197 ARM64: Done test exception
434 12:38:47.191743 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 12:38:47.194741 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 12:38:47.209133 Probing TPM: . done!
437 12:38:47.209694 TPM ready after 0 ms
438 12:38:47.216131 Connected to device vid:did:rid of 1ae0:0028:00
439 12:38:47.262841 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 12:38:47.263297 Initialized TPM device CR50 revision 0
441 12:38:47.274869 tlcl_send_startup: Startup return code is 0
442 12:38:47.275316 TPM: setup succeeded
443 12:38:47.286319 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 12:38:47.295050 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 12:38:47.307610 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 12:38:47.316006 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 12:38:47.319208 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 12:38:47.323278 in-header: 03 07 00 00 08 00 00 00
449 12:38:47.326649 in-data: aa e4 47 04 13 02 00 00
450 12:38:47.330044 Chrome EC: UHEPI supported
451 12:38:47.337133 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 12:38:47.340905 in-header: 03 9d 00 00 08 00 00 00
453 12:38:47.344942 in-data: 10 20 20 08 00 00 00 00
454 12:38:47.345387 Phase 1
455 12:38:47.351991 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 12:38:47.355717 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 12:38:47.363084 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 12:38:47.363532 Recovery requested (1009000e)
459 12:38:47.372359 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 12:38:47.377572 tlcl_extend: response is 0
461 12:38:47.385622 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 12:38:47.391294 tlcl_extend: response is 0
463 12:38:47.398041 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 12:38:47.418803 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 12:38:47.426015 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 12:38:47.426514
467 12:38:47.426873
468 12:38:47.436875 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 12:38:47.437303 ARM64: Exception handlers installed.
470 12:38:47.440549 ARM64: Testing exception
471 12:38:47.444041 ARM64: Done test exception
472 12:38:47.464425 pmic_efuse_setting: Set efuses in 11 msecs
473 12:38:47.467752 pmwrap_interface_init: Select PMIF_VLD_RDY
474 12:38:47.471727 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 12:38:47.479159 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 12:38:47.483045 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 12:38:47.486573 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 12:38:47.494296 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 12:38:47.497956 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 12:38:47.501707 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 12:38:47.505134 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 12:38:47.512174 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 12:38:47.515362 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 12:38:47.521918 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 12:38:47.525183 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 12:38:47.528377 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 12:38:47.535382 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 12:38:47.541871 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 12:38:47.548678 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 12:38:47.551828 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 12:38:47.558425 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 12:38:47.565916 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 12:38:47.569817 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 12:38:47.577199 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 12:38:47.580752 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 12:38:47.587204 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 12:38:47.590928 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 12:38:47.598062 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 12:38:47.604871 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 12:38:47.608136 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 12:38:47.611814 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 12:38:47.618437 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 12:38:47.622458 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 12:38:47.629725 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 12:38:47.633331 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 12:38:47.636690 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 12:38:47.644060 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 12:38:47.647447 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 12:38:47.651189 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 12:38:47.658247 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 12:38:47.661788 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 12:38:47.668579 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 12:38:47.671836 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 12:38:47.675160 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 12:38:47.678440 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 12:38:47.684891 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 12:38:47.688396 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 12:38:47.691774 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 12:38:47.698480 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 12:38:47.701460 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 12:38:47.704830 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 12:38:47.711812 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 12:38:47.714908 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 12:38:47.718134 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 12:38:47.724952 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 12:38:47.734818 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 12:38:47.738157 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 12:38:47.748630 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 12:38:47.754841 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 12:38:47.761455 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 12:38:47.764845 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 12:38:47.768264 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 12:38:47.776258 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x1a
534 12:38:47.782823 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 12:38:47.786152 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 12:38:47.792580 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 12:38:47.800989 [RTC]rtc_get_frequency_meter,154: input=15, output=793
538 12:38:47.804269 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
539 12:38:47.810912 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
540 12:38:47.814260 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
541 12:38:47.817379 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
542 12:38:47.820915 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
543 12:38:47.824267 ADC[4]: Raw value=895191 ID=7
544 12:38:47.827562 ADC[3]: Raw value=213440 ID=1
545 12:38:47.830774 RAM Code: 0x71
546 12:38:47.834272 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
547 12:38:47.837354 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
548 12:38:47.847777 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
549 12:38:47.854885 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
550 12:38:47.858201 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
551 12:38:47.861203 in-header: 03 07 00 00 08 00 00 00
552 12:38:47.864519 in-data: aa e4 47 04 13 02 00 00
553 12:38:47.864628 Chrome EC: UHEPI supported
554 12:38:47.871440 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
555 12:38:47.875684 in-header: 03 d5 00 00 08 00 00 00
556 12:38:47.879276 in-data: 98 20 60 08 00 00 00 00
557 12:38:47.882931 MRC: failed to locate region type 0.
558 12:38:47.890344 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
559 12:38:47.893703 DRAM-K: Running full calibration
560 12:38:47.900381 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
561 12:38:47.900521 header.status = 0x0
562 12:38:47.903509 header.version = 0x6 (expected: 0x6)
563 12:38:47.907131 header.size = 0xd00 (expected: 0xd00)
564 12:38:47.910423 header.flags = 0x0
565 12:38:47.913896 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
566 12:38:47.933126 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
567 12:38:47.939514 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
568 12:38:47.943038 dram_init: ddr_geometry: 2
569 12:38:47.946657 [EMI] MDL number = 2
570 12:38:47.947187 [EMI] Get MDL freq = 0
571 12:38:47.949800 dram_init: ddr_type: 0
572 12:38:47.950262 is_discrete_lpddr4: 1
573 12:38:47.953131 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
574 12:38:47.953655
575 12:38:47.954115
576 12:38:47.956523 [Bian_co] ETT version 0.0.0.1
577 12:38:47.963285 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
578 12:38:47.963813
579 12:38:47.966694 dramc_set_vcore_voltage set vcore to 650000
580 12:38:47.967104 Read voltage for 800, 4
581 12:38:47.970073 Vio18 = 0
582 12:38:47.970570 Vcore = 650000
583 12:38:47.971061 Vdram = 0
584 12:38:47.973395 Vddq = 0
585 12:38:47.973879 Vmddr = 0
586 12:38:47.976384 dram_init: config_dvfs: 1
587 12:38:47.979615 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
588 12:38:47.986157 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
589 12:38:47.989697 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
590 12:38:47.993074 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
591 12:38:47.996376 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
592 12:38:47.999413 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
593 12:38:48.002818 MEM_TYPE=3, freq_sel=18
594 12:38:48.006222 sv_algorithm_assistance_LP4_1600
595 12:38:48.009299 ============ PULL DRAM RESETB DOWN ============
596 12:38:48.012750 ========== PULL DRAM RESETB DOWN end =========
597 12:38:48.019491 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
598 12:38:48.022884 ===================================
599 12:38:48.026224 LPDDR4 DRAM CONFIGURATION
600 12:38:48.026318 ===================================
601 12:38:48.029738 EX_ROW_EN[0] = 0x0
602 12:38:48.032939 EX_ROW_EN[1] = 0x0
603 12:38:48.033025 LP4Y_EN = 0x0
604 12:38:48.036137 WORK_FSP = 0x0
605 12:38:48.036247 WL = 0x2
606 12:38:48.039622 RL = 0x2
607 12:38:48.039709 BL = 0x2
608 12:38:48.043140 RPST = 0x0
609 12:38:48.043226 RD_PRE = 0x0
610 12:38:48.046142 WR_PRE = 0x1
611 12:38:48.046229 WR_PST = 0x0
612 12:38:48.049558 DBI_WR = 0x0
613 12:38:48.049635 DBI_RD = 0x0
614 12:38:48.053069 OTF = 0x1
615 12:38:48.056479 ===================================
616 12:38:48.059674 ===================================
617 12:38:48.059751 ANA top config
618 12:38:48.062929 ===================================
619 12:38:48.066180 DLL_ASYNC_EN = 0
620 12:38:48.069401 ALL_SLAVE_EN = 1
621 12:38:48.072846 NEW_RANK_MODE = 1
622 12:38:48.072947 DLL_IDLE_MODE = 1
623 12:38:48.076102 LP45_APHY_COMB_EN = 1
624 12:38:48.079376 TX_ODT_DIS = 1
625 12:38:48.082823 NEW_8X_MODE = 1
626 12:38:48.086199 ===================================
627 12:38:48.089353 ===================================
628 12:38:48.092742 data_rate = 1600
629 12:38:48.092820 CKR = 1
630 12:38:48.096156 DQ_P2S_RATIO = 8
631 12:38:48.099427 ===================================
632 12:38:48.103055 CA_P2S_RATIO = 8
633 12:38:48.106391 DQ_CA_OPEN = 0
634 12:38:48.109565 DQ_SEMI_OPEN = 0
635 12:38:48.112870 CA_SEMI_OPEN = 0
636 12:38:48.112951 CA_FULL_RATE = 0
637 12:38:48.116282 DQ_CKDIV4_EN = 1
638 12:38:48.119569 CA_CKDIV4_EN = 1
639 12:38:48.122851 CA_PREDIV_EN = 0
640 12:38:48.126455 PH8_DLY = 0
641 12:38:48.126530 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
642 12:38:48.130093 DQ_AAMCK_DIV = 4
643 12:38:48.133529 CA_AAMCK_DIV = 4
644 12:38:48.137293 CA_ADMCK_DIV = 4
645 12:38:48.137406 DQ_TRACK_CA_EN = 0
646 12:38:48.141157 CA_PICK = 800
647 12:38:48.144720 CA_MCKIO = 800
648 12:38:48.148450 MCKIO_SEMI = 0
649 12:38:48.152089 PLL_FREQ = 3068
650 12:38:48.152178 DQ_UI_PI_RATIO = 32
651 12:38:48.156086 CA_UI_PI_RATIO = 0
652 12:38:48.160329 ===================================
653 12:38:48.164014 ===================================
654 12:38:48.164095 memory_type:LPDDR4
655 12:38:48.167740 GP_NUM : 10
656 12:38:48.167820 SRAM_EN : 1
657 12:38:48.171530 MD32_EN : 0
658 12:38:48.175021 ===================================
659 12:38:48.178958 [ANA_INIT] >>>>>>>>>>>>>>
660 12:38:48.179049 <<<<<< [CONFIGURE PHASE]: ANA_TX
661 12:38:48.182507 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
662 12:38:48.186302 ===================================
663 12:38:48.190163 data_rate = 1600,PCW = 0X7600
664 12:38:48.194103 ===================================
665 12:38:48.197749 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
666 12:38:48.201448 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 12:38:48.205110 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
668 12:38:48.212625 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
669 12:38:48.215917 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
670 12:38:48.219711 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
671 12:38:48.219850 [ANA_INIT] flow start
672 12:38:48.223155 [ANA_INIT] PLL >>>>>>>>
673 12:38:48.226594 [ANA_INIT] PLL <<<<<<<<
674 12:38:48.226681 [ANA_INIT] MIDPI >>>>>>>>
675 12:38:48.230403 [ANA_INIT] MIDPI <<<<<<<<
676 12:38:48.230497 [ANA_INIT] DLL >>>>>>>>
677 12:38:48.233884 [ANA_INIT] flow end
678 12:38:48.237835 ============ LP4 DIFF to SE enter ============
679 12:38:48.241655 ============ LP4 DIFF to SE exit ============
680 12:38:48.245150 [ANA_INIT] <<<<<<<<<<<<<
681 12:38:48.249006 [Flow] Enable top DCM control >>>>>
682 12:38:48.253176 [Flow] Enable top DCM control <<<<<
683 12:38:48.253291 Enable DLL master slave shuffle
684 12:38:48.260571 ==============================================================
685 12:38:48.260659 Gating Mode config
686 12:38:48.266971 ==============================================================
687 12:38:48.267052 Config description:
688 12:38:48.277169 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
689 12:38:48.283525 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
690 12:38:48.290580 SELPH_MODE 0: By rank 1: By Phase
691 12:38:48.293776 ==============================================================
692 12:38:48.296853 GAT_TRACK_EN = 1
693 12:38:48.300478 RX_GATING_MODE = 2
694 12:38:48.303757 RX_GATING_TRACK_MODE = 2
695 12:38:48.306928 SELPH_MODE = 1
696 12:38:48.310489 PICG_EARLY_EN = 1
697 12:38:48.313891 VALID_LAT_VALUE = 1
698 12:38:48.320350 ==============================================================
699 12:38:48.323843 Enter into Gating configuration >>>>
700 12:38:48.327115 Exit from Gating configuration <<<<
701 12:38:48.327203 Enter into DVFS_PRE_config >>>>>
702 12:38:48.340507 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
703 12:38:48.343864 Exit from DVFS_PRE_config <<<<<
704 12:38:48.347053 Enter into PICG configuration >>>>
705 12:38:48.350451 Exit from PICG configuration <<<<
706 12:38:48.350538 [RX_INPUT] configuration >>>>>
707 12:38:48.353840 [RX_INPUT] configuration <<<<<
708 12:38:48.360410 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
709 12:38:48.364013 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
710 12:38:48.370440 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
711 12:38:48.377109 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
712 12:38:48.383576 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
713 12:38:48.390483 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
714 12:38:48.393720 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
715 12:38:48.397072 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
716 12:38:48.400453 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
717 12:38:48.407204 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
718 12:38:48.410523 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
719 12:38:48.413733 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
720 12:38:48.417011 ===================================
721 12:38:48.420204 LPDDR4 DRAM CONFIGURATION
722 12:38:48.423727 ===================================
723 12:38:48.427163 EX_ROW_EN[0] = 0x0
724 12:38:48.427253 EX_ROW_EN[1] = 0x0
725 12:38:48.430332 LP4Y_EN = 0x0
726 12:38:48.430420 WORK_FSP = 0x0
727 12:38:48.433818 WL = 0x2
728 12:38:48.433917 RL = 0x2
729 12:38:48.437103 BL = 0x2
730 12:38:48.437188 RPST = 0x0
731 12:38:48.440420 RD_PRE = 0x0
732 12:38:48.440505 WR_PRE = 0x1
733 12:38:48.443747 WR_PST = 0x0
734 12:38:48.443833 DBI_WR = 0x0
735 12:38:48.446991 DBI_RD = 0x0
736 12:38:48.447076 OTF = 0x1
737 12:38:48.450451 ===================================
738 12:38:48.457120 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
739 12:38:48.460563 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
740 12:38:48.463814 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
741 12:38:48.467159 ===================================
742 12:38:48.470496 LPDDR4 DRAM CONFIGURATION
743 12:38:48.473802 ===================================
744 12:38:48.473888 EX_ROW_EN[0] = 0x10
745 12:38:48.477264 EX_ROW_EN[1] = 0x0
746 12:38:48.480602 LP4Y_EN = 0x0
747 12:38:48.480687 WORK_FSP = 0x0
748 12:38:48.483534 WL = 0x2
749 12:38:48.483629 RL = 0x2
750 12:38:48.487338 BL = 0x2
751 12:38:48.487487 RPST = 0x0
752 12:38:48.490357 RD_PRE = 0x0
753 12:38:48.490446 WR_PRE = 0x1
754 12:38:48.493632 WR_PST = 0x0
755 12:38:48.493718 DBI_WR = 0x0
756 12:38:48.497273 DBI_RD = 0x0
757 12:38:48.497358 OTF = 0x1
758 12:38:48.500561 ===================================
759 12:38:48.506985 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
760 12:38:48.511249 nWR fixed to 40
761 12:38:48.514430 [ModeRegInit_LP4] CH0 RK0
762 12:38:48.514541 [ModeRegInit_LP4] CH0 RK1
763 12:38:48.517631 [ModeRegInit_LP4] CH1 RK0
764 12:38:48.521062 [ModeRegInit_LP4] CH1 RK1
765 12:38:48.521139 match AC timing 13
766 12:38:48.527840 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
767 12:38:48.531276 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
768 12:38:48.534582 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
769 12:38:48.541127 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
770 12:38:48.544476 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
771 12:38:48.544569 [EMI DOE] emi_dcm 0
772 12:38:48.551308 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
773 12:38:48.551386 ==
774 12:38:48.554531 Dram Type= 6, Freq= 0, CH_0, rank 0
775 12:38:48.557998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
776 12:38:48.558075 ==
777 12:38:48.564627 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
778 12:38:48.571357 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
779 12:38:48.578608 [CA 0] Center 38 (7~69) winsize 63
780 12:38:48.581865 [CA 1] Center 37 (7~68) winsize 62
781 12:38:48.585303 [CA 2] Center 35 (5~66) winsize 62
782 12:38:48.588746 [CA 3] Center 35 (5~66) winsize 62
783 12:38:48.592045 [CA 4] Center 34 (4~65) winsize 62
784 12:38:48.595302 [CA 5] Center 34 (4~65) winsize 62
785 12:38:48.595381
786 12:38:48.598779 [CmdBusTrainingLP45] Vref(ca) range 1: 34
787 12:38:48.598865
788 12:38:48.602032 [CATrainingPosCal] consider 1 rank data
789 12:38:48.605408 u2DelayCellTimex100 = 270/100 ps
790 12:38:48.608630 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
791 12:38:48.611887 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
792 12:38:48.618419 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
793 12:38:48.621906 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
794 12:38:48.625389 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
795 12:38:48.628471 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
796 12:38:48.628610
797 12:38:48.631914 CA PerBit enable=1, Macro0, CA PI delay=34
798 12:38:48.632018
799 12:38:48.635296 [CBTSetCACLKResult] CA Dly = 34
800 12:38:48.635385 CS Dly: 6 (0~37)
801 12:38:48.638487 ==
802 12:38:48.638636 Dram Type= 6, Freq= 0, CH_0, rank 1
803 12:38:48.645401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 12:38:48.645518 ==
805 12:38:48.648525 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
806 12:38:48.655346 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
807 12:38:48.665130 [CA 0] Center 38 (7~69) winsize 63
808 12:38:48.668468 [CA 1] Center 37 (7~68) winsize 62
809 12:38:48.671811 [CA 2] Center 35 (5~66) winsize 62
810 12:38:48.675269 [CA 3] Center 35 (5~66) winsize 62
811 12:38:48.678545 [CA 4] Center 34 (4~65) winsize 62
812 12:38:48.681730 [CA 5] Center 34 (4~65) winsize 62
813 12:38:48.681819
814 12:38:48.685112 [CmdBusTrainingLP45] Vref(ca) range 1: 30
815 12:38:48.685200
816 12:38:48.688346 [CATrainingPosCal] consider 2 rank data
817 12:38:48.691622 u2DelayCellTimex100 = 270/100 ps
818 12:38:48.695049 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
819 12:38:48.698774 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
820 12:38:48.704987 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
821 12:38:48.708744 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
822 12:38:48.712359 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
823 12:38:48.716374 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
824 12:38:48.716464
825 12:38:48.719699 CA PerBit enable=1, Macro0, CA PI delay=34
826 12:38:48.719787
827 12:38:48.719878 [CBTSetCACLKResult] CA Dly = 34
828 12:38:48.723238 CS Dly: 6 (0~37)
829 12:38:48.723327
830 12:38:48.727170 ----->DramcWriteLeveling(PI) begin...
831 12:38:48.727263 ==
832 12:38:48.730485 Dram Type= 6, Freq= 0, CH_0, rank 0
833 12:38:48.734045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
834 12:38:48.734135 ==
835 12:38:48.737723 Write leveling (Byte 0): 31 => 31
836 12:38:48.741610 Write leveling (Byte 1): 31 => 31
837 12:38:48.745112 DramcWriteLeveling(PI) end<-----
838 12:38:48.745200
839 12:38:48.745288 ==
840 12:38:48.748827 Dram Type= 6, Freq= 0, CH_0, rank 0
841 12:38:48.752393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
842 12:38:48.752493 ==
843 12:38:48.755803 [Gating] SW mode calibration
844 12:38:48.763198 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
845 12:38:48.767311 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
846 12:38:48.771058 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
847 12:38:48.774710 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
848 12:38:48.778471 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
849 12:38:48.785930 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
850 12:38:48.789781 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 12:38:48.793426 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 12:38:48.796681 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 12:38:48.800824 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 12:38:48.804541 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 12:38:48.811735 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 12:38:48.815531 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 12:38:48.819164 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 12:38:48.823371 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:38:48.826712 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:38:48.834350 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:38:48.837975 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 12:38:48.841684 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 12:38:48.845410 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
864 12:38:48.849152 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
865 12:38:48.853306 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 12:38:48.861037 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 12:38:48.864736 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 12:38:48.868177 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 12:38:48.872112 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 12:38:48.875813 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 12:38:48.879389 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 12:38:48.886322 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 12:38:48.890167 0 9 12 | B1->B0 | 2727 3232 | 1 1 | (1 1) (1 1)
874 12:38:48.893901 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 12:38:48.897630 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 12:38:48.901354 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 12:38:48.908789 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 12:38:48.912352 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 12:38:48.916326 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 12:38:48.920057 0 10 8 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (1 0)
881 12:38:48.923239 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
882 12:38:48.930578 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 12:38:48.934304 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 12:38:48.937996 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 12:38:48.941435 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 12:38:48.945631 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 12:38:48.953260 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 12:38:48.956668 0 11 8 | B1->B0 | 2626 2f2f | 0 0 | (0 0) (0 0)
889 12:38:48.960279 0 11 12 | B1->B0 | 3333 3d3d | 1 0 | (0 0) (0 0)
890 12:38:48.963792 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 12:38:48.967437 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 12:38:48.971199 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 12:38:48.978639 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 12:38:48.982463 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 12:38:48.986195 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
896 12:38:48.989799 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
897 12:38:48.993436 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
898 12:38:49.001295 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 12:38:49.004830 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 12:38:49.008530 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 12:38:49.012170 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 12:38:49.015881 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 12:38:49.019935 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 12:38:49.027344 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 12:38:49.030831 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 12:38:49.034831 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 12:38:49.038132 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 12:38:49.044685 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 12:38:49.047904 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 12:38:49.051441 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 12:38:49.058006 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 12:38:49.061526 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
913 12:38:49.064624 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
914 12:38:49.068245 Total UI for P1: 0, mck2ui 16
915 12:38:49.071353 best dqsien dly found for B0: ( 0, 14, 8)
916 12:38:49.074513 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
917 12:38:49.078281 Total UI for P1: 0, mck2ui 16
918 12:38:49.081595 best dqsien dly found for B1: ( 0, 14, 12)
919 12:38:49.084791 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
920 12:38:49.088085 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
921 12:38:49.091419
922 12:38:49.094733 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
923 12:38:49.098255 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
924 12:38:49.101496 [Gating] SW calibration Done
925 12:38:49.101613 ==
926 12:38:49.104692 Dram Type= 6, Freq= 0, CH_0, rank 0
927 12:38:49.108051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 12:38:49.108126 ==
929 12:38:49.108191 RX Vref Scan: 0
930 12:38:49.108252
931 12:38:49.111522 RX Vref 0 -> 0, step: 1
932 12:38:49.111629
933 12:38:49.114883 RX Delay -130 -> 252, step: 16
934 12:38:49.118192 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
935 12:38:49.121429 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
936 12:38:49.128277 iDelay=206, Bit 2, Center 77 (-50 ~ 205) 256
937 12:38:49.131657 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
938 12:38:49.134847 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
939 12:38:49.138348 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
940 12:38:49.141431 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
941 12:38:49.144737 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
942 12:38:49.151461 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
943 12:38:49.154797 iDelay=206, Bit 9, Center 61 (-66 ~ 189) 256
944 12:38:49.158273 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
945 12:38:49.161569 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
946 12:38:49.164773 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
947 12:38:49.171603 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
948 12:38:49.174792 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
949 12:38:49.178036 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
950 12:38:49.178119 ==
951 12:38:49.181412 Dram Type= 6, Freq= 0, CH_0, rank 0
952 12:38:49.184788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
953 12:38:49.188153 ==
954 12:38:49.188229 DQS Delay:
955 12:38:49.188293 DQS0 = 0, DQS1 = 0
956 12:38:49.191638 DQM Delay:
957 12:38:49.191766 DQM0 = 79, DQM1 = 70
958 12:38:49.194771 DQ Delay:
959 12:38:49.194851 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
960 12:38:49.198045 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =85
961 12:38:49.201426 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
962 12:38:49.204710 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
963 12:38:49.204783
964 12:38:49.208034
965 12:38:49.208132 ==
966 12:38:49.211959 Dram Type= 6, Freq= 0, CH_0, rank 0
967 12:38:49.215142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 12:38:49.215253 ==
969 12:38:49.215358
970 12:38:49.215453
971 12:38:49.215544 TX Vref Scan disable
972 12:38:49.219136 == TX Byte 0 ==
973 12:38:49.222493 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
974 12:38:49.225794 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
975 12:38:49.229056 == TX Byte 1 ==
976 12:38:49.232367 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
977 12:38:49.235805 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
978 12:38:49.239119 ==
979 12:38:49.242438 Dram Type= 6, Freq= 0, CH_0, rank 0
980 12:38:49.245870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
981 12:38:49.245978 ==
982 12:38:49.258120 TX Vref=22, minBit 11, minWin=26, winSum=434
983 12:38:49.261279 TX Vref=24, minBit 1, minWin=27, winSum=440
984 12:38:49.264617 TX Vref=26, minBit 0, minWin=27, winSum=438
985 12:38:49.268063 TX Vref=28, minBit 0, minWin=27, winSum=443
986 12:38:49.271363 TX Vref=30, minBit 14, minWin=26, winSum=439
987 12:38:49.277910 TX Vref=32, minBit 2, minWin=27, winSum=442
988 12:38:49.281153 [TxChooseVref] Worse bit 0, Min win 27, Win sum 443, Final Vref 28
989 12:38:49.281270
990 12:38:49.284333 Final TX Range 1 Vref 28
991 12:38:49.284418
992 12:38:49.284483 ==
993 12:38:49.287973 Dram Type= 6, Freq= 0, CH_0, rank 0
994 12:38:49.291106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
995 12:38:49.294551 ==
996 12:38:49.294638
997 12:38:49.294705
998 12:38:49.294783 TX Vref Scan disable
999 12:38:49.297791 == TX Byte 0 ==
1000 12:38:49.301405 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1001 12:38:49.304734 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1002 12:38:49.307941 == TX Byte 1 ==
1003 12:38:49.311219 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1004 12:38:49.314524 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1005 12:38:49.318238
1006 12:38:49.318354 [DATLAT]
1007 12:38:49.318433 Freq=800, CH0 RK0
1008 12:38:49.318508
1009 12:38:49.321471 DATLAT Default: 0xa
1010 12:38:49.321580 0, 0xFFFF, sum = 0
1011 12:38:49.324762 1, 0xFFFF, sum = 0
1012 12:38:49.324843 2, 0xFFFF, sum = 0
1013 12:38:49.328120 3, 0xFFFF, sum = 0
1014 12:38:49.328209 4, 0xFFFF, sum = 0
1015 12:38:49.331504 5, 0xFFFF, sum = 0
1016 12:38:49.334522 6, 0xFFFF, sum = 0
1017 12:38:49.334600 7, 0xFFFF, sum = 0
1018 12:38:49.338121 8, 0xFFFF, sum = 0
1019 12:38:49.338197 9, 0x0, sum = 1
1020 12:38:49.338262 10, 0x0, sum = 2
1021 12:38:49.341455 11, 0x0, sum = 3
1022 12:38:49.341557 12, 0x0, sum = 4
1023 12:38:49.344735 best_step = 10
1024 12:38:49.344813
1025 12:38:49.344888 ==
1026 12:38:49.348093 Dram Type= 6, Freq= 0, CH_0, rank 0
1027 12:38:49.351392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1028 12:38:49.351485 ==
1029 12:38:49.354808 RX Vref Scan: 1
1030 12:38:49.354890
1031 12:38:49.354954 Set Vref Range= 32 -> 127
1032 12:38:49.355014
1033 12:38:49.358045 RX Vref 32 -> 127, step: 1
1034 12:38:49.358161
1035 12:38:49.361355 RX Delay -111 -> 252, step: 8
1036 12:38:49.361430
1037 12:38:49.364707 Set Vref, RX VrefLevel [Byte0]: 32
1038 12:38:49.368091 [Byte1]: 32
1039 12:38:49.368172
1040 12:38:49.371503 Set Vref, RX VrefLevel [Byte0]: 33
1041 12:38:49.374814 [Byte1]: 33
1042 12:38:49.378490
1043 12:38:49.378567 Set Vref, RX VrefLevel [Byte0]: 34
1044 12:38:49.381682 [Byte1]: 34
1045 12:38:49.386081
1046 12:38:49.386220 Set Vref, RX VrefLevel [Byte0]: 35
1047 12:38:49.389523 [Byte1]: 35
1048 12:38:49.393765
1049 12:38:49.393844 Set Vref, RX VrefLevel [Byte0]: 36
1050 12:38:49.397185 [Byte1]: 36
1051 12:38:49.401506
1052 12:38:49.401625 Set Vref, RX VrefLevel [Byte0]: 37
1053 12:38:49.404823 [Byte1]: 37
1054 12:38:49.409230
1055 12:38:49.409326 Set Vref, RX VrefLevel [Byte0]: 38
1056 12:38:49.412299 [Byte1]: 38
1057 12:38:49.416817
1058 12:38:49.416908 Set Vref, RX VrefLevel [Byte0]: 39
1059 12:38:49.420297 [Byte1]: 39
1060 12:38:49.424238
1061 12:38:49.424317 Set Vref, RX VrefLevel [Byte0]: 40
1062 12:38:49.427540 [Byte1]: 40
1063 12:38:49.432012
1064 12:38:49.432088 Set Vref, RX VrefLevel [Byte0]: 41
1065 12:38:49.435331 [Byte1]: 41
1066 12:38:49.439866
1067 12:38:49.439943 Set Vref, RX VrefLevel [Byte0]: 42
1068 12:38:49.443226 [Byte1]: 42
1069 12:38:49.447258
1070 12:38:49.447361 Set Vref, RX VrefLevel [Byte0]: 43
1071 12:38:49.450587 [Byte1]: 43
1072 12:38:49.455113
1073 12:38:49.455188 Set Vref, RX VrefLevel [Byte0]: 44
1074 12:38:49.458229 [Byte1]: 44
1075 12:38:49.462694
1076 12:38:49.462769 Set Vref, RX VrefLevel [Byte0]: 45
1077 12:38:49.466063 [Byte1]: 45
1078 12:38:49.470815
1079 12:38:49.470903 Set Vref, RX VrefLevel [Byte0]: 46
1080 12:38:49.474233 [Byte1]: 46
1081 12:38:49.478064
1082 12:38:49.478151 Set Vref, RX VrefLevel [Byte0]: 47
1083 12:38:49.481489 [Byte1]: 47
1084 12:38:49.485493
1085 12:38:49.485572 Set Vref, RX VrefLevel [Byte0]: 48
1086 12:38:49.489109 [Byte1]: 48
1087 12:38:49.493718
1088 12:38:49.493801 Set Vref, RX VrefLevel [Byte0]: 49
1089 12:38:49.497079 [Byte1]: 49
1090 12:38:49.501235
1091 12:38:49.501312 Set Vref, RX VrefLevel [Byte0]: 50
1092 12:38:49.504482 [Byte1]: 50
1093 12:38:49.508338
1094 12:38:49.508420 Set Vref, RX VrefLevel [Byte0]: 51
1095 12:38:49.511809 [Byte1]: 51
1096 12:38:49.516169
1097 12:38:49.516248 Set Vref, RX VrefLevel [Byte0]: 52
1098 12:38:49.519447 [Byte1]: 52
1099 12:38:49.523620
1100 12:38:49.523696 Set Vref, RX VrefLevel [Byte0]: 53
1101 12:38:49.527057 [Byte1]: 53
1102 12:38:49.531505
1103 12:38:49.531578 Set Vref, RX VrefLevel [Byte0]: 54
1104 12:38:49.534757 [Byte1]: 54
1105 12:38:49.538988
1106 12:38:49.539061 Set Vref, RX VrefLevel [Byte0]: 55
1107 12:38:49.542261 [Byte1]: 55
1108 12:38:49.546781
1109 12:38:49.546854 Set Vref, RX VrefLevel [Byte0]: 56
1110 12:38:49.550109 [Byte1]: 56
1111 12:38:49.554323
1112 12:38:49.554404 Set Vref, RX VrefLevel [Byte0]: 57
1113 12:38:49.557901 [Byte1]: 57
1114 12:38:49.561951
1115 12:38:49.562041 Set Vref, RX VrefLevel [Byte0]: 58
1116 12:38:49.565258 [Byte1]: 58
1117 12:38:49.569703
1118 12:38:49.569786 Set Vref, RX VrefLevel [Byte0]: 59
1119 12:38:49.573110 [Byte1]: 59
1120 12:38:49.577362
1121 12:38:49.577435 Set Vref, RX VrefLevel [Byte0]: 60
1122 12:38:49.580450 [Byte1]: 60
1123 12:38:49.585099
1124 12:38:49.585175 Set Vref, RX VrefLevel [Byte0]: 61
1125 12:38:49.588393 [Byte1]: 61
1126 12:38:49.592657
1127 12:38:49.592737 Set Vref, RX VrefLevel [Byte0]: 62
1128 12:38:49.595772 [Byte1]: 62
1129 12:38:49.600386
1130 12:38:49.600460 Set Vref, RX VrefLevel [Byte0]: 63
1131 12:38:49.603645 [Byte1]: 63
1132 12:38:49.607998
1133 12:38:49.608075 Set Vref, RX VrefLevel [Byte0]: 64
1134 12:38:49.611364 [Byte1]: 64
1135 12:38:49.615700
1136 12:38:49.615779 Set Vref, RX VrefLevel [Byte0]: 65
1137 12:38:49.618901 [Byte1]: 65
1138 12:38:49.623317
1139 12:38:49.623391 Set Vref, RX VrefLevel [Byte0]: 66
1140 12:38:49.626430 [Byte1]: 66
1141 12:38:49.630836
1142 12:38:49.630922 Set Vref, RX VrefLevel [Byte0]: 67
1143 12:38:49.634036 [Byte1]: 67
1144 12:38:49.638570
1145 12:38:49.638643 Set Vref, RX VrefLevel [Byte0]: 68
1146 12:38:49.641943 [Byte1]: 68
1147 12:38:49.646339
1148 12:38:49.646416 Set Vref, RX VrefLevel [Byte0]: 69
1149 12:38:49.649607 [Byte1]: 69
1150 12:38:49.653691
1151 12:38:49.653770 Set Vref, RX VrefLevel [Byte0]: 70
1152 12:38:49.656848 [Byte1]: 70
1153 12:38:49.661429
1154 12:38:49.661545 Set Vref, RX VrefLevel [Byte0]: 71
1155 12:38:49.664531 [Byte1]: 71
1156 12:38:49.668942
1157 12:38:49.669019 Set Vref, RX VrefLevel [Byte0]: 72
1158 12:38:49.672493 [Byte1]: 72
1159 12:38:49.676656
1160 12:38:49.676737 Set Vref, RX VrefLevel [Byte0]: 73
1161 12:38:49.679800 [Byte1]: 73
1162 12:38:49.684167
1163 12:38:49.684264 Set Vref, RX VrefLevel [Byte0]: 74
1164 12:38:49.687830 [Byte1]: 74
1165 12:38:49.692089
1166 12:38:49.692173 Set Vref, RX VrefLevel [Byte0]: 75
1167 12:38:49.695325 [Byte1]: 75
1168 12:38:49.699832
1169 12:38:49.699909 Set Vref, RX VrefLevel [Byte0]: 76
1170 12:38:49.702757 [Byte1]: 76
1171 12:38:49.707377
1172 12:38:49.707484 Set Vref, RX VrefLevel [Byte0]: 77
1173 12:38:49.710535 [Byte1]: 77
1174 12:38:49.714950
1175 12:38:49.715038 Set Vref, RX VrefLevel [Byte0]: 78
1176 12:38:49.718221 [Byte1]: 78
1177 12:38:49.722430
1178 12:38:49.722514 Set Vref, RX VrefLevel [Byte0]: 79
1179 12:38:49.726070 [Byte1]: 79
1180 12:38:49.730039
1181 12:38:49.730112 Final RX Vref Byte 0 = 59 to rank0
1182 12:38:49.733328 Final RX Vref Byte 1 = 59 to rank0
1183 12:38:49.737037 Final RX Vref Byte 0 = 59 to rank1
1184 12:38:49.740083 Final RX Vref Byte 1 = 59 to rank1==
1185 12:38:49.743852 Dram Type= 6, Freq= 0, CH_0, rank 0
1186 12:38:49.750354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1187 12:38:49.750435 ==
1188 12:38:49.750506 DQS Delay:
1189 12:38:49.750566 DQS0 = 0, DQS1 = 0
1190 12:38:49.753593 DQM Delay:
1191 12:38:49.753664 DQM0 = 81, DQM1 = 68
1192 12:38:49.757058 DQ Delay:
1193 12:38:49.760250 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1194 12:38:49.760336 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1195 12:38:49.763806 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1196 12:38:49.766908 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1197 12:38:49.766985
1198 12:38:49.770168
1199 12:38:49.776878 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c2b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
1200 12:38:49.780144 CH0 RK0: MR19=606, MR18=2C2B
1201 12:38:49.786938 CH0_RK0: MR19=0x606, MR18=0x2C2B, DQSOSC=398, MR23=63, INC=93, DEC=62
1202 12:38:49.787024
1203 12:38:49.790244 ----->DramcWriteLeveling(PI) begin...
1204 12:38:49.790355 ==
1205 12:38:49.793549 Dram Type= 6, Freq= 0, CH_0, rank 1
1206 12:38:49.797115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1207 12:38:49.797220 ==
1208 12:38:49.800313 Write leveling (Byte 0): 30 => 30
1209 12:38:49.803620 Write leveling (Byte 1): 30 => 30
1210 12:38:49.806842 DramcWriteLeveling(PI) end<-----
1211 12:38:49.806934
1212 12:38:49.806998 ==
1213 12:38:49.810442 Dram Type= 6, Freq= 0, CH_0, rank 1
1214 12:38:49.813602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1215 12:38:49.813713 ==
1216 12:38:49.817067 [Gating] SW mode calibration
1217 12:38:49.823831 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1218 12:38:49.830607 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1219 12:38:49.833686 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1220 12:38:49.836936 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1221 12:38:49.843746 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1222 12:38:49.846953 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1223 12:38:49.850268 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 12:38:49.856790 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 12:38:49.860434 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 12:38:49.863498 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 12:38:49.870297 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 12:38:49.873759 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 12:38:49.877005 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 12:38:49.880156 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 12:38:49.886755 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 12:38:49.930791 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 12:38:49.931192 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 12:38:49.931273 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 12:38:49.931521 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 12:38:49.931607 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1237 12:38:49.931670 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1238 12:38:49.931741 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 12:38:49.931801 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 12:38:49.931865 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 12:38:49.931943 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 12:38:49.975101 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 12:38:49.975488 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 12:38:49.975711 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 12:38:49.976058 0 9 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1246 12:38:49.976136 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 12:38:49.976220 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 12:38:49.976319 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 12:38:49.976418 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 12:38:49.976512 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 12:38:49.976686 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 12:38:49.979949 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 0) (1 0)
1253 12:38:49.983202 0 10 8 | B1->B0 | 3131 2626 | 1 0 | (1 0) (1 0)
1254 12:38:49.986458 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 12:38:49.993397 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 12:38:49.996379 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 12:38:50.000021 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 12:38:50.003374 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 12:38:50.010092 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 12:38:50.013053 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1261 12:38:50.016533 0 11 8 | B1->B0 | 2e2e 3939 | 0 0 | (0 0) (1 1)
1262 12:38:50.023309 0 11 12 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
1263 12:38:50.026509 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 12:38:50.030072 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 12:38:50.036678 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 12:38:50.039727 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 12:38:50.043540 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 12:38:50.050794 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1269 12:38:50.054611 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1270 12:38:50.057855 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1271 12:38:50.060830 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 12:38:50.067826 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 12:38:50.071569 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 12:38:50.074755 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 12:38:50.078119 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 12:38:50.085160 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 12:38:50.088298 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 12:38:50.091692 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 12:38:50.098007 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 12:38:50.101572 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 12:38:50.104951 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 12:38:50.111513 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 12:38:50.114672 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 12:38:50.118173 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 12:38:50.124633 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1286 12:38:50.128306 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1287 12:38:50.131596 Total UI for P1: 0, mck2ui 16
1288 12:38:50.134734 best dqsien dly found for B0: ( 0, 14, 8)
1289 12:38:50.138413 Total UI for P1: 0, mck2ui 16
1290 12:38:50.141589 best dqsien dly found for B1: ( 0, 14, 10)
1291 12:38:50.144764 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1292 12:38:50.147958 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1293 12:38:50.148044
1294 12:38:50.151260 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1295 12:38:50.154623 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1296 12:38:50.158070 [Gating] SW calibration Done
1297 12:38:50.158161 ==
1298 12:38:50.161162 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 12:38:50.164564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 12:38:50.164653 ==
1301 12:38:50.167813 RX Vref Scan: 0
1302 12:38:50.167900
1303 12:38:50.171447 RX Vref 0 -> 0, step: 1
1304 12:38:50.171534
1305 12:38:50.174820 RX Delay -130 -> 252, step: 16
1306 12:38:50.177792 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1307 12:38:50.181376 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1308 12:38:50.184596 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1309 12:38:50.187814 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1310 12:38:50.194622 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1311 12:38:50.197785 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1312 12:38:50.201325 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1313 12:38:50.204287 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1314 12:38:50.207767 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1315 12:38:50.211316 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1316 12:38:50.217751 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1317 12:38:50.221138 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1318 12:38:50.224661 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1319 12:38:50.227728 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1320 12:38:50.234484 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1321 12:38:50.237989 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1322 12:38:50.238075 ==
1323 12:38:50.241288 Dram Type= 6, Freq= 0, CH_0, rank 1
1324 12:38:50.244634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1325 12:38:50.244718 ==
1326 12:38:50.244823 DQS Delay:
1327 12:38:50.247853 DQS0 = 0, DQS1 = 0
1328 12:38:50.247962 DQM Delay:
1329 12:38:50.251285 DQM0 = 77, DQM1 = 69
1330 12:38:50.251395 DQ Delay:
1331 12:38:50.254488 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =77
1332 12:38:50.257986 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =93
1333 12:38:50.261358 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1334 12:38:50.264340 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1335 12:38:50.264420
1336 12:38:50.264485
1337 12:38:50.264547 ==
1338 12:38:50.267831 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 12:38:50.271027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1340 12:38:50.274275 ==
1341 12:38:50.274351
1342 12:38:50.274415
1343 12:38:50.274474 TX Vref Scan disable
1344 12:38:50.277818 == TX Byte 0 ==
1345 12:38:50.281046 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1346 12:38:50.284420 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1347 12:38:50.287692 == TX Byte 1 ==
1348 12:38:50.290960 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1349 12:38:50.294330 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1350 12:38:50.297558 ==
1351 12:38:50.297640 Dram Type= 6, Freq= 0, CH_0, rank 1
1352 12:38:50.304442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1353 12:38:50.304528 ==
1354 12:38:50.316271 TX Vref=22, minBit 1, minWin=26, winSum=432
1355 12:38:50.319863 TX Vref=24, minBit 0, minWin=27, winSum=438
1356 12:38:50.323091 TX Vref=26, minBit 1, minWin=27, winSum=439
1357 12:38:50.326190 TX Vref=28, minBit 1, minWin=27, winSum=444
1358 12:38:50.329707 TX Vref=30, minBit 9, minWin=27, winSum=444
1359 12:38:50.332818 TX Vref=32, minBit 2, minWin=27, winSum=443
1360 12:38:50.339516 [TxChooseVref] Worse bit 1, Min win 27, Win sum 444, Final Vref 28
1361 12:38:50.339603
1362 12:38:50.342880 Final TX Range 1 Vref 28
1363 12:38:50.342965
1364 12:38:50.343031 ==
1365 12:38:50.346016 Dram Type= 6, Freq= 0, CH_0, rank 1
1366 12:38:50.349313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1367 12:38:50.349397 ==
1368 12:38:50.352988
1369 12:38:50.353071
1370 12:38:50.353136 TX Vref Scan disable
1371 12:38:50.356290 == TX Byte 0 ==
1372 12:38:50.359685 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1373 12:38:50.362911 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1374 12:38:50.366063 == TX Byte 1 ==
1375 12:38:50.369701 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1376 12:38:50.372787 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1377 12:38:50.376336
1378 12:38:50.376413 [DATLAT]
1379 12:38:50.376477 Freq=800, CH0 RK1
1380 12:38:50.376537
1381 12:38:50.379447 DATLAT Default: 0xa
1382 12:38:50.379516 0, 0xFFFF, sum = 0
1383 12:38:50.382744 1, 0xFFFF, sum = 0
1384 12:38:50.382814 2, 0xFFFF, sum = 0
1385 12:38:50.386286 3, 0xFFFF, sum = 0
1386 12:38:50.386363 4, 0xFFFF, sum = 0
1387 12:38:50.389411 5, 0xFFFF, sum = 0
1388 12:38:50.389510 6, 0xFFFF, sum = 0
1389 12:38:50.392666 7, 0xFFFF, sum = 0
1390 12:38:50.396355 8, 0xFFFF, sum = 0
1391 12:38:50.396429 9, 0x0, sum = 1
1392 12:38:50.396490 10, 0x0, sum = 2
1393 12:38:50.399714 11, 0x0, sum = 3
1394 12:38:50.399789 12, 0x0, sum = 4
1395 12:38:50.402884 best_step = 10
1396 12:38:50.402954
1397 12:38:50.403022 ==
1398 12:38:50.406406 Dram Type= 6, Freq= 0, CH_0, rank 1
1399 12:38:50.409442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1400 12:38:50.409556 ==
1401 12:38:50.412674 RX Vref Scan: 0
1402 12:38:50.412757
1403 12:38:50.412817 RX Vref 0 -> 0, step: 1
1404 12:38:50.412875
1405 12:38:50.416036 RX Delay -111 -> 252, step: 8
1406 12:38:50.423145 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1407 12:38:50.426357 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1408 12:38:50.429589 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1409 12:38:50.432785 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1410 12:38:50.436333 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1411 12:38:50.442805 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1412 12:38:50.446533 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1413 12:38:50.449573 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1414 12:38:50.453160 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1415 12:38:50.456366 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1416 12:38:50.462945 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1417 12:38:50.466472 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1418 12:38:50.469613 iDelay=209, Bit 12, Center 72 (-47 ~ 192) 240
1419 12:38:50.472845 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1420 12:38:50.476195 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1421 12:38:50.483045 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1422 12:38:50.483124 ==
1423 12:38:50.486397 Dram Type= 6, Freq= 0, CH_0, rank 1
1424 12:38:50.489788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1425 12:38:50.489894 ==
1426 12:38:50.489985 DQS Delay:
1427 12:38:50.493016 DQS0 = 0, DQS1 = 0
1428 12:38:50.493087 DQM Delay:
1429 12:38:50.496126 DQM0 = 79, DQM1 = 70
1430 12:38:50.496196 DQ Delay:
1431 12:38:50.499673 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1432 12:38:50.502853 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =92
1433 12:38:50.506062 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1434 12:38:50.509481 DQ12 =72, DQ13 =76, DQ14 =80, DQ15 =80
1435 12:38:50.509593
1436 12:38:50.509655
1437 12:38:50.516279 [DQSOSCAuto] RK1, (LSB)MR18= 0x4722, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1438 12:38:50.519735 CH0 RK1: MR19=606, MR18=4722
1439 12:38:50.526020 CH0_RK1: MR19=0x606, MR18=0x4722, DQSOSC=392, MR23=63, INC=96, DEC=64
1440 12:38:50.529426 [RxdqsGatingPostProcess] freq 800
1441 12:38:50.536228 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1442 12:38:50.539625 Pre-setting of DQS Precalculation
1443 12:38:50.543038 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1444 12:38:50.543118 ==
1445 12:38:50.546199 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 12:38:50.549804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 12:38:50.549881 ==
1448 12:38:50.556404 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1449 12:38:50.562953 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1450 12:38:50.571349 [CA 0] Center 36 (6~66) winsize 61
1451 12:38:50.574521 [CA 1] Center 36 (6~67) winsize 62
1452 12:38:50.577836 [CA 2] Center 34 (4~64) winsize 61
1453 12:38:50.581373 [CA 3] Center 34 (4~64) winsize 61
1454 12:38:50.584524 [CA 4] Center 34 (4~64) winsize 61
1455 12:38:50.587671 [CA 5] Center 34 (4~64) winsize 61
1456 12:38:50.587761
1457 12:38:50.591255 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1458 12:38:50.591328
1459 12:38:50.594595 [CATrainingPosCal] consider 1 rank data
1460 12:38:50.597999 u2DelayCellTimex100 = 270/100 ps
1461 12:38:50.601273 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1462 12:38:50.604512 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1463 12:38:50.611278 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1464 12:38:50.614627 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1465 12:38:50.617662 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1466 12:38:50.621362 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1467 12:38:50.621463
1468 12:38:50.624380 CA PerBit enable=1, Macro0, CA PI delay=34
1469 12:38:50.624452
1470 12:38:50.627898 [CBTSetCACLKResult] CA Dly = 34
1471 12:38:50.627978 CS Dly: 5 (0~36)
1472 12:38:50.628040 ==
1473 12:38:50.631151 Dram Type= 6, Freq= 0, CH_1, rank 1
1474 12:38:50.637825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1475 12:38:50.637900 ==
1476 12:38:50.641358 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1477 12:38:50.647940 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1478 12:38:50.657383 [CA 0] Center 36 (6~66) winsize 61
1479 12:38:50.660881 [CA 1] Center 36 (6~67) winsize 62
1480 12:38:50.664036 [CA 2] Center 34 (4~65) winsize 62
1481 12:38:50.667306 [CA 3] Center 34 (4~64) winsize 61
1482 12:38:50.670810 [CA 4] Center 34 (4~65) winsize 62
1483 12:38:50.674057 [CA 5] Center 33 (3~64) winsize 62
1484 12:38:50.674126
1485 12:38:50.677530 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1486 12:38:50.677619
1487 12:38:50.680800 [CATrainingPosCal] consider 2 rank data
1488 12:38:50.684046 u2DelayCellTimex100 = 270/100 ps
1489 12:38:50.687361 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1490 12:38:50.690727 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1491 12:38:50.694248 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1492 12:38:50.700944 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1493 12:38:50.704849 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1494 12:38:50.707788 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1495 12:38:50.707872
1496 12:38:50.711398 CA PerBit enable=1, Macro0, CA PI delay=34
1497 12:38:50.711482
1498 12:38:50.714679 [CBTSetCACLKResult] CA Dly = 34
1499 12:38:50.714763 CS Dly: 5 (0~37)
1500 12:38:50.714829
1501 12:38:50.718731 ----->DramcWriteLeveling(PI) begin...
1502 12:38:50.718817 ==
1503 12:38:50.722122 Dram Type= 6, Freq= 0, CH_1, rank 0
1504 12:38:50.725760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1505 12:38:50.725846 ==
1506 12:38:50.729629 Write leveling (Byte 0): 27 => 27
1507 12:38:50.733226 Write leveling (Byte 1): 31 => 31
1508 12:38:50.736854 DramcWriteLeveling(PI) end<-----
1509 12:38:50.737025
1510 12:38:50.737128 ==
1511 12:38:50.740048 Dram Type= 6, Freq= 0, CH_1, rank 0
1512 12:38:50.743621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1513 12:38:50.743714 ==
1514 12:38:50.746839 [Gating] SW mode calibration
1515 12:38:50.753426 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1516 12:38:50.760406 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1517 12:38:50.763740 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1518 12:38:50.766932 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1519 12:38:50.773436 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1520 12:38:50.776813 0 6 12 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1521 12:38:50.780422 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 12:38:50.783650 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 12:38:50.790480 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 12:38:50.793712 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 12:38:50.797121 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 12:38:50.803526 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 12:38:50.807064 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 12:38:50.810460 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 12:38:50.816789 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 12:38:50.820157 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 12:38:50.823463 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 12:38:50.830397 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 12:38:50.833383 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 12:38:50.836905 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1535 12:38:50.843344 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1536 12:38:50.846792 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 12:38:50.850329 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 12:38:50.856737 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 12:38:50.860234 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 12:38:50.863558 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 12:38:50.870214 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 12:38:50.873413 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 12:38:50.876976 0 9 8 | B1->B0 | 2c2c 2929 | 0 0 | (0 0) (0 0)
1544 12:38:50.883455 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 12:38:50.886874 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 12:38:50.890085 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 12:38:50.893408 0 9 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
1548 12:38:50.900123 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 12:38:50.903688 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 12:38:50.906846 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 12:38:50.913616 0 10 8 | B1->B0 | 2d2d 2c2c | 0 1 | (1 0) (1 0)
1552 12:38:50.917083 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 12:38:50.920224 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 12:38:50.927127 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 12:38:50.930493 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 12:38:50.933535 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 12:38:50.940171 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 12:38:50.943707 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1559 12:38:50.946891 0 11 8 | B1->B0 | 3939 3535 | 0 0 | (1 1) (0 0)
1560 12:38:50.953711 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 12:38:50.957147 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 12:38:50.960489 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 12:38:50.966948 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 12:38:50.970478 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 12:38:50.973841 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 12:38:50.977013 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 12:38:50.983804 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 12:38:50.986911 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 12:38:50.990443 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 12:38:50.997112 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 12:38:51.000343 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 12:38:51.003387 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 12:38:51.010419 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 12:38:51.013594 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 12:38:51.016829 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 12:38:51.023640 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 12:38:51.026968 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 12:38:51.030171 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 12:38:51.037067 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 12:38:51.040178 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 12:38:51.043732 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 12:38:51.050521 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 12:38:51.053776 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1584 12:38:51.057057 Total UI for P1: 0, mck2ui 16
1585 12:38:51.060326 best dqsien dly found for B0: ( 0, 14, 6)
1586 12:38:51.063775 Total UI for P1: 0, mck2ui 16
1587 12:38:51.066979 best dqsien dly found for B1: ( 0, 14, 6)
1588 12:38:51.070308 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1589 12:38:51.073533 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1590 12:38:51.073617
1591 12:38:51.076956 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1592 12:38:51.080228 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1593 12:38:51.083598 [Gating] SW calibration Done
1594 12:38:51.083681 ==
1595 12:38:51.087194 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 12:38:51.090434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 12:38:51.090518 ==
1598 12:38:51.093793 RX Vref Scan: 0
1599 12:38:51.093877
1600 12:38:51.093942 RX Vref 0 -> 0, step: 1
1601 12:38:51.094003
1602 12:38:51.097037 RX Delay -130 -> 252, step: 16
1603 12:38:51.103711 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1604 12:38:51.107010 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1605 12:38:51.110475 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1606 12:38:51.113693 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1607 12:38:51.117310 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1608 12:38:51.120486 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1609 12:38:51.127316 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1610 12:38:51.130629 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1611 12:38:51.133793 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1612 12:38:51.136935 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1613 12:38:51.140308 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1614 12:38:51.147173 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1615 12:38:51.150475 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1616 12:38:51.153885 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1617 12:38:51.157110 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1618 12:38:51.163842 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1619 12:38:51.163940 ==
1620 12:38:51.166966 Dram Type= 6, Freq= 0, CH_1, rank 0
1621 12:38:51.170187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1622 12:38:51.170271 ==
1623 12:38:51.170337 DQS Delay:
1624 12:38:51.173388 DQS0 = 0, DQS1 = 0
1625 12:38:51.173471 DQM Delay:
1626 12:38:51.176932 DQM0 = 79, DQM1 = 70
1627 12:38:51.177015 DQ Delay:
1628 12:38:51.180234 DQ0 =77, DQ1 =77, DQ2 =61, DQ3 =77
1629 12:38:51.183487 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1630 12:38:51.187044 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1631 12:38:51.190188 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1632 12:38:51.190272
1633 12:38:51.190337
1634 12:38:51.190397 ==
1635 12:38:51.193658 Dram Type= 6, Freq= 0, CH_1, rank 0
1636 12:38:51.197030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1637 12:38:51.197114 ==
1638 12:38:51.197179
1639 12:38:51.197239
1640 12:38:51.200365 TX Vref Scan disable
1641 12:38:51.203545 == TX Byte 0 ==
1642 12:38:51.207010 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1643 12:38:51.210723 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1644 12:38:51.213923 == TX Byte 1 ==
1645 12:38:51.216941 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1646 12:38:51.220463 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1647 12:38:51.220547 ==
1648 12:38:51.223649 Dram Type= 6, Freq= 0, CH_1, rank 0
1649 12:38:51.226931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1650 12:38:51.230114 ==
1651 12:38:51.241679 TX Vref=22, minBit 0, minWin=27, winSum=439
1652 12:38:51.245405 TX Vref=24, minBit 1, minWin=27, winSum=442
1653 12:38:51.248616 TX Vref=26, minBit 1, minWin=27, winSum=446
1654 12:38:51.251965 TX Vref=28, minBit 8, minWin=27, winSum=450
1655 12:38:51.255254 TX Vref=30, minBit 5, minWin=27, winSum=450
1656 12:38:51.258596 TX Vref=32, minBit 6, minWin=27, winSum=448
1657 12:38:51.265083 [TxChooseVref] Worse bit 8, Min win 27, Win sum 450, Final Vref 28
1658 12:38:51.265168
1659 12:38:51.268544 Final TX Range 1 Vref 28
1660 12:38:51.268628
1661 12:38:51.268694 ==
1662 12:38:51.271733 Dram Type= 6, Freq= 0, CH_1, rank 0
1663 12:38:51.275221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1664 12:38:51.275305 ==
1665 12:38:51.275372
1666 12:38:51.278404
1667 12:38:51.278487 TX Vref Scan disable
1668 12:38:51.282132 == TX Byte 0 ==
1669 12:38:51.286088 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1670 12:38:51.289450 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1671 12:38:51.292638 == TX Byte 1 ==
1672 12:38:51.295854 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1673 12:38:51.299387 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1674 12:38:51.299470
1675 12:38:51.302739 [DATLAT]
1676 12:38:51.302822 Freq=800, CH1 RK0
1677 12:38:51.302887
1678 12:38:51.306138 DATLAT Default: 0xa
1679 12:38:51.306221 0, 0xFFFF, sum = 0
1680 12:38:51.309444 1, 0xFFFF, sum = 0
1681 12:38:51.309569 2, 0xFFFF, sum = 0
1682 12:38:51.312731 3, 0xFFFF, sum = 0
1683 12:38:51.312816 4, 0xFFFF, sum = 0
1684 12:38:51.316067 5, 0xFFFF, sum = 0
1685 12:38:51.316156 6, 0xFFFF, sum = 0
1686 12:38:51.319437 7, 0xFFFF, sum = 0
1687 12:38:51.319522 8, 0xFFFF, sum = 0
1688 12:38:51.322930 9, 0x0, sum = 1
1689 12:38:51.323019 10, 0x0, sum = 2
1690 12:38:51.326172 11, 0x0, sum = 3
1691 12:38:51.326257 12, 0x0, sum = 4
1692 12:38:51.329418 best_step = 10
1693 12:38:51.329540
1694 12:38:51.329607 ==
1695 12:38:51.332585 Dram Type= 6, Freq= 0, CH_1, rank 0
1696 12:38:51.336190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1697 12:38:51.336275 ==
1698 12:38:51.336341 RX Vref Scan: 1
1699 12:38:51.336403
1700 12:38:51.339235 Set Vref Range= 32 -> 127
1701 12:38:51.339318
1702 12:38:51.342630 RX Vref 32 -> 127, step: 1
1703 12:38:51.342713
1704 12:38:51.345892 RX Delay -111 -> 252, step: 8
1705 12:38:51.345988
1706 12:38:51.349164 Set Vref, RX VrefLevel [Byte0]: 32
1707 12:38:51.352807 [Byte1]: 32
1708 12:38:51.352891
1709 12:38:51.356036 Set Vref, RX VrefLevel [Byte0]: 33
1710 12:38:51.359274 [Byte1]: 33
1711 12:38:51.359358
1712 12:38:51.362780 Set Vref, RX VrefLevel [Byte0]: 34
1713 12:38:51.365802 [Byte1]: 34
1714 12:38:51.370150
1715 12:38:51.370233 Set Vref, RX VrefLevel [Byte0]: 35
1716 12:38:51.373420 [Byte1]: 35
1717 12:38:51.377622
1718 12:38:51.377705 Set Vref, RX VrefLevel [Byte0]: 36
1719 12:38:51.380866 [Byte1]: 36
1720 12:38:51.385347
1721 12:38:51.385430 Set Vref, RX VrefLevel [Byte0]: 37
1722 12:38:51.388555 [Byte1]: 37
1723 12:38:51.392788
1724 12:38:51.392871 Set Vref, RX VrefLevel [Byte0]: 38
1725 12:38:51.396383 [Byte1]: 38
1726 12:38:51.400481
1727 12:38:51.400564 Set Vref, RX VrefLevel [Byte0]: 39
1728 12:38:51.403767 [Byte1]: 39
1729 12:38:51.408043
1730 12:38:51.408126 Set Vref, RX VrefLevel [Byte0]: 40
1731 12:38:51.411384 [Byte1]: 40
1732 12:38:51.415727
1733 12:38:51.415810 Set Vref, RX VrefLevel [Byte0]: 41
1734 12:38:51.419403 [Byte1]: 41
1735 12:38:51.423408
1736 12:38:51.423492 Set Vref, RX VrefLevel [Byte0]: 42
1737 12:38:51.426968 [Byte1]: 42
1738 12:38:51.431012
1739 12:38:51.431095 Set Vref, RX VrefLevel [Byte0]: 43
1740 12:38:51.434297 [Byte1]: 43
1741 12:38:51.438777
1742 12:38:51.438860 Set Vref, RX VrefLevel [Byte0]: 44
1743 12:38:51.442304 [Byte1]: 44
1744 12:38:51.446475
1745 12:38:51.446558 Set Vref, RX VrefLevel [Byte0]: 45
1746 12:38:51.449992 [Byte1]: 45
1747 12:38:51.454041
1748 12:38:51.454124 Set Vref, RX VrefLevel [Byte0]: 46
1749 12:38:51.457370 [Byte1]: 46
1750 12:38:51.461918
1751 12:38:51.462001 Set Vref, RX VrefLevel [Byte0]: 47
1752 12:38:51.465131 [Byte1]: 47
1753 12:38:51.469595
1754 12:38:51.469678 Set Vref, RX VrefLevel [Byte0]: 48
1755 12:38:51.472814 [Byte1]: 48
1756 12:38:51.477055
1757 12:38:51.477138 Set Vref, RX VrefLevel [Byte0]: 49
1758 12:38:51.480248 [Byte1]: 49
1759 12:38:51.484615
1760 12:38:51.484699 Set Vref, RX VrefLevel [Byte0]: 50
1761 12:38:51.487839 [Byte1]: 50
1762 12:38:51.492308
1763 12:38:51.492391 Set Vref, RX VrefLevel [Byte0]: 51
1764 12:38:51.495665 [Byte1]: 51
1765 12:38:51.499894
1766 12:38:51.499977 Set Vref, RX VrefLevel [Byte0]: 52
1767 12:38:51.503307 [Byte1]: 52
1768 12:38:51.507688
1769 12:38:51.507771 Set Vref, RX VrefLevel [Byte0]: 53
1770 12:38:51.510918 [Byte1]: 53
1771 12:38:51.515324
1772 12:38:51.515407 Set Vref, RX VrefLevel [Byte0]: 54
1773 12:38:51.518713 [Byte1]: 54
1774 12:38:51.523004
1775 12:38:51.523087 Set Vref, RX VrefLevel [Byte0]: 55
1776 12:38:51.526066 [Byte1]: 55
1777 12:38:51.530639
1778 12:38:51.530722 Set Vref, RX VrefLevel [Byte0]: 56
1779 12:38:51.534036 [Byte1]: 56
1780 12:38:51.538125
1781 12:38:51.538208 Set Vref, RX VrefLevel [Byte0]: 57
1782 12:38:51.541392 [Byte1]: 57
1783 12:38:51.545795
1784 12:38:51.545901 Set Vref, RX VrefLevel [Byte0]: 58
1785 12:38:51.549240 [Byte1]: 58
1786 12:38:51.553579
1787 12:38:51.553662 Set Vref, RX VrefLevel [Byte0]: 59
1788 12:38:51.556805 [Byte1]: 59
1789 12:38:51.561326
1790 12:38:51.561409 Set Vref, RX VrefLevel [Byte0]: 60
1791 12:38:51.564625 [Byte1]: 60
1792 12:38:51.568979
1793 12:38:51.569062 Set Vref, RX VrefLevel [Byte0]: 61
1794 12:38:51.572175 [Byte1]: 61
1795 12:38:51.576576
1796 12:38:51.576659 Set Vref, RX VrefLevel [Byte0]: 62
1797 12:38:51.579836 [Byte1]: 62
1798 12:38:51.584134
1799 12:38:51.584217 Set Vref, RX VrefLevel [Byte0]: 63
1800 12:38:51.587536 [Byte1]: 63
1801 12:38:51.591899
1802 12:38:51.591982 Set Vref, RX VrefLevel [Byte0]: 64
1803 12:38:51.595172 [Byte1]: 64
1804 12:38:51.599596
1805 12:38:51.599679 Set Vref, RX VrefLevel [Byte0]: 65
1806 12:38:51.602737 [Byte1]: 65
1807 12:38:51.607216
1808 12:38:51.607330 Set Vref, RX VrefLevel [Byte0]: 66
1809 12:38:51.610549 [Byte1]: 66
1810 12:38:51.614565
1811 12:38:51.614648 Set Vref, RX VrefLevel [Byte0]: 67
1812 12:38:51.617985 [Byte1]: 67
1813 12:38:51.622144
1814 12:38:51.622220 Set Vref, RX VrefLevel [Byte0]: 68
1815 12:38:51.625473 [Byte1]: 68
1816 12:38:51.630064
1817 12:38:51.630135 Set Vref, RX VrefLevel [Byte0]: 69
1818 12:38:51.633098 [Byte1]: 69
1819 12:38:51.637451
1820 12:38:51.637600 Set Vref, RX VrefLevel [Byte0]: 70
1821 12:38:51.641078 [Byte1]: 70
1822 12:38:51.645069
1823 12:38:51.645141 Set Vref, RX VrefLevel [Byte0]: 71
1824 12:38:51.648347 [Byte1]: 71
1825 12:38:51.652768
1826 12:38:51.652838 Set Vref, RX VrefLevel [Byte0]: 72
1827 12:38:51.656358 [Byte1]: 72
1828 12:38:51.660350
1829 12:38:51.660421 Set Vref, RX VrefLevel [Byte0]: 73
1830 12:38:51.663840 [Byte1]: 73
1831 12:38:51.668285
1832 12:38:51.668370 Set Vref, RX VrefLevel [Byte0]: 74
1833 12:38:51.671697 [Byte1]: 74
1834 12:38:51.675726
1835 12:38:51.675809 Set Vref, RX VrefLevel [Byte0]: 75
1836 12:38:51.679050 [Byte1]: 75
1837 12:38:51.683557
1838 12:38:51.683641 Final RX Vref Byte 0 = 61 to rank0
1839 12:38:51.686827 Final RX Vref Byte 1 = 54 to rank0
1840 12:38:51.690106 Final RX Vref Byte 0 = 61 to rank1
1841 12:38:51.693665 Final RX Vref Byte 1 = 54 to rank1==
1842 12:38:51.696752 Dram Type= 6, Freq= 0, CH_1, rank 0
1843 12:38:51.703262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1844 12:38:51.703369 ==
1845 12:38:51.703438 DQS Delay:
1846 12:38:51.706654 DQS0 = 0, DQS1 = 0
1847 12:38:51.706738 DQM Delay:
1848 12:38:51.706804 DQM0 = 81, DQM1 = 71
1849 12:38:51.709829 DQ Delay:
1850 12:38:51.713389 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1851 12:38:51.716498 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1852 12:38:51.719672 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1853 12:38:51.723130 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1854 12:38:51.723214
1855 12:38:51.723280
1856 12:38:51.729835 [DQSOSCAuto] RK0, (LSB)MR18= 0x1721, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
1857 12:38:51.733257 CH1 RK0: MR19=606, MR18=1721
1858 12:38:51.739585 CH1_RK0: MR19=0x606, MR18=0x1721, DQSOSC=401, MR23=63, INC=91, DEC=61
1859 12:38:51.739669
1860 12:38:51.743332 ----->DramcWriteLeveling(PI) begin...
1861 12:38:51.743417 ==
1862 12:38:51.746304 Dram Type= 6, Freq= 0, CH_1, rank 1
1863 12:38:51.749909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1864 12:38:51.749994 ==
1865 12:38:51.753297 Write leveling (Byte 0): 28 => 28
1866 12:38:51.756489 Write leveling (Byte 1): 29 => 29
1867 12:38:51.759668 DramcWriteLeveling(PI) end<-----
1868 12:38:51.759752
1869 12:38:51.759817 ==
1870 12:38:51.763261 Dram Type= 6, Freq= 0, CH_1, rank 1
1871 12:38:51.766613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1872 12:38:51.766696 ==
1873 12:38:51.769735 [Gating] SW mode calibration
1874 12:38:51.776439 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1875 12:38:51.782871 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1876 12:38:51.786147 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1877 12:38:51.789751 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1878 12:38:51.796346 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 12:38:51.799463 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 12:38:51.802759 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 12:38:51.809552 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 12:38:51.812832 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 12:38:51.816099 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 12:38:51.822913 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 12:38:51.826086 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 12:38:51.829346 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 12:38:51.836166 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 12:38:51.839403 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 12:38:51.842631 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 12:38:51.849543 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 12:38:51.852920 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1892 12:38:51.856286 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 12:38:51.862646 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1894 12:38:51.866207 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 12:38:51.869314 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 12:38:51.876161 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 12:38:51.879439 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 12:38:51.883159 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 12:38:51.889478 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 12:38:51.892891 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 12:38:51.896175 0 9 4 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
1902 12:38:51.899512 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1903 12:38:51.906136 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 12:38:51.909408 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 12:38:51.913095 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1906 12:38:51.919637 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1907 12:38:51.922839 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 12:38:51.926171 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
1909 12:38:51.932842 0 10 4 | B1->B0 | 3131 2e2e | 0 0 | (0 1) (0 1)
1910 12:38:51.936087 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1911 12:38:51.939721 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 12:38:51.946538 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 12:38:51.949544 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 12:38:51.953086 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 12:38:51.959580 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 12:38:51.962958 0 11 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1917 12:38:51.966358 0 11 4 | B1->B0 | 2c2c 3939 | 0 1 | (0 0) (0 0)
1918 12:38:51.972994 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1919 12:38:51.976189 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 12:38:51.979731 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 12:38:51.982995 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 12:38:51.989855 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 12:38:51.992974 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 12:38:51.996263 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1925 12:38:52.003031 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1926 12:38:52.006286 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1927 12:38:52.009514 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 12:38:52.016206 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 12:38:52.019748 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 12:38:52.022873 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 12:38:52.029736 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 12:38:52.033014 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 12:38:52.036588 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 12:38:52.043075 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 12:38:52.046344 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 12:38:52.049534 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 12:38:52.056313 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 12:38:52.059765 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 12:38:52.062879 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 12:38:52.066539 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 12:38:52.073076 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1942 12:38:52.076426 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1943 12:38:52.079747 Total UI for P1: 0, mck2ui 16
1944 12:38:52.083088 best dqsien dly found for B0: ( 0, 14, 4)
1945 12:38:52.086488 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1946 12:38:52.089809 Total UI for P1: 0, mck2ui 16
1947 12:38:52.093024 best dqsien dly found for B1: ( 0, 14, 8)
1948 12:38:52.096294 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1949 12:38:52.099690 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1950 12:38:52.103156
1951 12:38:52.106474 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1952 12:38:52.109568 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1953 12:38:52.112971 [Gating] SW calibration Done
1954 12:38:52.113055 ==
1955 12:38:52.116463 Dram Type= 6, Freq= 0, CH_1, rank 1
1956 12:38:52.119801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1957 12:38:52.119886 ==
1958 12:38:52.119953 RX Vref Scan: 0
1959 12:38:52.120015
1960 12:38:52.122878 RX Vref 0 -> 0, step: 1
1961 12:38:52.122961
1962 12:38:52.126392 RX Delay -130 -> 252, step: 16
1963 12:38:52.129588 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1964 12:38:52.132687 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1965 12:38:52.139482 iDelay=206, Bit 2, Center 61 (-66 ~ 189) 256
1966 12:38:52.142656 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1967 12:38:52.146382 iDelay=206, Bit 4, Center 69 (-50 ~ 189) 240
1968 12:38:52.149431 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1969 12:38:52.152903 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1970 12:38:52.159441 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1971 12:38:52.162804 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1972 12:38:52.166352 iDelay=206, Bit 9, Center 61 (-66 ~ 189) 256
1973 12:38:52.169562 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1974 12:38:52.172860 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1975 12:38:52.179704 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1976 12:38:52.182909 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1977 12:38:52.186102 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1978 12:38:52.189527 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1979 12:38:52.189603 ==
1980 12:38:52.192845 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 12:38:52.196215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 12:38:52.199312 ==
1983 12:38:52.199387 DQS Delay:
1984 12:38:52.199450 DQS0 = 0, DQS1 = 0
1985 12:38:52.202722 DQM Delay:
1986 12:38:52.202793 DQM0 = 75, DQM1 = 71
1987 12:38:52.206207 DQ Delay:
1988 12:38:52.209629 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =69
1989 12:38:52.209716 DQ4 =69, DQ5 =85, DQ6 =85, DQ7 =77
1990 12:38:52.212965 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1991 12:38:52.216001 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1992 12:38:52.219388
1993 12:38:52.219471
1994 12:38:52.219537 ==
1995 12:38:52.222646 Dram Type= 6, Freq= 0, CH_1, rank 1
1996 12:38:52.226192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1997 12:38:52.226276 ==
1998 12:38:52.226343
1999 12:38:52.226404
2000 12:38:52.229547 TX Vref Scan disable
2001 12:38:52.229632 == TX Byte 0 ==
2002 12:38:52.236279 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2003 12:38:52.239667 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2004 12:38:52.239751 == TX Byte 1 ==
2005 12:38:52.246240 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2006 12:38:52.249426 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2007 12:38:52.249548 ==
2008 12:38:52.252911 Dram Type= 6, Freq= 0, CH_1, rank 1
2009 12:38:52.256192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2010 12:38:52.256277 ==
2011 12:38:52.269452 TX Vref=22, minBit 6, minWin=27, winSum=449
2012 12:38:52.273093 TX Vref=24, minBit 6, minWin=27, winSum=455
2013 12:38:52.276388 TX Vref=26, minBit 1, minWin=28, winSum=458
2014 12:38:52.279650 TX Vref=28, minBit 1, minWin=28, winSum=462
2015 12:38:52.282733 TX Vref=30, minBit 0, minWin=28, winSum=460
2016 12:38:52.286152 TX Vref=32, minBit 5, minWin=27, winSum=457
2017 12:38:52.292678 [TxChooseVref] Worse bit 1, Min win 28, Win sum 462, Final Vref 28
2018 12:38:52.292762
2019 12:38:52.296392 Final TX Range 1 Vref 28
2020 12:38:52.296477
2021 12:38:52.296542 ==
2022 12:38:52.299484 Dram Type= 6, Freq= 0, CH_1, rank 1
2023 12:38:52.302992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2024 12:38:52.303076 ==
2025 12:38:52.303142
2026 12:38:52.306337
2027 12:38:52.306419 TX Vref Scan disable
2028 12:38:52.309308 == TX Byte 0 ==
2029 12:38:52.312670 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2030 12:38:52.316008 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2031 12:38:52.319312 == TX Byte 1 ==
2032 12:38:52.322945 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2033 12:38:52.326310 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2034 12:38:52.329518
2035 12:38:52.329601 [DATLAT]
2036 12:38:52.329667 Freq=800, CH1 RK1
2037 12:38:52.329730
2038 12:38:52.332717 DATLAT Default: 0xa
2039 12:38:52.332800 0, 0xFFFF, sum = 0
2040 12:38:52.336083 1, 0xFFFF, sum = 0
2041 12:38:52.336168 2, 0xFFFF, sum = 0
2042 12:38:52.339662 3, 0xFFFF, sum = 0
2043 12:38:52.339748 4, 0xFFFF, sum = 0
2044 12:38:52.342804 5, 0xFFFF, sum = 0
2045 12:38:52.342889 6, 0xFFFF, sum = 0
2046 12:38:52.346403 7, 0xFFFF, sum = 0
2047 12:38:52.349662 8, 0xFFFF, sum = 0
2048 12:38:52.349747 9, 0x0, sum = 1
2049 12:38:52.349814 10, 0x0, sum = 2
2050 12:38:52.352965 11, 0x0, sum = 3
2051 12:38:52.353048 12, 0x0, sum = 4
2052 12:38:52.356181 best_step = 10
2053 12:38:52.356265
2054 12:38:52.356330 ==
2055 12:38:52.359369 Dram Type= 6, Freq= 0, CH_1, rank 1
2056 12:38:52.362732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2057 12:38:52.362820 ==
2058 12:38:52.366313 RX Vref Scan: 0
2059 12:38:52.366397
2060 12:38:52.366462 RX Vref 0 -> 0, step: 1
2061 12:38:52.366524
2062 12:38:52.369625 RX Delay -111 -> 252, step: 8
2063 12:38:52.376091 iDelay=209, Bit 0, Center 84 (-39 ~ 208) 248
2064 12:38:52.379628 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2065 12:38:52.382856 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2066 12:38:52.386095 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2067 12:38:52.389657 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2068 12:38:52.396443 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2069 12:38:52.399621 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2070 12:38:52.402865 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2071 12:38:52.406464 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2072 12:38:52.409640 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2073 12:38:52.416506 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2074 12:38:52.419619 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2075 12:38:52.422998 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2076 12:38:52.426118 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2077 12:38:52.429425 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2078 12:38:52.436140 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2079 12:38:52.436245 ==
2080 12:38:52.439523 Dram Type= 6, Freq= 0, CH_1, rank 1
2081 12:38:52.442731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2082 12:38:52.442841 ==
2083 12:38:52.442935 DQS Delay:
2084 12:38:52.446326 DQS0 = 0, DQS1 = 0
2085 12:38:52.446426 DQM Delay:
2086 12:38:52.449504 DQM0 = 78, DQM1 = 74
2087 12:38:52.449604 DQ Delay:
2088 12:38:52.452816 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =72
2089 12:38:52.456107 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2090 12:38:52.459319 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2091 12:38:52.462995 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
2092 12:38:52.463079
2093 12:38:52.463145
2094 12:38:52.469432 [DQSOSCAuto] RK1, (LSB)MR18= 0x253d, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
2095 12:38:52.472838 CH1 RK1: MR19=606, MR18=253D
2096 12:38:52.479400 CH1_RK1: MR19=0x606, MR18=0x253D, DQSOSC=394, MR23=63, INC=95, DEC=63
2097 12:38:52.482917 [RxdqsGatingPostProcess] freq 800
2098 12:38:52.489500 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2099 12:38:52.493007 Pre-setting of DQS Precalculation
2100 12:38:52.496301 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2101 12:38:52.502708 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2102 12:38:52.509649 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2103 12:38:52.509737
2104 12:38:52.509802
2105 12:38:52.512821 [Calibration Summary] 1600 Mbps
2106 12:38:52.516273 CH 0, Rank 0
2107 12:38:52.516357 SW Impedance : PASS
2108 12:38:52.519460 DUTY Scan : NO K
2109 12:38:52.522696 ZQ Calibration : PASS
2110 12:38:52.522781 Jitter Meter : NO K
2111 12:38:52.525996 CBT Training : PASS
2112 12:38:52.529657 Write leveling : PASS
2113 12:38:52.529740 RX DQS gating : PASS
2114 12:38:52.532914 RX DQ/DQS(RDDQC) : PASS
2115 12:38:52.532997 TX DQ/DQS : PASS
2116 12:38:52.536370 RX DATLAT : PASS
2117 12:38:52.539322 RX DQ/DQS(Engine): PASS
2118 12:38:52.539405 TX OE : NO K
2119 12:38:52.542658 All Pass.
2120 12:38:52.542741
2121 12:38:52.542806 CH 0, Rank 1
2122 12:38:52.546056 SW Impedance : PASS
2123 12:38:52.546140 DUTY Scan : NO K
2124 12:38:52.549456 ZQ Calibration : PASS
2125 12:38:52.552672 Jitter Meter : NO K
2126 12:38:52.552755 CBT Training : PASS
2127 12:38:52.556456 Write leveling : PASS
2128 12:38:52.559448 RX DQS gating : PASS
2129 12:38:52.559531 RX DQ/DQS(RDDQC) : PASS
2130 12:38:52.562900 TX DQ/DQS : PASS
2131 12:38:52.566077 RX DATLAT : PASS
2132 12:38:52.566160 RX DQ/DQS(Engine): PASS
2133 12:38:52.569392 TX OE : NO K
2134 12:38:52.569482 All Pass.
2135 12:38:52.569584
2136 12:38:52.572579 CH 1, Rank 0
2137 12:38:52.572663 SW Impedance : PASS
2138 12:38:52.575953 DUTY Scan : NO K
2139 12:38:52.579357 ZQ Calibration : PASS
2140 12:38:52.579440 Jitter Meter : NO K
2141 12:38:52.582711 CBT Training : PASS
2142 12:38:52.585929 Write leveling : PASS
2143 12:38:52.586032 RX DQS gating : PASS
2144 12:38:52.589214 RX DQ/DQS(RDDQC) : PASS
2145 12:38:52.589317 TX DQ/DQS : PASS
2146 12:38:52.592723 RX DATLAT : PASS
2147 12:38:52.595797 RX DQ/DQS(Engine): PASS
2148 12:38:52.595873 TX OE : NO K
2149 12:38:52.599411 All Pass.
2150 12:38:52.599489
2151 12:38:52.599566 CH 1, Rank 1
2152 12:38:52.602728 SW Impedance : PASS
2153 12:38:52.602808 DUTY Scan : NO K
2154 12:38:52.605978 ZQ Calibration : PASS
2155 12:38:52.609299 Jitter Meter : NO K
2156 12:38:52.609398 CBT Training : PASS
2157 12:38:52.612579 Write leveling : PASS
2158 12:38:52.615710 RX DQS gating : PASS
2159 12:38:52.615811 RX DQ/DQS(RDDQC) : PASS
2160 12:38:52.619382 TX DQ/DQS : PASS
2161 12:38:52.622395 RX DATLAT : PASS
2162 12:38:52.622501 RX DQ/DQS(Engine): PASS
2163 12:38:52.625999 TX OE : NO K
2164 12:38:52.626101 All Pass.
2165 12:38:52.626193
2166 12:38:52.629235 DramC Write-DBI off
2167 12:38:52.632606 PER_BANK_REFRESH: Hybrid Mode
2168 12:38:52.632704 TX_TRACKING: ON
2169 12:38:52.635846 [GetDramInforAfterCalByMRR] Vendor 6.
2170 12:38:52.639357 [GetDramInforAfterCalByMRR] Revision 606.
2171 12:38:52.642509 [GetDramInforAfterCalByMRR] Revision 2 0.
2172 12:38:52.645666 MR0 0x3b3b
2173 12:38:52.645768 MR8 0x5151
2174 12:38:52.649139 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2175 12:38:52.649239
2176 12:38:52.649331 MR0 0x3b3b
2177 12:38:52.652391 MR8 0x5151
2178 12:38:52.656006 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2179 12:38:52.656104
2180 12:38:52.662805 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2181 12:38:52.669357 [FAST_K] Save calibration result to emmc
2182 12:38:52.672834 [FAST_K] Save calibration result to emmc
2183 12:38:52.672939 dram_init: config_dvfs: 1
2184 12:38:52.676009 dramc_set_vcore_voltage set vcore to 662500
2185 12:38:52.679314 Read voltage for 1200, 2
2186 12:38:52.679410 Vio18 = 0
2187 12:38:52.682621 Vcore = 662500
2188 12:38:52.682720 Vdram = 0
2189 12:38:52.682810 Vddq = 0
2190 12:38:52.685897 Vmddr = 0
2191 12:38:52.689116 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2192 12:38:52.696035 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2193 12:38:52.696140 MEM_TYPE=3, freq_sel=15
2194 12:38:52.699083 sv_algorithm_assistance_LP4_1600
2195 12:38:52.705962 ============ PULL DRAM RESETB DOWN ============
2196 12:38:52.709142 ========== PULL DRAM RESETB DOWN end =========
2197 12:38:52.712500 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2198 12:38:52.716120 ===================================
2199 12:38:52.719329 LPDDR4 DRAM CONFIGURATION
2200 12:38:52.722503 ===================================
2201 12:38:52.726028 EX_ROW_EN[0] = 0x0
2202 12:38:52.726134 EX_ROW_EN[1] = 0x0
2203 12:38:52.729311 LP4Y_EN = 0x0
2204 12:38:52.729417 WORK_FSP = 0x0
2205 12:38:52.732811 WL = 0x4
2206 12:38:52.732909 RL = 0x4
2207 12:38:52.736157 BL = 0x2
2208 12:38:52.736263 RPST = 0x0
2209 12:38:52.739395 RD_PRE = 0x0
2210 12:38:52.739495 WR_PRE = 0x1
2211 12:38:52.742648 WR_PST = 0x0
2212 12:38:52.742746 DBI_WR = 0x0
2213 12:38:52.745965 DBI_RD = 0x0
2214 12:38:52.746064 OTF = 0x1
2215 12:38:52.749435 ===================================
2216 12:38:52.752899 ===================================
2217 12:38:52.756262 ANA top config
2218 12:38:52.759467 ===================================
2219 12:38:52.759565 DLL_ASYNC_EN = 0
2220 12:38:52.762863 ALL_SLAVE_EN = 0
2221 12:38:52.766046 NEW_RANK_MODE = 1
2222 12:38:52.769318 DLL_IDLE_MODE = 1
2223 12:38:52.769421 LP45_APHY_COMB_EN = 1
2224 12:38:52.772537 TX_ODT_DIS = 1
2225 12:38:52.776113 NEW_8X_MODE = 1
2226 12:38:52.779266 ===================================
2227 12:38:52.782619 ===================================
2228 12:38:52.785816 data_rate = 2400
2229 12:38:52.789388 CKR = 1
2230 12:38:52.792831 DQ_P2S_RATIO = 8
2231 12:38:52.796250 ===================================
2232 12:38:52.796348 CA_P2S_RATIO = 8
2233 12:38:52.799261 DQ_CA_OPEN = 0
2234 12:38:52.802872 DQ_SEMI_OPEN = 0
2235 12:38:52.806111 CA_SEMI_OPEN = 0
2236 12:38:52.809330 CA_FULL_RATE = 0
2237 12:38:52.812850 DQ_CKDIV4_EN = 0
2238 12:38:52.812960 CA_CKDIV4_EN = 0
2239 12:38:52.815988 CA_PREDIV_EN = 0
2240 12:38:52.819621 PH8_DLY = 17
2241 12:38:52.822872 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2242 12:38:52.826160 DQ_AAMCK_DIV = 4
2243 12:38:52.829269 CA_AAMCK_DIV = 4
2244 12:38:52.829377 CA_ADMCK_DIV = 4
2245 12:38:52.832891 DQ_TRACK_CA_EN = 0
2246 12:38:52.836157 CA_PICK = 1200
2247 12:38:52.839393 CA_MCKIO = 1200
2248 12:38:52.842573 MCKIO_SEMI = 0
2249 12:38:52.845944 PLL_FREQ = 2366
2250 12:38:52.849467 DQ_UI_PI_RATIO = 32
2251 12:38:52.849606 CA_UI_PI_RATIO = 0
2252 12:38:52.852854 ===================================
2253 12:38:52.855966 ===================================
2254 12:38:52.859518 memory_type:LPDDR4
2255 12:38:52.862684 GP_NUM : 10
2256 12:38:52.862822 SRAM_EN : 1
2257 12:38:52.865942 MD32_EN : 0
2258 12:38:52.869388 ===================================
2259 12:38:52.872544 [ANA_INIT] >>>>>>>>>>>>>>
2260 12:38:52.876109 <<<<<< [CONFIGURE PHASE]: ANA_TX
2261 12:38:52.879474 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2262 12:38:52.882576 ===================================
2263 12:38:52.882685 data_rate = 2400,PCW = 0X5b00
2264 12:38:52.886021 ===================================
2265 12:38:52.889425 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2266 12:38:52.895968 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2267 12:38:52.902842 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2268 12:38:52.906000 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2269 12:38:52.909424 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2270 12:38:52.912680 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2271 12:38:52.916342 [ANA_INIT] flow start
2272 12:38:52.916444 [ANA_INIT] PLL >>>>>>>>
2273 12:38:52.919472 [ANA_INIT] PLL <<<<<<<<
2274 12:38:52.922733 [ANA_INIT] MIDPI >>>>>>>>
2275 12:38:52.922838 [ANA_INIT] MIDPI <<<<<<<<
2276 12:38:52.926251 [ANA_INIT] DLL >>>>>>>>
2277 12:38:52.929567 [ANA_INIT] DLL <<<<<<<<
2278 12:38:52.929643 [ANA_INIT] flow end
2279 12:38:52.936264 ============ LP4 DIFF to SE enter ============
2280 12:38:52.939580 ============ LP4 DIFF to SE exit ============
2281 12:38:52.942948 [ANA_INIT] <<<<<<<<<<<<<
2282 12:38:52.946094 [Flow] Enable top DCM control >>>>>
2283 12:38:52.949362 [Flow] Enable top DCM control <<<<<
2284 12:38:52.949467 Enable DLL master slave shuffle
2285 12:38:52.956258 ==============================================================
2286 12:38:52.959447 Gating Mode config
2287 12:38:52.963101 ==============================================================
2288 12:38:52.966037 Config description:
2289 12:38:52.976275 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2290 12:38:52.982847 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2291 12:38:52.986053 SELPH_MODE 0: By rank 1: By Phase
2292 12:38:52.992829 ==============================================================
2293 12:38:52.996296 GAT_TRACK_EN = 1
2294 12:38:52.999654 RX_GATING_MODE = 2
2295 12:38:53.002666 RX_GATING_TRACK_MODE = 2
2296 12:38:53.002769 SELPH_MODE = 1
2297 12:38:53.006018 PICG_EARLY_EN = 1
2298 12:38:53.009338 VALID_LAT_VALUE = 1
2299 12:38:53.016111 ==============================================================
2300 12:38:53.019191 Enter into Gating configuration >>>>
2301 12:38:53.022824 Exit from Gating configuration <<<<
2302 12:38:53.025960 Enter into DVFS_PRE_config >>>>>
2303 12:38:53.036211 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2304 12:38:53.039320 Exit from DVFS_PRE_config <<<<<
2305 12:38:53.042559 Enter into PICG configuration >>>>
2306 12:38:53.046231 Exit from PICG configuration <<<<
2307 12:38:53.049598 [RX_INPUT] configuration >>>>>
2308 12:38:53.052795 [RX_INPUT] configuration <<<<<
2309 12:38:53.056150 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2310 12:38:53.062423 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2311 12:38:53.069171 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2312 12:38:53.076262 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2313 12:38:53.079503 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2314 12:38:53.085934 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2315 12:38:53.089331 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2316 12:38:53.096073 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2317 12:38:53.099409 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2318 12:38:53.102818 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2319 12:38:53.106039 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2320 12:38:53.112754 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2321 12:38:53.116278 ===================================
2322 12:38:53.116389 LPDDR4 DRAM CONFIGURATION
2323 12:38:53.119587 ===================================
2324 12:38:53.122821 EX_ROW_EN[0] = 0x0
2325 12:38:53.126331 EX_ROW_EN[1] = 0x0
2326 12:38:53.126435 LP4Y_EN = 0x0
2327 12:38:53.129582 WORK_FSP = 0x0
2328 12:38:53.129684 WL = 0x4
2329 12:38:53.132707 RL = 0x4
2330 12:38:53.132801 BL = 0x2
2331 12:38:53.136282 RPST = 0x0
2332 12:38:53.136399 RD_PRE = 0x0
2333 12:38:53.139610 WR_PRE = 0x1
2334 12:38:53.139725 WR_PST = 0x0
2335 12:38:53.143000 DBI_WR = 0x0
2336 12:38:53.143111 DBI_RD = 0x0
2337 12:38:53.146357 OTF = 0x1
2338 12:38:53.149714 ===================================
2339 12:38:53.152880 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2340 12:38:53.156019 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2341 12:38:53.162821 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2342 12:38:53.166153 ===================================
2343 12:38:53.166226 LPDDR4 DRAM CONFIGURATION
2344 12:38:53.169355 ===================================
2345 12:38:53.172940 EX_ROW_EN[0] = 0x10
2346 12:38:53.173041 EX_ROW_EN[1] = 0x0
2347 12:38:53.176130 LP4Y_EN = 0x0
2348 12:38:53.176230 WORK_FSP = 0x0
2349 12:38:53.179315 WL = 0x4
2350 12:38:53.179416 RL = 0x4
2351 12:38:53.182936 BL = 0x2
2352 12:38:53.183034 RPST = 0x0
2353 12:38:53.186069 RD_PRE = 0x0
2354 12:38:53.189483 WR_PRE = 0x1
2355 12:38:53.189572 WR_PST = 0x0
2356 12:38:53.192728 DBI_WR = 0x0
2357 12:38:53.192829 DBI_RD = 0x0
2358 12:38:53.196044 OTF = 0x1
2359 12:38:53.199300 ===================================
2360 12:38:53.202869 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2361 12:38:53.206297 ==
2362 12:38:53.209272 Dram Type= 6, Freq= 0, CH_0, rank 0
2363 12:38:53.212941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2364 12:38:53.213050 ==
2365 12:38:53.216156 [Duty_Offset_Calibration]
2366 12:38:53.216265 B0:2 B1:0 CA:4
2367 12:38:53.216368
2368 12:38:53.219462 [DutyScan_Calibration_Flow] k_type=0
2369 12:38:53.228791
2370 12:38:53.228914 ==CLK 0==
2371 12:38:53.232291 Final CLK duty delay cell = 0
2372 12:38:53.235361 [0] MAX Duty = 5031%(X100), DQS PI = 12
2373 12:38:53.238829 [0] MIN Duty = 4907%(X100), DQS PI = 8
2374 12:38:53.238936 [0] AVG Duty = 4969%(X100)
2375 12:38:53.242208
2376 12:38:53.242279 CH0 CLK Duty spec in!! Max-Min= 124%
2377 12:38:53.248749 [DutyScan_Calibration_Flow] ====Done====
2378 12:38:53.248870
2379 12:38:53.252119 [DutyScan_Calibration_Flow] k_type=1
2380 12:38:53.267195
2381 12:38:53.267325 ==DQS 0 ==
2382 12:38:53.270549 Final DQS duty delay cell = 0
2383 12:38:53.274003 [0] MAX Duty = 5093%(X100), DQS PI = 28
2384 12:38:53.277221 [0] MIN Duty = 4907%(X100), DQS PI = 2
2385 12:38:53.277324 [0] AVG Duty = 5000%(X100)
2386 12:38:53.280353
2387 12:38:53.280452 ==DQS 1 ==
2388 12:38:53.283969 Final DQS duty delay cell = -4
2389 12:38:53.287185 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2390 12:38:53.290786 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2391 12:38:53.294065 [-4] AVG Duty = 4922%(X100)
2392 12:38:53.294171
2393 12:38:53.297286 CH0 DQS 0 Duty spec in!! Max-Min= 186%
2394 12:38:53.297386
2395 12:38:53.300663 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2396 12:38:53.304029 [DutyScan_Calibration_Flow] ====Done====
2397 12:38:53.304102
2398 12:38:53.307444 [DutyScan_Calibration_Flow] k_type=3
2399 12:38:53.324715
2400 12:38:53.324825 ==DQM 0 ==
2401 12:38:53.327916 Final DQM duty delay cell = 0
2402 12:38:53.331422 [0] MAX Duty = 5124%(X100), DQS PI = 28
2403 12:38:53.334618 [0] MIN Duty = 4876%(X100), DQS PI = 0
2404 12:38:53.334726 [0] AVG Duty = 5000%(X100)
2405 12:38:53.338104
2406 12:38:53.338204 ==DQM 1 ==
2407 12:38:53.341231 Final DQM duty delay cell = 4
2408 12:38:53.344680 [4] MAX Duty = 5124%(X100), DQS PI = 50
2409 12:38:53.347898 [4] MIN Duty = 5031%(X100), DQS PI = 12
2410 12:38:53.351057 [4] AVG Duty = 5077%(X100)
2411 12:38:53.351168
2412 12:38:53.354307 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2413 12:38:53.354385
2414 12:38:53.357944 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2415 12:38:53.360983 [DutyScan_Calibration_Flow] ====Done====
2416 12:38:53.361091
2417 12:38:53.364380 [DutyScan_Calibration_Flow] k_type=2
2418 12:38:53.379509
2419 12:38:53.379593 ==DQ 0 ==
2420 12:38:53.382675 Final DQ duty delay cell = -4
2421 12:38:53.385869 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2422 12:38:53.389220 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2423 12:38:53.392847 [-4] AVG Duty = 4969%(X100)
2424 12:38:53.392929
2425 12:38:53.392993 ==DQ 1 ==
2426 12:38:53.396137 Final DQ duty delay cell = -4
2427 12:38:53.399467 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2428 12:38:53.402747 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2429 12:38:53.405938 [-4] AVG Duty = 4938%(X100)
2430 12:38:53.406020
2431 12:38:53.409319 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2432 12:38:53.409402
2433 12:38:53.412555 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2434 12:38:53.415908 [DutyScan_Calibration_Flow] ====Done====
2435 12:38:53.415992 ==
2436 12:38:53.419342 Dram Type= 6, Freq= 0, CH_1, rank 0
2437 12:38:53.422527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2438 12:38:53.422626 ==
2439 12:38:53.425864 [Duty_Offset_Calibration]
2440 12:38:53.425976 B0:1 B1:-2 CA:0
2441 12:38:53.426067
2442 12:38:53.429423 [DutyScan_Calibration_Flow] k_type=0
2443 12:38:53.439811
2444 12:38:53.439893 ==CLK 0==
2445 12:38:53.443316 Final CLK duty delay cell = 0
2446 12:38:53.446424 [0] MAX Duty = 5031%(X100), DQS PI = 16
2447 12:38:53.450048 [0] MIN Duty = 4844%(X100), DQS PI = 58
2448 12:38:53.453326 [0] AVG Duty = 4937%(X100)
2449 12:38:53.453408
2450 12:38:53.456494 CH1 CLK Duty spec in!! Max-Min= 187%
2451 12:38:53.460086 [DutyScan_Calibration_Flow] ====Done====
2452 12:38:53.460169
2453 12:38:53.463314 [DutyScan_Calibration_Flow] k_type=1
2454 12:38:53.478391
2455 12:38:53.478474 ==DQS 0 ==
2456 12:38:53.481636 Final DQS duty delay cell = -4
2457 12:38:53.485127 [-4] MAX Duty = 5000%(X100), DQS PI = 16
2458 12:38:53.488365 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2459 12:38:53.491835 [-4] AVG Duty = 4953%(X100)
2460 12:38:53.491913
2461 12:38:53.491994 ==DQS 1 ==
2462 12:38:53.494931 Final DQS duty delay cell = 0
2463 12:38:53.498545 [0] MAX Duty = 5093%(X100), DQS PI = 0
2464 12:38:53.501682 [0] MIN Duty = 4875%(X100), DQS PI = 26
2465 12:38:53.505000 [0] AVG Duty = 4984%(X100)
2466 12:38:53.505083
2467 12:38:53.508353 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2468 12:38:53.508436
2469 12:38:53.511686 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2470 12:38:53.515282 [DutyScan_Calibration_Flow] ====Done====
2471 12:38:53.515364
2472 12:38:53.518286 [DutyScan_Calibration_Flow] k_type=3
2473 12:38:53.534813
2474 12:38:53.534899 ==DQM 0 ==
2475 12:38:53.538139 Final DQM duty delay cell = 0
2476 12:38:53.541675 [0] MAX Duty = 5000%(X100), DQS PI = 22
2477 12:38:53.544993 [0] MIN Duty = 4876%(X100), DQS PI = 4
2478 12:38:53.545070 [0] AVG Duty = 4938%(X100)
2479 12:38:53.548393
2480 12:38:53.548468 ==DQM 1 ==
2481 12:38:53.551936 Final DQM duty delay cell = 0
2482 12:38:53.555092 [0] MAX Duty = 5031%(X100), DQS PI = 34
2483 12:38:53.558344 [0] MIN Duty = 4907%(X100), DQS PI = 4
2484 12:38:53.558428 [0] AVG Duty = 4969%(X100)
2485 12:38:53.558493
2486 12:38:53.565326 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2487 12:38:53.565408
2488 12:38:53.568512 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2489 12:38:53.571716 [DutyScan_Calibration_Flow] ====Done====
2490 12:38:53.571813
2491 12:38:53.575263 [DutyScan_Calibration_Flow] k_type=2
2492 12:38:53.591299
2493 12:38:53.591408 ==DQ 0 ==
2494 12:38:53.594847 Final DQ duty delay cell = 0
2495 12:38:53.597974 [0] MAX Duty = 5062%(X100), DQS PI = 18
2496 12:38:53.601322 [0] MIN Duty = 4938%(X100), DQS PI = 54
2497 12:38:53.601405 [0] AVG Duty = 5000%(X100)
2498 12:38:53.601470
2499 12:38:53.604580 ==DQ 1 ==
2500 12:38:53.607945 Final DQ duty delay cell = 0
2501 12:38:53.611438 [0] MAX Duty = 5093%(X100), DQS PI = 20
2502 12:38:53.614780 [0] MIN Duty = 4969%(X100), DQS PI = 26
2503 12:38:53.614890 [0] AVG Duty = 5031%(X100)
2504 12:38:53.614971
2505 12:38:53.618273 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2506 12:38:53.618384
2507 12:38:53.621383 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2508 12:38:53.628167 [DutyScan_Calibration_Flow] ====Done====
2509 12:38:53.631568 nWR fixed to 30
2510 12:38:53.631651 [ModeRegInit_LP4] CH0 RK0
2511 12:38:53.634693 [ModeRegInit_LP4] CH0 RK1
2512 12:38:53.638008 [ModeRegInit_LP4] CH1 RK0
2513 12:38:53.638092 [ModeRegInit_LP4] CH1 RK1
2514 12:38:53.641374 match AC timing 7
2515 12:38:53.644467 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2516 12:38:53.648091 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2517 12:38:53.654762 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2518 12:38:53.658073 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2519 12:38:53.664542 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2520 12:38:53.664653 ==
2521 12:38:53.668177 Dram Type= 6, Freq= 0, CH_0, rank 0
2522 12:38:53.671412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2523 12:38:53.671495 ==
2524 12:38:53.677749 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2525 12:38:53.684149 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2526 12:38:53.691444 [CA 0] Center 40 (10~71) winsize 62
2527 12:38:53.694635 [CA 1] Center 39 (9~70) winsize 62
2528 12:38:53.698062 [CA 2] Center 36 (6~66) winsize 61
2529 12:38:53.701244 [CA 3] Center 35 (5~66) winsize 62
2530 12:38:53.704838 [CA 4] Center 34 (4~65) winsize 62
2531 12:38:53.708003 [CA 5] Center 33 (3~64) winsize 62
2532 12:38:53.708081
2533 12:38:53.711427 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2534 12:38:53.711527
2535 12:38:53.714895 [CATrainingPosCal] consider 1 rank data
2536 12:38:53.718092 u2DelayCellTimex100 = 270/100 ps
2537 12:38:53.721351 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2538 12:38:53.724667 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2539 12:38:53.731609 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2540 12:38:53.734809 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2541 12:38:53.738052 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2542 12:38:53.741570 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2543 12:38:53.741645
2544 12:38:53.744809 CA PerBit enable=1, Macro0, CA PI delay=33
2545 12:38:53.744887
2546 12:38:53.748043 [CBTSetCACLKResult] CA Dly = 33
2547 12:38:53.748122 CS Dly: 7 (0~38)
2548 12:38:53.751423 ==
2549 12:38:53.754616 Dram Type= 6, Freq= 0, CH_0, rank 1
2550 12:38:53.758123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2551 12:38:53.758207 ==
2552 12:38:53.761293 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2553 12:38:53.767963 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2554 12:38:53.777484 [CA 0] Center 40 (10~70) winsize 61
2555 12:38:53.780983 [CA 1] Center 39 (9~70) winsize 62
2556 12:38:53.784314 [CA 2] Center 35 (5~66) winsize 62
2557 12:38:53.787428 [CA 3] Center 35 (5~66) winsize 62
2558 12:38:53.790594 [CA 4] Center 34 (3~65) winsize 63
2559 12:38:53.794199 [CA 5] Center 33 (3~64) winsize 62
2560 12:38:53.794276
2561 12:38:53.797340 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2562 12:38:53.797413
2563 12:38:53.800687 [CATrainingPosCal] consider 2 rank data
2564 12:38:53.803958 u2DelayCellTimex100 = 270/100 ps
2565 12:38:53.807567 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2566 12:38:53.810769 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2567 12:38:53.817392 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2568 12:38:53.820947 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2569 12:38:53.824089 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2570 12:38:53.827455 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2571 12:38:53.827558
2572 12:38:53.831093 CA PerBit enable=1, Macro0, CA PI delay=33
2573 12:38:53.831169
2574 12:38:53.834211 [CBTSetCACLKResult] CA Dly = 33
2575 12:38:53.834286 CS Dly: 8 (0~40)
2576 12:38:53.834355
2577 12:38:53.837459 ----->DramcWriteLeveling(PI) begin...
2578 12:38:53.841058 ==
2579 12:38:53.844263 Dram Type= 6, Freq= 0, CH_0, rank 0
2580 12:38:53.847759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2581 12:38:53.847838 ==
2582 12:38:53.851000 Write leveling (Byte 0): 32 => 32
2583 12:38:53.854248 Write leveling (Byte 1): 31 => 31
2584 12:38:53.857622 DramcWriteLeveling(PI) end<-----
2585 12:38:53.857698
2586 12:38:53.857768 ==
2587 12:38:53.860803 Dram Type= 6, Freq= 0, CH_0, rank 0
2588 12:38:53.864114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2589 12:38:53.864190 ==
2590 12:38:53.867748 [Gating] SW mode calibration
2591 12:38:53.874449 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2592 12:38:53.877705 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2593 12:38:53.884311 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 12:38:53.887460 0 15 4 | B1->B0 | 2a2a 3434 | 1 0 | (1 1) (0 0)
2595 12:38:53.890817 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2596 12:38:53.897697 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2597 12:38:53.901166 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2598 12:38:53.904299 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2599 12:38:53.910980 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2600 12:38:53.914169 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2601 12:38:53.917809 1 0 0 | B1->B0 | 3131 2828 | 1 1 | (1 1) (1 0)
2602 12:38:53.924476 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2603 12:38:53.927743 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2604 12:38:53.931036 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2605 12:38:53.937576 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2606 12:38:53.940805 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2607 12:38:53.944419 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 12:38:53.950957 1 0 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2609 12:38:53.954311 1 1 0 | B1->B0 | 2424 3030 | 0 1 | (0 0) (0 0)
2610 12:38:53.957626 1 1 4 | B1->B0 | 3e3e 4545 | 1 0 | (0 0) (0 0)
2611 12:38:53.964307 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 12:38:53.967434 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 12:38:53.970894 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 12:38:53.974295 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 12:38:53.980875 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 12:38:53.984340 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 12:38:53.987752 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2618 12:38:53.994449 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2619 12:38:53.997766 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 12:38:54.001041 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 12:38:54.007839 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 12:38:54.011222 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 12:38:54.014417 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 12:38:54.021342 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 12:38:54.024447 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 12:38:54.027830 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 12:38:54.034672 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 12:38:54.037615 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 12:38:54.040893 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 12:38:54.047861 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 12:38:54.050915 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 12:38:54.054602 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 12:38:54.060831 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2634 12:38:54.060943 Total UI for P1: 0, mck2ui 16
2635 12:38:54.064464 best dqsien dly found for B0: ( 1, 3, 30)
2636 12:38:54.071060 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2637 12:38:54.074235 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2638 12:38:54.077581 Total UI for P1: 0, mck2ui 16
2639 12:38:54.080917 best dqsien dly found for B1: ( 1, 4, 2)
2640 12:38:54.084097 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2641 12:38:54.087652 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2642 12:38:54.087729
2643 12:38:54.091005 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2644 12:38:54.094159 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2645 12:38:54.097755 [Gating] SW calibration Done
2646 12:38:54.097834 ==
2647 12:38:54.100876 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 12:38:54.107335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 12:38:54.107416 ==
2650 12:38:54.107481 RX Vref Scan: 0
2651 12:38:54.107551
2652 12:38:54.110604 RX Vref 0 -> 0, step: 1
2653 12:38:54.110679
2654 12:38:54.114087 RX Delay -40 -> 252, step: 8
2655 12:38:54.117617 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2656 12:38:54.120720 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2657 12:38:54.123961 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2658 12:38:54.127608 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2659 12:38:54.134187 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2660 12:38:54.137417 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2661 12:38:54.140803 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2662 12:38:54.144154 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2663 12:38:54.147379 iDelay=200, Bit 8, Center 95 (16 ~ 175) 160
2664 12:38:54.150485 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2665 12:38:54.157375 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2666 12:38:54.160552 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2667 12:38:54.163889 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2668 12:38:54.167459 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2669 12:38:54.173892 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2670 12:38:54.177077 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2671 12:38:54.177152 ==
2672 12:38:54.180719 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 12:38:54.184037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 12:38:54.184112 ==
2675 12:38:54.187225 DQS Delay:
2676 12:38:54.187307 DQS0 = 0, DQS1 = 0
2677 12:38:54.187370 DQM Delay:
2678 12:38:54.190586 DQM0 = 113, DQM1 = 103
2679 12:38:54.190665 DQ Delay:
2680 12:38:54.193784 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2681 12:38:54.197121 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2682 12:38:54.200544 DQ8 =95, DQ9 =87, DQ10 =103, DQ11 =99
2683 12:38:54.203835 DQ12 =107, DQ13 =111, DQ14 =115, DQ15 =111
2684 12:38:54.203916
2685 12:38:54.207046
2686 12:38:54.207125 ==
2687 12:38:54.210560 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 12:38:54.213641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 12:38:54.213724 ==
2690 12:38:54.213788
2691 12:38:54.213859
2692 12:38:54.217231 TX Vref Scan disable
2693 12:38:54.217311 == TX Byte 0 ==
2694 12:38:54.223625 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2695 12:38:54.227111 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2696 12:38:54.227196 == TX Byte 1 ==
2697 12:38:54.233891 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2698 12:38:54.237345 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2699 12:38:54.237450 ==
2700 12:38:54.240592 Dram Type= 6, Freq= 0, CH_0, rank 0
2701 12:38:54.243810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2702 12:38:54.243890 ==
2703 12:38:54.255899 TX Vref=22, minBit 12, minWin=25, winSum=418
2704 12:38:54.259541 TX Vref=24, minBit 1, minWin=26, winSum=425
2705 12:38:54.262652 TX Vref=26, minBit 7, minWin=26, winSum=433
2706 12:38:54.266046 TX Vref=28, minBit 0, minWin=27, winSum=435
2707 12:38:54.269124 TX Vref=30, minBit 10, minWin=26, winSum=437
2708 12:38:54.275824 TX Vref=32, minBit 3, minWin=26, winSum=432
2709 12:38:54.279356 [TxChooseVref] Worse bit 0, Min win 27, Win sum 435, Final Vref 28
2710 12:38:54.279431
2711 12:38:54.282583 Final TX Range 1 Vref 28
2712 12:38:54.282661
2713 12:38:54.282726 ==
2714 12:38:54.285986 Dram Type= 6, Freq= 0, CH_0, rank 0
2715 12:38:54.289335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2716 12:38:54.289411 ==
2717 12:38:54.292509
2718 12:38:54.292582
2719 12:38:54.292643 TX Vref Scan disable
2720 12:38:54.296136 == TX Byte 0 ==
2721 12:38:54.299313 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2722 12:38:54.302727 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2723 12:38:54.306217 == TX Byte 1 ==
2724 12:38:54.309272 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2725 12:38:54.312892 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2726 12:38:54.312965
2727 12:38:54.315932 [DATLAT]
2728 12:38:54.316006 Freq=1200, CH0 RK0
2729 12:38:54.316068
2730 12:38:54.319406 DATLAT Default: 0xd
2731 12:38:54.319482 0, 0xFFFF, sum = 0
2732 12:38:54.322640 1, 0xFFFF, sum = 0
2733 12:38:54.322730 2, 0xFFFF, sum = 0
2734 12:38:54.325916 3, 0xFFFF, sum = 0
2735 12:38:54.325991 4, 0xFFFF, sum = 0
2736 12:38:54.329286 5, 0xFFFF, sum = 0
2737 12:38:54.329392 6, 0xFFFF, sum = 0
2738 12:38:54.332513 7, 0xFFFF, sum = 0
2739 12:38:54.336056 8, 0xFFFF, sum = 0
2740 12:38:54.336131 9, 0xFFFF, sum = 0
2741 12:38:54.339433 10, 0xFFFF, sum = 0
2742 12:38:54.339514 11, 0xFFFF, sum = 0
2743 12:38:54.342721 12, 0x0, sum = 1
2744 12:38:54.342799 13, 0x0, sum = 2
2745 12:38:54.342867 14, 0x0, sum = 3
2746 12:38:54.346228 15, 0x0, sum = 4
2747 12:38:54.346303 best_step = 13
2748 12:38:54.346370
2749 12:38:54.349551 ==
2750 12:38:54.349653 Dram Type= 6, Freq= 0, CH_0, rank 0
2751 12:38:54.356222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2752 12:38:54.356302 ==
2753 12:38:54.356378 RX Vref Scan: 1
2754 12:38:54.356440
2755 12:38:54.359383 Set Vref Range= 32 -> 127
2756 12:38:54.359459
2757 12:38:54.362622 RX Vref 32 -> 127, step: 1
2758 12:38:54.362696
2759 12:38:54.366267 RX Delay -37 -> 252, step: 4
2760 12:38:54.366339
2761 12:38:54.369296 Set Vref, RX VrefLevel [Byte0]: 32
2762 12:38:54.372807 [Byte1]: 32
2763 12:38:54.372883
2764 12:38:54.376098 Set Vref, RX VrefLevel [Byte0]: 33
2765 12:38:54.379338 [Byte1]: 33
2766 12:38:54.379421
2767 12:38:54.382661 Set Vref, RX VrefLevel [Byte0]: 34
2768 12:38:54.386329 [Byte1]: 34
2769 12:38:54.390333
2770 12:38:54.390409 Set Vref, RX VrefLevel [Byte0]: 35
2771 12:38:54.393670 [Byte1]: 35
2772 12:38:54.398540
2773 12:38:54.398615 Set Vref, RX VrefLevel [Byte0]: 36
2774 12:38:54.401728 [Byte1]: 36
2775 12:38:54.406363
2776 12:38:54.406442 Set Vref, RX VrefLevel [Byte0]: 37
2777 12:38:54.409606 [Byte1]: 37
2778 12:38:54.414393
2779 12:38:54.414468 Set Vref, RX VrefLevel [Byte0]: 38
2780 12:38:54.417668 [Byte1]: 38
2781 12:38:54.422404
2782 12:38:54.422515 Set Vref, RX VrefLevel [Byte0]: 39
2783 12:38:54.425645 [Byte1]: 39
2784 12:38:54.430428
2785 12:38:54.430513 Set Vref, RX VrefLevel [Byte0]: 40
2786 12:38:54.433672 [Byte1]: 40
2787 12:38:54.438292
2788 12:38:54.438367 Set Vref, RX VrefLevel [Byte0]: 41
2789 12:38:54.441631 [Byte1]: 41
2790 12:38:54.446508
2791 12:38:54.446610 Set Vref, RX VrefLevel [Byte0]: 42
2792 12:38:54.449589 [Byte1]: 42
2793 12:38:54.454497
2794 12:38:54.454597 Set Vref, RX VrefLevel [Byte0]: 43
2795 12:38:54.457636 [Byte1]: 43
2796 12:38:54.462494
2797 12:38:54.462585 Set Vref, RX VrefLevel [Byte0]: 44
2798 12:38:54.465730 [Byte1]: 44
2799 12:38:54.470328
2800 12:38:54.473867 Set Vref, RX VrefLevel [Byte0]: 45
2801 12:38:54.473953 [Byte1]: 45
2802 12:38:54.478429
2803 12:38:54.478541 Set Vref, RX VrefLevel [Byte0]: 46
2804 12:38:54.481726 [Byte1]: 46
2805 12:38:54.486390
2806 12:38:54.486467 Set Vref, RX VrefLevel [Byte0]: 47
2807 12:38:54.489951 [Byte1]: 47
2808 12:38:54.494282
2809 12:38:54.494380 Set Vref, RX VrefLevel [Byte0]: 48
2810 12:38:54.497869 [Byte1]: 48
2811 12:38:54.502359
2812 12:38:54.502460 Set Vref, RX VrefLevel [Byte0]: 49
2813 12:38:54.505915 [Byte1]: 49
2814 12:38:54.510640
2815 12:38:54.510710 Set Vref, RX VrefLevel [Byte0]: 50
2816 12:38:54.513760 [Byte1]: 50
2817 12:38:54.518639
2818 12:38:54.518735 Set Vref, RX VrefLevel [Byte0]: 51
2819 12:38:54.521819 [Byte1]: 51
2820 12:38:54.526437
2821 12:38:54.526541 Set Vref, RX VrefLevel [Byte0]: 52
2822 12:38:54.529595 [Byte1]: 52
2823 12:38:54.534423
2824 12:38:54.534522 Set Vref, RX VrefLevel [Byte0]: 53
2825 12:38:54.537854 [Byte1]: 53
2826 12:38:54.542299
2827 12:38:54.542398 Set Vref, RX VrefLevel [Byte0]: 54
2828 12:38:54.545580 [Byte1]: 54
2829 12:38:54.550296
2830 12:38:54.550394 Set Vref, RX VrefLevel [Byte0]: 55
2831 12:38:54.553649 [Byte1]: 55
2832 12:38:54.558628
2833 12:38:54.558724 Set Vref, RX VrefLevel [Byte0]: 56
2834 12:38:54.561579 [Byte1]: 56
2835 12:38:54.566554
2836 12:38:54.566629 Set Vref, RX VrefLevel [Byte0]: 57
2837 12:38:54.569768 [Byte1]: 57
2838 12:38:54.574312
2839 12:38:54.574387 Set Vref, RX VrefLevel [Byte0]: 58
2840 12:38:54.577598 [Byte1]: 58
2841 12:38:54.582541
2842 12:38:54.582625 Set Vref, RX VrefLevel [Byte0]: 59
2843 12:38:54.585666 [Byte1]: 59
2844 12:38:54.590313
2845 12:38:54.590386 Set Vref, RX VrefLevel [Byte0]: 60
2846 12:38:54.593671 [Byte1]: 60
2847 12:38:54.598563
2848 12:38:54.598639 Set Vref, RX VrefLevel [Byte0]: 61
2849 12:38:54.601607 [Byte1]: 61
2850 12:38:54.606601
2851 12:38:54.606676 Set Vref, RX VrefLevel [Byte0]: 62
2852 12:38:54.609561 [Byte1]: 62
2853 12:38:54.614293
2854 12:38:54.614367 Set Vref, RX VrefLevel [Byte0]: 63
2855 12:38:54.617786 [Byte1]: 63
2856 12:38:54.622317
2857 12:38:54.622403 Set Vref, RX VrefLevel [Byte0]: 64
2858 12:38:54.625644 [Byte1]: 64
2859 12:38:54.630479
2860 12:38:54.630551 Set Vref, RX VrefLevel [Byte0]: 65
2861 12:38:54.633751 [Byte1]: 65
2862 12:38:54.638367
2863 12:38:54.638438 Set Vref, RX VrefLevel [Byte0]: 66
2864 12:38:54.641795 [Byte1]: 66
2865 12:38:54.646268
2866 12:38:54.646344 Set Vref, RX VrefLevel [Byte0]: 67
2867 12:38:54.649825 [Byte1]: 67
2868 12:38:54.654585
2869 12:38:54.654654 Set Vref, RX VrefLevel [Byte0]: 68
2870 12:38:54.657821 [Byte1]: 68
2871 12:38:54.662317
2872 12:38:54.662386 Set Vref, RX VrefLevel [Byte0]: 69
2873 12:38:54.665651 [Byte1]: 69
2874 12:38:54.670467
2875 12:38:54.670548 Set Vref, RX VrefLevel [Byte0]: 70
2876 12:38:54.673709 [Byte1]: 70
2877 12:38:54.678296
2878 12:38:54.678370 Set Vref, RX VrefLevel [Byte0]: 71
2879 12:38:54.681902 [Byte1]: 71
2880 12:38:54.686492
2881 12:38:54.686574 Set Vref, RX VrefLevel [Byte0]: 72
2882 12:38:54.689653 [Byte1]: 72
2883 12:38:54.694508
2884 12:38:54.694588 Set Vref, RX VrefLevel [Byte0]: 73
2885 12:38:54.697670 [Byte1]: 73
2886 12:38:54.702389
2887 12:38:54.702469 Set Vref, RX VrefLevel [Byte0]: 74
2888 12:38:54.705602 [Byte1]: 74
2889 12:38:54.710460
2890 12:38:54.710543 Final RX Vref Byte 0 = 62 to rank0
2891 12:38:54.714036 Final RX Vref Byte 1 = 54 to rank0
2892 12:38:54.717238 Final RX Vref Byte 0 = 62 to rank1
2893 12:38:54.720480 Final RX Vref Byte 1 = 54 to rank1==
2894 12:38:54.723817 Dram Type= 6, Freq= 0, CH_0, rank 0
2895 12:38:54.730603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2896 12:38:54.730684 ==
2897 12:38:54.730761 DQS Delay:
2898 12:38:54.730823 DQS0 = 0, DQS1 = 0
2899 12:38:54.733899 DQM Delay:
2900 12:38:54.733981 DQM0 = 112, DQM1 = 101
2901 12:38:54.737128 DQ Delay:
2902 12:38:54.740370 DQ0 =110, DQ1 =112, DQ2 =114, DQ3 =106
2903 12:38:54.743885 DQ4 =114, DQ5 =104, DQ6 =118, DQ7 =120
2904 12:38:54.747361 DQ8 =92, DQ9 =86, DQ10 =104, DQ11 =94
2905 12:38:54.750560 DQ12 =106, DQ13 =106, DQ14 =116, DQ15 =110
2906 12:38:54.750643
2907 12:38:54.750707
2908 12:38:54.757413 [DQSOSCAuto] RK0, (LSB)MR18= 0xfcfc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
2909 12:38:54.760663 CH0 RK0: MR19=303, MR18=FCFC
2910 12:38:54.767145 CH0_RK0: MR19=0x303, MR18=0xFCFC, DQSOSC=411, MR23=63, INC=38, DEC=25
2911 12:38:54.767250
2912 12:38:54.770339 ----->DramcWriteLeveling(PI) begin...
2913 12:38:54.770420 ==
2914 12:38:54.773930 Dram Type= 6, Freq= 0, CH_0, rank 1
2915 12:38:54.777232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2916 12:38:54.777306 ==
2917 12:38:54.780371 Write leveling (Byte 0): 33 => 33
2918 12:38:54.783984 Write leveling (Byte 1): 31 => 31
2919 12:38:54.787119 DramcWriteLeveling(PI) end<-----
2920 12:38:54.787198
2921 12:38:54.787260 ==
2922 12:38:54.790387 Dram Type= 6, Freq= 0, CH_0, rank 1
2923 12:38:54.797335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2924 12:38:54.797440 ==
2925 12:38:54.797573 [Gating] SW mode calibration
2926 12:38:54.807035 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2927 12:38:54.810420 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2928 12:38:54.813632 0 15 0 | B1->B0 | 2727 3434 | 1 1 | (0 0) (1 1)
2929 12:38:54.820448 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2930 12:38:54.823841 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2931 12:38:54.827239 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2932 12:38:54.833597 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2933 12:38:54.837093 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2934 12:38:54.840473 0 15 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
2935 12:38:54.847295 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
2936 12:38:54.850276 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
2937 12:38:54.853779 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2938 12:38:54.860552 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2939 12:38:54.864011 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2940 12:38:54.867228 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2941 12:38:54.874012 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2942 12:38:54.877291 1 0 24 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
2943 12:38:54.880512 1 0 28 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
2944 12:38:54.883715 1 1 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2945 12:38:54.890442 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 12:38:54.893773 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2947 12:38:54.897339 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2948 12:38:54.903784 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2949 12:38:54.906986 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2950 12:38:54.910612 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2951 12:38:54.917244 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2952 12:38:54.920360 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2953 12:38:54.923981 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 12:38:54.930487 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 12:38:54.933941 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 12:38:54.937284 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 12:38:54.943757 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 12:38:54.947205 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 12:38:54.950585 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 12:38:54.957263 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 12:38:54.960356 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 12:38:54.963894 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 12:38:54.970278 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 12:38:54.973665 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2965 12:38:54.977075 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2966 12:38:54.983835 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2967 12:38:54.987075 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2968 12:38:54.990293 Total UI for P1: 0, mck2ui 16
2969 12:38:54.993961 best dqsien dly found for B0: ( 1, 3, 26)
2970 12:38:54.997222 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2971 12:38:55.000474 Total UI for P1: 0, mck2ui 16
2972 12:38:55.003816 best dqsien dly found for B1: ( 1, 3, 28)
2973 12:38:55.007304 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2974 12:38:55.010414 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2975 12:38:55.010488
2976 12:38:55.013757 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2977 12:38:55.017081 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2978 12:38:55.020344 [Gating] SW calibration Done
2979 12:38:55.020430 ==
2980 12:38:55.023863 Dram Type= 6, Freq= 0, CH_0, rank 1
2981 12:38:55.030740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2982 12:38:55.030864 ==
2983 12:38:55.030967 RX Vref Scan: 0
2984 12:38:55.031065
2985 12:38:55.033913 RX Vref 0 -> 0, step: 1
2986 12:38:55.034015
2987 12:38:55.037067 RX Delay -40 -> 252, step: 8
2988 12:38:55.040657 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2989 12:38:55.043666 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2990 12:38:55.047339 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2991 12:38:55.050352 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2992 12:38:55.056998 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
2993 12:38:55.060402 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2994 12:38:55.063627 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2995 12:38:55.067112 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2996 12:38:55.070386 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2997 12:38:55.073852 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2998 12:38:55.080631 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2999 12:38:55.083938 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
3000 12:38:55.087169 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3001 12:38:55.090780 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3002 12:38:55.097102 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3003 12:38:55.100651 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3004 12:38:55.100735 ==
3005 12:38:55.103951 Dram Type= 6, Freq= 0, CH_0, rank 1
3006 12:38:55.107248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3007 12:38:55.107332 ==
3008 12:38:55.107398 DQS Delay:
3009 12:38:55.110701 DQS0 = 0, DQS1 = 0
3010 12:38:55.110785 DQM Delay:
3011 12:38:55.113780 DQM0 = 111, DQM1 = 102
3012 12:38:55.113865 DQ Delay:
3013 12:38:55.117340 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
3014 12:38:55.120336 DQ4 =111, DQ5 =99, DQ6 =119, DQ7 =123
3015 12:38:55.123717 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
3016 12:38:55.127122 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3017 12:38:55.127206
3018 12:38:55.127272
3019 12:38:55.130765 ==
3020 12:38:55.130849 Dram Type= 6, Freq= 0, CH_0, rank 1
3021 12:38:55.137339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3022 12:38:55.137424 ==
3023 12:38:55.137515
3024 12:38:55.137593
3025 12:38:55.140581 TX Vref Scan disable
3026 12:38:55.140693 == TX Byte 0 ==
3027 12:38:55.143896 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3028 12:38:55.150657 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3029 12:38:55.150741 == TX Byte 1 ==
3030 12:38:55.153967 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3031 12:38:55.160798 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3032 12:38:55.160881 ==
3033 12:38:55.164049 Dram Type= 6, Freq= 0, CH_0, rank 1
3034 12:38:55.167111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3035 12:38:55.167196 ==
3036 12:38:55.179111 TX Vref=22, minBit 1, minWin=25, winSum=423
3037 12:38:55.182400 TX Vref=24, minBit 1, minWin=26, winSum=426
3038 12:38:55.185748 TX Vref=26, minBit 12, minWin=26, winSum=437
3039 12:38:55.189030 TX Vref=28, minBit 12, minWin=26, winSum=440
3040 12:38:55.192296 TX Vref=30, minBit 1, minWin=27, winSum=443
3041 12:38:55.199038 TX Vref=32, minBit 10, minWin=26, winSum=438
3042 12:38:55.202268 [TxChooseVref] Worse bit 1, Min win 27, Win sum 443, Final Vref 30
3043 12:38:55.202353
3044 12:38:55.205728 Final TX Range 1 Vref 30
3045 12:38:55.205812
3046 12:38:55.205879 ==
3047 12:38:55.209248 Dram Type= 6, Freq= 0, CH_0, rank 1
3048 12:38:55.212550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 12:38:55.212633 ==
3050 12:38:55.215626
3051 12:38:55.215751
3052 12:38:55.215857 TX Vref Scan disable
3053 12:38:55.219254 == TX Byte 0 ==
3054 12:38:55.222390 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3055 12:38:55.229060 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3056 12:38:55.229140 == TX Byte 1 ==
3057 12:38:55.232412 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3058 12:38:55.239025 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3059 12:38:55.239114
3060 12:38:55.239180 [DATLAT]
3061 12:38:55.239240 Freq=1200, CH0 RK1
3062 12:38:55.239305
3063 12:38:55.242247 DATLAT Default: 0xd
3064 12:38:55.242326 0, 0xFFFF, sum = 0
3065 12:38:55.245892 1, 0xFFFF, sum = 0
3066 12:38:55.245967 2, 0xFFFF, sum = 0
3067 12:38:55.249042 3, 0xFFFF, sum = 0
3068 12:38:55.252481 4, 0xFFFF, sum = 0
3069 12:38:55.252560 5, 0xFFFF, sum = 0
3070 12:38:55.255820 6, 0xFFFF, sum = 0
3071 12:38:55.255903 7, 0xFFFF, sum = 0
3072 12:38:55.259101 8, 0xFFFF, sum = 0
3073 12:38:55.259174 9, 0xFFFF, sum = 0
3074 12:38:55.262396 10, 0xFFFF, sum = 0
3075 12:38:55.262474 11, 0xFFFF, sum = 0
3076 12:38:55.265635 12, 0x0, sum = 1
3077 12:38:55.265707 13, 0x0, sum = 2
3078 12:38:55.269248 14, 0x0, sum = 3
3079 12:38:55.269326 15, 0x0, sum = 4
3080 12:38:55.269389 best_step = 13
3081 12:38:55.269447
3082 12:38:55.272369 ==
3083 12:38:55.275871 Dram Type= 6, Freq= 0, CH_0, rank 1
3084 12:38:55.279241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3085 12:38:55.279316 ==
3086 12:38:55.279378 RX Vref Scan: 0
3087 12:38:55.279444
3088 12:38:55.282454 RX Vref 0 -> 0, step: 1
3089 12:38:55.282526
3090 12:38:55.285814 RX Delay -37 -> 252, step: 4
3091 12:38:55.289416 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3092 12:38:55.295540 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3093 12:38:55.298844 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3094 12:38:55.302370 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3095 12:38:55.305798 iDelay=195, Bit 4, Center 110 (43 ~ 178) 136
3096 12:38:55.309037 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3097 12:38:55.315621 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3098 12:38:55.318826 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3099 12:38:55.322314 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3100 12:38:55.325627 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3101 12:38:55.329267 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3102 12:38:55.332380 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3103 12:38:55.339001 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3104 12:38:55.342348 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3105 12:38:55.345705 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3106 12:38:55.348860 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3107 12:38:55.348935 ==
3108 12:38:55.352118 Dram Type= 6, Freq= 0, CH_0, rank 1
3109 12:38:55.358813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3110 12:38:55.358896 ==
3111 12:38:55.358965 DQS Delay:
3112 12:38:55.362376 DQS0 = 0, DQS1 = 0
3113 12:38:55.362450 DQM Delay:
3114 12:38:55.365738 DQM0 = 110, DQM1 = 102
3115 12:38:55.365818 DQ Delay:
3116 12:38:55.368940 DQ0 =108, DQ1 =112, DQ2 =108, DQ3 =108
3117 12:38:55.372329 DQ4 =110, DQ5 =100, DQ6 =120, DQ7 =120
3118 12:38:55.375603 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3119 12:38:55.379236 DQ12 =110, DQ13 =108, DQ14 =116, DQ15 =110
3120 12:38:55.379315
3121 12:38:55.379382
3122 12:38:55.388960 [DQSOSCAuto] RK1, (LSB)MR18= 0x14fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 402 ps
3123 12:38:55.389049 CH0 RK1: MR19=403, MR18=14FC
3124 12:38:55.395859 CH0_RK1: MR19=0x403, MR18=0x14FC, DQSOSC=402, MR23=63, INC=40, DEC=27
3125 12:38:55.399158 [RxdqsGatingPostProcess] freq 1200
3126 12:38:55.405679 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3127 12:38:55.409179 best DQS0 dly(2T, 0.5T) = (0, 11)
3128 12:38:55.412442 best DQS1 dly(2T, 0.5T) = (0, 12)
3129 12:38:55.415695 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3130 12:38:55.415779 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3131 12:38:55.418929 best DQS0 dly(2T, 0.5T) = (0, 11)
3132 12:38:55.422457 best DQS1 dly(2T, 0.5T) = (0, 11)
3133 12:38:55.425621 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3134 12:38:55.428823 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3135 12:38:55.432491 Pre-setting of DQS Precalculation
3136 12:38:55.438828 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3137 12:38:55.438912 ==
3138 12:38:55.442106 Dram Type= 6, Freq= 0, CH_1, rank 0
3139 12:38:55.445684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3140 12:38:55.445768 ==
3141 12:38:55.452139 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3142 12:38:55.455673 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3143 12:38:55.465261 [CA 0] Center 37 (7~67) winsize 61
3144 12:38:55.468707 [CA 1] Center 37 (7~68) winsize 62
3145 12:38:55.472117 [CA 2] Center 34 (4~64) winsize 61
3146 12:38:55.475459 [CA 3] Center 33 (3~64) winsize 62
3147 12:38:55.478819 [CA 4] Center 34 (4~64) winsize 61
3148 12:38:55.482035 [CA 5] Center 33 (3~63) winsize 61
3149 12:38:55.482110
3150 12:38:55.485332 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3151 12:38:55.485454
3152 12:38:55.488536 [CATrainingPosCal] consider 1 rank data
3153 12:38:55.491954 u2DelayCellTimex100 = 270/100 ps
3154 12:38:55.495483 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3155 12:38:55.498576 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3156 12:38:55.505346 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3157 12:38:55.508583 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3158 12:38:55.511986 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3159 12:38:55.515162 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3160 12:38:55.515238
3161 12:38:55.518446 CA PerBit enable=1, Macro0, CA PI delay=33
3162 12:38:55.518523
3163 12:38:55.522095 [CBTSetCACLKResult] CA Dly = 33
3164 12:38:55.522172 CS Dly: 5 (0~36)
3165 12:38:55.525114 ==
3166 12:38:55.525194 Dram Type= 6, Freq= 0, CH_1, rank 1
3167 12:38:55.531745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3168 12:38:55.531836 ==
3169 12:38:55.535346 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3170 12:38:55.541981 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3171 12:38:55.551105 [CA 0] Center 37 (7~67) winsize 61
3172 12:38:55.554105 [CA 1] Center 37 (7~68) winsize 62
3173 12:38:55.557720 [CA 2] Center 34 (4~65) winsize 62
3174 12:38:55.560865 [CA 3] Center 33 (3~64) winsize 62
3175 12:38:55.564087 [CA 4] Center 34 (4~65) winsize 62
3176 12:38:55.567445 [CA 5] Center 33 (3~63) winsize 61
3177 12:38:55.567519
3178 12:38:55.570740 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3179 12:38:55.570818
3180 12:38:55.574236 [CATrainingPosCal] consider 2 rank data
3181 12:38:55.577593 u2DelayCellTimex100 = 270/100 ps
3182 12:38:55.580974 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3183 12:38:55.584400 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3184 12:38:55.591051 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3185 12:38:55.594150 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3186 12:38:55.597568 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3187 12:38:55.600936 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3188 12:38:55.601023
3189 12:38:55.604080 CA PerBit enable=1, Macro0, CA PI delay=33
3190 12:38:55.604161
3191 12:38:55.607365 [CBTSetCACLKResult] CA Dly = 33
3192 12:38:55.607439 CS Dly: 6 (0~39)
3193 12:38:55.607509
3194 12:38:55.611043 ----->DramcWriteLeveling(PI) begin...
3195 12:38:55.614209 ==
3196 12:38:55.614286 Dram Type= 6, Freq= 0, CH_1, rank 0
3197 12:38:55.620825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3198 12:38:55.620912 ==
3199 12:38:55.624106 Write leveling (Byte 0): 24 => 24
3200 12:38:55.627354 Write leveling (Byte 1): 28 => 28
3201 12:38:55.630865 DramcWriteLeveling(PI) end<-----
3202 12:38:55.630941
3203 12:38:55.631005 ==
3204 12:38:55.634286 Dram Type= 6, Freq= 0, CH_1, rank 0
3205 12:38:55.637442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3206 12:38:55.637569 ==
3207 12:38:55.640705 [Gating] SW mode calibration
3208 12:38:55.647663 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3209 12:38:55.650936 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3210 12:38:55.657718 0 15 0 | B1->B0 | 3232 2d2d | 0 1 | (0 0) (0 0)
3211 12:38:55.660962 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3212 12:38:55.664258 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3213 12:38:55.670718 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3214 12:38:55.674325 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3215 12:38:55.677504 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3216 12:38:55.683954 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3217 12:38:55.687368 0 15 28 | B1->B0 | 2d2d 3131 | 1 1 | (1 0) (1 0)
3218 12:38:55.690624 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3219 12:38:55.697348 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3220 12:38:55.700695 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3221 12:38:55.703926 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3222 12:38:55.710717 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3223 12:38:55.713998 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3224 12:38:55.717401 1 0 24 | B1->B0 | 2727 2323 | 1 0 | (1 1) (0 0)
3225 12:38:55.724056 1 0 28 | B1->B0 | 4242 4343 | 0 0 | (0 0) (0 0)
3226 12:38:55.727335 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3227 12:38:55.730625 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 12:38:55.737450 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 12:38:55.740800 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3230 12:38:55.743967 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3231 12:38:55.747592 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3232 12:38:55.753993 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3233 12:38:55.757551 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3234 12:38:55.760615 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 12:38:55.767581 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 12:38:55.770807 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 12:38:55.773969 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 12:38:55.780919 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 12:38:55.784106 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 12:38:55.787431 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 12:38:55.794277 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 12:38:55.797270 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 12:38:55.800992 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 12:38:55.807494 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 12:38:55.810746 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3246 12:38:55.814041 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3247 12:38:55.820591 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3248 12:38:55.824098 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3249 12:38:55.827324 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3250 12:38:55.834163 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3251 12:38:55.834249 Total UI for P1: 0, mck2ui 16
3252 12:38:55.840922 best dqsien dly found for B0: ( 1, 3, 28)
3253 12:38:55.841006 Total UI for P1: 0, mck2ui 16
3254 12:38:55.844279 best dqsien dly found for B1: ( 1, 3, 28)
3255 12:38:55.850783 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3256 12:38:55.853969 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3257 12:38:55.854052
3258 12:38:55.857641 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3259 12:38:55.860837 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3260 12:38:55.863920 [Gating] SW calibration Done
3261 12:38:55.864003 ==
3262 12:38:55.867572 Dram Type= 6, Freq= 0, CH_1, rank 0
3263 12:38:55.870804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3264 12:38:55.870889 ==
3265 12:38:55.874109 RX Vref Scan: 0
3266 12:38:55.874192
3267 12:38:55.874257 RX Vref 0 -> 0, step: 1
3268 12:38:55.874319
3269 12:38:55.877301 RX Delay -40 -> 252, step: 8
3270 12:38:55.880806 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3271 12:38:55.884069 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3272 12:38:55.890889 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3273 12:38:55.894178 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3274 12:38:55.897272 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3275 12:38:55.900767 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3276 12:38:55.903844 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3277 12:38:55.910773 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3278 12:38:55.914024 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3279 12:38:55.917284 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3280 12:38:55.920530 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3281 12:38:55.923785 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3282 12:38:55.930415 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3283 12:38:55.934026 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3284 12:38:55.937249 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3285 12:38:55.940744 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3286 12:38:55.940820 ==
3287 12:38:55.944271 Dram Type= 6, Freq= 0, CH_1, rank 0
3288 12:38:55.950744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3289 12:38:55.950830 ==
3290 12:38:55.950898 DQS Delay:
3291 12:38:55.950958 DQS0 = 0, DQS1 = 0
3292 12:38:55.953796 DQM Delay:
3293 12:38:55.953898 DQM0 = 113, DQM1 = 105
3294 12:38:55.957321 DQ Delay:
3295 12:38:55.960665 DQ0 =119, DQ1 =107, DQ2 =103, DQ3 =111
3296 12:38:55.963842 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3297 12:38:55.967005 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
3298 12:38:55.970461 DQ12 =111, DQ13 =115, DQ14 =111, DQ15 =111
3299 12:38:55.970545
3300 12:38:55.970612
3301 12:38:55.970672 ==
3302 12:38:55.974162 Dram Type= 6, Freq= 0, CH_1, rank 0
3303 12:38:55.977460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3304 12:38:55.977578 ==
3305 12:38:55.977647
3306 12:38:55.980761
3307 12:38:55.980835 TX Vref Scan disable
3308 12:38:55.983914 == TX Byte 0 ==
3309 12:38:55.987440 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3310 12:38:55.990695 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3311 12:38:55.993901 == TX Byte 1 ==
3312 12:38:55.997282 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3313 12:38:56.000674 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3314 12:38:56.000759 ==
3315 12:38:56.004129 Dram Type= 6, Freq= 0, CH_1, rank 0
3316 12:38:56.010267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3317 12:38:56.010368 ==
3318 12:38:56.021410 TX Vref=22, minBit 11, minWin=24, winSum=407
3319 12:38:56.024280 TX Vref=24, minBit 11, minWin=24, winSum=412
3320 12:38:56.027887 TX Vref=26, minBit 8, minWin=25, winSum=418
3321 12:38:56.031305 TX Vref=28, minBit 9, minWin=25, winSum=424
3322 12:38:56.034658 TX Vref=30, minBit 9, minWin=25, winSum=423
3323 12:38:56.041336 TX Vref=32, minBit 9, minWin=25, winSum=421
3324 12:38:56.044510 [TxChooseVref] Worse bit 9, Min win 25, Win sum 424, Final Vref 28
3325 12:38:56.044594
3326 12:38:56.047810 Final TX Range 1 Vref 28
3327 12:38:56.047894
3328 12:38:56.047960 ==
3329 12:38:56.051098 Dram Type= 6, Freq= 0, CH_1, rank 0
3330 12:38:56.054475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3331 12:38:56.054559 ==
3332 12:38:56.057779
3333 12:38:56.057862
3334 12:38:56.057928 TX Vref Scan disable
3335 12:38:56.061130 == TX Byte 0 ==
3336 12:38:56.064549 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3337 12:38:56.067815 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3338 12:38:56.071130 == TX Byte 1 ==
3339 12:38:56.074489 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3340 12:38:56.077812 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3341 12:38:56.081270
3342 12:38:56.081353 [DATLAT]
3343 12:38:56.081444 Freq=1200, CH1 RK0
3344 12:38:56.081531
3345 12:38:56.084519 DATLAT Default: 0xd
3346 12:38:56.084603 0, 0xFFFF, sum = 0
3347 12:38:56.087764 1, 0xFFFF, sum = 0
3348 12:38:56.087849 2, 0xFFFF, sum = 0
3349 12:38:56.091379 3, 0xFFFF, sum = 0
3350 12:38:56.091464 4, 0xFFFF, sum = 0
3351 12:38:56.094615 5, 0xFFFF, sum = 0
3352 12:38:56.094701 6, 0xFFFF, sum = 0
3353 12:38:56.098095 7, 0xFFFF, sum = 0
3354 12:38:56.098181 8, 0xFFFF, sum = 0
3355 12:38:56.101266 9, 0xFFFF, sum = 0
3356 12:38:56.104598 10, 0xFFFF, sum = 0
3357 12:38:56.104748 11, 0xFFFF, sum = 0
3358 12:38:56.108027 12, 0x0, sum = 1
3359 12:38:56.108110 13, 0x0, sum = 2
3360 12:38:56.108183 14, 0x0, sum = 3
3361 12:38:56.111469 15, 0x0, sum = 4
3362 12:38:56.111571 best_step = 13
3363 12:38:56.111661
3364 12:38:56.114638 ==
3365 12:38:56.114757 Dram Type= 6, Freq= 0, CH_1, rank 0
3366 12:38:56.121272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3367 12:38:56.121357 ==
3368 12:38:56.121422 RX Vref Scan: 1
3369 12:38:56.121521
3370 12:38:56.124872 Set Vref Range= 32 -> 127
3371 12:38:56.124968
3372 12:38:56.128068 RX Vref 32 -> 127, step: 1
3373 12:38:56.128146
3374 12:38:56.131365 RX Delay -21 -> 252, step: 4
3375 12:38:56.131465
3376 12:38:56.134615 Set Vref, RX VrefLevel [Byte0]: 32
3377 12:38:56.137787 [Byte1]: 32
3378 12:38:56.137868
3379 12:38:56.141385 Set Vref, RX VrefLevel [Byte0]: 33
3380 12:38:56.144875 [Byte1]: 33
3381 12:38:56.144958
3382 12:38:56.148221 Set Vref, RX VrefLevel [Byte0]: 34
3383 12:38:56.151544 [Byte1]: 34
3384 12:38:56.155647
3385 12:38:56.155729 Set Vref, RX VrefLevel [Byte0]: 35
3386 12:38:56.158864 [Byte1]: 35
3387 12:38:56.163373
3388 12:38:56.163450 Set Vref, RX VrefLevel [Byte0]: 36
3389 12:38:56.166490 [Byte1]: 36
3390 12:38:56.171239
3391 12:38:56.171319 Set Vref, RX VrefLevel [Byte0]: 37
3392 12:38:56.174682 [Byte1]: 37
3393 12:38:56.179131
3394 12:38:56.179206 Set Vref, RX VrefLevel [Byte0]: 38
3395 12:38:56.182339 [Byte1]: 38
3396 12:38:56.187246
3397 12:38:56.187326 Set Vref, RX VrefLevel [Byte0]: 39
3398 12:38:56.190465 [Byte1]: 39
3399 12:38:56.194907
3400 12:38:56.194988 Set Vref, RX VrefLevel [Byte0]: 40
3401 12:38:56.198363 [Byte1]: 40
3402 12:38:56.203022
3403 12:38:56.203107 Set Vref, RX VrefLevel [Byte0]: 41
3404 12:38:56.206412 [Byte1]: 41
3405 12:38:56.210838
3406 12:38:56.210920 Set Vref, RX VrefLevel [Byte0]: 42
3407 12:38:56.214322 [Byte1]: 42
3408 12:38:56.218767
3409 12:38:56.218853 Set Vref, RX VrefLevel [Byte0]: 43
3410 12:38:56.222149 [Byte1]: 43
3411 12:38:56.226563
3412 12:38:56.226643 Set Vref, RX VrefLevel [Byte0]: 44
3413 12:38:56.230162 [Byte1]: 44
3414 12:38:56.234522
3415 12:38:56.234598 Set Vref, RX VrefLevel [Byte0]: 45
3416 12:38:56.238128 [Byte1]: 45
3417 12:38:56.242566
3418 12:38:56.242645 Set Vref, RX VrefLevel [Byte0]: 46
3419 12:38:56.247444 [Byte1]: 46
3420 12:38:56.250591
3421 12:38:56.250677 Set Vref, RX VrefLevel [Byte0]: 47
3422 12:38:56.253845 [Byte1]: 47
3423 12:38:56.258532
3424 12:38:56.258610 Set Vref, RX VrefLevel [Byte0]: 48
3425 12:38:56.261804 [Byte1]: 48
3426 12:38:56.266253
3427 12:38:56.266329 Set Vref, RX VrefLevel [Byte0]: 49
3428 12:38:56.269707 [Byte1]: 49
3429 12:38:56.274088
3430 12:38:56.274170 Set Vref, RX VrefLevel [Byte0]: 50
3431 12:38:56.277602 [Byte1]: 50
3432 12:38:56.282439
3433 12:38:56.282516 Set Vref, RX VrefLevel [Byte0]: 51
3434 12:38:56.285642 [Byte1]: 51
3435 12:38:56.290113
3436 12:38:56.290189 Set Vref, RX VrefLevel [Byte0]: 52
3437 12:38:56.293406 [Byte1]: 52
3438 12:38:56.298107
3439 12:38:56.298189 Set Vref, RX VrefLevel [Byte0]: 53
3440 12:38:56.301360 [Byte1]: 53
3441 12:38:56.306105
3442 12:38:56.306184 Set Vref, RX VrefLevel [Byte0]: 54
3443 12:38:56.309678 [Byte1]: 54
3444 12:38:56.313939
3445 12:38:56.314017 Set Vref, RX VrefLevel [Byte0]: 55
3446 12:38:56.317080 [Byte1]: 55
3447 12:38:56.321593
3448 12:38:56.321668 Set Vref, RX VrefLevel [Byte0]: 56
3449 12:38:56.325028 [Byte1]: 56
3450 12:38:56.329591
3451 12:38:56.329669 Set Vref, RX VrefLevel [Byte0]: 57
3452 12:38:56.332837 [Byte1]: 57
3453 12:38:56.337614
3454 12:38:56.337691 Set Vref, RX VrefLevel [Byte0]: 58
3455 12:38:56.340794 [Byte1]: 58
3456 12:38:56.345369
3457 12:38:56.345489 Set Vref, RX VrefLevel [Byte0]: 59
3458 12:38:56.349001 [Byte1]: 59
3459 12:38:56.353437
3460 12:38:56.353562 Set Vref, RX VrefLevel [Byte0]: 60
3461 12:38:56.356751 [Byte1]: 60
3462 12:38:56.361341
3463 12:38:56.361441 Set Vref, RX VrefLevel [Byte0]: 61
3464 12:38:56.364585 [Byte1]: 61
3465 12:38:56.369497
3466 12:38:56.369574 Set Vref, RX VrefLevel [Byte0]: 62
3467 12:38:56.372580 [Byte1]: 62
3468 12:38:56.377410
3469 12:38:56.377498 Set Vref, RX VrefLevel [Byte0]: 63
3470 12:38:56.380624 [Byte1]: 63
3471 12:38:56.385055
3472 12:38:56.388252 Set Vref, RX VrefLevel [Byte0]: 64
3473 12:38:56.388332 [Byte1]: 64
3474 12:38:56.393154
3475 12:38:56.393230 Set Vref, RX VrefLevel [Byte0]: 65
3476 12:38:56.396481 [Byte1]: 65
3477 12:38:56.401016
3478 12:38:56.401096 Set Vref, RX VrefLevel [Byte0]: 66
3479 12:38:56.404510 [Byte1]: 66
3480 12:38:56.408735
3481 12:38:56.408808 Final RX Vref Byte 0 = 56 to rank0
3482 12:38:56.412363 Final RX Vref Byte 1 = 48 to rank0
3483 12:38:56.415590 Final RX Vref Byte 0 = 56 to rank1
3484 12:38:56.418914 Final RX Vref Byte 1 = 48 to rank1==
3485 12:38:56.422333 Dram Type= 6, Freq= 0, CH_1, rank 0
3486 12:38:56.428831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3487 12:38:56.428923 ==
3488 12:38:56.429010 DQS Delay:
3489 12:38:56.429089 DQS0 = 0, DQS1 = 0
3490 12:38:56.432212 DQM Delay:
3491 12:38:56.432282 DQM0 = 114, DQM1 = 105
3492 12:38:56.435594 DQ Delay:
3493 12:38:56.438679 DQ0 =116, DQ1 =110, DQ2 =104, DQ3 =110
3494 12:38:56.442295 DQ4 =112, DQ5 =122, DQ6 =126, DQ7 =112
3495 12:38:56.445515 DQ8 =92, DQ9 =96, DQ10 =104, DQ11 =98
3496 12:38:56.448830 DQ12 =112, DQ13 =112, DQ14 =114, DQ15 =112
3497 12:38:56.448906
3498 12:38:56.448976
3499 12:38:56.455878 [DQSOSCAuto] RK0, (LSB)MR18= 0xecf3, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
3500 12:38:56.458828 CH1 RK0: MR19=303, MR18=ECF3
3501 12:38:56.465644 CH1_RK0: MR19=0x303, MR18=0xECF3, DQSOSC=415, MR23=63, INC=38, DEC=25
3502 12:38:56.465728
3503 12:38:56.468943 ----->DramcWriteLeveling(PI) begin...
3504 12:38:56.469041 ==
3505 12:38:56.472245 Dram Type= 6, Freq= 0, CH_1, rank 1
3506 12:38:56.475542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3507 12:38:56.475641 ==
3508 12:38:56.479045 Write leveling (Byte 0): 24 => 24
3509 12:38:56.482319 Write leveling (Byte 1): 28 => 28
3510 12:38:56.485739 DramcWriteLeveling(PI) end<-----
3511 12:38:56.485822
3512 12:38:56.485888 ==
3513 12:38:56.489247 Dram Type= 6, Freq= 0, CH_1, rank 1
3514 12:38:56.492506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3515 12:38:56.495658 ==
3516 12:38:56.495755 [Gating] SW mode calibration
3517 12:38:56.505893 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3518 12:38:56.509150 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3519 12:38:56.512619 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3520 12:38:56.519080 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3521 12:38:56.522709 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3522 12:38:56.525885 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3523 12:38:56.532762 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3524 12:38:56.535989 0 15 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3525 12:38:56.539196 0 15 24 | B1->B0 | 3333 2525 | 0 0 | (1 0) (1 0)
3526 12:38:56.545769 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3527 12:38:56.549457 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3528 12:38:56.552727 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3529 12:38:56.556050 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3530 12:38:56.562589 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3531 12:38:56.566044 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3532 12:38:56.569295 1 0 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3533 12:38:56.575915 1 0 24 | B1->B0 | 2929 4444 | 0 0 | (0 0) (0 0)
3534 12:38:56.579267 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 12:38:56.582468 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3536 12:38:56.589364 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 12:38:56.592572 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3538 12:38:56.595828 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3539 12:38:56.602440 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3540 12:38:56.605605 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3541 12:38:56.608946 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3542 12:38:56.615701 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3543 12:38:56.619232 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 12:38:56.622523 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 12:38:56.629007 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 12:38:56.632176 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 12:38:56.635677 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 12:38:56.642105 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 12:38:56.645693 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 12:38:56.649065 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 12:38:56.655650 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 12:38:56.659213 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 12:38:56.662465 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 12:38:56.665686 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 12:38:56.672285 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 12:38:56.675715 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 12:38:56.679076 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3558 12:38:56.685733 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3559 12:38:56.689029 Total UI for P1: 0, mck2ui 16
3560 12:38:56.692215 best dqsien dly found for B0: ( 1, 3, 24)
3561 12:38:56.695366 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3562 12:38:56.698871 Total UI for P1: 0, mck2ui 16
3563 12:38:56.702063 best dqsien dly found for B1: ( 1, 3, 26)
3564 12:38:56.705322 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3565 12:38:56.708586 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3566 12:38:56.708667
3567 12:38:56.712084 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3568 12:38:56.718432 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3569 12:38:56.718514 [Gating] SW calibration Done
3570 12:38:56.718585 ==
3571 12:38:56.721649 Dram Type= 6, Freq= 0, CH_1, rank 1
3572 12:38:56.728534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3573 12:38:56.728621 ==
3574 12:38:56.728688 RX Vref Scan: 0
3575 12:38:56.728758
3576 12:38:56.731660 RX Vref 0 -> 0, step: 1
3577 12:38:56.731743
3578 12:38:56.735339 RX Delay -40 -> 252, step: 8
3579 12:38:56.738462 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3580 12:38:56.741793 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3581 12:38:56.744986 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3582 12:38:56.751316 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3583 12:38:56.754759 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3584 12:38:56.758370 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3585 12:38:56.761670 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3586 12:38:56.764860 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3587 12:38:56.771436 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3588 12:38:56.774713 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3589 12:38:56.777771 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3590 12:38:56.781339 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3591 12:38:56.784327 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3592 12:38:56.791273 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3593 12:38:56.794359 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3594 12:38:56.797846 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3595 12:38:56.797930 ==
3596 12:38:56.801095 Dram Type= 6, Freq= 0, CH_1, rank 1
3597 12:38:56.804344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3598 12:38:56.804428 ==
3599 12:38:56.807797 DQS Delay:
3600 12:38:56.807882 DQS0 = 0, DQS1 = 0
3601 12:38:56.810960 DQM Delay:
3602 12:38:56.811048 DQM0 = 110, DQM1 = 107
3603 12:38:56.814588 DQ Delay:
3604 12:38:56.817747 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3605 12:38:56.821020 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3606 12:38:56.824115 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =99
3607 12:38:56.827777 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
3608 12:38:56.827861
3609 12:38:56.827926
3610 12:38:56.827986 ==
3611 12:38:56.831051 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 12:38:56.834302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 12:38:56.834386 ==
3614 12:38:56.834453
3615 12:38:56.834514
3616 12:38:56.837429 TX Vref Scan disable
3617 12:38:56.840990 == TX Byte 0 ==
3618 12:38:56.844172 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3619 12:38:56.847423 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3620 12:38:56.850689 == TX Byte 1 ==
3621 12:38:56.853938 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3622 12:38:56.857318 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3623 12:38:56.857419 ==
3624 12:38:56.860823 Dram Type= 6, Freq= 0, CH_1, rank 1
3625 12:38:56.864119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3626 12:38:56.867076 ==
3627 12:38:56.877722 TX Vref=22, minBit 11, minWin=25, winSum=422
3628 12:38:56.880877 TX Vref=24, minBit 9, minWin=25, winSum=426
3629 12:38:56.884179 TX Vref=26, minBit 3, minWin=26, winSum=431
3630 12:38:56.887416 TX Vref=28, minBit 7, minWin=26, winSum=434
3631 12:38:56.890917 TX Vref=30, minBit 9, minWin=26, winSum=436
3632 12:38:56.897462 TX Vref=32, minBit 8, minWin=25, winSum=430
3633 12:38:56.900716 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 30
3634 12:38:56.900800
3635 12:38:56.903953 Final TX Range 1 Vref 30
3636 12:38:56.904037
3637 12:38:56.904102 ==
3638 12:38:56.907480 Dram Type= 6, Freq= 0, CH_1, rank 1
3639 12:38:56.910791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3640 12:38:56.914142 ==
3641 12:38:56.914256
3642 12:38:56.914346
3643 12:38:56.914416 TX Vref Scan disable
3644 12:38:56.917407 == TX Byte 0 ==
3645 12:38:56.920927 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3646 12:38:56.927351 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3647 12:38:56.927441 == TX Byte 1 ==
3648 12:38:56.930769 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3649 12:38:56.937285 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3650 12:38:56.937393
3651 12:38:56.937542 [DATLAT]
3652 12:38:56.937638 Freq=1200, CH1 RK1
3653 12:38:56.937740
3654 12:38:56.940777 DATLAT Default: 0xd
3655 12:38:56.940859 0, 0xFFFF, sum = 0
3656 12:38:56.943918 1, 0xFFFF, sum = 0
3657 12:38:56.944003 2, 0xFFFF, sum = 0
3658 12:38:56.947264 3, 0xFFFF, sum = 0
3659 12:38:56.950857 4, 0xFFFF, sum = 0
3660 12:38:56.950928 5, 0xFFFF, sum = 0
3661 12:38:56.954001 6, 0xFFFF, sum = 0
3662 12:38:56.954072 7, 0xFFFF, sum = 0
3663 12:38:56.957267 8, 0xFFFF, sum = 0
3664 12:38:56.957345 9, 0xFFFF, sum = 0
3665 12:38:56.960466 10, 0xFFFF, sum = 0
3666 12:38:56.960545 11, 0xFFFF, sum = 0
3667 12:38:56.964164 12, 0x0, sum = 1
3668 12:38:56.964234 13, 0x0, sum = 2
3669 12:38:56.967271 14, 0x0, sum = 3
3670 12:38:56.967345 15, 0x0, sum = 4
3671 12:38:56.970772 best_step = 13
3672 12:38:56.970842
3673 12:38:56.970912 ==
3674 12:38:56.973660 Dram Type= 6, Freq= 0, CH_1, rank 1
3675 12:38:56.977328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3676 12:38:56.977414 ==
3677 12:38:56.977485 RX Vref Scan: 0
3678 12:38:56.977591
3679 12:38:56.980503 RX Vref 0 -> 0, step: 1
3680 12:38:56.980570
3681 12:38:56.983724 RX Delay -21 -> 252, step: 4
3682 12:38:56.987239 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3683 12:38:56.993638 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3684 12:38:56.996857 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3685 12:38:57.000370 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3686 12:38:57.003625 iDelay=195, Bit 4, Center 110 (43 ~ 178) 136
3687 12:38:57.006846 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3688 12:38:57.013822 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3689 12:38:57.017164 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3690 12:38:57.020280 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3691 12:38:57.023737 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3692 12:38:57.027045 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3693 12:38:57.033650 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3694 12:38:57.036941 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3695 12:38:57.040363 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3696 12:38:57.043489 iDelay=195, Bit 14, Center 114 (51 ~ 178) 128
3697 12:38:57.050180 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3698 12:38:57.050260 ==
3699 12:38:57.053393 Dram Type= 6, Freq= 0, CH_1, rank 1
3700 12:38:57.056674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3701 12:38:57.056751 ==
3702 12:38:57.056814 DQS Delay:
3703 12:38:57.059954 DQS0 = 0, DQS1 = 0
3704 12:38:57.060030 DQM Delay:
3705 12:38:57.063523 DQM0 = 111, DQM1 = 109
3706 12:38:57.063600 DQ Delay:
3707 12:38:57.066796 DQ0 =114, DQ1 =110, DQ2 =100, DQ3 =108
3708 12:38:57.070194 DQ4 =110, DQ5 =120, DQ6 =120, DQ7 =110
3709 12:38:57.073408 DQ8 =94, DQ9 =102, DQ10 =110, DQ11 =104
3710 12:38:57.076788 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =116
3711 12:38:57.076868
3712 12:38:57.076937
3713 12:38:57.086567 [DQSOSCAuto] RK1, (LSB)MR18= 0xf707, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 413 ps
3714 12:38:57.090041 CH1 RK1: MR19=304, MR18=F707
3715 12:38:57.093419 CH1_RK1: MR19=0x304, MR18=0xF707, DQSOSC=407, MR23=63, INC=39, DEC=26
3716 12:38:57.096592 [RxdqsGatingPostProcess] freq 1200
3717 12:38:57.103256 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3718 12:38:57.106429 best DQS0 dly(2T, 0.5T) = (0, 11)
3719 12:38:57.109842 best DQS1 dly(2T, 0.5T) = (0, 11)
3720 12:38:57.113035 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3721 12:38:57.116375 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3722 12:38:57.119698 best DQS0 dly(2T, 0.5T) = (0, 11)
3723 12:38:57.122911 best DQS1 dly(2T, 0.5T) = (0, 11)
3724 12:38:57.126106 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3725 12:38:57.129465 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3726 12:38:57.132816 Pre-setting of DQS Precalculation
3727 12:38:57.136075 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3728 12:38:57.142652 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3729 12:38:57.152640 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3730 12:38:57.152722
3731 12:38:57.152808
3732 12:38:57.152871 [Calibration Summary] 2400 Mbps
3733 12:38:57.156125 CH 0, Rank 0
3734 12:38:57.159382 SW Impedance : PASS
3735 12:38:57.159463 DUTY Scan : NO K
3736 12:38:57.162658 ZQ Calibration : PASS
3737 12:38:57.162746 Jitter Meter : NO K
3738 12:38:57.165923 CBT Training : PASS
3739 12:38:57.169113 Write leveling : PASS
3740 12:38:57.169219 RX DQS gating : PASS
3741 12:38:57.172347 RX DQ/DQS(RDDQC) : PASS
3742 12:38:57.175864 TX DQ/DQS : PASS
3743 12:38:57.175942 RX DATLAT : PASS
3744 12:38:57.179238 RX DQ/DQS(Engine): PASS
3745 12:38:57.182349 TX OE : NO K
3746 12:38:57.182428 All Pass.
3747 12:38:57.182496
3748 12:38:57.182557 CH 0, Rank 1
3749 12:38:57.185581 SW Impedance : PASS
3750 12:38:57.189177 DUTY Scan : NO K
3751 12:38:57.189283 ZQ Calibration : PASS
3752 12:38:57.192418 Jitter Meter : NO K
3753 12:38:57.195631 CBT Training : PASS
3754 12:38:57.195707 Write leveling : PASS
3755 12:38:57.198973 RX DQS gating : PASS
3756 12:38:57.202216 RX DQ/DQS(RDDQC) : PASS
3757 12:38:57.202333 TX DQ/DQS : PASS
3758 12:38:57.205437 RX DATLAT : PASS
3759 12:38:57.208962 RX DQ/DQS(Engine): PASS
3760 12:38:57.209042 TX OE : NO K
3761 12:38:57.212097 All Pass.
3762 12:38:57.212209
3763 12:38:57.212277 CH 1, Rank 0
3764 12:38:57.215358 SW Impedance : PASS
3765 12:38:57.215427 DUTY Scan : NO K
3766 12:38:57.218725 ZQ Calibration : PASS
3767 12:38:57.222015 Jitter Meter : NO K
3768 12:38:57.222103 CBT Training : PASS
3769 12:38:57.225577 Write leveling : PASS
3770 12:38:57.225663 RX DQS gating : PASS
3771 12:38:57.228747 RX DQ/DQS(RDDQC) : PASS
3772 12:38:57.232132 TX DQ/DQS : PASS
3773 12:38:57.232209 RX DATLAT : PASS
3774 12:38:57.235269 RX DQ/DQS(Engine): PASS
3775 12:38:57.238582 TX OE : NO K
3776 12:38:57.238659 All Pass.
3777 12:38:57.238724
3778 12:38:57.238793 CH 1, Rank 1
3779 12:38:57.241960 SW Impedance : PASS
3780 12:38:57.245395 DUTY Scan : NO K
3781 12:38:57.245536 ZQ Calibration : PASS
3782 12:38:57.248654 Jitter Meter : NO K
3783 12:38:57.252167 CBT Training : PASS
3784 12:38:57.252274 Write leveling : PASS
3785 12:38:57.255279 RX DQS gating : PASS
3786 12:38:57.258461 RX DQ/DQS(RDDQC) : PASS
3787 12:38:57.258581 TX DQ/DQS : PASS
3788 12:38:57.261779 RX DATLAT : PASS
3789 12:38:57.265198 RX DQ/DQS(Engine): PASS
3790 12:38:57.265309 TX OE : NO K
3791 12:38:57.265403 All Pass.
3792 12:38:57.268491
3793 12:38:57.268568 DramC Write-DBI off
3794 12:38:57.271817 PER_BANK_REFRESH: Hybrid Mode
3795 12:38:57.271902 TX_TRACKING: ON
3796 12:38:57.281841 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3797 12:38:57.285037 [FAST_K] Save calibration result to emmc
3798 12:38:57.288329 dramc_set_vcore_voltage set vcore to 650000
3799 12:38:57.291573 Read voltage for 600, 5
3800 12:38:57.291690 Vio18 = 0
3801 12:38:57.295217 Vcore = 650000
3802 12:38:57.295289 Vdram = 0
3803 12:38:57.295351 Vddq = 0
3804 12:38:57.295409 Vmddr = 0
3805 12:38:57.301695 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3806 12:38:57.308114 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3807 12:38:57.308219 MEM_TYPE=3, freq_sel=19
3808 12:38:57.311658 sv_algorithm_assistance_LP4_1600
3809 12:38:57.315050 ============ PULL DRAM RESETB DOWN ============
3810 12:38:57.321496 ========== PULL DRAM RESETB DOWN end =========
3811 12:38:57.324982 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3812 12:38:57.328341 ===================================
3813 12:38:57.331483 LPDDR4 DRAM CONFIGURATION
3814 12:38:57.334778 ===================================
3815 12:38:57.334859 EX_ROW_EN[0] = 0x0
3816 12:38:57.338131 EX_ROW_EN[1] = 0x0
3817 12:38:57.338205 LP4Y_EN = 0x0
3818 12:38:57.341395 WORK_FSP = 0x0
3819 12:38:57.344582 WL = 0x2
3820 12:38:57.344655 RL = 0x2
3821 12:38:57.347978 BL = 0x2
3822 12:38:57.348047 RPST = 0x0
3823 12:38:57.351264 RD_PRE = 0x0
3824 12:38:57.351338 WR_PRE = 0x1
3825 12:38:57.354515 WR_PST = 0x0
3826 12:38:57.354585 DBI_WR = 0x0
3827 12:38:57.357928 DBI_RD = 0x0
3828 12:38:57.358026 OTF = 0x1
3829 12:38:57.361227 ===================================
3830 12:38:57.364556 ===================================
3831 12:38:57.368004 ANA top config
3832 12:38:57.371482 ===================================
3833 12:38:57.371557 DLL_ASYNC_EN = 0
3834 12:38:57.374514 ALL_SLAVE_EN = 1
3835 12:38:57.378108 NEW_RANK_MODE = 1
3836 12:38:57.381319 DLL_IDLE_MODE = 1
3837 12:38:57.381445 LP45_APHY_COMB_EN = 1
3838 12:38:57.384597 TX_ODT_DIS = 1
3839 12:38:57.388255 NEW_8X_MODE = 1
3840 12:38:57.391473 ===================================
3841 12:38:57.394659 ===================================
3842 12:38:57.397810 data_rate = 1200
3843 12:38:57.401079 CKR = 1
3844 12:38:57.404386 DQ_P2S_RATIO = 8
3845 12:38:57.407871 ===================================
3846 12:38:57.407947 CA_P2S_RATIO = 8
3847 12:38:57.411071 DQ_CA_OPEN = 0
3848 12:38:57.414342 DQ_SEMI_OPEN = 0
3849 12:38:57.417637 CA_SEMI_OPEN = 0
3850 12:38:57.421188 CA_FULL_RATE = 0
3851 12:38:57.424443 DQ_CKDIV4_EN = 1
3852 12:38:57.424513 CA_CKDIV4_EN = 1
3853 12:38:57.427725 CA_PREDIV_EN = 0
3854 12:38:57.430944 PH8_DLY = 0
3855 12:38:57.434634 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3856 12:38:57.437682 DQ_AAMCK_DIV = 4
3857 12:38:57.441358 CA_AAMCK_DIV = 4
3858 12:38:57.441462 CA_ADMCK_DIV = 4
3859 12:38:57.444629 DQ_TRACK_CA_EN = 0
3860 12:38:57.447733 CA_PICK = 600
3861 12:38:57.451019 CA_MCKIO = 600
3862 12:38:57.454494 MCKIO_SEMI = 0
3863 12:38:57.458003 PLL_FREQ = 2288
3864 12:38:57.458082 DQ_UI_PI_RATIO = 32
3865 12:38:57.461137 CA_UI_PI_RATIO = 0
3866 12:38:57.464476 ===================================
3867 12:38:57.467730 ===================================
3868 12:38:57.471404 memory_type:LPDDR4
3869 12:38:57.474483 GP_NUM : 10
3870 12:38:57.474590 SRAM_EN : 1
3871 12:38:57.477629 MD32_EN : 0
3872 12:38:57.481045 ===================================
3873 12:38:57.484091 [ANA_INIT] >>>>>>>>>>>>>>
3874 12:38:57.484167 <<<<<< [CONFIGURE PHASE]: ANA_TX
3875 12:38:57.491055 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3876 12:38:57.491139 ===================================
3877 12:38:57.494294 data_rate = 1200,PCW = 0X5800
3878 12:38:57.497503 ===================================
3879 12:38:57.500728 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3880 12:38:57.507125 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3881 12:38:57.514166 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3882 12:38:57.517163 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3883 12:38:57.520741 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3884 12:38:57.523986 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3885 12:38:57.527169 [ANA_INIT] flow start
3886 12:38:57.527250 [ANA_INIT] PLL >>>>>>>>
3887 12:38:57.530296 [ANA_INIT] PLL <<<<<<<<
3888 12:38:57.533631 [ANA_INIT] MIDPI >>>>>>>>
3889 12:38:57.536875 [ANA_INIT] MIDPI <<<<<<<<
3890 12:38:57.536955 [ANA_INIT] DLL >>>>>>>>
3891 12:38:57.540163 [ANA_INIT] flow end
3892 12:38:57.543765 ============ LP4 DIFF to SE enter ============
3893 12:38:57.547047 ============ LP4 DIFF to SE exit ============
3894 12:38:57.550246 [ANA_INIT] <<<<<<<<<<<<<
3895 12:38:57.553567 [Flow] Enable top DCM control >>>>>
3896 12:38:57.556753 [Flow] Enable top DCM control <<<<<
3897 12:38:57.560221 Enable DLL master slave shuffle
3898 12:38:57.566690 ==============================================================
3899 12:38:57.566776 Gating Mode config
3900 12:38:57.573563 ==============================================================
3901 12:38:57.573648 Config description:
3902 12:38:57.583326 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3903 12:38:57.589983 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3904 12:38:57.596675 SELPH_MODE 0: By rank 1: By Phase
3905 12:38:57.599800 ==============================================================
3906 12:38:57.603274 GAT_TRACK_EN = 1
3907 12:38:57.606295 RX_GATING_MODE = 2
3908 12:38:57.609672 RX_GATING_TRACK_MODE = 2
3909 12:38:57.612798 SELPH_MODE = 1
3910 12:38:57.616429 PICG_EARLY_EN = 1
3911 12:38:57.619699 VALID_LAT_VALUE = 1
3912 12:38:57.626055 ==============================================================
3913 12:38:57.629725 Enter into Gating configuration >>>>
3914 12:38:57.632989 Exit from Gating configuration <<<<
3915 12:38:57.636327 Enter into DVFS_PRE_config >>>>>
3916 12:38:57.646310 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3917 12:38:57.649436 Exit from DVFS_PRE_config <<<<<
3918 12:38:57.652659 Enter into PICG configuration >>>>
3919 12:38:57.655957 Exit from PICG configuration <<<<
3920 12:38:57.659215 [RX_INPUT] configuration >>>>>
3921 12:38:57.659316 [RX_INPUT] configuration <<<<<
3922 12:38:57.666226 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3923 12:38:57.672493 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3924 12:38:57.679370 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3925 12:38:57.682553 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3926 12:38:57.689244 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3927 12:38:57.695913 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3928 12:38:57.699148 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3929 12:38:57.702379 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3930 12:38:57.709208 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3931 12:38:57.712406 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3932 12:38:57.715565 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3933 12:38:57.722386 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3934 12:38:57.725632 ===================================
3935 12:38:57.725752 LPDDR4 DRAM CONFIGURATION
3936 12:38:57.728850 ===================================
3937 12:38:57.732096 EX_ROW_EN[0] = 0x0
3938 12:38:57.735415 EX_ROW_EN[1] = 0x0
3939 12:38:57.735517 LP4Y_EN = 0x0
3940 12:38:57.738584 WORK_FSP = 0x0
3941 12:38:57.738664 WL = 0x2
3942 12:38:57.741909 RL = 0x2
3943 12:38:57.741982 BL = 0x2
3944 12:38:57.745185 RPST = 0x0
3945 12:38:57.745286 RD_PRE = 0x0
3946 12:38:57.748522 WR_PRE = 0x1
3947 12:38:57.748600 WR_PST = 0x0
3948 12:38:57.751741 DBI_WR = 0x0
3949 12:38:57.751817 DBI_RD = 0x0
3950 12:38:57.755479 OTF = 0x1
3951 12:38:57.758632 ===================================
3952 12:38:57.761906 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3953 12:38:57.765115 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3954 12:38:57.771680 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3955 12:38:57.774858 ===================================
3956 12:38:57.774964 LPDDR4 DRAM CONFIGURATION
3957 12:38:57.778467 ===================================
3958 12:38:57.781649 EX_ROW_EN[0] = 0x10
3959 12:38:57.785007 EX_ROW_EN[1] = 0x0
3960 12:38:57.785108 LP4Y_EN = 0x0
3961 12:38:57.788067 WORK_FSP = 0x0
3962 12:38:57.788168 WL = 0x2
3963 12:38:57.791645 RL = 0x2
3964 12:38:57.791726 BL = 0x2
3965 12:38:57.794836 RPST = 0x0
3966 12:38:57.794909 RD_PRE = 0x0
3967 12:38:57.798291 WR_PRE = 0x1
3968 12:38:57.798388 WR_PST = 0x0
3969 12:38:57.801542 DBI_WR = 0x0
3970 12:38:57.801645 DBI_RD = 0x0
3971 12:38:57.804732 OTF = 0x1
3972 12:38:57.808242 ===================================
3973 12:38:57.814843 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3974 12:38:57.818082 nWR fixed to 30
3975 12:38:57.818186 [ModeRegInit_LP4] CH0 RK0
3976 12:38:57.821329 [ModeRegInit_LP4] CH0 RK1
3977 12:38:57.824474 [ModeRegInit_LP4] CH1 RK0
3978 12:38:57.827974 [ModeRegInit_LP4] CH1 RK1
3979 12:38:57.828077 match AC timing 17
3980 12:38:57.834294 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3981 12:38:57.837778 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3982 12:38:57.841058 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3983 12:38:57.847729 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3984 12:38:57.850968 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3985 12:38:57.851084 ==
3986 12:38:57.854296 Dram Type= 6, Freq= 0, CH_0, rank 0
3987 12:38:57.857606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3988 12:38:57.857689 ==
3989 12:38:57.864441 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3990 12:38:57.870700 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3991 12:38:57.874164 [CA 0] Center 37 (7~67) winsize 61
3992 12:38:57.877243 [CA 1] Center 36 (6~67) winsize 62
3993 12:38:57.880822 [CA 2] Center 35 (5~65) winsize 61
3994 12:38:57.883862 [CA 3] Center 35 (5~65) winsize 61
3995 12:38:57.887140 [CA 4] Center 34 (4~65) winsize 62
3996 12:38:57.890380 [CA 5] Center 34 (4~64) winsize 61
3997 12:38:57.890461
3998 12:38:57.893791 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3999 12:38:57.893898
4000 12:38:57.897057 [CATrainingPosCal] consider 1 rank data
4001 12:38:57.900654 u2DelayCellTimex100 = 270/100 ps
4002 12:38:57.903909 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4003 12:38:57.907033 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4004 12:38:57.910380 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4005 12:38:57.913961 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4006 12:38:57.917056 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4007 12:38:57.920583 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4008 12:38:57.923867
4009 12:38:57.927098 CA PerBit enable=1, Macro0, CA PI delay=34
4010 12:38:57.927177
4011 12:38:57.930380 [CBTSetCACLKResult] CA Dly = 34
4012 12:38:57.930468 CS Dly: 4 (0~35)
4013 12:38:57.930540 ==
4014 12:38:57.933697 Dram Type= 6, Freq= 0, CH_0, rank 1
4015 12:38:57.937100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4016 12:38:57.937187 ==
4017 12:38:57.943694 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4018 12:38:57.950272 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4019 12:38:57.953624 [CA 0] Center 37 (7~67) winsize 61
4020 12:38:57.956865 [CA 1] Center 36 (6~67) winsize 62
4021 12:38:57.960301 [CA 2] Center 35 (5~65) winsize 61
4022 12:38:57.963616 [CA 3] Center 35 (5~65) winsize 61
4023 12:38:57.966815 [CA 4] Center 34 (4~64) winsize 61
4024 12:38:57.970435 [CA 5] Center 33 (3~64) winsize 62
4025 12:38:57.970511
4026 12:38:57.973429 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4027 12:38:57.973534
4028 12:38:57.976973 [CATrainingPosCal] consider 2 rank data
4029 12:38:57.980041 u2DelayCellTimex100 = 270/100 ps
4030 12:38:57.983577 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4031 12:38:57.986801 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4032 12:38:57.990036 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4033 12:38:57.993339 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4034 12:38:58.000034 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4035 12:38:58.003291 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4036 12:38:58.003376
4037 12:38:58.006597 CA PerBit enable=1, Macro0, CA PI delay=34
4038 12:38:58.006674
4039 12:38:58.009884 [CBTSetCACLKResult] CA Dly = 34
4040 12:38:58.009964 CS Dly: 5 (0~37)
4041 12:38:58.010029
4042 12:38:58.013094 ----->DramcWriteLeveling(PI) begin...
4043 12:38:58.013194 ==
4044 12:38:58.016379 Dram Type= 6, Freq= 0, CH_0, rank 0
4045 12:38:58.023327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4046 12:38:58.023421 ==
4047 12:38:58.026409 Write leveling (Byte 0): 32 => 32
4048 12:38:58.026533 Write leveling (Byte 1): 31 => 31
4049 12:38:58.030009 DramcWriteLeveling(PI) end<-----
4050 12:38:58.030114
4051 12:38:58.033183 ==
4052 12:38:58.036401 Dram Type= 6, Freq= 0, CH_0, rank 0
4053 12:38:58.039826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4054 12:38:58.039902 ==
4055 12:38:58.043231 [Gating] SW mode calibration
4056 12:38:58.050017 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4057 12:38:58.053118 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4058 12:38:58.059773 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4059 12:38:58.063125 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4060 12:38:58.066456 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4061 12:38:58.072766 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
4062 12:38:58.076274 0 9 16 | B1->B0 | 3333 2b2b | 0 0 | (0 0) (0 0)
4063 12:38:58.079693 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4064 12:38:58.086365 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4065 12:38:58.089751 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4066 12:38:58.093016 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4067 12:38:58.099265 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4068 12:38:58.102609 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4069 12:38:58.106281 0 10 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4070 12:38:58.112889 0 10 16 | B1->B0 | 3030 3b3b | 0 0 | (0 0) (0 0)
4071 12:38:58.116191 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 12:38:58.119424 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 12:38:58.125986 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 12:38:58.129401 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4075 12:38:58.132556 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4076 12:38:58.136086 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4077 12:38:58.142517 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4078 12:38:58.146052 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 12:38:58.149288 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 12:38:58.156100 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 12:38:58.159513 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 12:38:58.162533 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 12:38:58.169225 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 12:38:58.172450 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 12:38:58.175866 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 12:38:58.182536 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 12:38:58.185694 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 12:38:58.189033 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 12:38:58.195775 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 12:38:58.199081 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 12:38:58.202320 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 12:38:58.209036 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 12:38:58.212358 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 12:38:58.215645 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4095 12:38:58.218934 Total UI for P1: 0, mck2ui 16
4096 12:38:58.222061 best dqsien dly found for B0: ( 0, 13, 14)
4097 12:38:58.225374 Total UI for P1: 0, mck2ui 16
4098 12:38:58.228767 best dqsien dly found for B1: ( 0, 13, 14)
4099 12:38:58.232248 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4100 12:38:58.235288 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4101 12:38:58.235371
4102 12:38:58.242189 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4103 12:38:58.245394 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4104 12:38:58.248616 [Gating] SW calibration Done
4105 12:38:58.248708 ==
4106 12:38:58.251864 Dram Type= 6, Freq= 0, CH_0, rank 0
4107 12:38:58.255474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4108 12:38:58.255558 ==
4109 12:38:58.255624 RX Vref Scan: 0
4110 12:38:58.255688
4111 12:38:58.258543 RX Vref 0 -> 0, step: 1
4112 12:38:58.258644
4113 12:38:58.261883 RX Delay -230 -> 252, step: 16
4114 12:38:58.265338 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4115 12:38:58.271777 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4116 12:38:58.275091 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4117 12:38:58.278477 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4118 12:38:58.281664 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4119 12:38:58.285273 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4120 12:38:58.291756 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4121 12:38:58.295242 iDelay=218, Bit 7, Center 41 (-134 ~ 217) 352
4122 12:38:58.298321 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4123 12:38:58.301731 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4124 12:38:58.308246 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4125 12:38:58.311620 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4126 12:38:58.314947 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4127 12:38:58.318076 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4128 12:38:58.324656 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4129 12:38:58.328317 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4130 12:38:58.328415 ==
4131 12:38:58.331508 Dram Type= 6, Freq= 0, CH_0, rank 0
4132 12:38:58.334755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 12:38:58.334864 ==
4134 12:38:58.338045 DQS Delay:
4135 12:38:58.338129 DQS0 = 0, DQS1 = 0
4136 12:38:58.338193 DQM Delay:
4137 12:38:58.341559 DQM0 = 35, DQM1 = 29
4138 12:38:58.341673 DQ Delay:
4139 12:38:58.344776 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4140 12:38:58.348094 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =41
4141 12:38:58.351440 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4142 12:38:58.354677 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4143 12:38:58.354751
4144 12:38:58.354814
4145 12:38:58.354874 ==
4146 12:38:58.357855 Dram Type= 6, Freq= 0, CH_0, rank 0
4147 12:38:58.364644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 12:38:58.364754 ==
4149 12:38:58.364859
4150 12:38:58.364990
4151 12:38:58.365087 TX Vref Scan disable
4152 12:38:58.368021 == TX Byte 0 ==
4153 12:38:58.371133 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4154 12:38:58.377993 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4155 12:38:58.378083 == TX Byte 1 ==
4156 12:38:58.381155 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4157 12:38:58.387811 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4158 12:38:58.387917 ==
4159 12:38:58.391345 Dram Type= 6, Freq= 0, CH_0, rank 0
4160 12:38:58.394625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4161 12:38:58.394740 ==
4162 12:38:58.394843
4163 12:38:58.394935
4164 12:38:58.397745 TX Vref Scan disable
4165 12:38:58.400955 == TX Byte 0 ==
4166 12:38:58.404243 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4167 12:38:58.407623 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4168 12:38:58.410819 == TX Byte 1 ==
4169 12:38:58.414180 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4170 12:38:58.417346 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4171 12:38:58.417433
4172 12:38:58.417536 [DATLAT]
4173 12:38:58.420752 Freq=600, CH0 RK0
4174 12:38:58.420840
4175 12:38:58.424272 DATLAT Default: 0x9
4176 12:38:58.424358 0, 0xFFFF, sum = 0
4177 12:38:58.427571 1, 0xFFFF, sum = 0
4178 12:38:58.427663 2, 0xFFFF, sum = 0
4179 12:38:58.430839 3, 0xFFFF, sum = 0
4180 12:38:58.430924 4, 0xFFFF, sum = 0
4181 12:38:58.434147 5, 0xFFFF, sum = 0
4182 12:38:58.434239 6, 0xFFFF, sum = 0
4183 12:38:58.437266 7, 0xFFFF, sum = 0
4184 12:38:58.437345 8, 0x0, sum = 1
4185 12:38:58.440798 9, 0x0, sum = 2
4186 12:38:58.440878 10, 0x0, sum = 3
4187 12:38:58.444240 11, 0x0, sum = 4
4188 12:38:58.444323 best_step = 9
4189 12:38:58.444408
4190 12:38:58.444493 ==
4191 12:38:58.447258 Dram Type= 6, Freq= 0, CH_0, rank 0
4192 12:38:58.450491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4193 12:38:58.450580 ==
4194 12:38:58.454220 RX Vref Scan: 1
4195 12:38:58.454303
4196 12:38:58.457454 RX Vref 0 -> 0, step: 1
4197 12:38:58.457547
4198 12:38:58.457614 RX Delay -195 -> 252, step: 8
4199 12:38:58.457682
4200 12:38:58.460739 Set Vref, RX VrefLevel [Byte0]: 62
4201 12:38:58.463938 [Byte1]: 54
4202 12:38:58.468402
4203 12:38:58.468487 Final RX Vref Byte 0 = 62 to rank0
4204 12:38:58.471918 Final RX Vref Byte 1 = 54 to rank0
4205 12:38:58.475121 Final RX Vref Byte 0 = 62 to rank1
4206 12:38:58.478554 Final RX Vref Byte 1 = 54 to rank1==
4207 12:38:58.481739 Dram Type= 6, Freq= 0, CH_0, rank 0
4208 12:38:58.488203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4209 12:38:58.488305 ==
4210 12:38:58.488397 DQS Delay:
4211 12:38:58.491773 DQS0 = 0, DQS1 = 0
4212 12:38:58.491860 DQM Delay:
4213 12:38:58.491928 DQM0 = 35, DQM1 = 28
4214 12:38:58.494837 DQ Delay:
4215 12:38:58.498215 DQ0 =36, DQ1 =36, DQ2 =36, DQ3 =28
4216 12:38:58.501693 DQ4 =36, DQ5 =20, DQ6 =44, DQ7 =44
4217 12:38:58.504684 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4218 12:38:58.508017 DQ12 =32, DQ13 =36, DQ14 =40, DQ15 =36
4219 12:38:58.508104
4220 12:38:58.508172
4221 12:38:58.514674 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d3c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4222 12:38:58.518033 CH0 RK0: MR19=808, MR18=3D3C
4223 12:38:58.524806 CH0_RK0: MR19=0x808, MR18=0x3D3C, DQSOSC=398, MR23=63, INC=165, DEC=110
4224 12:38:58.524909
4225 12:38:58.527842 ----->DramcWriteLeveling(PI) begin...
4226 12:38:58.527942 ==
4227 12:38:58.531038 Dram Type= 6, Freq= 0, CH_0, rank 1
4228 12:38:58.534477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4229 12:38:58.534601 ==
4230 12:38:58.537799 Write leveling (Byte 0): 34 => 34
4231 12:38:58.541013 Write leveling (Byte 1): 31 => 31
4232 12:38:58.544194 DramcWriteLeveling(PI) end<-----
4233 12:38:58.544282
4234 12:38:58.544368 ==
4235 12:38:58.547547 Dram Type= 6, Freq= 0, CH_0, rank 1
4236 12:38:58.550899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4237 12:38:58.554333 ==
4238 12:38:58.554430 [Gating] SW mode calibration
4239 12:38:58.564444 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4240 12:38:58.567693 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4241 12:38:58.570910 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4242 12:38:58.577265 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4243 12:38:58.580833 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4244 12:38:58.584279 0 9 12 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
4245 12:38:58.590633 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (0 0) (0 0)
4246 12:38:58.594237 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4247 12:38:58.597387 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 12:38:58.603881 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4249 12:38:58.607285 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4250 12:38:58.610536 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4251 12:38:58.617240 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4252 12:38:58.620493 0 10 12 | B1->B0 | 2424 3636 | 0 0 | (0 0) (0 0)
4253 12:38:58.623717 0 10 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
4254 12:38:58.630722 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 12:38:58.633778 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 12:38:58.637266 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 12:38:58.643953 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 12:38:58.646958 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 12:38:58.650274 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4260 12:38:58.656973 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4261 12:38:58.660287 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4262 12:38:58.663619 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 12:38:58.670210 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 12:38:58.673455 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 12:38:58.677031 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 12:38:58.680190 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 12:38:58.686955 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 12:38:58.690362 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 12:38:58.693281 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 12:38:58.700212 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 12:38:58.703199 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 12:38:58.706843 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 12:38:58.713227 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 12:38:58.716723 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 12:38:58.720025 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4276 12:38:58.726652 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4277 12:38:58.730056 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4278 12:38:58.733447 Total UI for P1: 0, mck2ui 16
4279 12:38:58.736628 best dqsien dly found for B0: ( 0, 13, 10)
4280 12:38:58.740161 Total UI for P1: 0, mck2ui 16
4281 12:38:58.743395 best dqsien dly found for B1: ( 0, 13, 14)
4282 12:38:58.746679 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4283 12:38:58.749971 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4284 12:38:58.750086
4285 12:38:58.753327 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4286 12:38:58.756628 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4287 12:38:58.759923 [Gating] SW calibration Done
4288 12:38:58.760029 ==
4289 12:38:58.763042 Dram Type= 6, Freq= 0, CH_0, rank 1
4290 12:38:58.769989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4291 12:38:58.770075 ==
4292 12:38:58.770161 RX Vref Scan: 0
4293 12:38:58.770247
4294 12:38:58.773247 RX Vref 0 -> 0, step: 1
4295 12:38:58.773321
4296 12:38:58.776586 RX Delay -230 -> 252, step: 16
4297 12:38:58.779909 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4298 12:38:58.783244 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4299 12:38:58.786412 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4300 12:38:58.793066 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4301 12:38:58.796598 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4302 12:38:58.799743 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4303 12:38:58.803292 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4304 12:38:58.806492 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4305 12:38:58.813083 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4306 12:38:58.816469 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4307 12:38:58.819909 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4308 12:38:58.823062 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4309 12:38:58.829438 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4310 12:38:58.833058 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4311 12:38:58.835994 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4312 12:38:58.839671 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4313 12:38:58.843098 ==
4314 12:38:58.843178 Dram Type= 6, Freq= 0, CH_0, rank 1
4315 12:38:58.849341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4316 12:38:58.849425 ==
4317 12:38:58.849533 DQS Delay:
4318 12:38:58.852716 DQS0 = 0, DQS1 = 0
4319 12:38:58.852830 DQM Delay:
4320 12:38:58.856343 DQM0 = 35, DQM1 = 28
4321 12:38:58.856456 DQ Delay:
4322 12:38:58.859633 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4323 12:38:58.862681 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4324 12:38:58.866343 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4325 12:38:58.869551 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4326 12:38:58.869632
4327 12:38:58.869717
4328 12:38:58.869796 ==
4329 12:38:58.872624 Dram Type= 6, Freq= 0, CH_0, rank 1
4330 12:38:58.875898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4331 12:38:58.875978 ==
4332 12:38:58.876068
4333 12:38:58.876148
4334 12:38:58.879170 TX Vref Scan disable
4335 12:38:58.882792 == TX Byte 0 ==
4336 12:38:58.885984 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4337 12:38:58.889210 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4338 12:38:58.892457 == TX Byte 1 ==
4339 12:38:58.895789 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4340 12:38:58.899054 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4341 12:38:58.899131 ==
4342 12:38:58.902618 Dram Type= 6, Freq= 0, CH_0, rank 1
4343 12:38:58.909010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4344 12:38:58.909122 ==
4345 12:38:58.909226
4346 12:38:58.909332
4347 12:38:58.909431 TX Vref Scan disable
4348 12:38:58.913037 == TX Byte 0 ==
4349 12:38:58.916698 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4350 12:38:58.923215 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4351 12:38:58.923295 == TX Byte 1 ==
4352 12:38:58.926613 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4353 12:38:58.933264 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4354 12:38:58.933382
4355 12:38:58.933494 [DATLAT]
4356 12:38:58.933576 Freq=600, CH0 RK1
4357 12:38:58.933656
4358 12:38:58.936540 DATLAT Default: 0x9
4359 12:38:58.936614 0, 0xFFFF, sum = 0
4360 12:38:58.939669 1, 0xFFFF, sum = 0
4361 12:38:58.943106 2, 0xFFFF, sum = 0
4362 12:38:58.943190 3, 0xFFFF, sum = 0
4363 12:38:58.946330 4, 0xFFFF, sum = 0
4364 12:38:58.946415 5, 0xFFFF, sum = 0
4365 12:38:58.949795 6, 0xFFFF, sum = 0
4366 12:38:58.949881 7, 0xFFFF, sum = 0
4367 12:38:58.953138 8, 0x0, sum = 1
4368 12:38:58.953222 9, 0x0, sum = 2
4369 12:38:58.953288 10, 0x0, sum = 3
4370 12:38:58.956325 11, 0x0, sum = 4
4371 12:38:58.956411 best_step = 9
4372 12:38:58.956478
4373 12:38:58.956540 ==
4374 12:38:58.959574 Dram Type= 6, Freq= 0, CH_0, rank 1
4375 12:38:58.966410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4376 12:38:58.966494 ==
4377 12:38:58.966560 RX Vref Scan: 0
4378 12:38:58.966622
4379 12:38:58.969409 RX Vref 0 -> 0, step: 1
4380 12:38:58.969510
4381 12:38:58.972817 RX Delay -195 -> 252, step: 8
4382 12:38:58.976005 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4383 12:38:58.982770 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4384 12:38:58.986206 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4385 12:38:58.989306 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4386 12:38:58.992971 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4387 12:38:58.999467 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4388 12:38:59.002719 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4389 12:38:59.006048 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4390 12:38:59.009299 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4391 12:38:59.012899 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4392 12:38:59.019337 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4393 12:38:59.022689 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4394 12:38:59.025820 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4395 12:38:59.029338 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4396 12:38:59.035913 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4397 12:38:59.039288 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4398 12:38:59.039392 ==
4399 12:38:59.042542 Dram Type= 6, Freq= 0, CH_0, rank 1
4400 12:38:59.045764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 12:38:59.045872 ==
4402 12:38:59.049277 DQS Delay:
4403 12:38:59.049381 DQS0 = 0, DQS1 = 0
4404 12:38:59.049507 DQM Delay:
4405 12:38:59.052532 DQM0 = 33, DQM1 = 27
4406 12:38:59.052648 DQ Delay:
4407 12:38:59.055596 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4408 12:38:59.059078 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4409 12:38:59.062322 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4410 12:38:59.065575 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4411 12:38:59.065683
4412 12:38:59.065776
4413 12:38:59.075702 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d3b, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4414 12:38:59.079019 CH0 RK1: MR19=808, MR18=6D3B
4415 12:38:59.085438 CH0_RK1: MR19=0x808, MR18=0x6D3B, DQSOSC=389, MR23=63, INC=173, DEC=115
4416 12:38:59.085564 [RxdqsGatingPostProcess] freq 600
4417 12:38:59.092155 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4418 12:38:59.095250 Pre-setting of DQS Precalculation
4419 12:38:59.098941 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4420 12:38:59.102020 ==
4421 12:38:59.102128 Dram Type= 6, Freq= 0, CH_1, rank 0
4422 12:38:59.108642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4423 12:38:59.108751 ==
4424 12:38:59.111851 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4425 12:38:59.118472 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4426 12:38:59.122423 [CA 0] Center 35 (5~66) winsize 62
4427 12:38:59.125373 [CA 1] Center 35 (5~66) winsize 62
4428 12:38:59.129035 [CA 2] Center 34 (4~65) winsize 62
4429 12:38:59.132080 [CA 3] Center 34 (3~65) winsize 63
4430 12:38:59.135419 [CA 4] Center 34 (4~65) winsize 62
4431 12:38:59.138998 [CA 5] Center 33 (3~64) winsize 62
4432 12:38:59.139100
4433 12:38:59.142036 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4434 12:38:59.142140
4435 12:38:59.145732 [CATrainingPosCal] consider 1 rank data
4436 12:38:59.148741 u2DelayCellTimex100 = 270/100 ps
4437 12:38:59.152205 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4438 12:38:59.158625 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4439 12:38:59.162016 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4440 12:38:59.165304 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4441 12:38:59.168685 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4442 12:38:59.172077 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4443 12:38:59.172189
4444 12:38:59.175249 CA PerBit enable=1, Macro0, CA PI delay=33
4445 12:38:59.175360
4446 12:38:59.178804 [CBTSetCACLKResult] CA Dly = 33
4447 12:38:59.178913 CS Dly: 4 (0~35)
4448 12:38:59.182030 ==
4449 12:38:59.185292 Dram Type= 6, Freq= 0, CH_1, rank 1
4450 12:38:59.188599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4451 12:38:59.188711 ==
4452 12:38:59.191845 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4453 12:38:59.198341 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4454 12:38:59.202277 [CA 0] Center 35 (5~66) winsize 62
4455 12:38:59.205660 [CA 1] Center 36 (6~67) winsize 62
4456 12:38:59.209034 [CA 2] Center 34 (4~65) winsize 62
4457 12:38:59.212358 [CA 3] Center 34 (3~65) winsize 63
4458 12:38:59.215699 [CA 4] Center 34 (4~65) winsize 62
4459 12:38:59.218913 [CA 5] Center 34 (3~65) winsize 63
4460 12:38:59.219023
4461 12:38:59.222080 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4462 12:38:59.222192
4463 12:38:59.225357 [CATrainingPosCal] consider 2 rank data
4464 12:38:59.228644 u2DelayCellTimex100 = 270/100 ps
4465 12:38:59.232042 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4466 12:38:59.238595 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4467 12:38:59.241956 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4468 12:38:59.245205 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4469 12:38:59.248418 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4470 12:38:59.252063 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4471 12:38:59.252165
4472 12:38:59.255314 CA PerBit enable=1, Macro0, CA PI delay=33
4473 12:38:59.255416
4474 12:38:59.258616 [CBTSetCACLKResult] CA Dly = 33
4475 12:38:59.261809 CS Dly: 5 (0~38)
4476 12:38:59.261890
4477 12:38:59.265159 ----->DramcWriteLeveling(PI) begin...
4478 12:38:59.265268 ==
4479 12:38:59.268591 Dram Type= 6, Freq= 0, CH_1, rank 0
4480 12:38:59.271784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4481 12:38:59.271885 ==
4482 12:38:59.274865 Write leveling (Byte 0): 28 => 28
4483 12:38:59.278295 Write leveling (Byte 1): 28 => 28
4484 12:38:59.281591 DramcWriteLeveling(PI) end<-----
4485 12:38:59.281688
4486 12:38:59.281785 ==
4487 12:38:59.284872 Dram Type= 6, Freq= 0, CH_1, rank 0
4488 12:38:59.288258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4489 12:38:59.288361 ==
4490 12:38:59.291591 [Gating] SW mode calibration
4491 12:38:59.298270 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4492 12:38:59.305035 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4493 12:38:59.308573 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4494 12:38:59.311639 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4495 12:38:59.318278 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4496 12:38:59.321775 0 9 12 | B1->B0 | 2f2f 3232 | 1 1 | (1 1) (1 0)
4497 12:38:59.324978 0 9 16 | B1->B0 | 2a2a 2929 | 0 0 | (0 0) (0 0)
4498 12:38:59.331702 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4499 12:38:59.334769 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4500 12:38:59.338371 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4501 12:38:59.344662 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4502 12:38:59.348347 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4503 12:38:59.351616 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4504 12:38:59.354798 0 10 12 | B1->B0 | 2f2f 3030 | 0 0 | (0 0) (0 0)
4505 12:38:59.361632 0 10 16 | B1->B0 | 4343 4242 | 0 0 | (0 0) (0 0)
4506 12:38:59.364788 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4507 12:38:59.368188 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 12:38:59.374611 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 12:38:59.377958 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 12:38:59.381314 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4511 12:38:59.388023 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4512 12:38:59.391396 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4513 12:38:59.394626 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4514 12:38:59.401227 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 12:38:59.404816 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 12:38:59.408084 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 12:38:59.414624 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 12:38:59.417793 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 12:38:59.421342 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 12:38:59.427989 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 12:38:59.431413 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 12:38:59.434396 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 12:38:59.441325 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 12:38:59.444519 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 12:38:59.447686 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 12:38:59.454753 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 12:38:59.457591 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 12:38:59.461182 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4529 12:38:59.464183 Total UI for P1: 0, mck2ui 16
4530 12:38:59.467640 best dqsien dly found for B0: ( 0, 13, 10)
4531 12:38:59.474368 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4532 12:38:59.474449 Total UI for P1: 0, mck2ui 16
4533 12:38:59.481076 best dqsien dly found for B1: ( 0, 13, 12)
4534 12:38:59.484273 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4535 12:38:59.487636 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4536 12:38:59.487712
4537 12:38:59.490770 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4538 12:38:59.494233 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4539 12:38:59.497692 [Gating] SW calibration Done
4540 12:38:59.497765 ==
4541 12:38:59.500945 Dram Type= 6, Freq= 0, CH_1, rank 0
4542 12:38:59.504270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4543 12:38:59.504344 ==
4544 12:38:59.507543 RX Vref Scan: 0
4545 12:38:59.507616
4546 12:38:59.507683 RX Vref 0 -> 0, step: 1
4547 12:38:59.507743
4548 12:38:59.510866 RX Delay -230 -> 252, step: 16
4549 12:38:59.517265 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4550 12:38:59.520722 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4551 12:38:59.523998 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4552 12:38:59.527219 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4553 12:38:59.530498 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4554 12:38:59.537117 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4555 12:38:59.540404 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4556 12:38:59.544042 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4557 12:38:59.547085 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4558 12:38:59.554216 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4559 12:38:59.557459 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4560 12:38:59.560681 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4561 12:38:59.563845 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4562 12:38:59.567471 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4563 12:38:59.573779 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4564 12:38:59.577068 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4565 12:38:59.577139 ==
4566 12:38:59.580723 Dram Type= 6, Freq= 0, CH_1, rank 0
4567 12:38:59.583813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 12:38:59.583885 ==
4569 12:38:59.587270 DQS Delay:
4570 12:38:59.587371 DQS0 = 0, DQS1 = 0
4571 12:38:59.590407 DQM Delay:
4572 12:38:59.590495 DQM0 = 37, DQM1 = 27
4573 12:38:59.590571 DQ Delay:
4574 12:38:59.593771 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4575 12:38:59.596971 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4576 12:38:59.600206 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4577 12:38:59.603741 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4578 12:38:59.603824
4579 12:38:59.603888
4580 12:38:59.606992 ==
4581 12:38:59.607077 Dram Type= 6, Freq= 0, CH_1, rank 0
4582 12:38:59.613733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 12:38:59.613813 ==
4584 12:38:59.613900
4585 12:38:59.613977
4586 12:38:59.614053 TX Vref Scan disable
4587 12:38:59.617798 == TX Byte 0 ==
4588 12:38:59.620842 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4589 12:38:59.627636 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4590 12:38:59.627720 == TX Byte 1 ==
4591 12:38:59.630940 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4592 12:38:59.637427 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4593 12:38:59.637558 ==
4594 12:38:59.640739 Dram Type= 6, Freq= 0, CH_1, rank 0
4595 12:38:59.644294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 12:38:59.644374 ==
4597 12:38:59.644462
4598 12:38:59.644540
4599 12:38:59.647624 TX Vref Scan disable
4600 12:38:59.650782 == TX Byte 0 ==
4601 12:38:59.654203 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4602 12:38:59.657427 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4603 12:38:59.660592 == TX Byte 1 ==
4604 12:38:59.663765 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4605 12:38:59.667333 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4606 12:38:59.667415
4607 12:38:59.667492 [DATLAT]
4608 12:38:59.670575 Freq=600, CH1 RK0
4609 12:38:59.670652
4610 12:38:59.674062 DATLAT Default: 0x9
4611 12:38:59.674138 0, 0xFFFF, sum = 0
4612 12:38:59.677230 1, 0xFFFF, sum = 0
4613 12:38:59.677312 2, 0xFFFF, sum = 0
4614 12:38:59.680556 3, 0xFFFF, sum = 0
4615 12:38:59.680633 4, 0xFFFF, sum = 0
4616 12:38:59.683980 5, 0xFFFF, sum = 0
4617 12:38:59.684060 6, 0xFFFF, sum = 0
4618 12:38:59.687336 7, 0xFFFF, sum = 0
4619 12:38:59.687420 8, 0x0, sum = 1
4620 12:38:59.690365 9, 0x0, sum = 2
4621 12:38:59.690451 10, 0x0, sum = 3
4622 12:38:59.690533 11, 0x0, sum = 4
4623 12:38:59.693694 best_step = 9
4624 12:38:59.693768
4625 12:38:59.693866 ==
4626 12:38:59.697037 Dram Type= 6, Freq= 0, CH_1, rank 0
4627 12:38:59.700533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4628 12:38:59.700636 ==
4629 12:38:59.703666 RX Vref Scan: 1
4630 12:38:59.703742
4631 12:38:59.703828 RX Vref 0 -> 0, step: 1
4632 12:38:59.707015
4633 12:38:59.707099 RX Delay -195 -> 252, step: 8
4634 12:38:59.707181
4635 12:38:59.710522 Set Vref, RX VrefLevel [Byte0]: 56
4636 12:38:59.713814 [Byte1]: 48
4637 12:38:59.718237
4638 12:38:59.718321 Final RX Vref Byte 0 = 56 to rank0
4639 12:38:59.721410 Final RX Vref Byte 1 = 48 to rank0
4640 12:38:59.724821 Final RX Vref Byte 0 = 56 to rank1
4641 12:38:59.728009 Final RX Vref Byte 1 = 48 to rank1==
4642 12:38:59.731297 Dram Type= 6, Freq= 0, CH_1, rank 0
4643 12:38:59.737704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4644 12:38:59.737817 ==
4645 12:38:59.737914 DQS Delay:
4646 12:38:59.741191 DQS0 = 0, DQS1 = 0
4647 12:38:59.741294 DQM Delay:
4648 12:38:59.741389 DQM0 = 39, DQM1 = 30
4649 12:38:59.744662 DQ Delay:
4650 12:38:59.747960 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4651 12:38:59.751330 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4652 12:38:59.754569 DQ8 =16, DQ9 =16, DQ10 =28, DQ11 =24
4653 12:38:59.757725 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4654 12:38:59.757805
4655 12:38:59.757888
4656 12:38:59.764319 [DQSOSCAuto] RK0, (LSB)MR18= 0x202d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 403 ps
4657 12:38:59.767537 CH1 RK0: MR19=808, MR18=202D
4658 12:38:59.774392 CH1_RK0: MR19=0x808, MR18=0x202D, DQSOSC=401, MR23=63, INC=163, DEC=108
4659 12:38:59.774505
4660 12:38:59.777633 ----->DramcWriteLeveling(PI) begin...
4661 12:38:59.777734 ==
4662 12:38:59.780863 Dram Type= 6, Freq= 0, CH_1, rank 1
4663 12:38:59.784304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4664 12:38:59.784380 ==
4665 12:38:59.787522 Write leveling (Byte 0): 29 => 29
4666 12:38:59.790615 Write leveling (Byte 1): 28 => 28
4667 12:38:59.793901 DramcWriteLeveling(PI) end<-----
4668 12:38:59.793976
4669 12:38:59.794062 ==
4670 12:38:59.797504 Dram Type= 6, Freq= 0, CH_1, rank 1
4671 12:38:59.800609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 12:38:59.803992 ==
4673 12:38:59.804070 [Gating] SW mode calibration
4674 12:38:59.810478 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4675 12:38:59.817438 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4676 12:38:59.820530 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4677 12:38:59.827340 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4678 12:38:59.830709 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4679 12:38:59.833937 0 9 12 | B1->B0 | 3434 2b2b | 1 1 | (1 0) (1 0)
4680 12:38:59.840467 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4681 12:38:59.843633 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4682 12:38:59.847152 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4683 12:38:59.853537 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4684 12:38:59.856980 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4685 12:38:59.860243 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4686 12:38:59.866983 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4687 12:38:59.870246 0 10 12 | B1->B0 | 2e2e 3d3d | 0 1 | (0 0) (0 0)
4688 12:38:59.873558 0 10 16 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
4689 12:38:59.880002 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 12:38:59.883234 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 12:38:59.886561 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 12:38:59.893223 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4693 12:38:59.896450 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4694 12:38:59.899663 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4695 12:38:59.906331 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4696 12:38:59.909740 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 12:38:59.913243 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 12:38:59.919695 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 12:38:59.922876 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 12:38:59.926243 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 12:38:59.932986 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 12:38:59.936269 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 12:38:59.939613 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 12:38:59.946389 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 12:38:59.949563 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 12:38:59.952815 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 12:38:59.956242 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 12:38:59.962802 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 12:38:59.966100 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 12:38:59.969321 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 12:38:59.975915 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4712 12:38:59.979503 Total UI for P1: 0, mck2ui 16
4713 12:38:59.982757 best dqsien dly found for B0: ( 0, 13, 10)
4714 12:38:59.986021 Total UI for P1: 0, mck2ui 16
4715 12:38:59.989278 best dqsien dly found for B1: ( 0, 13, 10)
4716 12:38:59.992800 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4717 12:38:59.995978 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4718 12:38:59.996062
4719 12:38:59.999242 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4720 12:39:00.002531 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4721 12:39:00.005731 [Gating] SW calibration Done
4722 12:39:00.005815 ==
4723 12:39:00.009303 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 12:39:00.012491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 12:39:00.012576 ==
4726 12:39:00.015977 RX Vref Scan: 0
4727 12:39:00.016063
4728 12:39:00.019231 RX Vref 0 -> 0, step: 1
4729 12:39:00.019320
4730 12:39:00.019388 RX Delay -230 -> 252, step: 16
4731 12:39:00.025705 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4732 12:39:00.029035 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4733 12:39:00.032183 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4734 12:39:00.035663 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4735 12:39:00.042524 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4736 12:39:00.045537 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4737 12:39:00.049271 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4738 12:39:00.052623 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4739 12:39:00.055948 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4740 12:39:00.062449 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4741 12:39:00.065819 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4742 12:39:00.069054 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4743 12:39:00.072469 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4744 12:39:00.079161 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4745 12:39:00.082424 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4746 12:39:00.085729 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4747 12:39:00.085814 ==
4748 12:39:00.088972 Dram Type= 6, Freq= 0, CH_1, rank 1
4749 12:39:00.092236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4750 12:39:00.095499 ==
4751 12:39:00.095583 DQS Delay:
4752 12:39:00.095650 DQS0 = 0, DQS1 = 0
4753 12:39:00.099056 DQM Delay:
4754 12:39:00.099140 DQM0 = 35, DQM1 = 29
4755 12:39:00.102480 DQ Delay:
4756 12:39:00.102585 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4757 12:39:00.105609 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4758 12:39:00.108761 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4759 12:39:00.112396 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4760 12:39:00.112480
4761 12:39:00.115555
4762 12:39:00.115639 ==
4763 12:39:00.119052 Dram Type= 6, Freq= 0, CH_1, rank 1
4764 12:39:00.122302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4765 12:39:00.122401 ==
4766 12:39:00.122468
4767 12:39:00.122530
4768 12:39:00.125419 TX Vref Scan disable
4769 12:39:00.125527 == TX Byte 0 ==
4770 12:39:00.132176 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4771 12:39:00.135472 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4772 12:39:00.135571 == TX Byte 1 ==
4773 12:39:00.142014 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4774 12:39:00.145362 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4775 12:39:00.145446 ==
4776 12:39:00.148607 Dram Type= 6, Freq= 0, CH_1, rank 1
4777 12:39:00.151897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4778 12:39:00.151996 ==
4779 12:39:00.152062
4780 12:39:00.152123
4781 12:39:00.155243 TX Vref Scan disable
4782 12:39:00.158645 == TX Byte 0 ==
4783 12:39:00.162101 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4784 12:39:00.165330 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4785 12:39:00.168559 == TX Byte 1 ==
4786 12:39:00.171733 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4787 12:39:00.175346 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4788 12:39:00.175445
4789 12:39:00.178323 [DATLAT]
4790 12:39:00.178437 Freq=600, CH1 RK1
4791 12:39:00.178533
4792 12:39:00.181878 DATLAT Default: 0x9
4793 12:39:00.181976 0, 0xFFFF, sum = 0
4794 12:39:00.185012 1, 0xFFFF, sum = 0
4795 12:39:00.185097 2, 0xFFFF, sum = 0
4796 12:39:00.188611 3, 0xFFFF, sum = 0
4797 12:39:00.188697 4, 0xFFFF, sum = 0
4798 12:39:00.191722 5, 0xFFFF, sum = 0
4799 12:39:00.194890 6, 0xFFFF, sum = 0
4800 12:39:00.194976 7, 0xFFFF, sum = 0
4801 12:39:00.195045 8, 0x0, sum = 1
4802 12:39:00.198810 9, 0x0, sum = 2
4803 12:39:00.198896 10, 0x0, sum = 3
4804 12:39:00.201472 11, 0x0, sum = 4
4805 12:39:00.201579 best_step = 9
4806 12:39:00.201646
4807 12:39:00.201707 ==
4808 12:39:00.205109 Dram Type= 6, Freq= 0, CH_1, rank 1
4809 12:39:00.211694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4810 12:39:00.211778 ==
4811 12:39:00.211887 RX Vref Scan: 0
4812 12:39:00.211982
4813 12:39:00.214880 RX Vref 0 -> 0, step: 1
4814 12:39:00.214964
4815 12:39:00.218068 RX Delay -195 -> 252, step: 8
4816 12:39:00.221303 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4817 12:39:00.228042 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4818 12:39:00.231261 iDelay=205, Bit 2, Center 20 (-139 ~ 180) 320
4819 12:39:00.234686 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4820 12:39:00.238058 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4821 12:39:00.244638 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4822 12:39:00.247797 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4823 12:39:00.251189 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4824 12:39:00.254534 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4825 12:39:00.257805 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4826 12:39:00.264557 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4827 12:39:00.267663 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4828 12:39:00.271043 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4829 12:39:00.274464 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4830 12:39:00.280997 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4831 12:39:00.284451 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4832 12:39:00.284554 ==
4833 12:39:00.287649 Dram Type= 6, Freq= 0, CH_1, rank 1
4834 12:39:00.290924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4835 12:39:00.291035 ==
4836 12:39:00.294096 DQS Delay:
4837 12:39:00.294198 DQS0 = 0, DQS1 = 0
4838 12:39:00.297324 DQM Delay:
4839 12:39:00.297442 DQM0 = 36, DQM1 = 30
4840 12:39:00.297546 DQ Delay:
4841 12:39:00.300846 DQ0 =40, DQ1 =32, DQ2 =20, DQ3 =32
4842 12:39:00.304060 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4843 12:39:00.307608 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4844 12:39:00.310663 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4845 12:39:00.310743
4846 12:39:00.310810
4847 12:39:00.320553 [DQSOSCAuto] RK1, (LSB)MR18= 0x3859, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4848 12:39:00.323928 CH1 RK1: MR19=808, MR18=3859
4849 12:39:00.327260 CH1_RK1: MR19=0x808, MR18=0x3859, DQSOSC=393, MR23=63, INC=169, DEC=113
4850 12:39:00.330868 [RxdqsGatingPostProcess] freq 600
4851 12:39:00.337240 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4852 12:39:00.340765 Pre-setting of DQS Precalculation
4853 12:39:00.344108 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4854 12:39:00.353958 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4855 12:39:00.360573 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4856 12:39:00.360679
4857 12:39:00.360782
4858 12:39:00.363758 [Calibration Summary] 1200 Mbps
4859 12:39:00.363891 CH 0, Rank 0
4860 12:39:00.367030 SW Impedance : PASS
4861 12:39:00.367114 DUTY Scan : NO K
4862 12:39:00.370331 ZQ Calibration : PASS
4863 12:39:00.373894 Jitter Meter : NO K
4864 12:39:00.373999 CBT Training : PASS
4865 12:39:00.376962 Write leveling : PASS
4866 12:39:00.380599 RX DQS gating : PASS
4867 12:39:00.380722 RX DQ/DQS(RDDQC) : PASS
4868 12:39:00.383680 TX DQ/DQS : PASS
4869 12:39:00.386937 RX DATLAT : PASS
4870 12:39:00.387016 RX DQ/DQS(Engine): PASS
4871 12:39:00.390390 TX OE : NO K
4872 12:39:00.390468 All Pass.
4873 12:39:00.390531
4874 12:39:00.393445 CH 0, Rank 1
4875 12:39:00.393575 SW Impedance : PASS
4876 12:39:00.396994 DUTY Scan : NO K
4877 12:39:00.400061 ZQ Calibration : PASS
4878 12:39:00.400143 Jitter Meter : NO K
4879 12:39:00.403633 CBT Training : PASS
4880 12:39:00.403739 Write leveling : PASS
4881 12:39:00.406865 RX DQS gating : PASS
4882 12:39:00.410338 RX DQ/DQS(RDDQC) : PASS
4883 12:39:00.410433 TX DQ/DQS : PASS
4884 12:39:00.413551 RX DATLAT : PASS
4885 12:39:00.416942 RX DQ/DQS(Engine): PASS
4886 12:39:00.417053 TX OE : NO K
4887 12:39:00.420008 All Pass.
4888 12:39:00.420178
4889 12:39:00.420287 CH 1, Rank 0
4890 12:39:00.423257 SW Impedance : PASS
4891 12:39:00.423333 DUTY Scan : NO K
4892 12:39:00.426582 ZQ Calibration : PASS
4893 12:39:00.430205 Jitter Meter : NO K
4894 12:39:00.430279 CBT Training : PASS
4895 12:39:00.433357 Write leveling : PASS
4896 12:39:00.436583 RX DQS gating : PASS
4897 12:39:00.436653 RX DQ/DQS(RDDQC) : PASS
4898 12:39:00.439988 TX DQ/DQS : PASS
4899 12:39:00.443182 RX DATLAT : PASS
4900 12:39:00.443258 RX DQ/DQS(Engine): PASS
4901 12:39:00.446757 TX OE : NO K
4902 12:39:00.446834 All Pass.
4903 12:39:00.446897
4904 12:39:00.450018 CH 1, Rank 1
4905 12:39:00.450124 SW Impedance : PASS
4906 12:39:00.453329 DUTY Scan : NO K
4907 12:39:00.456322 ZQ Calibration : PASS
4908 12:39:00.456420 Jitter Meter : NO K
4909 12:39:00.459589 CBT Training : PASS
4910 12:39:00.463323 Write leveling : PASS
4911 12:39:00.463435 RX DQS gating : PASS
4912 12:39:00.466374 RX DQ/DQS(RDDQC) : PASS
4913 12:39:00.466487 TX DQ/DQS : PASS
4914 12:39:00.469632 RX DATLAT : PASS
4915 12:39:00.473094 RX DQ/DQS(Engine): PASS
4916 12:39:00.473199 TX OE : NO K
4917 12:39:00.476431 All Pass.
4918 12:39:00.476533
4919 12:39:00.476615 DramC Write-DBI off
4920 12:39:00.479735 PER_BANK_REFRESH: Hybrid Mode
4921 12:39:00.482834 TX_TRACKING: ON
4922 12:39:00.489667 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4923 12:39:00.492944 [FAST_K] Save calibration result to emmc
4924 12:39:00.496160 dramc_set_vcore_voltage set vcore to 662500
4925 12:39:00.499751 Read voltage for 933, 3
4926 12:39:00.499835 Vio18 = 0
4927 12:39:00.503022 Vcore = 662500
4928 12:39:00.503096 Vdram = 0
4929 12:39:00.503166 Vddq = 0
4930 12:39:00.506374 Vmddr = 0
4931 12:39:00.509766 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4932 12:39:00.516305 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4933 12:39:00.516383 MEM_TYPE=3, freq_sel=17
4934 12:39:00.519441 sv_algorithm_assistance_LP4_1600
4935 12:39:00.526191 ============ PULL DRAM RESETB DOWN ============
4936 12:39:00.529364 ========== PULL DRAM RESETB DOWN end =========
4937 12:39:00.533047 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4938 12:39:00.536426 ===================================
4939 12:39:00.539732 LPDDR4 DRAM CONFIGURATION
4940 12:39:00.542797 ===================================
4941 12:39:00.542915 EX_ROW_EN[0] = 0x0
4942 12:39:00.546353 EX_ROW_EN[1] = 0x0
4943 12:39:00.549768 LP4Y_EN = 0x0
4944 12:39:00.549882 WORK_FSP = 0x0
4945 12:39:00.552950 WL = 0x3
4946 12:39:00.553061 RL = 0x3
4947 12:39:00.556122 BL = 0x2
4948 12:39:00.556208 RPST = 0x0
4949 12:39:00.559644 RD_PRE = 0x0
4950 12:39:00.559722 WR_PRE = 0x1
4951 12:39:00.562731 WR_PST = 0x0
4952 12:39:00.562819 DBI_WR = 0x0
4953 12:39:00.566310 DBI_RD = 0x0
4954 12:39:00.566388 OTF = 0x1
4955 12:39:00.569469 ===================================
4956 12:39:00.572840 ===================================
4957 12:39:00.576187 ANA top config
4958 12:39:00.579456 ===================================
4959 12:39:00.579571 DLL_ASYNC_EN = 0
4960 12:39:00.582775 ALL_SLAVE_EN = 1
4961 12:39:00.586281 NEW_RANK_MODE = 1
4962 12:39:00.589397 DLL_IDLE_MODE = 1
4963 12:39:00.592862 LP45_APHY_COMB_EN = 1
4964 12:39:00.592974 TX_ODT_DIS = 1
4965 12:39:00.596091 NEW_8X_MODE = 1
4966 12:39:00.599438 ===================================
4967 12:39:00.602591 ===================================
4968 12:39:00.606157 data_rate = 1866
4969 12:39:00.609264 CKR = 1
4970 12:39:00.612591 DQ_P2S_RATIO = 8
4971 12:39:00.615948 ===================================
4972 12:39:00.616057 CA_P2S_RATIO = 8
4973 12:39:00.619348 DQ_CA_OPEN = 0
4974 12:39:00.622710 DQ_SEMI_OPEN = 0
4975 12:39:00.625717 CA_SEMI_OPEN = 0
4976 12:39:00.629043 CA_FULL_RATE = 0
4977 12:39:00.632633 DQ_CKDIV4_EN = 1
4978 12:39:00.632751 CA_CKDIV4_EN = 1
4979 12:39:00.636042 CA_PREDIV_EN = 0
4980 12:39:00.639314 PH8_DLY = 0
4981 12:39:00.642675 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4982 12:39:00.645926 DQ_AAMCK_DIV = 4
4983 12:39:00.648979 CA_AAMCK_DIV = 4
4984 12:39:00.649092 CA_ADMCK_DIV = 4
4985 12:39:00.652442 DQ_TRACK_CA_EN = 0
4986 12:39:00.655617 CA_PICK = 933
4987 12:39:00.659066 CA_MCKIO = 933
4988 12:39:00.662209 MCKIO_SEMI = 0
4989 12:39:00.665718 PLL_FREQ = 3732
4990 12:39:00.668900 DQ_UI_PI_RATIO = 32
4991 12:39:00.669014 CA_UI_PI_RATIO = 0
4992 12:39:00.672090 ===================================
4993 12:39:00.675448 ===================================
4994 12:39:00.678735 memory_type:LPDDR4
4995 12:39:00.681963 GP_NUM : 10
4996 12:39:00.682078 SRAM_EN : 1
4997 12:39:00.685370 MD32_EN : 0
4998 12:39:00.688842 ===================================
4999 12:39:00.691893 [ANA_INIT] >>>>>>>>>>>>>>
5000 12:39:00.695364 <<<<<< [CONFIGURE PHASE]: ANA_TX
5001 12:39:00.698808 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5002 12:39:00.701807 ===================================
5003 12:39:00.701894 data_rate = 1866,PCW = 0X8f00
5004 12:39:00.705139 ===================================
5005 12:39:00.711926 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5006 12:39:00.715417 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5007 12:39:00.721910 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5008 12:39:00.725321 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5009 12:39:00.728724 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5010 12:39:00.731767 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5011 12:39:00.735251 [ANA_INIT] flow start
5012 12:39:00.738654 [ANA_INIT] PLL >>>>>>>>
5013 12:39:00.738764 [ANA_INIT] PLL <<<<<<<<
5014 12:39:00.741887 [ANA_INIT] MIDPI >>>>>>>>
5015 12:39:00.745206 [ANA_INIT] MIDPI <<<<<<<<
5016 12:39:00.745317 [ANA_INIT] DLL >>>>>>>>
5017 12:39:00.748395 [ANA_INIT] flow end
5018 12:39:00.751923 ============ LP4 DIFF to SE enter ============
5019 12:39:00.755062 ============ LP4 DIFF to SE exit ============
5020 12:39:00.758575 [ANA_INIT] <<<<<<<<<<<<<
5021 12:39:00.761796 [Flow] Enable top DCM control >>>>>
5022 12:39:00.765250 [Flow] Enable top DCM control <<<<<
5023 12:39:00.768654 Enable DLL master slave shuffle
5024 12:39:00.775303 ==============================================================
5025 12:39:00.775389 Gating Mode config
5026 12:39:00.781722 ==============================================================
5027 12:39:00.781808 Config description:
5028 12:39:00.791846 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5029 12:39:00.798585 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5030 12:39:00.805018 SELPH_MODE 0: By rank 1: By Phase
5031 12:39:00.808191 ==============================================================
5032 12:39:00.811547 GAT_TRACK_EN = 1
5033 12:39:00.815057 RX_GATING_MODE = 2
5034 12:39:00.818325 RX_GATING_TRACK_MODE = 2
5035 12:39:00.821517 SELPH_MODE = 1
5036 12:39:00.825091 PICG_EARLY_EN = 1
5037 12:39:00.828419 VALID_LAT_VALUE = 1
5038 12:39:00.835049 ==============================================================
5039 12:39:00.838082 Enter into Gating configuration >>>>
5040 12:39:00.841273 Exit from Gating configuration <<<<
5041 12:39:00.844754 Enter into DVFS_PRE_config >>>>>
5042 12:39:00.854765 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5043 12:39:00.858101 Exit from DVFS_PRE_config <<<<<
5044 12:39:00.861490 Enter into PICG configuration >>>>
5045 12:39:00.864638 Exit from PICG configuration <<<<
5046 12:39:00.867914 [RX_INPUT] configuration >>>>>
5047 12:39:00.868026 [RX_INPUT] configuration <<<<<
5048 12:39:00.874358 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5049 12:39:00.881118 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5050 12:39:00.884494 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5051 12:39:00.891305 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5052 12:39:00.897626 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5053 12:39:00.904323 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5054 12:39:00.907565 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5055 12:39:00.910777 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5056 12:39:00.917618 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5057 12:39:00.920897 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5058 12:39:00.924319 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5059 12:39:00.930765 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5060 12:39:00.934271 ===================================
5061 12:39:00.934385 LPDDR4 DRAM CONFIGURATION
5062 12:39:00.937346 ===================================
5063 12:39:00.940641 EX_ROW_EN[0] = 0x0
5064 12:39:00.943920 EX_ROW_EN[1] = 0x0
5065 12:39:00.944041 LP4Y_EN = 0x0
5066 12:39:00.947257 WORK_FSP = 0x0
5067 12:39:00.947367 WL = 0x3
5068 12:39:00.950388 RL = 0x3
5069 12:39:00.950489 BL = 0x2
5070 12:39:00.953707 RPST = 0x0
5071 12:39:00.953821 RD_PRE = 0x0
5072 12:39:00.956890 WR_PRE = 0x1
5073 12:39:00.957012 WR_PST = 0x0
5074 12:39:00.960649 DBI_WR = 0x0
5075 12:39:00.960789 DBI_RD = 0x0
5076 12:39:00.963753 OTF = 0x1
5077 12:39:00.966846 ===================================
5078 12:39:00.970298 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5079 12:39:00.973839 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5080 12:39:00.980360 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5081 12:39:00.983683 ===================================
5082 12:39:00.983793 LPDDR4 DRAM CONFIGURATION
5083 12:39:00.986784 ===================================
5084 12:39:00.990057 EX_ROW_EN[0] = 0x10
5085 12:39:00.993286 EX_ROW_EN[1] = 0x0
5086 12:39:00.993397 LP4Y_EN = 0x0
5087 12:39:00.996958 WORK_FSP = 0x0
5088 12:39:00.997071 WL = 0x3
5089 12:39:01.000157 RL = 0x3
5090 12:39:01.000267 BL = 0x2
5091 12:39:01.003362 RPST = 0x0
5092 12:39:01.003476 RD_PRE = 0x0
5093 12:39:01.006689 WR_PRE = 0x1
5094 12:39:01.006799 WR_PST = 0x0
5095 12:39:01.009808 DBI_WR = 0x0
5096 12:39:01.009919 DBI_RD = 0x0
5097 12:39:01.013393 OTF = 0x1
5098 12:39:01.016647 ===================================
5099 12:39:01.023331 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5100 12:39:01.026733 nWR fixed to 30
5101 12:39:01.026840 [ModeRegInit_LP4] CH0 RK0
5102 12:39:01.029926 [ModeRegInit_LP4] CH0 RK1
5103 12:39:01.032987 [ModeRegInit_LP4] CH1 RK0
5104 12:39:01.036429 [ModeRegInit_LP4] CH1 RK1
5105 12:39:01.036513 match AC timing 9
5106 12:39:01.039747 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5107 12:39:01.046345 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5108 12:39:01.049720 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5109 12:39:01.056505 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5110 12:39:01.059593 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5111 12:39:01.059677 ==
5112 12:39:01.062838 Dram Type= 6, Freq= 0, CH_0, rank 0
5113 12:39:01.066354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5114 12:39:01.066471 ==
5115 12:39:01.072755 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5116 12:39:01.079392 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5117 12:39:01.082822 [CA 0] Center 38 (8~69) winsize 62
5118 12:39:01.085907 [CA 1] Center 38 (7~69) winsize 63
5119 12:39:01.089265 [CA 2] Center 35 (5~65) winsize 61
5120 12:39:01.092480 [CA 3] Center 34 (4~65) winsize 62
5121 12:39:01.096132 [CA 4] Center 34 (4~64) winsize 61
5122 12:39:01.099432 [CA 5] Center 33 (3~64) winsize 62
5123 12:39:01.099522
5124 12:39:01.102745 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5125 12:39:01.102830
5126 12:39:01.105846 [CATrainingPosCal] consider 1 rank data
5127 12:39:01.109041 u2DelayCellTimex100 = 270/100 ps
5128 12:39:01.112384 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5129 12:39:01.116066 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5130 12:39:01.119344 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5131 12:39:01.122591 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5132 12:39:01.125699 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5133 12:39:01.128929 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5134 12:39:01.129012
5135 12:39:01.135784 CA PerBit enable=1, Macro0, CA PI delay=33
5136 12:39:01.135902
5137 12:39:01.135969 [CBTSetCACLKResult] CA Dly = 33
5138 12:39:01.139169 CS Dly: 7 (0~38)
5139 12:39:01.139267 ==
5140 12:39:01.142356 Dram Type= 6, Freq= 0, CH_0, rank 1
5141 12:39:01.145619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5142 12:39:01.145705 ==
5143 12:39:01.152408 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5144 12:39:01.158959 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5145 12:39:01.162325 [CA 0] Center 38 (8~69) winsize 62
5146 12:39:01.165658 [CA 1] Center 38 (8~69) winsize 62
5147 12:39:01.169051 [CA 2] Center 35 (5~66) winsize 62
5148 12:39:01.172213 [CA 3] Center 35 (5~66) winsize 62
5149 12:39:01.175567 [CA 4] Center 34 (4~65) winsize 62
5150 12:39:01.178758 [CA 5] Center 33 (3~64) winsize 62
5151 12:39:01.178867
5152 12:39:01.182415 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5153 12:39:01.182521
5154 12:39:01.185392 [CATrainingPosCal] consider 2 rank data
5155 12:39:01.188762 u2DelayCellTimex100 = 270/100 ps
5156 12:39:01.192255 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5157 12:39:01.195346 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5158 12:39:01.198708 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5159 12:39:01.202042 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5160 12:39:01.205229 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5161 12:39:01.212016 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5162 12:39:01.212126
5163 12:39:01.215234 CA PerBit enable=1, Macro0, CA PI delay=33
5164 12:39:01.215340
5165 12:39:01.218439 [CBTSetCACLKResult] CA Dly = 33
5166 12:39:01.218546 CS Dly: 7 (0~39)
5167 12:39:01.218640
5168 12:39:01.221655 ----->DramcWriteLeveling(PI) begin...
5169 12:39:01.221738 ==
5170 12:39:01.224960 Dram Type= 6, Freq= 0, CH_0, rank 0
5171 12:39:01.231731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5172 12:39:01.231824 ==
5173 12:39:01.235098 Write leveling (Byte 0): 31 => 31
5174 12:39:01.235185 Write leveling (Byte 1): 29 => 29
5175 12:39:01.238343 DramcWriteLeveling(PI) end<-----
5176 12:39:01.238429
5177 12:39:01.238496 ==
5178 12:39:01.241655 Dram Type= 6, Freq= 0, CH_0, rank 0
5179 12:39:01.248343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5180 12:39:01.248430 ==
5181 12:39:01.251509 [Gating] SW mode calibration
5182 12:39:01.258293 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5183 12:39:01.261513 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5184 12:39:01.268381 0 14 0 | B1->B0 | 2323 2a2a | 1 0 | (1 1) (0 0)
5185 12:39:01.271421 0 14 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
5186 12:39:01.274762 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5187 12:39:01.281451 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5188 12:39:01.284791 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5189 12:39:01.288060 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5190 12:39:01.294590 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5191 12:39:01.297940 0 14 28 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
5192 12:39:01.301429 0 15 0 | B1->B0 | 3333 2c2c | 1 1 | (1 1) (1 0)
5193 12:39:01.307807 0 15 4 | B1->B0 | 2323 2323 | 1 0 | (1 0) (0 0)
5194 12:39:01.311353 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5195 12:39:01.314570 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5196 12:39:01.320986 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5197 12:39:01.324296 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5198 12:39:01.327553 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5199 12:39:01.334512 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5200 12:39:01.337702 1 0 0 | B1->B0 | 2b2b 3a3a | 0 0 | (0 0) (0 0)
5201 12:39:01.340928 1 0 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5202 12:39:01.347551 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 12:39:01.350941 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5204 12:39:01.354121 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5205 12:39:01.360815 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 12:39:01.363961 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 12:39:01.367369 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 12:39:01.374078 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5209 12:39:01.377454 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5210 12:39:01.380618 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 12:39:01.387294 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 12:39:01.390670 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 12:39:01.393953 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 12:39:01.400553 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 12:39:01.403845 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 12:39:01.407162 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 12:39:01.410251 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 12:39:01.416962 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 12:39:01.420382 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 12:39:01.423660 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 12:39:01.430447 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 12:39:01.433637 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 12:39:01.436985 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5224 12:39:01.443448 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5225 12:39:01.446794 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5226 12:39:01.450055 Total UI for P1: 0, mck2ui 16
5227 12:39:01.453185 best dqsien dly found for B0: ( 1, 2, 30)
5228 12:39:01.456586 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5229 12:39:01.460177 Total UI for P1: 0, mck2ui 16
5230 12:39:01.463279 best dqsien dly found for B1: ( 1, 3, 2)
5231 12:39:01.466464 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5232 12:39:01.469962 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5233 12:39:01.473048
5234 12:39:01.476464 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5235 12:39:01.479905 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5236 12:39:01.483051 [Gating] SW calibration Done
5237 12:39:01.483161 ==
5238 12:39:01.486523 Dram Type= 6, Freq= 0, CH_0, rank 0
5239 12:39:01.489708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5240 12:39:01.489811 ==
5241 12:39:01.489906 RX Vref Scan: 0
5242 12:39:01.489997
5243 12:39:01.493076 RX Vref 0 -> 0, step: 1
5244 12:39:01.493182
5245 12:39:01.496343 RX Delay -80 -> 252, step: 8
5246 12:39:01.499706 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5247 12:39:01.503102 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5248 12:39:01.506551 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5249 12:39:01.512935 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5250 12:39:01.516299 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5251 12:39:01.519576 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5252 12:39:01.522761 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5253 12:39:01.526236 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5254 12:39:01.532791 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5255 12:39:01.536208 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5256 12:39:01.539489 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5257 12:39:01.542653 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5258 12:39:01.546279 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5259 12:39:01.552786 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5260 12:39:01.556027 iDelay=208, Bit 14, Center 95 (-8 ~ 199) 208
5261 12:39:01.559582 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5262 12:39:01.559684 ==
5263 12:39:01.562730 Dram Type= 6, Freq= 0, CH_0, rank 0
5264 12:39:01.565990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5265 12:39:01.566098 ==
5266 12:39:01.569217 DQS Delay:
5267 12:39:01.569321 DQS0 = 0, DQS1 = 0
5268 12:39:01.572875 DQM Delay:
5269 12:39:01.572985 DQM0 = 95, DQM1 = 83
5270 12:39:01.573077 DQ Delay:
5271 12:39:01.576082 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =91
5272 12:39:01.579271 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5273 12:39:01.582578 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5274 12:39:01.586011 DQ12 =87, DQ13 =87, DQ14 =95, DQ15 =91
5275 12:39:01.586114
5276 12:39:01.586208
5277 12:39:01.589209 ==
5278 12:39:01.589310 Dram Type= 6, Freq= 0, CH_0, rank 0
5279 12:39:01.596030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5280 12:39:01.596143 ==
5281 12:39:01.596242
5282 12:39:01.596334
5283 12:39:01.599339 TX Vref Scan disable
5284 12:39:01.599446 == TX Byte 0 ==
5285 12:39:01.602515 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5286 12:39:01.609193 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5287 12:39:01.609311 == TX Byte 1 ==
5288 12:39:01.612304 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5289 12:39:01.619176 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5290 12:39:01.619290 ==
5291 12:39:01.622324 Dram Type= 6, Freq= 0, CH_0, rank 0
5292 12:39:01.625598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 12:39:01.625706 ==
5294 12:39:01.625804
5295 12:39:01.625895
5296 12:39:01.628906 TX Vref Scan disable
5297 12:39:01.632449 == TX Byte 0 ==
5298 12:39:01.635536 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5299 12:39:01.638861 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5300 12:39:01.642204 == TX Byte 1 ==
5301 12:39:01.645569 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5302 12:39:01.648807 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5303 12:39:01.648911
5304 12:39:01.652188 [DATLAT]
5305 12:39:01.652299 Freq=933, CH0 RK0
5306 12:39:01.652394
5307 12:39:01.655679 DATLAT Default: 0xd
5308 12:39:01.655782 0, 0xFFFF, sum = 0
5309 12:39:01.658790 1, 0xFFFF, sum = 0
5310 12:39:01.658912 2, 0xFFFF, sum = 0
5311 12:39:01.662304 3, 0xFFFF, sum = 0
5312 12:39:01.662410 4, 0xFFFF, sum = 0
5313 12:39:01.665794 5, 0xFFFF, sum = 0
5314 12:39:01.665905 6, 0xFFFF, sum = 0
5315 12:39:01.668980 7, 0xFFFF, sum = 0
5316 12:39:01.669091 8, 0xFFFF, sum = 0
5317 12:39:01.672341 9, 0xFFFF, sum = 0
5318 12:39:01.672451 10, 0x0, sum = 1
5319 12:39:01.675340 11, 0x0, sum = 2
5320 12:39:01.675449 12, 0x0, sum = 3
5321 12:39:01.678956 13, 0x0, sum = 4
5322 12:39:01.679067 best_step = 11
5323 12:39:01.679165
5324 12:39:01.679256 ==
5325 12:39:01.682229 Dram Type= 6, Freq= 0, CH_0, rank 0
5326 12:39:01.685337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5327 12:39:01.688819 ==
5328 12:39:01.688923 RX Vref Scan: 1
5329 12:39:01.689021
5330 12:39:01.692039 RX Vref 0 -> 0, step: 1
5331 12:39:01.692145
5332 12:39:01.695380 RX Delay -69 -> 252, step: 4
5333 12:39:01.695493
5334 12:39:01.698529 Set Vref, RX VrefLevel [Byte0]: 62
5335 12:39:01.701689 [Byte1]: 54
5336 12:39:01.701796
5337 12:39:01.705051 Final RX Vref Byte 0 = 62 to rank0
5338 12:39:01.708660 Final RX Vref Byte 1 = 54 to rank0
5339 12:39:01.711823 Final RX Vref Byte 0 = 62 to rank1
5340 12:39:01.715028 Final RX Vref Byte 1 = 54 to rank1==
5341 12:39:01.718420 Dram Type= 6, Freq= 0, CH_0, rank 0
5342 12:39:01.721723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5343 12:39:01.721835 ==
5344 12:39:01.725018 DQS Delay:
5345 12:39:01.725122 DQS0 = 0, DQS1 = 0
5346 12:39:01.725229 DQM Delay:
5347 12:39:01.728662 DQM0 = 95, DQM1 = 84
5348 12:39:01.728763 DQ Delay:
5349 12:39:01.731633 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5350 12:39:01.734954 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =108
5351 12:39:01.738181 DQ8 =78, DQ9 =72, DQ10 =82, DQ11 =80
5352 12:39:01.741777 DQ12 =88, DQ13 =88, DQ14 =96, DQ15 =90
5353 12:39:01.741883
5354 12:39:01.741978
5355 12:39:01.751441 [DQSOSCAuto] RK0, (LSB)MR18= 0x1615, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 414 ps
5356 12:39:01.754927 CH0 RK0: MR19=505, MR18=1615
5357 12:39:01.758095 CH0_RK0: MR19=0x505, MR18=0x1615, DQSOSC=414, MR23=63, INC=63, DEC=42
5358 12:39:01.758202
5359 12:39:01.761480 ----->DramcWriteLeveling(PI) begin...
5360 12:39:01.764782 ==
5361 12:39:01.764891 Dram Type= 6, Freq= 0, CH_0, rank 1
5362 12:39:01.771716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5363 12:39:01.771827 ==
5364 12:39:01.774913 Write leveling (Byte 0): 33 => 33
5365 12:39:01.778108 Write leveling (Byte 1): 29 => 29
5366 12:39:01.781365 DramcWriteLeveling(PI) end<-----
5367 12:39:01.781466
5368 12:39:01.781542 ==
5369 12:39:01.784878 Dram Type= 6, Freq= 0, CH_0, rank 1
5370 12:39:01.788202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5371 12:39:01.788314 ==
5372 12:39:01.791434 [Gating] SW mode calibration
5373 12:39:01.798254 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5374 12:39:01.801433 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5375 12:39:01.808103 0 14 0 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
5376 12:39:01.811315 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5377 12:39:01.814583 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5378 12:39:01.821585 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5379 12:39:01.824730 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5380 12:39:01.828001 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5381 12:39:01.834805 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5382 12:39:01.838175 0 14 28 | B1->B0 | 3333 2b2b | 0 0 | (0 0) (0 0)
5383 12:39:01.841447 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
5384 12:39:01.847988 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5385 12:39:01.851384 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5386 12:39:01.854855 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5387 12:39:01.861203 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5388 12:39:01.864596 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5389 12:39:01.867739 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5390 12:39:01.874389 0 15 28 | B1->B0 | 2727 3030 | 0 1 | (0 0) (0 0)
5391 12:39:01.877669 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5392 12:39:01.881055 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 12:39:01.887594 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 12:39:01.890751 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5395 12:39:01.894349 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 12:39:01.900628 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 12:39:01.904032 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 12:39:01.907310 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5399 12:39:01.914152 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5400 12:39:01.917521 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 12:39:01.920850 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 12:39:01.927300 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 12:39:01.930813 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 12:39:01.934357 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 12:39:01.940803 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 12:39:01.944095 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 12:39:01.947363 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 12:39:01.954095 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 12:39:01.957363 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 12:39:01.960629 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 12:39:01.964080 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 12:39:01.970639 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 12:39:01.974178 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 12:39:01.977451 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5415 12:39:01.980990 Total UI for P1: 0, mck2ui 16
5416 12:39:01.984191 best dqsien dly found for B0: ( 1, 2, 26)
5417 12:39:01.990633 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5418 12:39:01.994095 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5419 12:39:01.997282 Total UI for P1: 0, mck2ui 16
5420 12:39:02.000828 best dqsien dly found for B1: ( 1, 2, 30)
5421 12:39:02.004024 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5422 12:39:02.007310 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5423 12:39:02.007421
5424 12:39:02.010617 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5425 12:39:02.014261 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5426 12:39:02.017336 [Gating] SW calibration Done
5427 12:39:02.017439 ==
5428 12:39:02.020631 Dram Type= 6, Freq= 0, CH_0, rank 1
5429 12:39:02.024154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5430 12:39:02.027420 ==
5431 12:39:02.027523 RX Vref Scan: 0
5432 12:39:02.027626
5433 12:39:02.030602 RX Vref 0 -> 0, step: 1
5434 12:39:02.030701
5435 12:39:02.033995 RX Delay -80 -> 252, step: 8
5436 12:39:02.037365 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5437 12:39:02.040448 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5438 12:39:02.043784 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5439 12:39:02.047089 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5440 12:39:02.053784 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5441 12:39:02.057408 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5442 12:39:02.060471 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5443 12:39:02.063958 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5444 12:39:02.067087 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5445 12:39:02.070594 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5446 12:39:02.076988 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5447 12:39:02.080275 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5448 12:39:02.083596 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5449 12:39:02.087078 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5450 12:39:02.090334 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5451 12:39:02.096719 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5452 12:39:02.096798 ==
5453 12:39:02.100170 Dram Type= 6, Freq= 0, CH_0, rank 1
5454 12:39:02.103512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5455 12:39:02.103624 ==
5456 12:39:02.103730 DQS Delay:
5457 12:39:02.106755 DQS0 = 0, DQS1 = 0
5458 12:39:02.106857 DQM Delay:
5459 12:39:02.110007 DQM0 = 91, DQM1 = 84
5460 12:39:02.110109 DQ Delay:
5461 12:39:02.113535 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5462 12:39:02.116797 DQ4 =91, DQ5 =79, DQ6 =99, DQ7 =107
5463 12:39:02.120272 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
5464 12:39:02.123320 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5465 12:39:02.123433
5466 12:39:02.123525
5467 12:39:02.123626 ==
5468 12:39:02.126875 Dram Type= 6, Freq= 0, CH_0, rank 1
5469 12:39:02.130176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5470 12:39:02.133202 ==
5471 12:39:02.133325
5472 12:39:02.133424
5473 12:39:02.133560 TX Vref Scan disable
5474 12:39:02.136766 == TX Byte 0 ==
5475 12:39:02.139845 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5476 12:39:02.143456 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5477 12:39:02.146700 == TX Byte 1 ==
5478 12:39:02.149973 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5479 12:39:02.153174 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5480 12:39:02.156463 ==
5481 12:39:02.156565 Dram Type= 6, Freq= 0, CH_0, rank 1
5482 12:39:02.162985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5483 12:39:02.163089 ==
5484 12:39:02.163182
5485 12:39:02.163274
5486 12:39:02.166593 TX Vref Scan disable
5487 12:39:02.166701 == TX Byte 0 ==
5488 12:39:02.173021 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5489 12:39:02.176280 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5490 12:39:02.176384 == TX Byte 1 ==
5491 12:39:02.183041 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5492 12:39:02.186166 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5493 12:39:02.186265
5494 12:39:02.186359 [DATLAT]
5495 12:39:02.189675 Freq=933, CH0 RK1
5496 12:39:02.189775
5497 12:39:02.189869 DATLAT Default: 0xb
5498 12:39:02.192793 0, 0xFFFF, sum = 0
5499 12:39:02.192896 1, 0xFFFF, sum = 0
5500 12:39:02.196239 2, 0xFFFF, sum = 0
5501 12:39:02.196326 3, 0xFFFF, sum = 0
5502 12:39:02.199417 4, 0xFFFF, sum = 0
5503 12:39:02.199503 5, 0xFFFF, sum = 0
5504 12:39:02.202993 6, 0xFFFF, sum = 0
5505 12:39:02.203109 7, 0xFFFF, sum = 0
5506 12:39:02.206173 8, 0xFFFF, sum = 0
5507 12:39:02.209545 9, 0xFFFF, sum = 0
5508 12:39:02.209690 10, 0x0, sum = 1
5509 12:39:02.209804 11, 0x0, sum = 2
5510 12:39:02.212711 12, 0x0, sum = 3
5511 12:39:02.212796 13, 0x0, sum = 4
5512 12:39:02.216208 best_step = 11
5513 12:39:02.216305
5514 12:39:02.216371 ==
5515 12:39:02.219452 Dram Type= 6, Freq= 0, CH_0, rank 1
5516 12:39:02.222684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5517 12:39:02.222768 ==
5518 12:39:02.225994 RX Vref Scan: 0
5519 12:39:02.226081
5520 12:39:02.226147 RX Vref 0 -> 0, step: 1
5521 12:39:02.226210
5522 12:39:02.229283 RX Delay -69 -> 252, step: 4
5523 12:39:02.236642 iDelay=199, Bit 0, Center 90 (-1 ~ 182) 184
5524 12:39:02.240344 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5525 12:39:02.243394 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5526 12:39:02.246955 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5527 12:39:02.250275 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5528 12:39:02.253458 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5529 12:39:02.260256 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5530 12:39:02.263606 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5531 12:39:02.266850 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5532 12:39:02.270111 iDelay=199, Bit 9, Center 70 (-17 ~ 158) 176
5533 12:39:02.273644 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5534 12:39:02.279975 iDelay=199, Bit 11, Center 80 (-9 ~ 170) 180
5535 12:39:02.283308 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5536 12:39:02.286727 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5537 12:39:02.290037 iDelay=199, Bit 14, Center 92 (-1 ~ 186) 188
5538 12:39:02.293272 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5539 12:39:02.296401 ==
5540 12:39:02.296505 Dram Type= 6, Freq= 0, CH_0, rank 1
5541 12:39:02.303417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5542 12:39:02.303505 ==
5543 12:39:02.303619 DQS Delay:
5544 12:39:02.306546 DQS0 = 0, DQS1 = 0
5545 12:39:02.306623 DQM Delay:
5546 12:39:02.309945 DQM0 = 92, DQM1 = 85
5547 12:39:02.310020 DQ Delay:
5548 12:39:02.313246 DQ0 =90, DQ1 =94, DQ2 =90, DQ3 =88
5549 12:39:02.316605 DQ4 =92, DQ5 =82, DQ6 =104, DQ7 =102
5550 12:39:02.319627 DQ8 =78, DQ9 =70, DQ10 =86, DQ11 =80
5551 12:39:02.323085 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
5552 12:39:02.323194
5553 12:39:02.323295
5554 12:39:02.330007 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5555 12:39:02.333206 CH0 RK1: MR19=505, MR18=2D0E
5556 12:39:02.339720 CH0_RK1: MR19=0x505, MR18=0x2D0E, DQSOSC=407, MR23=63, INC=65, DEC=43
5557 12:39:02.343314 [RxdqsGatingPostProcess] freq 933
5558 12:39:02.349760 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5559 12:39:02.349881 best DQS0 dly(2T, 0.5T) = (0, 10)
5560 12:39:02.353232 best DQS1 dly(2T, 0.5T) = (0, 11)
5561 12:39:02.356450 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5562 12:39:02.359722 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5563 12:39:02.363077 best DQS0 dly(2T, 0.5T) = (0, 10)
5564 12:39:02.366404 best DQS1 dly(2T, 0.5T) = (0, 10)
5565 12:39:02.369458 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5566 12:39:02.372726 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5567 12:39:02.376419 Pre-setting of DQS Precalculation
5568 12:39:02.382743 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5569 12:39:02.382857 ==
5570 12:39:02.385918 Dram Type= 6, Freq= 0, CH_1, rank 0
5571 12:39:02.389454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5572 12:39:02.389544 ==
5573 12:39:02.395954 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5574 12:39:02.399029 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5575 12:39:02.403185 [CA 0] Center 37 (7~67) winsize 61
5576 12:39:02.406679 [CA 1] Center 37 (7~67) winsize 61
5577 12:39:02.409593 [CA 2] Center 34 (5~64) winsize 60
5578 12:39:02.413275 [CA 3] Center 34 (5~64) winsize 60
5579 12:39:02.416355 [CA 4] Center 34 (5~64) winsize 60
5580 12:39:02.419851 [CA 5] Center 34 (4~64) winsize 61
5581 12:39:02.419959
5582 12:39:02.423018 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5583 12:39:02.423119
5584 12:39:02.426452 [CATrainingPosCal] consider 1 rank data
5585 12:39:02.429648 u2DelayCellTimex100 = 270/100 ps
5586 12:39:02.432798 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5587 12:39:02.439403 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5588 12:39:02.443006 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5589 12:39:02.445973 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5590 12:39:02.449200 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5591 12:39:02.452658 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5592 12:39:02.452767
5593 12:39:02.456195 CA PerBit enable=1, Macro0, CA PI delay=34
5594 12:39:02.456307
5595 12:39:02.459307 [CBTSetCACLKResult] CA Dly = 34
5596 12:39:02.462705 CS Dly: 6 (0~37)
5597 12:39:02.462815 ==
5598 12:39:02.465980 Dram Type= 6, Freq= 0, CH_1, rank 1
5599 12:39:02.469077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5600 12:39:02.469185 ==
5601 12:39:02.476099 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5602 12:39:02.479311 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5603 12:39:02.483031 [CA 0] Center 37 (7~68) winsize 62
5604 12:39:02.486433 [CA 1] Center 37 (7~68) winsize 62
5605 12:39:02.489962 [CA 2] Center 35 (5~65) winsize 61
5606 12:39:02.493234 [CA 3] Center 34 (4~64) winsize 61
5607 12:39:02.496413 [CA 4] Center 35 (5~65) winsize 61
5608 12:39:02.499749 [CA 5] Center 34 (4~64) winsize 61
5609 12:39:02.499855
5610 12:39:02.503043 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5611 12:39:02.503151
5612 12:39:02.506190 [CATrainingPosCal] consider 2 rank data
5613 12:39:02.509698 u2DelayCellTimex100 = 270/100 ps
5614 12:39:02.512880 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5615 12:39:02.519602 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5616 12:39:02.522816 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5617 12:39:02.526231 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5618 12:39:02.529373 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5619 12:39:02.532789 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5620 12:39:02.532898
5621 12:39:02.536021 CA PerBit enable=1, Macro0, CA PI delay=34
5622 12:39:02.536147
5623 12:39:02.539277 [CBTSetCACLKResult] CA Dly = 34
5624 12:39:02.542599 CS Dly: 6 (0~38)
5625 12:39:02.542718
5626 12:39:02.545955 ----->DramcWriteLeveling(PI) begin...
5627 12:39:02.546073 ==
5628 12:39:02.549260 Dram Type= 6, Freq= 0, CH_1, rank 0
5629 12:39:02.552564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5630 12:39:02.552713 ==
5631 12:39:02.555796 Write leveling (Byte 0): 27 => 27
5632 12:39:02.559353 Write leveling (Byte 1): 28 => 28
5633 12:39:02.562589 DramcWriteLeveling(PI) end<-----
5634 12:39:02.562702
5635 12:39:02.562798 ==
5636 12:39:02.565776 Dram Type= 6, Freq= 0, CH_1, rank 0
5637 12:39:02.569082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5638 12:39:02.569191 ==
5639 12:39:02.572373 [Gating] SW mode calibration
5640 12:39:02.579095 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5641 12:39:02.585723 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5642 12:39:02.589374 0 14 0 | B1->B0 | 3030 3333 | 1 1 | (0 0) (1 1)
5643 12:39:02.592314 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5644 12:39:02.598933 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5645 12:39:02.602210 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5646 12:39:02.605727 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5647 12:39:02.612170 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5648 12:39:02.615462 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5649 12:39:02.618664 0 14 28 | B1->B0 | 2f2f 2e2e | 1 0 | (1 0) (0 1)
5650 12:39:02.625413 0 15 0 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
5651 12:39:02.628941 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5652 12:39:02.632207 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5653 12:39:02.638718 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5654 12:39:02.641887 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5655 12:39:02.645282 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5656 12:39:02.651957 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5657 12:39:02.655338 0 15 28 | B1->B0 | 2f2f 3030 | 0 0 | (0 0) (0 0)
5658 12:39:02.658586 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5659 12:39:02.665351 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 12:39:02.668413 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5661 12:39:02.671946 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 12:39:02.678351 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5663 12:39:02.681586 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 12:39:02.684951 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5665 12:39:02.691687 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5666 12:39:02.695054 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 12:39:02.698089 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 12:39:02.701586 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 12:39:02.708185 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 12:39:02.711445 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 12:39:02.714711 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 12:39:02.721472 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 12:39:02.724663 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 12:39:02.728253 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 12:39:02.734803 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 12:39:02.738079 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 12:39:02.741301 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 12:39:02.748020 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 12:39:02.751255 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 12:39:02.754699 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 12:39:02.761266 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5682 12:39:02.764582 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5683 12:39:02.769470 Total UI for P1: 0, mck2ui 16
5684 12:39:02.771298 best dqsien dly found for B0: ( 1, 2, 30)
5685 12:39:02.774500 Total UI for P1: 0, mck2ui 16
5686 12:39:02.777792 best dqsien dly found for B1: ( 1, 2, 28)
5687 12:39:02.781018 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5688 12:39:02.784617 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5689 12:39:02.784698
5690 12:39:02.787816 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5691 12:39:02.791138 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5692 12:39:02.794493 [Gating] SW calibration Done
5693 12:39:02.794581 ==
5694 12:39:02.797704 Dram Type= 6, Freq= 0, CH_1, rank 0
5695 12:39:02.800919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5696 12:39:02.804465 ==
5697 12:39:02.804575 RX Vref Scan: 0
5698 12:39:02.804674
5699 12:39:02.807755 RX Vref 0 -> 0, step: 1
5700 12:39:02.807859
5701 12:39:02.811005 RX Delay -80 -> 252, step: 8
5702 12:39:02.814404 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5703 12:39:02.817803 iDelay=208, Bit 1, Center 87 (-16 ~ 191) 208
5704 12:39:02.821074 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5705 12:39:02.824206 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5706 12:39:02.830777 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5707 12:39:02.834053 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5708 12:39:02.837348 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5709 12:39:02.840818 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5710 12:39:02.844053 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5711 12:39:02.847599 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5712 12:39:02.853887 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5713 12:39:02.857541 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5714 12:39:02.860728 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5715 12:39:02.863936 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5716 12:39:02.867355 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5717 12:39:02.873934 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5718 12:39:02.874020 ==
5719 12:39:02.877208 Dram Type= 6, Freq= 0, CH_1, rank 0
5720 12:39:02.880755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5721 12:39:02.880842 ==
5722 12:39:02.880913 DQS Delay:
5723 12:39:02.883975 DQS0 = 0, DQS1 = 0
5724 12:39:02.884065 DQM Delay:
5725 12:39:02.887396 DQM0 = 94, DQM1 = 87
5726 12:39:02.887482 DQ Delay:
5727 12:39:02.890579 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =95
5728 12:39:02.893711 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =95
5729 12:39:02.896969 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5730 12:39:02.900646 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =91
5731 12:39:02.900732
5732 12:39:02.900800
5733 12:39:02.900863 ==
5734 12:39:02.903854 Dram Type= 6, Freq= 0, CH_1, rank 0
5735 12:39:02.907172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5736 12:39:02.907258 ==
5737 12:39:02.907326
5738 12:39:02.910288
5739 12:39:02.910373 TX Vref Scan disable
5740 12:39:02.913573 == TX Byte 0 ==
5741 12:39:02.917197 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5742 12:39:02.920333 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5743 12:39:02.923794 == TX Byte 1 ==
5744 12:39:02.927197 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5745 12:39:02.930598 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5746 12:39:02.930684 ==
5747 12:39:02.933812 Dram Type= 6, Freq= 0, CH_1, rank 0
5748 12:39:02.940525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 12:39:02.940615 ==
5750 12:39:02.940682
5751 12:39:02.940744
5752 12:39:02.940805 TX Vref Scan disable
5753 12:39:02.944290 == TX Byte 0 ==
5754 12:39:02.947736 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5755 12:39:02.954255 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5756 12:39:02.954367 == TX Byte 1 ==
5757 12:39:02.957825 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5758 12:39:02.964343 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5759 12:39:02.964456
5760 12:39:02.964540 [DATLAT]
5761 12:39:02.964607 Freq=933, CH1 RK0
5762 12:39:02.964670
5763 12:39:02.967545 DATLAT Default: 0xd
5764 12:39:02.967657 0, 0xFFFF, sum = 0
5765 12:39:02.970787 1, 0xFFFF, sum = 0
5766 12:39:02.974394 2, 0xFFFF, sum = 0
5767 12:39:02.974483 3, 0xFFFF, sum = 0
5768 12:39:02.977777 4, 0xFFFF, sum = 0
5769 12:39:02.977865 5, 0xFFFF, sum = 0
5770 12:39:02.981017 6, 0xFFFF, sum = 0
5771 12:39:02.981104 7, 0xFFFF, sum = 0
5772 12:39:02.984027 8, 0xFFFF, sum = 0
5773 12:39:02.984142 9, 0xFFFF, sum = 0
5774 12:39:02.987310 10, 0x0, sum = 1
5775 12:39:02.987425 11, 0x0, sum = 2
5776 12:39:02.990998 12, 0x0, sum = 3
5777 12:39:02.991085 13, 0x0, sum = 4
5778 12:39:02.991154 best_step = 11
5779 12:39:02.991217
5780 12:39:02.994383 ==
5781 12:39:02.997582 Dram Type= 6, Freq= 0, CH_1, rank 0
5782 12:39:03.000647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5783 12:39:03.000762 ==
5784 12:39:03.000864 RX Vref Scan: 1
5785 12:39:03.000956
5786 12:39:03.003874 RX Vref 0 -> 0, step: 1
5787 12:39:03.003978
5788 12:39:03.007569 RX Delay -69 -> 252, step: 4
5789 12:39:03.007683
5790 12:39:03.010510 Set Vref, RX VrefLevel [Byte0]: 56
5791 12:39:03.014170 [Byte1]: 48
5792 12:39:03.014259
5793 12:39:03.017354 Final RX Vref Byte 0 = 56 to rank0
5794 12:39:03.020529 Final RX Vref Byte 1 = 48 to rank0
5795 12:39:03.024083 Final RX Vref Byte 0 = 56 to rank1
5796 12:39:03.027377 Final RX Vref Byte 1 = 48 to rank1==
5797 12:39:03.030618 Dram Type= 6, Freq= 0, CH_1, rank 0
5798 12:39:03.033695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5799 12:39:03.037250 ==
5800 12:39:03.037363 DQS Delay:
5801 12:39:03.037460 DQS0 = 0, DQS1 = 0
5802 12:39:03.040531 DQM Delay:
5803 12:39:03.040643 DQM0 = 96, DQM1 = 88
5804 12:39:03.043700 DQ Delay:
5805 12:39:03.047203 DQ0 =102, DQ1 =92, DQ2 =84, DQ3 =92
5806 12:39:03.050335 DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =92
5807 12:39:03.053979 DQ8 =76, DQ9 =80, DQ10 =88, DQ11 =80
5808 12:39:03.057027 DQ12 =96, DQ13 =94, DQ14 =96, DQ15 =94
5809 12:39:03.057144
5810 12:39:03.057243
5811 12:39:03.063727 [DQSOSCAuto] RK0, (LSB)MR18= 0x10a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 421 ps
5812 12:39:03.066960 CH1 RK0: MR19=505, MR18=10A
5813 12:39:03.073763 CH1_RK0: MR19=0x505, MR18=0x10A, DQSOSC=418, MR23=63, INC=62, DEC=41
5814 12:39:03.073853
5815 12:39:03.076940 ----->DramcWriteLeveling(PI) begin...
5816 12:39:03.077020 ==
5817 12:39:03.080255 Dram Type= 6, Freq= 0, CH_1, rank 1
5818 12:39:03.083513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5819 12:39:03.083600 ==
5820 12:39:03.087033 Write leveling (Byte 0): 25 => 25
5821 12:39:03.090106 Write leveling (Byte 1): 28 => 28
5822 12:39:03.093445 DramcWriteLeveling(PI) end<-----
5823 12:39:03.093574
5824 12:39:03.093667 ==
5825 12:39:03.097029 Dram Type= 6, Freq= 0, CH_1, rank 1
5826 12:39:03.100033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5827 12:39:03.100143 ==
5828 12:39:03.103345 [Gating] SW mode calibration
5829 12:39:03.110036 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5830 12:39:03.116891 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5831 12:39:03.120117 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
5832 12:39:03.123311 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5833 12:39:03.129888 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5834 12:39:03.133421 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5835 12:39:03.136686 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5836 12:39:03.143304 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5837 12:39:03.146383 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
5838 12:39:03.150080 0 14 28 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
5839 12:39:03.156533 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5840 12:39:03.159857 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5841 12:39:03.163364 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5842 12:39:03.169777 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5843 12:39:03.172938 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5844 12:39:03.176380 0 15 20 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
5845 12:39:03.182935 0 15 24 | B1->B0 | 2727 3333 | 0 0 | (0 0) (0 0)
5846 12:39:03.186300 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5847 12:39:03.189514 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5848 12:39:03.196145 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5849 12:39:03.199527 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5850 12:39:03.203092 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5851 12:39:03.209389 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5852 12:39:03.212868 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5853 12:39:03.216122 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5854 12:39:03.222590 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5855 12:39:03.226143 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 12:39:03.229213 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 12:39:03.235911 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 12:39:03.239131 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 12:39:03.242661 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 12:39:03.249233 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 12:39:03.252434 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 12:39:03.255698 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 12:39:03.262463 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 12:39:03.265548 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 12:39:03.269155 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 12:39:03.275756 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 12:39:03.278970 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 12:39:03.282246 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5869 12:39:03.288829 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5870 12:39:03.291980 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5871 12:39:03.295272 Total UI for P1: 0, mck2ui 16
5872 12:39:03.298458 best dqsien dly found for B0: ( 1, 2, 22)
5873 12:39:03.302042 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5874 12:39:03.305334 Total UI for P1: 0, mck2ui 16
5875 12:39:03.308343 best dqsien dly found for B1: ( 1, 2, 26)
5876 12:39:03.311967 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5877 12:39:03.315223 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5878 12:39:03.315333
5879 12:39:03.318773 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5880 12:39:03.325334 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5881 12:39:03.325460 [Gating] SW calibration Done
5882 12:39:03.325583 ==
5883 12:39:03.328616 Dram Type= 6, Freq= 0, CH_1, rank 1
5884 12:39:03.335313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5885 12:39:03.335425 ==
5886 12:39:03.335520 RX Vref Scan: 0
5887 12:39:03.335611
5888 12:39:03.338318 RX Vref 0 -> 0, step: 1
5889 12:39:03.338402
5890 12:39:03.341851 RX Delay -80 -> 252, step: 8
5891 12:39:03.345204 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5892 12:39:03.348336 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5893 12:39:03.351722 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5894 12:39:03.358403 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5895 12:39:03.361652 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5896 12:39:03.364803 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5897 12:39:03.368220 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5898 12:39:03.371449 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5899 12:39:03.375097 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5900 12:39:03.381433 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5901 12:39:03.385064 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5902 12:39:03.388390 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5903 12:39:03.391644 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5904 12:39:03.394781 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5905 12:39:03.401398 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5906 12:39:03.404763 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5907 12:39:03.404847 ==
5908 12:39:03.408038 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 12:39:03.411633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 12:39:03.411717 ==
5911 12:39:03.411785 DQS Delay:
5912 12:39:03.414688 DQS0 = 0, DQS1 = 0
5913 12:39:03.414792 DQM Delay:
5914 12:39:03.418405 DQM0 = 93, DQM1 = 88
5915 12:39:03.418488 DQ Delay:
5916 12:39:03.421730 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =91
5917 12:39:03.424690 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5918 12:39:03.428415 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =79
5919 12:39:03.431530 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5920 12:39:03.431614
5921 12:39:03.431679
5922 12:39:03.431741 ==
5923 12:39:03.434880 Dram Type= 6, Freq= 0, CH_1, rank 1
5924 12:39:03.438157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5925 12:39:03.441357 ==
5926 12:39:03.441470
5927 12:39:03.441549
5928 12:39:03.441628 TX Vref Scan disable
5929 12:39:03.444617 == TX Byte 0 ==
5930 12:39:03.447906 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5931 12:39:03.451085 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5932 12:39:03.454466 == TX Byte 1 ==
5933 12:39:03.458014 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5934 12:39:03.464665 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5935 12:39:03.464790 ==
5936 12:39:03.467917 Dram Type= 6, Freq= 0, CH_1, rank 1
5937 12:39:03.471063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5938 12:39:03.471142 ==
5939 12:39:03.471207
5940 12:39:03.471267
5941 12:39:03.474465 TX Vref Scan disable
5942 12:39:03.474570 == TX Byte 0 ==
5943 12:39:03.480987 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5944 12:39:03.484167 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5945 12:39:03.484296 == TX Byte 1 ==
5946 12:39:03.491260 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5947 12:39:03.494564 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5948 12:39:03.494649
5949 12:39:03.494714 [DATLAT]
5950 12:39:03.497416 Freq=933, CH1 RK1
5951 12:39:03.497539
5952 12:39:03.497611 DATLAT Default: 0xb
5953 12:39:03.500913 0, 0xFFFF, sum = 0
5954 12:39:03.501025 1, 0xFFFF, sum = 0
5955 12:39:03.504598 2, 0xFFFF, sum = 0
5956 12:39:03.504683 3, 0xFFFF, sum = 0
5957 12:39:03.507512 4, 0xFFFF, sum = 0
5958 12:39:03.507628 5, 0xFFFF, sum = 0
5959 12:39:03.511071 6, 0xFFFF, sum = 0
5960 12:39:03.514332 7, 0xFFFF, sum = 0
5961 12:39:03.514417 8, 0xFFFF, sum = 0
5962 12:39:03.517429 9, 0xFFFF, sum = 0
5963 12:39:03.517550 10, 0x0, sum = 1
5964 12:39:03.517620 11, 0x0, sum = 2
5965 12:39:03.520811 12, 0x0, sum = 3
5966 12:39:03.520897 13, 0x0, sum = 4
5967 12:39:03.524158 best_step = 11
5968 12:39:03.524267
5969 12:39:03.524360 ==
5970 12:39:03.527603 Dram Type= 6, Freq= 0, CH_1, rank 1
5971 12:39:03.530753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5972 12:39:03.530882 ==
5973 12:39:03.534069 RX Vref Scan: 0
5974 12:39:03.534215
5975 12:39:03.534311 RX Vref 0 -> 0, step: 1
5976 12:39:03.537328
5977 12:39:03.537438 RX Delay -69 -> 252, step: 4
5978 12:39:03.545245 iDelay=203, Bit 0, Center 94 (-5 ~ 194) 200
5979 12:39:03.548296 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5980 12:39:03.551683 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5981 12:39:03.554980 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5982 12:39:03.558422 iDelay=203, Bit 4, Center 88 (-9 ~ 186) 196
5983 12:39:03.564747 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5984 12:39:03.568269 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
5985 12:39:03.571412 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5986 12:39:03.574683 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5987 12:39:03.578157 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5988 12:39:03.581378 iDelay=203, Bit 10, Center 94 (3 ~ 186) 184
5989 12:39:03.588024 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5990 12:39:03.591568 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5991 12:39:03.594589 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5992 12:39:03.598122 iDelay=203, Bit 14, Center 100 (15 ~ 186) 172
5993 12:39:03.601123 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5994 12:39:03.604669 ==
5995 12:39:03.604756 Dram Type= 6, Freq= 0, CH_1, rank 1
5996 12:39:03.611368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5997 12:39:03.611456 ==
5998 12:39:03.611525 DQS Delay:
5999 12:39:03.614596 DQS0 = 0, DQS1 = 0
6000 12:39:03.614681 DQM Delay:
6001 12:39:03.617799 DQM0 = 91, DQM1 = 91
6002 12:39:03.617885 DQ Delay:
6003 12:39:03.621092 DQ0 =94, DQ1 =86, DQ2 =82, DQ3 =88
6004 12:39:03.624300 DQ4 =88, DQ5 =102, DQ6 =102, DQ7 =88
6005 12:39:03.627860 DQ8 =78, DQ9 =82, DQ10 =94, DQ11 =84
6006 12:39:03.631090 DQ12 =98, DQ13 =98, DQ14 =100, DQ15 =96
6007 12:39:03.631179
6008 12:39:03.631247
6009 12:39:03.637610 [DQSOSCAuto] RK1, (LSB)MR18= 0x1528, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 415 ps
6010 12:39:03.640878 CH1 RK1: MR19=505, MR18=1528
6011 12:39:03.647730 CH1_RK1: MR19=0x505, MR18=0x1528, DQSOSC=409, MR23=63, INC=64, DEC=43
6012 12:39:03.651055 [RxdqsGatingPostProcess] freq 933
6013 12:39:03.657668 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6014 12:39:03.660781 best DQS0 dly(2T, 0.5T) = (0, 10)
6015 12:39:03.660894 best DQS1 dly(2T, 0.5T) = (0, 10)
6016 12:39:03.663880 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6017 12:39:03.667504 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6018 12:39:03.670808 best DQS0 dly(2T, 0.5T) = (0, 10)
6019 12:39:03.674070 best DQS1 dly(2T, 0.5T) = (0, 10)
6020 12:39:03.677391 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6021 12:39:03.680716 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6022 12:39:03.683868 Pre-setting of DQS Precalculation
6023 12:39:03.690682 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6024 12:39:03.697201 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6025 12:39:03.703961 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6026 12:39:03.704069
6027 12:39:03.704163
6028 12:39:03.707118 [Calibration Summary] 1866 Mbps
6029 12:39:03.707281 CH 0, Rank 0
6030 12:39:03.710333 SW Impedance : PASS
6031 12:39:03.713824 DUTY Scan : NO K
6032 12:39:03.713899 ZQ Calibration : PASS
6033 12:39:03.717255 Jitter Meter : NO K
6034 12:39:03.720596 CBT Training : PASS
6035 12:39:03.720670 Write leveling : PASS
6036 12:39:03.723835 RX DQS gating : PASS
6037 12:39:03.723911 RX DQ/DQS(RDDQC) : PASS
6038 12:39:03.727002 TX DQ/DQS : PASS
6039 12:39:03.730260 RX DATLAT : PASS
6040 12:39:03.730331 RX DQ/DQS(Engine): PASS
6041 12:39:03.733756 TX OE : NO K
6042 12:39:03.733826 All Pass.
6043 12:39:03.733889
6044 12:39:03.737268 CH 0, Rank 1
6045 12:39:03.737413 SW Impedance : PASS
6046 12:39:03.740274 DUTY Scan : NO K
6047 12:39:03.743762 ZQ Calibration : PASS
6048 12:39:03.743869 Jitter Meter : NO K
6049 12:39:03.746955 CBT Training : PASS
6050 12:39:03.750611 Write leveling : PASS
6051 12:39:03.750714 RX DQS gating : PASS
6052 12:39:03.753389 RX DQ/DQS(RDDQC) : PASS
6053 12:39:03.757083 TX DQ/DQS : PASS
6054 12:39:03.757183 RX DATLAT : PASS
6055 12:39:03.760186 RX DQ/DQS(Engine): PASS
6056 12:39:03.763478 TX OE : NO K
6057 12:39:03.763580 All Pass.
6058 12:39:03.763680
6059 12:39:03.763768 CH 1, Rank 0
6060 12:39:03.767007 SW Impedance : PASS
6061 12:39:03.770090 DUTY Scan : NO K
6062 12:39:03.770199 ZQ Calibration : PASS
6063 12:39:03.773514 Jitter Meter : NO K
6064 12:39:03.776720 CBT Training : PASS
6065 12:39:03.776817 Write leveling : PASS
6066 12:39:03.779998 RX DQS gating : PASS
6067 12:39:03.780068 RX DQ/DQS(RDDQC) : PASS
6068 12:39:03.783199 TX DQ/DQS : PASS
6069 12:39:03.786564 RX DATLAT : PASS
6070 12:39:03.786641 RX DQ/DQS(Engine): PASS
6071 12:39:03.790091 TX OE : NO K
6072 12:39:03.790176 All Pass.
6073 12:39:03.790248
6074 12:39:03.793423 CH 1, Rank 1
6075 12:39:03.793532 SW Impedance : PASS
6076 12:39:03.796726 DUTY Scan : NO K
6077 12:39:03.800159 ZQ Calibration : PASS
6078 12:39:03.800268 Jitter Meter : NO K
6079 12:39:03.803352 CBT Training : PASS
6080 12:39:03.806487 Write leveling : PASS
6081 12:39:03.806590 RX DQS gating : PASS
6082 12:39:03.809953 RX DQ/DQS(RDDQC) : PASS
6083 12:39:03.813346 TX DQ/DQS : PASS
6084 12:39:03.813449 RX DATLAT : PASS
6085 12:39:03.816408 RX DQ/DQS(Engine): PASS
6086 12:39:03.819688 TX OE : NO K
6087 12:39:03.819795 All Pass.
6088 12:39:03.819888
6089 12:39:03.819977 DramC Write-DBI off
6090 12:39:03.823196 PER_BANK_REFRESH: Hybrid Mode
6091 12:39:03.826366 TX_TRACKING: ON
6092 12:39:03.833314 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6093 12:39:03.836592 [FAST_K] Save calibration result to emmc
6094 12:39:03.843208 dramc_set_vcore_voltage set vcore to 650000
6095 12:39:03.843334 Read voltage for 400, 6
6096 12:39:03.846303 Vio18 = 0
6097 12:39:03.846406 Vcore = 650000
6098 12:39:03.846502 Vdram = 0
6099 12:39:03.849772 Vddq = 0
6100 12:39:03.849847 Vmddr = 0
6101 12:39:03.852797 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6102 12:39:03.859587 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6103 12:39:03.862783 MEM_TYPE=3, freq_sel=20
6104 12:39:03.866104 sv_algorithm_assistance_LP4_800
6105 12:39:03.869297 ============ PULL DRAM RESETB DOWN ============
6106 12:39:03.872814 ========== PULL DRAM RESETB DOWN end =========
6107 12:39:03.875912 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6108 12:39:03.879616 ===================================
6109 12:39:03.882779 LPDDR4 DRAM CONFIGURATION
6110 12:39:03.886102 ===================================
6111 12:39:03.889301 EX_ROW_EN[0] = 0x0
6112 12:39:03.889402 EX_ROW_EN[1] = 0x0
6113 12:39:03.892534 LP4Y_EN = 0x0
6114 12:39:03.892609 WORK_FSP = 0x0
6115 12:39:03.895849 WL = 0x2
6116 12:39:03.895953 RL = 0x2
6117 12:39:03.898986 BL = 0x2
6118 12:39:03.902543 RPST = 0x0
6119 12:39:03.902647 RD_PRE = 0x0
6120 12:39:03.905652 WR_PRE = 0x1
6121 12:39:03.905754 WR_PST = 0x0
6122 12:39:03.908960 DBI_WR = 0x0
6123 12:39:03.909067 DBI_RD = 0x0
6124 12:39:03.912379 OTF = 0x1
6125 12:39:03.915534 ===================================
6126 12:39:03.918849 ===================================
6127 12:39:03.918974 ANA top config
6128 12:39:03.922368 ===================================
6129 12:39:03.925392 DLL_ASYNC_EN = 0
6130 12:39:03.928973 ALL_SLAVE_EN = 1
6131 12:39:03.929056 NEW_RANK_MODE = 1
6132 12:39:03.932185 DLL_IDLE_MODE = 1
6133 12:39:03.935388 LP45_APHY_COMB_EN = 1
6134 12:39:03.938701 TX_ODT_DIS = 1
6135 12:39:03.942045 NEW_8X_MODE = 1
6136 12:39:03.942129 ===================================
6137 12:39:03.945209 ===================================
6138 12:39:03.948624 data_rate = 800
6139 12:39:03.951796 CKR = 1
6140 12:39:03.955403 DQ_P2S_RATIO = 4
6141 12:39:03.958460 ===================================
6142 12:39:03.961933 CA_P2S_RATIO = 4
6143 12:39:03.965075 DQ_CA_OPEN = 0
6144 12:39:03.968412 DQ_SEMI_OPEN = 1
6145 12:39:03.968494 CA_SEMI_OPEN = 1
6146 12:39:03.971709 CA_FULL_RATE = 0
6147 12:39:03.974920 DQ_CKDIV4_EN = 0
6148 12:39:03.978507 CA_CKDIV4_EN = 1
6149 12:39:03.981884 CA_PREDIV_EN = 0
6150 12:39:03.985115 PH8_DLY = 0
6151 12:39:03.985215 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6152 12:39:03.988291 DQ_AAMCK_DIV = 0
6153 12:39:03.991671 CA_AAMCK_DIV = 0
6154 12:39:03.994988 CA_ADMCK_DIV = 4
6155 12:39:03.998211 DQ_TRACK_CA_EN = 0
6156 12:39:04.001741 CA_PICK = 800
6157 12:39:04.001818 CA_MCKIO = 400
6158 12:39:04.005036 MCKIO_SEMI = 400
6159 12:39:04.008328 PLL_FREQ = 3016
6160 12:39:04.011662 DQ_UI_PI_RATIO = 32
6161 12:39:04.014912 CA_UI_PI_RATIO = 32
6162 12:39:04.018014 ===================================
6163 12:39:04.021342 ===================================
6164 12:39:04.024735 memory_type:LPDDR4
6165 12:39:04.024841 GP_NUM : 10
6166 12:39:04.027906 SRAM_EN : 1
6167 12:39:04.031303 MD32_EN : 0
6168 12:39:04.034689 ===================================
6169 12:39:04.034800 [ANA_INIT] >>>>>>>>>>>>>>
6170 12:39:04.037992 <<<<<< [CONFIGURE PHASE]: ANA_TX
6171 12:39:04.041583 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6172 12:39:04.044945 ===================================
6173 12:39:04.048157 data_rate = 800,PCW = 0X7400
6174 12:39:04.051383 ===================================
6175 12:39:04.054458 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6176 12:39:04.061084 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6177 12:39:04.071278 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6178 12:39:04.074481 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6179 12:39:04.081077 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6180 12:39:04.084565 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6181 12:39:04.084654 [ANA_INIT] flow start
6182 12:39:04.087689 [ANA_INIT] PLL >>>>>>>>
6183 12:39:04.091102 [ANA_INIT] PLL <<<<<<<<
6184 12:39:04.091182 [ANA_INIT] MIDPI >>>>>>>>
6185 12:39:04.094347 [ANA_INIT] MIDPI <<<<<<<<
6186 12:39:04.097643 [ANA_INIT] DLL >>>>>>>>
6187 12:39:04.097751 [ANA_INIT] flow end
6188 12:39:04.104437 ============ LP4 DIFF to SE enter ============
6189 12:39:04.107709 ============ LP4 DIFF to SE exit ============
6190 12:39:04.107826 [ANA_INIT] <<<<<<<<<<<<<
6191 12:39:04.110877 [Flow] Enable top DCM control >>>>>
6192 12:39:04.114425 [Flow] Enable top DCM control <<<<<
6193 12:39:04.117582 Enable DLL master slave shuffle
6194 12:39:04.124078 ==============================================================
6195 12:39:04.127424 Gating Mode config
6196 12:39:04.131083 ==============================================================
6197 12:39:04.134329 Config description:
6198 12:39:04.144193 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6199 12:39:04.150855 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6200 12:39:04.154058 SELPH_MODE 0: By rank 1: By Phase
6201 12:39:04.160793 ==============================================================
6202 12:39:04.163974 GAT_TRACK_EN = 0
6203 12:39:04.167255 RX_GATING_MODE = 2
6204 12:39:04.167360 RX_GATING_TRACK_MODE = 2
6205 12:39:04.170866 SELPH_MODE = 1
6206 12:39:04.173872 PICG_EARLY_EN = 1
6207 12:39:04.177176 VALID_LAT_VALUE = 1
6208 12:39:04.183827 ==============================================================
6209 12:39:04.187210 Enter into Gating configuration >>>>
6210 12:39:04.190832 Exit from Gating configuration <<<<
6211 12:39:04.193854 Enter into DVFS_PRE_config >>>>>
6212 12:39:04.203903 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6213 12:39:04.207256 Exit from DVFS_PRE_config <<<<<
6214 12:39:04.210532 Enter into PICG configuration >>>>
6215 12:39:04.213692 Exit from PICG configuration <<<<
6216 12:39:04.217197 [RX_INPUT] configuration >>>>>
6217 12:39:04.220350 [RX_INPUT] configuration <<<<<
6218 12:39:04.223629 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6219 12:39:04.230462 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6220 12:39:04.237122 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6221 12:39:04.243729 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6222 12:39:04.247299 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6223 12:39:04.253964 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6224 12:39:04.256966 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6225 12:39:04.263762 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6226 12:39:04.266896 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6227 12:39:04.270321 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6228 12:39:04.273692 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6229 12:39:04.280065 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6230 12:39:04.283404 ===================================
6231 12:39:04.286621 LPDDR4 DRAM CONFIGURATION
6232 12:39:04.290200 ===================================
6233 12:39:04.290301 EX_ROW_EN[0] = 0x0
6234 12:39:04.293340 EX_ROW_EN[1] = 0x0
6235 12:39:04.293445 LP4Y_EN = 0x0
6236 12:39:04.296615 WORK_FSP = 0x0
6237 12:39:04.296730 WL = 0x2
6238 12:39:04.300157 RL = 0x2
6239 12:39:04.300261 BL = 0x2
6240 12:39:04.303452 RPST = 0x0
6241 12:39:04.303628 RD_PRE = 0x0
6242 12:39:04.306872 WR_PRE = 0x1
6243 12:39:04.306971 WR_PST = 0x0
6244 12:39:04.309939 DBI_WR = 0x0
6245 12:39:04.310041 DBI_RD = 0x0
6246 12:39:04.313211 OTF = 0x1
6247 12:39:04.316517 ===================================
6248 12:39:04.320076 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6249 12:39:04.323457 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6250 12:39:04.329899 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6251 12:39:04.333177 ===================================
6252 12:39:04.333278 LPDDR4 DRAM CONFIGURATION
6253 12:39:04.336463 ===================================
6254 12:39:04.339734 EX_ROW_EN[0] = 0x10
6255 12:39:04.343274 EX_ROW_EN[1] = 0x0
6256 12:39:04.343377 LP4Y_EN = 0x0
6257 12:39:04.346555 WORK_FSP = 0x0
6258 12:39:04.346653 WL = 0x2
6259 12:39:04.349780 RL = 0x2
6260 12:39:04.349851 BL = 0x2
6261 12:39:04.353376 RPST = 0x0
6262 12:39:04.353495 RD_PRE = 0x0
6263 12:39:04.356592 WR_PRE = 0x1
6264 12:39:04.356665 WR_PST = 0x0
6265 12:39:04.359685 DBI_WR = 0x0
6266 12:39:04.359767 DBI_RD = 0x0
6267 12:39:04.363211 OTF = 0x1
6268 12:39:04.366444 ===================================
6269 12:39:04.373177 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6270 12:39:04.376368 nWR fixed to 30
6271 12:39:04.376449 [ModeRegInit_LP4] CH0 RK0
6272 12:39:04.379900 [ModeRegInit_LP4] CH0 RK1
6273 12:39:04.383242 [ModeRegInit_LP4] CH1 RK0
6274 12:39:04.386276 [ModeRegInit_LP4] CH1 RK1
6275 12:39:04.386364 match AC timing 19
6276 12:39:04.393293 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6277 12:39:04.396153 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6278 12:39:04.399774 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6279 12:39:04.406431 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6280 12:39:04.409689 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6281 12:39:04.409793 ==
6282 12:39:04.412934 Dram Type= 6, Freq= 0, CH_0, rank 0
6283 12:39:04.416247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6284 12:39:04.416352 ==
6285 12:39:04.422921 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6286 12:39:04.429300 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6287 12:39:04.433011 [CA 0] Center 36 (8~64) winsize 57
6288 12:39:04.436012 [CA 1] Center 36 (8~64) winsize 57
6289 12:39:04.436113 [CA 2] Center 36 (8~64) winsize 57
6290 12:39:04.439538 [CA 3] Center 36 (8~64) winsize 57
6291 12:39:04.442807 [CA 4] Center 36 (8~64) winsize 57
6292 12:39:04.446129 [CA 5] Center 36 (8~64) winsize 57
6293 12:39:04.446201
6294 12:39:04.449336 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6295 12:39:04.449435
6296 12:39:04.456011 [CATrainingPosCal] consider 1 rank data
6297 12:39:04.456090 u2DelayCellTimex100 = 270/100 ps
6298 12:39:04.462534 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 12:39:04.466079 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 12:39:04.469239 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 12:39:04.472419 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 12:39:04.475614 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 12:39:04.479071 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 12:39:04.479228
6305 12:39:04.482329 CA PerBit enable=1, Macro0, CA PI delay=36
6306 12:39:04.482430
6307 12:39:04.485593 [CBTSetCACLKResult] CA Dly = 36
6308 12:39:04.489079 CS Dly: 1 (0~32)
6309 12:39:04.489219 ==
6310 12:39:04.492312 Dram Type= 6, Freq= 0, CH_0, rank 1
6311 12:39:04.495574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6312 12:39:04.495675 ==
6313 12:39:04.502065 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6314 12:39:04.505267 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6315 12:39:04.508800 [CA 0] Center 36 (8~64) winsize 57
6316 12:39:04.511934 [CA 1] Center 36 (8~64) winsize 57
6317 12:39:04.515294 [CA 2] Center 36 (8~64) winsize 57
6318 12:39:04.518641 [CA 3] Center 36 (8~64) winsize 57
6319 12:39:04.521865 [CA 4] Center 36 (8~64) winsize 57
6320 12:39:04.525268 [CA 5] Center 36 (8~64) winsize 57
6321 12:39:04.525372
6322 12:39:04.528525 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6323 12:39:04.528636
6324 12:39:04.531737 [CATrainingPosCal] consider 2 rank data
6325 12:39:04.534905 u2DelayCellTimex100 = 270/100 ps
6326 12:39:04.538354 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 12:39:04.545009 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 12:39:04.548209 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 12:39:04.551594 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 12:39:04.554846 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 12:39:04.558010 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6332 12:39:04.558087
6333 12:39:04.561673 CA PerBit enable=1, Macro0, CA PI delay=36
6334 12:39:04.561776
6335 12:39:04.564883 [CBTSetCACLKResult] CA Dly = 36
6336 12:39:04.564983 CS Dly: 1 (0~32)
6337 12:39:04.568182
6338 12:39:04.571331 ----->DramcWriteLeveling(PI) begin...
6339 12:39:04.571417 ==
6340 12:39:04.574618 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 12:39:04.578026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 12:39:04.578128 ==
6343 12:39:04.581245 Write leveling (Byte 0): 40 => 8
6344 12:39:04.584265 Write leveling (Byte 1): 40 => 8
6345 12:39:04.587892 DramcWriteLeveling(PI) end<-----
6346 12:39:04.587972
6347 12:39:04.588049 ==
6348 12:39:04.591153 Dram Type= 6, Freq= 0, CH_0, rank 0
6349 12:39:04.594367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 12:39:04.594455 ==
6351 12:39:04.597633 [Gating] SW mode calibration
6352 12:39:04.604371 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6353 12:39:04.611163 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6354 12:39:04.614150 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6355 12:39:04.617698 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6356 12:39:04.624302 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6357 12:39:04.627658 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6358 12:39:04.630792 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6359 12:39:04.637447 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6360 12:39:04.640845 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6361 12:39:04.644077 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6362 12:39:04.650782 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6363 12:39:04.650900 Total UI for P1: 0, mck2ui 16
6364 12:39:04.657182 best dqsien dly found for B0: ( 0, 14, 24)
6365 12:39:04.657296 Total UI for P1: 0, mck2ui 16
6366 12:39:04.660831 best dqsien dly found for B1: ( 0, 14, 24)
6367 12:39:04.667428 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6368 12:39:04.670657 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6369 12:39:04.670760
6370 12:39:04.673791 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6371 12:39:04.677328 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6372 12:39:04.680341 [Gating] SW calibration Done
6373 12:39:04.680440 ==
6374 12:39:04.683967 Dram Type= 6, Freq= 0, CH_0, rank 0
6375 12:39:04.687209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6376 12:39:04.687323 ==
6377 12:39:04.690688 RX Vref Scan: 0
6378 12:39:04.690811
6379 12:39:04.690901 RX Vref 0 -> 0, step: 1
6380 12:39:04.690963
6381 12:39:04.693634 RX Delay -410 -> 252, step: 16
6382 12:39:04.700590 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6383 12:39:04.703428 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6384 12:39:04.706793 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6385 12:39:04.710185 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6386 12:39:04.717054 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6387 12:39:04.720264 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6388 12:39:04.723398 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6389 12:39:04.726759 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6390 12:39:04.733418 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6391 12:39:04.736604 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6392 12:39:04.740055 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6393 12:39:04.743091 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6394 12:39:04.750043 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6395 12:39:04.753236 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6396 12:39:04.756552 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6397 12:39:04.762873 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6398 12:39:04.762954 ==
6399 12:39:04.766278 Dram Type= 6, Freq= 0, CH_0, rank 0
6400 12:39:04.769721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6401 12:39:04.769805 ==
6402 12:39:04.769873 DQS Delay:
6403 12:39:04.773091 DQS0 = 59, DQS1 = 59
6404 12:39:04.773176 DQM Delay:
6405 12:39:04.776225 DQM0 = 18, DQM1 = 10
6406 12:39:04.776322 DQ Delay:
6407 12:39:04.779706 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6408 12:39:04.783101 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6409 12:39:04.786607 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6410 12:39:04.789789 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6411 12:39:04.789865
6412 12:39:04.789938
6413 12:39:04.790003 ==
6414 12:39:04.792828 Dram Type= 6, Freq= 0, CH_0, rank 0
6415 12:39:04.796219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 12:39:04.796308 ==
6417 12:39:04.796374
6418 12:39:04.796442
6419 12:39:04.799431 TX Vref Scan disable
6420 12:39:04.799542 == TX Byte 0 ==
6421 12:39:04.805982 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6422 12:39:04.809688 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6423 12:39:04.809790 == TX Byte 1 ==
6424 12:39:04.816043 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6425 12:39:04.819463 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6426 12:39:04.819568 ==
6427 12:39:04.822749 Dram Type= 6, Freq= 0, CH_0, rank 0
6428 12:39:04.826053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6429 12:39:04.826143 ==
6430 12:39:04.826210
6431 12:39:04.826283
6432 12:39:04.829384 TX Vref Scan disable
6433 12:39:04.832668 == TX Byte 0 ==
6434 12:39:04.836034 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6435 12:39:04.839050 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6436 12:39:04.842548 == TX Byte 1 ==
6437 12:39:04.845579 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6438 12:39:04.849037 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6439 12:39:04.849122
6440 12:39:04.849192 [DATLAT]
6441 12:39:04.852318 Freq=400, CH0 RK0
6442 12:39:04.852400
6443 12:39:04.852473 DATLAT Default: 0xf
6444 12:39:04.855755 0, 0xFFFF, sum = 0
6445 12:39:04.859032 1, 0xFFFF, sum = 0
6446 12:39:04.859122 2, 0xFFFF, sum = 0
6447 12:39:04.862269 3, 0xFFFF, sum = 0
6448 12:39:04.862359 4, 0xFFFF, sum = 0
6449 12:39:04.865488 5, 0xFFFF, sum = 0
6450 12:39:04.865567 6, 0xFFFF, sum = 0
6451 12:39:04.868603 7, 0xFFFF, sum = 0
6452 12:39:04.868682 8, 0xFFFF, sum = 0
6453 12:39:04.872004 9, 0xFFFF, sum = 0
6454 12:39:04.872089 10, 0xFFFF, sum = 0
6455 12:39:04.875268 11, 0xFFFF, sum = 0
6456 12:39:04.875345 12, 0xFFFF, sum = 0
6457 12:39:04.878962 13, 0x0, sum = 1
6458 12:39:04.879042 14, 0x0, sum = 2
6459 12:39:04.881975 15, 0x0, sum = 3
6460 12:39:04.882063 16, 0x0, sum = 4
6461 12:39:04.885419 best_step = 14
6462 12:39:04.885545
6463 12:39:04.885639 ==
6464 12:39:04.888855 Dram Type= 6, Freq= 0, CH_0, rank 0
6465 12:39:04.892017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6466 12:39:04.892100 ==
6467 12:39:04.895473 RX Vref Scan: 1
6468 12:39:04.895547
6469 12:39:04.895608 RX Vref 0 -> 0, step: 1
6470 12:39:04.895708
6471 12:39:04.898482 RX Delay -359 -> 252, step: 8
6472 12:39:04.898557
6473 12:39:04.901958 Set Vref, RX VrefLevel [Byte0]: 62
6474 12:39:04.905234 [Byte1]: 54
6475 12:39:04.909608
6476 12:39:04.909708 Final RX Vref Byte 0 = 62 to rank0
6477 12:39:04.913354 Final RX Vref Byte 1 = 54 to rank0
6478 12:39:04.916573 Final RX Vref Byte 0 = 62 to rank1
6479 12:39:04.919758 Final RX Vref Byte 1 = 54 to rank1==
6480 12:39:04.923130 Dram Type= 6, Freq= 0, CH_0, rank 0
6481 12:39:04.929598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6482 12:39:04.929689 ==
6483 12:39:04.929797 DQS Delay:
6484 12:39:04.933139 DQS0 = 60, DQS1 = 68
6485 12:39:04.933237 DQM Delay:
6486 12:39:04.933315 DQM0 = 14, DQM1 = 14
6487 12:39:04.936384 DQ Delay:
6488 12:39:04.939640 DQ0 =12, DQ1 =16, DQ2 =16, DQ3 =8
6489 12:39:04.942815 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6490 12:39:04.942893 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6491 12:39:04.946329 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6492 12:39:04.949818
6493 12:39:04.949918
6494 12:39:04.956243 [DQSOSCAuto] RK0, (LSB)MR18= 0x8583, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6495 12:39:04.959411 CH0 RK0: MR19=C0C, MR18=8583
6496 12:39:04.966074 CH0_RK0: MR19=0xC0C, MR18=0x8583, DQSOSC=393, MR23=63, INC=382, DEC=254
6497 12:39:04.966159 ==
6498 12:39:04.969415 Dram Type= 6, Freq= 0, CH_0, rank 1
6499 12:39:04.972914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 12:39:04.973020 ==
6501 12:39:04.976257 [Gating] SW mode calibration
6502 12:39:04.982711 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6503 12:39:04.989325 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6504 12:39:04.992488 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6505 12:39:04.995896 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6506 12:39:05.002473 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6507 12:39:05.005871 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6508 12:39:05.009000 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6509 12:39:05.015684 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6510 12:39:05.019284 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6511 12:39:05.022498 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6512 12:39:05.029139 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6513 12:39:05.029264 Total UI for P1: 0, mck2ui 16
6514 12:39:05.035591 best dqsien dly found for B0: ( 0, 14, 24)
6515 12:39:05.035720 Total UI for P1: 0, mck2ui 16
6516 12:39:05.038713 best dqsien dly found for B1: ( 0, 14, 24)
6517 12:39:05.045395 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6518 12:39:05.048991 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6519 12:39:05.049102
6520 12:39:05.052196 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6521 12:39:05.055351 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6522 12:39:05.058786 [Gating] SW calibration Done
6523 12:39:05.058871 ==
6524 12:39:05.061952 Dram Type= 6, Freq= 0, CH_0, rank 1
6525 12:39:05.065437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6526 12:39:05.065543 ==
6527 12:39:05.068591 RX Vref Scan: 0
6528 12:39:05.068667
6529 12:39:05.068748 RX Vref 0 -> 0, step: 1
6530 12:39:05.068827
6531 12:39:05.071935 RX Delay -410 -> 252, step: 16
6532 12:39:05.078512 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6533 12:39:05.082035 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6534 12:39:05.085034 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6535 12:39:05.088306 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6536 12:39:05.095362 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6537 12:39:05.098460 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6538 12:39:05.101719 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6539 12:39:05.105288 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6540 12:39:05.111649 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6541 12:39:05.115034 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6542 12:39:05.118250 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6543 12:39:05.121398 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6544 12:39:05.127999 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6545 12:39:05.131502 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6546 12:39:05.134439 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6547 12:39:05.141141 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6548 12:39:05.141228 ==
6549 12:39:05.144501 Dram Type= 6, Freq= 0, CH_0, rank 1
6550 12:39:05.148109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6551 12:39:05.148194 ==
6552 12:39:05.148281 DQS Delay:
6553 12:39:05.151427 DQS0 = 59, DQS1 = 59
6554 12:39:05.151512 DQM Delay:
6555 12:39:05.154568 DQM0 = 17, DQM1 = 10
6556 12:39:05.154652 DQ Delay:
6557 12:39:05.157867 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6558 12:39:05.161059 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6559 12:39:05.164402 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6560 12:39:05.167724 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6561 12:39:05.167838
6562 12:39:05.167931
6563 12:39:05.168051 ==
6564 12:39:05.170983 Dram Type= 6, Freq= 0, CH_0, rank 1
6565 12:39:05.174262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6566 12:39:05.174367 ==
6567 12:39:05.174483
6568 12:39:05.174550
6569 12:39:05.177638 TX Vref Scan disable
6570 12:39:05.181168 == TX Byte 0 ==
6571 12:39:05.184440 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6572 12:39:05.187498 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6573 12:39:05.187602 == TX Byte 1 ==
6574 12:39:05.194483 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6575 12:39:05.197702 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6576 12:39:05.197810 ==
6577 12:39:05.200970 Dram Type= 6, Freq= 0, CH_0, rank 1
6578 12:39:05.204047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6579 12:39:05.204142 ==
6580 12:39:05.204210
6581 12:39:05.207675
6582 12:39:05.207769 TX Vref Scan disable
6583 12:39:05.210737 == TX Byte 0 ==
6584 12:39:05.214336 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6585 12:39:05.217286 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6586 12:39:05.220816 == TX Byte 1 ==
6587 12:39:05.224084 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6588 12:39:05.227056 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6589 12:39:05.227147
6590 12:39:05.227211 [DATLAT]
6591 12:39:05.230465 Freq=400, CH0 RK1
6592 12:39:05.230558
6593 12:39:05.233961 DATLAT Default: 0xe
6594 12:39:05.234035 0, 0xFFFF, sum = 0
6595 12:39:05.237105 1, 0xFFFF, sum = 0
6596 12:39:05.237180 2, 0xFFFF, sum = 0
6597 12:39:05.240424 3, 0xFFFF, sum = 0
6598 12:39:05.240503 4, 0xFFFF, sum = 0
6599 12:39:05.243783 5, 0xFFFF, sum = 0
6600 12:39:05.243861 6, 0xFFFF, sum = 0
6601 12:39:05.247051 7, 0xFFFF, sum = 0
6602 12:39:05.247140 8, 0xFFFF, sum = 0
6603 12:39:05.250683 9, 0xFFFF, sum = 0
6604 12:39:05.250762 10, 0xFFFF, sum = 0
6605 12:39:05.253982 11, 0xFFFF, sum = 0
6606 12:39:05.254067 12, 0xFFFF, sum = 0
6607 12:39:05.257245 13, 0x0, sum = 1
6608 12:39:05.257322 14, 0x0, sum = 2
6609 12:39:05.260351 15, 0x0, sum = 3
6610 12:39:05.260433 16, 0x0, sum = 4
6611 12:39:05.263625 best_step = 14
6612 12:39:05.263709
6613 12:39:05.263776 ==
6614 12:39:05.266792 Dram Type= 6, Freq= 0, CH_0, rank 1
6615 12:39:05.270421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6616 12:39:05.270498 ==
6617 12:39:05.273709 RX Vref Scan: 0
6618 12:39:05.273792
6619 12:39:05.273859 RX Vref 0 -> 0, step: 1
6620 12:39:05.273920
6621 12:39:05.276849 RX Delay -359 -> 252, step: 8
6622 12:39:05.284636 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6623 12:39:05.288068 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6624 12:39:05.291284 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6625 12:39:05.294463 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6626 12:39:05.301351 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6627 12:39:05.304410 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6628 12:39:05.307642 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6629 12:39:05.311111 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6630 12:39:05.317784 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6631 12:39:05.321098 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6632 12:39:05.324441 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6633 12:39:05.331168 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6634 12:39:05.334302 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6635 12:39:05.337839 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6636 12:39:05.340880 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6637 12:39:05.347580 iDelay=217, Bit 15, Center -52 (-303 ~ 200) 504
6638 12:39:05.347664 ==
6639 12:39:05.350974 Dram Type= 6, Freq= 0, CH_0, rank 1
6640 12:39:05.354410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6641 12:39:05.354489 ==
6642 12:39:05.354562 DQS Delay:
6643 12:39:05.357711 DQS0 = 60, DQS1 = 72
6644 12:39:05.357788 DQM Delay:
6645 12:39:05.360667 DQM0 = 11, DQM1 = 17
6646 12:39:05.360746 DQ Delay:
6647 12:39:05.364006 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6648 12:39:05.367328 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6649 12:39:05.370602 DQ8 =12, DQ9 =0, DQ10 =20, DQ11 =12
6650 12:39:05.373898 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =20
6651 12:39:05.373982
6652 12:39:05.374080
6653 12:39:05.380661 [DQSOSCAuto] RK1, (LSB)MR18= 0xc77c, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6654 12:39:05.383887 CH0 RK1: MR19=C0C, MR18=C77C
6655 12:39:05.390449 CH0_RK1: MR19=0xC0C, MR18=0xC77C, DQSOSC=385, MR23=63, INC=398, DEC=265
6656 12:39:05.393735 [RxdqsGatingPostProcess] freq 400
6657 12:39:05.400309 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6658 12:39:05.403671 best DQS0 dly(2T, 0.5T) = (0, 10)
6659 12:39:05.407072 best DQS1 dly(2T, 0.5T) = (0, 10)
6660 12:39:05.410483 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6661 12:39:05.410587 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6662 12:39:05.413582 best DQS0 dly(2T, 0.5T) = (0, 10)
6663 12:39:05.417026 best DQS1 dly(2T, 0.5T) = (0, 10)
6664 12:39:05.420422 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6665 12:39:05.423666 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6666 12:39:05.426813 Pre-setting of DQS Precalculation
6667 12:39:05.433619 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6668 12:39:05.433695 ==
6669 12:39:05.436871 Dram Type= 6, Freq= 0, CH_1, rank 0
6670 12:39:05.439910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6671 12:39:05.440016 ==
6672 12:39:05.446609 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6673 12:39:05.453489 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6674 12:39:05.456696 [CA 0] Center 36 (8~64) winsize 57
6675 12:39:05.456771 [CA 1] Center 36 (8~64) winsize 57
6676 12:39:05.460072 [CA 2] Center 36 (8~64) winsize 57
6677 12:39:05.463286 [CA 3] Center 36 (8~64) winsize 57
6678 12:39:05.466503 [CA 4] Center 36 (8~64) winsize 57
6679 12:39:05.469709 [CA 5] Center 36 (8~64) winsize 57
6680 12:39:05.469809
6681 12:39:05.472912 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6682 12:39:05.473015
6683 12:39:05.479858 [CATrainingPosCal] consider 1 rank data
6684 12:39:05.479932 u2DelayCellTimex100 = 270/100 ps
6685 12:39:05.482934 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 12:39:05.489851 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 12:39:05.493002 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 12:39:05.496136 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 12:39:05.499419 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 12:39:05.502922 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 12:39:05.503028
6692 12:39:05.506275 CA PerBit enable=1, Macro0, CA PI delay=36
6693 12:39:05.506385
6694 12:39:05.509680 [CBTSetCACLKResult] CA Dly = 36
6695 12:39:05.512813 CS Dly: 1 (0~32)
6696 12:39:05.512917 ==
6697 12:39:05.516294 Dram Type= 6, Freq= 0, CH_1, rank 1
6698 12:39:05.519435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6699 12:39:05.519538 ==
6700 12:39:05.525916 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6701 12:39:05.529397 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6702 12:39:05.532670 [CA 0] Center 36 (8~64) winsize 57
6703 12:39:05.535857 [CA 1] Center 36 (8~64) winsize 57
6704 12:39:05.539078 [CA 2] Center 36 (8~64) winsize 57
6705 12:39:05.542440 [CA 3] Center 36 (8~64) winsize 57
6706 12:39:05.545781 [CA 4] Center 36 (8~64) winsize 57
6707 12:39:05.549354 [CA 5] Center 36 (8~64) winsize 57
6708 12:39:05.549455
6709 12:39:05.552393 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6710 12:39:05.552493
6711 12:39:05.555783 [CATrainingPosCal] consider 2 rank data
6712 12:39:05.559333 u2DelayCellTimex100 = 270/100 ps
6713 12:39:05.562499 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 12:39:05.565702 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 12:39:05.572403 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 12:39:05.575706 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 12:39:05.578869 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 12:39:05.582050 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6719 12:39:05.582124
6720 12:39:05.585278 CA PerBit enable=1, Macro0, CA PI delay=36
6721 12:39:05.585375
6722 12:39:05.588582 [CBTSetCACLKResult] CA Dly = 36
6723 12:39:05.588686 CS Dly: 1 (0~32)
6724 12:39:05.588783
6725 12:39:05.592175 ----->DramcWriteLeveling(PI) begin...
6726 12:39:05.595313 ==
6727 12:39:05.598751 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 12:39:05.601989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 12:39:05.602063 ==
6730 12:39:05.605094 Write leveling (Byte 0): 40 => 8
6731 12:39:05.608722 Write leveling (Byte 1): 40 => 8
6732 12:39:05.612099 DramcWriteLeveling(PI) end<-----
6733 12:39:05.612207
6734 12:39:05.612320 ==
6735 12:39:05.615199 Dram Type= 6, Freq= 0, CH_1, rank 0
6736 12:39:05.618636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 12:39:05.618711 ==
6738 12:39:05.621827 [Gating] SW mode calibration
6739 12:39:05.628266 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6740 12:39:05.634804 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6741 12:39:05.638442 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6742 12:39:05.641616 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6743 12:39:05.648362 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6744 12:39:05.651618 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6745 12:39:05.654949 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6746 12:39:05.658001 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6747 12:39:05.664693 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6748 12:39:05.668152 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6749 12:39:05.671357 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6750 12:39:05.674823 Total UI for P1: 0, mck2ui 16
6751 12:39:05.678073 best dqsien dly found for B0: ( 0, 14, 24)
6752 12:39:05.681297 Total UI for P1: 0, mck2ui 16
6753 12:39:05.684543 best dqsien dly found for B1: ( 0, 14, 24)
6754 12:39:05.687814 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6755 12:39:05.694405 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6756 12:39:05.694488
6757 12:39:05.697606 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6758 12:39:05.700968 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6759 12:39:05.704142 [Gating] SW calibration Done
6760 12:39:05.704220 ==
6761 12:39:05.707378 Dram Type= 6, Freq= 0, CH_1, rank 0
6762 12:39:05.710656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6763 12:39:05.710737 ==
6764 12:39:05.713974 RX Vref Scan: 0
6765 12:39:05.714051
6766 12:39:05.714114 RX Vref 0 -> 0, step: 1
6767 12:39:05.714186
6768 12:39:05.717717 RX Delay -410 -> 252, step: 16
6769 12:39:05.724276 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6770 12:39:05.727414 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6771 12:39:05.730745 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6772 12:39:05.733950 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6773 12:39:05.740502 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6774 12:39:05.744086 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6775 12:39:05.747140 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6776 12:39:05.750618 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6777 12:39:05.757364 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6778 12:39:05.760507 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6779 12:39:05.763710 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6780 12:39:05.767034 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6781 12:39:05.773716 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6782 12:39:05.776900 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6783 12:39:05.780421 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6784 12:39:05.783552 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6785 12:39:05.787095 ==
6786 12:39:05.790115 Dram Type= 6, Freq= 0, CH_1, rank 0
6787 12:39:05.793423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6788 12:39:05.793556 ==
6789 12:39:05.793721 DQS Delay:
6790 12:39:05.796847 DQS0 = 51, DQS1 = 67
6791 12:39:05.796930 DQM Delay:
6792 12:39:05.800080 DQM0 = 12, DQM1 = 18
6793 12:39:05.800164 DQ Delay:
6794 12:39:05.803522 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6795 12:39:05.806569 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6796 12:39:05.809756 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6797 12:39:05.813423 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =32
6798 12:39:05.813543
6799 12:39:05.813610
6800 12:39:05.813671 ==
6801 12:39:05.816723 Dram Type= 6, Freq= 0, CH_1, rank 0
6802 12:39:05.819839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 12:39:05.819930 ==
6804 12:39:05.819997
6805 12:39:05.820059
6806 12:39:05.823082 TX Vref Scan disable
6807 12:39:05.823166 == TX Byte 0 ==
6808 12:39:05.829698 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6809 12:39:05.833276 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6810 12:39:05.833386 == TX Byte 1 ==
6811 12:39:05.839653 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6812 12:39:05.842997 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6813 12:39:05.843082 ==
6814 12:39:05.846362 Dram Type= 6, Freq= 0, CH_1, rank 0
6815 12:39:05.849371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6816 12:39:05.849501 ==
6817 12:39:05.849586
6818 12:39:05.849647
6819 12:39:05.853034 TX Vref Scan disable
6820 12:39:05.856277 == TX Byte 0 ==
6821 12:39:05.859381 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6822 12:39:05.862714 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6823 12:39:05.866115 == TX Byte 1 ==
6824 12:39:05.869390 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6825 12:39:05.872741 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6826 12:39:05.872825
6827 12:39:05.872891 [DATLAT]
6828 12:39:05.876036 Freq=400, CH1 RK0
6829 12:39:05.876120
6830 12:39:05.876186 DATLAT Default: 0xf
6831 12:39:05.879735 0, 0xFFFF, sum = 0
6832 12:39:05.879822 1, 0xFFFF, sum = 0
6833 12:39:05.882670 2, 0xFFFF, sum = 0
6834 12:39:05.885834 3, 0xFFFF, sum = 0
6835 12:39:05.885919 4, 0xFFFF, sum = 0
6836 12:39:05.889360 5, 0xFFFF, sum = 0
6837 12:39:05.889472 6, 0xFFFF, sum = 0
6838 12:39:05.892544 7, 0xFFFF, sum = 0
6839 12:39:05.892629 8, 0xFFFF, sum = 0
6840 12:39:05.895810 9, 0xFFFF, sum = 0
6841 12:39:05.895896 10, 0xFFFF, sum = 0
6842 12:39:05.899093 11, 0xFFFF, sum = 0
6843 12:39:05.899178 12, 0xFFFF, sum = 0
6844 12:39:05.902785 13, 0x0, sum = 1
6845 12:39:05.902870 14, 0x0, sum = 2
6846 12:39:05.905987 15, 0x0, sum = 3
6847 12:39:05.906071 16, 0x0, sum = 4
6848 12:39:05.909010 best_step = 14
6849 12:39:05.909106
6850 12:39:05.909177 ==
6851 12:39:05.912700 Dram Type= 6, Freq= 0, CH_1, rank 0
6852 12:39:05.915982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6853 12:39:05.916073 ==
6854 12:39:05.916138 RX Vref Scan: 1
6855 12:39:05.919141
6856 12:39:05.919215 RX Vref 0 -> 0, step: 1
6857 12:39:05.919279
6858 12:39:05.922496 RX Delay -375 -> 252, step: 8
6859 12:39:05.922574
6860 12:39:05.925692 Set Vref, RX VrefLevel [Byte0]: 56
6861 12:39:05.928863 [Byte1]: 48
6862 12:39:05.933388
6863 12:39:05.933485 Final RX Vref Byte 0 = 56 to rank0
6864 12:39:05.936514 Final RX Vref Byte 1 = 48 to rank0
6865 12:39:05.939804 Final RX Vref Byte 0 = 56 to rank1
6866 12:39:05.943048 Final RX Vref Byte 1 = 48 to rank1==
6867 12:39:05.946667 Dram Type= 6, Freq= 0, CH_1, rank 0
6868 12:39:05.953118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6869 12:39:05.953200 ==
6870 12:39:05.953275 DQS Delay:
6871 12:39:05.956360 DQS0 = 52, DQS1 = 68
6872 12:39:05.956468 DQM Delay:
6873 12:39:05.956545 DQM0 = 9, DQM1 = 14
6874 12:39:05.959943 DQ Delay:
6875 12:39:05.963114 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6876 12:39:05.963195 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
6877 12:39:05.966347 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6878 12:39:05.969648 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6879 12:39:05.969731
6880 12:39:05.969799
6881 12:39:05.979989 [DQSOSCAuto] RK0, (LSB)MR18= 0x5d6f, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
6882 12:39:05.983284 CH1 RK0: MR19=C0C, MR18=5D6F
6883 12:39:05.989654 CH1_RK0: MR19=0xC0C, MR18=0x5D6F, DQSOSC=395, MR23=63, INC=378, DEC=252
6884 12:39:05.989740 ==
6885 12:39:05.992870 Dram Type= 6, Freq= 0, CH_1, rank 1
6886 12:39:05.996436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 12:39:05.996522 ==
6888 12:39:05.999428 [Gating] SW mode calibration
6889 12:39:06.006338 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6890 12:39:06.009700 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6891 12:39:06.016305 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6892 12:39:06.019603 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6893 12:39:06.022846 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6894 12:39:06.029450 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6895 12:39:06.033215 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6896 12:39:06.036433 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6897 12:39:06.042857 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6898 12:39:06.046383 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6899 12:39:06.049340 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6900 12:39:06.052952 Total UI for P1: 0, mck2ui 16
6901 12:39:06.056154 best dqsien dly found for B0: ( 0, 14, 24)
6902 12:39:06.059409 Total UI for P1: 0, mck2ui 16
6903 12:39:06.062946 best dqsien dly found for B1: ( 0, 14, 24)
6904 12:39:06.066360 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6905 12:39:06.069930 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6906 12:39:06.070010
6907 12:39:06.076246 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6908 12:39:06.079580 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6909 12:39:06.083057 [Gating] SW calibration Done
6910 12:39:06.083167 ==
6911 12:39:06.086312 Dram Type= 6, Freq= 0, CH_1, rank 1
6912 12:39:06.089577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6913 12:39:06.089662 ==
6914 12:39:06.089733 RX Vref Scan: 0
6915 12:39:06.089803
6916 12:39:06.092784 RX Vref 0 -> 0, step: 1
6917 12:39:06.092862
6918 12:39:06.096442 RX Delay -410 -> 252, step: 16
6919 12:39:06.099600 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6920 12:39:06.105970 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6921 12:39:06.109283 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6922 12:39:06.112815 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6923 12:39:06.115956 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6924 12:39:06.122641 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6925 12:39:06.125835 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6926 12:39:06.129220 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6927 12:39:06.132665 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6928 12:39:06.135805 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6929 12:39:06.142794 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6930 12:39:06.145998 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6931 12:39:06.149136 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6932 12:39:06.155818 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6933 12:39:06.159339 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6934 12:39:06.162580 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6935 12:39:06.162659 ==
6936 12:39:06.165742 Dram Type= 6, Freq= 0, CH_1, rank 1
6937 12:39:06.169320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6938 12:39:06.172480 ==
6939 12:39:06.172591 DQS Delay:
6940 12:39:06.172683 DQS0 = 59, DQS1 = 59
6941 12:39:06.175904 DQM Delay:
6942 12:39:06.175981 DQM0 = 19, DQM1 = 12
6943 12:39:06.178906 DQ Delay:
6944 12:39:06.182410 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6945 12:39:06.182530 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6946 12:39:06.185697 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6947 12:39:06.188867 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6948 12:39:06.188951
6949 12:39:06.189015
6950 12:39:06.192332 ==
6951 12:39:06.195471 Dram Type= 6, Freq= 0, CH_1, rank 1
6952 12:39:06.199018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6953 12:39:06.199120 ==
6954 12:39:06.199189
6955 12:39:06.199251
6956 12:39:06.202329 TX Vref Scan disable
6957 12:39:06.202413 == TX Byte 0 ==
6958 12:39:06.205494 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6959 12:39:06.212452 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6960 12:39:06.212536 == TX Byte 1 ==
6961 12:39:06.215732 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6962 12:39:06.222366 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6963 12:39:06.222450 ==
6964 12:39:06.225841 Dram Type= 6, Freq= 0, CH_1, rank 1
6965 12:39:06.229063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6966 12:39:06.229182 ==
6967 12:39:06.229252
6968 12:39:06.229314
6969 12:39:06.232256 TX Vref Scan disable
6970 12:39:06.232340 == TX Byte 0 ==
6971 12:39:06.235579 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6972 12:39:06.242174 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6973 12:39:06.242259 == TX Byte 1 ==
6974 12:39:06.245644 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6975 12:39:06.252149 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6976 12:39:06.252234
6977 12:39:06.252301 [DATLAT]
6978 12:39:06.252363 Freq=400, CH1 RK1
6979 12:39:06.252434
6980 12:39:06.255334 DATLAT Default: 0xe
6981 12:39:06.258684 0, 0xFFFF, sum = 0
6982 12:39:06.258770 1, 0xFFFF, sum = 0
6983 12:39:06.262336 2, 0xFFFF, sum = 0
6984 12:39:06.262421 3, 0xFFFF, sum = 0
6985 12:39:06.265338 4, 0xFFFF, sum = 0
6986 12:39:06.265423 5, 0xFFFF, sum = 0
6987 12:39:06.268849 6, 0xFFFF, sum = 0
6988 12:39:06.268934 7, 0xFFFF, sum = 0
6989 12:39:06.272050 8, 0xFFFF, sum = 0
6990 12:39:06.272135 9, 0xFFFF, sum = 0
6991 12:39:06.275208 10, 0xFFFF, sum = 0
6992 12:39:06.275293 11, 0xFFFF, sum = 0
6993 12:39:06.278545 12, 0xFFFF, sum = 0
6994 12:39:06.278631 13, 0x0, sum = 1
6995 12:39:06.281801 14, 0x0, sum = 2
6996 12:39:06.281886 15, 0x0, sum = 3
6997 12:39:06.285047 16, 0x0, sum = 4
6998 12:39:06.285178 best_step = 14
6999 12:39:06.285287
7000 12:39:06.285377 ==
7001 12:39:06.288616 Dram Type= 6, Freq= 0, CH_1, rank 1
7002 12:39:06.291934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7003 12:39:06.294997 ==
7004 12:39:06.295080 RX Vref Scan: 0
7005 12:39:06.295148
7006 12:39:06.298454 RX Vref 0 -> 0, step: 1
7007 12:39:06.298554
7008 12:39:06.301644 RX Delay -359 -> 252, step: 8
7009 12:39:06.308482 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7010 12:39:06.311642 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7011 12:39:06.314829 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7012 12:39:06.318454 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7013 12:39:06.324859 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
7014 12:39:06.328405 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7015 12:39:06.331529 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7016 12:39:06.334693 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7017 12:39:06.341369 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7018 12:39:06.344834 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7019 12:39:06.348114 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7020 12:39:06.351441 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
7021 12:39:06.357842 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7022 12:39:06.361309 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7023 12:39:06.364566 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7024 12:39:06.367947 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7025 12:39:06.371209 ==
7026 12:39:06.374429 Dram Type= 6, Freq= 0, CH_1, rank 1
7027 12:39:06.377673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7028 12:39:06.377757 ==
7029 12:39:06.377826 DQS Delay:
7030 12:39:06.380948 DQS0 = 60, DQS1 = 64
7031 12:39:06.381024 DQM Delay:
7032 12:39:06.384211 DQM0 = 12, DQM1 = 10
7033 12:39:06.384293 DQ Delay:
7034 12:39:06.387480 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7035 12:39:06.390791 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7036 12:39:06.394043 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7037 12:39:06.397675 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7038 12:39:06.397777
7039 12:39:06.397871
7040 12:39:06.404236 [DQSOSCAuto] RK1, (LSB)MR18= 0x78a9, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
7041 12:39:06.407583 CH1 RK1: MR19=C0C, MR18=78A9
7042 12:39:06.413952 CH1_RK1: MR19=0xC0C, MR18=0x78A9, DQSOSC=388, MR23=63, INC=392, DEC=261
7043 12:39:06.417609 [RxdqsGatingPostProcess] freq 400
7044 12:39:06.424002 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7045 12:39:06.424084 best DQS0 dly(2T, 0.5T) = (0, 10)
7046 12:39:06.427146 best DQS1 dly(2T, 0.5T) = (0, 10)
7047 12:39:06.430631 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7048 12:39:06.433737 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7049 12:39:06.437044 best DQS0 dly(2T, 0.5T) = (0, 10)
7050 12:39:06.440608 best DQS1 dly(2T, 0.5T) = (0, 10)
7051 12:39:06.443779 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7052 12:39:06.447031 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7053 12:39:06.450497 Pre-setting of DQS Precalculation
7054 12:39:06.457019 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7055 12:39:06.463625 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7056 12:39:06.470342 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7057 12:39:06.470433
7058 12:39:06.470507
7059 12:39:06.473452 [Calibration Summary] 800 Mbps
7060 12:39:06.473558 CH 0, Rank 0
7061 12:39:06.476776 SW Impedance : PASS
7062 12:39:06.479800 DUTY Scan : NO K
7063 12:39:06.479905 ZQ Calibration : PASS
7064 12:39:06.483433 Jitter Meter : NO K
7065 12:39:06.486483 CBT Training : PASS
7066 12:39:06.486567 Write leveling : PASS
7067 12:39:06.489668 RX DQS gating : PASS
7068 12:39:06.493343 RX DQ/DQS(RDDQC) : PASS
7069 12:39:06.493422 TX DQ/DQS : PASS
7070 12:39:06.496609 RX DATLAT : PASS
7071 12:39:06.496691 RX DQ/DQS(Engine): PASS
7072 12:39:06.499879 TX OE : NO K
7073 12:39:06.499957 All Pass.
7074 12:39:06.500035
7075 12:39:06.502999 CH 0, Rank 1
7076 12:39:06.506528 SW Impedance : PASS
7077 12:39:06.506608 DUTY Scan : NO K
7078 12:39:06.509799 ZQ Calibration : PASS
7079 12:39:06.509885 Jitter Meter : NO K
7080 12:39:06.512971 CBT Training : PASS
7081 12:39:06.516388 Write leveling : NO K
7082 12:39:06.516481 RX DQS gating : PASS
7083 12:39:06.519665 RX DQ/DQS(RDDQC) : PASS
7084 12:39:06.522968 TX DQ/DQS : PASS
7085 12:39:06.523052 RX DATLAT : PASS
7086 12:39:06.526243 RX DQ/DQS(Engine): PASS
7087 12:39:06.529403 TX OE : NO K
7088 12:39:06.529555 All Pass.
7089 12:39:06.529627
7090 12:39:06.529690 CH 1, Rank 0
7091 12:39:06.532786 SW Impedance : PASS
7092 12:39:06.536266 DUTY Scan : NO K
7093 12:39:06.536349 ZQ Calibration : PASS
7094 12:39:06.539415 Jitter Meter : NO K
7095 12:39:06.542706 CBT Training : PASS
7096 12:39:06.542789 Write leveling : PASS
7097 12:39:06.546274 RX DQS gating : PASS
7098 12:39:06.549318 RX DQ/DQS(RDDQC) : PASS
7099 12:39:06.549409 TX DQ/DQS : PASS
7100 12:39:06.552938 RX DATLAT : PASS
7101 12:39:06.553020 RX DQ/DQS(Engine): PASS
7102 12:39:06.555908 TX OE : NO K
7103 12:39:06.556006 All Pass.
7104 12:39:06.556082
7105 12:39:06.559515 CH 1, Rank 1
7106 12:39:06.559630 SW Impedance : PASS
7107 12:39:06.562818 DUTY Scan : NO K
7108 12:39:06.565877 ZQ Calibration : PASS
7109 12:39:06.565991 Jitter Meter : NO K
7110 12:39:06.569603 CBT Training : PASS
7111 12:39:06.572706 Write leveling : NO K
7112 12:39:06.572791 RX DQS gating : PASS
7113 12:39:06.575928 RX DQ/DQS(RDDQC) : PASS
7114 12:39:06.579398 TX DQ/DQS : PASS
7115 12:39:06.579485 RX DATLAT : PASS
7116 12:39:06.582674 RX DQ/DQS(Engine): PASS
7117 12:39:06.585873 TX OE : NO K
7118 12:39:06.585961 All Pass.
7119 12:39:06.586037
7120 12:39:06.588978 DramC Write-DBI off
7121 12:39:06.589051 PER_BANK_REFRESH: Hybrid Mode
7122 12:39:06.592332 TX_TRACKING: ON
7123 12:39:06.602229 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7124 12:39:06.605472 [FAST_K] Save calibration result to emmc
7125 12:39:06.608999 dramc_set_vcore_voltage set vcore to 725000
7126 12:39:06.609083 Read voltage for 1600, 0
7127 12:39:06.612237 Vio18 = 0
7128 12:39:06.612322 Vcore = 725000
7129 12:39:06.612391 Vdram = 0
7130 12:39:06.615414 Vddq = 0
7131 12:39:06.615491 Vmddr = 0
7132 12:39:06.619088 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7133 12:39:06.625495 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7134 12:39:06.628943 MEM_TYPE=3, freq_sel=13
7135 12:39:06.632065 sv_algorithm_assistance_LP4_3733
7136 12:39:06.635413 ============ PULL DRAM RESETB DOWN ============
7137 12:39:06.638851 ========== PULL DRAM RESETB DOWN end =========
7138 12:39:06.645264 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7139 12:39:06.648798 ===================================
7140 12:39:06.648878 LPDDR4 DRAM CONFIGURATION
7141 12:39:06.651963 ===================================
7142 12:39:06.655101 EX_ROW_EN[0] = 0x0
7143 12:39:06.658288 EX_ROW_EN[1] = 0x0
7144 12:39:06.658375 LP4Y_EN = 0x0
7145 12:39:06.661510 WORK_FSP = 0x1
7146 12:39:06.661638 WL = 0x5
7147 12:39:06.665142 RL = 0x5
7148 12:39:06.665219 BL = 0x2
7149 12:39:06.668500 RPST = 0x0
7150 12:39:06.668583 RD_PRE = 0x0
7151 12:39:06.671699 WR_PRE = 0x1
7152 12:39:06.671783 WR_PST = 0x1
7153 12:39:06.674986 DBI_WR = 0x0
7154 12:39:06.675101 DBI_RD = 0x0
7155 12:39:06.678417 OTF = 0x1
7156 12:39:06.681734 ===================================
7157 12:39:06.684798 ===================================
7158 12:39:06.684878 ANA top config
7159 12:39:06.688047 ===================================
7160 12:39:06.691594 DLL_ASYNC_EN = 0
7161 12:39:06.694842 ALL_SLAVE_EN = 0
7162 12:39:06.698078 NEW_RANK_MODE = 1
7163 12:39:06.698171 DLL_IDLE_MODE = 1
7164 12:39:06.701231 LP45_APHY_COMB_EN = 1
7165 12:39:06.704564 TX_ODT_DIS = 0
7166 12:39:06.708055 NEW_8X_MODE = 1
7167 12:39:06.711378 ===================================
7168 12:39:06.714530 ===================================
7169 12:39:06.717680 data_rate = 3200
7170 12:39:06.717764 CKR = 1
7171 12:39:06.721017 DQ_P2S_RATIO = 8
7172 12:39:06.724340 ===================================
7173 12:39:06.727584 CA_P2S_RATIO = 8
7174 12:39:06.731010 DQ_CA_OPEN = 0
7175 12:39:06.734576 DQ_SEMI_OPEN = 0
7176 12:39:06.737748 CA_SEMI_OPEN = 0
7177 12:39:06.737838 CA_FULL_RATE = 0
7178 12:39:06.740790 DQ_CKDIV4_EN = 0
7179 12:39:06.744089 CA_CKDIV4_EN = 0
7180 12:39:06.747531 CA_PREDIV_EN = 0
7181 12:39:06.750757 PH8_DLY = 12
7182 12:39:06.754060 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7183 12:39:06.754137 DQ_AAMCK_DIV = 4
7184 12:39:06.757684 CA_AAMCK_DIV = 4
7185 12:39:06.760712 CA_ADMCK_DIV = 4
7186 12:39:06.763994 DQ_TRACK_CA_EN = 0
7187 12:39:06.767256 CA_PICK = 1600
7188 12:39:06.770856 CA_MCKIO = 1600
7189 12:39:06.774021 MCKIO_SEMI = 0
7190 12:39:06.777427 PLL_FREQ = 3068
7191 12:39:06.777571 DQ_UI_PI_RATIO = 32
7192 12:39:06.780326 CA_UI_PI_RATIO = 0
7193 12:39:06.783605 ===================================
7194 12:39:06.787113 ===================================
7195 12:39:06.790422 memory_type:LPDDR4
7196 12:39:06.793583 GP_NUM : 10
7197 12:39:06.793666 SRAM_EN : 1
7198 12:39:06.796934 MD32_EN : 0
7199 12:39:06.800485 ===================================
7200 12:39:06.803656 [ANA_INIT] >>>>>>>>>>>>>>
7201 12:39:06.803739 <<<<<< [CONFIGURE PHASE]: ANA_TX
7202 12:39:06.806959 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7203 12:39:06.810145 ===================================
7204 12:39:06.813603 data_rate = 3200,PCW = 0X7600
7205 12:39:06.817031 ===================================
7206 12:39:06.820018 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7207 12:39:06.826690 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7208 12:39:06.833741 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7209 12:39:06.836886 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7210 12:39:06.840024 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7211 12:39:06.843415 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7212 12:39:06.846528 [ANA_INIT] flow start
7213 12:39:06.846612 [ANA_INIT] PLL >>>>>>>>
7214 12:39:06.850018 [ANA_INIT] PLL <<<<<<<<
7215 12:39:06.853137 [ANA_INIT] MIDPI >>>>>>>>
7216 12:39:06.856602 [ANA_INIT] MIDPI <<<<<<<<
7217 12:39:06.856685 [ANA_INIT] DLL >>>>>>>>
7218 12:39:06.859899 [ANA_INIT] DLL <<<<<<<<
7219 12:39:06.860033 [ANA_INIT] flow end
7220 12:39:06.866673 ============ LP4 DIFF to SE enter ============
7221 12:39:06.869808 ============ LP4 DIFF to SE exit ============
7222 12:39:06.873323 [ANA_INIT] <<<<<<<<<<<<<
7223 12:39:06.876519 [Flow] Enable top DCM control >>>>>
7224 12:39:06.879711 [Flow] Enable top DCM control <<<<<
7225 12:39:06.879793 Enable DLL master slave shuffle
7226 12:39:06.886713 ==============================================================
7227 12:39:06.890072 Gating Mode config
7228 12:39:06.893322 ==============================================================
7229 12:39:06.896508 Config description:
7230 12:39:06.906500 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7231 12:39:06.913451 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7232 12:39:06.916606 SELPH_MODE 0: By rank 1: By Phase
7233 12:39:06.923358 ==============================================================
7234 12:39:06.926506 GAT_TRACK_EN = 1
7235 12:39:06.930016 RX_GATING_MODE = 2
7236 12:39:06.933274 RX_GATING_TRACK_MODE = 2
7237 12:39:06.936416 SELPH_MODE = 1
7238 12:39:06.936500 PICG_EARLY_EN = 1
7239 12:39:06.939700 VALID_LAT_VALUE = 1
7240 12:39:06.946419 ==============================================================
7241 12:39:06.949633 Enter into Gating configuration >>>>
7242 12:39:06.953063 Exit from Gating configuration <<<<
7243 12:39:06.956494 Enter into DVFS_PRE_config >>>>>
7244 12:39:06.966347 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7245 12:39:06.969365 Exit from DVFS_PRE_config <<<<<
7246 12:39:06.972683 Enter into PICG configuration >>>>
7247 12:39:06.976289 Exit from PICG configuration <<<<
7248 12:39:06.979430 [RX_INPUT] configuration >>>>>
7249 12:39:06.982721 [RX_INPUT] configuration <<<<<
7250 12:39:06.985838 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7251 12:39:06.992833 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7252 12:39:06.999075 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7253 12:39:07.005842 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7254 12:39:07.012318 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7255 12:39:07.019137 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7256 12:39:07.022391 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7257 12:39:07.025949 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7258 12:39:07.029069 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7259 12:39:07.035592 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7260 12:39:07.039029 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7261 12:39:07.042278 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7262 12:39:07.045738 ===================================
7263 12:39:07.048961 LPDDR4 DRAM CONFIGURATION
7264 12:39:07.052297 ===================================
7265 12:39:07.052380 EX_ROW_EN[0] = 0x0
7266 12:39:07.055740 EX_ROW_EN[1] = 0x0
7267 12:39:07.055828 LP4Y_EN = 0x0
7268 12:39:07.059098 WORK_FSP = 0x1
7269 12:39:07.059182 WL = 0x5
7270 12:39:07.062325 RL = 0x5
7271 12:39:07.065596 BL = 0x2
7272 12:39:07.065677 RPST = 0x0
7273 12:39:07.068866 RD_PRE = 0x0
7274 12:39:07.068946 WR_PRE = 0x1
7275 12:39:07.071946 WR_PST = 0x1
7276 12:39:07.072019 DBI_WR = 0x0
7277 12:39:07.075341 DBI_RD = 0x0
7278 12:39:07.075420 OTF = 0x1
7279 12:39:07.078645 ===================================
7280 12:39:07.082099 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7281 12:39:07.088562 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7282 12:39:07.091905 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7283 12:39:07.095518 ===================================
7284 12:39:07.098743 LPDDR4 DRAM CONFIGURATION
7285 12:39:07.101890 ===================================
7286 12:39:07.101972 EX_ROW_EN[0] = 0x10
7287 12:39:07.105358 EX_ROW_EN[1] = 0x0
7288 12:39:07.105438 LP4Y_EN = 0x0
7289 12:39:07.108651 WORK_FSP = 0x1
7290 12:39:07.108731 WL = 0x5
7291 12:39:07.111808 RL = 0x5
7292 12:39:07.111894 BL = 0x2
7293 12:39:07.115291 RPST = 0x0
7294 12:39:07.118587 RD_PRE = 0x0
7295 12:39:07.118664 WR_PRE = 0x1
7296 12:39:07.122054 WR_PST = 0x1
7297 12:39:07.122130 DBI_WR = 0x0
7298 12:39:07.125272 DBI_RD = 0x0
7299 12:39:07.125345 OTF = 0x1
7300 12:39:07.128441 ===================================
7301 12:39:07.135229 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7302 12:39:07.135310 ==
7303 12:39:07.138533 Dram Type= 6, Freq= 0, CH_0, rank 0
7304 12:39:07.141811 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7305 12:39:07.141912 ==
7306 12:39:07.145066 [Duty_Offset_Calibration]
7307 12:39:07.145144 B0:2 B1:0 CA:3
7308 12:39:07.148520
7309 12:39:07.151729 [DutyScan_Calibration_Flow] k_type=0
7310 12:39:07.160051
7311 12:39:07.160138 ==CLK 0==
7312 12:39:07.163224 Final CLK duty delay cell = 0
7313 12:39:07.166768 [0] MAX Duty = 5031%(X100), DQS PI = 12
7314 12:39:07.170076 [0] MIN Duty = 4907%(X100), DQS PI = 4
7315 12:39:07.170155 [0] AVG Duty = 4969%(X100)
7316 12:39:07.173260
7317 12:39:07.176492 CH0 CLK Duty spec in!! Max-Min= 124%
7318 12:39:07.179691 [DutyScan_Calibration_Flow] ====Done====
7319 12:39:07.179779
7320 12:39:07.183270 [DutyScan_Calibration_Flow] k_type=1
7321 12:39:07.199680
7322 12:39:07.199772 ==DQS 0 ==
7323 12:39:07.203043 Final DQS duty delay cell = 0
7324 12:39:07.206406 [0] MAX Duty = 5125%(X100), DQS PI = 30
7325 12:39:07.209953 [0] MIN Duty = 4875%(X100), DQS PI = 50
7326 12:39:07.212928 [0] AVG Duty = 5000%(X100)
7327 12:39:07.213014
7328 12:39:07.213081 ==DQS 1 ==
7329 12:39:07.216287 Final DQS duty delay cell = 0
7330 12:39:07.219517 [0] MAX Duty = 5156%(X100), DQS PI = 32
7331 12:39:07.222802 [0] MIN Duty = 5062%(X100), DQS PI = 0
7332 12:39:07.226092 [0] AVG Duty = 5109%(X100)
7333 12:39:07.226197
7334 12:39:07.229361 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7335 12:39:07.229491
7336 12:39:07.232983 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7337 12:39:07.236304 [DutyScan_Calibration_Flow] ====Done====
7338 12:39:07.236382
7339 12:39:07.239535 [DutyScan_Calibration_Flow] k_type=3
7340 12:39:07.257584
7341 12:39:07.257687 ==DQM 0 ==
7342 12:39:07.260862 Final DQM duty delay cell = 0
7343 12:39:07.264243 [0] MAX Duty = 5125%(X100), DQS PI = 12
7344 12:39:07.267663 [0] MIN Duty = 4875%(X100), DQS PI = 48
7345 12:39:07.270899 [0] AVG Duty = 5000%(X100)
7346 12:39:07.271026
7347 12:39:07.271167 ==DQM 1 ==
7348 12:39:07.274275 Final DQM duty delay cell = 4
7349 12:39:07.277608 [4] MAX Duty = 5187%(X100), DQS PI = 0
7350 12:39:07.280840 [4] MIN Duty = 5031%(X100), DQS PI = 24
7351 12:39:07.284247 [4] AVG Duty = 5109%(X100)
7352 12:39:07.284330
7353 12:39:07.287545 CH0 DQM 0 Duty spec in!! Max-Min= 250%
7354 12:39:07.287628
7355 12:39:07.290733 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7356 12:39:07.294127 [DutyScan_Calibration_Flow] ====Done====
7357 12:39:07.294219
7358 12:39:07.297538 [DutyScan_Calibration_Flow] k_type=2
7359 12:39:07.313999
7360 12:39:07.314100 ==DQ 0 ==
7361 12:39:07.317220 Final DQ duty delay cell = -4
7362 12:39:07.320638 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7363 12:39:07.324064 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7364 12:39:07.327188 [-4] AVG Duty = 4938%(X100)
7365 12:39:07.327274
7366 12:39:07.327342 ==DQ 1 ==
7367 12:39:07.330602 Final DQ duty delay cell = 0
7368 12:39:07.334293 [0] MAX Duty = 5156%(X100), DQS PI = 58
7369 12:39:07.337360 [0] MIN Duty = 5000%(X100), DQS PI = 16
7370 12:39:07.337486 [0] AVG Duty = 5078%(X100)
7371 12:39:07.340947
7372 12:39:07.343877 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7373 12:39:07.343963
7374 12:39:07.347553 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7375 12:39:07.350863 [DutyScan_Calibration_Flow] ====Done====
7376 12:39:07.350938 ==
7377 12:39:07.353995 Dram Type= 6, Freq= 0, CH_1, rank 0
7378 12:39:07.357219 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7379 12:39:07.357313 ==
7380 12:39:07.360961 [Duty_Offset_Calibration]
7381 12:39:07.361062 B0:1 B1:-2 CA:0
7382 12:39:07.361132
7383 12:39:07.364168 [DutyScan_Calibration_Flow] k_type=0
7384 12:39:07.374735
7385 12:39:07.374819 ==CLK 0==
7386 12:39:07.377684 Final CLK duty delay cell = 0
7387 12:39:07.381363 [0] MAX Duty = 5093%(X100), DQS PI = 22
7388 12:39:07.384638 [0] MIN Duty = 4844%(X100), DQS PI = 0
7389 12:39:07.387824 [0] AVG Duty = 4968%(X100)
7390 12:39:07.387902
7391 12:39:07.391195 CH1 CLK Duty spec in!! Max-Min= 249%
7392 12:39:07.394531 [DutyScan_Calibration_Flow] ====Done====
7393 12:39:07.394604
7394 12:39:07.397444 [DutyScan_Calibration_Flow] k_type=1
7395 12:39:07.414322
7396 12:39:07.414406 ==DQS 0 ==
7397 12:39:07.417737 Final DQS duty delay cell = 0
7398 12:39:07.420821 [0] MAX Duty = 5187%(X100), DQS PI = 24
7399 12:39:07.424142 [0] MIN Duty = 5062%(X100), DQS PI = 0
7400 12:39:07.424236 [0] AVG Duty = 5124%(X100)
7401 12:39:07.427575
7402 12:39:07.427657 ==DQS 1 ==
7403 12:39:07.430720 Final DQS duty delay cell = 0
7404 12:39:07.433985 [0] MAX Duty = 5093%(X100), DQS PI = 62
7405 12:39:07.437186 [0] MIN Duty = 4844%(X100), DQS PI = 24
7406 12:39:07.440694 [0] AVG Duty = 4968%(X100)
7407 12:39:07.440798
7408 12:39:07.444118 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7409 12:39:07.444209
7410 12:39:07.447378 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7411 12:39:07.450478 [DutyScan_Calibration_Flow] ====Done====
7412 12:39:07.450560
7413 12:39:07.453653 [DutyScan_Calibration_Flow] k_type=3
7414 12:39:07.471277
7415 12:39:07.471362 ==DQM 0 ==
7416 12:39:07.474232 Final DQM duty delay cell = 0
7417 12:39:07.477749 [0] MAX Duty = 5031%(X100), DQS PI = 24
7418 12:39:07.481051 [0] MIN Duty = 4813%(X100), DQS PI = 54
7419 12:39:07.484414 [0] AVG Duty = 4922%(X100)
7420 12:39:07.484494
7421 12:39:07.484559 ==DQM 1 ==
7422 12:39:07.487728 Final DQM duty delay cell = 0
7423 12:39:07.491032 [0] MAX Duty = 5062%(X100), DQS PI = 34
7424 12:39:07.494332 [0] MIN Duty = 4875%(X100), DQS PI = 26
7425 12:39:07.497566 [0] AVG Duty = 4968%(X100)
7426 12:39:07.497675
7427 12:39:07.500785 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7428 12:39:07.500860
7429 12:39:07.504147 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7430 12:39:07.507378 [DutyScan_Calibration_Flow] ====Done====
7431 12:39:07.507482
7432 12:39:07.510588 [DutyScan_Calibration_Flow] k_type=2
7433 12:39:07.528198
7434 12:39:07.528281 ==DQ 0 ==
7435 12:39:07.531948 Final DQ duty delay cell = 0
7436 12:39:07.535356 [0] MAX Duty = 5093%(X100), DQS PI = 22
7437 12:39:07.538372 [0] MIN Duty = 4907%(X100), DQS PI = 62
7438 12:39:07.538948 [0] AVG Duty = 5000%(X100)
7439 12:39:07.541787
7440 12:39:07.542351 ==DQ 1 ==
7441 12:39:07.545093 Final DQ duty delay cell = 0
7442 12:39:07.548604 [0] MAX Duty = 5125%(X100), DQS PI = 34
7443 12:39:07.551875 [0] MIN Duty = 4969%(X100), DQS PI = 24
7444 12:39:07.552348 [0] AVG Duty = 5047%(X100)
7445 12:39:07.552767
7446 12:39:07.555066 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7447 12:39:07.558267
7448 12:39:07.561799 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7449 12:39:07.565159 [DutyScan_Calibration_Flow] ====Done====
7450 12:39:07.568322 nWR fixed to 30
7451 12:39:07.568796 [ModeRegInit_LP4] CH0 RK0
7452 12:39:07.571702 [ModeRegInit_LP4] CH0 RK1
7453 12:39:07.575117 [ModeRegInit_LP4] CH1 RK0
7454 12:39:07.578442 [ModeRegInit_LP4] CH1 RK1
7455 12:39:07.579023 match AC timing 5
7456 12:39:07.581407 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7457 12:39:07.588190 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7458 12:39:07.591698 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7459 12:39:07.598058 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7460 12:39:07.601566 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7461 12:39:07.602107 [MiockJmeterHQA]
7462 12:39:07.602551
7463 12:39:07.604824 [DramcMiockJmeter] u1RxGatingPI = 0
7464 12:39:07.608310 0 : 4363, 4137
7465 12:39:07.609043 4 : 4252, 4027
7466 12:39:07.609764 8 : 4363, 4137
7467 12:39:07.611404 12 : 4363, 4137
7468 12:39:07.611856 16 : 4252, 4027
7469 12:39:07.614761 20 : 4253, 4026
7470 12:39:07.615359 24 : 4253, 4027
7471 12:39:07.617843 28 : 4252, 4027
7472 12:39:07.618429 32 : 4253, 4027
7473 12:39:07.621213 36 : 4252, 4026
7474 12:39:07.621726 40 : 4363, 4137
7475 12:39:07.622058 44 : 4252, 4027
7476 12:39:07.624725 48 : 4252, 4027
7477 12:39:07.625336 52 : 4253, 4027
7478 12:39:07.627951 56 : 4252, 4026
7479 12:39:07.628466 60 : 4252, 4027
7480 12:39:07.631126 64 : 4361, 4137
7481 12:39:07.631555 68 : 4361, 4138
7482 12:39:07.634656 72 : 4249, 4027
7483 12:39:07.635099 76 : 4250, 4027
7484 12:39:07.635450 80 : 4250, 4027
7485 12:39:07.637688 84 : 4250, 4026
7486 12:39:07.638276 88 : 4252, 4029
7487 12:39:07.640937 92 : 4360, 4138
7488 12:39:07.641601 96 : 4250, 4027
7489 12:39:07.644568 100 : 4250, 4027
7490 12:39:07.644977 104 : 4360, 4045
7491 12:39:07.647822 108 : 4250, 20
7492 12:39:07.648383 112 : 4361, 0
7493 12:39:07.648924 116 : 4250, 0
7494 12:39:07.651169 120 : 4250, 0
7495 12:39:07.651707 124 : 4250, 0
7496 12:39:07.654381 128 : 4252, 0
7497 12:39:07.654828 132 : 4250, 0
7498 12:39:07.655207 136 : 4250, 0
7499 12:39:07.658023 140 : 4250, 0
7500 12:39:07.658510 144 : 4361, 0
7501 12:39:07.658928 148 : 4360, 0
7502 12:39:07.660941 152 : 4361, 0
7503 12:39:07.661582 156 : 4250, 0
7504 12:39:07.664492 160 : 4250, 0
7505 12:39:07.665085 164 : 4363, 0
7506 12:39:07.665660 168 : 4250, 0
7507 12:39:07.667997 172 : 4250, 0
7508 12:39:07.668544 176 : 4250, 0
7509 12:39:07.671038 180 : 4252, 0
7510 12:39:07.671477 184 : 4250, 0
7511 12:39:07.671823 188 : 4250, 0
7512 12:39:07.674419 192 : 4250, 0
7513 12:39:07.674871 196 : 4361, 0
7514 12:39:07.675312 200 : 4250, 0
7515 12:39:07.677683 204 : 4361, 0
7516 12:39:07.678124 208 : 4249, 0
7517 12:39:07.681193 212 : 4250, 0
7518 12:39:07.681538 216 : 4363, 0
7519 12:39:07.681794 220 : 4250, 0
7520 12:39:07.684205 224 : 4250, 0
7521 12:39:07.684289 228 : 4250, 0
7522 12:39:07.687595 232 : 4250, 0
7523 12:39:07.687680 236 : 4250, 1151
7524 12:39:07.690953 240 : 4250, 4027
7525 12:39:07.691037 244 : 4362, 4140
7526 12:39:07.691120 248 : 4250, 4026
7527 12:39:07.694257 252 : 4250, 4027
7528 12:39:07.694344 256 : 4250, 4027
7529 12:39:07.697597 260 : 4250, 4026
7530 12:39:07.697684 264 : 4250, 4027
7531 12:39:07.700736 268 : 4250, 4026
7532 12:39:07.700823 272 : 4361, 4137
7533 12:39:07.704298 276 : 4250, 4026
7534 12:39:07.704385 280 : 4250, 4027
7535 12:39:07.707284 284 : 4360, 4137
7536 12:39:07.707371 288 : 4250, 4026
7537 12:39:07.710779 292 : 4250, 4027
7538 12:39:07.710866 296 : 4361, 4138
7539 12:39:07.714277 300 : 4250, 4027
7540 12:39:07.714364 304 : 4253, 4026
7541 12:39:07.714434 308 : 4250, 4027
7542 12:39:07.717530 312 : 4250, 4026
7543 12:39:07.717617 316 : 4250, 4027
7544 12:39:07.720820 320 : 4250, 4026
7545 12:39:07.720906 324 : 4361, 4137
7546 12:39:07.724070 328 : 4250, 4026
7547 12:39:07.724158 332 : 4250, 4027
7548 12:39:07.727229 336 : 4360, 4137
7549 12:39:07.727316 340 : 4250, 4027
7550 12:39:07.730454 344 : 4250, 4027
7551 12:39:07.730541 348 : 4361, 4137
7552 12:39:07.734033 352 : 4360, 4137
7553 12:39:07.734121 356 : 4250, 3030
7554 12:39:07.734190 360 : 4250, 4
7555 12:39:07.736976
7556 12:39:07.737062 MIOCK jitter meter ch=0
7557 12:39:07.737129
7558 12:39:07.740252 1T = (360-108) = 252 dly cells
7559 12:39:07.746929 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7560 12:39:07.747017 ==
7561 12:39:07.750495 Dram Type= 6, Freq= 0, CH_0, rank 0
7562 12:39:07.753470 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7563 12:39:07.753554 ==
7564 12:39:07.760081 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7565 12:39:07.763559 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7566 12:39:07.767237 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7567 12:39:07.773790 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7568 12:39:07.783203 [CA 0] Center 44 (14~75) winsize 62
7569 12:39:07.786454 [CA 1] Center 43 (13~74) winsize 62
7570 12:39:07.789818 [CA 2] Center 40 (11~69) winsize 59
7571 12:39:07.793131 [CA 3] Center 39 (10~68) winsize 59
7572 12:39:07.796284 [CA 4] Center 37 (8~67) winsize 60
7573 12:39:07.799862 [CA 5] Center 37 (7~67) winsize 61
7574 12:39:07.799973
7575 12:39:07.803111 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7576 12:39:07.803189
7577 12:39:07.806408 [CATrainingPosCal] consider 1 rank data
7578 12:39:07.809755 u2DelayCellTimex100 = 258/100 ps
7579 12:39:07.816376 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7580 12:39:07.819733 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7581 12:39:07.823027 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7582 12:39:07.826350 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7583 12:39:07.829856 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7584 12:39:07.832826 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7585 12:39:07.832938
7586 12:39:07.836090 CA PerBit enable=1, Macro0, CA PI delay=37
7587 12:39:07.836201
7588 12:39:07.839545 [CBTSetCACLKResult] CA Dly = 37
7589 12:39:07.842822 CS Dly: 11 (0~42)
7590 12:39:07.846125 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7591 12:39:07.849234 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7592 12:39:07.849369 ==
7593 12:39:07.852856 Dram Type= 6, Freq= 0, CH_0, rank 1
7594 12:39:07.859466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7595 12:39:07.859583 ==
7596 12:39:07.862334 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7597 12:39:07.869372 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7598 12:39:07.872560 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7599 12:39:07.879029 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7600 12:39:07.886943 [CA 0] Center 44 (13~75) winsize 63
7601 12:39:07.890206 [CA 1] Center 43 (13~74) winsize 62
7602 12:39:07.893461 [CA 2] Center 39 (10~69) winsize 60
7603 12:39:07.896732 [CA 3] Center 39 (10~68) winsize 59
7604 12:39:07.900381 [CA 4] Center 37 (8~67) winsize 60
7605 12:39:07.903509 [CA 5] Center 36 (7~66) winsize 60
7606 12:39:07.903593
7607 12:39:07.906679 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7608 12:39:07.906763
7609 12:39:07.913279 [CATrainingPosCal] consider 2 rank data
7610 12:39:07.913362 u2DelayCellTimex100 = 258/100 ps
7611 12:39:07.920041 CA0 delay=44 (14~75),Diff = 8 PI (30 cell)
7612 12:39:07.923593 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7613 12:39:07.926792 CA2 delay=40 (11~69),Diff = 4 PI (15 cell)
7614 12:39:07.929881 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7615 12:39:07.933369 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
7616 12:39:07.936804 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7617 12:39:07.936888
7618 12:39:07.939881 CA PerBit enable=1, Macro0, CA PI delay=36
7619 12:39:07.939965
7620 12:39:07.943189 [CBTSetCACLKResult] CA Dly = 36
7621 12:39:07.946519 CS Dly: 11 (0~43)
7622 12:39:07.950209 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7623 12:39:07.953193 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7624 12:39:07.953302
7625 12:39:07.956464 ----->DramcWriteLeveling(PI) begin...
7626 12:39:07.956549 ==
7627 12:39:07.960067 Dram Type= 6, Freq= 0, CH_0, rank 0
7628 12:39:07.966413 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7629 12:39:07.966498 ==
7630 12:39:07.969726 Write leveling (Byte 0): 34 => 34
7631 12:39:07.973019 Write leveling (Byte 1): 27 => 27
7632 12:39:07.973145 DramcWriteLeveling(PI) end<-----
7633 12:39:07.976492
7634 12:39:07.976574 ==
7635 12:39:07.979784 Dram Type= 6, Freq= 0, CH_0, rank 0
7636 12:39:07.983015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7637 12:39:07.983099 ==
7638 12:39:07.986381 [Gating] SW mode calibration
7639 12:39:07.993084 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7640 12:39:07.996425 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7641 12:39:08.003026 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7642 12:39:08.006323 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7643 12:39:08.009731 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7644 12:39:08.016426 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7645 12:39:08.019600 1 4 16 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
7646 12:39:08.022882 1 4 20 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7647 12:39:08.029624 1 4 24 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
7648 12:39:08.032978 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7649 12:39:08.036200 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7650 12:39:08.042807 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7651 12:39:08.046242 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7652 12:39:08.049318 1 5 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7653 12:39:08.056114 1 5 16 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
7654 12:39:08.059379 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7655 12:39:08.062720 1 5 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
7656 12:39:08.069279 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7657 12:39:08.072633 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7658 12:39:08.075866 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7659 12:39:08.082612 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7660 12:39:08.085836 1 6 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7661 12:39:08.089104 1 6 16 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
7662 12:39:08.096088 1 6 20 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7663 12:39:08.099215 1 6 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7664 12:39:08.102357 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7665 12:39:08.109053 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7666 12:39:08.112236 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7667 12:39:08.115846 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7668 12:39:08.122395 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7669 12:39:08.125772 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7670 12:39:08.128999 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7671 12:39:08.135632 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7672 12:39:08.138909 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 12:39:08.142339 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 12:39:08.148883 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 12:39:08.152173 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 12:39:08.155481 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 12:39:08.161981 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 12:39:08.165291 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 12:39:08.168702 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 12:39:08.171834 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 12:39:08.178670 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7682 12:39:08.181925 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7683 12:39:08.185420 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7684 12:39:08.192175 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7685 12:39:08.195124 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7686 12:39:08.198734 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7687 12:39:08.201968 Total UI for P1: 0, mck2ui 16
7688 12:39:08.205114 best dqsien dly found for B0: ( 1, 9, 14)
7689 12:39:08.211709 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7690 12:39:08.214884 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7691 12:39:08.218304 Total UI for P1: 0, mck2ui 16
7692 12:39:08.221769 best dqsien dly found for B1: ( 1, 9, 24)
7693 12:39:08.225023 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7694 12:39:08.228265 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7695 12:39:08.228349
7696 12:39:08.231553 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7697 12:39:08.235035 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7698 12:39:08.238706 [Gating] SW calibration Done
7699 12:39:08.238788 ==
7700 12:39:08.242028 Dram Type= 6, Freq= 0, CH_0, rank 0
7701 12:39:08.248629 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7702 12:39:08.248718 ==
7703 12:39:08.248807 RX Vref Scan: 0
7704 12:39:08.248889
7705 12:39:08.251838 RX Vref 0 -> 0, step: 1
7706 12:39:08.251925
7707 12:39:08.255045 RX Delay 0 -> 252, step: 8
7708 12:39:08.258477 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7709 12:39:08.261726 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7710 12:39:08.264827 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7711 12:39:08.268215 iDelay=192, Bit 3, Center 119 (64 ~ 175) 112
7712 12:39:08.274782 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7713 12:39:08.278049 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7714 12:39:08.281399 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7715 12:39:08.285054 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7716 12:39:08.288081 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7717 12:39:08.294736 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7718 12:39:08.298019 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7719 12:39:08.301244 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7720 12:39:08.304728 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7721 12:39:08.307808 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7722 12:39:08.314530 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7723 12:39:08.317701 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7724 12:39:08.317787 ==
7725 12:39:08.320952 Dram Type= 6, Freq= 0, CH_0, rank 0
7726 12:39:08.324467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7727 12:39:08.324554 ==
7728 12:39:08.327624 DQS Delay:
7729 12:39:08.327711 DQS0 = 0, DQS1 = 0
7730 12:39:08.331181 DQM Delay:
7731 12:39:08.331268 DQM0 = 127, DQM1 = 123
7732 12:39:08.331356 DQ Delay:
7733 12:39:08.334366 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7734 12:39:08.341025 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =135
7735 12:39:08.344213 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7736 12:39:08.347588 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7737 12:39:08.347676
7738 12:39:08.347763
7739 12:39:08.347905 ==
7740 12:39:08.350923 Dram Type= 6, Freq= 0, CH_0, rank 0
7741 12:39:08.354367 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7742 12:39:08.354463 ==
7743 12:39:08.354568
7744 12:39:08.354670
7745 12:39:08.357421 TX Vref Scan disable
7746 12:39:08.360760 == TX Byte 0 ==
7747 12:39:08.364384 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7748 12:39:08.367418 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7749 12:39:08.370691 == TX Byte 1 ==
7750 12:39:08.373946 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7751 12:39:08.377531 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7752 12:39:08.377619 ==
7753 12:39:08.380764 Dram Type= 6, Freq= 0, CH_0, rank 0
7754 12:39:08.386896 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7755 12:39:08.387043 ==
7756 12:39:08.399371
7757 12:39:08.402582 TX Vref early break, caculate TX vref
7758 12:39:08.406056 TX Vref=16, minBit 8, minWin=20, winSum=351
7759 12:39:08.409218 TX Vref=18, minBit 8, minWin=21, winSum=363
7760 12:39:08.412652 TX Vref=20, minBit 8, minWin=22, winSum=374
7761 12:39:08.415843 TX Vref=22, minBit 8, minWin=23, winSum=384
7762 12:39:08.419265 TX Vref=24, minBit 7, minWin=24, winSum=396
7763 12:39:08.425643 TX Vref=26, minBit 8, minWin=24, winSum=404
7764 12:39:08.429185 TX Vref=28, minBit 8, minWin=23, winSum=403
7765 12:39:08.432554 TX Vref=30, minBit 8, minWin=23, winSum=391
7766 12:39:08.435550 TX Vref=32, minBit 9, minWin=22, winSum=387
7767 12:39:08.439256 TX Vref=34, minBit 9, minWin=21, winSum=375
7768 12:39:08.445784 [TxChooseVref] Worse bit 8, Min win 24, Win sum 404, Final Vref 26
7769 12:39:08.445868
7770 12:39:08.449258 Final TX Range 0 Vref 26
7771 12:39:08.449747
7772 12:39:08.450080 ==
7773 12:39:08.453016 Dram Type= 6, Freq= 0, CH_0, rank 0
7774 12:39:08.456219 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7775 12:39:08.456755 ==
7776 12:39:08.457119
7777 12:39:08.457514
7778 12:39:08.459452 TX Vref Scan disable
7779 12:39:08.465946 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7780 12:39:08.466614 == TX Byte 0 ==
7781 12:39:08.469270 u2DelayCellOfst[0]=15 cells (4 PI)
7782 12:39:08.472515 u2DelayCellOfst[1]=18 cells (5 PI)
7783 12:39:08.475944 u2DelayCellOfst[2]=11 cells (3 PI)
7784 12:39:08.479185 u2DelayCellOfst[3]=15 cells (4 PI)
7785 12:39:08.482609 u2DelayCellOfst[4]=11 cells (3 PI)
7786 12:39:08.485750 u2DelayCellOfst[5]=0 cells (0 PI)
7787 12:39:08.489269 u2DelayCellOfst[6]=22 cells (6 PI)
7788 12:39:08.492408 u2DelayCellOfst[7]=22 cells (6 PI)
7789 12:39:08.495518 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7790 12:39:08.498933 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7791 12:39:08.502186 == TX Byte 1 ==
7792 12:39:08.505388 u2DelayCellOfst[8]=0 cells (0 PI)
7793 12:39:08.505638 u2DelayCellOfst[9]=0 cells (0 PI)
7794 12:39:08.508726 u2DelayCellOfst[10]=7 cells (2 PI)
7795 12:39:08.512161 u2DelayCellOfst[11]=3 cells (1 PI)
7796 12:39:08.515360 u2DelayCellOfst[12]=11 cells (3 PI)
7797 12:39:08.518834 u2DelayCellOfst[13]=11 cells (3 PI)
7798 12:39:08.522082 u2DelayCellOfst[14]=15 cells (4 PI)
7799 12:39:08.525331 u2DelayCellOfst[15]=11 cells (3 PI)
7800 12:39:08.528623 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7801 12:39:08.535253 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7802 12:39:08.535338 DramC Write-DBI on
7803 12:39:08.535410 ==
7804 12:39:08.538754 Dram Type= 6, Freq= 0, CH_0, rank 0
7805 12:39:08.545068 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7806 12:39:08.545152 ==
7807 12:39:08.545234
7808 12:39:08.545297
7809 12:39:08.545356 TX Vref Scan disable
7810 12:39:08.549025 == TX Byte 0 ==
7811 12:39:08.552306 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7812 12:39:08.555697 == TX Byte 1 ==
7813 12:39:08.559027 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7814 12:39:08.561974 DramC Write-DBI off
7815 12:39:08.562063
7816 12:39:08.562169 [DATLAT]
7817 12:39:08.562269 Freq=1600, CH0 RK0
7818 12:39:08.562366
7819 12:39:08.565253 DATLAT Default: 0xf
7820 12:39:08.565327 0, 0xFFFF, sum = 0
7821 12:39:08.568620 1, 0xFFFF, sum = 0
7822 12:39:08.571877 2, 0xFFFF, sum = 0
7823 12:39:08.571963 3, 0xFFFF, sum = 0
7824 12:39:08.575274 4, 0xFFFF, sum = 0
7825 12:39:08.575377 5, 0xFFFF, sum = 0
7826 12:39:08.578659 6, 0xFFFF, sum = 0
7827 12:39:08.578761 7, 0xFFFF, sum = 0
7828 12:39:08.581832 8, 0xFFFF, sum = 0
7829 12:39:08.581929 9, 0xFFFF, sum = 0
7830 12:39:08.585343 10, 0xFFFF, sum = 0
7831 12:39:08.585446 11, 0xFFFF, sum = 0
7832 12:39:08.588656 12, 0xFFFF, sum = 0
7833 12:39:08.588730 13, 0xFFFF, sum = 0
7834 12:39:08.591917 14, 0x0, sum = 1
7835 12:39:08.592003 15, 0x0, sum = 2
7836 12:39:08.595303 16, 0x0, sum = 3
7837 12:39:08.595419 17, 0x0, sum = 4
7838 12:39:08.598352 best_step = 15
7839 12:39:08.598427
7840 12:39:08.598489 ==
7841 12:39:08.601643 Dram Type= 6, Freq= 0, CH_0, rank 0
7842 12:39:08.605250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7843 12:39:08.605352 ==
7844 12:39:08.608787 RX Vref Scan: 1
7845 12:39:08.609208
7846 12:39:08.609612 Set Vref Range= 24 -> 127
7847 12:39:08.609939
7848 12:39:08.612225 RX Vref 24 -> 127, step: 1
7849 12:39:08.612647
7850 12:39:08.615377 RX Delay 11 -> 252, step: 4
7851 12:39:08.616227
7852 12:39:08.618564 Set Vref, RX VrefLevel [Byte0]: 24
7853 12:39:08.621921 [Byte1]: 24
7854 12:39:08.622365
7855 12:39:08.625060 Set Vref, RX VrefLevel [Byte0]: 25
7856 12:39:08.628681 [Byte1]: 25
7857 12:39:08.632129
7858 12:39:08.632567 Set Vref, RX VrefLevel [Byte0]: 26
7859 12:39:08.635304 [Byte1]: 26
7860 12:39:08.639343
7861 12:39:08.639576 Set Vref, RX VrefLevel [Byte0]: 27
7862 12:39:08.642813 [Byte1]: 27
7863 12:39:08.647195
7864 12:39:08.647383 Set Vref, RX VrefLevel [Byte0]: 28
7865 12:39:08.650427 [Byte1]: 28
7866 12:39:08.654755
7867 12:39:08.654889 Set Vref, RX VrefLevel [Byte0]: 29
7868 12:39:08.658095 [Byte1]: 29
7869 12:39:08.662195
7870 12:39:08.662313 Set Vref, RX VrefLevel [Byte0]: 30
7871 12:39:08.665450 [Byte1]: 30
7872 12:39:08.669713
7873 12:39:08.669808 Set Vref, RX VrefLevel [Byte0]: 31
7874 12:39:08.672989 [Byte1]: 31
7875 12:39:08.677397
7876 12:39:08.677513 Set Vref, RX VrefLevel [Byte0]: 32
7877 12:39:08.680724 [Byte1]: 32
7878 12:39:08.685114
7879 12:39:08.685226 Set Vref, RX VrefLevel [Byte0]: 33
7880 12:39:08.688455 [Byte1]: 33
7881 12:39:08.692446
7882 12:39:08.692541 Set Vref, RX VrefLevel [Byte0]: 34
7883 12:39:08.695809 [Byte1]: 34
7884 12:39:08.700340
7885 12:39:08.700454 Set Vref, RX VrefLevel [Byte0]: 35
7886 12:39:08.703366 [Byte1]: 35
7887 12:39:08.707783
7888 12:39:08.707860 Set Vref, RX VrefLevel [Byte0]: 36
7889 12:39:08.711079 [Byte1]: 36
7890 12:39:08.715226
7891 12:39:08.715316 Set Vref, RX VrefLevel [Byte0]: 37
7892 12:39:08.718865 [Byte1]: 37
7893 12:39:08.722840
7894 12:39:08.722946 Set Vref, RX VrefLevel [Byte0]: 38
7895 12:39:08.726345 [Byte1]: 38
7896 12:39:08.730456
7897 12:39:08.730535 Set Vref, RX VrefLevel [Byte0]: 39
7898 12:39:08.733953 [Byte1]: 39
7899 12:39:08.738352
7900 12:39:08.738434 Set Vref, RX VrefLevel [Byte0]: 40
7901 12:39:08.741321 [Byte1]: 40
7902 12:39:08.745752
7903 12:39:08.745861 Set Vref, RX VrefLevel [Byte0]: 41
7904 12:39:08.748958 [Byte1]: 41
7905 12:39:08.753405
7906 12:39:08.753531 Set Vref, RX VrefLevel [Byte0]: 42
7907 12:39:08.756578 [Byte1]: 42
7908 12:39:08.761061
7909 12:39:08.761139 Set Vref, RX VrefLevel [Byte0]: 43
7910 12:39:08.764191 [Byte1]: 43
7911 12:39:08.768704
7912 12:39:08.768793 Set Vref, RX VrefLevel [Byte0]: 44
7913 12:39:08.771949 [Byte1]: 44
7914 12:39:08.776139
7915 12:39:08.776215 Set Vref, RX VrefLevel [Byte0]: 45
7916 12:39:08.779461 [Byte1]: 45
7917 12:39:08.784008
7918 12:39:08.784090 Set Vref, RX VrefLevel [Byte0]: 46
7919 12:39:08.786953 [Byte1]: 46
7920 12:39:08.791535
7921 12:39:08.791610 Set Vref, RX VrefLevel [Byte0]: 47
7922 12:39:08.794875 [Byte1]: 47
7923 12:39:08.799059
7924 12:39:08.799157 Set Vref, RX VrefLevel [Byte0]: 48
7925 12:39:08.802443 [Byte1]: 48
7926 12:39:08.806712
7927 12:39:08.806788 Set Vref, RX VrefLevel [Byte0]: 49
7928 12:39:08.809943 [Byte1]: 49
7929 12:39:08.814483
7930 12:39:08.814602 Set Vref, RX VrefLevel [Byte0]: 50
7931 12:39:08.817702 [Byte1]: 50
7932 12:39:08.822131
7933 12:39:08.822213 Set Vref, RX VrefLevel [Byte0]: 51
7934 12:39:08.825396 [Byte1]: 51
7935 12:39:08.829589
7936 12:39:08.829680 Set Vref, RX VrefLevel [Byte0]: 52
7937 12:39:08.832911 [Byte1]: 52
7938 12:39:08.837371
7939 12:39:08.837508 Set Vref, RX VrefLevel [Byte0]: 53
7940 12:39:08.840213 [Byte1]: 53
7941 12:39:08.844665
7942 12:39:08.844770 Set Vref, RX VrefLevel [Byte0]: 54
7943 12:39:08.848256 [Byte1]: 54
7944 12:39:08.852182
7945 12:39:08.852300 Set Vref, RX VrefLevel [Byte0]: 55
7946 12:39:08.855505 [Byte1]: 55
7947 12:39:08.859845
7948 12:39:08.859987 Set Vref, RX VrefLevel [Byte0]: 56
7949 12:39:08.863422 [Byte1]: 56
7950 12:39:08.867505
7951 12:39:08.867632 Set Vref, RX VrefLevel [Byte0]: 57
7952 12:39:08.870850 [Byte1]: 57
7953 12:39:08.875381
7954 12:39:08.875487 Set Vref, RX VrefLevel [Byte0]: 58
7955 12:39:08.878452 [Byte1]: 58
7956 12:39:08.882911
7957 12:39:08.883015 Set Vref, RX VrefLevel [Byte0]: 59
7958 12:39:08.886174 [Byte1]: 59
7959 12:39:08.890629
7960 12:39:08.890741 Set Vref, RX VrefLevel [Byte0]: 60
7961 12:39:08.893517 [Byte1]: 60
7962 12:39:08.897965
7963 12:39:08.898067 Set Vref, RX VrefLevel [Byte0]: 61
7964 12:39:08.901184 [Byte1]: 61
7965 12:39:08.905734
7966 12:39:08.905810 Set Vref, RX VrefLevel [Byte0]: 62
7967 12:39:08.909136 [Byte1]: 62
7968 12:39:08.913359
7969 12:39:08.913461 Set Vref, RX VrefLevel [Byte0]: 63
7970 12:39:08.916545 [Byte1]: 63
7971 12:39:08.920957
7972 12:39:08.921035 Set Vref, RX VrefLevel [Byte0]: 64
7973 12:39:08.924432 [Byte1]: 64
7974 12:39:08.928634
7975 12:39:08.928709 Set Vref, RX VrefLevel [Byte0]: 65
7976 12:39:08.931937 [Byte1]: 65
7977 12:39:08.936168
7978 12:39:08.936251 Set Vref, RX VrefLevel [Byte0]: 66
7979 12:39:08.939432 [Byte1]: 66
7980 12:39:08.943797
7981 12:39:08.943911 Set Vref, RX VrefLevel [Byte0]: 67
7982 12:39:08.947233 [Byte1]: 67
7983 12:39:08.951203
7984 12:39:08.951280 Set Vref, RX VrefLevel [Byte0]: 68
7985 12:39:08.954864 [Byte1]: 68
7986 12:39:08.958841
7987 12:39:08.958917 Set Vref, RX VrefLevel [Byte0]: 69
7988 12:39:08.962243 [Byte1]: 69
7989 12:39:08.966598
7990 12:39:08.966675 Set Vref, RX VrefLevel [Byte0]: 70
7991 12:39:08.969783 [Byte1]: 70
7992 12:39:08.973952
7993 12:39:08.974031 Set Vref, RX VrefLevel [Byte0]: 71
7994 12:39:08.977563 [Byte1]: 71
7995 12:39:08.981987
7996 12:39:08.982080 Set Vref, RX VrefLevel [Byte0]: 72
7997 12:39:08.985065 [Byte1]: 72
7998 12:39:08.989405
7999 12:39:08.989493 Set Vref, RX VrefLevel [Byte0]: 73
8000 12:39:08.992790 [Byte1]: 73
8001 12:39:08.997250
8002 12:39:08.997365 Set Vref, RX VrefLevel [Byte0]: 74
8003 12:39:09.000564 [Byte1]: 74
8004 12:39:09.004796
8005 12:39:09.004878 Set Vref, RX VrefLevel [Byte0]: 75
8006 12:39:09.007910 [Byte1]: 75
8007 12:39:09.012207
8008 12:39:09.012304 Set Vref, RX VrefLevel [Byte0]: 76
8009 12:39:09.015518 [Byte1]: 76
8010 12:39:09.019979
8011 12:39:09.020056 Final RX Vref Byte 0 = 63 to rank0
8012 12:39:09.023266 Final RX Vref Byte 1 = 59 to rank0
8013 12:39:09.026614 Final RX Vref Byte 0 = 63 to rank1
8014 12:39:09.030017 Final RX Vref Byte 1 = 59 to rank1==
8015 12:39:09.033242 Dram Type= 6, Freq= 0, CH_0, rank 0
8016 12:39:09.039806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8017 12:39:09.039888 ==
8018 12:39:09.039954 DQS Delay:
8019 12:39:09.042940 DQS0 = 0, DQS1 = 0
8020 12:39:09.043015 DQM Delay:
8021 12:39:09.043088 DQM0 = 126, DQM1 = 119
8022 12:39:09.046553 DQ Delay:
8023 12:39:09.049997 DQ0 =126, DQ1 =128, DQ2 =124, DQ3 =122
8024 12:39:09.053341 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
8025 12:39:09.056592 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8026 12:39:09.060228 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
8027 12:39:09.060655
8028 12:39:09.060991
8029 12:39:09.061300
8030 12:39:09.063376 [DramC_TX_OE_Calibration] TA2
8031 12:39:09.066559 Original DQ_B0 (3 6) =30, OEN = 27
8032 12:39:09.070091 Original DQ_B1 (3 6) =30, OEN = 27
8033 12:39:09.073172 24, 0x0, End_B0=24 End_B1=24
8034 12:39:09.073890 25, 0x0, End_B0=25 End_B1=25
8035 12:39:09.076813 26, 0x0, End_B0=26 End_B1=26
8036 12:39:09.079702 27, 0x0, End_B0=27 End_B1=27
8037 12:39:09.083105 28, 0x0, End_B0=28 End_B1=28
8038 12:39:09.086714 29, 0x0, End_B0=29 End_B1=29
8039 12:39:09.087387 30, 0x0, End_B0=30 End_B1=30
8040 12:39:09.089899 31, 0x4141, End_B0=30 End_B1=30
8041 12:39:09.093185 Byte0 end_step=30 best_step=27
8042 12:39:09.096388 Byte1 end_step=30 best_step=27
8043 12:39:09.099521 Byte0 TX OE(2T, 0.5T) = (3, 3)
8044 12:39:09.102912 Byte1 TX OE(2T, 0.5T) = (3, 3)
8045 12:39:09.103363
8046 12:39:09.103731
8047 12:39:09.109824 [DQSOSCAuto] RK0, (LSB)MR18= 0x1211, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
8048 12:39:09.112987 CH0 RK0: MR19=303, MR18=1211
8049 12:39:09.119273 CH0_RK0: MR19=0x303, MR18=0x1211, DQSOSC=400, MR23=63, INC=23, DEC=15
8050 12:39:09.119580
8051 12:39:09.123051 ----->DramcWriteLeveling(PI) begin...
8052 12:39:09.123361 ==
8053 12:39:09.125958 Dram Type= 6, Freq= 0, CH_0, rank 1
8054 12:39:09.129373 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8055 12:39:09.129917 ==
8056 12:39:09.132609 Write leveling (Byte 0): 37 => 37
8057 12:39:09.136352 Write leveling (Byte 1): 29 => 29
8058 12:39:09.139484 DramcWriteLeveling(PI) end<-----
8059 12:39:09.140071
8060 12:39:09.140488 ==
8061 12:39:09.142711 Dram Type= 6, Freq= 0, CH_0, rank 1
8062 12:39:09.146290 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8063 12:39:09.146826 ==
8064 12:39:09.149146 [Gating] SW mode calibration
8065 12:39:09.156113 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8066 12:39:09.162616 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8067 12:39:09.166030 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8068 12:39:09.172665 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8069 12:39:09.175916 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8070 12:39:09.179215 1 4 12 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
8071 12:39:09.185898 1 4 16 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
8072 12:39:09.189395 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8073 12:39:09.192307 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8074 12:39:09.198835 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8075 12:39:09.202099 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8076 12:39:09.205101 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8077 12:39:09.212122 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
8078 12:39:09.215300 1 5 12 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
8079 12:39:09.218706 1 5 16 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
8080 12:39:09.221895 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8081 12:39:09.228210 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 12:39:09.231556 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8083 12:39:09.238279 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8084 12:39:09.241600 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8085 12:39:09.244756 1 6 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8086 12:39:09.248226 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8087 12:39:09.254816 1 6 16 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
8088 12:39:09.258100 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 12:39:09.264467 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8090 12:39:09.268070 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8091 12:39:09.271343 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8092 12:39:09.277977 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8093 12:39:09.281342 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8094 12:39:09.284371 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8095 12:39:09.287870 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8096 12:39:09.294596 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8097 12:39:09.297780 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 12:39:09.301016 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 12:39:09.307903 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 12:39:09.311215 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 12:39:09.314553 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 12:39:09.321193 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 12:39:09.324329 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 12:39:09.327527 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 12:39:09.334175 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 12:39:09.337386 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 12:39:09.340705 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 12:39:09.347344 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 12:39:09.350758 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8110 12:39:09.354169 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8111 12:39:09.360818 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8112 12:39:09.364083 Total UI for P1: 0, mck2ui 16
8113 12:39:09.367372 best dqsien dly found for B0: ( 1, 9, 10)
8114 12:39:09.370688 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8115 12:39:09.374272 Total UI for P1: 0, mck2ui 16
8116 12:39:09.377243 best dqsien dly found for B1: ( 1, 9, 16)
8117 12:39:09.380809 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8118 12:39:09.384211 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8119 12:39:09.384335
8120 12:39:09.387755 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8121 12:39:09.390859 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8122 12:39:09.394306 [Gating] SW calibration Done
8123 12:39:09.394534 ==
8124 12:39:09.397295 Dram Type= 6, Freq= 0, CH_0, rank 1
8125 12:39:09.403954 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8126 12:39:09.404145 ==
8127 12:39:09.404285 RX Vref Scan: 0
8128 12:39:09.404416
8129 12:39:09.407528 RX Vref 0 -> 0, step: 1
8130 12:39:09.407733
8131 12:39:09.410825 RX Delay 0 -> 252, step: 8
8132 12:39:09.414034 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8133 12:39:09.417277 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8134 12:39:09.420672 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8135 12:39:09.424015 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8136 12:39:09.430999 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8137 12:39:09.434138 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8138 12:39:09.437495 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8139 12:39:09.440648 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8140 12:39:09.444062 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8141 12:39:09.450745 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8142 12:39:09.454082 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8143 12:39:09.457282 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8144 12:39:09.460711 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8145 12:39:09.463754 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8146 12:39:09.470440 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8147 12:39:09.473684 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8148 12:39:09.474210 ==
8149 12:39:09.476920 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 12:39:09.480312 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 12:39:09.480744 ==
8152 12:39:09.483539 DQS Delay:
8153 12:39:09.483923 DQS0 = 0, DQS1 = 0
8154 12:39:09.484229 DQM Delay:
8155 12:39:09.486953 DQM0 = 128, DQM1 = 121
8156 12:39:09.487343 DQ Delay:
8157 12:39:09.490404 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8158 12:39:09.493668 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8159 12:39:09.499950 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8160 12:39:09.503381 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8161 12:39:09.503596
8162 12:39:09.503762
8163 12:39:09.503918 ==
8164 12:39:09.506811 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 12:39:09.509958 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 12:39:09.510134 ==
8167 12:39:09.510271
8168 12:39:09.510396
8169 12:39:09.513446 TX Vref Scan disable
8170 12:39:09.516654 == TX Byte 0 ==
8171 12:39:09.519940 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8172 12:39:09.523328 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8173 12:39:09.526659 == TX Byte 1 ==
8174 12:39:09.529939 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8175 12:39:09.533455 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8176 12:39:09.533580 ==
8177 12:39:09.536394 Dram Type= 6, Freq= 0, CH_0, rank 1
8178 12:39:09.539748 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8179 12:39:09.539831 ==
8180 12:39:09.556245
8181 12:39:09.559779 TX Vref early break, caculate TX vref
8182 12:39:09.562817 TX Vref=16, minBit 8, minWin=22, winSum=380
8183 12:39:09.566286 TX Vref=18, minBit 8, minWin=22, winSum=386
8184 12:39:09.569384 TX Vref=20, minBit 8, minWin=23, winSum=394
8185 12:39:09.572780 TX Vref=22, minBit 13, minWin=24, winSum=403
8186 12:39:09.576011 TX Vref=24, minBit 5, minWin=25, winSum=409
8187 12:39:09.582738 TX Vref=26, minBit 2, minWin=25, winSum=412
8188 12:39:09.586059 TX Vref=28, minBit 8, minWin=25, winSum=416
8189 12:39:09.589505 TX Vref=30, minBit 8, minWin=25, winSum=415
8190 12:39:09.592446 TX Vref=32, minBit 8, minWin=23, winSum=407
8191 12:39:09.595656 TX Vref=34, minBit 8, minWin=23, winSum=402
8192 12:39:09.599080 TX Vref=36, minBit 8, minWin=23, winSum=391
8193 12:39:09.605869 [TxChooseVref] Worse bit 8, Min win 25, Win sum 416, Final Vref 28
8194 12:39:09.606023
8195 12:39:09.609178 Final TX Range 0 Vref 28
8196 12:39:09.609427
8197 12:39:09.609620 ==
8198 12:39:09.612300 Dram Type= 6, Freq= 0, CH_0, rank 1
8199 12:39:09.615611 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8200 12:39:09.615829 ==
8201 12:39:09.616028
8202 12:39:09.619204
8203 12:39:09.619435 TX Vref Scan disable
8204 12:39:09.625626 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8205 12:39:09.625811 == TX Byte 0 ==
8206 12:39:09.628899 u2DelayCellOfst[0]=11 cells (3 PI)
8207 12:39:09.632234 u2DelayCellOfst[1]=15 cells (4 PI)
8208 12:39:09.635608 u2DelayCellOfst[2]=11 cells (3 PI)
8209 12:39:09.638965 u2DelayCellOfst[3]=11 cells (3 PI)
8210 12:39:09.642375 u2DelayCellOfst[4]=7 cells (2 PI)
8211 12:39:09.645741 u2DelayCellOfst[5]=0 cells (0 PI)
8212 12:39:09.648723 u2DelayCellOfst[6]=15 cells (4 PI)
8213 12:39:09.652250 u2DelayCellOfst[7]=15 cells (4 PI)
8214 12:39:09.655555 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8215 12:39:09.658690 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8216 12:39:09.662090 == TX Byte 1 ==
8217 12:39:09.665441 u2DelayCellOfst[8]=0 cells (0 PI)
8218 12:39:09.668536 u2DelayCellOfst[9]=0 cells (0 PI)
8219 12:39:09.671878 u2DelayCellOfst[10]=3 cells (1 PI)
8220 12:39:09.671963 u2DelayCellOfst[11]=3 cells (1 PI)
8221 12:39:09.675257 u2DelayCellOfst[12]=11 cells (3 PI)
8222 12:39:09.678689 u2DelayCellOfst[13]=7 cells (2 PI)
8223 12:39:09.682377 u2DelayCellOfst[14]=11 cells (3 PI)
8224 12:39:09.685348 u2DelayCellOfst[15]=7 cells (2 PI)
8225 12:39:09.691821 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8226 12:39:09.695289 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8227 12:39:09.695376 DramC Write-DBI on
8228 12:39:09.695481 ==
8229 12:39:09.698431 Dram Type= 6, Freq= 0, CH_0, rank 1
8230 12:39:09.705015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8231 12:39:09.705103 ==
8232 12:39:09.705192
8233 12:39:09.705274
8234 12:39:09.705374 TX Vref Scan disable
8235 12:39:09.709267 == TX Byte 0 ==
8236 12:39:09.712481 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8237 12:39:09.715912 == TX Byte 1 ==
8238 12:39:09.719105 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8239 12:39:09.722869 DramC Write-DBI off
8240 12:39:09.722979
8241 12:39:09.723078 [DATLAT]
8242 12:39:09.723174 Freq=1600, CH0 RK1
8243 12:39:09.723264
8244 12:39:09.725885 DATLAT Default: 0xf
8245 12:39:09.726009 0, 0xFFFF, sum = 0
8246 12:39:09.729358 1, 0xFFFF, sum = 0
8247 12:39:09.729471 2, 0xFFFF, sum = 0
8248 12:39:09.732523 3, 0xFFFF, sum = 0
8249 12:39:09.735736 4, 0xFFFF, sum = 0
8250 12:39:09.735844 5, 0xFFFF, sum = 0
8251 12:39:09.739061 6, 0xFFFF, sum = 0
8252 12:39:09.739167 7, 0xFFFF, sum = 0
8253 12:39:09.742420 8, 0xFFFF, sum = 0
8254 12:39:09.742524 9, 0xFFFF, sum = 0
8255 12:39:09.745830 10, 0xFFFF, sum = 0
8256 12:39:09.745947 11, 0xFFFF, sum = 0
8257 12:39:09.749032 12, 0xFFFF, sum = 0
8258 12:39:09.749148 13, 0xCFFF, sum = 0
8259 12:39:09.752362 14, 0x0, sum = 1
8260 12:39:09.752479 15, 0x0, sum = 2
8261 12:39:09.755581 16, 0x0, sum = 3
8262 12:39:09.755695 17, 0x0, sum = 4
8263 12:39:09.758830 best_step = 15
8264 12:39:09.758943
8265 12:39:09.759043 ==
8266 12:39:09.762361 Dram Type= 6, Freq= 0, CH_0, rank 1
8267 12:39:09.765675 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8268 12:39:09.765757 ==
8269 12:39:09.769014 RX Vref Scan: 0
8270 12:39:09.769113
8271 12:39:09.769204 RX Vref 0 -> 0, step: 1
8272 12:39:09.769297
8273 12:39:09.772367 RX Delay 3 -> 252, step: 4
8274 12:39:09.775585 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8275 12:39:09.782014 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8276 12:39:09.785584 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8277 12:39:09.788825 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8278 12:39:09.792034 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8279 12:39:09.795417 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8280 12:39:09.802271 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8281 12:39:09.805447 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8282 12:39:09.808695 iDelay=191, Bit 8, Center 112 (55 ~ 170) 116
8283 12:39:09.811930 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8284 12:39:09.815210 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8285 12:39:09.821751 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8286 12:39:09.825188 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8287 12:39:09.828603 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8288 12:39:09.832185 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8289 12:39:09.838554 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8290 12:39:09.838636 ==
8291 12:39:09.841793 Dram Type= 6, Freq= 0, CH_0, rank 1
8292 12:39:09.845079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8293 12:39:09.845198 ==
8294 12:39:09.845298 DQS Delay:
8295 12:39:09.848517 DQS0 = 0, DQS1 = 0
8296 12:39:09.848623 DQM Delay:
8297 12:39:09.852115 DQM0 = 124, DQM1 = 118
8298 12:39:09.852239 DQ Delay:
8299 12:39:09.855154 DQ0 =124, DQ1 =126, DQ2 =122, DQ3 =122
8300 12:39:09.858442 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8301 12:39:09.862137 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
8302 12:39:09.865334 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8303 12:39:09.865455
8304 12:39:09.865538
8305 12:39:09.865644
8306 12:39:09.868722 [DramC_TX_OE_Calibration] TA2
8307 12:39:09.872179 Original DQ_B0 (3 6) =30, OEN = 27
8308 12:39:09.875195 Original DQ_B1 (3 6) =30, OEN = 27
8309 12:39:09.878796 24, 0x0, End_B0=24 End_B1=24
8310 12:39:09.882126 25, 0x0, End_B0=25 End_B1=25
8311 12:39:09.882212 26, 0x0, End_B0=26 End_B1=26
8312 12:39:09.885050 27, 0x0, End_B0=27 End_B1=27
8313 12:39:09.888328 28, 0x0, End_B0=28 End_B1=28
8314 12:39:09.892031 29, 0x0, End_B0=29 End_B1=29
8315 12:39:09.895318 30, 0x0, End_B0=30 End_B1=30
8316 12:39:09.895394 31, 0x4141, End_B0=30 End_B1=30
8317 12:39:09.898488 Byte0 end_step=30 best_step=27
8318 12:39:09.902007 Byte1 end_step=30 best_step=27
8319 12:39:09.905200 Byte0 TX OE(2T, 0.5T) = (3, 3)
8320 12:39:09.908417 Byte1 TX OE(2T, 0.5T) = (3, 3)
8321 12:39:09.908530
8322 12:39:09.908630
8323 12:39:09.914848 [DQSOSCAuto] RK1, (LSB)MR18= 0x2311, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
8324 12:39:09.918452 CH0 RK1: MR19=303, MR18=2311
8325 12:39:09.924971 CH0_RK1: MR19=0x303, MR18=0x2311, DQSOSC=392, MR23=63, INC=24, DEC=16
8326 12:39:09.928341 [RxdqsGatingPostProcess] freq 1600
8327 12:39:09.934801 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8328 12:39:09.934909 best DQS0 dly(2T, 0.5T) = (1, 1)
8329 12:39:09.938173 best DQS1 dly(2T, 0.5T) = (1, 1)
8330 12:39:09.941612 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8331 12:39:09.944960 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8332 12:39:09.948336 best DQS0 dly(2T, 0.5T) = (1, 1)
8333 12:39:09.951714 best DQS1 dly(2T, 0.5T) = (1, 1)
8334 12:39:09.954936 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8335 12:39:09.958267 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8336 12:39:09.961594 Pre-setting of DQS Precalculation
8337 12:39:09.964834 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8338 12:39:09.964946 ==
8339 12:39:09.968028 Dram Type= 6, Freq= 0, CH_1, rank 0
8340 12:39:09.974687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8341 12:39:09.974775 ==
8342 12:39:09.978011 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8343 12:39:09.984658 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8344 12:39:09.988046 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8345 12:39:09.994730 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8346 12:39:10.002355 [CA 0] Center 42 (13~71) winsize 59
8347 12:39:10.005687 [CA 1] Center 42 (13~72) winsize 60
8348 12:39:10.008960 [CA 2] Center 38 (9~67) winsize 59
8349 12:39:10.012221 [CA 3] Center 37 (8~66) winsize 59
8350 12:39:10.015613 [CA 4] Center 37 (8~67) winsize 60
8351 12:39:10.019223 [CA 5] Center 36 (7~66) winsize 60
8352 12:39:10.019304
8353 12:39:10.022230 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8354 12:39:10.022332
8355 12:39:10.025389 [CATrainingPosCal] consider 1 rank data
8356 12:39:10.029042 u2DelayCellTimex100 = 258/100 ps
8357 12:39:10.032065 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8358 12:39:10.038774 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8359 12:39:10.041976 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8360 12:39:10.045328 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8361 12:39:10.048799 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8362 12:39:10.051943 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8363 12:39:10.052054
8364 12:39:10.055286 CA PerBit enable=1, Macro0, CA PI delay=36
8365 12:39:10.055400
8366 12:39:10.058749 [CBTSetCACLKResult] CA Dly = 36
8367 12:39:10.062119 CS Dly: 10 (0~41)
8368 12:39:10.065407 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8369 12:39:10.068826 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8370 12:39:10.068938 ==
8371 12:39:10.071805 Dram Type= 6, Freq= 0, CH_1, rank 1
8372 12:39:10.075276 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8373 12:39:10.078558 ==
8374 12:39:10.081952 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8375 12:39:10.085248 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8376 12:39:10.091784 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8377 12:39:10.098398 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8378 12:39:10.105739 [CA 0] Center 42 (13~71) winsize 59
8379 12:39:10.109045 [CA 1] Center 42 (12~72) winsize 61
8380 12:39:10.112257 [CA 2] Center 37 (8~67) winsize 60
8381 12:39:10.115803 [CA 3] Center 36 (7~66) winsize 60
8382 12:39:10.118935 [CA 4] Center 37 (8~67) winsize 60
8383 12:39:10.122336 [CA 5] Center 36 (6~66) winsize 61
8384 12:39:10.122420
8385 12:39:10.125654 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8386 12:39:10.125739
8387 12:39:10.128610 [CATrainingPosCal] consider 2 rank data
8388 12:39:10.132209 u2DelayCellTimex100 = 258/100 ps
8389 12:39:10.138737 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8390 12:39:10.142223 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8391 12:39:10.145434 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8392 12:39:10.148753 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8393 12:39:10.151818 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8394 12:39:10.155221 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8395 12:39:10.155314
8396 12:39:10.158580 CA PerBit enable=1, Macro0, CA PI delay=36
8397 12:39:10.158695
8398 12:39:10.162085 [CBTSetCACLKResult] CA Dly = 36
8399 12:39:10.165312 CS Dly: 11 (0~43)
8400 12:39:10.168322 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8401 12:39:10.172025 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8402 12:39:10.172104
8403 12:39:10.175107 ----->DramcWriteLeveling(PI) begin...
8404 12:39:10.175189 ==
8405 12:39:10.178499 Dram Type= 6, Freq= 0, CH_1, rank 0
8406 12:39:10.185585 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8407 12:39:10.186019 ==
8408 12:39:10.188619 Write leveling (Byte 0): 24 => 24
8409 12:39:10.189047 Write leveling (Byte 1): 29 => 29
8410 12:39:10.192248 DramcWriteLeveling(PI) end<-----
8411 12:39:10.192839
8412 12:39:10.195323 ==
8413 12:39:10.195752 Dram Type= 6, Freq= 0, CH_1, rank 0
8414 12:39:10.202054 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8415 12:39:10.202777 ==
8416 12:39:10.205132 [Gating] SW mode calibration
8417 12:39:10.211643 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8418 12:39:10.214990 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8419 12:39:10.221806 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8420 12:39:10.225026 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8421 12:39:10.228488 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8422 12:39:10.234842 1 4 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8423 12:39:10.238394 1 4 16 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8424 12:39:10.241645 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8425 12:39:10.247947 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8426 12:39:10.251387 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8427 12:39:10.254620 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8428 12:39:10.261470 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8429 12:39:10.264810 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8430 12:39:10.268041 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8431 12:39:10.274850 1 5 16 | B1->B0 | 2828 2929 | 0 0 | (0 0) (1 0)
8432 12:39:10.278051 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8433 12:39:10.281314 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8434 12:39:10.287939 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8435 12:39:10.291021 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8436 12:39:10.294444 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8437 12:39:10.297699 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8438 12:39:10.304356 1 6 12 | B1->B0 | 2929 2424 | 0 0 | (0 0) (0 0)
8439 12:39:10.307925 1 6 16 | B1->B0 | 4343 4040 | 0 0 | (0 0) (0 0)
8440 12:39:10.310955 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8441 12:39:10.317764 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8442 12:39:10.320964 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8443 12:39:10.324182 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8444 12:39:10.331176 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8445 12:39:10.334468 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8446 12:39:10.337454 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8447 12:39:10.344519 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8448 12:39:10.347416 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 12:39:10.350913 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 12:39:10.357644 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 12:39:10.361144 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 12:39:10.364424 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 12:39:10.371113 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 12:39:10.374410 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 12:39:10.377754 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 12:39:10.384064 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 12:39:10.387618 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 12:39:10.390954 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8459 12:39:10.397661 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8460 12:39:10.401005 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8461 12:39:10.404015 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8462 12:39:10.410717 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8463 12:39:10.414057 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8464 12:39:10.417471 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8465 12:39:10.420677 Total UI for P1: 0, mck2ui 16
8466 12:39:10.424044 best dqsien dly found for B0: ( 1, 9, 14)
8467 12:39:10.427744 Total UI for P1: 0, mck2ui 16
8468 12:39:10.430700 best dqsien dly found for B1: ( 1, 9, 16)
8469 12:39:10.434114 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8470 12:39:10.437177 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8471 12:39:10.437266
8472 12:39:10.440678 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8473 12:39:10.447211 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8474 12:39:10.447296 [Gating] SW calibration Done
8475 12:39:10.450541 ==
8476 12:39:10.450627 Dram Type= 6, Freq= 0, CH_1, rank 0
8477 12:39:10.457377 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8478 12:39:10.457462 ==
8479 12:39:10.457565 RX Vref Scan: 0
8480 12:39:10.457631
8481 12:39:10.460841 RX Vref 0 -> 0, step: 1
8482 12:39:10.460924
8483 12:39:10.463764 RX Delay 0 -> 252, step: 8
8484 12:39:10.467243 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8485 12:39:10.470642 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8486 12:39:10.473625 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8487 12:39:10.480303 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8488 12:39:10.483584 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8489 12:39:10.486971 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8490 12:39:10.490359 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8491 12:39:10.493623 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8492 12:39:10.500243 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8493 12:39:10.503500 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8494 12:39:10.506825 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8495 12:39:10.510537 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8496 12:39:10.513744 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8497 12:39:10.520405 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8498 12:39:10.523624 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8499 12:39:10.526743 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8500 12:39:10.526852 ==
8501 12:39:10.530238 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 12:39:10.533765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 12:39:10.533875 ==
8504 12:39:10.536939 DQS Delay:
8505 12:39:10.537044 DQS0 = 0, DQS1 = 0
8506 12:39:10.540260 DQM Delay:
8507 12:39:10.540375 DQM0 = 130, DQM1 = 126
8508 12:39:10.543473 DQ Delay:
8509 12:39:10.546890 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8510 12:39:10.550387 DQ4 =127, DQ5 =139, DQ6 =143, DQ7 =131
8511 12:39:10.553315 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8512 12:39:10.556651 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8513 12:39:10.556799
8514 12:39:10.556935
8515 12:39:10.557067 ==
8516 12:39:10.560153 Dram Type= 6, Freq= 0, CH_1, rank 0
8517 12:39:10.563384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8518 12:39:10.563539 ==
8519 12:39:10.563671
8520 12:39:10.563802
8521 12:39:10.566941 TX Vref Scan disable
8522 12:39:10.570369 == TX Byte 0 ==
8523 12:39:10.573467 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8524 12:39:10.576853 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8525 12:39:10.580093 == TX Byte 1 ==
8526 12:39:10.583346 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8527 12:39:10.586633 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8528 12:39:10.586747 ==
8529 12:39:10.589884 Dram Type= 6, Freq= 0, CH_1, rank 0
8530 12:39:10.596225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8531 12:39:10.596310 ==
8532 12:39:10.609093
8533 12:39:10.612411 TX Vref early break, caculate TX vref
8534 12:39:10.615819 TX Vref=16, minBit 8, minWin=21, winSum=362
8535 12:39:10.619220 TX Vref=18, minBit 9, minWin=21, winSum=369
8536 12:39:10.622628 TX Vref=20, minBit 9, minWin=22, winSum=378
8537 12:39:10.625743 TX Vref=22, minBit 8, minWin=23, winSum=395
8538 12:39:10.628918 TX Vref=24, minBit 10, minWin=24, winSum=403
8539 12:39:10.635719 TX Vref=26, minBit 9, minWin=24, winSum=411
8540 12:39:10.639066 TX Vref=28, minBit 11, minWin=24, winSum=414
8541 12:39:10.642163 TX Vref=30, minBit 0, minWin=25, winSum=412
8542 12:39:10.645639 TX Vref=32, minBit 0, minWin=24, winSum=402
8543 12:39:10.649042 TX Vref=34, minBit 9, minWin=23, winSum=396
8544 12:39:10.652131 TX Vref=36, minBit 9, minWin=22, winSum=385
8545 12:39:10.658772 [TxChooseVref] Worse bit 0, Min win 25, Win sum 412, Final Vref 30
8546 12:39:10.658857
8547 12:39:10.662358 Final TX Range 0 Vref 30
8548 12:39:10.662485
8549 12:39:10.662566 ==
8550 12:39:10.665451 Dram Type= 6, Freq= 0, CH_1, rank 0
8551 12:39:10.669073 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8552 12:39:10.669200 ==
8553 12:39:10.669266
8554 12:39:10.672228
8555 12:39:10.672312 TX Vref Scan disable
8556 12:39:10.679103 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8557 12:39:10.679212 == TX Byte 0 ==
8558 12:39:10.682388 u2DelayCellOfst[0]=18 cells (5 PI)
8559 12:39:10.685363 u2DelayCellOfst[1]=15 cells (4 PI)
8560 12:39:10.689058 u2DelayCellOfst[2]=0 cells (0 PI)
8561 12:39:10.692390 u2DelayCellOfst[3]=7 cells (2 PI)
8562 12:39:10.695629 u2DelayCellOfst[4]=7 cells (2 PI)
8563 12:39:10.699036 u2DelayCellOfst[5]=22 cells (6 PI)
8564 12:39:10.702242 u2DelayCellOfst[6]=22 cells (6 PI)
8565 12:39:10.705352 u2DelayCellOfst[7]=7 cells (2 PI)
8566 12:39:10.708945 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8567 12:39:10.712389 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8568 12:39:10.715560 == TX Byte 1 ==
8569 12:39:10.718876 u2DelayCellOfst[8]=0 cells (0 PI)
8570 12:39:10.718960 u2DelayCellOfst[9]=7 cells (2 PI)
8571 12:39:10.722208 u2DelayCellOfst[10]=15 cells (4 PI)
8572 12:39:10.725628 u2DelayCellOfst[11]=7 cells (2 PI)
8573 12:39:10.728892 u2DelayCellOfst[12]=15 cells (4 PI)
8574 12:39:10.732505 u2DelayCellOfst[13]=18 cells (5 PI)
8575 12:39:10.735684 u2DelayCellOfst[14]=18 cells (5 PI)
8576 12:39:10.738624 u2DelayCellOfst[15]=22 cells (6 PI)
8577 12:39:10.745390 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8578 12:39:10.748756 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8579 12:39:10.748929 DramC Write-DBI on
8580 12:39:10.749029 ==
8581 12:39:10.751714 Dram Type= 6, Freq= 0, CH_1, rank 0
8582 12:39:10.758640 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8583 12:39:10.758855 ==
8584 12:39:10.759041
8585 12:39:10.759207
8586 12:39:10.759381 TX Vref Scan disable
8587 12:39:10.762505 == TX Byte 0 ==
8588 12:39:10.765770 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8589 12:39:10.769291 == TX Byte 1 ==
8590 12:39:10.772346 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8591 12:39:10.775962 DramC Write-DBI off
8592 12:39:10.776176
8593 12:39:10.776366 [DATLAT]
8594 12:39:10.776550 Freq=1600, CH1 RK0
8595 12:39:10.776731
8596 12:39:10.779328 DATLAT Default: 0xf
8597 12:39:10.779477 0, 0xFFFF, sum = 0
8598 12:39:10.782447 1, 0xFFFF, sum = 0
8599 12:39:10.782600 2, 0xFFFF, sum = 0
8600 12:39:10.785936 3, 0xFFFF, sum = 0
8601 12:39:10.789290 4, 0xFFFF, sum = 0
8602 12:39:10.789526 5, 0xFFFF, sum = 0
8603 12:39:10.792470 6, 0xFFFF, sum = 0
8604 12:39:10.792685 7, 0xFFFF, sum = 0
8605 12:39:10.795599 8, 0xFFFF, sum = 0
8606 12:39:10.795698 9, 0xFFFF, sum = 0
8607 12:39:10.798958 10, 0xFFFF, sum = 0
8608 12:39:10.799032 11, 0xFFFF, sum = 0
8609 12:39:10.802752 12, 0xFFFF, sum = 0
8610 12:39:10.802835 13, 0x8FFF, sum = 0
8611 12:39:10.805529 14, 0x0, sum = 1
8612 12:39:10.805613 15, 0x0, sum = 2
8613 12:39:10.809239 16, 0x0, sum = 3
8614 12:39:10.809324 17, 0x0, sum = 4
8615 12:39:10.812380 best_step = 15
8616 12:39:10.812496
8617 12:39:10.812566 ==
8618 12:39:10.815686 Dram Type= 6, Freq= 0, CH_1, rank 0
8619 12:39:10.819198 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8620 12:39:10.819294 ==
8621 12:39:10.819401 RX Vref Scan: 1
8622 12:39:10.822211
8623 12:39:10.822300 Set Vref Range= 24 -> 127
8624 12:39:10.822371
8625 12:39:10.826005 RX Vref 24 -> 127, step: 1
8626 12:39:10.826185
8627 12:39:10.829164 RX Delay 11 -> 252, step: 4
8628 12:39:10.829299
8629 12:39:10.832393 Set Vref, RX VrefLevel [Byte0]: 24
8630 12:39:10.835820 [Byte1]: 24
8631 12:39:10.835934
8632 12:39:10.839116 Set Vref, RX VrefLevel [Byte0]: 25
8633 12:39:10.842577 [Byte1]: 25
8634 12:39:10.842799
8635 12:39:10.845905 Set Vref, RX VrefLevel [Byte0]: 26
8636 12:39:10.848768 [Byte1]: 26
8637 12:39:10.853312
8638 12:39:10.853506 Set Vref, RX VrefLevel [Byte0]: 27
8639 12:39:10.856495 [Byte1]: 27
8640 12:39:10.860615
8641 12:39:10.860828 Set Vref, RX VrefLevel [Byte0]: 28
8642 12:39:10.863852 [Byte1]: 28
8643 12:39:10.868451
8644 12:39:10.868840 Set Vref, RX VrefLevel [Byte0]: 29
8645 12:39:10.871701 [Byte1]: 29
8646 12:39:10.875989
8647 12:39:10.876385 Set Vref, RX VrefLevel [Byte0]: 30
8648 12:39:10.879587 [Byte1]: 30
8649 12:39:10.884023
8650 12:39:10.884538 Set Vref, RX VrefLevel [Byte0]: 31
8651 12:39:10.887099 [Byte1]: 31
8652 12:39:10.891261
8653 12:39:10.891895 Set Vref, RX VrefLevel [Byte0]: 32
8654 12:39:10.894565 [Byte1]: 32
8655 12:39:10.898674
8656 12:39:10.899171 Set Vref, RX VrefLevel [Byte0]: 33
8657 12:39:10.902209 [Byte1]: 33
8658 12:39:10.906275
8659 12:39:10.906764 Set Vref, RX VrefLevel [Byte0]: 34
8660 12:39:10.909660 [Byte1]: 34
8661 12:39:10.914143
8662 12:39:10.914634 Set Vref, RX VrefLevel [Byte0]: 35
8663 12:39:10.917392 [Byte1]: 35
8664 12:39:10.921826
8665 12:39:10.922172 Set Vref, RX VrefLevel [Byte0]: 36
8666 12:39:10.925006 [Byte1]: 36
8667 12:39:10.929179
8668 12:39:10.929546 Set Vref, RX VrefLevel [Byte0]: 37
8669 12:39:10.932504 [Byte1]: 37
8670 12:39:10.937097
8671 12:39:10.937454 Set Vref, RX VrefLevel [Byte0]: 38
8672 12:39:10.940006 [Byte1]: 38
8673 12:39:10.944413
8674 12:39:10.947766 Set Vref, RX VrefLevel [Byte0]: 39
8675 12:39:10.951071 [Byte1]: 39
8676 12:39:10.951538
8677 12:39:10.954486 Set Vref, RX VrefLevel [Byte0]: 40
8678 12:39:10.957525 [Byte1]: 40
8679 12:39:10.957958
8680 12:39:10.960931 Set Vref, RX VrefLevel [Byte0]: 41
8681 12:39:10.964074 [Byte1]: 41
8682 12:39:10.964526
8683 12:39:10.967566 Set Vref, RX VrefLevel [Byte0]: 42
8684 12:39:10.971065 [Byte1]: 42
8685 12:39:10.974827
8686 12:39:10.975163 Set Vref, RX VrefLevel [Byte0]: 43
8687 12:39:10.978369 [Byte1]: 43
8688 12:39:10.982617
8689 12:39:10.983010 Set Vref, RX VrefLevel [Byte0]: 44
8690 12:39:10.985543 [Byte1]: 44
8691 12:39:10.990181
8692 12:39:10.990645 Set Vref, RX VrefLevel [Byte0]: 45
8693 12:39:10.993454 [Byte1]: 45
8694 12:39:10.997876
8695 12:39:10.998320 Set Vref, RX VrefLevel [Byte0]: 46
8696 12:39:11.001002 [Byte1]: 46
8697 12:39:11.005639
8698 12:39:11.006062 Set Vref, RX VrefLevel [Byte0]: 47
8699 12:39:11.009012 [Byte1]: 47
8700 12:39:11.013597
8701 12:39:11.014311 Set Vref, RX VrefLevel [Byte0]: 48
8702 12:39:11.016675 [Byte1]: 48
8703 12:39:11.020729
8704 12:39:11.021149 Set Vref, RX VrefLevel [Byte0]: 49
8705 12:39:11.023998 [Byte1]: 49
8706 12:39:11.028695
8707 12:39:11.029220 Set Vref, RX VrefLevel [Byte0]: 50
8708 12:39:11.032082 [Byte1]: 50
8709 12:39:11.035936
8710 12:39:11.036480 Set Vref, RX VrefLevel [Byte0]: 51
8711 12:39:11.039232 [Byte1]: 51
8712 12:39:11.043767
8713 12:39:11.044292 Set Vref, RX VrefLevel [Byte0]: 52
8714 12:39:11.046717 [Byte1]: 52
8715 12:39:11.051074
8716 12:39:11.051549 Set Vref, RX VrefLevel [Byte0]: 53
8717 12:39:11.054716 [Byte1]: 53
8718 12:39:11.058855
8719 12:39:11.059277 Set Vref, RX VrefLevel [Byte0]: 54
8720 12:39:11.062092 [Byte1]: 54
8721 12:39:11.066177
8722 12:39:11.066602 Set Vref, RX VrefLevel [Byte0]: 55
8723 12:39:11.069862 [Byte1]: 55
8724 12:39:11.074300
8725 12:39:11.074846 Set Vref, RX VrefLevel [Byte0]: 56
8726 12:39:11.077383 [Byte1]: 56
8727 12:39:11.081590
8728 12:39:11.082115 Set Vref, RX VrefLevel [Byte0]: 57
8729 12:39:11.085058 [Byte1]: 57
8730 12:39:11.089744
8731 12:39:11.090271 Set Vref, RX VrefLevel [Byte0]: 58
8732 12:39:11.092687 [Byte1]: 58
8733 12:39:11.096828
8734 12:39:11.097251 Set Vref, RX VrefLevel [Byte0]: 59
8735 12:39:11.100451 [Byte1]: 59
8736 12:39:11.104807
8737 12:39:11.105338 Set Vref, RX VrefLevel [Byte0]: 60
8738 12:39:11.107694 [Byte1]: 60
8739 12:39:11.112453
8740 12:39:11.112977 Set Vref, RX VrefLevel [Byte0]: 61
8741 12:39:11.115576 [Byte1]: 61
8742 12:39:11.120182
8743 12:39:11.120770 Set Vref, RX VrefLevel [Byte0]: 62
8744 12:39:11.122952 [Byte1]: 62
8745 12:39:11.127340
8746 12:39:11.127863 Set Vref, RX VrefLevel [Byte0]: 63
8747 12:39:11.130671 [Byte1]: 63
8748 12:39:11.135330
8749 12:39:11.135858 Set Vref, RX VrefLevel [Byte0]: 64
8750 12:39:11.138547 [Byte1]: 64
8751 12:39:11.142634
8752 12:39:11.143164 Set Vref, RX VrefLevel [Byte0]: 65
8753 12:39:11.146069 [Byte1]: 65
8754 12:39:11.150559
8755 12:39:11.151294 Set Vref, RX VrefLevel [Byte0]: 66
8756 12:39:11.153386 [Byte1]: 66
8757 12:39:11.158103
8758 12:39:11.158630 Set Vref, RX VrefLevel [Byte0]: 67
8759 12:39:11.161128 [Byte1]: 67
8760 12:39:11.165755
8761 12:39:11.166283 Set Vref, RX VrefLevel [Byte0]: 68
8762 12:39:11.169192 [Byte1]: 68
8763 12:39:11.173212
8764 12:39:11.173817 Set Vref, RX VrefLevel [Byte0]: 69
8765 12:39:11.176605 [Byte1]: 69
8766 12:39:11.180915
8767 12:39:11.181454 Set Vref, RX VrefLevel [Byte0]: 70
8768 12:39:11.184375 [Byte1]: 70
8769 12:39:11.188795
8770 12:39:11.189325 Final RX Vref Byte 0 = 58 to rank0
8771 12:39:11.192072 Final RX Vref Byte 1 = 57 to rank0
8772 12:39:11.195122 Final RX Vref Byte 0 = 58 to rank1
8773 12:39:11.198685 Final RX Vref Byte 1 = 57 to rank1==
8774 12:39:11.201923 Dram Type= 6, Freq= 0, CH_1, rank 0
8775 12:39:11.208133 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8776 12:39:11.208636 ==
8777 12:39:11.208978 DQS Delay:
8778 12:39:11.209298 DQS0 = 0, DQS1 = 0
8779 12:39:11.211695 DQM Delay:
8780 12:39:11.212225 DQM0 = 131, DQM1 = 123
8781 12:39:11.215086 DQ Delay:
8782 12:39:11.218224 DQ0 =136, DQ1 =128, DQ2 =120, DQ3 =128
8783 12:39:11.221164 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =126
8784 12:39:11.224273 DQ8 =108, DQ9 =114, DQ10 =122, DQ11 =116
8785 12:39:11.227973 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8786 12:39:11.228398
8787 12:39:11.228749
8788 12:39:11.229062
8789 12:39:11.231308 [DramC_TX_OE_Calibration] TA2
8790 12:39:11.234487 Original DQ_B0 (3 6) =30, OEN = 27
8791 12:39:11.237757 Original DQ_B1 (3 6) =30, OEN = 27
8792 12:39:11.241188 24, 0x0, End_B0=24 End_B1=24
8793 12:39:11.241876 25, 0x0, End_B0=25 End_B1=25
8794 12:39:11.244518 26, 0x0, End_B0=26 End_B1=26
8795 12:39:11.248053 27, 0x0, End_B0=27 End_B1=27
8796 12:39:11.251283 28, 0x0, End_B0=28 End_B1=28
8797 12:39:11.254607 29, 0x0, End_B0=29 End_B1=29
8798 12:39:11.255045 30, 0x0, End_B0=30 End_B1=30
8799 12:39:11.257952 31, 0x4141, End_B0=30 End_B1=30
8800 12:39:11.261123 Byte0 end_step=30 best_step=27
8801 12:39:11.264498 Byte1 end_step=30 best_step=27
8802 12:39:11.267981 Byte0 TX OE(2T, 0.5T) = (3, 3)
8803 12:39:11.271011 Byte1 TX OE(2T, 0.5T) = (3, 3)
8804 12:39:11.271474
8805 12:39:11.271814
8806 12:39:11.277617 [DQSOSCAuto] RK0, (LSB)MR18= 0x90e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 405 ps
8807 12:39:11.280708 CH1 RK0: MR19=303, MR18=90E
8808 12:39:11.287037 CH1_RK0: MR19=0x303, MR18=0x90E, DQSOSC=402, MR23=63, INC=22, DEC=15
8809 12:39:11.287152
8810 12:39:11.290437 ----->DramcWriteLeveling(PI) begin...
8811 12:39:11.290548 ==
8812 12:39:11.294012 Dram Type= 6, Freq= 0, CH_1, rank 1
8813 12:39:11.297318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8814 12:39:11.297431 ==
8815 12:39:11.300586 Write leveling (Byte 0): 23 => 23
8816 12:39:11.303826 Write leveling (Byte 1): 26 => 26
8817 12:39:11.306968 DramcWriteLeveling(PI) end<-----
8818 12:39:11.307077
8819 12:39:11.307176 ==
8820 12:39:11.310258 Dram Type= 6, Freq= 0, CH_1, rank 1
8821 12:39:11.313655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8822 12:39:11.313768 ==
8823 12:39:11.317006 [Gating] SW mode calibration
8824 12:39:11.323638 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8825 12:39:11.330396 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8826 12:39:11.333760 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 12:39:11.340240 1 4 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8828 12:39:11.343373 1 4 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8829 12:39:11.346967 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8830 12:39:11.349923 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 12:39:11.356639 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8832 12:39:11.359932 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8833 12:39:11.363180 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 12:39:11.369937 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8835 12:39:11.373337 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8836 12:39:11.376490 1 5 8 | B1->B0 | 3434 2828 | 0 1 | (0 1) (1 0)
8837 12:39:11.383062 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8838 12:39:11.386362 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 12:39:11.389459 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8840 12:39:11.396674 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 12:39:11.399798 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 12:39:11.403164 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8843 12:39:11.409741 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8844 12:39:11.413113 1 6 8 | B1->B0 | 2727 4444 | 1 0 | (0 0) (1 1)
8845 12:39:11.416656 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8846 12:39:11.423263 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 12:39:11.426808 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 12:39:11.429854 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 12:39:11.436518 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 12:39:11.439451 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 12:39:11.443317 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 12:39:11.449408 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8853 12:39:11.452709 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8854 12:39:11.456301 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 12:39:11.463178 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 12:39:11.466280 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 12:39:11.469315 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 12:39:11.475866 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 12:39:11.479487 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 12:39:11.482482 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 12:39:11.489118 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 12:39:11.492460 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 12:39:11.495665 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 12:39:11.502054 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 12:39:11.505725 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 12:39:11.509048 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 12:39:11.515129 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 12:39:11.518550 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8869 12:39:11.521690 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8870 12:39:11.528601 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8871 12:39:11.528707 Total UI for P1: 0, mck2ui 16
8872 12:39:11.534998 best dqsien dly found for B0: ( 1, 9, 10)
8873 12:39:11.535085 Total UI for P1: 0, mck2ui 16
8874 12:39:11.541625 best dqsien dly found for B1: ( 1, 9, 10)
8875 12:39:11.544774 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8876 12:39:11.548174 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8877 12:39:11.548276
8878 12:39:11.551373 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8879 12:39:11.555045 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8880 12:39:11.558081 [Gating] SW calibration Done
8881 12:39:11.558180 ==
8882 12:39:11.561633 Dram Type= 6, Freq= 0, CH_1, rank 1
8883 12:39:11.565000 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8884 12:39:11.565093 ==
8885 12:39:11.568309 RX Vref Scan: 0
8886 12:39:11.568401
8887 12:39:11.568495 RX Vref 0 -> 0, step: 1
8888 12:39:11.571551
8889 12:39:11.571650 RX Delay 0 -> 252, step: 8
8890 12:39:11.574895 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8891 12:39:11.581335 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8892 12:39:11.584567 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8893 12:39:11.587870 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8894 12:39:11.591312 iDelay=200, Bit 4, Center 123 (64 ~ 183) 120
8895 12:39:11.594627 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8896 12:39:11.601277 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8897 12:39:11.604531 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8898 12:39:11.607860 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8899 12:39:11.611100 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8900 12:39:11.614316 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8901 12:39:11.621040 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8902 12:39:11.624331 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8903 12:39:11.627807 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8904 12:39:11.630986 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8905 12:39:11.637702 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8906 12:39:11.637818 ==
8907 12:39:11.640970 Dram Type= 6, Freq= 0, CH_1, rank 1
8908 12:39:11.644316 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8909 12:39:11.644439 ==
8910 12:39:11.644530 DQS Delay:
8911 12:39:11.647631 DQS0 = 0, DQS1 = 0
8912 12:39:11.647756 DQM Delay:
8913 12:39:11.650966 DQM0 = 128, DQM1 = 127
8914 12:39:11.651127 DQ Delay:
8915 12:39:11.654360 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =127
8916 12:39:11.657637 DQ4 =123, DQ5 =139, DQ6 =139, DQ7 =127
8917 12:39:11.660917 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8918 12:39:11.664387 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8919 12:39:11.664543
8920 12:39:11.664680
8921 12:39:11.667756 ==
8922 12:39:11.670780 Dram Type= 6, Freq= 0, CH_1, rank 1
8923 12:39:11.674147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8924 12:39:11.674301 ==
8925 12:39:11.674421
8926 12:39:11.674531
8927 12:39:11.677766 TX Vref Scan disable
8928 12:39:11.677940 == TX Byte 0 ==
8929 12:39:11.681208 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8930 12:39:11.688206 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8931 12:39:11.688538 == TX Byte 1 ==
8932 12:39:11.691146 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8933 12:39:11.698141 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8934 12:39:11.698637 ==
8935 12:39:11.701648 Dram Type= 6, Freq= 0, CH_1, rank 1
8936 12:39:11.704562 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8937 12:39:11.705050 ==
8938 12:39:11.718636
8939 12:39:11.721949 TX Vref early break, caculate TX vref
8940 12:39:11.725247 TX Vref=16, minBit 0, minWin=22, winSum=378
8941 12:39:11.728799 TX Vref=18, minBit 0, minWin=23, winSum=391
8942 12:39:11.731882 TX Vref=20, minBit 0, minWin=24, winSum=399
8943 12:39:11.735282 TX Vref=22, minBit 0, minWin=25, winSum=406
8944 12:39:11.738492 TX Vref=24, minBit 0, minWin=23, winSum=412
8945 12:39:11.745289 TX Vref=26, minBit 5, minWin=25, winSum=423
8946 12:39:11.748735 TX Vref=28, minBit 5, minWin=24, winSum=424
8947 12:39:11.751869 TX Vref=30, minBit 5, minWin=24, winSum=418
8948 12:39:11.755140 TX Vref=32, minBit 1, minWin=24, winSum=411
8949 12:39:11.758703 TX Vref=34, minBit 1, minWin=23, winSum=403
8950 12:39:11.761742 TX Vref=36, minBit 5, minWin=22, winSum=398
8951 12:39:11.768407 [TxChooseVref] Worse bit 5, Min win 25, Win sum 423, Final Vref 26
8952 12:39:11.768859
8953 12:39:11.771631 Final TX Range 0 Vref 26
8954 12:39:11.772075
8955 12:39:11.772525 ==
8956 12:39:11.774932 Dram Type= 6, Freq= 0, CH_1, rank 1
8957 12:39:11.778635 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8958 12:39:11.779097 ==
8959 12:39:11.779546
8960 12:39:11.779987
8961 12:39:11.781748 TX Vref Scan disable
8962 12:39:11.788333 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8963 12:39:11.788808 == TX Byte 0 ==
8964 12:39:11.791530 u2DelayCellOfst[0]=18 cells (5 PI)
8965 12:39:11.795041 u2DelayCellOfst[1]=11 cells (3 PI)
8966 12:39:11.798091 u2DelayCellOfst[2]=0 cells (0 PI)
8967 12:39:11.801710 u2DelayCellOfst[3]=3 cells (1 PI)
8968 12:39:11.805048 u2DelayCellOfst[4]=7 cells (2 PI)
8969 12:39:11.808203 u2DelayCellOfst[5]=18 cells (5 PI)
8970 12:39:11.811439 u2DelayCellOfst[6]=15 cells (4 PI)
8971 12:39:11.814946 u2DelayCellOfst[7]=3 cells (1 PI)
8972 12:39:11.818113 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8973 12:39:11.821338 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8974 12:39:11.824712 == TX Byte 1 ==
8975 12:39:11.828108 u2DelayCellOfst[8]=0 cells (0 PI)
8976 12:39:11.831399 u2DelayCellOfst[9]=7 cells (2 PI)
8977 12:39:11.831842 u2DelayCellOfst[10]=15 cells (4 PI)
8978 12:39:11.834720 u2DelayCellOfst[11]=7 cells (2 PI)
8979 12:39:11.837796 u2DelayCellOfst[12]=15 cells (4 PI)
8980 12:39:11.841645 u2DelayCellOfst[13]=18 cells (5 PI)
8981 12:39:11.844563 u2DelayCellOfst[14]=18 cells (5 PI)
8982 12:39:11.847778 u2DelayCellOfst[15]=22 cells (6 PI)
8983 12:39:11.854566 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8984 12:39:11.858045 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8985 12:39:11.858528 DramC Write-DBI on
8986 12:39:11.858980 ==
8987 12:39:11.861103 Dram Type= 6, Freq= 0, CH_1, rank 1
8988 12:39:11.867517 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8989 12:39:11.868072 ==
8990 12:39:11.868626
8991 12:39:11.869077
8992 12:39:11.871187 TX Vref Scan disable
8993 12:39:11.871621 == TX Byte 0 ==
8994 12:39:11.878116 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8995 12:39:11.878664 == TX Byte 1 ==
8996 12:39:11.881332 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8997 12:39:11.884419 DramC Write-DBI off
8998 12:39:11.884961
8999 12:39:11.885303 [DATLAT]
9000 12:39:11.887490 Freq=1600, CH1 RK1
9001 12:39:11.888034
9002 12:39:11.888381 DATLAT Default: 0xf
9003 12:39:11.891228 0, 0xFFFF, sum = 0
9004 12:39:11.891778 1, 0xFFFF, sum = 0
9005 12:39:11.894075 2, 0xFFFF, sum = 0
9006 12:39:11.894513 3, 0xFFFF, sum = 0
9007 12:39:11.897671 4, 0xFFFF, sum = 0
9008 12:39:11.898221 5, 0xFFFF, sum = 0
9009 12:39:11.900891 6, 0xFFFF, sum = 0
9010 12:39:11.901441 7, 0xFFFF, sum = 0
9011 12:39:11.904205 8, 0xFFFF, sum = 0
9012 12:39:11.904752 9, 0xFFFF, sum = 0
9013 12:39:11.907517 10, 0xFFFF, sum = 0
9014 12:39:11.910761 11, 0xFFFF, sum = 0
9015 12:39:11.911201 12, 0xFFFF, sum = 0
9016 12:39:11.914181 13, 0x8FFF, sum = 0
9017 12:39:11.914724 14, 0x0, sum = 1
9018 12:39:11.917366 15, 0x0, sum = 2
9019 12:39:11.917985 16, 0x0, sum = 3
9020 12:39:11.920576 17, 0x0, sum = 4
9021 12:39:11.921012 best_step = 15
9022 12:39:11.921355
9023 12:39:11.921759 ==
9024 12:39:11.924138 Dram Type= 6, Freq= 0, CH_1, rank 1
9025 12:39:11.927546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9026 12:39:11.928089 ==
9027 12:39:11.930464 RX Vref Scan: 0
9028 12:39:11.930896
9029 12:39:11.933927 RX Vref 0 -> 0, step: 1
9030 12:39:11.934498
9031 12:39:11.934846 RX Delay 3 -> 252, step: 4
9032 12:39:11.941095 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
9033 12:39:11.944232 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
9034 12:39:11.947315 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
9035 12:39:11.950924 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
9036 12:39:11.953862 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
9037 12:39:11.960513 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
9038 12:39:11.964079 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
9039 12:39:11.967455 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
9040 12:39:11.970489 iDelay=195, Bit 8, Center 108 (51 ~ 166) 116
9041 12:39:11.973782 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9042 12:39:11.980769 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9043 12:39:11.984055 iDelay=195, Bit 11, Center 118 (63 ~ 174) 112
9044 12:39:11.987665 iDelay=195, Bit 12, Center 130 (75 ~ 186) 112
9045 12:39:11.990901 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
9046 12:39:11.997364 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
9047 12:39:12.000620 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9048 12:39:12.001180 ==
9049 12:39:12.004266 Dram Type= 6, Freq= 0, CH_1, rank 1
9050 12:39:12.007174 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9051 12:39:12.007736 ==
9052 12:39:12.008204 DQS Delay:
9053 12:39:12.010509 DQS0 = 0, DQS1 = 0
9054 12:39:12.010956 DQM Delay:
9055 12:39:12.014127 DQM0 = 128, DQM1 = 124
9056 12:39:12.014682 DQ Delay:
9057 12:39:12.017419 DQ0 =132, DQ1 =126, DQ2 =114, DQ3 =126
9058 12:39:12.020567 DQ4 =124, DQ5 =138, DQ6 =140, DQ7 =124
9059 12:39:12.023592 DQ8 =108, DQ9 =112, DQ10 =128, DQ11 =118
9060 12:39:12.030409 DQ12 =130, DQ13 =132, DQ14 =132, DQ15 =134
9061 12:39:12.030939
9062 12:39:12.031280
9063 12:39:12.031597
9064 12:39:12.033569 [DramC_TX_OE_Calibration] TA2
9065 12:39:12.034023 Original DQ_B0 (3 6) =30, OEN = 27
9066 12:39:12.037129 Original DQ_B1 (3 6) =30, OEN = 27
9067 12:39:12.040316 24, 0x0, End_B0=24 End_B1=24
9068 12:39:12.043740 25, 0x0, End_B0=25 End_B1=25
9069 12:39:12.046970 26, 0x0, End_B0=26 End_B1=26
9070 12:39:12.050185 27, 0x0, End_B0=27 End_B1=27
9071 12:39:12.050640 28, 0x0, End_B0=28 End_B1=28
9072 12:39:12.053361 29, 0x0, End_B0=29 End_B1=29
9073 12:39:12.056989 30, 0x0, End_B0=30 End_B1=30
9074 12:39:12.060046 31, 0x4545, End_B0=30 End_B1=30
9075 12:39:12.063867 Byte0 end_step=30 best_step=27
9076 12:39:12.064441 Byte1 end_step=30 best_step=27
9077 12:39:12.066798 Byte0 TX OE(2T, 0.5T) = (3, 3)
9078 12:39:12.070051 Byte1 TX OE(2T, 0.5T) = (3, 3)
9079 12:39:12.070503
9080 12:39:12.070966
9081 12:39:12.080246 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
9082 12:39:12.080812 CH1 RK1: MR19=303, MR18=F1B
9083 12:39:12.086995 CH1_RK1: MR19=0x303, MR18=0xF1B, DQSOSC=396, MR23=63, INC=23, DEC=15
9084 12:39:12.090219 [RxdqsGatingPostProcess] freq 1600
9085 12:39:12.097047 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9086 12:39:12.100228 best DQS0 dly(2T, 0.5T) = (1, 1)
9087 12:39:12.103129 best DQS1 dly(2T, 0.5T) = (1, 1)
9088 12:39:12.106535 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9089 12:39:12.109941 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9090 12:39:12.110390 best DQS0 dly(2T, 0.5T) = (1, 1)
9091 12:39:12.113411 best DQS1 dly(2T, 0.5T) = (1, 1)
9092 12:39:12.116650 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9093 12:39:12.120220 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9094 12:39:12.123270 Pre-setting of DQS Precalculation
9095 12:39:12.129576 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9096 12:39:12.136449 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9097 12:39:12.143072 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9098 12:39:12.143508
9099 12:39:12.143847
9100 12:39:12.146289 [Calibration Summary] 3200 Mbps
9101 12:39:12.146897 CH 0, Rank 0
9102 12:39:12.149541 SW Impedance : PASS
9103 12:39:12.152711 DUTY Scan : NO K
9104 12:39:12.153143 ZQ Calibration : PASS
9105 12:39:12.155997 Jitter Meter : NO K
9106 12:39:12.159479 CBT Training : PASS
9107 12:39:12.159911 Write leveling : PASS
9108 12:39:12.162582 RX DQS gating : PASS
9109 12:39:12.166096 RX DQ/DQS(RDDQC) : PASS
9110 12:39:12.166529 TX DQ/DQS : PASS
9111 12:39:12.169304 RX DATLAT : PASS
9112 12:39:12.169785 RX DQ/DQS(Engine): PASS
9113 12:39:12.172782 TX OE : PASS
9114 12:39:12.173337 All Pass.
9115 12:39:12.173783
9116 12:39:12.176190 CH 0, Rank 1
9117 12:39:12.176754 SW Impedance : PASS
9118 12:39:12.179719 DUTY Scan : NO K
9119 12:39:12.182721 ZQ Calibration : PASS
9120 12:39:12.183306 Jitter Meter : NO K
9121 12:39:12.186250 CBT Training : PASS
9122 12:39:12.189382 Write leveling : PASS
9123 12:39:12.189900 RX DQS gating : PASS
9124 12:39:12.192604 RX DQ/DQS(RDDQC) : PASS
9125 12:39:12.195925 TX DQ/DQS : PASS
9126 12:39:12.196519 RX DATLAT : PASS
9127 12:39:12.199288 RX DQ/DQS(Engine): PASS
9128 12:39:12.202148 TX OE : PASS
9129 12:39:12.202582 All Pass.
9130 12:39:12.202922
9131 12:39:12.203354 CH 1, Rank 0
9132 12:39:12.205583 SW Impedance : PASS
9133 12:39:12.208836 DUTY Scan : NO K
9134 12:39:12.209267 ZQ Calibration : PASS
9135 12:39:12.212264 Jitter Meter : NO K
9136 12:39:12.215456 CBT Training : PASS
9137 12:39:12.215889 Write leveling : PASS
9138 12:39:12.218791 RX DQS gating : PASS
9139 12:39:12.222342 RX DQ/DQS(RDDQC) : PASS
9140 12:39:12.222789 TX DQ/DQS : PASS
9141 12:39:12.225536 RX DATLAT : PASS
9142 12:39:12.226148 RX DQ/DQS(Engine): PASS
9143 12:39:12.228999 TX OE : PASS
9144 12:39:12.229448 All Pass.
9145 12:39:12.229944
9146 12:39:12.232248 CH 1, Rank 1
9147 12:39:12.232694 SW Impedance : PASS
9148 12:39:12.235615 DUTY Scan : NO K
9149 12:39:12.238901 ZQ Calibration : PASS
9150 12:39:12.239348 Jitter Meter : NO K
9151 12:39:12.242243 CBT Training : PASS
9152 12:39:12.245589 Write leveling : PASS
9153 12:39:12.246033 RX DQS gating : PASS
9154 12:39:12.248857 RX DQ/DQS(RDDQC) : PASS
9155 12:39:12.251648 TX DQ/DQS : PASS
9156 12:39:12.251735 RX DATLAT : PASS
9157 12:39:12.254833 RX DQ/DQS(Engine): PASS
9158 12:39:12.258396 TX OE : PASS
9159 12:39:12.258486 All Pass.
9160 12:39:12.258573
9161 12:39:12.261594 DramC Write-DBI on
9162 12:39:12.261682 PER_BANK_REFRESH: Hybrid Mode
9163 12:39:12.264800 TX_TRACKING: ON
9164 12:39:12.274739 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9165 12:39:12.281732 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9166 12:39:12.288001 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9167 12:39:12.291575 [FAST_K] Save calibration result to emmc
9168 12:39:12.294843 sync common calibartion params.
9169 12:39:12.298265 sync cbt_mode0:1, 1:1
9170 12:39:12.298349 dram_init: ddr_geometry: 2
9171 12:39:12.301469 dram_init: ddr_geometry: 2
9172 12:39:12.304796 dram_init: ddr_geometry: 2
9173 12:39:12.308225 0:dram_rank_size:100000000
9174 12:39:12.308310 1:dram_rank_size:100000000
9175 12:39:12.314729 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9176 12:39:12.318126 DFS_SHUFFLE_HW_MODE: ON
9177 12:39:12.321395 dramc_set_vcore_voltage set vcore to 725000
9178 12:39:12.321506 Read voltage for 1600, 0
9179 12:39:12.324713 Vio18 = 0
9180 12:39:12.324815 Vcore = 725000
9181 12:39:12.324891 Vdram = 0
9182 12:39:12.327951 Vddq = 0
9183 12:39:12.328047 Vmddr = 0
9184 12:39:12.331544 switch to 3200 Mbps bootup
9185 12:39:12.331641 [DramcRunTimeConfig]
9186 12:39:12.331717 PHYPLL
9187 12:39:12.334465 DPM_CONTROL_AFTERK: ON
9188 12:39:12.337885 PER_BANK_REFRESH: ON
9189 12:39:12.337982 REFRESH_OVERHEAD_REDUCTION: ON
9190 12:39:12.341638 CMD_PICG_NEW_MODE: OFF
9191 12:39:12.344528 XRTWTW_NEW_MODE: ON
9192 12:39:12.344625 XRTRTR_NEW_MODE: ON
9193 12:39:12.347873 TX_TRACKING: ON
9194 12:39:12.347970 RDSEL_TRACKING: OFF
9195 12:39:12.351529 DQS Precalculation for DVFS: ON
9196 12:39:12.351625 RX_TRACKING: OFF
9197 12:39:12.354711 HW_GATING DBG: ON
9198 12:39:12.358055 ZQCS_ENABLE_LP4: ON
9199 12:39:12.358154 RX_PICG_NEW_MODE: ON
9200 12:39:12.361321 TX_PICG_NEW_MODE: ON
9201 12:39:12.361418 ENABLE_RX_DCM_DPHY: ON
9202 12:39:12.364473 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9203 12:39:12.367656 DUMMY_READ_FOR_TRACKING: OFF
9204 12:39:12.371139 !!! SPM_CONTROL_AFTERK: OFF
9205 12:39:12.374388 !!! SPM could not control APHY
9206 12:39:12.374494 IMPEDANCE_TRACKING: ON
9207 12:39:12.377692 TEMP_SENSOR: ON
9208 12:39:12.377806 HW_SAVE_FOR_SR: OFF
9209 12:39:12.381011 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9210 12:39:12.384424 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9211 12:39:12.387853 Read ODT Tracking: ON
9212 12:39:12.390988 Refresh Rate DeBounce: ON
9213 12:39:12.391112 DFS_NO_QUEUE_FLUSH: ON
9214 12:39:12.394319 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9215 12:39:12.397958 ENABLE_DFS_RUNTIME_MRW: OFF
9216 12:39:12.400989 DDR_RESERVE_NEW_MODE: ON
9217 12:39:12.401114 MR_CBT_SWITCH_FREQ: ON
9218 12:39:12.404272 =========================
9219 12:39:12.422628 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9220 12:39:12.425935 dram_init: ddr_geometry: 2
9221 12:39:12.444138 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9222 12:39:12.447879 dram_init: dram init end (result: 0)
9223 12:39:12.454464 DRAM-K: Full calibration passed in 24549 msecs
9224 12:39:12.457872 MRC: failed to locate region type 0.
9225 12:39:12.458423 DRAM rank0 size:0x100000000,
9226 12:39:12.461181 DRAM rank1 size=0x100000000
9227 12:39:12.471178 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9228 12:39:12.477953 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9229 12:39:12.484757 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9230 12:39:12.491225 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9231 12:39:12.494461 DRAM rank0 size:0x100000000,
9232 12:39:12.497920 DRAM rank1 size=0x100000000
9233 12:39:12.498540 CBMEM:
9234 12:39:12.501237 IMD: root @ 0xfffff000 254 entries.
9235 12:39:12.504545 IMD: root @ 0xffffec00 62 entries.
9236 12:39:12.507664 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9237 12:39:12.514058 WARNING: RO_VPD is uninitialized or empty.
9238 12:39:12.517381 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9239 12:39:12.524586 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9240 12:39:12.537521 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9241 12:39:12.548617 BS: romstage times (exec / console): total (unknown) / 24014 ms
9242 12:39:12.549066
9243 12:39:12.549547
9244 12:39:12.558875 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9245 12:39:12.562267 ARM64: Exception handlers installed.
9246 12:39:12.565535 ARM64: Testing exception
9247 12:39:12.568731 ARM64: Done test exception
9248 12:39:12.569196 Enumerating buses...
9249 12:39:12.571865 Show all devs... Before device enumeration.
9250 12:39:12.575378 Root Device: enabled 1
9251 12:39:12.578532 CPU_CLUSTER: 0: enabled 1
9252 12:39:12.579011 CPU: 00: enabled 1
9253 12:39:12.581669 Compare with tree...
9254 12:39:12.582115 Root Device: enabled 1
9255 12:39:12.585274 CPU_CLUSTER: 0: enabled 1
9256 12:39:12.588687 CPU: 00: enabled 1
9257 12:39:12.589134 Root Device scanning...
9258 12:39:12.591584 scan_static_bus for Root Device
9259 12:39:12.594855 CPU_CLUSTER: 0 enabled
9260 12:39:12.598122 scan_static_bus for Root Device done
9261 12:39:12.601447 scan_bus: bus Root Device finished in 8 msecs
9262 12:39:12.601937 done
9263 12:39:12.608003 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9264 12:39:12.611316 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9265 12:39:12.617698 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9266 12:39:12.621235 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9267 12:39:12.624202 Allocating resources...
9268 12:39:12.627786 Reading resources...
9269 12:39:12.631033 Root Device read_resources bus 0 link: 0
9270 12:39:12.634497 DRAM rank0 size:0x100000000,
9271 12:39:12.634584 DRAM rank1 size=0x100000000
9272 12:39:12.637800 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9273 12:39:12.640869 CPU: 00 missing read_resources
9274 12:39:12.647407 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9275 12:39:12.650878 Root Device read_resources bus 0 link: 0 done
9276 12:39:12.650965 Done reading resources.
9277 12:39:12.657344 Show resources in subtree (Root Device)...After reading.
9278 12:39:12.660590 Root Device child on link 0 CPU_CLUSTER: 0
9279 12:39:12.664095 CPU_CLUSTER: 0 child on link 0 CPU: 00
9280 12:39:12.674097 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9281 12:39:12.674191 CPU: 00
9282 12:39:12.677380 Root Device assign_resources, bus 0 link: 0
9283 12:39:12.680522 CPU_CLUSTER: 0 missing set_resources
9284 12:39:12.687158 Root Device assign_resources, bus 0 link: 0 done
9285 12:39:12.687267 Done setting resources.
9286 12:39:12.693810 Show resources in subtree (Root Device)...After assigning values.
9287 12:39:12.697093 Root Device child on link 0 CPU_CLUSTER: 0
9288 12:39:12.700574 CPU_CLUSTER: 0 child on link 0 CPU: 00
9289 12:39:12.710331 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9290 12:39:12.710419 CPU: 00
9291 12:39:12.713719 Done allocating resources.
9292 12:39:12.720257 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9293 12:39:12.720344 Enabling resources...
9294 12:39:12.720432 done.
9295 12:39:12.726866 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9296 12:39:12.730209 Initializing devices...
9297 12:39:12.730305 Root Device init
9298 12:39:12.733621 init hardware done!
9299 12:39:12.733714 0x00000018: ctrlr->caps
9300 12:39:12.736780 52.000 MHz: ctrlr->f_max
9301 12:39:12.740110 0.400 MHz: ctrlr->f_min
9302 12:39:12.740305 0x40ff8080: ctrlr->voltages
9303 12:39:12.743918 sclk: 390625
9304 12:39:12.744118 Bus Width = 1
9305 12:39:12.744259 sclk: 390625
9306 12:39:12.746771 Bus Width = 1
9307 12:39:12.750011 Early init status = 3
9308 12:39:12.753787 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9309 12:39:12.756942 in-header: 03 fc 00 00 01 00 00 00
9310 12:39:12.760581 in-data: 00
9311 12:39:12.763653 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9312 12:39:12.768860 in-header: 03 fd 00 00 00 00 00 00
9313 12:39:12.772618 in-data:
9314 12:39:12.775689 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9315 12:39:12.779894 in-header: 03 fc 00 00 01 00 00 00
9316 12:39:12.783393 in-data: 00
9317 12:39:12.786683 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9318 12:39:12.792484 in-header: 03 fd 00 00 00 00 00 00
9319 12:39:12.795667 in-data:
9320 12:39:12.798726 [SSUSB] Setting up USB HOST controller...
9321 12:39:12.802516 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9322 12:39:12.805926 [SSUSB] phy power-on done.
9323 12:39:12.808783 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9324 12:39:12.815657 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9325 12:39:12.818946 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9326 12:39:12.825501 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9327 12:39:12.832034 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9328 12:39:12.838940 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9329 12:39:12.845458 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9330 12:39:12.852162 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9331 12:39:12.855665 SPM: binary array size = 0x9dc
9332 12:39:12.859002 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9333 12:39:12.865404 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9334 12:39:12.872316 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9335 12:39:12.875845 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9336 12:39:12.882180 configure_display: Starting display init
9337 12:39:12.915812 anx7625_power_on_init: Init interface.
9338 12:39:12.919257 anx7625_disable_pd_protocol: Disabled PD feature.
9339 12:39:12.922218 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9340 12:39:12.949997 anx7625_start_dp_work: Secure OCM version=00
9341 12:39:12.953333 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9342 12:39:12.968430 sp_tx_get_edid_block: EDID Block = 1
9343 12:39:13.070496 Extracted contents:
9344 12:39:13.073880 header: 00 ff ff ff ff ff ff 00
9345 12:39:13.077308 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9346 12:39:13.080338 version: 01 04
9347 12:39:13.084099 basic params: 95 1f 11 78 0a
9348 12:39:13.087649 chroma info: 76 90 94 55 54 90 27 21 50 54
9349 12:39:13.090811 established: 00 00 00
9350 12:39:13.097464 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9351 12:39:13.100641 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9352 12:39:13.107326 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9353 12:39:13.114166 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9354 12:39:13.120576 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9355 12:39:13.124161 extensions: 00
9356 12:39:13.124746 checksum: fb
9357 12:39:13.125128
9358 12:39:13.127125 Manufacturer: IVO Model 57d Serial Number 0
9359 12:39:13.130165 Made week 0 of 2020
9360 12:39:13.130635 EDID version: 1.4
9361 12:39:13.133551 Digital display
9362 12:39:13.136791 6 bits per primary color channel
9363 12:39:13.137240 DisplayPort interface
9364 12:39:13.140332 Maximum image size: 31 cm x 17 cm
9365 12:39:13.143581 Gamma: 220%
9366 12:39:13.144008 Check DPMS levels
9367 12:39:13.146679 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9368 12:39:13.153492 First detailed timing is preferred timing
9369 12:39:13.153803 Established timings supported:
9370 12:39:13.156964 Standard timings supported:
9371 12:39:13.159935 Detailed timings
9372 12:39:13.163192 Hex of detail: 383680a07038204018303c0035ae10000019
9373 12:39:13.166825 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9374 12:39:13.173546 0780 0798 07c8 0820 hborder 0
9375 12:39:13.176764 0438 043b 0447 0458 vborder 0
9376 12:39:13.180166 -hsync -vsync
9377 12:39:13.180700 Did detailed timing
9378 12:39:13.186421 Hex of detail: 000000000000000000000000000000000000
9379 12:39:13.186937 Manufacturer-specified data, tag 0
9380 12:39:13.193099 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9381 12:39:13.196890 ASCII string: InfoVision
9382 12:39:13.199742 Hex of detail: 000000fe00523134304e574635205248200a
9383 12:39:13.203541 ASCII string: R140NWF5 RH
9384 12:39:13.204073 Checksum
9385 12:39:13.206501 Checksum: 0xfb (valid)
9386 12:39:13.210188 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9387 12:39:13.213441 DSI data_rate: 832800000 bps
9388 12:39:13.219966 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9389 12:39:13.223229 anx7625_parse_edid: pixelclock(138800).
9390 12:39:13.226428 hactive(1920), hsync(48), hfp(24), hbp(88)
9391 12:39:13.229744 vactive(1080), vsync(12), vfp(3), vbp(17)
9392 12:39:13.232930 anx7625_dsi_config: config dsi.
9393 12:39:13.239736 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9394 12:39:13.252782 anx7625_dsi_config: success to config DSI
9395 12:39:13.256227 anx7625_dp_start: MIPI phy setup OK.
9396 12:39:13.259459 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9397 12:39:13.262842 mtk_ddp_mode_set invalid vrefresh 60
9398 12:39:13.266081 main_disp_path_setup
9399 12:39:13.266506 ovl_layer_smi_id_en
9400 12:39:13.269422 ovl_layer_smi_id_en
9401 12:39:13.269884 ccorr_config
9402 12:39:13.270219 aal_config
9403 12:39:13.272410 gamma_config
9404 12:39:13.272864 postmask_config
9405 12:39:13.276106 dither_config
9406 12:39:13.279707 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9407 12:39:13.285996 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9408 12:39:13.289337 Root Device init finished in 555 msecs
9409 12:39:13.292420 CPU_CLUSTER: 0 init
9410 12:39:13.299347 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9411 12:39:13.302405 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9412 12:39:13.306074 APU_MBOX 0x190000b0 = 0x10001
9413 12:39:13.309008 APU_MBOX 0x190001b0 = 0x10001
9414 12:39:13.312577 APU_MBOX 0x190005b0 = 0x10001
9415 12:39:13.315860 APU_MBOX 0x190006b0 = 0x10001
9416 12:39:13.319187 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9417 12:39:13.331636 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9418 12:39:13.344500 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9419 12:39:13.350727 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9420 12:39:13.362520 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9421 12:39:13.371408 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9422 12:39:13.374863 CPU_CLUSTER: 0 init finished in 81 msecs
9423 12:39:13.378055 Devices initialized
9424 12:39:13.381461 Show all devs... After init.
9425 12:39:13.381927 Root Device: enabled 1
9426 12:39:13.385076 CPU_CLUSTER: 0: enabled 1
9427 12:39:13.388397 CPU: 00: enabled 1
9428 12:39:13.391347 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9429 12:39:13.394639 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9430 12:39:13.398193 ELOG: NV offset 0x57f000 size 0x1000
9431 12:39:13.404845 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9432 12:39:13.411414 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9433 12:39:13.414821 ELOG: Event(17) added with size 13 at 2024-02-05 12:39:17 UTC
9434 12:39:13.417824 out: cmd=0x121: 03 db 21 01 00 00 00 00
9435 12:39:13.421990 in-header: 03 75 00 00 2c 00 00 00
9436 12:39:13.435287 in-data: ea 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9437 12:39:13.441969 ELOG: Event(A1) added with size 10 at 2024-02-05 12:39:17 UTC
9438 12:39:13.448467 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9439 12:39:13.455264 ELOG: Event(A0) added with size 9 at 2024-02-05 12:39:17 UTC
9440 12:39:13.458362 elog_add_boot_reason: Logged dev mode boot
9441 12:39:13.461586 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9442 12:39:13.464965 Finalize devices...
9443 12:39:13.465624 Devices finalized
9444 12:39:13.471583 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9445 12:39:13.474784 Writing coreboot table at 0xffe64000
9446 12:39:13.478015 0. 000000000010a000-0000000000113fff: RAMSTAGE
9447 12:39:13.481502 1. 0000000040000000-00000000400fffff: RAM
9448 12:39:13.488355 2. 0000000040100000-000000004032afff: RAMSTAGE
9449 12:39:13.491486 3. 000000004032b000-00000000545fffff: RAM
9450 12:39:13.494691 4. 0000000054600000-000000005465ffff: BL31
9451 12:39:13.498207 5. 0000000054660000-00000000ffe63fff: RAM
9452 12:39:13.504950 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9453 12:39:13.508128 7. 0000000100000000-000000023fffffff: RAM
9454 12:39:13.508569 Passing 5 GPIOs to payload:
9455 12:39:13.514598 NAME | PORT | POLARITY | VALUE
9456 12:39:13.517930 EC in RW | 0x000000aa | low | undefined
9457 12:39:13.524436 EC interrupt | 0x00000005 | low | undefined
9458 12:39:13.528062 TPM interrupt | 0x000000ab | high | undefined
9459 12:39:13.531190 SD card detect | 0x00000011 | high | undefined
9460 12:39:13.538032 speaker enable | 0x00000093 | high | undefined
9461 12:39:13.541167 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9462 12:39:13.544321 in-header: 03 f9 00 00 02 00 00 00
9463 12:39:13.547720 in-data: 02 00
9464 12:39:13.548284 ADC[4]: Raw value=897780 ID=7
9465 12:39:13.550919 ADC[3]: Raw value=213440 ID=1
9466 12:39:13.554538 RAM Code: 0x71
9467 12:39:13.554983 ADC[6]: Raw value=74722 ID=0
9468 12:39:13.557917 ADC[5]: Raw value=212330 ID=1
9469 12:39:13.561181 SKU Code: 0x1
9470 12:39:13.564377 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 21e3
9471 12:39:13.567539 coreboot table: 964 bytes.
9472 12:39:13.571093 IMD ROOT 0. 0xfffff000 0x00001000
9473 12:39:13.574106 IMD SMALL 1. 0xffffe000 0x00001000
9474 12:39:13.577524 RO MCACHE 2. 0xffffc000 0x00001104
9475 12:39:13.580685 CONSOLE 3. 0xfff7c000 0x00080000
9476 12:39:13.584148 FMAP 4. 0xfff7b000 0x00000452
9477 12:39:13.587361 TIME STAMP 5. 0xfff7a000 0x00000910
9478 12:39:13.590693 VBOOT WORK 6. 0xfff66000 0x00014000
9479 12:39:13.594142 RAMOOPS 7. 0xffe66000 0x00100000
9480 12:39:13.597345 COREBOOT 8. 0xffe64000 0x00002000
9481 12:39:13.600523 IMD small region:
9482 12:39:13.603936 IMD ROOT 0. 0xffffec00 0x00000400
9483 12:39:13.607396 VPD 1. 0xffffeb80 0x0000006c
9484 12:39:13.610746 MMC STATUS 2. 0xffffeb60 0x00000004
9485 12:39:13.614090 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9486 12:39:13.617169 Probing TPM: done!
9487 12:39:13.621007 Connected to device vid:did:rid of 1ae0:0028:00
9488 12:39:13.631373 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9489 12:39:13.634462 Initialized TPM device CR50 revision 0
9490 12:39:13.638423 Checking cr50 for pending updates
9491 12:39:13.641918 Reading cr50 TPM mode
9492 12:39:13.650547 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9493 12:39:13.657325 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9494 12:39:13.697438 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9495 12:39:13.700712 Checking segment from ROM address 0x40100000
9496 12:39:13.704039 Checking segment from ROM address 0x4010001c
9497 12:39:13.710734 Loading segment from ROM address 0x40100000
9498 12:39:13.711315 code (compression=0)
9499 12:39:13.720677 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9500 12:39:13.727155 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9501 12:39:13.727745 it's not compressed!
9502 12:39:13.733963 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9503 12:39:13.737088 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9504 12:39:13.757708 Loading segment from ROM address 0x4010001c
9505 12:39:13.758235 Entry Point 0x80000000
9506 12:39:13.760988 Loaded segments
9507 12:39:13.764592 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9508 12:39:13.771101 Jumping to boot code at 0x80000000(0xffe64000)
9509 12:39:13.777604 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9510 12:39:13.784328 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9511 12:39:13.792130 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9512 12:39:13.795596 Checking segment from ROM address 0x40100000
9513 12:39:13.798897 Checking segment from ROM address 0x4010001c
9514 12:39:13.805785 Loading segment from ROM address 0x40100000
9515 12:39:13.806438 code (compression=1)
9516 12:39:13.812079 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9517 12:39:13.821945 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9518 12:39:13.822547 using LZMA
9519 12:39:13.830405 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9520 12:39:13.837230 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9521 12:39:13.840417 Loading segment from ROM address 0x4010001c
9522 12:39:13.840848 Entry Point 0x54601000
9523 12:39:13.843810 Loaded segments
9524 12:39:13.847108 NOTICE: MT8192 bl31_setup
9525 12:39:13.854164 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9526 12:39:13.857729 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9527 12:39:13.860801 WARNING: region 0:
9528 12:39:13.863906 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9529 12:39:13.864342 WARNING: region 1:
9530 12:39:13.870604 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9531 12:39:13.874042 WARNING: region 2:
9532 12:39:13.876840 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9533 12:39:13.880672 WARNING: region 3:
9534 12:39:13.883911 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9535 12:39:13.887228 WARNING: region 4:
9536 12:39:13.893888 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9537 12:39:13.894410 WARNING: region 5:
9538 12:39:13.897362 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9539 12:39:13.900608 WARNING: region 6:
9540 12:39:13.904124 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9541 12:39:13.907420 WARNING: region 7:
9542 12:39:13.910591 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9543 12:39:13.917281 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9544 12:39:13.920976 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9545 12:39:13.923943 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9546 12:39:13.930517 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9547 12:39:13.933797 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9548 12:39:13.937209 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9549 12:39:13.943842 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9550 12:39:13.947255 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9551 12:39:13.953896 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9552 12:39:13.957273 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9553 12:39:13.960663 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9554 12:39:13.967217 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9555 12:39:13.970308 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9556 12:39:13.973696 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9557 12:39:13.980612 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9558 12:39:13.983666 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9559 12:39:13.990372 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9560 12:39:13.993602 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9561 12:39:13.997213 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9562 12:39:14.003807 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9563 12:39:14.007160 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9564 12:39:14.010703 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9565 12:39:14.017408 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9566 12:39:14.020824 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9567 12:39:14.027401 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9568 12:39:14.030932 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9569 12:39:14.034029 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9570 12:39:14.040459 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9571 12:39:14.043834 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9572 12:39:14.050661 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9573 12:39:14.054116 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9574 12:39:14.057534 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9575 12:39:14.063918 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9576 12:39:14.067442 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9577 12:39:14.070626 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9578 12:39:14.074044 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9579 12:39:14.077442 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9580 12:39:14.084451 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9581 12:39:14.087708 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9582 12:39:14.090882 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9583 12:39:14.094233 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9584 12:39:14.101057 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9585 12:39:14.103860 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9586 12:39:14.107114 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9587 12:39:14.114017 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9588 12:39:14.117511 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9589 12:39:14.120668 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9590 12:39:14.123937 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9591 12:39:14.130812 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9592 12:39:14.134288 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9593 12:39:14.140823 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9594 12:39:14.143922 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9595 12:39:14.147521 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9596 12:39:14.154378 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9597 12:39:14.157432 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9598 12:39:14.164148 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9599 12:39:14.167365 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9600 12:39:14.170727 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9601 12:39:14.177542 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9602 12:39:14.180831 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9603 12:39:14.187473 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9604 12:39:14.190638 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9605 12:39:14.197434 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9606 12:39:14.200768 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9607 12:39:14.207274 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9608 12:39:14.210885 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9609 12:39:14.213877 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9610 12:39:14.220692 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9611 12:39:14.224009 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9612 12:39:14.230641 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9613 12:39:14.233933 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9614 12:39:14.240849 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9615 12:39:14.243979 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9616 12:39:14.247210 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9617 12:39:14.254001 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9618 12:39:14.257310 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9619 12:39:14.263794 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9620 12:39:14.267442 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9621 12:39:14.273790 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9622 12:39:14.277253 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9623 12:39:14.284025 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9624 12:39:14.287270 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9625 12:39:14.290650 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9626 12:39:14.297279 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9627 12:39:14.300374 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9628 12:39:14.307174 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9629 12:39:14.310519 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9630 12:39:14.317345 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9631 12:39:14.320706 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9632 12:39:14.323859 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9633 12:39:14.330570 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9634 12:39:14.334110 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9635 12:39:14.340711 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9636 12:39:14.343913 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9637 12:39:14.350812 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9638 12:39:14.353958 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9639 12:39:14.357280 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9640 12:39:14.364084 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9641 12:39:14.367194 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9642 12:39:14.370458 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9643 12:39:14.374017 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9644 12:39:14.380635 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9645 12:39:14.384171 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9646 12:39:14.387270 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9647 12:39:14.394244 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9648 12:39:14.397629 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9649 12:39:14.404044 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9650 12:39:14.407287 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9651 12:39:14.410749 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9652 12:39:14.417369 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9653 12:39:14.420930 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9654 12:39:14.427705 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9655 12:39:14.430869 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9656 12:39:14.434270 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9657 12:39:14.440705 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9658 12:39:14.444120 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9659 12:39:14.447306 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9660 12:39:14.453943 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9661 12:39:14.457560 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9662 12:39:14.460647 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9663 12:39:14.463866 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9664 12:39:14.470752 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9665 12:39:14.473994 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9666 12:39:14.477256 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9667 12:39:14.483993 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9668 12:39:14.487240 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9669 12:39:14.490821 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9670 12:39:14.497357 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9671 12:39:14.500798 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9672 12:39:14.507703 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9673 12:39:14.510774 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9674 12:39:14.514123 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9675 12:39:14.520724 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9676 12:39:14.523777 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9677 12:39:14.530701 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9678 12:39:14.534267 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9679 12:39:14.537316 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9680 12:39:14.544220 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9681 12:39:14.547297 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9682 12:39:14.550578 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9683 12:39:14.557360 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9684 12:39:14.560698 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9685 12:39:14.567635 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9686 12:39:14.570600 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9687 12:39:14.574110 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9688 12:39:14.580617 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9689 12:39:14.583917 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9690 12:39:14.587495 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9691 12:39:14.594208 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9692 12:39:14.597635 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9693 12:39:14.604042 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9694 12:39:14.607534 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9695 12:39:14.610812 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9696 12:39:14.617426 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9697 12:39:14.620894 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9698 12:39:14.627705 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9699 12:39:14.630726 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9700 12:39:14.634004 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9701 12:39:14.640664 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9702 12:39:14.643886 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9703 12:39:14.650752 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9704 12:39:14.653867 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9705 12:39:14.657215 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9706 12:39:14.664027 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9707 12:39:14.667532 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9708 12:39:14.670892 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9709 12:39:14.677417 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9710 12:39:14.680638 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9711 12:39:14.687073 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9712 12:39:14.690668 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9713 12:39:14.693960 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9714 12:39:14.700633 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9715 12:39:14.703756 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9716 12:39:14.710665 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9717 12:39:14.713999 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9718 12:39:14.717209 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9719 12:39:14.723676 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9720 12:39:14.727010 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9721 12:39:14.733635 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9722 12:39:14.737128 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9723 12:39:14.740266 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9724 12:39:14.747015 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9725 12:39:14.750150 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9726 12:39:14.756965 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9727 12:39:14.759967 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9728 12:39:14.763719 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9729 12:39:14.770135 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9730 12:39:14.773473 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9731 12:39:14.779938 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9732 12:39:14.783419 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9733 12:39:14.786798 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9734 12:39:14.793046 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9735 12:39:14.796391 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9736 12:39:14.803173 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9737 12:39:14.806518 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9738 12:39:14.809853 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9739 12:39:14.816440 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9740 12:39:14.819629 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9741 12:39:14.826273 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9742 12:39:14.829450 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9743 12:39:14.836386 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9744 12:39:14.839446 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9745 12:39:14.842881 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9746 12:39:14.849247 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9747 12:39:14.852611 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9748 12:39:14.859351 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9749 12:39:14.862488 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9750 12:39:14.869114 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9751 12:39:14.872823 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9752 12:39:14.876035 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9753 12:39:14.882440 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9754 12:39:14.886118 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9755 12:39:14.892490 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9756 12:39:14.895616 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9757 12:39:14.899177 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9758 12:39:14.905669 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9759 12:39:14.908991 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9760 12:39:14.915601 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9761 12:39:14.918858 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9762 12:39:14.925599 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9763 12:39:14.928743 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9764 12:39:14.932028 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9765 12:39:14.938501 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9766 12:39:14.941943 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9767 12:39:14.948713 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9768 12:39:14.951784 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9769 12:39:14.955439 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9770 12:39:14.962024 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9771 12:39:14.965597 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9772 12:39:14.968616 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9773 12:39:14.975294 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9774 12:39:14.978570 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9775 12:39:14.982093 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9776 12:39:14.985641 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9777 12:39:14.992092 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9778 12:39:14.995205 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9779 12:39:15.002140 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9780 12:39:15.005491 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9781 12:39:15.008934 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9782 12:39:15.015517 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9783 12:39:15.018789 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9784 12:39:15.022224 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9785 12:39:15.028563 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9786 12:39:15.031721 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9787 12:39:15.038466 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9788 12:39:15.041910 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9789 12:39:15.045102 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9790 12:39:15.051706 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9791 12:39:15.054924 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9792 12:39:15.058341 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9793 12:39:15.065037 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9794 12:39:15.068241 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9795 12:39:15.074854 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9796 12:39:15.077864 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9797 12:39:15.081332 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9798 12:39:15.088259 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9799 12:39:15.091469 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9800 12:39:15.095020 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9801 12:39:15.101633 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9802 12:39:15.104537 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9803 12:39:15.108225 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9804 12:39:15.114437 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9805 12:39:15.118250 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9806 12:39:15.124485 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9807 12:39:15.127533 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9808 12:39:15.130778 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9809 12:39:15.137641 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9810 12:39:15.141085 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9811 12:39:15.144272 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9812 12:39:15.150746 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9813 12:39:15.154073 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9814 12:39:15.156957 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9815 12:39:15.160277 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9816 12:39:15.164345 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9817 12:39:15.170053 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9818 12:39:15.173549 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9819 12:39:15.176981 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9820 12:39:15.184036 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9821 12:39:15.187200 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9822 12:39:15.190262 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9823 12:39:15.193847 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9824 12:39:15.200616 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9825 12:39:15.203471 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9826 12:39:15.210417 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9827 12:39:15.213855 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9828 12:39:15.216820 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9829 12:39:15.223807 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9830 12:39:15.226813 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9831 12:39:15.233753 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9832 12:39:15.237031 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9833 12:39:15.240022 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9834 12:39:15.247013 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9835 12:39:15.249893 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9836 12:39:15.256573 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9837 12:39:15.260239 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9838 12:39:15.266557 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9839 12:39:15.270168 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9840 12:39:15.273086 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9841 12:39:15.279742 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9842 12:39:15.283037 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9843 12:39:15.290148 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9844 12:39:15.293648 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9845 12:39:15.296678 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9846 12:39:15.302931 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9847 12:39:15.306432 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9848 12:39:15.313088 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9849 12:39:15.316209 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9850 12:39:15.320041 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9851 12:39:15.326441 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9852 12:39:15.329578 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9853 12:39:15.336499 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9854 12:39:15.339549 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9855 12:39:15.346217 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9856 12:39:15.349860 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9857 12:39:15.352702 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9858 12:39:15.359806 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9859 12:39:15.363147 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9860 12:39:15.369392 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9861 12:39:15.372577 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9862 12:39:15.376124 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9863 12:39:15.382657 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9864 12:39:15.385827 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9865 12:39:15.389462 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9866 12:39:15.396157 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9867 12:39:15.399303 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9868 12:39:15.405863 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9869 12:39:15.409078 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9870 12:39:15.415581 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9871 12:39:15.419377 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9872 12:39:15.422478 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9873 12:39:15.429199 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9874 12:39:15.432184 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9875 12:39:15.439310 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9876 12:39:15.442401 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9877 12:39:15.449088 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9878 12:39:15.452448 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9879 12:39:15.455490 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9880 12:39:15.462139 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9881 12:39:15.465271 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9882 12:39:15.471850 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9883 12:39:15.475195 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9884 12:39:15.478767 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9885 12:39:15.485426 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9886 12:39:15.488666 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9887 12:39:15.495379 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9888 12:39:15.498532 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9889 12:39:15.501901 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9890 12:39:15.508422 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9891 12:39:15.512125 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9892 12:39:15.518578 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9893 12:39:15.521831 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9894 12:39:15.528431 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9895 12:39:15.531735 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9896 12:39:15.535142 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9897 12:39:15.541688 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9898 12:39:15.545404 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9899 12:39:15.551950 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9900 12:39:15.555115 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9901 12:39:15.561723 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9902 12:39:15.565156 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9903 12:39:15.568000 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9904 12:39:15.574827 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9905 12:39:15.578183 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9906 12:39:15.584976 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9907 12:39:15.588249 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9908 12:39:15.594371 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9909 12:39:15.597995 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9910 12:39:15.600973 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9911 12:39:15.607625 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9912 12:39:15.611123 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9913 12:39:15.617823 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9914 12:39:15.621323 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9915 12:39:15.627648 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9916 12:39:15.631220 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9917 12:39:15.637645 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9918 12:39:15.641033 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9919 12:39:15.644336 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9920 12:39:15.650918 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9921 12:39:15.654012 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9922 12:39:15.661201 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9923 12:39:15.664047 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9924 12:39:15.670851 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9925 12:39:15.673813 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9926 12:39:15.680400 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9927 12:39:15.684031 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9928 12:39:15.687490 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9929 12:39:15.694267 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9930 12:39:15.697353 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9931 12:39:15.704190 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9932 12:39:15.707272 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9933 12:39:15.713653 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9934 12:39:15.717237 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9935 12:39:15.720399 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9936 12:39:15.727176 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9937 12:39:15.730588 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9938 12:39:15.737161 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9939 12:39:15.740698 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9940 12:39:15.747154 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9941 12:39:15.750164 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9942 12:39:15.753658 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9943 12:39:15.760394 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9944 12:39:15.763491 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9945 12:39:15.769944 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9946 12:39:15.773245 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9947 12:39:15.779809 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9948 12:39:15.783419 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9949 12:39:15.790161 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9950 12:39:15.793448 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9951 12:39:15.796848 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9952 12:39:15.803271 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9953 12:39:15.806724 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9954 12:39:15.813498 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9955 12:39:15.816432 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9956 12:39:15.823451 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9957 12:39:15.826385 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9958 12:39:15.833054 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9959 12:39:15.836519 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9960 12:39:15.843068 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9961 12:39:15.846382 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9962 12:39:15.853096 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9963 12:39:15.856366 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9964 12:39:15.862720 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9965 12:39:15.866300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9966 12:39:15.872826 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9967 12:39:15.875783 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9968 12:39:15.882676 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9969 12:39:15.885882 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9970 12:39:15.892847 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9971 12:39:15.896276 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9972 12:39:15.902779 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9973 12:39:15.906110 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9974 12:39:15.912655 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9975 12:39:15.916189 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9976 12:39:15.922389 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9977 12:39:15.925728 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9978 12:39:15.928829 INFO: [APUAPC] vio 0
9979 12:39:15.932288 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9980 12:39:15.939192 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9981 12:39:15.942689 INFO: [APUAPC] D0_APC_0: 0x400510
9982 12:39:15.943233 INFO: [APUAPC] D0_APC_1: 0x0
9983 12:39:15.946007 INFO: [APUAPC] D0_APC_2: 0x1540
9984 12:39:15.949081 INFO: [APUAPC] D0_APC_3: 0x0
9985 12:39:15.952675 INFO: [APUAPC] D1_APC_0: 0xffffffff
9986 12:39:15.955757 INFO: [APUAPC] D1_APC_1: 0xffffffff
9987 12:39:15.958798 INFO: [APUAPC] D1_APC_2: 0x3fffff
9988 12:39:15.962132 INFO: [APUAPC] D1_APC_3: 0x0
9989 12:39:15.965321 INFO: [APUAPC] D2_APC_0: 0xffffffff
9990 12:39:15.968518 INFO: [APUAPC] D2_APC_1: 0xffffffff
9991 12:39:15.971870 INFO: [APUAPC] D2_APC_2: 0x3fffff
9992 12:39:15.975418 INFO: [APUAPC] D2_APC_3: 0x0
9993 12:39:15.978544 INFO: [APUAPC] D3_APC_0: 0xffffffff
9994 12:39:15.982021 INFO: [APUAPC] D3_APC_1: 0xffffffff
9995 12:39:15.985589 INFO: [APUAPC] D3_APC_2: 0x3fffff
9996 12:39:15.988950 INFO: [APUAPC] D3_APC_3: 0x0
9997 12:39:15.991932 INFO: [APUAPC] D4_APC_0: 0xffffffff
9998 12:39:15.995540 INFO: [APUAPC] D4_APC_1: 0xffffffff
9999 12:39:15.998769 INFO: [APUAPC] D4_APC_2: 0x3fffff
10000 12:39:16.002149 INFO: [APUAPC] D4_APC_3: 0x0
10001 12:39:16.005089 INFO: [APUAPC] D5_APC_0: 0xffffffff
10002 12:39:16.008276 INFO: [APUAPC] D5_APC_1: 0xffffffff
10003 12:39:16.012245 INFO: [APUAPC] D5_APC_2: 0x3fffff
10004 12:39:16.015166 INFO: [APUAPC] D5_APC_3: 0x0
10005 12:39:16.018316 INFO: [APUAPC] D6_APC_0: 0xffffffff
10006 12:39:16.022318 INFO: [APUAPC] D6_APC_1: 0xffffffff
10007 12:39:16.025528 INFO: [APUAPC] D6_APC_2: 0x3fffff
10008 12:39:16.028647 INFO: [APUAPC] D6_APC_3: 0x0
10009 12:39:16.031641 INFO: [APUAPC] D7_APC_0: 0xffffffff
10010 12:39:16.035129 INFO: [APUAPC] D7_APC_1: 0xffffffff
10011 12:39:16.038620 INFO: [APUAPC] D7_APC_2: 0x3fffff
10012 12:39:16.042052 INFO: [APUAPC] D7_APC_3: 0x0
10013 12:39:16.045076 INFO: [APUAPC] D8_APC_0: 0xffffffff
10014 12:39:16.048772 INFO: [APUAPC] D8_APC_1: 0xffffffff
10015 12:39:16.052143 INFO: [APUAPC] D8_APC_2: 0x3fffff
10016 12:39:16.055358 INFO: [APUAPC] D8_APC_3: 0x0
10017 12:39:16.058324 INFO: [APUAPC] D9_APC_0: 0xffffffff
10018 12:39:16.061640 INFO: [APUAPC] D9_APC_1: 0xffffffff
10019 12:39:16.065163 INFO: [APUAPC] D9_APC_2: 0x3fffff
10020 12:39:16.068291 INFO: [APUAPC] D9_APC_3: 0x0
10021 12:39:16.071502 INFO: [APUAPC] D10_APC_0: 0xffffffff
10022 12:39:16.074785 INFO: [APUAPC] D10_APC_1: 0xffffffff
10023 12:39:16.078152 INFO: [APUAPC] D10_APC_2: 0x3fffff
10024 12:39:16.081552 INFO: [APUAPC] D10_APC_3: 0x0
10025 12:39:16.084776 INFO: [APUAPC] D11_APC_0: 0xffffffff
10026 12:39:16.088030 INFO: [APUAPC] D11_APC_1: 0xffffffff
10027 12:39:16.091642 INFO: [APUAPC] D11_APC_2: 0x3fffff
10028 12:39:16.094642 INFO: [APUAPC] D11_APC_3: 0x0
10029 12:39:16.097928 INFO: [APUAPC] D12_APC_0: 0xffffffff
10030 12:39:16.101411 INFO: [APUAPC] D12_APC_1: 0xffffffff
10031 12:39:16.104895 INFO: [APUAPC] D12_APC_2: 0x3fffff
10032 12:39:16.107875 INFO: [APUAPC] D12_APC_3: 0x0
10033 12:39:16.111514 INFO: [APUAPC] D13_APC_0: 0xffffffff
10034 12:39:16.114446 INFO: [APUAPC] D13_APC_1: 0xffffffff
10035 12:39:16.117844 INFO: [APUAPC] D13_APC_2: 0x3fffff
10036 12:39:16.121269 INFO: [APUAPC] D13_APC_3: 0x0
10037 12:39:16.124489 INFO: [APUAPC] D14_APC_0: 0xffffffff
10038 12:39:16.128138 INFO: [APUAPC] D14_APC_1: 0xffffffff
10039 12:39:16.131114 INFO: [APUAPC] D14_APC_2: 0x3fffff
10040 12:39:16.134412 INFO: [APUAPC] D14_APC_3: 0x0
10041 12:39:16.137992 INFO: [APUAPC] D15_APC_0: 0xffffffff
10042 12:39:16.141375 INFO: [APUAPC] D15_APC_1: 0xffffffff
10043 12:39:16.144676 INFO: [APUAPC] D15_APC_2: 0x3fffff
10044 12:39:16.148152 INFO: [APUAPC] D15_APC_3: 0x0
10045 12:39:16.151208 INFO: [APUAPC] APC_CON: 0x4
10046 12:39:16.154427 INFO: [NOCDAPC] D0_APC_0: 0x0
10047 12:39:16.154927 INFO: [NOCDAPC] D0_APC_1: 0x0
10048 12:39:16.157523 INFO: [NOCDAPC] D1_APC_0: 0x0
10049 12:39:16.160901 INFO: [NOCDAPC] D1_APC_1: 0xfff
10050 12:39:16.164364 INFO: [NOCDAPC] D2_APC_0: 0x0
10051 12:39:16.167631 INFO: [NOCDAPC] D2_APC_1: 0xfff
10052 12:39:16.170660 INFO: [NOCDAPC] D3_APC_0: 0x0
10053 12:39:16.174068 INFO: [NOCDAPC] D3_APC_1: 0xfff
10054 12:39:16.177371 INFO: [NOCDAPC] D4_APC_0: 0x0
10055 12:39:16.180910 INFO: [NOCDAPC] D4_APC_1: 0xfff
10056 12:39:16.184120 INFO: [NOCDAPC] D5_APC_0: 0x0
10057 12:39:16.187769 INFO: [NOCDAPC] D5_APC_1: 0xfff
10058 12:39:16.188312 INFO: [NOCDAPC] D6_APC_0: 0x0
10059 12:39:16.190423 INFO: [NOCDAPC] D6_APC_1: 0xfff
10060 12:39:16.193800 INFO: [NOCDAPC] D7_APC_0: 0x0
10061 12:39:16.197219 INFO: [NOCDAPC] D7_APC_1: 0xfff
10062 12:39:16.200802 INFO: [NOCDAPC] D8_APC_0: 0x0
10063 12:39:16.204054 INFO: [NOCDAPC] D8_APC_1: 0xfff
10064 12:39:16.207170 INFO: [NOCDAPC] D9_APC_0: 0x0
10065 12:39:16.210442 INFO: [NOCDAPC] D9_APC_1: 0xfff
10066 12:39:16.214172 INFO: [NOCDAPC] D10_APC_0: 0x0
10067 12:39:16.217582 INFO: [NOCDAPC] D10_APC_1: 0xfff
10068 12:39:16.220983 INFO: [NOCDAPC] D11_APC_0: 0x0
10069 12:39:16.223913 INFO: [NOCDAPC] D11_APC_1: 0xfff
10070 12:39:16.224456 INFO: [NOCDAPC] D12_APC_0: 0x0
10071 12:39:16.226987 INFO: [NOCDAPC] D12_APC_1: 0xfff
10072 12:39:16.230597 INFO: [NOCDAPC] D13_APC_0: 0x0
10073 12:39:16.233932 INFO: [NOCDAPC] D13_APC_1: 0xfff
10074 12:39:16.237000 INFO: [NOCDAPC] D14_APC_0: 0x0
10075 12:39:16.240493 INFO: [NOCDAPC] D14_APC_1: 0xfff
10076 12:39:16.244053 INFO: [NOCDAPC] D15_APC_0: 0x0
10077 12:39:16.247338 INFO: [NOCDAPC] D15_APC_1: 0xfff
10078 12:39:16.250165 INFO: [NOCDAPC] APC_CON: 0x4
10079 12:39:16.253758 INFO: [APUAPC] set_apusys_apc done
10080 12:39:16.256700 INFO: [DEVAPC] devapc_init done
10081 12:39:16.260109 INFO: GICv3 without legacy support detected.
10082 12:39:16.263797 INFO: ARM GICv3 driver initialized in EL3
10083 12:39:16.267335 INFO: Maximum SPI INTID supported: 639
10084 12:39:16.273539 INFO: BL31: Initializing runtime services
10085 12:39:16.276463 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10086 12:39:16.280264 INFO: SPM: enable CPC mode
10087 12:39:16.287122 INFO: mcdi ready for mcusys-off-idle and system suspend
10088 12:39:16.289811 INFO: BL31: Preparing for EL3 exit to normal world
10089 12:39:16.293260 INFO: Entry point address = 0x80000000
10090 12:39:16.296713 INFO: SPSR = 0x8
10091 12:39:16.302061
10092 12:39:16.302589
10093 12:39:16.302931
10094 12:39:16.305205 Starting depthcharge on Spherion...
10095 12:39:16.305786
10096 12:39:16.306136 Wipe memory regions:
10097 12:39:16.306459
10098 12:39:16.309013 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10099 12:39:16.309560 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10100 12:39:16.309970 Setting prompt string to ['asurada:']
10101 12:39:16.310381 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10102 12:39:16.311057 [0x00000040000000, 0x00000054600000)
10103 12:39:16.430749
10104 12:39:16.431306 [0x00000054660000, 0x00000080000000)
10105 12:39:16.691067
10106 12:39:16.691603 [0x000000821a7280, 0x000000ffe64000)
10107 12:39:17.435209
10108 12:39:17.435748 [0x00000100000000, 0x00000240000000)
10109 12:39:19.323454
10110 12:39:19.326726 Initializing XHCI USB controller at 0x11200000.
10111 12:39:20.364604
10112 12:39:20.367682 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10113 12:39:20.368151
10114 12:39:20.368504
10115 12:39:20.368824
10116 12:39:20.369637 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10118 12:39:20.471273 asurada: tftpboot 192.168.201.1 12703533/tftp-deploy-0ti03h9j/kernel/image.itb 12703533/tftp-deploy-0ti03h9j/kernel/cmdline
10119 12:39:20.471919 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10120 12:39:20.472460 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10121 12:39:20.476550 tftpboot 192.168.201.1 12703533/tftp-deploy-0ti03h9j/kernel/image.ittp-deploy-0ti03h9j/kernel/cmdline
10122 12:39:20.476991
10123 12:39:20.477332 Waiting for link
10124 12:39:20.637619
10125 12:39:20.638191 R8152: Initializing
10126 12:39:20.638537
10127 12:39:20.640578 Version 6 (ocp_data = 5c30)
10128 12:39:20.641010
10129 12:39:20.643706 R8152: Done initializing
10130 12:39:20.644138
10131 12:39:20.644481 Adding net device
10132 12:39:22.543846
10133 12:39:22.544353 done.
10134 12:39:22.544701
10135 12:39:22.545026 MAC: 00:24:32:30:78:ff
10136 12:39:22.545338
10137 12:39:22.546939 Sending DHCP discover... done.
10138 12:39:22.547373
10139 12:39:27.618032 Waiting for reply... done.
10140 12:39:27.618568
10141 12:39:27.618910 Sending DHCP request... done.
10142 12:39:27.621206
10143 12:39:27.621678 Waiting for reply... done.
10144 12:39:27.622028
10145 12:39:27.624475 My ip is 192.168.201.21
10146 12:39:27.624905
10147 12:39:27.627768 The DHCP server ip is 192.168.201.1
10148 12:39:27.628340
10149 12:39:27.631339 TFTP server IP predefined by user: 192.168.201.1
10150 12:39:27.631892
10151 12:39:27.637909 Bootfile predefined by user: 12703533/tftp-deploy-0ti03h9j/kernel/image.itb
10152 12:39:27.638382
10153 12:39:27.641175 Sending tftp read request... done.
10154 12:39:27.641650
10155 12:39:27.649384 Waiting for the transfer...
10156 12:39:27.649870
10157 12:39:28.298423 00000000 ################################################################
10158 12:39:28.298565
10159 12:39:28.850733 00080000 ################################################################
10160 12:39:28.850878
10161 12:39:29.387987 00100000 ################################################################
10162 12:39:29.388133
10163 12:39:29.916654 00180000 ################################################################
10164 12:39:29.916809
10165 12:39:30.471729 00200000 ################################################################
10166 12:39:30.471872
10167 12:39:31.091126 00280000 ################################################################
10168 12:39:31.091283
10169 12:39:31.665840 00300000 ################################################################
10170 12:39:31.666003
10171 12:39:32.240199 00380000 ################################################################
10172 12:39:32.240342
10173 12:39:32.785038 00400000 ################################################################
10174 12:39:32.785174
10175 12:39:33.329186 00480000 ################################################################
10176 12:39:33.329357
10177 12:39:33.858478 00500000 ################################################################
10178 12:39:33.858630
10179 12:39:34.389147 00580000 ################################################################
10180 12:39:34.389288
10181 12:39:34.936302 00600000 ################################################################
10182 12:39:34.936444
10183 12:39:35.476972 00680000 ################################################################
10184 12:39:35.477138
10185 12:39:36.012723 00700000 ################################################################
10186 12:39:36.012864
10187 12:39:36.572692 00780000 ################################################################
10188 12:39:36.572826
10189 12:39:37.147249 00800000 ################################################################
10190 12:39:37.147390
10191 12:39:37.735108 00880000 ################################################################
10192 12:39:37.735254
10193 12:39:38.280547 00900000 ################################################################
10194 12:39:38.280689
10195 12:39:38.811751 00980000 ################################################################
10196 12:39:38.811917
10197 12:39:39.368045 00a00000 ################################################################
10198 12:39:39.368194
10199 12:39:39.903832 00a80000 ################################################################
10200 12:39:39.904009
10201 12:39:40.443055 00b00000 ################################################################
10202 12:39:40.443196
10203 12:39:41.059564 00b80000 ################################################################
10204 12:39:41.060134
10205 12:39:41.651314 00c00000 ################################################################
10206 12:39:41.651450
10207 12:39:42.196430 00c80000 ################################################################
10208 12:39:42.196576
10209 12:39:42.766459 00d00000 ################################################################
10210 12:39:42.766607
10211 12:39:43.333620 00d80000 ################################################################
10212 12:39:43.333759
10213 12:39:43.909733 00e00000 ################################################################
10214 12:39:43.909893
10215 12:39:44.486495 00e80000 ################################################################
10216 12:39:44.486633
10217 12:39:45.074704 00f00000 ################################################################
10218 12:39:45.074871
10219 12:39:45.690379 00f80000 ################################################################
10220 12:39:45.691077
10221 12:39:46.334287 01000000 ################################################################
10222 12:39:46.334437
10223 12:39:46.895752 01080000 ################################################################
10224 12:39:46.895891
10225 12:39:47.421049 01100000 ################################################################
10226 12:39:47.421219
10227 12:39:47.967821 01180000 ################################################################
10228 12:39:47.967962
10229 12:39:48.523576 01200000 ################################################################
10230 12:39:48.523720
10231 12:39:49.078795 01280000 ################################################################
10232 12:39:49.078947
10233 12:39:49.626776 01300000 ################################################################
10234 12:39:49.626919
10235 12:39:50.202549 01380000 ################################################################
10236 12:39:50.202685
10237 12:39:50.786320 01400000 ################################################################
10238 12:39:50.786459
10239 12:39:51.372823 01480000 ################################################################
10240 12:39:51.373010
10241 12:39:51.947422 01500000 ################################################################
10242 12:39:51.947565
10243 12:39:52.576086 01580000 ################################################################
10244 12:39:52.576597
10245 12:39:53.239058 01600000 ################################################################
10246 12:39:53.239220
10247 12:39:53.853295 01680000 ################################################################
10248 12:39:53.853433
10249 12:39:54.473885 01700000 ################################################################
10250 12:39:54.474024
10251 12:39:55.118879 01780000 ################################################################
10252 12:39:55.119396
10253 12:39:55.813550 01800000 ################################################################
10254 12:39:55.814050
10255 12:39:56.513427 01880000 ################################################################
10256 12:39:56.513986
10257 12:39:57.209458 01900000 ################################################################
10258 12:39:57.210045
10259 12:39:57.905098 01980000 ################################################################
10260 12:39:57.906346
10261 12:39:58.609192 01a00000 ################################################################
10262 12:39:58.609778
10263 12:39:59.260843 01a80000 ################################################################
10264 12:39:59.261036
10265 12:39:59.939918 01b00000 ################################################################
10266 12:39:59.940514
10267 12:40:00.634194 01b80000 ################################################################
10268 12:40:00.634743
10269 12:40:01.309754 01c00000 ################################################################
10270 12:40:01.310260
10271 12:40:01.337303 01c80000 ### done.
10272 12:40:01.337900
10273 12:40:01.340509 The bootfile was 29904670 bytes long.
10274 12:40:01.340938
10275 12:40:01.343824 Sending tftp read request... done.
10276 12:40:01.344435
10277 12:40:01.348199 Waiting for the transfer...
10278 12:40:01.348673
10279 12:40:01.349047 00000000 # done.
10280 12:40:01.349642
10281 12:40:01.354834 Command line loaded dynamically from TFTP file: 12703533/tftp-deploy-0ti03h9j/kernel/cmdline
10282 12:40:01.355417
10283 12:40:01.378184 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12703533/extract-nfsrootfs-ijr2jn3z,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10284 12:40:01.378798
10285 12:40:01.379178 Loading FIT.
10286 12:40:01.379530
10287 12:40:01.381361 Image ramdisk-1 has 17802498 bytes.
10288 12:40:01.382013
10289 12:40:01.384872 Image fdt-1 has 47278 bytes.
10290 12:40:01.385344
10291 12:40:01.388215 Image kernel-1 has 12052857 bytes.
10292 12:40:01.388689
10293 12:40:01.397963 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10294 12:40:01.398541
10295 12:40:01.414713 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10296 12:40:01.415311
10297 12:40:01.421462 Choosing best match conf-1 for compat google,spherion-rev2.
10298 12:40:01.421986
10299 12:40:01.429034 Connected to device vid:did:rid of 1ae0:0028:00
10300 12:40:01.437197
10301 12:40:01.440421 tpm_get_response: command 0x17b, return code 0x0
10302 12:40:01.440902
10303 12:40:01.446848 ec_init: CrosEC protocol v3 supported (256, 248)
10304 12:40:01.447325
10305 12:40:01.450108 tpm_cleanup: add release locality here.
10306 12:40:01.450584
10307 12:40:01.453768 Shutting down all USB controllers.
10308 12:40:01.454244
10309 12:40:01.456947 Removing current net device
10310 12:40:01.457421
10311 12:40:01.460188 Exiting depthcharge with code 4 at timestamp: 74448640
10312 12:40:01.460664
10313 12:40:01.466924 LZMA decompressing kernel-1 to 0x821a6718
10314 12:40:01.467521
10315 12:40:01.470288 LZMA decompressing kernel-1 to 0x40000000
10316 12:40:02.968662
10317 12:40:02.969265 jumping to kernel
10318 12:40:02.971170 end: 2.2.4 bootloader-commands (duration 00:00:47) [common]
10319 12:40:02.971859 start: 2.2.5 auto-login-action (timeout 00:03:39) [common]
10320 12:40:02.972444 Setting prompt string to ['Linux version [0-9]']
10321 12:40:02.972968 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10322 12:40:02.973342 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10323 12:40:03.051092
10324 12:40:03.054272 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10325 12:40:03.058433 start: 2.2.5.1 login-action (timeout 00:03:38) [common]
10326 12:40:03.058922 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10327 12:40:03.059401 Setting prompt string to []
10328 12:40:03.059897 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10329 12:40:03.060346 Using line separator: #'\n'#
10330 12:40:03.060789 No login prompt set.
10331 12:40:03.061210 Parsing kernel messages
10332 12:40:03.061577 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10333 12:40:03.062122 [login-action] Waiting for messages, (timeout 00:03:38)
10334 12:40:03.062457 Waiting using forced prompt support (timeout 00:01:49)
10335 12:40:03.077783 [ 0.000000] Linux version 6.1.75-cip14 (KernelCI@build-j98433-arm64-gcc-10-defconfig-arm64-chromebook-89n64) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Feb 5 12:20:06 UTC 2024
10336 12:40:03.081031 [ 0.000000] random: crng init done
10337 12:40:03.087397 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10338 12:40:03.090684 [ 0.000000] efi: UEFI not found.
10339 12:40:03.097280 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10340 12:40:03.104005 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10341 12:40:03.113840 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10342 12:40:03.123983 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10343 12:40:03.130306 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10344 12:40:03.136931 [ 0.000000] printk: bootconsole [mtk8250] enabled
10345 12:40:03.143537 [ 0.000000] NUMA: No NUMA configuration found
10346 12:40:03.150283 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10347 12:40:03.153075 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10348 12:40:03.156815 [ 0.000000] Zone ranges:
10349 12:40:03.163164 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10350 12:40:03.166850 [ 0.000000] DMA32 empty
10351 12:40:03.173207 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10352 12:40:03.176465 [ 0.000000] Movable zone start for each node
10353 12:40:03.179765 [ 0.000000] Early memory node ranges
10354 12:40:03.186303 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10355 12:40:03.193226 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10356 12:40:03.199870 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10357 12:40:03.206288 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10358 12:40:03.213190 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10359 12:40:03.219229 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10360 12:40:03.275681 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10361 12:40:03.282248 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10362 12:40:03.289125 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10363 12:40:03.292349 [ 0.000000] psci: probing for conduit method from DT.
10364 12:40:03.298676 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10365 12:40:03.301847 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10366 12:40:03.308630 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10367 12:40:03.312415 [ 0.000000] psci: SMC Calling Convention v1.2
10368 12:40:03.318481 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10369 12:40:03.321577 [ 0.000000] Detected VIPT I-cache on CPU0
10370 12:40:03.328466 [ 0.000000] CPU features: detected: GIC system register CPU interface
10371 12:40:03.334948 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10372 12:40:03.341576 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10373 12:40:03.348257 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10374 12:40:03.355071 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10375 12:40:03.365420 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10376 12:40:03.368730 [ 0.000000] alternatives: applying boot alternatives
10377 12:40:03.375327 [ 0.000000] Fallback order for Node 0: 0
10378 12:40:03.381808 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10379 12:40:03.384782 [ 0.000000] Policy zone: Normal
10380 12:40:03.408058 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12703533/extract-nfsrootfs-ijr2jn3z,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10381 12:40:03.417930 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10382 12:40:03.428207 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10383 12:40:03.438243 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10384 12:40:03.444819 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10385 12:40:03.447893 <6>[ 0.000000] software IO TLB: area num 8.
10386 12:40:03.504861 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10387 12:40:03.653535 <6>[ 0.000000] Memory: 7949868K/8385536K available (17984K kernel code, 4118K rwdata, 19612K rodata, 8448K init, 616K bss, 402900K reserved, 32768K cma-reserved)
10388 12:40:03.660139 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10389 12:40:03.666537 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10390 12:40:03.670254 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10391 12:40:03.676732 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10392 12:40:03.683141 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10393 12:40:03.686747 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10394 12:40:03.696377 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10395 12:40:03.703238 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10396 12:40:03.709716 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10397 12:40:03.716396 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10398 12:40:03.719777 <6>[ 0.000000] GICv3: 608 SPIs implemented
10399 12:40:03.723059 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10400 12:40:03.729714 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10401 12:40:03.732964 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10402 12:40:03.739515 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10403 12:40:03.752567 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10404 12:40:03.765935 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10405 12:40:03.772441 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10406 12:40:03.780108 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10407 12:40:03.793162 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10408 12:40:03.799788 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10409 12:40:03.806447 <6>[ 0.009186] Console: colour dummy device 80x25
10410 12:40:03.816502 <6>[ 0.013913] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10411 12:40:03.823225 <6>[ 0.024420] pid_max: default: 32768 minimum: 301
10412 12:40:03.826606 <6>[ 0.029321] LSM: Security Framework initializing
10413 12:40:03.833063 <6>[ 0.034291] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10414 12:40:03.842994 <6>[ 0.042105] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10415 12:40:03.852725 <6>[ 0.051573] cblist_init_generic: Setting adjustable number of callback queues.
10416 12:40:03.856059 <6>[ 0.059016] cblist_init_generic: Setting shift to 3 and lim to 1.
10417 12:40:03.866364 <6>[ 0.065355] cblist_init_generic: Setting adjustable number of callback queues.
10418 12:40:03.873005 <6>[ 0.072782] cblist_init_generic: Setting shift to 3 and lim to 1.
10419 12:40:03.876207 <6>[ 0.079183] rcu: Hierarchical SRCU implementation.
10420 12:40:03.882826 <6>[ 0.084199] rcu: Max phase no-delay instances is 1000.
10421 12:40:03.889684 <6>[ 0.091224] EFI services will not be available.
10422 12:40:03.892931 <6>[ 0.096177] smp: Bringing up secondary CPUs ...
10423 12:40:03.901616 <6>[ 0.101228] Detected VIPT I-cache on CPU1
10424 12:40:03.907796 <6>[ 0.101298] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10425 12:40:03.914492 <6>[ 0.101329] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10426 12:40:03.917822 <6>[ 0.101671] Detected VIPT I-cache on CPU2
10427 12:40:03.924323 <6>[ 0.101722] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10428 12:40:03.934319 <6>[ 0.101740] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10429 12:40:03.937636 <6>[ 0.102003] Detected VIPT I-cache on CPU3
10430 12:40:03.944003 <6>[ 0.102049] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10431 12:40:03.950809 <6>[ 0.102064] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10432 12:40:03.954005 <6>[ 0.102369] CPU features: detected: Spectre-v4
10433 12:40:03.960891 <6>[ 0.102375] CPU features: detected: Spectre-BHB
10434 12:40:03.964117 <6>[ 0.102381] Detected PIPT I-cache on CPU4
10435 12:40:03.970773 <6>[ 0.102438] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10436 12:40:03.977457 <6>[ 0.102455] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10437 12:40:03.983828 <6>[ 0.102748] Detected PIPT I-cache on CPU5
10438 12:40:03.990250 <6>[ 0.102809] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10439 12:40:03.996891 <6>[ 0.102826] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10440 12:40:04.000266 <6>[ 0.103107] Detected PIPT I-cache on CPU6
10441 12:40:04.006886 <6>[ 0.103170] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10442 12:40:04.013594 <6>[ 0.103186] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10443 12:40:04.020048 <6>[ 0.103486] Detected PIPT I-cache on CPU7
10444 12:40:04.026830 <6>[ 0.103550] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10445 12:40:04.033211 <6>[ 0.103566] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10446 12:40:04.036610 <6>[ 0.103613] smp: Brought up 1 node, 8 CPUs
10447 12:40:04.043409 <6>[ 0.244958] SMP: Total of 8 processors activated.
10448 12:40:04.046907 <6>[ 0.249879] CPU features: detected: 32-bit EL0 Support
10449 12:40:04.056263 <6>[ 0.255241] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10450 12:40:04.062953 <6>[ 0.264096] CPU features: detected: Common not Private translations
10451 12:40:04.069664 <6>[ 0.270571] CPU features: detected: CRC32 instructions
10452 12:40:04.072981 <6>[ 0.275956] CPU features: detected: RCpc load-acquire (LDAPR)
10453 12:40:04.079527 <6>[ 0.281953] CPU features: detected: LSE atomic instructions
10454 12:40:04.086079 <6>[ 0.287770] CPU features: detected: Privileged Access Never
10455 12:40:04.092843 <6>[ 0.293585] CPU features: detected: RAS Extension Support
10456 12:40:04.099717 <6>[ 0.299194] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10457 12:40:04.102949 <6>[ 0.306458] CPU: All CPU(s) started at EL2
10458 12:40:04.109516 <6>[ 0.310775] alternatives: applying system-wide alternatives
10459 12:40:04.118931 <6>[ 0.321523] devtmpfs: initialized
10460 12:40:04.131336 <6>[ 0.330320] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10461 12:40:04.141198 <6>[ 0.340281] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10462 12:40:04.147682 <6>[ 0.348463] pinctrl core: initialized pinctrl subsystem
10463 12:40:04.151140 <6>[ 0.355091] DMI not present or invalid.
10464 12:40:04.157843 <6>[ 0.359504] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10465 12:40:04.167567 <6>[ 0.366384] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10466 12:40:04.174268 <6>[ 0.373969] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10467 12:40:04.184227 <6>[ 0.382190] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10468 12:40:04.187343 <6>[ 0.390435] audit: initializing netlink subsys (disabled)
10469 12:40:04.197597 <5>[ 0.396125] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10470 12:40:04.204104 <6>[ 0.396818] thermal_sys: Registered thermal governor 'step_wise'
10471 12:40:04.210750 <6>[ 0.404092] thermal_sys: Registered thermal governor 'power_allocator'
10472 12:40:04.214033 <6>[ 0.410345] cpuidle: using governor menu
10473 12:40:04.220591 <6>[ 0.421305] NET: Registered PF_QIPCRTR protocol family
10474 12:40:04.227182 <6>[ 0.426783] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10475 12:40:04.230437 <6>[ 0.433883] ASID allocator initialised with 32768 entries
10476 12:40:04.237941 <6>[ 0.440426] Serial: AMBA PL011 UART driver
10477 12:40:04.246650 <4>[ 0.449090] Trying to register duplicate clock ID: 134
10478 12:40:04.300776 <6>[ 0.506471] KASLR enabled
10479 12:40:04.315217 <6>[ 0.514301] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10480 12:40:04.321941 <6>[ 0.521315] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10481 12:40:04.328663 <6>[ 0.527803] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10482 12:40:04.335031 <6>[ 0.534808] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10483 12:40:04.341823 <6>[ 0.541294] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10484 12:40:04.348312 <6>[ 0.548298] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10485 12:40:04.354872 <6>[ 0.554789] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10486 12:40:04.361586 <6>[ 0.561794] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10487 12:40:04.364918 <6>[ 0.569311] ACPI: Interpreter disabled.
10488 12:40:04.373646 <6>[ 0.575727] iommu: Default domain type: Translated
10489 12:40:04.380048 <6>[ 0.580840] iommu: DMA domain TLB invalidation policy: strict mode
10490 12:40:04.383188 <5>[ 0.587500] SCSI subsystem initialized
10491 12:40:04.390029 <6>[ 0.591663] usbcore: registered new interface driver usbfs
10492 12:40:04.396321 <6>[ 0.597395] usbcore: registered new interface driver hub
10493 12:40:04.399539 <6>[ 0.602945] usbcore: registered new device driver usb
10494 12:40:04.406819 <6>[ 0.609049] pps_core: LinuxPPS API ver. 1 registered
10495 12:40:04.416601 <6>[ 0.614243] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10496 12:40:04.419814 <6>[ 0.623591] PTP clock support registered
10497 12:40:04.423072 <6>[ 0.627836] EDAC MC: Ver: 3.0.0
10498 12:40:04.430760 <6>[ 0.632990] FPGA manager framework
10499 12:40:04.437415 <6>[ 0.636670] Advanced Linux Sound Architecture Driver Initialized.
10500 12:40:04.440430 <6>[ 0.643450] vgaarb: loaded
10501 12:40:04.447139 <6>[ 0.646565] clocksource: Switched to clocksource arch_sys_counter
10502 12:40:04.450299 <5>[ 0.653002] VFS: Disk quotas dquot_6.6.0
10503 12:40:04.457113 <6>[ 0.657187] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10504 12:40:04.460341 <6>[ 0.664374] pnp: PnP ACPI: disabled
10505 12:40:04.468701 <6>[ 0.671012] NET: Registered PF_INET protocol family
10506 12:40:04.478635 <6>[ 0.676608] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10507 12:40:04.490037 <6>[ 0.688932] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10508 12:40:04.499823 <6>[ 0.697746] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10509 12:40:04.506281 <6>[ 0.705719] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10510 12:40:04.512964 <6>[ 0.714419] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10511 12:40:04.525533 <6>[ 0.724173] TCP: Hash tables configured (established 65536 bind 65536)
10512 12:40:04.531691 <6>[ 0.731042] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10513 12:40:04.538332 <6>[ 0.738244] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10514 12:40:04.544869 <6>[ 0.745947] NET: Registered PF_UNIX/PF_LOCAL protocol family
10515 12:40:04.551702 <6>[ 0.752096] RPC: Registered named UNIX socket transport module.
10516 12:40:04.554904 <6>[ 0.758250] RPC: Registered udp transport module.
10517 12:40:04.561636 <6>[ 0.763183] RPC: Registered tcp transport module.
10518 12:40:04.568235 <6>[ 0.768116] RPC: Registered tcp NFSv4.1 backchannel transport module.
10519 12:40:04.571794 <6>[ 0.774782] PCI: CLS 0 bytes, default 64
10520 12:40:04.574673 <6>[ 0.779102] Unpacking initramfs...
10521 12:40:04.592040 <6>[ 0.791126] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10522 12:40:04.602159 <6>[ 0.799786] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10523 12:40:04.605512 <6>[ 0.808637] kvm [1]: IPA Size Limit: 40 bits
10524 12:40:04.611867 <6>[ 0.813164] kvm [1]: GICv3: no GICV resource entry
10525 12:40:04.615463 <6>[ 0.818185] kvm [1]: disabling GICv2 emulation
10526 12:40:04.622040 <6>[ 0.822874] kvm [1]: GIC system register CPU interface enabled
10527 12:40:04.625280 <6>[ 0.829049] kvm [1]: vgic interrupt IRQ18
10528 12:40:04.631701 <6>[ 0.833405] kvm [1]: VHE mode initialized successfully
10529 12:40:04.638755 <5>[ 0.839946] Initialise system trusted keyrings
10530 12:40:04.645200 <6>[ 0.844748] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10531 12:40:04.652719 <6>[ 0.854770] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10532 12:40:04.658864 <5>[ 0.861195] NFS: Registering the id_resolver key type
10533 12:40:04.662631 <5>[ 0.866496] Key type id_resolver registered
10534 12:40:04.669165 <5>[ 0.870910] Key type id_legacy registered
10535 12:40:04.675710 <6>[ 0.875192] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10536 12:40:04.682335 <6>[ 0.882113] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10537 12:40:04.688883 <6>[ 0.889854] 9p: Installing v9fs 9p2000 file system support
10538 12:40:04.724441 <5>[ 0.927266] Key type asymmetric registered
10539 12:40:04.727695 <5>[ 0.931598] Asymmetric key parser 'x509' registered
10540 12:40:04.737369 <6>[ 0.936742] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10541 12:40:04.741053 <6>[ 0.944357] io scheduler mq-deadline registered
10542 12:40:04.744140 <6>[ 0.949138] io scheduler kyber registered
10543 12:40:04.763167 <6>[ 0.966211] EINJ: ACPI disabled.
10544 12:40:04.795600 <4>[ 0.991883] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10545 12:40:04.805592 <4>[ 1.002538] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10546 12:40:04.820288 <6>[ 1.023247] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10547 12:40:04.828366 <6>[ 1.031241] printk: console [ttyS0] disabled
10548 12:40:04.856351 <6>[ 1.055878] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10549 12:40:04.863111 <6>[ 1.065347] printk: console [ttyS0] enabled
10550 12:40:04.866264 <6>[ 1.065347] printk: console [ttyS0] enabled
10551 12:40:04.873080 <6>[ 1.074241] printk: bootconsole [mtk8250] disabled
10552 12:40:04.876050 <6>[ 1.074241] printk: bootconsole [mtk8250] disabled
10553 12:40:04.882947 <6>[ 1.085520] SuperH (H)SCI(F) driver initialized
10554 12:40:04.886193 <6>[ 1.090809] msm_serial: driver initialized
10555 12:40:04.900193 <6>[ 1.099839] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10556 12:40:04.910375 <6>[ 1.108388] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10557 12:40:04.917048 <6>[ 1.116930] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10558 12:40:04.927192 <6>[ 1.125559] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10559 12:40:04.933555 <6>[ 1.134265] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10560 12:40:04.943474 <6>[ 1.142978] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10561 12:40:04.953535 <6>[ 1.151519] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10562 12:40:04.960022 <6>[ 1.160317] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10563 12:40:04.970163 <6>[ 1.168864] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10564 12:40:04.981510 <6>[ 1.184542] loop: module loaded
10565 12:40:04.988384 <6>[ 1.190616] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10566 12:40:05.010899 <4>[ 1.213952] mtk-pmic-keys: Failed to locate of_node [id: -1]
10567 12:40:05.018101 <6>[ 1.220917] megasas: 07.719.03.00-rc1
10568 12:40:05.027554 <6>[ 1.230550] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10569 12:40:05.039172 <6>[ 1.241952] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10570 12:40:05.055783 <6>[ 1.258472] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10571 12:40:05.111797 <6>[ 1.308110] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10572 12:40:05.316807 <6>[ 1.519542] Freeing initrd memory: 17380K
10573 12:40:05.327528 <6>[ 1.530000] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10574 12:40:05.338374 <6>[ 1.541116] tun: Universal TUN/TAP device driver, 1.6
10575 12:40:05.341848 <6>[ 1.547208] thunder_xcv, ver 1.0
10576 12:40:05.345285 <6>[ 1.550712] thunder_bgx, ver 1.0
10577 12:40:05.348881 <6>[ 1.554201] nicpf, ver 1.0
10578 12:40:05.359004 <6>[ 1.558223] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10579 12:40:05.362546 <6>[ 1.565699] hns3: Copyright (c) 2017 Huawei Corporation.
10580 12:40:05.368885 <6>[ 1.571286] hclge is initializing
10581 12:40:05.372412 <6>[ 1.574867] e1000: Intel(R) PRO/1000 Network Driver
10582 12:40:05.378858 <6>[ 1.579996] e1000: Copyright (c) 1999-2006 Intel Corporation.
10583 12:40:05.382527 <6>[ 1.586008] e1000e: Intel(R) PRO/1000 Network Driver
10584 12:40:05.388756 <6>[ 1.591223] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10585 12:40:05.395447 <6>[ 1.597415] igb: Intel(R) Gigabit Ethernet Network Driver
10586 12:40:05.402207 <6>[ 1.603065] igb: Copyright (c) 2007-2014 Intel Corporation.
10587 12:40:05.408818 <6>[ 1.608918] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10588 12:40:05.415499 <6>[ 1.615436] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10589 12:40:05.419017 <6>[ 1.621902] sky2: driver version 1.30
10590 12:40:05.425603 <6>[ 1.626903] VFIO - User Level meta-driver version: 0.3
10591 12:40:05.432745 <6>[ 1.635152] usbcore: registered new interface driver usb-storage
10592 12:40:05.439278 <6>[ 1.641597] usbcore: registered new device driver onboard-usb-hub
10593 12:40:05.448001 <6>[ 1.650767] mt6397-rtc mt6359-rtc: registered as rtc0
10594 12:40:05.457859 <6>[ 1.656231] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-05T12:40:09 UTC (1707136809)
10595 12:40:05.461136 <6>[ 1.665816] i2c_dev: i2c /dev entries driver
10596 12:40:05.478277 <6>[ 1.677585] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10597 12:40:05.498851 <6>[ 1.701589] cpu cpu0: EM: created perf domain
10598 12:40:05.502205 <6>[ 1.706530] cpu cpu4: EM: created perf domain
10599 12:40:05.509419 <6>[ 1.712192] sdhci: Secure Digital Host Controller Interface driver
10600 12:40:05.516108 <6>[ 1.718623] sdhci: Copyright(c) Pierre Ossman
10601 12:40:05.522482 <6>[ 1.723587] Synopsys Designware Multimedia Card Interface Driver
10602 12:40:05.529467 <6>[ 1.730218] sdhci-pltfm: SDHCI platform and OF driver helper
10603 12:40:05.532642 <6>[ 1.730337] mmc0: CQHCI version 5.10
10604 12:40:05.539407 <6>[ 1.740180] ledtrig-cpu: registered to indicate activity on CPUs
10605 12:40:05.545837 <6>[ 1.747234] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10606 12:40:05.552765 <6>[ 1.754282] usbcore: registered new interface driver usbhid
10607 12:40:05.556057 <6>[ 1.760103] usbhid: USB HID core driver
10608 12:40:05.562230 <6>[ 1.764314] spi_master spi0: will run message pump with realtime priority
10609 12:40:05.606971 <6>[ 1.802448] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10610 12:40:05.626020 <6>[ 1.818425] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10611 12:40:05.629259 <6>[ 1.832041] mmc0: Command Queue Engine enabled
10612 12:40:05.635687 <6>[ 1.836820] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10613 12:40:05.642477 <6>[ 1.843758] cros-ec-spi spi0.0: Chrome EC device registered
10614 12:40:05.645997 <6>[ 1.844076] mmcblk0: mmc0:0001 DA4128 116 GiB
10615 12:40:05.656917 <6>[ 1.859797] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10616 12:40:05.664404 <6>[ 1.867109] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10617 12:40:05.670972 <6>[ 1.873015] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10618 12:40:05.677482 <6>[ 1.878895] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10619 12:40:05.687616 <6>[ 1.884201] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10620 12:40:05.694350 <6>[ 1.896000] NET: Registered PF_PACKET protocol family
10621 12:40:05.697572 <6>[ 1.901401] 9pnet: Installing 9P2000 support
10622 12:40:05.704046 <5>[ 1.905967] Key type dns_resolver registered
10623 12:40:05.707427 <6>[ 1.910968] registered taskstats version 1
10624 12:40:05.714363 <5>[ 1.915357] Loading compiled-in X.509 certificates
10625 12:40:05.743103 <4>[ 1.939058] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10626 12:40:05.753120 <4>[ 1.949865] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10627 12:40:05.759533 <3>[ 1.960420] debugfs: File 'uA_load' in directory '/' already present!
10628 12:40:05.766532 <3>[ 1.967126] debugfs: File 'min_uV' in directory '/' already present!
10629 12:40:05.773255 <3>[ 1.973737] debugfs: File 'max_uV' in directory '/' already present!
10630 12:40:05.779778 <3>[ 1.980346] debugfs: File 'constraint_flags' in directory '/' already present!
10631 12:40:05.790841 <3>[ 1.989987] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10632 12:40:05.800591 <6>[ 2.003376] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10633 12:40:05.807482 <6>[ 2.010110] xhci-mtk 11200000.usb: xHCI Host Controller
10634 12:40:05.813999 <6>[ 2.015613] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10635 12:40:05.824534 <6>[ 2.023451] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10636 12:40:05.831046 <6>[ 2.032869] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10637 12:40:05.837528 <6>[ 2.038947] xhci-mtk 11200000.usb: xHCI Host Controller
10638 12:40:05.844400 <6>[ 2.044423] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10639 12:40:05.850883 <6>[ 2.052068] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10640 12:40:05.857425 <6>[ 2.059746] hub 1-0:1.0: USB hub found
10641 12:40:05.860800 <6>[ 2.063755] hub 1-0:1.0: 1 port detected
10642 12:40:05.867400 <6>[ 2.068019] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10643 12:40:05.874108 <6>[ 2.076554] hub 2-0:1.0: USB hub found
10644 12:40:05.877348 <6>[ 2.080559] hub 2-0:1.0: 1 port detected
10645 12:40:05.886033 <6>[ 2.088680] mtk-msdc 11f70000.mmc: Got CD GPIO
10646 12:40:05.897636 <6>[ 2.096959] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10647 12:40:05.904560 <6>[ 2.104992] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10648 12:40:05.914296 <4>[ 2.112967] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10649 12:40:05.924350 <6>[ 2.122494] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10650 12:40:05.930729 <6>[ 2.130594] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10651 12:40:05.937336 <6>[ 2.138613] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10652 12:40:05.947487 <6>[ 2.146523] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10653 12:40:05.954276 <6>[ 2.154355] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10654 12:40:05.963911 <6>[ 2.162176] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10655 12:40:05.973880 <6>[ 2.172389] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10656 12:40:05.980595 <6>[ 2.180746] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10657 12:40:05.990504 <6>[ 2.189108] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10658 12:40:05.996957 <6>[ 2.197448] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10659 12:40:06.006965 <6>[ 2.205798] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10660 12:40:06.013523 <6>[ 2.214138] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10661 12:40:06.023628 <6>[ 2.222487] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10662 12:40:06.030097 <6>[ 2.230827] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10663 12:40:06.040597 <6>[ 2.239177] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10664 12:40:06.047112 <6>[ 2.247518] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10665 12:40:06.056757 <6>[ 2.255872] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10666 12:40:06.063232 <6>[ 2.264211] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10667 12:40:06.073406 <6>[ 2.272550] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10668 12:40:06.079965 <6>[ 2.280889] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10669 12:40:06.090047 <6>[ 2.289230] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10670 12:40:06.096522 <6>[ 2.297979] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10671 12:40:06.103410 <6>[ 2.305123] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10672 12:40:06.109851 <6>[ 2.311904] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10673 12:40:06.116395 <6>[ 2.318665] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10674 12:40:06.126146 <6>[ 2.325592] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10675 12:40:06.132982 <6>[ 2.332437] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10676 12:40:06.142763 <6>[ 2.341564] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10677 12:40:06.152746 <6>[ 2.350684] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10678 12:40:06.162828 <6>[ 2.359978] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10679 12:40:06.172813 <6>[ 2.369469] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10680 12:40:06.179264 <6>[ 2.378941] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10681 12:40:06.189215 <6>[ 2.388061] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10682 12:40:06.199106 <6>[ 2.397527] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10683 12:40:06.208982 <6>[ 2.406647] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10684 12:40:06.218983 <6>[ 2.415941] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10685 12:40:06.228751 <6>[ 2.426101] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10686 12:40:06.238843 <6>[ 2.437686] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10687 12:40:06.245113 <6>[ 2.447378] Trying to probe devices needed for running init ...
10688 12:40:06.268020 <6>[ 2.466931] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10689 12:40:06.295853 <6>[ 2.498395] hub 2-1:1.0: USB hub found
10690 12:40:06.299072 <6>[ 2.502945] hub 2-1:1.0: 3 ports detected
10691 12:40:06.307713 <6>[ 2.510254] hub 2-1:1.0: USB hub found
10692 12:40:06.310797 <6>[ 2.514646] hub 2-1:1.0: 3 ports detected
10693 12:40:06.419234 <6>[ 2.618778] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10694 12:40:06.574247 <6>[ 2.776779] hub 1-1:1.0: USB hub found
10695 12:40:06.577470 <6>[ 2.781251] hub 1-1:1.0: 4 ports detected
10696 12:40:06.586717 <6>[ 2.789363] hub 1-1:1.0: USB hub found
10697 12:40:06.589952 <6>[ 2.793712] hub 1-1:1.0: 4 ports detected
10698 12:40:06.659555 <6>[ 2.859072] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10699 12:40:06.911332 <6>[ 3.110879] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10700 12:40:07.044153 <6>[ 3.246810] hub 1-1.4:1.0: USB hub found
10701 12:40:07.047328 <6>[ 3.251485] hub 1-1.4:1.0: 2 ports detected
10702 12:40:07.057305 <6>[ 3.259897] hub 1-1.4:1.0: USB hub found
10703 12:40:07.060520 <6>[ 3.264495] hub 1-1.4:1.0: 2 ports detected
10704 12:40:07.359428 <6>[ 3.558862] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10705 12:40:07.551378 <6>[ 3.750865] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10706 12:40:18.528914 <6>[ 14.735847] ALSA device list:
10707 12:40:18.535102 <6>[ 14.739141] No soundcards found.
10708 12:40:18.543530 <6>[ 14.747140] Freeing unused kernel memory: 8448K
10709 12:40:18.546280 <6>[ 14.752128] Run /init as init process
10710 12:40:18.558275 Loading, please wait...
10711 12:40:18.579453 Starting version 247.3-7+deb11u2
10712 12:40:18.785549 <6>[ 14.985629] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10713 12:40:18.791601 <3>[ 14.987721] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10714 12:40:18.798410 <6>[ 15.000450] remoteproc remoteproc0: scp is available
10715 12:40:18.805361 <3>[ 15.001309] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10716 12:40:18.811792 <6>[ 15.007212] remoteproc remoteproc0: powering up scp
10717 12:40:18.818144 <3>[ 15.014683] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10718 12:40:18.828479 <6>[ 15.019749] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10719 12:40:18.834679 <6>[ 15.037278] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10720 12:40:18.841055 <3>[ 15.037542] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10721 12:40:18.851108 <6>[ 15.038271] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10722 12:40:18.857828 <3>[ 15.058869] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10723 12:40:18.864326 <4>[ 15.064240] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10724 12:40:18.874186 <3>[ 15.066965] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10725 12:40:18.880785 <3>[ 15.066970] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10726 12:40:18.890531 <3>[ 15.066974] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 12:40:18.897466 <6>[ 15.070639] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10728 12:40:18.904412 <6>[ 15.071782] usbcore: registered new device driver r8152-cfgselector
10729 12:40:18.914656 <4>[ 15.074348] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10730 12:40:18.917681 <4>[ 15.074348] Fallback method does not support PEC.
10731 12:40:18.924533 <3>[ 15.074905] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10732 12:40:18.934362 <4>[ 15.076378] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10733 12:40:18.941109 <3>[ 15.079073] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 12:40:18.947941 <3>[ 15.079095] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 12:40:18.958445 <3>[ 15.079099] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 12:40:18.965353 <6>[ 15.082499] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10737 12:40:18.971750 <6>[ 15.082835] mc: Linux media interface: v0.10
10738 12:40:18.978279 <3>[ 15.091510] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10739 12:40:18.988220 <6>[ 15.098784] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10740 12:40:18.994661 <3>[ 15.106235] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10741 12:40:19.004821 <3>[ 15.106238] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10742 12:40:19.011544 <3>[ 15.106243] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10743 12:40:19.018174 <3>[ 15.106247] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10744 12:40:19.028111 <3>[ 15.129505] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10745 12:40:19.038128 <3>[ 15.134725] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10746 12:40:19.041305 <6>[ 15.135261] videodev: Linux video capture interface: v2.00
10747 12:40:19.051198 <3>[ 15.163545] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10748 12:40:19.061062 <6>[ 15.168224] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10749 12:40:19.067718 <6>[ 15.168232] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10750 12:40:19.074528 <6>[ 15.180637] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10751 12:40:19.084280 <6>[ 15.181415] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10752 12:40:19.090648 <6>[ 15.187469] remoteproc remoteproc0: remote processor scp is now up
10753 12:40:19.097461 <6>[ 15.211079] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10754 12:40:19.107720 <6>[ 15.214057] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10755 12:40:19.117637 <6>[ 15.229605] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10756 12:40:19.124286 <6>[ 15.231991] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10757 12:40:19.131069 <6>[ 15.232000] pci_bus 0000:00: root bus resource [bus 00-ff]
10758 12:40:19.137225 <6>[ 15.232010] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10759 12:40:19.147593 <6>[ 15.232016] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10760 12:40:19.153701 <6>[ 15.232061] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10761 12:40:19.160175 <6>[ 15.232086] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10762 12:40:19.163854 <6>[ 15.232181] pci 0000:00:00.0: supports D1 D2
10763 12:40:19.173387 <6>[ 15.232186] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10764 12:40:19.180294 <6>[ 15.234256] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10765 12:40:19.187168 <6>[ 15.234403] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10766 12:40:19.193744 <6>[ 15.234438] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10767 12:40:19.200241 <6>[ 15.234461] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10768 12:40:19.210009 <6>[ 15.234485] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10769 12:40:19.213458 <6>[ 15.234626] pci 0000:01:00.0: supports D1 D2
10770 12:40:19.219905 <6>[ 15.234631] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10771 12:40:19.226475 <6>[ 15.246676] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10772 12:40:19.236337 <4>[ 15.249013] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10773 12:40:19.243012 <4>[ 15.249025] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10774 12:40:19.252709 <6>[ 15.293617] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10775 12:40:19.256007 <6>[ 15.294698] r8152 2-1.3:1.0 eth0: v1.12.13
10776 12:40:19.262891 <6>[ 15.294782] usbcore: registered new interface driver r8152
10777 12:40:19.272725 <6>[ 15.299529] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10778 12:40:19.276007 <6>[ 15.334643] Bluetooth: Core ver 2.22
10779 12:40:19.282592 <6>[ 15.338836] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10780 12:40:19.289216 <6>[ 15.339444] usbcore: registered new interface driver cdc_ether
10781 12:40:19.295910 <6>[ 15.346107] NET: Registered PF_BLUETOOTH protocol family
10782 12:40:19.302372 <6>[ 15.355848] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10783 12:40:19.308983 <6>[ 15.355969] usbcore: registered new interface driver r8153_ecm
10784 12:40:19.315474 <6>[ 15.362094] Bluetooth: HCI device and connection manager initialized
10785 12:40:19.322409 <6>[ 15.369574] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10786 12:40:19.329158 <6>[ 15.374097] Bluetooth: HCI socket layer initialized
10787 12:40:19.335528 <6>[ 15.376237] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10788 12:40:19.342056 <6>[ 15.380954] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10789 12:40:19.348637 <6>[ 15.389198] Bluetooth: L2CAP socket layer initialized
10790 12:40:19.352032 <6>[ 15.395464] pci 0000:00:00.0: PCI bridge to [bus 01]
10791 12:40:19.361931 <6>[ 15.396364] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10792 12:40:19.371569 <6>[ 15.397433] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10793 12:40:19.378140 <6>[ 15.397538] usbcore: registered new interface driver uvcvideo
10794 12:40:19.384767 <6>[ 15.402932] Bluetooth: SCO socket layer initialized
10795 12:40:19.391827 <6>[ 15.410397] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10796 12:40:19.398025 <6>[ 15.423158] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10797 12:40:19.404759 <6>[ 15.472768] usbcore: registered new interface driver btusb
10798 12:40:19.414424 <4>[ 15.473664] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10799 12:40:19.421558 <3>[ 15.473678] Bluetooth: hci0: Failed to load firmware file (-2)
10800 12:40:19.427713 <3>[ 15.473683] Bluetooth: hci0: Failed to set up firmware (-2)
10801 12:40:19.437619 <4>[ 15.473688] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10802 12:40:19.444557 <6>[ 15.480732] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10803 12:40:19.451040 <6>[ 15.652667] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10804 12:40:19.457578 <6>[ 15.659411] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10805 12:40:19.471947 <5>[ 15.672758] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10806 12:40:19.491494 <5>[ 15.691923] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10807 12:40:19.497927 <5>[ 15.699400] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10808 12:40:19.507928 <4>[ 15.707845] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10809 12:40:19.514195 <6>[ 15.716727] cfg80211: failed to load regulatory.db
10810 12:40:19.560212 <6>[ 15.760556] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10811 12:40:19.566615 <6>[ 15.768069] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10812 12:40:19.591182 <6>[ 15.794763] mt7921e 0000:01:00.0: ASIC revision: 79610010
10813 12:40:19.694057 <6>[ 15.894229] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10814 12:40:19.696632 <6>[ 15.894229]
10815 12:40:19.716406 Begin: Loading essential drivers ... done.
10816 12:40:19.719858 Begin: Running /scripts/init-premount ... done.
10817 12:40:19.726420 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10818 12:40:19.736600 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10819 12:40:19.739116 Device /sys/class/net/enx0024323078ff found
10820 12:40:19.739545 done.
10821 12:40:19.790114 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10822 12:40:19.961272 <6>[ 16.162192] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10823 12:40:20.809448 <6>[ 17.013562] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10824 12:40:20.946958 <6>[ 17.150954] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10825 12:40:20.950269 IP-Config: no response after 2 secs - giving up
10826 12:40:20.990476 IP-Config: wlp1s0 hardware address d8:f3:bc:78:28:07 mtu 1500 DHCP
10827 12:40:21.705786 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10828 12:40:21.712783 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10829 12:40:21.719008 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10830 12:40:21.725737 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10831 12:40:21.732622 host : mt8192-asurada-spherion-r0-cbg-8
10832 12:40:21.739003 domain : lava-rack
10833 12:40:21.742152 rootserver: 192.168.201.1 rootpath:
10834 12:40:21.742574 filename :
10835 12:40:21.899369 done.
10836 12:40:21.908629 Begin: Running /scripts/nfs-bottom ... done.
10837 12:40:21.927278 Begin: Running /scripts/init-bottom ... done.
10838 12:40:23.190390 <6>[ 19.394917] NET: Registered PF_INET6 protocol family
10839 12:40:23.198172 <6>[ 19.402679] Segment Routing with IPv6
10840 12:40:23.201377 <6>[ 19.406663] In-situ OAM (IOAM) with IPv6
10841 12:40:23.345807 <30>[ 19.530353] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10842 12:40:23.352527 <30>[ 19.554848] systemd[1]: Detected architecture arm64.
10843 12:40:23.373776
10844 12:40:23.377012 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10845 12:40:23.377591
10846 12:40:23.393377 <30>[ 19.597925] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10847 12:40:24.445074 <30>[ 20.646196] systemd[1]: Queued start job for default target Graphical Interface.
10848 12:40:24.473055 <30>[ 20.677165] systemd[1]: Created slice system-getty.slice.
10849 12:40:24.479190 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10850 12:40:24.495535 <30>[ 20.700246] systemd[1]: Created slice system-modprobe.slice.
10851 12:40:24.502412 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10852 12:40:24.519483 <30>[ 20.724102] systemd[1]: Created slice system-serial\x2dgetty.slice.
10853 12:40:24.529562 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10854 12:40:24.543462 <30>[ 20.747906] systemd[1]: Created slice User and Session Slice.
10855 12:40:24.550210 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10856 12:40:24.570404 <30>[ 20.771712] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10857 12:40:24.580658 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10858 12:40:24.598218 <30>[ 20.799510] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10859 12:40:24.604913 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10860 12:40:24.629785 <30>[ 20.827423] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10861 12:40:24.636331 <30>[ 20.839682] systemd[1]: Reached target Local Encrypted Volumes.
10862 12:40:24.642676 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10863 12:40:24.658595 <30>[ 20.863346] systemd[1]: Reached target Paths.
10864 12:40:24.665024 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10865 12:40:24.678834 <30>[ 20.883280] systemd[1]: Reached target Remote File Systems.
10866 12:40:24.685540 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10867 12:40:24.702628 <30>[ 20.907210] systemd[1]: Reached target Slices.
10868 12:40:24.709125 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10869 12:40:24.722592 <30>[ 20.926881] systemd[1]: Reached target Swap.
10870 12:40:24.725617 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10871 12:40:24.746021 <30>[ 20.947360] systemd[1]: Listening on initctl Compatibility Named Pipe.
10872 12:40:24.752289 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10873 12:40:24.759710 <30>[ 20.963776] systemd[1]: Listening on Journal Audit Socket.
10874 12:40:24.765856 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10875 12:40:24.783888 <30>[ 20.988671] systemd[1]: Listening on Journal Socket (/dev/log).
10876 12:40:24.790422 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10877 12:40:24.806654 <30>[ 21.011416] systemd[1]: Listening on Journal Socket.
10878 12:40:24.813513 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10879 12:40:24.831440 <30>[ 21.032737] systemd[1]: Listening on Network Service Netlink Socket.
10880 12:40:24.837859 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10881 12:40:24.854416 <30>[ 21.058815] systemd[1]: Listening on udev Control Socket.
10882 12:40:24.860860 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10883 12:40:24.874931 <30>[ 21.079299] systemd[1]: Listening on udev Kernel Socket.
10884 12:40:24.881019 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10885 12:40:24.938229 <30>[ 21.143045] systemd[1]: Mounting Huge Pages File System...
10886 12:40:24.945181 Mounting [0;1;39mHuge Pages File System[0m...
10887 12:40:24.962473 <30>[ 21.166983] systemd[1]: Mounting POSIX Message Queue File System...
10888 12:40:24.969147 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10889 12:40:24.990488 <30>[ 21.195429] systemd[1]: Mounting Kernel Debug File System...
10890 12:40:24.997156 Mounting [0;1;39mKernel Debug File System[0m...
10891 12:40:25.013861 <30>[ 21.215123] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10892 12:40:25.034106 <30>[ 21.235271] systemd[1]: Starting Create list of static device nodes for the current kernel...
10893 12:40:25.040502 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10894 12:40:25.063679 <30>[ 21.268099] systemd[1]: Starting Load Kernel Module configfs...
10895 12:40:25.070036 Starting [0;1;39mLoad Kernel Module configfs[0m...
10896 12:40:25.091005 <30>[ 21.295655] systemd[1]: Starting Load Kernel Module drm...
10897 12:40:25.097583 Starting [0;1;39mLoad Kernel Module drm[0m...
10898 12:40:25.113545 <30>[ 21.318321] systemd[1]: Starting Load Kernel Module fuse...
10899 12:40:25.120205 Starting [0;1;39mLoad Kernel Module fuse[0m...
10900 12:40:25.146738 <30>[ 21.348175] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10901 12:40:25.163936 <30>[ 21.368300] systemd[1]: Starting Journal Service...
10902 12:40:25.166942 <6>[ 21.368642] fuse: init (API version 7.37)
10903 12:40:25.173861 Starting [0;1;39mJournal Service[0m...
10904 12:40:25.219025 <30>[ 21.423675] systemd[1]: Starting Load Kernel Modules...
10905 12:40:25.225618 Starting [0;1;39mLoad Kernel Modules[0m...
10906 12:40:25.246132 <30>[ 21.447611] systemd[1]: Starting Remount Root and Kernel File Systems...
10907 12:40:25.252487 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10908 12:40:25.269697 <30>[ 21.474179] systemd[1]: Starting Coldplug All udev Devices...
10909 12:40:25.275956 Starting [0;1;39mColdplug All udev Devices[0m...
10910 12:40:25.294883 <30>[ 21.499759] systemd[1]: Mounted Huge Pages File System.
10911 12:40:25.301838 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10912 12:40:25.319314 <30>[ 21.523682] systemd[1]: Mounted POSIX Message Queue File System.
10913 12:40:25.325976 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10914 12:40:25.342614 <30>[ 21.547329] systemd[1]: Mounted Kernel Debug File System.
10915 12:40:25.349314 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10916 12:40:25.372302 <30>[ 21.572905] systemd[1]: Finished Create list of static device nodes for the current kernel.
10917 12:40:25.381971 <3>[ 21.581497] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 12:40:25.388382 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10919 12:40:25.403115 <30>[ 21.607450] systemd[1]: modprobe@configfs.service: Succeeded.
10920 12:40:25.412925 <3>[ 21.610164] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 12:40:25.419745 <30>[ 21.614325] systemd[1]: Finished Load Kernel Module configfs.
10922 12:40:25.426373 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10923 12:40:25.438854 <30>[ 21.643528] systemd[1]: modprobe@drm.service: Succeeded.
10924 12:40:25.445580 <30>[ 21.649897] systemd[1]: Finished Load Kernel Module drm.
10925 12:40:25.452247 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10926 12:40:25.471988 <3>[ 21.673177] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 12:40:25.478472 <30>[ 21.683234] systemd[1]: modprobe@fuse.service: Succeeded.
10928 12:40:25.485339 <30>[ 21.689969] systemd[1]: Finished Load Kernel Module fuse.
10929 12:40:25.491655 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10930 12:40:25.508252 <30>[ 21.712418] systemd[1]: Finished Load Kernel Modules.
10931 12:40:25.517783 <3>[ 21.713947] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 12:40:25.521096 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10933 12:40:25.539821 <30>[ 21.744151] systemd[1]: Finished Remount Root and Kernel File Systems.
10934 12:40:25.549407 <3>[ 21.746742] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 12:40:25.556658 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10936 12:40:25.580721 <3>[ 21.782266] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10937 12:40:25.612268 <3>[ 21.813642] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 12:40:25.626290 <30>[ 21.831226] systemd[1]: Mounting FUSE Control File System...
10939 12:40:25.633326 Mounting [0;1;39mFUSE Control File System[0m...
10940 12:40:25.643443 <3>[ 21.843338] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 12:40:25.650972 <30>[ 21.855566] systemd[1]: Mounting Kernel Configuration File System...
10942 12:40:25.657825 Mounting [0;1;39mKernel Configuration File System[0m...
10943 12:40:25.671973 <3>[ 21.873503] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 12:40:25.688348 <30>[ 21.889830] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10945 12:40:25.699049 <30>[ 21.899088] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10946 12:40:25.708833 <3>[ 21.906965] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 12:40:25.712073 <30>[ 21.911660] systemd[1]: Starting Load/Save Random Seed...
10948 12:40:25.718963 Starting [0;1;39mLoad/Save Random Seed[0m...
10949 12:40:25.758809 <30>[ 21.963476] systemd[1]: Starting Apply Kernel Variables...
10950 12:40:25.765687 Starting [0;1;39mApply Kernel Variables[0m...
10951 12:40:25.785686 <30>[ 21.990417] systemd[1]: Starting Create System Users...
10952 12:40:25.792939 Starting [0;1;39mCreate System Users[0m...
10953 12:40:25.809683 <4>[ 22.002883] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10954 12:40:25.816313 <3>[ 22.018601] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10955 12:40:25.822789 <30>[ 22.020123] systemd[1]: Started Journal Service.
10956 12:40:25.825878 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10957 12:40:25.850041 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10958 12:40:25.866050 See 'systemctl status systemd-udev-trigger.service' for details.
10959 12:40:25.883164 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10960 12:40:25.898228 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10961 12:40:25.915041 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10962 12:40:25.934956 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10963 12:40:25.956081 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10964 12:40:25.994611 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10965 12:40:26.012432 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10966 12:40:26.060961 <46>[ 22.262815] systemd-journald[299]: Received client request to flush runtime journal.
10967 12:40:27.152760 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10968 12:40:27.166341 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10969 12:40:27.181993 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10970 12:40:27.250330 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10971 12:40:27.456847 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10972 12:40:27.502801 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10973 12:40:27.640939 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10974 12:40:27.687401 Starting [0;1;39mNetwork Service[0m...
10975 12:40:27.985011 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10976 12:40:28.005965 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10977 12:40:28.054441 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10978 12:40:28.300365 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10979 12:40:28.360887 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10980 12:40:28.398891 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10981 12:40:28.448456 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10982 12:40:28.468523 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10983 12:40:28.487928 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10984 12:40:28.506605 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10985 12:40:28.594547 Starting [0;1;39mNetwork Name Resolution[0m...
10986 12:40:28.624408 Starting [0;1;39mNetwork Time Synchronization[0m...
10987 12:40:28.642121 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10988 12:40:28.702309 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10989 12:40:28.848128 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10990 12:40:28.870649 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10991 12:40:28.889111 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10992 12:40:28.901358 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10993 12:40:28.917164 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10994 12:40:28.954407 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10995 12:40:28.979157 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10996 12:40:29.004439 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10997 12:40:29.637412 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10998 12:40:29.649292 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10999 12:40:29.727576 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11000 12:40:29.741375 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11001 12:40:29.757341 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11002 12:40:29.802940 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11003 12:40:30.221830 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11004 12:40:30.322315 Starting [0;1;39mUser Login Management[0m...
11005 12:40:30.639838 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11006 12:40:30.658156 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11007 12:40:30.676947 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11008 12:40:30.730417 Starting [0;1;39mPermit User Sessions[0m...
11009 12:40:30.757957 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11010 12:40:30.777191 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11011 12:40:30.799742 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11012 12:40:30.866730 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11013 12:40:30.885284 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11014 12:40:30.903911 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11015 12:40:30.922160 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11016 12:40:30.938398 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11017 12:40:30.999641 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11018 12:40:31.079197 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11019 12:40:31.158193
11020 12:40:31.158716
11021 12:40:31.161304 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11022 12:40:31.161784
11023 12:40:31.164534 debian-bullseye-arm64 login: root (automatic login)
11024 12:40:31.164958
11025 12:40:31.165289
11026 12:40:31.603718 Linux debian-bullseye-arm64 6.1.75-cip14 #1 SMP PREEMPT Mon Feb 5 12:20:06 UTC 2024 aarch64
11027 12:40:31.604229
11028 12:40:31.610402 The programs included with the Debian GNU/Linux system are free software;
11029 12:40:31.616845 the exact distribution terms for each program are described in the
11030 12:40:31.620317 individual files in /usr/share/doc/*/copyright.
11031 12:40:31.620819
11032 12:40:31.626807 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11033 12:40:31.630089 permitted by applicable law.
11034 12:40:32.742677 Matched prompt #10: / #
11036 12:40:32.743877 Setting prompt string to ['/ #']
11037 12:40:32.744338 end: 2.2.5.1 login-action (duration 00:00:30) [common]
11039 12:40:32.745313 end: 2.2.5 auto-login-action (duration 00:00:30) [common]
11040 12:40:32.745821 start: 2.2.6 expect-shell-connection (timeout 00:03:09) [common]
11041 12:40:32.746210 Setting prompt string to ['/ #']
11042 12:40:32.746520 Forcing a shell prompt, looking for ['/ #']
11044 12:40:32.797309 / #
11045 12:40:32.798048 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11046 12:40:32.798505 Waiting using forced prompt support (timeout 00:02:30)
11047 12:40:32.803146
11048 12:40:32.803983 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11049 12:40:32.804557 start: 2.2.7 export-device-env (timeout 00:03:09) [common]
11051 12:40:32.905755 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12703533/extract-nfsrootfs-ijr2jn3z'
11052 12:40:32.911224 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12703533/extract-nfsrootfs-ijr2jn3z'
11054 12:40:33.012721 / # export NFS_SERVER_IP='192.168.201.1'
11055 12:40:33.018959 export NFS_SERVER_IP='192.168.201.1'
11056 12:40:33.019926 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11057 12:40:33.020468 end: 2.2 depthcharge-retry (duration 00:01:51) [common]
11058 12:40:33.020988 end: 2 depthcharge-action (duration 00:01:51) [common]
11059 12:40:33.021556 start: 3 lava-test-retry (timeout 00:07:22) [common]
11060 12:40:33.022065 start: 3.1 lava-test-shell (timeout 00:07:22) [common]
11061 12:40:33.022487 Using namespace: common
11063 12:40:33.123999 / # #
11064 12:40:33.124691 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11065 12:40:33.130386 #
11066 12:40:33.131279 Using /lava-12703533
11068 12:40:33.232570 / # export SHELL=/bin/bash
11069 12:40:33.238895 export SHELL=/bin/bash
11071 12:40:33.340653 / # . /lava-12703533/environment
11072 12:40:33.346962 . /lava-12703533/environment
11074 12:40:33.455828 / # /lava-12703533/bin/lava-test-runner /lava-12703533/0
11075 12:40:33.456466 Test shell timeout: 10s (minimum of the action and connection timeout)
11076 12:40:33.462048 /lava-12703533/bin/lava-test-runner /lava-12703533/0
11077 12:40:33.839332 + export TESTRUN_ID=0_timesync-off
11078 12:40:33.842626 + TESTRUN_ID=0_timesync-off
11079 12:40:33.845632 + cd /lava-12703533/0/tests/0_timesync-off
11080 12:40:33.848999 ++ cat uuid
11081 12:40:33.858057 + UUID=12703533_1.6.2.3.1
11082 12:40:33.858484 + set +x
11083 12:40:33.864726 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12703533_1.6.2.3.1>
11084 12:40:33.865437 Received signal: <STARTRUN> 0_timesync-off 12703533_1.6.2.3.1
11085 12:40:33.865848 Starting test lava.0_timesync-off (12703533_1.6.2.3.1)
11086 12:40:33.866268 Skipping test definition patterns.
11087 12:40:33.868310 + systemctl stop systemd-timesyncd
11088 12:40:33.943746 + set +x
11089 12:40:33.947035 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12703533_1.6.2.3.1>
11090 12:40:33.947801 Received signal: <ENDRUN> 0_timesync-off 12703533_1.6.2.3.1
11091 12:40:33.948517 Ending use of test pattern.
11092 12:40:33.949152 Ending test lava.0_timesync-off (12703533_1.6.2.3.1), duration 0.08
11094 12:40:34.050121 + export TESTRUN_ID=1_kselftest-rtc
11095 12:40:34.053368 + TESTRUN_ID=1_kselftest-rtc
11096 12:40:34.056567 + cd /lava-12703533/0/tests/1_kselftest-rtc
11097 12:40:34.060073 ++ cat uuid
11098 12:40:34.068131 + UUID=12703533_1.6.2.3.5
11099 12:40:34.068580 + set +x
11100 12:40:34.074614 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 12703533_1.6.2.3.5>
11101 12:40:34.075319 Received signal: <STARTRUN> 1_kselftest-rtc 12703533_1.6.2.3.5
11102 12:40:34.075704 Starting test lava.1_kselftest-rtc (12703533_1.6.2.3.5)
11103 12:40:34.076220 Skipping test definition patterns.
11104 12:40:34.078079 + cd ./automated/linux/kselftest/
11105 12:40:34.104606 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11106 12:40:34.165270 INFO: install_deps skipped
11107 12:40:34.310604 --2024-02-05 12:40:34-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11108 12:40:34.336658 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11109 12:40:34.470231 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11110 12:40:34.603138 HTTP request sent, awaiting response... 200 OK
11111 12:40:34.606078 Length: 2966020 (2.8M) [application/octet-stream]
11112 12:40:34.609420 Saving to: 'kselftest.tar.xz'
11113 12:40:34.609906
11114 12:40:34.610249
11115 12:40:34.869098 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11116 12:40:35.135101 kselftest.tar.xz 1%[ ] 47.81K 181KB/s
11117 12:40:35.401624 kselftest.tar.xz 7%[> ] 217.50K 410KB/s
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11121 12:40:35.739361
11122 12:40:35.997542 2024-02-05 12:40:35 (2.51 MB/s) - 'kselftest.tar.xz' saved [2966020/2966020]
11123 12:40:35.997691
11124 12:40:42.555356 skiplist:
11125 12:40:42.558754 ========================================
11126 12:40:42.561787 ========================================
11127 12:40:42.616274 rtc:rtctest
11128 12:40:42.637870 ============== Tests to run ===============
11129 12:40:42.637969 rtc:rtctest
11130 12:40:42.644283 ===========End Tests to run ===============
11131 12:40:42.647929 shardfile-rtc pass
11132 12:40:42.761684 <12>[ 38.969006] kselftest: Running tests in rtc
11133 12:40:42.773439 TAP version 13
11134 12:40:42.788225 1..1
11135 12:40:42.825261 # selftests: rtc: rtctest
11136 12:40:43.270794 # TAP version 13
11137 12:40:43.270938 # 1..8
11138 12:40:43.273980 # # Starting 8 tests from 2 test cases.
11139 12:40:43.277339 # # RUN rtc.date_read ...
11140 12:40:43.283991 # # rtctest.c:49:date_read:Current RTC date/time is 05/02/2024 12:40:42.
11141 12:40:43.287383 # # OK rtc.date_read
11142 12:40:43.290619 # ok 1 rtc.date_read
11143 12:40:43.293728 # # RUN rtc.date_read_loop ...
11144 12:40:43.303825 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11145 12:40:49.947980 <6>[ 46.159043] vpu: disabling
11146 12:40:49.951194 <6>[ 46.162148] vproc2: disabling
11147 12:40:49.954882 <6>[ 46.166059] vproc1: disabling
11148 12:40:49.958705 <6>[ 46.170089] vaud18: disabling
11149 12:40:49.965664 <6>[ 46.173825] vsram_others: disabling
11150 12:40:49.969148 <6>[ 46.178023] va09: disabling
11151 12:40:49.972320 <6>[ 46.181418] vsram_md: disabling
11152 12:40:49.975470 <6>[ 46.185215] Vgpu: disabling
11153 12:41:13.021264 # # rtctest.c:115:date_read_loop:Performed 2621 RTC time reads.
11154 12:41:13.024491 # # OK rtc.date_read_loop
11155 12:41:13.027918 # ok 2 rtc.date_read_loop
11156 12:41:13.031314 # # RUN rtc.uie_read ...
11157 12:41:15.999087 # # OK rtc.uie_read
11158 12:41:16.002222 # ok 3 rtc.uie_read
11159 12:41:16.005655 # # RUN rtc.uie_select ...
11160 12:41:18.998553 # # OK rtc.uie_select
11161 12:41:19.002090 # ok 4 rtc.uie_select
11162 12:41:19.005077 # # RUN rtc.alarm_alm_set ...
11163 12:41:19.011806 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 12:41:22.
11164 12:41:19.015173 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11165 12:41:19.021699 # # alarm_alm_set: Test terminated by assertion
11166 12:41:19.025222 # # FAIL rtc.alarm_alm_set
11167 12:41:19.028429 # not ok 5 rtc.alarm_alm_set
11168 12:41:19.031546 # # RUN rtc.alarm_wkalm_set ...
11169 12:41:19.038132 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 05/02/2024 12:41:22.
11170 12:41:22.001174 # # OK rtc.alarm_wkalm_set
11171 12:41:22.001314 # ok 6 rtc.alarm_wkalm_set
11172 12:41:22.008033 # # RUN rtc.alarm_alm_set_minute ...
11173 12:41:22.011162 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 12:42:00.
11174 12:41:22.017783 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11175 12:41:22.024372 # # alarm_alm_set_minute: Test terminated by assertion
11176 12:41:22.027562 # # FAIL rtc.alarm_alm_set_minute
11177 12:41:22.030805 # not ok 7 rtc.alarm_alm_set_minute
11178 12:41:22.034231 # # RUN rtc.alarm_wkalm_set_minute ...
11179 12:41:22.040622 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 05/02/2024 12:42:00.
11180 12:41:59.997072 # # OK rtc.alarm_wkalm_set_minute
11181 12:42:00.000273 # ok 8 rtc.alarm_wkalm_set_minute
11182 12:42:00.003477 # # FAILED: 6 / 8 tests passed.
11183 12:42:00.006919 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11184 12:42:00.010080 not ok 1 selftests: rtc: rtctest # exit=1
11185 12:42:00.639384 rtc_rtctest_rtc_date_read pass
11186 12:42:00.642677 rtc_rtctest_rtc_date_read_loop pass
11187 12:42:00.645912 rtc_rtctest_rtc_uie_read pass
11188 12:42:00.649020 rtc_rtctest_rtc_uie_select pass
11189 12:42:00.652663 rtc_rtctest_rtc_alarm_alm_set fail
11190 12:42:00.655845 rtc_rtctest_rtc_alarm_wkalm_set pass
11191 12:42:00.659028 rtc_rtctest_rtc_alarm_alm_set_minute fail
11192 12:42:00.662390 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11193 12:42:00.665614 rtc_rtctest fail
11194 12:42:00.668895 + ../../utils/send-to-lava.sh ./output/result.txt
11195 12:42:00.756690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
11196 12:42:00.757030 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
11198 12:42:00.813357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11199 12:42:00.813719 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11201 12:42:00.878518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11202 12:42:00.878849 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11204 12:42:00.936638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11205 12:42:00.936960 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11207 12:42:00.997986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11208 12:42:00.998310 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11210 12:42:01.063081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11211 12:42:01.063404 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11213 12:42:01.123262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11214 12:42:01.123579 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11216 12:42:01.191570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11217 12:42:01.191892 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11219 12:42:01.257862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11220 12:42:01.258207 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11222 12:42:01.312304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11223 12:42:01.312447 + set +x
11224 12:42:01.312692 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11226 12:42:01.319064 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 12703533_1.6.2.3.5>
11227 12:42:01.319320 Received signal: <ENDRUN> 1_kselftest-rtc 12703533_1.6.2.3.5
11228 12:42:01.319397 Ending use of test pattern.
11229 12:42:01.319460 Ending test lava.1_kselftest-rtc (12703533_1.6.2.3.5), duration 87.24
11231 12:42:01.319684 ok: lava_test_shell seems to have completed
11232 12:42:01.319819 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
shardfile-rtc: pass
11233 12:42:01.319909 end: 3.1 lava-test-shell (duration 00:01:28) [common]
11234 12:42:01.319997 end: 3 lava-test-retry (duration 00:01:28) [common]
11235 12:42:01.320088 start: 4 finalize (timeout 00:05:54) [common]
11236 12:42:01.320185 start: 4.1 power-off (timeout 00:00:30) [common]
11237 12:42:01.320338 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11238 12:42:01.396212 >> Command sent successfully.
11239 12:42:01.398621 Returned 0 in 0 seconds
11240 12:42:01.499041 end: 4.1 power-off (duration 00:00:00) [common]
11242 12:42:01.499387 start: 4.2 read-feedback (timeout 00:05:53) [common]
11244 12:42:01.499965 Listened to connection for namespace 'common' for up to 1s
11245 12:42:02.500604 Finalising connection for namespace 'common'
11246 12:42:02.500790 Disconnecting from shell: Finalise
11247 12:42:02.500870 / #
11248 12:42:02.601176 end: 4.2 read-feedback (duration 00:00:01) [common]
11249 12:42:02.601362 end: 4 finalize (duration 00:00:01) [common]
11250 12:42:02.601491 Cleaning after the job
11251 12:42:02.601624 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703533/tftp-deploy-0ti03h9j/ramdisk
11252 12:42:02.604405 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703533/tftp-deploy-0ti03h9j/kernel
11253 12:42:02.617394 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703533/tftp-deploy-0ti03h9j/dtb
11254 12:42:02.617641 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703533/tftp-deploy-0ti03h9j/nfsrootfs
11255 12:42:02.707064 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703533/tftp-deploy-0ti03h9j/modules
11256 12:42:02.714350 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12703533
11257 12:42:03.358066 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12703533
11258 12:42:03.358246 Job finished correctly