Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 17
- Kernel Errors: 36
1 12:36:44.542065 lava-dispatcher, installed at version: 2024.01
2 12:36:44.542294 start: 0 validate
3 12:36:44.542428 Start time: 2024-02-05 12:36:44.542421+00:00 (UTC)
4 12:36:44.542566 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:36:44.542698 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 12:36:44.810995 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:36:44.811718 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:37:57.881721 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:37:57.881935 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:37:58.147159 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:37:58.147879 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:37:58.670838 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:37:58.671014 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:37:58.935634 validate duration: 74.39
16 12:37:58.935894 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:37:58.935990 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:37:58.936078 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:37:58.936205 Not decompressing ramdisk as can be used compressed.
20 12:37:58.936290 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/initrd.cpio.gz
21 12:37:58.936353 saving as /var/lib/lava/dispatcher/tmp/12703510/tftp-deploy-mt650d1d/ramdisk/initrd.cpio.gz
22 12:37:58.936417 total size: 4665398 (4 MB)
23 12:37:59.200837 progress 0 % (0 MB)
24 12:37:59.202521 progress 5 % (0 MB)
25 12:37:59.203858 progress 10 % (0 MB)
26 12:37:59.205173 progress 15 % (0 MB)
27 12:37:59.206425 progress 20 % (0 MB)
28 12:37:59.207670 progress 25 % (1 MB)
29 12:37:59.208954 progress 30 % (1 MB)
30 12:37:59.210195 progress 35 % (1 MB)
31 12:37:59.211424 progress 40 % (1 MB)
32 12:37:59.212867 progress 45 % (2 MB)
33 12:37:59.214106 progress 50 % (2 MB)
34 12:37:59.215351 progress 55 % (2 MB)
35 12:37:59.216716 progress 60 % (2 MB)
36 12:37:59.217990 progress 65 % (2 MB)
37 12:37:59.219256 progress 70 % (3 MB)
38 12:37:59.220489 progress 75 % (3 MB)
39 12:37:59.221730 progress 80 % (3 MB)
40 12:37:59.223149 progress 85 % (3 MB)
41 12:37:59.224379 progress 90 % (4 MB)
42 12:37:59.225618 progress 95 % (4 MB)
43 12:37:59.226876 progress 100 % (4 MB)
44 12:37:59.227029 4 MB downloaded in 0.29 s (15.31 MB/s)
45 12:37:59.227177 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:37:59.227421 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:37:59.227507 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:37:59.227590 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:37:59.227730 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:37:59.227799 saving as /var/lib/lava/dispatcher/tmp/12703510/tftp-deploy-mt650d1d/kernel/Image
52 12:37:59.227858 total size: 51534336 (49 MB)
53 12:37:59.227917 No compression specified
54 12:37:59.229007 progress 0 % (0 MB)
55 12:37:59.243157 progress 5 % (2 MB)
56 12:37:59.257815 progress 10 % (4 MB)
57 12:37:59.272050 progress 15 % (7 MB)
58 12:37:59.286681 progress 20 % (9 MB)
59 12:37:59.301117 progress 25 % (12 MB)
60 12:37:59.315399 progress 30 % (14 MB)
61 12:37:59.329846 progress 35 % (17 MB)
62 12:37:59.344148 progress 40 % (19 MB)
63 12:37:59.358731 progress 45 % (22 MB)
64 12:37:59.373205 progress 50 % (24 MB)
65 12:37:59.387346 progress 55 % (27 MB)
66 12:37:59.401940 progress 60 % (29 MB)
67 12:37:59.416534 progress 65 % (31 MB)
68 12:37:59.430783 progress 70 % (34 MB)
69 12:37:59.445133 progress 75 % (36 MB)
70 12:37:59.459769 progress 80 % (39 MB)
71 12:37:59.474548 progress 85 % (41 MB)
72 12:37:59.491728 progress 90 % (44 MB)
73 12:37:59.507796 progress 95 % (46 MB)
74 12:37:59.522420 progress 100 % (49 MB)
75 12:37:59.522672 49 MB downloaded in 0.29 s (166.71 MB/s)
76 12:37:59.522828 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:37:59.523059 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:37:59.523152 start: 1.3 download-retry (timeout 00:09:59) [common]
80 12:37:59.523237 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 12:37:59.523380 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:37:59.523453 saving as /var/lib/lava/dispatcher/tmp/12703510/tftp-deploy-mt650d1d/dtb/mt8192-asurada-spherion-r0.dtb
83 12:37:59.523516 total size: 47278 (0 MB)
84 12:37:59.523578 No compression specified
85 12:37:59.524732 progress 69 % (0 MB)
86 12:37:59.525051 progress 100 % (0 MB)
87 12:37:59.525209 0 MB downloaded in 0.00 s (26.68 MB/s)
88 12:37:59.525330 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:37:59.525549 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:37:59.525633 start: 1.4 download-retry (timeout 00:09:59) [common]
92 12:37:59.525716 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 12:37:59.525829 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/full.rootfs.tar.xz
94 12:37:59.525896 saving as /var/lib/lava/dispatcher/tmp/12703510/tftp-deploy-mt650d1d/nfsrootfs/full.rootfs.tar
95 12:37:59.525956 total size: 89451516 (85 MB)
96 12:37:59.526016 Using unxz to decompress xz
97 12:37:59.530249 progress 0 % (0 MB)
98 12:37:59.742715 progress 5 % (4 MB)
99 12:37:59.961135 progress 10 % (8 MB)
100 12:38:00.217801 progress 15 % (12 MB)
101 12:38:00.412250 progress 20 % (17 MB)
102 12:38:00.507811 progress 25 % (21 MB)
103 12:38:00.760937 progress 30 % (25 MB)
104 12:38:01.057885 progress 35 % (29 MB)
105 12:38:01.327615 progress 40 % (34 MB)
106 12:38:01.598491 progress 45 % (38 MB)
107 12:38:01.852000 progress 50 % (42 MB)
108 12:38:02.126007 progress 55 % (46 MB)
109 12:38:02.382855 progress 60 % (51 MB)
110 12:38:02.651355 progress 65 % (55 MB)
111 12:38:02.945147 progress 70 % (59 MB)
112 12:38:03.251245 progress 75 % (64 MB)
113 12:38:03.557303 progress 80 % (68 MB)
114 12:38:03.821200 progress 85 % (72 MB)
115 12:38:04.062742 progress 90 % (76 MB)
116 12:38:04.333117 progress 95 % (81 MB)
117 12:38:04.602954 progress 100 % (85 MB)
118 12:38:04.609206 85 MB downloaded in 5.08 s (16.78 MB/s)
119 12:38:04.609500 end: 1.4.1 http-download (duration 00:00:05) [common]
121 12:38:04.609797 end: 1.4 download-retry (duration 00:00:05) [common]
122 12:38:04.609909 start: 1.5 download-retry (timeout 00:09:54) [common]
123 12:38:04.610012 start: 1.5.1 http-download (timeout 00:09:54) [common]
124 12:38:04.610170 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:38:04.610242 saving as /var/lib/lava/dispatcher/tmp/12703510/tftp-deploy-mt650d1d/modules/modules.tar
126 12:38:04.610304 total size: 8639964 (8 MB)
127 12:38:04.610374 Using unxz to decompress xz
128 12:38:04.615017 progress 0 % (0 MB)
129 12:38:04.636478 progress 5 % (0 MB)
130 12:38:04.660296 progress 10 % (0 MB)
131 12:38:04.685336 progress 15 % (1 MB)
132 12:38:04.710092 progress 20 % (1 MB)
133 12:38:04.735504 progress 25 % (2 MB)
134 12:38:04.763875 progress 30 % (2 MB)
135 12:38:04.789771 progress 35 % (2 MB)
136 12:38:04.814304 progress 40 % (3 MB)
137 12:38:04.840282 progress 45 % (3 MB)
138 12:38:04.865929 progress 50 % (4 MB)
139 12:38:04.892288 progress 55 % (4 MB)
140 12:38:04.917091 progress 60 % (4 MB)
141 12:38:04.943115 progress 65 % (5 MB)
142 12:38:04.968906 progress 70 % (5 MB)
143 12:38:04.993807 progress 75 % (6 MB)
144 12:38:05.022177 progress 80 % (6 MB)
145 12:38:05.051575 progress 85 % (7 MB)
146 12:38:05.078356 progress 90 % (7 MB)
147 12:38:05.109441 progress 95 % (7 MB)
148 12:38:05.138607 progress 100 % (8 MB)
149 12:38:05.144680 8 MB downloaded in 0.53 s (15.42 MB/s)
150 12:38:05.144948 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:38:05.145216 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:38:05.145307 start: 1.6 prepare-tftp-overlay (timeout 00:09:54) [common]
154 12:38:05.145403 start: 1.6.1 extract-nfsrootfs (timeout 00:09:54) [common]
155 12:38:06.887077 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12703510/extract-nfsrootfs-kw_0knxi
156 12:38:06.887296 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 12:38:06.887419 start: 1.6.2 lava-overlay (timeout 00:09:52) [common]
158 12:38:06.887593 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5
159 12:38:06.887742 makedir: /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5/lava-12703510/bin
160 12:38:06.887860 makedir: /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5/lava-12703510/tests
161 12:38:06.887976 makedir: /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5/lava-12703510/results
162 12:38:06.888092 Creating /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5/lava-12703510/bin/lava-add-keys
163 12:38:06.888280 Creating /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5/lava-12703510/bin/lava-add-sources
164 12:38:06.888454 Creating /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5/lava-12703510/bin/lava-background-process-start
165 12:38:06.888629 Creating /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5/lava-12703510/bin/lava-background-process-stop
166 12:38:06.888839 Creating /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5/lava-12703510/bin/lava-common-functions
167 12:38:06.888985 Creating /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5/lava-12703510/bin/lava-echo-ipv4
168 12:38:06.889131 Creating /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5/lava-12703510/bin/lava-install-packages
169 12:38:06.889274 Creating /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5/lava-12703510/bin/lava-installed-packages
170 12:38:06.889416 Creating /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5/lava-12703510/bin/lava-os-build
171 12:38:06.889564 Creating /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5/lava-12703510/bin/lava-probe-channel
172 12:38:06.889735 Creating /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5/lava-12703510/bin/lava-probe-ip
173 12:38:06.889905 Creating /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5/lava-12703510/bin/lava-target-ip
174 12:38:06.890072 Creating /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5/lava-12703510/bin/lava-target-mac
175 12:38:06.890216 Creating /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5/lava-12703510/bin/lava-target-storage
176 12:38:06.890362 Creating /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5/lava-12703510/bin/lava-test-case
177 12:38:06.890507 Creating /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5/lava-12703510/bin/lava-test-event
178 12:38:06.890649 Creating /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5/lava-12703510/bin/lava-test-feedback
179 12:38:06.890791 Creating /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5/lava-12703510/bin/lava-test-raise
180 12:38:06.890937 Creating /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5/lava-12703510/bin/lava-test-reference
181 12:38:06.891108 Creating /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5/lava-12703510/bin/lava-test-runner
182 12:38:06.891280 Creating /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5/lava-12703510/bin/lava-test-set
183 12:38:06.891446 Creating /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5/lava-12703510/bin/lava-test-shell
184 12:38:06.891592 Updating /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5/lava-12703510/bin/lava-install-packages (oe)
185 12:38:06.891762 Updating /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5/lava-12703510/bin/lava-installed-packages (oe)
186 12:38:06.891908 Creating /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5/lava-12703510/environment
187 12:38:06.892028 LAVA metadata
188 12:38:06.892109 - LAVA_JOB_ID=12703510
189 12:38:06.892217 - LAVA_DISPATCHER_IP=192.168.201.1
190 12:38:06.892366 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:52) [common]
191 12:38:06.892465 skipped lava-vland-overlay
192 12:38:06.892584 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 12:38:06.892849 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:52) [common]
194 12:38:06.892948 skipped lava-multinode-overlay
195 12:38:06.893050 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 12:38:06.893148 start: 1.6.2.3 test-definition (timeout 00:09:52) [common]
197 12:38:06.893237 Loading test definitions
198 12:38:06.893348 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:52) [common]
199 12:38:06.893458 Using /lava-12703510 at stage 0
200 12:38:06.893787 uuid=12703510_1.6.2.3.1 testdef=None
201 12:38:06.893886 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 12:38:06.893987 start: 1.6.2.3.2 test-overlay (timeout 00:09:52) [common]
203 12:38:06.894691 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 12:38:06.894966 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:52) [common]
206 12:38:06.895579 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 12:38:06.895839 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:52) [common]
209 12:38:06.897084 runner path: /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5/lava-12703510/0/tests/0_lc-compliance test_uuid 12703510_1.6.2.3.1
210 12:38:06.897257 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 12:38:06.897488 Creating lava-test-runner.conf files
213 12:38:06.897573 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12703510/lava-overlay-bow4wgd5/lava-12703510/0 for stage 0
214 12:38:06.897692 - 0_lc-compliance
215 12:38:06.897830 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 12:38:06.897929 start: 1.6.2.4 compress-overlay (timeout 00:09:52) [common]
217 12:38:06.905212 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 12:38:06.905343 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:52) [common]
219 12:38:06.905449 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 12:38:06.905558 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 12:38:06.905686 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:52) [common]
222 12:38:07.027728 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 12:38:07.028131 start: 1.6.4 extract-modules (timeout 00:09:52) [common]
224 12:38:07.028267 extracting modules file /var/lib/lava/dispatcher/tmp/12703510/tftp-deploy-mt650d1d/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12703510/extract-nfsrootfs-kw_0knxi
225 12:38:07.250930 extracting modules file /var/lib/lava/dispatcher/tmp/12703510/tftp-deploy-mt650d1d/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12703510/extract-overlay-ramdisk-_fsazaqu/ramdisk
226 12:38:07.481046 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 12:38:07.481230 start: 1.6.5 apply-overlay-tftp (timeout 00:09:51) [common]
228 12:38:07.481345 [common] Applying overlay to NFS
229 12:38:07.481430 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12703510/compress-overlay-fxyu2_gw/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12703510/extract-nfsrootfs-kw_0knxi
230 12:38:07.488134 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 12:38:07.488277 start: 1.6.6 configure-preseed-file (timeout 00:09:51) [common]
232 12:38:07.488389 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 12:38:07.488517 start: 1.6.7 compress-ramdisk (timeout 00:09:51) [common]
234 12:38:07.488635 Building ramdisk /var/lib/lava/dispatcher/tmp/12703510/extract-overlay-ramdisk-_fsazaqu/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12703510/extract-overlay-ramdisk-_fsazaqu/ramdisk
235 12:38:07.795514 >> 119430 blocks
236 12:38:09.725604 rename /var/lib/lava/dispatcher/tmp/12703510/extract-overlay-ramdisk-_fsazaqu/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12703510/tftp-deploy-mt650d1d/ramdisk/ramdisk.cpio.gz
237 12:38:09.726078 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 12:38:09.726257 start: 1.6.8 prepare-kernel (timeout 00:09:49) [common]
239 12:38:09.726408 start: 1.6.8.1 prepare-fit (timeout 00:09:49) [common]
240 12:38:09.726560 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12703510/tftp-deploy-mt650d1d/kernel/Image'
241 12:38:22.979663 Returned 0 in 13 seconds
242 12:38:23.080333 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12703510/tftp-deploy-mt650d1d/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12703510/tftp-deploy-mt650d1d/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12703510/tftp-deploy-mt650d1d/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12703510/tftp-deploy-mt650d1d/kernel/image.itb
243 12:38:23.451297 output: FIT description: Kernel Image image with one or more FDT blobs
244 12:38:23.451697 output: Created: Mon Feb 5 12:38:23 2024
245 12:38:23.451806 output: Image 0 (kernel-1)
246 12:38:23.451893 output: Description:
247 12:38:23.451996 output: Created: Mon Feb 5 12:38:23 2024
248 12:38:23.452097 output: Type: Kernel Image
249 12:38:23.452195 output: Compression: lzma compressed
250 12:38:23.452274 output: Data Size: 12052857 Bytes = 11770.37 KiB = 11.49 MiB
251 12:38:23.452371 output: Architecture: AArch64
252 12:38:23.452465 output: OS: Linux
253 12:38:23.452561 output: Load Address: 0x00000000
254 12:38:23.452656 output: Entry Point: 0x00000000
255 12:38:23.452795 output: Hash algo: crc32
256 12:38:23.452892 output: Hash value: 8a14336a
257 12:38:23.452988 output: Image 1 (fdt-1)
258 12:38:23.453083 output: Description: mt8192-asurada-spherion-r0
259 12:38:23.453181 output: Created: Mon Feb 5 12:38:23 2024
260 12:38:23.453273 output: Type: Flat Device Tree
261 12:38:23.453366 output: Compression: uncompressed
262 12:38:23.453458 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
263 12:38:23.453549 output: Architecture: AArch64
264 12:38:23.453653 output: Hash algo: crc32
265 12:38:23.453747 output: Hash value: cc4352de
266 12:38:23.453838 output: Image 2 (ramdisk-1)
267 12:38:23.453930 output: Description: unavailable
268 12:38:23.454021 output: Created: Mon Feb 5 12:38:23 2024
269 12:38:23.454113 output: Type: RAMDisk Image
270 12:38:23.454203 output: Compression: Unknown Compression
271 12:38:23.454294 output: Data Size: 17801764 Bytes = 17384.54 KiB = 16.98 MiB
272 12:38:23.454385 output: Architecture: AArch64
273 12:38:23.454475 output: OS: Linux
274 12:38:23.454565 output: Load Address: unavailable
275 12:38:23.454656 output: Entry Point: unavailable
276 12:38:23.454747 output: Hash algo: crc32
277 12:38:23.454837 output: Hash value: a1902881
278 12:38:23.454926 output: Default Configuration: 'conf-1'
279 12:38:23.455017 output: Configuration 0 (conf-1)
280 12:38:23.455107 output: Description: mt8192-asurada-spherion-r0
281 12:38:23.455200 output: Kernel: kernel-1
282 12:38:23.455295 output: Init Ramdisk: ramdisk-1
283 12:38:23.455387 output: FDT: fdt-1
284 12:38:23.455477 output: Loadables: kernel-1
285 12:38:23.455568 output:
286 12:38:23.455852 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
287 12:38:23.455990 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
288 12:38:23.456126 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
289 12:38:23.456248 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:35) [common]
290 12:38:23.456362 No LXC device requested
291 12:38:23.456477 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 12:38:23.456596 start: 1.8 deploy-device-env (timeout 00:09:35) [common]
293 12:38:23.456714 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 12:38:23.456858 Checking files for TFTP limit of 4294967296 bytes.
295 12:38:23.457508 end: 1 tftp-deploy (duration 00:00:25) [common]
296 12:38:23.457642 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 12:38:23.457765 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 12:38:23.457934 substitutions:
299 12:38:23.458027 - {DTB}: 12703510/tftp-deploy-mt650d1d/dtb/mt8192-asurada-spherion-r0.dtb
300 12:38:23.458117 - {INITRD}: 12703510/tftp-deploy-mt650d1d/ramdisk/ramdisk.cpio.gz
301 12:38:23.458205 - {KERNEL}: 12703510/tftp-deploy-mt650d1d/kernel/Image
302 12:38:23.458290 - {LAVA_MAC}: None
303 12:38:23.458374 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12703510/extract-nfsrootfs-kw_0knxi
304 12:38:23.458461 - {NFS_SERVER_IP}: 192.168.201.1
305 12:38:23.458545 - {PRESEED_CONFIG}: None
306 12:38:23.458629 - {PRESEED_LOCAL}: None
307 12:38:23.458711 - {RAMDISK}: 12703510/tftp-deploy-mt650d1d/ramdisk/ramdisk.cpio.gz
308 12:38:23.458794 - {ROOT_PART}: None
309 12:38:23.458877 - {ROOT}: None
310 12:38:23.458959 - {SERVER_IP}: 192.168.201.1
311 12:38:23.459042 - {TEE}: None
312 12:38:23.459125 Parsed boot commands:
313 12:38:23.459206 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 12:38:23.459438 Parsed boot commands: tftpboot 192.168.201.1 12703510/tftp-deploy-mt650d1d/kernel/image.itb 12703510/tftp-deploy-mt650d1d/kernel/cmdline
315 12:38:23.459557 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 12:38:23.459671 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 12:38:23.459793 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 12:38:23.459908 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 12:38:23.460010 Not connected, no need to disconnect.
320 12:38:23.460114 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 12:38:23.460226 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 12:38:23.460323 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
323 12:38:23.464813 Setting prompt string to ['lava-test: # ']
324 12:38:23.465211 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 12:38:23.465329 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 12:38:23.465449 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 12:38:23.465574 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 12:38:23.465860 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
329 12:38:28.600773 >> Command sent successfully.
330 12:38:28.603094 Returned 0 in 5 seconds
331 12:38:28.703495 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 12:38:28.703811 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 12:38:28.703911 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 12:38:28.704004 Setting prompt string to 'Starting depthcharge on Spherion...'
336 12:38:28.704071 Changing prompt to 'Starting depthcharge on Spherion...'
337 12:38:28.704138 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 12:38:28.704406 [Enter `^Ec?' for help]
339 12:38:28.886867
340 12:38:28.887012
341 12:38:28.887081 F0: 102B 0000
342 12:38:28.887148
343 12:38:28.887209 F3: 1001 0000 [0200]
344 12:38:28.887271
345 12:38:28.890234 F3: 1001 0000
346 12:38:28.890318
347 12:38:28.890383 F7: 102D 0000
348 12:38:28.890444
349 12:38:28.894264 F1: 0000 0000
350 12:38:28.894346
351 12:38:28.894410 V0: 0000 0000 [0001]
352 12:38:28.894471
353 12:38:28.894528 00: 0007 8000
354 12:38:28.894589
355 12:38:28.897404 01: 0000 0000
356 12:38:28.897487
357 12:38:28.897551 BP: 0C00 0209 [0000]
358 12:38:28.897611
359 12:38:28.901434 G0: 1182 0000
360 12:38:28.901524
361 12:38:28.901588 EC: 0000 0021 [4000]
362 12:38:28.901648
363 12:38:28.905052 S7: 0000 0000 [0000]
364 12:38:28.905133
365 12:38:28.905198 CC: 0000 0000 [0001]
366 12:38:28.905257
367 12:38:28.907860 T0: 0000 0040 [010F]
368 12:38:28.907945
369 12:38:28.908009 Jump to BL
370 12:38:28.908069
371 12:38:28.933427
372 12:38:28.933513
373 12:38:28.933578
374 12:38:28.940765 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 12:38:28.943659 ARM64: Exception handlers installed.
376 12:38:28.947415 ARM64: Testing exception
377 12:38:28.950972 ARM64: Done test exception
378 12:38:28.957194 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 12:38:28.966971 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 12:38:28.974039 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 12:38:28.984129 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 12:38:28.991078 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 12:38:29.000907 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 12:38:29.012363 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 12:38:29.018912 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 12:38:29.036937 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 12:38:29.039891 WDT: Last reset was cold boot
388 12:38:29.043090 SPI1(PAD0) initialized at 2873684 Hz
389 12:38:29.046566 SPI5(PAD0) initialized at 992727 Hz
390 12:38:29.050165 VBOOT: Loading verstage.
391 12:38:29.056106 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 12:38:29.060043 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 12:38:29.063156 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 12:38:29.066224 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 12:38:29.073767 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 12:38:29.080359 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 12:38:29.091307 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
398 12:38:29.091393
399 12:38:29.091484
400 12:38:29.101297 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 12:38:29.105193 ARM64: Exception handlers installed.
402 12:38:29.107866 ARM64: Testing exception
403 12:38:29.107949 ARM64: Done test exception
404 12:38:29.114760 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 12:38:29.118221 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 12:38:29.132969 Probing TPM: . done!
407 12:38:29.133055 TPM ready after 0 ms
408 12:38:29.138972 Connected to device vid:did:rid of 1ae0:0028:00
409 12:38:29.148663 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
410 12:38:29.188251 Initialized TPM device CR50 revision 0
411 12:38:29.199091 tlcl_send_startup: Startup return code is 0
412 12:38:29.199180 TPM: setup succeeded
413 12:38:29.210681 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 12:38:29.219320 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 12:38:29.229441 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 12:38:29.238206 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 12:38:29.242116 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 12:38:29.245181 in-header: 03 07 00 00 08 00 00 00
419 12:38:29.248921 in-data: aa e4 47 04 13 02 00 00
420 12:38:29.251482 Chrome EC: UHEPI supported
421 12:38:29.258847 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 12:38:29.261656 in-header: 03 9d 00 00 08 00 00 00
423 12:38:29.265085 in-data: 10 20 20 08 00 00 00 00
424 12:38:29.265168 Phase 1
425 12:38:29.268621 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 12:38:29.275649 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 12:38:29.281693 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 12:38:29.285263 Recovery requested (1009000e)
429 12:38:29.291670 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 12:38:29.297489 tlcl_extend: response is 0
431 12:38:29.304931 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 12:38:29.310648 tlcl_extend: response is 0
433 12:38:29.317387 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 12:38:29.337362 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
435 12:38:29.344513 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 12:38:29.344614
437 12:38:29.344681
438 12:38:29.355306 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 12:38:29.358395 ARM64: Exception handlers installed.
440 12:38:29.361509 ARM64: Testing exception
441 12:38:29.361597 ARM64: Done test exception
442 12:38:29.384044 pmic_efuse_setting: Set efuses in 11 msecs
443 12:38:29.387092 pmwrap_interface_init: Select PMIF_VLD_RDY
444 12:38:29.393734 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 12:38:29.397639 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 12:38:29.401025 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 12:38:29.409181 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 12:38:29.411842 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 12:38:29.416468 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 12:38:29.423187 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 12:38:29.426894 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 12:38:29.429830 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 12:38:29.436407 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 12:38:29.439612 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 12:38:29.446699 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 12:38:29.450029 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 12:38:29.456513 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 12:38:29.462832 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 12:38:29.466332 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 12:38:29.473340 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 12:38:29.480142 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 12:38:29.483778 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 12:38:29.490751 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 12:38:29.494087 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 12:38:29.500587 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 12:38:29.507256 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 12:38:29.510959 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 12:38:29.517496 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 12:38:29.523548 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 12:38:29.526845 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 12:38:29.533640 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 12:38:29.537204 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 12:38:29.540841 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 12:38:29.547816 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 12:38:29.554199 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 12:38:29.557229 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 12:38:29.564077 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 12:38:29.567273 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 12:38:29.574143 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 12:38:29.577152 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 12:38:29.583469 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 12:38:29.587246 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 12:38:29.590452 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 12:38:29.593984 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 12:38:29.600288 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 12:38:29.603827 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 12:38:29.607563 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 12:38:29.613566 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 12:38:29.617274 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 12:38:29.621152 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 12:38:29.627644 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 12:38:29.630530 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 12:38:29.633798 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 12:38:29.637209 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 12:38:29.647170 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 12:38:29.654372 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 12:38:29.660450 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 12:38:29.667132 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 12:38:29.677905 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 12:38:29.680743 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 12:38:29.684350 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 12:38:29.691046 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 12:38:29.697477 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
504 12:38:29.701065 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 12:38:29.707873 [RTC]rtc_osc_init,62: osc32con val = 0xde70
506 12:38:29.711469 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 12:38:29.720109 [RTC]rtc_get_frequency_meter,154: input=15, output=763
508 12:38:29.729670 [RTC]rtc_get_frequency_meter,154: input=23, output=948
509 12:38:29.740267 [RTC]rtc_get_frequency_meter,154: input=19, output=857
510 12:38:29.749290 [RTC]rtc_get_frequency_meter,154: input=17, output=810
511 12:38:29.758567 [RTC]rtc_get_frequency_meter,154: input=16, output=788
512 12:38:29.768115 [RTC]rtc_get_frequency_meter,154: input=16, output=788
513 12:38:29.777857 [RTC]rtc_get_frequency_meter,154: input=17, output=811
514 12:38:29.781652 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
515 12:38:29.788312 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
516 12:38:29.791437 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
517 12:38:29.794992 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
518 12:38:29.801337 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
519 12:38:29.804577 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
520 12:38:29.808796 ADC[4]: Raw value=671168 ID=5
521 12:38:29.808892 ADC[3]: Raw value=212549 ID=1
522 12:38:29.811166 RAM Code: 0x51
523 12:38:29.815362 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
524 12:38:29.821793 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
525 12:38:29.828460 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
526 12:38:29.834688 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
527 12:38:29.838052 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
528 12:38:29.841491 in-header: 03 07 00 00 08 00 00 00
529 12:38:29.844647 in-data: aa e4 47 04 13 02 00 00
530 12:38:29.848448 Chrome EC: UHEPI supported
531 12:38:29.854325 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
532 12:38:29.858123 in-header: 03 d5 00 00 08 00 00 00
533 12:38:29.861437 in-data: 98 20 60 08 00 00 00 00
534 12:38:29.865197 MRC: failed to locate region type 0.
535 12:38:29.870992 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
536 12:38:29.874945 DRAM-K: Running full calibration
537 12:38:29.878332 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
538 12:38:29.881580 header.status = 0x0
539 12:38:29.884316 header.version = 0x6 (expected: 0x6)
540 12:38:29.888073 header.size = 0xd00 (expected: 0xd00)
541 12:38:29.888168 header.flags = 0x0
542 12:38:29.894211 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
543 12:38:29.913387 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
544 12:38:29.919844 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
545 12:38:29.922736 dram_init: ddr_geometry: 0
546 12:38:29.926818 [EMI] MDL number = 0
547 12:38:29.926913 [EMI] Get MDL freq = 0
548 12:38:29.929979 dram_init: ddr_type: 0
549 12:38:29.930065 is_discrete_lpddr4: 1
550 12:38:29.933566 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
551 12:38:29.933652
552 12:38:29.933716
553 12:38:29.936581 [Bian_co] ETT version 0.0.0.1
554 12:38:29.940617 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
555 12:38:29.940718
556 12:38:29.947422 dramc_set_vcore_voltage set vcore to 650000
557 12:38:29.947539 Read voltage for 800, 4
558 12:38:29.950776 Vio18 = 0
559 12:38:29.950865 Vcore = 650000
560 12:38:29.950932 Vdram = 0
561 12:38:29.953864 Vddq = 0
562 12:38:29.953953 Vmddr = 0
563 12:38:29.956961 dram_init: config_dvfs: 1
564 12:38:29.960499 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
565 12:38:29.967553 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
566 12:38:29.971125 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
567 12:38:29.973576 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
568 12:38:29.978030 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
569 12:38:29.980902 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
570 12:38:29.983831 MEM_TYPE=3, freq_sel=18
571 12:38:29.988179 sv_algorithm_assistance_LP4_1600
572 12:38:29.990494 ============ PULL DRAM RESETB DOWN ============
573 12:38:29.994000 ========== PULL DRAM RESETB DOWN end =========
574 12:38:30.000828 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
575 12:38:30.004067 ===================================
576 12:38:30.004175 LPDDR4 DRAM CONFIGURATION
577 12:38:30.007418 ===================================
578 12:38:30.010324 EX_ROW_EN[0] = 0x0
579 12:38:30.010425 EX_ROW_EN[1] = 0x0
580 12:38:30.014774 LP4Y_EN = 0x0
581 12:38:30.017534 WORK_FSP = 0x0
582 12:38:30.017632 WL = 0x2
583 12:38:30.020416 RL = 0x2
584 12:38:30.020505 BL = 0x2
585 12:38:30.023509 RPST = 0x0
586 12:38:30.023597 RD_PRE = 0x0
587 12:38:30.026745 WR_PRE = 0x1
588 12:38:30.026834 WR_PST = 0x0
589 12:38:30.031219 DBI_WR = 0x0
590 12:38:30.031318 DBI_RD = 0x0
591 12:38:30.034880 OTF = 0x1
592 12:38:30.036870 ===================================
593 12:38:30.040269 ===================================
594 12:38:30.040362 ANA top config
595 12:38:30.044204 ===================================
596 12:38:30.047102 DLL_ASYNC_EN = 0
597 12:38:30.050238 ALL_SLAVE_EN = 1
598 12:38:30.050328 NEW_RANK_MODE = 1
599 12:38:30.053727 DLL_IDLE_MODE = 1
600 12:38:30.056918 LP45_APHY_COMB_EN = 1
601 12:38:30.060227 TX_ODT_DIS = 1
602 12:38:30.063470 NEW_8X_MODE = 1
603 12:38:30.063561 ===================================
604 12:38:30.067687 ===================================
605 12:38:30.070430 data_rate = 1600
606 12:38:30.073543 CKR = 1
607 12:38:30.077100 DQ_P2S_RATIO = 8
608 12:38:30.080357 ===================================
609 12:38:30.083754 CA_P2S_RATIO = 8
610 12:38:30.087445 DQ_CA_OPEN = 0
611 12:38:30.087536 DQ_SEMI_OPEN = 0
612 12:38:30.090477 CA_SEMI_OPEN = 0
613 12:38:30.093852 CA_FULL_RATE = 0
614 12:38:30.097295 DQ_CKDIV4_EN = 1
615 12:38:30.100771 CA_CKDIV4_EN = 1
616 12:38:30.104122 CA_PREDIV_EN = 0
617 12:38:30.104222 PH8_DLY = 0
618 12:38:30.106862 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
619 12:38:30.110390 DQ_AAMCK_DIV = 4
620 12:38:30.114244 CA_AAMCK_DIV = 4
621 12:38:30.116969 CA_ADMCK_DIV = 4
622 12:38:30.120395 DQ_TRACK_CA_EN = 0
623 12:38:30.120482 CA_PICK = 800
624 12:38:30.123915 CA_MCKIO = 800
625 12:38:30.127113 MCKIO_SEMI = 0
626 12:38:30.130715 PLL_FREQ = 3068
627 12:38:30.134616 DQ_UI_PI_RATIO = 32
628 12:38:30.137279 CA_UI_PI_RATIO = 0
629 12:38:30.140597 ===================================
630 12:38:30.144798 ===================================
631 12:38:30.144904 memory_type:LPDDR4
632 12:38:30.147453 GP_NUM : 10
633 12:38:30.150671 SRAM_EN : 1
634 12:38:30.150766 MD32_EN : 0
635 12:38:30.154243 ===================================
636 12:38:30.157095 [ANA_INIT] >>>>>>>>>>>>>>
637 12:38:30.160330 <<<<<< [CONFIGURE PHASE]: ANA_TX
638 12:38:30.163703 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
639 12:38:30.167304 ===================================
640 12:38:30.170314 data_rate = 1600,PCW = 0X7600
641 12:38:30.173429 ===================================
642 12:38:30.177741 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
643 12:38:30.180649 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 12:38:30.187998 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
645 12:38:30.190268 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
646 12:38:30.194120 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
647 12:38:30.196861 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
648 12:38:30.200473 [ANA_INIT] flow start
649 12:38:30.203874 [ANA_INIT] PLL >>>>>>>>
650 12:38:30.203963 [ANA_INIT] PLL <<<<<<<<
651 12:38:30.206853 [ANA_INIT] MIDPI >>>>>>>>
652 12:38:30.210195 [ANA_INIT] MIDPI <<<<<<<<
653 12:38:30.213549 [ANA_INIT] DLL >>>>>>>>
654 12:38:30.213651 [ANA_INIT] flow end
655 12:38:30.217581 ============ LP4 DIFF to SE enter ============
656 12:38:30.224053 ============ LP4 DIFF to SE exit ============
657 12:38:30.224169 [ANA_INIT] <<<<<<<<<<<<<
658 12:38:30.227142 [Flow] Enable top DCM control >>>>>
659 12:38:30.230136 [Flow] Enable top DCM control <<<<<
660 12:38:30.233495 Enable DLL master slave shuffle
661 12:38:30.240697 ==============================================================
662 12:38:30.240945 Gating Mode config
663 12:38:30.246901 ==============================================================
664 12:38:30.250917 Config description:
665 12:38:30.257542 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
666 12:38:30.263693 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
667 12:38:30.270552 SELPH_MODE 0: By rank 1: By Phase
668 12:38:30.273482 ==============================================================
669 12:38:30.277451 GAT_TRACK_EN = 1
670 12:38:30.280647 RX_GATING_MODE = 2
671 12:38:30.284241 RX_GATING_TRACK_MODE = 2
672 12:38:30.287618 SELPH_MODE = 1
673 12:38:30.291435 PICG_EARLY_EN = 1
674 12:38:30.294923 VALID_LAT_VALUE = 1
675 12:38:30.301968 ==============================================================
676 12:38:30.303628 Enter into Gating configuration >>>>
677 12:38:30.307457 Exit from Gating configuration <<<<
678 12:38:30.307547 Enter into DVFS_PRE_config >>>>>
679 12:38:30.321234 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
680 12:38:30.323812 Exit from DVFS_PRE_config <<<<<
681 12:38:30.327919 Enter into PICG configuration >>>>
682 12:38:30.331141 Exit from PICG configuration <<<<
683 12:38:30.331233 [RX_INPUT] configuration >>>>>
684 12:38:30.333840 [RX_INPUT] configuration <<<<<
685 12:38:30.340471 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
686 12:38:30.344268 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
687 12:38:30.350981 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
688 12:38:30.357583 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
689 12:38:30.363947 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
690 12:38:30.370741 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
691 12:38:30.373827 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
692 12:38:30.377403 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
693 12:38:30.380618 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
694 12:38:30.387562 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
695 12:38:30.390748 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
696 12:38:30.394465 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 12:38:30.397166 ===================================
698 12:38:30.400644 LPDDR4 DRAM CONFIGURATION
699 12:38:30.404534 ===================================
700 12:38:30.407591 EX_ROW_EN[0] = 0x0
701 12:38:30.407702 EX_ROW_EN[1] = 0x0
702 12:38:30.411117 LP4Y_EN = 0x0
703 12:38:30.411253 WORK_FSP = 0x0
704 12:38:30.414099 WL = 0x2
705 12:38:30.414201 RL = 0x2
706 12:38:30.417203 BL = 0x2
707 12:38:30.417298 RPST = 0x0
708 12:38:30.420305 RD_PRE = 0x0
709 12:38:30.420396 WR_PRE = 0x1
710 12:38:30.424533 WR_PST = 0x0
711 12:38:30.424624 DBI_WR = 0x0
712 12:38:30.427246 DBI_RD = 0x0
713 12:38:30.427332 OTF = 0x1
714 12:38:30.431423 ===================================
715 12:38:30.437332 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
716 12:38:30.440958 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
717 12:38:30.444008 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
718 12:38:30.447151 ===================================
719 12:38:30.450624 LPDDR4 DRAM CONFIGURATION
720 12:38:30.454561 ===================================
721 12:38:30.454661 EX_ROW_EN[0] = 0x10
722 12:38:30.457523 EX_ROW_EN[1] = 0x0
723 12:38:30.461485 LP4Y_EN = 0x0
724 12:38:30.461579 WORK_FSP = 0x0
725 12:38:30.464065 WL = 0x2
726 12:38:30.464151 RL = 0x2
727 12:38:30.467577 BL = 0x2
728 12:38:30.467665 RPST = 0x0
729 12:38:30.470699 RD_PRE = 0x0
730 12:38:30.470792 WR_PRE = 0x1
731 12:38:30.473829 WR_PST = 0x0
732 12:38:30.473920 DBI_WR = 0x0
733 12:38:30.476860 DBI_RD = 0x0
734 12:38:30.476946 OTF = 0x1
735 12:38:30.480583 ===================================
736 12:38:30.486805 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
737 12:38:30.491212 nWR fixed to 40
738 12:38:30.495235 [ModeRegInit_LP4] CH0 RK0
739 12:38:30.495331 [ModeRegInit_LP4] CH0 RK1
740 12:38:30.498293 [ModeRegInit_LP4] CH1 RK0
741 12:38:30.501400 [ModeRegInit_LP4] CH1 RK1
742 12:38:30.501491 match AC timing 12
743 12:38:30.507734 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
744 12:38:30.511384 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
745 12:38:30.514707 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
746 12:38:30.522253 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
747 12:38:30.524367 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
748 12:38:30.524462 [EMI DOE] emi_dcm 0
749 12:38:30.531431 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
750 12:38:30.531533 ==
751 12:38:30.534492 Dram Type= 6, Freq= 0, CH_0, rank 0
752 12:38:30.537993 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
753 12:38:30.538089 ==
754 12:38:30.545033 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
755 12:38:30.551617 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
756 12:38:30.559522 [CA 0] Center 37 (7~68) winsize 62
757 12:38:30.561839 [CA 1] Center 37 (6~68) winsize 63
758 12:38:30.566476 [CA 2] Center 35 (5~66) winsize 62
759 12:38:30.568356 [CA 3] Center 35 (4~66) winsize 63
760 12:38:30.572355 [CA 4] Center 34 (3~65) winsize 63
761 12:38:30.575324 [CA 5] Center 33 (3~64) winsize 62
762 12:38:30.575414
763 12:38:30.578630 [CmdBusTrainingLP45] Vref(ca) range 1: 34
764 12:38:30.578717
765 12:38:30.581903 [CATrainingPosCal] consider 1 rank data
766 12:38:30.586247 u2DelayCellTimex100 = 270/100 ps
767 12:38:30.589363 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
768 12:38:30.591955 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
769 12:38:30.598931 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
770 12:38:30.602172 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
771 12:38:30.605214 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
772 12:38:30.609040 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
773 12:38:30.609133
774 12:38:30.612481 CA PerBit enable=1, Macro0, CA PI delay=33
775 12:38:30.612599
776 12:38:30.615216 [CBTSetCACLKResult] CA Dly = 33
777 12:38:30.615303 CS Dly: 5 (0~36)
778 12:38:30.618545 ==
779 12:38:30.618633 Dram Type= 6, Freq= 0, CH_0, rank 1
780 12:38:30.625260 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
781 12:38:30.625357 ==
782 12:38:30.629077 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 12:38:30.635247 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 12:38:30.644721 [CA 0] Center 37 (6~68) winsize 63
785 12:38:30.648178 [CA 1] Center 37 (6~68) winsize 63
786 12:38:30.651512 [CA 2] Center 35 (4~66) winsize 63
787 12:38:30.654706 [CA 3] Center 34 (4~65) winsize 62
788 12:38:30.657885 [CA 4] Center 34 (4~64) winsize 61
789 12:38:30.661765 [CA 5] Center 33 (3~64) winsize 62
790 12:38:30.661868
791 12:38:30.664874 [CmdBusTrainingLP45] Vref(ca) range 1: 34
792 12:38:30.664964
793 12:38:30.668609 [CATrainingPosCal] consider 2 rank data
794 12:38:30.672207 u2DelayCellTimex100 = 270/100 ps
795 12:38:30.674863 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
796 12:38:30.681648 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
797 12:38:30.684892 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
798 12:38:30.687780 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
799 12:38:30.691255 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
800 12:38:30.694530 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
801 12:38:30.694625
802 12:38:30.697744 CA PerBit enable=1, Macro0, CA PI delay=33
803 12:38:30.697860
804 12:38:30.701336 [CBTSetCACLKResult] CA Dly = 33
805 12:38:30.701452 CS Dly: 6 (0~38)
806 12:38:30.701525
807 12:38:30.704291 ----->DramcWriteLeveling(PI) begin...
808 12:38:30.708457 ==
809 12:38:30.711351 Dram Type= 6, Freq= 0, CH_0, rank 0
810 12:38:30.714960 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
811 12:38:30.715069 ==
812 12:38:30.717957 Write leveling (Byte 0): 29 => 29
813 12:38:30.721889 Write leveling (Byte 1): 28 => 28
814 12:38:30.724932 DramcWriteLeveling(PI) end<-----
815 12:38:30.725026
816 12:38:30.725093 ==
817 12:38:30.728130 Dram Type= 6, Freq= 0, CH_0, rank 0
818 12:38:30.732191 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
819 12:38:30.732279 ==
820 12:38:30.734856 [Gating] SW mode calibration
821 12:38:30.741055 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
822 12:38:30.745756 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
823 12:38:30.751283 0 6 0 | B1->B0 | 3030 2f2f | 1 1 | (1 1) (1 1)
824 12:38:30.754620 0 6 4 | B1->B0 | 2a2a 2727 | 0 0 | (1 1) (1 1)
825 12:38:30.758356 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 12:38:30.764888 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:38:30.767808 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 12:38:30.771519 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 12:38:30.778270 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 12:38:30.781013 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 12:38:30.784543 0 7 0 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
832 12:38:30.792080 0 7 4 | B1->B0 | 3838 4141 | 0 0 | (0 0) (0 0)
833 12:38:30.794354 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 12:38:30.798376 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 12:38:30.804352 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 12:38:30.807590 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 12:38:30.810904 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 12:38:30.818582 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 12:38:30.821190 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 12:38:30.824335 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:38:30.830939 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:38:30.834617 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:38:30.837473 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:38:30.844798 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:38:30.847728 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:38:30.851027 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:38:30.854731 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:38:30.860769 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 12:38:30.864496 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 12:38:30.867805 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 12:38:30.874325 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 12:38:30.878446 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 12:38:30.881003 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 12:38:30.887531 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 12:38:30.891616 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 12:38:30.894203 Total UI for P1: 0, mck2ui 16
857 12:38:30.897767 best dqsien dly found for B0: ( 0, 9, 30)
858 12:38:30.901888 Total UI for P1: 0, mck2ui 16
859 12:38:30.904913 best dqsien dly found for B1: ( 0, 9, 30)
860 12:38:30.909079 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
861 12:38:30.910941 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
862 12:38:30.911029
863 12:38:30.914606 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
864 12:38:30.917360 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
865 12:38:30.921510 [Gating] SW calibration Done
866 12:38:30.921599 ==
867 12:38:30.924609 Dram Type= 6, Freq= 0, CH_0, rank 0
868 12:38:30.931120 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
869 12:38:30.931227 ==
870 12:38:30.931297 RX Vref Scan: 0
871 12:38:30.931360
872 12:38:30.935536 RX Vref 0 -> 0, step: 1
873 12:38:30.935625
874 12:38:30.938449 RX Delay -130 -> 252, step: 16
875 12:38:30.941932 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
876 12:38:30.945418 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
877 12:38:30.948345 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
878 12:38:30.951645 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
879 12:38:30.955545 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
880 12:38:30.961675 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
881 12:38:30.965036 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
882 12:38:30.968235 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
883 12:38:30.972429 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
884 12:38:30.975103 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
885 12:38:30.981622 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
886 12:38:30.985045 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
887 12:38:30.989323 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
888 12:38:30.992381 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
889 12:38:30.996006 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
890 12:38:31.001613 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
891 12:38:31.001713 ==
892 12:38:31.004906 Dram Type= 6, Freq= 0, CH_0, rank 0
893 12:38:31.009300 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
894 12:38:31.009392 ==
895 12:38:31.009460 DQS Delay:
896 12:38:31.011666 DQS0 = 0, DQS1 = 0
897 12:38:31.011752 DQM Delay:
898 12:38:31.014897 DQM0 = 81, DQM1 = 73
899 12:38:31.014986 DQ Delay:
900 12:38:31.018521 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
901 12:38:31.021944 DQ4 =77, DQ5 =69, DQ6 =93, DQ7 =93
902 12:38:31.025175 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
903 12:38:31.028210 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
904 12:38:31.028297
905 12:38:31.028363
906 12:38:31.028425 ==
907 12:38:31.031511 Dram Type= 6, Freq= 0, CH_0, rank 0
908 12:38:31.035318 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
909 12:38:31.035410 ==
910 12:38:31.035478
911 12:38:31.035540
912 12:38:31.038172 TX Vref Scan disable
913 12:38:31.042683 == TX Byte 0 ==
914 12:38:31.045134 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
915 12:38:31.048236 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
916 12:38:31.052577 == TX Byte 1 ==
917 12:38:31.055097 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
918 12:38:31.058486 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
919 12:38:31.058577 ==
920 12:38:31.061989 Dram Type= 6, Freq= 0, CH_0, rank 0
921 12:38:31.068168 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
922 12:38:31.068262 ==
923 12:38:31.079679 TX Vref=22, minBit 2, minWin=27, winSum=442
924 12:38:31.082935 TX Vref=24, minBit 2, minWin=27, winSum=446
925 12:38:31.086275 TX Vref=26, minBit 4, minWin=27, winSum=448
926 12:38:31.089591 TX Vref=28, minBit 0, minWin=28, winSum=452
927 12:38:31.092819 TX Vref=30, minBit 0, minWin=28, winSum=451
928 12:38:31.096865 TX Vref=32, minBit 0, minWin=28, winSum=453
929 12:38:31.102944 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 32
930 12:38:31.103047
931 12:38:31.106513 Final TX Range 1 Vref 32
932 12:38:31.106603
933 12:38:31.106689 ==
934 12:38:31.109995 Dram Type= 6, Freq= 0, CH_0, rank 0
935 12:38:31.113236 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
936 12:38:31.113340 ==
937 12:38:31.113429
938 12:38:31.116950
939 12:38:31.117042 TX Vref Scan disable
940 12:38:31.119965 == TX Byte 0 ==
941 12:38:31.123225 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
942 12:38:31.130139 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
943 12:38:31.130281 == TX Byte 1 ==
944 12:38:31.133245 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
945 12:38:31.140263 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
946 12:38:31.140369
947 12:38:31.140438 [DATLAT]
948 12:38:31.140500 Freq=800, CH0 RK0
949 12:38:31.140560
950 12:38:31.143168 DATLAT Default: 0xa
951 12:38:31.143253 0, 0xFFFF, sum = 0
952 12:38:31.146207 1, 0xFFFF, sum = 0
953 12:38:31.146326 2, 0xFFFF, sum = 0
954 12:38:31.149443 3, 0xFFFF, sum = 0
955 12:38:31.149531 4, 0xFFFF, sum = 0
956 12:38:31.152847 5, 0xFFFF, sum = 0
957 12:38:31.156638 6, 0xFFFF, sum = 0
958 12:38:31.156775 7, 0xFFFF, sum = 0
959 12:38:31.156846 8, 0x0, sum = 1
960 12:38:31.159811 9, 0x0, sum = 2
961 12:38:31.159899 10, 0x0, sum = 3
962 12:38:31.162883 11, 0x0, sum = 4
963 12:38:31.162970 best_step = 9
964 12:38:31.163036
965 12:38:31.163098 ==
966 12:38:31.166776 Dram Type= 6, Freq= 0, CH_0, rank 0
967 12:38:31.172847 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
968 12:38:31.172942 ==
969 12:38:31.173010 RX Vref Scan: 1
970 12:38:31.173072
971 12:38:31.176471 Set Vref Range= 32 -> 127
972 12:38:31.176556
973 12:38:31.180123 RX Vref 32 -> 127, step: 1
974 12:38:31.180209
975 12:38:31.182731 RX Delay -111 -> 252, step: 8
976 12:38:31.182817
977 12:38:31.186275 Set Vref, RX VrefLevel [Byte0]: 32
978 12:38:31.189493 [Byte1]: 32
979 12:38:31.189581
980 12:38:31.192690 Set Vref, RX VrefLevel [Byte0]: 33
981 12:38:31.195954 [Byte1]: 33
982 12:38:31.196040
983 12:38:31.199388 Set Vref, RX VrefLevel [Byte0]: 34
984 12:38:31.203130 [Byte1]: 34
985 12:38:31.206102
986 12:38:31.206190 Set Vref, RX VrefLevel [Byte0]: 35
987 12:38:31.209636 [Byte1]: 35
988 12:38:31.213443
989 12:38:31.213545 Set Vref, RX VrefLevel [Byte0]: 36
990 12:38:31.217260 [Byte1]: 36
991 12:38:31.221044
992 12:38:31.221138 Set Vref, RX VrefLevel [Byte0]: 37
993 12:38:31.224247 [Byte1]: 37
994 12:38:31.229205
995 12:38:31.229306 Set Vref, RX VrefLevel [Byte0]: 38
996 12:38:31.232394 [Byte1]: 38
997 12:38:31.236576
998 12:38:31.236691 Set Vref, RX VrefLevel [Byte0]: 39
999 12:38:31.240013 [Byte1]: 39
1000 12:38:31.244124
1001 12:38:31.244215 Set Vref, RX VrefLevel [Byte0]: 40
1002 12:38:31.247208 [Byte1]: 40
1003 12:38:31.251676
1004 12:38:31.251768 Set Vref, RX VrefLevel [Byte0]: 41
1005 12:38:31.254840 [Byte1]: 41
1006 12:38:31.259487
1007 12:38:31.259585 Set Vref, RX VrefLevel [Byte0]: 42
1008 12:38:31.262407 [Byte1]: 42
1009 12:38:31.266894
1010 12:38:31.266990 Set Vref, RX VrefLevel [Byte0]: 43
1011 12:38:31.270769 [Byte1]: 43
1012 12:38:31.275123
1013 12:38:31.275215 Set Vref, RX VrefLevel [Byte0]: 44
1014 12:38:31.278114 [Byte1]: 44
1015 12:38:31.282413
1016 12:38:31.282507 Set Vref, RX VrefLevel [Byte0]: 45
1017 12:38:31.285445 [Byte1]: 45
1018 12:38:31.290690
1019 12:38:31.290783 Set Vref, RX VrefLevel [Byte0]: 46
1020 12:38:31.293287 [Byte1]: 46
1021 12:38:31.297615
1022 12:38:31.297704 Set Vref, RX VrefLevel [Byte0]: 47
1023 12:38:31.300595 [Byte1]: 47
1024 12:38:31.305808
1025 12:38:31.305937 Set Vref, RX VrefLevel [Byte0]: 48
1026 12:38:31.308893 [Byte1]: 48
1027 12:38:31.312740
1028 12:38:31.312846 Set Vref, RX VrefLevel [Byte0]: 49
1029 12:38:31.316294 [Byte1]: 49
1030 12:38:31.321179
1031 12:38:31.321279 Set Vref, RX VrefLevel [Byte0]: 50
1032 12:38:31.323777 [Byte1]: 50
1033 12:38:31.328075
1034 12:38:31.328170 Set Vref, RX VrefLevel [Byte0]: 51
1035 12:38:31.331607 [Byte1]: 51
1036 12:38:31.335533
1037 12:38:31.335626 Set Vref, RX VrefLevel [Byte0]: 52
1038 12:38:31.339429 [Byte1]: 52
1039 12:38:31.343874
1040 12:38:31.343972 Set Vref, RX VrefLevel [Byte0]: 53
1041 12:38:31.346578 [Byte1]: 53
1042 12:38:31.351308
1043 12:38:31.351403 Set Vref, RX VrefLevel [Byte0]: 54
1044 12:38:31.354809 [Byte1]: 54
1045 12:38:31.358764
1046 12:38:31.358859 Set Vref, RX VrefLevel [Byte0]: 55
1047 12:38:31.362263 [Byte1]: 55
1048 12:38:31.366304
1049 12:38:31.366396 Set Vref, RX VrefLevel [Byte0]: 56
1050 12:38:31.369484 [Byte1]: 56
1051 12:38:31.374262
1052 12:38:31.374358 Set Vref, RX VrefLevel [Byte0]: 57
1053 12:38:31.378309 [Byte1]: 57
1054 12:38:31.381436
1055 12:38:31.381526 Set Vref, RX VrefLevel [Byte0]: 58
1056 12:38:31.384792 [Byte1]: 58
1057 12:38:31.389167
1058 12:38:31.389256 Set Vref, RX VrefLevel [Byte0]: 59
1059 12:38:31.392595 [Byte1]: 59
1060 12:38:31.396986
1061 12:38:31.397074 Set Vref, RX VrefLevel [Byte0]: 60
1062 12:38:31.400696 [Byte1]: 60
1063 12:38:31.404340
1064 12:38:31.404428 Set Vref, RX VrefLevel [Byte0]: 61
1065 12:38:31.408294 [Byte1]: 61
1066 12:38:31.412938
1067 12:38:31.413040 Set Vref, RX VrefLevel [Byte0]: 62
1068 12:38:31.415711 [Byte1]: 62
1069 12:38:31.421034
1070 12:38:31.421130 Set Vref, RX VrefLevel [Byte0]: 63
1071 12:38:31.423544 [Byte1]: 63
1072 12:38:31.427716
1073 12:38:31.427810 Set Vref, RX VrefLevel [Byte0]: 64
1074 12:38:31.430924 [Byte1]: 64
1075 12:38:31.435617
1076 12:38:31.435709 Set Vref, RX VrefLevel [Byte0]: 65
1077 12:38:31.439420 [Byte1]: 65
1078 12:38:31.442731
1079 12:38:31.442821 Set Vref, RX VrefLevel [Byte0]: 66
1080 12:38:31.446667 [Byte1]: 66
1081 12:38:31.451015
1082 12:38:31.451106 Set Vref, RX VrefLevel [Byte0]: 67
1083 12:38:31.455743 [Byte1]: 67
1084 12:38:31.458496
1085 12:38:31.458589 Set Vref, RX VrefLevel [Byte0]: 68
1086 12:38:31.462067 [Byte1]: 68
1087 12:38:31.467151
1088 12:38:31.467246 Set Vref, RX VrefLevel [Byte0]: 69
1089 12:38:31.470859 [Byte1]: 69
1090 12:38:31.473469
1091 12:38:31.473561 Set Vref, RX VrefLevel [Byte0]: 70
1092 12:38:31.476946 [Byte1]: 70
1093 12:38:31.481305
1094 12:38:31.481399 Set Vref, RX VrefLevel [Byte0]: 71
1095 12:38:31.485091 [Byte1]: 71
1096 12:38:31.488646
1097 12:38:31.488797 Set Vref, RX VrefLevel [Byte0]: 72
1098 12:38:31.492318 [Byte1]: 72
1099 12:38:31.496186
1100 12:38:31.496276 Set Vref, RX VrefLevel [Byte0]: 73
1101 12:38:31.499410 [Byte1]: 73
1102 12:38:31.504583
1103 12:38:31.504699 Final RX Vref Byte 0 = 52 to rank0
1104 12:38:31.507631 Final RX Vref Byte 1 = 48 to rank0
1105 12:38:31.510668 Final RX Vref Byte 0 = 52 to rank1
1106 12:38:31.514885 Final RX Vref Byte 1 = 48 to rank1==
1107 12:38:31.517231 Dram Type= 6, Freq= 0, CH_0, rank 0
1108 12:38:31.523874 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1109 12:38:31.523979 ==
1110 12:38:31.524067 DQS Delay:
1111 12:38:31.524151 DQS0 = 0, DQS1 = 0
1112 12:38:31.527562 DQM Delay:
1113 12:38:31.527652 DQM0 = 83, DQM1 = 73
1114 12:38:31.530983 DQ Delay:
1115 12:38:31.533762 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1116 12:38:31.537255 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1117 12:38:31.537346 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1118 12:38:31.544042 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1119 12:38:31.544147
1120 12:38:31.544236
1121 12:38:31.550622 [DQSOSCAuto] RK0, (LSB)MR18= 0x3737, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1122 12:38:31.553870 CH0 RK0: MR19=606, MR18=3737
1123 12:38:31.560825 CH0_RK0: MR19=0x606, MR18=0x3737, DQSOSC=395, MR23=63, INC=94, DEC=63
1124 12:38:31.560943
1125 12:38:31.563856 ----->DramcWriteLeveling(PI) begin...
1126 12:38:31.563946 ==
1127 12:38:31.567373 Dram Type= 6, Freq= 0, CH_0, rank 1
1128 12:38:31.570798 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1129 12:38:31.570893 ==
1130 12:38:31.573878 Write leveling (Byte 0): 29 => 29
1131 12:38:31.577400 Write leveling (Byte 1): 29 => 29
1132 12:38:31.580656 DramcWriteLeveling(PI) end<-----
1133 12:38:31.580764
1134 12:38:31.580831 ==
1135 12:38:31.583829 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 12:38:31.587154 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1137 12:38:31.587243 ==
1138 12:38:31.590255 [Gating] SW mode calibration
1139 12:38:31.597193 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1140 12:38:31.603789 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1141 12:38:31.607544 0 6 0 | B1->B0 | 3333 3030 | 0 1 | (0 0) (1 0)
1142 12:38:31.611847 0 6 4 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
1143 12:38:31.617464 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1144 12:38:31.620658 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1145 12:38:31.624116 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1146 12:38:31.632097 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 12:38:31.633789 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 12:38:31.637759 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 12:38:31.644430 0 7 0 | B1->B0 | 2626 3333 | 1 0 | (0 0) (0 0)
1150 12:38:31.647073 0 7 4 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
1151 12:38:31.650530 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1152 12:38:31.657441 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1153 12:38:31.660761 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1154 12:38:31.663969 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1155 12:38:31.670833 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1156 12:38:31.674293 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1157 12:38:31.676927 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1158 12:38:31.681132 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1159 12:38:31.687620 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1160 12:38:31.690578 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1161 12:38:31.693800 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1162 12:38:31.700410 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1163 12:38:31.703576 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1164 12:38:31.707569 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1165 12:38:31.714236 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1166 12:38:31.717382 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1167 12:38:31.720403 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1168 12:38:31.728112 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1169 12:38:31.730392 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1170 12:38:31.734622 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1171 12:38:31.740310 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1172 12:38:31.743812 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1173 12:38:31.747746 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1174 12:38:31.754043 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1175 12:38:31.754148 Total UI for P1: 0, mck2ui 16
1176 12:38:31.757619 best dqsien dly found for B0: ( 0, 9, 30)
1177 12:38:31.760431 Total UI for P1: 0, mck2ui 16
1178 12:38:31.764011 best dqsien dly found for B1: ( 0, 10, 0)
1179 12:38:31.767950 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1180 12:38:31.773866 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1181 12:38:31.773968
1182 12:38:31.777360 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1183 12:38:31.780406 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1184 12:38:31.784027 [Gating] SW calibration Done
1185 12:38:31.784116 ==
1186 12:38:31.786989 Dram Type= 6, Freq= 0, CH_0, rank 1
1187 12:38:31.790715 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1188 12:38:31.790806 ==
1189 12:38:31.794159 RX Vref Scan: 0
1190 12:38:31.794245
1191 12:38:31.794311 RX Vref 0 -> 0, step: 1
1192 12:38:31.794373
1193 12:38:31.797238 RX Delay -130 -> 252, step: 16
1194 12:38:31.801034 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1195 12:38:31.806957 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1196 12:38:31.810664 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1197 12:38:31.854456 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1198 12:38:31.854598 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1199 12:38:31.854903 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1200 12:38:31.855066 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1201 12:38:31.855297 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1202 12:38:31.855391 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1203 12:38:31.855452 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1204 12:38:31.855726 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1205 12:38:31.856547 iDelay=222, Bit 11, Center 61 (-50 ~ 173) 224
1206 12:38:31.856629 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1207 12:38:31.857306 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
1208 12:38:31.888962 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1209 12:38:31.889099 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
1210 12:38:31.889392 ==
1211 12:38:31.889543 Dram Type= 6, Freq= 0, CH_0, rank 1
1212 12:38:31.889847 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1213 12:38:31.889945 ==
1214 12:38:31.890004 DQS Delay:
1215 12:38:31.890061 DQS0 = 0, DQS1 = 0
1216 12:38:31.890313 DQM Delay:
1217 12:38:31.890373 DQM0 = 83, DQM1 = 70
1218 12:38:31.890430 DQ Delay:
1219 12:38:31.890840 DQ0 =77, DQ1 =85, DQ2 =85, DQ3 =77
1220 12:38:31.890936 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1221 12:38:31.891289 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1222 12:38:31.891371 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
1223 12:38:31.893785
1224 12:38:31.893880
1225 12:38:31.893972 ==
1226 12:38:31.894045 Dram Type= 6, Freq= 0, CH_0, rank 1
1227 12:38:31.897346 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1228 12:38:31.897429 ==
1229 12:38:31.897493
1230 12:38:31.897551
1231 12:38:31.900894 TX Vref Scan disable
1232 12:38:31.900976 == TX Byte 0 ==
1233 12:38:31.907610 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1234 12:38:31.910697 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1235 12:38:31.910786 == TX Byte 1 ==
1236 12:38:31.916957 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1237 12:38:31.920680 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1238 12:38:31.920829 ==
1239 12:38:31.923608 Dram Type= 6, Freq= 0, CH_0, rank 1
1240 12:38:31.927646 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1241 12:38:31.927739 ==
1242 12:38:31.940649 TX Vref=22, minBit 0, minWin=27, winSum=446
1243 12:38:31.944524 TX Vref=24, minBit 0, minWin=28, winSum=452
1244 12:38:31.947375 TX Vref=26, minBit 3, minWin=27, winSum=453
1245 12:38:31.950857 TX Vref=28, minBit 2, minWin=28, winSum=457
1246 12:38:31.954809 TX Vref=30, minBit 2, minWin=28, winSum=460
1247 12:38:31.960832 TX Vref=32, minBit 0, minWin=28, winSum=458
1248 12:38:31.964256 [TxChooseVref] Worse bit 2, Min win 28, Win sum 460, Final Vref 30
1249 12:38:31.964359
1250 12:38:31.967578 Final TX Range 1 Vref 30
1251 12:38:31.967667
1252 12:38:31.967731 ==
1253 12:38:31.970795 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 12:38:31.974102 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1255 12:38:31.974190 ==
1256 12:38:31.977522
1257 12:38:31.977607
1258 12:38:31.977673 TX Vref Scan disable
1259 12:38:31.980636 == TX Byte 0 ==
1260 12:38:31.983886 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1261 12:38:31.991111 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1262 12:38:31.991225 == TX Byte 1 ==
1263 12:38:31.994354 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1264 12:38:32.000363 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1265 12:38:32.000462
1266 12:38:32.000527 [DATLAT]
1267 12:38:32.000587 Freq=800, CH0 RK1
1268 12:38:32.000647
1269 12:38:32.004625 DATLAT Default: 0x9
1270 12:38:32.004718 0, 0xFFFF, sum = 0
1271 12:38:32.007614 1, 0xFFFF, sum = 0
1272 12:38:32.007699 2, 0xFFFF, sum = 0
1273 12:38:32.010504 3, 0xFFFF, sum = 0
1274 12:38:32.013884 4, 0xFFFF, sum = 0
1275 12:38:32.013972 5, 0xFFFF, sum = 0
1276 12:38:32.017657 6, 0xFFFF, sum = 0
1277 12:38:32.017750 7, 0xFFFF, sum = 0
1278 12:38:32.021123 8, 0x0, sum = 1
1279 12:38:32.021211 9, 0x0, sum = 2
1280 12:38:32.021278 10, 0x0, sum = 3
1281 12:38:32.024098 11, 0x0, sum = 4
1282 12:38:32.024184 best_step = 9
1283 12:38:32.024250
1284 12:38:32.024311 ==
1285 12:38:32.027649 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 12:38:32.034098 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1287 12:38:32.034206 ==
1288 12:38:32.034272 RX Vref Scan: 0
1289 12:38:32.034334
1290 12:38:32.037286 RX Vref 0 -> 0, step: 1
1291 12:38:32.037371
1292 12:38:32.041189 RX Delay -111 -> 252, step: 8
1293 12:38:32.043703 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1294 12:38:32.047358 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1295 12:38:32.053983 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1296 12:38:32.056870 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1297 12:38:32.060541 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1298 12:38:32.064947 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1299 12:38:32.066979 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1300 12:38:32.073705 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1301 12:38:32.076878 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1302 12:38:32.080172 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1303 12:38:32.083312 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1304 12:38:32.087457 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1305 12:38:32.093266 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1306 12:38:32.096979 iDelay=217, Bit 13, Center 80 (-31 ~ 192) 224
1307 12:38:32.100062 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1308 12:38:32.103416 iDelay=217, Bit 15, Center 80 (-31 ~ 192) 224
1309 12:38:32.103507 ==
1310 12:38:32.106574 Dram Type= 6, Freq= 0, CH_0, rank 1
1311 12:38:32.113536 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1312 12:38:32.113645 ==
1313 12:38:32.113713 DQS Delay:
1314 12:38:32.116764 DQS0 = 0, DQS1 = 0
1315 12:38:32.116886 DQM Delay:
1316 12:38:32.116991 DQM0 = 86, DQM1 = 74
1317 12:38:32.120549 DQ Delay:
1318 12:38:32.123610 DQ0 =80, DQ1 =88, DQ2 =84, DQ3 =84
1319 12:38:32.126670 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1320 12:38:32.130666 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =64
1321 12:38:32.133527 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
1322 12:38:32.133624
1323 12:38:32.133691
1324 12:38:32.140010 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b4b, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
1325 12:38:32.143343 CH0 RK1: MR19=606, MR18=4B4B
1326 12:38:32.150069 CH0_RK1: MR19=0x606, MR18=0x4B4B, DQSOSC=391, MR23=63, INC=96, DEC=64
1327 12:38:32.153924 [RxdqsGatingPostProcess] freq 800
1328 12:38:32.156979 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1329 12:38:32.161823 Pre-setting of DQS Precalculation
1330 12:38:32.167605 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1331 12:38:32.167719 ==
1332 12:38:32.170124 Dram Type= 6, Freq= 0, CH_1, rank 0
1333 12:38:32.173533 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1334 12:38:32.173620 ==
1335 12:38:32.180420 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1336 12:38:32.183993 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1337 12:38:32.193582 [CA 0] Center 36 (6~67) winsize 62
1338 12:38:32.196564 [CA 1] Center 36 (6~67) winsize 62
1339 12:38:32.200381 [CA 2] Center 34 (4~65) winsize 62
1340 12:38:32.203217 [CA 3] Center 34 (4~65) winsize 62
1341 12:38:32.207334 [CA 4] Center 33 (3~64) winsize 62
1342 12:38:32.210039 [CA 5] Center 33 (3~64) winsize 62
1343 12:38:32.210125
1344 12:38:32.213457 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1345 12:38:32.213577
1346 12:38:32.216732 [CATrainingPosCal] consider 1 rank data
1347 12:38:32.220248 u2DelayCellTimex100 = 270/100 ps
1348 12:38:32.223497 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1349 12:38:32.226959 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1350 12:38:32.233531 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1351 12:38:32.237011 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1352 12:38:32.239931 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1353 12:38:32.243241 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1354 12:38:32.243333
1355 12:38:32.246620 CA PerBit enable=1, Macro0, CA PI delay=33
1356 12:38:32.246705
1357 12:38:32.250135 [CBTSetCACLKResult] CA Dly = 33
1358 12:38:32.250222 CS Dly: 5 (0~36)
1359 12:38:32.250287 ==
1360 12:38:32.253515 Dram Type= 6, Freq= 0, CH_1, rank 1
1361 12:38:32.260203 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1362 12:38:32.260318 ==
1363 12:38:32.263705 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1364 12:38:32.270154 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1365 12:38:32.280378 [CA 0] Center 36 (6~67) winsize 62
1366 12:38:32.282611 [CA 1] Center 36 (5~68) winsize 64
1367 12:38:32.286564 [CA 2] Center 34 (4~65) winsize 62
1368 12:38:32.289338 [CA 3] Center 34 (4~65) winsize 62
1369 12:38:32.292901 [CA 4] Center 33 (3~64) winsize 62
1370 12:38:32.295994 [CA 5] Center 33 (3~64) winsize 62
1371 12:38:32.296082
1372 12:38:32.299120 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1373 12:38:32.299203
1374 12:38:32.302548 [CATrainingPosCal] consider 2 rank data
1375 12:38:32.306227 u2DelayCellTimex100 = 270/100 ps
1376 12:38:32.309077 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1377 12:38:32.312330 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1378 12:38:32.321438 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1379 12:38:32.322965 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1380 12:38:32.325897 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1381 12:38:32.329331 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1382 12:38:32.329421
1383 12:38:32.332202 CA PerBit enable=1, Macro0, CA PI delay=33
1384 12:38:32.332287
1385 12:38:32.336222 [CBTSetCACLKResult] CA Dly = 33
1386 12:38:32.336307 CS Dly: 5 (0~37)
1387 12:38:32.336373
1388 12:38:32.339798 ----->DramcWriteLeveling(PI) begin...
1389 12:38:32.342769 ==
1390 12:38:32.345772 Dram Type= 6, Freq= 0, CH_1, rank 0
1391 12:38:32.349156 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1392 12:38:32.349247 ==
1393 12:38:32.352213 Write leveling (Byte 0): 24 => 24
1394 12:38:32.355618 Write leveling (Byte 1): 24 => 24
1395 12:38:32.359267 DramcWriteLeveling(PI) end<-----
1396 12:38:32.359366
1397 12:38:32.359431 ==
1398 12:38:32.362520 Dram Type= 6, Freq= 0, CH_1, rank 0
1399 12:38:32.365980 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1400 12:38:32.366071 ==
1401 12:38:32.369078 [Gating] SW mode calibration
1402 12:38:32.375526 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1403 12:38:32.378878 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1404 12:38:32.386225 0 6 0 | B1->B0 | 2f2f 2525 | 1 0 | (1 0) (1 1)
1405 12:38:32.388928 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1406 12:38:32.392533 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1407 12:38:32.400830 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1408 12:38:32.402482 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1409 12:38:32.406072 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1410 12:38:32.412645 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1411 12:38:32.415889 0 6 28 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
1412 12:38:32.419697 0 7 0 | B1->B0 | 2f2f 3d3d | 1 1 | (0 0) (0 0)
1413 12:38:32.426389 0 7 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1414 12:38:32.429567 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1415 12:38:32.432304 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1416 12:38:32.439423 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1417 12:38:32.442419 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1418 12:38:32.445763 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1419 12:38:32.452134 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1420 12:38:32.455874 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1421 12:38:32.459000 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1422 12:38:32.465523 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1423 12:38:32.469172 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1424 12:38:32.472383 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1425 12:38:32.475655 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1426 12:38:32.482355 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1427 12:38:32.486012 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1428 12:38:32.489032 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1429 12:38:32.495616 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1430 12:38:32.499725 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1431 12:38:32.502100 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1432 12:38:32.508979 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1433 12:38:32.512146 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1434 12:38:32.515963 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1435 12:38:32.522695 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1436 12:38:32.525920 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1437 12:38:32.529295 Total UI for P1: 0, mck2ui 16
1438 12:38:32.532276 best dqsien dly found for B0: ( 0, 9, 28)
1439 12:38:32.535908 Total UI for P1: 0, mck2ui 16
1440 12:38:32.539142 best dqsien dly found for B1: ( 0, 9, 30)
1441 12:38:32.542278 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1442 12:38:32.545547 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1443 12:38:32.545634
1444 12:38:32.549284 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1445 12:38:32.552283 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1446 12:38:32.555419 [Gating] SW calibration Done
1447 12:38:32.555509 ==
1448 12:38:32.558973 Dram Type= 6, Freq= 0, CH_1, rank 0
1449 12:38:32.562063 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1450 12:38:32.566141 ==
1451 12:38:32.566233 RX Vref Scan: 0
1452 12:38:32.566300
1453 12:38:32.568849 RX Vref 0 -> 0, step: 1
1454 12:38:32.568934
1455 12:38:32.572568 RX Delay -130 -> 252, step: 16
1456 12:38:32.575912 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1457 12:38:32.578498 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1458 12:38:32.581947 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1459 12:38:32.585229 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1460 12:38:32.591847 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1461 12:38:32.595604 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1462 12:38:32.598825 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1463 12:38:32.601926 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1464 12:38:32.605949 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1465 12:38:32.612177 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1466 12:38:32.614998 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1467 12:38:32.618207 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1468 12:38:32.621575 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1469 12:38:32.628415 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1470 12:38:32.632913 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1471 12:38:32.636297 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1472 12:38:32.636389 ==
1473 12:38:32.638163 Dram Type= 6, Freq= 0, CH_1, rank 0
1474 12:38:32.641732 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1475 12:38:32.641820 ==
1476 12:38:32.644841 DQS Delay:
1477 12:38:32.644927 DQS0 = 0, DQS1 = 0
1478 12:38:32.648299 DQM Delay:
1479 12:38:32.648384 DQM0 = 81, DQM1 = 72
1480 12:38:32.648449 DQ Delay:
1481 12:38:32.651694 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1482 12:38:32.654906 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1483 12:38:32.658722 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =69
1484 12:38:32.661871 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =77
1485 12:38:32.661962
1486 12:38:32.662027
1487 12:38:32.662087 ==
1488 12:38:32.665556 Dram Type= 6, Freq= 0, CH_1, rank 0
1489 12:38:32.671948 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1490 12:38:32.672049 ==
1491 12:38:32.672116
1492 12:38:32.672177
1493 12:38:32.672235 TX Vref Scan disable
1494 12:38:32.675858 == TX Byte 0 ==
1495 12:38:32.678713 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1496 12:38:32.681883 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1497 12:38:32.685814 == TX Byte 1 ==
1498 12:38:32.689279 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1499 12:38:32.692356 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1500 12:38:32.695477 ==
1501 12:38:32.699476 Dram Type= 6, Freq= 0, CH_1, rank 0
1502 12:38:32.701848 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1503 12:38:32.701937 ==
1504 12:38:32.714876 TX Vref=22, minBit 0, minWin=27, winSum=446
1505 12:38:32.717853 TX Vref=24, minBit 3, minWin=27, winSum=450
1506 12:38:32.720755 TX Vref=26, minBit 0, minWin=28, winSum=454
1507 12:38:32.723979 TX Vref=28, minBit 1, minWin=28, winSum=456
1508 12:38:32.727210 TX Vref=30, minBit 0, minWin=28, winSum=458
1509 12:38:32.733965 TX Vref=32, minBit 0, minWin=28, winSum=454
1510 12:38:32.737396 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 30
1511 12:38:32.737494
1512 12:38:32.740768 Final TX Range 1 Vref 30
1513 12:38:32.740853
1514 12:38:32.740917 ==
1515 12:38:32.744171 Dram Type= 6, Freq= 0, CH_1, rank 0
1516 12:38:32.747965 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1517 12:38:32.748056 ==
1518 12:38:32.751621
1519 12:38:32.751707
1520 12:38:32.751771 TX Vref Scan disable
1521 12:38:32.754274 == TX Byte 0 ==
1522 12:38:32.757751 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1523 12:38:32.767541 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1524 12:38:32.767669 == TX Byte 1 ==
1525 12:38:32.767738 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1526 12:38:32.774426 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1527 12:38:32.774524
1528 12:38:32.774591 [DATLAT]
1529 12:38:32.774664 Freq=800, CH1 RK0
1530 12:38:32.774723
1531 12:38:32.777290 DATLAT Default: 0xa
1532 12:38:32.777370 0, 0xFFFF, sum = 0
1533 12:38:32.780698 1, 0xFFFF, sum = 0
1534 12:38:32.780820 2, 0xFFFF, sum = 0
1535 12:38:32.784323 3, 0xFFFF, sum = 0
1536 12:38:32.784407 4, 0xFFFF, sum = 0
1537 12:38:32.787550 5, 0xFFFF, sum = 0
1538 12:38:32.790885 6, 0xFFFF, sum = 0
1539 12:38:32.790972 7, 0xFFFF, sum = 0
1540 12:38:32.791036 8, 0x0, sum = 1
1541 12:38:32.794227 9, 0x0, sum = 2
1542 12:38:32.794311 10, 0x0, sum = 3
1543 12:38:32.797356 11, 0x0, sum = 4
1544 12:38:32.797439 best_step = 9
1545 12:38:32.797501
1546 12:38:32.797559 ==
1547 12:38:32.801297 Dram Type= 6, Freq= 0, CH_1, rank 0
1548 12:38:32.807465 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1549 12:38:32.807564 ==
1550 12:38:32.807631 RX Vref Scan: 1
1551 12:38:32.807690
1552 12:38:32.810627 Set Vref Range= 32 -> 127
1553 12:38:32.810710
1554 12:38:32.814311 RX Vref 32 -> 127, step: 1
1555 12:38:32.814399
1556 12:38:32.814463 RX Delay -111 -> 252, step: 8
1557 12:38:32.818298
1558 12:38:32.818390 Set Vref, RX VrefLevel [Byte0]: 32
1559 12:38:32.820587 [Byte1]: 32
1560 12:38:32.826140
1561 12:38:32.826232 Set Vref, RX VrefLevel [Byte0]: 33
1562 12:38:32.828339 [Byte1]: 33
1563 12:38:32.833257
1564 12:38:32.833347 Set Vref, RX VrefLevel [Byte0]: 34
1565 12:38:32.836525 [Byte1]: 34
1566 12:38:32.840379
1567 12:38:32.840465 Set Vref, RX VrefLevel [Byte0]: 35
1568 12:38:32.843787 [Byte1]: 35
1569 12:38:32.849140
1570 12:38:32.849235 Set Vref, RX VrefLevel [Byte0]: 36
1571 12:38:32.851955 [Byte1]: 36
1572 12:38:32.855642
1573 12:38:32.855731 Set Vref, RX VrefLevel [Byte0]: 37
1574 12:38:32.858808 [Byte1]: 37
1575 12:38:32.863795
1576 12:38:32.863891 Set Vref, RX VrefLevel [Byte0]: 38
1577 12:38:32.866940 [Byte1]: 38
1578 12:38:32.871081
1579 12:38:32.871172 Set Vref, RX VrefLevel [Byte0]: 39
1580 12:38:32.874543 [Byte1]: 39
1581 12:38:32.878753
1582 12:38:32.878842 Set Vref, RX VrefLevel [Byte0]: 40
1583 12:38:32.882274 [Byte1]: 40
1584 12:38:32.885998
1585 12:38:32.886089 Set Vref, RX VrefLevel [Byte0]: 41
1586 12:38:32.889500 [Byte1]: 41
1587 12:38:32.893953
1588 12:38:32.894043 Set Vref, RX VrefLevel [Byte0]: 42
1589 12:38:32.897512 [Byte1]: 42
1590 12:38:32.901512
1591 12:38:32.901600 Set Vref, RX VrefLevel [Byte0]: 43
1592 12:38:32.905641 [Byte1]: 43
1593 12:38:32.909346
1594 12:38:32.909435 Set Vref, RX VrefLevel [Byte0]: 44
1595 12:38:32.915598 [Byte1]: 44
1596 12:38:32.915697
1597 12:38:32.918964 Set Vref, RX VrefLevel [Byte0]: 45
1598 12:38:32.922887 [Byte1]: 45
1599 12:38:32.922979
1600 12:38:32.926110 Set Vref, RX VrefLevel [Byte0]: 46
1601 12:38:32.928654 [Byte1]: 46
1602 12:38:32.928782
1603 12:38:32.932089 Set Vref, RX VrefLevel [Byte0]: 47
1604 12:38:32.935432 [Byte1]: 47
1605 12:38:32.943049
1606 12:38:32.943153 Set Vref, RX VrefLevel [Byte0]: 48
1607 12:38:32.943221 [Byte1]: 48
1608 12:38:32.948211
1609 12:38:32.948297 Set Vref, RX VrefLevel [Byte0]: 49
1610 12:38:32.950860 [Byte1]: 49
1611 12:38:32.955395
1612 12:38:32.955483 Set Vref, RX VrefLevel [Byte0]: 50
1613 12:38:32.958125 [Byte1]: 50
1614 12:38:32.962374
1615 12:38:32.962479 Set Vref, RX VrefLevel [Byte0]: 51
1616 12:38:32.966265 [Byte1]: 51
1617 12:38:32.970621
1618 12:38:32.970712 Set Vref, RX VrefLevel [Byte0]: 52
1619 12:38:32.973609 [Byte1]: 52
1620 12:38:32.978321
1621 12:38:32.978408 Set Vref, RX VrefLevel [Byte0]: 53
1622 12:38:32.981365 [Byte1]: 53
1623 12:38:32.985856
1624 12:38:32.985944 Set Vref, RX VrefLevel [Byte0]: 54
1625 12:38:32.989037 [Byte1]: 54
1626 12:38:32.993261
1627 12:38:32.993347 Set Vref, RX VrefLevel [Byte0]: 55
1628 12:38:32.997158 [Byte1]: 55
1629 12:38:33.000901
1630 12:38:33.000988 Set Vref, RX VrefLevel [Byte0]: 56
1631 12:38:33.004294 [Byte1]: 56
1632 12:38:33.008643
1633 12:38:33.008761 Set Vref, RX VrefLevel [Byte0]: 57
1634 12:38:33.011945 [Byte1]: 57
1635 12:38:33.017049
1636 12:38:33.017151 Set Vref, RX VrefLevel [Byte0]: 58
1637 12:38:33.019862 [Byte1]: 58
1638 12:38:33.024117
1639 12:38:33.024206 Set Vref, RX VrefLevel [Byte0]: 59
1640 12:38:33.027772 [Byte1]: 59
1641 12:38:33.031846
1642 12:38:33.031933 Set Vref, RX VrefLevel [Byte0]: 60
1643 12:38:33.034954 [Byte1]: 60
1644 12:38:33.039044
1645 12:38:33.039130 Set Vref, RX VrefLevel [Byte0]: 61
1646 12:38:33.042485 [Byte1]: 61
1647 12:38:33.047259
1648 12:38:33.047348 Set Vref, RX VrefLevel [Byte0]: 62
1649 12:38:33.050408 [Byte1]: 62
1650 12:38:33.055202
1651 12:38:33.055294 Set Vref, RX VrefLevel [Byte0]: 63
1652 12:38:33.059018 [Byte1]: 63
1653 12:38:33.062522
1654 12:38:33.062627 Set Vref, RX VrefLevel [Byte0]: 64
1655 12:38:33.065141 [Byte1]: 64
1656 12:38:33.070555
1657 12:38:33.070648 Set Vref, RX VrefLevel [Byte0]: 65
1658 12:38:33.073227 [Byte1]: 65
1659 12:38:33.077457
1660 12:38:33.077546 Set Vref, RX VrefLevel [Byte0]: 66
1661 12:38:33.081266 [Byte1]: 66
1662 12:38:33.085015
1663 12:38:33.085104 Set Vref, RX VrefLevel [Byte0]: 67
1664 12:38:33.088048 [Byte1]: 67
1665 12:38:33.092659
1666 12:38:33.092774 Set Vref, RX VrefLevel [Byte0]: 68
1667 12:38:33.096334 [Byte1]: 68
1668 12:38:33.100524
1669 12:38:33.100630 Set Vref, RX VrefLevel [Byte0]: 69
1670 12:38:33.104461 [Byte1]: 69
1671 12:38:33.108388
1672 12:38:33.108477 Set Vref, RX VrefLevel [Byte0]: 70
1673 12:38:33.111431 [Byte1]: 70
1674 12:38:33.115842
1675 12:38:33.115936 Set Vref, RX VrefLevel [Byte0]: 71
1676 12:38:33.119073 [Byte1]: 71
1677 12:38:33.123072
1678 12:38:33.123164 Set Vref, RX VrefLevel [Byte0]: 72
1679 12:38:33.126974 [Byte1]: 72
1680 12:38:33.130979
1681 12:38:33.131071 Set Vref, RX VrefLevel [Byte0]: 73
1682 12:38:33.134763 [Byte1]: 73
1683 12:38:33.139790
1684 12:38:33.139886 Set Vref, RX VrefLevel [Byte0]: 74
1685 12:38:33.141604 [Byte1]: 74
1686 12:38:33.146174
1687 12:38:33.146261 Set Vref, RX VrefLevel [Byte0]: 75
1688 12:38:33.149450 [Byte1]: 75
1689 12:38:33.153796
1690 12:38:33.153884 Set Vref, RX VrefLevel [Byte0]: 76
1691 12:38:33.157037 [Byte1]: 76
1692 12:38:33.162133
1693 12:38:33.162230 Set Vref, RX VrefLevel [Byte0]: 77
1694 12:38:33.164956 [Byte1]: 77
1695 12:38:33.168983
1696 12:38:33.169072 Set Vref, RX VrefLevel [Byte0]: 78
1697 12:38:33.172517 [Byte1]: 78
1698 12:38:33.176763
1699 12:38:33.176850 Final RX Vref Byte 0 = 59 to rank0
1700 12:38:33.179889 Final RX Vref Byte 1 = 52 to rank0
1701 12:38:33.183301 Final RX Vref Byte 0 = 59 to rank1
1702 12:38:33.186632 Final RX Vref Byte 1 = 52 to rank1==
1703 12:38:33.190475 Dram Type= 6, Freq= 0, CH_1, rank 0
1704 12:38:33.193824 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1705 12:38:33.196795 ==
1706 12:38:33.196884 DQS Delay:
1707 12:38:33.196949 DQS0 = 0, DQS1 = 0
1708 12:38:33.200075 DQM Delay:
1709 12:38:33.200158 DQM0 = 82, DQM1 = 75
1710 12:38:33.203821 DQ Delay:
1711 12:38:33.206569 DQ0 =88, DQ1 =80, DQ2 =72, DQ3 =80
1712 12:38:33.206656 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1713 12:38:33.210880 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64
1714 12:38:33.214077 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1715 12:38:33.217169
1716 12:38:33.217262
1717 12:38:33.224399 [DQSOSCAuto] RK0, (LSB)MR18= 0x5050, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
1718 12:38:33.226824 CH1 RK0: MR19=606, MR18=5050
1719 12:38:33.233856 CH1_RK0: MR19=0x606, MR18=0x5050, DQSOSC=389, MR23=63, INC=97, DEC=65
1720 12:38:33.233963
1721 12:38:33.236779 ----->DramcWriteLeveling(PI) begin...
1722 12:38:33.236866 ==
1723 12:38:33.241119 Dram Type= 6, Freq= 0, CH_1, rank 1
1724 12:38:33.243438 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1725 12:38:33.243523 ==
1726 12:38:33.246888 Write leveling (Byte 0): 25 => 25
1727 12:38:33.250975 Write leveling (Byte 1): 25 => 25
1728 12:38:33.253524 DramcWriteLeveling(PI) end<-----
1729 12:38:33.253609
1730 12:38:33.253672 ==
1731 12:38:33.256783 Dram Type= 6, Freq= 0, CH_1, rank 1
1732 12:38:33.260104 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1733 12:38:33.260190 ==
1734 12:38:33.263516 [Gating] SW mode calibration
1735 12:38:33.269769 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1736 12:38:33.277937 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1737 12:38:33.279921 0 6 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
1738 12:38:33.284938 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1739 12:38:33.290445 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1740 12:38:33.293587 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1741 12:38:33.296680 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1742 12:38:33.303981 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1743 12:38:33.306872 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1744 12:38:33.310145 0 6 28 | B1->B0 | 2727 2f2f | 0 0 | (0 0) (0 0)
1745 12:38:33.316795 0 7 0 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
1746 12:38:33.319927 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1747 12:38:33.323573 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1748 12:38:33.329782 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1749 12:38:33.333651 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1750 12:38:33.336960 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1751 12:38:33.340141 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1752 12:38:33.346997 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1753 12:38:33.350036 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1754 12:38:33.353394 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1755 12:38:33.360979 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1756 12:38:33.363178 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1757 12:38:33.367216 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1758 12:38:33.373149 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1759 12:38:33.377137 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1760 12:38:33.380248 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1761 12:38:33.386639 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1762 12:38:33.390032 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1763 12:38:33.393687 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1764 12:38:33.400203 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1765 12:38:33.403673 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1766 12:38:33.407009 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1767 12:38:33.413967 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1768 12:38:33.417111 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1769 12:38:33.420327 Total UI for P1: 0, mck2ui 16
1770 12:38:33.423566 best dqsien dly found for B0: ( 0, 9, 26)
1771 12:38:33.427481 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1772 12:38:33.429946 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1773 12:38:33.433595 Total UI for P1: 0, mck2ui 16
1774 12:38:33.437006 best dqsien dly found for B1: ( 0, 9, 30)
1775 12:38:33.440400 best DQS0 dly(MCK, UI, PI) = (0, 9, 26)
1776 12:38:33.443325 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1777 12:38:33.446842
1778 12:38:33.451049 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 26)
1779 12:38:33.453577 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1780 12:38:33.457441 [Gating] SW calibration Done
1781 12:38:33.457530 ==
1782 12:38:33.460142 Dram Type= 6, Freq= 0, CH_1, rank 1
1783 12:38:33.463750 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1784 12:38:33.463841 ==
1785 12:38:33.463906 RX Vref Scan: 0
1786 12:38:33.467016
1787 12:38:33.467100 RX Vref 0 -> 0, step: 1
1788 12:38:33.467165
1789 12:38:33.470095 RX Delay -130 -> 252, step: 16
1790 12:38:33.473902 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1791 12:38:33.476677 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1792 12:38:33.484220 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1793 12:38:33.487071 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1794 12:38:33.490433 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1795 12:38:33.493513 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1796 12:38:33.499139 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1797 12:38:33.503760 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1798 12:38:33.507929 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1799 12:38:33.510897 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1800 12:38:33.513483 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1801 12:38:33.517065 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1802 12:38:33.523656 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1803 12:38:33.527244 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1804 12:38:33.530948 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1805 12:38:33.533872 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1806 12:38:33.533959 ==
1807 12:38:33.537438 Dram Type= 6, Freq= 0, CH_1, rank 1
1808 12:38:33.543760 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1809 12:38:33.543857 ==
1810 12:38:33.543924 DQS Delay:
1811 12:38:33.547010 DQS0 = 0, DQS1 = 0
1812 12:38:33.547095 DQM Delay:
1813 12:38:33.547161 DQM0 = 86, DQM1 = 72
1814 12:38:33.550010 DQ Delay:
1815 12:38:33.553287 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1816 12:38:33.556506 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1817 12:38:33.559910 DQ8 =53, DQ9 =53, DQ10 =69, DQ11 =61
1818 12:38:33.563358 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1819 12:38:33.563444
1820 12:38:33.563509
1821 12:38:33.563569 ==
1822 12:38:33.567118 Dram Type= 6, Freq= 0, CH_1, rank 1
1823 12:38:33.569978 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1824 12:38:33.570065 ==
1825 12:38:33.570129
1826 12:38:33.570189
1827 12:38:33.573094 TX Vref Scan disable
1828 12:38:33.573182 == TX Byte 0 ==
1829 12:38:33.579800 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1830 12:38:33.583504 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1831 12:38:33.583598 == TX Byte 1 ==
1832 12:38:33.589988 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1833 12:38:33.593138 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1834 12:38:33.593228 ==
1835 12:38:33.596591 Dram Type= 6, Freq= 0, CH_1, rank 1
1836 12:38:33.599705 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1837 12:38:33.599794 ==
1838 12:38:33.614190 TX Vref=22, minBit 0, minWin=27, winSum=449
1839 12:38:33.617446 TX Vref=24, minBit 0, minWin=27, winSum=450
1840 12:38:33.620869 TX Vref=26, minBit 0, minWin=28, winSum=454
1841 12:38:33.624054 TX Vref=28, minBit 0, minWin=28, winSum=456
1842 12:38:33.627345 TX Vref=30, minBit 9, minWin=27, winSum=455
1843 12:38:33.630967 TX Vref=32, minBit 9, minWin=27, winSum=454
1844 12:38:33.637381 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 28
1845 12:38:33.637486
1846 12:38:33.641495 Final TX Range 1 Vref 28
1847 12:38:33.641584
1848 12:38:33.641649 ==
1849 12:38:33.643829 Dram Type= 6, Freq= 0, CH_1, rank 1
1850 12:38:33.647309 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1851 12:38:33.647395 ==
1852 12:38:33.647460
1853 12:38:33.651004
1854 12:38:33.651089 TX Vref Scan disable
1855 12:38:33.654282 == TX Byte 0 ==
1856 12:38:33.656972 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1857 12:38:33.660901 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1858 12:38:33.664549 == TX Byte 1 ==
1859 12:38:33.667425 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1860 12:38:33.670531 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1861 12:38:33.673747
1862 12:38:33.673833 [DATLAT]
1863 12:38:33.673899 Freq=800, CH1 RK1
1864 12:38:33.673960
1865 12:38:33.677126 DATLAT Default: 0x9
1866 12:38:33.677209 0, 0xFFFF, sum = 0
1867 12:38:33.680604 1, 0xFFFF, sum = 0
1868 12:38:33.680689 2, 0xFFFF, sum = 0
1869 12:38:33.683743 3, 0xFFFF, sum = 0
1870 12:38:33.683828 4, 0xFFFF, sum = 0
1871 12:38:33.687442 5, 0xFFFF, sum = 0
1872 12:38:33.687529 6, 0xFFFF, sum = 0
1873 12:38:33.690711 7, 0xFFFF, sum = 0
1874 12:38:33.690796 8, 0x0, sum = 1
1875 12:38:33.693729 9, 0x0, sum = 2
1876 12:38:33.693814 10, 0x0, sum = 3
1877 12:38:33.697211 11, 0x0, sum = 4
1878 12:38:33.697298 best_step = 9
1879 12:38:33.697363
1880 12:38:33.697423 ==
1881 12:38:33.700517 Dram Type= 6, Freq= 0, CH_1, rank 1
1882 12:38:33.707497 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1883 12:38:33.707595 ==
1884 12:38:33.707662 RX Vref Scan: 0
1885 12:38:33.707722
1886 12:38:33.710807 RX Vref 0 -> 0, step: 1
1887 12:38:33.710890
1888 12:38:33.714488 RX Delay -111 -> 252, step: 8
1889 12:38:33.717049 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
1890 12:38:33.720539 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1891 12:38:33.727044 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1892 12:38:33.730587 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1893 12:38:33.734285 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1894 12:38:33.737139 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1895 12:38:33.741320 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1896 12:38:33.745282 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
1897 12:38:33.750402 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1898 12:38:33.753714 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1899 12:38:33.756939 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1900 12:38:33.760952 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1901 12:38:33.767114 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1902 12:38:33.771073 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1903 12:38:33.773884 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1904 12:38:33.778468 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1905 12:38:33.778554 ==
1906 12:38:33.780590 Dram Type= 6, Freq= 0, CH_1, rank 1
1907 12:38:33.785130 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1908 12:38:33.786982 ==
1909 12:38:33.787065 DQS Delay:
1910 12:38:33.787128 DQS0 = 0, DQS1 = 0
1911 12:38:33.790273 DQM Delay:
1912 12:38:33.790354 DQM0 = 84, DQM1 = 75
1913 12:38:33.794023 DQ Delay:
1914 12:38:33.796866 DQ0 =88, DQ1 =76, DQ2 =76, DQ3 =80
1915 12:38:33.796949 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
1916 12:38:33.800278 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1917 12:38:33.803910 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1918 12:38:33.807105
1919 12:38:33.807188
1920 12:38:33.813432 [DQSOSCAuto] RK1, (LSB)MR18= 0x4141, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1921 12:38:33.816796 CH1 RK1: MR19=606, MR18=4141
1922 12:38:33.823335 CH1_RK1: MR19=0x606, MR18=0x4141, DQSOSC=393, MR23=63, INC=95, DEC=63
1923 12:38:33.828061 [RxdqsGatingPostProcess] freq 800
1924 12:38:33.830490 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1925 12:38:33.833538 Pre-setting of DQS Precalculation
1926 12:38:33.840824 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1927 12:38:33.846682 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1928 12:38:33.853839 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1929 12:38:33.853954
1930 12:38:33.854023
1931 12:38:33.856841 [Calibration Summary] 1600 Mbps
1932 12:38:33.856924 CH 0, Rank 0
1933 12:38:33.860406 SW Impedance : PASS
1934 12:38:33.860495 DUTY Scan : NO K
1935 12:38:33.863857 ZQ Calibration : PASS
1936 12:38:33.867170 Jitter Meter : NO K
1937 12:38:33.867255 CBT Training : PASS
1938 12:38:33.870794 Write leveling : PASS
1939 12:38:33.873457 RX DQS gating : PASS
1940 12:38:33.873542 RX DQ/DQS(RDDQC) : PASS
1941 12:38:33.876963 TX DQ/DQS : PASS
1942 12:38:33.880098 RX DATLAT : PASS
1943 12:38:33.880182 RX DQ/DQS(Engine): PASS
1944 12:38:33.884229 TX OE : NO K
1945 12:38:33.884313 All Pass.
1946 12:38:33.884377
1947 12:38:33.887453 CH 0, Rank 1
1948 12:38:33.887535 SW Impedance : PASS
1949 12:38:33.890818 DUTY Scan : NO K
1950 12:38:33.893683 ZQ Calibration : PASS
1951 12:38:33.893766 Jitter Meter : NO K
1952 12:38:33.896810 CBT Training : PASS
1953 12:38:33.896893 Write leveling : PASS
1954 12:38:33.900268 RX DQS gating : PASS
1955 12:38:33.903616 RX DQ/DQS(RDDQC) : PASS
1956 12:38:33.903699 TX DQ/DQS : PASS
1957 12:38:33.906945 RX DATLAT : PASS
1958 12:38:33.909944 RX DQ/DQS(Engine): PASS
1959 12:38:33.910029 TX OE : NO K
1960 12:38:33.913328 All Pass.
1961 12:38:33.913413
1962 12:38:33.913476 CH 1, Rank 0
1963 12:38:33.917630 SW Impedance : PASS
1964 12:38:33.917719 DUTY Scan : NO K
1965 12:38:33.920119 ZQ Calibration : PASS
1966 12:38:33.923414 Jitter Meter : NO K
1967 12:38:33.923500 CBT Training : PASS
1968 12:38:33.926435 Write leveling : PASS
1969 12:38:33.930710 RX DQS gating : PASS
1970 12:38:33.930800 RX DQ/DQS(RDDQC) : PASS
1971 12:38:33.933912 TX DQ/DQS : PASS
1972 12:38:33.937032 RX DATLAT : PASS
1973 12:38:33.937116 RX DQ/DQS(Engine): PASS
1974 12:38:33.940271 TX OE : NO K
1975 12:38:33.940353 All Pass.
1976 12:38:33.940415
1977 12:38:33.943770 CH 1, Rank 1
1978 12:38:33.943851 SW Impedance : PASS
1979 12:38:33.947577 DUTY Scan : NO K
1980 12:38:33.947718 ZQ Calibration : PASS
1981 12:38:33.950909 Jitter Meter : NO K
1982 12:38:33.953823 CBT Training : PASS
1983 12:38:33.953923 Write leveling : PASS
1984 12:38:33.957260 RX DQS gating : PASS
1985 12:38:33.960508 RX DQ/DQS(RDDQC) : PASS
1986 12:38:33.960601 TX DQ/DQS : PASS
1987 12:38:33.963511 RX DATLAT : PASS
1988 12:38:33.966872 RX DQ/DQS(Engine): PASS
1989 12:38:33.966962 TX OE : NO K
1990 12:38:33.970289 All Pass.
1991 12:38:33.970376
1992 12:38:33.970461 DramC Write-DBI off
1993 12:38:33.973269 PER_BANK_REFRESH: Hybrid Mode
1994 12:38:33.973396 TX_TRACKING: ON
1995 12:38:33.977754 [GetDramInforAfterCalByMRR] Vendor 6.
1996 12:38:33.980841 [GetDramInforAfterCalByMRR] Revision 606.
1997 12:38:33.987471 [GetDramInforAfterCalByMRR] Revision 2 0.
1998 12:38:33.987565 MR0 0x3939
1999 12:38:33.987630 MR8 0x1111
2000 12:38:33.990570 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2001 12:38:33.990652
2002 12:38:33.994031 MR0 0x3939
2003 12:38:33.994114 MR8 0x1111
2004 12:38:33.997024 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2005 12:38:33.997112
2006 12:38:34.007400 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2007 12:38:34.010618 [FAST_K] Save calibration result to emmc
2008 12:38:34.013656 [FAST_K] Save calibration result to emmc
2009 12:38:34.017242 dram_init: config_dvfs: 1
2010 12:38:34.020107 dramc_set_vcore_voltage set vcore to 662500
2011 12:38:34.023652 Read voltage for 1200, 2
2012 12:38:34.023745 Vio18 = 0
2013 12:38:34.023809 Vcore = 662500
2014 12:38:34.026810 Vdram = 0
2015 12:38:34.026891 Vddq = 0
2016 12:38:34.026953 Vmddr = 0
2017 12:38:34.033692 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2018 12:38:34.036933 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2019 12:38:34.040118 MEM_TYPE=3, freq_sel=15
2020 12:38:34.044284 sv_algorithm_assistance_LP4_1600
2021 12:38:34.047058 ============ PULL DRAM RESETB DOWN ============
2022 12:38:34.050773 ========== PULL DRAM RESETB DOWN end =========
2023 12:38:34.056674 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2024 12:38:34.060615 ===================================
2025 12:38:34.060723 LPDDR4 DRAM CONFIGURATION
2026 12:38:34.064046 ===================================
2027 12:38:34.067280 EX_ROW_EN[0] = 0x0
2028 12:38:34.067370 EX_ROW_EN[1] = 0x0
2029 12:38:34.070553 LP4Y_EN = 0x0
2030 12:38:34.073555 WORK_FSP = 0x0
2031 12:38:34.073661 WL = 0x4
2032 12:38:34.077081 RL = 0x4
2033 12:38:34.077164 BL = 0x2
2034 12:38:34.080465 RPST = 0x0
2035 12:38:34.080549 RD_PRE = 0x0
2036 12:38:34.083561 WR_PRE = 0x1
2037 12:38:34.083630 WR_PST = 0x0
2038 12:38:34.088641 DBI_WR = 0x0
2039 12:38:34.088821 DBI_RD = 0x0
2040 12:38:34.089928 OTF = 0x1
2041 12:38:34.093964 ===================================
2042 12:38:34.097619 ===================================
2043 12:38:34.097707 ANA top config
2044 12:38:34.100310 ===================================
2045 12:38:34.103566 DLL_ASYNC_EN = 0
2046 12:38:34.107182 ALL_SLAVE_EN = 0
2047 12:38:34.107266 NEW_RANK_MODE = 1
2048 12:38:34.110432 DLL_IDLE_MODE = 1
2049 12:38:34.113577 LP45_APHY_COMB_EN = 1
2050 12:38:34.117493 TX_ODT_DIS = 1
2051 12:38:34.117581 NEW_8X_MODE = 1
2052 12:38:34.120894 ===================================
2053 12:38:34.124313 ===================================
2054 12:38:34.127109 data_rate = 2400
2055 12:38:34.130182 CKR = 1
2056 12:38:34.134195 DQ_P2S_RATIO = 8
2057 12:38:34.137267 ===================================
2058 12:38:34.140105 CA_P2S_RATIO = 8
2059 12:38:34.143615 DQ_CA_OPEN = 0
2060 12:38:34.143706 DQ_SEMI_OPEN = 0
2061 12:38:34.147160 CA_SEMI_OPEN = 0
2062 12:38:34.150155 CA_FULL_RATE = 0
2063 12:38:34.153371 DQ_CKDIV4_EN = 0
2064 12:38:34.156950 CA_CKDIV4_EN = 0
2065 12:38:34.160502 CA_PREDIV_EN = 0
2066 12:38:34.160598 PH8_DLY = 17
2067 12:38:34.163663 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2068 12:38:34.166957 DQ_AAMCK_DIV = 4
2069 12:38:34.170535 CA_AAMCK_DIV = 4
2070 12:38:34.173473 CA_ADMCK_DIV = 4
2071 12:38:34.177263 DQ_TRACK_CA_EN = 0
2072 12:38:34.177356 CA_PICK = 1200
2073 12:38:34.180400 CA_MCKIO = 1200
2074 12:38:34.183833 MCKIO_SEMI = 0
2075 12:38:34.187233 PLL_FREQ = 2366
2076 12:38:34.190588 DQ_UI_PI_RATIO = 32
2077 12:38:34.193798 CA_UI_PI_RATIO = 0
2078 12:38:34.196980 ===================================
2079 12:38:34.200626 ===================================
2080 12:38:34.200727 memory_type:LPDDR4
2081 12:38:34.203651 GP_NUM : 10
2082 12:38:34.206973 SRAM_EN : 1
2083 12:38:34.207061 MD32_EN : 0
2084 12:38:34.210366 ===================================
2085 12:38:34.213725 [ANA_INIT] >>>>>>>>>>>>>>
2086 12:38:34.216958 <<<<<< [CONFIGURE PHASE]: ANA_TX
2087 12:38:34.220502 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2088 12:38:34.223749 ===================================
2089 12:38:34.227232 data_rate = 2400,PCW = 0X5b00
2090 12:38:34.230222 ===================================
2091 12:38:34.234255 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2092 12:38:34.236925 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2093 12:38:34.244200 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2094 12:38:34.247776 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2095 12:38:34.250091 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2096 12:38:34.253686 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2097 12:38:34.256946 [ANA_INIT] flow start
2098 12:38:34.260546 [ANA_INIT] PLL >>>>>>>>
2099 12:38:34.260645 [ANA_INIT] PLL <<<<<<<<
2100 12:38:34.264555 [ANA_INIT] MIDPI >>>>>>>>
2101 12:38:34.267721 [ANA_INIT] MIDPI <<<<<<<<
2102 12:38:34.270316 [ANA_INIT] DLL >>>>>>>>
2103 12:38:34.270408 [ANA_INIT] DLL <<<<<<<<
2104 12:38:34.273495 [ANA_INIT] flow end
2105 12:38:34.277327 ============ LP4 DIFF to SE enter ============
2106 12:38:34.280156 ============ LP4 DIFF to SE exit ============
2107 12:38:34.283744 [ANA_INIT] <<<<<<<<<<<<<
2108 12:38:34.287281 [Flow] Enable top DCM control >>>>>
2109 12:38:34.290467 [Flow] Enable top DCM control <<<<<
2110 12:38:34.293698 Enable DLL master slave shuffle
2111 12:38:34.298005 ==============================================================
2112 12:38:34.300287 Gating Mode config
2113 12:38:34.307265 ==============================================================
2114 12:38:34.307370 Config description:
2115 12:38:34.317339 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2116 12:38:34.323726 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2117 12:38:34.330607 SELPH_MODE 0: By rank 1: By Phase
2118 12:38:34.333808 ==============================================================
2119 12:38:34.337002 GAT_TRACK_EN = 1
2120 12:38:34.340186 RX_GATING_MODE = 2
2121 12:38:34.343426 RX_GATING_TRACK_MODE = 2
2122 12:38:34.347741 SELPH_MODE = 1
2123 12:38:34.350399 PICG_EARLY_EN = 1
2124 12:38:34.354541 VALID_LAT_VALUE = 1
2125 12:38:34.357239 ==============================================================
2126 12:38:34.360198 Enter into Gating configuration >>>>
2127 12:38:34.363783 Exit from Gating configuration <<<<
2128 12:38:34.367838 Enter into DVFS_PRE_config >>>>>
2129 12:38:34.380561 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2130 12:38:34.383473 Exit from DVFS_PRE_config <<<<<
2131 12:38:34.383573 Enter into PICG configuration >>>>
2132 12:38:34.386844 Exit from PICG configuration <<<<
2133 12:38:34.390023 [RX_INPUT] configuration >>>>>
2134 12:38:34.394154 [RX_INPUT] configuration <<<<<
2135 12:38:34.400004 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2136 12:38:34.403352 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2137 12:38:34.410054 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2138 12:38:34.416813 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2139 12:38:34.423487 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2140 12:38:34.430117 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2141 12:38:34.434188 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2142 12:38:34.437012 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2143 12:38:34.439880 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2144 12:38:34.447155 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2145 12:38:34.449921 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2146 12:38:34.453553 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2147 12:38:34.456665 ===================================
2148 12:38:34.460213 LPDDR4 DRAM CONFIGURATION
2149 12:38:34.463339 ===================================
2150 12:38:34.463425 EX_ROW_EN[0] = 0x0
2151 12:38:34.466666 EX_ROW_EN[1] = 0x0
2152 12:38:34.469946 LP4Y_EN = 0x0
2153 12:38:34.470030 WORK_FSP = 0x0
2154 12:38:34.473436 WL = 0x4
2155 12:38:34.473517 RL = 0x4
2156 12:38:34.477312 BL = 0x2
2157 12:38:34.477395 RPST = 0x0
2158 12:38:34.480342 RD_PRE = 0x0
2159 12:38:34.480423 WR_PRE = 0x1
2160 12:38:34.483560 WR_PST = 0x0
2161 12:38:34.483641 DBI_WR = 0x0
2162 12:38:34.486994 DBI_RD = 0x0
2163 12:38:34.487077 OTF = 0x1
2164 12:38:34.489838 ===================================
2165 12:38:34.493397 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2166 12:38:34.499931 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2167 12:38:34.503642 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2168 12:38:34.506978 ===================================
2169 12:38:34.510308 LPDDR4 DRAM CONFIGURATION
2170 12:38:34.513962 ===================================
2171 12:38:34.514054 EX_ROW_EN[0] = 0x10
2172 12:38:34.517096 EX_ROW_EN[1] = 0x0
2173 12:38:34.517179 LP4Y_EN = 0x0
2174 12:38:34.519960 WORK_FSP = 0x0
2175 12:38:34.520044 WL = 0x4
2176 12:38:34.523920 RL = 0x4
2177 12:38:34.526593 BL = 0x2
2178 12:38:34.526692 RPST = 0x0
2179 12:38:34.529796 RD_PRE = 0x0
2180 12:38:34.529877 WR_PRE = 0x1
2181 12:38:34.533358 WR_PST = 0x0
2182 12:38:34.533456 DBI_WR = 0x0
2183 12:38:34.537173 DBI_RD = 0x0
2184 12:38:34.537268 OTF = 0x1
2185 12:38:34.540174 ===================================
2186 12:38:34.546834 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2187 12:38:34.546937 ==
2188 12:38:34.549799 Dram Type= 6, Freq= 0, CH_0, rank 0
2189 12:38:34.553135 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2190 12:38:34.553226 ==
2191 12:38:34.557139 [Duty_Offset_Calibration]
2192 12:38:34.559863 B0:0 B1:2 CA:1
2193 12:38:34.559953
2194 12:38:34.562972 [DutyScan_Calibration_Flow] k_type=0
2195 12:38:34.570981
2196 12:38:34.571102 ==CLK 0==
2197 12:38:34.574556 Final CLK duty delay cell = 0
2198 12:38:34.577702 [0] MAX Duty = 5093%(X100), DQS PI = 12
2199 12:38:34.581116 [0] MIN Duty = 4938%(X100), DQS PI = 52
2200 12:38:34.581207 [0] AVG Duty = 5015%(X100)
2201 12:38:34.584540
2202 12:38:34.587792 CH0 CLK Duty spec in!! Max-Min= 155%
2203 12:38:34.591468 [DutyScan_Calibration_Flow] ====Done====
2204 12:38:34.591559
2205 12:38:34.594376 [DutyScan_Calibration_Flow] k_type=1
2206 12:38:34.610533
2207 12:38:34.610680 ==DQS 0 ==
2208 12:38:34.613842 Final DQS duty delay cell = 0
2209 12:38:34.617272 [0] MAX Duty = 5125%(X100), DQS PI = 30
2210 12:38:34.620374 [0] MIN Duty = 5031%(X100), DQS PI = 4
2211 12:38:34.620472 [0] AVG Duty = 5078%(X100)
2212 12:38:34.624058
2213 12:38:34.624147 ==DQS 1 ==
2214 12:38:34.627099 Final DQS duty delay cell = 0
2215 12:38:34.630258 [0] MAX Duty = 5031%(X100), DQS PI = 8
2216 12:38:34.633717 [0] MIN Duty = 4906%(X100), DQS PI = 16
2217 12:38:34.637246 [0] AVG Duty = 4968%(X100)
2218 12:38:34.637338
2219 12:38:34.640021 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2220 12:38:34.640105
2221 12:38:34.643387 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2222 12:38:34.647140 [DutyScan_Calibration_Flow] ====Done====
2223 12:38:34.647256
2224 12:38:34.650656 [DutyScan_Calibration_Flow] k_type=3
2225 12:38:34.667251
2226 12:38:34.667409 ==DQM 0 ==
2227 12:38:34.670794 Final DQM duty delay cell = 0
2228 12:38:34.674280 [0] MAX Duty = 5156%(X100), DQS PI = 22
2229 12:38:34.677934 [0] MIN Duty = 5000%(X100), DQS PI = 40
2230 12:38:34.680679 [0] AVG Duty = 5078%(X100)
2231 12:38:34.680807
2232 12:38:34.680872 ==DQM 1 ==
2233 12:38:34.684671 Final DQM duty delay cell = 4
2234 12:38:34.687374 [4] MAX Duty = 5187%(X100), DQS PI = 52
2235 12:38:34.691171 [4] MIN Duty = 5000%(X100), DQS PI = 18
2236 12:38:34.693788 [4] AVG Duty = 5093%(X100)
2237 12:38:34.693876
2238 12:38:34.697477 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2239 12:38:34.697565
2240 12:38:34.701356 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2241 12:38:34.703980 [DutyScan_Calibration_Flow] ====Done====
2242 12:38:34.704098
2243 12:38:34.708343 [DutyScan_Calibration_Flow] k_type=2
2244 12:38:34.722228
2245 12:38:34.722370 ==DQ 0 ==
2246 12:38:34.726512 Final DQ duty delay cell = -4
2247 12:38:34.729591 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2248 12:38:34.732681 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2249 12:38:34.736948 [-4] AVG Duty = 4937%(X100)
2250 12:38:34.737042
2251 12:38:34.737107 ==DQ 1 ==
2252 12:38:34.739334 Final DQ duty delay cell = -4
2253 12:38:34.742972 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2254 12:38:34.745611 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2255 12:38:34.749146 [-4] AVG Duty = 4984%(X100)
2256 12:38:34.749238
2257 12:38:34.752459 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2258 12:38:34.752545
2259 12:38:34.755810 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2260 12:38:34.759091 [DutyScan_Calibration_Flow] ====Done====
2261 12:38:34.759179 ==
2262 12:38:34.763038 Dram Type= 6, Freq= 0, CH_1, rank 0
2263 12:38:34.766374 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2264 12:38:34.766468 ==
2265 12:38:34.768898 [Duty_Offset_Calibration]
2266 12:38:34.768981 B0:0 B1:4 CA:-5
2267 12:38:34.769045
2268 12:38:34.772361 [DutyScan_Calibration_Flow] k_type=0
2269 12:38:34.783730
2270 12:38:34.783851 ==CLK 0==
2271 12:38:34.787094 Final CLK duty delay cell = 0
2272 12:38:34.789948 [0] MAX Duty = 5094%(X100), DQS PI = 24
2273 12:38:34.792634 [0] MIN Duty = 4875%(X100), DQS PI = 48
2274 12:38:34.792782 [0] AVG Duty = 4984%(X100)
2275 12:38:34.796205
2276 12:38:34.799582 CH1 CLK Duty spec in!! Max-Min= 219%
2277 12:38:34.802855 [DutyScan_Calibration_Flow] ====Done====
2278 12:38:34.802949
2279 12:38:34.806656 [DutyScan_Calibration_Flow] k_type=1
2280 12:38:34.821573
2281 12:38:34.821724 ==DQS 0 ==
2282 12:38:34.824738 Final DQS duty delay cell = 0
2283 12:38:34.829204 [0] MAX Duty = 5125%(X100), DQS PI = 16
2284 12:38:34.832054 [0] MIN Duty = 4875%(X100), DQS PI = 40
2285 12:38:34.832147 [0] AVG Duty = 5000%(X100)
2286 12:38:34.835215
2287 12:38:34.835302 ==DQS 1 ==
2288 12:38:34.838129 Final DQS duty delay cell = -4
2289 12:38:34.841930 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2290 12:38:34.845033 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2291 12:38:34.848471 [-4] AVG Duty = 4953%(X100)
2292 12:38:34.848593
2293 12:38:34.851718 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2294 12:38:34.851808
2295 12:38:34.855061 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2296 12:38:34.858306 [DutyScan_Calibration_Flow] ====Done====
2297 12:38:34.858394
2298 12:38:34.861337 [DutyScan_Calibration_Flow] k_type=3
2299 12:38:34.876253
2300 12:38:34.876398 ==DQM 0 ==
2301 12:38:34.879459 Final DQM duty delay cell = -4
2302 12:38:34.883067 [-4] MAX Duty = 5094%(X100), DQS PI = 30
2303 12:38:34.886625 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2304 12:38:34.889996 [-4] AVG Duty = 4969%(X100)
2305 12:38:34.890084
2306 12:38:34.890148 ==DQM 1 ==
2307 12:38:34.893053 Final DQM duty delay cell = -4
2308 12:38:34.896799 [-4] MAX Duty = 5062%(X100), DQS PI = 2
2309 12:38:34.899625 [-4] MIN Duty = 4907%(X100), DQS PI = 60
2310 12:38:34.902620 [-4] AVG Duty = 4984%(X100)
2311 12:38:34.902708
2312 12:38:34.905930 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2313 12:38:34.906017
2314 12:38:34.909704 CH1 DQM 1 Duty spec in!! Max-Min= 155%
2315 12:38:34.913286 [DutyScan_Calibration_Flow] ====Done====
2316 12:38:34.913378
2317 12:38:34.916345 [DutyScan_Calibration_Flow] k_type=2
2318 12:38:34.933322
2319 12:38:34.933478 ==DQ 0 ==
2320 12:38:34.936609 Final DQ duty delay cell = 0
2321 12:38:34.939971 [0] MAX Duty = 5062%(X100), DQS PI = 0
2322 12:38:34.943334 [0] MIN Duty = 4938%(X100), DQS PI = 44
2323 12:38:34.943429 [0] AVG Duty = 5000%(X100)
2324 12:38:34.946712
2325 12:38:34.946794 ==DQ 1 ==
2326 12:38:34.950151 Final DQ duty delay cell = 0
2327 12:38:34.953968 [0] MAX Duty = 5000%(X100), DQS PI = 8
2328 12:38:34.957190 [0] MIN Duty = 4875%(X100), DQS PI = 16
2329 12:38:34.957270 [0] AVG Duty = 4937%(X100)
2330 12:38:34.957340
2331 12:38:34.960470 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2332 12:38:34.963223
2333 12:38:34.968204 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2334 12:38:34.970694 [DutyScan_Calibration_Flow] ====Done====
2335 12:38:34.973140 nWR fixed to 30
2336 12:38:34.973230 [ModeRegInit_LP4] CH0 RK0
2337 12:38:34.976425 [ModeRegInit_LP4] CH0 RK1
2338 12:38:34.980632 [ModeRegInit_LP4] CH1 RK0
2339 12:38:34.980750 [ModeRegInit_LP4] CH1 RK1
2340 12:38:34.983546 match AC timing 6
2341 12:38:34.986635 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2342 12:38:34.990197 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2343 12:38:34.997008 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2344 12:38:35.000242 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2345 12:38:35.007349 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2346 12:38:35.007478 ==
2347 12:38:35.010113 Dram Type= 6, Freq= 0, CH_0, rank 0
2348 12:38:35.014363 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2349 12:38:35.014455 ==
2350 12:38:35.020611 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2351 12:38:35.023229 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2352 12:38:35.033049 [CA 0] Center 39 (9~70) winsize 62
2353 12:38:35.036495 [CA 1] Center 39 (8~70) winsize 63
2354 12:38:35.040052 [CA 2] Center 36 (5~67) winsize 63
2355 12:38:35.043393 [CA 3] Center 35 (4~66) winsize 63
2356 12:38:35.046586 [CA 4] Center 34 (3~65) winsize 63
2357 12:38:35.049722 [CA 5] Center 33 (3~64) winsize 62
2358 12:38:35.049803
2359 12:38:35.053325 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2360 12:38:35.053409
2361 12:38:35.056362 [CATrainingPosCal] consider 1 rank data
2362 12:38:35.059586 u2DelayCellTimex100 = 270/100 ps
2363 12:38:35.062952 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2364 12:38:35.066245 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2365 12:38:35.073134 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2366 12:38:35.076351 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2367 12:38:35.080186 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2368 12:38:35.082994 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2369 12:38:35.083075
2370 12:38:35.086857 CA PerBit enable=1, Macro0, CA PI delay=33
2371 12:38:35.086936
2372 12:38:35.091383 [CBTSetCACLKResult] CA Dly = 33
2373 12:38:35.091478 CS Dly: 7 (0~38)
2374 12:38:35.091547 ==
2375 12:38:35.093183 Dram Type= 6, Freq= 0, CH_0, rank 1
2376 12:38:35.099953 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2377 12:38:35.100054 ==
2378 12:38:35.103206 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2379 12:38:35.110031 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2380 12:38:35.119883 [CA 0] Center 39 (8~70) winsize 63
2381 12:38:35.121656 [CA 1] Center 38 (8~69) winsize 62
2382 12:38:35.125269 [CA 2] Center 36 (5~67) winsize 63
2383 12:38:35.128684 [CA 3] Center 35 (4~66) winsize 63
2384 12:38:35.132436 [CA 4] Center 33 (3~64) winsize 62
2385 12:38:35.135607 [CA 5] Center 34 (3~65) winsize 63
2386 12:38:35.135697
2387 12:38:35.139068 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2388 12:38:35.139152
2389 12:38:35.142456 [CATrainingPosCal] consider 2 rank data
2390 12:38:35.145141 u2DelayCellTimex100 = 270/100 ps
2391 12:38:35.148655 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2392 12:38:35.152359 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2393 12:38:35.158207 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2394 12:38:35.161815 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2395 12:38:35.165319 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2396 12:38:35.168530 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2397 12:38:35.168619
2398 12:38:35.171859 CA PerBit enable=1, Macro0, CA PI delay=33
2399 12:38:35.171949
2400 12:38:35.175034 [CBTSetCACLKResult] CA Dly = 33
2401 12:38:35.175119 CS Dly: 7 (0~39)
2402 12:38:35.175184
2403 12:38:35.178901 ----->DramcWriteLeveling(PI) begin...
2404 12:38:35.182250 ==
2405 12:38:35.185159 Dram Type= 6, Freq= 0, CH_0, rank 0
2406 12:38:35.188550 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2407 12:38:35.188636 ==
2408 12:38:35.191346 Write leveling (Byte 0): 27 => 27
2409 12:38:35.195974 Write leveling (Byte 1): 25 => 25
2410 12:38:35.198227 DramcWriteLeveling(PI) end<-----
2411 12:38:35.198314
2412 12:38:35.198378 ==
2413 12:38:35.202858 Dram Type= 6, Freq= 0, CH_0, rank 0
2414 12:38:35.205069 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2415 12:38:35.205155 ==
2416 12:38:35.208407 [Gating] SW mode calibration
2417 12:38:35.214894 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2418 12:38:35.221838 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2419 12:38:35.224584 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2420 12:38:35.227942 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2421 12:38:35.235570 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2422 12:38:35.237811 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2423 12:38:35.241191 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2424 12:38:35.248196 0 11 20 | B1->B0 | 2c2c 2a2a | 1 0 | (1 0) (1 0)
2425 12:38:35.251640 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2426 12:38:35.255242 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2427 12:38:35.258862 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2428 12:38:35.264685 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2429 12:38:35.268127 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2430 12:38:35.271799 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2431 12:38:35.278126 0 12 16 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
2432 12:38:35.281319 0 12 20 | B1->B0 | 3737 3e3e | 0 0 | (0 0) (1 1)
2433 12:38:35.284747 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2434 12:38:35.291414 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2435 12:38:35.294454 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2436 12:38:35.297900 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2437 12:38:35.304636 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2438 12:38:35.307819 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2439 12:38:35.311522 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2440 12:38:35.317975 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2441 12:38:35.321360 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2442 12:38:35.324534 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2443 12:38:35.331304 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2444 12:38:35.334482 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2445 12:38:35.338036 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2446 12:38:35.344659 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2447 12:38:35.347764 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2448 12:38:35.351587 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2449 12:38:35.357862 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2450 12:38:35.361298 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2451 12:38:35.364739 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2452 12:38:35.368154 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2453 12:38:35.374577 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2454 12:38:35.378036 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2455 12:38:35.381541 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2456 12:38:35.388404 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2457 12:38:35.391740 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2458 12:38:35.394898 Total UI for P1: 0, mck2ui 16
2459 12:38:35.398129 best dqsien dly found for B0: ( 0, 15, 18)
2460 12:38:35.401174 Total UI for P1: 0, mck2ui 16
2461 12:38:35.404379 best dqsien dly found for B1: ( 0, 15, 18)
2462 12:38:35.408974 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2463 12:38:35.411096 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2464 12:38:35.411185
2465 12:38:35.414879 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2466 12:38:35.418165 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2467 12:38:35.421119 [Gating] SW calibration Done
2468 12:38:35.421213 ==
2469 12:38:35.424902 Dram Type= 6, Freq= 0, CH_0, rank 0
2470 12:38:35.432002 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2471 12:38:35.432107 ==
2472 12:38:35.432176 RX Vref Scan: 0
2473 12:38:35.432238
2474 12:38:35.434959 RX Vref 0 -> 0, step: 1
2475 12:38:35.435044
2476 12:38:35.438016 RX Delay -40 -> 252, step: 8
2477 12:38:35.440970 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2478 12:38:35.444317 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2479 12:38:35.448031 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2480 12:38:35.451388 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2481 12:38:35.458126 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2482 12:38:35.461110 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2483 12:38:35.464479 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2484 12:38:35.467831 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2485 12:38:35.471027 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2486 12:38:35.477671 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2487 12:38:35.480867 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2488 12:38:35.484467 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2489 12:38:35.487690 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2490 12:38:35.490925 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2491 12:38:35.497778 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2492 12:38:35.501765 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2493 12:38:35.501868 ==
2494 12:38:35.504296 Dram Type= 6, Freq= 0, CH_0, rank 0
2495 12:38:35.507488 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2496 12:38:35.507576 ==
2497 12:38:35.510797 DQS Delay:
2498 12:38:35.510884 DQS0 = 0, DQS1 = 0
2499 12:38:35.510968 DQM Delay:
2500 12:38:35.514433 DQM0 = 115, DQM1 = 105
2501 12:38:35.514519 DQ Delay:
2502 12:38:35.518123 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2503 12:38:35.521101 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2504 12:38:35.524503 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =99
2505 12:38:35.530885 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2506 12:38:35.530999
2507 12:38:35.531089
2508 12:38:35.531170 ==
2509 12:38:35.534335 Dram Type= 6, Freq= 0, CH_0, rank 0
2510 12:38:35.537940 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2511 12:38:35.538032 ==
2512 12:38:35.538118
2513 12:38:35.538198
2514 12:38:35.540952 TX Vref Scan disable
2515 12:38:35.541062 == TX Byte 0 ==
2516 12:38:35.548167 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2517 12:38:35.551075 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2518 12:38:35.551168 == TX Byte 1 ==
2519 12:38:35.558698 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2520 12:38:35.561071 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2521 12:38:35.561169 ==
2522 12:38:35.564203 Dram Type= 6, Freq= 0, CH_0, rank 0
2523 12:38:35.568468 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2524 12:38:35.568561 ==
2525 12:38:35.579984 TX Vref=22, minBit 8, minWin=25, winSum=413
2526 12:38:35.583059 TX Vref=24, minBit 8, minWin=25, winSum=420
2527 12:38:35.586692 TX Vref=26, minBit 8, minWin=26, winSum=429
2528 12:38:35.590183 TX Vref=28, minBit 10, minWin=25, winSum=432
2529 12:38:35.593141 TX Vref=30, minBit 11, minWin=26, winSum=437
2530 12:38:35.600476 TX Vref=32, minBit 12, minWin=26, winSum=437
2531 12:38:35.603621 [TxChooseVref] Worse bit 11, Min win 26, Win sum 437, Final Vref 30
2532 12:38:35.603728
2533 12:38:35.606771 Final TX Range 1 Vref 30
2534 12:38:35.606857
2535 12:38:35.606921 ==
2536 12:38:35.609895 Dram Type= 6, Freq= 0, CH_0, rank 0
2537 12:38:35.613681 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2538 12:38:35.617097 ==
2539 12:38:35.617187
2540 12:38:35.617252
2541 12:38:35.617312 TX Vref Scan disable
2542 12:38:35.620789 == TX Byte 0 ==
2543 12:38:35.623396 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2544 12:38:35.627047 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2545 12:38:35.629731 == TX Byte 1 ==
2546 12:38:35.633885 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2547 12:38:35.639900 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2548 12:38:35.639999
2549 12:38:35.640066 [DATLAT]
2550 12:38:35.640127 Freq=1200, CH0 RK0
2551 12:38:35.640186
2552 12:38:35.643265 DATLAT Default: 0xd
2553 12:38:35.643350 0, 0xFFFF, sum = 0
2554 12:38:35.646422 1, 0xFFFF, sum = 0
2555 12:38:35.646511 2, 0xFFFF, sum = 0
2556 12:38:35.650215 3, 0xFFFF, sum = 0
2557 12:38:35.654527 4, 0xFFFF, sum = 0
2558 12:38:35.654619 5, 0xFFFF, sum = 0
2559 12:38:35.657040 6, 0xFFFF, sum = 0
2560 12:38:35.657124 7, 0xFFFF, sum = 0
2561 12:38:35.660360 8, 0xFFFF, sum = 0
2562 12:38:35.660456 9, 0xFFFF, sum = 0
2563 12:38:35.663792 10, 0xFFFF, sum = 0
2564 12:38:35.663890 11, 0x0, sum = 1
2565 12:38:35.666459 12, 0x0, sum = 2
2566 12:38:35.666549 13, 0x0, sum = 3
2567 12:38:35.666616 14, 0x0, sum = 4
2568 12:38:35.669967 best_step = 12
2569 12:38:35.670058
2570 12:38:35.670125 ==
2571 12:38:35.673189 Dram Type= 6, Freq= 0, CH_0, rank 0
2572 12:38:35.676825 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2573 12:38:35.676922 ==
2574 12:38:35.680068 RX Vref Scan: 1
2575 12:38:35.680155
2576 12:38:35.683948 Set Vref Range= 32 -> 127
2577 12:38:35.684036
2578 12:38:35.684101 RX Vref 32 -> 127, step: 1
2579 12:38:35.684162
2580 12:38:35.686671 RX Delay -21 -> 252, step: 4
2581 12:38:35.686760
2582 12:38:35.690080 Set Vref, RX VrefLevel [Byte0]: 32
2583 12:38:35.693378 [Byte1]: 32
2584 12:38:35.696573
2585 12:38:35.696659 Set Vref, RX VrefLevel [Byte0]: 33
2586 12:38:35.700623 [Byte1]: 33
2587 12:38:35.704654
2588 12:38:35.704766 Set Vref, RX VrefLevel [Byte0]: 34
2589 12:38:35.708080 [Byte1]: 34
2590 12:38:35.712597
2591 12:38:35.712691 Set Vref, RX VrefLevel [Byte0]: 35
2592 12:38:35.716026 [Byte1]: 35
2593 12:38:35.720652
2594 12:38:35.725464 Set Vref, RX VrefLevel [Byte0]: 36
2595 12:38:35.727208 [Byte1]: 36
2596 12:38:35.727298
2597 12:38:35.731057 Set Vref, RX VrefLevel [Byte0]: 37
2598 12:38:35.733716 [Byte1]: 37
2599 12:38:35.733804
2600 12:38:35.736602 Set Vref, RX VrefLevel [Byte0]: 38
2601 12:38:35.740303 [Byte1]: 38
2602 12:38:35.744445
2603 12:38:35.744535 Set Vref, RX VrefLevel [Byte0]: 39
2604 12:38:35.747500 [Byte1]: 39
2605 12:38:35.752290
2606 12:38:35.752384 Set Vref, RX VrefLevel [Byte0]: 40
2607 12:38:35.755445 [Byte1]: 40
2608 12:38:35.760069
2609 12:38:35.760169 Set Vref, RX VrefLevel [Byte0]: 41
2610 12:38:35.764339 [Byte1]: 41
2611 12:38:35.768577
2612 12:38:35.768700 Set Vref, RX VrefLevel [Byte0]: 42
2613 12:38:35.772257 [Byte1]: 42
2614 12:38:35.775989
2615 12:38:35.776083 Set Vref, RX VrefLevel [Byte0]: 43
2616 12:38:35.779306 [Byte1]: 43
2617 12:38:35.783617
2618 12:38:35.783709 Set Vref, RX VrefLevel [Byte0]: 44
2619 12:38:35.787395 [Byte1]: 44
2620 12:38:35.792098
2621 12:38:35.792191 Set Vref, RX VrefLevel [Byte0]: 45
2622 12:38:35.795145 [Byte1]: 45
2623 12:38:35.799743
2624 12:38:35.799836 Set Vref, RX VrefLevel [Byte0]: 46
2625 12:38:35.802904 [Byte1]: 46
2626 12:38:35.807556
2627 12:38:35.807647 Set Vref, RX VrefLevel [Byte0]: 47
2628 12:38:35.811353 [Byte1]: 47
2629 12:38:35.816214
2630 12:38:35.816310 Set Vref, RX VrefLevel [Byte0]: 48
2631 12:38:35.819303 [Byte1]: 48
2632 12:38:35.824019
2633 12:38:35.824120 Set Vref, RX VrefLevel [Byte0]: 49
2634 12:38:35.827132 [Byte1]: 49
2635 12:38:35.832108
2636 12:38:35.832200 Set Vref, RX VrefLevel [Byte0]: 50
2637 12:38:35.835018 [Byte1]: 50
2638 12:38:35.839556
2639 12:38:35.839648 Set Vref, RX VrefLevel [Byte0]: 51
2640 12:38:35.843226 [Byte1]: 51
2641 12:38:35.847720
2642 12:38:35.847814 Set Vref, RX VrefLevel [Byte0]: 52
2643 12:38:35.850488 [Byte1]: 52
2644 12:38:35.855165
2645 12:38:35.855259 Set Vref, RX VrefLevel [Byte0]: 53
2646 12:38:35.858697 [Byte1]: 53
2647 12:38:35.863695
2648 12:38:35.863800 Set Vref, RX VrefLevel [Byte0]: 54
2649 12:38:35.866753 [Byte1]: 54
2650 12:38:35.870898
2651 12:38:35.870987 Set Vref, RX VrefLevel [Byte0]: 55
2652 12:38:35.874752 [Byte1]: 55
2653 12:38:35.878966
2654 12:38:35.879058 Set Vref, RX VrefLevel [Byte0]: 56
2655 12:38:35.883043 [Byte1]: 56
2656 12:38:35.887034
2657 12:38:35.887124 Set Vref, RX VrefLevel [Byte0]: 57
2658 12:38:35.890387 [Byte1]: 57
2659 12:38:35.894744
2660 12:38:35.894834 Set Vref, RX VrefLevel [Byte0]: 58
2661 12:38:35.898185 [Byte1]: 58
2662 12:38:35.903206
2663 12:38:35.903298 Set Vref, RX VrefLevel [Byte0]: 59
2664 12:38:35.906824 [Byte1]: 59
2665 12:38:35.911403
2666 12:38:35.911509 Set Vref, RX VrefLevel [Byte0]: 60
2667 12:38:35.914356 [Byte1]: 60
2668 12:38:35.918498
2669 12:38:35.921735 Set Vref, RX VrefLevel [Byte0]: 61
2670 12:38:35.925005 [Byte1]: 61
2671 12:38:35.925103
2672 12:38:35.928109 Set Vref, RX VrefLevel [Byte0]: 62
2673 12:38:35.931678 [Byte1]: 62
2674 12:38:35.931766
2675 12:38:35.935274 Set Vref, RX VrefLevel [Byte0]: 63
2676 12:38:35.938767 [Byte1]: 63
2677 12:38:35.942413
2678 12:38:35.942504 Set Vref, RX VrefLevel [Byte0]: 64
2679 12:38:35.946035 [Byte1]: 64
2680 12:38:35.950194
2681 12:38:35.950284 Set Vref, RX VrefLevel [Byte0]: 65
2682 12:38:35.953664 [Byte1]: 65
2683 12:38:35.958399
2684 12:38:35.958494 Final RX Vref Byte 0 = 49 to rank0
2685 12:38:35.961258 Final RX Vref Byte 1 = 49 to rank0
2686 12:38:35.964903 Final RX Vref Byte 0 = 49 to rank1
2687 12:38:35.968394 Final RX Vref Byte 1 = 49 to rank1==
2688 12:38:35.971182 Dram Type= 6, Freq= 0, CH_0, rank 0
2689 12:38:35.978627 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2690 12:38:35.978738 ==
2691 12:38:35.978808 DQS Delay:
2692 12:38:35.978869 DQS0 = 0, DQS1 = 0
2693 12:38:35.981486 DQM Delay:
2694 12:38:35.981570 DQM0 = 115, DQM1 = 105
2695 12:38:35.984768 DQ Delay:
2696 12:38:35.987910 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =110
2697 12:38:35.991909 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =122
2698 12:38:35.994509 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =96
2699 12:38:35.998253 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2700 12:38:35.998341
2701 12:38:35.998406
2702 12:38:36.004760 [DQSOSCAuto] RK0, (LSB)MR18= 0x808, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
2703 12:38:36.008797 CH0 RK0: MR19=404, MR18=808
2704 12:38:36.014757 CH0_RK0: MR19=0x404, MR18=0x808, DQSOSC=406, MR23=63, INC=39, DEC=26
2705 12:38:36.014861
2706 12:38:36.017997 ----->DramcWriteLeveling(PI) begin...
2707 12:38:36.018085 ==
2708 12:38:36.021420 Dram Type= 6, Freq= 0, CH_0, rank 1
2709 12:38:36.024875 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2710 12:38:36.024973 ==
2711 12:38:36.027849 Write leveling (Byte 0): 27 => 27
2712 12:38:36.031447 Write leveling (Byte 1): 23 => 23
2713 12:38:36.034806 DramcWriteLeveling(PI) end<-----
2714 12:38:36.034895
2715 12:38:36.034983 ==
2716 12:38:36.038358 Dram Type= 6, Freq= 0, CH_0, rank 1
2717 12:38:36.045055 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2718 12:38:36.045157 ==
2719 12:38:36.045225 [Gating] SW mode calibration
2720 12:38:36.054594 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2721 12:38:36.058617 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2722 12:38:36.061005 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2723 12:38:36.068435 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2724 12:38:36.071740 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2725 12:38:36.074377 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2726 12:38:36.081004 0 11 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2727 12:38:36.084507 0 11 20 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
2728 12:38:36.088079 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2729 12:38:36.094331 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2730 12:38:36.098217 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2731 12:38:36.101537 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2732 12:38:36.108364 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2733 12:38:36.111280 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2734 12:38:36.114394 0 12 16 | B1->B0 | 2727 3939 | 0 0 | (0 0) (0 0)
2735 12:38:36.121443 0 12 20 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
2736 12:38:36.124850 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2737 12:38:36.127787 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2738 12:38:36.135365 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2739 12:38:36.137907 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2740 12:38:36.141395 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2741 12:38:36.145542 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2742 12:38:36.152575 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2743 12:38:36.155017 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2744 12:38:36.158061 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2745 12:38:36.164319 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2746 12:38:36.168095 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2747 12:38:36.170870 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2748 12:38:36.177985 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2749 12:38:36.181247 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2750 12:38:36.184683 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2751 12:38:36.191316 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2752 12:38:36.195092 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2753 12:38:36.197906 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2754 12:38:36.204222 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2755 12:38:36.207772 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2756 12:38:36.210848 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2757 12:38:36.217464 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2758 12:38:36.221437 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2759 12:38:36.224067 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2760 12:38:36.228222 Total UI for P1: 0, mck2ui 16
2761 12:38:36.231603 best dqsien dly found for B0: ( 0, 15, 16)
2762 12:38:36.237597 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2763 12:38:36.237681 Total UI for P1: 0, mck2ui 16
2764 12:38:36.240701 best dqsien dly found for B1: ( 0, 15, 18)
2765 12:38:36.248246 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2766 12:38:36.251104 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2767 12:38:36.251187
2768 12:38:36.254324 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2769 12:38:36.257535 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2770 12:38:36.261491 [Gating] SW calibration Done
2771 12:38:36.261636 ==
2772 12:38:36.264290 Dram Type= 6, Freq= 0, CH_0, rank 1
2773 12:38:36.267501 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2774 12:38:36.267579 ==
2775 12:38:36.270992 RX Vref Scan: 0
2776 12:38:36.271101
2777 12:38:36.271200 RX Vref 0 -> 0, step: 1
2778 12:38:36.271282
2779 12:38:36.274785 RX Delay -40 -> 252, step: 8
2780 12:38:36.277579 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2781 12:38:36.284677 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160
2782 12:38:36.287924 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2783 12:38:36.290948 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2784 12:38:36.294642 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2785 12:38:36.297776 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2786 12:38:36.301144 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2787 12:38:36.308305 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2788 12:38:36.311057 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2789 12:38:36.314787 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2790 12:38:36.317633 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2791 12:38:36.321345 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2792 12:38:36.327796 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2793 12:38:36.331055 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2794 12:38:36.333866 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2795 12:38:36.337624 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2796 12:38:36.337708 ==
2797 12:38:36.341027 Dram Type= 6, Freq= 0, CH_0, rank 1
2798 12:38:36.347517 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2799 12:38:36.347603 ==
2800 12:38:36.347689 DQS Delay:
2801 12:38:36.350802 DQS0 = 0, DQS1 = 0
2802 12:38:36.350890 DQM Delay:
2803 12:38:36.350975 DQM0 = 116, DQM1 = 107
2804 12:38:36.353934 DQ Delay:
2805 12:38:36.357287 DQ0 =111, DQ1 =119, DQ2 =115, DQ3 =111
2806 12:38:36.361088 DQ4 =119, DQ5 =107, DQ6 =123, DQ7 =123
2807 12:38:36.364296 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2808 12:38:36.367838 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =115
2809 12:38:36.367915
2810 12:38:36.367979
2811 12:38:36.368076 ==
2812 12:38:36.370951 Dram Type= 6, Freq= 0, CH_0, rank 1
2813 12:38:36.374631 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2814 12:38:36.374709 ==
2815 12:38:36.378288
2816 12:38:36.378360
2817 12:38:36.378420 TX Vref Scan disable
2818 12:38:36.381130 == TX Byte 0 ==
2819 12:38:36.384371 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2820 12:38:36.387567 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2821 12:38:36.390694 == TX Byte 1 ==
2822 12:38:36.395046 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
2823 12:38:36.397860 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
2824 12:38:36.397951 ==
2825 12:38:36.400857 Dram Type= 6, Freq= 0, CH_0, rank 1
2826 12:38:36.407245 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2827 12:38:36.407337 ==
2828 12:38:36.418379 TX Vref=22, minBit 8, minWin=25, winSum=419
2829 12:38:36.421390 TX Vref=24, minBit 8, minWin=25, winSum=425
2830 12:38:36.424559 TX Vref=26, minBit 8, minWin=25, winSum=426
2831 12:38:36.429114 TX Vref=28, minBit 8, minWin=25, winSum=428
2832 12:38:36.431743 TX Vref=30, minBit 10, minWin=25, winSum=433
2833 12:38:36.438342 TX Vref=32, minBit 8, minWin=25, winSum=433
2834 12:38:36.441526 [TxChooseVref] Worse bit 10, Min win 25, Win sum 433, Final Vref 30
2835 12:38:36.441623
2836 12:38:36.444890 Final TX Range 1 Vref 30
2837 12:38:36.444960
2838 12:38:36.445023 ==
2839 12:38:36.448666 Dram Type= 6, Freq= 0, CH_0, rank 1
2840 12:38:36.451560 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2841 12:38:36.451660 ==
2842 12:38:36.454755
2843 12:38:36.454824
2844 12:38:36.454883 TX Vref Scan disable
2845 12:38:36.458454 == TX Byte 0 ==
2846 12:38:36.461720 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2847 12:38:36.464812 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2848 12:38:36.468018 == TX Byte 1 ==
2849 12:38:36.471384 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
2850 12:38:36.474694 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
2851 12:38:36.478264
2852 12:38:36.478337 [DATLAT]
2853 12:38:36.478400 Freq=1200, CH0 RK1
2854 12:38:36.478459
2855 12:38:36.481570 DATLAT Default: 0xc
2856 12:38:36.481653 0, 0xFFFF, sum = 0
2857 12:38:36.484626 1, 0xFFFF, sum = 0
2858 12:38:36.484756 2, 0xFFFF, sum = 0
2859 12:38:36.488004 3, 0xFFFF, sum = 0
2860 12:38:36.491658 4, 0xFFFF, sum = 0
2861 12:38:36.491762 5, 0xFFFF, sum = 0
2862 12:38:36.494827 6, 0xFFFF, sum = 0
2863 12:38:36.494931 7, 0xFFFF, sum = 0
2864 12:38:36.498290 8, 0xFFFF, sum = 0
2865 12:38:36.498388 9, 0xFFFF, sum = 0
2866 12:38:36.501657 10, 0xFFFF, sum = 0
2867 12:38:36.501756 11, 0x0, sum = 1
2868 12:38:36.505418 12, 0x0, sum = 2
2869 12:38:36.505517 13, 0x0, sum = 3
2870 12:38:36.507804 14, 0x0, sum = 4
2871 12:38:36.507902 best_step = 12
2872 12:38:36.507992
2873 12:38:36.508080 ==
2874 12:38:36.511841 Dram Type= 6, Freq= 0, CH_0, rank 1
2875 12:38:36.515344 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2876 12:38:36.515442 ==
2877 12:38:36.517761 RX Vref Scan: 0
2878 12:38:36.517837
2879 12:38:36.521762 RX Vref 0 -> 0, step: 1
2880 12:38:36.521862
2881 12:38:36.521952 RX Delay -21 -> 252, step: 4
2882 12:38:36.528992 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2883 12:38:36.532358 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2884 12:38:36.535085 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2885 12:38:36.538341 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2886 12:38:36.542060 iDelay=199, Bit 4, Center 116 (43 ~ 190) 148
2887 12:38:36.549468 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2888 12:38:36.552151 iDelay=199, Bit 6, Center 124 (55 ~ 194) 140
2889 12:38:36.554962 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2890 12:38:36.558351 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2891 12:38:36.561930 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2892 12:38:36.568524 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2893 12:38:36.572095 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2894 12:38:36.575051 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
2895 12:38:36.578904 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2896 12:38:36.582945 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
2897 12:38:36.588942 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2898 12:38:36.589052 ==
2899 12:38:36.591935 Dram Type= 6, Freq= 0, CH_0, rank 1
2900 12:38:36.595029 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2901 12:38:36.595131 ==
2902 12:38:36.595221 DQS Delay:
2903 12:38:36.598457 DQS0 = 0, DQS1 = 0
2904 12:38:36.598530 DQM Delay:
2905 12:38:36.601821 DQM0 = 115, DQM1 = 105
2906 12:38:36.601920 DQ Delay:
2907 12:38:36.604826 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2908 12:38:36.608937 DQ4 =116, DQ5 =108, DQ6 =124, DQ7 =124
2909 12:38:36.611937 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2910 12:38:36.615541 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
2911 12:38:36.615644
2912 12:38:36.615736
2913 12:38:36.625307 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2914 12:38:36.628914 CH0 RK1: MR19=404, MR18=E0E
2915 12:38:36.632183 CH0_RK1: MR19=0x404, MR18=0xE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
2916 12:38:36.635720 [RxdqsGatingPostProcess] freq 1200
2917 12:38:36.642026 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2918 12:38:36.645230 Pre-setting of DQS Precalculation
2919 12:38:36.648463 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2920 12:38:36.648553 ==
2921 12:38:36.652313 Dram Type= 6, Freq= 0, CH_1, rank 0
2922 12:38:36.658817 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2923 12:38:36.658899 ==
2924 12:38:36.662162 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2925 12:38:36.668432 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2926 12:38:36.677123 [CA 0] Center 37 (7~68) winsize 62
2927 12:38:36.681887 [CA 1] Center 37 (7~68) winsize 62
2928 12:38:36.683518 [CA 2] Center 34 (4~65) winsize 62
2929 12:38:36.687236 [CA 3] Center 33 (3~64) winsize 62
2930 12:38:36.691172 [CA 4] Center 32 (2~63) winsize 62
2931 12:38:36.694077 [CA 5] Center 32 (2~63) winsize 62
2932 12:38:36.694154
2933 12:38:36.697044 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2934 12:38:36.697114
2935 12:38:36.700919 [CATrainingPosCal] consider 1 rank data
2936 12:38:36.703983 u2DelayCellTimex100 = 270/100 ps
2937 12:38:36.706863 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2938 12:38:36.710192 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2939 12:38:36.717446 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2940 12:38:36.720853 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2941 12:38:36.724106 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2942 12:38:36.727395 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2943 12:38:36.727477
2944 12:38:36.730288 CA PerBit enable=1, Macro0, CA PI delay=32
2945 12:38:36.730370
2946 12:38:36.734091 [CBTSetCACLKResult] CA Dly = 32
2947 12:38:36.734173 CS Dly: 5 (0~36)
2948 12:38:36.734241 ==
2949 12:38:36.737317 Dram Type= 6, Freq= 0, CH_1, rank 1
2950 12:38:36.743687 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2951 12:38:36.743790 ==
2952 12:38:36.746671 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2953 12:38:36.753305 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2954 12:38:36.761974 [CA 0] Center 37 (6~68) winsize 63
2955 12:38:36.765855 [CA 1] Center 37 (6~68) winsize 63
2956 12:38:36.769491 [CA 2] Center 33 (3~64) winsize 62
2957 12:38:36.772825 [CA 3] Center 33 (3~64) winsize 62
2958 12:38:36.775727 [CA 4] Center 32 (2~63) winsize 62
2959 12:38:36.779017 [CA 5] Center 32 (1~63) winsize 63
2960 12:38:36.779119
2961 12:38:36.781963 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2962 12:38:36.782060
2963 12:38:36.786031 [CATrainingPosCal] consider 2 rank data
2964 12:38:36.789578 u2DelayCellTimex100 = 270/100 ps
2965 12:38:36.792787 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2966 12:38:36.796404 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2967 12:38:36.803614 CA2 delay=34 (4~64),Diff = 2 PI (9 cell)
2968 12:38:36.805552 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2969 12:38:36.809383 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2970 12:38:36.812700 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2971 12:38:36.812824
2972 12:38:36.815900 CA PerBit enable=1, Macro0, CA PI delay=32
2973 12:38:36.815982
2974 12:38:36.819034 [CBTSetCACLKResult] CA Dly = 32
2975 12:38:36.819117 CS Dly: 6 (0~38)
2976 12:38:36.819182
2977 12:38:36.822614 ----->DramcWriteLeveling(PI) begin...
2978 12:38:36.826122 ==
2979 12:38:36.826209 Dram Type= 6, Freq= 0, CH_1, rank 0
2980 12:38:36.832347 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2981 12:38:36.832433 ==
2982 12:38:36.836042 Write leveling (Byte 0): 21 => 21
2983 12:38:36.839165 Write leveling (Byte 1): 24 => 24
2984 12:38:36.842733 DramcWriteLeveling(PI) end<-----
2985 12:38:36.842816
2986 12:38:36.842880 ==
2987 12:38:36.845913 Dram Type= 6, Freq= 0, CH_1, rank 0
2988 12:38:36.849504 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2989 12:38:36.849587 ==
2990 12:38:36.852263 [Gating] SW mode calibration
2991 12:38:36.858890 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2992 12:38:36.862656 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2993 12:38:36.869148 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2994 12:38:36.871974 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2995 12:38:36.875602 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2996 12:38:36.882451 0 11 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
2997 12:38:36.885948 0 11 16 | B1->B0 | 3434 2b2b | 0 0 | (0 0) (0 0)
2998 12:38:36.889007 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2999 12:38:36.895590 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3000 12:38:36.899231 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3001 12:38:36.902177 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3002 12:38:36.909071 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3003 12:38:36.912066 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3004 12:38:36.915445 0 12 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3005 12:38:36.922083 0 12 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
3006 12:38:36.925748 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3007 12:38:36.929035 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3008 12:38:36.935534 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3009 12:38:36.939201 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3010 12:38:36.942083 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3011 12:38:36.948784 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3012 12:38:36.953131 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3013 12:38:36.955669 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3014 12:38:36.962232 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3015 12:38:36.965348 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3016 12:38:36.969334 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3017 12:38:36.973895 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3018 12:38:36.978943 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3019 12:38:36.982703 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3020 12:38:36.985903 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3021 12:38:36.992086 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3022 12:38:36.995432 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3023 12:38:36.998934 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3024 12:38:37.005947 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3025 12:38:37.008982 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3026 12:38:37.012336 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3027 12:38:37.018668 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3028 12:38:37.022425 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3029 12:38:37.025688 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3030 12:38:37.032466 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3031 12:38:37.032630 Total UI for P1: 0, mck2ui 16
3032 12:38:37.039400 best dqsien dly found for B0: ( 0, 15, 14)
3033 12:38:37.041921 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3034 12:38:37.045781 Total UI for P1: 0, mck2ui 16
3035 12:38:37.048400 best dqsien dly found for B1: ( 0, 15, 18)
3036 12:38:37.051656 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3037 12:38:37.055321 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3038 12:38:37.055417
3039 12:38:37.058386 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3040 12:38:37.062259 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3041 12:38:37.065870 [Gating] SW calibration Done
3042 12:38:37.065976 ==
3043 12:38:37.068501 Dram Type= 6, Freq= 0, CH_1, rank 0
3044 12:38:37.072047 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3045 12:38:37.075279 ==
3046 12:38:37.075374 RX Vref Scan: 0
3047 12:38:37.075439
3048 12:38:37.079241 RX Vref 0 -> 0, step: 1
3049 12:38:37.079333
3050 12:38:37.081752 RX Delay -40 -> 252, step: 8
3051 12:38:37.084936 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3052 12:38:37.088613 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3053 12:38:37.091987 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3054 12:38:37.095866 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3055 12:38:37.101767 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3056 12:38:37.105829 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3057 12:38:37.108638 iDelay=208, Bit 6, Center 119 (40 ~ 199) 160
3058 12:38:37.112228 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3059 12:38:37.114766 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3060 12:38:37.121561 iDelay=208, Bit 9, Center 103 (32 ~ 175) 144
3061 12:38:37.125390 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3062 12:38:37.128696 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3063 12:38:37.131455 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3064 12:38:37.134619 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3065 12:38:37.141548 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3066 12:38:37.145335 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3067 12:38:37.145419 ==
3068 12:38:37.147860 Dram Type= 6, Freq= 0, CH_1, rank 0
3069 12:38:37.152516 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3070 12:38:37.152603 ==
3071 12:38:37.155942 DQS Delay:
3072 12:38:37.156025 DQS0 = 0, DQS1 = 0
3073 12:38:37.156090 DQM Delay:
3074 12:38:37.158118 DQM0 = 115, DQM1 = 109
3075 12:38:37.158201 DQ Delay:
3076 12:38:37.161464 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3077 12:38:37.164942 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3078 12:38:37.167999 DQ8 =87, DQ9 =103, DQ10 =111, DQ11 =103
3079 12:38:37.174803 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =119
3080 12:38:37.174893
3081 12:38:37.174958
3082 12:38:37.175018 ==
3083 12:38:37.179119 Dram Type= 6, Freq= 0, CH_1, rank 0
3084 12:38:37.181274 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3085 12:38:37.181358 ==
3086 12:38:37.181422
3087 12:38:37.181482
3088 12:38:37.185188 TX Vref Scan disable
3089 12:38:37.185271 == TX Byte 0 ==
3090 12:38:37.191255 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3091 12:38:37.194779 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3092 12:38:37.194866 == TX Byte 1 ==
3093 12:38:37.201143 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3094 12:38:37.204498 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3095 12:38:37.204583 ==
3096 12:38:37.207836 Dram Type= 6, Freq= 0, CH_1, rank 0
3097 12:38:37.211044 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3098 12:38:37.211129 ==
3099 12:38:37.224449 TX Vref=22, minBit 9, minWin=25, winSum=413
3100 12:38:37.227708 TX Vref=24, minBit 3, minWin=25, winSum=418
3101 12:38:37.230524 TX Vref=26, minBit 15, minWin=25, winSum=422
3102 12:38:37.233689 TX Vref=28, minBit 15, minWin=25, winSum=427
3103 12:38:37.237642 TX Vref=30, minBit 8, minWin=26, winSum=429
3104 12:38:37.240809 TX Vref=32, minBit 8, minWin=26, winSum=425
3105 12:38:37.247778 [TxChooseVref] Worse bit 8, Min win 26, Win sum 429, Final Vref 30
3106 12:38:37.247870
3107 12:38:37.251228 Final TX Range 1 Vref 30
3108 12:38:37.251314
3109 12:38:37.251378 ==
3110 12:38:37.254606 Dram Type= 6, Freq= 0, CH_1, rank 0
3111 12:38:37.257339 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3112 12:38:37.257423 ==
3113 12:38:37.257489
3114 12:38:37.260430
3115 12:38:37.260512 TX Vref Scan disable
3116 12:38:37.264370 == TX Byte 0 ==
3117 12:38:37.267402 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3118 12:38:37.271154 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3119 12:38:37.274688 == TX Byte 1 ==
3120 12:38:37.277661 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3121 12:38:37.280813 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3122 12:38:37.280897
3123 12:38:37.284407 [DATLAT]
3124 12:38:37.284490 Freq=1200, CH1 RK0
3125 12:38:37.284556
3126 12:38:37.287215 DATLAT Default: 0xd
3127 12:38:37.287298 0, 0xFFFF, sum = 0
3128 12:38:37.290973 1, 0xFFFF, sum = 0
3129 12:38:37.291058 2, 0xFFFF, sum = 0
3130 12:38:37.293982 3, 0xFFFF, sum = 0
3131 12:38:37.294066 4, 0xFFFF, sum = 0
3132 12:38:37.297233 5, 0xFFFF, sum = 0
3133 12:38:37.297318 6, 0xFFFF, sum = 0
3134 12:38:37.301033 7, 0xFFFF, sum = 0
3135 12:38:37.301118 8, 0xFFFF, sum = 0
3136 12:38:37.304244 9, 0xFFFF, sum = 0
3137 12:38:37.307264 10, 0xFFFF, sum = 0
3138 12:38:37.307348 11, 0x0, sum = 1
3139 12:38:37.307413 12, 0x0, sum = 2
3140 12:38:37.310611 13, 0x0, sum = 3
3141 12:38:37.310694 14, 0x0, sum = 4
3142 12:38:37.315089 best_step = 12
3143 12:38:37.315171
3144 12:38:37.315235 ==
3145 12:38:37.317602 Dram Type= 6, Freq= 0, CH_1, rank 0
3146 12:38:37.321625 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3147 12:38:37.321708 ==
3148 12:38:37.325870 RX Vref Scan: 1
3149 12:38:37.325957
3150 12:38:37.326022 Set Vref Range= 32 -> 127
3151 12:38:37.326081
3152 12:38:37.328420 RX Vref 32 -> 127, step: 1
3153 12:38:37.328527
3154 12:38:37.330907 RX Delay -29 -> 252, step: 4
3155 12:38:37.330989
3156 12:38:37.334047 Set Vref, RX VrefLevel [Byte0]: 32
3157 12:38:37.338056 [Byte1]: 32
3158 12:38:37.338139
3159 12:38:37.340967 Set Vref, RX VrefLevel [Byte0]: 33
3160 12:38:37.344551 [Byte1]: 33
3161 12:38:37.349091
3162 12:38:37.349175 Set Vref, RX VrefLevel [Byte0]: 34
3163 12:38:37.352338 [Byte1]: 34
3164 12:38:37.357464
3165 12:38:37.357549 Set Vref, RX VrefLevel [Byte0]: 35
3166 12:38:37.360089 [Byte1]: 35
3167 12:38:37.364762
3168 12:38:37.364862 Set Vref, RX VrefLevel [Byte0]: 36
3169 12:38:37.367701 [Byte1]: 36
3170 12:38:37.372713
3171 12:38:37.376234 Set Vref, RX VrefLevel [Byte0]: 37
3172 12:38:37.376318 [Byte1]: 37
3173 12:38:37.380862
3174 12:38:37.380944 Set Vref, RX VrefLevel [Byte0]: 38
3175 12:38:37.384126 [Byte1]: 38
3176 12:38:37.388462
3177 12:38:37.388547 Set Vref, RX VrefLevel [Byte0]: 39
3178 12:38:37.391988 [Byte1]: 39
3179 12:38:37.396537
3180 12:38:37.396621 Set Vref, RX VrefLevel [Byte0]: 40
3181 12:38:37.399841 [Byte1]: 40
3182 12:38:37.404963
3183 12:38:37.405048 Set Vref, RX VrefLevel [Byte0]: 41
3184 12:38:37.407657 [Byte1]: 41
3185 12:38:37.412551
3186 12:38:37.412634 Set Vref, RX VrefLevel [Byte0]: 42
3187 12:38:37.416919 [Byte1]: 42
3188 12:38:37.420187
3189 12:38:37.420270 Set Vref, RX VrefLevel [Byte0]: 43
3190 12:38:37.423258 [Byte1]: 43
3191 12:38:37.428522
3192 12:38:37.428615 Set Vref, RX VrefLevel [Byte0]: 44
3193 12:38:37.431210 [Byte1]: 44
3194 12:38:37.436018
3195 12:38:37.436103 Set Vref, RX VrefLevel [Byte0]: 45
3196 12:38:37.439683 [Byte1]: 45
3197 12:38:37.444267
3198 12:38:37.444351 Set Vref, RX VrefLevel [Byte0]: 46
3199 12:38:37.447451 [Byte1]: 46
3200 12:38:37.452118
3201 12:38:37.452202 Set Vref, RX VrefLevel [Byte0]: 47
3202 12:38:37.455490 [Byte1]: 47
3203 12:38:37.461518
3204 12:38:37.461602 Set Vref, RX VrefLevel [Byte0]: 48
3205 12:38:37.463477 [Byte1]: 48
3206 12:38:37.468150
3207 12:38:37.468234 Set Vref, RX VrefLevel [Byte0]: 49
3208 12:38:37.471500 [Byte1]: 49
3209 12:38:37.475798
3210 12:38:37.475881 Set Vref, RX VrefLevel [Byte0]: 50
3211 12:38:37.479704 [Byte1]: 50
3212 12:38:37.483505
3213 12:38:37.483588 Set Vref, RX VrefLevel [Byte0]: 51
3214 12:38:37.487255 [Byte1]: 51
3215 12:38:37.492042
3216 12:38:37.492125 Set Vref, RX VrefLevel [Byte0]: 52
3217 12:38:37.494873 [Byte1]: 52
3218 12:38:37.500348
3219 12:38:37.500433 Set Vref, RX VrefLevel [Byte0]: 53
3220 12:38:37.503609 [Byte1]: 53
3221 12:38:37.507684
3222 12:38:37.507769 Set Vref, RX VrefLevel [Byte0]: 54
3223 12:38:37.510939 [Byte1]: 54
3224 12:38:37.516008
3225 12:38:37.516093 Set Vref, RX VrefLevel [Byte0]: 55
3226 12:38:37.518792 [Byte1]: 55
3227 12:38:37.523551
3228 12:38:37.523634 Set Vref, RX VrefLevel [Byte0]: 56
3229 12:38:37.527078 [Byte1]: 56
3230 12:38:37.531568
3231 12:38:37.531654 Set Vref, RX VrefLevel [Byte0]: 57
3232 12:38:37.535401 [Byte1]: 57
3233 12:38:37.539321
3234 12:38:37.539406 Set Vref, RX VrefLevel [Byte0]: 58
3235 12:38:37.543460 [Byte1]: 58
3236 12:38:37.547941
3237 12:38:37.548026 Set Vref, RX VrefLevel [Byte0]: 59
3238 12:38:37.550767 [Byte1]: 59
3239 12:38:37.555590
3240 12:38:37.555674 Set Vref, RX VrefLevel [Byte0]: 60
3241 12:38:37.559019 [Byte1]: 60
3242 12:38:37.563529
3243 12:38:37.563614 Set Vref, RX VrefLevel [Byte0]: 61
3244 12:38:37.566731 [Byte1]: 61
3245 12:38:37.571561
3246 12:38:37.571644 Set Vref, RX VrefLevel [Byte0]: 62
3247 12:38:37.574665 [Byte1]: 62
3248 12:38:37.579469
3249 12:38:37.579552 Set Vref, RX VrefLevel [Byte0]: 63
3250 12:38:37.582548 [Byte1]: 63
3251 12:38:37.587485
3252 12:38:37.587593 Set Vref, RX VrefLevel [Byte0]: 64
3253 12:38:37.590694 [Byte1]: 64
3254 12:38:37.595493
3255 12:38:37.595592 Set Vref, RX VrefLevel [Byte0]: 65
3256 12:38:37.598579 [Byte1]: 65
3257 12:38:37.603213
3258 12:38:37.603310 Final RX Vref Byte 0 = 56 to rank0
3259 12:38:37.606797 Final RX Vref Byte 1 = 48 to rank0
3260 12:38:37.610679 Final RX Vref Byte 0 = 56 to rank1
3261 12:38:37.613254 Final RX Vref Byte 1 = 48 to rank1==
3262 12:38:37.616479 Dram Type= 6, Freq= 0, CH_1, rank 0
3263 12:38:37.623725 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3264 12:38:37.623813 ==
3265 12:38:37.623878 DQS Delay:
3266 12:38:37.623938 DQS0 = 0, DQS1 = 0
3267 12:38:37.627056 DQM Delay:
3268 12:38:37.627140 DQM0 = 115, DQM1 = 105
3269 12:38:37.629855 DQ Delay:
3270 12:38:37.633043 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3271 12:38:37.637742 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3272 12:38:37.640198 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3273 12:38:37.643387 DQ12 =112, DQ13 =114, DQ14 =116, DQ15 =114
3274 12:38:37.643472
3275 12:38:37.643535
3276 12:38:37.650116 [DQSOSCAuto] RK0, (LSB)MR18= 0x1515, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
3277 12:38:37.653184 CH1 RK0: MR19=404, MR18=1515
3278 12:38:37.659876 CH1_RK0: MR19=0x404, MR18=0x1515, DQSOSC=401, MR23=63, INC=40, DEC=27
3279 12:38:37.659959
3280 12:38:37.664162 ----->DramcWriteLeveling(PI) begin...
3281 12:38:37.664247 ==
3282 12:38:37.667135 Dram Type= 6, Freq= 0, CH_1, rank 1
3283 12:38:37.669807 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3284 12:38:37.672913 ==
3285 12:38:37.672994 Write leveling (Byte 0): 22 => 22
3286 12:38:37.676048 Write leveling (Byte 1): 22 => 22
3287 12:38:37.680420 DramcWriteLeveling(PI) end<-----
3288 12:38:37.680496
3289 12:38:37.680581 ==
3290 12:38:37.683067 Dram Type= 6, Freq= 0, CH_1, rank 1
3291 12:38:37.689377 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3292 12:38:37.689454 ==
3293 12:38:37.689517 [Gating] SW mode calibration
3294 12:38:37.699481 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3295 12:38:37.703065 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3296 12:38:37.710086 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3297 12:38:37.714065 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3298 12:38:37.716503 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3299 12:38:37.719909 0 11 12 | B1->B0 | 3434 2424 | 1 0 | (1 0) (1 0)
3300 12:38:37.726384 0 11 16 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
3301 12:38:37.729783 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3302 12:38:37.733052 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3303 12:38:37.739936 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3304 12:38:37.742800 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3305 12:38:37.745896 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3306 12:38:37.753577 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3307 12:38:37.756231 0 12 12 | B1->B0 | 2323 3232 | 1 0 | (0 0) (0 0)
3308 12:38:37.759250 0 12 16 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
3309 12:38:37.766075 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3310 12:38:37.769547 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3311 12:38:37.772947 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3312 12:38:37.779892 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3313 12:38:37.783224 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3314 12:38:37.785956 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3315 12:38:37.792856 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3316 12:38:37.796161 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3317 12:38:37.799565 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3318 12:38:37.806186 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3319 12:38:37.809386 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3320 12:38:37.812917 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3321 12:38:37.817500 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3322 12:38:37.823499 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3323 12:38:37.827034 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3324 12:38:37.829644 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3325 12:38:37.835942 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3326 12:38:37.839614 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3327 12:38:37.843085 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3328 12:38:37.849471 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3329 12:38:37.852501 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3330 12:38:37.856122 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3331 12:38:37.862237 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3332 12:38:37.865805 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3333 12:38:37.869258 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3334 12:38:37.872741 Total UI for P1: 0, mck2ui 16
3335 12:38:37.875739 best dqsien dly found for B0: ( 0, 15, 14)
3336 12:38:37.879465 Total UI for P1: 0, mck2ui 16
3337 12:38:37.882126 best dqsien dly found for B1: ( 0, 15, 14)
3338 12:38:37.886828 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3339 12:38:37.889227 best DQS1 dly(MCK, UI, PI) = (0, 15, 14)
3340 12:38:37.892441
3341 12:38:37.895573 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3342 12:38:37.898979 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 14)
3343 12:38:37.902281 [Gating] SW calibration Done
3344 12:38:37.902364 ==
3345 12:38:37.905755 Dram Type= 6, Freq= 0, CH_1, rank 1
3346 12:38:37.910453 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3347 12:38:37.910537 ==
3348 12:38:37.910601 RX Vref Scan: 0
3349 12:38:37.910660
3350 12:38:37.912239 RX Vref 0 -> 0, step: 1
3351 12:38:37.912346
3352 12:38:37.915646 RX Delay -40 -> 252, step: 8
3353 12:38:37.920060 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3354 12:38:37.922174 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3355 12:38:37.928961 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3356 12:38:37.932073 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3357 12:38:37.935976 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3358 12:38:37.939012 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3359 12:38:37.942522 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3360 12:38:37.948892 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3361 12:38:37.952278 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3362 12:38:37.955880 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3363 12:38:37.959093 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3364 12:38:37.962448 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
3365 12:38:37.965571 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3366 12:38:37.972228 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3367 12:38:37.975474 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3368 12:38:37.979135 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3369 12:38:37.979219 ==
3370 12:38:37.982205 Dram Type= 6, Freq= 0, CH_1, rank 1
3371 12:38:37.985819 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3372 12:38:37.988875 ==
3373 12:38:37.988958 DQS Delay:
3374 12:38:37.989021 DQS0 = 0, DQS1 = 0
3375 12:38:37.991969 DQM Delay:
3376 12:38:37.992050 DQM0 = 115, DQM1 = 105
3377 12:38:37.995606 DQ Delay:
3378 12:38:37.998633 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3379 12:38:38.002949 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3380 12:38:38.005413 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =95
3381 12:38:38.009157 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3382 12:38:38.009236
3383 12:38:38.009325
3384 12:38:38.009412 ==
3385 12:38:38.012603 Dram Type= 6, Freq= 0, CH_1, rank 1
3386 12:38:38.016104 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3387 12:38:38.016187 ==
3388 12:38:38.016273
3389 12:38:38.016358
3390 12:38:38.018730 TX Vref Scan disable
3391 12:38:38.022077 == TX Byte 0 ==
3392 12:38:38.025880 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3393 12:38:38.028675 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3394 12:38:38.032988 == TX Byte 1 ==
3395 12:38:38.035506 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3396 12:38:38.039476 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3397 12:38:38.039582 ==
3398 12:38:38.042518 Dram Type= 6, Freq= 0, CH_1, rank 1
3399 12:38:38.045202 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3400 12:38:38.049161 ==
3401 12:38:38.058559 TX Vref=22, minBit 0, minWin=26, winSum=424
3402 12:38:38.062527 TX Vref=24, minBit 1, minWin=26, winSum=426
3403 12:38:38.065336 TX Vref=26, minBit 3, minWin=26, winSum=428
3404 12:38:38.068870 TX Vref=28, minBit 4, minWin=26, winSum=429
3405 12:38:38.072159 TX Vref=30, minBit 9, minWin=26, winSum=432
3406 12:38:38.078628 TX Vref=32, minBit 0, minWin=26, winSum=431
3407 12:38:38.082041 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 30
3408 12:38:38.082150
3409 12:38:38.084987 Final TX Range 1 Vref 30
3410 12:38:38.085063
3411 12:38:38.085128 ==
3412 12:38:38.088860 Dram Type= 6, Freq= 0, CH_1, rank 1
3413 12:38:38.091721 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3414 12:38:38.091819 ==
3415 12:38:38.091910
3416 12:38:38.095684
3417 12:38:38.095785 TX Vref Scan disable
3418 12:38:38.098597 == TX Byte 0 ==
3419 12:38:38.101930 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3420 12:38:38.105112 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3421 12:38:38.108551 == TX Byte 1 ==
3422 12:38:38.111688 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3423 12:38:38.115299 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3424 12:38:38.115401
3425 12:38:38.118606 [DATLAT]
3426 12:38:38.118710 Freq=1200, CH1 RK1
3427 12:38:38.118803
3428 12:38:38.121725 DATLAT Default: 0xc
3429 12:38:38.121823 0, 0xFFFF, sum = 0
3430 12:38:38.125218 1, 0xFFFF, sum = 0
3431 12:38:38.125321 2, 0xFFFF, sum = 0
3432 12:38:38.129109 3, 0xFFFF, sum = 0
3433 12:38:38.129192 4, 0xFFFF, sum = 0
3434 12:38:38.133165 5, 0xFFFF, sum = 0
3435 12:38:38.133241 6, 0xFFFF, sum = 0
3436 12:38:38.135414 7, 0xFFFF, sum = 0
3437 12:38:38.135498 8, 0xFFFF, sum = 0
3438 12:38:38.138488 9, 0xFFFF, sum = 0
3439 12:38:38.142131 10, 0xFFFF, sum = 0
3440 12:38:38.142217 11, 0x0, sum = 1
3441 12:38:38.142283 12, 0x0, sum = 2
3442 12:38:38.145373 13, 0x0, sum = 3
3443 12:38:38.145457 14, 0x0, sum = 4
3444 12:38:38.148718 best_step = 12
3445 12:38:38.148834
3446 12:38:38.148923 ==
3447 12:38:38.152678 Dram Type= 6, Freq= 0, CH_1, rank 1
3448 12:38:38.155524 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3449 12:38:38.155608 ==
3450 12:38:38.158580 RX Vref Scan: 0
3451 12:38:38.158699
3452 12:38:38.158774 RX Vref 0 -> 0, step: 1
3453 12:38:38.158835
3454 12:38:38.161827 RX Delay -21 -> 252, step: 4
3455 12:38:38.169536 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3456 12:38:38.172102 iDelay=199, Bit 1, Center 108 (39 ~ 178) 140
3457 12:38:38.175641 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3458 12:38:38.179078 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3459 12:38:38.182423 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3460 12:38:38.189464 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3461 12:38:38.192234 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3462 12:38:38.195603 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3463 12:38:38.198595 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3464 12:38:38.202537 iDelay=199, Bit 9, Center 90 (23 ~ 158) 136
3465 12:38:38.209880 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3466 12:38:38.212015 iDelay=199, Bit 11, Center 96 (31 ~ 162) 132
3467 12:38:38.215885 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3468 12:38:38.218875 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3469 12:38:38.222081 iDelay=199, Bit 14, Center 114 (47 ~ 182) 136
3470 12:38:38.228595 iDelay=199, Bit 15, Center 112 (47 ~ 178) 132
3471 12:38:38.228714 ==
3472 12:38:38.232147 Dram Type= 6, Freq= 0, CH_1, rank 1
3473 12:38:38.235294 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3474 12:38:38.235379 ==
3475 12:38:38.235445 DQS Delay:
3476 12:38:38.238927 DQS0 = 0, DQS1 = 0
3477 12:38:38.239011 DQM Delay:
3478 12:38:38.241944 DQM0 = 114, DQM1 = 103
3479 12:38:38.242027 DQ Delay:
3480 12:38:38.245341 DQ0 =116, DQ1 =108, DQ2 =108, DQ3 =112
3481 12:38:38.248730 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3482 12:38:38.251939 DQ8 =86, DQ9 =90, DQ10 =106, DQ11 =96
3483 12:38:38.255414 DQ12 =112, DQ13 =112, DQ14 =114, DQ15 =112
3484 12:38:38.255499
3485 12:38:38.255564
3486 12:38:38.265026 [DQSOSCAuto] RK1, (LSB)MR18= 0x808, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
3487 12:38:38.268344 CH1 RK1: MR19=404, MR18=808
3488 12:38:38.272118 CH1_RK1: MR19=0x404, MR18=0x808, DQSOSC=406, MR23=63, INC=39, DEC=26
3489 12:38:38.275292 [RxdqsGatingPostProcess] freq 1200
3490 12:38:38.281994 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3491 12:38:38.285162 Pre-setting of DQS Precalculation
3492 12:38:38.288655 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3493 12:38:38.299536 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3494 12:38:38.305708 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3495 12:38:38.305815
3496 12:38:38.305878
3497 12:38:38.308663 [Calibration Summary] 2400 Mbps
3498 12:38:38.308801 CH 0, Rank 0
3499 12:38:38.312601 SW Impedance : PASS
3500 12:38:38.312714 DUTY Scan : NO K
3501 12:38:38.315386 ZQ Calibration : PASS
3502 12:38:38.318995 Jitter Meter : NO K
3503 12:38:38.319084 CBT Training : PASS
3504 12:38:38.321885 Write leveling : PASS
3505 12:38:38.325704 RX DQS gating : PASS
3506 12:38:38.325778 RX DQ/DQS(RDDQC) : PASS
3507 12:38:38.328745 TX DQ/DQS : PASS
3508 12:38:38.328840 RX DATLAT : PASS
3509 12:38:38.332552 RX DQ/DQS(Engine): PASS
3510 12:38:38.335623 TX OE : NO K
3511 12:38:38.335732 All Pass.
3512 12:38:38.335818
3513 12:38:38.335889 CH 0, Rank 1
3514 12:38:38.338856 SW Impedance : PASS
3515 12:38:38.341583 DUTY Scan : NO K
3516 12:38:38.341684 ZQ Calibration : PASS
3517 12:38:38.346610 Jitter Meter : NO K
3518 12:38:38.348913 CBT Training : PASS
3519 12:38:38.349013 Write leveling : PASS
3520 12:38:38.351794 RX DQS gating : PASS
3521 12:38:38.355200 RX DQ/DQS(RDDQC) : PASS
3522 12:38:38.355292 TX DQ/DQS : PASS
3523 12:38:38.358376 RX DATLAT : PASS
3524 12:38:38.361891 RX DQ/DQS(Engine): PASS
3525 12:38:38.361993 TX OE : NO K
3526 12:38:38.365230 All Pass.
3527 12:38:38.365337
3528 12:38:38.365428 CH 1, Rank 0
3529 12:38:38.368893 SW Impedance : PASS
3530 12:38:38.368997 DUTY Scan : NO K
3531 12:38:38.371736 ZQ Calibration : PASS
3532 12:38:38.375139 Jitter Meter : NO K
3533 12:38:38.375242 CBT Training : PASS
3534 12:38:38.378381 Write leveling : PASS
3535 12:38:38.378487 RX DQS gating : PASS
3536 12:38:38.381706 RX DQ/DQS(RDDQC) : PASS
3537 12:38:38.385091 TX DQ/DQS : PASS
3538 12:38:38.385185 RX DATLAT : PASS
3539 12:38:38.388877 RX DQ/DQS(Engine): PASS
3540 12:38:38.391592 TX OE : NO K
3541 12:38:38.391695 All Pass.
3542 12:38:38.391786
3543 12:38:38.391873 CH 1, Rank 1
3544 12:38:38.395886 SW Impedance : PASS
3545 12:38:38.398146 DUTY Scan : NO K
3546 12:38:38.398249 ZQ Calibration : PASS
3547 12:38:38.401599 Jitter Meter : NO K
3548 12:38:38.405439 CBT Training : PASS
3549 12:38:38.405527 Write leveling : PASS
3550 12:38:38.408823 RX DQS gating : PASS
3551 12:38:38.411850 RX DQ/DQS(RDDQC) : PASS
3552 12:38:38.411923 TX DQ/DQS : PASS
3553 12:38:38.415675 RX DATLAT : PASS
3554 12:38:38.418445 RX DQ/DQS(Engine): PASS
3555 12:38:38.418531 TX OE : NO K
3556 12:38:38.418594 All Pass.
3557 12:38:38.421608
3558 12:38:38.421701 DramC Write-DBI off
3559 12:38:38.425141 PER_BANK_REFRESH: Hybrid Mode
3560 12:38:38.425220 TX_TRACKING: ON
3561 12:38:38.435060 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3562 12:38:38.438493 [FAST_K] Save calibration result to emmc
3563 12:38:38.441704 dramc_set_vcore_voltage set vcore to 650000
3564 12:38:38.444934 Read voltage for 600, 5
3565 12:38:38.445011 Vio18 = 0
3566 12:38:38.450260 Vcore = 650000
3567 12:38:38.450359 Vdram = 0
3568 12:38:38.450448 Vddq = 0
3569 12:38:38.450537 Vmddr = 0
3570 12:38:38.455478 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3571 12:38:38.462237 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3572 12:38:38.462345 MEM_TYPE=3, freq_sel=19
3573 12:38:38.465194 sv_algorithm_assistance_LP4_1600
3574 12:38:38.468323 ============ PULL DRAM RESETB DOWN ============
3575 12:38:38.475085 ========== PULL DRAM RESETB DOWN end =========
3576 12:38:38.478333 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3577 12:38:38.481882 ===================================
3578 12:38:38.485144 LPDDR4 DRAM CONFIGURATION
3579 12:38:38.488183 ===================================
3580 12:38:38.488261 EX_ROW_EN[0] = 0x0
3581 12:38:38.491837 EX_ROW_EN[1] = 0x0
3582 12:38:38.491910 LP4Y_EN = 0x0
3583 12:38:38.495173 WORK_FSP = 0x0
3584 12:38:38.495250 WL = 0x2
3585 12:38:38.498537 RL = 0x2
3586 12:38:38.498610 BL = 0x2
3587 12:38:38.501872 RPST = 0x0
3588 12:38:38.501976 RD_PRE = 0x0
3589 12:38:38.505284 WR_PRE = 0x1
3590 12:38:38.505367 WR_PST = 0x0
3591 12:38:38.508414 DBI_WR = 0x0
3592 12:38:38.512084 DBI_RD = 0x0
3593 12:38:38.512187 OTF = 0x1
3594 12:38:38.515313 ===================================
3595 12:38:38.518417 ===================================
3596 12:38:38.518504 ANA top config
3597 12:38:38.522430 ===================================
3598 12:38:38.525496 DLL_ASYNC_EN = 0
3599 12:38:38.528534 ALL_SLAVE_EN = 1
3600 12:38:38.531392 NEW_RANK_MODE = 1
3601 12:38:38.534982 DLL_IDLE_MODE = 1
3602 12:38:38.535082 LP45_APHY_COMB_EN = 1
3603 12:38:38.539335 TX_ODT_DIS = 1
3604 12:38:38.542025 NEW_8X_MODE = 1
3605 12:38:38.544593 ===================================
3606 12:38:38.548575 ===================================
3607 12:38:38.551258 data_rate = 1200
3608 12:38:38.555160 CKR = 1
3609 12:38:38.555235 DQ_P2S_RATIO = 8
3610 12:38:38.557859 ===================================
3611 12:38:38.561737 CA_P2S_RATIO = 8
3612 12:38:38.565181 DQ_CA_OPEN = 0
3613 12:38:38.568489 DQ_SEMI_OPEN = 0
3614 12:38:38.571362 CA_SEMI_OPEN = 0
3615 12:38:38.574359 CA_FULL_RATE = 0
3616 12:38:38.574501 DQ_CKDIV4_EN = 1
3617 12:38:38.577989 CA_CKDIV4_EN = 1
3618 12:38:38.582776 CA_PREDIV_EN = 0
3619 12:38:38.585995 PH8_DLY = 0
3620 12:38:38.589330 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3621 12:38:38.590960 DQ_AAMCK_DIV = 4
3622 12:38:38.591043 CA_AAMCK_DIV = 4
3623 12:38:38.594399 CA_ADMCK_DIV = 4
3624 12:38:38.598414 DQ_TRACK_CA_EN = 0
3625 12:38:38.600866 CA_PICK = 600
3626 12:38:38.604874 CA_MCKIO = 600
3627 12:38:38.607922 MCKIO_SEMI = 0
3628 12:38:38.610929 PLL_FREQ = 2288
3629 12:38:38.614298 DQ_UI_PI_RATIO = 32
3630 12:38:38.614372 CA_UI_PI_RATIO = 0
3631 12:38:38.617253 ===================================
3632 12:38:38.621154 ===================================
3633 12:38:38.624230 memory_type:LPDDR4
3634 12:38:38.627239 GP_NUM : 10
3635 12:38:38.627351 SRAM_EN : 1
3636 12:38:38.630546 MD32_EN : 0
3637 12:38:38.633870 ===================================
3638 12:38:38.637397 [ANA_INIT] >>>>>>>>>>>>>>
3639 12:38:38.640882 <<<<<< [CONFIGURE PHASE]: ANA_TX
3640 12:38:38.643729 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3641 12:38:38.647118 ===================================
3642 12:38:38.647203 data_rate = 1200,PCW = 0X5800
3643 12:38:38.650903 ===================================
3644 12:38:38.653566 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3645 12:38:38.660217 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3646 12:38:38.667977 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3647 12:38:38.671032 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3648 12:38:38.673847 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3649 12:38:38.676724 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3650 12:38:38.680899 [ANA_INIT] flow start
3651 12:38:38.684417 [ANA_INIT] PLL >>>>>>>>
3652 12:38:38.684521 [ANA_INIT] PLL <<<<<<<<
3653 12:38:38.687058 [ANA_INIT] MIDPI >>>>>>>>
3654 12:38:38.690714 [ANA_INIT] MIDPI <<<<<<<<
3655 12:38:38.690819 [ANA_INIT] DLL >>>>>>>>
3656 12:38:38.693566 [ANA_INIT] flow end
3657 12:38:38.696869 ============ LP4 DIFF to SE enter ============
3658 12:38:38.700395 ============ LP4 DIFF to SE exit ============
3659 12:38:38.703557 [ANA_INIT] <<<<<<<<<<<<<
3660 12:38:38.706819 [Flow] Enable top DCM control >>>>>
3661 12:38:38.710515 [Flow] Enable top DCM control <<<<<
3662 12:38:38.713558 Enable DLL master slave shuffle
3663 12:38:38.719963 ==============================================================
3664 12:38:38.720076 Gating Mode config
3665 12:38:38.726474 ==============================================================
3666 12:38:38.726552 Config description:
3667 12:38:38.737445 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3668 12:38:38.743051 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3669 12:38:38.749843 SELPH_MODE 0: By rank 1: By Phase
3670 12:38:38.752935 ==============================================================
3671 12:38:38.756550 GAT_TRACK_EN = 1
3672 12:38:38.761036 RX_GATING_MODE = 2
3673 12:38:38.763214 RX_GATING_TRACK_MODE = 2
3674 12:38:38.766162 SELPH_MODE = 1
3675 12:38:38.769906 PICG_EARLY_EN = 1
3676 12:38:38.773060 VALID_LAT_VALUE = 1
3677 12:38:38.779517 ==============================================================
3678 12:38:38.782617 Enter into Gating configuration >>>>
3679 12:38:38.785961 Exit from Gating configuration <<<<
3680 12:38:38.790123 Enter into DVFS_PRE_config >>>>>
3681 12:38:38.799062 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3682 12:38:38.802867 Exit from DVFS_PRE_config <<<<<
3683 12:38:38.805853 Enter into PICG configuration >>>>
3684 12:38:38.809096 Exit from PICG configuration <<<<
3685 12:38:38.812975 [RX_INPUT] configuration >>>>>
3686 12:38:38.813064 [RX_INPUT] configuration <<<<<
3687 12:38:38.819534 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3688 12:38:38.826539 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3689 12:38:38.832398 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3690 12:38:38.835418 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3691 12:38:38.842254 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3692 12:38:38.848655 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3693 12:38:38.852676 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3694 12:38:38.859063 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3695 12:38:38.862043 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3696 12:38:38.865435 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3697 12:38:38.869346 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3698 12:38:38.875403 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3699 12:38:38.878433 ===================================
3700 12:38:38.878525 LPDDR4 DRAM CONFIGURATION
3701 12:38:38.881834 ===================================
3702 12:38:38.885843 EX_ROW_EN[0] = 0x0
3703 12:38:38.889282 EX_ROW_EN[1] = 0x0
3704 12:38:38.889369 LP4Y_EN = 0x0
3705 12:38:38.891935 WORK_FSP = 0x0
3706 12:38:38.892018 WL = 0x2
3707 12:38:38.895284 RL = 0x2
3708 12:38:38.895368 BL = 0x2
3709 12:38:38.899061 RPST = 0x0
3710 12:38:38.899146 RD_PRE = 0x0
3711 12:38:38.901603 WR_PRE = 0x1
3712 12:38:38.901690 WR_PST = 0x0
3713 12:38:38.905344 DBI_WR = 0x0
3714 12:38:38.905429 DBI_RD = 0x0
3715 12:38:38.908433 OTF = 0x1
3716 12:38:38.911867 ===================================
3717 12:38:38.914604 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3718 12:38:38.918296 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3719 12:38:38.924718 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3720 12:38:38.928617 ===================================
3721 12:38:38.928747 LPDDR4 DRAM CONFIGURATION
3722 12:38:38.931861 ===================================
3723 12:38:38.935171 EX_ROW_EN[0] = 0x10
3724 12:38:38.938563 EX_ROW_EN[1] = 0x0
3725 12:38:38.938647 LP4Y_EN = 0x0
3726 12:38:38.941482 WORK_FSP = 0x0
3727 12:38:38.941566 WL = 0x2
3728 12:38:38.944498 RL = 0x2
3729 12:38:38.944581 BL = 0x2
3730 12:38:38.947972 RPST = 0x0
3731 12:38:38.948056 RD_PRE = 0x0
3732 12:38:38.951825 WR_PRE = 0x1
3733 12:38:38.951911 WR_PST = 0x0
3734 12:38:38.954813 DBI_WR = 0x0
3735 12:38:38.954897 DBI_RD = 0x0
3736 12:38:38.959060 OTF = 0x1
3737 12:38:38.961664 ===================================
3738 12:38:38.968426 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3739 12:38:38.971552 nWR fixed to 30
3740 12:38:38.971647 [ModeRegInit_LP4] CH0 RK0
3741 12:38:38.974680 [ModeRegInit_LP4] CH0 RK1
3742 12:38:38.978868 [ModeRegInit_LP4] CH1 RK0
3743 12:38:38.981231 [ModeRegInit_LP4] CH1 RK1
3744 12:38:38.981319 match AC timing 16
3745 12:38:38.984246 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3746 12:38:38.991048 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3747 12:38:38.994614 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3748 12:38:39.001550 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3749 12:38:39.004359 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3750 12:38:39.004455 ==
3751 12:38:39.007495 Dram Type= 6, Freq= 0, CH_0, rank 0
3752 12:38:39.011072 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3753 12:38:39.011159 ==
3754 12:38:39.017661 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3755 12:38:39.024575 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3756 12:38:39.027527 [CA 0] Center 35 (5~66) winsize 62
3757 12:38:39.030711 [CA 1] Center 35 (5~66) winsize 62
3758 12:38:39.034343 [CA 2] Center 34 (4~65) winsize 62
3759 12:38:39.038061 [CA 3] Center 34 (3~65) winsize 63
3760 12:38:39.041601 [CA 4] Center 33 (3~64) winsize 62
3761 12:38:39.044226 [CA 5] Center 33 (3~64) winsize 62
3762 12:38:39.044326
3763 12:38:39.047762 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3764 12:38:39.047859
3765 12:38:39.050677 [CATrainingPosCal] consider 1 rank data
3766 12:38:39.054681 u2DelayCellTimex100 = 270/100 ps
3767 12:38:39.057304 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3768 12:38:39.062004 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3769 12:38:39.064301 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3770 12:38:39.067414 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3771 12:38:39.070614 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3772 12:38:39.074105 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3773 12:38:39.074207
3774 12:38:39.080991 CA PerBit enable=1, Macro0, CA PI delay=33
3775 12:38:39.081102
3776 12:38:39.081194 [CBTSetCACLKResult] CA Dly = 33
3777 12:38:39.083827 CS Dly: 5 (0~36)
3778 12:38:39.083922 ==
3779 12:38:39.087253 Dram Type= 6, Freq= 0, CH_0, rank 1
3780 12:38:39.090524 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3781 12:38:39.090621 ==
3782 12:38:39.097055 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3783 12:38:39.103520 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3784 12:38:39.106831 [CA 0] Center 35 (5~66) winsize 62
3785 12:38:39.110503 [CA 1] Center 35 (5~66) winsize 62
3786 12:38:39.113875 [CA 2] Center 34 (4~65) winsize 62
3787 12:38:39.116850 [CA 3] Center 34 (3~65) winsize 63
3788 12:38:39.120468 [CA 4] Center 33 (3~64) winsize 62
3789 12:38:39.123238 [CA 5] Center 33 (3~64) winsize 62
3790 12:38:39.123339
3791 12:38:39.126825 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3792 12:38:39.126916
3793 12:38:39.130160 [CATrainingPosCal] consider 2 rank data
3794 12:38:39.133863 u2DelayCellTimex100 = 270/100 ps
3795 12:38:39.136957 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3796 12:38:39.140340 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3797 12:38:39.143668 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3798 12:38:39.146961 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3799 12:38:39.150221 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3800 12:38:39.157066 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3801 12:38:39.157155
3802 12:38:39.159973 CA PerBit enable=1, Macro0, CA PI delay=33
3803 12:38:39.160072
3804 12:38:39.163349 [CBTSetCACLKResult] CA Dly = 33
3805 12:38:39.163452 CS Dly: 5 (0~36)
3806 12:38:39.163541
3807 12:38:39.166657 ----->DramcWriteLeveling(PI) begin...
3808 12:38:39.166762 ==
3809 12:38:39.170131 Dram Type= 6, Freq= 0, CH_0, rank 0
3810 12:38:39.176807 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3811 12:38:39.176888 ==
3812 12:38:39.179805 Write leveling (Byte 0): 32 => 32
3813 12:38:39.179891 Write leveling (Byte 1): 29 => 29
3814 12:38:39.184127 DramcWriteLeveling(PI) end<-----
3815 12:38:39.184211
3816 12:38:39.184275 ==
3817 12:38:39.186774 Dram Type= 6, Freq= 0, CH_0, rank 0
3818 12:38:39.193311 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3819 12:38:39.193397 ==
3820 12:38:39.197065 [Gating] SW mode calibration
3821 12:38:39.203301 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3822 12:38:39.206435 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3823 12:38:39.213224 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3824 12:38:39.216161 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3825 12:38:39.219626 0 5 8 | B1->B0 | 3030 2f2f | 0 0 | (0 1) (1 0)
3826 12:38:39.225842 0 5 12 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
3827 12:38:39.229301 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3828 12:38:39.232930 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3829 12:38:39.239179 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3830 12:38:39.242529 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3831 12:38:39.246252 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3832 12:38:39.252731 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3833 12:38:39.256114 0 6 8 | B1->B0 | 2d2d 3434 | 0 0 | (0 0) (0 0)
3834 12:38:39.259487 0 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3835 12:38:39.266557 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3836 12:38:39.269318 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3837 12:38:39.272727 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3838 12:38:39.276052 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3839 12:38:39.282453 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3840 12:38:39.285935 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3841 12:38:39.288953 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3842 12:38:39.296324 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3843 12:38:39.299148 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3844 12:38:39.302330 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3845 12:38:39.309410 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3846 12:38:39.312599 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3847 12:38:39.315917 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3848 12:38:39.321953 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3849 12:38:39.325286 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3850 12:38:39.329272 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3851 12:38:39.336092 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3852 12:38:39.338798 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3853 12:38:39.342002 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3854 12:38:39.348905 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3855 12:38:39.352517 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3856 12:38:39.355458 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3857 12:38:39.361818 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3858 12:38:39.365430 Total UI for P1: 0, mck2ui 16
3859 12:38:39.368888 best dqsien dly found for B0: ( 0, 9, 6)
3860 12:38:39.372503 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3861 12:38:39.375089 Total UI for P1: 0, mck2ui 16
3862 12:38:39.378580 best dqsien dly found for B1: ( 0, 9, 8)
3863 12:38:39.382163 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
3864 12:38:39.386015 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3865 12:38:39.386100
3866 12:38:39.388550 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
3867 12:38:39.392112 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3868 12:38:39.395670 [Gating] SW calibration Done
3869 12:38:39.395752 ==
3870 12:38:39.398227 Dram Type= 6, Freq= 0, CH_0, rank 0
3871 12:38:39.402535 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3872 12:38:39.405145 ==
3873 12:38:39.405227 RX Vref Scan: 0
3874 12:38:39.405291
3875 12:38:39.408900 RX Vref 0 -> 0, step: 1
3876 12:38:39.408982
3877 12:38:39.411520 RX Delay -230 -> 252, step: 16
3878 12:38:39.414944 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3879 12:38:39.418257 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3880 12:38:39.421973 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3881 12:38:39.428677 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3882 12:38:39.431721 iDelay=218, Bit 4, Center 41 (-134 ~ 217) 352
3883 12:38:39.434518 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
3884 12:38:39.438936 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3885 12:38:39.441925 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3886 12:38:39.447754 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3887 12:38:39.451903 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3888 12:38:39.454801 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3889 12:38:39.457883 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3890 12:38:39.464561 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3891 12:38:39.468439 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3892 12:38:39.471369 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3893 12:38:39.474547 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3894 12:38:39.474629 ==
3895 12:38:39.477867 Dram Type= 6, Freq= 0, CH_0, rank 0
3896 12:38:39.484293 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3897 12:38:39.484376 ==
3898 12:38:39.484442 DQS Delay:
3899 12:38:39.487652 DQS0 = 0, DQS1 = 0
3900 12:38:39.487733 DQM Delay:
3901 12:38:39.487798 DQM0 = 38, DQM1 = 33
3902 12:38:39.490951 DQ Delay:
3903 12:38:39.494169 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3904 12:38:39.497831 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
3905 12:38:39.501277 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3906 12:38:39.505190 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3907 12:38:39.505272
3908 12:38:39.505336
3909 12:38:39.505395 ==
3910 12:38:39.507662 Dram Type= 6, Freq= 0, CH_0, rank 0
3911 12:38:39.511161 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3912 12:38:39.511244 ==
3913 12:38:39.511308
3914 12:38:39.511367
3915 12:38:39.514261 TX Vref Scan disable
3916 12:38:39.517618 == TX Byte 0 ==
3917 12:38:39.521286 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
3918 12:38:39.524834 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
3919 12:38:39.527691 == TX Byte 1 ==
3920 12:38:39.531210 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3921 12:38:39.534072 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3922 12:38:39.534156 ==
3923 12:38:39.537487 Dram Type= 6, Freq= 0, CH_0, rank 0
3924 12:38:39.541315 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3925 12:38:39.544057 ==
3926 12:38:39.544139
3927 12:38:39.544203
3928 12:38:39.544262 TX Vref Scan disable
3929 12:38:39.547924 == TX Byte 0 ==
3930 12:38:39.551438 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
3931 12:38:39.558268 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
3932 12:38:39.558351 == TX Byte 1 ==
3933 12:38:39.561122 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3934 12:38:39.567755 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3935 12:38:39.567840
3936 12:38:39.567904 [DATLAT]
3937 12:38:39.567964 Freq=600, CH0 RK0
3938 12:38:39.568023
3939 12:38:39.572310 DATLAT Default: 0x9
3940 12:38:39.572393 0, 0xFFFF, sum = 0
3941 12:38:39.574956 1, 0xFFFF, sum = 0
3942 12:38:39.575039 2, 0xFFFF, sum = 0
3943 12:38:39.578032 3, 0xFFFF, sum = 0
3944 12:38:39.581318 4, 0xFFFF, sum = 0
3945 12:38:39.581402 5, 0xFFFF, sum = 0
3946 12:38:39.585309 6, 0xFFFF, sum = 0
3947 12:38:39.585393 7, 0x0, sum = 1
3948 12:38:39.585458 8, 0x0, sum = 2
3949 12:38:39.588593 9, 0x0, sum = 3
3950 12:38:39.588678 10, 0x0, sum = 4
3951 12:38:39.591510 best_step = 8
3952 12:38:39.591592
3953 12:38:39.591656 ==
3954 12:38:39.595162 Dram Type= 6, Freq= 0, CH_0, rank 0
3955 12:38:39.598234 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3956 12:38:39.598316 ==
3957 12:38:39.601266 RX Vref Scan: 1
3958 12:38:39.601348
3959 12:38:39.601411 RX Vref 0 -> 0, step: 1
3960 12:38:39.601471
3961 12:38:39.605509 RX Delay -195 -> 252, step: 8
3962 12:38:39.605591
3963 12:38:39.608493 Set Vref, RX VrefLevel [Byte0]: 49
3964 12:38:39.611453 [Byte1]: 49
3965 12:38:39.615400
3966 12:38:39.615482 Final RX Vref Byte 0 = 49 to rank0
3967 12:38:39.618423 Final RX Vref Byte 1 = 49 to rank0
3968 12:38:39.621691 Final RX Vref Byte 0 = 49 to rank1
3969 12:38:39.625159 Final RX Vref Byte 1 = 49 to rank1==
3970 12:38:39.628919 Dram Type= 6, Freq= 0, CH_0, rank 0
3971 12:38:39.636124 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3972 12:38:39.636209 ==
3973 12:38:39.636274 DQS Delay:
3974 12:38:39.636334 DQS0 = 0, DQS1 = 0
3975 12:38:39.638338 DQM Delay:
3976 12:38:39.638420 DQM0 = 40, DQM1 = 30
3977 12:38:39.642185 DQ Delay:
3978 12:38:39.644876 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
3979 12:38:39.648590 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =48
3980 12:38:39.648672 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
3981 12:38:39.655418 DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =40
3982 12:38:39.655501
3983 12:38:39.655569
3984 12:38:39.661609 [DQSOSCAuto] RK0, (LSB)MR18= 0x5b5b, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
3985 12:38:39.665143 CH0 RK0: MR19=808, MR18=5B5B
3986 12:38:39.671383 CH0_RK0: MR19=0x808, MR18=0x5B5B, DQSOSC=392, MR23=63, INC=170, DEC=113
3987 12:38:39.671501
3988 12:38:39.675759 ----->DramcWriteLeveling(PI) begin...
3989 12:38:39.675869 ==
3990 12:38:39.678343 Dram Type= 6, Freq= 0, CH_0, rank 1
3991 12:38:39.681431 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3992 12:38:39.681532 ==
3993 12:38:39.684698 Write leveling (Byte 0): 31 => 31
3994 12:38:39.688252 Write leveling (Byte 1): 30 => 30
3995 12:38:39.691529 DramcWriteLeveling(PI) end<-----
3996 12:38:39.691611
3997 12:38:39.691675 ==
3998 12:38:39.694946 Dram Type= 6, Freq= 0, CH_0, rank 1
3999 12:38:39.698072 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4000 12:38:39.698155 ==
4001 12:38:39.700955 [Gating] SW mode calibration
4002 12:38:39.707998 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4003 12:38:39.714799 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4004 12:38:39.717820 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4005 12:38:39.724341 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4006 12:38:39.728256 0 5 8 | B1->B0 | 3232 2f2f | 0 0 | (0 1) (1 1)
4007 12:38:39.731143 0 5 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4008 12:38:39.738020 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 12:38:39.740866 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 12:38:39.744875 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 12:38:39.750770 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 12:38:39.754313 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 12:38:39.757546 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 12:38:39.760649 0 6 8 | B1->B0 | 2c2c 3232 | 0 0 | (0 0) (0 0)
4015 12:38:39.767420 0 6 12 | B1->B0 | 4545 4242 | 0 0 | (0 0) (0 0)
4016 12:38:39.770674 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 12:38:39.774001 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 12:38:39.781057 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 12:38:39.783848 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 12:38:39.787195 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 12:38:39.793992 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 12:38:39.797475 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4023 12:38:39.800540 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4024 12:38:39.807650 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 12:38:39.810457 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 12:38:39.814265 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 12:38:39.820641 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 12:38:39.824185 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 12:38:39.827577 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 12:38:39.833824 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 12:38:39.837593 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 12:38:39.841204 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 12:38:39.847886 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 12:38:39.850836 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 12:38:39.853539 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 12:38:39.860016 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 12:38:39.863806 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4038 12:38:39.867691 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4039 12:38:39.873700 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 12:38:39.873785 Total UI for P1: 0, mck2ui 16
4041 12:38:39.880045 best dqsien dly found for B0: ( 0, 9, 10)
4042 12:38:39.880129 Total UI for P1: 0, mck2ui 16
4043 12:38:39.886752 best dqsien dly found for B1: ( 0, 9, 6)
4044 12:38:39.889938 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
4045 12:38:39.893640 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4046 12:38:39.893724
4047 12:38:39.896593 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
4048 12:38:39.900187 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4049 12:38:39.903437 [Gating] SW calibration Done
4050 12:38:39.903519 ==
4051 12:38:39.906633 Dram Type= 6, Freq= 0, CH_0, rank 1
4052 12:38:39.909832 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4053 12:38:39.909942 ==
4054 12:38:39.913960 RX Vref Scan: 0
4055 12:38:39.914043
4056 12:38:39.914108 RX Vref 0 -> 0, step: 1
4057 12:38:39.914168
4058 12:38:39.917377 RX Delay -230 -> 252, step: 16
4059 12:38:39.923188 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4060 12:38:39.926289 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4061 12:38:39.929860 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4062 12:38:39.933023 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4063 12:38:39.936696 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4064 12:38:39.943137 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4065 12:38:39.946820 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4066 12:38:39.949259 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4067 12:38:39.953250 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4068 12:38:39.959404 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4069 12:38:39.963068 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4070 12:38:39.966401 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4071 12:38:39.969113 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4072 12:38:39.976232 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4073 12:38:39.979352 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4074 12:38:39.983422 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4075 12:38:39.983505 ==
4076 12:38:39.985930 Dram Type= 6, Freq= 0, CH_0, rank 1
4077 12:38:39.988917 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4078 12:38:39.992312 ==
4079 12:38:39.992395 DQS Delay:
4080 12:38:39.992459 DQS0 = 0, DQS1 = 0
4081 12:38:39.995959 DQM Delay:
4082 12:38:39.996042 DQM0 = 43, DQM1 = 33
4083 12:38:39.999304 DQ Delay:
4084 12:38:39.999388 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =33
4085 12:38:40.003242 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4086 12:38:40.006086 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4087 12:38:40.009101 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4088 12:38:40.009184
4089 12:38:40.012521
4090 12:38:40.012628 ==
4091 12:38:40.015736 Dram Type= 6, Freq= 0, CH_0, rank 1
4092 12:38:40.019003 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4093 12:38:40.019086 ==
4094 12:38:40.019150
4095 12:38:40.019209
4096 12:38:40.022695 TX Vref Scan disable
4097 12:38:40.022779 == TX Byte 0 ==
4098 12:38:40.028844 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4099 12:38:40.032464 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4100 12:38:40.032577 == TX Byte 1 ==
4101 12:38:40.039503 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4102 12:38:40.042265 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4103 12:38:40.042349 ==
4104 12:38:40.045560 Dram Type= 6, Freq= 0, CH_0, rank 1
4105 12:38:40.048783 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4106 12:38:40.048867 ==
4107 12:38:40.048931
4108 12:38:40.048991
4109 12:38:40.052288 TX Vref Scan disable
4110 12:38:40.055446 == TX Byte 0 ==
4111 12:38:40.059383 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4112 12:38:40.061863 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4113 12:38:40.066121 == TX Byte 1 ==
4114 12:38:40.068984 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4115 12:38:40.072251 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4116 12:38:40.072334
4117 12:38:40.075459 [DATLAT]
4118 12:38:40.075567 Freq=600, CH0 RK1
4119 12:38:40.075659
4120 12:38:40.078778 DATLAT Default: 0x8
4121 12:38:40.078860 0, 0xFFFF, sum = 0
4122 12:38:40.082326 1, 0xFFFF, sum = 0
4123 12:38:40.082411 2, 0xFFFF, sum = 0
4124 12:38:40.085170 3, 0xFFFF, sum = 0
4125 12:38:40.085253 4, 0xFFFF, sum = 0
4126 12:38:40.089014 5, 0xFFFF, sum = 0
4127 12:38:40.089098 6, 0xFFFF, sum = 0
4128 12:38:40.091944 7, 0x0, sum = 1
4129 12:38:40.092027 8, 0x0, sum = 2
4130 12:38:40.095403 9, 0x0, sum = 3
4131 12:38:40.095486 10, 0x0, sum = 4
4132 12:38:40.099012 best_step = 8
4133 12:38:40.099125
4134 12:38:40.099191 ==
4135 12:38:40.102534 Dram Type= 6, Freq= 0, CH_0, rank 1
4136 12:38:40.105069 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4137 12:38:40.105152 ==
4138 12:38:40.108811 RX Vref Scan: 0
4139 12:38:40.108893
4140 12:38:40.108957 RX Vref 0 -> 0, step: 1
4141 12:38:40.109017
4142 12:38:40.111958 RX Delay -195 -> 252, step: 8
4143 12:38:40.118581 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4144 12:38:40.122172 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4145 12:38:40.126487 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4146 12:38:40.128887 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4147 12:38:40.135600 iDelay=205, Bit 4, Center 48 (-107 ~ 204) 312
4148 12:38:40.139540 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4149 12:38:40.141918 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4150 12:38:40.145732 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4151 12:38:40.148235 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4152 12:38:40.155873 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4153 12:38:40.158267 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4154 12:38:40.162078 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4155 12:38:40.165145 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4156 12:38:40.171965 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4157 12:38:40.175449 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4158 12:38:40.178739 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4159 12:38:40.178822 ==
4160 12:38:40.181440 Dram Type= 6, Freq= 0, CH_0, rank 1
4161 12:38:40.188069 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4162 12:38:40.188155 ==
4163 12:38:40.188220 DQS Delay:
4164 12:38:40.188279 DQS0 = 0, DQS1 = 0
4165 12:38:40.191581 DQM Delay:
4166 12:38:40.191662 DQM0 = 42, DQM1 = 33
4167 12:38:40.194837 DQ Delay:
4168 12:38:40.198489 DQ0 =36, DQ1 =44, DQ2 =40, DQ3 =36
4169 12:38:40.198571 DQ4 =48, DQ5 =32, DQ6 =48, DQ7 =52
4170 12:38:40.201832 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4171 12:38:40.205115 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4172 12:38:40.208450
4173 12:38:40.208532
4174 12:38:40.215491 [DQSOSCAuto] RK1, (LSB)MR18= 0x6565, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
4175 12:38:40.218273 CH0 RK1: MR19=808, MR18=6565
4176 12:38:40.225589 CH0_RK1: MR19=0x808, MR18=0x6565, DQSOSC=390, MR23=63, INC=172, DEC=114
4177 12:38:40.228003 [RxdqsGatingPostProcess] freq 600
4178 12:38:40.231826 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4179 12:38:40.234812 Pre-setting of DQS Precalculation
4180 12:38:40.240922 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4181 12:38:40.241007 ==
4182 12:38:40.244901 Dram Type= 6, Freq= 0, CH_1, rank 0
4183 12:38:40.247630 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4184 12:38:40.247713 ==
4185 12:38:40.254183 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4186 12:38:40.261388 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4187 12:38:40.264575 [CA 0] Center 35 (5~66) winsize 62
4188 12:38:40.267351 [CA 1] Center 35 (5~66) winsize 62
4189 12:38:40.271413 [CA 2] Center 33 (3~64) winsize 62
4190 12:38:40.273908 [CA 3] Center 33 (3~64) winsize 62
4191 12:38:40.277977 [CA 4] Center 33 (2~64) winsize 63
4192 12:38:40.278061 [CA 5] Center 33 (2~64) winsize 63
4193 12:38:40.281814
4194 12:38:40.284361 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4195 12:38:40.284444
4196 12:38:40.287426 [CATrainingPosCal] consider 1 rank data
4197 12:38:40.290929 u2DelayCellTimex100 = 270/100 ps
4198 12:38:40.294108 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4199 12:38:40.297618 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4200 12:38:40.300568 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4201 12:38:40.303960 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4202 12:38:40.307531 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4203 12:38:40.311099 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4204 12:38:40.311185
4205 12:38:40.314457 CA PerBit enable=1, Macro0, CA PI delay=33
4206 12:38:40.316982
4207 12:38:40.317065 [CBTSetCACLKResult] CA Dly = 33
4208 12:38:40.320487 CS Dly: 4 (0~35)
4209 12:38:40.320569 ==
4210 12:38:40.324034 Dram Type= 6, Freq= 0, CH_1, rank 1
4211 12:38:40.327413 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4212 12:38:40.327516 ==
4213 12:38:40.334657 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4214 12:38:40.340696 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4215 12:38:40.343964 [CA 0] Center 35 (5~65) winsize 61
4216 12:38:40.347119 [CA 1] Center 34 (4~65) winsize 62
4217 12:38:40.350936 [CA 2] Center 33 (3~64) winsize 62
4218 12:38:40.353819 [CA 3] Center 33 (3~64) winsize 62
4219 12:38:40.357148 [CA 4] Center 32 (2~63) winsize 62
4220 12:38:40.360797 [CA 5] Center 32 (2~63) winsize 62
4221 12:38:40.360881
4222 12:38:40.364567 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4223 12:38:40.364649
4224 12:38:40.367089 [CATrainingPosCal] consider 2 rank data
4225 12:38:40.370144 u2DelayCellTimex100 = 270/100 ps
4226 12:38:40.374295 CA0 delay=35 (5~65),Diff = 3 PI (28 cell)
4227 12:38:40.376867 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4228 12:38:40.380299 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4229 12:38:40.383463 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4230 12:38:40.387126 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4231 12:38:40.390733 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4232 12:38:40.390816
4233 12:38:40.396899 CA PerBit enable=1, Macro0, CA PI delay=32
4234 12:38:40.396982
4235 12:38:40.400136 [CBTSetCACLKResult] CA Dly = 32
4236 12:38:40.400218 CS Dly: 4 (0~36)
4237 12:38:40.400284
4238 12:38:40.404580 ----->DramcWriteLeveling(PI) begin...
4239 12:38:40.404692 ==
4240 12:38:40.406728 Dram Type= 6, Freq= 0, CH_1, rank 0
4241 12:38:40.410317 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4242 12:38:40.410401 ==
4243 12:38:40.413138 Write leveling (Byte 0): 29 => 29
4244 12:38:40.416895 Write leveling (Byte 1): 29 => 29
4245 12:38:40.419877 DramcWriteLeveling(PI) end<-----
4246 12:38:40.419959
4247 12:38:40.420022 ==
4248 12:38:40.423257 Dram Type= 6, Freq= 0, CH_1, rank 0
4249 12:38:40.429640 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4250 12:38:40.429745 ==
4251 12:38:40.429810 [Gating] SW mode calibration
4252 12:38:40.440005 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4253 12:38:40.443578 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4254 12:38:40.447574 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4255 12:38:40.453260 0 5 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
4256 12:38:40.456427 0 5 8 | B1->B0 | 2c2c 2525 | 0 0 | (0 1) (0 1)
4257 12:38:40.460151 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4258 12:38:40.466412 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4259 12:38:40.469545 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4260 12:38:40.472972 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4261 12:38:40.480493 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4262 12:38:40.483190 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4263 12:38:40.486137 0 6 4 | B1->B0 | 2424 3030 | 0 0 | (0 0) (1 1)
4264 12:38:40.492597 0 6 8 | B1->B0 | 3636 4141 | 0 0 | (0 0) (0 0)
4265 12:38:40.495931 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4266 12:38:40.499554 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4267 12:38:40.506287 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4268 12:38:40.509282 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4269 12:38:40.512821 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4270 12:38:40.519506 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4271 12:38:40.522521 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4272 12:38:40.525776 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4273 12:38:40.532216 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 12:38:40.536002 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 12:38:40.539179 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 12:38:40.545527 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 12:38:40.548848 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 12:38:40.551907 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 12:38:40.558777 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 12:38:40.562064 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 12:38:40.565779 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 12:38:40.572513 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 12:38:40.575095 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 12:38:40.578796 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 12:38:40.585605 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 12:38:40.588526 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 12:38:40.591799 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 12:38:40.598526 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4289 12:38:40.598611 Total UI for P1: 0, mck2ui 16
4290 12:38:40.605103 best dqsien dly found for B0: ( 0, 9, 6)
4291 12:38:40.608434 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4292 12:38:40.612332 Total UI for P1: 0, mck2ui 16
4293 12:38:40.615336 best dqsien dly found for B1: ( 0, 9, 8)
4294 12:38:40.618766 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4295 12:38:40.622537 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4296 12:38:40.622619
4297 12:38:40.625788 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4298 12:38:40.628718 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4299 12:38:40.631663 [Gating] SW calibration Done
4300 12:38:40.631770 ==
4301 12:38:40.635484 Dram Type= 6, Freq= 0, CH_1, rank 0
4302 12:38:40.638480 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4303 12:38:40.641317 ==
4304 12:38:40.641412 RX Vref Scan: 0
4305 12:38:40.641504
4306 12:38:40.644765 RX Vref 0 -> 0, step: 1
4307 12:38:40.644860
4308 12:38:40.648432 RX Delay -230 -> 252, step: 16
4309 12:38:40.652167 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4310 12:38:40.654568 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4311 12:38:40.658264 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4312 12:38:40.664992 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4313 12:38:40.667996 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4314 12:38:40.671006 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4315 12:38:40.674180 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4316 12:38:40.678351 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4317 12:38:40.685044 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4318 12:38:40.687841 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4319 12:38:40.690816 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4320 12:38:40.694556 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4321 12:38:40.701001 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4322 12:38:40.704508 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4323 12:38:40.708197 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4324 12:38:40.710998 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4325 12:38:40.713834 ==
4326 12:38:40.717664 Dram Type= 6, Freq= 0, CH_1, rank 0
4327 12:38:40.720806 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4328 12:38:40.720889 ==
4329 12:38:40.720954 DQS Delay:
4330 12:38:40.724420 DQS0 = 0, DQS1 = 0
4331 12:38:40.724503 DQM Delay:
4332 12:38:40.727061 DQM0 = 39, DQM1 = 30
4333 12:38:40.727144 DQ Delay:
4334 12:38:40.730581 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4335 12:38:40.734568 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4336 12:38:40.736986 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4337 12:38:40.740189 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =41
4338 12:38:40.740286
4339 12:38:40.740373
4340 12:38:40.740459 ==
4341 12:38:40.743877 Dram Type= 6, Freq= 0, CH_1, rank 0
4342 12:38:40.747319 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4343 12:38:40.747416 ==
4344 12:38:40.747507
4345 12:38:40.747592
4346 12:38:40.750347 TX Vref Scan disable
4347 12:38:40.754055 == TX Byte 0 ==
4348 12:38:40.756991 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4349 12:38:40.760636 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4350 12:38:40.764481 == TX Byte 1 ==
4351 12:38:40.767836 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4352 12:38:40.771179 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4353 12:38:40.771278 ==
4354 12:38:40.773850 Dram Type= 6, Freq= 0, CH_1, rank 0
4355 12:38:40.780102 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4356 12:38:40.780202 ==
4357 12:38:40.780292
4358 12:38:40.780380
4359 12:38:40.780463 TX Vref Scan disable
4360 12:38:40.784369 == TX Byte 0 ==
4361 12:38:40.787887 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4362 12:38:40.794166 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4363 12:38:40.794271 == TX Byte 1 ==
4364 12:38:40.797465 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4365 12:38:40.803997 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4366 12:38:40.804202
4367 12:38:40.804289 [DATLAT]
4368 12:38:40.804350 Freq=600, CH1 RK0
4369 12:38:40.804409
4370 12:38:40.807290 DATLAT Default: 0x9
4371 12:38:40.807374 0, 0xFFFF, sum = 0
4372 12:38:40.810575 1, 0xFFFF, sum = 0
4373 12:38:40.814136 2, 0xFFFF, sum = 0
4374 12:38:40.814248 3, 0xFFFF, sum = 0
4375 12:38:40.817029 4, 0xFFFF, sum = 0
4376 12:38:40.817125 5, 0xFFFF, sum = 0
4377 12:38:40.820325 6, 0xFFFF, sum = 0
4378 12:38:40.820421 7, 0x0, sum = 1
4379 12:38:40.824826 8, 0x0, sum = 2
4380 12:38:40.824936 9, 0x0, sum = 3
4381 12:38:40.825036 10, 0x0, sum = 4
4382 12:38:40.827779 best_step = 8
4383 12:38:40.827877
4384 12:38:40.827972 ==
4385 12:38:40.830669 Dram Type= 6, Freq= 0, CH_1, rank 0
4386 12:38:40.834097 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4387 12:38:40.834177 ==
4388 12:38:40.837100 RX Vref Scan: 1
4389 12:38:40.837182
4390 12:38:40.837246 RX Vref 0 -> 0, step: 1
4391 12:38:40.837306
4392 12:38:40.841270 RX Delay -195 -> 252, step: 8
4393 12:38:40.841363
4394 12:38:40.843822 Set Vref, RX VrefLevel [Byte0]: 56
4395 12:38:40.847213 [Byte1]: 48
4396 12:38:40.851441
4397 12:38:40.851555 Final RX Vref Byte 0 = 56 to rank0
4398 12:38:40.854564 Final RX Vref Byte 1 = 48 to rank0
4399 12:38:40.857800 Final RX Vref Byte 0 = 56 to rank1
4400 12:38:40.862007 Final RX Vref Byte 1 = 48 to rank1==
4401 12:38:40.864383 Dram Type= 6, Freq= 0, CH_1, rank 0
4402 12:38:40.871075 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4403 12:38:40.871164 ==
4404 12:38:40.871229 DQS Delay:
4405 12:38:40.874372 DQS0 = 0, DQS1 = 0
4406 12:38:40.874456 DQM Delay:
4407 12:38:40.874519 DQM0 = 38, DQM1 = 30
4408 12:38:40.877742 DQ Delay:
4409 12:38:40.880951 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4410 12:38:40.885288 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4411 12:38:40.888106 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4412 12:38:40.891086 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4413 12:38:40.891189
4414 12:38:40.891279
4415 12:38:40.897784 [DQSOSCAuto] RK0, (LSB)MR18= 0x7575, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
4416 12:38:40.901081 CH1 RK0: MR19=808, MR18=7575
4417 12:38:40.907877 CH1_RK0: MR19=0x808, MR18=0x7575, DQSOSC=387, MR23=63, INC=175, DEC=116
4418 12:38:40.907977
4419 12:38:40.910837 ----->DramcWriteLeveling(PI) begin...
4420 12:38:40.910938 ==
4421 12:38:40.914150 Dram Type= 6, Freq= 0, CH_1, rank 1
4422 12:38:40.917767 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4423 12:38:40.917877 ==
4424 12:38:40.920887 Write leveling (Byte 0): 27 => 27
4425 12:38:40.923989 Write leveling (Byte 1): 29 => 29
4426 12:38:40.927572 DramcWriteLeveling(PI) end<-----
4427 12:38:40.927649
4428 12:38:40.927712 ==
4429 12:38:40.930712 Dram Type= 6, Freq= 0, CH_1, rank 1
4430 12:38:40.933971 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4431 12:38:40.934057 ==
4432 12:38:40.937315 [Gating] SW mode calibration
4433 12:38:40.944245 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4434 12:38:40.950462 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4435 12:38:40.954042 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4436 12:38:40.960737 0 5 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
4437 12:38:40.964074 0 5 8 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
4438 12:38:40.967433 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4439 12:38:40.974009 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 12:38:40.978394 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 12:38:40.980242 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 12:38:40.987941 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 12:38:40.990934 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 12:38:40.994081 0 6 4 | B1->B0 | 2424 2f2f | 0 1 | (0 0) (0 0)
4445 12:38:41.000425 0 6 8 | B1->B0 | 3434 4141 | 0 0 | (0 0) (0 0)
4446 12:38:41.003997 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4447 12:38:41.007261 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 12:38:41.013842 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 12:38:41.017192 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 12:38:41.020291 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 12:38:41.023574 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 12:38:41.029892 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4453 12:38:41.033402 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4454 12:38:41.036946 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 12:38:41.043450 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 12:38:41.046720 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 12:38:41.049957 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 12:38:41.056791 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 12:38:41.059930 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 12:38:41.063388 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 12:38:41.070336 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 12:38:41.074131 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 12:38:41.076273 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 12:38:41.083427 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 12:38:41.086485 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 12:38:41.089695 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 12:38:41.098102 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 12:38:41.099987 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4469 12:38:41.103441 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4470 12:38:41.110022 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 12:38:41.112846 Total UI for P1: 0, mck2ui 16
4472 12:38:41.116073 best dqsien dly found for B0: ( 0, 9, 6)
4473 12:38:41.116157 Total UI for P1: 0, mck2ui 16
4474 12:38:41.122973 best dqsien dly found for B1: ( 0, 9, 6)
4475 12:38:41.126871 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4476 12:38:41.129434 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4477 12:38:41.129552
4478 12:38:41.133267 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4479 12:38:41.136552 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4480 12:38:41.139246 [Gating] SW calibration Done
4481 12:38:41.139404 ==
4482 12:38:41.142855 Dram Type= 6, Freq= 0, CH_1, rank 1
4483 12:38:41.145999 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4484 12:38:41.146122 ==
4485 12:38:41.149657 RX Vref Scan: 0
4486 12:38:41.149805
4487 12:38:41.149926 RX Vref 0 -> 0, step: 1
4488 12:38:41.150045
4489 12:38:41.152543 RX Delay -230 -> 252, step: 16
4490 12:38:41.159407 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4491 12:38:41.162590 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4492 12:38:41.165949 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4493 12:38:41.169289 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4494 12:38:41.172538 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4495 12:38:41.179731 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4496 12:38:41.182947 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4497 12:38:41.185872 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4498 12:38:41.189168 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4499 12:38:41.195778 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4500 12:38:41.198701 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4501 12:38:41.202376 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4502 12:38:41.205515 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4503 12:38:41.212017 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4504 12:38:41.215622 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4505 12:38:41.219124 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4506 12:38:41.219224 ==
4507 12:38:41.223105 Dram Type= 6, Freq= 0, CH_1, rank 1
4508 12:38:41.225273 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4509 12:38:41.225365 ==
4510 12:38:41.228906 DQS Delay:
4511 12:38:41.229015 DQS0 = 0, DQS1 = 0
4512 12:38:41.232622 DQM Delay:
4513 12:38:41.232749 DQM0 = 40, DQM1 = 33
4514 12:38:41.232835 DQ Delay:
4515 12:38:41.236451 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4516 12:38:41.239016 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4517 12:38:41.242186 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4518 12:38:41.245537 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4519 12:38:41.245624
4520 12:38:41.245690
4521 12:38:41.248637 ==
4522 12:38:41.252023 Dram Type= 6, Freq= 0, CH_1, rank 1
4523 12:38:41.255320 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4524 12:38:41.255418 ==
4525 12:38:41.255515
4526 12:38:41.255615
4527 12:38:41.258649 TX Vref Scan disable
4528 12:38:41.258732 == TX Byte 0 ==
4529 12:38:41.265124 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4530 12:38:41.268480 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4531 12:38:41.268573 == TX Byte 1 ==
4532 12:38:41.275375 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4533 12:38:41.278313 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4534 12:38:41.278396 ==
4535 12:38:41.281485 Dram Type= 6, Freq= 0, CH_1, rank 1
4536 12:38:41.284673 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4537 12:38:41.284790 ==
4538 12:38:41.284873
4539 12:38:41.284946
4540 12:38:41.289010 TX Vref Scan disable
4541 12:38:41.292277 == TX Byte 0 ==
4542 12:38:41.295567 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4543 12:38:41.298349 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4544 12:38:41.302288 == TX Byte 1 ==
4545 12:38:41.304697 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4546 12:38:41.308860 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4547 12:38:41.311222
4548 12:38:41.311304 [DATLAT]
4549 12:38:41.311369 Freq=600, CH1 RK1
4550 12:38:41.311430
4551 12:38:41.314944 DATLAT Default: 0x8
4552 12:38:41.315027 0, 0xFFFF, sum = 0
4553 12:38:41.318857 1, 0xFFFF, sum = 0
4554 12:38:41.318941 2, 0xFFFF, sum = 0
4555 12:38:41.321258 3, 0xFFFF, sum = 0
4556 12:38:41.321342 4, 0xFFFF, sum = 0
4557 12:38:41.324392 5, 0xFFFF, sum = 0
4558 12:38:41.328522 6, 0xFFFF, sum = 0
4559 12:38:41.328606 7, 0x0, sum = 1
4560 12:38:41.328672 8, 0x0, sum = 2
4561 12:38:41.331243 9, 0x0, sum = 3
4562 12:38:41.331334 10, 0x0, sum = 4
4563 12:38:41.334536 best_step = 8
4564 12:38:41.334635
4565 12:38:41.334731 ==
4566 12:38:41.337998 Dram Type= 6, Freq= 0, CH_1, rank 1
4567 12:38:41.341885 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4568 12:38:41.341986 ==
4569 12:38:41.344868 RX Vref Scan: 0
4570 12:38:41.344966
4571 12:38:41.345060 RX Vref 0 -> 0, step: 1
4572 12:38:41.345135
4573 12:38:41.347779 RX Delay -195 -> 252, step: 8
4574 12:38:41.355074 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4575 12:38:41.358527 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4576 12:38:41.361413 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4577 12:38:41.364962 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4578 12:38:41.371545 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4579 12:38:41.375987 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4580 12:38:41.378294 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4581 12:38:41.381396 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4582 12:38:41.388989 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4583 12:38:41.391079 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4584 12:38:41.394879 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4585 12:38:41.397725 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4586 12:38:41.401765 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4587 12:38:41.408214 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4588 12:38:41.412570 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4589 12:38:41.414378 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4590 12:38:41.414484 ==
4591 12:38:41.417927 Dram Type= 6, Freq= 0, CH_1, rank 1
4592 12:38:41.425014 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4593 12:38:41.425121 ==
4594 12:38:41.425188 DQS Delay:
4595 12:38:41.425249 DQS0 = 0, DQS1 = 0
4596 12:38:41.428059 DQM Delay:
4597 12:38:41.428126 DQM0 = 36, DQM1 = 30
4598 12:38:41.431259 DQ Delay:
4599 12:38:41.434635 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4600 12:38:41.437626 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4601 12:38:41.437708 DQ8 =16, DQ9 =20, DQ10 =28, DQ11 =20
4602 12:38:41.444418 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4603 12:38:41.444503
4604 12:38:41.444566
4605 12:38:41.451104 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f5f, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4606 12:38:41.454684 CH1 RK1: MR19=808, MR18=5F5F
4607 12:38:41.461740 CH1_RK1: MR19=0x808, MR18=0x5F5F, DQSOSC=391, MR23=63, INC=171, DEC=114
4608 12:38:41.464085 [RxdqsGatingPostProcess] freq 600
4609 12:38:41.467429 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4610 12:38:41.471097 Pre-setting of DQS Precalculation
4611 12:38:41.478283 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4612 12:38:41.483906 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4613 12:38:41.491231 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4614 12:38:41.491366
4615 12:38:41.491462
4616 12:38:41.494436 [Calibration Summary] 1200 Mbps
4617 12:38:41.494526 CH 0, Rank 0
4618 12:38:41.497566 SW Impedance : PASS
4619 12:38:41.502194 DUTY Scan : NO K
4620 12:38:41.502289 ZQ Calibration : PASS
4621 12:38:41.503814 Jitter Meter : NO K
4622 12:38:41.507741 CBT Training : PASS
4623 12:38:41.507830 Write leveling : PASS
4624 12:38:41.510550 RX DQS gating : PASS
4625 12:38:41.514469 RX DQ/DQS(RDDQC) : PASS
4626 12:38:41.514559 TX DQ/DQS : PASS
4627 12:38:41.517399 RX DATLAT : PASS
4628 12:38:41.520839 RX DQ/DQS(Engine): PASS
4629 12:38:41.520921 TX OE : NO K
4630 12:38:41.520991 All Pass.
4631 12:38:41.521056
4632 12:38:41.523755 CH 0, Rank 1
4633 12:38:41.523837 SW Impedance : PASS
4634 12:38:41.527292 DUTY Scan : NO K
4635 12:38:41.530410 ZQ Calibration : PASS
4636 12:38:41.530518 Jitter Meter : NO K
4637 12:38:41.533829 CBT Training : PASS
4638 12:38:41.537096 Write leveling : PASS
4639 12:38:41.537180 RX DQS gating : PASS
4640 12:38:41.540132 RX DQ/DQS(RDDQC) : PASS
4641 12:38:41.544257 TX DQ/DQS : PASS
4642 12:38:41.544403 RX DATLAT : PASS
4643 12:38:41.546709 RX DQ/DQS(Engine): PASS
4644 12:38:41.550721 TX OE : NO K
4645 12:38:41.550804 All Pass.
4646 12:38:41.550872
4647 12:38:41.550937 CH 1, Rank 0
4648 12:38:41.553836 SW Impedance : PASS
4649 12:38:41.556838 DUTY Scan : NO K
4650 12:38:41.556919 ZQ Calibration : PASS
4651 12:38:41.560860 Jitter Meter : NO K
4652 12:38:41.563704 CBT Training : PASS
4653 12:38:41.563810 Write leveling : PASS
4654 12:38:41.567038 RX DQS gating : PASS
4655 12:38:41.570377 RX DQ/DQS(RDDQC) : PASS
4656 12:38:41.570461 TX DQ/DQS : PASS
4657 12:38:41.573121 RX DATLAT : PASS
4658 12:38:41.576583 RX DQ/DQS(Engine): PASS
4659 12:38:41.576689 TX OE : NO K
4660 12:38:41.576880 All Pass.
4661 12:38:41.579928
4662 12:38:41.580009 CH 1, Rank 1
4663 12:38:41.583592 SW Impedance : PASS
4664 12:38:41.583675 DUTY Scan : NO K
4665 12:38:41.586770 ZQ Calibration : PASS
4666 12:38:41.586851 Jitter Meter : NO K
4667 12:38:41.590610 CBT Training : PASS
4668 12:38:41.593358 Write leveling : PASS
4669 12:38:41.593443 RX DQS gating : PASS
4670 12:38:41.596659 RX DQ/DQS(RDDQC) : PASS
4671 12:38:41.600256 TX DQ/DQS : PASS
4672 12:38:41.600364 RX DATLAT : PASS
4673 12:38:41.603235 RX DQ/DQS(Engine): PASS
4674 12:38:41.606932 TX OE : NO K
4675 12:38:41.607038 All Pass.
4676 12:38:41.607138
4677 12:38:41.609964 DramC Write-DBI off
4678 12:38:41.610081 PER_BANK_REFRESH: Hybrid Mode
4679 12:38:41.613802 TX_TRACKING: ON
4680 12:38:41.620056 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4681 12:38:41.626776 [FAST_K] Save calibration result to emmc
4682 12:38:41.629658 dramc_set_vcore_voltage set vcore to 662500
4683 12:38:41.629816 Read voltage for 933, 3
4684 12:38:41.633622 Vio18 = 0
4685 12:38:41.633802 Vcore = 662500
4686 12:38:41.633936 Vdram = 0
4687 12:38:41.636806 Vddq = 0
4688 12:38:41.636947 Vmddr = 0
4689 12:38:41.639721 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4690 12:38:41.646087 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4691 12:38:41.649479 MEM_TYPE=3, freq_sel=17
4692 12:38:41.652990 sv_algorithm_assistance_LP4_1600
4693 12:38:41.656105 ============ PULL DRAM RESETB DOWN ============
4694 12:38:41.659355 ========== PULL DRAM RESETB DOWN end =========
4695 12:38:41.666127 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4696 12:38:41.669546 ===================================
4697 12:38:41.669671 LPDDR4 DRAM CONFIGURATION
4698 12:38:41.672692 ===================================
4699 12:38:41.676699 EX_ROW_EN[0] = 0x0
4700 12:38:41.676829 EX_ROW_EN[1] = 0x0
4701 12:38:41.679957 LP4Y_EN = 0x0
4702 12:38:41.680067 WORK_FSP = 0x0
4703 12:38:41.682997 WL = 0x3
4704 12:38:41.683100 RL = 0x3
4705 12:38:41.686118 BL = 0x2
4706 12:38:41.689161 RPST = 0x0
4707 12:38:41.689274 RD_PRE = 0x0
4708 12:38:41.692798 WR_PRE = 0x1
4709 12:38:41.692920 WR_PST = 0x0
4710 12:38:41.696168 DBI_WR = 0x0
4711 12:38:41.696275 DBI_RD = 0x0
4712 12:38:41.699421 OTF = 0x1
4713 12:38:41.703425 ===================================
4714 12:38:41.706432 ===================================
4715 12:38:41.706517 ANA top config
4716 12:38:41.710452 ===================================
4717 12:38:41.712468 DLL_ASYNC_EN = 0
4718 12:38:41.715828 ALL_SLAVE_EN = 1
4719 12:38:41.715914 NEW_RANK_MODE = 1
4720 12:38:41.719890 DLL_IDLE_MODE = 1
4721 12:38:41.722513 LP45_APHY_COMB_EN = 1
4722 12:38:41.726741 TX_ODT_DIS = 1
4723 12:38:41.726842 NEW_8X_MODE = 1
4724 12:38:41.729290 ===================================
4725 12:38:41.733025 ===================================
4726 12:38:41.736252 data_rate = 1866
4727 12:38:41.739603 CKR = 1
4728 12:38:41.742619 DQ_P2S_RATIO = 8
4729 12:38:41.746924 ===================================
4730 12:38:41.748995 CA_P2S_RATIO = 8
4731 12:38:41.752643 DQ_CA_OPEN = 0
4732 12:38:41.752812 DQ_SEMI_OPEN = 0
4733 12:38:41.755645 CA_SEMI_OPEN = 0
4734 12:38:41.758859 CA_FULL_RATE = 0
4735 12:38:41.762326 DQ_CKDIV4_EN = 1
4736 12:38:41.766199 CA_CKDIV4_EN = 1
4737 12:38:41.768897 CA_PREDIV_EN = 0
4738 12:38:41.768994 PH8_DLY = 0
4739 12:38:41.772244 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4740 12:38:41.775785 DQ_AAMCK_DIV = 4
4741 12:38:41.779183 CA_AAMCK_DIV = 4
4742 12:38:41.782717 CA_ADMCK_DIV = 4
4743 12:38:41.785840 DQ_TRACK_CA_EN = 0
4744 12:38:41.789402 CA_PICK = 933
4745 12:38:41.789492 CA_MCKIO = 933
4746 12:38:41.792969 MCKIO_SEMI = 0
4747 12:38:41.796014 PLL_FREQ = 3732
4748 12:38:41.799174 DQ_UI_PI_RATIO = 32
4749 12:38:41.802581 CA_UI_PI_RATIO = 0
4750 12:38:41.805484 ===================================
4751 12:38:41.808752 ===================================
4752 12:38:41.812601 memory_type:LPDDR4
4753 12:38:41.812684 GP_NUM : 10
4754 12:38:41.816070 SRAM_EN : 1
4755 12:38:41.816150 MD32_EN : 0
4756 12:38:41.818541 ===================================
4757 12:38:41.822643 [ANA_INIT] >>>>>>>>>>>>>>
4758 12:38:41.825801 <<<<<< [CONFIGURE PHASE]: ANA_TX
4759 12:38:41.828571 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4760 12:38:41.831984 ===================================
4761 12:38:41.835228 data_rate = 1866,PCW = 0X8f00
4762 12:38:41.838882 ===================================
4763 12:38:41.841644 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4764 12:38:41.848944 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4765 12:38:41.851498 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4766 12:38:41.859415 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4767 12:38:41.861815 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4768 12:38:41.865309 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4769 12:38:41.865438 [ANA_INIT] flow start
4770 12:38:41.868277 [ANA_INIT] PLL >>>>>>>>
4771 12:38:41.871843 [ANA_INIT] PLL <<<<<<<<
4772 12:38:41.871925 [ANA_INIT] MIDPI >>>>>>>>
4773 12:38:41.874849 [ANA_INIT] MIDPI <<<<<<<<
4774 12:38:41.878456 [ANA_INIT] DLL >>>>>>>>
4775 12:38:41.878545 [ANA_INIT] flow end
4776 12:38:41.885109 ============ LP4 DIFF to SE enter ============
4777 12:38:41.888194 ============ LP4 DIFF to SE exit ============
4778 12:38:41.891737 [ANA_INIT] <<<<<<<<<<<<<
4779 12:38:41.894819 [Flow] Enable top DCM control >>>>>
4780 12:38:41.898364 [Flow] Enable top DCM control <<<<<
4781 12:38:41.898484 Enable DLL master slave shuffle
4782 12:38:41.904574 ==============================================================
4783 12:38:41.908472 Gating Mode config
4784 12:38:41.911605 ==============================================================
4785 12:38:41.915093 Config description:
4786 12:38:41.925292 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4787 12:38:41.931710 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4788 12:38:41.934724 SELPH_MODE 0: By rank 1: By Phase
4789 12:38:41.941360 ==============================================================
4790 12:38:41.944959 GAT_TRACK_EN = 1
4791 12:38:41.948170 RX_GATING_MODE = 2
4792 12:38:41.951223 RX_GATING_TRACK_MODE = 2
4793 12:38:41.954216 SELPH_MODE = 1
4794 12:38:41.954302 PICG_EARLY_EN = 1
4795 12:38:41.957734 VALID_LAT_VALUE = 1
4796 12:38:41.964340 ==============================================================
4797 12:38:41.967768 Enter into Gating configuration >>>>
4798 12:38:41.971260 Exit from Gating configuration <<<<
4799 12:38:41.975090 Enter into DVFS_PRE_config >>>>>
4800 12:38:41.984393 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4801 12:38:41.987949 Exit from DVFS_PRE_config <<<<<
4802 12:38:41.990972 Enter into PICG configuration >>>>
4803 12:38:41.994266 Exit from PICG configuration <<<<
4804 12:38:41.997374 [RX_INPUT] configuration >>>>>
4805 12:38:42.000534 [RX_INPUT] configuration <<<<<
4806 12:38:42.004725 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4807 12:38:42.010831 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4808 12:38:42.017155 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4809 12:38:42.023736 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4810 12:38:42.030854 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4811 12:38:42.037179 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4812 12:38:42.040552 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4813 12:38:42.044341 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4814 12:38:42.047521 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4815 12:38:42.050605 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4816 12:38:42.057939 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4817 12:38:42.060690 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4818 12:38:42.063664 ===================================
4819 12:38:42.067109 LPDDR4 DRAM CONFIGURATION
4820 12:38:42.070583 ===================================
4821 12:38:42.070675 EX_ROW_EN[0] = 0x0
4822 12:38:42.073591 EX_ROW_EN[1] = 0x0
4823 12:38:42.073702 LP4Y_EN = 0x0
4824 12:38:42.076735 WORK_FSP = 0x0
4825 12:38:42.076880 WL = 0x3
4826 12:38:42.080570 RL = 0x3
4827 12:38:42.083747 BL = 0x2
4828 12:38:42.083828 RPST = 0x0
4829 12:38:42.086694 RD_PRE = 0x0
4830 12:38:42.086775 WR_PRE = 0x1
4831 12:38:42.090758 WR_PST = 0x0
4832 12:38:42.090839 DBI_WR = 0x0
4833 12:38:42.093466 DBI_RD = 0x0
4834 12:38:42.093635 OTF = 0x1
4835 12:38:42.097238 ===================================
4836 12:38:42.100194 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4837 12:38:42.106579 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4838 12:38:42.110173 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4839 12:38:42.113144 ===================================
4840 12:38:42.117087 LPDDR4 DRAM CONFIGURATION
4841 12:38:42.120420 ===================================
4842 12:38:42.120501 EX_ROW_EN[0] = 0x10
4843 12:38:42.123477 EX_ROW_EN[1] = 0x0
4844 12:38:42.123556 LP4Y_EN = 0x0
4845 12:38:42.126662 WORK_FSP = 0x0
4846 12:38:42.126742 WL = 0x3
4847 12:38:42.129897 RL = 0x3
4848 12:38:42.133680 BL = 0x2
4849 12:38:42.133770 RPST = 0x0
4850 12:38:42.137033 RD_PRE = 0x0
4851 12:38:42.137134 WR_PRE = 0x1
4852 12:38:42.140146 WR_PST = 0x0
4853 12:38:42.140215 DBI_WR = 0x0
4854 12:38:42.143078 DBI_RD = 0x0
4855 12:38:42.143160 OTF = 0x1
4856 12:38:42.147203 ===================================
4857 12:38:42.153144 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4858 12:38:42.157108 nWR fixed to 30
4859 12:38:42.160171 [ModeRegInit_LP4] CH0 RK0
4860 12:38:42.160273 [ModeRegInit_LP4] CH0 RK1
4861 12:38:42.163237 [ModeRegInit_LP4] CH1 RK0
4862 12:38:42.166941 [ModeRegInit_LP4] CH1 RK1
4863 12:38:42.167023 match AC timing 8
4864 12:38:42.174667 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4865 12:38:42.176911 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4866 12:38:42.180063 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4867 12:38:42.186825 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4868 12:38:42.190193 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4869 12:38:42.190274 ==
4870 12:38:42.193550 Dram Type= 6, Freq= 0, CH_0, rank 0
4871 12:38:42.196844 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4872 12:38:42.196925 ==
4873 12:38:42.203244 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4874 12:38:42.210344 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4875 12:38:42.213205 [CA 0] Center 38 (8~69) winsize 62
4876 12:38:42.216972 [CA 1] Center 38 (7~69) winsize 63
4877 12:38:42.219626 [CA 2] Center 36 (6~67) winsize 62
4878 12:38:42.223277 [CA 3] Center 36 (6~66) winsize 61
4879 12:38:42.226326 [CA 4] Center 34 (4~65) winsize 62
4880 12:38:42.230007 [CA 5] Center 34 (4~65) winsize 62
4881 12:38:42.230087
4882 12:38:42.233318 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4883 12:38:42.233399
4884 12:38:42.236538 [CATrainingPosCal] consider 1 rank data
4885 12:38:42.240312 u2DelayCellTimex100 = 270/100 ps
4886 12:38:42.243264 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4887 12:38:42.246304 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
4888 12:38:42.249686 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4889 12:38:42.253005 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4890 12:38:42.256181 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4891 12:38:42.262849 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4892 12:38:42.263025
4893 12:38:42.266626 CA PerBit enable=1, Macro0, CA PI delay=34
4894 12:38:42.266734
4895 12:38:42.269205 [CBTSetCACLKResult] CA Dly = 34
4896 12:38:42.269298 CS Dly: 7 (0~38)
4897 12:38:42.269365 ==
4898 12:38:42.272594 Dram Type= 6, Freq= 0, CH_0, rank 1
4899 12:38:42.279199 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4900 12:38:42.279328 ==
4901 12:38:42.282498 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4902 12:38:42.289159 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4903 12:38:42.292506 [CA 0] Center 38 (8~69) winsize 62
4904 12:38:42.295349 [CA 1] Center 38 (7~69) winsize 63
4905 12:38:42.300536 [CA 2] Center 36 (5~67) winsize 63
4906 12:38:42.302959 [CA 3] Center 35 (5~66) winsize 62
4907 12:38:42.305382 [CA 4] Center 34 (4~65) winsize 62
4908 12:38:42.308814 [CA 5] Center 34 (4~65) winsize 62
4909 12:38:42.308909
4910 12:38:42.311854 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4911 12:38:42.311939
4912 12:38:42.315598 [CATrainingPosCal] consider 2 rank data
4913 12:38:42.318749 u2DelayCellTimex100 = 270/100 ps
4914 12:38:42.322350 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4915 12:38:42.325809 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
4916 12:38:42.328907 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4917 12:38:42.335752 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4918 12:38:42.340942 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4919 12:38:42.342492 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4920 12:38:42.342574
4921 12:38:42.345383 CA PerBit enable=1, Macro0, CA PI delay=34
4922 12:38:42.345466
4923 12:38:42.349081 [CBTSetCACLKResult] CA Dly = 34
4924 12:38:42.349164 CS Dly: 7 (0~39)
4925 12:38:42.349227
4926 12:38:42.352125 ----->DramcWriteLeveling(PI) begin...
4927 12:38:42.355346 ==
4928 12:38:42.355428 Dram Type= 6, Freq= 0, CH_0, rank 0
4929 12:38:42.363464 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4930 12:38:42.363549 ==
4931 12:38:42.365959 Write leveling (Byte 0): 27 => 27
4932 12:38:42.368854 Write leveling (Byte 1): 27 => 27
4933 12:38:42.371905 DramcWriteLeveling(PI) end<-----
4934 12:38:42.371987
4935 12:38:42.372050 ==
4936 12:38:42.375602 Dram Type= 6, Freq= 0, CH_0, rank 0
4937 12:38:42.379314 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4938 12:38:42.379396 ==
4939 12:38:42.382218 [Gating] SW mode calibration
4940 12:38:42.388745 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4941 12:38:42.395953 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4942 12:38:42.398558 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4943 12:38:42.401895 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4944 12:38:42.405193 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4945 12:38:42.412330 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4946 12:38:42.415283 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4947 12:38:42.422398 0 10 20 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
4948 12:38:42.425644 0 10 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4949 12:38:42.428223 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4950 12:38:42.434790 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4951 12:38:42.438493 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4952 12:38:42.441633 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4953 12:38:42.448044 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4954 12:38:42.451449 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4955 12:38:42.454732 0 11 20 | B1->B0 | 2323 2f2f | 1 0 | (0 0) (0 0)
4956 12:38:42.458344 0 11 24 | B1->B0 | 3939 4141 | 0 0 | (1 1) (0 0)
4957 12:38:42.464838 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4958 12:38:42.467787 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4959 12:38:42.470942 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4960 12:38:42.478558 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4961 12:38:42.481464 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4962 12:38:42.484633 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4963 12:38:42.491186 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4964 12:38:42.494211 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4965 12:38:42.498504 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4966 12:38:42.504747 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4967 12:38:42.507930 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4968 12:38:42.511016 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4969 12:38:42.518371 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4970 12:38:42.521484 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4971 12:38:42.524674 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4972 12:38:42.530905 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4973 12:38:42.534683 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4974 12:38:42.537605 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4975 12:38:42.544250 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4976 12:38:42.547540 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4977 12:38:42.550768 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4978 12:38:42.557773 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4979 12:38:42.560684 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4980 12:38:42.564000 Total UI for P1: 0, mck2ui 16
4981 12:38:42.567818 best dqsien dly found for B1: ( 0, 14, 18)
4982 12:38:42.570752 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4983 12:38:42.574183 Total UI for P1: 0, mck2ui 16
4984 12:38:42.577158 best dqsien dly found for B0: ( 0, 14, 20)
4985 12:38:42.581204 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
4986 12:38:42.584436 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
4987 12:38:42.584516
4988 12:38:42.590875 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
4989 12:38:42.593822 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
4990 12:38:42.593903 [Gating] SW calibration Done
4991 12:38:42.597147 ==
4992 12:38:42.600924 Dram Type= 6, Freq= 0, CH_0, rank 0
4993 12:38:42.603835 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4994 12:38:42.603915 ==
4995 12:38:42.603978 RX Vref Scan: 0
4996 12:38:42.604037
4997 12:38:42.607756 RX Vref 0 -> 0, step: 1
4998 12:38:42.607836
4999 12:38:42.610888 RX Delay -80 -> 252, step: 8
5000 12:38:42.614001 iDelay=200, Bit 0, Center 91 (-8 ~ 191) 200
5001 12:38:42.617587 iDelay=200, Bit 1, Center 95 (0 ~ 191) 192
5002 12:38:42.621511 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200
5003 12:38:42.627458 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5004 12:38:42.630644 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5005 12:38:42.633996 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5006 12:38:42.637229 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5007 12:38:42.640368 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5008 12:38:42.643799 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5009 12:38:42.650682 iDelay=200, Bit 9, Center 71 (-24 ~ 167) 192
5010 12:38:42.654521 iDelay=200, Bit 10, Center 83 (-16 ~ 183) 200
5011 12:38:42.658231 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5012 12:38:42.661226 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5013 12:38:42.664464 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5014 12:38:42.670613 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5015 12:38:42.673603 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5016 12:38:42.673686 ==
5017 12:38:42.676972 Dram Type= 6, Freq= 0, CH_0, rank 0
5018 12:38:42.680373 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5019 12:38:42.680480 ==
5020 12:38:42.680551 DQS Delay:
5021 12:38:42.683925 DQS0 = 0, DQS1 = 0
5022 12:38:42.684019 DQM Delay:
5023 12:38:42.687039 DQM0 = 95, DQM1 = 86
5024 12:38:42.687141 DQ Delay:
5025 12:38:42.690045 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5026 12:38:42.693527 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5027 12:38:42.696501 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =79
5028 12:38:42.700277 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5029 12:38:42.700359
5030 12:38:42.700422
5031 12:38:42.700482 ==
5032 12:38:42.704027 Dram Type= 6, Freq= 0, CH_0, rank 0
5033 12:38:42.709941 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5034 12:38:42.710051 ==
5035 12:38:42.710149
5036 12:38:42.710238
5037 12:38:42.710304 TX Vref Scan disable
5038 12:38:42.713634 == TX Byte 0 ==
5039 12:38:42.716747 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5040 12:38:42.723409 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5041 12:38:42.723490 == TX Byte 1 ==
5042 12:38:42.726589 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5043 12:38:42.733223 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5044 12:38:42.733310 ==
5045 12:38:42.736636 Dram Type= 6, Freq= 0, CH_0, rank 0
5046 12:38:42.739756 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5047 12:38:42.739837 ==
5048 12:38:42.739899
5049 12:38:42.739957
5050 12:38:42.743516 TX Vref Scan disable
5051 12:38:42.743596 == TX Byte 0 ==
5052 12:38:42.750235 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5053 12:38:42.753638 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5054 12:38:42.753718 == TX Byte 1 ==
5055 12:38:42.759641 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5056 12:38:42.762906 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5057 12:38:42.762986
5058 12:38:42.763049 [DATLAT]
5059 12:38:42.767366 Freq=933, CH0 RK0
5060 12:38:42.767446
5061 12:38:42.767509 DATLAT Default: 0xd
5062 12:38:42.770249 0, 0xFFFF, sum = 0
5063 12:38:42.770331 1, 0xFFFF, sum = 0
5064 12:38:42.773243 2, 0xFFFF, sum = 0
5065 12:38:42.776241 3, 0xFFFF, sum = 0
5066 12:38:42.776322 4, 0xFFFF, sum = 0
5067 12:38:42.780091 5, 0xFFFF, sum = 0
5068 12:38:42.780172 6, 0xFFFF, sum = 0
5069 12:38:42.783026 7, 0xFFFF, sum = 0
5070 12:38:42.783107 8, 0xFFFF, sum = 0
5071 12:38:42.786939 9, 0xFFFF, sum = 0
5072 12:38:42.787021 10, 0x0, sum = 1
5073 12:38:42.789814 11, 0x0, sum = 2
5074 12:38:42.789895 12, 0x0, sum = 3
5075 12:38:42.789959 13, 0x0, sum = 4
5076 12:38:42.792809 best_step = 11
5077 12:38:42.792888
5078 12:38:42.792950 ==
5079 12:38:42.796911 Dram Type= 6, Freq= 0, CH_0, rank 0
5080 12:38:42.799729 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5081 12:38:42.799809 ==
5082 12:38:42.802965 RX Vref Scan: 1
5083 12:38:42.803045
5084 12:38:42.806454 RX Vref 0 -> 0, step: 1
5085 12:38:42.806533
5086 12:38:42.806595 RX Delay -69 -> 252, step: 4
5087 12:38:42.806654
5088 12:38:42.809705 Set Vref, RX VrefLevel [Byte0]: 49
5089 12:38:42.812630 [Byte1]: 49
5090 12:38:42.818043
5091 12:38:42.818123 Final RX Vref Byte 0 = 49 to rank0
5092 12:38:42.820340 Final RX Vref Byte 1 = 49 to rank0
5093 12:38:42.823926 Final RX Vref Byte 0 = 49 to rank1
5094 12:38:42.827250 Final RX Vref Byte 1 = 49 to rank1==
5095 12:38:42.830305 Dram Type= 6, Freq= 0, CH_0, rank 0
5096 12:38:42.837143 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5097 12:38:42.837224 ==
5098 12:38:42.837287 DQS Delay:
5099 12:38:42.840128 DQS0 = 0, DQS1 = 0
5100 12:38:42.840208 DQM Delay:
5101 12:38:42.840271 DQM0 = 97, DQM1 = 86
5102 12:38:42.844729 DQ Delay:
5103 12:38:42.847920 DQ0 =92, DQ1 =100, DQ2 =96, DQ3 =94
5104 12:38:42.850199 DQ4 =102, DQ5 =86, DQ6 =104, DQ7 =104
5105 12:38:42.853612 DQ8 =78, DQ9 =70, DQ10 =86, DQ11 =78
5106 12:38:42.856868 DQ12 =94, DQ13 =94, DQ14 =96, DQ15 =96
5107 12:38:42.856948
5108 12:38:42.857011
5109 12:38:42.863292 [DQSOSCAuto] RK0, (LSB)MR18= 0x2222, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5110 12:38:42.866931 CH0 RK0: MR19=505, MR18=2222
5111 12:38:42.873366 CH0_RK0: MR19=0x505, MR18=0x2222, DQSOSC=411, MR23=63, INC=64, DEC=42
5112 12:38:42.873447
5113 12:38:42.877479 ----->DramcWriteLeveling(PI) begin...
5114 12:38:42.877563 ==
5115 12:38:42.880206 Dram Type= 6, Freq= 0, CH_0, rank 1
5116 12:38:42.883295 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5117 12:38:42.883376 ==
5118 12:38:42.886587 Write leveling (Byte 0): 28 => 28
5119 12:38:42.890319 Write leveling (Byte 1): 24 => 24
5120 12:38:42.893640 DramcWriteLeveling(PI) end<-----
5121 12:38:42.893720
5122 12:38:42.893783 ==
5123 12:38:42.897255 Dram Type= 6, Freq= 0, CH_0, rank 1
5124 12:38:42.900079 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5125 12:38:42.903317 ==
5126 12:38:42.903397 [Gating] SW mode calibration
5127 12:38:42.909966 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5128 12:38:42.916363 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5129 12:38:42.919589 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 12:38:42.926440 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 12:38:42.929661 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 12:38:42.933684 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 12:38:42.939748 0 10 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5134 12:38:42.943319 0 10 20 | B1->B0 | 3030 2e2e | 0 0 | (1 0) (0 0)
5135 12:38:42.946582 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5136 12:38:42.952863 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 12:38:42.956074 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 12:38:42.959673 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 12:38:42.966077 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 12:38:42.969996 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 12:38:42.973671 0 11 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5142 12:38:42.980218 0 11 20 | B1->B0 | 2b2b 3838 | 0 1 | (0 0) (1 1)
5143 12:38:42.982881 0 11 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5144 12:38:42.986915 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 12:38:42.992733 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 12:38:42.996147 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 12:38:42.999301 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 12:38:43.006359 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 12:38:43.009109 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 12:38:43.012612 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5151 12:38:43.019150 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 12:38:43.022345 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 12:38:43.025859 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 12:38:43.032218 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 12:38:43.035611 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 12:38:43.039918 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 12:38:43.045367 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 12:38:43.049029 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 12:38:43.052123 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 12:38:43.058406 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 12:38:43.062411 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 12:38:43.065277 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 12:38:43.072160 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 12:38:43.075066 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 12:38:43.078531 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 12:38:43.085803 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 12:38:43.088742 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 12:38:43.091841 Total UI for P1: 0, mck2ui 16
5169 12:38:43.095417 best dqsien dly found for B0: ( 0, 14, 22)
5170 12:38:43.098604 Total UI for P1: 0, mck2ui 16
5171 12:38:43.101435 best dqsien dly found for B1: ( 0, 14, 22)
5172 12:38:43.105470 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5173 12:38:43.108062 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5174 12:38:43.108151
5175 12:38:43.111678 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5176 12:38:43.115287 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5177 12:38:43.118186 [Gating] SW calibration Done
5178 12:38:43.118266 ==
5179 12:38:43.121312 Dram Type= 6, Freq= 0, CH_0, rank 1
5180 12:38:43.124674 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5181 12:38:43.127985 ==
5182 12:38:43.128066 RX Vref Scan: 0
5183 12:38:43.128129
5184 12:38:43.131476 RX Vref 0 -> 0, step: 1
5185 12:38:43.131557
5186 12:38:43.135064 RX Delay -80 -> 252, step: 8
5187 12:38:43.137916 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5188 12:38:43.141433 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5189 12:38:43.144873 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5190 12:38:43.148230 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5191 12:38:43.151408 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5192 12:38:43.157768 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5193 12:38:43.160994 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5194 12:38:43.165232 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5195 12:38:43.167589 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5196 12:38:43.171379 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5197 12:38:43.174494 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5198 12:38:43.181042 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5199 12:38:43.184178 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5200 12:38:43.187752 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5201 12:38:43.191025 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5202 12:38:43.193857 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5203 12:38:43.197684 ==
5204 12:38:43.200551 Dram Type= 6, Freq= 0, CH_0, rank 1
5205 12:38:43.203943 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5206 12:38:43.204047 ==
5207 12:38:43.204112 DQS Delay:
5208 12:38:43.208304 DQS0 = 0, DQS1 = 0
5209 12:38:43.208384 DQM Delay:
5210 12:38:43.210332 DQM0 = 96, DQM1 = 84
5211 12:38:43.210412 DQ Delay:
5212 12:38:43.214686 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =91
5213 12:38:43.217266 DQ4 =99, DQ5 =87, DQ6 =99, DQ7 =107
5214 12:38:43.220564 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =79
5215 12:38:43.224259 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5216 12:38:43.224339
5217 12:38:43.224401
5218 12:38:43.224459 ==
5219 12:38:43.227466 Dram Type= 6, Freq= 0, CH_0, rank 1
5220 12:38:43.231608 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5221 12:38:43.231688 ==
5222 12:38:43.231751
5223 12:38:43.233689
5224 12:38:43.233768 TX Vref Scan disable
5225 12:38:43.237339 == TX Byte 0 ==
5226 12:38:43.240581 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5227 12:38:43.243421 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5228 12:38:43.247441 == TX Byte 1 ==
5229 12:38:43.250244 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5230 12:38:43.253937 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5231 12:38:43.254017 ==
5232 12:38:43.256981 Dram Type= 6, Freq= 0, CH_0, rank 1
5233 12:38:43.263549 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5234 12:38:43.263630 ==
5235 12:38:43.263694
5236 12:38:43.263752
5237 12:38:43.263807 TX Vref Scan disable
5238 12:38:43.267935 == TX Byte 0 ==
5239 12:38:43.271435 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5240 12:38:43.277580 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5241 12:38:43.277662 == TX Byte 1 ==
5242 12:38:43.281015 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5243 12:38:43.287694 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5244 12:38:43.287776
5245 12:38:43.287840 [DATLAT]
5246 12:38:43.287899 Freq=933, CH0 RK1
5247 12:38:43.287957
5248 12:38:43.291211 DATLAT Default: 0xb
5249 12:38:43.291293 0, 0xFFFF, sum = 0
5250 12:38:43.294558 1, 0xFFFF, sum = 0
5251 12:38:43.297523 2, 0xFFFF, sum = 0
5252 12:38:43.297606 3, 0xFFFF, sum = 0
5253 12:38:43.300571 4, 0xFFFF, sum = 0
5254 12:38:43.300653 5, 0xFFFF, sum = 0
5255 12:38:43.303925 6, 0xFFFF, sum = 0
5256 12:38:43.304008 7, 0xFFFF, sum = 0
5257 12:38:43.307224 8, 0xFFFF, sum = 0
5258 12:38:43.307308 9, 0xFFFF, sum = 0
5259 12:38:43.310584 10, 0x0, sum = 1
5260 12:38:43.310666 11, 0x0, sum = 2
5261 12:38:43.314787 12, 0x0, sum = 3
5262 12:38:43.314870 13, 0x0, sum = 4
5263 12:38:43.314935 best_step = 11
5264 12:38:43.317666
5265 12:38:43.317747 ==
5266 12:38:43.320570 Dram Type= 6, Freq= 0, CH_0, rank 1
5267 12:38:43.324248 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5268 12:38:43.324331 ==
5269 12:38:43.324395 RX Vref Scan: 0
5270 12:38:43.324454
5271 12:38:43.327294 RX Vref 0 -> 0, step: 1
5272 12:38:43.327376
5273 12:38:43.330179 RX Delay -69 -> 252, step: 4
5274 12:38:43.334356 iDelay=203, Bit 0, Center 94 (3 ~ 186) 184
5275 12:38:43.340377 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5276 12:38:43.344290 iDelay=203, Bit 2, Center 98 (7 ~ 190) 184
5277 12:38:43.347518 iDelay=203, Bit 3, Center 92 (3 ~ 182) 180
5278 12:38:43.350750 iDelay=203, Bit 4, Center 102 (11 ~ 194) 184
5279 12:38:43.353614 iDelay=203, Bit 5, Center 88 (-5 ~ 182) 188
5280 12:38:43.360084 iDelay=203, Bit 6, Center 102 (11 ~ 194) 184
5281 12:38:43.363789 iDelay=203, Bit 7, Center 108 (15 ~ 202) 188
5282 12:38:43.366789 iDelay=203, Bit 8, Center 74 (-13 ~ 162) 176
5283 12:38:43.370610 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5284 12:38:43.373540 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5285 12:38:43.380691 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5286 12:38:43.383377 iDelay=203, Bit 12, Center 92 (3 ~ 182) 180
5287 12:38:43.387916 iDelay=203, Bit 13, Center 90 (-1 ~ 182) 184
5288 12:38:43.390035 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5289 12:38:43.393467 iDelay=203, Bit 15, Center 94 (3 ~ 186) 184
5290 12:38:43.393561 ==
5291 12:38:43.396964 Dram Type= 6, Freq= 0, CH_0, rank 1
5292 12:38:43.403260 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5293 12:38:43.403343 ==
5294 12:38:43.403408 DQS Delay:
5295 12:38:43.403468 DQS0 = 0, DQS1 = 0
5296 12:38:43.407333 DQM Delay:
5297 12:38:43.407415 DQM0 = 97, DQM1 = 85
5298 12:38:43.410914 DQ Delay:
5299 12:38:43.413845 DQ0 =94, DQ1 =98, DQ2 =98, DQ3 =92
5300 12:38:43.416930 DQ4 =102, DQ5 =88, DQ6 =102, DQ7 =108
5301 12:38:43.420693 DQ8 =74, DQ9 =72, DQ10 =88, DQ11 =78
5302 12:38:43.423042 DQ12 =92, DQ13 =90, DQ14 =98, DQ15 =94
5303 12:38:43.423124
5304 12:38:43.423187
5305 12:38:43.430215 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c2c, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5306 12:38:43.433659 CH0 RK1: MR19=505, MR18=2C2C
5307 12:38:43.440036 CH0_RK1: MR19=0x505, MR18=0x2C2C, DQSOSC=408, MR23=63, INC=65, DEC=43
5308 12:38:43.443409 [RxdqsGatingPostProcess] freq 933
5309 12:38:43.446416 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5310 12:38:43.450074 Pre-setting of DQS Precalculation
5311 12:38:43.456741 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5312 12:38:43.456837 ==
5313 12:38:43.460069 Dram Type= 6, Freq= 0, CH_1, rank 0
5314 12:38:43.462997 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5315 12:38:43.463079 ==
5316 12:38:43.470036 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5317 12:38:43.476511 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5318 12:38:43.479860 [CA 0] Center 37 (6~68) winsize 63
5319 12:38:43.483199 [CA 1] Center 37 (6~68) winsize 63
5320 12:38:43.486491 [CA 2] Center 35 (5~65) winsize 61
5321 12:38:43.489335 [CA 3] Center 34 (4~64) winsize 61
5322 12:38:43.492890 [CA 4] Center 33 (2~64) winsize 63
5323 12:38:43.492973 [CA 5] Center 33 (3~63) winsize 61
5324 12:38:43.496206
5325 12:38:43.499538 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5326 12:38:43.499621
5327 12:38:43.503006 [CATrainingPosCal] consider 1 rank data
5328 12:38:43.506918 u2DelayCellTimex100 = 270/100 ps
5329 12:38:43.509720 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5330 12:38:43.513046 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5331 12:38:43.516812 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5332 12:38:43.519845 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5333 12:38:43.523442 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5334 12:38:43.525954 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5335 12:38:43.526035
5336 12:38:43.530388 CA PerBit enable=1, Macro0, CA PI delay=33
5337 12:38:43.534273
5338 12:38:43.534354 [CBTSetCACLKResult] CA Dly = 33
5339 12:38:43.536895 CS Dly: 5 (0~36)
5340 12:38:43.536976 ==
5341 12:38:43.539286 Dram Type= 6, Freq= 0, CH_1, rank 1
5342 12:38:43.542620 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5343 12:38:43.542702 ==
5344 12:38:43.549890 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5345 12:38:43.556135 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5346 12:38:43.559554 [CA 0] Center 37 (6~68) winsize 63
5347 12:38:43.562402 [CA 1] Center 37 (6~68) winsize 63
5348 12:38:43.566172 [CA 2] Center 34 (4~65) winsize 62
5349 12:38:43.569657 [CA 3] Center 34 (3~65) winsize 63
5350 12:38:43.572244 [CA 4] Center 33 (3~64) winsize 62
5351 12:38:43.575559 [CA 5] Center 33 (2~64) winsize 63
5352 12:38:43.575653
5353 12:38:43.579389 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5354 12:38:43.579501
5355 12:38:43.582838 [CATrainingPosCal] consider 2 rank data
5356 12:38:43.586712 u2DelayCellTimex100 = 270/100 ps
5357 12:38:43.589409 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5358 12:38:43.592276 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5359 12:38:43.595830 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5360 12:38:43.598870 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5361 12:38:43.602567 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5362 12:38:43.605855 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5363 12:38:43.605936
5364 12:38:43.612761 CA PerBit enable=1, Macro0, CA PI delay=33
5365 12:38:43.612841
5366 12:38:43.615543 [CBTSetCACLKResult] CA Dly = 33
5367 12:38:43.615623 CS Dly: 5 (0~37)
5368 12:38:43.615686
5369 12:38:43.619047 ----->DramcWriteLeveling(PI) begin...
5370 12:38:43.619131 ==
5371 12:38:43.622191 Dram Type= 6, Freq= 0, CH_1, rank 0
5372 12:38:43.625547 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5373 12:38:43.628738 ==
5374 12:38:43.628819 Write leveling (Byte 0): 23 => 23
5375 12:38:43.631788 Write leveling (Byte 1): 24 => 24
5376 12:38:43.635456 DramcWriteLeveling(PI) end<-----
5377 12:38:43.635556
5378 12:38:43.635641 ==
5379 12:38:43.638963 Dram Type= 6, Freq= 0, CH_1, rank 0
5380 12:38:43.644931 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5381 12:38:43.645012 ==
5382 12:38:43.648236 [Gating] SW mode calibration
5383 12:38:43.654856 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5384 12:38:43.659050 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5385 12:38:43.664727 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5386 12:38:43.667999 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5387 12:38:43.671903 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5388 12:38:43.678150 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5389 12:38:43.681484 0 10 16 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
5390 12:38:43.685219 0 10 20 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
5391 12:38:43.692520 0 10 24 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
5392 12:38:43.694944 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5393 12:38:43.697992 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5394 12:38:43.701397 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5395 12:38:43.708228 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5396 12:38:43.711543 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5397 12:38:43.714415 0 11 16 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
5398 12:38:43.721306 0 11 20 | B1->B0 | 2e2e 4646 | 0 0 | (1 1) (0 0)
5399 12:38:43.724788 0 11 24 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5400 12:38:43.728581 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5401 12:38:43.734726 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5402 12:38:43.738237 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5403 12:38:43.741002 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5404 12:38:43.747610 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5405 12:38:43.750977 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5406 12:38:43.754435 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5407 12:38:43.761397 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 12:38:43.764023 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 12:38:43.767408 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 12:38:43.774777 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 12:38:43.777150 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 12:38:43.780516 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 12:38:43.787768 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 12:38:43.790652 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 12:38:43.793854 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 12:38:43.800442 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 12:38:43.803771 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 12:38:43.806862 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 12:38:43.813809 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 12:38:43.816998 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 12:38:43.820974 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5422 12:38:43.827124 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5423 12:38:43.827205 Total UI for P1: 0, mck2ui 16
5424 12:38:43.833752 best dqsien dly found for B0: ( 0, 14, 16)
5425 12:38:43.836812 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5426 12:38:43.840310 Total UI for P1: 0, mck2ui 16
5427 12:38:43.843549 best dqsien dly found for B1: ( 0, 14, 20)
5428 12:38:43.846675 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5429 12:38:43.850380 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5430 12:38:43.850460
5431 12:38:43.853873 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5432 12:38:43.857009 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5433 12:38:43.860122 [Gating] SW calibration Done
5434 12:38:43.860202 ==
5435 12:38:43.863386 Dram Type= 6, Freq= 0, CH_1, rank 0
5436 12:38:43.867176 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5437 12:38:43.870379 ==
5438 12:38:43.870499 RX Vref Scan: 0
5439 12:38:43.870615
5440 12:38:43.873391 RX Vref 0 -> 0, step: 1
5441 12:38:43.873471
5442 12:38:43.876836 RX Delay -80 -> 252, step: 8
5443 12:38:43.880224 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5444 12:38:43.883848 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5445 12:38:43.886520 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5446 12:38:43.890288 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5447 12:38:43.896497 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5448 12:38:43.900440 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5449 12:38:43.903511 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5450 12:38:43.906536 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5451 12:38:43.909989 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5452 12:38:43.913084 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5453 12:38:43.920134 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5454 12:38:43.922973 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5455 12:38:43.926285 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5456 12:38:43.929977 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5457 12:38:43.932895 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5458 12:38:43.941330 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5459 12:38:43.941412 ==
5460 12:38:43.943151 Dram Type= 6, Freq= 0, CH_1, rank 0
5461 12:38:43.946606 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5462 12:38:43.946687 ==
5463 12:38:43.946750 DQS Delay:
5464 12:38:43.949737 DQS0 = 0, DQS1 = 0
5465 12:38:43.949818 DQM Delay:
5466 12:38:43.952678 DQM0 = 95, DQM1 = 88
5467 12:38:43.952801 DQ Delay:
5468 12:38:43.956522 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5469 12:38:43.960279 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =91
5470 12:38:43.962941 DQ8 =71, DQ9 =79, DQ10 =91, DQ11 =79
5471 12:38:43.966402 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =99
5472 12:38:43.966482
5473 12:38:43.966545
5474 12:38:43.966604 ==
5475 12:38:43.969399 Dram Type= 6, Freq= 0, CH_1, rank 0
5476 12:38:43.973006 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5477 12:38:43.973088 ==
5478 12:38:43.973150
5479 12:38:43.976007
5480 12:38:43.976086 TX Vref Scan disable
5481 12:38:43.980009 == TX Byte 0 ==
5482 12:38:43.983390 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5483 12:38:43.986262 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5484 12:38:43.990535 == TX Byte 1 ==
5485 12:38:43.993111 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5486 12:38:43.996290 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5487 12:38:43.996371 ==
5488 12:38:43.999773 Dram Type= 6, Freq= 0, CH_1, rank 0
5489 12:38:44.005894 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5490 12:38:44.005975 ==
5491 12:38:44.006038
5492 12:38:44.006097
5493 12:38:44.006152 TX Vref Scan disable
5494 12:38:44.010245 == TX Byte 0 ==
5495 12:38:44.013679 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5496 12:38:44.016641 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5497 12:38:44.020624 == TX Byte 1 ==
5498 12:38:44.023346 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5499 12:38:44.029903 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5500 12:38:44.029984
5501 12:38:44.030046 [DATLAT]
5502 12:38:44.030105 Freq=933, CH1 RK0
5503 12:38:44.030162
5504 12:38:44.033641 DATLAT Default: 0xd
5505 12:38:44.033721 0, 0xFFFF, sum = 0
5506 12:38:44.036570 1, 0xFFFF, sum = 0
5507 12:38:44.036652 2, 0xFFFF, sum = 0
5508 12:38:44.039770 3, 0xFFFF, sum = 0
5509 12:38:44.043002 4, 0xFFFF, sum = 0
5510 12:38:44.043086 5, 0xFFFF, sum = 0
5511 12:38:44.046719 6, 0xFFFF, sum = 0
5512 12:38:44.046795 7, 0xFFFF, sum = 0
5513 12:38:44.050333 8, 0xFFFF, sum = 0
5514 12:38:44.050416 9, 0xFFFF, sum = 0
5515 12:38:44.053209 10, 0x0, sum = 1
5516 12:38:44.053292 11, 0x0, sum = 2
5517 12:38:44.056904 12, 0x0, sum = 3
5518 12:38:44.056987 13, 0x0, sum = 4
5519 12:38:44.057052 best_step = 11
5520 12:38:44.057111
5521 12:38:44.060255 ==
5522 12:38:44.063526 Dram Type= 6, Freq= 0, CH_1, rank 0
5523 12:38:44.066353 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5524 12:38:44.066436 ==
5525 12:38:44.066501 RX Vref Scan: 1
5526 12:38:44.066560
5527 12:38:44.069931 RX Vref 0 -> 0, step: 1
5528 12:38:44.070013
5529 12:38:44.072739 RX Delay -69 -> 252, step: 4
5530 12:38:44.072834
5531 12:38:44.076782 Set Vref, RX VrefLevel [Byte0]: 56
5532 12:38:44.079424 [Byte1]: 48
5533 12:38:44.079506
5534 12:38:44.083150 Final RX Vref Byte 0 = 56 to rank0
5535 12:38:44.086713 Final RX Vref Byte 1 = 48 to rank0
5536 12:38:44.089748 Final RX Vref Byte 0 = 56 to rank1
5537 12:38:44.093090 Final RX Vref Byte 1 = 48 to rank1==
5538 12:38:44.096643 Dram Type= 6, Freq= 0, CH_1, rank 0
5539 12:38:44.100182 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5540 12:38:44.102819 ==
5541 12:38:44.102901 DQS Delay:
5542 12:38:44.102965 DQS0 = 0, DQS1 = 0
5543 12:38:44.106544 DQM Delay:
5544 12:38:44.106625 DQM0 = 94, DQM1 = 87
5545 12:38:44.110031 DQ Delay:
5546 12:38:44.110113 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =92
5547 12:38:44.112871 DQ4 =92, DQ5 =104, DQ6 =102, DQ7 =90
5548 12:38:44.115837 DQ8 =70, DQ9 =76, DQ10 =88, DQ11 =80
5549 12:38:44.122510 DQ12 =94, DQ13 =100, DQ14 =96, DQ15 =98
5550 12:38:44.122591
5551 12:38:44.122655
5552 12:38:44.130924 [DQSOSCAuto] RK0, (LSB)MR18= 0x3131, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
5553 12:38:44.132613 CH1 RK0: MR19=505, MR18=3131
5554 12:38:44.139259 CH1_RK0: MR19=0x505, MR18=0x3131, DQSOSC=406, MR23=63, INC=65, DEC=43
5555 12:38:44.139341
5556 12:38:44.142788 ----->DramcWriteLeveling(PI) begin...
5557 12:38:44.142873 ==
5558 12:38:44.146319 Dram Type= 6, Freq= 0, CH_1, rank 1
5559 12:38:44.149743 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5560 12:38:44.149824 ==
5561 12:38:44.152489 Write leveling (Byte 0): 22 => 22
5562 12:38:44.155767 Write leveling (Byte 1): 21 => 21
5563 12:38:44.158980 DramcWriteLeveling(PI) end<-----
5564 12:38:44.159060
5565 12:38:44.159123 ==
5566 12:38:44.162282 Dram Type= 6, Freq= 0, CH_1, rank 1
5567 12:38:44.165800 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5568 12:38:44.165880 ==
5569 12:38:44.168830 [Gating] SW mode calibration
5570 12:38:44.175867 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5571 12:38:44.182775 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5572 12:38:44.186008 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 12:38:44.192776 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5574 12:38:44.196053 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5575 12:38:44.198850 0 10 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5576 12:38:44.202278 0 10 16 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
5577 12:38:44.209145 0 10 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5578 12:38:44.212699 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 12:38:44.215237 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 12:38:44.221856 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 12:38:44.225565 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5582 12:38:44.228604 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 12:38:44.235882 0 11 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5584 12:38:44.238561 0 11 16 | B1->B0 | 2424 3d3d | 0 0 | (0 0) (1 1)
5585 12:38:44.242133 0 11 20 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
5586 12:38:44.248351 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 12:38:44.252580 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 12:38:44.255301 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 12:38:44.262689 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 12:38:44.265262 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 12:38:44.268872 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 12:38:44.274895 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5593 12:38:44.278883 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 12:38:44.282199 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 12:38:44.288506 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 12:38:44.292237 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 12:38:44.296605 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 12:38:44.302211 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 12:38:44.305168 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 12:38:44.308438 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 12:38:44.314964 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 12:38:44.318308 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 12:38:44.321660 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 12:38:44.327902 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 12:38:44.332209 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 12:38:44.334620 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 12:38:44.341677 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 12:38:44.344491 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5609 12:38:44.348735 Total UI for P1: 0, mck2ui 16
5610 12:38:44.350992 best dqsien dly found for B0: ( 0, 14, 14)
5611 12:38:44.354448 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5612 12:38:44.361242 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 12:38:44.361323 Total UI for P1: 0, mck2ui 16
5614 12:38:44.365021 best dqsien dly found for B1: ( 0, 14, 18)
5615 12:38:44.371336 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5616 12:38:44.375222 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5617 12:38:44.375303
5618 12:38:44.378328 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5619 12:38:44.381401 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5620 12:38:44.384451 [Gating] SW calibration Done
5621 12:38:44.384531 ==
5622 12:38:44.387795 Dram Type= 6, Freq= 0, CH_1, rank 1
5623 12:38:44.391105 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5624 12:38:44.391185 ==
5625 12:38:44.394587 RX Vref Scan: 0
5626 12:38:44.394667
5627 12:38:44.394730 RX Vref 0 -> 0, step: 1
5628 12:38:44.394788
5629 12:38:44.397930 RX Delay -80 -> 252, step: 8
5630 12:38:44.400982 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5631 12:38:44.407361 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5632 12:38:44.411063 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5633 12:38:44.414810 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5634 12:38:44.418230 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5635 12:38:44.421370 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5636 12:38:44.424657 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5637 12:38:44.431064 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5638 12:38:44.434347 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5639 12:38:44.437214 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5640 12:38:44.441024 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5641 12:38:44.444107 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5642 12:38:44.450736 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5643 12:38:44.454868 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5644 12:38:44.457940 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5645 12:38:44.461333 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5646 12:38:44.461414 ==
5647 12:38:44.465108 Dram Type= 6, Freq= 0, CH_1, rank 1
5648 12:38:44.467390 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5649 12:38:44.467471 ==
5650 12:38:44.470402 DQS Delay:
5651 12:38:44.470482 DQS0 = 0, DQS1 = 0
5652 12:38:44.473919 DQM Delay:
5653 12:38:44.474000 DQM0 = 97, DQM1 = 87
5654 12:38:44.474063 DQ Delay:
5655 12:38:44.477478 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5656 12:38:44.481262 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5657 12:38:44.484336 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5658 12:38:44.487068 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =95
5659 12:38:44.487148
5660 12:38:44.490733
5661 12:38:44.490813 ==
5662 12:38:44.494445 Dram Type= 6, Freq= 0, CH_1, rank 1
5663 12:38:44.497210 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5664 12:38:44.497290 ==
5665 12:38:44.497353
5666 12:38:44.497411
5667 12:38:44.500926 TX Vref Scan disable
5668 12:38:44.501005 == TX Byte 0 ==
5669 12:38:44.507350 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5670 12:38:44.511021 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5671 12:38:44.511102 == TX Byte 1 ==
5672 12:38:44.517141 Update DQ dly =704 (2 ,5, 32) DQ OEN =(2 ,2)
5673 12:38:44.520592 Update DQM dly =704 (2 ,5, 32) DQM OEN =(2 ,2)
5674 12:38:44.520672 ==
5675 12:38:44.524072 Dram Type= 6, Freq= 0, CH_1, rank 1
5676 12:38:44.526865 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5677 12:38:44.526946 ==
5678 12:38:44.527009
5679 12:38:44.527066
5680 12:38:44.530125 TX Vref Scan disable
5681 12:38:44.533821 == TX Byte 0 ==
5682 12:38:44.537451 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5683 12:38:44.540537 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5684 12:38:44.543734 == TX Byte 1 ==
5685 12:38:44.549385 Update DQ dly =704 (2 ,5, 32) DQ OEN =(2 ,2)
5686 12:38:44.550297 Update DQM dly =704 (2 ,5, 32) DQM OEN =(2 ,2)
5687 12:38:44.550378
5688 12:38:44.553120 [DATLAT]
5689 12:38:44.553200 Freq=933, CH1 RK1
5690 12:38:44.553264
5691 12:38:44.556905 DATLAT Default: 0xb
5692 12:38:44.556985 0, 0xFFFF, sum = 0
5693 12:38:44.559855 1, 0xFFFF, sum = 0
5694 12:38:44.559936 2, 0xFFFF, sum = 0
5695 12:38:44.564322 3, 0xFFFF, sum = 0
5696 12:38:44.564407 4, 0xFFFF, sum = 0
5697 12:38:44.567237 5, 0xFFFF, sum = 0
5698 12:38:44.567319 6, 0xFFFF, sum = 0
5699 12:38:44.569804 7, 0xFFFF, sum = 0
5700 12:38:44.569903 8, 0xFFFF, sum = 0
5701 12:38:44.573874 9, 0xFFFF, sum = 0
5702 12:38:44.573958 10, 0x0, sum = 1
5703 12:38:44.576577 11, 0x0, sum = 2
5704 12:38:44.576659 12, 0x0, sum = 3
5705 12:38:44.579930 13, 0x0, sum = 4
5706 12:38:44.580013 best_step = 11
5707 12:38:44.580077
5708 12:38:44.580137 ==
5709 12:38:44.583050 Dram Type= 6, Freq= 0, CH_1, rank 1
5710 12:38:44.589826 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5711 12:38:44.589909 ==
5712 12:38:44.589974 RX Vref Scan: 0
5713 12:38:44.590034
5714 12:38:44.593620 RX Vref 0 -> 0, step: 1
5715 12:38:44.593702
5716 12:38:44.596359 RX Delay -69 -> 252, step: 4
5717 12:38:44.599475 iDelay=203, Bit 0, Center 96 (3 ~ 190) 188
5718 12:38:44.603405 iDelay=203, Bit 1, Center 92 (-1 ~ 186) 188
5719 12:38:44.609595 iDelay=203, Bit 2, Center 86 (-5 ~ 178) 184
5720 12:38:44.612907 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5721 12:38:44.616239 iDelay=203, Bit 4, Center 94 (-1 ~ 190) 192
5722 12:38:44.619782 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5723 12:38:44.623060 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5724 12:38:44.633669 iDelay=203, Bit 7, Center 94 (-1 ~ 190) 192
5725 12:38:44.633760 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5726 12:38:44.636073 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5727 12:38:44.639425 iDelay=203, Bit 10, Center 86 (-5 ~ 178) 184
5728 12:38:44.642650 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5729 12:38:44.649988 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5730 12:38:44.652422 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5731 12:38:44.655723 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5732 12:38:44.659298 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5733 12:38:44.659380 ==
5734 12:38:44.662878 Dram Type= 6, Freq= 0, CH_1, rank 1
5735 12:38:44.665560 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5736 12:38:44.669049 ==
5737 12:38:44.669130 DQS Delay:
5738 12:38:44.669195 DQS0 = 0, DQS1 = 0
5739 12:38:44.672389 DQM Delay:
5740 12:38:44.672471 DQM0 = 95, DQM1 = 87
5741 12:38:44.675521 DQ Delay:
5742 12:38:44.675604 DQ0 =96, DQ1 =92, DQ2 =86, DQ3 =92
5743 12:38:44.679151 DQ4 =94, DQ5 =106, DQ6 =104, DQ7 =94
5744 12:38:44.682542 DQ8 =74, DQ9 =76, DQ10 =86, DQ11 =80
5745 12:38:44.686243 DQ12 =96, DQ13 =96, DQ14 =94, DQ15 =96
5746 12:38:44.688692
5747 12:38:44.688811
5748 12:38:44.695983 [DQSOSCAuto] RK1, (LSB)MR18= 0x2121, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
5749 12:38:44.698781 CH1 RK1: MR19=505, MR18=2121
5750 12:38:44.705672 CH1_RK1: MR19=0x505, MR18=0x2121, DQSOSC=411, MR23=63, INC=64, DEC=42
5751 12:38:44.709068 [RxdqsGatingPostProcess] freq 933
5752 12:38:44.712124 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5753 12:38:44.715231 Pre-setting of DQS Precalculation
5754 12:38:44.722418 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5755 12:38:44.729356 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5756 12:38:44.735407 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5757 12:38:44.735489
5758 12:38:44.735553
5759 12:38:44.738733 [Calibration Summary] 1866 Mbps
5760 12:38:44.738815 CH 0, Rank 0
5761 12:38:44.741771 SW Impedance : PASS
5762 12:38:44.745738 DUTY Scan : NO K
5763 12:38:44.745820 ZQ Calibration : PASS
5764 12:38:44.748869 Jitter Meter : NO K
5765 12:38:44.751886 CBT Training : PASS
5766 12:38:44.751968 Write leveling : PASS
5767 12:38:44.755685 RX DQS gating : PASS
5768 12:38:44.758605 RX DQ/DQS(RDDQC) : PASS
5769 12:38:44.758687 TX DQ/DQS : PASS
5770 12:38:44.762039 RX DATLAT : PASS
5771 12:38:44.762121 RX DQ/DQS(Engine): PASS
5772 12:38:44.765448 TX OE : NO K
5773 12:38:44.765530 All Pass.
5774 12:38:44.765594
5775 12:38:44.768596 CH 0, Rank 1
5776 12:38:44.768677 SW Impedance : PASS
5777 12:38:44.772313 DUTY Scan : NO K
5778 12:38:44.775641 ZQ Calibration : PASS
5779 12:38:44.775722 Jitter Meter : NO K
5780 12:38:44.778257 CBT Training : PASS
5781 12:38:44.781675 Write leveling : PASS
5782 12:38:44.781757 RX DQS gating : PASS
5783 12:38:44.785079 RX DQ/DQS(RDDQC) : PASS
5784 12:38:44.787936 TX DQ/DQS : PASS
5785 12:38:44.788019 RX DATLAT : PASS
5786 12:38:44.791713 RX DQ/DQS(Engine): PASS
5787 12:38:44.794676 TX OE : NO K
5788 12:38:44.794758 All Pass.
5789 12:38:44.794821
5790 12:38:44.794880 CH 1, Rank 0
5791 12:38:44.798375 SW Impedance : PASS
5792 12:38:44.801481 DUTY Scan : NO K
5793 12:38:44.801563 ZQ Calibration : PASS
5794 12:38:44.805497 Jitter Meter : NO K
5795 12:38:44.808961 CBT Training : PASS
5796 12:38:44.809042 Write leveling : PASS
5797 12:38:44.811596 RX DQS gating : PASS
5798 12:38:44.815168 RX DQ/DQS(RDDQC) : PASS
5799 12:38:44.815251 TX DQ/DQS : PASS
5800 12:38:44.818471 RX DATLAT : PASS
5801 12:38:44.818553 RX DQ/DQS(Engine): PASS
5802 12:38:44.822008 TX OE : NO K
5803 12:38:44.822090 All Pass.
5804 12:38:44.822154
5805 12:38:44.825213 CH 1, Rank 1
5806 12:38:44.825295 SW Impedance : PASS
5807 12:38:44.828103 DUTY Scan : NO K
5808 12:38:44.831804 ZQ Calibration : PASS
5809 12:38:44.831886 Jitter Meter : NO K
5810 12:38:44.835582 CBT Training : PASS
5811 12:38:44.837747 Write leveling : PASS
5812 12:38:44.837854 RX DQS gating : PASS
5813 12:38:44.841545 RX DQ/DQS(RDDQC) : PASS
5814 12:38:44.845058 TX DQ/DQS : PASS
5815 12:38:44.845142 RX DATLAT : PASS
5816 12:38:44.848189 RX DQ/DQS(Engine): PASS
5817 12:38:44.851005 TX OE : NO K
5818 12:38:44.851088 All Pass.
5819 12:38:44.851151
5820 12:38:44.854869 DramC Write-DBI off
5821 12:38:44.854954 PER_BANK_REFRESH: Hybrid Mode
5822 12:38:44.857900 TX_TRACKING: ON
5823 12:38:44.865010 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5824 12:38:44.871424 [FAST_K] Save calibration result to emmc
5825 12:38:44.874900 dramc_set_vcore_voltage set vcore to 650000
5826 12:38:44.874982 Read voltage for 400, 6
5827 12:38:44.877606 Vio18 = 0
5828 12:38:44.877688 Vcore = 650000
5829 12:38:44.877751 Vdram = 0
5830 12:38:44.881514 Vddq = 0
5831 12:38:44.881596 Vmddr = 0
5832 12:38:44.884929 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5833 12:38:44.891385 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5834 12:38:44.894382 MEM_TYPE=3, freq_sel=20
5835 12:38:44.898168 sv_algorithm_assistance_LP4_800
5836 12:38:44.901691 ============ PULL DRAM RESETB DOWN ============
5837 12:38:44.904620 ========== PULL DRAM RESETB DOWN end =========
5838 12:38:44.908051 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5839 12:38:44.911151 ===================================
5840 12:38:44.914465 LPDDR4 DRAM CONFIGURATION
5841 12:38:44.917513 ===================================
5842 12:38:44.921252 EX_ROW_EN[0] = 0x0
5843 12:38:44.921345 EX_ROW_EN[1] = 0x0
5844 12:38:44.924284 LP4Y_EN = 0x0
5845 12:38:44.924365 WORK_FSP = 0x0
5846 12:38:44.927936 WL = 0x2
5847 12:38:44.928017 RL = 0x2
5848 12:38:44.931294 BL = 0x2
5849 12:38:44.931376 RPST = 0x0
5850 12:38:44.934584 RD_PRE = 0x0
5851 12:38:44.934666 WR_PRE = 0x1
5852 12:38:44.937829 WR_PST = 0x0
5853 12:38:44.940972 DBI_WR = 0x0
5854 12:38:44.941054 DBI_RD = 0x0
5855 12:38:44.944411 OTF = 0x1
5856 12:38:44.947548 ===================================
5857 12:38:44.950581 ===================================
5858 12:38:44.950662 ANA top config
5859 12:38:44.954612 ===================================
5860 12:38:44.957238 DLL_ASYNC_EN = 0
5861 12:38:44.960973 ALL_SLAVE_EN = 1
5862 12:38:44.961055 NEW_RANK_MODE = 1
5863 12:38:44.964177 DLL_IDLE_MODE = 1
5864 12:38:44.967131 LP45_APHY_COMB_EN = 1
5865 12:38:44.970758 TX_ODT_DIS = 1
5866 12:38:44.970839 NEW_8X_MODE = 1
5867 12:38:44.974041 ===================================
5868 12:38:44.977060 ===================================
5869 12:38:44.980755 data_rate = 800
5870 12:38:44.983994 CKR = 1
5871 12:38:44.987341 DQ_P2S_RATIO = 4
5872 12:38:44.990747 ===================================
5873 12:38:44.994050 CA_P2S_RATIO = 4
5874 12:38:44.997153 DQ_CA_OPEN = 0
5875 12:38:44.997235 DQ_SEMI_OPEN = 1
5876 12:38:45.000782 CA_SEMI_OPEN = 1
5877 12:38:45.003809 CA_FULL_RATE = 0
5878 12:38:45.007456 DQ_CKDIV4_EN = 0
5879 12:38:45.010207 CA_CKDIV4_EN = 1
5880 12:38:45.013938 CA_PREDIV_EN = 0
5881 12:38:45.014020 PH8_DLY = 0
5882 12:38:45.017680 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5883 12:38:45.020058 DQ_AAMCK_DIV = 0
5884 12:38:45.023751 CA_AAMCK_DIV = 0
5885 12:38:45.026589 CA_ADMCK_DIV = 4
5886 12:38:45.030159 DQ_TRACK_CA_EN = 0
5887 12:38:45.033881 CA_PICK = 800
5888 12:38:45.033962 CA_MCKIO = 400
5889 12:38:45.037213 MCKIO_SEMI = 400
5890 12:38:45.039786 PLL_FREQ = 3016
5891 12:38:45.043484 DQ_UI_PI_RATIO = 32
5892 12:38:45.046763 CA_UI_PI_RATIO = 32
5893 12:38:45.050254 ===================================
5894 12:38:45.053227 ===================================
5895 12:38:45.056680 memory_type:LPDDR4
5896 12:38:45.056800 GP_NUM : 10
5897 12:38:45.059787 SRAM_EN : 1
5898 12:38:45.063427 MD32_EN : 0
5899 12:38:45.063509 ===================================
5900 12:38:45.066396 [ANA_INIT] >>>>>>>>>>>>>>
5901 12:38:45.070332 <<<<<< [CONFIGURE PHASE]: ANA_TX
5902 12:38:45.073249 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5903 12:38:45.076421 ===================================
5904 12:38:45.080349 data_rate = 800,PCW = 0X7400
5905 12:38:45.083419 ===================================
5906 12:38:45.086461 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5907 12:38:45.093136 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5908 12:38:45.103301 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5909 12:38:45.106510 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5910 12:38:45.110231 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5911 12:38:45.114130 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5912 12:38:45.116320 [ANA_INIT] flow start
5913 12:38:45.119606 [ANA_INIT] PLL >>>>>>>>
5914 12:38:45.119689 [ANA_INIT] PLL <<<<<<<<
5915 12:38:45.123174 [ANA_INIT] MIDPI >>>>>>>>
5916 12:38:45.126268 [ANA_INIT] MIDPI <<<<<<<<
5917 12:38:45.129971 [ANA_INIT] DLL >>>>>>>>
5918 12:38:45.130053 [ANA_INIT] flow end
5919 12:38:45.133203 ============ LP4 DIFF to SE enter ============
5920 12:38:45.140075 ============ LP4 DIFF to SE exit ============
5921 12:38:45.140158 [ANA_INIT] <<<<<<<<<<<<<
5922 12:38:45.143783 [Flow] Enable top DCM control >>>>>
5923 12:38:45.146250 [Flow] Enable top DCM control <<<<<
5924 12:38:45.149572 Enable DLL master slave shuffle
5925 12:38:45.156020 ==============================================================
5926 12:38:45.156102 Gating Mode config
5927 12:38:45.162563 ==============================================================
5928 12:38:45.166179 Config description:
5929 12:38:45.176413 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5930 12:38:45.182640 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5931 12:38:45.186227 SELPH_MODE 0: By rank 1: By Phase
5932 12:38:45.192574 ==============================================================
5933 12:38:45.195889 GAT_TRACK_EN = 0
5934 12:38:45.199602 RX_GATING_MODE = 2
5935 12:38:45.199684 RX_GATING_TRACK_MODE = 2
5936 12:38:45.202572 SELPH_MODE = 1
5937 12:38:45.205837 PICG_EARLY_EN = 1
5938 12:38:45.209203 VALID_LAT_VALUE = 1
5939 12:38:45.216181 ==============================================================
5940 12:38:45.219729 Enter into Gating configuration >>>>
5941 12:38:45.222482 Exit from Gating configuration <<<<
5942 12:38:45.226278 Enter into DVFS_PRE_config >>>>>
5943 12:38:45.235684 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5944 12:38:45.239133 Exit from DVFS_PRE_config <<<<<
5945 12:38:45.242915 Enter into PICG configuration >>>>
5946 12:38:45.245860 Exit from PICG configuration <<<<
5947 12:38:45.249638 [RX_INPUT] configuration >>>>>
5948 12:38:45.252123 [RX_INPUT] configuration <<<<<
5949 12:38:45.255973 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5950 12:38:45.262117 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5951 12:38:45.269706 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5952 12:38:45.275133 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5953 12:38:45.279241 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5954 12:38:45.285821 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5955 12:38:45.288600 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5956 12:38:45.295275 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5957 12:38:45.298985 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5958 12:38:45.302186 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5959 12:38:45.305265 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5960 12:38:45.312224 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5961 12:38:45.315328 ===================================
5962 12:38:45.319188 LPDDR4 DRAM CONFIGURATION
5963 12:38:45.321976 ===================================
5964 12:38:45.322058 EX_ROW_EN[0] = 0x0
5965 12:38:45.324903 EX_ROW_EN[1] = 0x0
5966 12:38:45.324984 LP4Y_EN = 0x0
5967 12:38:45.328628 WORK_FSP = 0x0
5968 12:38:45.328815 WL = 0x2
5969 12:38:45.331690 RL = 0x2
5970 12:38:45.331771 BL = 0x2
5971 12:38:45.335203 RPST = 0x0
5972 12:38:45.335284 RD_PRE = 0x0
5973 12:38:45.338432 WR_PRE = 0x1
5974 12:38:45.338545 WR_PST = 0x0
5975 12:38:45.341970 DBI_WR = 0x0
5976 12:38:45.342052 DBI_RD = 0x0
5977 12:38:45.345100 OTF = 0x1
5978 12:38:45.348283 ===================================
5979 12:38:45.351517 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5980 12:38:45.355470 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5981 12:38:45.361426 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5982 12:38:45.365198 ===================================
5983 12:38:45.365279 LPDDR4 DRAM CONFIGURATION
5984 12:38:45.368135 ===================================
5985 12:38:45.371925 EX_ROW_EN[0] = 0x10
5986 12:38:45.374955 EX_ROW_EN[1] = 0x0
5987 12:38:45.375036 LP4Y_EN = 0x0
5988 12:38:45.378298 WORK_FSP = 0x0
5989 12:38:45.378380 WL = 0x2
5990 12:38:45.381419 RL = 0x2
5991 12:38:45.381501 BL = 0x2
5992 12:38:45.385199 RPST = 0x0
5993 12:38:45.385279 RD_PRE = 0x0
5994 12:38:45.388401 WR_PRE = 0x1
5995 12:38:45.388482 WR_PST = 0x0
5996 12:38:45.391269 DBI_WR = 0x0
5997 12:38:45.391390 DBI_RD = 0x0
5998 12:38:45.395042 OTF = 0x1
5999 12:38:45.398156 ===================================
6000 12:38:45.405317 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6001 12:38:45.407910 nWR fixed to 30
6002 12:38:45.410765 [ModeRegInit_LP4] CH0 RK0
6003 12:38:45.410846 [ModeRegInit_LP4] CH0 RK1
6004 12:38:45.415025 [ModeRegInit_LP4] CH1 RK0
6005 12:38:45.417676 [ModeRegInit_LP4] CH1 RK1
6006 12:38:45.417756 match AC timing 18
6007 12:38:45.424203 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6008 12:38:45.427587 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6009 12:38:45.430857 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6010 12:38:45.437839 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6011 12:38:45.441162 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6012 12:38:45.441244 ==
6013 12:38:45.444514 Dram Type= 6, Freq= 0, CH_0, rank 0
6014 12:38:45.448241 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6015 12:38:45.448322 ==
6016 12:38:45.454399 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6017 12:38:45.460638 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6018 12:38:45.464474 [CA 0] Center 36 (8~64) winsize 57
6019 12:38:45.467810 [CA 1] Center 36 (8~64) winsize 57
6020 12:38:45.471237 [CA 2] Center 36 (8~64) winsize 57
6021 12:38:45.471318 [CA 3] Center 36 (8~64) winsize 57
6022 12:38:45.474006 [CA 4] Center 36 (8~64) winsize 57
6023 12:38:45.478055 [CA 5] Center 36 (8~64) winsize 57
6024 12:38:45.478136
6025 12:38:45.483884 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6026 12:38:45.483966
6027 12:38:45.487630 [CATrainingPosCal] consider 1 rank data
6028 12:38:45.487711 u2DelayCellTimex100 = 270/100 ps
6029 12:38:45.494568 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6030 12:38:45.497261 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6031 12:38:45.500928 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6032 12:38:45.504863 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6033 12:38:45.507078 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6034 12:38:45.510675 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6035 12:38:45.510756
6036 12:38:45.513847 CA PerBit enable=1, Macro0, CA PI delay=36
6037 12:38:45.513928
6038 12:38:45.517390 [CBTSetCACLKResult] CA Dly = 36
6039 12:38:45.520986 CS Dly: 1 (0~32)
6040 12:38:45.521066 ==
6041 12:38:45.523440 Dram Type= 6, Freq= 0, CH_0, rank 1
6042 12:38:45.526880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6043 12:38:45.526961 ==
6044 12:38:45.534132 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6045 12:38:45.536843 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6046 12:38:45.541081 [CA 0] Center 36 (8~64) winsize 57
6047 12:38:45.543911 [CA 1] Center 36 (8~64) winsize 57
6048 12:38:45.546791 [CA 2] Center 36 (8~64) winsize 57
6049 12:38:45.550320 [CA 3] Center 36 (8~64) winsize 57
6050 12:38:45.553352 [CA 4] Center 36 (8~64) winsize 57
6051 12:38:45.557409 [CA 5] Center 36 (8~64) winsize 57
6052 12:38:45.557490
6053 12:38:45.559959 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6054 12:38:45.560040
6055 12:38:45.564260 [CATrainingPosCal] consider 2 rank data
6056 12:38:45.566800 u2DelayCellTimex100 = 270/100 ps
6057 12:38:45.570343 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6058 12:38:45.573464 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6059 12:38:45.580444 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6060 12:38:45.583439 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6061 12:38:45.586908 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6062 12:38:45.590328 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6063 12:38:45.590409
6064 12:38:45.593927 CA PerBit enable=1, Macro0, CA PI delay=36
6065 12:38:45.594008
6066 12:38:45.596874 [CBTSetCACLKResult] CA Dly = 36
6067 12:38:45.596954 CS Dly: 1 (0~32)
6068 12:38:45.597017
6069 12:38:45.600579 ----->DramcWriteLeveling(PI) begin...
6070 12:38:45.603958 ==
6071 12:38:45.606870 Dram Type= 6, Freq= 0, CH_0, rank 0
6072 12:38:45.609948 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6073 12:38:45.610030 ==
6074 12:38:45.613508 Write leveling (Byte 0): 32 => 0
6075 12:38:45.616591 Write leveling (Byte 1): 32 => 0
6076 12:38:45.620039 DramcWriteLeveling(PI) end<-----
6077 12:38:45.620120
6078 12:38:45.620183 ==
6079 12:38:45.623672 Dram Type= 6, Freq= 0, CH_0, rank 0
6080 12:38:45.626565 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6081 12:38:45.626646 ==
6082 12:38:45.630101 [Gating] SW mode calibration
6083 12:38:45.636675 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6084 12:38:45.640009 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6085 12:38:45.646650 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6086 12:38:45.649844 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6087 12:38:45.653556 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6088 12:38:45.659568 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6089 12:38:45.663015 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6090 12:38:45.665835 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6091 12:38:45.673343 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6092 12:38:45.676158 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6093 12:38:45.679414 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6094 12:38:45.682581 Total UI for P1: 0, mck2ui 16
6095 12:38:45.686369 best dqsien dly found for B0: ( 0, 10, 16)
6096 12:38:45.689186 Total UI for P1: 0, mck2ui 16
6097 12:38:45.692944 best dqsien dly found for B1: ( 0, 10, 24)
6098 12:38:45.695981 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6099 12:38:45.702879 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6100 12:38:45.702960
6101 12:38:45.706592 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6102 12:38:45.709085 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6103 12:38:45.712829 [Gating] SW calibration Done
6104 12:38:45.712910 ==
6105 12:38:45.715441 Dram Type= 6, Freq= 0, CH_0, rank 0
6106 12:38:45.719399 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6107 12:38:45.719487 ==
6108 12:38:45.722089 RX Vref Scan: 0
6109 12:38:45.722163
6110 12:38:45.722222 RX Vref 0 -> 0, step: 1
6111 12:38:45.722280
6112 12:38:45.725743 RX Delay -410 -> 252, step: 16
6113 12:38:45.732537 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6114 12:38:45.735578 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6115 12:38:45.738869 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6116 12:38:45.742492 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6117 12:38:45.748759 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6118 12:38:45.752741 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6119 12:38:45.755674 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6120 12:38:45.758887 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6121 12:38:45.765540 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6122 12:38:45.768485 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6123 12:38:45.771955 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6124 12:38:45.775202 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6125 12:38:45.782159 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6126 12:38:45.785823 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6127 12:38:45.788662 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6128 12:38:45.792210 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6129 12:38:45.795119 ==
6130 12:38:45.798713 Dram Type= 6, Freq= 0, CH_0, rank 0
6131 12:38:45.801699 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6132 12:38:45.801780 ==
6133 12:38:45.801843 DQS Delay:
6134 12:38:45.805004 DQS0 = 43, DQS1 = 59
6135 12:38:45.805083 DQM Delay:
6136 12:38:45.808412 DQM0 = 5, DQM1 = 14
6137 12:38:45.808492 DQ Delay:
6138 12:38:45.811413 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6139 12:38:45.814999 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6140 12:38:45.815079 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6141 12:38:45.821576 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6142 12:38:45.821656
6143 12:38:45.821719
6144 12:38:45.821776 ==
6145 12:38:45.825101 Dram Type= 6, Freq= 0, CH_0, rank 0
6146 12:38:45.828170 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6147 12:38:45.828251 ==
6148 12:38:45.828313
6149 12:38:45.828372
6150 12:38:45.831491 TX Vref Scan disable
6151 12:38:45.831574 == TX Byte 0 ==
6152 12:38:45.838422 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6153 12:38:45.841737 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6154 12:38:45.841818 == TX Byte 1 ==
6155 12:38:45.848746 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6156 12:38:45.851574 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6157 12:38:45.851654 ==
6158 12:38:45.855093 Dram Type= 6, Freq= 0, CH_0, rank 0
6159 12:38:45.858252 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6160 12:38:45.858333 ==
6161 12:38:45.858406
6162 12:38:45.858526
6163 12:38:45.861299 TX Vref Scan disable
6164 12:38:45.861379 == TX Byte 0 ==
6165 12:38:45.867856 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6166 12:38:45.871526 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6167 12:38:45.871607 == TX Byte 1 ==
6168 12:38:45.878094 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6169 12:38:45.882816 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6170 12:38:45.882896
6171 12:38:45.882959 [DATLAT]
6172 12:38:45.884561 Freq=400, CH0 RK0
6173 12:38:45.884667
6174 12:38:45.884786 DATLAT Default: 0xf
6175 12:38:45.887880 0, 0xFFFF, sum = 0
6176 12:38:45.887961 1, 0xFFFF, sum = 0
6177 12:38:45.891672 2, 0xFFFF, sum = 0
6178 12:38:45.891753 3, 0xFFFF, sum = 0
6179 12:38:45.894638 4, 0xFFFF, sum = 0
6180 12:38:45.894720 5, 0xFFFF, sum = 0
6181 12:38:45.898136 6, 0xFFFF, sum = 0
6182 12:38:45.900909 7, 0xFFFF, sum = 0
6183 12:38:45.900991 8, 0xFFFF, sum = 0
6184 12:38:45.904786 9, 0xFFFF, sum = 0
6185 12:38:45.904866 10, 0xFFFF, sum = 0
6186 12:38:45.908263 11, 0xFFFF, sum = 0
6187 12:38:45.908344 12, 0x0, sum = 1
6188 12:38:45.911171 13, 0x0, sum = 2
6189 12:38:45.911252 14, 0x0, sum = 3
6190 12:38:45.915100 15, 0x0, sum = 4
6191 12:38:45.915182 best_step = 13
6192 12:38:45.915244
6193 12:38:45.915303 ==
6194 12:38:45.917698 Dram Type= 6, Freq= 0, CH_0, rank 0
6195 12:38:45.921314 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6196 12:38:45.921394 ==
6197 12:38:45.924669 RX Vref Scan: 1
6198 12:38:45.924785
6199 12:38:45.928314 RX Vref 0 -> 0, step: 1
6200 12:38:45.928393
6201 12:38:45.928456 RX Delay -359 -> 252, step: 8
6202 12:38:45.928515
6203 12:38:45.930782 Set Vref, RX VrefLevel [Byte0]: 49
6204 12:38:45.934180 [Byte1]: 49
6205 12:38:45.939767
6206 12:38:45.939848 Final RX Vref Byte 0 = 49 to rank0
6207 12:38:45.943206 Final RX Vref Byte 1 = 49 to rank0
6208 12:38:45.947213 Final RX Vref Byte 0 = 49 to rank1
6209 12:38:45.950087 Final RX Vref Byte 1 = 49 to rank1==
6210 12:38:45.953420 Dram Type= 6, Freq= 0, CH_0, rank 0
6211 12:38:45.956381 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6212 12:38:45.959918 ==
6213 12:38:45.959998 DQS Delay:
6214 12:38:45.960060 DQS0 = 52, DQS1 = 68
6215 12:38:45.963063 DQM Delay:
6216 12:38:45.963142 DQM0 = 9, DQM1 = 17
6217 12:38:45.966325 DQ Delay:
6218 12:38:45.966405 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =4
6219 12:38:45.969552 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6220 12:38:45.973148 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6221 12:38:45.976536 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6222 12:38:45.976648
6223 12:38:45.976777
6224 12:38:45.986288 [DQSOSCAuto] RK0, (LSB)MR18= 0xa9a9, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6225 12:38:45.990847 CH0 RK0: MR19=C0C, MR18=A9A9
6226 12:38:45.996615 CH0_RK0: MR19=0xC0C, MR18=0xA9A9, DQSOSC=388, MR23=63, INC=392, DEC=261
6227 12:38:45.996728 ==
6228 12:38:45.999730 Dram Type= 6, Freq= 0, CH_0, rank 1
6229 12:38:46.003158 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6230 12:38:46.003239 ==
6231 12:38:46.006302 [Gating] SW mode calibration
6232 12:38:46.012679 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6233 12:38:46.016164 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6234 12:38:46.023382 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6235 12:38:46.025721 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6236 12:38:46.030789 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6237 12:38:46.036403 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6238 12:38:46.039801 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6239 12:38:46.043259 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6240 12:38:46.049239 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6241 12:38:46.053632 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6242 12:38:46.056380 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6243 12:38:46.059281 Total UI for P1: 0, mck2ui 16
6244 12:38:46.062338 best dqsien dly found for B0: ( 0, 10, 16)
6245 12:38:46.066015 Total UI for P1: 0, mck2ui 16
6246 12:38:46.069178 best dqsien dly found for B1: ( 0, 10, 16)
6247 12:38:46.072118 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6248 12:38:46.078967 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6249 12:38:46.079049
6250 12:38:46.082533 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6251 12:38:46.085388 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6252 12:38:46.089476 [Gating] SW calibration Done
6253 12:38:46.089556 ==
6254 12:38:46.092142 Dram Type= 6, Freq= 0, CH_0, rank 1
6255 12:38:46.095235 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6256 12:38:46.095316 ==
6257 12:38:46.099211 RX Vref Scan: 0
6258 12:38:46.099315
6259 12:38:46.099381 RX Vref 0 -> 0, step: 1
6260 12:38:46.099440
6261 12:38:46.102411 RX Delay -410 -> 252, step: 16
6262 12:38:46.108594 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6263 12:38:46.111920 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6264 12:38:46.115443 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6265 12:38:46.118783 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6266 12:38:46.125817 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6267 12:38:46.128532 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6268 12:38:46.131605 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6269 12:38:46.134982 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6270 12:38:46.141943 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6271 12:38:46.144843 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6272 12:38:46.148418 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6273 12:38:46.151386 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6274 12:38:46.158154 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6275 12:38:46.161866 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6276 12:38:46.164618 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6277 12:38:46.168507 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6278 12:38:46.171625 ==
6279 12:38:46.174844 Dram Type= 6, Freq= 0, CH_0, rank 1
6280 12:38:46.178837 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6281 12:38:46.178918 ==
6282 12:38:46.178982 DQS Delay:
6283 12:38:46.181521 DQS0 = 43, DQS1 = 59
6284 12:38:46.181601 DQM Delay:
6285 12:38:46.185099 DQM0 = 7, DQM1 = 15
6286 12:38:46.185179 DQ Delay:
6287 12:38:46.187785 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6288 12:38:46.190987 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6289 12:38:46.194500 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6290 12:38:46.198248 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6291 12:38:46.198329
6292 12:38:46.198392
6293 12:38:46.198451 ==
6294 12:38:46.201094 Dram Type= 6, Freq= 0, CH_0, rank 1
6295 12:38:46.205762 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6296 12:38:46.205843 ==
6297 12:38:46.205906
6298 12:38:46.205993
6299 12:38:46.207944 TX Vref Scan disable
6300 12:38:46.208024 == TX Byte 0 ==
6301 12:38:46.214407 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6302 12:38:46.217547 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6303 12:38:46.217628 == TX Byte 1 ==
6304 12:38:46.223994 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6305 12:38:46.227790 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6306 12:38:46.227871 ==
6307 12:38:46.230980 Dram Type= 6, Freq= 0, CH_0, rank 1
6308 12:38:46.234269 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6309 12:38:46.234350 ==
6310 12:38:46.234413
6311 12:38:46.234471
6312 12:38:46.237414 TX Vref Scan disable
6313 12:38:46.237495 == TX Byte 0 ==
6314 12:38:46.243990 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6315 12:38:46.247193 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6316 12:38:46.247274 == TX Byte 1 ==
6317 12:38:46.253787 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6318 12:38:46.257468 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6319 12:38:46.257549
6320 12:38:46.257612 [DATLAT]
6321 12:38:46.260914 Freq=400, CH0 RK1
6322 12:38:46.260995
6323 12:38:46.261058 DATLAT Default: 0xd
6324 12:38:46.263893 0, 0xFFFF, sum = 0
6325 12:38:46.263975 1, 0xFFFF, sum = 0
6326 12:38:46.266905 2, 0xFFFF, sum = 0
6327 12:38:46.266986 3, 0xFFFF, sum = 0
6328 12:38:46.270371 4, 0xFFFF, sum = 0
6329 12:38:46.270453 5, 0xFFFF, sum = 0
6330 12:38:46.273466 6, 0xFFFF, sum = 0
6331 12:38:46.277237 7, 0xFFFF, sum = 0
6332 12:38:46.277319 8, 0xFFFF, sum = 0
6333 12:38:46.280301 9, 0xFFFF, sum = 0
6334 12:38:46.280382 10, 0xFFFF, sum = 0
6335 12:38:46.283757 11, 0xFFFF, sum = 0
6336 12:38:46.283839 12, 0x0, sum = 1
6337 12:38:46.286828 13, 0x0, sum = 2
6338 12:38:46.286909 14, 0x0, sum = 3
6339 12:38:46.290217 15, 0x0, sum = 4
6340 12:38:46.290298 best_step = 13
6341 12:38:46.290361
6342 12:38:46.290419 ==
6343 12:38:46.293450 Dram Type= 6, Freq= 0, CH_0, rank 1
6344 12:38:46.297128 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6345 12:38:46.297209 ==
6346 12:38:46.300233 RX Vref Scan: 0
6347 12:38:46.300312
6348 12:38:46.303427 RX Vref 0 -> 0, step: 1
6349 12:38:46.303507
6350 12:38:46.303569 RX Delay -359 -> 252, step: 8
6351 12:38:46.312127 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6352 12:38:46.315546 iDelay=217, Bit 1, Center -36 (-287 ~ 216) 504
6353 12:38:46.319607 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6354 12:38:46.322181 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6355 12:38:46.329073 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6356 12:38:46.331811 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6357 12:38:46.335264 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6358 12:38:46.341883 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6359 12:38:46.345210 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6360 12:38:46.348652 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6361 12:38:46.352142 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6362 12:38:46.358527 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6363 12:38:46.361726 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6364 12:38:46.364973 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6365 12:38:46.368575 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6366 12:38:46.375191 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6367 12:38:46.375271 ==
6368 12:38:46.378349 Dram Type= 6, Freq= 0, CH_0, rank 1
6369 12:38:46.381918 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6370 12:38:46.382001 ==
6371 12:38:46.382064 DQS Delay:
6372 12:38:46.384652 DQS0 = 52, DQS1 = 64
6373 12:38:46.384770 DQM Delay:
6374 12:38:46.387982 DQM0 = 10, DQM1 = 13
6375 12:38:46.388065 DQ Delay:
6376 12:38:46.391505 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =4
6377 12:38:46.394838 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6378 12:38:46.398112 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6379 12:38:46.402073 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6380 12:38:46.402153
6381 12:38:46.402215
6382 12:38:46.408085 [DQSOSCAuto] RK1, (LSB)MR18= 0xcdcd, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6383 12:38:46.411456 CH0 RK1: MR19=C0C, MR18=CDCD
6384 12:38:46.418017 CH0_RK1: MR19=0xC0C, MR18=0xCDCD, DQSOSC=384, MR23=63, INC=400, DEC=267
6385 12:38:46.421975 [RxdqsGatingPostProcess] freq 400
6386 12:38:46.427904 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6387 12:38:46.431219 Pre-setting of DQS Precalculation
6388 12:38:46.434602 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6389 12:38:46.434682 ==
6390 12:38:46.437932 Dram Type= 6, Freq= 0, CH_1, rank 0
6391 12:38:46.441919 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6392 12:38:46.442002 ==
6393 12:38:46.448201 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6394 12:38:46.454617 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6395 12:38:46.458216 [CA 0] Center 36 (8~64) winsize 57
6396 12:38:46.461189 [CA 1] Center 36 (8~64) winsize 57
6397 12:38:46.464143 [CA 2] Center 36 (8~64) winsize 57
6398 12:38:46.468383 [CA 3] Center 36 (8~64) winsize 57
6399 12:38:46.470801 [CA 4] Center 36 (8~64) winsize 57
6400 12:38:46.474271 [CA 5] Center 36 (8~64) winsize 57
6401 12:38:46.474373
6402 12:38:46.478031 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6403 12:38:46.478108
6404 12:38:46.480846 [CATrainingPosCal] consider 1 rank data
6405 12:38:46.484483 u2DelayCellTimex100 = 270/100 ps
6406 12:38:46.487440 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6407 12:38:46.490797 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6408 12:38:46.494226 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6409 12:38:46.497590 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6410 12:38:46.501456 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6411 12:38:46.504157 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6412 12:38:46.504252
6413 12:38:46.507829 CA PerBit enable=1, Macro0, CA PI delay=36
6414 12:38:46.507902
6415 12:38:46.510622 [CBTSetCACLKResult] CA Dly = 36
6416 12:38:46.514863 CS Dly: 1 (0~32)
6417 12:38:46.514932 ==
6418 12:38:46.517421 Dram Type= 6, Freq= 0, CH_1, rank 1
6419 12:38:46.520780 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6420 12:38:46.520850 ==
6421 12:38:46.527224 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6422 12:38:46.534692 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6423 12:38:46.537596 [CA 0] Center 36 (8~64) winsize 57
6424 12:38:46.540515 [CA 1] Center 36 (8~64) winsize 57
6425 12:38:46.540629 [CA 2] Center 36 (8~64) winsize 57
6426 12:38:46.543997 [CA 3] Center 36 (8~64) winsize 57
6427 12:38:46.547373 [CA 4] Center 36 (8~64) winsize 57
6428 12:38:46.550497 [CA 5] Center 36 (8~64) winsize 57
6429 12:38:46.550578
6430 12:38:46.553917 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6431 12:38:46.557013
6432 12:38:46.560257 [CATrainingPosCal] consider 2 rank data
6433 12:38:46.560338 u2DelayCellTimex100 = 270/100 ps
6434 12:38:46.567885 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6435 12:38:46.570822 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6436 12:38:46.574168 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6437 12:38:46.577469 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6438 12:38:46.580867 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6439 12:38:46.583765 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6440 12:38:46.583846
6441 12:38:46.587003 CA PerBit enable=1, Macro0, CA PI delay=36
6442 12:38:46.587084
6443 12:38:46.590615 [CBTSetCACLKResult] CA Dly = 36
6444 12:38:46.594155 CS Dly: 1 (0~32)
6445 12:38:46.594236
6446 12:38:46.597089 ----->DramcWriteLeveling(PI) begin...
6447 12:38:46.597171 ==
6448 12:38:46.600973 Dram Type= 6, Freq= 0, CH_1, rank 0
6449 12:38:46.603918 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6450 12:38:46.603999 ==
6451 12:38:46.607667 Write leveling (Byte 0): 32 => 0
6452 12:38:46.610341 Write leveling (Byte 1): 32 => 0
6453 12:38:46.613774 DramcWriteLeveling(PI) end<-----
6454 12:38:46.613854
6455 12:38:46.613917 ==
6456 12:38:46.617318 Dram Type= 6, Freq= 0, CH_1, rank 0
6457 12:38:46.621028 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6458 12:38:46.621109 ==
6459 12:38:46.623490 [Gating] SW mode calibration
6460 12:38:46.630146 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6461 12:38:46.636953 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6462 12:38:46.641307 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6463 12:38:46.643563 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6464 12:38:46.650294 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6465 12:38:46.653913 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6466 12:38:46.657111 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6467 12:38:46.663492 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6468 12:38:46.666619 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6469 12:38:46.670327 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6470 12:38:46.677014 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6471 12:38:46.677115 Total UI for P1: 0, mck2ui 16
6472 12:38:46.679904 best dqsien dly found for B0: ( 0, 10, 16)
6473 12:38:46.683589 Total UI for P1: 0, mck2ui 16
6474 12:38:46.686367 best dqsien dly found for B1: ( 0, 10, 16)
6475 12:38:46.692867 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6476 12:38:46.696887 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6477 12:38:46.696967
6478 12:38:46.700098 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6479 12:38:46.703391 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6480 12:38:46.706265 [Gating] SW calibration Done
6481 12:38:46.706345 ==
6482 12:38:46.711207 Dram Type= 6, Freq= 0, CH_1, rank 0
6483 12:38:46.712887 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6484 12:38:46.712968 ==
6485 12:38:46.716709 RX Vref Scan: 0
6486 12:38:46.716821
6487 12:38:46.716883 RX Vref 0 -> 0, step: 1
6488 12:38:46.716942
6489 12:38:46.719979 RX Delay -410 -> 252, step: 16
6490 12:38:46.726462 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6491 12:38:46.729982 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6492 12:38:46.733067 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6493 12:38:46.736575 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6494 12:38:46.742597 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6495 12:38:46.746615 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6496 12:38:46.749672 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6497 12:38:46.752499 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6498 12:38:46.759115 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6499 12:38:46.762734 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6500 12:38:46.765968 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6501 12:38:46.769378 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6502 12:38:46.776833 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6503 12:38:46.779102 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6504 12:38:46.782639 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6505 12:38:46.789095 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6506 12:38:46.789175 ==
6507 12:38:46.792613 Dram Type= 6, Freq= 0, CH_1, rank 0
6508 12:38:46.795470 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6509 12:38:46.795551 ==
6510 12:38:46.795614 DQS Delay:
6511 12:38:46.798690 DQS0 = 43, DQS1 = 59
6512 12:38:46.798771 DQM Delay:
6513 12:38:46.802210 DQM0 = 6, DQM1 = 15
6514 12:38:46.802291 DQ Delay:
6515 12:38:46.805349 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6516 12:38:46.808550 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6517 12:38:46.812077 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6518 12:38:46.815668 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6519 12:38:46.815749
6520 12:38:46.815811
6521 12:38:46.815870 ==
6522 12:38:46.818674 Dram Type= 6, Freq= 0, CH_1, rank 0
6523 12:38:46.821882 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6524 12:38:46.821963 ==
6525 12:38:46.822026
6526 12:38:46.822084
6527 12:38:46.825720 TX Vref Scan disable
6528 12:38:46.825801 == TX Byte 0 ==
6529 12:38:46.832069 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6530 12:38:46.835211 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6531 12:38:46.835293 == TX Byte 1 ==
6532 12:38:46.842065 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6533 12:38:46.845582 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6534 12:38:46.845663 ==
6535 12:38:46.848652 Dram Type= 6, Freq= 0, CH_1, rank 0
6536 12:38:46.851701 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6537 12:38:46.851799 ==
6538 12:38:46.854914
6539 12:38:46.854994
6540 12:38:46.855057 TX Vref Scan disable
6541 12:38:46.858491 == TX Byte 0 ==
6542 12:38:46.861385 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6543 12:38:46.865043 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6544 12:38:46.868869 == TX Byte 1 ==
6545 12:38:46.871862 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6546 12:38:46.874772 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6547 12:38:46.874863
6548 12:38:46.878743 [DATLAT]
6549 12:38:46.878824 Freq=400, CH1 RK0
6550 12:38:46.878888
6551 12:38:46.881911 DATLAT Default: 0xf
6552 12:38:46.881993 0, 0xFFFF, sum = 0
6553 12:38:46.885285 1, 0xFFFF, sum = 0
6554 12:38:46.885367 2, 0xFFFF, sum = 0
6555 12:38:46.888192 3, 0xFFFF, sum = 0
6556 12:38:46.888274 4, 0xFFFF, sum = 0
6557 12:38:46.891651 5, 0xFFFF, sum = 0
6558 12:38:46.891734 6, 0xFFFF, sum = 0
6559 12:38:46.894876 7, 0xFFFF, sum = 0
6560 12:38:46.894958 8, 0xFFFF, sum = 0
6561 12:38:46.898687 9, 0xFFFF, sum = 0
6562 12:38:46.898770 10, 0xFFFF, sum = 0
6563 12:38:46.901888 11, 0xFFFF, sum = 0
6564 12:38:46.901970 12, 0x0, sum = 1
6565 12:38:46.904830 13, 0x0, sum = 2
6566 12:38:46.904912 14, 0x0, sum = 3
6567 12:38:46.907748 15, 0x0, sum = 4
6568 12:38:46.907831 best_step = 13
6569 12:38:46.907894
6570 12:38:46.907957 ==
6571 12:38:46.911180 Dram Type= 6, Freq= 0, CH_1, rank 0
6572 12:38:46.918182 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6573 12:38:46.918264 ==
6574 12:38:46.918328 RX Vref Scan: 1
6575 12:38:46.918388
6576 12:38:46.921771 RX Vref 0 -> 0, step: 1
6577 12:38:46.921852
6578 12:38:46.924536 RX Delay -359 -> 252, step: 8
6579 12:38:46.924617
6580 12:38:46.927778 Set Vref, RX VrefLevel [Byte0]: 56
6581 12:38:46.930860 [Byte1]: 48
6582 12:38:46.934166
6583 12:38:46.934250 Final RX Vref Byte 0 = 56 to rank0
6584 12:38:46.937948 Final RX Vref Byte 1 = 48 to rank0
6585 12:38:46.941161 Final RX Vref Byte 0 = 56 to rank1
6586 12:38:46.944421 Final RX Vref Byte 1 = 48 to rank1==
6587 12:38:46.947374 Dram Type= 6, Freq= 0, CH_1, rank 0
6588 12:38:46.953965 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6589 12:38:46.954048 ==
6590 12:38:46.954112 DQS Delay:
6591 12:38:46.957455 DQS0 = 48, DQS1 = 68
6592 12:38:46.957536 DQM Delay:
6593 12:38:46.957600 DQM0 = 7, DQM1 = 20
6594 12:38:46.960892 DQ Delay:
6595 12:38:46.960974 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4
6596 12:38:46.964765 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =4
6597 12:38:46.967266 DQ8 =0, DQ9 =12, DQ10 =24, DQ11 =12
6598 12:38:46.970801 DQ12 =28, DQ13 =28, DQ14 =28, DQ15 =28
6599 12:38:46.970884
6600 12:38:46.970947
6601 12:38:46.981098 [DQSOSCAuto] RK0, (LSB)MR18= 0xe3e3, (MSB)MR19= 0xc0c, tDQSOscB0 = 381 ps tDQSOscB1 = 381 ps
6602 12:38:46.984208 CH1 RK0: MR19=C0C, MR18=E3E3
6603 12:38:46.990252 CH1_RK0: MR19=0xC0C, MR18=0xE3E3, DQSOSC=381, MR23=63, INC=406, DEC=271
6604 12:38:46.990333 ==
6605 12:38:46.993820 Dram Type= 6, Freq= 0, CH_1, rank 1
6606 12:38:46.997145 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6607 12:38:46.997227 ==
6608 12:38:47.000088 [Gating] SW mode calibration
6609 12:38:47.006895 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6610 12:38:47.013565 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6611 12:38:47.016683 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6612 12:38:47.020069 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6613 12:38:47.026993 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6614 12:38:47.030388 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6615 12:38:47.033761 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6616 12:38:47.040361 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6617 12:38:47.043297 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6618 12:38:47.047234 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6619 12:38:47.053692 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6620 12:38:47.053774 Total UI for P1: 0, mck2ui 16
6621 12:38:47.056407 best dqsien dly found for B0: ( 0, 10, 16)
6622 12:38:47.059961 Total UI for P1: 0, mck2ui 16
6623 12:38:47.063199 best dqsien dly found for B1: ( 0, 10, 16)
6624 12:38:47.069603 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6625 12:38:47.072801 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6626 12:38:47.072882
6627 12:38:47.077080 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6628 12:38:47.079918 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6629 12:38:47.083090 [Gating] SW calibration Done
6630 12:38:47.083172 ==
6631 12:38:47.086205 Dram Type= 6, Freq= 0, CH_1, rank 1
6632 12:38:47.089540 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6633 12:38:47.089623 ==
6634 12:38:47.093172 RX Vref Scan: 0
6635 12:38:47.093253
6636 12:38:47.093316 RX Vref 0 -> 0, step: 1
6637 12:38:47.093375
6638 12:38:47.096250 RX Delay -410 -> 252, step: 16
6639 12:38:47.102695 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6640 12:38:47.106480 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6641 12:38:47.109506 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6642 12:38:47.112623 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6643 12:38:47.119293 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6644 12:38:47.122448 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6645 12:38:47.125785 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6646 12:38:47.129501 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6647 12:38:47.136493 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6648 12:38:47.139384 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6649 12:38:47.143693 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6650 12:38:47.146102 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6651 12:38:47.153128 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6652 12:38:47.155797 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6653 12:38:47.159250 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6654 12:38:47.162815 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6655 12:38:47.166024 ==
6656 12:38:47.169275 Dram Type= 6, Freq= 0, CH_1, rank 1
6657 12:38:47.172469 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6658 12:38:47.172551 ==
6659 12:38:47.172615 DQS Delay:
6660 12:38:47.175557 DQS0 = 35, DQS1 = 59
6661 12:38:47.175638 DQM Delay:
6662 12:38:47.179457 DQM0 = 3, DQM1 = 18
6663 12:38:47.179539 DQ Delay:
6664 12:38:47.182527 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6665 12:38:47.186573 DQ4 =0, DQ5 =16, DQ6 =8, DQ7 =0
6666 12:38:47.189162 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6667 12:38:47.192153 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6668 12:38:47.192234
6669 12:38:47.192297
6670 12:38:47.192356 ==
6671 12:38:47.195336 Dram Type= 6, Freq= 0, CH_1, rank 1
6672 12:38:47.199058 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6673 12:38:47.199140 ==
6674 12:38:47.199204
6675 12:38:47.199263
6676 12:38:47.202110 TX Vref Scan disable
6677 12:38:47.202191 == TX Byte 0 ==
6678 12:38:47.208828 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6679 12:38:47.212081 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6680 12:38:47.212162 == TX Byte 1 ==
6681 12:38:47.218600 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6682 12:38:47.222548 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6683 12:38:47.222630 ==
6684 12:38:47.224886 Dram Type= 6, Freq= 0, CH_1, rank 1
6685 12:38:47.228352 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6686 12:38:47.228434 ==
6687 12:38:47.228498
6688 12:38:47.228557
6689 12:38:47.232106 TX Vref Scan disable
6690 12:38:47.232187 == TX Byte 0 ==
6691 12:38:47.238157 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6692 12:38:47.241911 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6693 12:38:47.241993 == TX Byte 1 ==
6694 12:38:47.249193 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6695 12:38:47.251410 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6696 12:38:47.251492
6697 12:38:47.251589 [DATLAT]
6698 12:38:47.254792 Freq=400, CH1 RK1
6699 12:38:47.254873
6700 12:38:47.254936 DATLAT Default: 0xd
6701 12:38:47.258536 0, 0xFFFF, sum = 0
6702 12:38:47.258619 1, 0xFFFF, sum = 0
6703 12:38:47.261992 2, 0xFFFF, sum = 0
6704 12:38:47.262075 3, 0xFFFF, sum = 0
6705 12:38:47.264585 4, 0xFFFF, sum = 0
6706 12:38:47.264668 5, 0xFFFF, sum = 0
6707 12:38:47.267863 6, 0xFFFF, sum = 0
6708 12:38:47.267946 7, 0xFFFF, sum = 0
6709 12:38:47.271577 8, 0xFFFF, sum = 0
6710 12:38:47.274580 9, 0xFFFF, sum = 0
6711 12:38:47.274664 10, 0xFFFF, sum = 0
6712 12:38:47.278397 11, 0xFFFF, sum = 0
6713 12:38:47.278480 12, 0x0, sum = 1
6714 12:38:47.281103 13, 0x0, sum = 2
6715 12:38:47.281186 14, 0x0, sum = 3
6716 12:38:47.281250 15, 0x0, sum = 4
6717 12:38:47.285320 best_step = 13
6718 12:38:47.285401
6719 12:38:47.285465 ==
6720 12:38:47.288275 Dram Type= 6, Freq= 0, CH_1, rank 1
6721 12:38:47.291394 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6722 12:38:47.291476 ==
6723 12:38:47.294656 RX Vref Scan: 0
6724 12:38:47.294737
6725 12:38:47.298221 RX Vref 0 -> 0, step: 1
6726 12:38:47.298302
6727 12:38:47.298365 RX Delay -359 -> 252, step: 8
6728 12:38:47.306457 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6729 12:38:47.309801 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6730 12:38:47.313496 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6731 12:38:47.316421 iDelay=225, Bit 3, Center -40 (-287 ~ 208) 496
6732 12:38:47.323173 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6733 12:38:47.326436 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6734 12:38:47.330182 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6735 12:38:47.332854 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6736 12:38:47.340550 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6737 12:38:47.343159 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6738 12:38:47.346696 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6739 12:38:47.352822 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6740 12:38:47.356820 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6741 12:38:47.360220 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6742 12:38:47.362657 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6743 12:38:47.369590 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
6744 12:38:47.369674 ==
6745 12:38:47.372251 Dram Type= 6, Freq= 0, CH_1, rank 1
6746 12:38:47.376504 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6747 12:38:47.376585 ==
6748 12:38:47.376649 DQS Delay:
6749 12:38:47.379229 DQS0 = 48, DQS1 = 64
6750 12:38:47.379309 DQM Delay:
6751 12:38:47.382318 DQM0 = 10, DQM1 = 15
6752 12:38:47.382399 DQ Delay:
6753 12:38:47.385997 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6754 12:38:47.389763 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6755 12:38:47.392737 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6756 12:38:47.395906 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6757 12:38:47.395986
6758 12:38:47.396050
6759 12:38:47.402752 [DQSOSCAuto] RK1, (LSB)MR18= 0xa6a6, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6760 12:38:47.405676 CH1 RK1: MR19=C0C, MR18=A6A6
6761 12:38:47.412062 CH1_RK1: MR19=0xC0C, MR18=0xA6A6, DQSOSC=389, MR23=63, INC=390, DEC=260
6762 12:38:47.415472 [RxdqsGatingPostProcess] freq 400
6763 12:38:47.422442 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6764 12:38:47.425604 Pre-setting of DQS Precalculation
6765 12:38:47.428906 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6766 12:38:47.435337 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6767 12:38:47.442188 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6768 12:38:47.445076
6769 12:38:47.445157
6770 12:38:47.445220 [Calibration Summary] 800 Mbps
6771 12:38:47.449195 CH 0, Rank 0
6772 12:38:47.449276 SW Impedance : PASS
6773 12:38:47.452150 DUTY Scan : NO K
6774 12:38:47.455432 ZQ Calibration : PASS
6775 12:38:47.455513 Jitter Meter : NO K
6776 12:38:47.459085 CBT Training : PASS
6777 12:38:47.461874 Write leveling : PASS
6778 12:38:47.461983 RX DQS gating : PASS
6779 12:38:47.465135 RX DQ/DQS(RDDQC) : PASS
6780 12:38:47.468113 TX DQ/DQS : PASS
6781 12:38:47.468195 RX DATLAT : PASS
6782 12:38:47.472488 RX DQ/DQS(Engine): PASS
6783 12:38:47.475094 TX OE : NO K
6784 12:38:47.475175 All Pass.
6785 12:38:47.475238
6786 12:38:47.475296 CH 0, Rank 1
6787 12:38:47.478774 SW Impedance : PASS
6788 12:38:47.481973 DUTY Scan : NO K
6789 12:38:47.482080 ZQ Calibration : PASS
6790 12:38:47.485427 Jitter Meter : NO K
6791 12:38:47.488353 CBT Training : PASS
6792 12:38:47.488433 Write leveling : NO K
6793 12:38:47.491466 RX DQS gating : PASS
6794 12:38:47.491547 RX DQ/DQS(RDDQC) : PASS
6795 12:38:47.495087 TX DQ/DQS : PASS
6796 12:38:47.498696 RX DATLAT : PASS
6797 12:38:47.498778 RX DQ/DQS(Engine): PASS
6798 12:38:47.501670 TX OE : NO K
6799 12:38:47.501756 All Pass.
6800 12:38:47.501910
6801 12:38:47.505099 CH 1, Rank 0
6802 12:38:47.505184 SW Impedance : PASS
6803 12:38:47.509456 DUTY Scan : NO K
6804 12:38:47.512132 ZQ Calibration : PASS
6805 12:38:47.512213 Jitter Meter : NO K
6806 12:38:47.515903 CBT Training : PASS
6807 12:38:47.519183 Write leveling : PASS
6808 12:38:47.519265 RX DQS gating : PASS
6809 12:38:47.521692 RX DQ/DQS(RDDQC) : PASS
6810 12:38:47.525208 TX DQ/DQS : PASS
6811 12:38:47.525290 RX DATLAT : PASS
6812 12:38:47.528295 RX DQ/DQS(Engine): PASS
6813 12:38:47.531762 TX OE : NO K
6814 12:38:47.531843 All Pass.
6815 12:38:47.531907
6816 12:38:47.531966 CH 1, Rank 1
6817 12:38:47.535074 SW Impedance : PASS
6818 12:38:47.538014 DUTY Scan : NO K
6819 12:38:47.538095 ZQ Calibration : PASS
6820 12:38:47.541436 Jitter Meter : NO K
6821 12:38:47.541518 CBT Training : PASS
6822 12:38:47.544668 Write leveling : NO K
6823 12:38:47.548134 RX DQS gating : PASS
6824 12:38:47.548215 RX DQ/DQS(RDDQC) : PASS
6825 12:38:47.551783 TX DQ/DQS : PASS
6826 12:38:47.555090 RX DATLAT : PASS
6827 12:38:47.555171 RX DQ/DQS(Engine): PASS
6828 12:38:47.558222 TX OE : NO K
6829 12:38:47.558304 All Pass.
6830 12:38:47.558368
6831 12:38:47.561166 DramC Write-DBI off
6832 12:38:47.564893 PER_BANK_REFRESH: Hybrid Mode
6833 12:38:47.564975 TX_TRACKING: ON
6834 12:38:47.574654 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6835 12:38:47.577589 [FAST_K] Save calibration result to emmc
6836 12:38:47.580971 dramc_set_vcore_voltage set vcore to 725000
6837 12:38:47.585020 Read voltage for 1600, 0
6838 12:38:47.585107 Vio18 = 0
6839 12:38:47.588111 Vcore = 725000
6840 12:38:47.588183 Vdram = 0
6841 12:38:47.588251 Vddq = 0
6842 12:38:47.588312 Vmddr = 0
6843 12:38:47.594846 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6844 12:38:47.597682 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6845 12:38:47.601267 MEM_TYPE=3, freq_sel=13
6846 12:38:47.604712 sv_algorithm_assistance_LP4_3733
6847 12:38:47.607612 ============ PULL DRAM RESETB DOWN ============
6848 12:38:47.614356 ========== PULL DRAM RESETB DOWN end =========
6849 12:38:47.617535 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6850 12:38:47.621034 ===================================
6851 12:38:47.624609 LPDDR4 DRAM CONFIGURATION
6852 12:38:47.627840 ===================================
6853 12:38:47.627923 EX_ROW_EN[0] = 0x0
6854 12:38:47.630743 EX_ROW_EN[1] = 0x0
6855 12:38:47.630825 LP4Y_EN = 0x0
6856 12:38:47.634433 WORK_FSP = 0x1
6857 12:38:47.634514 WL = 0x5
6858 12:38:47.638157 RL = 0x5
6859 12:38:47.638239 BL = 0x2
6860 12:38:47.641008 RPST = 0x0
6861 12:38:47.641088 RD_PRE = 0x0
6862 12:38:47.644254 WR_PRE = 0x1
6863 12:38:47.644326 WR_PST = 0x1
6864 12:38:47.648023 DBI_WR = 0x0
6865 12:38:47.651056 DBI_RD = 0x0
6866 12:38:47.651127 OTF = 0x1
6867 12:38:47.654311 ===================================
6868 12:38:47.657929 ===================================
6869 12:38:47.658008 ANA top config
6870 12:38:47.660992 ===================================
6871 12:38:47.664137 DLL_ASYNC_EN = 0
6872 12:38:47.667785 ALL_SLAVE_EN = 0
6873 12:38:47.670779 NEW_RANK_MODE = 1
6874 12:38:47.674619 DLL_IDLE_MODE = 1
6875 12:38:47.674742 LP45_APHY_COMB_EN = 1
6876 12:38:47.678751 TX_ODT_DIS = 0
6877 12:38:47.681372 NEW_8X_MODE = 1
6878 12:38:47.684157 ===================================
6879 12:38:47.687125 ===================================
6880 12:38:47.690826 data_rate = 3200
6881 12:38:47.693748 CKR = 1
6882 12:38:47.693830 DQ_P2S_RATIO = 8
6883 12:38:47.697619 ===================================
6884 12:38:47.700660 CA_P2S_RATIO = 8
6885 12:38:47.704209 DQ_CA_OPEN = 0
6886 12:38:47.707600 DQ_SEMI_OPEN = 0
6887 12:38:47.710462 CA_SEMI_OPEN = 0
6888 12:38:47.713768 CA_FULL_RATE = 0
6889 12:38:47.713851 DQ_CKDIV4_EN = 0
6890 12:38:47.717549 CA_CKDIV4_EN = 0
6891 12:38:47.720512 CA_PREDIV_EN = 0
6892 12:38:47.723985 PH8_DLY = 12
6893 12:38:47.727151 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6894 12:38:47.730996 DQ_AAMCK_DIV = 4
6895 12:38:47.731078 CA_AAMCK_DIV = 4
6896 12:38:47.733486 CA_ADMCK_DIV = 4
6897 12:38:47.736965 DQ_TRACK_CA_EN = 0
6898 12:38:47.740029 CA_PICK = 1600
6899 12:38:47.743789 CA_MCKIO = 1600
6900 12:38:47.748036 MCKIO_SEMI = 0
6901 12:38:47.750965 PLL_FREQ = 3068
6902 12:38:47.753688 DQ_UI_PI_RATIO = 32
6903 12:38:47.753770 CA_UI_PI_RATIO = 0
6904 12:38:47.757047 ===================================
6905 12:38:47.760115 ===================================
6906 12:38:47.763245 memory_type:LPDDR4
6907 12:38:47.766964 GP_NUM : 10
6908 12:38:47.767048 SRAM_EN : 1
6909 12:38:47.770104 MD32_EN : 0
6910 12:38:47.774388 ===================================
6911 12:38:47.776640 [ANA_INIT] >>>>>>>>>>>>>>
6912 12:38:47.780422 <<<<<< [CONFIGURE PHASE]: ANA_TX
6913 12:38:47.783761 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6914 12:38:47.786586 ===================================
6915 12:38:47.786669 data_rate = 3200,PCW = 0X7600
6916 12:38:47.790673 ===================================
6917 12:38:47.793524 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6918 12:38:47.799545 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6919 12:38:47.806568 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6920 12:38:47.810364 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6921 12:38:47.812968 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6922 12:38:47.817074 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6923 12:38:47.819656 [ANA_INIT] flow start
6924 12:38:47.822904 [ANA_INIT] PLL >>>>>>>>
6925 12:38:47.822986 [ANA_INIT] PLL <<<<<<<<
6926 12:38:47.826590 [ANA_INIT] MIDPI >>>>>>>>
6927 12:38:47.829899 [ANA_INIT] MIDPI <<<<<<<<
6928 12:38:47.829980 [ANA_INIT] DLL >>>>>>>>
6929 12:38:47.833060 [ANA_INIT] DLL <<<<<<<<
6930 12:38:47.836294 [ANA_INIT] flow end
6931 12:38:47.840220 ============ LP4 DIFF to SE enter ============
6932 12:38:47.842504 ============ LP4 DIFF to SE exit ============
6933 12:38:47.845950 [ANA_INIT] <<<<<<<<<<<<<
6934 12:38:47.849834 [Flow] Enable top DCM control >>>>>
6935 12:38:47.852691 [Flow] Enable top DCM control <<<<<
6936 12:38:47.855933 Enable DLL master slave shuffle
6937 12:38:47.859442 ==============================================================
6938 12:38:47.862081 Gating Mode config
6939 12:38:47.869159 ==============================================================
6940 12:38:47.869240 Config description:
6941 12:38:47.879736 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6942 12:38:47.885738 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6943 12:38:47.892355 SELPH_MODE 0: By rank 1: By Phase
6944 12:38:47.895369 ==============================================================
6945 12:38:47.899055 GAT_TRACK_EN = 1
6946 12:38:47.902725 RX_GATING_MODE = 2
6947 12:38:47.905236 RX_GATING_TRACK_MODE = 2
6948 12:38:47.909062 SELPH_MODE = 1
6949 12:38:47.912141 PICG_EARLY_EN = 1
6950 12:38:47.915511 VALID_LAT_VALUE = 1
6951 12:38:47.918698 ==============================================================
6952 12:38:47.922184 Enter into Gating configuration >>>>
6953 12:38:47.925663 Exit from Gating configuration <<<<
6954 12:38:47.928916 Enter into DVFS_PRE_config >>>>>
6955 12:38:47.942058 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6956 12:38:47.945817 Exit from DVFS_PRE_config <<<<<
6957 12:38:47.948959 Enter into PICG configuration >>>>
6958 12:38:47.949045 Exit from PICG configuration <<<<
6959 12:38:47.952055 [RX_INPUT] configuration >>>>>
6960 12:38:47.955221 [RX_INPUT] configuration <<<<<
6961 12:38:47.961797 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6962 12:38:47.965351 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6963 12:38:47.972080 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6964 12:38:47.978026 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6965 12:38:47.984955 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6966 12:38:47.991873 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6967 12:38:47.994959 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6968 12:38:47.998204 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6969 12:38:48.003556 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6970 12:38:48.008841 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6971 12:38:48.012281 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6972 12:38:48.015674 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6973 12:38:48.018438 ===================================
6974 12:38:48.021554 LPDDR4 DRAM CONFIGURATION
6975 12:38:48.024660 ===================================
6976 12:38:48.028491 EX_ROW_EN[0] = 0x0
6977 12:38:48.028573 EX_ROW_EN[1] = 0x0
6978 12:38:48.031371 LP4Y_EN = 0x0
6979 12:38:48.031453 WORK_FSP = 0x1
6980 12:38:48.034745 WL = 0x5
6981 12:38:48.034826 RL = 0x5
6982 12:38:48.038201 BL = 0x2
6983 12:38:48.038282 RPST = 0x0
6984 12:38:48.041622 RD_PRE = 0x0
6985 12:38:48.041706 WR_PRE = 0x1
6986 12:38:48.044745 WR_PST = 0x1
6987 12:38:48.044841 DBI_WR = 0x0
6988 12:38:48.047864 DBI_RD = 0x0
6989 12:38:48.047945 OTF = 0x1
6990 12:38:48.051384 ===================================
6991 12:38:48.058335 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6992 12:38:48.062297 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6993 12:38:48.064404 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6994 12:38:48.068879 ===================================
6995 12:38:48.071890 LPDDR4 DRAM CONFIGURATION
6996 12:38:48.074269 ===================================
6997 12:38:48.077882 EX_ROW_EN[0] = 0x10
6998 12:38:48.077964 EX_ROW_EN[1] = 0x0
6999 12:38:48.081231 LP4Y_EN = 0x0
7000 12:38:48.081312 WORK_FSP = 0x1
7001 12:38:48.085160 WL = 0x5
7002 12:38:48.085242 RL = 0x5
7003 12:38:48.087684 BL = 0x2
7004 12:38:48.087764 RPST = 0x0
7005 12:38:48.091036 RD_PRE = 0x0
7006 12:38:48.091118 WR_PRE = 0x1
7007 12:38:48.094418 WR_PST = 0x1
7008 12:38:48.094500 DBI_WR = 0x0
7009 12:38:48.098512 DBI_RD = 0x0
7010 12:38:48.098593 OTF = 0x1
7011 12:38:48.101142 ===================================
7012 12:38:48.108388 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7013 12:38:48.108470 ==
7014 12:38:48.111084 Dram Type= 6, Freq= 0, CH_0, rank 0
7015 12:38:48.117474 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7016 12:38:48.117556 ==
7017 12:38:48.117620 [Duty_Offset_Calibration]
7018 12:38:48.120866 B0:0 B1:2 CA:1
7019 12:38:48.120948
7020 12:38:48.124314 [DutyScan_Calibration_Flow] k_type=0
7021 12:38:48.133755
7022 12:38:48.133836 ==CLK 0==
7023 12:38:48.137044 Final CLK duty delay cell = 0
7024 12:38:48.139861 [0] MAX Duty = 5187%(X100), DQS PI = 24
7025 12:38:48.143730 [0] MIN Duty = 4938%(X100), DQS PI = 54
7026 12:38:48.146228 [0] AVG Duty = 5062%(X100)
7027 12:38:48.146310
7028 12:38:48.149919 CH0 CLK Duty spec in!! Max-Min= 249%
7029 12:38:48.153012 [DutyScan_Calibration_Flow] ====Done====
7030 12:38:48.153094
7031 12:38:48.156132 [DutyScan_Calibration_Flow] k_type=1
7032 12:38:48.173643
7033 12:38:48.173724 ==DQS 0 ==
7034 12:38:48.176931 Final DQS duty delay cell = 0
7035 12:38:48.179794 [0] MAX Duty = 5156%(X100), DQS PI = 34
7036 12:38:48.183572 [0] MIN Duty = 5031%(X100), DQS PI = 8
7037 12:38:48.186896 [0] AVG Duty = 5093%(X100)
7038 12:38:48.186977
7039 12:38:48.187041 ==DQS 1 ==
7040 12:38:48.190245 Final DQS duty delay cell = 0
7041 12:38:48.193136 [0] MAX Duty = 5031%(X100), DQS PI = 2
7042 12:38:48.196936 [0] MIN Duty = 4876%(X100), DQS PI = 18
7043 12:38:48.199718 [0] AVG Duty = 4953%(X100)
7044 12:38:48.199800
7045 12:38:48.203136 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7046 12:38:48.203218
7047 12:38:48.206511 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7048 12:38:48.209956 [DutyScan_Calibration_Flow] ====Done====
7049 12:38:48.210037
7050 12:38:48.212852 [DutyScan_Calibration_Flow] k_type=3
7051 12:38:48.232202
7052 12:38:48.232283 ==DQM 0 ==
7053 12:38:48.233846 Final DQM duty delay cell = 0
7054 12:38:48.237188 [0] MAX Duty = 5218%(X100), DQS PI = 22
7055 12:38:48.240873 [0] MIN Duty = 4907%(X100), DQS PI = 58
7056 12:38:48.244593 [0] AVG Duty = 5062%(X100)
7057 12:38:48.244674
7058 12:38:48.244783 ==DQM 1 ==
7059 12:38:48.247432 Final DQM duty delay cell = 0
7060 12:38:48.250181 [0] MAX Duty = 5031%(X100), DQS PI = 50
7061 12:38:48.253458 [0] MIN Duty = 4782%(X100), DQS PI = 14
7062 12:38:48.257028 [0] AVG Duty = 4906%(X100)
7063 12:38:48.257110
7064 12:38:48.260184 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7065 12:38:48.260266
7066 12:38:48.263418 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7067 12:38:48.267681 [DutyScan_Calibration_Flow] ====Done====
7068 12:38:48.267763
7069 12:38:48.270375 [DutyScan_Calibration_Flow] k_type=2
7070 12:38:48.286593
7071 12:38:48.286674 ==DQ 0 ==
7072 12:38:48.290466 Final DQ duty delay cell = 0
7073 12:38:48.293503 [0] MAX Duty = 5187%(X100), DQS PI = 16
7074 12:38:48.297518 [0] MIN Duty = 4938%(X100), DQS PI = 56
7075 12:38:48.297599 [0] AVG Duty = 5062%(X100)
7076 12:38:48.300509
7077 12:38:48.300590 ==DQ 1 ==
7078 12:38:48.303772 Final DQ duty delay cell = -4
7079 12:38:48.307110 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7080 12:38:48.310372 [-4] MIN Duty = 4844%(X100), DQS PI = 36
7081 12:38:48.313380 [-4] AVG Duty = 4953%(X100)
7082 12:38:48.313462
7083 12:38:48.316386 CH0 DQ 0 Duty spec in!! Max-Min= 249%
7084 12:38:48.316467
7085 12:38:48.320077 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7086 12:38:48.323411 [DutyScan_Calibration_Flow] ====Done====
7087 12:38:48.323492 ==
7088 12:38:48.326441 Dram Type= 6, Freq= 0, CH_1, rank 0
7089 12:38:48.330099 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7090 12:38:48.330181 ==
7091 12:38:48.333232 [Duty_Offset_Calibration]
7092 12:38:48.333313 B0:0 B1:5 CA:-5
7093 12:38:48.333376
7094 12:38:48.336163 [DutyScan_Calibration_Flow] k_type=0
7095 12:38:48.347846
7096 12:38:48.347930 ==CLK 0==
7097 12:38:48.350770 Final CLK duty delay cell = 0
7098 12:38:48.354004 [0] MAX Duty = 5156%(X100), DQS PI = 20
7099 12:38:48.357553 [0] MIN Duty = 4906%(X100), DQS PI = 52
7100 12:38:48.357634 [0] AVG Duty = 5031%(X100)
7101 12:38:48.362272
7102 12:38:48.364241 CH1 CLK Duty spec in!! Max-Min= 250%
7103 12:38:48.367873 [DutyScan_Calibration_Flow] ====Done====
7104 12:38:48.367955
7105 12:38:48.370669 [DutyScan_Calibration_Flow] k_type=1
7106 12:38:48.386627
7107 12:38:48.386710 ==DQS 0 ==
7108 12:38:48.389909 Final DQS duty delay cell = 0
7109 12:38:48.393069 [0] MAX Duty = 5156%(X100), DQS PI = 18
7110 12:38:48.396200 [0] MIN Duty = 4907%(X100), DQS PI = 42
7111 12:38:48.399390 [0] AVG Duty = 5031%(X100)
7112 12:38:48.399471
7113 12:38:48.399535 ==DQS 1 ==
7114 12:38:48.402897 Final DQS duty delay cell = -4
7115 12:38:48.406526 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7116 12:38:48.409447 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7117 12:38:48.412694 [-4] AVG Duty = 4922%(X100)
7118 12:38:48.412785
7119 12:38:48.416151 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7120 12:38:48.416233
7121 12:38:48.419544 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7122 12:38:48.422580 [DutyScan_Calibration_Flow] ====Done====
7123 12:38:48.422665
7124 12:38:48.425874 [DutyScan_Calibration_Flow] k_type=3
7125 12:38:48.441884
7126 12:38:48.441966 ==DQM 0 ==
7127 12:38:48.445421 Final DQM duty delay cell = -4
7128 12:38:48.448677 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7129 12:38:48.452055 [-4] MIN Duty = 4813%(X100), DQS PI = 42
7130 12:38:48.455451 [-4] AVG Duty = 4953%(X100)
7131 12:38:48.455533
7132 12:38:48.455597 ==DQM 1 ==
7133 12:38:48.458827 Final DQM duty delay cell = -4
7134 12:38:48.462375 [-4] MAX Duty = 5062%(X100), DQS PI = 14
7135 12:38:48.465747 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7136 12:38:48.468899 [-4] AVG Duty = 4984%(X100)
7137 12:38:48.468981
7138 12:38:48.471734 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7139 12:38:48.471815
7140 12:38:48.476976 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7141 12:38:48.478753 [DutyScan_Calibration_Flow] ====Done====
7142 12:38:48.478835
7143 12:38:48.481836 [DutyScan_Calibration_Flow] k_type=2
7144 12:38:48.499870
7145 12:38:48.499952 ==DQ 0 ==
7146 12:38:48.503769 Final DQ duty delay cell = 0
7147 12:38:48.506210 [0] MAX Duty = 5093%(X100), DQS PI = 20
7148 12:38:48.510068 [0] MIN Duty = 4938%(X100), DQS PI = 46
7149 12:38:48.510151 [0] AVG Duty = 5015%(X100)
7150 12:38:48.513200
7151 12:38:48.513280 ==DQ 1 ==
7152 12:38:48.516728 Final DQ duty delay cell = 0
7153 12:38:48.519581 [0] MAX Duty = 5031%(X100), DQS PI = 4
7154 12:38:48.522764 [0] MIN Duty = 4907%(X100), DQS PI = 22
7155 12:38:48.522846 [0] AVG Duty = 4969%(X100)
7156 12:38:48.522910
7157 12:38:48.529400 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7158 12:38:48.529482
7159 12:38:48.532834 CH1 DQ 1 Duty spec in!! Max-Min= 124%
7160 12:38:48.535979 [DutyScan_Calibration_Flow] ====Done====
7161 12:38:48.539797 nWR fixed to 30
7162 12:38:48.539880 [ModeRegInit_LP4] CH0 RK0
7163 12:38:48.543334 [ModeRegInit_LP4] CH0 RK1
7164 12:38:48.546684 [ModeRegInit_LP4] CH1 RK0
7165 12:38:48.549228 [ModeRegInit_LP4] CH1 RK1
7166 12:38:48.549309 match AC timing 4
7167 12:38:48.552621 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7168 12:38:48.558982 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7169 12:38:48.562811 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7170 12:38:48.568825 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7171 12:38:48.572673 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7172 12:38:48.572800 [MiockJmeterHQA]
7173 12:38:48.572865
7174 12:38:48.575546 [DramcMiockJmeter] u1RxGatingPI = 0
7175 12:38:48.579808 0 : 4257, 4029
7176 12:38:48.579892 4 : 4255, 4030
7177 12:38:48.582295 8 : 4252, 4027
7178 12:38:48.582378 12 : 4253, 4027
7179 12:38:48.582444 16 : 4255, 4029
7180 12:38:48.586036 20 : 4363, 4137
7181 12:38:48.586119 24 : 4252, 4027
7182 12:38:48.589347 28 : 4363, 4137
7183 12:38:48.589429 32 : 4255, 4029
7184 12:38:48.593013 36 : 4253, 4027
7185 12:38:48.593096 40 : 4252, 4027
7186 12:38:48.595499 44 : 4252, 4027
7187 12:38:48.595582 48 : 4363, 4137
7188 12:38:48.595647 52 : 4252, 4027
7189 12:38:48.598934 56 : 4363, 4138
7190 12:38:48.599020 60 : 4250, 4027
7191 12:38:48.602377 64 : 4250, 4027
7192 12:38:48.602460 68 : 4250, 4027
7193 12:38:48.605248 72 : 4361, 4138
7194 12:38:48.605332 76 : 4250, 4027
7195 12:38:48.608667 80 : 4360, 4137
7196 12:38:48.608774 84 : 4249, 4027
7197 12:38:48.608840 88 : 4250, 4027
7198 12:38:48.612386 92 : 4250, 4027
7199 12:38:48.612468 96 : 4250, 4027
7200 12:38:48.615085 100 : 4361, 2587
7201 12:38:48.615201 104 : 4250, 0
7202 12:38:48.618608 108 : 4250, 0
7203 12:38:48.618691 112 : 4252, 0
7204 12:38:48.618755 116 : 4249, 0
7205 12:38:48.621746 120 : 4250, 0
7206 12:38:48.621829 124 : 4253, 0
7207 12:38:48.625918 128 : 4360, 0
7208 12:38:48.626000 132 : 4360, 0
7209 12:38:48.626065 136 : 4363, 0
7210 12:38:48.628569 140 : 4250, 0
7211 12:38:48.628652 144 : 4250, 0
7212 12:38:48.631614 148 : 4250, 0
7213 12:38:48.631697 152 : 4250, 0
7214 12:38:48.631761 156 : 4250, 0
7215 12:38:48.635710 160 : 4250, 0
7216 12:38:48.635793 164 : 4252, 0
7217 12:38:48.638330 168 : 4250, 0
7218 12:38:48.638413 172 : 4360, 0
7219 12:38:48.638478 176 : 4250, 0
7220 12:38:48.641676 180 : 4249, 0
7221 12:38:48.641760 184 : 4361, 0
7222 12:38:48.641825 188 : 4360, 0
7223 12:38:48.645002 192 : 4250, 0
7224 12:38:48.645085 196 : 4250, 0
7225 12:38:48.648207 200 : 4250, 0
7226 12:38:48.648289 204 : 4250, 0
7227 12:38:48.648354 208 : 4250, 0
7228 12:38:48.652369 212 : 4250, 0
7229 12:38:48.652452 216 : 4250, 0
7230 12:38:48.655533 220 : 4361, 647
7231 12:38:48.655616 224 : 4250, 3971
7232 12:38:48.658179 228 : 4250, 4027
7233 12:38:48.658262 232 : 4250, 4027
7234 12:38:48.661518 236 : 4361, 4137
7235 12:38:48.661600 240 : 4250, 4027
7236 12:38:48.661666 244 : 4250, 4027
7237 12:38:48.665007 248 : 4361, 4137
7238 12:38:48.665091 252 : 4361, 4138
7239 12:38:48.668089 256 : 4247, 4025
7240 12:38:48.668172 260 : 4360, 4138
7241 12:38:48.671151 264 : 4361, 4137
7242 12:38:48.671234 268 : 4250, 4027
7243 12:38:48.674869 272 : 4250, 4027
7244 12:38:48.674952 276 : 4250, 4027
7245 12:38:48.677621 280 : 4250, 4027
7246 12:38:48.677717 284 : 4250, 4027
7247 12:38:48.681428 288 : 4250, 4027
7248 12:38:48.681511 292 : 4250, 4027
7249 12:38:48.684817 296 : 4250, 4027
7250 12:38:48.684901 300 : 4361, 4137
7251 12:38:48.688442 304 : 4360, 4138
7252 12:38:48.688525 308 : 4247, 4025
7253 12:38:48.688590 312 : 4360, 4138
7254 12:38:48.691460 316 : 4361, 4137
7255 12:38:48.691543 320 : 4250, 4027
7256 12:38:48.694370 324 : 4250, 4027
7257 12:38:48.694453 328 : 4250, 4027
7258 12:38:48.697788 332 : 4250, 4027
7259 12:38:48.697871 336 : 4250, 3950
7260 12:38:48.701265 340 : 4249, 2033
7261 12:38:48.701347
7262 12:38:48.704391 MIOCK jitter meter ch=0
7263 12:38:48.704473
7264 12:38:48.704536 1T = (340-104) = 236 dly cells
7265 12:38:48.710633 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7266 12:38:48.710715 ==
7267 12:38:48.714351 Dram Type= 6, Freq= 0, CH_0, rank 0
7268 12:38:48.717315 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7269 12:38:48.722230 ==
7270 12:38:48.724287 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7271 12:38:48.727439 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7272 12:38:48.733954 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7273 12:38:48.740589 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7274 12:38:48.747233 [CA 0] Center 42 (12~72) winsize 61
7275 12:38:48.750727 [CA 1] Center 41 (11~72) winsize 62
7276 12:38:48.753877 [CA 2] Center 37 (7~67) winsize 61
7277 12:38:48.756698 [CA 3] Center 37 (7~67) winsize 61
7278 12:38:48.760309 [CA 4] Center 35 (5~66) winsize 62
7279 12:38:48.763336 [CA 5] Center 35 (5~65) winsize 61
7280 12:38:48.763418
7281 12:38:48.766666 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7282 12:38:48.766748
7283 12:38:48.769986 [CATrainingPosCal] consider 1 rank data
7284 12:38:48.773153 u2DelayCellTimex100 = 275/100 ps
7285 12:38:48.776920 CA0 delay=42 (12~72),Diff = 7 PI (24 cell)
7286 12:38:48.783394 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7287 12:38:48.787162 CA2 delay=37 (7~67),Diff = 2 PI (7 cell)
7288 12:38:48.789805 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7289 12:38:48.793120 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7290 12:38:48.796665 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7291 12:38:48.796757
7292 12:38:48.799857 CA PerBit enable=1, Macro0, CA PI delay=35
7293 12:38:48.799939
7294 12:38:48.803061 [CBTSetCACLKResult] CA Dly = 35
7295 12:38:48.806979 CS Dly: 11 (0~42)
7296 12:38:48.809932 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7297 12:38:48.813446 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7298 12:38:48.813528 ==
7299 12:38:48.816329 Dram Type= 6, Freq= 0, CH_0, rank 1
7300 12:38:48.820179 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7301 12:38:48.823222 ==
7302 12:38:48.827006 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7303 12:38:48.829574 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7304 12:38:48.836326 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7305 12:38:48.842907 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7306 12:38:48.849637 [CA 0] Center 42 (12~73) winsize 62
7307 12:38:48.853585 [CA 1] Center 42 (12~73) winsize 62
7308 12:38:48.856272 [CA 2] Center 38 (9~68) winsize 60
7309 12:38:48.859866 [CA 3] Center 37 (8~67) winsize 60
7310 12:38:48.862952 [CA 4] Center 36 (6~66) winsize 61
7311 12:38:48.865870 [CA 5] Center 36 (6~66) winsize 61
7312 12:38:48.865952
7313 12:38:48.869409 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7314 12:38:48.869490
7315 12:38:48.873066 [CATrainingPosCal] consider 2 rank data
7316 12:38:48.875831 u2DelayCellTimex100 = 275/100 ps
7317 12:38:48.879548 CA0 delay=42 (12~72),Diff = 7 PI (24 cell)
7318 12:38:48.885876 CA1 delay=42 (12~72),Diff = 7 PI (24 cell)
7319 12:38:48.889479 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7320 12:38:48.892560 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7321 12:38:48.897076 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7322 12:38:48.899949 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7323 12:38:48.900031
7324 12:38:48.902289 CA PerBit enable=1, Macro0, CA PI delay=35
7325 12:38:48.902370
7326 12:38:48.905920 [CBTSetCACLKResult] CA Dly = 35
7327 12:38:48.909055 CS Dly: 11 (0~42)
7328 12:38:48.912235 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7329 12:38:48.915499 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7330 12:38:48.915598
7331 12:38:48.919033 ----->DramcWriteLeveling(PI) begin...
7332 12:38:48.919116 ==
7333 12:38:48.923964 Dram Type= 6, Freq= 0, CH_0, rank 0
7334 12:38:48.929421 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7335 12:38:48.929504 ==
7336 12:38:48.932322 Write leveling (Byte 0): 29 => 29
7337 12:38:48.932403 Write leveling (Byte 1): 27 => 27
7338 12:38:48.935346 DramcWriteLeveling(PI) end<-----
7339 12:38:48.935426
7340 12:38:48.935489 ==
7341 12:38:48.939290 Dram Type= 6, Freq= 0, CH_0, rank 0
7342 12:38:48.945886 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7343 12:38:48.945968 ==
7344 12:38:48.949074 [Gating] SW mode calibration
7345 12:38:48.955561 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7346 12:38:48.958751 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7347 12:38:48.965242 0 12 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7348 12:38:48.968743 0 12 4 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
7349 12:38:48.972080 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7350 12:38:48.978555 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7351 12:38:48.982215 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7352 12:38:48.985209 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7353 12:38:48.991897 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7354 12:38:48.995218 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7355 12:38:48.998679 0 13 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7356 12:38:49.005060 0 13 4 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
7357 12:38:49.009532 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7358 12:38:49.012460 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7359 12:38:49.018528 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7360 12:38:49.022030 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7361 12:38:49.025383 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7362 12:38:49.031863 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7363 12:38:49.034902 0 14 0 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7364 12:38:49.039054 0 14 4 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
7365 12:38:49.041574 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7366 12:38:49.048388 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7367 12:38:49.051964 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7368 12:38:49.055311 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7369 12:38:49.061406 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7370 12:38:49.065244 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7371 12:38:49.068533 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7372 12:38:49.074557 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7373 12:38:49.078486 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7374 12:38:49.081570 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7375 12:38:49.087739 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7376 12:38:49.091849 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7377 12:38:49.095000 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7378 12:38:49.101347 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7379 12:38:49.104506 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7380 12:38:49.108402 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7381 12:38:49.114968 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7382 12:38:49.118157 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7383 12:38:49.121381 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7384 12:38:49.128143 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7385 12:38:49.131354 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7386 12:38:49.134544 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7387 12:38:49.141103 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7388 12:38:49.144512 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7389 12:38:49.148836 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7390 12:38:49.150869 Total UI for P1: 0, mck2ui 16
7391 12:38:49.154330 best dqsien dly found for B0: ( 1, 1, 2)
7392 12:38:49.158416 Total UI for P1: 0, mck2ui 16
7393 12:38:49.161085 best dqsien dly found for B1: ( 1, 1, 4)
7394 12:38:49.164372 best DQS0 dly(MCK, UI, PI) = (1, 1, 2)
7395 12:38:49.168323 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7396 12:38:49.168427
7397 12:38:49.171228 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 2)
7398 12:38:49.177689 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7399 12:38:49.177794 [Gating] SW calibration Done
7400 12:38:49.177887 ==
7401 12:38:49.181130 Dram Type= 6, Freq= 0, CH_0, rank 0
7402 12:38:49.188297 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7403 12:38:49.188406 ==
7404 12:38:49.188500 RX Vref Scan: 0
7405 12:38:49.188587
7406 12:38:49.191210 RX Vref 0 -> 0, step: 1
7407 12:38:49.191304
7408 12:38:49.194205 RX Delay 0 -> 252, step: 8
7409 12:38:49.197185 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7410 12:38:49.200663 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7411 12:38:49.203854 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7412 12:38:49.210638 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7413 12:38:49.213809 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7414 12:38:49.217364 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
7415 12:38:49.221012 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7416 12:38:49.224276 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7417 12:38:49.230586 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7418 12:38:49.234040 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7419 12:38:49.238064 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7420 12:38:49.240538 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7421 12:38:49.244555 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7422 12:38:49.250193 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7423 12:38:49.253487 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7424 12:38:49.257272 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7425 12:38:49.257354 ==
7426 12:38:49.260416 Dram Type= 6, Freq= 0, CH_0, rank 0
7427 12:38:49.264235 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7428 12:38:49.264318 ==
7429 12:38:49.266970 DQS Delay:
7430 12:38:49.267051 DQS0 = 0, DQS1 = 0
7431 12:38:49.270687 DQM Delay:
7432 12:38:49.270768 DQM0 = 130, DQM1 = 123
7433 12:38:49.273734 DQ Delay:
7434 12:38:49.277989 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7435 12:38:49.279983 DQ4 =135, DQ5 =115, DQ6 =139, DQ7 =139
7436 12:38:49.283979 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
7437 12:38:49.286812 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7438 12:38:49.286894
7439 12:38:49.286956
7440 12:38:49.287014 ==
7441 12:38:49.290117 Dram Type= 6, Freq= 0, CH_0, rank 0
7442 12:38:49.293653 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7443 12:38:49.293735 ==
7444 12:38:49.293799
7445 12:38:49.293859
7446 12:38:49.296754 TX Vref Scan disable
7447 12:38:49.300077 == TX Byte 0 ==
7448 12:38:49.303603 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7449 12:38:49.306382 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7450 12:38:49.309999 == TX Byte 1 ==
7451 12:38:49.313065 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7452 12:38:49.316751 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7453 12:38:49.316833 ==
7454 12:38:49.319652 Dram Type= 6, Freq= 0, CH_0, rank 0
7455 12:38:49.327270 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7456 12:38:49.327352 ==
7457 12:38:49.338006
7458 12:38:49.341887 TX Vref early break, caculate TX vref
7459 12:38:49.345172 TX Vref=16, minBit 8, minWin=22, winSum=371
7460 12:38:49.347806 TX Vref=18, minBit 8, minWin=22, winSum=383
7461 12:38:49.351447 TX Vref=20, minBit 8, minWin=23, winSum=389
7462 12:38:49.354789 TX Vref=22, minBit 1, minWin=24, winSum=397
7463 12:38:49.358141 TX Vref=24, minBit 8, minWin=24, winSum=406
7464 12:38:49.364887 TX Vref=26, minBit 8, minWin=24, winSum=413
7465 12:38:49.368296 TX Vref=28, minBit 0, minWin=25, winSum=414
7466 12:38:49.371683 TX Vref=30, minBit 0, minWin=25, winSum=408
7467 12:38:49.374578 TX Vref=32, minBit 1, minWin=24, winSum=401
7468 12:38:49.378691 TX Vref=34, minBit 8, minWin=23, winSum=390
7469 12:38:49.384457 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 28
7470 12:38:49.384539
7471 12:38:49.387711 Final TX Range 0 Vref 28
7472 12:38:49.387794
7473 12:38:49.387859 ==
7474 12:38:49.390979 Dram Type= 6, Freq= 0, CH_0, rank 0
7475 12:38:49.394987 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7476 12:38:49.395069 ==
7477 12:38:49.395134
7478 12:38:49.395192
7479 12:38:49.397329 TX Vref Scan disable
7480 12:38:49.404132 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7481 12:38:49.404214 == TX Byte 0 ==
7482 12:38:49.407244 u2DelayCellOfst[0]=10 cells (3 PI)
7483 12:38:49.411099 u2DelayCellOfst[1]=17 cells (5 PI)
7484 12:38:49.414271 u2DelayCellOfst[2]=10 cells (3 PI)
7485 12:38:49.417774 u2DelayCellOfst[3]=10 cells (3 PI)
7486 12:38:49.420874 u2DelayCellOfst[4]=7 cells (2 PI)
7487 12:38:49.423993 u2DelayCellOfst[5]=0 cells (0 PI)
7488 12:38:49.427541 u2DelayCellOfst[6]=17 cells (5 PI)
7489 12:38:49.430956 u2DelayCellOfst[7]=14 cells (4 PI)
7490 12:38:49.434147 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7491 12:38:49.437733 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7492 12:38:49.441152 == TX Byte 1 ==
7493 12:38:49.441233 u2DelayCellOfst[8]=3 cells (1 PI)
7494 12:38:49.443892 u2DelayCellOfst[9]=0 cells (0 PI)
7495 12:38:49.447598 u2DelayCellOfst[10]=14 cells (4 PI)
7496 12:38:49.451602 u2DelayCellOfst[11]=7 cells (2 PI)
7497 12:38:49.454546 u2DelayCellOfst[12]=14 cells (4 PI)
7498 12:38:49.458133 u2DelayCellOfst[13]=17 cells (5 PI)
7499 12:38:49.460494 u2DelayCellOfst[14]=21 cells (6 PI)
7500 12:38:49.463602 u2DelayCellOfst[15]=17 cells (5 PI)
7501 12:38:49.467427 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7502 12:38:49.473916 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7503 12:38:49.473998 DramC Write-DBI on
7504 12:38:49.474062 ==
7505 12:38:49.477178 Dram Type= 6, Freq= 0, CH_0, rank 0
7506 12:38:49.483547 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7507 12:38:49.483630 ==
7508 12:38:49.483694
7509 12:38:49.483753
7510 12:38:49.483810 TX Vref Scan disable
7511 12:38:49.487911 == TX Byte 0 ==
7512 12:38:49.491153 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7513 12:38:49.494599 == TX Byte 1 ==
7514 12:38:49.497356 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7515 12:38:49.501095 DramC Write-DBI off
7516 12:38:49.501177
7517 12:38:49.501240 [DATLAT]
7518 12:38:49.501300 Freq=1600, CH0 RK0
7519 12:38:49.501358
7520 12:38:49.504286 DATLAT Default: 0xf
7521 12:38:49.504367 0, 0xFFFF, sum = 0
7522 12:38:49.507022 1, 0xFFFF, sum = 0
7523 12:38:49.510949 2, 0xFFFF, sum = 0
7524 12:38:49.511032 3, 0xFFFF, sum = 0
7525 12:38:49.514181 4, 0xFFFF, sum = 0
7526 12:38:49.514264 5, 0xFFFF, sum = 0
7527 12:38:49.517381 6, 0xFFFF, sum = 0
7528 12:38:49.517464 7, 0xFFFF, sum = 0
7529 12:38:49.520446 8, 0xFFFF, sum = 0
7530 12:38:49.520529 9, 0xFFFF, sum = 0
7531 12:38:49.524489 10, 0xFFFF, sum = 0
7532 12:38:49.524573 11, 0xFFFF, sum = 0
7533 12:38:49.527273 12, 0xBFF, sum = 0
7534 12:38:49.527356 13, 0x0, sum = 1
7535 12:38:49.530347 14, 0x0, sum = 2
7536 12:38:49.530429 15, 0x0, sum = 3
7537 12:38:49.533813 16, 0x0, sum = 4
7538 12:38:49.533897 best_step = 14
7539 12:38:49.533960
7540 12:38:49.534020 ==
7541 12:38:49.537283 Dram Type= 6, Freq= 0, CH_0, rank 0
7542 12:38:49.540499 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7543 12:38:49.543845 ==
7544 12:38:49.543952 RX Vref Scan: 1
7545 12:38:49.544043
7546 12:38:49.549598 Set Vref Range= 24 -> 127
7547 12:38:49.549681
7548 12:38:49.550144 RX Vref 24 -> 127, step: 1
7549 12:38:49.550225
7550 12:38:49.550288 RX Delay 11 -> 252, step: 4
7551 12:38:49.550349
7552 12:38:49.554118 Set Vref, RX VrefLevel [Byte0]: 24
7553 12:38:49.556666 [Byte1]: 24
7554 12:38:49.561020
7555 12:38:49.561101 Set Vref, RX VrefLevel [Byte0]: 25
7556 12:38:49.563971 [Byte1]: 25
7557 12:38:49.569061
7558 12:38:49.569141 Set Vref, RX VrefLevel [Byte0]: 26
7559 12:38:49.571722 [Byte1]: 26
7560 12:38:49.576440
7561 12:38:49.576521 Set Vref, RX VrefLevel [Byte0]: 27
7562 12:38:49.579537 [Byte1]: 27
7563 12:38:49.584199
7564 12:38:49.584279 Set Vref, RX VrefLevel [Byte0]: 28
7565 12:38:49.586920 [Byte1]: 28
7566 12:38:49.591030
7567 12:38:49.591112 Set Vref, RX VrefLevel [Byte0]: 29
7568 12:38:49.594416 [Byte1]: 29
7569 12:38:49.598890
7570 12:38:49.598971 Set Vref, RX VrefLevel [Byte0]: 30
7571 12:38:49.602120 [Byte1]: 30
7572 12:38:49.606245
7573 12:38:49.606326 Set Vref, RX VrefLevel [Byte0]: 31
7574 12:38:49.609494 [Byte1]: 31
7575 12:38:49.614192
7576 12:38:49.614277 Set Vref, RX VrefLevel [Byte0]: 32
7577 12:38:49.617773 [Byte1]: 32
7578 12:38:49.621599
7579 12:38:49.621681 Set Vref, RX VrefLevel [Byte0]: 33
7580 12:38:49.624537 [Byte1]: 33
7581 12:38:49.628824
7582 12:38:49.628906 Set Vref, RX VrefLevel [Byte0]: 34
7583 12:38:49.632752 [Byte1]: 34
7584 12:38:49.636715
7585 12:38:49.636829 Set Vref, RX VrefLevel [Byte0]: 35
7586 12:38:49.640207 [Byte1]: 35
7587 12:38:49.644373
7588 12:38:49.644465 Set Vref, RX VrefLevel [Byte0]: 36
7589 12:38:49.648226 [Byte1]: 36
7590 12:38:49.651942
7591 12:38:49.652049 Set Vref, RX VrefLevel [Byte0]: 37
7592 12:38:49.655420 [Byte1]: 37
7593 12:38:49.659796
7594 12:38:49.659877 Set Vref, RX VrefLevel [Byte0]: 38
7595 12:38:49.662950 [Byte1]: 38
7596 12:38:49.667426
7597 12:38:49.667508 Set Vref, RX VrefLevel [Byte0]: 39
7598 12:38:49.670762 [Byte1]: 39
7599 12:38:49.675602
7600 12:38:49.675684 Set Vref, RX VrefLevel [Byte0]: 40
7601 12:38:49.678246 [Byte1]: 40
7602 12:38:49.682400
7603 12:38:49.682481 Set Vref, RX VrefLevel [Byte0]: 41
7604 12:38:49.685933 [Byte1]: 41
7605 12:38:49.690027
7606 12:38:49.690109 Set Vref, RX VrefLevel [Byte0]: 42
7607 12:38:49.693254 [Byte1]: 42
7608 12:38:49.697716
7609 12:38:49.697797 Set Vref, RX VrefLevel [Byte0]: 43
7610 12:38:49.701088 [Byte1]: 43
7611 12:38:49.705462
7612 12:38:49.705544 Set Vref, RX VrefLevel [Byte0]: 44
7613 12:38:49.708751 [Byte1]: 44
7614 12:38:49.714278
7615 12:38:49.714360 Set Vref, RX VrefLevel [Byte0]: 45
7616 12:38:49.716325 [Byte1]: 45
7617 12:38:49.721060
7618 12:38:49.721141 Set Vref, RX VrefLevel [Byte0]: 46
7619 12:38:49.723586 [Byte1]: 46
7620 12:38:49.728186
7621 12:38:49.728268 Set Vref, RX VrefLevel [Byte0]: 47
7622 12:38:49.731489 [Byte1]: 47
7623 12:38:49.735791
7624 12:38:49.735873 Set Vref, RX VrefLevel [Byte0]: 48
7625 12:38:49.739119 [Byte1]: 48
7626 12:38:49.743207
7627 12:38:49.743289 Set Vref, RX VrefLevel [Byte0]: 49
7628 12:38:49.746757 [Byte1]: 49
7629 12:38:49.750950
7630 12:38:49.751032 Set Vref, RX VrefLevel [Byte0]: 50
7631 12:38:49.754256 [Byte1]: 50
7632 12:38:49.758990
7633 12:38:49.759072 Set Vref, RX VrefLevel [Byte0]: 51
7634 12:38:49.762062 [Byte1]: 51
7635 12:38:49.766006
7636 12:38:49.766087 Set Vref, RX VrefLevel [Byte0]: 52
7637 12:38:49.769731 [Byte1]: 52
7638 12:38:49.773774
7639 12:38:49.773858 Set Vref, RX VrefLevel [Byte0]: 53
7640 12:38:49.777038 [Byte1]: 53
7641 12:38:49.781224
7642 12:38:49.781304 Set Vref, RX VrefLevel [Byte0]: 54
7643 12:38:49.785008 [Byte1]: 54
7644 12:38:49.788758
7645 12:38:49.788856 Set Vref, RX VrefLevel [Byte0]: 55
7646 12:38:49.792807 [Byte1]: 55
7647 12:38:49.796641
7648 12:38:49.796781 Set Vref, RX VrefLevel [Byte0]: 56
7649 12:38:49.800089 [Byte1]: 56
7650 12:38:49.804345
7651 12:38:49.804425 Set Vref, RX VrefLevel [Byte0]: 57
7652 12:38:49.807885 [Byte1]: 57
7653 12:38:49.812778
7654 12:38:49.812858 Set Vref, RX VrefLevel [Byte0]: 58
7655 12:38:49.816316 [Byte1]: 58
7656 12:38:49.819585
7657 12:38:49.819666 Set Vref, RX VrefLevel [Byte0]: 59
7658 12:38:49.822578 [Byte1]: 59
7659 12:38:49.827238
7660 12:38:49.827318 Set Vref, RX VrefLevel [Byte0]: 60
7661 12:38:49.830540 [Byte1]: 60
7662 12:38:49.834775
7663 12:38:49.834855 Set Vref, RX VrefLevel [Byte0]: 61
7664 12:38:49.838432 [Byte1]: 61
7665 12:38:49.842175
7666 12:38:49.842255 Set Vref, RX VrefLevel [Byte0]: 62
7667 12:38:49.845667 [Byte1]: 62
7668 12:38:49.849815
7669 12:38:49.849895 Set Vref, RX VrefLevel [Byte0]: 63
7670 12:38:49.856538 [Byte1]: 63
7671 12:38:49.856646
7672 12:38:49.859517 Set Vref, RX VrefLevel [Byte0]: 64
7673 12:38:49.862568 [Byte1]: 64
7674 12:38:49.862643
7675 12:38:49.866271 Set Vref, RX VrefLevel [Byte0]: 65
7676 12:38:49.869590 [Byte1]: 65
7677 12:38:49.869665
7678 12:38:49.872744 Set Vref, RX VrefLevel [Byte0]: 66
7679 12:38:49.877659 [Byte1]: 66
7680 12:38:49.880626
7681 12:38:49.880761 Set Vref, RX VrefLevel [Byte0]: 67
7682 12:38:49.883904 [Byte1]: 67
7683 12:38:49.887979
7684 12:38:49.888058 Set Vref, RX VrefLevel [Byte0]: 68
7685 12:38:49.891525 [Byte1]: 68
7686 12:38:49.895439
7687 12:38:49.895511 Set Vref, RX VrefLevel [Byte0]: 69
7688 12:38:49.898713 [Byte1]: 69
7689 12:38:49.903455
7690 12:38:49.903544 Set Vref, RX VrefLevel [Byte0]: 70
7691 12:38:49.906617 [Byte1]: 70
7692 12:38:49.910744
7693 12:38:49.910862 Set Vref, RX VrefLevel [Byte0]: 71
7694 12:38:49.914222 [Byte1]: 71
7695 12:38:49.918926
7696 12:38:49.919007 Set Vref, RX VrefLevel [Byte0]: 72
7697 12:38:49.921982 [Byte1]: 72
7698 12:38:49.926119
7699 12:38:49.926192 Final RX Vref Byte 0 = 55 to rank0
7700 12:38:49.929327 Final RX Vref Byte 1 = 54 to rank0
7701 12:38:49.932693 Final RX Vref Byte 0 = 55 to rank1
7702 12:38:49.935725 Final RX Vref Byte 1 = 54 to rank1==
7703 12:38:49.939094 Dram Type= 6, Freq= 0, CH_0, rank 0
7704 12:38:49.945913 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7705 12:38:49.945996 ==
7706 12:38:49.946079 DQS Delay:
7707 12:38:49.946160 DQS0 = 0, DQS1 = 0
7708 12:38:49.949908 DQM Delay:
7709 12:38:49.949988 DQM0 = 126, DQM1 = 120
7710 12:38:49.952346 DQ Delay:
7711 12:38:49.956360 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7712 12:38:49.959151 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7713 12:38:49.962879 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7714 12:38:49.965743 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7715 12:38:49.965844
7716 12:38:49.965925
7717 12:38:49.966005
7718 12:38:49.969785 [DramC_TX_OE_Calibration] TA2
7719 12:38:49.972492 Original DQ_B0 (3 6) =30, OEN = 27
7720 12:38:49.976414 Original DQ_B1 (3 6) =30, OEN = 27
7721 12:38:49.979145 24, 0x0, End_B0=24 End_B1=24
7722 12:38:49.979249 25, 0x0, End_B0=25 End_B1=25
7723 12:38:49.982513 26, 0x0, End_B0=26 End_B1=26
7724 12:38:49.986068 27, 0x0, End_B0=27 End_B1=27
7725 12:38:49.988926 28, 0x0, End_B0=28 End_B1=28
7726 12:38:49.989008 29, 0x0, End_B0=29 End_B1=29
7727 12:38:49.992816 30, 0x0, End_B0=30 End_B1=30
7728 12:38:49.995874 31, 0x4141, End_B0=30 End_B1=30
7729 12:38:49.999156 Byte0 end_step=30 best_step=27
7730 12:38:50.002393 Byte1 end_step=30 best_step=27
7731 12:38:50.005761 Byte0 TX OE(2T, 0.5T) = (3, 3)
7732 12:38:50.005842 Byte1 TX OE(2T, 0.5T) = (3, 3)
7733 12:38:50.009327
7734 12:38:50.009407
7735 12:38:50.015512 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
7736 12:38:50.019046 CH0 RK0: MR19=303, MR18=1B1B
7737 12:38:50.025989 CH0_RK0: MR19=0x303, MR18=0x1B1B, DQSOSC=396, MR23=63, INC=23, DEC=15
7738 12:38:50.026072
7739 12:38:50.028853 ----->DramcWriteLeveling(PI) begin...
7740 12:38:50.028969 ==
7741 12:38:50.032320 Dram Type= 6, Freq= 0, CH_0, rank 1
7742 12:38:50.035400 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7743 12:38:50.035482 ==
7744 12:38:50.038776 Write leveling (Byte 0): 29 => 29
7745 12:38:50.042048 Write leveling (Byte 1): 25 => 25
7746 12:38:50.045383 DramcWriteLeveling(PI) end<-----
7747 12:38:50.045465
7748 12:38:50.045528 ==
7749 12:38:50.048956 Dram Type= 6, Freq= 0, CH_0, rank 1
7750 12:38:50.051753 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7751 12:38:50.051834 ==
7752 12:38:50.055452 [Gating] SW mode calibration
7753 12:38:50.062622 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7754 12:38:50.068493 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7755 12:38:50.072491 0 12 0 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
7756 12:38:50.078841 0 12 4 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
7757 12:38:50.081594 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7758 12:38:50.085056 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7759 12:38:50.088648 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7760 12:38:50.095041 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7761 12:38:50.098637 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7762 12:38:50.102193 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7763 12:38:50.108512 0 13 0 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 1)
7764 12:38:50.111557 0 13 4 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
7765 12:38:50.115662 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7766 12:38:50.121261 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7767 12:38:50.124743 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7768 12:38:50.128469 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7769 12:38:50.135090 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7770 12:38:50.138172 0 13 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7771 12:38:50.141331 0 14 0 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
7772 12:38:50.148652 0 14 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
7773 12:38:50.151120 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7774 12:38:50.154508 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7775 12:38:50.161684 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7776 12:38:50.164651 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7777 12:38:50.167523 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7778 12:38:50.174287 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7779 12:38:50.177495 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7780 12:38:50.180760 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7781 12:38:50.187791 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7782 12:38:50.191491 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7783 12:38:50.195353 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7784 12:38:50.201174 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7785 12:38:50.204399 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7786 12:38:50.208202 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7787 12:38:50.214581 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7788 12:38:50.217977 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7789 12:38:50.220731 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7790 12:38:50.227657 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7791 12:38:50.230636 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7792 12:38:50.234066 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7793 12:38:50.240646 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7794 12:38:50.244410 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7795 12:38:50.247403 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7796 12:38:50.254030 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7797 12:38:50.257229 Total UI for P1: 0, mck2ui 16
7798 12:38:50.261029 best dqsien dly found for B0: ( 1, 0, 30)
7799 12:38:50.261567 Total UI for P1: 0, mck2ui 16
7800 12:38:50.267170 best dqsien dly found for B1: ( 1, 1, 0)
7801 12:38:50.270773 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7802 12:38:50.273997 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
7803 12:38:50.274464
7804 12:38:50.277621 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7805 12:38:50.280661 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
7806 12:38:50.284669 [Gating] SW calibration Done
7807 12:38:50.285262 ==
7808 12:38:50.287224 Dram Type= 6, Freq= 0, CH_0, rank 1
7809 12:38:50.290669 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7810 12:38:50.291387 ==
7811 12:38:50.293777 RX Vref Scan: 0
7812 12:38:50.294258
7813 12:38:50.294618 RX Vref 0 -> 0, step: 1
7814 12:38:50.294954
7815 12:38:50.297444 RX Delay 0 -> 252, step: 8
7816 12:38:50.300648 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7817 12:38:50.307426 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7818 12:38:50.310357 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7819 12:38:50.313703 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7820 12:38:50.317667 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7821 12:38:50.320585 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7822 12:38:50.326763 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7823 12:38:50.330216 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7824 12:38:50.333060 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7825 12:38:50.337016 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7826 12:38:50.340179 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7827 12:38:50.346304 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7828 12:38:50.349733 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7829 12:38:50.352977 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7830 12:38:50.357023 iDelay=200, Bit 14, Center 135 (72 ~ 199) 128
7831 12:38:50.363055 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7832 12:38:50.363649 ==
7833 12:38:50.366997 Dram Type= 6, Freq= 0, CH_0, rank 1
7834 12:38:50.369926 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7835 12:38:50.370399 ==
7836 12:38:50.370763 DQS Delay:
7837 12:38:50.373015 DQS0 = 0, DQS1 = 0
7838 12:38:50.373479 DQM Delay:
7839 12:38:50.376788 DQM0 = 130, DQM1 = 124
7840 12:38:50.377254 DQ Delay:
7841 12:38:50.379609 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =123
7842 12:38:50.382894 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7843 12:38:50.386503 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7844 12:38:50.390108 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7845 12:38:50.390703
7846 12:38:50.391113
7847 12:38:50.393591 ==
7848 12:38:50.396433 Dram Type= 6, Freq= 0, CH_0, rank 1
7849 12:38:50.399944 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7850 12:38:50.400676 ==
7851 12:38:50.401155
7852 12:38:50.401506
7853 12:38:50.402884 TX Vref Scan disable
7854 12:38:50.403344 == TX Byte 0 ==
7855 12:38:50.406769 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7856 12:38:50.412495 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7857 12:38:50.413000 == TX Byte 1 ==
7858 12:38:50.416803 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7859 12:38:50.422875 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7860 12:38:50.423435 ==
7861 12:38:50.426116 Dram Type= 6, Freq= 0, CH_0, rank 1
7862 12:38:50.429610 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7863 12:38:50.430173 ==
7864 12:38:50.444125
7865 12:38:50.447683 TX Vref early break, caculate TX vref
7866 12:38:50.450276 TX Vref=16, minBit 8, minWin=22, winSum=375
7867 12:38:50.453845 TX Vref=18, minBit 1, minWin=23, winSum=382
7868 12:38:50.457285 TX Vref=20, minBit 1, minWin=23, winSum=391
7869 12:38:50.460501 TX Vref=22, minBit 1, minWin=24, winSum=396
7870 12:38:50.463686 TX Vref=24, minBit 1, minWin=23, winSum=404
7871 12:38:50.470562 TX Vref=26, minBit 9, minWin=25, winSum=410
7872 12:38:50.473721 TX Vref=28, minBit 6, minWin=25, winSum=413
7873 12:38:50.476962 TX Vref=30, minBit 4, minWin=25, winSum=412
7874 12:38:50.480431 TX Vref=32, minBit 8, minWin=23, winSum=398
7875 12:38:50.484137 TX Vref=34, minBit 8, minWin=22, winSum=394
7876 12:38:50.487268 TX Vref=36, minBit 6, minWin=23, winSum=387
7877 12:38:50.493713 [TxChooseVref] Worse bit 6, Min win 25, Win sum 413, Final Vref 28
7878 12:38:50.494269
7879 12:38:50.497649 Final TX Range 0 Vref 28
7880 12:38:50.498215
7881 12:38:50.498579 ==
7882 12:38:50.501076 Dram Type= 6, Freq= 0, CH_0, rank 1
7883 12:38:50.503873 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7884 12:38:50.504347 ==
7885 12:38:50.504738
7886 12:38:50.506678
7887 12:38:50.507172 TX Vref Scan disable
7888 12:38:50.513256 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7889 12:38:50.513809 == TX Byte 0 ==
7890 12:38:50.516877 u2DelayCellOfst[0]=10 cells (3 PI)
7891 12:38:50.520040 u2DelayCellOfst[1]=14 cells (4 PI)
7892 12:38:50.523344 u2DelayCellOfst[2]=7 cells (2 PI)
7893 12:38:50.527139 u2DelayCellOfst[3]=10 cells (3 PI)
7894 12:38:50.529941 u2DelayCellOfst[4]=7 cells (2 PI)
7895 12:38:50.532990 u2DelayCellOfst[5]=0 cells (0 PI)
7896 12:38:50.537896 u2DelayCellOfst[6]=14 cells (4 PI)
7897 12:38:50.540124 u2DelayCellOfst[7]=14 cells (4 PI)
7898 12:38:50.543070 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7899 12:38:50.546947 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7900 12:38:50.550201 == TX Byte 1 ==
7901 12:38:50.553527 u2DelayCellOfst[8]=3 cells (1 PI)
7902 12:38:50.556432 u2DelayCellOfst[9]=0 cells (0 PI)
7903 12:38:50.559553 u2DelayCellOfst[10]=10 cells (3 PI)
7904 12:38:50.563203 u2DelayCellOfst[11]=7 cells (2 PI)
7905 12:38:50.563786 u2DelayCellOfst[12]=17 cells (5 PI)
7906 12:38:50.566310 u2DelayCellOfst[13]=17 cells (5 PI)
7907 12:38:50.569596 u2DelayCellOfst[14]=21 cells (6 PI)
7908 12:38:50.573130 u2DelayCellOfst[15]=17 cells (5 PI)
7909 12:38:50.580230 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7910 12:38:50.582501 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7911 12:38:50.582966 DramC Write-DBI on
7912 12:38:50.585972 ==
7913 12:38:50.589524 Dram Type= 6, Freq= 0, CH_0, rank 1
7914 12:38:50.593003 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7915 12:38:50.593579 ==
7916 12:38:50.593957
7917 12:38:50.594298
7918 12:38:50.595966 TX Vref Scan disable
7919 12:38:50.596427 == TX Byte 0 ==
7920 12:38:50.602342 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7921 12:38:50.602807 == TX Byte 1 ==
7922 12:38:50.605550 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7923 12:38:50.609245 DramC Write-DBI off
7924 12:38:50.609707
7925 12:38:50.610068 [DATLAT]
7926 12:38:50.612305 Freq=1600, CH0 RK1
7927 12:38:50.612806
7928 12:38:50.613171 DATLAT Default: 0xe
7929 12:38:50.615492 0, 0xFFFF, sum = 0
7930 12:38:50.615887 1, 0xFFFF, sum = 0
7931 12:38:50.619118 2, 0xFFFF, sum = 0
7932 12:38:50.619688 3, 0xFFFF, sum = 0
7933 12:38:50.622626 4, 0xFFFF, sum = 0
7934 12:38:50.623202 5, 0xFFFF, sum = 0
7935 12:38:50.626228 6, 0xFFFF, sum = 0
7936 12:38:50.626803 7, 0xFFFF, sum = 0
7937 12:38:50.629614 8, 0xFFFF, sum = 0
7938 12:38:50.632861 9, 0xFFFF, sum = 0
7939 12:38:50.633441 10, 0xFFFF, sum = 0
7940 12:38:50.635635 11, 0xFFFF, sum = 0
7941 12:38:50.636105 12, 0x8BFF, sum = 0
7942 12:38:50.639291 13, 0x0, sum = 1
7943 12:38:50.639868 14, 0x0, sum = 2
7944 12:38:50.642233 15, 0x0, sum = 3
7945 12:38:50.642784 16, 0x0, sum = 4
7946 12:38:50.643156 best_step = 14
7947 12:38:50.645815
7948 12:38:50.646498 ==
7949 12:38:50.649420 Dram Type= 6, Freq= 0, CH_0, rank 1
7950 12:38:50.652212 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7951 12:38:50.652681 ==
7952 12:38:50.653106 RX Vref Scan: 0
7953 12:38:50.653448
7954 12:38:50.655782 RX Vref 0 -> 0, step: 1
7955 12:38:50.656324
7956 12:38:50.660028 RX Delay 11 -> 252, step: 4
7957 12:38:50.662027 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7958 12:38:50.669234 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
7959 12:38:50.672411 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7960 12:38:50.675585 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
7961 12:38:50.678913 iDelay=195, Bit 4, Center 132 (75 ~ 190) 116
7962 12:38:50.681979 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7963 12:38:50.685296 iDelay=195, Bit 6, Center 136 (79 ~ 194) 116
7964 12:38:50.692403 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7965 12:38:50.695739 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7966 12:38:50.698894 iDelay=195, Bit 9, Center 108 (55 ~ 162) 108
7967 12:38:50.702421 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7968 12:38:50.708331 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7969 12:38:50.712323 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7970 12:38:50.715460 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
7971 12:38:50.718804 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
7972 12:38:50.721443 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7973 12:38:50.725729 ==
7974 12:38:50.728471 Dram Type= 6, Freq= 0, CH_0, rank 1
7975 12:38:50.731791 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7976 12:38:50.732251 ==
7977 12:38:50.732613 DQS Delay:
7978 12:38:50.735090 DQS0 = 0, DQS1 = 0
7979 12:38:50.735548 DQM Delay:
7980 12:38:50.739134 DQM0 = 128, DQM1 = 120
7981 12:38:50.739722 DQ Delay:
7982 12:38:50.741909 DQ0 =124, DQ1 =130, DQ2 =126, DQ3 =122
7983 12:38:50.745212 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7984 12:38:50.748542 DQ8 =108, DQ9 =108, DQ10 =122, DQ11 =112
7985 12:38:50.751358 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
7986 12:38:50.751906
7987 12:38:50.752264
7988 12:38:50.752595
7989 12:38:50.755222 [DramC_TX_OE_Calibration] TA2
7990 12:38:50.758695 Original DQ_B0 (3 6) =30, OEN = 27
7991 12:38:50.761603 Original DQ_B1 (3 6) =30, OEN = 27
7992 12:38:50.765288 24, 0x0, End_B0=24 End_B1=24
7993 12:38:50.768217 25, 0x0, End_B0=25 End_B1=25
7994 12:38:50.768820 26, 0x0, End_B0=26 End_B1=26
7995 12:38:50.771544 27, 0x0, End_B0=27 End_B1=27
7996 12:38:50.775357 28, 0x0, End_B0=28 End_B1=28
7997 12:38:50.778141 29, 0x0, End_B0=29 End_B1=29
7998 12:38:50.781412 30, 0x0, End_B0=30 End_B1=30
7999 12:38:50.781883 31, 0x5151, End_B0=30 End_B1=30
8000 12:38:50.784814 Byte0 end_step=30 best_step=27
8001 12:38:50.787936 Byte1 end_step=30 best_step=27
8002 12:38:50.791845 Byte0 TX OE(2T, 0.5T) = (3, 3)
8003 12:38:50.794434 Byte1 TX OE(2T, 0.5T) = (3, 3)
8004 12:38:50.795001
8005 12:38:50.795365
8006 12:38:50.801553 [DQSOSCAuto] RK1, (LSB)MR18= 0x2525, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
8007 12:38:50.804115 CH0 RK1: MR19=303, MR18=2525
8008 12:38:50.812246 CH0_RK1: MR19=0x303, MR18=0x2525, DQSOSC=391, MR23=63, INC=24, DEC=16
8009 12:38:50.814452 [RxdqsGatingPostProcess] freq 1600
8010 12:38:50.820856 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8011 12:38:50.824406 Pre-setting of DQS Precalculation
8012 12:38:50.827635 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8013 12:38:50.828284 ==
8014 12:38:50.831224 Dram Type= 6, Freq= 0, CH_1, rank 0
8015 12:38:50.834062 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8016 12:38:50.834623 ==
8017 12:38:50.840854 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8018 12:38:50.844219 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8019 12:38:50.850438 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8020 12:38:50.853745 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8021 12:38:50.863250 [CA 0] Center 41 (11~71) winsize 61
8022 12:38:50.866809 [CA 1] Center 41 (10~72) winsize 63
8023 12:38:50.870002 [CA 2] Center 37 (8~67) winsize 60
8024 12:38:50.874137 [CA 3] Center 36 (7~66) winsize 60
8025 12:38:50.876215 [CA 4] Center 34 (4~64) winsize 61
8026 12:38:50.880043 [CA 5] Center 34 (5~64) winsize 60
8027 12:38:50.880503
8028 12:38:50.883398 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8029 12:38:50.883857
8030 12:38:50.887364 [CATrainingPosCal] consider 1 rank data
8031 12:38:50.890495 u2DelayCellTimex100 = 275/100 ps
8032 12:38:50.895998 CA0 delay=41 (11~71),Diff = 7 PI (24 cell)
8033 12:38:50.899266 CA1 delay=41 (10~72),Diff = 7 PI (24 cell)
8034 12:38:50.902757 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
8035 12:38:50.905994 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
8036 12:38:50.909622 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8037 12:38:50.912736 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8038 12:38:50.913204
8039 12:38:50.917149 CA PerBit enable=1, Macro0, CA PI delay=34
8040 12:38:50.917719
8041 12:38:50.919807 [CBTSetCACLKResult] CA Dly = 34
8042 12:38:50.922889 CS Dly: 8 (0~39)
8043 12:38:50.926144 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8044 12:38:50.930541 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8045 12:38:50.931098 ==
8046 12:38:50.932652 Dram Type= 6, Freq= 0, CH_1, rank 1
8047 12:38:50.939276 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8048 12:38:50.939821 ==
8049 12:38:50.942331 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8050 12:38:50.946569 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8051 12:38:50.953215 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8052 12:38:50.958956 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8053 12:38:50.965274 [CA 0] Center 40 (10~70) winsize 61
8054 12:38:50.968927 [CA 1] Center 39 (9~70) winsize 62
8055 12:38:50.972166 [CA 2] Center 35 (6~65) winsize 60
8056 12:38:50.975629 [CA 3] Center 35 (5~65) winsize 61
8057 12:38:50.978963 [CA 4] Center 32 (3~62) winsize 60
8058 12:38:50.982676 [CA 5] Center 33 (4~62) winsize 59
8059 12:38:50.983136
8060 12:38:50.985935 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8061 12:38:50.986498
8062 12:38:50.988804 [CATrainingPosCal] consider 2 rank data
8063 12:38:50.992190 u2DelayCellTimex100 = 275/100 ps
8064 12:38:50.998826 CA0 delay=40 (11~70),Diff = 7 PI (24 cell)
8065 12:38:51.002634 CA1 delay=40 (10~70),Diff = 7 PI (24 cell)
8066 12:38:51.006021 CA2 delay=36 (8~65),Diff = 3 PI (10 cell)
8067 12:38:51.008227 CA3 delay=36 (7~65),Diff = 3 PI (10 cell)
8068 12:38:51.011636 CA4 delay=33 (4~62),Diff = 0 PI (0 cell)
8069 12:38:51.014936 CA5 delay=33 (5~62),Diff = 0 PI (0 cell)
8070 12:38:51.015392
8071 12:38:51.018606 CA PerBit enable=1, Macro0, CA PI delay=33
8072 12:38:51.019160
8073 12:38:51.022050 [CBTSetCACLKResult] CA Dly = 33
8074 12:38:51.025978 CS Dly: 9 (0~41)
8075 12:38:51.028367 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8076 12:38:51.031559 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8077 12:38:51.032062
8078 12:38:51.035228 ----->DramcWriteLeveling(PI) begin...
8079 12:38:51.035692 ==
8080 12:38:51.039831 Dram Type= 6, Freq= 0, CH_1, rank 0
8081 12:38:51.045214 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8082 12:38:51.045746 ==
8083 12:38:51.049037 Write leveling (Byte 0): 22 => 22
8084 12:38:51.049560 Write leveling (Byte 1): 22 => 22
8085 12:38:51.051831 DramcWriteLeveling(PI) end<-----
8086 12:38:51.052288
8087 12:38:51.054860 ==
8088 12:38:51.055322 Dram Type= 6, Freq= 0, CH_1, rank 0
8089 12:38:51.061637 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8090 12:38:51.062166 ==
8091 12:38:51.065574 [Gating] SW mode calibration
8092 12:38:51.071615 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8093 12:38:51.075499 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8094 12:38:51.081810 0 12 0 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
8095 12:38:51.085381 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8096 12:38:51.088699 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8097 12:38:51.095622 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8098 12:38:51.098250 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8099 12:38:51.101643 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8100 12:38:51.107719 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8101 12:38:51.111128 0 12 28 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
8102 12:38:51.114912 0 13 0 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
8103 12:38:51.121479 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8104 12:38:51.124891 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8105 12:38:51.128317 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8106 12:38:51.134358 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8107 12:38:51.138357 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8108 12:38:51.141889 0 13 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8109 12:38:51.147402 0 13 28 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8110 12:38:51.151081 0 14 0 | B1->B0 | 3030 4646 | 1 0 | (0 0) (0 0)
8111 12:38:51.154004 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8112 12:38:51.160958 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8113 12:38:51.164087 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8114 12:38:51.168270 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8115 12:38:51.173885 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8116 12:38:51.177540 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8117 12:38:51.180421 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8118 12:38:51.187543 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8119 12:38:51.190894 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8120 12:38:51.194258 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8121 12:38:51.197400 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8122 12:38:51.204483 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8123 12:38:51.207181 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8124 12:38:51.213684 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8125 12:38:51.218109 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8126 12:38:51.220900 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8127 12:38:51.227551 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8128 12:38:51.230292 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8129 12:38:51.233641 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8130 12:38:51.237109 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8131 12:38:51.243412 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8132 12:38:51.247043 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8133 12:38:51.253340 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8134 12:38:51.257290 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8135 12:38:51.260119 Total UI for P1: 0, mck2ui 16
8136 12:38:51.263538 best dqsien dly found for B0: ( 1, 0, 26)
8137 12:38:51.267332 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8138 12:38:51.269490 Total UI for P1: 0, mck2ui 16
8139 12:38:51.273173 best dqsien dly found for B1: ( 1, 1, 0)
8140 12:38:51.276519 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8141 12:38:51.279689 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8142 12:38:51.280278
8143 12:38:51.282756 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8144 12:38:51.287253 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8145 12:38:51.289923 [Gating] SW calibration Done
8146 12:38:51.290469 ==
8147 12:38:51.293508 Dram Type= 6, Freq= 0, CH_1, rank 0
8148 12:38:51.302627 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8149 12:38:51.303189 ==
8150 12:38:51.303555 RX Vref Scan: 0
8151 12:38:51.303893
8152 12:38:51.304572 RX Vref 0 -> 0, step: 1
8153 12:38:51.304992
8154 12:38:51.306032 RX Delay 0 -> 252, step: 8
8155 12:38:51.309785 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8156 12:38:51.312779 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8157 12:38:51.316278 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8158 12:38:51.319979 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8159 12:38:51.326189 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8160 12:38:51.329543 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8161 12:38:51.333304 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8162 12:38:51.336584 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8163 12:38:51.339680 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8164 12:38:51.346627 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8165 12:38:51.349635 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8166 12:38:51.352686 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8167 12:38:51.357669 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8168 12:38:51.362281 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8169 12:38:51.365800 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8170 12:38:51.369430 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8171 12:38:51.369989 ==
8172 12:38:51.372619 Dram Type= 6, Freq= 0, CH_1, rank 0
8173 12:38:51.375686 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8174 12:38:51.376237 ==
8175 12:38:51.379157 DQS Delay:
8176 12:38:51.379712 DQS0 = 0, DQS1 = 0
8177 12:38:51.382492 DQM Delay:
8178 12:38:51.382971 DQM0 = 130, DQM1 = 126
8179 12:38:51.385666 DQ Delay:
8180 12:38:51.388508 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =127
8181 12:38:51.392115 DQ4 =131, DQ5 =139, DQ6 =135, DQ7 =127
8182 12:38:51.395811 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8183 12:38:51.399059 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8184 12:38:51.399628
8185 12:38:51.399997
8186 12:38:51.400329 ==
8187 12:38:51.402505 Dram Type= 6, Freq= 0, CH_1, rank 0
8188 12:38:51.405269 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8189 12:38:51.405730 ==
8190 12:38:51.406092
8191 12:38:51.406422
8192 12:38:51.408670 TX Vref Scan disable
8193 12:38:51.413918 == TX Byte 0 ==
8194 12:38:51.415524 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8195 12:38:51.418883 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8196 12:38:51.421815 == TX Byte 1 ==
8197 12:38:51.425160 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8198 12:38:51.428385 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8199 12:38:51.429020 ==
8200 12:38:51.431807 Dram Type= 6, Freq= 0, CH_1, rank 0
8201 12:38:51.439176 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8202 12:38:51.439733 ==
8203 12:38:51.449401
8204 12:38:51.452987 TX Vref early break, caculate TX vref
8205 12:38:51.456303 TX Vref=16, minBit 0, minWin=21, winSum=366
8206 12:38:51.459525 TX Vref=18, minBit 3, minWin=21, winSum=372
8207 12:38:51.463177 TX Vref=20, minBit 0, minWin=23, winSum=381
8208 12:38:51.465827 TX Vref=22, minBit 3, minWin=23, winSum=395
8209 12:38:51.469310 TX Vref=24, minBit 0, minWin=24, winSum=401
8210 12:38:51.476368 TX Vref=26, minBit 3, minWin=24, winSum=408
8211 12:38:51.479031 TX Vref=28, minBit 3, minWin=24, winSum=414
8212 12:38:51.483050 TX Vref=30, minBit 0, minWin=24, winSum=403
8213 12:38:51.485796 TX Vref=32, minBit 1, minWin=23, winSum=394
8214 12:38:51.489038 TX Vref=34, minBit 1, minWin=23, winSum=385
8215 12:38:51.495872 [TxChooseVref] Worse bit 3, Min win 24, Win sum 414, Final Vref 28
8216 12:38:51.496448
8217 12:38:51.499669 Final TX Range 0 Vref 28
8218 12:38:51.500231
8219 12:38:51.500586 ==
8220 12:38:51.502686 Dram Type= 6, Freq= 0, CH_1, rank 0
8221 12:38:51.505281 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8222 12:38:51.505764 ==
8223 12:38:51.506129
8224 12:38:51.506461
8225 12:38:51.509229 TX Vref Scan disable
8226 12:38:51.515767 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8227 12:38:51.516353 == TX Byte 0 ==
8228 12:38:51.518496 u2DelayCellOfst[0]=17 cells (5 PI)
8229 12:38:51.522417 u2DelayCellOfst[1]=14 cells (4 PI)
8230 12:38:51.525502 u2DelayCellOfst[2]=0 cells (0 PI)
8231 12:38:51.528890 u2DelayCellOfst[3]=7 cells (2 PI)
8232 12:38:51.532228 u2DelayCellOfst[4]=10 cells (3 PI)
8233 12:38:51.535772 u2DelayCellOfst[5]=17 cells (5 PI)
8234 12:38:51.538837 u2DelayCellOfst[6]=17 cells (5 PI)
8235 12:38:51.542240 u2DelayCellOfst[7]=10 cells (3 PI)
8236 12:38:51.545687 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8237 12:38:51.548482 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8238 12:38:51.552149 == TX Byte 1 ==
8239 12:38:51.554778 u2DelayCellOfst[8]=0 cells (0 PI)
8240 12:38:51.555234 u2DelayCellOfst[9]=3 cells (1 PI)
8241 12:38:51.559382 u2DelayCellOfst[10]=10 cells (3 PI)
8242 12:38:51.561478 u2DelayCellOfst[11]=3 cells (1 PI)
8243 12:38:51.565174 u2DelayCellOfst[12]=17 cells (5 PI)
8244 12:38:51.568887 u2DelayCellOfst[13]=21 cells (6 PI)
8245 12:38:51.572071 u2DelayCellOfst[14]=21 cells (6 PI)
8246 12:38:51.575207 u2DelayCellOfst[15]=21 cells (6 PI)
8247 12:38:51.578484 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8248 12:38:51.585028 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8249 12:38:51.585485 DramC Write-DBI on
8250 12:38:51.585840 ==
8251 12:38:51.588303 Dram Type= 6, Freq= 0, CH_1, rank 0
8252 12:38:51.594996 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8253 12:38:51.595554 ==
8254 12:38:51.595915
8255 12:38:51.596248
8256 12:38:51.596565 TX Vref Scan disable
8257 12:38:51.598811 == TX Byte 0 ==
8258 12:38:51.602078 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8259 12:38:51.605419 == TX Byte 1 ==
8260 12:38:51.608364 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8261 12:38:51.611899 DramC Write-DBI off
8262 12:38:51.612367
8263 12:38:51.612778 [DATLAT]
8264 12:38:51.613141 Freq=1600, CH1 RK0
8265 12:38:51.613468
8266 12:38:51.614986 DATLAT Default: 0xf
8267 12:38:51.615451 0, 0xFFFF, sum = 0
8268 12:38:51.618340 1, 0xFFFF, sum = 0
8269 12:38:51.621686 2, 0xFFFF, sum = 0
8270 12:38:51.622152 3, 0xFFFF, sum = 0
8271 12:38:51.624967 4, 0xFFFF, sum = 0
8272 12:38:51.625463 5, 0xFFFF, sum = 0
8273 12:38:51.628820 6, 0xFFFF, sum = 0
8274 12:38:51.629355 7, 0xFFFF, sum = 0
8275 12:38:51.632240 8, 0xFFFF, sum = 0
8276 12:38:51.632812 9, 0xFFFF, sum = 0
8277 12:38:51.635094 10, 0xFFFF, sum = 0
8278 12:38:51.635633 11, 0xFFFF, sum = 0
8279 12:38:51.638098 12, 0x8F7F, sum = 0
8280 12:38:51.638563 13, 0x0, sum = 1
8281 12:38:51.641593 14, 0x0, sum = 2
8282 12:38:51.642155 15, 0x0, sum = 3
8283 12:38:51.644828 16, 0x0, sum = 4
8284 12:38:51.645373 best_step = 14
8285 12:38:51.645739
8286 12:38:51.646074 ==
8287 12:38:51.648286 Dram Type= 6, Freq= 0, CH_1, rank 0
8288 12:38:51.651962 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8289 12:38:51.655068 ==
8290 12:38:51.655543 RX Vref Scan: 1
8291 12:38:51.655904
8292 12:38:51.658277 Set Vref Range= 24 -> 127
8293 12:38:51.658846
8294 12:38:51.661631 RX Vref 24 -> 127, step: 1
8295 12:38:51.662090
8296 12:38:51.662450 RX Delay 3 -> 252, step: 4
8297 12:38:51.662787
8298 12:38:51.665436 Set Vref, RX VrefLevel [Byte0]: 24
8299 12:38:51.667905 [Byte1]: 24
8300 12:38:51.671593
8301 12:38:51.672052 Set Vref, RX VrefLevel [Byte0]: 25
8302 12:38:51.675265 [Byte1]: 25
8303 12:38:51.679667
8304 12:38:51.680191 Set Vref, RX VrefLevel [Byte0]: 26
8305 12:38:51.683307 [Byte1]: 26
8306 12:38:51.689070
8307 12:38:51.689677 Set Vref, RX VrefLevel [Byte0]: 27
8308 12:38:51.690987 [Byte1]: 27
8309 12:38:51.694969
8310 12:38:51.695520 Set Vref, RX VrefLevel [Byte0]: 28
8311 12:38:51.698403 [Byte1]: 28
8312 12:38:51.702631
8313 12:38:51.703091 Set Vref, RX VrefLevel [Byte0]: 29
8314 12:38:51.705778 [Byte1]: 29
8315 12:38:51.709950
8316 12:38:51.710408 Set Vref, RX VrefLevel [Byte0]: 30
8317 12:38:51.713617 [Byte1]: 30
8318 12:38:51.718425
8319 12:38:51.718970 Set Vref, RX VrefLevel [Byte0]: 31
8320 12:38:51.721591 [Byte1]: 31
8321 12:38:51.725718
8322 12:38:51.726176 Set Vref, RX VrefLevel [Byte0]: 32
8323 12:38:51.728823 [Byte1]: 32
8324 12:38:51.733470
8325 12:38:51.734021 Set Vref, RX VrefLevel [Byte0]: 33
8326 12:38:51.736779 [Byte1]: 33
8327 12:38:51.740657
8328 12:38:51.741225 Set Vref, RX VrefLevel [Byte0]: 34
8329 12:38:51.744636 [Byte1]: 34
8330 12:38:51.749037
8331 12:38:51.749494 Set Vref, RX VrefLevel [Byte0]: 35
8332 12:38:51.751905 [Byte1]: 35
8333 12:38:51.755681
8334 12:38:51.756137 Set Vref, RX VrefLevel [Byte0]: 36
8335 12:38:51.759202 [Byte1]: 36
8336 12:38:51.763450
8337 12:38:51.763960 Set Vref, RX VrefLevel [Byte0]: 37
8338 12:38:51.766937 [Byte1]: 37
8339 12:38:51.771405
8340 12:38:51.771764 Set Vref, RX VrefLevel [Byte0]: 38
8341 12:38:51.774656 [Byte1]: 38
8342 12:38:51.778996
8343 12:38:51.779314 Set Vref, RX VrefLevel [Byte0]: 39
8344 12:38:51.782369 [Byte1]: 39
8345 12:38:51.786792
8346 12:38:51.787110 Set Vref, RX VrefLevel [Byte0]: 40
8347 12:38:51.789522 [Byte1]: 40
8348 12:38:51.794584
8349 12:38:51.795102 Set Vref, RX VrefLevel [Byte0]: 41
8350 12:38:51.797349 [Byte1]: 41
8351 12:38:51.802217
8352 12:38:51.802630 Set Vref, RX VrefLevel [Byte0]: 42
8353 12:38:51.805384 [Byte1]: 42
8354 12:38:51.809433
8355 12:38:51.809845 Set Vref, RX VrefLevel [Byte0]: 43
8356 12:38:51.812463 [Byte1]: 43
8357 12:38:51.817145
8358 12:38:51.817590 Set Vref, RX VrefLevel [Byte0]: 44
8359 12:38:51.820205 [Byte1]: 44
8360 12:38:51.825038
8361 12:38:51.825493 Set Vref, RX VrefLevel [Byte0]: 45
8362 12:38:51.828629 [Byte1]: 45
8363 12:38:51.833237
8364 12:38:51.833828 Set Vref, RX VrefLevel [Byte0]: 46
8365 12:38:51.836411 [Byte1]: 46
8366 12:38:51.840417
8367 12:38:51.841008 Set Vref, RX VrefLevel [Byte0]: 47
8368 12:38:51.843685 [Byte1]: 47
8369 12:38:51.848524
8370 12:38:51.849056 Set Vref, RX VrefLevel [Byte0]: 48
8371 12:38:51.851180 [Byte1]: 48
8372 12:38:51.856118
8373 12:38:51.856577 Set Vref, RX VrefLevel [Byte0]: 49
8374 12:38:51.858913 [Byte1]: 49
8375 12:38:51.863561
8376 12:38:51.864112 Set Vref, RX VrefLevel [Byte0]: 50
8377 12:38:51.866257 [Byte1]: 50
8378 12:38:51.870724
8379 12:38:51.871292 Set Vref, RX VrefLevel [Byte0]: 51
8380 12:38:51.874354 [Byte1]: 51
8381 12:38:51.878433
8382 12:38:51.878892 Set Vref, RX VrefLevel [Byte0]: 52
8383 12:38:51.881758 [Byte1]: 52
8384 12:38:51.886732
8385 12:38:51.887205 Set Vref, RX VrefLevel [Byte0]: 53
8386 12:38:51.889664 [Byte1]: 53
8387 12:38:51.893947
8388 12:38:51.894558 Set Vref, RX VrefLevel [Byte0]: 54
8389 12:38:51.897235 [Byte1]: 54
8390 12:38:51.901944
8391 12:38:51.902396 Set Vref, RX VrefLevel [Byte0]: 55
8392 12:38:51.904888 [Byte1]: 55
8393 12:38:51.909190
8394 12:38:51.909714 Set Vref, RX VrefLevel [Byte0]: 56
8395 12:38:51.912539 [Byte1]: 56
8396 12:38:51.916627
8397 12:38:51.917118 Set Vref, RX VrefLevel [Byte0]: 57
8398 12:38:51.920336 [Byte1]: 57
8399 12:38:51.924837
8400 12:38:51.925357 Set Vref, RX VrefLevel [Byte0]: 58
8401 12:38:51.927578 [Byte1]: 58
8402 12:38:51.932179
8403 12:38:51.932639 Set Vref, RX VrefLevel [Byte0]: 59
8404 12:38:51.935384 [Byte1]: 59
8405 12:38:51.940087
8406 12:38:51.940640 Set Vref, RX VrefLevel [Byte0]: 60
8407 12:38:51.943920 [Byte1]: 60
8408 12:38:51.947430
8409 12:38:51.947956 Set Vref, RX VrefLevel [Byte0]: 61
8410 12:38:51.950500 [Byte1]: 61
8411 12:38:51.955536
8412 12:38:51.956214 Set Vref, RX VrefLevel [Byte0]: 62
8413 12:38:51.958138 [Byte1]: 62
8414 12:38:51.962832
8415 12:38:51.963292 Set Vref, RX VrefLevel [Byte0]: 63
8416 12:38:51.965785 [Byte1]: 63
8417 12:38:51.970412
8418 12:38:51.970875 Set Vref, RX VrefLevel [Byte0]: 64
8419 12:38:51.973711 [Byte1]: 64
8420 12:38:51.978042
8421 12:38:51.978590 Set Vref, RX VrefLevel [Byte0]: 65
8422 12:38:51.981233 [Byte1]: 65
8423 12:38:51.985908
8424 12:38:51.986366 Set Vref, RX VrefLevel [Byte0]: 66
8425 12:38:51.988928 [Byte1]: 66
8426 12:38:51.993218
8427 12:38:51.993678 Set Vref, RX VrefLevel [Byte0]: 67
8428 12:38:51.996804 [Byte1]: 67
8429 12:38:52.001458
8430 12:38:52.002011 Set Vref, RX VrefLevel [Byte0]: 68
8431 12:38:52.004536 [Byte1]: 68
8432 12:38:52.008935
8433 12:38:52.009493 Set Vref, RX VrefLevel [Byte0]: 69
8434 12:38:52.012891 [Byte1]: 69
8435 12:38:52.016657
8436 12:38:52.017242 Set Vref, RX VrefLevel [Byte0]: 70
8437 12:38:52.019840 [Byte1]: 70
8438 12:38:52.023494
8439 12:38:52.024077 Set Vref, RX VrefLevel [Byte0]: 71
8440 12:38:52.026961 [Byte1]: 71
8441 12:38:52.031842
8442 12:38:52.032402 Set Vref, RX VrefLevel [Byte0]: 72
8443 12:38:52.034739 [Byte1]: 72
8444 12:38:52.039293
8445 12:38:52.039855 Set Vref, RX VrefLevel [Byte0]: 73
8446 12:38:52.042518 [Byte1]: 73
8447 12:38:52.047217
8448 12:38:52.047781 Set Vref, RX VrefLevel [Byte0]: 74
8449 12:38:52.051018 [Byte1]: 74
8450 12:38:52.054227
8451 12:38:52.054933 Set Vref, RX VrefLevel [Byte0]: 75
8452 12:38:52.057853 [Byte1]: 75
8453 12:38:52.062105
8454 12:38:52.062663 Set Vref, RX VrefLevel [Byte0]: 76
8455 12:38:52.068567 [Byte1]: 76
8456 12:38:52.069087
8457 12:38:52.071643 Final RX Vref Byte 0 = 61 to rank0
8458 12:38:52.075284 Final RX Vref Byte 1 = 55 to rank0
8459 12:38:52.078969 Final RX Vref Byte 0 = 61 to rank1
8460 12:38:52.081627 Final RX Vref Byte 1 = 55 to rank1==
8461 12:38:52.084937 Dram Type= 6, Freq= 0, CH_1, rank 0
8462 12:38:52.088532 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8463 12:38:52.089091 ==
8464 12:38:52.089456 DQS Delay:
8465 12:38:52.091658 DQS0 = 0, DQS1 = 0
8466 12:38:52.092112 DQM Delay:
8467 12:38:52.095165 DQM0 = 128, DQM1 = 124
8468 12:38:52.095609 DQ Delay:
8469 12:38:52.097912 DQ0 =132, DQ1 =122, DQ2 =116, DQ3 =126
8470 12:38:52.101296 DQ4 =130, DQ5 =138, DQ6 =138, DQ7 =126
8471 12:38:52.105108 DQ8 =106, DQ9 =114, DQ10 =128, DQ11 =114
8472 12:38:52.108520 DQ12 =132, DQ13 =134, DQ14 =134, DQ15 =134
8473 12:38:52.111468
8474 12:38:52.111924
8475 12:38:52.112282
8476 12:38:52.112611 [DramC_TX_OE_Calibration] TA2
8477 12:38:52.114914 Original DQ_B0 (3 6) =30, OEN = 27
8478 12:38:52.117833 Original DQ_B1 (3 6) =30, OEN = 27
8479 12:38:52.121133 24, 0x0, End_B0=24 End_B1=24
8480 12:38:52.125359 25, 0x0, End_B0=25 End_B1=25
8481 12:38:52.127964 26, 0x0, End_B0=26 End_B1=26
8482 12:38:52.128629 27, 0x0, End_B0=27 End_B1=27
8483 12:38:52.131219 28, 0x0, End_B0=28 End_B1=28
8484 12:38:52.134501 29, 0x0, End_B0=29 End_B1=29
8485 12:38:52.137622 30, 0x0, End_B0=30 End_B1=30
8486 12:38:52.141088 31, 0x4141, End_B0=30 End_B1=30
8487 12:38:52.144153 Byte0 end_step=30 best_step=27
8488 12:38:52.144616 Byte1 end_step=30 best_step=27
8489 12:38:52.147477 Byte0 TX OE(2T, 0.5T) = (3, 3)
8490 12:38:52.150915 Byte1 TX OE(2T, 0.5T) = (3, 3)
8491 12:38:52.151376
8492 12:38:52.151735
8493 12:38:52.160744 [DQSOSCAuto] RK0, (LSB)MR18= 0x2525, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
8494 12:38:52.161248 CH1 RK0: MR19=303, MR18=2525
8495 12:38:52.167189 CH1_RK0: MR19=0x303, MR18=0x2525, DQSOSC=391, MR23=63, INC=24, DEC=16
8496 12:38:52.167720
8497 12:38:52.171335 ----->DramcWriteLeveling(PI) begin...
8498 12:38:52.171807 ==
8499 12:38:52.175313 Dram Type= 6, Freq= 0, CH_1, rank 1
8500 12:38:52.180619 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8501 12:38:52.181141 ==
8502 12:38:52.184234 Write leveling (Byte 0): 22 => 22
8503 12:38:52.187203 Write leveling (Byte 1): 20 => 20
8504 12:38:52.187661 DramcWriteLeveling(PI) end<-----
8505 12:38:52.190694
8506 12:38:52.191149 ==
8507 12:38:52.193810 Dram Type= 6, Freq= 0, CH_1, rank 1
8508 12:38:52.197579 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8509 12:38:52.198147 ==
8510 12:38:52.200528 [Gating] SW mode calibration
8511 12:38:52.207205 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8512 12:38:52.210800 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8513 12:38:52.217400 0 12 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8514 12:38:52.220483 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8515 12:38:52.223773 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8516 12:38:52.230304 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8517 12:38:52.233645 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8518 12:38:52.236920 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8519 12:38:52.243949 0 12 24 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
8520 12:38:52.246754 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8521 12:38:52.250216 0 13 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8522 12:38:52.256682 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8523 12:38:52.260293 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8524 12:38:52.263073 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8525 12:38:52.269746 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8526 12:38:52.273116 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8527 12:38:52.276385 0 13 24 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8528 12:38:52.283229 0 13 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
8529 12:38:52.287441 0 14 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8530 12:38:52.289736 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8531 12:38:52.296683 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8532 12:38:52.299813 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8533 12:38:52.303137 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8534 12:38:52.310529 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8535 12:38:52.312962 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8536 12:38:52.316672 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8537 12:38:52.322930 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8538 12:38:52.326005 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8539 12:38:52.328977 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8540 12:38:52.336023 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8541 12:38:52.339093 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8542 12:38:52.342148 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8543 12:38:52.349154 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8544 12:38:52.352484 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8545 12:38:52.356201 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8546 12:38:52.362618 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8547 12:38:52.365735 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8548 12:38:52.368868 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8549 12:38:52.375605 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8550 12:38:52.379371 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8551 12:38:52.381763 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8552 12:38:52.388358 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8553 12:38:52.388543 Total UI for P1: 0, mck2ui 16
8554 12:38:52.396019 best dqsien dly found for B0: ( 1, 0, 22)
8555 12:38:52.399387 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8556 12:38:52.402691 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8557 12:38:52.406046 Total UI for P1: 0, mck2ui 16
8558 12:38:52.408847 best dqsien dly found for B1: ( 1, 0, 30)
8559 12:38:52.411876 best DQS0 dly(MCK, UI, PI) = (1, 0, 22)
8560 12:38:52.415096 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8561 12:38:52.415227
8562 12:38:52.418283 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 22)
8563 12:38:52.424978 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8564 12:38:52.425144 [Gating] SW calibration Done
8565 12:38:52.428555 ==
8566 12:38:52.428768 Dram Type= 6, Freq= 0, CH_1, rank 1
8567 12:38:52.435198 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8568 12:38:52.435513 ==
8569 12:38:52.435702 RX Vref Scan: 0
8570 12:38:52.435874
8571 12:38:52.438822 RX Vref 0 -> 0, step: 1
8572 12:38:52.439101
8573 12:38:52.441874 RX Delay 0 -> 252, step: 8
8574 12:38:52.445316 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8575 12:38:52.449046 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8576 12:38:52.452332 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8577 12:38:52.458817 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8578 12:38:52.462163 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8579 12:38:52.464857 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8580 12:38:52.468467 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8581 12:38:52.471994 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8582 12:38:52.478180 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8583 12:38:52.481399 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8584 12:38:52.484926 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8585 12:38:52.488664 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8586 12:38:52.492662 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8587 12:38:52.497993 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8588 12:38:52.501686 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8589 12:38:52.505104 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8590 12:38:52.505561 ==
8591 12:38:52.508135 Dram Type= 6, Freq= 0, CH_1, rank 1
8592 12:38:52.511752 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8593 12:38:52.515145 ==
8594 12:38:52.515627 DQS Delay:
8595 12:38:52.516049 DQS0 = 0, DQS1 = 0
8596 12:38:52.518258 DQM Delay:
8597 12:38:52.518719 DQM0 = 132, DQM1 = 125
8598 12:38:52.521281 DQ Delay:
8599 12:38:52.525199 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8600 12:38:52.528211 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8601 12:38:52.530940 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8602 12:38:52.535321 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =131
8603 12:38:52.535893
8604 12:38:52.536259
8605 12:38:52.536598 ==
8606 12:38:52.537515 Dram Type= 6, Freq= 0, CH_1, rank 1
8607 12:38:52.541288 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8608 12:38:52.541814 ==
8609 12:38:52.542178
8610 12:38:52.544927
8611 12:38:52.545381 TX Vref Scan disable
8612 12:38:52.547872 == TX Byte 0 ==
8613 12:38:52.551529 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8614 12:38:52.555026 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8615 12:38:52.557697 == TX Byte 1 ==
8616 12:38:52.561241 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8617 12:38:52.564887 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8618 12:38:52.565347 ==
8619 12:38:52.567376 Dram Type= 6, Freq= 0, CH_1, rank 1
8620 12:38:52.574327 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8621 12:38:52.574854 ==
8622 12:38:52.586729
8623 12:38:52.590257 TX Vref early break, caculate TX vref
8624 12:38:52.593201 TX Vref=16, minBit 0, minWin=23, winSum=380
8625 12:38:52.596514 TX Vref=18, minBit 0, minWin=22, winSum=387
8626 12:38:52.600094 TX Vref=20, minBit 0, minWin=23, winSum=397
8627 12:38:52.602978 TX Vref=22, minBit 0, minWin=24, winSum=404
8628 12:38:52.606407 TX Vref=24, minBit 0, minWin=25, winSum=413
8629 12:38:52.613774 TX Vref=26, minBit 0, minWin=25, winSum=416
8630 12:38:52.616476 TX Vref=28, minBit 0, minWin=25, winSum=421
8631 12:38:52.619934 TX Vref=30, minBit 0, minWin=24, winSum=418
8632 12:38:52.623254 TX Vref=32, minBit 1, minWin=24, winSum=413
8633 12:38:52.626274 TX Vref=34, minBit 0, minWin=22, winSum=401
8634 12:38:52.629735 TX Vref=36, minBit 0, minWin=23, winSum=392
8635 12:38:52.637045 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 28
8636 12:38:52.637463
8637 12:38:52.639632 Final TX Range 0 Vref 28
8638 12:38:52.640052
8639 12:38:52.640377 ==
8640 12:38:52.643233 Dram Type= 6, Freq= 0, CH_1, rank 1
8641 12:38:52.647260 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8642 12:38:52.647686 ==
8643 12:38:52.648015
8644 12:38:52.649695
8645 12:38:52.650115 TX Vref Scan disable
8646 12:38:52.656097 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8647 12:38:52.656525 == TX Byte 0 ==
8648 12:38:52.659907 u2DelayCellOfst[0]=17 cells (5 PI)
8649 12:38:52.662697 u2DelayCellOfst[1]=10 cells (3 PI)
8650 12:38:52.666434 u2DelayCellOfst[2]=0 cells (0 PI)
8651 12:38:52.669468 u2DelayCellOfst[3]=10 cells (3 PI)
8652 12:38:52.672609 u2DelayCellOfst[4]=10 cells (3 PI)
8653 12:38:52.676631 u2DelayCellOfst[5]=17 cells (5 PI)
8654 12:38:52.679617 u2DelayCellOfst[6]=14 cells (4 PI)
8655 12:38:52.683127 u2DelayCellOfst[7]=7 cells (2 PI)
8656 12:38:52.686236 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8657 12:38:52.689887 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8658 12:38:52.692809 == TX Byte 1 ==
8659 12:38:52.696678 u2DelayCellOfst[8]=0 cells (0 PI)
8660 12:38:52.699517 u2DelayCellOfst[9]=3 cells (1 PI)
8661 12:38:52.700040 u2DelayCellOfst[10]=7 cells (2 PI)
8662 12:38:52.702809 u2DelayCellOfst[11]=3 cells (1 PI)
8663 12:38:52.706318 u2DelayCellOfst[12]=14 cells (4 PI)
8664 12:38:52.709546 u2DelayCellOfst[13]=17 cells (5 PI)
8665 12:38:52.712411 u2DelayCellOfst[14]=17 cells (5 PI)
8666 12:38:52.716006 u2DelayCellOfst[15]=17 cells (5 PI)
8667 12:38:52.722397 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8668 12:38:52.725827 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8669 12:38:52.726432 DramC Write-DBI on
8670 12:38:52.726805 ==
8671 12:38:52.729268 Dram Type= 6, Freq= 0, CH_1, rank 1
8672 12:38:52.736008 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8673 12:38:52.736639 ==
8674 12:38:52.737044
8675 12:38:52.737386
8676 12:38:52.737707 TX Vref Scan disable
8677 12:38:52.740425 == TX Byte 0 ==
8678 12:38:52.743499 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8679 12:38:52.747175 == TX Byte 1 ==
8680 12:38:52.749560 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8681 12:38:52.753526 DramC Write-DBI off
8682 12:38:52.754061
8683 12:38:52.754428 [DATLAT]
8684 12:38:52.754791 Freq=1600, CH1 RK1
8685 12:38:52.755278
8686 12:38:52.756848 DATLAT Default: 0xe
8687 12:38:52.757322 0, 0xFFFF, sum = 0
8688 12:38:52.759603 1, 0xFFFF, sum = 0
8689 12:38:52.763056 2, 0xFFFF, sum = 0
8690 12:38:52.763623 3, 0xFFFF, sum = 0
8691 12:38:52.766566 4, 0xFFFF, sum = 0
8692 12:38:52.767070 5, 0xFFFF, sum = 0
8693 12:38:52.769886 6, 0xFFFF, sum = 0
8694 12:38:52.770358 7, 0xFFFF, sum = 0
8695 12:38:52.773205 8, 0xFFFF, sum = 0
8696 12:38:52.773700 9, 0xFFFF, sum = 0
8697 12:38:52.776617 10, 0xFFFF, sum = 0
8698 12:38:52.777149 11, 0xFFFF, sum = 0
8699 12:38:52.779997 12, 0x8F7F, sum = 0
8700 12:38:52.780471 13, 0x0, sum = 1
8701 12:38:52.783217 14, 0x0, sum = 2
8702 12:38:52.783805 15, 0x0, sum = 3
8703 12:38:52.785964 16, 0x0, sum = 4
8704 12:38:52.786436 best_step = 14
8705 12:38:52.786802
8706 12:38:52.787141 ==
8707 12:38:52.790268 Dram Type= 6, Freq= 0, CH_1, rank 1
8708 12:38:52.792646 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8709 12:38:52.796047 ==
8710 12:38:52.796485 RX Vref Scan: 0
8711 12:38:52.796949
8712 12:38:52.799730 RX Vref 0 -> 0, step: 1
8713 12:38:52.800236
8714 12:38:52.800575 RX Delay 3 -> 252, step: 4
8715 12:38:52.806839 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8716 12:38:52.810373 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8717 12:38:52.813623 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8718 12:38:52.817267 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8719 12:38:52.823484 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8720 12:38:52.826868 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8721 12:38:52.830104 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8722 12:38:52.833374 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8723 12:38:52.836615 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8724 12:38:52.843018 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8725 12:38:52.846562 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8726 12:38:52.850500 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8727 12:38:52.853496 iDelay=195, Bit 12, Center 130 (71 ~ 190) 120
8728 12:38:52.856255 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8729 12:38:52.863554 iDelay=195, Bit 14, Center 134 (75 ~ 194) 120
8730 12:38:52.866361 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8731 12:38:52.866863 ==
8732 12:38:52.869766 Dram Type= 6, Freq= 0, CH_1, rank 1
8733 12:38:52.872971 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8734 12:38:52.873465 ==
8735 12:38:52.876205 DQS Delay:
8736 12:38:52.876680 DQS0 = 0, DQS1 = 0
8737 12:38:52.877110 DQM Delay:
8738 12:38:52.879859 DQM0 = 127, DQM1 = 122
8739 12:38:52.880361 DQ Delay:
8740 12:38:52.883431 DQ0 =128, DQ1 =124, DQ2 =118, DQ3 =124
8741 12:38:52.886452 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8742 12:38:52.889947 DQ8 =106, DQ9 =110, DQ10 =124, DQ11 =114
8743 12:38:52.896153 DQ12 =130, DQ13 =132, DQ14 =134, DQ15 =132
8744 12:38:52.896576
8745 12:38:52.896964
8746 12:38:52.897280
8747 12:38:52.899240 [DramC_TX_OE_Calibration] TA2
8748 12:38:52.903158 Original DQ_B0 (3 6) =30, OEN = 27
8749 12:38:52.903674 Original DQ_B1 (3 6) =30, OEN = 27
8750 12:38:52.906710 24, 0x0, End_B0=24 End_B1=24
8751 12:38:52.910036 25, 0x0, End_B0=25 End_B1=25
8752 12:38:52.912554 26, 0x0, End_B0=26 End_B1=26
8753 12:38:52.916211 27, 0x0, End_B0=27 End_B1=27
8754 12:38:52.916794 28, 0x0, End_B0=28 End_B1=28
8755 12:38:52.919451 29, 0x0, End_B0=29 End_B1=29
8756 12:38:52.922796 30, 0x0, End_B0=30 End_B1=30
8757 12:38:52.926070 31, 0x4141, End_B0=30 End_B1=30
8758 12:38:52.929648 Byte0 end_step=30 best_step=27
8759 12:38:52.930151 Byte1 end_step=30 best_step=27
8760 12:38:52.932586 Byte0 TX OE(2T, 0.5T) = (3, 3)
8761 12:38:52.936370 Byte1 TX OE(2T, 0.5T) = (3, 3)
8762 12:38:52.936833
8763 12:38:52.937169
8764 12:38:52.946008 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
8765 12:38:52.946429 CH1 RK1: MR19=303, MR18=1F1F
8766 12:38:52.952907 CH1_RK1: MR19=0x303, MR18=0x1F1F, DQSOSC=394, MR23=63, INC=23, DEC=15
8767 12:38:52.955822 [RxdqsGatingPostProcess] freq 1600
8768 12:38:52.962415 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8769 12:38:52.965657 Pre-setting of DQS Precalculation
8770 12:38:52.968914 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8771 12:38:52.979497 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8772 12:38:52.985852 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8773 12:38:52.986280
8774 12:38:52.986740
8775 12:38:52.989074 [Calibration Summary] 3200 Mbps
8776 12:38:52.989492 CH 0, Rank 0
8777 12:38:52.992326 SW Impedance : PASS
8778 12:38:52.992832 DUTY Scan : NO K
8779 12:38:52.995941 ZQ Calibration : PASS
8780 12:38:52.999082 Jitter Meter : NO K
8781 12:38:52.999503 CBT Training : PASS
8782 12:38:53.002672 Write leveling : PASS
8783 12:38:53.005630 RX DQS gating : PASS
8784 12:38:53.006048 RX DQ/DQS(RDDQC) : PASS
8785 12:38:53.008983 TX DQ/DQS : PASS
8786 12:38:53.009398 RX DATLAT : PASS
8787 12:38:53.012698 RX DQ/DQS(Engine): PASS
8788 12:38:53.015403 TX OE : PASS
8789 12:38:53.015822 All Pass.
8790 12:38:53.016146
8791 12:38:53.016491 CH 0, Rank 1
8792 12:38:53.019847 SW Impedance : PASS
8793 12:38:53.022142 DUTY Scan : NO K
8794 12:38:53.022562 ZQ Calibration : PASS
8795 12:38:53.025616 Jitter Meter : NO K
8796 12:38:53.028944 CBT Training : PASS
8797 12:38:53.029359 Write leveling : PASS
8798 12:38:53.032698 RX DQS gating : PASS
8799 12:38:53.035288 RX DQ/DQS(RDDQC) : PASS
8800 12:38:53.035701 TX DQ/DQS : PASS
8801 12:38:53.040394 RX DATLAT : PASS
8802 12:38:53.042752 RX DQ/DQS(Engine): PASS
8803 12:38:53.043241 TX OE : PASS
8804 12:38:53.045488 All Pass.
8805 12:38:53.045905
8806 12:38:53.046230 CH 1, Rank 0
8807 12:38:53.048977 SW Impedance : PASS
8808 12:38:53.049502 DUTY Scan : NO K
8809 12:38:53.052081 ZQ Calibration : PASS
8810 12:38:53.055693 Jitter Meter : NO K
8811 12:38:53.056199 CBT Training : PASS
8812 12:38:53.058820 Write leveling : PASS
8813 12:38:53.062315 RX DQS gating : PASS
8814 12:38:53.062730 RX DQ/DQS(RDDQC) : PASS
8815 12:38:53.065834 TX DQ/DQS : PASS
8816 12:38:53.066253 RX DATLAT : PASS
8817 12:38:53.068764 RX DQ/DQS(Engine): PASS
8818 12:38:53.072181 TX OE : PASS
8819 12:38:53.072595 All Pass.
8820 12:38:53.072995
8821 12:38:53.073307 CH 1, Rank 1
8822 12:38:53.075592 SW Impedance : PASS
8823 12:38:53.078708 DUTY Scan : NO K
8824 12:38:53.079152 ZQ Calibration : PASS
8825 12:38:53.081777 Jitter Meter : NO K
8826 12:38:53.085195 CBT Training : PASS
8827 12:38:53.085738 Write leveling : PASS
8828 12:38:53.088805 RX DQS gating : PASS
8829 12:38:53.091694 RX DQ/DQS(RDDQC) : PASS
8830 12:38:53.092240 TX DQ/DQS : PASS
8831 12:38:53.095054 RX DATLAT : PASS
8832 12:38:53.098424 RX DQ/DQS(Engine): PASS
8833 12:38:53.098869 TX OE : PASS
8834 12:38:53.101923 All Pass.
8835 12:38:53.102354
8836 12:38:53.102789 DramC Write-DBI on
8837 12:38:53.105968 PER_BANK_REFRESH: Hybrid Mode
8838 12:38:53.106519 TX_TRACKING: ON
8839 12:38:53.114903 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8840 12:38:53.122770 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8841 12:38:53.131929 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8842 12:38:53.135173 [FAST_K] Save calibration result to emmc
8843 12:38:53.138913 sync common calibartion params.
8844 12:38:53.139478 sync cbt_mode0:0, 1:0
8845 12:38:53.141886 dram_init: ddr_geometry: 0
8846 12:38:53.145302 dram_init: ddr_geometry: 0
8847 12:38:53.145786 dram_init: ddr_geometry: 0
8848 12:38:53.148557 0:dram_rank_size:80000000
8849 12:38:53.151981 1:dram_rank_size:80000000
8850 12:38:53.155104 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8851 12:38:53.158129 DFS_SHUFFLE_HW_MODE: ON
8852 12:38:53.161381 dramc_set_vcore_voltage set vcore to 725000
8853 12:38:53.164861 Read voltage for 1600, 0
8854 12:38:53.165340 Vio18 = 0
8855 12:38:53.168331 Vcore = 725000
8856 12:38:53.168844 Vdram = 0
8857 12:38:53.169214 Vddq = 0
8858 12:38:53.169671 Vmddr = 0
8859 12:38:53.171430 switch to 3200 Mbps bootup
8860 12:38:53.174677 [DramcRunTimeConfig]
8861 12:38:53.175268 PHYPLL
8862 12:38:53.177899 DPM_CONTROL_AFTERK: ON
8863 12:38:53.178387 PER_BANK_REFRESH: ON
8864 12:38:53.181105 REFRESH_OVERHEAD_REDUCTION: ON
8865 12:38:53.184826 CMD_PICG_NEW_MODE: OFF
8866 12:38:53.185332 XRTWTW_NEW_MODE: ON
8867 12:38:53.187779 XRTRTR_NEW_MODE: ON
8868 12:38:53.188192 TX_TRACKING: ON
8869 12:38:53.191441 RDSEL_TRACKING: OFF
8870 12:38:53.194630 DQS Precalculation for DVFS: ON
8871 12:38:53.195158 RX_TRACKING: OFF
8872 12:38:53.198017 HW_GATING DBG: ON
8873 12:38:53.198557 ZQCS_ENABLE_LP4: ON
8874 12:38:53.201401 RX_PICG_NEW_MODE: ON
8875 12:38:53.201842 TX_PICG_NEW_MODE: ON
8876 12:38:53.204634 ENABLE_RX_DCM_DPHY: ON
8877 12:38:53.208816 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8878 12:38:53.210839 DUMMY_READ_FOR_TRACKING: OFF
8879 12:38:53.211256 !!! SPM_CONTROL_AFTERK: OFF
8880 12:38:53.214109 !!! SPM could not control APHY
8881 12:38:53.217704 IMPEDANCE_TRACKING: ON
8882 12:38:53.218121 TEMP_SENSOR: ON
8883 12:38:53.220921 HW_SAVE_FOR_SR: OFF
8884 12:38:53.224984 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8885 12:38:53.227400 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8886 12:38:53.227830 Read ODT Tracking: ON
8887 12:38:53.230884 Refresh Rate DeBounce: ON
8888 12:38:53.234601 DFS_NO_QUEUE_FLUSH: ON
8889 12:38:53.237205 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8890 12:38:53.241079 ENABLE_DFS_RUNTIME_MRW: OFF
8891 12:38:53.241495 DDR_RESERVE_NEW_MODE: ON
8892 12:38:53.244286 MR_CBT_SWITCH_FREQ: ON
8893 12:38:53.247099 =========================
8894 12:38:53.265334 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8895 12:38:53.267844 dram_init: ddr_geometry: 0
8896 12:38:53.286248 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8897 12:38:53.289570 dram_init: dram init end (result: 0)
8898 12:38:53.295793 DRAM-K: Full calibration passed in 23410 msecs
8899 12:38:53.299272 MRC: failed to locate region type 0.
8900 12:38:53.299832 DRAM rank0 size:0x80000000,
8901 12:38:53.302334 DRAM rank1 size=0x80000000
8902 12:38:53.312930 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8903 12:38:53.319162 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8904 12:38:53.325823 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8905 12:38:53.333183 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8906 12:38:53.335777 DRAM rank0 size:0x80000000,
8907 12:38:53.339344 DRAM rank1 size=0x80000000
8908 12:38:53.339935 CBMEM:
8909 12:38:53.342317 IMD: root @ 0xfffff000 254 entries.
8910 12:38:53.345674 IMD: root @ 0xffffec00 62 entries.
8911 12:38:53.349403 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8912 12:38:53.352368 WARNING: RO_VPD is uninitialized or empty.
8913 12:38:53.359178 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8914 12:38:53.365379 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8915 12:38:53.378332 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8916 12:38:53.389442 BS: romstage times (exec / console): total (unknown) / 22948 ms
8917 12:38:53.389869
8918 12:38:53.390201
8919 12:38:53.399850 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8920 12:38:53.402881 ARM64: Exception handlers installed.
8921 12:38:53.405684 ARM64: Testing exception
8922 12:38:53.409193 ARM64: Done test exception
8923 12:38:53.409657 Enumerating buses...
8924 12:38:53.412747 Show all devs... Before device enumeration.
8925 12:38:53.416246 Root Device: enabled 1
8926 12:38:53.419304 CPU_CLUSTER: 0: enabled 1
8927 12:38:53.419749 CPU: 00: enabled 1
8928 12:38:53.422317 Compare with tree...
8929 12:38:53.422734 Root Device: enabled 1
8930 12:38:53.425605 CPU_CLUSTER: 0: enabled 1
8931 12:38:53.429453 CPU: 00: enabled 1
8932 12:38:53.429943 Root Device scanning...
8933 12:38:53.432638 scan_static_bus for Root Device
8934 12:38:53.435834 CPU_CLUSTER: 0 enabled
8935 12:38:53.439057 scan_static_bus for Root Device done
8936 12:38:53.442154 scan_bus: bus Root Device finished in 8 msecs
8937 12:38:53.442576 done
8938 12:38:53.449027 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8939 12:38:53.452524 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8940 12:38:53.459192 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8941 12:38:53.462125 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8942 12:38:53.465524 Allocating resources...
8943 12:38:53.468605 Reading resources...
8944 12:38:53.472060 Root Device read_resources bus 0 link: 0
8945 12:38:53.475346 DRAM rank0 size:0x80000000,
8946 12:38:53.475763 DRAM rank1 size=0x80000000
8947 12:38:53.478520 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8948 12:38:53.481927 CPU: 00 missing read_resources
8949 12:38:53.488984 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8950 12:38:53.492587 Root Device read_resources bus 0 link: 0 done
8951 12:38:53.493182 Done reading resources.
8952 12:38:53.498924 Show resources in subtree (Root Device)...After reading.
8953 12:38:53.502476 Root Device child on link 0 CPU_CLUSTER: 0
8954 12:38:53.505169 CPU_CLUSTER: 0 child on link 0 CPU: 00
8955 12:38:53.515860 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8956 12:38:53.516394 CPU: 00
8957 12:38:53.518004 Root Device assign_resources, bus 0 link: 0
8958 12:38:53.521494 CPU_CLUSTER: 0 missing set_resources
8959 12:38:53.528819 Root Device assign_resources, bus 0 link: 0 done
8960 12:38:53.529394 Done setting resources.
8961 12:38:53.535584 Show resources in subtree (Root Device)...After assigning values.
8962 12:38:53.538800 Root Device child on link 0 CPU_CLUSTER: 0
8963 12:38:53.541266 CPU_CLUSTER: 0 child on link 0 CPU: 00
8964 12:38:53.551331 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8965 12:38:53.551992 CPU: 00
8966 12:38:53.554732 Done allocating resources.
8967 12:38:53.561847 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8968 12:38:53.562296 Enabling resources...
8969 12:38:53.562629 done.
8970 12:38:53.568290 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8971 12:38:53.568913 Initializing devices...
8972 12:38:53.571714 Root Device init
8973 12:38:53.574437 init hardware done!
8974 12:38:53.574853 0x00000018: ctrlr->caps
8975 12:38:53.578229 52.000 MHz: ctrlr->f_max
8976 12:38:53.578738 0.400 MHz: ctrlr->f_min
8977 12:38:53.581838 0x40ff8080: ctrlr->voltages
8978 12:38:53.585342 sclk: 390625
8979 12:38:53.585763 Bus Width = 1
8980 12:38:53.586090 sclk: 390625
8981 12:38:53.587843 Bus Width = 1
8982 12:38:53.588262 Early init status = 3
8983 12:38:53.594534 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8984 12:38:53.597611 in-header: 03 fc 00 00 01 00 00 00
8985 12:38:53.601131 in-data: 00
8986 12:38:53.604747 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8987 12:38:53.609182 in-header: 03 fd 00 00 00 00 00 00
8988 12:38:53.612654 in-data:
8989 12:38:53.615707 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8990 12:38:53.619972 in-header: 03 fc 00 00 01 00 00 00
8991 12:38:53.622918 in-data: 00
8992 12:38:53.626724 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8993 12:38:53.631752 in-header: 03 fd 00 00 00 00 00 00
8994 12:38:53.635059 in-data:
8995 12:38:53.637830 [SSUSB] Setting up USB HOST controller...
8996 12:38:53.641302 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8997 12:38:53.644623 [SSUSB] phy power-on done.
8998 12:38:53.648782 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8999 12:38:53.654499 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9000 12:38:53.658118 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9001 12:38:53.664553 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9002 12:38:53.671513 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9003 12:38:53.678776 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9004 12:38:53.685414 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9005 12:38:53.690978 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9006 12:38:53.695028 SPM: binary array size = 0x9dc
9007 12:38:53.698287 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9008 12:38:53.704769 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9009 12:38:53.711128 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9010 12:38:53.718176 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9011 12:38:53.721343 configure_display: Starting display init
9012 12:38:53.755068 anx7625_power_on_init: Init interface.
9013 12:38:53.758563 anx7625_disable_pd_protocol: Disabled PD feature.
9014 12:38:53.761775 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9015 12:38:53.789353 anx7625_start_dp_work: Secure OCM version=00
9016 12:38:53.792646 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9017 12:38:53.807792 sp_tx_get_edid_block: EDID Block = 1
9018 12:38:53.910136 Extracted contents:
9019 12:38:53.913354 header: 00 ff ff ff ff ff ff 00
9020 12:38:53.917085 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9021 12:38:53.920319 version: 01 04
9022 12:38:53.923190 basic params: 95 1f 11 78 0a
9023 12:38:53.926123 chroma info: 76 90 94 55 54 90 27 21 50 54
9024 12:38:53.929444 established: 00 00 00
9025 12:38:53.936105 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9026 12:38:53.940084 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9027 12:38:53.946131 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9028 12:38:53.952886 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9029 12:38:53.959292 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9030 12:38:53.962912 extensions: 00
9031 12:38:53.963392 checksum: fb
9032 12:38:53.964067
9033 12:38:53.966441 Manufacturer: IVO Model 57d Serial Number 0
9034 12:38:53.969031 Made week 0 of 2020
9035 12:38:53.973941 EDID version: 1.4
9036 12:38:53.974431 Digital display
9037 12:38:53.975506 6 bits per primary color channel
9038 12:38:53.975995 DisplayPort interface
9039 12:38:53.978799 Maximum image size: 31 cm x 17 cm
9040 12:38:53.982299 Gamma: 220%
9041 12:38:53.982782 Check DPMS levels
9042 12:38:53.985861 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9043 12:38:53.993043 First detailed timing is preferred timing
9044 12:38:53.993565 Established timings supported:
9045 12:38:53.995686 Standard timings supported:
9046 12:38:53.999093 Detailed timings
9047 12:38:54.002695 Hex of detail: 383680a07038204018303c0035ae10000019
9048 12:38:54.009065 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9049 12:38:54.012765 0780 0798 07c8 0820 hborder 0
9050 12:38:54.015812 0438 043b 0447 0458 vborder 0
9051 12:38:54.018601 -hsync -vsync
9052 12:38:54.019083 Did detailed timing
9053 12:38:54.025221 Hex of detail: 000000000000000000000000000000000000
9054 12:38:54.029326 Manufacturer-specified data, tag 0
9055 12:38:54.032305 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9056 12:38:54.035377 ASCII string: InfoVision
9057 12:38:54.038773 Hex of detail: 000000fe00523134304e574635205248200a
9058 12:38:54.041924 ASCII string: R140NWF5 RH
9059 12:38:54.042484 Checksum
9060 12:38:54.045805 Checksum: 0xfb (valid)
9061 12:38:54.048507 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9062 12:38:54.051939 DSI data_rate: 832800000 bps
9063 12:38:54.059255 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9064 12:38:54.062151 anx7625_parse_edid: pixelclock(138800).
9065 12:38:54.065370 hactive(1920), hsync(48), hfp(24), hbp(88)
9066 12:38:54.068219 vactive(1080), vsync(12), vfp(3), vbp(17)
9067 12:38:54.072329 anx7625_dsi_config: config dsi.
9068 12:38:54.078664 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9069 12:38:54.092136 anx7625_dsi_config: success to config DSI
9070 12:38:54.095227 anx7625_dp_start: MIPI phy setup OK.
9071 12:38:54.098339 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9072 12:38:54.101650 mtk_ddp_mode_set invalid vrefresh 60
9073 12:38:54.104879 main_disp_path_setup
9074 12:38:54.105342 ovl_layer_smi_id_en
9075 12:38:54.108581 ovl_layer_smi_id_en
9076 12:38:54.109156 ccorr_config
9077 12:38:54.109528 aal_config
9078 12:38:54.111683 gamma_config
9079 12:38:54.112142 postmask_config
9080 12:38:54.115489 dither_config
9081 12:38:54.118507 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9082 12:38:54.124980 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9083 12:38:54.128157 Root Device init finished in 553 msecs
9084 12:38:54.132455 CPU_CLUSTER: 0 init
9085 12:38:54.138527 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9086 12:38:54.141540 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9087 12:38:54.144532 APU_MBOX 0x190000b0 = 0x10001
9088 12:38:54.148005 APU_MBOX 0x190001b0 = 0x10001
9089 12:38:54.151969 APU_MBOX 0x190005b0 = 0x10001
9090 12:38:54.155330 APU_MBOX 0x190006b0 = 0x10001
9091 12:38:54.161236 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9092 12:38:54.171494 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9093 12:38:54.183283 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9094 12:38:54.189913 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9095 12:38:54.201993 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9096 12:38:54.210863 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9097 12:38:54.213998 CPU_CLUSTER: 0 init finished in 81 msecs
9098 12:38:54.217057 Devices initialized
9099 12:38:54.220771 Show all devs... After init.
9100 12:38:54.221309 Root Device: enabled 1
9101 12:38:54.223710 CPU_CLUSTER: 0: enabled 1
9102 12:38:54.228472 CPU: 00: enabled 1
9103 12:38:54.230808 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9104 12:38:54.234125 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9105 12:38:54.236864 ELOG: NV offset 0x57f000 size 0x1000
9106 12:38:54.243641 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9107 12:38:54.250328 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9108 12:38:54.253646 ELOG: Event(17) added with size 13 at 2024-02-05 12:38:58 UTC
9109 12:38:54.257021 out: cmd=0x121: 03 db 21 01 00 00 00 00
9110 12:38:54.261303 in-header: 03 0d 00 00 2c 00 00 00
9111 12:38:54.273892 in-data: 56 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9112 12:38:54.280540 ELOG: Event(A1) added with size 10 at 2024-02-05 12:38:58 UTC
9113 12:38:54.287476 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9114 12:38:54.293877 ELOG: Event(A0) added with size 9 at 2024-02-05 12:38:58 UTC
9115 12:38:54.297169 elog_add_boot_reason: Logged dev mode boot
9116 12:38:54.300470 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9117 12:38:54.303944 Finalize devices...
9118 12:38:54.304466 Devices finalized
9119 12:38:54.310176 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9120 12:38:54.313422 Writing coreboot table at 0xffe64000
9121 12:38:54.316990 0. 000000000010a000-0000000000113fff: RAMSTAGE
9122 12:38:54.320287 1. 0000000040000000-00000000400fffff: RAM
9123 12:38:54.326725 2. 0000000040100000-000000004032afff: RAMSTAGE
9124 12:38:54.330277 3. 000000004032b000-00000000545fffff: RAM
9125 12:38:54.333735 4. 0000000054600000-000000005465ffff: BL31
9126 12:38:54.337207 5. 0000000054660000-00000000ffe63fff: RAM
9127 12:38:54.343283 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9128 12:38:54.346546 7. 0000000100000000-000000013fffffff: RAM
9129 12:38:54.349852 Passing 5 GPIOs to payload:
9130 12:38:54.353588 NAME | PORT | POLARITY | VALUE
9131 12:38:54.356657 EC in RW | 0x000000aa | low | undefined
9132 12:38:54.363723 EC interrupt | 0x00000005 | low | undefined
9133 12:38:54.366673 TPM interrupt | 0x000000ab | high | undefined
9134 12:38:54.372944 SD card detect | 0x00000011 | high | undefined
9135 12:38:54.377144 speaker enable | 0x00000093 | high | undefined
9136 12:38:54.379967 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9137 12:38:54.383523 in-header: 03 ef 00 00 02 00 00 00
9138 12:38:54.386132 in-data: 0c 00
9139 12:38:54.386547 ADC[4]: Raw value=668958 ID=5
9140 12:38:54.389748 ADC[3]: Raw value=212549 ID=1
9141 12:38:54.392993 RAM Code: 0x51
9142 12:38:54.393437 ADC[6]: Raw value=74410 ID=0
9143 12:38:54.396607 ADC[5]: Raw value=211812 ID=1
9144 12:38:54.399797 SKU Code: 0x1
9145 12:38:54.403654 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 891a
9146 12:38:54.405787 coreboot table: 964 bytes.
9147 12:38:54.410253 IMD ROOT 0. 0xfffff000 0x00001000
9148 12:38:54.413498 IMD SMALL 1. 0xffffe000 0x00001000
9149 12:38:54.416265 RO MCACHE 2. 0xffffc000 0x00001104
9150 12:38:54.419598 CONSOLE 3. 0xfff7c000 0x00080000
9151 12:38:54.423156 FMAP 4. 0xfff7b000 0x00000452
9152 12:38:54.426813 TIME STAMP 5. 0xfff7a000 0x00000910
9153 12:38:54.429263 VBOOT WORK 6. 0xfff66000 0x00014000
9154 12:38:54.432417 RAMOOPS 7. 0xffe66000 0x00100000
9155 12:38:54.435562 COREBOOT 8. 0xffe64000 0x00002000
9156 12:38:54.439116 IMD small region:
9157 12:38:54.442538 IMD ROOT 0. 0xffffec00 0x00000400
9158 12:38:54.446079 VPD 1. 0xffffeb80 0x0000006c
9159 12:38:54.449761 MMC STATUS 2. 0xffffeb60 0x00000004
9160 12:38:54.452617 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9161 12:38:54.455724 Probing TPM: done!
9162 12:38:54.459254 Connected to device vid:did:rid of 1ae0:0028:00
9163 12:38:54.469400 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9164 12:38:54.472971 Initialized TPM device CR50 revision 0
9165 12:38:54.476101 Checking cr50 for pending updates
9166 12:38:54.480086 Reading cr50 TPM mode
9167 12:38:54.488684 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9168 12:38:54.495405 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9169 12:38:54.535642 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9170 12:38:54.539889 Checking segment from ROM address 0x40100000
9171 12:38:54.542736 Checking segment from ROM address 0x4010001c
9172 12:38:54.551259 Loading segment from ROM address 0x40100000
9173 12:38:54.551961 code (compression=0)
9174 12:38:54.559393 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9175 12:38:54.566196 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9176 12:38:54.566804 it's not compressed!
9177 12:38:54.572004 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9178 12:38:54.575384 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9179 12:38:54.596384 Loading segment from ROM address 0x4010001c
9180 12:38:54.596943 Entry Point 0x80000000
9181 12:38:54.599579 Loaded segments
9182 12:38:54.603065 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9183 12:38:54.609845 Jumping to boot code at 0x80000000(0xffe64000)
9184 12:38:54.615810 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9185 12:38:54.622652 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9186 12:38:54.630188 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9187 12:38:54.633518 Checking segment from ROM address 0x40100000
9188 12:38:54.637745 Checking segment from ROM address 0x4010001c
9189 12:38:54.644416 Loading segment from ROM address 0x40100000
9190 12:38:54.644941 code (compression=1)
9191 12:38:54.650627 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9192 12:38:54.660160 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9193 12:38:54.660585 using LZMA
9194 12:38:54.668411 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9195 12:38:54.675246 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9196 12:38:54.678726 Loading segment from ROM address 0x4010001c
9197 12:38:54.679146 Entry Point 0x54601000
9198 12:38:54.682524 Loaded segments
9199 12:38:54.685721 NOTICE: MT8192 bl31_setup
9200 12:38:54.692432 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9201 12:38:54.696973 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9202 12:38:54.698852 WARNING: region 0:
9203 12:38:54.702374 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9204 12:38:54.702794 WARNING: region 1:
9205 12:38:54.708824 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9206 12:38:54.712587 WARNING: region 2:
9207 12:38:54.715583 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9208 12:38:54.719737 WARNING: region 3:
9209 12:38:54.722926 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9210 12:38:54.725486 WARNING: region 4:
9211 12:38:54.732518 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9212 12:38:54.733045 WARNING: region 5:
9213 12:38:54.735772 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9214 12:38:54.738932 WARNING: region 6:
9215 12:38:54.743171 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9216 12:38:54.746029 WARNING: region 7:
9217 12:38:54.749102 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9218 12:38:54.755840 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9219 12:38:54.758638 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9220 12:38:54.762678 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9221 12:38:54.768760 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9222 12:38:54.772865 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9223 12:38:54.775688 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9224 12:38:54.782103 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9225 12:38:54.785980 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9226 12:38:54.792253 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9227 12:38:54.795208 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9228 12:38:54.798820 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9229 12:38:54.805796 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9230 12:38:54.808853 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9231 12:38:54.812369 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9232 12:38:54.819194 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9233 12:38:54.822769 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9234 12:38:54.825918 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9235 12:38:54.832762 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9236 12:38:54.836175 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9237 12:38:54.842870 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9238 12:38:54.845715 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9239 12:38:54.849438 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9240 12:38:54.855806 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9241 12:38:54.860053 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9242 12:38:54.865425 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9243 12:38:54.868973 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9244 12:38:54.871745 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9245 12:38:54.879086 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9246 12:38:54.882235 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9247 12:38:54.889188 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9248 12:38:54.892155 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9249 12:38:54.895228 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9250 12:38:54.901789 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9251 12:38:54.905669 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9252 12:38:54.909200 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9253 12:38:54.912750 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9254 12:38:54.919054 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9255 12:38:54.923606 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9256 12:38:54.925404 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9257 12:38:54.929152 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9258 12:38:54.936744 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9259 12:38:54.938859 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9260 12:38:54.942976 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9261 12:38:54.945674 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9262 12:38:54.952604 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9263 12:38:54.955725 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9264 12:38:54.959621 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9265 12:38:54.962058 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9266 12:38:54.968974 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9267 12:38:54.972647 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9268 12:38:54.979002 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9269 12:38:54.982768 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9270 12:38:54.985870 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9271 12:38:54.991782 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9272 12:38:54.995282 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9273 12:38:55.002364 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9274 12:38:55.005619 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9275 12:38:55.012568 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9276 12:38:55.015172 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9277 12:38:55.019355 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9278 12:38:55.025357 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9279 12:38:55.028915 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9280 12:38:55.035229 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9281 12:38:55.039014 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9282 12:38:55.045611 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9283 12:38:55.049896 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9284 12:38:55.055786 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9285 12:38:55.059751 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9286 12:38:55.062277 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9287 12:38:55.068796 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9288 12:38:55.072283 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9289 12:38:55.079195 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9290 12:38:55.081970 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9291 12:38:55.088655 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9292 12:38:55.092336 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9293 12:38:55.096496 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9294 12:38:55.102564 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9295 12:38:55.105501 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9296 12:38:55.112403 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9297 12:38:55.115312 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9298 12:38:55.122223 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9299 12:38:55.125082 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9300 12:38:55.128670 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9301 12:38:55.135284 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9302 12:38:55.138538 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9303 12:38:55.145032 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9304 12:38:55.148766 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9305 12:38:55.155524 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9306 12:38:55.158731 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9307 12:38:55.162058 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9308 12:38:55.168954 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9309 12:38:55.172113 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9310 12:38:55.178797 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9311 12:38:55.182421 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9312 12:38:55.188493 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9313 12:38:55.191843 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9314 12:38:55.195189 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9315 12:38:55.202051 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9316 12:38:55.206340 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9317 12:38:55.208458 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9318 12:38:55.212448 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9319 12:38:55.218473 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9320 12:38:55.221828 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9321 12:38:55.228918 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9322 12:38:55.232281 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9323 12:38:55.235346 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9324 12:38:55.241974 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9325 12:38:55.244914 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9326 12:38:55.251656 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9327 12:38:55.255420 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9328 12:38:55.259021 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9329 12:38:55.265281 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9330 12:38:55.268137 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9331 12:38:55.275284 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9332 12:38:55.278517 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9333 12:38:55.281429 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9334 12:38:55.284699 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9335 12:38:55.292090 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9336 12:38:55.294971 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9337 12:38:55.298021 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9338 12:38:55.304972 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9339 12:38:55.308126 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9340 12:38:55.311327 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9341 12:38:55.314619 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9342 12:38:55.321934 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9343 12:38:55.325157 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9344 12:38:55.331722 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9345 12:38:55.336256 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9346 12:38:55.338361 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9347 12:38:55.345266 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9348 12:38:55.349098 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9349 12:38:55.355818 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9350 12:38:55.358574 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9351 12:38:55.361857 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9352 12:38:55.368136 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9353 12:38:55.371863 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9354 12:38:55.375751 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9355 12:38:55.382247 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9356 12:38:55.385142 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9357 12:38:55.391964 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9358 12:38:55.395191 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9359 12:38:55.398596 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9360 12:38:55.405114 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9361 12:38:55.408837 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9362 12:38:55.415806 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9363 12:38:55.418521 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9364 12:38:55.422583 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9365 12:38:55.428911 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9366 12:38:55.431909 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9367 12:38:55.435195 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9368 12:38:55.442106 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9369 12:38:55.445590 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9370 12:38:55.452104 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9371 12:38:55.455606 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9372 12:38:55.458794 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9373 12:38:55.465800 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9374 12:38:55.469206 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9375 12:38:55.474998 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9376 12:38:55.478498 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9377 12:38:55.482239 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9378 12:38:55.487970 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9379 12:38:55.491684 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9380 12:38:55.498021 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9381 12:38:55.501627 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9382 12:38:55.504809 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9383 12:38:55.511721 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9384 12:38:55.515513 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9385 12:38:55.518947 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9386 12:38:55.524826 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9387 12:38:55.528085 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9388 12:38:55.535270 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9389 12:38:55.537979 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9390 12:38:55.541790 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9391 12:38:55.548628 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9392 12:38:55.552289 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9393 12:38:55.557890 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9394 12:38:55.561123 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9395 12:38:55.565122 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9396 12:38:55.571507 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9397 12:38:55.574554 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9398 12:38:55.581014 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9399 12:38:55.584387 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9400 12:38:55.587627 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9401 12:38:55.594526 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9402 12:38:55.598217 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9403 12:38:55.604788 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9404 12:38:55.608038 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9405 12:38:55.611193 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9406 12:38:55.617945 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9407 12:38:55.620643 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9408 12:38:55.627810 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9409 12:38:55.632044 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9410 12:38:55.638292 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9411 12:38:55.641319 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9412 12:38:55.644305 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9413 12:38:55.650786 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9414 12:38:55.654157 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9415 12:38:55.661084 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9416 12:38:55.664034 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9417 12:38:55.667783 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9418 12:38:55.673645 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9419 12:38:55.677363 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9420 12:38:55.683978 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9421 12:38:55.686764 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9422 12:38:55.693354 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9423 12:38:55.696814 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9424 12:38:55.699907 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9425 12:38:55.706878 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9426 12:38:55.710546 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9427 12:38:55.716679 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9428 12:38:55.720149 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9429 12:38:55.726870 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9430 12:38:55.730080 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9431 12:38:55.733631 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9432 12:38:55.739982 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9433 12:38:55.743123 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9434 12:38:55.750758 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9435 12:38:55.753192 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9436 12:38:55.760025 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9437 12:38:55.763493 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9438 12:38:55.766565 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9439 12:38:55.773292 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9440 12:38:55.776152 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9441 12:38:55.783348 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9442 12:38:55.787121 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9443 12:38:55.789336 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9444 12:38:55.796540 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9445 12:38:55.799311 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9446 12:38:55.806292 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9447 12:38:55.809396 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9448 12:38:55.812880 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9449 12:38:55.816248 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9450 12:38:55.822555 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9451 12:38:55.825693 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9452 12:38:55.829407 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9453 12:38:55.835811 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9454 12:38:55.838776 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9455 12:38:55.842300 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9456 12:38:55.849504 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9457 12:38:55.853263 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9458 12:38:55.858718 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9459 12:38:55.862143 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9460 12:38:55.866129 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9461 12:38:55.872272 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9462 12:38:55.875315 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9463 12:38:55.878476 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9464 12:38:55.885340 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9465 12:38:55.888383 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9466 12:38:55.892220 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9467 12:38:55.898475 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9468 12:38:55.901357 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9469 12:38:55.908420 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9470 12:38:55.911374 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9471 12:38:55.915568 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9472 12:38:55.921329 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9473 12:38:55.925208 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9474 12:38:55.932459 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9475 12:38:55.935138 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9476 12:38:55.938018 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9477 12:38:55.944551 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9478 12:38:55.948618 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9479 12:38:55.951276 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9480 12:38:55.958529 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9481 12:38:55.960971 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9482 12:38:55.964697 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9483 12:38:55.971143 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9484 12:38:55.974191 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9485 12:38:55.981266 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9486 12:38:55.984673 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9487 12:38:55.987578 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9488 12:38:55.991208 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9489 12:38:55.997901 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9490 12:38:56.000942 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9491 12:38:56.003869 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9492 12:38:56.007699 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9493 12:38:56.011347 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9494 12:38:56.017283 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9495 12:38:56.020616 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9496 12:38:56.023855 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9497 12:38:56.027517 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9498 12:38:56.034476 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9499 12:38:56.038583 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9500 12:38:56.040939 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9501 12:38:56.047786 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9502 12:38:56.050914 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9503 12:38:56.057519 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9504 12:38:56.061205 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9505 12:38:56.067269 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9506 12:38:56.070938 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9507 12:38:56.073904 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9508 12:38:56.080641 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9509 12:38:56.083903 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9510 12:38:56.089922 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9511 12:38:56.093774 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9512 12:38:56.100869 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9513 12:38:56.104003 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9514 12:38:56.107461 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9515 12:38:56.113826 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9516 12:38:56.118411 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9517 12:38:56.120547 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9518 12:38:56.127395 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9519 12:38:56.130195 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9520 12:38:56.137017 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9521 12:38:56.141026 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9522 12:38:56.146719 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9523 12:38:56.150521 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9524 12:38:56.153531 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9525 12:38:56.160052 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9526 12:38:56.163706 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9527 12:38:56.170164 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9528 12:38:56.173237 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9529 12:38:56.179467 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9530 12:38:56.183329 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9531 12:38:56.187460 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9532 12:38:56.193037 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9533 12:38:56.196447 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9534 12:38:56.203037 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9535 12:38:56.206628 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9536 12:38:56.209553 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9537 12:38:56.216577 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9538 12:38:56.220083 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9539 12:38:56.226611 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9540 12:38:56.229681 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9541 12:38:56.233244 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9542 12:38:56.239690 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9543 12:38:56.242550 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9544 12:38:56.249112 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9545 12:38:56.252677 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9546 12:38:56.259192 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9547 12:38:56.262482 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9548 12:38:56.265531 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9549 12:38:56.272856 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9550 12:38:56.276366 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9551 12:38:56.282309 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9552 12:38:56.285871 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9553 12:38:56.288821 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9554 12:38:56.296289 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9555 12:38:56.298988 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9556 12:38:56.305481 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9557 12:38:56.309314 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9558 12:38:56.311951 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9559 12:38:56.319083 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9560 12:38:56.321825 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9561 12:38:56.328944 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9562 12:38:56.332810 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9563 12:38:56.338293 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9564 12:38:56.342256 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9565 12:38:56.345458 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9566 12:38:56.352091 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9567 12:38:56.355537 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9568 12:38:56.361486 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9569 12:38:56.364509 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9570 12:38:56.371677 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9571 12:38:56.374507 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9572 12:38:56.377838 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9573 12:38:56.384849 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9574 12:38:56.388286 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9575 12:38:56.394535 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9576 12:38:56.397716 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9577 12:38:56.404687 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9578 12:38:56.408058 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9579 12:38:56.410742 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9580 12:38:56.418400 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9581 12:38:56.421609 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9582 12:38:56.427451 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9583 12:38:56.430914 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9584 12:38:56.437565 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9585 12:38:56.440657 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9586 12:38:56.447173 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9587 12:38:56.450768 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9588 12:38:56.453618 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9589 12:38:56.460564 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9590 12:38:56.464277 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9591 12:38:56.470295 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9592 12:38:56.473903 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9593 12:38:56.480506 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9594 12:38:56.483118 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9595 12:38:56.489609 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9596 12:38:56.493704 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9597 12:38:56.496788 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9598 12:38:56.503585 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9599 12:38:56.507692 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9600 12:38:56.513242 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9601 12:38:56.516214 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9602 12:38:56.523286 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9603 12:38:56.527142 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9604 12:38:56.529388 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9605 12:38:56.537472 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9606 12:38:56.541159 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9607 12:38:56.546076 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9608 12:38:56.549379 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9609 12:38:56.556174 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9610 12:38:56.559419 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9611 12:38:56.566244 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9612 12:38:56.569382 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9613 12:38:56.572634 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9614 12:38:56.579333 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9615 12:38:56.582818 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9616 12:38:56.589195 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9617 12:38:56.592775 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9618 12:38:56.598892 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9619 12:38:56.602016 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9620 12:38:56.605657 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9621 12:38:56.612524 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9622 12:38:56.615557 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9623 12:38:56.622672 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9624 12:38:56.625822 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9625 12:38:56.632621 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9626 12:38:56.635816 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9627 12:38:56.642045 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9628 12:38:56.645302 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9629 12:38:56.652574 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9630 12:38:56.655997 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9631 12:38:56.662226 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9632 12:38:56.665248 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9633 12:38:56.671847 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9634 12:38:56.676271 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9635 12:38:56.682008 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9636 12:38:56.685187 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9637 12:38:56.691326 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9638 12:38:56.694764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9639 12:38:56.701993 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9640 12:38:56.704821 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9641 12:38:56.711952 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9642 12:38:56.714841 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9643 12:38:56.721831 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9644 12:38:56.724903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9645 12:38:56.731275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9646 12:38:56.734583 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9647 12:38:56.741695 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9648 12:38:56.745376 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9649 12:38:56.751666 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9650 12:38:56.755457 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9651 12:38:56.761163 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9652 12:38:56.764221 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9653 12:38:56.768370 INFO: [APUAPC] vio 0
9654 12:38:56.771259 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9655 12:38:56.777559 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9656 12:38:56.781145 INFO: [APUAPC] D0_APC_0: 0x400510
9657 12:38:56.781607 INFO: [APUAPC] D0_APC_1: 0x0
9658 12:38:56.784546 INFO: [APUAPC] D0_APC_2: 0x1540
9659 12:38:56.787455 INFO: [APUAPC] D0_APC_3: 0x0
9660 12:38:56.790910 INFO: [APUAPC] D1_APC_0: 0xffffffff
9661 12:38:56.794036 INFO: [APUAPC] D1_APC_1: 0xffffffff
9662 12:38:56.797395 INFO: [APUAPC] D1_APC_2: 0x3fffff
9663 12:38:56.801034 INFO: [APUAPC] D1_APC_3: 0x0
9664 12:38:56.803903 INFO: [APUAPC] D2_APC_0: 0xffffffff
9665 12:38:56.807497 INFO: [APUAPC] D2_APC_1: 0xffffffff
9666 12:38:56.811073 INFO: [APUAPC] D2_APC_2: 0x3fffff
9667 12:38:56.814060 INFO: [APUAPC] D2_APC_3: 0x0
9668 12:38:56.817349 INFO: [APUAPC] D3_APC_0: 0xffffffff
9669 12:38:56.820574 INFO: [APUAPC] D3_APC_1: 0xffffffff
9670 12:38:56.823767 INFO: [APUAPC] D3_APC_2: 0x3fffff
9671 12:38:56.827527 INFO: [APUAPC] D3_APC_3: 0x0
9672 12:38:56.830360 INFO: [APUAPC] D4_APC_0: 0xffffffff
9673 12:38:56.833282 INFO: [APUAPC] D4_APC_1: 0xffffffff
9674 12:38:56.837630 INFO: [APUAPC] D4_APC_2: 0x3fffff
9675 12:38:56.840286 INFO: [APUAPC] D4_APC_3: 0x0
9676 12:38:56.844413 INFO: [APUAPC] D5_APC_0: 0xffffffff
9677 12:38:56.846884 INFO: [APUAPC] D5_APC_1: 0xffffffff
9678 12:38:56.850761 INFO: [APUAPC] D5_APC_2: 0x3fffff
9679 12:38:56.853420 INFO: [APUAPC] D5_APC_3: 0x0
9680 12:38:56.857008 INFO: [APUAPC] D6_APC_0: 0xffffffff
9681 12:38:56.860691 INFO: [APUAPC] D6_APC_1: 0xffffffff
9682 12:38:56.863426 INFO: [APUAPC] D6_APC_2: 0x3fffff
9683 12:38:56.866489 INFO: [APUAPC] D6_APC_3: 0x0
9684 12:38:56.870093 INFO: [APUAPC] D7_APC_0: 0xffffffff
9685 12:38:56.873404 INFO: [APUAPC] D7_APC_1: 0xffffffff
9686 12:38:56.876976 INFO: [APUAPC] D7_APC_2: 0x3fffff
9687 12:38:56.879689 INFO: [APUAPC] D7_APC_3: 0x0
9688 12:38:56.884245 INFO: [APUAPC] D8_APC_0: 0xffffffff
9689 12:38:56.886247 INFO: [APUAPC] D8_APC_1: 0xffffffff
9690 12:38:56.890206 INFO: [APUAPC] D8_APC_2: 0x3fffff
9691 12:38:56.892816 INFO: [APUAPC] D8_APC_3: 0x0
9692 12:38:56.896317 INFO: [APUAPC] D9_APC_0: 0xffffffff
9693 12:38:56.899839 INFO: [APUAPC] D9_APC_1: 0xffffffff
9694 12:38:56.903670 INFO: [APUAPC] D9_APC_2: 0x3fffff
9695 12:38:56.906362 INFO: [APUAPC] D9_APC_3: 0x0
9696 12:38:56.909888 INFO: [APUAPC] D10_APC_0: 0xffffffff
9697 12:38:56.912881 INFO: [APUAPC] D10_APC_1: 0xffffffff
9698 12:38:56.916560 INFO: [APUAPC] D10_APC_2: 0x3fffff
9699 12:38:56.920236 INFO: [APUAPC] D10_APC_3: 0x0
9700 12:38:56.922789 INFO: [APUAPC] D11_APC_0: 0xffffffff
9701 12:38:56.926366 INFO: [APUAPC] D11_APC_1: 0xffffffff
9702 12:38:56.930017 INFO: [APUAPC] D11_APC_2: 0x3fffff
9703 12:38:56.933021 INFO: [APUAPC] D11_APC_3: 0x0
9704 12:38:56.936077 INFO: [APUAPC] D12_APC_0: 0xffffffff
9705 12:38:56.939751 INFO: [APUAPC] D12_APC_1: 0xffffffff
9706 12:38:56.943033 INFO: [APUAPC] D12_APC_2: 0x3fffff
9707 12:38:56.946117 INFO: [APUAPC] D12_APC_3: 0x0
9708 12:38:56.949813 INFO: [APUAPC] D13_APC_0: 0xffffffff
9709 12:38:56.952803 INFO: [APUAPC] D13_APC_1: 0xffffffff
9710 12:38:56.956179 INFO: [APUAPC] D13_APC_2: 0x3fffff
9711 12:38:56.959517 INFO: [APUAPC] D13_APC_3: 0x0
9712 12:38:56.962589 INFO: [APUAPC] D14_APC_0: 0xffffffff
9713 12:38:56.966812 INFO: [APUAPC] D14_APC_1: 0xffffffff
9714 12:38:56.969679 INFO: [APUAPC] D14_APC_2: 0x3fffff
9715 12:38:56.972930 INFO: [APUAPC] D14_APC_3: 0x0
9716 12:38:56.975929 INFO: [APUAPC] D15_APC_0: 0xffffffff
9717 12:38:56.979389 INFO: [APUAPC] D15_APC_1: 0xffffffff
9718 12:38:56.982852 INFO: [APUAPC] D15_APC_2: 0x3fffff
9719 12:38:56.985990 INFO: [APUAPC] D15_APC_3: 0x0
9720 12:38:56.989244 INFO: [APUAPC] APC_CON: 0x4
9721 12:38:56.992512 INFO: [NOCDAPC] D0_APC_0: 0x0
9722 12:38:56.993036 INFO: [NOCDAPC] D0_APC_1: 0x0
9723 12:38:56.996316 INFO: [NOCDAPC] D1_APC_0: 0x0
9724 12:38:56.998760 INFO: [NOCDAPC] D1_APC_1: 0xfff
9725 12:38:57.002027 INFO: [NOCDAPC] D2_APC_0: 0x0
9726 12:38:57.005676 INFO: [NOCDAPC] D2_APC_1: 0xfff
9727 12:38:57.010003 INFO: [NOCDAPC] D3_APC_0: 0x0
9728 12:38:57.011809 INFO: [NOCDAPC] D3_APC_1: 0xfff
9729 12:38:57.016219 INFO: [NOCDAPC] D4_APC_0: 0x0
9730 12:38:57.018776 INFO: [NOCDAPC] D4_APC_1: 0xfff
9731 12:38:57.022262 INFO: [NOCDAPC] D5_APC_0: 0x0
9732 12:38:57.025191 INFO: [NOCDAPC] D5_APC_1: 0xfff
9733 12:38:57.025652 INFO: [NOCDAPC] D6_APC_0: 0x0
9734 12:38:57.028935 INFO: [NOCDAPC] D6_APC_1: 0xfff
9735 12:38:57.031911 INFO: [NOCDAPC] D7_APC_0: 0x0
9736 12:38:57.035546 INFO: [NOCDAPC] D7_APC_1: 0xfff
9737 12:38:57.038661 INFO: [NOCDAPC] D8_APC_0: 0x0
9738 12:38:57.042438 INFO: [NOCDAPC] D8_APC_1: 0xfff
9739 12:38:57.045429 INFO: [NOCDAPC] D9_APC_0: 0x0
9740 12:38:57.049078 INFO: [NOCDAPC] D9_APC_1: 0xfff
9741 12:38:57.051488 INFO: [NOCDAPC] D10_APC_0: 0x0
9742 12:38:57.055144 INFO: [NOCDAPC] D10_APC_1: 0xfff
9743 12:38:57.058193 INFO: [NOCDAPC] D11_APC_0: 0x0
9744 12:38:57.061657 INFO: [NOCDAPC] D11_APC_1: 0xfff
9745 12:38:57.064772 INFO: [NOCDAPC] D12_APC_0: 0x0
9746 12:38:57.067933 INFO: [NOCDAPC] D12_APC_1: 0xfff
9747 12:38:57.071622 INFO: [NOCDAPC] D13_APC_0: 0x0
9748 12:38:57.072186 INFO: [NOCDAPC] D13_APC_1: 0xfff
9749 12:38:57.075140 INFO: [NOCDAPC] D14_APC_0: 0x0
9750 12:38:57.077707 INFO: [NOCDAPC] D14_APC_1: 0xfff
9751 12:38:57.081135 INFO: [NOCDAPC] D15_APC_0: 0x0
9752 12:38:57.085264 INFO: [NOCDAPC] D15_APC_1: 0xfff
9753 12:38:57.087914 INFO: [NOCDAPC] APC_CON: 0x4
9754 12:38:57.091160 INFO: [APUAPC] set_apusys_apc done
9755 12:38:57.094951 INFO: [DEVAPC] devapc_init done
9756 12:38:57.097594 INFO: GICv3 without legacy support detected.
9757 12:38:57.104436 INFO: ARM GICv3 driver initialized in EL3
9758 12:38:57.108022 INFO: Maximum SPI INTID supported: 639
9759 12:38:57.111171 INFO: BL31: Initializing runtime services
9760 12:38:57.117570 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9761 12:38:57.118118 INFO: SPM: enable CPC mode
9762 12:38:57.124322 INFO: mcdi ready for mcusys-off-idle and system suspend
9763 12:38:57.128142 INFO: BL31: Preparing for EL3 exit to normal world
9764 12:38:57.134009 INFO: Entry point address = 0x80000000
9765 12:38:57.134555 INFO: SPSR = 0x8
9766 12:38:57.140645
9767 12:38:57.141290
9768 12:38:57.141662
9769 12:38:57.144368 Starting depthcharge on Spherion...
9770 12:38:57.145027
9771 12:38:57.145416 Wipe memory regions:
9772 12:38:57.145763
9773 12:38:57.148438 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9774 12:38:57.149082 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9775 12:38:57.149730 Setting prompt string to ['asurada:']
9776 12:38:57.150197 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9777 12:38:57.150924 [0x00000040000000, 0x00000054600000)
9778 12:38:57.269354
9779 12:38:57.269906 [0x00000054660000, 0x00000080000000)
9780 12:38:57.529199
9781 12:38:57.529467 [0x000000821a7280, 0x000000ffe64000)
9782 12:38:58.274893
9783 12:38:58.275445 [0x00000100000000, 0x00000140000000)
9784 12:38:58.656167
9785 12:38:58.659786 Initializing XHCI USB controller at 0x11200000.
9786 12:38:59.696996
9787 12:38:59.700658 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9788 12:38:59.701169
9789 12:38:59.701530
9790 12:38:59.701860
9791 12:38:59.702715 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9793 12:38:59.804183 asurada: tftpboot 192.168.201.1 12703510/tftp-deploy-mt650d1d/kernel/image.itb 12703510/tftp-deploy-mt650d1d/kernel/cmdline
9794 12:38:59.804879 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9795 12:38:59.805331 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9796 12:38:59.809751 tftpboot 192.168.201.1 12703510/tftp-deploy-mt650d1d/kernel/image.ittp-deploy-mt650d1d/kernel/cmdline
9797 12:38:59.809835
9798 12:38:59.809900 Waiting for link
9799 12:38:59.970937
9800 12:38:59.971496 R8152: Initializing
9801 12:38:59.971867
9802 12:38:59.973838 Version 9 (ocp_data = 6010)
9803 12:38:59.974397
9804 12:38:59.976936 R8152: Done initializing
9805 12:38:59.977499
9806 12:38:59.977868 Adding net device
9807 12:39:01.891277
9808 12:39:01.891856 done.
9809 12:39:01.892226
9810 12:39:01.892570 MAC: 00:e0:4c:68:03:bd
9811 12:39:01.892945
9812 12:39:01.893995 Sending DHCP discover... done.
9813 12:39:01.894712
9814 12:39:01.896848 Waiting for reply... done.
9815 12:39:01.897482
9816 12:39:01.901275 Sending DHCP request... done.
9817 12:39:01.901867
9818 12:39:01.908106 Waiting for reply... done.
9819 12:39:01.908595
9820 12:39:01.909025 My ip is 192.168.201.16
9821 12:39:01.909391
9822 12:39:01.911238 The DHCP server ip is 192.168.201.1
9823 12:39:01.911692
9824 12:39:01.918284 TFTP server IP predefined by user: 192.168.201.1
9825 12:39:01.918809
9826 12:39:01.925141 Bootfile predefined by user: 12703510/tftp-deploy-mt650d1d/kernel/image.itb
9827 12:39:01.926004
9828 12:39:01.927905 Sending tftp read request... done.
9829 12:39:01.928452
9830 12:39:01.934715 Waiting for the transfer...
9831 12:39:01.935195
9832 12:39:02.216122 00000000 ################################################################
9833 12:39:02.216255
9834 12:39:02.471752 00080000 ################################################################
9835 12:39:02.471885
9836 12:39:02.739584 00100000 ################################################################
9837 12:39:02.739715
9838 12:39:02.995473 00180000 ################################################################
9839 12:39:02.995609
9840 12:39:03.270331 00200000 ################################################################
9841 12:39:03.270466
9842 12:39:03.525002 00280000 ################################################################
9843 12:39:03.525134
9844 12:39:03.785068 00300000 ################################################################
9845 12:39:03.785197
9846 12:39:04.044803 00380000 ################################################################
9847 12:39:04.044934
9848 12:39:04.299518 00400000 ################################################################
9849 12:39:04.299655
9850 12:39:04.559235 00480000 ################################################################
9851 12:39:04.559380
9852 12:39:04.828368 00500000 ################################################################
9853 12:39:04.828510
9854 12:39:05.116105 00580000 ################################################################
9855 12:39:05.116234
9856 12:39:05.374764 00600000 ################################################################
9857 12:39:05.374912
9858 12:39:05.625476 00680000 ################################################################
9859 12:39:05.625640
9860 12:39:05.886592 00700000 ################################################################
9861 12:39:05.886775
9862 12:39:06.152604 00780000 ################################################################
9863 12:39:06.152751
9864 12:39:06.408701 00800000 ################################################################
9865 12:39:06.408875
9866 12:39:06.666735 00880000 ################################################################
9867 12:39:06.666901
9868 12:39:06.922518 00900000 ################################################################
9869 12:39:06.922688
9870 12:39:07.180407 00980000 ################################################################
9871 12:39:07.180544
9872 12:39:07.437371 00a00000 ################################################################
9873 12:39:07.437509
9874 12:39:07.687576 00a80000 ################################################################
9875 12:39:07.687733
9876 12:39:07.939251 00b00000 ################################################################
9877 12:39:07.939431
9878 12:39:08.194562 00b80000 ################################################################
9879 12:39:08.194729
9880 12:39:08.447389 00c00000 ################################################################
9881 12:39:08.447564
9882 12:39:08.706169 00c80000 ################################################################
9883 12:39:08.706307
9884 12:39:08.959650 00d00000 ################################################################
9885 12:39:08.959777
9886 12:39:09.216771 00d80000 ################################################################
9887 12:39:09.216900
9888 12:39:09.474609 00e00000 ################################################################
9889 12:39:09.474747
9890 12:39:09.750702 00e80000 ################################################################
9891 12:39:09.750829
9892 12:39:10.011581 00f00000 ################################################################
9893 12:39:10.011712
9894 12:39:10.276931 00f80000 ################################################################
9895 12:39:10.277077
9896 12:39:10.532841 01000000 ################################################################
9897 12:39:10.532979
9898 12:39:10.798587 01080000 ################################################################
9899 12:39:10.798741
9900 12:39:11.059350 01100000 ################################################################
9901 12:39:11.059482
9902 12:39:11.319491 01180000 ################################################################
9903 12:39:11.319632
9904 12:39:11.575091 01200000 ################################################################
9905 12:39:11.575234
9906 12:39:11.834942 01280000 ################################################################
9907 12:39:11.835085
9908 12:39:12.098840 01300000 ################################################################
9909 12:39:12.098973
9910 12:39:12.359943 01380000 ################################################################
9911 12:39:12.360086
9912 12:39:12.623023 01400000 ################################################################
9913 12:39:12.623159
9914 12:39:12.887100 01480000 ################################################################
9915 12:39:12.887227
9916 12:39:13.146086 01500000 ################################################################
9917 12:39:13.146218
9918 12:39:13.407421 01580000 ################################################################
9919 12:39:13.407556
9920 12:39:13.664837 01600000 ################################################################
9921 12:39:13.664974
9922 12:39:13.927689 01680000 ################################################################
9923 12:39:13.927823
9924 12:39:14.196538 01700000 ################################################################
9925 12:39:14.196674
9926 12:39:14.455967 01780000 ################################################################
9927 12:39:14.456105
9928 12:39:14.711217 01800000 ################################################################
9929 12:39:14.711357
9930 12:39:14.961030 01880000 ################################################################
9931 12:39:14.961219
9932 12:39:15.207402 01900000 ################################################################
9933 12:39:15.207557
9934 12:39:15.458706 01980000 ################################################################
9935 12:39:15.458851
9936 12:39:15.708865 01a00000 ################################################################
9937 12:39:15.709040
9938 12:39:15.957875 01a80000 ################################################################
9939 12:39:15.958025
9940 12:39:16.205587 01b00000 ################################################################
9941 12:39:16.205735
9942 12:39:16.461783 01b80000 ################################################################
9943 12:39:16.461947
9944 12:39:16.712897 01c00000 ################################################################
9945 12:39:16.713061
9946 12:39:16.722118 01c80000 ### done.
9947 12:39:16.722231
9948 12:39:16.724588 The bootfile was 29903934 bytes long.
9949 12:39:16.724698
9950 12:39:16.727969 Sending tftp read request... done.
9951 12:39:16.728083
9952 12:39:16.731718 Waiting for the transfer...
9953 12:39:16.731810
9954 12:39:16.731903 00000000 # done.
9955 12:39:16.732007
9956 12:39:16.740597 Command line loaded dynamically from TFTP file: 12703510/tftp-deploy-mt650d1d/kernel/cmdline
9957 12:39:16.740714
9958 12:39:16.760610 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12703510/extract-nfsrootfs-kw_0knxi,tcp,hard ip=dhcp tftpserverip=192.168.201.1
9959 12:39:16.760737
9960 12:39:16.764495 Loading FIT.
9961 12:39:16.764601
9962 12:39:16.767728 Image ramdisk-1 has 17801764 bytes.
9963 12:39:16.767830
9964 12:39:16.770421 Image fdt-1 has 47278 bytes.
9965 12:39:16.770527
9966 12:39:16.770632 Image kernel-1 has 12052857 bytes.
9967 12:39:16.770731
9968 12:39:16.780929 Compat preference: google,spherion-rev12-sku1 google,spherion-rev12 google,spherion-sku1 google,spherion
9969 12:39:16.781038
9970 12:39:16.800625 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion (match) mediatek,mt8192
9971 12:39:16.800742
9972 12:39:16.803431 Choosing best match conf-1 for compat google,spherion.
9973 12:39:16.807535
9974 12:39:16.812058 Connected to device vid:did:rid of 1ae0:0028:00
9975 12:39:16.819083
9976 12:39:16.822727 tpm_get_response: command 0x17b, return code 0x0
9977 12:39:16.822835
9978 12:39:16.825743 ec_init: CrosEC protocol v3 supported (256, 248)
9979 12:39:16.829869
9980 12:39:16.833406 tpm_cleanup: add release locality here.
9981 12:39:16.833516
9982 12:39:16.833610 Shutting down all USB controllers.
9983 12:39:16.836818
9984 12:39:16.836924 Removing current net device
9985 12:39:16.837023
9986 12:39:16.843229 Exiting depthcharge with code 4 at timestamp: 47906513
9987 12:39:16.843368
9988 12:39:16.846444 LZMA decompressing kernel-1 to 0x821a6718
9989 12:39:16.846544
9990 12:39:16.849574 LZMA decompressing kernel-1 to 0x40000000
9991 12:39:18.350347
9992 12:39:18.351005 jumping to kernel
9993 12:39:18.352978 end: 2.2.4 bootloader-commands (duration 00:00:21) [common]
9994 12:39:18.353520 start: 2.2.5 auto-login-action (timeout 00:04:05) [common]
9995 12:39:18.353930 Setting prompt string to ['Linux version [0-9]']
9996 12:39:18.354280 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9997 12:39:18.354792 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
9998 12:39:18.400836
9999 12:39:18.403912 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10000 12:39:18.407954 start: 2.2.5.1 login-action (timeout 00:04:05) [common]
10001 12:39:18.408415 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10002 12:39:18.408809 Setting prompt string to []
10003 12:39:18.409190 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10004 12:39:18.409566 Using line separator: #'\n'#
10005 12:39:18.409867 No login prompt set.
10006 12:39:18.410180 Parsing kernel messages
10007 12:39:18.410462 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10008 12:39:18.410973 [login-action] Waiting for messages, (timeout 00:04:05)
10009 12:39:18.411298 Waiting using forced prompt support (timeout 00:02:03)
10010 12:39:18.427119 [ 0.000000] Linux version 6.1.75-cip14 (KernelCI@build-j98433-arm64-gcc-10-defconfig-arm64-chromebook-89n64) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Feb 5 12:20:06 UTC 2024
10011 12:39:18.430181 [ 0.000000] random: crng init done
10012 12:39:18.437734 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10013 12:39:18.440569 [ 0.000000] efi: UEFI not found.
10014 12:39:18.446796 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10015 12:39:18.453759 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10016 12:39:18.463721 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10017 12:39:18.473356 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10018 12:39:18.480038 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10019 12:39:18.486133 [ 0.000000] printk: bootconsole [mtk8250] enabled
10020 12:39:18.493143 [ 0.000000] NUMA: No NUMA configuration found
10021 12:39:18.499394 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10022 12:39:18.503033 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d4a00-0x13f7d6fff]
10023 12:39:18.506278 [ 0.000000] Zone ranges:
10024 12:39:18.513473 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10025 12:39:18.516582 [ 0.000000] DMA32 empty
10026 12:39:18.522647 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10027 12:39:18.525811 [ 0.000000] Movable zone start for each node
10028 12:39:18.530073 [ 0.000000] Early memory node ranges
10029 12:39:18.536054 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10030 12:39:18.542561 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10031 12:39:18.549530 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10032 12:39:18.555565 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10033 12:39:18.562302 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10034 12:39:18.569542 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10035 12:39:18.599690 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10036 12:39:18.605736 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10037 12:39:18.612778 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10038 12:39:18.615852 [ 0.000000] psci: probing for conduit method from DT.
10039 12:39:18.622344 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10040 12:39:18.626034 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10041 12:39:18.632815 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10042 12:39:18.636046 [ 0.000000] psci: SMC Calling Convention v1.2
10043 12:39:18.642233 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10044 12:39:18.645774 [ 0.000000] Detected VIPT I-cache on CPU0
10045 12:39:18.652345 [ 0.000000] CPU features: detected: GIC system register CPU interface
10046 12:39:18.659021 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10047 12:39:18.665673 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10048 12:39:18.671844 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10049 12:39:18.682123 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10050 12:39:18.688749 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10051 12:39:18.692167 [ 0.000000] alternatives: applying boot alternatives
10052 12:39:18.698521 [ 0.000000] Fallback order for Node 0: 0
10053 12:39:18.705534 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10054 12:39:18.709020 [ 0.000000] Policy zone: Normal
10055 12:39:18.731717 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12703510/extract-nfsrootfs-kw_0knxi,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10056 12:39:18.743626 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10057 12:39:18.751469 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10058 12:39:18.758613 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10059 12:39:18.764688 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10060 12:39:18.771649 <6>[ 0.000000] software IO TLB: area num 8.
10061 12:39:18.827152 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10062 12:39:18.907286 <6>[ 0.000000] Memory: 3835456K/4191232K available (17984K kernel code, 4118K rwdata, 19612K rodata, 8448K init, 616K bss, 323008K reserved, 32768K cma-reserved)
10063 12:39:18.914480 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10064 12:39:18.920770 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10065 12:39:18.923738 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10066 12:39:18.930706 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10067 12:39:18.937081 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10068 12:39:18.940898 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10069 12:39:18.950461 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10070 12:39:18.956590 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10071 12:39:18.963399 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10072 12:39:18.970026 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10073 12:39:18.973563 <6>[ 0.000000] GICv3: 608 SPIs implemented
10074 12:39:18.976754 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10075 12:39:18.983161 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10076 12:39:18.986735 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10077 12:39:18.993157 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10078 12:39:19.005835 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10079 12:39:19.018964 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10080 12:39:19.025582 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10081 12:39:19.033853 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10082 12:39:19.047189 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10083 12:39:19.054250 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10084 12:39:19.060065 <6>[ 0.009179] Console: colour dummy device 80x25
10085 12:39:19.070437 <6>[ 0.013905] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10086 12:39:19.077992 <6>[ 0.024347] pid_max: default: 32768 minimum: 301
10087 12:39:19.081263 <6>[ 0.029248] LSM: Security Framework initializing
10088 12:39:19.087449 <6>[ 0.034163] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10089 12:39:19.096794 <6>[ 0.041769] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10090 12:39:19.103367 <6>[ 0.051052] cblist_init_generic: Setting adjustable number of callback queues.
10091 12:39:19.109617 <6>[ 0.058495] cblist_init_generic: Setting shift to 3 and lim to 1.
10092 12:39:19.119420 <6>[ 0.064833] cblist_init_generic: Setting adjustable number of callback queues.
10093 12:39:19.125682 <6>[ 0.072260] cblist_init_generic: Setting shift to 3 and lim to 1.
10094 12:39:19.129668 <6>[ 0.078661] rcu: Hierarchical SRCU implementation.
10095 12:39:19.135953 <6>[ 0.083707] rcu: Max phase no-delay instances is 1000.
10096 12:39:19.142424 <6>[ 0.090731] EFI services will not be available.
10097 12:39:19.145839 <6>[ 0.095714] smp: Bringing up secondary CPUs ...
10098 12:39:19.154481 <6>[ 0.100767] Detected VIPT I-cache on CPU1
10099 12:39:19.160645 <6>[ 0.100836] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10100 12:39:19.167037 <6>[ 0.100867] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10101 12:39:19.171359 <6>[ 0.101205] Detected VIPT I-cache on CPU2
10102 12:39:19.177633 <6>[ 0.101257] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10103 12:39:19.183828 <6>[ 0.101275] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10104 12:39:19.190478 <6>[ 0.101535] Detected VIPT I-cache on CPU3
10105 12:39:19.197310 <6>[ 0.101582] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10106 12:39:19.203404 <6>[ 0.101596] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10107 12:39:19.206962 <6>[ 0.101900] CPU features: detected: Spectre-v4
10108 12:39:19.213161 <6>[ 0.101906] CPU features: detected: Spectre-BHB
10109 12:39:19.216545 <6>[ 0.101912] Detected PIPT I-cache on CPU4
10110 12:39:19.223050 <6>[ 0.101968] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10111 12:39:19.230087 <6>[ 0.101985] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10112 12:39:19.236395 <6>[ 0.102274] Detected PIPT I-cache on CPU5
10113 12:39:19.243523 <6>[ 0.102335] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10114 12:39:19.249604 <6>[ 0.102352] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10115 12:39:19.253082 <6>[ 0.102630] Detected PIPT I-cache on CPU6
10116 12:39:19.259622 <6>[ 0.102690] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10117 12:39:19.266392 <6>[ 0.102706] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10118 12:39:19.273033 <6>[ 0.103009] Detected PIPT I-cache on CPU7
10119 12:39:19.279664 <6>[ 0.103073] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10120 12:39:19.285717 <6>[ 0.103090] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10121 12:39:19.289082 <6>[ 0.103137] smp: Brought up 1 node, 8 CPUs
10122 12:39:19.296382 <6>[ 0.244510] SMP: Total of 8 processors activated.
10123 12:39:19.299117 <6>[ 0.249431] CPU features: detected: 32-bit EL0 Support
10124 12:39:19.309303 <6>[ 0.254793] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10125 12:39:19.315485 <6>[ 0.263647] CPU features: detected: Common not Private translations
10126 12:39:19.322676 <6>[ 0.270162] CPU features: detected: CRC32 instructions
10127 12:39:19.325984 <6>[ 0.275547] CPU features: detected: RCpc load-acquire (LDAPR)
10128 12:39:19.332380 <6>[ 0.281507] CPU features: detected: LSE atomic instructions
10129 12:39:19.339384 <6>[ 0.287288] CPU features: detected: Privileged Access Never
10130 12:39:19.345514 <6>[ 0.293067] CPU features: detected: RAS Extension Support
10131 12:39:19.353035 <6>[ 0.298676] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10132 12:39:19.355172 <6>[ 0.305893] CPU: All CPU(s) started at EL2
10133 12:39:19.362071 <6>[ 0.310210] alternatives: applying system-wide alternatives
10134 12:39:19.370868 <6>[ 0.320165] devtmpfs: initialized
10135 12:39:19.386464 <6>[ 0.328420] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10136 12:39:19.393140 <6>[ 0.338379] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10137 12:39:19.398783 <6>[ 0.346595] pinctrl core: initialized pinctrl subsystem
10138 12:39:19.402848 <6>[ 0.353243] DMI not present or invalid.
10139 12:39:19.409004 <6>[ 0.357645] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10140 12:39:19.419310 <6>[ 0.364505] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10141 12:39:19.425797 <6>[ 0.371954] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10142 12:39:19.434816 <6>[ 0.380048] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10143 12:39:19.438676 <6>[ 0.388207] audit: initializing netlink subsys (disabled)
10144 12:39:19.448978 <5>[ 0.393902] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10145 12:39:19.454525 <6>[ 0.394599] thermal_sys: Registered thermal governor 'step_wise'
10146 12:39:19.461203 <6>[ 0.401871] thermal_sys: Registered thermal governor 'power_allocator'
10147 12:39:19.464719 <6>[ 0.408125] cpuidle: using governor menu
10148 12:39:19.471417 <6>[ 0.419090] NET: Registered PF_QIPCRTR protocol family
10149 12:39:19.478030 <6>[ 0.424568] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10150 12:39:19.484635 <6>[ 0.431666] ASID allocator initialised with 32768 entries
10151 12:39:19.487770 <6>[ 0.438216] Serial: AMBA PL011 UART driver
10152 12:39:19.497749 <4>[ 0.446931] Trying to register duplicate clock ID: 134
10153 12:39:19.554076 <6>[ 0.506514] KASLR enabled
10154 12:39:19.569226 <6>[ 0.514239] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10155 12:39:19.575498 <6>[ 0.521253] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10156 12:39:19.582213 <6>[ 0.527742] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10157 12:39:19.589499 <6>[ 0.534745] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10158 12:39:19.595498 <6>[ 0.541231] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10159 12:39:19.601783 <6>[ 0.548234] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10160 12:39:19.608620 <6>[ 0.554723] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10161 12:39:19.615628 <6>[ 0.561727] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10162 12:39:19.618851 <6>[ 0.569241] ACPI: Interpreter disabled.
10163 12:39:19.626988 <6>[ 0.575653] iommu: Default domain type: Translated
10164 12:39:19.633116 <6>[ 0.580765] iommu: DMA domain TLB invalidation policy: strict mode
10165 12:39:19.636584 <5>[ 0.587427] SCSI subsystem initialized
10166 12:39:19.643308 <6>[ 0.591588] usbcore: registered new interface driver usbfs
10167 12:39:19.649945 <6>[ 0.597321] usbcore: registered new interface driver hub
10168 12:39:19.653019 <6>[ 0.602874] usbcore: registered new device driver usb
10169 12:39:19.660118 <6>[ 0.608975] pps_core: LinuxPPS API ver. 1 registered
10170 12:39:19.669842 <6>[ 0.614170] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10171 12:39:19.673412 <6>[ 0.623521] PTP clock support registered
10172 12:39:19.676994 <6>[ 0.627762] EDAC MC: Ver: 3.0.0
10173 12:39:19.684880 <6>[ 0.632921] FPGA manager framework
10174 12:39:19.687249 <6>[ 0.636602] Advanced Linux Sound Architecture Driver Initialized.
10175 12:39:19.691739 <6>[ 0.643385] vgaarb: loaded
10176 12:39:19.698071 <6>[ 0.646538] clocksource: Switched to clocksource arch_sys_counter
10177 12:39:19.704414 <5>[ 0.652974] VFS: Disk quotas dquot_6.6.0
10178 12:39:19.711875 <6>[ 0.657160] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10179 12:39:19.714600 <6>[ 0.664351] pnp: PnP ACPI: disabled
10180 12:39:19.722857 <6>[ 0.671006] NET: Registered PF_INET protocol family
10181 12:39:19.728897 <6>[ 0.676387] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10182 12:39:19.740819 <6>[ 0.686402] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10183 12:39:19.750411 <6>[ 0.695192] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10184 12:39:19.757275 <6>[ 0.703156] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10185 12:39:19.763851 <6>[ 0.711557] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10186 12:39:19.774388 <6>[ 0.720210] TCP: Hash tables configured (established 32768 bind 32768)
10187 12:39:19.781303 <6>[ 0.727070] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10188 12:39:19.787972 <6>[ 0.734092] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10189 12:39:19.794221 <6>[ 0.741610] NET: Registered PF_UNIX/PF_LOCAL protocol family
10190 12:39:19.801177 <6>[ 0.747758] RPC: Registered named UNIX socket transport module.
10191 12:39:19.804394 <6>[ 0.753911] RPC: Registered udp transport module.
10192 12:39:19.810757 <6>[ 0.758845] RPC: Registered tcp transport module.
10193 12:39:19.819394 <6>[ 0.763776] RPC: Registered tcp NFSv4.1 backchannel transport module.
10194 12:39:19.821037 <6>[ 0.770442] PCI: CLS 0 bytes, default 64
10195 12:39:19.823847 <6>[ 0.774779] Unpacking initramfs...
10196 12:39:19.849012 <6>[ 0.794625] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10197 12:39:19.859107 <6>[ 0.803266] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10198 12:39:19.862842 <6>[ 0.812029] kvm [1]: IPA Size Limit: 40 bits
10199 12:39:19.868636 <6>[ 0.816554] kvm [1]: GICv3: no GICV resource entry
10200 12:39:19.872452 <6>[ 0.821577] kvm [1]: disabling GICv2 emulation
10201 12:39:19.878540 <6>[ 0.826263] kvm [1]: GIC system register CPU interface enabled
10202 12:39:19.881918 <6>[ 0.832424] kvm [1]: vgic interrupt IRQ18
10203 12:39:19.888898 <6>[ 0.836775] kvm [1]: VHE mode initialized successfully
10204 12:39:19.895997 <5>[ 0.843203] Initialise system trusted keyrings
10205 12:39:19.902045 <6>[ 0.848003] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10206 12:39:19.909342 <6>[ 0.858024] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10207 12:39:19.915822 <5>[ 0.864481] NFS: Registering the id_resolver key type
10208 12:39:19.919733 <5>[ 0.869792] Key type id_resolver registered
10209 12:39:19.925570 <5>[ 0.874208] Key type id_legacy registered
10210 12:39:19.933029 <6>[ 0.878485] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10211 12:39:19.938922 <6>[ 0.885408] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10212 12:39:19.945413 <6>[ 0.893159] 9p: Installing v9fs 9p2000 file system support
10213 12:39:19.983133 <5>[ 0.931605] Key type asymmetric registered
10214 12:39:19.987088 <5>[ 0.935935] Asymmetric key parser 'x509' registered
10215 12:39:19.996186 <6>[ 0.941080] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10216 12:39:19.999059 <6>[ 0.948700] io scheduler mq-deadline registered
10217 12:39:20.003016 <6>[ 0.953482] io scheduler kyber registered
10218 12:39:20.022223 <6>[ 0.970568] EINJ: ACPI disabled.
10219 12:39:20.053814 <4>[ 0.995733] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10220 12:39:20.063414 <4>[ 1.006349] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10221 12:39:20.078710 <6>[ 1.027396] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10222 12:39:20.087019 <6>[ 1.035475] printk: console [ttyS0] disabled
10223 12:39:20.115072 <6>[ 1.060103] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10224 12:39:20.121071 <6>[ 1.069578] printk: console [ttyS0] enabled
10225 12:39:20.124491 <6>[ 1.069578] printk: console [ttyS0] enabled
10226 12:39:20.131316 <6>[ 1.078475] printk: bootconsole [mtk8250] disabled
10227 12:39:20.134868 <6>[ 1.078475] printk: bootconsole [mtk8250] disabled
10228 12:39:20.141240 <6>[ 1.089691] SuperH (H)SCI(F) driver initialized
10229 12:39:20.144435 <6>[ 1.094983] msm_serial: driver initialized
10230 12:39:20.158617 <6>[ 1.104001] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10231 12:39:20.168213 <6>[ 1.112548] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10232 12:39:20.175395 <6>[ 1.121092] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10233 12:39:20.185103 <6>[ 1.129721] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10234 12:39:20.194702 <6>[ 1.138427] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10235 12:39:20.201557 <6>[ 1.147148] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10236 12:39:20.211823 <6>[ 1.155690] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10237 12:39:20.218170 <6>[ 1.164495] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10238 12:39:20.228076 <6>[ 1.173038] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10239 12:39:20.239934 <6>[ 1.188583] loop: module loaded
10240 12:39:20.246625 <6>[ 1.194625] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10241 12:39:20.269412 <4>[ 1.218291] mtk-pmic-keys: Failed to locate of_node [id: -1]
10242 12:39:20.276476 <6>[ 1.225387] megasas: 07.719.03.00-rc1
10243 12:39:20.287172 <6>[ 1.235217] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10244 12:39:20.293002 <6>[ 1.241938] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10245 12:39:20.310254 <6>[ 1.258645] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10246 12:39:20.366178 <6>[ 1.308656] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10247 12:39:20.570502 <6>[ 1.519855] Freeing initrd memory: 17380K
10248 12:39:20.581098 <6>[ 1.530212] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10249 12:39:20.592613 <6>[ 1.541260] tun: Universal TUN/TAP device driver, 1.6
10250 12:39:20.595254 <6>[ 1.547338] thunder_xcv, ver 1.0
10251 12:39:20.598641 <6>[ 1.550845] thunder_bgx, ver 1.0
10252 12:39:20.601770 <6>[ 1.554335] nicpf, ver 1.0
10253 12:39:20.612081 <6>[ 1.558366] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10254 12:39:20.615915 <6>[ 1.565842] hns3: Copyright (c) 2017 Huawei Corporation.
10255 12:39:20.619353 <6>[ 1.571430] hclge is initializing
10256 12:39:20.625732 <6>[ 1.575010] e1000: Intel(R) PRO/1000 Network Driver
10257 12:39:20.633514 <6>[ 1.580139] e1000: Copyright (c) 1999-2006 Intel Corporation.
10258 12:39:20.635773 <6>[ 1.586156] e1000e: Intel(R) PRO/1000 Network Driver
10259 12:39:20.642437 <6>[ 1.591372] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10260 12:39:20.650525 <6>[ 1.597558] igb: Intel(R) Gigabit Ethernet Network Driver
10261 12:39:20.655764 <6>[ 1.603207] igb: Copyright (c) 2007-2014 Intel Corporation.
10262 12:39:20.662597 <6>[ 1.609044] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10263 12:39:20.669681 <6>[ 1.615562] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10264 12:39:20.672600 <6>[ 1.622028] sky2: driver version 1.30
10265 12:39:20.678682 <6>[ 1.627027] VFIO - User Level meta-driver version: 0.3
10266 12:39:20.686242 <6>[ 1.635291] usbcore: registered new interface driver usb-storage
10267 12:39:20.692913 <6>[ 1.641737] usbcore: registered new device driver onboard-usb-hub
10268 12:39:20.702139 <6>[ 1.650949] mt6397-rtc mt6359-rtc: registered as rtc0
10269 12:39:20.711890 <6>[ 1.656414] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-05T12:39:24 UTC (1707136764)
10270 12:39:20.715240 <6>[ 1.665981] i2c_dev: i2c /dev entries driver
10271 12:39:20.732165 <6>[ 1.677736] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10272 12:39:20.751801 <6>[ 1.700709] cpu cpu0: EM: created perf domain
10273 12:39:20.754796 <6>[ 1.705601] cpu cpu4: EM: created perf domain
10274 12:39:20.762180 <6>[ 1.711153] sdhci: Secure Digital Host Controller Interface driver
10275 12:39:20.769011 <6>[ 1.717585] sdhci: Copyright(c) Pierre Ossman
10276 12:39:20.775330 <6>[ 1.722483] Synopsys Designware Multimedia Card Interface Driver
10277 12:39:20.782377 <6>[ 1.729069] sdhci-pltfm: SDHCI platform and OF driver helper
10278 12:39:20.785840 <6>[ 1.729118] mmc0: CQHCI version 5.10
10279 12:39:20.792550 <6>[ 1.739288] ledtrig-cpu: registered to indicate activity on CPUs
10280 12:39:20.798498 <6>[ 1.746302] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10281 12:39:20.805401 <6>[ 1.753343] usbcore: registered new interface driver usbhid
10282 12:39:20.808547 <6>[ 1.759165] usbhid: USB HID core driver
10283 12:39:20.815386 <6>[ 1.763366] spi_master spi0: will run message pump with realtime priority
10284 12:39:20.856597 <6>[ 1.798691] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10285 12:39:20.875292 <6>[ 1.813677] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10286 12:39:20.882240 <6>[ 1.828352] cros-ec-spi spi0.0: Chrome EC device registered
10287 12:39:20.885349 <6>[ 1.834359] mmc0: Command Queue Engine enabled
10288 12:39:20.892220 <6>[ 1.839119] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10289 12:39:20.898616 <6>[ 1.846814] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10290 12:39:20.908023 <6>[ 1.857142] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10291 12:39:20.914908 <6>[ 1.864374] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10292 12:39:20.925424 <6>[ 1.867192] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10293 12:39:20.928338 <6>[ 1.870271] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10294 12:39:20.934956 <6>[ 1.879817] NET: Registered PF_PACKET protocol family
10295 12:39:20.942675 <6>[ 1.884766] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10296 12:39:20.944592 <6>[ 1.889505] 9pnet: Installing 9P2000 support
10297 12:39:20.951453 <5>[ 1.900499] Key type dns_resolver registered
10298 12:39:20.955280 <6>[ 1.905449] registered taskstats version 1
10299 12:39:20.961136 <5>[ 1.909831] Loading compiled-in X.509 certificates
10300 12:39:20.990530 <4>[ 1.931846] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10301 12:39:20.999598 <4>[ 1.942596] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10302 12:39:21.005999 <3>[ 1.953129] debugfs: File 'uA_load' in directory '/' already present!
10303 12:39:21.012788 <3>[ 1.959869] debugfs: File 'min_uV' in directory '/' already present!
10304 12:39:21.019562 <3>[ 1.966483] debugfs: File 'max_uV' in directory '/' already present!
10305 12:39:21.025961 <3>[ 1.973091] debugfs: File 'constraint_flags' in directory '/' already present!
10306 12:39:21.037521 <3>[ 1.982768] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10307 12:39:21.046451 <6>[ 1.995267] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10308 12:39:21.052825 <6>[ 2.001884] xhci-mtk 11200000.usb: xHCI Host Controller
10309 12:39:21.059239 <6>[ 2.007376] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10310 12:39:21.069705 <6>[ 2.015233] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10311 12:39:21.076569 <6>[ 2.024649] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10312 12:39:21.082966 <6>[ 2.030712] xhci-mtk 11200000.usb: xHCI Host Controller
10313 12:39:21.090945 <6>[ 2.036186] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10314 12:39:21.097199 <6>[ 2.043829] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10315 12:39:21.102824 <6>[ 2.051414] hub 1-0:1.0: USB hub found
10316 12:39:21.105971 <6>[ 2.055419] hub 1-0:1.0: 1 port detected
10317 12:39:21.113568 <6>[ 2.059679] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10318 12:39:21.119965 <6>[ 2.068189] hub 2-0:1.0: USB hub found
10319 12:39:21.122734 <6>[ 2.072192] hub 2-0:1.0: 1 port detected
10320 12:39:21.130823 <6>[ 2.079607] mtk-msdc 11f70000.mmc: Got CD GPIO
10321 12:39:21.144684 <6>[ 2.087860] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10322 12:39:21.148661 <6>[ 2.095879] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10323 12:39:21.158763 <4>[ 2.103768] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10324 12:39:21.169874 <6>[ 2.113290] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10325 12:39:21.175522 <6>[ 2.121369] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10326 12:39:21.182277 <6>[ 2.129495] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10327 12:39:21.192201 <6>[ 2.137433] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10328 12:39:21.198979 <6>[ 2.145250] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10329 12:39:21.208637 <6>[ 2.153067] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10330 12:39:21.218740 <6>[ 2.163542] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10331 12:39:21.225512 <6>[ 2.171926] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10332 12:39:21.235063 <6>[ 2.180266] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10333 12:39:21.241554 <6>[ 2.188604] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10334 12:39:21.252283 <6>[ 2.196942] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10335 12:39:21.257886 <6>[ 2.205281] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10336 12:39:21.268378 <6>[ 2.213620] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10337 12:39:21.277668 <6>[ 2.221958] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10338 12:39:21.284874 <6>[ 2.230298] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10339 12:39:21.294834 <6>[ 2.238635] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10340 12:39:21.301112 <6>[ 2.246974] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10341 12:39:21.310919 <6>[ 2.255323] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10342 12:39:21.317795 <6>[ 2.263664] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10343 12:39:21.328444 <6>[ 2.272001] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10344 12:39:21.333985 <6>[ 2.280347] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10345 12:39:21.340981 <6>[ 2.289065] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10346 12:39:21.347062 <6>[ 2.296186] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10347 12:39:21.353917 <6>[ 2.302929] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10348 12:39:21.364006 <6>[ 2.309664] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10349 12:39:21.370855 <6>[ 2.316573] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10350 12:39:21.377514 <6>[ 2.323412] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10351 12:39:21.386824 <6>[ 2.332539] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10352 12:39:21.396739 <6>[ 2.341659] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10353 12:39:21.406809 <6>[ 2.350952] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10354 12:39:21.416641 <6>[ 2.360418] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10355 12:39:21.423379 <6>[ 2.369885] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10356 12:39:21.433284 <6>[ 2.379004] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10357 12:39:21.443296 <6>[ 2.388468] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10358 12:39:21.453140 <6>[ 2.397586] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10359 12:39:21.462769 <6>[ 2.406879] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10360 12:39:21.473252 <6>[ 2.417039] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10361 12:39:21.483243 <6>[ 2.428975] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10362 12:39:21.489641 <6>[ 2.438053] Trying to probe devices needed for running init ...
10363 12:39:21.513490 <6>[ 2.459054] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10364 12:39:21.541168 <6>[ 2.490341] hub 2-1:1.0: USB hub found
10365 12:39:21.544886 <6>[ 2.494804] hub 2-1:1.0: 3 ports detected
10366 12:39:21.553438 <6>[ 2.502201] hub 2-1:1.0: USB hub found
10367 12:39:21.556054 <6>[ 2.506532] hub 2-1:1.0: 3 ports detected
10368 12:39:21.664571 <6>[ 2.610807] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10369 12:39:21.819307 <6>[ 2.768890] hub 1-1:1.0: USB hub found
10370 12:39:21.822989 <6>[ 2.773378] hub 1-1:1.0: 4 ports detected
10371 12:39:21.833551 <6>[ 2.782308] hub 1-1:1.0: USB hub found
10372 12:39:21.836041 <6>[ 2.786910] hub 1-1:1.0: 4 ports detected
10373 12:39:21.904702 <6>[ 2.851062] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10374 12:39:22.156678 <6>[ 3.102850] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10375 12:39:22.289289 <6>[ 3.238615] hub 1-1.4:1.0: USB hub found
10376 12:39:22.292348 <6>[ 3.243281] hub 1-1.4:1.0: 2 ports detected
10377 12:39:22.301854 <6>[ 3.251385] hub 1-1.4:1.0: USB hub found
10378 12:39:22.305189 <6>[ 3.256074] hub 1-1.4:1.0: 2 ports detected
10379 12:39:22.600786 <6>[ 3.546819] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10380 12:39:22.793116 <6>[ 3.738820] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10381 12:39:33.781987 <6>[ 14.735797] ALSA device list:
10382 12:39:33.788501 <6>[ 14.739095] No soundcards found.
10383 12:39:33.797347 <6>[ 14.746914] Freeing unused kernel memory: 8448K
10384 12:39:33.800053 <6>[ 14.751900] Run /init as init process
10385 12:39:33.811332 Loading, please wait...
10386 12:39:33.831922 Starting version 247.3-7+deb11u2
10387 12:39:34.023456 <3>[ 14.970308] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10388 12:39:34.033314 <3>[ 14.979093] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10389 12:39:34.039816 <3>[ 14.987208] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10390 12:39:34.049861 <3>[ 14.996082] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10391 12:39:34.056874 <6>[ 14.997142] usbcore: registered new device driver r8152-cfgselector
10392 12:39:34.063071 <6>[ 14.997456] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10393 12:39:34.072695 <6>[ 14.997506] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10394 12:39:34.080089 <6>[ 14.997512] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10395 12:39:34.089417 <3>[ 15.004383] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10396 12:39:34.092554 <6>[ 15.018760] mc: Linux media interface: v0.10
10397 12:39:34.100112 <3>[ 15.027025] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10398 12:39:34.109826 <3>[ 15.027030] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10399 12:39:34.116088 <4>[ 15.027265] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10400 12:39:34.122380 <4>[ 15.033539] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10401 12:39:34.129630 <6>[ 15.039624] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10402 12:39:34.139371 <3>[ 15.043789] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10403 12:39:34.146206 <3>[ 15.043830] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10404 12:39:34.156055 <4>[ 15.063759] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10405 12:39:34.160096 <4>[ 15.063759] Fallback method does not support PEC.
10406 12:39:34.169703 <3>[ 15.064522] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10407 12:39:34.179061 <3>[ 15.086038] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10408 12:39:34.186173 <3>[ 15.086713] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10409 12:39:34.192689 <3>[ 15.086716] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10410 12:39:34.202210 <3>[ 15.086750] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10411 12:39:34.212153 <3>[ 15.113673] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10412 12:39:34.218936 <6>[ 15.115859] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10413 12:39:34.222151 <6>[ 15.115863] pci_bus 0000:00: root bus resource [bus 00-ff]
10414 12:39:34.232238 <6>[ 15.115867] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10415 12:39:34.242113 <6>[ 15.115869] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10416 12:39:34.245176 <6>[ 15.115896] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10417 12:39:34.255522 <6>[ 15.115909] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10418 12:39:34.258416 <6>[ 15.115978] pci 0000:00:00.0: supports D1 D2
10419 12:39:34.264979 <6>[ 15.115980] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10420 12:39:34.276462 <3>[ 15.116522] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10421 12:39:34.281620 <6>[ 15.116867] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10422 12:39:34.288030 <6>[ 15.116935] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10423 12:39:34.295090 <6>[ 15.116960] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10424 12:39:34.301237 <6>[ 15.116975] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10425 12:39:34.311378 <6>[ 15.116990] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10426 12:39:34.315152 <6>[ 15.117094] pci 0000:01:00.0: supports D1 D2
10427 12:39:34.322081 <6>[ 15.117096] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10428 12:39:34.331683 <6>[ 15.118965] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10429 12:39:34.337991 <6>[ 15.130720] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10430 12:39:34.344118 <3>[ 15.133367] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10431 12:39:34.354111 <6>[ 15.139456] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10432 12:39:34.363808 <6>[ 15.140052] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10433 12:39:34.374899 <6>[ 15.141249] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10434 12:39:34.380380 <6>[ 15.141474] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10435 12:39:34.391827 <3>[ 15.149521] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10436 12:39:34.397376 <6>[ 15.150517] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10437 12:39:34.407278 <4>[ 15.151011] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10438 12:39:34.414307 <4>[ 15.151020] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10439 12:39:34.421104 <6>[ 15.152758] remoteproc remoteproc0: scp is available
10440 12:39:34.423681 <6>[ 15.152801] remoteproc remoteproc0: powering up scp
10441 12:39:34.434165 <6>[ 15.152803] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10442 12:39:34.440556 <6>[ 15.152818] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10443 12:39:34.446519 <6>[ 15.157598] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10444 12:39:34.453120 <3>[ 15.166376] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10445 12:39:34.463157 <3>[ 15.166402] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10446 12:39:34.470054 <6>[ 15.172258] videodev: Linux video capture interface: v2.00
10447 12:39:34.478499 <6>[ 15.173281] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10448 12:39:34.480042 <6>[ 15.187814] Bluetooth: Core ver 2.22
10449 12:39:34.489809 <6>[ 15.196180] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10450 12:39:34.492974 <6>[ 15.202961] r8152 2-1.3:1.0 eth0: v1.12.13
10451 12:39:34.499670 <6>[ 15.203026] NET: Registered PF_BLUETOOTH protocol family
10452 12:39:34.506878 <6>[ 15.203032] Bluetooth: HCI device and connection manager initialized
10453 12:39:34.509877 <6>[ 15.203052] Bluetooth: HCI socket layer initialized
10454 12:39:34.516210 <6>[ 15.203059] Bluetooth: L2CAP socket layer initialized
10455 12:39:34.519878 <6>[ 15.203075] Bluetooth: SCO socket layer initialized
10456 12:39:34.529706 <6>[ 15.209816] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10457 12:39:34.532907 <6>[ 15.209832] pci 0000:00:00.0: PCI bridge to [bus 01]
10458 12:39:34.540330 <6>[ 15.214429] usbcore: registered new interface driver r8152
10459 12:39:34.546493 <6>[ 15.221213] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10460 12:39:34.552644 <6>[ 15.221542] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10461 12:39:34.562264 <6>[ 15.238750] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10462 12:39:34.565949 <6>[ 15.244451] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10463 12:39:34.572116 <6>[ 15.251965] usbcore: registered new interface driver cdc_ether
10464 12:39:34.579000 <6>[ 15.259424] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10465 12:39:34.585379 <6>[ 15.259635] usbcore: registered new interface driver btusb
10466 12:39:34.592174 <6>[ 15.259766] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10467 12:39:34.602110 <4>[ 15.266665] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10468 12:39:34.614982 <6>[ 15.267419] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10469 12:39:34.618322 <6>[ 15.267492] usbcore: registered new interface driver uvcvideo
10470 12:39:34.625320 <6>[ 15.271188] usbcore: registered new interface driver r8153_ecm
10471 12:39:34.631886 <3>[ 15.277689] Bluetooth: hci0: Failed to load firmware file (-2)
10472 12:39:34.638114 <3>[ 15.277692] Bluetooth: hci0: Failed to set up firmware (-2)
10473 12:39:34.648353 <4>[ 15.277695] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10474 12:39:34.655361 <5>[ 15.280361] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10475 12:39:34.665353 <6>[ 15.286193] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10476 12:39:34.671440 <6>[ 15.286202] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10477 12:39:34.678049 <6>[ 15.293813] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10478 12:39:34.687792 <6>[ 15.294320] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10479 12:39:34.694821 <6>[ 15.296769] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10480 12:39:34.700702 <6>[ 15.301074] remoteproc remoteproc0: remote processor scp is now up
10481 12:39:34.707685 <5>[ 15.306300] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10482 12:39:34.717247 <5>[ 15.664313] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10483 12:39:34.731112 <4>[ 15.678919] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10484 12:39:34.738040 <6>[ 15.687820] cfg80211: failed to load regulatory.db
10485 12:39:34.773773 <6>[ 15.721511] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10486 12:39:34.780031 <6>[ 15.729007] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10487 12:39:34.805018 <6>[ 15.755567] mt7921e 0000:01:00.0: ASIC revision: 79610010
10488 12:39:34.905636 <6>[ 15.853148] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10489 12:39:34.909974 <6>[ 15.853148]
10490 12:39:34.912595 Begin: Loading essential drivers ... done.
10491 12:39:34.915660 Begin: Running /scripts/init-premount ... done.
10492 12:39:34.922842 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10493 12:39:34.932202 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10494 12:39:34.935667 Device /sys/class/net/enx00e04c6803bd found
10495 12:39:34.936142 done.
10496 12:39:34.984516 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10497 12:39:35.176749 <6>[ 16.123761] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10498 12:39:35.906167 <6>[ 16.856635] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10499 12:39:36.016314 <6>[ 16.967369] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10500 12:39:36.207404 IP-Config: no response after 2 secs - giving up
10501 12:39:36.236105 IP-Config: wlp1s0 hardware address 74:4c:a1:92:35:3b mtu 1500 DHCP
10502 12:39:36.950795 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10503 12:39:36.953877 IP-Config: enx00e04c6803bd complete (dhcp from 192.168.201.1):
10504 12:39:36.963757 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10505 12:39:36.970469 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10506 12:39:36.977376 host : mt8192-asurada-spherion-r0-cbg-4
10507 12:39:36.983851 domain : lava-rack
10508 12:39:36.987268 rootserver: 192.168.201.1 rootpath:
10509 12:39:36.987351 filename :
10510 12:39:37.055263 done.
10511 12:39:37.061807 Begin: Running /scripts/nfs-bottom ... done.
10512 12:39:37.079380 Begin: Running /scripts/init-bottom ... done.
10513 12:39:38.253003 <6>[ 19.204387] NET: Registered PF_INET6 protocol family
10514 12:39:38.260435 <6>[ 19.211548] Segment Routing with IPv6
10515 12:39:38.263785 <6>[ 19.215558] In-situ OAM (IOAM) with IPv6
10516 12:39:38.400786 <30>[ 19.331716] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10517 12:39:38.406227 <30>[ 19.356157] systemd[1]: Detected architecture arm64.
10518 12:39:38.424220
10519 12:39:38.426809 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10520 12:39:38.426886
10521 12:39:38.441034 <30>[ 19.392772] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10522 12:39:39.479681 <30>[ 20.427551] systemd[1]: Queued start job for default target Graphical Interface.
10523 12:39:39.522687 <30>[ 20.473173] systemd[1]: Created slice system-getty.slice.
10524 12:39:39.528841 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10525 12:39:39.545368 <30>[ 20.496260] systemd[1]: Created slice system-modprobe.slice.
10526 12:39:39.551382 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10527 12:39:39.569004 <30>[ 20.520067] systemd[1]: Created slice system-serial\x2dgetty.slice.
10528 12:39:39.579107 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10529 12:39:39.592873 <30>[ 20.543884] systemd[1]: Created slice User and Session Slice.
10530 12:39:39.599881 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10531 12:39:39.620246 <30>[ 20.567557] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10532 12:39:39.629774 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10533 12:39:39.647721 <30>[ 20.595576] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10534 12:39:39.654406 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10535 12:39:39.679020 <30>[ 20.623009] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10536 12:39:39.685856 <30>[ 20.635163] systemd[1]: Reached target Local Encrypted Volumes.
10537 12:39:39.692021 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10538 12:39:39.707861 <30>[ 20.658953] systemd[1]: Reached target Paths.
10539 12:39:39.711397 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10540 12:39:39.728191 <30>[ 20.678815] systemd[1]: Reached target Remote File Systems.
10541 12:39:39.734758 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10542 12:39:39.752018 <30>[ 20.703184] systemd[1]: Reached target Slices.
10543 12:39:39.758827 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10544 12:39:39.772903 <30>[ 20.722851] systemd[1]: Reached target Swap.
10545 12:39:39.774781 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10546 12:39:39.795466 <30>[ 20.743316] systemd[1]: Listening on initctl Compatibility Named Pipe.
10547 12:39:39.802372 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10548 12:39:39.809002 <30>[ 20.759384] systemd[1]: Listening on Journal Audit Socket.
10549 12:39:39.816992 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10550 12:39:39.833553 <30>[ 20.784140] systemd[1]: Listening on Journal Socket (/dev/log).
10551 12:39:39.839939 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10552 12:39:39.856796 <30>[ 20.807380] systemd[1]: Listening on Journal Socket.
10553 12:39:39.863069 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10554 12:39:39.881039 <30>[ 20.828385] systemd[1]: Listening on Network Service Netlink Socket.
10555 12:39:39.886817 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10556 12:39:39.903038 <30>[ 20.853978] systemd[1]: Listening on udev Control Socket.
10557 12:39:39.910326 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10558 12:39:39.924617 <30>[ 20.875264] systemd[1]: Listening on udev Kernel Socket.
10559 12:39:39.930743 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10560 12:39:39.983745 <30>[ 20.934963] systemd[1]: Mounting Huge Pages File System...
10561 12:39:39.990043 Mounting [0;1;39mHuge Pages File System[0m...
10562 12:39:40.007974 <30>[ 20.959114] systemd[1]: Mounting POSIX Message Queue File System...
10563 12:39:40.015111 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10564 12:39:40.035730 <30>[ 20.987040] systemd[1]: Mounting Kernel Debug File System...
10565 12:39:40.042604 Mounting [0;1;39mKernel Debug File System[0m...
10566 12:39:40.059183 <30>[ 21.007242] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10567 12:39:40.085196 <30>[ 21.032392] systemd[1]: Starting Create list of static device nodes for the current kernel...
10568 12:39:40.090935 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10569 12:39:40.110322 <30>[ 21.061706] systemd[1]: Starting Load Kernel Module configfs...
10570 12:39:40.117064 Starting [0;1;39mLoad Kernel Module configfs[0m...
10571 12:39:40.136323 <30>[ 21.087235] systemd[1]: Starting Load Kernel Module drm...
10572 12:39:40.142632 Starting [0;1;39mLoad Kernel Module drm[0m...
10573 12:39:40.160472 <30>[ 21.111630] systemd[1]: Starting Load Kernel Module fuse...
10574 12:39:40.166901 Starting [0;1;39mLoad Kernel Module fuse[0m...
10575 12:39:40.198191 <6>[ 21.149043] fuse: init (API version 7.37)
10576 12:39:40.207838 <30>[ 21.149899] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10577 12:39:40.248922 <30>[ 21.199424] systemd[1]: Starting Journal Service...
10578 12:39:40.251671 Starting [0;1;39mJournal Service[0m...
10579 12:39:40.275952 <30>[ 21.227143] systemd[1]: Starting Load Kernel Modules...
10580 12:39:40.282477 Starting [0;1;39mLoad Kernel Modules[0m...
10581 12:39:40.301533 <30>[ 21.249636] systemd[1]: Starting Remount Root and Kernel File Systems...
10582 12:39:40.308070 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10583 12:39:40.328100 <30>[ 21.279578] systemd[1]: Starting Coldplug All udev Devices...
10584 12:39:40.334715 Starting [0;1;39mColdplug All udev Devices[0m...
10585 12:39:40.352335 <30>[ 21.303933] systemd[1]: Mounted Huge Pages File System.
10586 12:39:40.359356 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10587 12:39:40.376674 <30>[ 21.327357] systemd[1]: Mounted POSIX Message Queue File System.
10588 12:39:40.383365 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10589 12:39:40.404567 <30>[ 21.355449] systemd[1]: Mounted Kernel Debug File System.
10590 12:39:40.414999 <3>[ 21.360168] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10591 12:39:40.420977 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10592 12:39:40.440664 <30>[ 21.387796] systemd[1]: Finished Create list of static device nodes for the current kernel.
10593 12:39:40.450716 [[0;32m OK [0m] Finished [0<3>[ 21.398373] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10594 12:39:40.457057 ;1;39mCreate list of st… nodes for the current kernel[0m.
10595 12:39:40.473369 <30>[ 21.424583] systemd[1]: modprobe@configfs.service: Succeeded.
10596 12:39:40.480856 <30>[ 21.431398] systemd[1]: Finished Load Kernel Module configfs.
10597 12:39:40.487298 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10598 12:39:40.497564 <3>[ 21.444131] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10599 12:39:40.505312 <30>[ 21.455533] systemd[1]: modprobe@drm.service: Succeeded.
10600 12:39:40.511966 <30>[ 21.461712] systemd[1]: Finished Load Kernel Module drm.
10601 12:39:40.525693 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m<3>[ 21.472661] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10602 12:39:40.526248 .
10603 12:39:40.546316 <30>[ 21.495887] systemd[1]: modprobe@fuse.service: Succeeded.
10604 12:39:40.552505 <30>[ 21.502343] systemd[1]: Finished Load Kernel Module fuse.
10605 12:39:40.561587 <3>[ 21.503521] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10606 12:39:40.569061 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10607 12:39:40.585803 <30>[ 21.537216] systemd[1]: Finished Load Kernel Modules.
10608 12:39:40.595563 <3>[ 21.537967] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10609 12:39:40.602391 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10610 12:39:40.620845 <30>[ 21.568116] systemd[1]: Finished Remount Root and Kernel File Systems.
10611 12:39:40.627157 <3>[ 21.571236] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10612 12:39:40.634295 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10613 12:39:40.655750 <3>[ 21.604158] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10614 12:39:40.681053 <30>[ 21.631765] systemd[1]: Mounting FUSE Control File System...
10615 12:39:40.690511 <3>[ 21.635287] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10616 12:39:40.697338 Mounting [0;1;39mFUSE Control File System[0m...
10617 12:39:40.714396 <30>[ 21.665512] systemd[1]: Mounting Kernel Configuration File System...
10618 12:39:40.723939 <3>[ 21.665791] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10619 12:39:40.731550 Mounting [0;1;39mKernel Configuration File System[0m...
10620 12:39:40.759238 <30>[ 21.707196] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10621 12:39:40.769876 <30>[ 21.716373] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10622 12:39:40.812791 <30>[ 21.763348] systemd[1]: Starting Load/Save Random Seed...
10623 12:39:40.818786 Starting [0;1;39mLoad/Save Random Seed[0m...
10624 12:39:40.850924 <4>[ 21.792608] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10625 12:39:40.857689 <30>[ 21.792966] systemd[1]: Starting Apply Kernel Variables...
10626 12:39:40.864814 <3>[ 21.808332] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10627 12:39:40.871431 Starting [0;1;39mApply Kernel Variables[0m...
10628 12:39:40.890621 <30>[ 21.841829] systemd[1]: Starting Create System Users...
10629 12:39:40.897257 Starting [0;1;39mCreate System Users[0m...
10630 12:39:40.914105 <30>[ 21.865447] systemd[1]: Started Journal Service.
10631 12:39:40.920803 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10632 12:39:40.944520 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10633 12:39:40.956127 See 'systemctl status systemd-udev-trigger.service' for details.
10634 12:39:40.973121 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10635 12:39:40.987770 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10636 12:39:41.004207 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10637 12:39:41.022349 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10638 12:39:41.040943 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10639 12:39:41.105116 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10640 12:39:41.122252 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10641 12:39:41.151232 <46>[ 22.100061] systemd-journald[293]: Received client request to flush runtime journal.
10642 12:39:41.186454 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10643 12:39:41.199342 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10644 12:39:41.215740 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10645 12:39:41.271695 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10646 12:39:42.554125 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10647 12:39:42.588079 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10648 12:39:42.621778 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10649 12:39:42.646096 Starting [0;1;39mNetwork Service[0m...
10650 12:39:42.961935 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10651 12:39:42.986649 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10652 12:39:43.047186 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10653 12:39:43.319433 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10654 12:39:43.338679 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10655 12:39:43.376299 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10656 12:39:43.395939 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10657 12:39:43.433802 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10658 12:39:43.461959 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10659 12:39:43.504029 Starting [0;1;39mNetwork Name Resolution[0m...
10660 12:39:43.529572 Starting [0;1;39mNetwork Time Synchronization[0m...
10661 12:39:43.547501 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10662 12:39:43.564867 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10663 12:39:43.613525 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10664 12:39:43.732618 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10665 12:39:43.747526 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10666 12:39:43.766379 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10667 12:39:43.779653 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10668 12:39:43.795789 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10669 12:39:43.924235 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10670 12:39:43.988294 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10671 12:39:44.018944 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10672 12:39:44.054084 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10673 12:39:44.067057 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10674 12:39:44.329710 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10675 12:39:44.343229 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10676 12:39:44.359122 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10677 12:39:44.411983 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10678 12:39:44.876128 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10679 12:39:45.251804 Starting [0;1;39mUser Login Management[0m...
10680 12:39:45.269161 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10681 12:39:45.286866 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10682 12:39:45.306837 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10683 12:39:45.353813 Starting [0;1;39mPermit User Sessions[0m...
10684 12:39:45.417935 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10685 12:39:45.441454 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10686 12:39:45.491533 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10687 12:39:45.511668 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10688 12:39:45.526752 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10689 12:39:45.563077 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10690 12:39:45.581281 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10691 12:39:45.599363 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10692 12:39:45.651724 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10693 12:39:45.698933 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10694 12:39:45.764095
10695 12:39:45.764250
10696 12:39:45.767984 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10697 12:39:45.768066
10698 12:39:45.771649 debian-bullseye-arm64 login: root (automatic login)
10699 12:39:45.771730
10700 12:39:45.771794
10701 12:39:46.060562 Linux debian-bullseye-arm64 6.1.75-cip14 #1 SMP PREEMPT Mon Feb 5 12:20:06 UTC 2024 aarch64
10702 12:39:46.060760
10703 12:39:46.066787 The programs included with the Debian GNU/Linux system are free software;
10704 12:39:46.073361 the exact distribution terms for each program are described in the
10705 12:39:46.076626 individual files in /usr/share/doc/*/copyright.
10706 12:39:46.076806
10707 12:39:46.083088 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10708 12:39:46.086205 permitted by applicable law.
10709 12:39:46.140207 Matched prompt #10: / #
10711 12:39:46.140541 Setting prompt string to ['/ #']
10712 12:39:46.140663 end: 2.2.5.1 login-action (duration 00:00:28) [common]
10714 12:39:46.140912 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
10715 12:39:46.141026 start: 2.2.6 expect-shell-connection (timeout 00:03:37) [common]
10716 12:39:46.141098 Setting prompt string to ['/ #']
10717 12:39:46.141159 Forcing a shell prompt, looking for ['/ #']
10719 12:39:46.191422 / #
10720 12:39:46.192018 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10721 12:39:46.192515 Waiting using forced prompt support (timeout 00:02:30)
10722 12:39:46.198000
10723 12:39:46.198944 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10724 12:39:46.199472 start: 2.2.7 export-device-env (timeout 00:03:37) [common]
10726 12:39:46.300592 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12703510/extract-nfsrootfs-kw_0knxi'
10727 12:39:46.307761 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12703510/extract-nfsrootfs-kw_0knxi'
10729 12:39:46.409295 / # export NFS_SERVER_IP='192.168.201.1'
10730 12:39:46.414914 export NFS_SERVER_IP='192.168.201.1'
10731 12:39:46.415220 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10732 12:39:46.415347 end: 2.2 depthcharge-retry (duration 00:01:23) [common]
10733 12:39:46.415463 end: 2 depthcharge-action (duration 00:01:23) [common]
10734 12:39:46.415581 start: 3 lava-test-retry (timeout 00:30:00) [common]
10735 12:39:46.415698 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
10736 12:39:46.415801 Using namespace: common
10738 12:39:46.516501 / # #
10739 12:39:46.517195 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
10740 12:39:46.523469 #
10741 12:39:46.524340 Using /lava-12703510
10743 12:39:46.625768 / # export SHELL=/bin/sh
10744 12:39:46.632871 export SHELL=/bin/sh
10746 12:39:46.734622 / # . /lava-12703510/environment
10747 12:39:46.741026 . /lava-12703510/environment
10749 12:39:46.848801 / # /lava-12703510/bin/lava-test-runner /lava-12703510/0
10750 12:39:46.849409 Test shell timeout: 10s (minimum of the action and connection timeout)
10751 12:39:46.855466 /lava-12703510/bin/lava-test-runner /lava-12703510/0
10752 12:39:47.081745 + export TESTRUN_ID=0_lc-compliance
10753 12:39:47.087592 + cd /lava-12703510/0/tests/0_lc-compliance
10754 12:39:47.087721 + cat uuid
10755 12:39:47.091270 + UUID=12703510_1.6.2.3.1
10756 12:39:47.091375 + set +x
10757 12:39:47.097711 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 12703510_1.6.2.3.1>
10758 12:39:47.097964 Received signal: <STARTRUN> 0_lc-compliance 12703510_1.6.2.3.1
10759 12:39:47.098037 Starting test lava.0_lc-compliance (12703510_1.6.2.3.1)
10760 12:39:47.098120 Skipping test definition patterns.
10761 12:39:47.101286 + /usr/bin/lc-compliance-parser.sh
10762 12:39:48.280445 [0:00:29.111296077] [398] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:297 [0mlibcamera v0.0.0+1-1f607da9
10763 12:39:48.283579 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
10764 12:39:48.298359 [0:00:29.128761693] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10765 12:39:48.358736 [0:00:29.189576385] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10766 12:39:48.367547 [==========] Running 120 tests from 1 test suite.
10767 12:39:48.414760 [0:00:29.245840539] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10768 12:39:48.438044 [----------] Global test environment set-up.
10769 12:39:48.468134 [0:00:29.299159385] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10770 12:39:48.503374 [----------] 120 tests from CaptureTests/SingleStream
10771 12:39:48.571846 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
10772 12:39:48.631294 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
10773 12:39:48.632019 Received signal: <TESTSET> START CaptureTests/SingleStream
10774 12:39:48.632390 Starting test_set CaptureTests/SingleStream
10775 12:39:48.634310 Camera needs 4 requests, can't test only 1
10776 12:39:48.702872 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10777 12:39:48.751932
10778 12:39:48.830518 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (61 ms)
10779 12:39:48.899209 [0:00:29.729291847] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10780 12:39:48.925776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
10781 12:39:48.926484 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
10783 12:39:48.941711 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
10784 12:39:48.994360 Camera needs 4 requests, can't test only 2
10785 12:39:49.070987 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10786 12:39:49.143911
10787 12:39:49.217091 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (57 ms)
10788 12:39:49.298423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
10789 12:39:49.298738 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
10791 12:39:49.310067 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
10792 12:39:49.350793 Camera needs 4 requests, can't test only 3
10793 12:39:49.396107 [0:00:30.227317924] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10794 12:39:49.405834 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10795 12:39:49.455876
10796 12:39:49.511627 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (52 ms)
10797 12:39:49.572827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
10798 12:39:49.573139 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
10800 12:39:49.583484 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
10801 12:39:49.629858 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (431 ms)
10802 12:39:49.702030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
10803 12:39:49.702330 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
10805 12:39:49.715416 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
10806 12:39:49.757477 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (499 ms)
10807 12:39:49.824523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
10808 12:39:49.824809 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
10810 12:39:49.834367 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
10811 12:39:50.083832 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (695 ms)
10812 12:39:50.093279 [0:00:30.924273308] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10813 12:39:50.152718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
10814 12:39:50.153011 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
10816 12:39:50.165100 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
10817 12:39:51.081783 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (998 ms)
10818 12:39:51.091074 [0:00:31.922053847] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10819 12:39:51.154239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
10820 12:39:51.154521 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
10822 12:39:51.164922 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
10823 12:39:52.479579 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (1397 ms)
10824 12:39:52.488651 [0:00:33.319103462] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10825 12:39:52.562055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
10826 12:39:52.562365 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
10828 12:39:52.575130 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
10829 12:39:54.609121 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (2130 ms)
10830 12:39:54.618923 [0:00:35.449929155] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10831 12:39:54.681159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
10832 12:39:54.681468 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
10834 12:39:54.692159 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
10835 12:39:57.839801 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (3230 ms)
10836 12:39:57.848956 [0:00:38.679660770] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10837 12:39:57.901144 [0:00:38.733216540] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10838 12:39:57.932822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
10839 12:39:57.933529 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
10841 12:39:57.953991 [0:00:38.786033463] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10842 12:39:57.957168 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
10843 12:39:58.001966 Camera needs 4 requests, can't test only 1
10844 12:39:58.012153 [0:00:38.840935616] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10845 12:39:58.083187 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10846 12:39:58.155189
10847 12:39:58.229072 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (54 ms)
10848 12:39:58.299737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
10849 12:39:58.300030 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
10851 12:39:58.312912 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
10852 12:39:58.365413 Camera needs 4 requests, can't test only 2
10853 12:39:58.375172 [0:00:39.204598232] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10854 12:39:58.446387 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10855 12:39:58.520828
10856 12:39:58.592370 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (53 ms)
10857 12:39:58.669863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
10858 12:39:58.670574 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
10860 12:39:58.686831 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
10861 12:39:58.738361 Camera needs 4 requests, can't test only 3
10862 12:39:58.813254 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10863 12:39:58.838187 [0:00:39.670652155] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10864 12:39:58.892295
10865 12:39:58.977070 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (55 ms)
10866 12:39:59.068998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
10867 12:39:59.069965 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
10869 12:39:59.084183 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
10870 12:39:59.130944 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (364 ms)
10871 12:39:59.217345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
10872 12:39:59.218063 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
10874 12:39:59.232341 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
10875 12:39:59.280982 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (465 ms)
10876 12:39:59.368403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
10877 12:39:59.369208 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
10879 12:39:59.385185 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
10880 12:39:59.525497 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (695 ms)
10881 12:39:59.538716 [0:00:40.366619617] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10882 12:39:59.619675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
10883 12:39:59.620380 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
10885 12:39:59.635480 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
10886 12:40:00.461127 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (936 ms)
10887 12:40:00.474533 [0:00:41.302373540] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10888 12:40:00.568604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
10889 12:40:00.569453 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
10891 12:40:00.584670 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
10892 12:40:01.858994 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (1398 ms)
10893 12:40:01.872380 [0:00:42.700562617] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10894 12:40:01.957152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
10895 12:40:01.957923 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
10897 12:40:01.974625 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
10898 12:40:03.958488 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (2098 ms)
10899 12:40:03.969848 [0:00:44.798486078] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10900 12:40:04.054891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
10901 12:40:04.055672 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
10903 12:40:04.071757 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
10904 12:40:05.201406 <6>[ 46.158759] vpu: disabling
10905 12:40:05.205256 <6>[ 46.161935] vproc2: disabling
10906 12:40:05.207768 <6>[ 46.165387] vproc1: disabling
10907 12:40:05.211545 <6>[ 46.169031] vaud18: disabling
10908 12:40:05.218448 <6>[ 46.172688] vsram_others: disabling
10909 12:40:05.221576 <6>[ 46.176791] va09: disabling
10910 12:40:05.225490 <6>[ 46.180080] vsram_md: disabling
10911 12:40:05.228633 <6>[ 46.183776] Vgpu: disabling
10912 12:40:07.156674 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (3201 ms)
10913 12:40:07.169803 [0:00:47.999484848] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10914 12:40:07.223421 [0:00:48.056963156] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10915 12:40:07.244529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
10916 12:40:07.244851 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
10918 12:40:07.257873 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
10919 12:40:07.278353 [0:00:48.111575079] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10920 12:40:07.305257 Camera needs 4 requests, can't test only 1
10921 12:40:07.333944 [0:00:48.167673002] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10922 12:40:07.368970 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10923 12:40:07.427592
10924 12:40:07.487282 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (58 ms)
10925 12:40:07.564475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
10926 12:40:07.564801 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
10928 12:40:07.577951 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
10929 12:40:07.618718 Camera needs 4 requests, can't test only 2
10930 12:40:07.674793 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10931 12:40:07.700230 [0:00:48.533638309] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10932 12:40:07.733906
10933 12:40:07.802385 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (55 ms)
10934 12:40:07.873207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
10935 12:40:07.873526 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
10937 12:40:07.887286 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
10938 12:40:07.928596 Camera needs 4 requests, can't test only 3
10939 12:40:07.992029 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10940 12:40:08.041084
10941 12:40:08.101024 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (55 ms)
10942 12:40:08.168328 [0:00:49.001591694] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10943 12:40:08.174818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
10944 12:40:08.175102 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
10946 12:40:08.188625 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
10947 12:40:08.231928 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (366 ms)
10948 12:40:08.306922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
10949 12:40:08.307245 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
10951 12:40:08.319680 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
10952 12:40:08.363712 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (468 ms)
10953 12:40:08.435167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
10954 12:40:08.435487 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
10956 12:40:08.450122 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
10957 12:40:08.889029 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (730 ms)
10958 12:40:08.902021 [0:00:49.731981771] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10959 12:40:08.970471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
10960 12:40:08.970794 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
10962 12:40:08.983696 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
10963 12:40:09.790944 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (902 ms)
10964 12:40:09.803962 [0:00:50.634149310] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10965 12:40:09.865546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
10966 12:40:09.865871 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
10968 12:40:09.879773 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
10969 12:40:11.189209 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (1397 ms)
10970 12:40:11.202130 [0:00:52.031788002] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10971 12:40:11.266710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
10972 12:40:11.267032 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
10974 12:40:11.278153 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
10975 12:40:13.287569 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (2099 ms)
10976 12:40:13.300056 [0:00:54.130441694] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10977 12:40:13.361756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
10978 12:40:13.362078 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
10980 12:40:13.374216 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
10981 12:40:16.488392 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (3201 ms)
10982 12:40:16.501415 [0:00:57.331664233] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10983 12:40:16.553833 [0:00:57.388387695] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10984 12:40:16.573813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
10985 12:40:16.574114 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
10987 12:40:16.586360 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
10988 12:40:16.610343 [0:00:57.445221925] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10989 12:40:16.636117 Camera needs 4 requests, can't test only 1
10990 12:40:16.665066 [0:00:57.499221464] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10991 12:40:16.698453 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10992 12:40:16.760322
10993 12:40:16.822978 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (57 ms)
10994 12:40:16.886153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
10995 12:40:16.886476 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
10997 12:40:16.895424 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
10998 12:40:16.935117 Camera needs 4 requests, can't test only 2
10999 12:40:16.992024 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11000 12:40:17.031362 [0:00:57.864556083] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11001 12:40:17.046274
11002 12:40:17.104341 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (57 ms)
11003 12:40:17.172557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11004 12:40:17.172890 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11006 12:40:17.182075 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11007 12:40:17.226901 Camera needs 4 requests, can't test only 3
11008 12:40:17.292523 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11009 12:40:17.351555
11010 12:40:17.418452 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (55 ms)
11011 12:40:17.493976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11012 12:40:17.494301 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11014 12:40:17.506678 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11015 12:40:17.552276 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (364 ms)
11016 12:40:17.562073 [0:00:58.393982115] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11017 12:40:17.629994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11018 12:40:17.630323 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11020 12:40:17.643456 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11021 12:40:17.685529 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (530 ms)
11022 12:40:17.754412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11023 12:40:17.754737 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11025 12:40:17.769469 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11026 12:40:18.246696 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (695 ms)
11027 12:40:18.260426 [0:00:59.090543333] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11028 12:40:18.350585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11029 12:40:18.351270 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11031 12:40:18.366565 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11032 12:40:19.246014 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (998 ms)
11033 12:40:19.259433 [0:01:00.088828169] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11034 12:40:19.329413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11035 12:40:19.329806 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11037 12:40:19.341773 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11038 12:40:20.643144 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (1397 ms)
11039 12:40:20.655635 [0:01:01.486247396] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11040 12:40:20.735743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11041 12:40:20.736046 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11043 12:40:20.750401 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11044 12:40:22.773985 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (2131 ms)
11045 12:40:22.788350 [0:01:03.617109057] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11046 12:40:22.868869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11047 12:40:22.869648 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11049 12:40:22.885718 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11050 12:40:26.003707 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (3230 ms)
11051 12:40:26.017430 [0:01:06.847436002] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11052 12:40:26.071105 [0:01:06.905443045] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11053 12:40:26.077819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11054 12:40:26.078106 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11056 12:40:26.089708 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11057 12:40:26.125572 [0:01:06.960189974] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11058 12:40:26.128991 Camera needs 4 requests, can't test only 1
11059 12:40:26.177839 [0:01:07.012448706] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11060 12:40:26.186770 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11061 12:40:26.237023
11062 12:40:26.300411 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (58 ms)
11063 12:40:26.364003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11064 12:40:26.364285 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11066 12:40:26.373630 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11067 12:40:26.413499 Camera needs 4 requests, can't test only 2
11068 12:40:26.472399 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11069 12:40:26.525593
11070 12:40:26.581478 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (56 ms)
11071 12:40:26.641121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11072 12:40:26.641408 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11074 12:40:26.651402 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11075 12:40:26.688541 Camera needs 4 requests, can't test only 3
11076 12:40:26.743378 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11077 12:40:26.799193
11078 12:40:26.856071 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (53 ms)
11079 12:40:26.915634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11080 12:40:26.915922 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11082 12:40:26.926134 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11083 12:40:27.321545 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (1151 ms)
11084 12:40:27.334638 [0:01:08.163970380] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11085 12:40:27.390630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11086 12:40:27.390928 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11088 12:40:27.402305 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11089 12:40:28.737878 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (1417 ms)
11090 12:40:28.751305 [0:01:09.580938120] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11091 12:40:28.803835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11092 12:40:28.804150 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11094 12:40:28.812255 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11095 12:40:30.788309 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (2049 ms)
11096 12:40:30.801250 [0:01:11.630967779] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11097 12:40:30.856009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11098 12:40:30.856278 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11100 12:40:30.863728 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11101 12:40:33.470116 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (2683 ms)
11102 12:40:33.485923 [0:01:14.313490046] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11103 12:40:33.541433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11104 12:40:33.541740 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11106 12:40:33.555042 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11107 12:40:37.586047 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (4115 ms)
11108 12:40:37.598496 [0:01:18.428091415] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11109 12:40:37.654939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11110 12:40:37.655263 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11112 12:40:37.666763 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11113 12:40:43.895008 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (6310 ms)
11114 12:40:43.907822 [0:01:24.738872116] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11115 12:40:43.971712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11116 12:40:43.972071 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11118 12:40:43.981965 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11119 12:40:53.509034 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (9615 ms)
11120 12:40:53.521961 [0:01:34.353066227] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11121 12:40:53.569725 [0:01:34.405612938] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11122 12:40:53.600983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11123 12:40:53.601863 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11125 12:40:53.623449 [0:01:34.458670255] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11126 12:40:53.628999 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11127 12:40:53.667202 Camera needs 4 requests, can't test only 1
11128 12:40:53.677797 [0:01:34.511585113] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11129 12:40:53.744846 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11130 12:40:53.813969
11131 12:40:53.898551 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (52 ms)
11132 12:40:53.991147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11133 12:40:53.991887 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11135 12:40:54.004374 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11136 12:40:54.055266 Camera needs 4 requests, can't test only 2
11137 12:40:54.132674 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11138 12:40:54.210884
11139 12:40:54.292284 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (53 ms)
11140 12:40:54.387367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11141 12:40:54.388222 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11143 12:40:54.399341 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11144 12:40:54.455567 Camera needs 4 requests, can't test only 3
11145 12:40:54.530933 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11146 12:40:54.603178
11147 12:40:54.689541 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (53 ms)
11148 12:40:54.783369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11149 12:40:54.784115 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11151 12:40:54.795332 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11152 12:40:54.853458 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (1184 ms)
11153 12:40:54.863680 [0:01:35.694877008] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11154 12:40:54.940124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11155 12:40:54.940946 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11157 12:40:54.950569 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11158 12:40:56.239268 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (1384 ms)
11159 12:40:56.248171 [0:01:37.079668585] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11160 12:40:56.332333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11161 12:40:56.333122 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11163 12:40:56.344796 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11164 12:40:58.285918 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (2048 ms)
11165 12:40:58.295866 [0:01:39.127658487] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11166 12:40:58.350323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11167 12:40:58.350595 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11169 12:40:58.357887 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11170 12:41:01.003576 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (2718 ms)
11171 12:41:01.012807 [0:01:41.845515449] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11172 12:41:01.065951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11173 12:41:01.066242 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11175 12:41:01.072458 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11176 12:41:05.181424 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (4179 ms)
11177 12:41:05.190853 [0:01:46.023937502] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11178 12:41:05.244203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11179 12:41:05.244478 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11181 12:41:05.250354 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11182 12:41:11.492322 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (6311 ms)
11183 12:41:11.501755 [0:01:52.335067884] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11184 12:41:11.558539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11185 12:41:11.558810 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11187 12:41:11.564632 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11188 12:41:21.168526 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (9677 ms)
11189 12:41:21.178136 [0:02:02.012396647] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11190 12:41:21.224689 [0:02:02.063830299] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11191 12:41:21.271415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11192 12:41:21.272217 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11194 12:41:21.281452 [0:02:02.117725473] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11195 12:41:21.288471 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11196 12:41:21.330581 [0:02:02.169935156] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11197 12:41:21.334245 Camera needs 4 requests, can't test only 1
11198 12:41:21.413675 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11199 12:41:21.476633
11200 12:41:21.556232 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (52 ms)
11201 12:41:21.632666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11202 12:41:21.633097 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11204 12:41:21.640915 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11205 12:41:21.685401 Camera needs 4 requests, can't test only 2
11206 12:41:21.753237 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11207 12:41:21.824781
11208 12:41:21.901352 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (53 ms)
11209 12:41:21.982116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11210 12:41:21.982934 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11212 12:41:21.992345 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11213 12:41:22.040268 Camera needs 4 requests, can't test only 3
11214 12:41:22.109378 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11215 12:41:22.174818
11216 12:41:22.248330 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (53 ms)
11217 12:41:22.338336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11218 12:41:22.339065 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11220 12:41:22.353416 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11221 12:41:22.410564 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (1084 ms)
11222 12:41:22.420015 [0:02:03.254494776] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11223 12:41:22.492657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11224 12:41:22.493442 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11226 12:41:22.503990 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11227 12:41:23.798971 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (1389 ms)
11228 12:41:23.808855 [0:02:04.642012224] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11229 12:41:23.894139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11230 12:41:23.895015 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11232 12:41:23.905855 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11233 12:41:25.910272 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (2110 ms)
11234 12:41:25.919236 [0:02:06.752944305] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11235 12:41:26.003725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11236 12:41:26.004457 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11238 12:41:26.015158 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11239 12:41:28.591661 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (2681 ms)
11240 12:41:28.602028 [0:02:09.434606383] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11241 12:41:28.681100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11242 12:41:28.681823 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11244 12:41:28.693650 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11245 12:41:32.705712 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (4114 ms)
11246 12:41:32.716343 [0:02:13.548237618] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11247 12:41:32.797931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11248 12:41:32.798648 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11250 12:41:32.808483 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11251 12:41:39.015196 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (6310 ms)
11252 12:41:39.024851 [0:02:19.858224590] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11253 12:41:39.086464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11254 12:41:39.086762 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11256 12:41:39.094358 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11257 12:41:48.629884 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (9614 ms)
11258 12:41:48.639977 [0:02:29.471766407] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11259 12:41:48.686733 [0:02:29.523917874] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11260 12:41:48.716494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11261 12:41:48.717324 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11263 12:41:48.727196 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11264 12:41:48.741326 [0:02:29.578415356] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11265 12:41:48.775705 Camera needs 4 requests, can't test only 1
11266 12:41:48.794852 [0:02:29.631844049] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11267 12:41:48.853772 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11268 12:41:48.922203
11269 12:41:49.000314 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (52 ms)
11270 12:41:49.088491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11271 12:41:49.089324 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11273 12:41:49.101119 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11274 12:41:49.151404 Camera needs 4 requests, can't test only 2
11275 12:41:49.227162 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11276 12:41:49.295590
11277 12:41:49.375683 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (54 ms)
11278 12:41:49.462379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11279 12:41:49.463180 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11281 12:41:49.473965 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11282 12:41:49.525401 Camera needs 4 requests, can't test only 3
11283 12:41:49.603636 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11284 12:41:49.674714
11285 12:41:49.755784 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (53 ms)
11286 12:41:49.844213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11287 12:41:49.845049 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11289 12:41:49.855471 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11290 12:41:49.880660 [0:02:30.717905123] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11291 12:41:49.907725 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (1086 ms)
11292 12:41:49.988069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11293 12:41:49.988374 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11295 12:41:49.996262 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11296 12:41:51.266212 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (1390 ms)
11297 12:41:51.275044 [0:02:32.108051438] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11298 12:41:51.329251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11299 12:41:51.329554 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11301 12:41:51.337441 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11302 12:41:53.379089 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (2112 ms)
11303 12:41:53.387862 [0:02:34.220485001] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11304 12:41:53.459502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11305 12:41:53.460314 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11307 12:41:53.472335 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11308 12:41:56.096813 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (2718 ms)
11309 12:41:56.105850 [0:02:36.938669531] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11310 12:41:56.185523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11311 12:41:56.185834 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11313 12:41:56.194656 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11314 12:42:00.210487 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (4115 ms)
11315 12:42:00.220320 [0:02:41.052723331] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11316 12:42:00.297768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11317 12:42:00.298630 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11319 12:42:00.308453 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11320 12:42:06.520469 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (6309 ms)
11321 12:42:06.529712 [0:02:47.362918533] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11322 12:42:06.603763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11323 12:42:06.604105 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11325 12:42:06.614778 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11326 12:42:16.261289 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (9742 ms)
11327 12:42:16.271511 [0:02:57.104244211] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11328 12:42:16.341660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11329 12:42:16.342592 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11331 12:42:16.352231 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11332 12:42:16.552424 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (295 ms)
11333 12:42:16.565689 [0:02:57.399028779] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11334 12:42:16.638678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11335 12:42:16.638966 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11337 12:42:16.648675 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11338 12:42:16.816510 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (264 ms)
11339 12:42:16.830155 [0:02:57.662903457] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11340 12:42:16.890117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11341 12:42:16.890997 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11343 12:42:16.905702 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11344 12:42:17.114948 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (296 ms)
11345 12:42:17.125841 [0:02:57.959437279] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11346 12:42:17.190819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11347 12:42:17.191115 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11349 12:42:17.201641 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11350 12:42:17.541656 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (428 ms)
11351 12:42:17.553900 [0:02:58.387385288] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11352 12:42:17.624578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11353 12:42:17.625318 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11355 12:42:17.636787 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11356 12:42:18.037441 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (497 ms)
11357 12:42:18.050608 [0:02:58.884236033] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11358 12:42:18.107880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11359 12:42:18.108160 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11361 12:42:18.118622 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11362 12:42:18.765493 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (728 ms)
11363 12:42:18.779165 [0:02:59.612199502] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11364 12:42:18.853944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11365 12:42:18.854709 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11367 12:42:18.868112 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11368 12:42:19.664346 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (898 ms)
11369 12:42:19.676856 [0:03:00.510883822] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11370 12:42:19.744557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11371 12:42:19.744875 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11373 12:42:19.755751 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11374 12:42:21.058305 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (1395 ms)
11375 12:42:21.071363 [0:03:01.905013872] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11376 12:42:21.134711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11377 12:42:21.135509 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11379 12:42:21.148117 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11380 12:42:23.152562 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (2094 ms)
11381 12:42:23.165675 [0:03:03.999487960] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11382 12:42:23.239599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11383 12:42:23.240474 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11385 12:42:23.253380 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11386 12:42:26.349423 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (3197 ms)
11387 12:42:26.363013 [0:03:07.196605322] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11388 12:42:26.422824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11389 12:42:26.423171 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11391 12:42:26.433939 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11392 12:42:26.680672 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (327 ms)
11393 12:42:26.691033 [0:03:07.524371184] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11394 12:42:26.760376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11395 12:42:26.760864 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11397 12:42:26.770078 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11398 12:42:27.042787 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (361 ms)
11399 12:42:27.052279 [0:03:07.885761454] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11400 12:42:27.141899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11401 12:42:27.142715 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11403 12:42:27.154452 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11404 12:42:27.341441 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (299 ms)
11405 12:42:27.351255 [0:03:08.184148043] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11406 12:42:27.433505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11407 12:42:27.434299 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11409 12:42:27.445043 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11410 12:42:27.704312 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (363 ms)
11411 12:42:27.713935 [0:03:08.547253435] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11412 12:42:27.797242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11413 12:42:27.798104 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11415 12:42:27.809354 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11416 12:42:28.167396 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (463 ms)
11417 12:42:28.178002 [0:03:09.010863212] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11418 12:42:28.260949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11419 12:42:28.261231 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11421 12:42:28.270637 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11422 12:42:28.862380 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (695 ms)
11423 12:42:28.872133 [0:03:09.706180889] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11424 12:42:28.959981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11425 12:42:28.960796 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11427 12:42:28.971985 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11428 12:42:29.856538 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (994 ms)
11429 12:42:29.866324 [0:03:10.700074518] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11430 12:42:29.951504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11431 12:42:29.952309 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11433 12:42:29.962629 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11434 12:42:31.187410 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (1331 ms)
11435 12:42:31.197613 [0:03:12.031154214] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11436 12:42:31.273132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11437 12:42:31.274346 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11439 12:42:31.283170 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11440 12:42:33.314226 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (2127 ms)
11441 12:42:33.324422 [0:03:14.158339533] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11442 12:42:33.398516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11443 12:42:33.399405 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11445 12:42:33.409917 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11446 12:42:36.541124 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (3227 ms)
11447 12:42:36.550766 [0:03:17.385045837] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11448 12:42:36.624694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11449 12:42:36.625039 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11451 12:42:36.634820 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11452 12:42:36.837232 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (295 ms)
11453 12:42:36.845790 [0:03:17.680355351] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11454 12:42:36.925228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11455 12:42:36.925930 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11457 12:42:36.935329 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11458 12:42:37.133307 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (297 ms)
11459 12:42:37.142790 [0:03:17.977240952] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11460 12:42:37.226707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11461 12:42:37.227477 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11463 12:42:37.238590 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11464 12:42:37.429273 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (296 ms)
11465 12:42:37.439796 [0:03:18.273808214] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11466 12:42:37.515719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11467 12:42:37.516003 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11469 12:42:37.525735 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11470 12:42:37.858452 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (429 ms)
11471 12:42:37.867941 [0:03:18.702445017] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11472 12:42:37.952276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11473 12:42:37.953212 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11475 12:42:37.964534 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11476 12:42:38.354649 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (496 ms)
11477 12:42:38.365625 [0:03:19.199049721] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11478 12:42:38.440503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11479 12:42:38.440949 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11481 12:42:38.452420 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11482 12:42:39.049461 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (695 ms)
11483 12:42:39.059036 [0:03:19.893919816] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11484 12:42:39.147995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11485 12:42:39.148268 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11487 12:42:39.156517 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11488 12:42:39.980772 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (932 ms)
11489 12:42:39.991071 [0:03:20.825426652] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11490 12:42:40.067724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11491 12:42:40.068497 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11493 12:42:40.078764 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11494 12:42:41.375800 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (1394 ms)
11495 12:42:41.385567 [0:03:22.219668169] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11496 12:42:41.465187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11497 12:42:41.465908 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11499 12:42:41.477916 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11500 12:42:43.470433 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (2095 ms)
11501 12:42:43.479020 [0:03:24.314181055] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11502 12:42:43.559738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11503 12:42:43.560325 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11505 12:42:43.571235 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11506 12:42:46.666318 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (3197 ms)
11507 12:42:46.676756 [0:03:27.511238123] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11508 12:42:46.752540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11509 12:42:46.753273 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11511 12:42:46.761668 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11512 12:42:46.994209 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (328 ms)
11513 12:42:47.004039 [0:03:27.839188746] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11514 12:42:47.076084 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11516 12:42:47.078821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11517 12:42:47.090461 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11518 12:42:47.356039 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (361 ms)
11519 12:42:47.365453 [0:03:28.200146323] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11520 12:42:47.444160 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11522 12:42:47.446713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11523 12:42:47.459781 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11524 12:42:47.653374 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (298 ms)
11525 12:42:47.664551 [0:03:28.498742376] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11526 12:42:47.733563 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11528 12:42:47.736023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11529 12:42:47.746969 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11530 12:42:48.017121 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (363 ms)
11531 12:42:48.026152 [0:03:28.861688186] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11532 12:42:48.110130 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11534 12:42:48.113160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11535 12:42:48.125954 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11536 12:42:48.479947 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (464 ms)
11537 12:42:48.489512 [0:03:29.324941622] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11538 12:42:48.567201 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11540 12:42:48.569920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11541 12:42:48.580497 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11542 12:42:49.174994 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (695 ms)
11543 12:42:49.184747 [0:03:30.019702053] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11544 12:42:49.265300 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11546 12:42:49.267041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11547 12:42:49.278360 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11548 12:42:50.169341 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (994 ms)
11549 12:42:50.179412 [0:03:31.014619898] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11550 12:42:50.254600 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11552 12:42:50.257321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11553 12:42:50.268408 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11554 12:42:51.500799 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (1331 ms)
11555 12:42:51.509964 [0:03:32.345911184] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11556 12:42:51.592997 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11558 12:42:51.596371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11559 12:42:51.606259 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11560 12:42:53.627315 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (2127 ms)
11561 12:42:53.637986 [0:03:34.472591811] [398] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11562 12:42:53.708939 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11564 12:42:53.711980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11565 12:42:53.722629 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11566 12:42:56.791269 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (3163 ms)
11567 12:42:56.874748 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11569 12:42:56.877872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11570 12:42:56.888605 [----------] 120 tests from CaptureTests/SingleStream (188508 ms total)
11571 12:42:56.949961
11572 12:42:57.017748 [----------] Global test environment tear-down
11573 12:42:57.087938 [==========] 120 tests from 1 test suite ran. (188508 ms total)
11574 12:42:57.155574 <LAVA_SIGNAL_TESTSET STOP>
11575 12:42:57.156289 Received signal: <TESTSET> STOP
11576 12:42:57.156653 Closing test_set CaptureTests/SingleStream
11577 12:42:57.165298 + set +x
11578 12:42:57.168930 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 12703510_1.6.2.3.1>
11579 12:42:57.169601 Received signal: <ENDRUN> 0_lc-compliance 12703510_1.6.2.3.1
11580 12:42:57.169996 Ending use of test pattern.
11581 12:42:57.170307 Ending test lava.0_lc-compliance (12703510_1.6.2.3.1), duration 190.07
11583 12:42:57.172159 <LAVA_TEST_RUNNER EXIT>
11584 12:42:57.172811 ok: lava_test_shell seems to have completed
11585 12:42:57.181663 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11586 12:42:57.182557 end: 3.1 lava-test-shell (duration 00:03:11) [common]
11587 12:42:57.183009 end: 3 lava-test-retry (duration 00:03:11) [common]
11588 12:42:57.183443 start: 4 finalize (timeout 00:10:00) [common]
11589 12:42:57.183903 start: 4.1 power-off (timeout 00:00:30) [common]
11590 12:42:57.184639 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
11591 12:42:57.277622 >> Command sent successfully.
11592 12:42:57.283355 Returned 0 in 0 seconds
11593 12:42:57.384395 end: 4.1 power-off (duration 00:00:00) [common]
11595 12:42:57.385989 start: 4.2 read-feedback (timeout 00:10:00) [common]
11596 12:42:57.387326 Listened to connection for namespace 'common' for up to 1s
11597 12:42:58.388033 Finalising connection for namespace 'common'
11598 12:42:58.388758 Disconnecting from shell: Finalise
11599 12:42:58.389207 / #
11600 12:42:58.490237 end: 4.2 read-feedback (duration 00:00:01) [common]
11601 12:42:58.490961 end: 4 finalize (duration 00:00:01) [common]
11602 12:42:58.491603 Cleaning after the job
11603 12:42:58.492134 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703510/tftp-deploy-mt650d1d/ramdisk
11604 12:42:58.496247 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703510/tftp-deploy-mt650d1d/kernel
11605 12:42:58.508851 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703510/tftp-deploy-mt650d1d/dtb
11606 12:42:58.509008 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703510/tftp-deploy-mt650d1d/nfsrootfs
11607 12:42:58.566697 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703510/tftp-deploy-mt650d1d/modules
11608 12:42:58.573979 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12703510
11609 12:42:58.889062 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12703510
11610 12:42:58.889241 Job finished correctly