Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 37
- Kernel Errors: 34
1 12:42:58.912935 lava-dispatcher, installed at version: 2024.01
2 12:42:58.913141 start: 0 validate
3 12:42:58.913265 Start time: 2024-02-05 12:42:58.913258+00:00 (UTC)
4 12:42:58.913384 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:42:58.913512 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 12:42:59.186468 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:42:59.186639 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:42:59.450438 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:42:59.450603 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:42:59.715248 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:42:59.715414 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:42:59.981564 validate duration: 1.07
14 12:42:59.981880 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:42:59.982032 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:42:59.982164 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:42:59.982319 Not decompressing ramdisk as can be used compressed.
18 12:42:59.982435 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/rootfs.cpio.gz
19 12:42:59.982500 saving as /var/lib/lava/dispatcher/tmp/12703558/tftp-deploy-so37e02b/ramdisk/rootfs.cpio.gz
20 12:42:59.982564 total size: 84918747 (80 MB)
21 12:42:59.983904 progress 0 % (0 MB)
22 12:43:00.006329 progress 5 % (4 MB)
23 12:43:00.027546 progress 10 % (8 MB)
24 12:43:00.048721 progress 15 % (12 MB)
25 12:43:00.069977 progress 20 % (16 MB)
26 12:43:00.091109 progress 25 % (20 MB)
27 12:43:00.112304 progress 30 % (24 MB)
28 12:43:00.133490 progress 35 % (28 MB)
29 12:43:00.154541 progress 40 % (32 MB)
30 12:43:00.175692 progress 45 % (36 MB)
31 12:43:00.196702 progress 50 % (40 MB)
32 12:43:00.217849 progress 55 % (44 MB)
33 12:43:00.238958 progress 60 % (48 MB)
34 12:43:00.260236 progress 65 % (52 MB)
35 12:43:00.281556 progress 70 % (56 MB)
36 12:43:00.302795 progress 75 % (60 MB)
37 12:43:00.324002 progress 80 % (64 MB)
38 12:43:00.345137 progress 85 % (68 MB)
39 12:43:00.366284 progress 90 % (72 MB)
40 12:43:00.387587 progress 95 % (76 MB)
41 12:43:00.408630 progress 100 % (80 MB)
42 12:43:00.408838 80 MB downloaded in 0.43 s (189.98 MB/s)
43 12:43:00.409003 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:43:00.409250 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:43:00.409339 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:43:00.409425 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:43:00.409561 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:43:00.409631 saving as /var/lib/lava/dispatcher/tmp/12703558/tftp-deploy-so37e02b/kernel/Image
50 12:43:00.409693 total size: 51534336 (49 MB)
51 12:43:00.409756 No compression specified
52 12:43:00.410888 progress 0 % (0 MB)
53 12:43:00.423740 progress 5 % (2 MB)
54 12:43:00.436722 progress 10 % (4 MB)
55 12:43:00.449563 progress 15 % (7 MB)
56 12:43:00.462536 progress 20 % (9 MB)
57 12:43:00.475484 progress 25 % (12 MB)
58 12:43:00.488287 progress 30 % (14 MB)
59 12:43:00.501316 progress 35 % (17 MB)
60 12:43:00.514243 progress 40 % (19 MB)
61 12:43:00.526985 progress 45 % (22 MB)
62 12:43:00.540032 progress 50 % (24 MB)
63 12:43:00.552862 progress 55 % (27 MB)
64 12:43:00.565790 progress 60 % (29 MB)
65 12:43:00.578678 progress 65 % (31 MB)
66 12:43:00.591503 progress 70 % (34 MB)
67 12:43:00.604497 progress 75 % (36 MB)
68 12:43:00.617518 progress 80 % (39 MB)
69 12:43:00.630355 progress 85 % (41 MB)
70 12:43:00.643347 progress 90 % (44 MB)
71 12:43:00.656226 progress 95 % (46 MB)
72 12:43:00.668781 progress 100 % (49 MB)
73 12:43:00.668994 49 MB downloaded in 0.26 s (189.54 MB/s)
74 12:43:00.669145 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:43:00.669378 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:43:00.669472 start: 1.3 download-retry (timeout 00:09:59) [common]
78 12:43:00.669558 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 12:43:00.669693 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:43:00.669765 saving as /var/lib/lava/dispatcher/tmp/12703558/tftp-deploy-so37e02b/dtb/mt8192-asurada-spherion-r0.dtb
81 12:43:00.669827 total size: 47278 (0 MB)
82 12:43:00.669889 No compression specified
83 12:43:00.671054 progress 69 % (0 MB)
84 12:43:00.671329 progress 100 % (0 MB)
85 12:43:00.671484 0 MB downloaded in 0.00 s (27.26 MB/s)
86 12:43:00.671606 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:43:00.671831 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:43:00.671918 start: 1.4 download-retry (timeout 00:09:59) [common]
90 12:43:00.672001 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 12:43:00.672113 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:43:00.672181 saving as /var/lib/lava/dispatcher/tmp/12703558/tftp-deploy-so37e02b/modules/modules.tar
93 12:43:00.672241 total size: 8639964 (8 MB)
94 12:43:00.672303 Using unxz to decompress xz
95 12:43:00.675838 progress 0 % (0 MB)
96 12:43:00.696558 progress 5 % (0 MB)
97 12:43:00.719705 progress 10 % (0 MB)
98 12:43:00.743004 progress 15 % (1 MB)
99 12:43:00.766254 progress 20 % (1 MB)
100 12:43:00.790042 progress 25 % (2 MB)
101 12:43:00.816922 progress 30 % (2 MB)
102 12:43:00.841062 progress 35 % (2 MB)
103 12:43:00.864022 progress 40 % (3 MB)
104 12:43:00.888056 progress 45 % (3 MB)
105 12:43:00.912977 progress 50 % (4 MB)
106 12:43:00.939063 progress 55 % (4 MB)
107 12:43:00.963756 progress 60 % (4 MB)
108 12:43:00.988987 progress 65 % (5 MB)
109 12:43:01.014066 progress 70 % (5 MB)
110 12:43:01.037646 progress 75 % (6 MB)
111 12:43:01.064554 progress 80 % (6 MB)
112 12:43:01.091955 progress 85 % (7 MB)
113 12:43:01.116334 progress 90 % (7 MB)
114 12:43:01.145455 progress 95 % (7 MB)
115 12:43:01.172804 progress 100 % (8 MB)
116 12:43:01.178680 8 MB downloaded in 0.51 s (16.27 MB/s)
117 12:43:01.178985 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:43:01.179384 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:43:01.179520 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:43:01.179658 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:43:01.179784 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:43:01.179918 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:43:01.180213 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53
125 12:43:01.180400 makedir: /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/bin
126 12:43:01.180547 makedir: /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/tests
127 12:43:01.180693 makedir: /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/results
128 12:43:01.180855 Creating /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/bin/lava-add-keys
129 12:43:01.181054 Creating /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/bin/lava-add-sources
130 12:43:01.181237 Creating /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/bin/lava-background-process-start
131 12:43:01.181422 Creating /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/bin/lava-background-process-stop
132 12:43:01.181600 Creating /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/bin/lava-common-functions
133 12:43:01.181780 Creating /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/bin/lava-echo-ipv4
134 12:43:01.181969 Creating /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/bin/lava-install-packages
135 12:43:01.182149 Creating /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/bin/lava-installed-packages
136 12:43:01.182328 Creating /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/bin/lava-os-build
137 12:43:01.182507 Creating /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/bin/lava-probe-channel
138 12:43:01.182688 Creating /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/bin/lava-probe-ip
139 12:43:01.182866 Creating /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/bin/lava-target-ip
140 12:43:01.183045 Creating /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/bin/lava-target-mac
141 12:43:01.183224 Creating /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/bin/lava-target-storage
142 12:43:01.183409 Creating /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/bin/lava-test-case
143 12:43:01.183589 Creating /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/bin/lava-test-event
144 12:43:01.183769 Creating /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/bin/lava-test-feedback
145 12:43:01.183952 Creating /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/bin/lava-test-raise
146 12:43:01.184132 Creating /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/bin/lava-test-reference
147 12:43:01.184313 Creating /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/bin/lava-test-runner
148 12:43:01.184494 Creating /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/bin/lava-test-set
149 12:43:01.184675 Creating /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/bin/lava-test-shell
150 12:43:01.184859 Updating /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/bin/lava-install-packages (oe)
151 12:43:01.185076 Updating /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/bin/lava-installed-packages (oe)
152 12:43:01.185254 Creating /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/environment
153 12:43:01.185401 LAVA metadata
154 12:43:01.185517 - LAVA_JOB_ID=12703558
155 12:43:01.185621 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:43:01.185769 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:43:01.185875 skipped lava-vland-overlay
158 12:43:01.185997 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:43:01.186127 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:43:01.186240 skipped lava-multinode-overlay
161 12:43:01.186359 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:43:01.186489 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:43:01.186608 Loading test definitions
164 12:43:01.186754 start: 1.5.2.3.1 git-repo-action (timeout 00:09:59) [common]
165 12:43:01.186873 Using /lava-12703558 at stage 0
166 12:43:01.187024 Fetching tests from https://github.com/kernelci/kernelci-core
167 12:43:01.187161 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/0/tests/0_sleep'
168 12:43:01.826741 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/0/tests/0_sleep
169 12:43:01.828286 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 12:43:01.828821 uuid=12703558_1.5.2.3.1 testdef=None
171 12:43:01.829011 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 12:43:01.829396 start: 1.5.2.3.2 test-overlay (timeout 00:09:58) [common]
174 12:43:01.830276 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 12:43:01.830648 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:58) [common]
177 12:43:01.831701 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 12:43:01.832072 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:58) [common]
180 12:43:01.833119 runner path: /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/0/tests/0_sleep test_uuid 12703558_1.5.2.3.1
181 12:43:01.833245 sleep_params='mem'
182 12:43:01.833443 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 12:43:01.833796 Creating lava-test-runner.conf files
185 12:43:01.833900 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12703558/lava-overlay-t05slh53/lava-12703558/0 for stage 0
186 12:43:01.834090 - 0_sleep
187 12:43:01.834248 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 12:43:01.834388 start: 1.5.2.4 compress-overlay (timeout 00:09:58) [common]
189 12:43:01.976564 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 12:43:01.976738 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:58) [common]
191 12:43:01.976858 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 12:43:01.976976 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 12:43:01.977084 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:58) [common]
194 12:43:04.225746 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
195 12:43:04.226162 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
196 12:43:04.226339 extracting modules file /var/lib/lava/dispatcher/tmp/12703558/tftp-deploy-so37e02b/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12703558/extract-overlay-ramdisk-2hju_f77/ramdisk
197 12:43:04.439832 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 12:43:04.440012 start: 1.5.5 apply-overlay-tftp (timeout 00:09:56) [common]
199 12:43:04.440132 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12703558/compress-overlay-sfzgm1kp/overlay-1.5.2.4.tar.gz to ramdisk
200 12:43:04.440215 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12703558/compress-overlay-sfzgm1kp/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12703558/extract-overlay-ramdisk-2hju_f77/ramdisk
201 12:43:04.534021 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 12:43:04.534171 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
203 12:43:04.534264 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 12:43:04.534353 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
205 12:43:04.534433 Building ramdisk /var/lib/lava/dispatcher/tmp/12703558/extract-overlay-ramdisk-2hju_f77/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12703558/extract-overlay-ramdisk-2hju_f77/ramdisk
206 12:43:05.869531 >> 563700 blocks
207 12:43:15.464711 rename /var/lib/lava/dispatcher/tmp/12703558/extract-overlay-ramdisk-2hju_f77/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12703558/tftp-deploy-so37e02b/ramdisk/ramdisk.cpio.gz
208 12:43:15.465134 end: 1.5.7 compress-ramdisk (duration 00:00:11) [common]
209 12:43:15.465259 start: 1.5.8 prepare-kernel (timeout 00:09:45) [common]
210 12:43:15.465359 start: 1.5.8.1 prepare-fit (timeout 00:09:45) [common]
211 12:43:15.465467 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12703558/tftp-deploy-so37e02b/kernel/Image'
212 12:43:28.067350 Returned 0 in 12 seconds
213 12:43:28.168393 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12703558/tftp-deploy-so37e02b/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12703558/tftp-deploy-so37e02b/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12703558/tftp-deploy-so37e02b/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12703558/tftp-deploy-so37e02b/kernel/image.itb
214 12:43:29.471492 output: FIT description: Kernel Image image with one or more FDT blobs
215 12:43:29.471827 output: Created: Mon Feb 5 12:43:29 2024
216 12:43:29.471905 output: Image 0 (kernel-1)
217 12:43:29.471971 output: Description:
218 12:43:29.472034 output: Created: Mon Feb 5 12:43:29 2024
219 12:43:29.472094 output: Type: Kernel Image
220 12:43:29.472153 output: Compression: lzma compressed
221 12:43:29.472213 output: Data Size: 12052857 Bytes = 11770.37 KiB = 11.49 MiB
222 12:43:29.472270 output: Architecture: AArch64
223 12:43:29.472327 output: OS: Linux
224 12:43:29.472387 output: Load Address: 0x00000000
225 12:43:29.472443 output: Entry Point: 0x00000000
226 12:43:29.472504 output: Hash algo: crc32
227 12:43:29.472558 output: Hash value: 8a14336a
228 12:43:29.472615 output: Image 1 (fdt-1)
229 12:43:29.472671 output: Description: mt8192-asurada-spherion-r0
230 12:43:29.472724 output: Created: Mon Feb 5 12:43:29 2024
231 12:43:29.472778 output: Type: Flat Device Tree
232 12:43:29.472831 output: Compression: uncompressed
233 12:43:29.472885 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
234 12:43:29.472940 output: Architecture: AArch64
235 12:43:29.472993 output: Hash algo: crc32
236 12:43:29.473046 output: Hash value: cc4352de
237 12:43:29.473099 output: Image 2 (ramdisk-1)
238 12:43:29.473152 output: Description: unavailable
239 12:43:29.473205 output: Created: Mon Feb 5 12:43:29 2024
240 12:43:29.473258 output: Type: RAMDisk Image
241 12:43:29.473311 output: Compression: Unknown Compression
242 12:43:29.473365 output: Data Size: 98371715 Bytes = 96066.13 KiB = 93.81 MiB
243 12:43:29.473419 output: Architecture: AArch64
244 12:43:29.473472 output: OS: Linux
245 12:43:29.473526 output: Load Address: unavailable
246 12:43:29.473579 output: Entry Point: unavailable
247 12:43:29.473632 output: Hash algo: crc32
248 12:43:29.473685 output: Hash value: ebc2d623
249 12:43:29.473738 output: Default Configuration: 'conf-1'
250 12:43:29.473791 output: Configuration 0 (conf-1)
251 12:43:29.473844 output: Description: mt8192-asurada-spherion-r0
252 12:43:29.473897 output: Kernel: kernel-1
253 12:43:29.473964 output: Init Ramdisk: ramdisk-1
254 12:43:29.474021 output: FDT: fdt-1
255 12:43:29.474085 output: Loadables: kernel-1
256 12:43:29.474177 output:
257 12:43:29.474427 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
258 12:43:29.474557 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
259 12:43:29.474671 end: 1.5 prepare-tftp-overlay (duration 00:00:28) [common]
260 12:43:29.474766 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:31) [common]
261 12:43:29.474849 No LXC device requested
262 12:43:29.474927 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 12:43:29.475019 start: 1.7 deploy-device-env (timeout 00:09:31) [common]
264 12:43:29.475101 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 12:43:29.475170 Checking files for TFTP limit of 4294967296 bytes.
266 12:43:29.475649 end: 1 tftp-deploy (duration 00:00:29) [common]
267 12:43:29.475753 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 12:43:29.475852 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 12:43:29.475978 substitutions:
270 12:43:29.476048 - {DTB}: 12703558/tftp-deploy-so37e02b/dtb/mt8192-asurada-spherion-r0.dtb
271 12:43:29.476113 - {INITRD}: 12703558/tftp-deploy-so37e02b/ramdisk/ramdisk.cpio.gz
272 12:43:29.476174 - {KERNEL}: 12703558/tftp-deploy-so37e02b/kernel/Image
273 12:43:29.476232 - {LAVA_MAC}: None
274 12:43:29.476291 - {PRESEED_CONFIG}: None
275 12:43:29.476348 - {PRESEED_LOCAL}: None
276 12:43:29.476405 - {RAMDISK}: 12703558/tftp-deploy-so37e02b/ramdisk/ramdisk.cpio.gz
277 12:43:29.476462 - {ROOT_PART}: None
278 12:43:29.476517 - {ROOT}: None
279 12:43:29.476572 - {SERVER_IP}: 192.168.201.1
280 12:43:29.476628 - {TEE}: None
281 12:43:29.476683 Parsed boot commands:
282 12:43:29.476737 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 12:43:29.476905 Parsed boot commands: tftpboot 192.168.201.1 12703558/tftp-deploy-so37e02b/kernel/image.itb 12703558/tftp-deploy-so37e02b/kernel/cmdline
284 12:43:29.476998 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 12:43:29.477082 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 12:43:29.477172 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 12:43:29.477261 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 12:43:29.477333 Not connected, no need to disconnect.
289 12:43:29.477452 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 12:43:29.477578 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 12:43:29.477684 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
292 12:43:29.481071 Setting prompt string to ['lava-test: # ']
293 12:43:29.481451 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 12:43:29.481560 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 12:43:29.481658 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 12:43:29.481750 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 12:43:29.481977 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
298 12:43:34.630166 >> Command sent successfully.
299 12:43:34.640251 Returned 0 in 5 seconds
300 12:43:34.741521 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 12:43:34.743218 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 12:43:34.743792 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 12:43:34.744268 Setting prompt string to 'Starting depthcharge on Spherion...'
305 12:43:34.744653 Changing prompt to 'Starting depthcharge on Spherion...'
306 12:43:34.745125 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 12:43:34.746764 [Enter `^Ec?' for help]
308 12:43:34.906869
309 12:43:34.907403
310 12:43:34.907866 F0: 102B 0000
311 12:43:34.908349
312 12:43:34.908684 F3: 1001 0000 [0200]
313 12:43:34.909020
314 12:43:34.910103 F3: 1001 0000
315 12:43:34.910766
316 12:43:34.911256 F7: 102D 0000
317 12:43:34.911593
318 12:43:34.911906 F1: 0000 0000
319 12:43:34.912262
320 12:43:34.914185 V0: 0000 0000 [0001]
321 12:43:34.914700
322 12:43:34.915040 00: 0007 8000
323 12:43:34.915565
324 12:43:34.917622 01: 0000 0000
325 12:43:34.918142
326 12:43:34.918800 BP: 0C00 0209 [0000]
327 12:43:34.919414
328 12:43:34.922184 G0: 1182 0000
329 12:43:34.922851
330 12:43:34.923476 EC: 0000 0021 [4000]
331 12:43:34.924077
332 12:43:34.924684 S7: 0000 0000 [0000]
333 12:43:34.925282
334 12:43:34.926176 CC: 0000 0000 [0001]
335 12:43:34.926786
336 12:43:34.927373 T0: 0000 0040 [010F]
337 12:43:34.928664
338 12:43:34.929307 Jump to BL
339 12:43:34.929914
340 12:43:34.953367
341 12:43:34.954083
342 12:43:34.954717
343 12:43:34.961025 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 12:43:34.964537 ARM64: Exception handlers installed.
345 12:43:34.968181 ARM64: Testing exception
346 12:43:34.971684 ARM64: Done test exception
347 12:43:34.979131 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 12:43:34.985653 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 12:43:34.992910 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 12:43:35.003981 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 12:43:35.010590 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 12:43:35.020940 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 12:43:35.030950 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 12:43:35.037971 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 12:43:35.056037 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 12:43:35.059014 WDT: Last reset was cold boot
357 12:43:35.062915 SPI1(PAD0) initialized at 2873684 Hz
358 12:43:35.066114 SPI5(PAD0) initialized at 992727 Hz
359 12:43:35.069095 VBOOT: Loading verstage.
360 12:43:35.075948 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 12:43:35.079261 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 12:43:35.082624 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 12:43:35.085716 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 12:43:35.093217 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 12:43:35.099549 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 12:43:35.110517 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
367 12:43:35.110684
368 12:43:35.110804
369 12:43:35.120766 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 12:43:35.124021 ARM64: Exception handlers installed.
371 12:43:35.127412 ARM64: Testing exception
372 12:43:35.127510 ARM64: Done test exception
373 12:43:35.134088 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 12:43:35.137847 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 12:43:35.151799 Probing TPM: . done!
376 12:43:35.152231 TPM ready after 0 ms
377 12:43:35.158653 Connected to device vid:did:rid of 1ae0:0028:00
378 12:43:35.165566 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
379 12:43:35.169248 Initialized TPM device CR50 revision 0
380 12:43:35.234349 tlcl_send_startup: Startup return code is 0
381 12:43:35.234783 TPM: setup succeeded
382 12:43:35.246077 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 12:43:35.254826 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 12:43:35.265151 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 12:43:35.274245 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 12:43:35.277186 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 12:43:35.285282 in-header: 03 07 00 00 08 00 00 00
388 12:43:35.288896 in-data: aa e4 47 04 13 02 00 00
389 12:43:35.292732 Chrome EC: UHEPI supported
390 12:43:35.300309 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 12:43:35.304069 in-header: 03 ad 00 00 08 00 00 00
392 12:43:35.307591 in-data: 00 20 20 08 00 00 00 00
393 12:43:35.307732 Phase 1
394 12:43:35.311496 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 12:43:35.318532 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 12:43:35.322556 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 12:43:35.326399 Recovery requested (1009000e)
398 12:43:35.335837 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 12:43:35.341177 tlcl_extend: response is 0
400 12:43:35.350894 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 12:43:35.356164 tlcl_extend: response is 0
402 12:43:35.363078 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 12:43:35.383696 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
404 12:43:35.390513 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 12:43:35.391086
406 12:43:35.391465
407 12:43:35.400579 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 12:43:35.403864 ARM64: Exception handlers installed.
409 12:43:35.404342 ARM64: Testing exception
410 12:43:35.407214 ARM64: Done test exception
411 12:43:35.425747 pmic_efuse_setting: Set efuses in 11 msecs
412 12:43:35.433979 pmwrap_interface_init: Select PMIF_VLD_RDY
413 12:43:35.437270 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 12:43:35.441669 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 12:43:35.447862 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 12:43:35.451744 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 12:43:35.458509 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 12:43:35.462124 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 12:43:35.466026 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 12:43:35.473846 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 12:43:35.478118 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 12:43:35.481642 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 12:43:35.485072 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 12:43:35.488915 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 12:43:35.495536 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 12:43:35.502282 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 12:43:35.505504 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 12:43:35.512700 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 12:43:35.520731 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 12:43:35.523563 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 12:43:35.530554 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 12:43:35.533987 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 12:43:35.541329 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 12:43:35.545132 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 12:43:35.551632 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 12:43:35.558401 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 12:43:35.561663 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 12:43:35.568344 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 12:43:35.571397 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 12:43:35.578358 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 12:43:35.581866 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 12:43:35.588294 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 12:43:35.591648 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 12:43:35.598521 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 12:43:35.601875 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 12:43:35.608429 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 12:43:35.611945 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 12:43:35.618424 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 12:43:35.621884 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 12:43:35.628723 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 12:43:35.631840 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 12:43:35.635345 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 12:43:35.642377 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 12:43:35.645557 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 12:43:35.649332 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 12:43:35.652330 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 12:43:35.659279 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 12:43:35.662414 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 12:43:35.665846 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 12:43:35.672816 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 12:43:35.676116 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 12:43:35.679432 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 12:43:35.682968 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 12:43:35.692867 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 12:43:35.699349 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 12:43:35.706197 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 12:43:35.713027 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 12:43:35.719984 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 12:43:35.726583 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 12:43:35.729726 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 12:43:35.733195 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 12:43:35.741866 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x18
473 12:43:35.748062 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 12:43:35.751309 [RTC]rtc_osc_init,62: osc32con val = 0xde70
475 12:43:35.754753 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 12:43:35.766138 [RTC]rtc_get_frequency_meter,154: input=15, output=771
477 12:43:35.775432 [RTC]rtc_get_frequency_meter,154: input=23, output=957
478 12:43:35.785299 [RTC]rtc_get_frequency_meter,154: input=19, output=864
479 12:43:35.794526 [RTC]rtc_get_frequency_meter,154: input=17, output=817
480 12:43:35.803919 [RTC]rtc_get_frequency_meter,154: input=16, output=796
481 12:43:35.807637 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
482 12:43:35.814269 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
483 12:43:35.817431 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
484 12:43:35.820974 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
485 12:43:35.824368 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
486 12:43:35.827628 ADC[4]: Raw value=903245 ID=7
487 12:43:35.830606 ADC[3]: Raw value=213179 ID=1
488 12:43:35.831090 RAM Code: 0x71
489 12:43:35.837661 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
490 12:43:35.841088 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
491 12:43:35.850983 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
492 12:43:35.857422 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
493 12:43:35.861343 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
494 12:43:35.864376 in-header: 03 07 00 00 08 00 00 00
495 12:43:35.868054 in-data: aa e4 47 04 13 02 00 00
496 12:43:35.870789 Chrome EC: UHEPI supported
497 12:43:35.878207 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
498 12:43:35.880962 in-header: 03 ed 00 00 08 00 00 00
499 12:43:35.884428 in-data: 80 20 60 08 00 00 00 00
500 12:43:35.887731 MRC: failed to locate region type 0.
501 12:43:35.890872 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
502 12:43:35.894621 DRAM-K: Running full calibration
503 12:43:35.900860 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
504 12:43:35.904020 header.status = 0x0
505 12:43:35.907526 header.version = 0x6 (expected: 0x6)
506 12:43:35.911279 header.size = 0xd00 (expected: 0xd00)
507 12:43:35.911861 header.flags = 0x0
508 12:43:35.917754 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
509 12:43:35.935750 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
510 12:43:35.942481 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
511 12:43:35.945654 dram_init: ddr_geometry: 2
512 12:43:35.949075 [EMI] MDL number = 2
513 12:43:35.949590 [EMI] Get MDL freq = 0
514 12:43:35.952494 dram_init: ddr_type: 0
515 12:43:35.953150 is_discrete_lpddr4: 1
516 12:43:35.955734 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
517 12:43:35.956211
518 12:43:35.956588
519 12:43:35.959299 [Bian_co] ETT version 0.0.0.1
520 12:43:35.963194 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
521 12:43:35.963681
522 12:43:35.970196 dramc_set_vcore_voltage set vcore to 650000
523 12:43:35.970698 Read voltage for 800, 4
524 12:43:35.971077 Vio18 = 0
525 12:43:35.973998 Vcore = 650000
526 12:43:35.974487 Vdram = 0
527 12:43:35.974867 Vddq = 0
528 12:43:35.977356 Vmddr = 0
529 12:43:35.977988 dram_init: config_dvfs: 1
530 12:43:35.985202 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
531 12:43:35.988619 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
532 12:43:35.992551 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
533 12:43:35.996223 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
534 12:43:35.999800 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
535 12:43:36.003552 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
536 12:43:36.007223 MEM_TYPE=3, freq_sel=18
537 12:43:36.010632 sv_algorithm_assistance_LP4_1600
538 12:43:36.014615 ============ PULL DRAM RESETB DOWN ============
539 12:43:36.018254 ========== PULL DRAM RESETB DOWN end =========
540 12:43:36.021966 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
541 12:43:36.025281 ===================================
542 12:43:36.028976 LPDDR4 DRAM CONFIGURATION
543 12:43:36.032428 ===================================
544 12:43:36.032915 EX_ROW_EN[0] = 0x0
545 12:43:36.035443 EX_ROW_EN[1] = 0x0
546 12:43:36.035897 LP4Y_EN = 0x0
547 12:43:36.038683 WORK_FSP = 0x0
548 12:43:36.039116 WL = 0x2
549 12:43:36.042457 RL = 0x2
550 12:43:36.042984 BL = 0x2
551 12:43:36.045879 RPST = 0x0
552 12:43:36.046453 RD_PRE = 0x0
553 12:43:36.048843 WR_PRE = 0x1
554 12:43:36.049378 WR_PST = 0x0
555 12:43:36.052402 DBI_WR = 0x0
556 12:43:36.052936 DBI_RD = 0x0
557 12:43:36.055574 OTF = 0x1
558 12:43:36.058947 ===================================
559 12:43:36.062226 ===================================
560 12:43:36.062667 ANA top config
561 12:43:36.065675 ===================================
562 12:43:36.068885 DLL_ASYNC_EN = 0
563 12:43:36.072133 ALL_SLAVE_EN = 1
564 12:43:36.076227 NEW_RANK_MODE = 1
565 12:43:36.076788 DLL_IDLE_MODE = 1
566 12:43:36.079613 LP45_APHY_COMB_EN = 1
567 12:43:36.082967 TX_ODT_DIS = 1
568 12:43:36.086584 NEW_8X_MODE = 1
569 12:43:36.087141 ===================================
570 12:43:36.090431 ===================================
571 12:43:36.093972 data_rate = 1600
572 12:43:36.097834 CKR = 1
573 12:43:36.101650 DQ_P2S_RATIO = 8
574 12:43:36.102260 ===================================
575 12:43:36.105138 CA_P2S_RATIO = 8
576 12:43:36.108312 DQ_CA_OPEN = 0
577 12:43:36.111646 DQ_SEMI_OPEN = 0
578 12:43:36.114798 CA_SEMI_OPEN = 0
579 12:43:36.118116 CA_FULL_RATE = 0
580 12:43:36.118548 DQ_CKDIV4_EN = 1
581 12:43:36.121620 CA_CKDIV4_EN = 1
582 12:43:36.125080 CA_PREDIV_EN = 0
583 12:43:36.128401 PH8_DLY = 0
584 12:43:36.132059 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
585 12:43:36.134926 DQ_AAMCK_DIV = 4
586 12:43:36.135361 CA_AAMCK_DIV = 4
587 12:43:36.138312 CA_ADMCK_DIV = 4
588 12:43:36.141686 DQ_TRACK_CA_EN = 0
589 12:43:36.144934 CA_PICK = 800
590 12:43:36.148311 CA_MCKIO = 800
591 12:43:36.152208 MCKIO_SEMI = 0
592 12:43:36.155162 PLL_FREQ = 3068
593 12:43:36.155697 DQ_UI_PI_RATIO = 32
594 12:43:36.158136 CA_UI_PI_RATIO = 0
595 12:43:36.161775 ===================================
596 12:43:36.165246 ===================================
597 12:43:36.168765 memory_type:LPDDR4
598 12:43:36.172440 GP_NUM : 10
599 12:43:36.172992 SRAM_EN : 1
600 12:43:36.175470 MD32_EN : 0
601 12:43:36.178855 ===================================
602 12:43:36.179395 [ANA_INIT] >>>>>>>>>>>>>>
603 12:43:36.182355 <<<<<< [CONFIGURE PHASE]: ANA_TX
604 12:43:36.185751 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
605 12:43:36.189686 ===================================
606 12:43:36.193192 data_rate = 1600,PCW = 0X7600
607 12:43:36.196579 ===================================
608 12:43:36.200432 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
609 12:43:36.204078 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
610 12:43:36.211984 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
611 12:43:36.215117 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
612 12:43:36.218537 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
613 12:43:36.221996 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
614 12:43:36.222590 [ANA_INIT] flow start
615 12:43:36.225374 [ANA_INIT] PLL >>>>>>>>
616 12:43:36.228558 [ANA_INIT] PLL <<<<<<<<
617 12:43:36.231722 [ANA_INIT] MIDPI >>>>>>>>
618 12:43:36.232153 [ANA_INIT] MIDPI <<<<<<<<
619 12:43:36.235059 [ANA_INIT] DLL >>>>>>>>
620 12:43:36.235490 [ANA_INIT] flow end
621 12:43:36.242214 ============ LP4 DIFF to SE enter ============
622 12:43:36.245451 ============ LP4 DIFF to SE exit ============
623 12:43:36.248474 [ANA_INIT] <<<<<<<<<<<<<
624 12:43:36.251915 [Flow] Enable top DCM control >>>>>
625 12:43:36.255540 [Flow] Enable top DCM control <<<<<
626 12:43:36.256075 Enable DLL master slave shuffle
627 12:43:36.262162 ==============================================================
628 12:43:36.265283 Gating Mode config
629 12:43:36.268485 ==============================================================
630 12:43:36.272033 Config description:
631 12:43:36.282473 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
632 12:43:36.288782 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
633 12:43:36.292396 SELPH_MODE 0: By rank 1: By Phase
634 12:43:36.298880 ==============================================================
635 12:43:36.301903 GAT_TRACK_EN = 1
636 12:43:36.305055 RX_GATING_MODE = 2
637 12:43:36.308506 RX_GATING_TRACK_MODE = 2
638 12:43:36.311737 SELPH_MODE = 1
639 12:43:36.312218 PICG_EARLY_EN = 1
640 12:43:36.315407 VALID_LAT_VALUE = 1
641 12:43:36.322563 ==============================================================
642 12:43:36.325450 Enter into Gating configuration >>>>
643 12:43:36.329045 Exit from Gating configuration <<<<
644 12:43:36.331802 Enter into DVFS_PRE_config >>>>>
645 12:43:36.342069 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
646 12:43:36.345180 Exit from DVFS_PRE_config <<<<<
647 12:43:36.348735 Enter into PICG configuration >>>>
648 12:43:36.352211 Exit from PICG configuration <<<<
649 12:43:36.355106 [RX_INPUT] configuration >>>>>
650 12:43:36.358550 [RX_INPUT] configuration <<<<<
651 12:43:36.362032 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
652 12:43:36.368353 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
653 12:43:36.375139 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
654 12:43:36.382109 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
655 12:43:36.388753 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
656 12:43:36.391929 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
657 12:43:36.395636 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
658 12:43:36.401873 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
659 12:43:36.405757 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
660 12:43:36.409462 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
661 12:43:36.412811 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
662 12:43:36.419613 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
663 12:43:36.422872 ===================================
664 12:43:36.423477 LPDDR4 DRAM CONFIGURATION
665 12:43:36.426107 ===================================
666 12:43:36.429666 EX_ROW_EN[0] = 0x0
667 12:43:36.430287 EX_ROW_EN[1] = 0x0
668 12:43:36.432924 LP4Y_EN = 0x0
669 12:43:36.433507 WORK_FSP = 0x0
670 12:43:36.436336 WL = 0x2
671 12:43:36.436916 RL = 0x2
672 12:43:36.439394 BL = 0x2
673 12:43:36.442788 RPST = 0x0
674 12:43:36.443267 RD_PRE = 0x0
675 12:43:36.446501 WR_PRE = 0x1
676 12:43:36.447088 WR_PST = 0x0
677 12:43:36.449464 DBI_WR = 0x0
678 12:43:36.449956 DBI_RD = 0x0
679 12:43:36.452830 OTF = 0x1
680 12:43:36.456079 ===================================
681 12:43:36.459103 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
682 12:43:36.462546 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
683 12:43:36.466138 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
684 12:43:36.469422 ===================================
685 12:43:36.472461 LPDDR4 DRAM CONFIGURATION
686 12:43:36.476412 ===================================
687 12:43:36.479732 EX_ROW_EN[0] = 0x10
688 12:43:36.480304 EX_ROW_EN[1] = 0x0
689 12:43:36.482866 LP4Y_EN = 0x0
690 12:43:36.483343 WORK_FSP = 0x0
691 12:43:36.486316 WL = 0x2
692 12:43:36.486891 RL = 0x2
693 12:43:36.489283 BL = 0x2
694 12:43:36.489758 RPST = 0x0
695 12:43:36.493144 RD_PRE = 0x0
696 12:43:36.493718 WR_PRE = 0x1
697 12:43:36.496288 WR_PST = 0x0
698 12:43:36.496865 DBI_WR = 0x0
699 12:43:36.499410 DBI_RD = 0x0
700 12:43:36.499987 OTF = 0x1
701 12:43:36.502699 ===================================
702 12:43:36.509624 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
703 12:43:36.514513 nWR fixed to 40
704 12:43:36.517613 [ModeRegInit_LP4] CH0 RK0
705 12:43:36.518266 [ModeRegInit_LP4] CH0 RK1
706 12:43:36.521128 [ModeRegInit_LP4] CH1 RK0
707 12:43:36.524564 [ModeRegInit_LP4] CH1 RK1
708 12:43:36.525140 match AC timing 13
709 12:43:36.530841 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
710 12:43:36.534329 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
711 12:43:36.538205 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
712 12:43:36.544692 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
713 12:43:36.548223 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
714 12:43:36.548839 [EMI DOE] emi_dcm 0
715 12:43:36.554261 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
716 12:43:36.554780 ==
717 12:43:36.557980 Dram Type= 6, Freq= 0, CH_0, rank 0
718 12:43:36.561202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
719 12:43:36.561830 ==
720 12:43:36.567530 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
721 12:43:36.571109 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
722 12:43:36.581877 [CA 0] Center 38 (7~69) winsize 63
723 12:43:36.585511 [CA 1] Center 38 (7~69) winsize 63
724 12:43:36.588674 [CA 2] Center 35 (5~66) winsize 62
725 12:43:36.592078 [CA 3] Center 35 (5~66) winsize 62
726 12:43:36.595431 [CA 4] Center 35 (4~66) winsize 63
727 12:43:36.598931 [CA 5] Center 33 (3~64) winsize 62
728 12:43:36.599537
729 12:43:36.601987 [CmdBusTrainingLP45] Vref(ca) range 1: 32
730 12:43:36.602597
731 12:43:36.605365 [CATrainingPosCal] consider 1 rank data
732 12:43:36.609072 u2DelayCellTimex100 = 270/100 ps
733 12:43:36.612524 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
734 12:43:36.615605 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
735 12:43:36.622293 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
736 12:43:36.625573 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
737 12:43:36.629338 CA4 delay=35 (4~66),Diff = 2 PI (14 cell)
738 12:43:36.633012 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
739 12:43:36.633644
740 12:43:36.636490 CA PerBit enable=1, Macro0, CA PI delay=33
741 12:43:36.637120
742 12:43:36.640287 [CBTSetCACLKResult] CA Dly = 33
743 12:43:36.640900 CS Dly: 5 (0~36)
744 12:43:36.641399 ==
745 12:43:36.644203 Dram Type= 6, Freq= 0, CH_0, rank 1
746 12:43:36.647397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
747 12:43:36.647898 ==
748 12:43:36.654990 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
749 12:43:36.658276 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
750 12:43:36.669055 [CA 0] Center 38 (7~69) winsize 63
751 12:43:36.672804 [CA 1] Center 38 (7~69) winsize 63
752 12:43:36.676054 [CA 2] Center 36 (6~67) winsize 62
753 12:43:36.679765 [CA 3] Center 36 (5~67) winsize 63
754 12:43:36.683638 [CA 4] Center 35 (4~66) winsize 63
755 12:43:36.687101 [CA 5] Center 34 (4~65) winsize 62
756 12:43:36.687631
757 12:43:36.690879 [CmdBusTrainingLP45] Vref(ca) range 1: 32
758 12:43:36.691360
759 12:43:36.694953 [CATrainingPosCal] consider 2 rank data
760 12:43:36.695432 u2DelayCellTimex100 = 270/100 ps
761 12:43:36.698231 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
762 12:43:36.701996 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
763 12:43:36.706000 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
764 12:43:36.709788 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
765 12:43:36.714039 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
766 12:43:36.717709 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
767 12:43:36.718362
768 12:43:36.721514 CA PerBit enable=1, Macro0, CA PI delay=34
769 12:43:36.722152
770 12:43:36.724990 [CBTSetCACLKResult] CA Dly = 34
771 12:43:36.725563 CS Dly: 6 (0~38)
772 12:43:36.728349
773 12:43:36.728922 ----->DramcWriteLeveling(PI) begin...
774 12:43:36.731982 ==
775 12:43:36.732462 Dram Type= 6, Freq= 0, CH_0, rank 0
776 12:43:36.739788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
777 12:43:36.740352 ==
778 12:43:36.740730 Write leveling (Byte 0): 31 => 31
779 12:43:36.743176 Write leveling (Byte 1): 31 => 31
780 12:43:36.747278 DramcWriteLeveling(PI) end<-----
781 12:43:36.747853
782 12:43:36.748230 ==
783 12:43:36.750719 Dram Type= 6, Freq= 0, CH_0, rank 0
784 12:43:36.754362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
785 12:43:36.754941 ==
786 12:43:36.758507 [Gating] SW mode calibration
787 12:43:36.765349 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
788 12:43:36.769445 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
789 12:43:36.772858 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
790 12:43:36.780185 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
791 12:43:36.783604 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
792 12:43:36.787646 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:43:36.791270 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:43:36.794579 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:43:36.802341 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:43:36.806044 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:43:36.810003 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:43:36.813567 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:43:36.816885 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:43:36.824279 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:43:36.828006 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:43:36.831471 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:43:36.834940 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 12:43:36.839162 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 12:43:36.846529 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
806 12:43:36.850100 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
807 12:43:36.853840 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:43:36.857841 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:43:36.861095 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 12:43:36.868317 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 12:43:36.871777 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:43:36.875462 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 12:43:36.879794 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 12:43:36.883247 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
815 12:43:36.886798 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
816 12:43:36.894172 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 12:43:36.897935 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 12:43:36.901726 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 12:43:36.904961 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 12:43:36.908531 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 12:43:36.916711 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 12:43:36.920249 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
823 12:43:36.924388 0 10 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
824 12:43:36.927974 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
825 12:43:36.931564 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 12:43:36.935139 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:43:36.942720 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 12:43:36.946532 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 12:43:36.950311 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 12:43:36.954380 0 11 4 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
831 12:43:36.957988 0 11 8 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
832 12:43:36.963984 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
833 12:43:36.967345 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 12:43:36.970712 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 12:43:36.977366 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 12:43:36.980915 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 12:43:36.984167 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 12:43:36.991260 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
839 12:43:36.994212 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
840 12:43:36.997570 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:43:37.004188 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:43:37.007514 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:43:37.011043 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:43:37.014466 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:43:37.021284 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:43:37.024752 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:43:37.027987 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:43:37.034542 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 12:43:37.037711 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 12:43:37.041056 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 12:43:37.047588 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 12:43:37.051385 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 12:43:37.054427 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
854 12:43:37.061253 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
855 12:43:37.064508 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
856 12:43:37.068094 Total UI for P1: 0, mck2ui 16
857 12:43:37.071139 best dqsien dly found for B0: ( 0, 14, 2)
858 12:43:37.074450 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
859 12:43:37.078302 Total UI for P1: 0, mck2ui 16
860 12:43:37.081657 best dqsien dly found for B1: ( 0, 14, 8)
861 12:43:37.084634 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
862 12:43:37.088070 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
863 12:43:37.088543
864 12:43:37.091397 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
865 12:43:37.094733 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
866 12:43:37.098336 [Gating] SW calibration Done
867 12:43:37.098958 ==
868 12:43:37.101686 Dram Type= 6, Freq= 0, CH_0, rank 0
869 12:43:37.107960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
870 12:43:37.108440 ==
871 12:43:37.108815 RX Vref Scan: 0
872 12:43:37.109162
873 12:43:37.111379 RX Vref 0 -> 0, step: 1
874 12:43:37.111913
875 12:43:37.114718 RX Delay -130 -> 252, step: 16
876 12:43:37.118370 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
877 12:43:37.121280 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
878 12:43:37.124982 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
879 12:43:37.128184 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
880 12:43:37.134593 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
881 12:43:37.138194 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
882 12:43:37.141344 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
883 12:43:37.145011 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
884 12:43:37.148354 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
885 12:43:37.155012 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
886 12:43:37.158145 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
887 12:43:37.161874 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
888 12:43:37.165024 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
889 12:43:37.168454 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
890 12:43:37.174987 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
891 12:43:37.178506 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
892 12:43:37.179085 ==
893 12:43:37.181809 Dram Type= 6, Freq= 0, CH_0, rank 0
894 12:43:37.184780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
895 12:43:37.185258 ==
896 12:43:37.188646 DQS Delay:
897 12:43:37.189365 DQS0 = 0, DQS1 = 0
898 12:43:37.189792 DQM Delay:
899 12:43:37.191529 DQM0 = 91, DQM1 = 81
900 12:43:37.192113 DQ Delay:
901 12:43:37.194803 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
902 12:43:37.198254 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
903 12:43:37.201581 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
904 12:43:37.204804 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
905 12:43:37.205275
906 12:43:37.205643
907 12:43:37.206052 ==
908 12:43:37.207984 Dram Type= 6, Freq= 0, CH_0, rank 0
909 12:43:37.214960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
910 12:43:37.215540 ==
911 12:43:37.215917
912 12:43:37.216277
913 12:43:37.216613 TX Vref Scan disable
914 12:43:37.218352 == TX Byte 0 ==
915 12:43:37.221631 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
916 12:43:37.225075 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
917 12:43:37.228146 == TX Byte 1 ==
918 12:43:37.231954 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
919 12:43:37.235124 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
920 12:43:37.238580 ==
921 12:43:37.241759 Dram Type= 6, Freq= 0, CH_0, rank 0
922 12:43:37.245348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
923 12:43:37.245937 ==
924 12:43:37.257361 TX Vref=22, minBit 11, minWin=26, winSum=439
925 12:43:37.260364 TX Vref=24, minBit 6, minWin=27, winSum=441
926 12:43:37.263833 TX Vref=26, minBit 6, minWin=27, winSum=446
927 12:43:37.267413 TX Vref=28, minBit 8, minWin=27, winSum=452
928 12:43:37.270526 TX Vref=30, minBit 5, minWin=28, winSum=457
929 12:43:37.277236 TX Vref=32, minBit 3, minWin=28, winSum=456
930 12:43:37.280557 [TxChooseVref] Worse bit 5, Min win 28, Win sum 457, Final Vref 30
931 12:43:37.281035
932 12:43:37.283993 Final TX Range 1 Vref 30
933 12:43:37.284490
934 12:43:37.284859 ==
935 12:43:37.287109 Dram Type= 6, Freq= 0, CH_0, rank 0
936 12:43:37.290909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
937 12:43:37.291490 ==
938 12:43:37.293614
939 12:43:37.294118
940 12:43:37.294492 TX Vref Scan disable
941 12:43:37.297144 == TX Byte 0 ==
942 12:43:37.300774 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
943 12:43:37.303678 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
944 12:43:37.307041 == TX Byte 1 ==
945 12:43:37.310692 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
946 12:43:37.314017 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
947 12:43:37.316966
948 12:43:37.317437 [DATLAT]
949 12:43:37.317812 Freq=800, CH0 RK0
950 12:43:37.318218
951 12:43:37.320853 DATLAT Default: 0xa
952 12:43:37.321323 0, 0xFFFF, sum = 0
953 12:43:37.323852 1, 0xFFFF, sum = 0
954 12:43:37.324341 2, 0xFFFF, sum = 0
955 12:43:37.327284 3, 0xFFFF, sum = 0
956 12:43:37.327785 4, 0xFFFF, sum = 0
957 12:43:37.330488 5, 0xFFFF, sum = 0
958 12:43:37.330974 6, 0xFFFF, sum = 0
959 12:43:37.334050 7, 0xFFFF, sum = 0
960 12:43:37.334536 8, 0xFFFF, sum = 0
961 12:43:37.337489 9, 0x0, sum = 1
962 12:43:37.338021 10, 0x0, sum = 2
963 12:43:37.340833 11, 0x0, sum = 3
964 12:43:37.341316 12, 0x0, sum = 4
965 12:43:37.344215 best_step = 10
966 12:43:37.344788
967 12:43:37.345165 ==
968 12:43:37.347943 Dram Type= 6, Freq= 0, CH_0, rank 0
969 12:43:37.350590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
970 12:43:37.351117 ==
971 12:43:37.354324 RX Vref Scan: 1
972 12:43:37.354916
973 12:43:37.355412 Set Vref Range= 32 -> 127
974 12:43:37.355873
975 12:43:37.357462 RX Vref 32 -> 127, step: 1
976 12:43:37.358007
977 12:43:37.360778 RX Delay -79 -> 252, step: 8
978 12:43:37.361268
979 12:43:37.364109 Set Vref, RX VrefLevel [Byte0]: 32
980 12:43:37.367604 [Byte1]: 32
981 12:43:37.368191
982 12:43:37.370787 Set Vref, RX VrefLevel [Byte0]: 33
983 12:43:37.374208 [Byte1]: 33
984 12:43:37.377640
985 12:43:37.378249 Set Vref, RX VrefLevel [Byte0]: 34
986 12:43:37.380980 [Byte1]: 34
987 12:43:37.384806
988 12:43:37.385294 Set Vref, RX VrefLevel [Byte0]: 35
989 12:43:37.388142 [Byte1]: 35
990 12:43:37.392426
991 12:43:37.392919 Set Vref, RX VrefLevel [Byte0]: 36
992 12:43:37.395739 [Byte1]: 36
993 12:43:37.400271
994 12:43:37.400856 Set Vref, RX VrefLevel [Byte0]: 37
995 12:43:37.403372 [Byte1]: 37
996 12:43:37.408115
997 12:43:37.408604 Set Vref, RX VrefLevel [Byte0]: 38
998 12:43:37.411528 [Byte1]: 38
999 12:43:37.415186
1000 12:43:37.415760 Set Vref, RX VrefLevel [Byte0]: 39
1001 12:43:37.418511 [Byte1]: 39
1002 12:43:37.422711
1003 12:43:37.423203 Set Vref, RX VrefLevel [Byte0]: 40
1004 12:43:37.426099 [Byte1]: 40
1005 12:43:37.430526
1006 12:43:37.431103 Set Vref, RX VrefLevel [Byte0]: 41
1007 12:43:37.433913 [Byte1]: 41
1008 12:43:37.438572
1009 12:43:37.439245 Set Vref, RX VrefLevel [Byte0]: 42
1010 12:43:37.442324 [Byte1]: 42
1011 12:43:37.445927
1012 12:43:37.446564 Set Vref, RX VrefLevel [Byte0]: 43
1013 12:43:37.449226 [Byte1]: 43
1014 12:43:37.453622
1015 12:43:37.454136 Set Vref, RX VrefLevel [Byte0]: 44
1016 12:43:37.456811 [Byte1]: 44
1017 12:43:37.460728
1018 12:43:37.461203 Set Vref, RX VrefLevel [Byte0]: 45
1019 12:43:37.464135 [Byte1]: 45
1020 12:43:37.468078
1021 12:43:37.468641 Set Vref, RX VrefLevel [Byte0]: 46
1022 12:43:37.471237 [Byte1]: 46
1023 12:43:37.475956
1024 12:43:37.476538 Set Vref, RX VrefLevel [Byte0]: 47
1025 12:43:37.479242 [Byte1]: 47
1026 12:43:37.482826
1027 12:43:37.483297 Set Vref, RX VrefLevel [Byte0]: 48
1028 12:43:37.486324 [Byte1]: 48
1029 12:43:37.490892
1030 12:43:37.491453 Set Vref, RX VrefLevel [Byte0]: 49
1031 12:43:37.494236 [Byte1]: 49
1032 12:43:37.498447
1033 12:43:37.499009 Set Vref, RX VrefLevel [Byte0]: 50
1034 12:43:37.501569 [Byte1]: 50
1035 12:43:37.505732
1036 12:43:37.506353 Set Vref, RX VrefLevel [Byte0]: 51
1037 12:43:37.509212 [Byte1]: 51
1038 12:43:37.513469
1039 12:43:37.514074 Set Vref, RX VrefLevel [Byte0]: 52
1040 12:43:37.516494 [Byte1]: 52
1041 12:43:37.520918
1042 12:43:37.521491 Set Vref, RX VrefLevel [Byte0]: 53
1043 12:43:37.524200 [Byte1]: 53
1044 12:43:37.528648
1045 12:43:37.529242 Set Vref, RX VrefLevel [Byte0]: 54
1046 12:43:37.531853 [Byte1]: 54
1047 12:43:37.535759
1048 12:43:37.536293 Set Vref, RX VrefLevel [Byte0]: 55
1049 12:43:37.539216 [Byte1]: 55
1050 12:43:37.543667
1051 12:43:37.544233 Set Vref, RX VrefLevel [Byte0]: 56
1052 12:43:37.546775 [Byte1]: 56
1053 12:43:37.551229
1054 12:43:37.551696 Set Vref, RX VrefLevel [Byte0]: 57
1055 12:43:37.554011 [Byte1]: 57
1056 12:43:37.558549
1057 12:43:37.559149 Set Vref, RX VrefLevel [Byte0]: 58
1058 12:43:37.561637 [Byte1]: 58
1059 12:43:37.566052
1060 12:43:37.566621 Set Vref, RX VrefLevel [Byte0]: 59
1061 12:43:37.569349 [Byte1]: 59
1062 12:43:37.573586
1063 12:43:37.574148 Set Vref, RX VrefLevel [Byte0]: 60
1064 12:43:37.577044 [Byte1]: 60
1065 12:43:37.581199
1066 12:43:37.581668 Set Vref, RX VrefLevel [Byte0]: 61
1067 12:43:37.585004 [Byte1]: 61
1068 12:43:37.588928
1069 12:43:37.589500 Set Vref, RX VrefLevel [Byte0]: 62
1070 12:43:37.592360 [Byte1]: 62
1071 12:43:37.596566
1072 12:43:37.597136 Set Vref, RX VrefLevel [Byte0]: 63
1073 12:43:37.599873 [Byte1]: 63
1074 12:43:37.604013
1075 12:43:37.604579 Set Vref, RX VrefLevel [Byte0]: 64
1076 12:43:37.607194 [Byte1]: 64
1077 12:43:37.611438
1078 12:43:37.612003 Set Vref, RX VrefLevel [Byte0]: 65
1079 12:43:37.614849 [Byte1]: 65
1080 12:43:37.619170
1081 12:43:37.619775 Set Vref, RX VrefLevel [Byte0]: 66
1082 12:43:37.622172 [Byte1]: 66
1083 12:43:37.626441
1084 12:43:37.626909 Set Vref, RX VrefLevel [Byte0]: 67
1085 12:43:37.629907 [Byte1]: 67
1086 12:43:37.634047
1087 12:43:37.634514 Set Vref, RX VrefLevel [Byte0]: 68
1088 12:43:37.637394 [Byte1]: 68
1089 12:43:37.641742
1090 12:43:37.642376 Set Vref, RX VrefLevel [Byte0]: 69
1091 12:43:37.644992 [Byte1]: 69
1092 12:43:37.649128
1093 12:43:37.649611 Set Vref, RX VrefLevel [Byte0]: 70
1094 12:43:37.652285 [Byte1]: 70
1095 12:43:37.656726
1096 12:43:37.657287 Set Vref, RX VrefLevel [Byte0]: 71
1097 12:43:37.660000 [Byte1]: 71
1098 12:43:37.664609
1099 12:43:37.665204 Set Vref, RX VrefLevel [Byte0]: 72
1100 12:43:37.667686 [Byte1]: 72
1101 12:43:37.671902
1102 12:43:37.672488 Set Vref, RX VrefLevel [Byte0]: 73
1103 12:43:37.674942 [Byte1]: 73
1104 12:43:37.679167
1105 12:43:37.679725 Set Vref, RX VrefLevel [Byte0]: 74
1106 12:43:37.682379 [Byte1]: 74
1107 12:43:37.686762
1108 12:43:37.687226 Set Vref, RX VrefLevel [Byte0]: 75
1109 12:43:37.690029 [Byte1]: 75
1110 12:43:37.694742
1111 12:43:37.695311 Set Vref, RX VrefLevel [Byte0]: 76
1112 12:43:37.698153 [Byte1]: 76
1113 12:43:37.702116
1114 12:43:37.702725 Final RX Vref Byte 0 = 61 to rank0
1115 12:43:37.705448 Final RX Vref Byte 1 = 55 to rank0
1116 12:43:37.708568 Final RX Vref Byte 0 = 61 to rank1
1117 12:43:37.712190 Final RX Vref Byte 1 = 55 to rank1==
1118 12:43:37.715762 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 12:43:37.721897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 12:43:37.722489 ==
1121 12:43:37.722859 DQS Delay:
1122 12:43:37.723200 DQS0 = 0, DQS1 = 0
1123 12:43:37.725149 DQM Delay:
1124 12:43:37.725613 DQM0 = 93, DQM1 = 81
1125 12:43:37.728497 DQ Delay:
1126 12:43:37.731884 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1127 12:43:37.735098 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1128 12:43:37.738664 DQ8 =76, DQ9 =72, DQ10 =80, DQ11 =76
1129 12:43:37.741878 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1130 12:43:37.742513
1131 12:43:37.742894
1132 12:43:37.748979 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c37, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1133 12:43:37.751847 CH0 RK0: MR19=606, MR18=3C37
1134 12:43:37.758756 CH0_RK0: MR19=0x606, MR18=0x3C37, DQSOSC=394, MR23=63, INC=95, DEC=63
1135 12:43:37.759316
1136 12:43:37.761975 ----->DramcWriteLeveling(PI) begin...
1137 12:43:37.762455 ==
1138 12:43:37.765388 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 12:43:37.768383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 12:43:37.768856 ==
1141 12:43:37.772473 Write leveling (Byte 0): 31 => 31
1142 12:43:37.775851 Write leveling (Byte 1): 28 => 28
1143 12:43:37.778966 DramcWriteLeveling(PI) end<-----
1144 12:43:37.779414
1145 12:43:37.779751 ==
1146 12:43:37.781841 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 12:43:37.785579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 12:43:37.786137 ==
1149 12:43:37.789182 [Gating] SW mode calibration
1150 12:43:37.795760 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 12:43:37.802627 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 12:43:37.805470 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 12:43:37.809094 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1154 12:43:37.815603 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 12:43:37.819249 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 12:43:37.822131 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 12:43:37.829068 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 12:43:37.832509 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 12:43:37.876635 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 12:43:37.877267 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 12:43:37.877652 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 12:43:37.878054 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 12:43:37.878842 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:43:37.879305 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:43:37.879676 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:43:37.880023 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:43:37.880438 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 12:43:37.880933 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:43:37.920703 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1170 12:43:37.921212 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 12:43:37.921558 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 12:43:37.921878 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 12:43:37.922574 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 12:43:37.922923 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 12:43:37.923231 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:43:37.923528 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:43:37.923823 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1178 12:43:37.924114 0 9 8 | B1->B0 | 2e2e 3333 | 1 1 | (0 0) (1 1)
1179 12:43:37.963961 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 12:43:37.964059 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 12:43:37.964134 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 12:43:37.964393 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 12:43:37.964470 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 12:43:37.964796 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 12:43:37.965078 0 10 4 | B1->B0 | 3434 3030 | 0 0 | (0 1) (1 0)
1186 12:43:37.965160 0 10 8 | B1->B0 | 2e2e 2525 | 0 0 | (1 0) (0 0)
1187 12:43:37.965417 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 12:43:37.965885 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 12:43:37.969417 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 12:43:37.972533 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 12:43:37.975943 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 12:43:37.979458 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 12:43:37.985909 0 11 4 | B1->B0 | 2a2a 3333 | 1 0 | (0 0) (0 0)
1194 12:43:37.989351 0 11 8 | B1->B0 | 3939 4545 | 0 0 | (0 0) (0 0)
1195 12:43:37.992605 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 12:43:37.999432 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 12:43:38.002887 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 12:43:38.006082 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 12:43:38.013406 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 12:43:38.016708 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1201 12:43:38.020972 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1202 12:43:38.024902 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1203 12:43:38.028191 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 12:43:38.034892 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 12:43:38.038107 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 12:43:38.041976 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 12:43:38.045353 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 12:43:38.052162 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 12:43:38.055450 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 12:43:38.058862 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 12:43:38.065603 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 12:43:38.069091 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 12:43:38.072076 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 12:43:38.078704 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 12:43:38.082479 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 12:43:38.085990 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 12:43:38.092283 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 12:43:38.095601 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 12:43:38.099141 Total UI for P1: 0, mck2ui 16
1220 12:43:38.102559 best dqsien dly found for B0: ( 0, 14, 6)
1221 12:43:38.105812 Total UI for P1: 0, mck2ui 16
1222 12:43:38.109323 best dqsien dly found for B1: ( 0, 14, 6)
1223 12:43:38.112617 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1224 12:43:38.116048 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1225 12:43:38.116452
1226 12:43:38.119084 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1227 12:43:38.122406 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1228 12:43:38.125887 [Gating] SW calibration Done
1229 12:43:38.126421 ==
1230 12:43:38.129168 Dram Type= 6, Freq= 0, CH_0, rank 1
1231 12:43:38.132587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1232 12:43:38.133094 ==
1233 12:43:38.135965 RX Vref Scan: 0
1234 12:43:38.136485
1235 12:43:38.136980 RX Vref 0 -> 0, step: 1
1236 12:43:38.137448
1237 12:43:38.139342 RX Delay -130 -> 252, step: 16
1238 12:43:38.142789 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1239 12:43:38.149320 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1240 12:43:38.152561 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1241 12:43:38.155918 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1242 12:43:38.159414 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1243 12:43:38.162640 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1244 12:43:38.169374 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1245 12:43:38.172427 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1246 12:43:38.176084 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1247 12:43:38.179173 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1248 12:43:38.182695 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1249 12:43:38.189287 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1250 12:43:38.192832 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1251 12:43:38.196363 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
1252 12:43:38.199488 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1253 12:43:38.203104 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1254 12:43:38.206411 ==
1255 12:43:38.210143 Dram Type= 6, Freq= 0, CH_0, rank 1
1256 12:43:38.212743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1257 12:43:38.213171 ==
1258 12:43:38.213502 DQS Delay:
1259 12:43:38.216050 DQS0 = 0, DQS1 = 0
1260 12:43:38.216472 DQM Delay:
1261 12:43:38.219499 DQM0 = 89, DQM1 = 80
1262 12:43:38.219922 DQ Delay:
1263 12:43:38.223040 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1264 12:43:38.226334 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1265 12:43:38.229662 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1266 12:43:38.233117 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1267 12:43:38.233539
1268 12:43:38.233869
1269 12:43:38.234215 ==
1270 12:43:38.236148 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 12:43:38.239514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1272 12:43:38.239939 ==
1273 12:43:38.240271
1274 12:43:38.240581
1275 12:43:38.242884 TX Vref Scan disable
1276 12:43:38.246282 == TX Byte 0 ==
1277 12:43:38.249852 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1278 12:43:38.252984 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1279 12:43:38.256119 == TX Byte 1 ==
1280 12:43:38.259557 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1281 12:43:38.262923 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1282 12:43:38.263350 ==
1283 12:43:38.266259 Dram Type= 6, Freq= 0, CH_0, rank 1
1284 12:43:38.269907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1285 12:43:38.273124 ==
1286 12:43:38.284166 TX Vref=22, minBit 8, minWin=27, winSum=444
1287 12:43:38.287912 TX Vref=24, minBit 3, minWin=27, winSum=450
1288 12:43:38.290904 TX Vref=26, minBit 8, minWin=27, winSum=450
1289 12:43:38.294500 TX Vref=28, minBit 8, minWin=27, winSum=453
1290 12:43:38.297745 TX Vref=30, minBit 8, minWin=27, winSum=454
1291 12:43:38.304224 TX Vref=32, minBit 8, minWin=27, winSum=453
1292 12:43:38.307600 [TxChooseVref] Worse bit 8, Min win 27, Win sum 454, Final Vref 30
1293 12:43:38.308025
1294 12:43:38.311015 Final TX Range 1 Vref 30
1295 12:43:38.311439
1296 12:43:38.311772 ==
1297 12:43:38.314459 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 12:43:38.317627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 12:43:38.317709 ==
1300 12:43:38.317773
1301 12:43:38.320431
1302 12:43:38.320519 TX Vref Scan disable
1303 12:43:38.324249 == TX Byte 0 ==
1304 12:43:38.327144 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1305 12:43:38.330951 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1306 12:43:38.334283 == TX Byte 1 ==
1307 12:43:38.337852 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1308 12:43:38.340538 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1309 12:43:38.344208
1310 12:43:38.344329 [DATLAT]
1311 12:43:38.344423 Freq=800, CH0 RK1
1312 12:43:38.344513
1313 12:43:38.347481 DATLAT Default: 0xa
1314 12:43:38.347602 0, 0xFFFF, sum = 0
1315 12:43:38.351121 1, 0xFFFF, sum = 0
1316 12:43:38.351258 2, 0xFFFF, sum = 0
1317 12:43:38.354313 3, 0xFFFF, sum = 0
1318 12:43:38.354467 4, 0xFFFF, sum = 0
1319 12:43:38.357554 5, 0xFFFF, sum = 0
1320 12:43:38.360826 6, 0xFFFF, sum = 0
1321 12:43:38.361002 7, 0xFFFF, sum = 0
1322 12:43:38.364289 8, 0xFFFF, sum = 0
1323 12:43:38.364492 9, 0x0, sum = 1
1324 12:43:38.364653 10, 0x0, sum = 2
1325 12:43:38.367704 11, 0x0, sum = 3
1326 12:43:38.367906 12, 0x0, sum = 4
1327 12:43:38.370901 best_step = 10
1328 12:43:38.371140
1329 12:43:38.371326 ==
1330 12:43:38.374458 Dram Type= 6, Freq= 0, CH_0, rank 1
1331 12:43:38.377858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1332 12:43:38.378191 ==
1333 12:43:38.381358 RX Vref Scan: 0
1334 12:43:38.381737
1335 12:43:38.382076 RX Vref 0 -> 0, step: 1
1336 12:43:38.382365
1337 12:43:38.384308 RX Delay -95 -> 252, step: 8
1338 12:43:38.391384 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1339 12:43:38.394330 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1340 12:43:38.397886 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1341 12:43:38.401070 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1342 12:43:38.404543 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1343 12:43:38.411365 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1344 12:43:38.414258 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1345 12:43:38.417729 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1346 12:43:38.421132 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1347 12:43:38.424717 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1348 12:43:38.431363 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1349 12:43:38.434981 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1350 12:43:38.437780 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1351 12:43:38.441616 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1352 12:43:38.444705 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1353 12:43:38.451356 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1354 12:43:38.451770 ==
1355 12:43:38.454881 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 12:43:38.458219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 12:43:38.458635 ==
1358 12:43:38.458958 DQS Delay:
1359 12:43:38.461444 DQS0 = 0, DQS1 = 0
1360 12:43:38.461855 DQM Delay:
1361 12:43:38.464514 DQM0 = 90, DQM1 = 83
1362 12:43:38.464925 DQ Delay:
1363 12:43:38.467808 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1364 12:43:38.471074 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1365 12:43:38.474904 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =80
1366 12:43:38.478112 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =88
1367 12:43:38.478527
1368 12:43:38.478851
1369 12:43:38.484603 [DQSOSCAuto] RK1, (LSB)MR18= 0x411b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
1370 12:43:38.488035 CH0 RK1: MR19=606, MR18=411B
1371 12:43:38.494580 CH0_RK1: MR19=0x606, MR18=0x411B, DQSOSC=393, MR23=63, INC=95, DEC=63
1372 12:43:38.498279 [RxdqsGatingPostProcess] freq 800
1373 12:43:38.504749 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1374 12:43:38.507804 Pre-setting of DQS Precalculation
1375 12:43:38.511424 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1376 12:43:38.511842 ==
1377 12:43:38.514583 Dram Type= 6, Freq= 0, CH_1, rank 0
1378 12:43:38.518160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1379 12:43:38.518581 ==
1380 12:43:38.524881 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1381 12:43:38.531267 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1382 12:43:38.539382 [CA 0] Center 36 (6~67) winsize 62
1383 12:43:38.543127 [CA 1] Center 36 (6~67) winsize 62
1384 12:43:38.546400 [CA 2] Center 34 (4~65) winsize 62
1385 12:43:38.549715 [CA 3] Center 34 (3~65) winsize 63
1386 12:43:38.553090 [CA 4] Center 34 (4~65) winsize 62
1387 12:43:38.556535 [CA 5] Center 33 (3~64) winsize 62
1388 12:43:38.556949
1389 12:43:38.559709 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1390 12:43:38.560121
1391 12:43:38.563156 [CATrainingPosCal] consider 1 rank data
1392 12:43:38.566435 u2DelayCellTimex100 = 270/100 ps
1393 12:43:38.569743 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1394 12:43:38.572620 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1395 12:43:38.579743 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1396 12:43:38.583129 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1397 12:43:38.586399 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1398 12:43:38.589544 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1399 12:43:38.590261
1400 12:43:38.592923 CA PerBit enable=1, Macro0, CA PI delay=33
1401 12:43:38.593350
1402 12:43:38.596070 [CBTSetCACLKResult] CA Dly = 33
1403 12:43:38.596518 CS Dly: 4 (0~35)
1404 12:43:38.596863 ==
1405 12:43:38.599329 Dram Type= 6, Freq= 0, CH_1, rank 1
1406 12:43:38.606373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1407 12:43:38.606811 ==
1408 12:43:38.609617 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1409 12:43:38.616038 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1410 12:43:38.625576 [CA 0] Center 37 (7~67) winsize 61
1411 12:43:38.629014 [CA 1] Center 37 (6~68) winsize 63
1412 12:43:38.632450 [CA 2] Center 35 (4~66) winsize 63
1413 12:43:38.635916 [CA 3] Center 34 (4~65) winsize 62
1414 12:43:38.638837 [CA 4] Center 34 (4~65) winsize 62
1415 12:43:38.642393 [CA 5] Center 34 (4~65) winsize 62
1416 12:43:38.642821
1417 12:43:38.646061 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1418 12:43:38.646492
1419 12:43:38.649236 [CATrainingPosCal] consider 2 rank data
1420 12:43:38.652742 u2DelayCellTimex100 = 270/100 ps
1421 12:43:38.655793 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1422 12:43:38.659076 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1423 12:43:38.665619 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1424 12:43:38.669069 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1425 12:43:38.672655 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1426 12:43:38.675801 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1427 12:43:38.676258
1428 12:43:38.679381 CA PerBit enable=1, Macro0, CA PI delay=34
1429 12:43:38.679812
1430 12:43:38.682913 [CBTSetCACLKResult] CA Dly = 34
1431 12:43:38.683340 CS Dly: 5 (0~38)
1432 12:43:38.683674
1433 12:43:38.686653 ----->DramcWriteLeveling(PI) begin...
1434 12:43:38.687087 ==
1435 12:43:38.690005 Dram Type= 6, Freq= 0, CH_1, rank 0
1436 12:43:38.694046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1437 12:43:38.694478 ==
1438 12:43:38.697526 Write leveling (Byte 0): 26 => 26
1439 12:43:38.701399 Write leveling (Byte 1): 28 => 28
1440 12:43:38.704662 DramcWriteLeveling(PI) end<-----
1441 12:43:38.705117
1442 12:43:38.705544 ==
1443 12:43:38.708704 Dram Type= 6, Freq= 0, CH_1, rank 0
1444 12:43:38.712073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1445 12:43:38.712513 ==
1446 12:43:38.715846 [Gating] SW mode calibration
1447 12:43:38.722564 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1448 12:43:38.725828 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1449 12:43:38.732263 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1450 12:43:38.735999 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1451 12:43:38.739044 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 12:43:38.745709 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 12:43:38.749231 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 12:43:38.752775 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 12:43:38.759400 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 12:43:38.762265 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 12:43:38.765583 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 12:43:38.772329 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:43:38.775929 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 12:43:38.779282 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 12:43:38.782743 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:43:38.789035 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:43:38.793079 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:43:38.796008 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 12:43:38.802779 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:43:38.806329 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1467 12:43:38.809712 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 12:43:38.815895 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 12:43:38.819363 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 12:43:38.822642 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 12:43:38.829429 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 12:43:38.832823 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:43:38.836328 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:43:38.842968 0 9 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1475 12:43:38.846401 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1476 12:43:38.849194 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 12:43:38.852943 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 12:43:38.859372 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 12:43:38.862387 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 12:43:38.865851 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 12:43:38.872418 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 12:43:38.875860 0 10 4 | B1->B0 | 2b2b 2424 | 0 0 | (0 0) (0 0)
1483 12:43:38.879094 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 12:43:38.886040 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 12:43:38.888958 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 12:43:38.892284 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 12:43:38.899142 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 12:43:38.902566 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 12:43:38.905851 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1490 12:43:38.912516 0 11 4 | B1->B0 | 2a2a 3b3b | 0 0 | (0 0) (0 0)
1491 12:43:38.915936 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 12:43:38.919286 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 12:43:38.925997 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 12:43:38.929003 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 12:43:38.932705 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 12:43:38.939209 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 12:43:38.942771 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 12:43:38.945864 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1499 12:43:38.949259 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 12:43:38.955916 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 12:43:38.959006 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 12:43:38.962530 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 12:43:38.969690 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 12:43:38.972498 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 12:43:38.975836 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 12:43:38.982434 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 12:43:38.986074 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 12:43:38.989292 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 12:43:38.996061 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 12:43:38.999494 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 12:43:39.003115 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 12:43:39.009192 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 12:43:39.012832 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 12:43:39.015773 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1515 12:43:39.022634 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1516 12:43:39.022732 Total UI for P1: 0, mck2ui 16
1517 12:43:39.025904 best dqsien dly found for B0: ( 0, 14, 4)
1518 12:43:39.032798 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 12:43:39.036237 Total UI for P1: 0, mck2ui 16
1520 12:43:39.039130 best dqsien dly found for B1: ( 0, 14, 6)
1521 12:43:39.042543 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1522 12:43:39.046211 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1523 12:43:39.046310
1524 12:43:39.049416 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1525 12:43:39.052517 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1526 12:43:39.056015 [Gating] SW calibration Done
1527 12:43:39.056131 ==
1528 12:43:39.059374 Dram Type= 6, Freq= 0, CH_1, rank 0
1529 12:43:39.062787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1530 12:43:39.062916 ==
1531 12:43:39.066145 RX Vref Scan: 0
1532 12:43:39.066285
1533 12:43:39.066424 RX Vref 0 -> 0, step: 1
1534 12:43:39.066555
1535 12:43:39.069730 RX Delay -130 -> 252, step: 16
1536 12:43:39.076384 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1537 12:43:39.079793 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1538 12:43:39.083129 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1539 12:43:39.086486 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1540 12:43:39.089742 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1541 12:43:39.093385 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1542 12:43:39.100140 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1543 12:43:39.103263 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1544 12:43:39.106549 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1545 12:43:39.110031 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1546 12:43:39.113179 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1547 12:43:39.120005 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1548 12:43:39.123265 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1549 12:43:39.126567 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1550 12:43:39.129884 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1551 12:43:39.136526 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1552 12:43:39.137090 ==
1553 12:43:39.139613 Dram Type= 6, Freq= 0, CH_1, rank 0
1554 12:43:39.142946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1555 12:43:39.143393 ==
1556 12:43:39.143926 DQS Delay:
1557 12:43:39.146357 DQS0 = 0, DQS1 = 0
1558 12:43:39.146782 DQM Delay:
1559 12:43:39.149546 DQM0 = 91, DQM1 = 87
1560 12:43:39.149999 DQ Delay:
1561 12:43:39.153112 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =93
1562 12:43:39.156245 DQ4 =93, DQ5 =101, DQ6 =101, DQ7 =93
1563 12:43:39.159420 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1564 12:43:39.163140 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1565 12:43:39.163568
1566 12:43:39.163902
1567 12:43:39.164210 ==
1568 12:43:39.166494 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 12:43:39.169496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 12:43:39.170142 ==
1571 12:43:39.170550
1572 12:43:39.170898
1573 12:43:39.173078 TX Vref Scan disable
1574 12:43:39.176450 == TX Byte 0 ==
1575 12:43:39.179948 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1576 12:43:39.182990 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1577 12:43:39.186531 == TX Byte 1 ==
1578 12:43:39.189774 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1579 12:43:39.193114 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1580 12:43:39.193540 ==
1581 12:43:39.196747 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 12:43:39.200148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 12:43:39.203116 ==
1584 12:43:39.214561 TX Vref=22, minBit 10, minWin=27, winSum=451
1585 12:43:39.218067 TX Vref=24, minBit 15, minWin=27, winSum=456
1586 12:43:39.221132 TX Vref=26, minBit 10, minWin=27, winSum=456
1587 12:43:39.224678 TX Vref=28, minBit 15, minWin=27, winSum=459
1588 12:43:39.227996 TX Vref=30, minBit 8, minWin=28, winSum=460
1589 12:43:39.234647 TX Vref=32, minBit 12, minWin=27, winSum=456
1590 12:43:39.238151 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 30
1591 12:43:39.238559
1592 12:43:39.241294 Final TX Range 1 Vref 30
1593 12:43:39.241812
1594 12:43:39.242329 ==
1595 12:43:39.244492 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 12:43:39.247925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 12:43:39.251388 ==
1598 12:43:39.251808
1599 12:43:39.252136
1600 12:43:39.252446 TX Vref Scan disable
1601 12:43:39.254734 == TX Byte 0 ==
1602 12:43:39.258419 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1603 12:43:39.261804 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1604 12:43:39.265258 == TX Byte 1 ==
1605 12:43:39.268751 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1606 12:43:39.272440 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1607 12:43:39.272901
1608 12:43:39.275431 [DATLAT]
1609 12:43:39.275856 Freq=800, CH1 RK0
1610 12:43:39.276197
1611 12:43:39.278940 DATLAT Default: 0xa
1612 12:43:39.279364 0, 0xFFFF, sum = 0
1613 12:43:39.282238 1, 0xFFFF, sum = 0
1614 12:43:39.282693 2, 0xFFFF, sum = 0
1615 12:43:39.285213 3, 0xFFFF, sum = 0
1616 12:43:39.285656 4, 0xFFFF, sum = 0
1617 12:43:39.288708 5, 0xFFFF, sum = 0
1618 12:43:39.289142 6, 0xFFFF, sum = 0
1619 12:43:39.291988 7, 0xFFFF, sum = 0
1620 12:43:39.292423 8, 0xFFFF, sum = 0
1621 12:43:39.295695 9, 0x0, sum = 1
1622 12:43:39.296130 10, 0x0, sum = 2
1623 12:43:39.299058 11, 0x0, sum = 3
1624 12:43:39.299492 12, 0x0, sum = 4
1625 12:43:39.302128 best_step = 10
1626 12:43:39.302556
1627 12:43:39.302897 ==
1628 12:43:39.305497 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 12:43:39.309190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 12:43:39.309621 ==
1631 12:43:39.309996 RX Vref Scan: 1
1632 12:43:39.312211
1633 12:43:39.312635 Set Vref Range= 32 -> 127
1634 12:43:39.312976
1635 12:43:39.315557 RX Vref 32 -> 127, step: 1
1636 12:43:39.315984
1637 12:43:39.319007 RX Delay -79 -> 252, step: 8
1638 12:43:39.319440
1639 12:43:39.322034 Set Vref, RX VrefLevel [Byte0]: 32
1640 12:43:39.325269 [Byte1]: 32
1641 12:43:39.325697
1642 12:43:39.328883 Set Vref, RX VrefLevel [Byte0]: 33
1643 12:43:39.332194 [Byte1]: 33
1644 12:43:39.332623
1645 12:43:39.335537 Set Vref, RX VrefLevel [Byte0]: 34
1646 12:43:39.339116 [Byte1]: 34
1647 12:43:39.342464
1648 12:43:39.342891 Set Vref, RX VrefLevel [Byte0]: 35
1649 12:43:39.345691 [Byte1]: 35
1650 12:43:39.350370
1651 12:43:39.350795 Set Vref, RX VrefLevel [Byte0]: 36
1652 12:43:39.353433 [Byte1]: 36
1653 12:43:39.357792
1654 12:43:39.358267 Set Vref, RX VrefLevel [Byte0]: 37
1655 12:43:39.361099 [Byte1]: 37
1656 12:43:39.365170
1657 12:43:39.365253 Set Vref, RX VrefLevel [Byte0]: 38
1658 12:43:39.368427 [Byte1]: 38
1659 12:43:39.372810
1660 12:43:39.372892 Set Vref, RX VrefLevel [Byte0]: 39
1661 12:43:39.375678 [Byte1]: 39
1662 12:43:39.379916
1663 12:43:39.380003 Set Vref, RX VrefLevel [Byte0]: 40
1664 12:43:39.383641 [Byte1]: 40
1665 12:43:39.387437
1666 12:43:39.387537 Set Vref, RX VrefLevel [Byte0]: 41
1667 12:43:39.390814 [Byte1]: 41
1668 12:43:39.395242
1669 12:43:39.395326 Set Vref, RX VrefLevel [Byte0]: 42
1670 12:43:39.398102 [Byte1]: 42
1671 12:43:39.402864
1672 12:43:39.402947 Set Vref, RX VrefLevel [Byte0]: 43
1673 12:43:39.405926 [Byte1]: 43
1674 12:43:39.410149
1675 12:43:39.410232 Set Vref, RX VrefLevel [Byte0]: 44
1676 12:43:39.413402 [Byte1]: 44
1677 12:43:39.417840
1678 12:43:39.417924 Set Vref, RX VrefLevel [Byte0]: 45
1679 12:43:39.421211 [Byte1]: 45
1680 12:43:39.425243
1681 12:43:39.425329 Set Vref, RX VrefLevel [Byte0]: 46
1682 12:43:39.428775 [Byte1]: 46
1683 12:43:39.432867
1684 12:43:39.432951 Set Vref, RX VrefLevel [Byte0]: 47
1685 12:43:39.436141 [Byte1]: 47
1686 12:43:39.440626
1687 12:43:39.440709 Set Vref, RX VrefLevel [Byte0]: 48
1688 12:43:39.443486 [Byte1]: 48
1689 12:43:39.447885
1690 12:43:39.447969 Set Vref, RX VrefLevel [Byte0]: 49
1691 12:43:39.451053 [Byte1]: 49
1692 12:43:39.455628
1693 12:43:39.455711 Set Vref, RX VrefLevel [Byte0]: 50
1694 12:43:39.458714 [Byte1]: 50
1695 12:43:39.462911
1696 12:43:39.462994 Set Vref, RX VrefLevel [Byte0]: 51
1697 12:43:39.466380 [Byte1]: 51
1698 12:43:39.470731
1699 12:43:39.470814 Set Vref, RX VrefLevel [Byte0]: 52
1700 12:43:39.473796 [Byte1]: 52
1701 12:43:39.478058
1702 12:43:39.478141 Set Vref, RX VrefLevel [Byte0]: 53
1703 12:43:39.481472 [Byte1]: 53
1704 12:43:39.485561
1705 12:43:39.485644 Set Vref, RX VrefLevel [Byte0]: 54
1706 12:43:39.489262 [Byte1]: 54
1707 12:43:39.493027
1708 12:43:39.493110 Set Vref, RX VrefLevel [Byte0]: 55
1709 12:43:39.496298 [Byte1]: 55
1710 12:43:39.501045
1711 12:43:39.501129 Set Vref, RX VrefLevel [Byte0]: 56
1712 12:43:39.503839 [Byte1]: 56
1713 12:43:39.508504
1714 12:43:39.508587 Set Vref, RX VrefLevel [Byte0]: 57
1715 12:43:39.511478 [Byte1]: 57
1716 12:43:39.515667
1717 12:43:39.515750 Set Vref, RX VrefLevel [Byte0]: 58
1718 12:43:39.518895 [Byte1]: 58
1719 12:43:39.523332
1720 12:43:39.523415 Set Vref, RX VrefLevel [Byte0]: 59
1721 12:43:39.526660 [Byte1]: 59
1722 12:43:39.530797
1723 12:43:39.530880 Set Vref, RX VrefLevel [Byte0]: 60
1724 12:43:39.534189 [Byte1]: 60
1725 12:43:39.538688
1726 12:43:39.538771 Set Vref, RX VrefLevel [Byte0]: 61
1727 12:43:39.541712 [Byte1]: 61
1728 12:43:39.545950
1729 12:43:39.546047 Set Vref, RX VrefLevel [Byte0]: 62
1730 12:43:39.549440 [Byte1]: 62
1731 12:43:39.553637
1732 12:43:39.553720 Set Vref, RX VrefLevel [Byte0]: 63
1733 12:43:39.556976 [Byte1]: 63
1734 12:43:39.561015
1735 12:43:39.561098 Set Vref, RX VrefLevel [Byte0]: 64
1736 12:43:39.564221 [Byte1]: 64
1737 12:43:39.568568
1738 12:43:39.568652 Set Vref, RX VrefLevel [Byte0]: 65
1739 12:43:39.571864 [Byte1]: 65
1740 12:43:39.576135
1741 12:43:39.576220 Set Vref, RX VrefLevel [Byte0]: 66
1742 12:43:39.579525 [Byte1]: 66
1743 12:43:39.583844
1744 12:43:39.583958 Set Vref, RX VrefLevel [Byte0]: 67
1745 12:43:39.586958 [Byte1]: 67
1746 12:43:39.591308
1747 12:43:39.591383 Set Vref, RX VrefLevel [Byte0]: 68
1748 12:43:39.594563 [Byte1]: 68
1749 12:43:39.598853
1750 12:43:39.598927 Set Vref, RX VrefLevel [Byte0]: 69
1751 12:43:39.602079 [Byte1]: 69
1752 12:43:39.606392
1753 12:43:39.606509 Set Vref, RX VrefLevel [Byte0]: 70
1754 12:43:39.609504 [Byte1]: 70
1755 12:43:39.613726
1756 12:43:39.613837 Set Vref, RX VrefLevel [Byte0]: 71
1757 12:43:39.617329 [Byte1]: 71
1758 12:43:39.621697
1759 12:43:39.621777 Set Vref, RX VrefLevel [Byte0]: 72
1760 12:43:39.624949 [Byte1]: 72
1761 12:43:39.629154
1762 12:43:39.629250 Set Vref, RX VrefLevel [Byte0]: 73
1763 12:43:39.632434 [Byte1]: 73
1764 12:43:39.636863
1765 12:43:39.637000 Set Vref, RX VrefLevel [Byte0]: 74
1766 12:43:39.639739 [Byte1]: 74
1767 12:43:39.644396
1768 12:43:39.644563 Set Vref, RX VrefLevel [Byte0]: 75
1769 12:43:39.647702 [Byte1]: 75
1770 12:43:39.652199
1771 12:43:39.652336 Set Vref, RX VrefLevel [Byte0]: 76
1772 12:43:39.655509 [Byte1]: 76
1773 12:43:39.659845
1774 12:43:39.660263 Set Vref, RX VrefLevel [Byte0]: 77
1775 12:43:39.663062 [Byte1]: 77
1776 12:43:39.666899
1777 12:43:39.667413 Set Vref, RX VrefLevel [Byte0]: 78
1778 12:43:39.670366 [Byte1]: 78
1779 12:43:39.674601
1780 12:43:39.675019 Final RX Vref Byte 0 = 52 to rank0
1781 12:43:39.677857 Final RX Vref Byte 1 = 62 to rank0
1782 12:43:39.681338 Final RX Vref Byte 0 = 52 to rank1
1783 12:43:39.684668 Final RX Vref Byte 1 = 62 to rank1==
1784 12:43:39.687900 Dram Type= 6, Freq= 0, CH_1, rank 0
1785 12:43:39.694418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1786 12:43:39.694851 ==
1787 12:43:39.695192 DQS Delay:
1788 12:43:39.695509 DQS0 = 0, DQS1 = 0
1789 12:43:39.697845 DQM Delay:
1790 12:43:39.698303 DQM0 = 92, DQM1 = 82
1791 12:43:39.701382 DQ Delay:
1792 12:43:39.704547 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1793 12:43:39.707984 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =88
1794 12:43:39.711408 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1795 12:43:39.714620 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1796 12:43:39.715050
1797 12:43:39.715389
1798 12:43:39.721248 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b49, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1799 12:43:39.724522 CH1 RK0: MR19=606, MR18=2B49
1800 12:43:39.731393 CH1_RK0: MR19=0x606, MR18=0x2B49, DQSOSC=391, MR23=63, INC=96, DEC=64
1801 12:43:39.731825
1802 12:43:39.734813 ----->DramcWriteLeveling(PI) begin...
1803 12:43:39.735254 ==
1804 12:43:39.738276 Dram Type= 6, Freq= 0, CH_1, rank 1
1805 12:43:39.741384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1806 12:43:39.741845 ==
1807 12:43:39.745148 Write leveling (Byte 0): 28 => 28
1808 12:43:39.748470 Write leveling (Byte 1): 28 => 28
1809 12:43:39.751667 DramcWriteLeveling(PI) end<-----
1810 12:43:39.752125
1811 12:43:39.752463 ==
1812 12:43:39.755046 Dram Type= 6, Freq= 0, CH_1, rank 1
1813 12:43:39.758310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1814 12:43:39.758743 ==
1815 12:43:39.761622 [Gating] SW mode calibration
1816 12:43:39.768041 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1817 12:43:39.775051 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1818 12:43:39.778333 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1819 12:43:39.781702 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1820 12:43:39.788286 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1821 12:43:39.791669 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 12:43:39.794945 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 12:43:39.801613 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 12:43:39.805042 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 12:43:39.808401 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 12:43:39.814812 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 12:43:39.818378 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 12:43:39.822023 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 12:43:39.825037 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 12:43:39.831940 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 12:43:39.835352 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 12:43:39.838605 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 12:43:39.845493 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 12:43:39.848900 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1835 12:43:39.851878 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1836 12:43:39.858581 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 12:43:39.861909 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 12:43:39.865388 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 12:43:39.871702 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 12:43:39.875484 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 12:43:39.878326 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 12:43:39.881842 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 12:43:39.888751 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 12:43:39.891959 0 9 8 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
1845 12:43:39.895322 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 12:43:39.901993 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 12:43:39.905305 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 12:43:39.909045 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 12:43:39.915702 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 12:43:39.919015 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 12:43:39.922455 0 10 4 | B1->B0 | 2f2f 2f2f | 1 1 | (1 1) (1 0)
1852 12:43:39.929002 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 12:43:39.932328 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 12:43:39.936022 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 12:43:39.942577 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 12:43:39.945881 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 12:43:39.949142 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 12:43:39.952203 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 12:43:39.959222 0 11 4 | B1->B0 | 2b2b 2f2f | 0 0 | (0 0) (1 1)
1860 12:43:39.962527 0 11 8 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
1861 12:43:39.965901 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 12:43:39.972472 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 12:43:39.976170 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 12:43:39.979075 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 12:43:39.986080 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 12:43:39.989111 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1867 12:43:39.992426 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1868 12:43:39.999091 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1869 12:43:40.002845 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 12:43:40.005988 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 12:43:40.012908 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 12:43:40.016090 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 12:43:40.019564 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 12:43:40.022822 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 12:43:40.029355 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 12:43:40.032732 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 12:43:40.036116 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 12:43:40.042919 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 12:43:40.046245 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 12:43:40.049252 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 12:43:40.056123 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 12:43:40.059555 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 12:43:40.062923 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1884 12:43:40.069473 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1885 12:43:40.070118 Total UI for P1: 0, mck2ui 16
1886 12:43:40.076072 best dqsien dly found for B0: ( 0, 14, 4)
1887 12:43:40.076508 Total UI for P1: 0, mck2ui 16
1888 12:43:40.079587 best dqsien dly found for B1: ( 0, 14, 4)
1889 12:43:40.086354 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1890 12:43:40.089724 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1891 12:43:40.090198
1892 12:43:40.093062 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1893 12:43:40.096890 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1894 12:43:40.099797 [Gating] SW calibration Done
1895 12:43:40.100226 ==
1896 12:43:40.103066 Dram Type= 6, Freq= 0, CH_1, rank 1
1897 12:43:40.106464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1898 12:43:40.107026 ==
1899 12:43:40.107431 RX Vref Scan: 0
1900 12:43:40.107820
1901 12:43:40.109369 RX Vref 0 -> 0, step: 1
1902 12:43:40.109805
1903 12:43:40.113237 RX Delay -130 -> 252, step: 16
1904 12:43:40.116395 iDelay=206, Bit 0, Center 101 (-2 ~ 205) 208
1905 12:43:40.119761 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1906 12:43:40.126491 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1907 12:43:40.129560 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1908 12:43:40.133112 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1909 12:43:40.136583 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1910 12:43:40.139830 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1911 12:43:40.146562 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1912 12:43:40.149597 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1913 12:43:40.152805 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1914 12:43:40.156525 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1915 12:43:40.159662 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1916 12:43:40.166503 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1917 12:43:40.169808 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1918 12:43:40.173166 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1919 12:43:40.176625 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1920 12:43:40.177095 ==
1921 12:43:40.179890 Dram Type= 6, Freq= 0, CH_1, rank 1
1922 12:43:40.182988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1923 12:43:40.186552 ==
1924 12:43:40.187015 DQS Delay:
1925 12:43:40.187455 DQS0 = 0, DQS1 = 0
1926 12:43:40.189865 DQM Delay:
1927 12:43:40.190353 DQM0 = 91, DQM1 = 82
1928 12:43:40.193118 DQ Delay:
1929 12:43:40.196539 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1930 12:43:40.199831 DQ4 =93, DQ5 =101, DQ6 =101, DQ7 =85
1931 12:43:40.203163 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1932 12:43:40.206443 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1933 12:43:40.206913
1934 12:43:40.207294
1935 12:43:40.207648 ==
1936 12:43:40.209715 Dram Type= 6, Freq= 0, CH_1, rank 1
1937 12:43:40.213159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1938 12:43:40.213606 ==
1939 12:43:40.213984
1940 12:43:40.214316
1941 12:43:40.216387 TX Vref Scan disable
1942 12:43:40.216816 == TX Byte 0 ==
1943 12:43:40.222976 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1944 12:43:40.226363 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1945 12:43:40.226792 == TX Byte 1 ==
1946 12:43:40.232938 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1947 12:43:40.236526 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1948 12:43:40.236968 ==
1949 12:43:40.239764 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 12:43:40.243047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 12:43:40.243457 ==
1952 12:43:40.256451 TX Vref=22, minBit 13, minWin=27, winSum=450
1953 12:43:40.260261 TX Vref=24, minBit 13, minWin=27, winSum=453
1954 12:43:40.263553 TX Vref=26, minBit 9, minWin=28, winSum=460
1955 12:43:40.266439 TX Vref=28, minBit 8, minWin=28, winSum=461
1956 12:43:40.269794 TX Vref=30, minBit 8, minWin=28, winSum=461
1957 12:43:40.276663 TX Vref=32, minBit 9, minWin=27, winSum=457
1958 12:43:40.279796 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 28
1959 12:43:40.280345
1960 12:43:40.283121 Final TX Range 1 Vref 28
1961 12:43:40.283723
1962 12:43:40.284253 ==
1963 12:43:40.286458 Dram Type= 6, Freq= 0, CH_1, rank 1
1964 12:43:40.290218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1965 12:43:40.290798 ==
1966 12:43:40.293491
1967 12:43:40.294100
1968 12:43:40.294555 TX Vref Scan disable
1969 12:43:40.296983 == TX Byte 0 ==
1970 12:43:40.300042 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1971 12:43:40.303320 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1972 12:43:40.306747 == TX Byte 1 ==
1973 12:43:40.310321 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1974 12:43:40.313703 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1975 12:43:40.316634
1976 12:43:40.317057 [DATLAT]
1977 12:43:40.317388 Freq=800, CH1 RK1
1978 12:43:40.317702
1979 12:43:40.320670 DATLAT Default: 0xa
1980 12:43:40.321328 0, 0xFFFF, sum = 0
1981 12:43:40.323542 1, 0xFFFF, sum = 0
1982 12:43:40.323972 2, 0xFFFF, sum = 0
1983 12:43:40.327099 3, 0xFFFF, sum = 0
1984 12:43:40.327530 4, 0xFFFF, sum = 0
1985 12:43:40.330296 5, 0xFFFF, sum = 0
1986 12:43:40.330729 6, 0xFFFF, sum = 0
1987 12:43:40.333642 7, 0xFFFF, sum = 0
1988 12:43:40.336926 8, 0xFFFF, sum = 0
1989 12:43:40.337353 9, 0x0, sum = 1
1990 12:43:40.337696 10, 0x0, sum = 2
1991 12:43:40.340642 11, 0x0, sum = 3
1992 12:43:40.341243 12, 0x0, sum = 4
1993 12:43:40.343723 best_step = 10
1994 12:43:40.344147
1995 12:43:40.344604 ==
1996 12:43:40.347129 Dram Type= 6, Freq= 0, CH_1, rank 1
1997 12:43:40.350403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1998 12:43:40.350926 ==
1999 12:43:40.353639 RX Vref Scan: 0
2000 12:43:40.354089
2001 12:43:40.354432 RX Vref 0 -> 0, step: 1
2002 12:43:40.354744
2003 12:43:40.357374 RX Delay -95 -> 252, step: 8
2004 12:43:40.363529 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2005 12:43:40.367108 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2006 12:43:40.370210 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2007 12:43:40.373770 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2008 12:43:40.376901 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2009 12:43:40.383535 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2010 12:43:40.387107 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2011 12:43:40.390610 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2012 12:43:40.393768 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2013 12:43:40.396708 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2014 12:43:40.400036 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2015 12:43:40.406658 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2016 12:43:40.409815 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2017 12:43:40.413241 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2018 12:43:40.416922 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2019 12:43:40.423508 iDelay=209, Bit 15, Center 92 (-23 ~ 208) 232
2020 12:43:40.423598 ==
2021 12:43:40.426801 Dram Type= 6, Freq= 0, CH_1, rank 1
2022 12:43:40.430195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2023 12:43:40.430293 ==
2024 12:43:40.430368 DQS Delay:
2025 12:43:40.433288 DQS0 = 0, DQS1 = 0
2026 12:43:40.433384 DQM Delay:
2027 12:43:40.436428 DQM0 = 91, DQM1 = 83
2028 12:43:40.436533 DQ Delay:
2029 12:43:40.439897 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2030 12:43:40.443303 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2031 12:43:40.446648 DQ8 =68, DQ9 =72, DQ10 =88, DQ11 =80
2032 12:43:40.449846 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =92
2033 12:43:40.449930
2034 12:43:40.450043
2035 12:43:40.456728 [DQSOSCAuto] RK1, (LSB)MR18= 0x390e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2036 12:43:40.460113 CH1 RK1: MR19=606, MR18=390E
2037 12:43:40.466342 CH1_RK1: MR19=0x606, MR18=0x390E, DQSOSC=395, MR23=63, INC=94, DEC=63
2038 12:43:40.469912 [RxdqsGatingPostProcess] freq 800
2039 12:43:40.476547 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2040 12:43:40.476632 Pre-setting of DQS Precalculation
2041 12:43:40.483189 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2042 12:43:40.490003 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2043 12:43:40.496475 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2044 12:43:40.496563
2045 12:43:40.496629
2046 12:43:40.499752 [Calibration Summary] 1600 Mbps
2047 12:43:40.503032 CH 0, Rank 0
2048 12:43:40.503108 SW Impedance : PASS
2049 12:43:40.506372 DUTY Scan : NO K
2050 12:43:40.509683 ZQ Calibration : PASS
2051 12:43:40.509753 Jitter Meter : NO K
2052 12:43:40.513145 CBT Training : PASS
2053 12:43:40.513233 Write leveling : PASS
2054 12:43:40.516376 RX DQS gating : PASS
2055 12:43:40.520049 RX DQ/DQS(RDDQC) : PASS
2056 12:43:40.520133 TX DQ/DQS : PASS
2057 12:43:40.523473 RX DATLAT : PASS
2058 12:43:40.526314 RX DQ/DQS(Engine): PASS
2059 12:43:40.526398 TX OE : NO K
2060 12:43:40.530075 All Pass.
2061 12:43:40.530158
2062 12:43:40.530223 CH 0, Rank 1
2063 12:43:40.533225 SW Impedance : PASS
2064 12:43:40.533308 DUTY Scan : NO K
2065 12:43:40.536658 ZQ Calibration : PASS
2066 12:43:40.539997 Jitter Meter : NO K
2067 12:43:40.540081 CBT Training : PASS
2068 12:43:40.543318 Write leveling : PASS
2069 12:43:40.546561 RX DQS gating : PASS
2070 12:43:40.546645 RX DQ/DQS(RDDQC) : PASS
2071 12:43:40.550155 TX DQ/DQS : PASS
2072 12:43:40.550239 RX DATLAT : PASS
2073 12:43:40.553363 RX DQ/DQS(Engine): PASS
2074 12:43:40.556848 TX OE : NO K
2075 12:43:40.556943 All Pass.
2076 12:43:40.557010
2077 12:43:40.557070 CH 1, Rank 0
2078 12:43:40.560093 SW Impedance : PASS
2079 12:43:40.563347 DUTY Scan : NO K
2080 12:43:40.563431 ZQ Calibration : PASS
2081 12:43:40.566988 Jitter Meter : NO K
2082 12:43:40.570269 CBT Training : PASS
2083 12:43:40.570351 Write leveling : PASS
2084 12:43:40.573692 RX DQS gating : PASS
2085 12:43:40.577019 RX DQ/DQS(RDDQC) : PASS
2086 12:43:40.577102 TX DQ/DQS : PASS
2087 12:43:40.580321 RX DATLAT : PASS
2088 12:43:40.583468 RX DQ/DQS(Engine): PASS
2089 12:43:40.583551 TX OE : NO K
2090 12:43:40.583617 All Pass.
2091 12:43:40.583679
2092 12:43:40.586603 CH 1, Rank 1
2093 12:43:40.590082 SW Impedance : PASS
2094 12:43:40.590165 DUTY Scan : NO K
2095 12:43:40.593563 ZQ Calibration : PASS
2096 12:43:40.593645 Jitter Meter : NO K
2097 12:43:40.596672 CBT Training : PASS
2098 12:43:40.600274 Write leveling : PASS
2099 12:43:40.600357 RX DQS gating : PASS
2100 12:43:40.603700 RX DQ/DQS(RDDQC) : PASS
2101 12:43:40.606959 TX DQ/DQS : PASS
2102 12:43:40.607043 RX DATLAT : PASS
2103 12:43:40.610311 RX DQ/DQS(Engine): PASS
2104 12:43:40.613568 TX OE : NO K
2105 12:43:40.613651 All Pass.
2106 12:43:40.613717
2107 12:43:40.613777 DramC Write-DBI off
2108 12:43:40.616944 PER_BANK_REFRESH: Hybrid Mode
2109 12:43:40.620253 TX_TRACKING: ON
2110 12:43:40.623554 [GetDramInforAfterCalByMRR] Vendor 6.
2111 12:43:40.627035 [GetDramInforAfterCalByMRR] Revision 606.
2112 12:43:40.629823 [GetDramInforAfterCalByMRR] Revision 2 0.
2113 12:43:40.629906 MR0 0x3b3b
2114 12:43:40.633640 MR8 0x5151
2115 12:43:40.636754 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2116 12:43:40.636838
2117 12:43:40.636903 MR0 0x3b3b
2118 12:43:40.636964 MR8 0x5151
2119 12:43:40.640258 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2120 12:43:40.643647
2121 12:43:40.650434 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2122 12:43:40.653532 [FAST_K] Save calibration result to emmc
2123 12:43:40.656889 [FAST_K] Save calibration result to emmc
2124 12:43:40.660164 dram_init: config_dvfs: 1
2125 12:43:40.663593 dramc_set_vcore_voltage set vcore to 662500
2126 12:43:40.666776 Read voltage for 1200, 2
2127 12:43:40.666873 Vio18 = 0
2128 12:43:40.670260 Vcore = 662500
2129 12:43:40.670341 Vdram = 0
2130 12:43:40.670421 Vddq = 0
2131 12:43:40.670482 Vmddr = 0
2132 12:43:40.676872 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2133 12:43:40.683475 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2134 12:43:40.683557 MEM_TYPE=3, freq_sel=15
2135 12:43:40.687018 sv_algorithm_assistance_LP4_1600
2136 12:43:40.690632 ============ PULL DRAM RESETB DOWN ============
2137 12:43:40.697188 ========== PULL DRAM RESETB DOWN end =========
2138 12:43:40.700470 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2139 12:43:40.703844 ===================================
2140 12:43:40.707274 LPDDR4 DRAM CONFIGURATION
2141 12:43:40.710344 ===================================
2142 12:43:40.710425 EX_ROW_EN[0] = 0x0
2143 12:43:40.713722 EX_ROW_EN[1] = 0x0
2144 12:43:40.713803 LP4Y_EN = 0x0
2145 12:43:40.717222 WORK_FSP = 0x0
2146 12:43:40.717304 WL = 0x4
2147 12:43:40.720425 RL = 0x4
2148 12:43:40.720506 BL = 0x2
2149 12:43:40.723775 RPST = 0x0
2150 12:43:40.723856 RD_PRE = 0x0
2151 12:43:40.726879 WR_PRE = 0x1
2152 12:43:40.726960 WR_PST = 0x0
2153 12:43:40.730161 DBI_WR = 0x0
2154 12:43:40.730243 DBI_RD = 0x0
2155 12:43:40.733583 OTF = 0x1
2156 12:43:40.736878 ===================================
2157 12:43:40.740473 ===================================
2158 12:43:40.740554 ANA top config
2159 12:43:40.743615 ===================================
2160 12:43:40.746886 DLL_ASYNC_EN = 0
2161 12:43:40.750259 ALL_SLAVE_EN = 0
2162 12:43:40.753628 NEW_RANK_MODE = 1
2163 12:43:40.753710 DLL_IDLE_MODE = 1
2164 12:43:40.756960 LP45_APHY_COMB_EN = 1
2165 12:43:40.760632 TX_ODT_DIS = 1
2166 12:43:40.763694 NEW_8X_MODE = 1
2167 12:43:40.767102 ===================================
2168 12:43:40.770489 ===================================
2169 12:43:40.773767 data_rate = 2400
2170 12:43:40.777000 CKR = 1
2171 12:43:40.777081 DQ_P2S_RATIO = 8
2172 12:43:40.780222 ===================================
2173 12:43:40.783569 CA_P2S_RATIO = 8
2174 12:43:40.787121 DQ_CA_OPEN = 0
2175 12:43:40.790264 DQ_SEMI_OPEN = 0
2176 12:43:40.793533 CA_SEMI_OPEN = 0
2177 12:43:40.793615 CA_FULL_RATE = 0
2178 12:43:40.796804 DQ_CKDIV4_EN = 0
2179 12:43:40.800352 CA_CKDIV4_EN = 0
2180 12:43:40.803870 CA_PREDIV_EN = 0
2181 12:43:40.806980 PH8_DLY = 17
2182 12:43:40.810163 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2183 12:43:40.810305 DQ_AAMCK_DIV = 4
2184 12:43:40.813861 CA_AAMCK_DIV = 4
2185 12:43:40.816930 CA_ADMCK_DIV = 4
2186 12:43:40.820210 DQ_TRACK_CA_EN = 0
2187 12:43:40.823587 CA_PICK = 1200
2188 12:43:40.826971 CA_MCKIO = 1200
2189 12:43:40.830031 MCKIO_SEMI = 0
2190 12:43:40.830140 PLL_FREQ = 2366
2191 12:43:40.833367 DQ_UI_PI_RATIO = 32
2192 12:43:40.836837 CA_UI_PI_RATIO = 0
2193 12:43:40.840241 ===================================
2194 12:43:40.843342 ===================================
2195 12:43:40.846867 memory_type:LPDDR4
2196 12:43:40.850284 GP_NUM : 10
2197 12:43:40.850367 SRAM_EN : 1
2198 12:43:40.853476 MD32_EN : 0
2199 12:43:40.856789 ===================================
2200 12:43:40.856873 [ANA_INIT] >>>>>>>>>>>>>>
2201 12:43:40.860091 <<<<<< [CONFIGURE PHASE]: ANA_TX
2202 12:43:40.863324 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2203 12:43:40.866610 ===================================
2204 12:43:40.870070 data_rate = 2400,PCW = 0X5b00
2205 12:43:40.873496 ===================================
2206 12:43:40.876926 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2207 12:43:40.883416 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2208 12:43:40.886901 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2209 12:43:40.893521 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2210 12:43:40.896663 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2211 12:43:40.899949 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2212 12:43:40.900033 [ANA_INIT] flow start
2213 12:43:40.903389 [ANA_INIT] PLL >>>>>>>>
2214 12:43:40.906867 [ANA_INIT] PLL <<<<<<<<
2215 12:43:40.909867 [ANA_INIT] MIDPI >>>>>>>>
2216 12:43:40.909977 [ANA_INIT] MIDPI <<<<<<<<
2217 12:43:40.913260 [ANA_INIT] DLL >>>>>>>>
2218 12:43:40.916821 [ANA_INIT] DLL <<<<<<<<
2219 12:43:40.916904 [ANA_INIT] flow end
2220 12:43:40.919925 ============ LP4 DIFF to SE enter ============
2221 12:43:40.926739 ============ LP4 DIFF to SE exit ============
2222 12:43:40.926823 [ANA_INIT] <<<<<<<<<<<<<
2223 12:43:40.930133 [Flow] Enable top DCM control >>>>>
2224 12:43:40.933415 [Flow] Enable top DCM control <<<<<
2225 12:43:40.936651 Enable DLL master slave shuffle
2226 12:43:40.943621 ==============================================================
2227 12:43:40.943703 Gating Mode config
2228 12:43:40.950300 ==============================================================
2229 12:43:40.953690 Config description:
2230 12:43:40.963543 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2231 12:43:40.967102 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2232 12:43:40.973477 SELPH_MODE 0: By rank 1: By Phase
2233 12:43:40.980025 ==============================================================
2234 12:43:40.983635 GAT_TRACK_EN = 1
2235 12:43:40.983739 RX_GATING_MODE = 2
2236 12:43:40.987251 RX_GATING_TRACK_MODE = 2
2237 12:43:40.990606 SELPH_MODE = 1
2238 12:43:40.993771 PICG_EARLY_EN = 1
2239 12:43:40.996687 VALID_LAT_VALUE = 1
2240 12:43:41.003850 ==============================================================
2241 12:43:41.006846 Enter into Gating configuration >>>>
2242 12:43:41.010238 Exit from Gating configuration <<<<
2243 12:43:41.013680 Enter into DVFS_PRE_config >>>>>
2244 12:43:41.023957 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2245 12:43:41.026831 Exit from DVFS_PRE_config <<<<<
2246 12:43:41.030146 Enter into PICG configuration >>>>
2247 12:43:41.033336 Exit from PICG configuration <<<<
2248 12:43:41.036738 [RX_INPUT] configuration >>>>>
2249 12:43:41.036820 [RX_INPUT] configuration <<<<<
2250 12:43:41.043331 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2251 12:43:41.050327 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2252 12:43:41.053498 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2253 12:43:41.060472 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2254 12:43:41.067110 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2255 12:43:41.073704 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2256 12:43:41.076986 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2257 12:43:41.080423 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2258 12:43:41.087171 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2259 12:43:41.090218 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2260 12:43:41.093637 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2261 12:43:41.097022 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2262 12:43:41.100560 ===================================
2263 12:43:41.103829 LPDDR4 DRAM CONFIGURATION
2264 12:43:41.107123 ===================================
2265 12:43:41.110668 EX_ROW_EN[0] = 0x0
2266 12:43:41.110751 EX_ROW_EN[1] = 0x0
2267 12:43:41.113836 LP4Y_EN = 0x0
2268 12:43:41.113920 WORK_FSP = 0x0
2269 12:43:41.117796 WL = 0x4
2270 12:43:41.117879 RL = 0x4
2271 12:43:41.120898 BL = 0x2
2272 12:43:41.120981 RPST = 0x0
2273 12:43:41.124237 RD_PRE = 0x0
2274 12:43:41.124320 WR_PRE = 0x1
2275 12:43:41.127166 WR_PST = 0x0
2276 12:43:41.127249 DBI_WR = 0x0
2277 12:43:41.130406 DBI_RD = 0x0
2278 12:43:41.130488 OTF = 0x1
2279 12:43:41.134027 ===================================
2280 12:43:41.140734 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2281 12:43:41.143846 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2282 12:43:41.147157 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2283 12:43:41.150470 ===================================
2284 12:43:41.153818 LPDDR4 DRAM CONFIGURATION
2285 12:43:41.157185 ===================================
2286 12:43:41.160463 EX_ROW_EN[0] = 0x10
2287 12:43:41.160545 EX_ROW_EN[1] = 0x0
2288 12:43:41.163945 LP4Y_EN = 0x0
2289 12:43:41.164027 WORK_FSP = 0x0
2290 12:43:41.167234 WL = 0x4
2291 12:43:41.167317 RL = 0x4
2292 12:43:41.170660 BL = 0x2
2293 12:43:41.170742 RPST = 0x0
2294 12:43:41.173868 RD_PRE = 0x0
2295 12:43:41.173955 WR_PRE = 0x1
2296 12:43:41.177040 WR_PST = 0x0
2297 12:43:41.177123 DBI_WR = 0x0
2298 12:43:41.180537 DBI_RD = 0x0
2299 12:43:41.180622 OTF = 0x1
2300 12:43:41.183940 ===================================
2301 12:43:41.190377 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2302 12:43:41.190460 ==
2303 12:43:41.193880 Dram Type= 6, Freq= 0, CH_0, rank 0
2304 12:43:41.197498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2305 12:43:41.200417 ==
2306 12:43:41.200498 [Duty_Offset_Calibration]
2307 12:43:41.203701 B0:2 B1:0 CA:1
2308 12:43:41.203781
2309 12:43:41.207110 [DutyScan_Calibration_Flow] k_type=0
2310 12:43:41.214955
2311 12:43:41.215035 ==CLK 0==
2312 12:43:41.218192 Final CLK duty delay cell = -4
2313 12:43:41.221686 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2314 12:43:41.224927 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2315 12:43:41.228450 [-4] AVG Duty = 4953%(X100)
2316 12:43:41.228531
2317 12:43:41.231293 CH0 CLK Duty spec in!! Max-Min= 156%
2318 12:43:41.234689 [DutyScan_Calibration_Flow] ====Done====
2319 12:43:41.234770
2320 12:43:41.238085 [DutyScan_Calibration_Flow] k_type=1
2321 12:43:41.253480
2322 12:43:41.253562 ==DQS 0 ==
2323 12:43:41.256842 Final DQS duty delay cell = 0
2324 12:43:41.260287 [0] MAX Duty = 5187%(X100), DQS PI = 32
2325 12:43:41.263892 [0] MIN Duty = 4938%(X100), DQS PI = 0
2326 12:43:41.263973 [0] AVG Duty = 5062%(X100)
2327 12:43:41.266962
2328 12:43:41.267043 ==DQS 1 ==
2329 12:43:41.270454 Final DQS duty delay cell = -4
2330 12:43:41.273786 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2331 12:43:41.277134 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2332 12:43:41.280084 [-4] AVG Duty = 5031%(X100)
2333 12:43:41.280165
2334 12:43:41.283739 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2335 12:43:41.283820
2336 12:43:41.287260 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2337 12:43:41.290129 [DutyScan_Calibration_Flow] ====Done====
2338 12:43:41.290210
2339 12:43:41.293550 [DutyScan_Calibration_Flow] k_type=3
2340 12:43:41.310302
2341 12:43:41.310384 ==DQM 0 ==
2342 12:43:41.314054 Final DQM duty delay cell = 0
2343 12:43:41.317448 [0] MAX Duty = 5062%(X100), DQS PI = 24
2344 12:43:41.320326 [0] MIN Duty = 4844%(X100), DQS PI = 0
2345 12:43:41.320407 [0] AVG Duty = 4953%(X100)
2346 12:43:41.323850
2347 12:43:41.323930 ==DQM 1 ==
2348 12:43:41.327389 Final DQM duty delay cell = 0
2349 12:43:41.330412 [0] MAX Duty = 5187%(X100), DQS PI = 46
2350 12:43:41.333835 [0] MIN Duty = 5000%(X100), DQS PI = 12
2351 12:43:41.333917 [0] AVG Duty = 5093%(X100)
2352 12:43:41.337185
2353 12:43:41.340636 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2354 12:43:41.340721
2355 12:43:41.343837 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2356 12:43:41.347245 [DutyScan_Calibration_Flow] ====Done====
2357 12:43:41.347328
2358 12:43:41.350837 [DutyScan_Calibration_Flow] k_type=2
2359 12:43:41.366056
2360 12:43:41.366143 ==DQ 0 ==
2361 12:43:41.369681 Final DQ duty delay cell = -4
2362 12:43:41.372676 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2363 12:43:41.376416 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2364 12:43:41.379930 [-4] AVG Duty = 4953%(X100)
2365 12:43:41.380007
2366 12:43:41.380071 ==DQ 1 ==
2367 12:43:41.383214 Final DQ duty delay cell = 0
2368 12:43:41.386212 [0] MAX Duty = 4938%(X100), DQS PI = 6
2369 12:43:41.389548 [0] MIN Duty = 4907%(X100), DQS PI = 0
2370 12:43:41.389650 [0] AVG Duty = 4922%(X100)
2371 12:43:41.389740
2372 12:43:41.392960 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2373 12:43:41.396360
2374 12:43:41.399526 CH0 DQ 1 Duty spec in!! Max-Min= 31%
2375 12:43:41.403111 [DutyScan_Calibration_Flow] ====Done====
2376 12:43:41.403183 ==
2377 12:43:41.406573 Dram Type= 6, Freq= 0, CH_1, rank 0
2378 12:43:41.409533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2379 12:43:41.409602 ==
2380 12:43:41.412876 [Duty_Offset_Calibration]
2381 12:43:41.412943 B0:0 B1:-1 CA:2
2382 12:43:41.413002
2383 12:43:41.416220 [DutyScan_Calibration_Flow] k_type=0
2384 12:43:41.426294
2385 12:43:41.426364 ==CLK 0==
2386 12:43:41.429809 Final CLK duty delay cell = 0
2387 12:43:41.432939 [0] MAX Duty = 5156%(X100), DQS PI = 16
2388 12:43:41.436455 [0] MIN Duty = 4938%(X100), DQS PI = 44
2389 12:43:41.436563 [0] AVG Duty = 5047%(X100)
2390 12:43:41.439650
2391 12:43:41.443154 CH1 CLK Duty spec in!! Max-Min= 218%
2392 12:43:41.446219 [DutyScan_Calibration_Flow] ====Done====
2393 12:43:41.446293
2394 12:43:41.449325 [DutyScan_Calibration_Flow] k_type=1
2395 12:43:41.465436
2396 12:43:41.465522 ==DQS 0 ==
2397 12:43:41.468870 Final DQS duty delay cell = 0
2398 12:43:41.472425 [0] MAX Duty = 5093%(X100), DQS PI = 24
2399 12:43:41.475899 [0] MIN Duty = 4969%(X100), DQS PI = 0
2400 12:43:41.475976 [0] AVG Duty = 5031%(X100)
2401 12:43:41.479109
2402 12:43:41.479183 ==DQS 1 ==
2403 12:43:41.482621 Final DQS duty delay cell = 0
2404 12:43:41.485735 [0] MAX Duty = 5156%(X100), DQS PI = 0
2405 12:43:41.489005 [0] MIN Duty = 4844%(X100), DQS PI = 36
2406 12:43:41.489082 [0] AVG Duty = 5000%(X100)
2407 12:43:41.492720
2408 12:43:41.495652 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2409 12:43:41.495722
2410 12:43:41.498916 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2411 12:43:41.502297 [DutyScan_Calibration_Flow] ====Done====
2412 12:43:41.502374
2413 12:43:41.505865 [DutyScan_Calibration_Flow] k_type=3
2414 12:43:41.522849
2415 12:43:41.522930 ==DQM 0 ==
2416 12:43:41.526124 Final DQM duty delay cell = 4
2417 12:43:41.529517 [4] MAX Duty = 5093%(X100), DQS PI = 4
2418 12:43:41.532910 [4] MIN Duty = 4969%(X100), DQS PI = 28
2419 12:43:41.532982 [4] AVG Duty = 5031%(X100)
2420 12:43:41.536758
2421 12:43:41.536840 ==DQM 1 ==
2422 12:43:41.539844 Final DQM duty delay cell = 0
2423 12:43:41.542844 [0] MAX Duty = 5249%(X100), DQS PI = 0
2424 12:43:41.546214 [0] MIN Duty = 4875%(X100), DQS PI = 36
2425 12:43:41.546290 [0] AVG Duty = 5062%(X100)
2426 12:43:41.546352
2427 12:43:41.553085 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2428 12:43:41.553173
2429 12:43:41.556313 CH1 DQM 1 Duty spec in!! Max-Min= 374%
2430 12:43:41.559442 [DutyScan_Calibration_Flow] ====Done====
2431 12:43:41.559515
2432 12:43:41.562872 [DutyScan_Calibration_Flow] k_type=2
2433 12:43:41.579306
2434 12:43:41.579383 ==DQ 0 ==
2435 12:43:41.582640 Final DQ duty delay cell = 0
2436 12:43:41.585908 [0] MAX Duty = 5062%(X100), DQS PI = 20
2437 12:43:41.589703 [0] MIN Duty = 4938%(X100), DQS PI = 0
2438 12:43:41.589779 [0] AVG Duty = 5000%(X100)
2439 12:43:41.589849
2440 12:43:41.592970 ==DQ 1 ==
2441 12:43:41.596248 Final DQ duty delay cell = 0
2442 12:43:41.599639 [0] MAX Duty = 5031%(X100), DQS PI = 2
2443 12:43:41.603033 [0] MIN Duty = 4813%(X100), DQS PI = 36
2444 12:43:41.603102 [0] AVG Duty = 4922%(X100)
2445 12:43:41.603168
2446 12:43:41.606164 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2447 12:43:41.606231
2448 12:43:41.609883 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2449 12:43:41.613246 [DutyScan_Calibration_Flow] ====Done====
2450 12:43:41.618672 nWR fixed to 30
2451 12:43:41.621618 [ModeRegInit_LP4] CH0 RK0
2452 12:43:41.621687 [ModeRegInit_LP4] CH0 RK1
2453 12:43:41.624965 [ModeRegInit_LP4] CH1 RK0
2454 12:43:41.628310 [ModeRegInit_LP4] CH1 RK1
2455 12:43:41.628379 match AC timing 7
2456 12:43:41.635048 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2457 12:43:41.638319 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2458 12:43:41.641898 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2459 12:43:41.648409 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2460 12:43:41.652001 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2461 12:43:41.652077 ==
2462 12:43:41.655127 Dram Type= 6, Freq= 0, CH_0, rank 0
2463 12:43:41.658273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2464 12:43:41.658348 ==
2465 12:43:41.664906 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2466 12:43:41.671689 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2467 12:43:41.679189 [CA 0] Center 38 (7~69) winsize 63
2468 12:43:41.682357 [CA 1] Center 38 (8~69) winsize 62
2469 12:43:41.686138 [CA 2] Center 35 (5~66) winsize 62
2470 12:43:41.689344 [CA 3] Center 35 (4~66) winsize 63
2471 12:43:41.692381 [CA 4] Center 34 (4~65) winsize 62
2472 12:43:41.695721 [CA 5] Center 33 (3~63) winsize 61
2473 12:43:41.695791
2474 12:43:41.699339 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2475 12:43:41.699410
2476 12:43:41.702698 [CATrainingPosCal] consider 1 rank data
2477 12:43:41.706163 u2DelayCellTimex100 = 270/100 ps
2478 12:43:41.709404 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2479 12:43:41.712611 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2480 12:43:41.719123 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2481 12:43:41.722648 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2482 12:43:41.725992 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2483 12:43:41.729326 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2484 12:43:41.729395
2485 12:43:41.732274 CA PerBit enable=1, Macro0, CA PI delay=33
2486 12:43:41.732349
2487 12:43:41.735542 [CBTSetCACLKResult] CA Dly = 33
2488 12:43:41.735620 CS Dly: 6 (0~37)
2489 12:43:41.735684 ==
2490 12:43:41.738990 Dram Type= 6, Freq= 0, CH_0, rank 1
2491 12:43:41.746039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2492 12:43:41.746118 ==
2493 12:43:41.749304 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2494 12:43:41.755680 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2495 12:43:41.765105 [CA 0] Center 39 (8~70) winsize 63
2496 12:43:41.768109 [CA 1] Center 38 (8~69) winsize 62
2497 12:43:41.771617 [CA 2] Center 35 (5~66) winsize 62
2498 12:43:41.775038 [CA 3] Center 35 (5~66) winsize 62
2499 12:43:41.778533 [CA 4] Center 34 (4~65) winsize 62
2500 12:43:41.781584 [CA 5] Center 34 (4~64) winsize 61
2501 12:43:41.781660
2502 12:43:41.785127 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2503 12:43:41.785198
2504 12:43:41.788427 [CATrainingPosCal] consider 2 rank data
2505 12:43:41.792008 u2DelayCellTimex100 = 270/100 ps
2506 12:43:41.794993 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2507 12:43:41.798242 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2508 12:43:41.802039 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2509 12:43:41.808348 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2510 12:43:41.811756 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2511 12:43:41.815175 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2512 12:43:41.815251
2513 12:43:41.818438 CA PerBit enable=1, Macro0, CA PI delay=33
2514 12:43:41.818517
2515 12:43:41.821781 [CBTSetCACLKResult] CA Dly = 33
2516 12:43:41.821855 CS Dly: 7 (0~39)
2517 12:43:41.821917
2518 12:43:41.825219 ----->DramcWriteLeveling(PI) begin...
2519 12:43:41.825295 ==
2520 12:43:41.828496 Dram Type= 6, Freq= 0, CH_0, rank 0
2521 12:43:41.835106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2522 12:43:41.835180 ==
2523 12:43:41.838710 Write leveling (Byte 0): 33 => 33
2524 12:43:41.841922 Write leveling (Byte 1): 31 => 31
2525 12:43:41.842032 DramcWriteLeveling(PI) end<-----
2526 12:43:41.842094
2527 12:43:41.845276 ==
2528 12:43:41.848648 Dram Type= 6, Freq= 0, CH_0, rank 0
2529 12:43:41.852217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2530 12:43:41.852394 ==
2531 12:43:41.855436 [Gating] SW mode calibration
2532 12:43:41.861860 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2533 12:43:41.865319 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2534 12:43:41.871814 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2535 12:43:41.875229 0 15 4 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
2536 12:43:41.878837 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 12:43:41.885600 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 12:43:41.889070 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 12:43:41.892061 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 12:43:41.899005 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2541 12:43:41.901935 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2542 12:43:41.905871 1 0 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
2543 12:43:41.912211 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 12:43:41.915724 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 12:43:41.919188 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 12:43:41.922423 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 12:43:41.929128 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 12:43:41.932541 1 0 24 | B1->B0 | 2323 3433 | 0 1 | (0 0) (0 0)
2549 12:43:41.935662 1 0 28 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
2550 12:43:41.942423 1 1 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
2551 12:43:41.946058 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 12:43:41.949394 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 12:43:41.955895 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 12:43:41.959095 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 12:43:41.962432 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 12:43:41.969231 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 12:43:41.972561 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2558 12:43:41.975476 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2559 12:43:41.982231 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 12:43:41.985881 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 12:43:41.989236 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 12:43:41.995858 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 12:43:41.999025 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 12:43:42.002392 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 12:43:42.005865 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 12:43:42.012244 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 12:43:42.015446 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 12:43:42.019253 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 12:43:42.025931 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 12:43:42.028983 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 12:43:42.032278 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 12:43:42.039045 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2573 12:43:42.042453 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2574 12:43:42.045428 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2575 12:43:42.049178 Total UI for P1: 0, mck2ui 16
2576 12:43:42.052392 best dqsien dly found for B0: ( 1, 3, 26)
2577 12:43:42.058973 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2578 12:43:42.059427 Total UI for P1: 0, mck2ui 16
2579 12:43:42.065924 best dqsien dly found for B1: ( 1, 4, 0)
2580 12:43:42.068996 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2581 12:43:42.072161 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2582 12:43:42.072586
2583 12:43:42.075619 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2584 12:43:42.078918 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2585 12:43:42.082179 [Gating] SW calibration Done
2586 12:43:42.082609 ==
2587 12:43:42.085925 Dram Type= 6, Freq= 0, CH_0, rank 0
2588 12:43:42.089216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2589 12:43:42.089864 ==
2590 12:43:42.092620 RX Vref Scan: 0
2591 12:43:42.093049
2592 12:43:42.093387 RX Vref 0 -> 0, step: 1
2593 12:43:42.093699
2594 12:43:42.095949 RX Delay -40 -> 252, step: 8
2595 12:43:42.098846 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
2596 12:43:42.102294 iDelay=200, Bit 1, Center 127 (56 ~ 199) 144
2597 12:43:42.109274 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2598 12:43:42.112694 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2599 12:43:42.115846 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2600 12:43:42.119155 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2601 12:43:42.122615 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2602 12:43:42.129164 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2603 12:43:42.132287 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2604 12:43:42.136066 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2605 12:43:42.139444 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2606 12:43:42.142852 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2607 12:43:42.149463 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2608 12:43:42.152564 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2609 12:43:42.155948 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2610 12:43:42.159204 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2611 12:43:42.159633 ==
2612 12:43:42.162732 Dram Type= 6, Freq= 0, CH_0, rank 0
2613 12:43:42.165974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2614 12:43:42.169331 ==
2615 12:43:42.169757 DQS Delay:
2616 12:43:42.170144 DQS0 = 0, DQS1 = 0
2617 12:43:42.172556 DQM Delay:
2618 12:43:42.172986 DQM0 = 123, DQM1 = 110
2619 12:43:42.176154 DQ Delay:
2620 12:43:42.179630 DQ0 =123, DQ1 =127, DQ2 =119, DQ3 =119
2621 12:43:42.182519 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2622 12:43:42.185829 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2623 12:43:42.189262 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2624 12:43:42.189397
2625 12:43:42.189490
2626 12:43:42.189579 ==
2627 12:43:42.192340 Dram Type= 6, Freq= 0, CH_0, rank 0
2628 12:43:42.195771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2629 12:43:42.195856 ==
2630 12:43:42.195922
2631 12:43:42.195982
2632 12:43:42.199097 TX Vref Scan disable
2633 12:43:42.202352 == TX Byte 0 ==
2634 12:43:42.205838 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2635 12:43:42.208918 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2636 12:43:42.212593 == TX Byte 1 ==
2637 12:43:42.215651 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2638 12:43:42.219179 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2639 12:43:42.219276 ==
2640 12:43:42.222377 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 12:43:42.225750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 12:43:42.229258 ==
2643 12:43:42.239617 TX Vref=22, minBit 7, minWin=23, winSum=402
2644 12:43:42.242787 TX Vref=24, minBit 0, minWin=25, winSum=407
2645 12:43:42.245877 TX Vref=26, minBit 0, minWin=25, winSum=413
2646 12:43:42.249516 TX Vref=28, minBit 7, minWin=25, winSum=420
2647 12:43:42.253063 TX Vref=30, minBit 3, minWin=25, winSum=418
2648 12:43:42.256256 TX Vref=32, minBit 3, minWin=25, winSum=417
2649 12:43:42.262925 [TxChooseVref] Worse bit 7, Min win 25, Win sum 420, Final Vref 28
2650 12:43:42.263173
2651 12:43:42.266363 Final TX Range 1 Vref 28
2652 12:43:42.266670
2653 12:43:42.266920 ==
2654 12:43:42.269877 Dram Type= 6, Freq= 0, CH_0, rank 0
2655 12:43:42.273371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2656 12:43:42.273824 ==
2657 12:43:42.274250
2658 12:43:42.274574
2659 12:43:42.276625 TX Vref Scan disable
2660 12:43:42.279714 == TX Byte 0 ==
2661 12:43:42.282996 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2662 12:43:42.286384 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2663 12:43:42.289721 == TX Byte 1 ==
2664 12:43:42.293247 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2665 12:43:42.296262 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2666 12:43:42.296693
2667 12:43:42.299950 [DATLAT]
2668 12:43:42.300374 Freq=1200, CH0 RK0
2669 12:43:42.300715
2670 12:43:42.302982 DATLAT Default: 0xd
2671 12:43:42.303517 0, 0xFFFF, sum = 0
2672 12:43:42.306408 1, 0xFFFF, sum = 0
2673 12:43:42.306845 2, 0xFFFF, sum = 0
2674 12:43:42.309758 3, 0xFFFF, sum = 0
2675 12:43:42.310231 4, 0xFFFF, sum = 0
2676 12:43:42.313245 5, 0xFFFF, sum = 0
2677 12:43:42.313680 6, 0xFFFF, sum = 0
2678 12:43:42.316658 7, 0xFFFF, sum = 0
2679 12:43:42.317091 8, 0xFFFF, sum = 0
2680 12:43:42.319583 9, 0xFFFF, sum = 0
2681 12:43:42.319989 10, 0xFFFF, sum = 0
2682 12:43:42.323277 11, 0xFFFF, sum = 0
2683 12:43:42.323711 12, 0x0, sum = 1
2684 12:43:42.326391 13, 0x0, sum = 2
2685 12:43:42.326825 14, 0x0, sum = 3
2686 12:43:42.330028 15, 0x0, sum = 4
2687 12:43:42.330462 best_step = 13
2688 12:43:42.330800
2689 12:43:42.331112 ==
2690 12:43:42.333224 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 12:43:42.339651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 12:43:42.340082 ==
2693 12:43:42.340421 RX Vref Scan: 1
2694 12:43:42.340736
2695 12:43:42.343418 Set Vref Range= 32 -> 127
2696 12:43:42.343848
2697 12:43:42.346378 RX Vref 32 -> 127, step: 1
2698 12:43:42.346810
2699 12:43:42.349666 RX Delay -13 -> 252, step: 4
2700 12:43:42.350120
2701 12:43:42.350463 Set Vref, RX VrefLevel [Byte0]: 32
2702 12:43:42.352984 [Byte1]: 32
2703 12:43:42.357687
2704 12:43:42.358137 Set Vref, RX VrefLevel [Byte0]: 33
2705 12:43:42.361072 [Byte1]: 33
2706 12:43:42.365793
2707 12:43:42.366283 Set Vref, RX VrefLevel [Byte0]: 34
2708 12:43:42.369134 [Byte1]: 34
2709 12:43:42.373423
2710 12:43:42.373849 Set Vref, RX VrefLevel [Byte0]: 35
2711 12:43:42.376778 [Byte1]: 35
2712 12:43:42.381519
2713 12:43:42.382002 Set Vref, RX VrefLevel [Byte0]: 36
2714 12:43:42.384625 [Byte1]: 36
2715 12:43:42.389436
2716 12:43:42.389862 Set Vref, RX VrefLevel [Byte0]: 37
2717 12:43:42.392296 [Byte1]: 37
2718 12:43:42.397111
2719 12:43:42.397536 Set Vref, RX VrefLevel [Byte0]: 38
2720 12:43:42.400436 [Byte1]: 38
2721 12:43:42.405162
2722 12:43:42.405587 Set Vref, RX VrefLevel [Byte0]: 39
2723 12:43:42.408435 [Byte1]: 39
2724 12:43:42.412975
2725 12:43:42.413398 Set Vref, RX VrefLevel [Byte0]: 40
2726 12:43:42.416176 [Byte1]: 40
2727 12:43:42.420794
2728 12:43:42.421222 Set Vref, RX VrefLevel [Byte0]: 41
2729 12:43:42.424108 [Byte1]: 41
2730 12:43:42.428872
2731 12:43:42.429311 Set Vref, RX VrefLevel [Byte0]: 42
2732 12:43:42.431992 [Byte1]: 42
2733 12:43:42.436631
2734 12:43:42.437059 Set Vref, RX VrefLevel [Byte0]: 43
2735 12:43:42.439999 [Byte1]: 43
2736 12:43:42.444319
2737 12:43:42.444747 Set Vref, RX VrefLevel [Byte0]: 44
2738 12:43:42.447830 [Byte1]: 44
2739 12:43:42.452730
2740 12:43:42.453156 Set Vref, RX VrefLevel [Byte0]: 45
2741 12:43:42.456139 [Byte1]: 45
2742 12:43:42.460087
2743 12:43:42.460513 Set Vref, RX VrefLevel [Byte0]: 46
2744 12:43:42.463433 [Byte1]: 46
2745 12:43:42.468387
2746 12:43:42.468819 Set Vref, RX VrefLevel [Byte0]: 47
2747 12:43:42.471668 [Byte1]: 47
2748 12:43:42.476111
2749 12:43:42.476537 Set Vref, RX VrefLevel [Byte0]: 48
2750 12:43:42.479431 [Byte1]: 48
2751 12:43:42.483704
2752 12:43:42.484131 Set Vref, RX VrefLevel [Byte0]: 49
2753 12:43:42.487160 [Byte1]: 49
2754 12:43:42.491652
2755 12:43:42.492081 Set Vref, RX VrefLevel [Byte0]: 50
2756 12:43:42.494991 [Byte1]: 50
2757 12:43:42.499694
2758 12:43:42.500121 Set Vref, RX VrefLevel [Byte0]: 51
2759 12:43:42.502851 [Byte1]: 51
2760 12:43:42.507791
2761 12:43:42.508218 Set Vref, RX VrefLevel [Byte0]: 52
2762 12:43:42.511044 [Byte1]: 52
2763 12:43:42.515331
2764 12:43:42.515761 Set Vref, RX VrefLevel [Byte0]: 53
2765 12:43:42.518751 [Byte1]: 53
2766 12:43:42.523243
2767 12:43:42.523673 Set Vref, RX VrefLevel [Byte0]: 54
2768 12:43:42.526652 [Byte1]: 54
2769 12:43:42.531129
2770 12:43:42.531558 Set Vref, RX VrefLevel [Byte0]: 55
2771 12:43:42.534624 [Byte1]: 55
2772 12:43:42.539291
2773 12:43:42.539714 Set Vref, RX VrefLevel [Byte0]: 56
2774 12:43:42.542362 [Byte1]: 56
2775 12:43:42.547089
2776 12:43:42.547514 Set Vref, RX VrefLevel [Byte0]: 57
2777 12:43:42.550513 [Byte1]: 57
2778 12:43:42.555034
2779 12:43:42.555615 Set Vref, RX VrefLevel [Byte0]: 58
2780 12:43:42.558412 [Byte1]: 58
2781 12:43:42.562660
2782 12:43:42.563082 Set Vref, RX VrefLevel [Byte0]: 59
2783 12:43:42.566051 [Byte1]: 59
2784 12:43:42.570761
2785 12:43:42.571184 Set Vref, RX VrefLevel [Byte0]: 60
2786 12:43:42.574266 [Byte1]: 60
2787 12:43:42.578628
2788 12:43:42.579052 Set Vref, RX VrefLevel [Byte0]: 61
2789 12:43:42.582024 [Byte1]: 61
2790 12:43:42.586716
2791 12:43:42.587141 Set Vref, RX VrefLevel [Byte0]: 62
2792 12:43:42.590016 [Byte1]: 62
2793 12:43:42.594492
2794 12:43:42.594927 Set Vref, RX VrefLevel [Byte0]: 63
2795 12:43:42.597804 [Byte1]: 63
2796 12:43:42.602175
2797 12:43:42.602596 Set Vref, RX VrefLevel [Byte0]: 64
2798 12:43:42.605423 [Byte1]: 64
2799 12:43:42.610094
2800 12:43:42.610517 Set Vref, RX VrefLevel [Byte0]: 65
2801 12:43:42.613543 [Byte1]: 65
2802 12:43:42.618053
2803 12:43:42.618476 Set Vref, RX VrefLevel [Byte0]: 66
2804 12:43:42.621711 [Byte1]: 66
2805 12:43:42.626503
2806 12:43:42.627080 Set Vref, RX VrefLevel [Byte0]: 67
2807 12:43:42.629565 [Byte1]: 67
2808 12:43:42.634128
2809 12:43:42.634607 Set Vref, RX VrefLevel [Byte0]: 68
2810 12:43:42.637181 [Byte1]: 68
2811 12:43:42.641812
2812 12:43:42.642306 Set Vref, RX VrefLevel [Byte0]: 69
2813 12:43:42.645205 [Byte1]: 69
2814 12:43:42.649419
2815 12:43:42.649886 Set Vref, RX VrefLevel [Byte0]: 70
2816 12:43:42.652956 [Byte1]: 70
2817 12:43:42.657638
2818 12:43:42.658134 Set Vref, RX VrefLevel [Byte0]: 71
2819 12:43:42.660781 [Byte1]: 71
2820 12:43:42.665716
2821 12:43:42.666221 Final RX Vref Byte 0 = 61 to rank0
2822 12:43:42.668943 Final RX Vref Byte 1 = 49 to rank0
2823 12:43:42.672220 Final RX Vref Byte 0 = 61 to rank1
2824 12:43:42.675366 Final RX Vref Byte 1 = 49 to rank1==
2825 12:43:42.678899 Dram Type= 6, Freq= 0, CH_0, rank 0
2826 12:43:42.685742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2827 12:43:42.686205 ==
2828 12:43:42.686544 DQS Delay:
2829 12:43:42.686854 DQS0 = 0, DQS1 = 0
2830 12:43:42.688746 DQM Delay:
2831 12:43:42.689170 DQM0 = 123, DQM1 = 109
2832 12:43:42.692188 DQ Delay:
2833 12:43:42.695767 DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120
2834 12:43:42.699054 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2835 12:43:42.702297 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =106
2836 12:43:42.706037 DQ12 =114, DQ13 =110, DQ14 =122, DQ15 =116
2837 12:43:42.706468
2838 12:43:42.706803
2839 12:43:42.712078 [DQSOSCAuto] RK0, (LSB)MR18= 0xb08, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2840 12:43:42.715354 CH0 RK0: MR19=404, MR18=B08
2841 12:43:42.722376 CH0_RK0: MR19=0x404, MR18=0xB08, DQSOSC=405, MR23=63, INC=39, DEC=26
2842 12:43:42.722804
2843 12:43:42.725198 ----->DramcWriteLeveling(PI) begin...
2844 12:43:42.725625 ==
2845 12:43:42.728418 Dram Type= 6, Freq= 0, CH_0, rank 1
2846 12:43:42.732180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2847 12:43:42.735449 ==
2848 12:43:42.735872 Write leveling (Byte 0): 35 => 35
2849 12:43:42.738695 Write leveling (Byte 1): 31 => 31
2850 12:43:42.742104 DramcWriteLeveling(PI) end<-----
2851 12:43:42.742532
2852 12:43:42.742868 ==
2853 12:43:42.745094 Dram Type= 6, Freq= 0, CH_0, rank 1
2854 12:43:42.751919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2855 12:43:42.752348 ==
2856 12:43:42.752686 [Gating] SW mode calibration
2857 12:43:42.761581 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2858 12:43:42.765140 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2859 12:43:42.768196 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2860 12:43:42.774918 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 12:43:42.778229 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 12:43:42.781836 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 12:43:42.787869 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 12:43:42.791433 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 12:43:42.794782 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2866 12:43:42.801728 0 15 28 | B1->B0 | 2f2f 2f2f | 1 0 | (1 0) (0 1)
2867 12:43:42.805174 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2868 12:43:42.808685 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 12:43:42.815004 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 12:43:42.818394 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 12:43:42.821877 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 12:43:42.828536 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 12:43:42.831765 1 0 24 | B1->B0 | 2424 2929 | 0 1 | (0 0) (0 0)
2874 12:43:42.835043 1 0 28 | B1->B0 | 3737 3e3e | 0 0 | (0 0) (0 0)
2875 12:43:42.841755 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2876 12:43:42.845027 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 12:43:42.848377 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 12:43:42.851949 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 12:43:42.858707 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 12:43:42.861870 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 12:43:42.865387 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 12:43:42.871770 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2883 12:43:42.875332 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 12:43:42.878432 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 12:43:42.885532 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 12:43:42.888443 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 12:43:42.891820 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 12:43:42.898643 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 12:43:42.902281 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 12:43:42.905487 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 12:43:42.911914 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 12:43:42.915362 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 12:43:42.918909 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 12:43:42.925512 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 12:43:42.928617 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 12:43:42.931843 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 12:43:42.938712 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2898 12:43:42.942059 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2899 12:43:42.945086 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2900 12:43:42.948372 Total UI for P1: 0, mck2ui 16
2901 12:43:42.951771 best dqsien dly found for B0: ( 1, 3, 26)
2902 12:43:42.955004 Total UI for P1: 0, mck2ui 16
2903 12:43:42.958507 best dqsien dly found for B1: ( 1, 3, 30)
2904 12:43:42.961723 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2905 12:43:42.965051 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2906 12:43:42.965477
2907 12:43:42.968576 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2908 12:43:42.971630 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2909 12:43:42.974841 [Gating] SW calibration Done
2910 12:43:42.974923 ==
2911 12:43:42.978332 Dram Type= 6, Freq= 0, CH_0, rank 1
2912 12:43:42.984812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2913 12:43:42.984895 ==
2914 12:43:42.984961 RX Vref Scan: 0
2915 12:43:42.985022
2916 12:43:42.988208 RX Vref 0 -> 0, step: 1
2917 12:43:42.988291
2918 12:43:42.991474 RX Delay -40 -> 252, step: 8
2919 12:43:42.994812 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2920 12:43:42.998587 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2921 12:43:43.001853 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2922 12:43:43.005103 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2923 12:43:43.011604 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2924 12:43:43.014788 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2925 12:43:43.018476 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2926 12:43:43.021861 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2927 12:43:43.024787 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2928 12:43:43.028746 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2929 12:43:43.035401 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2930 12:43:43.038306 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2931 12:43:43.041458 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2932 12:43:43.045180 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2933 12:43:43.051953 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2934 12:43:43.055401 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2935 12:43:43.055485 ==
2936 12:43:43.058843 Dram Type= 6, Freq= 0, CH_0, rank 1
2937 12:43:43.061874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2938 12:43:43.061995 ==
2939 12:43:43.062061 DQS Delay:
2940 12:43:43.065073 DQS0 = 0, DQS1 = 0
2941 12:43:43.065155 DQM Delay:
2942 12:43:43.068532 DQM0 = 120, DQM1 = 108
2943 12:43:43.068615 DQ Delay:
2944 12:43:43.071929 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2945 12:43:43.075317 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2946 12:43:43.078889 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2947 12:43:43.082088 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2948 12:43:43.082172
2949 12:43:43.082237
2950 12:43:43.085306 ==
2951 12:43:43.088748 Dram Type= 6, Freq= 0, CH_0, rank 1
2952 12:43:43.091783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2953 12:43:43.091867 ==
2954 12:43:43.091933
2955 12:43:43.091993
2956 12:43:43.095212 TX Vref Scan disable
2957 12:43:43.095296 == TX Byte 0 ==
2958 12:43:43.098555 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2959 12:43:43.105170 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2960 12:43:43.105259 == TX Byte 1 ==
2961 12:43:43.108679 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2962 12:43:43.115238 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2963 12:43:43.115348 ==
2964 12:43:43.118872 Dram Type= 6, Freq= 0, CH_0, rank 1
2965 12:43:43.122141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2966 12:43:43.122239 ==
2967 12:43:43.134556 TX Vref=22, minBit 1, minWin=24, winSum=408
2968 12:43:43.137550 TX Vref=24, minBit 0, minWin=25, winSum=410
2969 12:43:43.140796 TX Vref=26, minBit 1, minWin=25, winSum=414
2970 12:43:43.144286 TX Vref=28, minBit 1, minWin=25, winSum=415
2971 12:43:43.147923 TX Vref=30, minBit 1, minWin=25, winSum=421
2972 12:43:43.151218 TX Vref=32, minBit 3, minWin=25, winSum=420
2973 12:43:43.157984 [TxChooseVref] Worse bit 1, Min win 25, Win sum 421, Final Vref 30
2974 12:43:43.158097
2975 12:43:43.160932 Final TX Range 1 Vref 30
2976 12:43:43.161055
2977 12:43:43.161153 ==
2978 12:43:43.164486 Dram Type= 6, Freq= 0, CH_0, rank 1
2979 12:43:43.167691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2980 12:43:43.167894 ==
2981 12:43:43.168002
2982 12:43:43.168103
2983 12:43:43.171206 TX Vref Scan disable
2984 12:43:43.174550 == TX Byte 0 ==
2985 12:43:43.177631 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2986 12:43:43.181091 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2987 12:43:43.184245 == TX Byte 1 ==
2988 12:43:43.188158 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2989 12:43:43.190997 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2990 12:43:43.191440
2991 12:43:43.194784 [DATLAT]
2992 12:43:43.195368 Freq=1200, CH0 RK1
2993 12:43:43.195839
2994 12:43:43.198137 DATLAT Default: 0xd
2995 12:43:43.198752 0, 0xFFFF, sum = 0
2996 12:43:43.201197 1, 0xFFFF, sum = 0
2997 12:43:43.201882 2, 0xFFFF, sum = 0
2998 12:43:43.204392 3, 0xFFFF, sum = 0
2999 12:43:43.205045 4, 0xFFFF, sum = 0
3000 12:43:43.207767 5, 0xFFFF, sum = 0
3001 12:43:43.208355 6, 0xFFFF, sum = 0
3002 12:43:43.211483 7, 0xFFFF, sum = 0
3003 12:43:43.212068 8, 0xFFFF, sum = 0
3004 12:43:43.214756 9, 0xFFFF, sum = 0
3005 12:43:43.218152 10, 0xFFFF, sum = 0
3006 12:43:43.218710 11, 0xFFFF, sum = 0
3007 12:43:43.221153 12, 0x0, sum = 1
3008 12:43:43.221547 13, 0x0, sum = 2
3009 12:43:43.222062 14, 0x0, sum = 3
3010 12:43:43.224783 15, 0x0, sum = 4
3011 12:43:43.225344 best_step = 13
3012 12:43:43.225760
3013 12:43:43.226138 ==
3014 12:43:43.228108 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 12:43:43.234532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 12:43:43.235104 ==
3017 12:43:43.235607 RX Vref Scan: 0
3018 12:43:43.236091
3019 12:43:43.237749 RX Vref 0 -> 0, step: 1
3020 12:43:43.238267
3021 12:43:43.241384 RX Delay -21 -> 252, step: 4
3022 12:43:43.244826 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3023 12:43:43.247742 iDelay=199, Bit 1, Center 122 (55 ~ 190) 136
3024 12:43:43.254653 iDelay=199, Bit 2, Center 118 (51 ~ 186) 136
3025 12:43:43.258142 iDelay=199, Bit 3, Center 116 (51 ~ 182) 132
3026 12:43:43.261300 iDelay=199, Bit 4, Center 122 (55 ~ 190) 136
3027 12:43:43.264676 iDelay=199, Bit 5, Center 114 (51 ~ 178) 128
3028 12:43:43.268011 iDelay=199, Bit 6, Center 128 (59 ~ 198) 140
3029 12:43:43.274595 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3030 12:43:43.277978 iDelay=199, Bit 8, Center 98 (35 ~ 162) 128
3031 12:43:43.281131 iDelay=199, Bit 9, Center 94 (31 ~ 158) 128
3032 12:43:43.284723 iDelay=199, Bit 10, Center 110 (47 ~ 174) 128
3033 12:43:43.287926 iDelay=199, Bit 11, Center 106 (43 ~ 170) 128
3034 12:43:43.294630 iDelay=199, Bit 12, Center 114 (51 ~ 178) 128
3035 12:43:43.297424 iDelay=199, Bit 13, Center 110 (47 ~ 174) 128
3036 12:43:43.300820 iDelay=199, Bit 14, Center 116 (55 ~ 178) 124
3037 12:43:43.304347 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
3038 12:43:43.304430 ==
3039 12:43:43.307612 Dram Type= 6, Freq= 0, CH_0, rank 1
3040 12:43:43.314115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3041 12:43:43.314233 ==
3042 12:43:43.314307 DQS Delay:
3043 12:43:43.314373 DQS0 = 0, DQS1 = 0
3044 12:43:43.317559 DQM Delay:
3045 12:43:43.317647 DQM0 = 120, DQM1 = 107
3046 12:43:43.320806 DQ Delay:
3047 12:43:43.324149 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =116
3048 12:43:43.327315 DQ4 =122, DQ5 =114, DQ6 =128, DQ7 =124
3049 12:43:43.330856 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3050 12:43:43.334105 DQ12 =114, DQ13 =110, DQ14 =116, DQ15 =114
3051 12:43:43.334230
3052 12:43:43.334327
3053 12:43:43.341312 [DQSOSCAuto] RK1, (LSB)MR18= 0xef5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 404 ps
3054 12:43:43.344177 CH0 RK1: MR19=403, MR18=EF5
3055 12:43:43.351397 CH0_RK1: MR19=0x403, MR18=0xEF5, DQSOSC=404, MR23=63, INC=40, DEC=26
3056 12:43:43.354218 [RxdqsGatingPostProcess] freq 1200
3057 12:43:43.360784 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3058 12:43:43.364282 best DQS0 dly(2T, 0.5T) = (0, 11)
3059 12:43:43.364589 best DQS1 dly(2T, 0.5T) = (0, 12)
3060 12:43:43.367832 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3061 12:43:43.371104 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3062 12:43:43.374545 best DQS0 dly(2T, 0.5T) = (0, 11)
3063 12:43:43.378025 best DQS1 dly(2T, 0.5T) = (0, 11)
3064 12:43:43.381418 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3065 12:43:43.384735 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3066 12:43:43.387833 Pre-setting of DQS Precalculation
3067 12:43:43.391657 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3068 12:43:43.394939 ==
3069 12:43:43.397932 Dram Type= 6, Freq= 0, CH_1, rank 0
3070 12:43:43.401227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 12:43:43.401657 ==
3072 12:43:43.404770 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3073 12:43:43.411202 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3074 12:43:43.420463 [CA 0] Center 37 (7~68) winsize 62
3075 12:43:43.423983 [CA 1] Center 37 (7~68) winsize 62
3076 12:43:43.427367 [CA 2] Center 35 (5~65) winsize 61
3077 12:43:43.430391 [CA 3] Center 34 (4~65) winsize 62
3078 12:43:43.433928 [CA 4] Center 34 (4~64) winsize 61
3079 12:43:43.437174 [CA 5] Center 33 (3~64) winsize 62
3080 12:43:43.437593
3081 12:43:43.440525 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3082 12:43:43.440947
3083 12:43:43.443508 [CATrainingPosCal] consider 1 rank data
3084 12:43:43.447434 u2DelayCellTimex100 = 270/100 ps
3085 12:43:43.450407 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3086 12:43:43.453843 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3087 12:43:43.460740 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3088 12:43:43.463894 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3089 12:43:43.467344 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3090 12:43:43.470668 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3091 12:43:43.471089
3092 12:43:43.474164 CA PerBit enable=1, Macro0, CA PI delay=33
3093 12:43:43.474583
3094 12:43:43.477067 [CBTSetCACLKResult] CA Dly = 33
3095 12:43:43.477186 CS Dly: 5 (0~36)
3096 12:43:43.477253 ==
3097 12:43:43.480577 Dram Type= 6, Freq= 0, CH_1, rank 1
3098 12:43:43.486937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3099 12:43:43.487021 ==
3100 12:43:43.490673 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3101 12:43:43.496909 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3102 12:43:43.505605 [CA 0] Center 38 (8~68) winsize 61
3103 12:43:43.509038 [CA 1] Center 38 (7~69) winsize 63
3104 12:43:43.512759 [CA 2] Center 35 (5~66) winsize 62
3105 12:43:43.515769 [CA 3] Center 35 (5~65) winsize 61
3106 12:43:43.519247 [CA 4] Center 34 (4~64) winsize 61
3107 12:43:43.522227 [CA 5] Center 34 (4~64) winsize 61
3108 12:43:43.522318
3109 12:43:43.525837 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3110 12:43:43.525919
3111 12:43:43.529295 [CATrainingPosCal] consider 2 rank data
3112 12:43:43.532548 u2DelayCellTimex100 = 270/100 ps
3113 12:43:43.535543 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3114 12:43:43.539136 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3115 12:43:43.542617 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3116 12:43:43.549128 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3117 12:43:43.552625 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3118 12:43:43.555884 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3119 12:43:43.555968
3120 12:43:43.559141 CA PerBit enable=1, Macro0, CA PI delay=34
3121 12:43:43.559208
3122 12:43:43.562502 [CBTSetCACLKResult] CA Dly = 34
3123 12:43:43.562583 CS Dly: 6 (0~39)
3124 12:43:43.562648
3125 12:43:43.565707 ----->DramcWriteLeveling(PI) begin...
3126 12:43:43.568894 ==
3127 12:43:43.568970 Dram Type= 6, Freq= 0, CH_1, rank 0
3128 12:43:43.575804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3129 12:43:43.575887 ==
3130 12:43:43.579273 Write leveling (Byte 0): 25 => 25
3131 12:43:43.582610 Write leveling (Byte 1): 27 => 27
3132 12:43:43.582692 DramcWriteLeveling(PI) end<-----
3133 12:43:43.585863
3134 12:43:43.585975 ==
3135 12:43:43.589009 Dram Type= 6, Freq= 0, CH_1, rank 0
3136 12:43:43.592715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3137 12:43:43.592827 ==
3138 12:43:43.595952 [Gating] SW mode calibration
3139 12:43:43.602763 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3140 12:43:43.605808 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3141 12:43:43.612679 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 12:43:43.616069 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 12:43:43.619218 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 12:43:43.626115 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 12:43:43.629581 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 12:43:43.632574 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3147 12:43:43.639437 0 15 24 | B1->B0 | 2f2f 2d2d | 0 0 | (0 0) (0 0)
3148 12:43:43.642944 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 12:43:43.646034 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 12:43:43.652581 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 12:43:43.656124 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 12:43:43.659027 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 12:43:43.665742 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 12:43:43.669489 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3155 12:43:43.672665 1 0 24 | B1->B0 | 4040 4545 | 0 0 | (0 0) (0 0)
3156 12:43:43.676031 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 12:43:43.682541 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 12:43:43.685785 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 12:43:43.689163 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 12:43:43.695959 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 12:43:43.699641 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 12:43:43.702598 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 12:43:43.709281 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3164 12:43:43.712877 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3165 12:43:43.716339 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 12:43:43.722723 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 12:43:43.726231 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 12:43:43.729200 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 12:43:43.736341 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 12:43:43.739615 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 12:43:43.742623 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 12:43:43.749485 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 12:43:43.753013 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 12:43:43.756296 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 12:43:43.759183 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 12:43:43.766101 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 12:43:43.769352 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 12:43:43.772523 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3179 12:43:43.779508 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3180 12:43:43.782958 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3181 12:43:43.785886 Total UI for P1: 0, mck2ui 16
3182 12:43:43.789623 best dqsien dly found for B0: ( 1, 3, 22)
3183 12:43:43.792615 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 12:43:43.796263 Total UI for P1: 0, mck2ui 16
3185 12:43:43.799518 best dqsien dly found for B1: ( 1, 3, 26)
3186 12:43:43.802794 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3187 12:43:43.806089 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3188 12:43:43.806173
3189 12:43:43.812714 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3190 12:43:43.816106 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3191 12:43:43.816191 [Gating] SW calibration Done
3192 12:43:43.819800 ==
3193 12:43:43.823141 Dram Type= 6, Freq= 0, CH_1, rank 0
3194 12:43:43.825909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3195 12:43:43.826001 ==
3196 12:43:43.826068 RX Vref Scan: 0
3197 12:43:43.826130
3198 12:43:43.829375 RX Vref 0 -> 0, step: 1
3199 12:43:43.829458
3200 12:43:43.833025 RX Delay -40 -> 252, step: 8
3201 12:43:43.836122 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3202 12:43:43.839405 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3203 12:43:43.843139 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3204 12:43:43.849394 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3205 12:43:43.853016 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3206 12:43:43.856079 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3207 12:43:43.859726 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3208 12:43:43.862910 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3209 12:43:43.869552 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3210 12:43:43.872998 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3211 12:43:43.875910 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3212 12:43:43.879608 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3213 12:43:43.883188 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3214 12:43:43.889703 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3215 12:43:43.893063 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3216 12:43:43.896460 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3217 12:43:43.896575 ==
3218 12:43:43.899848 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 12:43:43.903039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 12:43:43.903165 ==
3221 12:43:43.906345 DQS Delay:
3222 12:43:43.906484 DQS0 = 0, DQS1 = 0
3223 12:43:43.909464 DQM Delay:
3224 12:43:43.909619 DQM0 = 120, DQM1 = 112
3225 12:43:43.909742 DQ Delay:
3226 12:43:43.912814 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =123
3227 12:43:43.919931 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3228 12:43:43.922856 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3229 12:43:43.926325 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3230 12:43:43.926572
3231 12:43:43.926767
3232 12:43:43.926948 ==
3233 12:43:43.929703 Dram Type= 6, Freq= 0, CH_1, rank 0
3234 12:43:43.933621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3235 12:43:43.934066 ==
3236 12:43:43.934389
3237 12:43:43.934684
3238 12:43:43.936568 TX Vref Scan disable
3239 12:43:43.936964 == TX Byte 0 ==
3240 12:43:43.943310 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3241 12:43:43.946786 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3242 12:43:43.947221 == TX Byte 1 ==
3243 12:43:43.953681 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3244 12:43:43.957010 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3245 12:43:43.957573 ==
3246 12:43:43.960248 Dram Type= 6, Freq= 0, CH_1, rank 0
3247 12:43:43.963700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3248 12:43:43.964180 ==
3249 12:43:43.976250 TX Vref=22, minBit 10, minWin=23, winSum=404
3250 12:43:43.979762 TX Vref=24, minBit 11, minWin=24, winSum=409
3251 12:43:43.982723 TX Vref=26, minBit 3, minWin=25, winSum=413
3252 12:43:43.986045 TX Vref=28, minBit 10, minWin=25, winSum=421
3253 12:43:43.989272 TX Vref=30, minBit 10, minWin=25, winSum=422
3254 12:43:43.995823 TX Vref=32, minBit 1, minWin=26, winSum=424
3255 12:43:43.999222 [TxChooseVref] Worse bit 1, Min win 26, Win sum 424, Final Vref 32
3256 12:43:43.999695
3257 12:43:44.002672 Final TX Range 1 Vref 32
3258 12:43:44.003142
3259 12:43:44.003513 ==
3260 12:43:44.005969 Dram Type= 6, Freq= 0, CH_1, rank 0
3261 12:43:44.009402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3262 12:43:44.010031 ==
3263 12:43:44.012363
3264 12:43:44.012786
3265 12:43:44.013119 TX Vref Scan disable
3266 12:43:44.015759 == TX Byte 0 ==
3267 12:43:44.019226 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3268 12:43:44.022446 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3269 12:43:44.026292 == TX Byte 1 ==
3270 12:43:44.029360 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3271 12:43:44.032498 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3272 12:43:44.035827
3273 12:43:44.036297 [DATLAT]
3274 12:43:44.036787 Freq=1200, CH1 RK0
3275 12:43:44.037176
3276 12:43:44.039334 DATLAT Default: 0xd
3277 12:43:44.039819 0, 0xFFFF, sum = 0
3278 12:43:44.042772 1, 0xFFFF, sum = 0
3279 12:43:44.043236 2, 0xFFFF, sum = 0
3280 12:43:44.045921 3, 0xFFFF, sum = 0
3281 12:43:44.049563 4, 0xFFFF, sum = 0
3282 12:43:44.050041 5, 0xFFFF, sum = 0
3283 12:43:44.052612 6, 0xFFFF, sum = 0
3284 12:43:44.053052 7, 0xFFFF, sum = 0
3285 12:43:44.056141 8, 0xFFFF, sum = 0
3286 12:43:44.056661 9, 0xFFFF, sum = 0
3287 12:43:44.059759 10, 0xFFFF, sum = 0
3288 12:43:44.060332 11, 0xFFFF, sum = 0
3289 12:43:44.062900 12, 0x0, sum = 1
3290 12:43:44.063331 13, 0x0, sum = 2
3291 12:43:44.066201 14, 0x0, sum = 3
3292 12:43:44.066634 15, 0x0, sum = 4
3293 12:43:44.066975 best_step = 13
3294 12:43:44.067288
3295 12:43:44.069371 ==
3296 12:43:44.072772 Dram Type= 6, Freq= 0, CH_1, rank 0
3297 12:43:44.075944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3298 12:43:44.076373 ==
3299 12:43:44.076709 RX Vref Scan: 1
3300 12:43:44.077018
3301 12:43:44.079173 Set Vref Range= 32 -> 127
3302 12:43:44.079589
3303 12:43:44.082822 RX Vref 32 -> 127, step: 1
3304 12:43:44.083234
3305 12:43:44.085910 RX Delay -13 -> 252, step: 4
3306 12:43:44.086361
3307 12:43:44.089419 Set Vref, RX VrefLevel [Byte0]: 32
3308 12:43:44.092756 [Byte1]: 32
3309 12:43:44.093171
3310 12:43:44.096064 Set Vref, RX VrefLevel [Byte0]: 33
3311 12:43:44.098814 [Byte1]: 33
3312 12:43:44.102346
3313 12:43:44.102569 Set Vref, RX VrefLevel [Byte0]: 34
3314 12:43:44.105865 [Byte1]: 34
3315 12:43:44.109964
3316 12:43:44.110201 Set Vref, RX VrefLevel [Byte0]: 35
3317 12:43:44.113669 [Byte1]: 35
3318 12:43:44.117807
3319 12:43:44.118113 Set Vref, RX VrefLevel [Byte0]: 36
3320 12:43:44.121361 [Byte1]: 36
3321 12:43:44.126094
3322 12:43:44.126327 Set Vref, RX VrefLevel [Byte0]: 37
3323 12:43:44.129226 [Byte1]: 37
3324 12:43:44.133736
3325 12:43:44.134022 Set Vref, RX VrefLevel [Byte0]: 38
3326 12:43:44.137063 [Byte1]: 38
3327 12:43:44.141631
3328 12:43:44.142009 Set Vref, RX VrefLevel [Byte0]: 39
3329 12:43:44.145274 [Byte1]: 39
3330 12:43:44.149912
3331 12:43:44.150411 Set Vref, RX VrefLevel [Byte0]: 40
3332 12:43:44.153143 [Byte1]: 40
3333 12:43:44.157727
3334 12:43:44.158202 Set Vref, RX VrefLevel [Byte0]: 41
3335 12:43:44.160871 [Byte1]: 41
3336 12:43:44.165660
3337 12:43:44.166187 Set Vref, RX VrefLevel [Byte0]: 42
3338 12:43:44.168502 [Byte1]: 42
3339 12:43:44.173412
3340 12:43:44.173884 Set Vref, RX VrefLevel [Byte0]: 43
3341 12:43:44.176776 [Byte1]: 43
3342 12:43:44.181255
3343 12:43:44.181710 Set Vref, RX VrefLevel [Byte0]: 44
3344 12:43:44.184667 [Byte1]: 44
3345 12:43:44.189081
3346 12:43:44.189496 Set Vref, RX VrefLevel [Byte0]: 45
3347 12:43:44.192457 [Byte1]: 45
3348 12:43:44.197016
3349 12:43:44.197433 Set Vref, RX VrefLevel [Byte0]: 46
3350 12:43:44.200511 [Byte1]: 46
3351 12:43:44.204673
3352 12:43:44.205136 Set Vref, RX VrefLevel [Byte0]: 47
3353 12:43:44.208348 [Byte1]: 47
3354 12:43:44.213018
3355 12:43:44.213447 Set Vref, RX VrefLevel [Byte0]: 48
3356 12:43:44.216286 [Byte1]: 48
3357 12:43:44.220781
3358 12:43:44.221242 Set Vref, RX VrefLevel [Byte0]: 49
3359 12:43:44.223995 [Byte1]: 49
3360 12:43:44.228678
3361 12:43:44.229135 Set Vref, RX VrefLevel [Byte0]: 50
3362 12:43:44.231735 [Byte1]: 50
3363 12:43:44.236503
3364 12:43:44.236963 Set Vref, RX VrefLevel [Byte0]: 51
3365 12:43:44.239981 [Byte1]: 51
3366 12:43:44.244190
3367 12:43:44.244650 Set Vref, RX VrefLevel [Byte0]: 52
3368 12:43:44.247694 [Byte1]: 52
3369 12:43:44.251968
3370 12:43:44.252426 Set Vref, RX VrefLevel [Byte0]: 53
3371 12:43:44.255711 [Byte1]: 53
3372 12:43:44.260211
3373 12:43:44.260700 Set Vref, RX VrefLevel [Byte0]: 54
3374 12:43:44.263802 [Byte1]: 54
3375 12:43:44.267973
3376 12:43:44.268443 Set Vref, RX VrefLevel [Byte0]: 55
3377 12:43:44.271472 [Byte1]: 55
3378 12:43:44.275693
3379 12:43:44.276118 Set Vref, RX VrefLevel [Byte0]: 56
3380 12:43:44.279261 [Byte1]: 56
3381 12:43:44.284007
3382 12:43:44.284478 Set Vref, RX VrefLevel [Byte0]: 57
3383 12:43:44.287013 [Byte1]: 57
3384 12:43:44.291720
3385 12:43:44.292189 Set Vref, RX VrefLevel [Byte0]: 58
3386 12:43:44.294813 [Byte1]: 58
3387 12:43:44.299571
3388 12:43:44.299678 Set Vref, RX VrefLevel [Byte0]: 59
3389 12:43:44.302627 [Byte1]: 59
3390 12:43:44.307113
3391 12:43:44.307197 Set Vref, RX VrefLevel [Byte0]: 60
3392 12:43:44.310385 [Byte1]: 60
3393 12:43:44.315230
3394 12:43:44.315313 Set Vref, RX VrefLevel [Byte0]: 61
3395 12:43:44.318173 [Byte1]: 61
3396 12:43:44.322769
3397 12:43:44.322853 Set Vref, RX VrefLevel [Byte0]: 62
3398 12:43:44.326053 [Byte1]: 62
3399 12:43:44.330691
3400 12:43:44.330775 Set Vref, RX VrefLevel [Byte0]: 63
3401 12:43:44.334222 [Byte1]: 63
3402 12:43:44.338728
3403 12:43:44.338811 Set Vref, RX VrefLevel [Byte0]: 64
3404 12:43:44.342155 [Byte1]: 64
3405 12:43:44.346477
3406 12:43:44.346563 Set Vref, RX VrefLevel [Byte0]: 65
3407 12:43:44.349692 [Byte1]: 65
3408 12:43:44.354524
3409 12:43:44.354607 Set Vref, RX VrefLevel [Byte0]: 66
3410 12:43:44.357776 [Byte1]: 66
3411 12:43:44.362279
3412 12:43:44.362363 Set Vref, RX VrefLevel [Byte0]: 67
3413 12:43:44.365566 [Byte1]: 67
3414 12:43:44.370348
3415 12:43:44.370431 Final RX Vref Byte 0 = 53 to rank0
3416 12:43:44.373279 Final RX Vref Byte 1 = 56 to rank0
3417 12:43:44.377029 Final RX Vref Byte 0 = 53 to rank1
3418 12:43:44.380036 Final RX Vref Byte 1 = 56 to rank1==
3419 12:43:44.383540 Dram Type= 6, Freq= 0, CH_1, rank 0
3420 12:43:44.387080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3421 12:43:44.390478 ==
3422 12:43:44.390563 DQS Delay:
3423 12:43:44.390629 DQS0 = 0, DQS1 = 0
3424 12:43:44.393632 DQM Delay:
3425 12:43:44.393716 DQM0 = 119, DQM1 = 112
3426 12:43:44.396874 DQ Delay:
3427 12:43:44.400366 DQ0 =120, DQ1 =114, DQ2 =112, DQ3 =118
3428 12:43:44.403667 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =116
3429 12:43:44.407040 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3430 12:43:44.410399 DQ12 =122, DQ13 =118, DQ14 =118, DQ15 =120
3431 12:43:44.410483
3432 12:43:44.410549
3433 12:43:44.417188 [DQSOSCAuto] RK0, (LSB)MR18= 0xff12, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3434 12:43:44.420118 CH1 RK0: MR19=304, MR18=FF12
3435 12:43:44.427187 CH1_RK0: MR19=0x304, MR18=0xFF12, DQSOSC=403, MR23=63, INC=40, DEC=26
3436 12:43:44.427272
3437 12:43:44.430513 ----->DramcWriteLeveling(PI) begin...
3438 12:43:44.430599 ==
3439 12:43:44.433449 Dram Type= 6, Freq= 0, CH_1, rank 1
3440 12:43:44.436769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3441 12:43:44.440417 ==
3442 12:43:44.440501 Write leveling (Byte 0): 26 => 26
3443 12:43:44.444031 Write leveling (Byte 1): 30 => 30
3444 12:43:44.447291 DramcWriteLeveling(PI) end<-----
3445 12:43:44.447375
3446 12:43:44.447441 ==
3447 12:43:44.450745 Dram Type= 6, Freq= 0, CH_1, rank 1
3448 12:43:44.457106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3449 12:43:44.457191 ==
3450 12:43:44.457256 [Gating] SW mode calibration
3451 12:43:44.467013 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3452 12:43:44.470468 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3453 12:43:44.473735 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 12:43:44.480490 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 12:43:44.483579 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3456 12:43:44.486833 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3457 12:43:44.493879 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3458 12:43:44.497432 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3459 12:43:44.500599 0 15 24 | B1->B0 | 2828 3434 | 1 1 | (1 0) (1 0)
3460 12:43:44.507111 0 15 28 | B1->B0 | 2323 2a2a | 0 0 | (1 0) (1 0)
3461 12:43:44.510479 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 12:43:44.513717 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 12:43:44.520456 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 12:43:44.523723 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 12:43:44.527120 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3466 12:43:44.534294 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3467 12:43:44.537867 1 0 24 | B1->B0 | 4040 2e2e | 0 0 | (0 0) (0 0)
3468 12:43:44.541462 1 0 28 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
3469 12:43:44.544543 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 12:43:44.551142 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 12:43:44.554760 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 12:43:44.557814 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 12:43:44.564678 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 12:43:44.568129 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3475 12:43:44.570828 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3476 12:43:44.578295 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3477 12:43:44.580960 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 12:43:44.584318 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 12:43:44.590891 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 12:43:44.594236 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 12:43:44.597232 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 12:43:44.604372 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 12:43:44.607565 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 12:43:44.610728 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 12:43:44.617629 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 12:43:44.620763 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 12:43:44.624521 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 12:43:44.630641 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 12:43:44.634300 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 12:43:44.637509 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 12:43:44.644521 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3492 12:43:44.647667 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3493 12:43:44.650588 Total UI for P1: 0, mck2ui 16
3494 12:43:44.654351 best dqsien dly found for B1: ( 1, 3, 24)
3495 12:43:44.657781 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3496 12:43:44.660717 Total UI for P1: 0, mck2ui 16
3497 12:43:44.664288 best dqsien dly found for B0: ( 1, 3, 26)
3498 12:43:44.667337 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3499 12:43:44.670879 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3500 12:43:44.671457
3501 12:43:44.674003 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3502 12:43:44.680802 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3503 12:43:44.681376 [Gating] SW calibration Done
3504 12:43:44.681753 ==
3505 12:43:44.684090 Dram Type= 6, Freq= 0, CH_1, rank 1
3506 12:43:44.690984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3507 12:43:44.691553 ==
3508 12:43:44.691929 RX Vref Scan: 0
3509 12:43:44.692279
3510 12:43:44.694185 RX Vref 0 -> 0, step: 1
3511 12:43:44.694664
3512 12:43:44.697495 RX Delay -40 -> 252, step: 8
3513 12:43:44.700821 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3514 12:43:44.704136 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3515 12:43:44.707578 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3516 12:43:44.710573 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3517 12:43:44.717317 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3518 12:43:44.720970 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3519 12:43:44.724459 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3520 12:43:44.727593 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3521 12:43:44.730852 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3522 12:43:44.737189 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3523 12:43:44.740481 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3524 12:43:44.744288 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3525 12:43:44.747257 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3526 12:43:44.750800 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3527 12:43:44.757286 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3528 12:43:44.760589 iDelay=200, Bit 15, Center 123 (48 ~ 199) 152
3529 12:43:44.761161 ==
3530 12:43:44.764065 Dram Type= 6, Freq= 0, CH_1, rank 1
3531 12:43:44.767077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3532 12:43:44.767558 ==
3533 12:43:44.770796 DQS Delay:
3534 12:43:44.771375 DQS0 = 0, DQS1 = 0
3535 12:43:44.771795 DQM Delay:
3536 12:43:44.774313 DQM0 = 120, DQM1 = 113
3537 12:43:44.774878 DQ Delay:
3538 12:43:44.777477 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3539 12:43:44.780934 DQ4 =119, DQ5 =131, DQ6 =127, DQ7 =115
3540 12:43:44.783777 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3541 12:43:44.790897 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =123
3542 12:43:44.791464
3543 12:43:44.791841
3544 12:43:44.792190 ==
3545 12:43:44.794010 Dram Type= 6, Freq= 0, CH_1, rank 1
3546 12:43:44.797132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3547 12:43:44.797624 ==
3548 12:43:44.798029
3549 12:43:44.798379
3550 12:43:44.800288 TX Vref Scan disable
3551 12:43:44.800761 == TX Byte 0 ==
3552 12:43:44.807192 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3553 12:43:44.810316 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3554 12:43:44.810792 == TX Byte 1 ==
3555 12:43:44.817393 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3556 12:43:44.820177 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3557 12:43:44.820668 ==
3558 12:43:44.823993 Dram Type= 6, Freq= 0, CH_1, rank 1
3559 12:43:44.827277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3560 12:43:44.827870 ==
3561 12:43:44.840096 TX Vref=22, minBit 1, minWin=25, winSum=421
3562 12:43:44.843507 TX Vref=24, minBit 1, minWin=26, winSum=428
3563 12:43:44.846589 TX Vref=26, minBit 3, minWin=26, winSum=429
3564 12:43:44.849923 TX Vref=28, minBit 3, minWin=26, winSum=430
3565 12:43:44.853763 TX Vref=30, minBit 10, minWin=26, winSum=433
3566 12:43:44.860138 TX Vref=32, minBit 1, minWin=26, winSum=426
3567 12:43:44.863131 [TxChooseVref] Worse bit 10, Min win 26, Win sum 433, Final Vref 30
3568 12:43:44.863610
3569 12:43:44.866605 Final TX Range 1 Vref 30
3570 12:43:44.867082
3571 12:43:44.867457 ==
3572 12:43:44.870078 Dram Type= 6, Freq= 0, CH_1, rank 1
3573 12:43:44.873666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3574 12:43:44.874327 ==
3575 12:43:44.876395
3576 12:43:44.876863
3577 12:43:44.877234 TX Vref Scan disable
3578 12:43:44.879598 == TX Byte 0 ==
3579 12:43:44.882955 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3580 12:43:44.890001 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3581 12:43:44.890576 == TX Byte 1 ==
3582 12:43:44.893036 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3583 12:43:44.899760 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3584 12:43:44.900234
3585 12:43:44.900607 [DATLAT]
3586 12:43:44.900953 Freq=1200, CH1 RK1
3587 12:43:44.901286
3588 12:43:44.903344 DATLAT Default: 0xd
3589 12:43:44.903919 0, 0xFFFF, sum = 0
3590 12:43:44.906142 1, 0xFFFF, sum = 0
3591 12:43:44.906629 2, 0xFFFF, sum = 0
3592 12:43:44.909822 3, 0xFFFF, sum = 0
3593 12:43:44.913022 4, 0xFFFF, sum = 0
3594 12:43:44.913578 5, 0xFFFF, sum = 0
3595 12:43:44.916562 6, 0xFFFF, sum = 0
3596 12:43:44.917076 7, 0xFFFF, sum = 0
3597 12:43:44.919493 8, 0xFFFF, sum = 0
3598 12:43:44.919972 9, 0xFFFF, sum = 0
3599 12:43:44.922848 10, 0xFFFF, sum = 0
3600 12:43:44.923328 11, 0xFFFF, sum = 0
3601 12:43:44.926385 12, 0x0, sum = 1
3602 12:43:44.926865 13, 0x0, sum = 2
3603 12:43:44.929645 14, 0x0, sum = 3
3604 12:43:44.930168 15, 0x0, sum = 4
3605 12:43:44.932900 best_step = 13
3606 12:43:44.933478
3607 12:43:44.933853 ==
3608 12:43:44.936548 Dram Type= 6, Freq= 0, CH_1, rank 1
3609 12:43:44.939888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3610 12:43:44.940486 ==
3611 12:43:44.940864 RX Vref Scan: 0
3612 12:43:44.941217
3613 12:43:44.942627 RX Vref 0 -> 0, step: 1
3614 12:43:44.943103
3615 12:43:44.946065 RX Delay -13 -> 252, step: 4
3616 12:43:44.949599 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3617 12:43:44.956330 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3618 12:43:44.959687 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3619 12:43:44.962594 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3620 12:43:44.966236 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3621 12:43:44.969705 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3622 12:43:44.976122 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3623 12:43:44.979402 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3624 12:43:44.982710 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3625 12:43:44.985923 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3626 12:43:44.989170 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3627 12:43:44.996000 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3628 12:43:44.999506 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3629 12:43:45.002963 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3630 12:43:45.006141 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3631 12:43:45.009618 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3632 12:43:45.012889 ==
3633 12:43:45.016352 Dram Type= 6, Freq= 0, CH_1, rank 1
3634 12:43:45.019366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3635 12:43:45.019839 ==
3636 12:43:45.020228 DQS Delay:
3637 12:43:45.022897 DQS0 = 0, DQS1 = 0
3638 12:43:45.023499 DQM Delay:
3639 12:43:45.026267 DQM0 = 119, DQM1 = 113
3640 12:43:45.026864 DQ Delay:
3641 12:43:45.029620 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3642 12:43:45.032892 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3643 12:43:45.036077 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =108
3644 12:43:45.039378 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3645 12:43:45.039851
3646 12:43:45.040218
3647 12:43:45.049574 [DQSOSCAuto] RK1, (LSB)MR18= 0xbef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3648 12:43:45.050172 CH1 RK1: MR19=403, MR18=BEF
3649 12:43:45.056336 CH1_RK1: MR19=0x403, MR18=0xBEF, DQSOSC=405, MR23=63, INC=39, DEC=26
3650 12:43:45.059366 [RxdqsGatingPostProcess] freq 1200
3651 12:43:45.065673 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3652 12:43:45.069473 best DQS0 dly(2T, 0.5T) = (0, 11)
3653 12:43:45.072441 best DQS1 dly(2T, 0.5T) = (0, 11)
3654 12:43:45.075896 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3655 12:43:45.079104 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3656 12:43:45.082765 best DQS0 dly(2T, 0.5T) = (0, 11)
3657 12:43:45.086089 best DQS1 dly(2T, 0.5T) = (0, 11)
3658 12:43:45.089114 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3659 12:43:45.092726 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3660 12:43:45.093301 Pre-setting of DQS Precalculation
3661 12:43:45.099159 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3662 12:43:45.106220 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3663 12:43:45.112344 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3664 12:43:45.112910
3665 12:43:45.113281
3666 12:43:45.115489 [Calibration Summary] 2400 Mbps
3667 12:43:45.118945 CH 0, Rank 0
3668 12:43:45.119372 SW Impedance : PASS
3669 12:43:45.122367 DUTY Scan : NO K
3670 12:43:45.125787 ZQ Calibration : PASS
3671 12:43:45.126445 Jitter Meter : NO K
3672 12:43:45.128865 CBT Training : PASS
3673 12:43:45.129333 Write leveling : PASS
3674 12:43:45.132306 RX DQS gating : PASS
3675 12:43:45.135746 RX DQ/DQS(RDDQC) : PASS
3676 12:43:45.136369 TX DQ/DQS : PASS
3677 12:43:45.138988 RX DATLAT : PASS
3678 12:43:45.142396 RX DQ/DQS(Engine): PASS
3679 12:43:45.142867 TX OE : NO K
3680 12:43:45.145502 All Pass.
3681 12:43:45.145996
3682 12:43:45.146375 CH 0, Rank 1
3683 12:43:45.148955 SW Impedance : PASS
3684 12:43:45.149425 DUTY Scan : NO K
3685 12:43:45.152278 ZQ Calibration : PASS
3686 12:43:45.155426 Jitter Meter : NO K
3687 12:43:45.156043 CBT Training : PASS
3688 12:43:45.159127 Write leveling : PASS
3689 12:43:45.162465 RX DQS gating : PASS
3690 12:43:45.162938 RX DQ/DQS(RDDQC) : PASS
3691 12:43:45.165715 TX DQ/DQS : PASS
3692 12:43:45.168614 RX DATLAT : PASS
3693 12:43:45.169084 RX DQ/DQS(Engine): PASS
3694 12:43:45.172385 TX OE : NO K
3695 12:43:45.172858 All Pass.
3696 12:43:45.173230
3697 12:43:45.175437 CH 1, Rank 0
3698 12:43:45.175907 SW Impedance : PASS
3699 12:43:45.178955 DUTY Scan : NO K
3700 12:43:45.182231 ZQ Calibration : PASS
3701 12:43:45.182736 Jitter Meter : NO K
3702 12:43:45.185871 CBT Training : PASS
3703 12:43:45.186495 Write leveling : PASS
3704 12:43:45.188784 RX DQS gating : PASS
3705 12:43:45.192415 RX DQ/DQS(RDDQC) : PASS
3706 12:43:45.192986 TX DQ/DQS : PASS
3707 12:43:45.195623 RX DATLAT : PASS
3708 12:43:45.198887 RX DQ/DQS(Engine): PASS
3709 12:43:45.199361 TX OE : NO K
3710 12:43:45.202120 All Pass.
3711 12:43:45.202591
3712 12:43:45.202963 CH 1, Rank 1
3713 12:43:45.205684 SW Impedance : PASS
3714 12:43:45.206203 DUTY Scan : NO K
3715 12:43:45.209134 ZQ Calibration : PASS
3716 12:43:45.212168 Jitter Meter : NO K
3717 12:43:45.212640 CBT Training : PASS
3718 12:43:45.215801 Write leveling : PASS
3719 12:43:45.218877 RX DQS gating : PASS
3720 12:43:45.219443 RX DQ/DQS(RDDQC) : PASS
3721 12:43:45.222098 TX DQ/DQS : PASS
3722 12:43:45.225751 RX DATLAT : PASS
3723 12:43:45.226342 RX DQ/DQS(Engine): PASS
3724 12:43:45.229035 TX OE : NO K
3725 12:43:45.229598 All Pass.
3726 12:43:45.230018
3727 12:43:45.232190 DramC Write-DBI off
3728 12:43:45.235304 PER_BANK_REFRESH: Hybrid Mode
3729 12:43:45.235773 TX_TRACKING: ON
3730 12:43:45.245124 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3731 12:43:45.248463 [FAST_K] Save calibration result to emmc
3732 12:43:45.251960 dramc_set_vcore_voltage set vcore to 650000
3733 12:43:45.254944 Read voltage for 600, 5
3734 12:43:45.255517 Vio18 = 0
3735 12:43:45.255956 Vcore = 650000
3736 12:43:45.258619 Vdram = 0
3737 12:43:45.259092 Vddq = 0
3738 12:43:45.259465 Vmddr = 0
3739 12:43:45.265276 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3740 12:43:45.268778 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3741 12:43:45.271637 MEM_TYPE=3, freq_sel=19
3742 12:43:45.275332 sv_algorithm_assistance_LP4_1600
3743 12:43:45.278450 ============ PULL DRAM RESETB DOWN ============
3744 12:43:45.281805 ========== PULL DRAM RESETB DOWN end =========
3745 12:43:45.288526 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3746 12:43:45.291921 ===================================
3747 12:43:45.292394 LPDDR4 DRAM CONFIGURATION
3748 12:43:45.295239 ===================================
3749 12:43:45.298408 EX_ROW_EN[0] = 0x0
3750 12:43:45.298839 EX_ROW_EN[1] = 0x0
3751 12:43:45.301993 LP4Y_EN = 0x0
3752 12:43:45.305239 WORK_FSP = 0x0
3753 12:43:45.305711 WL = 0x2
3754 12:43:45.308773 RL = 0x2
3755 12:43:45.309245 BL = 0x2
3756 12:43:45.312012 RPST = 0x0
3757 12:43:45.312499 RD_PRE = 0x0
3758 12:43:45.315384 WR_PRE = 0x1
3759 12:43:45.315813 WR_PST = 0x0
3760 12:43:45.318099 DBI_WR = 0x0
3761 12:43:45.318527 DBI_RD = 0x0
3762 12:43:45.321459 OTF = 0x1
3763 12:43:45.325121 ===================================
3764 12:43:45.328372 ===================================
3765 12:43:45.328801 ANA top config
3766 12:43:45.331671 ===================================
3767 12:43:45.334964 DLL_ASYNC_EN = 0
3768 12:43:45.338156 ALL_SLAVE_EN = 1
3769 12:43:45.338586 NEW_RANK_MODE = 1
3770 12:43:45.341662 DLL_IDLE_MODE = 1
3771 12:43:45.345155 LP45_APHY_COMB_EN = 1
3772 12:43:45.348223 TX_ODT_DIS = 1
3773 12:43:45.351612 NEW_8X_MODE = 1
3774 12:43:45.352049 ===================================
3775 12:43:45.355068 ===================================
3776 12:43:45.358618 data_rate = 1200
3777 12:43:45.361600 CKR = 1
3778 12:43:45.364935 DQ_P2S_RATIO = 8
3779 12:43:45.368510 ===================================
3780 12:43:45.371552 CA_P2S_RATIO = 8
3781 12:43:45.375013 DQ_CA_OPEN = 0
3782 12:43:45.375097 DQ_SEMI_OPEN = 0
3783 12:43:45.378091 CA_SEMI_OPEN = 0
3784 12:43:45.381321 CA_FULL_RATE = 0
3785 12:43:45.384805 DQ_CKDIV4_EN = 1
3786 12:43:45.387961 CA_CKDIV4_EN = 1
3787 12:43:45.391222 CA_PREDIV_EN = 0
3788 12:43:45.391311 PH8_DLY = 0
3789 12:43:45.394579 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3790 12:43:45.397851 DQ_AAMCK_DIV = 4
3791 12:43:45.401383 CA_AAMCK_DIV = 4
3792 12:43:45.404719 CA_ADMCK_DIV = 4
3793 12:43:45.408129 DQ_TRACK_CA_EN = 0
3794 12:43:45.408218 CA_PICK = 600
3795 12:43:45.411564 CA_MCKIO = 600
3796 12:43:45.414793 MCKIO_SEMI = 0
3797 12:43:45.418230 PLL_FREQ = 2288
3798 12:43:45.421155 DQ_UI_PI_RATIO = 32
3799 12:43:45.424697 CA_UI_PI_RATIO = 0
3800 12:43:45.427707 ===================================
3801 12:43:45.431281 ===================================
3802 12:43:45.434566 memory_type:LPDDR4
3803 12:43:45.434721 GP_NUM : 10
3804 12:43:45.437917 SRAM_EN : 1
3805 12:43:45.438089 MD32_EN : 0
3806 12:43:45.441345 ===================================
3807 12:43:45.444582 [ANA_INIT] >>>>>>>>>>>>>>
3808 12:43:45.448118 <<<<<< [CONFIGURE PHASE]: ANA_TX
3809 12:43:45.451185 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3810 12:43:45.454814 ===================================
3811 12:43:45.457839 data_rate = 1200,PCW = 0X5800
3812 12:43:45.461493 ===================================
3813 12:43:45.464585 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3814 12:43:45.468072 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3815 12:43:45.474408 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3816 12:43:45.481391 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3817 12:43:45.484610 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3818 12:43:45.487928 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3819 12:43:45.488403 [ANA_INIT] flow start
3820 12:43:45.490995 [ANA_INIT] PLL >>>>>>>>
3821 12:43:45.494519 [ANA_INIT] PLL <<<<<<<<
3822 12:43:45.494947 [ANA_INIT] MIDPI >>>>>>>>
3823 12:43:45.497791 [ANA_INIT] MIDPI <<<<<<<<
3824 12:43:45.500993 [ANA_INIT] DLL >>>>>>>>
3825 12:43:45.501423 [ANA_INIT] flow end
3826 12:43:45.507884 ============ LP4 DIFF to SE enter ============
3827 12:43:45.511195 ============ LP4 DIFF to SE exit ============
3828 12:43:45.511630 [ANA_INIT] <<<<<<<<<<<<<
3829 12:43:45.514513 [Flow] Enable top DCM control >>>>>
3830 12:43:45.517892 [Flow] Enable top DCM control <<<<<
3831 12:43:45.520795 Enable DLL master slave shuffle
3832 12:43:45.527735 ==============================================================
3833 12:43:45.530747 Gating Mode config
3834 12:43:45.534113 ==============================================================
3835 12:43:45.537348 Config description:
3836 12:43:45.547415 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3837 12:43:45.554166 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3838 12:43:45.557568 SELPH_MODE 0: By rank 1: By Phase
3839 12:43:45.563979 ==============================================================
3840 12:43:45.567425 GAT_TRACK_EN = 1
3841 12:43:45.570625 RX_GATING_MODE = 2
3842 12:43:45.574182 RX_GATING_TRACK_MODE = 2
3843 12:43:45.574734 SELPH_MODE = 1
3844 12:43:45.577431 PICG_EARLY_EN = 1
3845 12:43:45.580471 VALID_LAT_VALUE = 1
3846 12:43:45.587055 ==============================================================
3847 12:43:45.590512 Enter into Gating configuration >>>>
3848 12:43:45.593978 Exit from Gating configuration <<<<
3849 12:43:45.597068 Enter into DVFS_PRE_config >>>>>
3850 12:43:45.607121 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3851 12:43:45.610504 Exit from DVFS_PRE_config <<<<<
3852 12:43:45.613825 Enter into PICG configuration >>>>
3853 12:43:45.617210 Exit from PICG configuration <<<<
3854 12:43:45.620336 [RX_INPUT] configuration >>>>>
3855 12:43:45.623512 [RX_INPUT] configuration <<<<<
3856 12:43:45.627009 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3857 12:43:45.633600 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3858 12:43:45.640358 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3859 12:43:45.647304 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3860 12:43:45.653758 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3861 12:43:45.657006 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3862 12:43:45.660342 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3863 12:43:45.667421 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3864 12:43:45.670561 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3865 12:43:45.673803 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3866 12:43:45.677126 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3867 12:43:45.683624 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3868 12:43:45.687247 ===================================
3869 12:43:45.690389 LPDDR4 DRAM CONFIGURATION
3870 12:43:45.693818 ===================================
3871 12:43:45.694321 EX_ROW_EN[0] = 0x0
3872 12:43:45.696969 EX_ROW_EN[1] = 0x0
3873 12:43:45.697442 LP4Y_EN = 0x0
3874 12:43:45.700220 WORK_FSP = 0x0
3875 12:43:45.700697 WL = 0x2
3876 12:43:45.703423 RL = 0x2
3877 12:43:45.703894 BL = 0x2
3878 12:43:45.707320 RPST = 0x0
3879 12:43:45.707792 RD_PRE = 0x0
3880 12:43:45.710219 WR_PRE = 0x1
3881 12:43:45.710682 WR_PST = 0x0
3882 12:43:45.713510 DBI_WR = 0x0
3883 12:43:45.714010 DBI_RD = 0x0
3884 12:43:45.716927 OTF = 0x1
3885 12:43:45.720401 ===================================
3886 12:43:45.723848 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3887 12:43:45.726896 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3888 12:43:45.733507 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3889 12:43:45.737089 ===================================
3890 12:43:45.737583 LPDDR4 DRAM CONFIGURATION
3891 12:43:45.740254 ===================================
3892 12:43:45.743492 EX_ROW_EN[0] = 0x10
3893 12:43:45.746690 EX_ROW_EN[1] = 0x0
3894 12:43:45.747161 LP4Y_EN = 0x0
3895 12:43:45.750088 WORK_FSP = 0x0
3896 12:43:45.750567 WL = 0x2
3897 12:43:45.753504 RL = 0x2
3898 12:43:45.754002 BL = 0x2
3899 12:43:45.756756 RPST = 0x0
3900 12:43:45.757219 RD_PRE = 0x0
3901 12:43:45.760304 WR_PRE = 0x1
3902 12:43:45.760868 WR_PST = 0x0
3903 12:43:45.763386 DBI_WR = 0x0
3904 12:43:45.763991 DBI_RD = 0x0
3905 12:43:45.766525 OTF = 0x1
3906 12:43:45.770266 ===================================
3907 12:43:45.776642 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3908 12:43:45.779712 nWR fixed to 30
3909 12:43:45.783098 [ModeRegInit_LP4] CH0 RK0
3910 12:43:45.783566 [ModeRegInit_LP4] CH0 RK1
3911 12:43:45.786599 [ModeRegInit_LP4] CH1 RK0
3912 12:43:45.790017 [ModeRegInit_LP4] CH1 RK1
3913 12:43:45.790585 match AC timing 17
3914 12:43:45.796375 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3915 12:43:45.799724 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3916 12:43:45.803156 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3917 12:43:45.809605 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3918 12:43:45.813156 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3919 12:43:45.813623 ==
3920 12:43:45.816682 Dram Type= 6, Freq= 0, CH_0, rank 0
3921 12:43:45.820149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3922 12:43:45.820622 ==
3923 12:43:45.826452 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3924 12:43:45.833183 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3925 12:43:45.836499 [CA 0] Center 36 (6~67) winsize 62
3926 12:43:45.839647 [CA 1] Center 36 (6~67) winsize 62
3927 12:43:45.843140 [CA 2] Center 34 (4~65) winsize 62
3928 12:43:45.846560 [CA 3] Center 34 (4~65) winsize 62
3929 12:43:45.849780 [CA 4] Center 34 (3~65) winsize 63
3930 12:43:45.852713 [CA 5] Center 33 (2~64) winsize 63
3931 12:43:45.853180
3932 12:43:45.856111 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3933 12:43:45.856579
3934 12:43:45.859428 [CATrainingPosCal] consider 1 rank data
3935 12:43:45.862714 u2DelayCellTimex100 = 270/100 ps
3936 12:43:45.866609 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3937 12:43:45.869697 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3938 12:43:45.873126 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3939 12:43:45.876409 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3940 12:43:45.879801 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3941 12:43:45.882824 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3942 12:43:45.883294
3943 12:43:45.889693 CA PerBit enable=1, Macro0, CA PI delay=33
3944 12:43:45.890373
3945 12:43:45.890767 [CBTSetCACLKResult] CA Dly = 33
3946 12:43:45.892849 CS Dly: 4 (0~35)
3947 12:43:45.893316 ==
3948 12:43:45.896366 Dram Type= 6, Freq= 0, CH_0, rank 1
3949 12:43:45.899688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3950 12:43:45.900301 ==
3951 12:43:45.906251 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3952 12:43:45.913023 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3953 12:43:45.916030 [CA 0] Center 36 (6~67) winsize 62
3954 12:43:45.919458 [CA 1] Center 36 (6~67) winsize 62
3955 12:43:45.922806 [CA 2] Center 34 (4~65) winsize 62
3956 12:43:45.926083 [CA 3] Center 34 (4~65) winsize 62
3957 12:43:45.929574 [CA 4] Center 34 (3~65) winsize 63
3958 12:43:45.932970 [CA 5] Center 33 (3~64) winsize 62
3959 12:43:45.933515
3960 12:43:45.936512 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3961 12:43:45.937079
3962 12:43:45.939594 [CATrainingPosCal] consider 2 rank data
3963 12:43:45.942666 u2DelayCellTimex100 = 270/100 ps
3964 12:43:45.946007 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3965 12:43:45.949596 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3966 12:43:45.952822 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3967 12:43:45.956458 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3968 12:43:45.959627 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3969 12:43:45.963010 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3970 12:43:45.963483
3971 12:43:45.969568 CA PerBit enable=1, Macro0, CA PI delay=33
3972 12:43:45.970078
3973 12:43:45.972949 [CBTSetCACLKResult] CA Dly = 33
3974 12:43:45.973419 CS Dly: 5 (0~37)
3975 12:43:45.973616
3976 12:43:45.975732 ----->DramcWriteLeveling(PI) begin...
3977 12:43:45.975816 ==
3978 12:43:45.979215 Dram Type= 6, Freq= 0, CH_0, rank 0
3979 12:43:45.982543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3980 12:43:45.982627 ==
3981 12:43:45.985717 Write leveling (Byte 0): 32 => 32
3982 12:43:45.989055 Write leveling (Byte 1): 29 => 29
3983 12:43:45.992654 DramcWriteLeveling(PI) end<-----
3984 12:43:45.992737
3985 12:43:45.992801 ==
3986 12:43:45.995519 Dram Type= 6, Freq= 0, CH_0, rank 0
3987 12:43:46.002603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3988 12:43:46.002688 ==
3989 12:43:46.002753 [Gating] SW mode calibration
3990 12:43:46.012336 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3991 12:43:46.015630 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3992 12:43:46.019050 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3993 12:43:46.025722 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3994 12:43:46.028644 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3995 12:43:46.032230 0 9 12 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (1 1)
3996 12:43:46.039108 0 9 16 | B1->B0 | 2c2c 2323 | 1 0 | (1 1) (0 0)
3997 12:43:46.042104 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 12:43:46.045493 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 12:43:46.052244 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 12:43:46.055746 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 12:43:46.058834 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 12:43:46.065440 0 10 8 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
4003 12:43:46.068848 0 10 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
4004 12:43:46.072213 0 10 16 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
4005 12:43:46.078771 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 12:43:46.082166 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 12:43:46.085768 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 12:43:46.092206 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 12:43:46.095542 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 12:43:46.099189 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 12:43:46.101923 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4012 12:43:46.108932 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4013 12:43:46.112536 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 12:43:46.115657 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 12:43:46.122070 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 12:43:46.125648 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 12:43:46.128818 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 12:43:46.135562 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 12:43:46.139076 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 12:43:46.142236 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 12:43:46.148900 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 12:43:46.151942 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 12:43:46.155365 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 12:43:46.161964 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 12:43:46.165229 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 12:43:46.169160 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 12:43:46.175682 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4028 12:43:46.178651 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4029 12:43:46.181908 Total UI for P1: 0, mck2ui 16
4030 12:43:46.185497 best dqsien dly found for B0: ( 0, 13, 12)
4031 12:43:46.188787 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 12:43:46.192124 Total UI for P1: 0, mck2ui 16
4033 12:43:46.195498 best dqsien dly found for B1: ( 0, 13, 16)
4034 12:43:46.198716 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4035 12:43:46.201869 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4036 12:43:46.201976
4037 12:43:46.208385 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4038 12:43:46.211839 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4039 12:43:46.211924 [Gating] SW calibration Done
4040 12:43:46.215353 ==
4041 12:43:46.218723 Dram Type= 6, Freq= 0, CH_0, rank 0
4042 12:43:46.221624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4043 12:43:46.221709 ==
4044 12:43:46.221776 RX Vref Scan: 0
4045 12:43:46.221837
4046 12:43:46.225038 RX Vref 0 -> 0, step: 1
4047 12:43:46.225121
4048 12:43:46.228223 RX Delay -230 -> 252, step: 16
4049 12:43:46.231701 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4050 12:43:46.234772 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4051 12:43:46.241566 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4052 12:43:46.245061 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4053 12:43:46.248329 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4054 12:43:46.251473 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4055 12:43:46.258120 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4056 12:43:46.261328 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4057 12:43:46.264787 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4058 12:43:46.268255 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4059 12:43:46.271329 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4060 12:43:46.277732 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4061 12:43:46.281426 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4062 12:43:46.284799 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4063 12:43:46.287712 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4064 12:43:46.294262 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4065 12:43:46.294346 ==
4066 12:43:46.297658 Dram Type= 6, Freq= 0, CH_0, rank 0
4067 12:43:46.301031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4068 12:43:46.301117 ==
4069 12:43:46.301183 DQS Delay:
4070 12:43:46.304171 DQS0 = 0, DQS1 = 0
4071 12:43:46.304255 DQM Delay:
4072 12:43:46.307385 DQM0 = 54, DQM1 = 40
4073 12:43:46.307469 DQ Delay:
4074 12:43:46.311078 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4075 12:43:46.314226 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4076 12:43:46.317519 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4077 12:43:46.320767 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4078 12:43:46.320851
4079 12:43:46.320916
4080 12:43:46.320977 ==
4081 12:43:46.324391 Dram Type= 6, Freq= 0, CH_0, rank 0
4082 12:43:46.327194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4083 12:43:46.330672 ==
4084 12:43:46.330781
4085 12:43:46.330876
4086 12:43:46.330956 TX Vref Scan disable
4087 12:43:46.334391 == TX Byte 0 ==
4088 12:43:46.337397 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4089 12:43:46.343787 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4090 12:43:46.343871 == TX Byte 1 ==
4091 12:43:46.347249 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4092 12:43:46.353850 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4093 12:43:46.353976 ==
4094 12:43:46.357233 Dram Type= 6, Freq= 0, CH_0, rank 0
4095 12:43:46.360805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4096 12:43:46.360889 ==
4097 12:43:46.360956
4098 12:43:46.361017
4099 12:43:46.363971 TX Vref Scan disable
4100 12:43:46.367132 == TX Byte 0 ==
4101 12:43:46.370238 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4102 12:43:46.373689 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4103 12:43:46.377386 == TX Byte 1 ==
4104 12:43:46.380582 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4105 12:43:46.383956 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4106 12:43:46.384040
4107 12:43:46.384106 [DATLAT]
4108 12:43:46.387203 Freq=600, CH0 RK0
4109 12:43:46.387286
4110 12:43:46.390479 DATLAT Default: 0x9
4111 12:43:46.390562 0, 0xFFFF, sum = 0
4112 12:43:46.393605 1, 0xFFFF, sum = 0
4113 12:43:46.393691 2, 0xFFFF, sum = 0
4114 12:43:46.396867 3, 0xFFFF, sum = 0
4115 12:43:46.396952 4, 0xFFFF, sum = 0
4116 12:43:46.400161 5, 0xFFFF, sum = 0
4117 12:43:46.400247 6, 0xFFFF, sum = 0
4118 12:43:46.403620 7, 0xFFFF, sum = 0
4119 12:43:46.403705 8, 0x0, sum = 1
4120 12:43:46.407007 9, 0x0, sum = 2
4121 12:43:46.407092 10, 0x0, sum = 3
4122 12:43:46.407159 11, 0x0, sum = 4
4123 12:43:46.410206 best_step = 9
4124 12:43:46.410290
4125 12:43:46.410355 ==
4126 12:43:46.413616 Dram Type= 6, Freq= 0, CH_0, rank 0
4127 12:43:46.417006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4128 12:43:46.417090 ==
4129 12:43:46.420251 RX Vref Scan: 1
4130 12:43:46.420334
4131 12:43:46.420400 RX Vref 0 -> 0, step: 1
4132 12:43:46.423538
4133 12:43:46.423621 RX Delay -179 -> 252, step: 8
4134 12:43:46.423687
4135 12:43:46.426915 Set Vref, RX VrefLevel [Byte0]: 61
4136 12:43:46.430306 [Byte1]: 49
4137 12:43:46.434335
4138 12:43:46.434418 Final RX Vref Byte 0 = 61 to rank0
4139 12:43:46.438096 Final RX Vref Byte 1 = 49 to rank0
4140 12:43:46.441348 Final RX Vref Byte 0 = 61 to rank1
4141 12:43:46.444847 Final RX Vref Byte 1 = 49 to rank1==
4142 12:43:46.447622 Dram Type= 6, Freq= 0, CH_0, rank 0
4143 12:43:46.454615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4144 12:43:46.454700 ==
4145 12:43:46.454766 DQS Delay:
4146 12:43:46.454827 DQS0 = 0, DQS1 = 0
4147 12:43:46.458079 DQM Delay:
4148 12:43:46.458163 DQM0 = 48, DQM1 = 37
4149 12:43:46.461265 DQ Delay:
4150 12:43:46.464605 DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =44
4151 12:43:46.467587 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4152 12:43:46.467672 DQ8 =32, DQ9 =24, DQ10 =36, DQ11 =32
4153 12:43:46.474364 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4154 12:43:46.474448
4155 12:43:46.474514
4156 12:43:46.481331 [DQSOSCAuto] RK0, (LSB)MR18= 0x5e58, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4157 12:43:46.484706 CH0 RK0: MR19=808, MR18=5E58
4158 12:43:46.490939 CH0_RK0: MR19=0x808, MR18=0x5E58, DQSOSC=392, MR23=63, INC=170, DEC=113
4159 12:43:46.491023
4160 12:43:46.494110 ----->DramcWriteLeveling(PI) begin...
4161 12:43:46.494195 ==
4162 12:43:46.497596 Dram Type= 6, Freq= 0, CH_0, rank 1
4163 12:43:46.500787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4164 12:43:46.500872 ==
4165 12:43:46.504312 Write leveling (Byte 0): 32 => 32
4166 12:43:46.507593 Write leveling (Byte 1): 31 => 31
4167 12:43:46.510904 DramcWriteLeveling(PI) end<-----
4168 12:43:46.510988
4169 12:43:46.511053 ==
4170 12:43:46.514261 Dram Type= 6, Freq= 0, CH_0, rank 1
4171 12:43:46.517465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4172 12:43:46.517549 ==
4173 12:43:46.520813 [Gating] SW mode calibration
4174 12:43:46.527736 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4175 12:43:46.534275 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4176 12:43:46.537746 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4177 12:43:46.540856 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4178 12:43:46.547519 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4179 12:43:46.550858 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
4180 12:43:46.554386 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
4181 12:43:46.561021 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 12:43:46.564392 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 12:43:46.567959 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 12:43:46.573860 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 12:43:46.577571 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 12:43:46.580831 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 12:43:46.587424 0 10 12 | B1->B0 | 2d2d 2f2f | 0 1 | (0 0) (0 0)
4188 12:43:46.590756 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4189 12:43:46.594206 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 12:43:46.600752 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 12:43:46.604106 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 12:43:46.607443 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 12:43:46.614310 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 12:43:46.617591 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4195 12:43:46.620940 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4196 12:43:46.627858 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 12:43:46.631023 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 12:43:46.634116 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 12:43:46.641011 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 12:43:46.643943 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 12:43:46.647347 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 12:43:46.654223 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 12:43:46.657291 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 12:43:46.660714 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 12:43:46.664063 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 12:43:46.670883 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 12:43:46.674136 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 12:43:46.677559 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 12:43:46.684046 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 12:43:46.687391 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 12:43:46.690470 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 12:43:46.697403 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4213 12:43:46.700684 Total UI for P1: 0, mck2ui 16
4214 12:43:46.704153 best dqsien dly found for B0: ( 0, 13, 14)
4215 12:43:46.707439 Total UI for P1: 0, mck2ui 16
4216 12:43:46.710852 best dqsien dly found for B1: ( 0, 13, 14)
4217 12:43:46.713848 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4218 12:43:46.717184 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4219 12:43:46.717608
4220 12:43:46.720487 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4221 12:43:46.723786 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4222 12:43:46.727190 [Gating] SW calibration Done
4223 12:43:46.727614 ==
4224 12:43:46.730431 Dram Type= 6, Freq= 0, CH_0, rank 1
4225 12:43:46.733593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4226 12:43:46.734050 ==
4227 12:43:46.737220 RX Vref Scan: 0
4228 12:43:46.737642
4229 12:43:46.740147 RX Vref 0 -> 0, step: 1
4230 12:43:46.740570
4231 12:43:46.740907 RX Delay -230 -> 252, step: 16
4232 12:43:46.746828 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4233 12:43:46.750072 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4234 12:43:46.753422 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4235 12:43:46.756763 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4236 12:43:46.763496 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4237 12:43:46.766482 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4238 12:43:46.769836 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4239 12:43:46.773353 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4240 12:43:46.780098 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4241 12:43:46.783286 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4242 12:43:46.786382 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4243 12:43:46.789695 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4244 12:43:46.796465 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4245 12:43:46.799876 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4246 12:43:46.803137 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4247 12:43:46.806559 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4248 12:43:46.807008 ==
4249 12:43:46.810049 Dram Type= 6, Freq= 0, CH_0, rank 1
4250 12:43:46.816691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4251 12:43:46.817196 ==
4252 12:43:46.817532 DQS Delay:
4253 12:43:46.817842 DQS0 = 0, DQS1 = 0
4254 12:43:46.820073 DQM Delay:
4255 12:43:46.820624 DQM0 = 49, DQM1 = 42
4256 12:43:46.823396 DQ Delay:
4257 12:43:46.826824 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4258 12:43:46.827265 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4259 12:43:46.830043 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4260 12:43:46.836570 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4261 12:43:46.836989
4262 12:43:46.837338
4263 12:43:46.837652 ==
4264 12:43:46.839592 Dram Type= 6, Freq= 0, CH_0, rank 1
4265 12:43:46.843013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4266 12:43:46.843438 ==
4267 12:43:46.843770
4268 12:43:46.844079
4269 12:43:46.846410 TX Vref Scan disable
4270 12:43:46.846847 == TX Byte 0 ==
4271 12:43:46.852853 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4272 12:43:46.856232 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4273 12:43:46.856851 == TX Byte 1 ==
4274 12:43:46.862905 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4275 12:43:46.866185 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4276 12:43:46.866661 ==
4277 12:43:46.869449 Dram Type= 6, Freq= 0, CH_0, rank 1
4278 12:43:46.873148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4279 12:43:46.873739 ==
4280 12:43:46.874323
4281 12:43:46.874730
4282 12:43:46.876065 TX Vref Scan disable
4283 12:43:46.879378 == TX Byte 0 ==
4284 12:43:46.882483 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4285 12:43:46.889536 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4286 12:43:46.890133 == TX Byte 1 ==
4287 12:43:46.892805 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4288 12:43:46.899801 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4289 12:43:46.900358
4290 12:43:46.900702 [DATLAT]
4291 12:43:46.901012 Freq=600, CH0 RK1
4292 12:43:46.901352
4293 12:43:46.902856 DATLAT Default: 0x9
4294 12:43:46.903429 0, 0xFFFF, sum = 0
4295 12:43:46.906138 1, 0xFFFF, sum = 0
4296 12:43:46.909539 2, 0xFFFF, sum = 0
4297 12:43:46.910041 3, 0xFFFF, sum = 0
4298 12:43:46.912836 4, 0xFFFF, sum = 0
4299 12:43:46.913389 5, 0xFFFF, sum = 0
4300 12:43:46.915638 6, 0xFFFF, sum = 0
4301 12:43:46.916082 7, 0xFFFF, sum = 0
4302 12:43:46.919013 8, 0x0, sum = 1
4303 12:43:46.919442 9, 0x0, sum = 2
4304 12:43:46.919788 10, 0x0, sum = 3
4305 12:43:46.922296 11, 0x0, sum = 4
4306 12:43:46.922728 best_step = 9
4307 12:43:46.923063
4308 12:43:46.923392 ==
4309 12:43:46.925756 Dram Type= 6, Freq= 0, CH_0, rank 1
4310 12:43:46.932543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4311 12:43:46.933048 ==
4312 12:43:46.933551 RX Vref Scan: 0
4313 12:43:46.933892
4314 12:43:46.935690 RX Vref 0 -> 0, step: 1
4315 12:43:46.936051
4316 12:43:46.939037 RX Delay -179 -> 252, step: 8
4317 12:43:46.942599 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4318 12:43:46.948872 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4319 12:43:46.952504 iDelay=205, Bit 2, Center 48 (-99 ~ 196) 296
4320 12:43:46.955417 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4321 12:43:46.958940 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4322 12:43:46.962139 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4323 12:43:46.969146 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4324 12:43:46.971958 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4325 12:43:46.975441 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4326 12:43:46.978899 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4327 12:43:46.982217 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4328 12:43:46.989075 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4329 12:43:46.992253 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4330 12:43:46.995760 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4331 12:43:46.998981 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4332 12:43:47.005647 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4333 12:43:47.006431 ==
4334 12:43:47.009482 Dram Type= 6, Freq= 0, CH_0, rank 1
4335 12:43:47.012523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4336 12:43:47.013084 ==
4337 12:43:47.013442 DQS Delay:
4338 12:43:47.015902 DQS0 = 0, DQS1 = 0
4339 12:43:47.016357 DQM Delay:
4340 12:43:47.019501 DQM0 = 49, DQM1 = 42
4341 12:43:47.020057 DQ Delay:
4342 12:43:47.022630 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =44
4343 12:43:47.025735 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =56
4344 12:43:47.029303 DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =36
4345 12:43:47.032526 DQ12 =48, DQ13 =48, DQ14 =52, DQ15 =52
4346 12:43:47.033088
4347 12:43:47.033447
4348 12:43:47.039150 [DQSOSCAuto] RK1, (LSB)MR18= 0x6330, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4349 12:43:47.042422 CH0 RK1: MR19=808, MR18=6330
4350 12:43:47.048896 CH0_RK1: MR19=0x808, MR18=0x6330, DQSOSC=391, MR23=63, INC=171, DEC=114
4351 12:43:47.052350 [RxdqsGatingPostProcess] freq 600
4352 12:43:47.059162 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4353 12:43:47.062767 Pre-setting of DQS Precalculation
4354 12:43:47.065733 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4355 12:43:47.066225 ==
4356 12:43:47.069146 Dram Type= 6, Freq= 0, CH_1, rank 0
4357 12:43:47.072181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4358 12:43:47.072663 ==
4359 12:43:47.078905 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4360 12:43:47.085747 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4361 12:43:47.088812 [CA 0] Center 35 (5~66) winsize 62
4362 12:43:47.092405 [CA 1] Center 35 (5~66) winsize 62
4363 12:43:47.095632 [CA 2] Center 34 (4~65) winsize 62
4364 12:43:47.098713 [CA 3] Center 33 (3~64) winsize 62
4365 12:43:47.102082 [CA 4] Center 34 (3~65) winsize 63
4366 12:43:47.105360 [CA 5] Center 33 (3~64) winsize 62
4367 12:43:47.105844
4368 12:43:47.108804 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4369 12:43:47.109377
4370 12:43:47.112241 [CATrainingPosCal] consider 1 rank data
4371 12:43:47.115332 u2DelayCellTimex100 = 270/100 ps
4372 12:43:47.118815 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4373 12:43:47.122231 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4374 12:43:47.125460 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4375 12:43:47.129057 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4376 12:43:47.132310 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4377 12:43:47.135569 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4378 12:43:47.136146
4379 12:43:47.142346 CA PerBit enable=1, Macro0, CA PI delay=33
4380 12:43:47.142922
4381 12:43:47.145632 [CBTSetCACLKResult] CA Dly = 33
4382 12:43:47.146270 CS Dly: 5 (0~36)
4383 12:43:47.146651 ==
4384 12:43:47.149082 Dram Type= 6, Freq= 0, CH_1, rank 1
4385 12:43:47.152072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4386 12:43:47.152547 ==
4387 12:43:47.158575 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4388 12:43:47.165503 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4389 12:43:47.168913 [CA 0] Center 35 (5~66) winsize 62
4390 12:43:47.172155 [CA 1] Center 35 (5~66) winsize 62
4391 12:43:47.175295 [CA 2] Center 34 (4~65) winsize 62
4392 12:43:47.178358 [CA 3] Center 34 (4~64) winsize 61
4393 12:43:47.182108 [CA 4] Center 34 (4~65) winsize 62
4394 12:43:47.185264 [CA 5] Center 33 (3~64) winsize 62
4395 12:43:47.185735
4396 12:43:47.188790 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4397 12:43:47.189260
4398 12:43:47.191746 [CATrainingPosCal] consider 2 rank data
4399 12:43:47.195147 u2DelayCellTimex100 = 270/100 ps
4400 12:43:47.198633 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4401 12:43:47.202051 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4402 12:43:47.205060 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4403 12:43:47.208555 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4404 12:43:47.212209 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4405 12:43:47.218396 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4406 12:43:47.218874
4407 12:43:47.221975 CA PerBit enable=1, Macro0, CA PI delay=33
4408 12:43:47.222453
4409 12:43:47.225293 [CBTSetCACLKResult] CA Dly = 33
4410 12:43:47.225766 CS Dly: 5 (0~36)
4411 12:43:47.226187
4412 12:43:47.228598 ----->DramcWriteLeveling(PI) begin...
4413 12:43:47.229077 ==
4414 12:43:47.231697 Dram Type= 6, Freq= 0, CH_1, rank 0
4415 12:43:47.238875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4416 12:43:47.239456 ==
4417 12:43:47.242407 Write leveling (Byte 0): 31 => 31
4418 12:43:47.242983 Write leveling (Byte 1): 31 => 31
4419 12:43:47.245750 DramcWriteLeveling(PI) end<-----
4420 12:43:47.246376
4421 12:43:47.246761 ==
4422 12:43:47.248821 Dram Type= 6, Freq= 0, CH_1, rank 0
4423 12:43:47.255442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4424 12:43:47.256033 ==
4425 12:43:47.256411 [Gating] SW mode calibration
4426 12:43:47.265380 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4427 12:43:47.268597 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4428 12:43:47.271997 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4429 12:43:47.278688 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4430 12:43:47.281765 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
4431 12:43:47.288136 0 9 12 | B1->B0 | 2c2c 2b2b | 1 0 | (1 0) (0 0)
4432 12:43:47.291908 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 12:43:47.294581 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 12:43:47.301266 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 12:43:47.304717 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 12:43:47.308401 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4437 12:43:47.311590 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4438 12:43:47.318481 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
4439 12:43:47.321243 0 10 12 | B1->B0 | 3d3d 3a3a | 0 0 | (0 0) (0 0)
4440 12:43:47.324822 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 12:43:47.331683 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 12:43:47.334919 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 12:43:47.338449 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 12:43:47.344890 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 12:43:47.348628 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 12:43:47.351826 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4447 12:43:47.358120 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 12:43:47.361739 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 12:43:47.364566 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 12:43:47.371406 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 12:43:47.374910 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 12:43:47.378261 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 12:43:47.384817 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 12:43:47.387815 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 12:43:47.391460 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 12:43:47.397809 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 12:43:47.401285 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 12:43:47.404453 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 12:43:47.410656 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 12:43:47.414127 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 12:43:47.417528 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 12:43:47.424265 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4463 12:43:47.427514 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4464 12:43:47.430621 Total UI for P1: 0, mck2ui 16
4465 12:43:47.434388 best dqsien dly found for B0: ( 0, 13, 8)
4466 12:43:47.437739 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 12:43:47.440839 Total UI for P1: 0, mck2ui 16
4468 12:43:47.444204 best dqsien dly found for B1: ( 0, 13, 12)
4469 12:43:47.447494 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4470 12:43:47.450761 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4471 12:43:47.451325
4472 12:43:47.457477 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4473 12:43:47.460861 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4474 12:43:47.461433 [Gating] SW calibration Done
4475 12:43:47.463630 ==
4476 12:43:47.467170 Dram Type= 6, Freq= 0, CH_1, rank 0
4477 12:43:47.470145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4478 12:43:47.470657 ==
4479 12:43:47.471029 RX Vref Scan: 0
4480 12:43:47.471377
4481 12:43:47.473742 RX Vref 0 -> 0, step: 1
4482 12:43:47.474359
4483 12:43:47.477385 RX Delay -230 -> 252, step: 16
4484 12:43:47.480471 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4485 12:43:47.483806 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4486 12:43:47.490631 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4487 12:43:47.493880 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4488 12:43:47.497368 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4489 12:43:47.500755 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4490 12:43:47.503727 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4491 12:43:47.510555 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4492 12:43:47.513974 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4493 12:43:47.517019 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4494 12:43:47.520132 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4495 12:43:47.527340 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4496 12:43:47.530374 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4497 12:43:47.533580 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4498 12:43:47.536986 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4499 12:43:47.543587 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4500 12:43:47.544158 ==
4501 12:43:47.546937 Dram Type= 6, Freq= 0, CH_1, rank 0
4502 12:43:47.550394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4503 12:43:47.550962 ==
4504 12:43:47.551335 DQS Delay:
4505 12:43:47.553645 DQS0 = 0, DQS1 = 0
4506 12:43:47.554235 DQM Delay:
4507 12:43:47.557261 DQM0 = 53, DQM1 = 42
4508 12:43:47.557864 DQ Delay:
4509 12:43:47.559908 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4510 12:43:47.563790 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4511 12:43:47.566861 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4512 12:43:47.570063 DQ12 =57, DQ13 =57, DQ14 =41, DQ15 =41
4513 12:43:47.570624
4514 12:43:47.570992
4515 12:43:47.571335 ==
4516 12:43:47.573441 Dram Type= 6, Freq= 0, CH_1, rank 0
4517 12:43:47.576666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4518 12:43:47.577224 ==
4519 12:43:47.577597
4520 12:43:47.577979
4521 12:43:47.580257 TX Vref Scan disable
4522 12:43:47.583357 == TX Byte 0 ==
4523 12:43:47.586935 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4524 12:43:47.590436 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4525 12:43:47.593224 == TX Byte 1 ==
4526 12:43:47.597125 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4527 12:43:47.599653 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4528 12:43:47.600126 ==
4529 12:43:47.603773 Dram Type= 6, Freq= 0, CH_1, rank 0
4530 12:43:47.610367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4531 12:43:47.610935 ==
4532 12:43:47.611301
4533 12:43:47.611638
4534 12:43:47.611962 TX Vref Scan disable
4535 12:43:47.614221 == TX Byte 0 ==
4536 12:43:47.617388 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4537 12:43:47.624189 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4538 12:43:47.624803 == TX Byte 1 ==
4539 12:43:47.627678 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4540 12:43:47.634152 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4541 12:43:47.634617
4542 12:43:47.634980 [DATLAT]
4543 12:43:47.635319 Freq=600, CH1 RK0
4544 12:43:47.635736
4545 12:43:47.637035 DATLAT Default: 0x9
4546 12:43:47.637498 0, 0xFFFF, sum = 0
4547 12:43:47.640416 1, 0xFFFF, sum = 0
4548 12:43:47.640887 2, 0xFFFF, sum = 0
4549 12:43:47.644035 3, 0xFFFF, sum = 0
4550 12:43:47.647201 4, 0xFFFF, sum = 0
4551 12:43:47.647675 5, 0xFFFF, sum = 0
4552 12:43:47.650593 6, 0xFFFF, sum = 0
4553 12:43:47.651064 7, 0xFFFF, sum = 0
4554 12:43:47.654101 8, 0x0, sum = 1
4555 12:43:47.654575 9, 0x0, sum = 2
4556 12:43:47.654951 10, 0x0, sum = 3
4557 12:43:47.657248 11, 0x0, sum = 4
4558 12:43:47.657823 best_step = 9
4559 12:43:47.658333
4560 12:43:47.658684 ==
4561 12:43:47.660434 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 12:43:47.667395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 12:43:47.667965 ==
4564 12:43:47.668338 RX Vref Scan: 1
4565 12:43:47.668679
4566 12:43:47.670487 RX Vref 0 -> 0, step: 1
4567 12:43:47.670953
4568 12:43:47.674012 RX Delay -179 -> 252, step: 8
4569 12:43:47.674578
4570 12:43:47.677244 Set Vref, RX VrefLevel [Byte0]: 53
4571 12:43:47.680630 [Byte1]: 56
4572 12:43:47.681197
4573 12:43:47.684289 Final RX Vref Byte 0 = 53 to rank0
4574 12:43:47.687127 Final RX Vref Byte 1 = 56 to rank0
4575 12:43:47.690841 Final RX Vref Byte 0 = 53 to rank1
4576 12:43:47.694188 Final RX Vref Byte 1 = 56 to rank1==
4577 12:43:47.697491 Dram Type= 6, Freq= 0, CH_1, rank 0
4578 12:43:47.700785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 12:43:47.701354 ==
4580 12:43:47.704099 DQS Delay:
4581 12:43:47.704663 DQS0 = 0, DQS1 = 0
4582 12:43:47.705032 DQM Delay:
4583 12:43:47.707599 DQM0 = 49, DQM1 = 41
4584 12:43:47.708174 DQ Delay:
4585 12:43:47.710381 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4586 12:43:47.713887 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4587 12:43:47.717026 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4588 12:43:47.720658 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4589 12:43:47.721244
4590 12:43:47.721727
4591 12:43:47.730774 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a71, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4592 12:43:47.733931 CH1 RK0: MR19=808, MR18=4A71
4593 12:43:47.737256 CH1_RK0: MR19=0x808, MR18=0x4A71, DQSOSC=388, MR23=63, INC=174, DEC=116
4594 12:43:47.737723
4595 12:43:47.740330 ----->DramcWriteLeveling(PI) begin...
4596 12:43:47.743949 ==
4597 12:43:47.747007 Dram Type= 6, Freq= 0, CH_1, rank 1
4598 12:43:47.750327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4599 12:43:47.750894 ==
4600 12:43:47.754047 Write leveling (Byte 0): 31 => 31
4601 12:43:47.757311 Write leveling (Byte 1): 29 => 29
4602 12:43:47.760463 DramcWriteLeveling(PI) end<-----
4603 12:43:47.761077
4604 12:43:47.761606 ==
4605 12:43:47.763769 Dram Type= 6, Freq= 0, CH_1, rank 1
4606 12:43:47.766953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4607 12:43:47.767424 ==
4608 12:43:47.769852 [Gating] SW mode calibration
4609 12:43:47.776982 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4610 12:43:47.780236 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4611 12:43:47.786939 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4612 12:43:47.790261 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4613 12:43:47.793720 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4614 12:43:47.799938 0 9 12 | B1->B0 | 2a2a 2f2f | 1 1 | (1 1) (1 0)
4615 12:43:47.803256 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 12:43:47.806457 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 12:43:47.813369 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 12:43:47.816425 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 12:43:47.819911 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4620 12:43:47.826442 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4621 12:43:47.829686 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4622 12:43:47.833052 0 10 12 | B1->B0 | 4343 2e2e | 0 1 | (1 1) (0 0)
4623 12:43:47.840196 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4624 12:43:47.843183 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 12:43:47.846277 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 12:43:47.853494 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 12:43:47.856799 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4628 12:43:47.859968 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 12:43:47.866572 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 12:43:47.870152 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4631 12:43:47.873531 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 12:43:47.880307 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 12:43:47.883566 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 12:43:47.886844 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 12:43:47.889981 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 12:43:47.896901 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 12:43:47.900106 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 12:43:47.903772 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 12:43:47.910191 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 12:43:47.913435 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 12:43:47.916931 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 12:43:47.923779 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 12:43:47.926868 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 12:43:47.930405 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 12:43:47.936965 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 12:43:47.940322 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4647 12:43:47.943385 Total UI for P1: 0, mck2ui 16
4648 12:43:47.946925 best dqsien dly found for B1: ( 0, 13, 10)
4649 12:43:47.950270 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 12:43:47.953653 Total UI for P1: 0, mck2ui 16
4651 12:43:47.956694 best dqsien dly found for B0: ( 0, 13, 12)
4652 12:43:47.960209 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4653 12:43:47.963373 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4654 12:43:47.963994
4655 12:43:47.970272 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4656 12:43:47.973402 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4657 12:43:47.973989 [Gating] SW calibration Done
4658 12:43:47.976862 ==
4659 12:43:47.980402 Dram Type= 6, Freq= 0, CH_1, rank 1
4660 12:43:47.983173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4661 12:43:47.983651 ==
4662 12:43:47.984021 RX Vref Scan: 0
4663 12:43:47.984359
4664 12:43:47.986819 RX Vref 0 -> 0, step: 1
4665 12:43:47.987384
4666 12:43:47.990127 RX Delay -230 -> 252, step: 16
4667 12:43:47.993773 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4668 12:43:47.996871 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4669 12:43:48.003746 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4670 12:43:48.006721 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4671 12:43:48.009873 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4672 12:43:48.013529 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4673 12:43:48.016506 iDelay=218, Bit 6, Center 49 (-102 ~ 201) 304
4674 12:43:48.023268 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4675 12:43:48.026470 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4676 12:43:48.029860 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4677 12:43:48.033335 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4678 12:43:48.039822 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4679 12:43:48.043214 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4680 12:43:48.046610 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4681 12:43:48.049531 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4682 12:43:48.056410 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4683 12:43:48.057025 ==
4684 12:43:48.059679 Dram Type= 6, Freq= 0, CH_1, rank 1
4685 12:43:48.063078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4686 12:43:48.063552 ==
4687 12:43:48.063989 DQS Delay:
4688 12:43:48.066258 DQS0 = 0, DQS1 = 0
4689 12:43:48.066727 DQM Delay:
4690 12:43:48.069699 DQM0 = 51, DQM1 = 45
4691 12:43:48.070212 DQ Delay:
4692 12:43:48.073096 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4693 12:43:48.076441 DQ4 =49, DQ5 =65, DQ6 =49, DQ7 =49
4694 12:43:48.079645 DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =41
4695 12:43:48.082898 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4696 12:43:48.083370
4697 12:43:48.083738
4698 12:43:48.084082 ==
4699 12:43:48.086220 Dram Type= 6, Freq= 0, CH_1, rank 1
4700 12:43:48.089979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4701 12:43:48.090553 ==
4702 12:43:48.090928
4703 12:43:48.092894
4704 12:43:48.093361 TX Vref Scan disable
4705 12:43:48.096455 == TX Byte 0 ==
4706 12:43:48.099514 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4707 12:43:48.103145 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4708 12:43:48.106700 == TX Byte 1 ==
4709 12:43:48.109717 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4710 12:43:48.112564 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4711 12:43:48.113034 ==
4712 12:43:48.116424 Dram Type= 6, Freq= 0, CH_1, rank 1
4713 12:43:48.122796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4714 12:43:48.123368 ==
4715 12:43:48.123741
4716 12:43:48.124079
4717 12:43:48.124404 TX Vref Scan disable
4718 12:43:48.127099 == TX Byte 0 ==
4719 12:43:48.130670 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4720 12:43:48.137579 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4721 12:43:48.138176 == TX Byte 1 ==
4722 12:43:48.140662 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4723 12:43:48.147491 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4724 12:43:48.148061
4725 12:43:48.148432 [DATLAT]
4726 12:43:48.148779 Freq=600, CH1 RK1
4727 12:43:48.149112
4728 12:43:48.150563 DATLAT Default: 0x9
4729 12:43:48.151031 0, 0xFFFF, sum = 0
4730 12:43:48.153899 1, 0xFFFF, sum = 0
4731 12:43:48.154428 2, 0xFFFF, sum = 0
4732 12:43:48.157265 3, 0xFFFF, sum = 0
4733 12:43:48.160435 4, 0xFFFF, sum = 0
4734 12:43:48.160919 5, 0xFFFF, sum = 0
4735 12:43:48.163726 6, 0xFFFF, sum = 0
4736 12:43:48.164201 7, 0xFFFF, sum = 0
4737 12:43:48.167198 8, 0x0, sum = 1
4738 12:43:48.167773 9, 0x0, sum = 2
4739 12:43:48.168153 10, 0x0, sum = 3
4740 12:43:48.170598 11, 0x0, sum = 4
4741 12:43:48.171076 best_step = 9
4742 12:43:48.171446
4743 12:43:48.171787 ==
4744 12:43:48.174303 Dram Type= 6, Freq= 0, CH_1, rank 1
4745 12:43:48.180774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4746 12:43:48.181368 ==
4747 12:43:48.181745 RX Vref Scan: 0
4748 12:43:48.182120
4749 12:43:48.183935 RX Vref 0 -> 0, step: 1
4750 12:43:48.184408
4751 12:43:48.187197 RX Delay -179 -> 252, step: 8
4752 12:43:48.190474 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4753 12:43:48.197438 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4754 12:43:48.200494 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4755 12:43:48.203815 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4756 12:43:48.207473 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4757 12:43:48.210723 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4758 12:43:48.213957 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4759 12:43:48.220882 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4760 12:43:48.224189 iDelay=205, Bit 8, Center 28 (-115 ~ 172) 288
4761 12:43:48.227098 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4762 12:43:48.230583 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4763 12:43:48.237375 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4764 12:43:48.240431 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4765 12:43:48.243822 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4766 12:43:48.247310 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4767 12:43:48.250608 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4768 12:43:48.253552 ==
4769 12:43:48.254138 Dram Type= 6, Freq= 0, CH_1, rank 1
4770 12:43:48.260382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4771 12:43:48.260853 ==
4772 12:43:48.261418 DQS Delay:
4773 12:43:48.264069 DQS0 = 0, DQS1 = 0
4774 12:43:48.264626 DQM Delay:
4775 12:43:48.267317 DQM0 = 49, DQM1 = 43
4776 12:43:48.267783 DQ Delay:
4777 12:43:48.270568 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4778 12:43:48.273992 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4779 12:43:48.276980 DQ8 =28, DQ9 =32, DQ10 =44, DQ11 =40
4780 12:43:48.280481 DQ12 =56, DQ13 =48, DQ14 =48, DQ15 =52
4781 12:43:48.280950
4782 12:43:48.281318
4783 12:43:48.287138 [DQSOSCAuto] RK1, (LSB)MR18= 0x581f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4784 12:43:48.290630 CH1 RK1: MR19=808, MR18=581F
4785 12:43:48.297475 CH1_RK1: MR19=0x808, MR18=0x581F, DQSOSC=393, MR23=63, INC=169, DEC=113
4786 12:43:48.300365 [RxdqsGatingPostProcess] freq 600
4787 12:43:48.303922 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4788 12:43:48.307408 Pre-setting of DQS Precalculation
4789 12:43:48.313534 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4790 12:43:48.320736 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4791 12:43:48.326947 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4792 12:43:48.327462
4793 12:43:48.327998
4794 12:43:48.330328 [Calibration Summary] 1200 Mbps
4795 12:43:48.330898 CH 0, Rank 0
4796 12:43:48.333590 SW Impedance : PASS
4797 12:43:48.336818 DUTY Scan : NO K
4798 12:43:48.337288 ZQ Calibration : PASS
4799 12:43:48.340345 Jitter Meter : NO K
4800 12:43:48.343575 CBT Training : PASS
4801 12:43:48.344137 Write leveling : PASS
4802 12:43:48.347348 RX DQS gating : PASS
4803 12:43:48.350461 RX DQ/DQS(RDDQC) : PASS
4804 12:43:48.351028 TX DQ/DQS : PASS
4805 12:43:48.353655 RX DATLAT : PASS
4806 12:43:48.356928 RX DQ/DQS(Engine): PASS
4807 12:43:48.357563 TX OE : NO K
4808 12:43:48.360135 All Pass.
4809 12:43:48.360599
4810 12:43:48.360971 CH 0, Rank 1
4811 12:43:48.363407 SW Impedance : PASS
4812 12:43:48.363878 DUTY Scan : NO K
4813 12:43:48.367157 ZQ Calibration : PASS
4814 12:43:48.370317 Jitter Meter : NO K
4815 12:43:48.370913 CBT Training : PASS
4816 12:43:48.373270 Write leveling : PASS
4817 12:43:48.376882 RX DQS gating : PASS
4818 12:43:48.377449 RX DQ/DQS(RDDQC) : PASS
4819 12:43:48.380529 TX DQ/DQS : PASS
4820 12:43:48.381104 RX DATLAT : PASS
4821 12:43:48.383879 RX DQ/DQS(Engine): PASS
4822 12:43:48.386693 TX OE : NO K
4823 12:43:48.387167 All Pass.
4824 12:43:48.387538
4825 12:43:48.387885 CH 1, Rank 0
4826 12:43:48.390340 SW Impedance : PASS
4827 12:43:48.393542 DUTY Scan : NO K
4828 12:43:48.394175 ZQ Calibration : PASS
4829 12:43:48.397153 Jitter Meter : NO K
4830 12:43:48.399852 CBT Training : PASS
4831 12:43:48.400324 Write leveling : PASS
4832 12:43:48.403863 RX DQS gating : PASS
4833 12:43:48.406972 RX DQ/DQS(RDDQC) : PASS
4834 12:43:48.407546 TX DQ/DQS : PASS
4835 12:43:48.410272 RX DATLAT : PASS
4836 12:43:48.413453 RX DQ/DQS(Engine): PASS
4837 12:43:48.414060 TX OE : NO K
4838 12:43:48.414438 All Pass.
4839 12:43:48.416896
4840 12:43:48.417458 CH 1, Rank 1
4841 12:43:48.420452 SW Impedance : PASS
4842 12:43:48.421015 DUTY Scan : NO K
4843 12:43:48.423556 ZQ Calibration : PASS
4844 12:43:48.424025 Jitter Meter : NO K
4845 12:43:48.426892 CBT Training : PASS
4846 12:43:48.430178 Write leveling : PASS
4847 12:43:48.430648 RX DQS gating : PASS
4848 12:43:48.433462 RX DQ/DQS(RDDQC) : PASS
4849 12:43:48.436961 TX DQ/DQS : PASS
4850 12:43:48.437531 RX DATLAT : PASS
4851 12:43:48.440283 RX DQ/DQS(Engine): PASS
4852 12:43:48.443264 TX OE : NO K
4853 12:43:48.443740 All Pass.
4854 12:43:48.444110
4855 12:43:48.446556 DramC Write-DBI off
4856 12:43:48.447024 PER_BANK_REFRESH: Hybrid Mode
4857 12:43:48.450280 TX_TRACKING: ON
4858 12:43:48.456721 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4859 12:43:48.463490 [FAST_K] Save calibration result to emmc
4860 12:43:48.466825 dramc_set_vcore_voltage set vcore to 662500
4861 12:43:48.467393 Read voltage for 933, 3
4862 12:43:48.470236 Vio18 = 0
4863 12:43:48.470800 Vcore = 662500
4864 12:43:48.471168 Vdram = 0
4865 12:43:48.473321 Vddq = 0
4866 12:43:48.473885 Vmddr = 0
4867 12:43:48.477007 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4868 12:43:48.482965 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4869 12:43:48.486290 MEM_TYPE=3, freq_sel=17
4870 12:43:48.490038 sv_algorithm_assistance_LP4_1600
4871 12:43:48.493467 ============ PULL DRAM RESETB DOWN ============
4872 12:43:48.496471 ========== PULL DRAM RESETB DOWN end =========
4873 12:43:48.499651 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4874 12:43:48.503594 ===================================
4875 12:43:48.506299 LPDDR4 DRAM CONFIGURATION
4876 12:43:48.510231 ===================================
4877 12:43:48.513220 EX_ROW_EN[0] = 0x0
4878 12:43:48.513752 EX_ROW_EN[1] = 0x0
4879 12:43:48.516593 LP4Y_EN = 0x0
4880 12:43:48.517057 WORK_FSP = 0x0
4881 12:43:48.520188 WL = 0x3
4882 12:43:48.520761 RL = 0x3
4883 12:43:48.523403 BL = 0x2
4884 12:43:48.523869 RPST = 0x0
4885 12:43:48.526319 RD_PRE = 0x0
4886 12:43:48.526781 WR_PRE = 0x1
4887 12:43:48.529656 WR_PST = 0x0
4888 12:43:48.533392 DBI_WR = 0x0
4889 12:43:48.533988 DBI_RD = 0x0
4890 12:43:48.536802 OTF = 0x1
4891 12:43:48.539662 ===================================
4892 12:43:48.543088 ===================================
4893 12:43:48.543557 ANA top config
4894 12:43:48.546420 ===================================
4895 12:43:48.550058 DLL_ASYNC_EN = 0
4896 12:43:48.553317 ALL_SLAVE_EN = 1
4897 12:43:48.553883 NEW_RANK_MODE = 1
4898 12:43:48.556474 DLL_IDLE_MODE = 1
4899 12:43:48.559794 LP45_APHY_COMB_EN = 1
4900 12:43:48.563163 TX_ODT_DIS = 1
4901 12:43:48.563755 NEW_8X_MODE = 1
4902 12:43:48.566629 ===================================
4903 12:43:48.570108 ===================================
4904 12:43:48.573329 data_rate = 1866
4905 12:43:48.576811 CKR = 1
4906 12:43:48.579747 DQ_P2S_RATIO = 8
4907 12:43:48.583004 ===================================
4908 12:43:48.586241 CA_P2S_RATIO = 8
4909 12:43:48.589981 DQ_CA_OPEN = 0
4910 12:43:48.590559 DQ_SEMI_OPEN = 0
4911 12:43:48.592881 CA_SEMI_OPEN = 0
4912 12:43:48.596655 CA_FULL_RATE = 0
4913 12:43:48.599793 DQ_CKDIV4_EN = 1
4914 12:43:48.602949 CA_CKDIV4_EN = 1
4915 12:43:48.606315 CA_PREDIV_EN = 0
4916 12:43:48.606934 PH8_DLY = 0
4917 12:43:48.609886 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4918 12:43:48.612692 DQ_AAMCK_DIV = 4
4919 12:43:48.616053 CA_AAMCK_DIV = 4
4920 12:43:48.619925 CA_ADMCK_DIV = 4
4921 12:43:48.622595 DQ_TRACK_CA_EN = 0
4922 12:43:48.623077 CA_PICK = 933
4923 12:43:48.626081 CA_MCKIO = 933
4924 12:43:48.629599 MCKIO_SEMI = 0
4925 12:43:48.632718 PLL_FREQ = 3732
4926 12:43:48.636513 DQ_UI_PI_RATIO = 32
4927 12:43:48.639148 CA_UI_PI_RATIO = 0
4928 12:43:48.642952 ===================================
4929 12:43:48.646037 ===================================
4930 12:43:48.646512 memory_type:LPDDR4
4931 12:43:48.649316 GP_NUM : 10
4932 12:43:48.652867 SRAM_EN : 1
4933 12:43:48.653435 MD32_EN : 0
4934 12:43:48.655810 ===================================
4935 12:43:48.659252 [ANA_INIT] >>>>>>>>>>>>>>
4936 12:43:48.662776 <<<<<< [CONFIGURE PHASE]: ANA_TX
4937 12:43:48.665812 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4938 12:43:48.669045 ===================================
4939 12:43:48.672076 data_rate = 1866,PCW = 0X8f00
4940 12:43:48.675609 ===================================
4941 12:43:48.678819 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4942 12:43:48.682513 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4943 12:43:48.688959 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4944 12:43:48.695528 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4945 12:43:48.698591 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4946 12:43:48.701740 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4947 12:43:48.702243 [ANA_INIT] flow start
4948 12:43:48.705557 [ANA_INIT] PLL >>>>>>>>
4949 12:43:48.708931 [ANA_INIT] PLL <<<<<<<<
4950 12:43:48.709506 [ANA_INIT] MIDPI >>>>>>>>
4951 12:43:48.712469 [ANA_INIT] MIDPI <<<<<<<<
4952 12:43:48.715668 [ANA_INIT] DLL >>>>>>>>
4953 12:43:48.716145 [ANA_INIT] flow end
4954 12:43:48.718614 ============ LP4 DIFF to SE enter ============
4955 12:43:48.725981 ============ LP4 DIFF to SE exit ============
4956 12:43:48.726564 [ANA_INIT] <<<<<<<<<<<<<
4957 12:43:48.728529 [Flow] Enable top DCM control >>>>>
4958 12:43:48.732408 [Flow] Enable top DCM control <<<<<
4959 12:43:48.735428 Enable DLL master slave shuffle
4960 12:43:48.742406 ==============================================================
4961 12:43:48.745314 Gating Mode config
4962 12:43:48.748935 ==============================================================
4963 12:43:48.751903 Config description:
4964 12:43:48.761802 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4965 12:43:48.768799 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4966 12:43:48.772076 SELPH_MODE 0: By rank 1: By Phase
4967 12:43:48.778576 ==============================================================
4968 12:43:48.782345 GAT_TRACK_EN = 1
4969 12:43:48.785147 RX_GATING_MODE = 2
4970 12:43:48.785623 RX_GATING_TRACK_MODE = 2
4971 12:43:48.788904 SELPH_MODE = 1
4972 12:43:48.791820 PICG_EARLY_EN = 1
4973 12:43:48.795333 VALID_LAT_VALUE = 1
4974 12:43:48.801694 ==============================================================
4975 12:43:48.804970 Enter into Gating configuration >>>>
4976 12:43:48.808391 Exit from Gating configuration <<<<
4977 12:43:48.811809 Enter into DVFS_PRE_config >>>>>
4978 12:43:48.821867 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4979 12:43:48.824639 Exit from DVFS_PRE_config <<<<<
4980 12:43:48.828088 Enter into PICG configuration >>>>
4981 12:43:48.831764 Exit from PICG configuration <<<<
4982 12:43:48.834775 [RX_INPUT] configuration >>>>>
4983 12:43:48.838036 [RX_INPUT] configuration <<<<<
4984 12:43:48.841550 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4985 12:43:48.848060 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4986 12:43:48.854553 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4987 12:43:48.861544 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4988 12:43:48.864441 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4989 12:43:48.871464 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4990 12:43:48.874836 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4991 12:43:48.881302 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4992 12:43:48.884718 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4993 12:43:48.888290 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4994 12:43:48.891320 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4995 12:43:48.898183 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4996 12:43:48.901564 ===================================
4997 12:43:48.904427 LPDDR4 DRAM CONFIGURATION
4998 12:43:48.908131 ===================================
4999 12:43:48.908701 EX_ROW_EN[0] = 0x0
5000 12:43:48.911106 EX_ROW_EN[1] = 0x0
5001 12:43:48.911568 LP4Y_EN = 0x0
5002 12:43:48.914689 WORK_FSP = 0x0
5003 12:43:48.915250 WL = 0x3
5004 12:43:48.918261 RL = 0x3
5005 12:43:48.918830 BL = 0x2
5006 12:43:48.921481 RPST = 0x0
5007 12:43:48.921981 RD_PRE = 0x0
5008 12:43:48.924915 WR_PRE = 0x1
5009 12:43:48.925484 WR_PST = 0x0
5010 12:43:48.927787 DBI_WR = 0x0
5011 12:43:48.928251 DBI_RD = 0x0
5012 12:43:48.931476 OTF = 0x1
5013 12:43:48.934525 ===================================
5014 12:43:48.937798 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5015 12:43:48.941224 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5016 12:43:48.947805 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5017 12:43:48.951070 ===================================
5018 12:43:48.951633 LPDDR4 DRAM CONFIGURATION
5019 12:43:48.954270 ===================================
5020 12:43:48.957992 EX_ROW_EN[0] = 0x10
5021 12:43:48.961172 EX_ROW_EN[1] = 0x0
5022 12:43:48.961747 LP4Y_EN = 0x0
5023 12:43:48.964266 WORK_FSP = 0x0
5024 12:43:48.964834 WL = 0x3
5025 12:43:48.967490 RL = 0x3
5026 12:43:48.967953 BL = 0x2
5027 12:43:48.970841 RPST = 0x0
5028 12:43:48.971303 RD_PRE = 0x0
5029 12:43:48.974058 WR_PRE = 0x1
5030 12:43:48.974521 WR_PST = 0x0
5031 12:43:48.977967 DBI_WR = 0x0
5032 12:43:48.978536 DBI_RD = 0x0
5033 12:43:48.981433 OTF = 0x1
5034 12:43:48.984153 ===================================
5035 12:43:48.990857 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5036 12:43:48.994506 nWR fixed to 30
5037 12:43:48.995076 [ModeRegInit_LP4] CH0 RK0
5038 12:43:48.997738 [ModeRegInit_LP4] CH0 RK1
5039 12:43:49.001100 [ModeRegInit_LP4] CH1 RK0
5040 12:43:49.004035 [ModeRegInit_LP4] CH1 RK1
5041 12:43:49.004501 match AC timing 9
5042 12:43:49.008027 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5043 12:43:49.014313 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5044 12:43:49.017723 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5045 12:43:49.024586 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5046 12:43:49.027527 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5047 12:43:49.028096 ==
5048 12:43:49.030584 Dram Type= 6, Freq= 0, CH_0, rank 0
5049 12:43:49.034096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5050 12:43:49.034684 ==
5051 12:43:49.040494 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5052 12:43:49.047568 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5053 12:43:49.050405 [CA 0] Center 38 (7~69) winsize 63
5054 12:43:49.053882 [CA 1] Center 38 (7~69) winsize 63
5055 12:43:49.057565 [CA 2] Center 35 (5~66) winsize 62
5056 12:43:49.060681 [CA 3] Center 34 (4~65) winsize 62
5057 12:43:49.063858 [CA 4] Center 34 (4~65) winsize 62
5058 12:43:49.067263 [CA 5] Center 33 (3~64) winsize 62
5059 12:43:49.067726
5060 12:43:49.070653 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5061 12:43:49.071117
5062 12:43:49.073911 [CATrainingPosCal] consider 1 rank data
5063 12:43:49.077332 u2DelayCellTimex100 = 270/100 ps
5064 12:43:49.080491 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5065 12:43:49.083885 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5066 12:43:49.087209 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5067 12:43:49.090758 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5068 12:43:49.094274 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5069 12:43:49.097655 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5070 12:43:49.098273
5071 12:43:49.104055 CA PerBit enable=1, Macro0, CA PI delay=33
5072 12:43:49.104626
5073 12:43:49.104992 [CBTSetCACLKResult] CA Dly = 33
5074 12:43:49.106835 CS Dly: 6 (0~37)
5075 12:43:49.107298 ==
5076 12:43:49.110766 Dram Type= 6, Freq= 0, CH_0, rank 1
5077 12:43:49.114376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5078 12:43:49.115004 ==
5079 12:43:49.120266 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5080 12:43:49.127085 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5081 12:43:49.130366 [CA 0] Center 38 (8~69) winsize 62
5082 12:43:49.134060 [CA 1] Center 38 (8~69) winsize 62
5083 12:43:49.137377 [CA 2] Center 36 (6~66) winsize 61
5084 12:43:49.140347 [CA 3] Center 35 (5~66) winsize 62
5085 12:43:49.143898 [CA 4] Center 34 (4~65) winsize 62
5086 12:43:49.147240 [CA 5] Center 34 (4~65) winsize 62
5087 12:43:49.147843
5088 12:43:49.150148 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5089 12:43:49.150613
5090 12:43:49.153904 [CATrainingPosCal] consider 2 rank data
5091 12:43:49.157206 u2DelayCellTimex100 = 270/100 ps
5092 12:43:49.160160 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5093 12:43:49.163508 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5094 12:43:49.166743 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5095 12:43:49.170217 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5096 12:43:49.173268 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5097 12:43:49.176849 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5098 12:43:49.177408
5099 12:43:49.183497 CA PerBit enable=1, Macro0, CA PI delay=34
5100 12:43:49.184060
5101 12:43:49.186752 [CBTSetCACLKResult] CA Dly = 34
5102 12:43:49.187215 CS Dly: 7 (0~39)
5103 12:43:49.187580
5104 12:43:49.190382 ----->DramcWriteLeveling(PI) begin...
5105 12:43:49.190945 ==
5106 12:43:49.193754 Dram Type= 6, Freq= 0, CH_0, rank 0
5107 12:43:49.197124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5108 12:43:49.197687 ==
5109 12:43:49.200393 Write leveling (Byte 0): 30 => 30
5110 12:43:49.203330 Write leveling (Byte 1): 29 => 29
5111 12:43:49.206892 DramcWriteLeveling(PI) end<-----
5112 12:43:49.207455
5113 12:43:49.207820 ==
5114 12:43:49.210037 Dram Type= 6, Freq= 0, CH_0, rank 0
5115 12:43:49.216910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5116 12:43:49.217505 ==
5117 12:43:49.217881 [Gating] SW mode calibration
5118 12:43:49.226596 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5119 12:43:49.229992 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5120 12:43:49.233420 0 14 0 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
5121 12:43:49.240231 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 12:43:49.243653 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 12:43:49.246893 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5124 12:43:49.253315 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5125 12:43:49.256965 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5126 12:43:49.259786 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
5127 12:43:49.266775 0 14 28 | B1->B0 | 3333 2424 | 0 0 | (0 1) (1 0)
5128 12:43:49.270244 0 15 0 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
5129 12:43:49.273270 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 12:43:49.279848 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 12:43:49.283214 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5132 12:43:49.286354 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5133 12:43:49.293009 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5134 12:43:49.296478 0 15 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
5135 12:43:49.300107 0 15 28 | B1->B0 | 2e2d 4646 | 1 0 | (1 1) (0 0)
5136 12:43:49.306406 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 12:43:49.309846 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 12:43:49.312839 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 12:43:49.319834 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 12:43:49.323052 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5141 12:43:49.326350 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 12:43:49.333068 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5143 12:43:49.336342 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5144 12:43:49.339672 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 12:43:49.346370 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 12:43:49.349425 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 12:43:49.352921 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 12:43:49.359388 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 12:43:49.362817 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 12:43:49.366181 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 12:43:49.372473 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 12:43:49.375725 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 12:43:49.379282 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 12:43:49.382552 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 12:43:49.389138 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 12:43:49.392760 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 12:43:49.399140 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5158 12:43:49.402456 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5159 12:43:49.405826 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5160 12:43:49.409203 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5161 12:43:49.412379 Total UI for P1: 0, mck2ui 16
5162 12:43:49.415576 best dqsien dly found for B0: ( 1, 2, 24)
5163 12:43:49.422328 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5164 12:43:49.425807 Total UI for P1: 0, mck2ui 16
5165 12:43:49.428866 best dqsien dly found for B1: ( 1, 3, 0)
5166 12:43:49.431902 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5167 12:43:49.435412 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5168 12:43:49.435977
5169 12:43:49.438857 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5170 12:43:49.442203 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5171 12:43:49.445447 [Gating] SW calibration Done
5172 12:43:49.446049 ==
5173 12:43:49.448566 Dram Type= 6, Freq= 0, CH_0, rank 0
5174 12:43:49.452249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5175 12:43:49.452820 ==
5176 12:43:49.455419 RX Vref Scan: 0
5177 12:43:49.455887
5178 12:43:49.456254 RX Vref 0 -> 0, step: 1
5179 12:43:49.458717
5180 12:43:49.459183 RX Delay -80 -> 252, step: 8
5181 12:43:49.465536 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5182 12:43:49.468343 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5183 12:43:49.472109 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5184 12:43:49.475079 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5185 12:43:49.478517 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5186 12:43:49.481811 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5187 12:43:49.488743 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5188 12:43:49.491971 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5189 12:43:49.495442 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5190 12:43:49.498813 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5191 12:43:49.502111 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5192 12:43:49.505156 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5193 12:43:49.511818 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5194 12:43:49.514989 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5195 12:43:49.518354 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5196 12:43:49.521915 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5197 12:43:49.522545 ==
5198 12:43:49.525071 Dram Type= 6, Freq= 0, CH_0, rank 0
5199 12:43:49.528690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5200 12:43:49.531786 ==
5201 12:43:49.532253 DQS Delay:
5202 12:43:49.532622 DQS0 = 0, DQS1 = 0
5203 12:43:49.535305 DQM Delay:
5204 12:43:49.535885 DQM0 = 105, DQM1 = 89
5205 12:43:49.538287 DQ Delay:
5206 12:43:49.541827 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5207 12:43:49.545229 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5208 12:43:49.548344 DQ8 =83, DQ9 =75, DQ10 =91, DQ11 =87
5209 12:43:49.551825 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5210 12:43:49.552395
5211 12:43:49.552762
5212 12:43:49.553100 ==
5213 12:43:49.555084 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 12:43:49.558168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 12:43:49.558637 ==
5216 12:43:49.559005
5217 12:43:49.559342
5218 12:43:49.561844 TX Vref Scan disable
5219 12:43:49.562438 == TX Byte 0 ==
5220 12:43:49.568020 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5221 12:43:49.571402 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5222 12:43:49.571954 == TX Byte 1 ==
5223 12:43:49.578373 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5224 12:43:49.581487 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5225 12:43:49.581989 ==
5226 12:43:49.584955 Dram Type= 6, Freq= 0, CH_0, rank 0
5227 12:43:49.588402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5228 12:43:49.588892 ==
5229 12:43:49.589280
5230 12:43:49.589621
5231 12:43:49.591519 TX Vref Scan disable
5232 12:43:49.594761 == TX Byte 0 ==
5233 12:43:49.598008 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5234 12:43:49.601918 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5235 12:43:49.605025 == TX Byte 1 ==
5236 12:43:49.608415 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5237 12:43:49.611336 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5238 12:43:49.611907
5239 12:43:49.615091 [DATLAT]
5240 12:43:49.615655 Freq=933, CH0 RK0
5241 12:43:49.616026
5242 12:43:49.617928 DATLAT Default: 0xd
5243 12:43:49.618427 0, 0xFFFF, sum = 0
5244 12:43:49.621296 1, 0xFFFF, sum = 0
5245 12:43:49.621766 2, 0xFFFF, sum = 0
5246 12:43:49.624808 3, 0xFFFF, sum = 0
5247 12:43:49.625384 4, 0xFFFF, sum = 0
5248 12:43:49.628024 5, 0xFFFF, sum = 0
5249 12:43:49.628615 6, 0xFFFF, sum = 0
5250 12:43:49.631377 7, 0xFFFF, sum = 0
5251 12:43:49.634882 8, 0xFFFF, sum = 0
5252 12:43:49.635459 9, 0xFFFF, sum = 0
5253 12:43:49.635838 10, 0x0, sum = 1
5254 12:43:49.638247 11, 0x0, sum = 2
5255 12:43:49.638856 12, 0x0, sum = 3
5256 12:43:49.641369 13, 0x0, sum = 4
5257 12:43:49.641983 best_step = 11
5258 12:43:49.642486
5259 12:43:49.642842 ==
5260 12:43:49.644428 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 12:43:49.651318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 12:43:49.651888 ==
5263 12:43:49.652278 RX Vref Scan: 1
5264 12:43:49.652646
5265 12:43:49.654493 RX Vref 0 -> 0, step: 1
5266 12:43:49.654959
5267 12:43:49.658097 RX Delay -61 -> 252, step: 4
5268 12:43:49.658668
5269 12:43:49.661572 Set Vref, RX VrefLevel [Byte0]: 61
5270 12:43:49.664883 [Byte1]: 49
5271 12:43:49.665451
5272 12:43:49.668307 Final RX Vref Byte 0 = 61 to rank0
5273 12:43:49.671667 Final RX Vref Byte 1 = 49 to rank0
5274 12:43:49.674506 Final RX Vref Byte 0 = 61 to rank1
5275 12:43:49.677818 Final RX Vref Byte 1 = 49 to rank1==
5276 12:43:49.681301 Dram Type= 6, Freq= 0, CH_0, rank 0
5277 12:43:49.684630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 12:43:49.685100 ==
5279 12:43:49.687690 DQS Delay:
5280 12:43:49.688170 DQS0 = 0, DQS1 = 0
5281 12:43:49.690808 DQM Delay:
5282 12:43:49.691272 DQM0 = 107, DQM1 = 92
5283 12:43:49.691670 DQ Delay:
5284 12:43:49.694668 DQ0 =106, DQ1 =106, DQ2 =104, DQ3 =104
5285 12:43:49.698022 DQ4 =108, DQ5 =100, DQ6 =118, DQ7 =116
5286 12:43:49.701368 DQ8 =84, DQ9 =78, DQ10 =92, DQ11 =90
5287 12:43:49.708200 DQ12 =98, DQ13 =94, DQ14 =102, DQ15 =100
5288 12:43:49.708900
5289 12:43:49.709274
5290 12:43:49.714687 [DQSOSCAuto] RK0, (LSB)MR18= 0x221e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
5291 12:43:49.718112 CH0 RK0: MR19=505, MR18=221E
5292 12:43:49.724976 CH0_RK0: MR19=0x505, MR18=0x221E, DQSOSC=411, MR23=63, INC=64, DEC=42
5293 12:43:49.725549
5294 12:43:49.728099 ----->DramcWriteLeveling(PI) begin...
5295 12:43:49.728576 ==
5296 12:43:49.731246 Dram Type= 6, Freq= 0, CH_0, rank 1
5297 12:43:49.734600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 12:43:49.735174 ==
5299 12:43:49.737669 Write leveling (Byte 0): 34 => 34
5300 12:43:49.740944 Write leveling (Byte 1): 28 => 28
5301 12:43:49.744197 DramcWriteLeveling(PI) end<-----
5302 12:43:49.744650
5303 12:43:49.745003 ==
5304 12:43:49.747911 Dram Type= 6, Freq= 0, CH_0, rank 1
5305 12:43:49.751183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5306 12:43:49.751638 ==
5307 12:43:49.754114 [Gating] SW mode calibration
5308 12:43:49.760902 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5309 12:43:49.767677 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5310 12:43:49.770877 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5311 12:43:49.774406 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 12:43:49.781217 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5313 12:43:49.784659 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 12:43:49.787911 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5315 12:43:49.794601 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5316 12:43:49.797659 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5317 12:43:49.801186 0 14 28 | B1->B0 | 3030 2727 | 0 0 | (0 1) (0 0)
5318 12:43:49.807815 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 12:43:49.811364 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 12:43:49.814297 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5321 12:43:49.821113 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 12:43:49.824630 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5323 12:43:49.827863 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5324 12:43:49.833876 0 15 24 | B1->B0 | 2525 2d2d | 0 0 | (0 0) (0 0)
5325 12:43:49.837438 0 15 28 | B1->B0 | 3c3c 4545 | 1 0 | (0 0) (0 0)
5326 12:43:49.840833 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 12:43:49.847810 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 12:43:49.850948 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 12:43:49.854359 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 12:43:49.861043 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 12:43:49.863818 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5332 12:43:49.867311 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 12:43:49.873757 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5334 12:43:49.877294 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 12:43:49.880793 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 12:43:49.887140 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 12:43:49.890300 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 12:43:49.893602 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 12:43:49.900486 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 12:43:49.903668 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 12:43:49.906790 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 12:43:49.913691 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 12:43:49.917085 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 12:43:49.920020 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 12:43:49.926768 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 12:43:49.929816 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 12:43:49.933096 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 12:43:49.940102 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5349 12:43:49.943171 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5350 12:43:49.946500 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 12:43:49.950176 Total UI for P1: 0, mck2ui 16
5352 12:43:49.953478 best dqsien dly found for B0: ( 1, 2, 26)
5353 12:43:49.956478 Total UI for P1: 0, mck2ui 16
5354 12:43:49.960004 best dqsien dly found for B1: ( 1, 2, 28)
5355 12:43:49.963391 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5356 12:43:49.966792 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5357 12:43:49.967368
5358 12:43:49.970113 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5359 12:43:49.976721 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5360 12:43:49.977301 [Gating] SW calibration Done
5361 12:43:49.977678 ==
5362 12:43:49.979736 Dram Type= 6, Freq= 0, CH_0, rank 1
5363 12:43:49.986453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5364 12:43:49.987038 ==
5365 12:43:49.987417 RX Vref Scan: 0
5366 12:43:49.987766
5367 12:43:49.990014 RX Vref 0 -> 0, step: 1
5368 12:43:49.990586
5369 12:43:49.993316 RX Delay -80 -> 252, step: 8
5370 12:43:49.997089 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5371 12:43:49.999712 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5372 12:43:50.003115 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5373 12:43:50.006243 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5374 12:43:50.012999 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5375 12:43:50.015971 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5376 12:43:50.019577 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5377 12:43:50.022575 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5378 12:43:50.025974 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5379 12:43:50.032630 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5380 12:43:50.036686 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5381 12:43:50.039868 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5382 12:43:50.042600 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5383 12:43:50.046428 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5384 12:43:50.049710 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5385 12:43:50.056452 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5386 12:43:50.057023 ==
5387 12:43:50.059588 Dram Type= 6, Freq= 0, CH_0, rank 1
5388 12:43:50.062820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5389 12:43:50.063392 ==
5390 12:43:50.063762 DQS Delay:
5391 12:43:50.066170 DQS0 = 0, DQS1 = 0
5392 12:43:50.066632 DQM Delay:
5393 12:43:50.069785 DQM0 = 105, DQM1 = 90
5394 12:43:50.070396 DQ Delay:
5395 12:43:50.072652 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5396 12:43:50.076380 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =111
5397 12:43:50.079737 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5398 12:43:50.082826 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5399 12:43:50.083389
5400 12:43:50.083757
5401 12:43:50.084097 ==
5402 12:43:50.085774 Dram Type= 6, Freq= 0, CH_0, rank 1
5403 12:43:50.089398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5404 12:43:50.092866 ==
5405 12:43:50.093432
5406 12:43:50.093800
5407 12:43:50.094225 TX Vref Scan disable
5408 12:43:50.095592 == TX Byte 0 ==
5409 12:43:50.099185 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5410 12:43:50.102394 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5411 12:43:50.105746 == TX Byte 1 ==
5412 12:43:50.109755 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5413 12:43:50.112570 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5414 12:43:50.113136 ==
5415 12:43:50.115862 Dram Type= 6, Freq= 0, CH_0, rank 1
5416 12:43:50.122462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5417 12:43:50.123016 ==
5418 12:43:50.123383
5419 12:43:50.123758
5420 12:43:50.125525 TX Vref Scan disable
5421 12:43:50.126156 == TX Byte 0 ==
5422 12:43:50.132303 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5423 12:43:50.135873 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5424 12:43:50.136437 == TX Byte 1 ==
5425 12:43:50.142264 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5426 12:43:50.145817 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5427 12:43:50.146428
5428 12:43:50.146799 [DATLAT]
5429 12:43:50.148943 Freq=933, CH0 RK1
5430 12:43:50.149409
5431 12:43:50.149770 DATLAT Default: 0xb
5432 12:43:50.152159 0, 0xFFFF, sum = 0
5433 12:43:50.152755 1, 0xFFFF, sum = 0
5434 12:43:50.155736 2, 0xFFFF, sum = 0
5435 12:43:50.156313 3, 0xFFFF, sum = 0
5436 12:43:50.158844 4, 0xFFFF, sum = 0
5437 12:43:50.159415 5, 0xFFFF, sum = 0
5438 12:43:50.162329 6, 0xFFFF, sum = 0
5439 12:43:50.162850 7, 0xFFFF, sum = 0
5440 12:43:50.165667 8, 0xFFFF, sum = 0
5441 12:43:50.166284 9, 0xFFFF, sum = 0
5442 12:43:50.168890 10, 0x0, sum = 1
5443 12:43:50.169460 11, 0x0, sum = 2
5444 12:43:50.172057 12, 0x0, sum = 3
5445 12:43:50.172528 13, 0x0, sum = 4
5446 12:43:50.175329 best_step = 11
5447 12:43:50.175792
5448 12:43:50.176155 ==
5449 12:43:50.178638 Dram Type= 6, Freq= 0, CH_0, rank 1
5450 12:43:50.182095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5451 12:43:50.182661 ==
5452 12:43:50.185914 RX Vref Scan: 0
5453 12:43:50.186530
5454 12:43:50.186903 RX Vref 0 -> 0, step: 1
5455 12:43:50.187245
5456 12:43:50.188409 RX Delay -53 -> 252, step: 4
5457 12:43:50.195796 iDelay=203, Bit 0, Center 104 (19 ~ 190) 172
5458 12:43:50.199378 iDelay=203, Bit 1, Center 106 (19 ~ 194) 176
5459 12:43:50.202760 iDelay=203, Bit 2, Center 102 (15 ~ 190) 176
5460 12:43:50.206070 iDelay=203, Bit 3, Center 98 (15 ~ 182) 168
5461 12:43:50.209244 iDelay=203, Bit 4, Center 104 (19 ~ 190) 172
5462 12:43:50.215975 iDelay=203, Bit 5, Center 96 (11 ~ 182) 172
5463 12:43:50.219331 iDelay=203, Bit 6, Center 114 (27 ~ 202) 176
5464 12:43:50.222584 iDelay=203, Bit 7, Center 112 (27 ~ 198) 172
5465 12:43:50.225575 iDelay=203, Bit 8, Center 84 (-1 ~ 170) 172
5466 12:43:50.229151 iDelay=203, Bit 9, Center 80 (-1 ~ 162) 164
5467 12:43:50.232393 iDelay=203, Bit 10, Center 94 (11 ~ 178) 168
5468 12:43:50.239583 iDelay=203, Bit 11, Center 92 (11 ~ 174) 164
5469 12:43:50.242627 iDelay=203, Bit 12, Center 96 (11 ~ 182) 172
5470 12:43:50.245847 iDelay=203, Bit 13, Center 94 (11 ~ 178) 168
5471 12:43:50.249444 iDelay=203, Bit 14, Center 100 (15 ~ 186) 172
5472 12:43:50.252580 iDelay=203, Bit 15, Center 98 (15 ~ 182) 168
5473 12:43:50.256074 ==
5474 12:43:50.259340 Dram Type= 6, Freq= 0, CH_0, rank 1
5475 12:43:50.262758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5476 12:43:50.263331 ==
5477 12:43:50.263700 DQS Delay:
5478 12:43:50.265600 DQS0 = 0, DQS1 = 0
5479 12:43:50.266092 DQM Delay:
5480 12:43:50.269251 DQM0 = 104, DQM1 = 92
5481 12:43:50.269844 DQ Delay:
5482 12:43:50.272381 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =98
5483 12:43:50.275729 DQ4 =104, DQ5 =96, DQ6 =114, DQ7 =112
5484 12:43:50.278952 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5485 12:43:50.282531 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98
5486 12:43:50.283105
5487 12:43:50.283476
5488 12:43:50.292573 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a0b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5489 12:43:50.293154 CH0 RK1: MR19=505, MR18=2A0B
5490 12:43:50.299095 CH0_RK1: MR19=0x505, MR18=0x2A0B, DQSOSC=408, MR23=63, INC=65, DEC=43
5491 12:43:50.302290 [RxdqsGatingPostProcess] freq 933
5492 12:43:50.308913 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5493 12:43:50.312002 best DQS0 dly(2T, 0.5T) = (0, 10)
5494 12:43:50.315287 best DQS1 dly(2T, 0.5T) = (0, 11)
5495 12:43:50.318610 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5496 12:43:50.322047 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5497 12:43:50.322661 best DQS0 dly(2T, 0.5T) = (0, 10)
5498 12:43:50.325307 best DQS1 dly(2T, 0.5T) = (0, 10)
5499 12:43:50.328872 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5500 12:43:50.332189 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5501 12:43:50.335575 Pre-setting of DQS Precalculation
5502 12:43:50.342350 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5503 12:43:50.342883 ==
5504 12:43:50.345562 Dram Type= 6, Freq= 0, CH_1, rank 0
5505 12:43:50.348889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5506 12:43:50.349416 ==
5507 12:43:50.355234 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5508 12:43:50.362107 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5509 12:43:50.365301 [CA 0] Center 37 (7~68) winsize 62
5510 12:43:50.368733 [CA 1] Center 37 (7~68) winsize 62
5511 12:43:50.372322 [CA 2] Center 35 (6~65) winsize 60
5512 12:43:50.375196 [CA 3] Center 35 (5~65) winsize 61
5513 12:43:50.378790 [CA 4] Center 35 (5~66) winsize 62
5514 12:43:50.379310 [CA 5] Center 34 (4~64) winsize 61
5515 12:43:50.382189
5516 12:43:50.385685 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5517 12:43:50.386299
5518 12:43:50.388438 [CATrainingPosCal] consider 1 rank data
5519 12:43:50.391760 u2DelayCellTimex100 = 270/100 ps
5520 12:43:50.395160 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5521 12:43:50.398504 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5522 12:43:50.401932 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5523 12:43:50.405179 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5524 12:43:50.408517 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5525 12:43:50.411673 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5526 12:43:50.412200
5527 12:43:50.415093 CA PerBit enable=1, Macro0, CA PI delay=34
5528 12:43:50.418380
5529 12:43:50.418900 [CBTSetCACLKResult] CA Dly = 34
5530 12:43:50.421859 CS Dly: 6 (0~37)
5531 12:43:50.422511 ==
5532 12:43:50.425001 Dram Type= 6, Freq= 0, CH_1, rank 1
5533 12:43:50.428108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5534 12:43:50.428620 ==
5535 12:43:50.434775 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5536 12:43:50.441361 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5537 12:43:50.444705 [CA 0] Center 37 (7~68) winsize 62
5538 12:43:50.448164 [CA 1] Center 37 (7~68) winsize 62
5539 12:43:50.451542 [CA 2] Center 36 (6~66) winsize 61
5540 12:43:50.454627 [CA 3] Center 35 (5~65) winsize 61
5541 12:43:50.458391 [CA 4] Center 35 (5~65) winsize 61
5542 12:43:50.461147 [CA 5] Center 34 (5~64) winsize 60
5543 12:43:50.461673
5544 12:43:50.465174 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5545 12:43:50.465707
5546 12:43:50.467954 [CATrainingPosCal] consider 2 rank data
5547 12:43:50.471133 u2DelayCellTimex100 = 270/100 ps
5548 12:43:50.474497 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5549 12:43:50.477608 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5550 12:43:50.481586 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5551 12:43:50.484971 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5552 12:43:50.488380 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5553 12:43:50.491627 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5554 12:43:50.492151
5555 12:43:50.498086 CA PerBit enable=1, Macro0, CA PI delay=34
5556 12:43:50.498619
5557 12:43:50.498956 [CBTSetCACLKResult] CA Dly = 34
5558 12:43:50.501385 CS Dly: 7 (0~39)
5559 12:43:50.501908
5560 12:43:50.504859 ----->DramcWriteLeveling(PI) begin...
5561 12:43:50.505392 ==
5562 12:43:50.508237 Dram Type= 6, Freq= 0, CH_1, rank 0
5563 12:43:50.511373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5564 12:43:50.511900 ==
5565 12:43:50.514743 Write leveling (Byte 0): 29 => 29
5566 12:43:50.517868 Write leveling (Byte 1): 30 => 30
5567 12:43:50.521302 DramcWriteLeveling(PI) end<-----
5568 12:43:50.521828
5569 12:43:50.522335 ==
5570 12:43:50.524283 Dram Type= 6, Freq= 0, CH_1, rank 0
5571 12:43:50.527749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5572 12:43:50.531183 ==
5573 12:43:50.531700 [Gating] SW mode calibration
5574 12:43:50.541340 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5575 12:43:50.544168 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5576 12:43:50.547711 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 12:43:50.554257 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 12:43:50.557769 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5579 12:43:50.560569 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5580 12:43:50.567607 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5581 12:43:50.570694 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5582 12:43:50.574050 0 14 24 | B1->B0 | 3232 3131 | 1 1 | (1 0) (1 0)
5583 12:43:50.580662 0 14 28 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
5584 12:43:50.584296 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 12:43:50.587417 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 12:43:50.593901 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 12:43:50.597380 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 12:43:50.600543 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5589 12:43:50.607249 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5590 12:43:50.610805 0 15 24 | B1->B0 | 2525 2e2e | 0 0 | (0 0) (0 0)
5591 12:43:50.614339 0 15 28 | B1->B0 | 4343 4545 | 0 0 | (1 1) (0 0)
5592 12:43:50.620721 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 12:43:50.623886 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 12:43:50.627457 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 12:43:50.633657 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5596 12:43:50.637147 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5597 12:43:50.640687 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 12:43:50.647336 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5599 12:43:50.650257 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5600 12:43:50.653679 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 12:43:50.660211 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 12:43:50.663444 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 12:43:50.666947 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 12:43:50.673503 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 12:43:50.677015 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 12:43:50.680065 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 12:43:50.687038 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 12:43:50.690085 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 12:43:50.693930 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 12:43:50.697285 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 12:43:50.703905 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 12:43:50.706859 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 12:43:50.710257 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5614 12:43:50.716774 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5615 12:43:50.720128 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5616 12:43:50.723703 Total UI for P1: 0, mck2ui 16
5617 12:43:50.727116 best dqsien dly found for B0: ( 1, 2, 22)
5618 12:43:50.730533 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5619 12:43:50.733691 Total UI for P1: 0, mck2ui 16
5620 12:43:50.737283 best dqsien dly found for B1: ( 1, 2, 26)
5621 12:43:50.740663 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5622 12:43:50.743348 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5623 12:43:50.743815
5624 12:43:50.750069 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5625 12:43:50.753295 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5626 12:43:50.756875 [Gating] SW calibration Done
5627 12:43:50.757609 ==
5628 12:43:50.760310 Dram Type= 6, Freq= 0, CH_1, rank 0
5629 12:43:50.763185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5630 12:43:50.763692 ==
5631 12:43:50.764060 RX Vref Scan: 0
5632 12:43:50.764403
5633 12:43:50.766543 RX Vref 0 -> 0, step: 1
5634 12:43:50.767004
5635 12:43:50.770027 RX Delay -80 -> 252, step: 8
5636 12:43:50.773639 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5637 12:43:50.776495 iDelay=208, Bit 1, Center 99 (16 ~ 183) 168
5638 12:43:50.779949 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5639 12:43:50.786602 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5640 12:43:50.790162 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5641 12:43:50.793648 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5642 12:43:50.797006 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5643 12:43:50.800536 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5644 12:43:50.806788 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5645 12:43:50.810312 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5646 12:43:50.813719 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5647 12:43:50.817041 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5648 12:43:50.820313 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5649 12:43:50.826300 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5650 12:43:50.829905 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5651 12:43:50.833424 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5652 12:43:50.833993 ==
5653 12:43:50.836951 Dram Type= 6, Freq= 0, CH_1, rank 0
5654 12:43:50.840291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5655 12:43:50.840824 ==
5656 12:43:50.843580 DQS Delay:
5657 12:43:50.844108 DQS0 = 0, DQS1 = 0
5658 12:43:50.844448 DQM Delay:
5659 12:43:50.846853 DQM0 = 103, DQM1 = 96
5660 12:43:50.847376 DQ Delay:
5661 12:43:50.850506 DQ0 =103, DQ1 =99, DQ2 =91, DQ3 =103
5662 12:43:50.853601 DQ4 =103, DQ5 =111, DQ6 =115, DQ7 =103
5663 12:43:50.856775 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5664 12:43:50.859970 DQ12 =107, DQ13 =107, DQ14 =99, DQ15 =99
5665 12:43:50.860447
5666 12:43:50.860779
5667 12:43:50.862909 ==
5668 12:43:50.866480 Dram Type= 6, Freq= 0, CH_1, rank 0
5669 12:43:50.870027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5670 12:43:50.870563 ==
5671 12:43:50.870900
5672 12:43:50.871209
5673 12:43:50.873248 TX Vref Scan disable
5674 12:43:50.873764 == TX Byte 0 ==
5675 12:43:50.876074 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5676 12:43:50.883160 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5677 12:43:50.883654 == TX Byte 1 ==
5678 12:43:50.889533 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5679 12:43:50.892893 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5680 12:43:50.893424 ==
5681 12:43:50.896430 Dram Type= 6, Freq= 0, CH_1, rank 0
5682 12:43:50.899780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5683 12:43:50.900307 ==
5684 12:43:50.900644
5685 12:43:50.900953
5686 12:43:50.903158 TX Vref Scan disable
5687 12:43:50.906578 == TX Byte 0 ==
5688 12:43:50.909613 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5689 12:43:50.912908 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5690 12:43:50.915883 == TX Byte 1 ==
5691 12:43:50.919609 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5692 12:43:50.923204 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5693 12:43:50.923734
5694 12:43:50.926216 [DATLAT]
5695 12:43:50.926635 Freq=933, CH1 RK0
5696 12:43:50.927020
5697 12:43:50.929601 DATLAT Default: 0xd
5698 12:43:50.930167 0, 0xFFFF, sum = 0
5699 12:43:50.933061 1, 0xFFFF, sum = 0
5700 12:43:50.933592 2, 0xFFFF, sum = 0
5701 12:43:50.936510 3, 0xFFFF, sum = 0
5702 12:43:50.937040 4, 0xFFFF, sum = 0
5703 12:43:50.939771 5, 0xFFFF, sum = 0
5704 12:43:50.940301 6, 0xFFFF, sum = 0
5705 12:43:50.943136 7, 0xFFFF, sum = 0
5706 12:43:50.943667 8, 0xFFFF, sum = 0
5707 12:43:50.946125 9, 0xFFFF, sum = 0
5708 12:43:50.946650 10, 0x0, sum = 1
5709 12:43:50.949858 11, 0x0, sum = 2
5710 12:43:50.950422 12, 0x0, sum = 3
5711 12:43:50.952655 13, 0x0, sum = 4
5712 12:43:50.953169 best_step = 11
5713 12:43:50.953504
5714 12:43:50.953813 ==
5715 12:43:50.956185 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 12:43:50.959716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 12:43:50.962866 ==
5718 12:43:50.963427 RX Vref Scan: 1
5719 12:43:50.963768
5720 12:43:50.966255 RX Vref 0 -> 0, step: 1
5721 12:43:50.966716
5722 12:43:50.967092 RX Delay -53 -> 252, step: 4
5723 12:43:50.969476
5724 12:43:50.969919 Set Vref, RX VrefLevel [Byte0]: 53
5725 12:43:50.972997 [Byte1]: 56
5726 12:43:50.977533
5727 12:43:50.977979 Final RX Vref Byte 0 = 53 to rank0
5728 12:43:50.981166 Final RX Vref Byte 1 = 56 to rank0
5729 12:43:50.984584 Final RX Vref Byte 0 = 53 to rank1
5730 12:43:50.987727 Final RX Vref Byte 1 = 56 to rank1==
5731 12:43:50.990762 Dram Type= 6, Freq= 0, CH_1, rank 0
5732 12:43:50.997755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 12:43:50.998314 ==
5734 12:43:50.998654 DQS Delay:
5735 12:43:50.998965 DQS0 = 0, DQS1 = 0
5736 12:43:51.001455 DQM Delay:
5737 12:43:51.002005 DQM0 = 104, DQM1 = 96
5738 12:43:51.004336 DQ Delay:
5739 12:43:51.007639 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5740 12:43:51.011118 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =100
5741 12:43:51.014519 DQ8 =88, DQ9 =84, DQ10 =100, DQ11 =92
5742 12:43:51.017894 DQ12 =106, DQ13 =102, DQ14 =100, DQ15 =102
5743 12:43:51.018497
5744 12:43:51.018868
5745 12:43:51.024404 [DQSOSCAuto] RK0, (LSB)MR18= 0x1932, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5746 12:43:51.027651 CH1 RK0: MR19=505, MR18=1932
5747 12:43:51.034344 CH1_RK0: MR19=0x505, MR18=0x1932, DQSOSC=406, MR23=63, INC=65, DEC=43
5748 12:43:51.034812
5749 12:43:51.037389 ----->DramcWriteLeveling(PI) begin...
5750 12:43:51.037995 ==
5751 12:43:51.040948 Dram Type= 6, Freq= 0, CH_1, rank 1
5752 12:43:51.044118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5753 12:43:51.044685 ==
5754 12:43:51.048007 Write leveling (Byte 0): 26 => 26
5755 12:43:51.050572 Write leveling (Byte 1): 28 => 28
5756 12:43:51.054234 DramcWriteLeveling(PI) end<-----
5757 12:43:51.054795
5758 12:43:51.055165 ==
5759 12:43:51.057594 Dram Type= 6, Freq= 0, CH_1, rank 1
5760 12:43:51.064123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5761 12:43:51.064678 ==
5762 12:43:51.065049 [Gating] SW mode calibration
5763 12:43:51.074267 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5764 12:43:51.077090 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5765 12:43:51.080768 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
5766 12:43:51.087553 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5767 12:43:51.090472 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5768 12:43:51.093903 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5769 12:43:51.100671 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5770 12:43:51.104291 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5771 12:43:51.106982 0 14 24 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 0)
5772 12:43:51.114048 0 14 28 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
5773 12:43:51.117367 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 12:43:51.120679 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 12:43:51.127435 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5776 12:43:51.130237 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5777 12:43:51.133793 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5778 12:43:51.140696 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5779 12:43:51.144020 0 15 24 | B1->B0 | 2c2c 2828 | 0 0 | (0 0) (0 0)
5780 12:43:51.147192 0 15 28 | B1->B0 | 4242 3f3f | 0 0 | (0 0) (0 0)
5781 12:43:51.154185 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 12:43:51.157406 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 12:43:51.160347 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 12:43:51.167046 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5785 12:43:51.170528 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 12:43:51.173840 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5787 12:43:51.180589 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5788 12:43:51.183821 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5789 12:43:51.186785 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 12:43:51.193767 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 12:43:51.196981 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 12:43:51.200060 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 12:43:51.206937 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 12:43:51.210203 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 12:43:51.213482 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 12:43:51.220446 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 12:43:51.223735 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 12:43:51.227157 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 12:43:51.229997 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 12:43:51.236712 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 12:43:51.240394 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 12:43:51.243525 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 12:43:51.249918 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5804 12:43:51.253079 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5805 12:43:51.256556 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 12:43:51.260116 Total UI for P1: 0, mck2ui 16
5807 12:43:51.263330 best dqsien dly found for B0: ( 1, 2, 26)
5808 12:43:51.266886 Total UI for P1: 0, mck2ui 16
5809 12:43:51.270107 best dqsien dly found for B1: ( 1, 2, 28)
5810 12:43:51.273236 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5811 12:43:51.276430 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5812 12:43:51.276906
5813 12:43:51.283349 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5814 12:43:51.286440 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5815 12:43:51.289779 [Gating] SW calibration Done
5816 12:43:51.290336 ==
5817 12:43:51.293418 Dram Type= 6, Freq= 0, CH_1, rank 1
5818 12:43:51.296608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5819 12:43:51.297080 ==
5820 12:43:51.297449 RX Vref Scan: 0
5821 12:43:51.297834
5822 12:43:51.299667 RX Vref 0 -> 0, step: 1
5823 12:43:51.300299
5824 12:43:51.303537 RX Delay -80 -> 252, step: 8
5825 12:43:51.306349 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5826 12:43:51.310042 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5827 12:43:51.313648 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5828 12:43:51.320028 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5829 12:43:51.323130 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5830 12:43:51.326371 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5831 12:43:51.329814 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5832 12:43:51.332691 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5833 12:43:51.336659 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5834 12:43:51.342696 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5835 12:43:51.346068 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5836 12:43:51.349360 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5837 12:43:51.352739 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5838 12:43:51.356114 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5839 12:43:51.362803 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5840 12:43:51.366040 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5841 12:43:51.366463 ==
5842 12:43:51.369638 Dram Type= 6, Freq= 0, CH_1, rank 1
5843 12:43:51.373293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5844 12:43:51.373877 ==
5845 12:43:51.374294 DQS Delay:
5846 12:43:51.376584 DQS0 = 0, DQS1 = 0
5847 12:43:51.377108 DQM Delay:
5848 12:43:51.379646 DQM0 = 101, DQM1 = 95
5849 12:43:51.380069 DQ Delay:
5850 12:43:51.383340 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5851 12:43:51.386301 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =99
5852 12:43:51.389567 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5853 12:43:51.392951 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5854 12:43:51.393527
5855 12:43:51.393901
5856 12:43:51.394309 ==
5857 12:43:51.396376 Dram Type= 6, Freq= 0, CH_1, rank 1
5858 12:43:51.402938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5859 12:43:51.403545 ==
5860 12:43:51.404042
5861 12:43:51.404502
5862 12:43:51.404950 TX Vref Scan disable
5863 12:43:51.406669 == TX Byte 0 ==
5864 12:43:51.410322 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5865 12:43:51.416805 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5866 12:43:51.417387 == TX Byte 1 ==
5867 12:43:51.420254 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5868 12:43:51.423178 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5869 12:43:51.426572 ==
5870 12:43:51.429834 Dram Type= 6, Freq= 0, CH_1, rank 1
5871 12:43:51.433187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5872 12:43:51.433663 ==
5873 12:43:51.434088
5874 12:43:51.434448
5875 12:43:51.436955 TX Vref Scan disable
5876 12:43:51.437529 == TX Byte 0 ==
5877 12:43:51.443398 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5878 12:43:51.446425 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5879 12:43:51.446861 == TX Byte 1 ==
5880 12:43:51.453178 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5881 12:43:51.456737 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5882 12:43:51.457279
5883 12:43:51.457621 [DATLAT]
5884 12:43:51.459464 Freq=933, CH1 RK1
5885 12:43:51.459890
5886 12:43:51.460224 DATLAT Default: 0xb
5887 12:43:51.463322 0, 0xFFFF, sum = 0
5888 12:43:51.463867 1, 0xFFFF, sum = 0
5889 12:43:51.466415 2, 0xFFFF, sum = 0
5890 12:43:51.466948 3, 0xFFFF, sum = 0
5891 12:43:51.469796 4, 0xFFFF, sum = 0
5892 12:43:51.473330 5, 0xFFFF, sum = 0
5893 12:43:51.473862 6, 0xFFFF, sum = 0
5894 12:43:51.476410 7, 0xFFFF, sum = 0
5895 12:43:51.476849 8, 0xFFFF, sum = 0
5896 12:43:51.479319 9, 0xFFFF, sum = 0
5897 12:43:51.479798 10, 0x0, sum = 1
5898 12:43:51.482575 11, 0x0, sum = 2
5899 12:43:51.483055 12, 0x0, sum = 3
5900 12:43:51.483433 13, 0x0, sum = 4
5901 12:43:51.486239 best_step = 11
5902 12:43:51.486821
5903 12:43:51.487199 ==
5904 12:43:51.489672 Dram Type= 6, Freq= 0, CH_1, rank 1
5905 12:43:51.493144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5906 12:43:51.493713 ==
5907 12:43:51.496468 RX Vref Scan: 0
5908 12:43:51.496939
5909 12:43:51.497313 RX Vref 0 -> 0, step: 1
5910 12:43:51.499182
5911 12:43:51.499653 RX Delay -53 -> 252, step: 4
5912 12:43:51.506982 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5913 12:43:51.510603 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5914 12:43:51.513725 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5915 12:43:51.516971 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5916 12:43:51.520497 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5917 12:43:51.526875 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5918 12:43:51.530259 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5919 12:43:51.533744 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5920 12:43:51.537020 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5921 12:43:51.540465 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5922 12:43:51.543666 iDelay=199, Bit 10, Center 98 (11 ~ 186) 176
5923 12:43:51.550319 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5924 12:43:51.553370 iDelay=199, Bit 12, Center 108 (23 ~ 194) 172
5925 12:43:51.556886 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5926 12:43:51.560322 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5927 12:43:51.567030 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5928 12:43:51.567599 ==
5929 12:43:51.570163 Dram Type= 6, Freq= 0, CH_1, rank 1
5930 12:43:51.573342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5931 12:43:51.573911 ==
5932 12:43:51.574332 DQS Delay:
5933 12:43:51.576569 DQS0 = 0, DQS1 = 0
5934 12:43:51.577035 DQM Delay:
5935 12:43:51.579789 DQM0 = 104, DQM1 = 97
5936 12:43:51.580254 DQ Delay:
5937 12:43:51.583506 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =102
5938 12:43:51.586381 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =102
5939 12:43:51.589703 DQ8 =86, DQ9 =88, DQ10 =98, DQ11 =92
5940 12:43:51.593253 DQ12 =108, DQ13 =102, DQ14 =102, DQ15 =106
5941 12:43:51.593814
5942 12:43:51.594239
5943 12:43:51.603380 [DQSOSCAuto] RK1, (LSB)MR18= 0x2300, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
5944 12:43:51.603953 CH1 RK1: MR19=505, MR18=2300
5945 12:43:51.610112 CH1_RK1: MR19=0x505, MR18=0x2300, DQSOSC=410, MR23=63, INC=64, DEC=42
5946 12:43:51.613048 [RxdqsGatingPostProcess] freq 933
5947 12:43:51.619941 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5948 12:43:51.623084 best DQS0 dly(2T, 0.5T) = (0, 10)
5949 12:43:51.626435 best DQS1 dly(2T, 0.5T) = (0, 10)
5950 12:43:51.629600 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5951 12:43:51.632887 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5952 12:43:51.636182 best DQS0 dly(2T, 0.5T) = (0, 10)
5953 12:43:51.639386 best DQS1 dly(2T, 0.5T) = (0, 10)
5954 12:43:51.642713 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5955 12:43:51.643187 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5956 12:43:51.646408 Pre-setting of DQS Precalculation
5957 12:43:51.652848 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5958 12:43:51.659322 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5959 12:43:51.666150 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5960 12:43:51.666730
5961 12:43:51.667108
5962 12:43:51.669379 [Calibration Summary] 1866 Mbps
5963 12:43:51.672953 CH 0, Rank 0
5964 12:43:51.673531 SW Impedance : PASS
5965 12:43:51.676310 DUTY Scan : NO K
5966 12:43:51.679323 ZQ Calibration : PASS
5967 12:43:51.679797 Jitter Meter : NO K
5968 12:43:51.682705 CBT Training : PASS
5969 12:43:51.686061 Write leveling : PASS
5970 12:43:51.686639 RX DQS gating : PASS
5971 12:43:51.689436 RX DQ/DQS(RDDQC) : PASS
5972 12:43:51.692352 TX DQ/DQS : PASS
5973 12:43:51.692828 RX DATLAT : PASS
5974 12:43:51.695738 RX DQ/DQS(Engine): PASS
5975 12:43:51.696211 TX OE : NO K
5976 12:43:51.699269 All Pass.
5977 12:43:51.699739
5978 12:43:51.700115 CH 0, Rank 1
5979 12:43:51.702161 SW Impedance : PASS
5980 12:43:51.702632 DUTY Scan : NO K
5981 12:43:51.705691 ZQ Calibration : PASS
5982 12:43:51.709004 Jitter Meter : NO K
5983 12:43:51.709558 CBT Training : PASS
5984 12:43:51.712230 Write leveling : PASS
5985 12:43:51.715898 RX DQS gating : PASS
5986 12:43:51.716481 RX DQ/DQS(RDDQC) : PASS
5987 12:43:51.719400 TX DQ/DQS : PASS
5988 12:43:51.721978 RX DATLAT : PASS
5989 12:43:51.722452 RX DQ/DQS(Engine): PASS
5990 12:43:51.725774 TX OE : NO K
5991 12:43:51.726392 All Pass.
5992 12:43:51.726772
5993 12:43:51.728723 CH 1, Rank 0
5994 12:43:51.729308 SW Impedance : PASS
5995 12:43:51.731951 DUTY Scan : NO K
5996 12:43:51.735203 ZQ Calibration : PASS
5997 12:43:51.735751 Jitter Meter : NO K
5998 12:43:51.738595 CBT Training : PASS
5999 12:43:51.742129 Write leveling : PASS
6000 12:43:51.742655 RX DQS gating : PASS
6001 12:43:51.745246 RX DQ/DQS(RDDQC) : PASS
6002 12:43:51.748859 TX DQ/DQS : PASS
6003 12:43:51.749455 RX DATLAT : PASS
6004 12:43:51.751669 RX DQ/DQS(Engine): PASS
6005 12:43:51.752097 TX OE : NO K
6006 12:43:51.755269 All Pass.
6007 12:43:51.755775
6008 12:43:51.756114 CH 1, Rank 1
6009 12:43:51.758641 SW Impedance : PASS
6010 12:43:51.759070 DUTY Scan : NO K
6011 12:43:51.761748 ZQ Calibration : PASS
6012 12:43:51.765048 Jitter Meter : NO K
6013 12:43:51.765474 CBT Training : PASS
6014 12:43:51.768802 Write leveling : PASS
6015 12:43:51.771591 RX DQS gating : PASS
6016 12:43:51.772064 RX DQ/DQS(RDDQC) : PASS
6017 12:43:51.775402 TX DQ/DQS : PASS
6018 12:43:51.778725 RX DATLAT : PASS
6019 12:43:51.779201 RX DQ/DQS(Engine): PASS
6020 12:43:51.781493 TX OE : NO K
6021 12:43:51.781999 All Pass.
6022 12:43:51.782377
6023 12:43:51.784946 DramC Write-DBI off
6024 12:43:51.788525 PER_BANK_REFRESH: Hybrid Mode
6025 12:43:51.789051 TX_TRACKING: ON
6026 12:43:51.798293 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6027 12:43:51.801783 [FAST_K] Save calibration result to emmc
6028 12:43:51.805144 dramc_set_vcore_voltage set vcore to 650000
6029 12:43:51.808389 Read voltage for 400, 6
6030 12:43:51.808935 Vio18 = 0
6031 12:43:51.809311 Vcore = 650000
6032 12:43:51.811986 Vdram = 0
6033 12:43:51.812551 Vddq = 0
6034 12:43:51.812999 Vmddr = 0
6035 12:43:51.818252 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6036 12:43:51.821784 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6037 12:43:51.825141 MEM_TYPE=3, freq_sel=20
6038 12:43:51.828063 sv_algorithm_assistance_LP4_800
6039 12:43:51.831685 ============ PULL DRAM RESETB DOWN ============
6040 12:43:51.834980 ========== PULL DRAM RESETB DOWN end =========
6041 12:43:51.841972 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6042 12:43:51.844780 ===================================
6043 12:43:51.848147 LPDDR4 DRAM CONFIGURATION
6044 12:43:51.851649 ===================================
6045 12:43:51.852124 EX_ROW_EN[0] = 0x0
6046 12:43:51.854869 EX_ROW_EN[1] = 0x0
6047 12:43:51.855374 LP4Y_EN = 0x0
6048 12:43:51.857985 WORK_FSP = 0x0
6049 12:43:51.858456 WL = 0x2
6050 12:43:51.861292 RL = 0x2
6051 12:43:51.861877 BL = 0x2
6052 12:43:51.865242 RPST = 0x0
6053 12:43:51.865782 RD_PRE = 0x0
6054 12:43:51.868044 WR_PRE = 0x1
6055 12:43:51.868567 WR_PST = 0x0
6056 12:43:51.871432 DBI_WR = 0x0
6057 12:43:51.871862 DBI_RD = 0x0
6058 12:43:51.874606 OTF = 0x1
6059 12:43:51.877998 ===================================
6060 12:43:51.881631 ===================================
6061 12:43:51.882187 ANA top config
6062 12:43:51.884599 ===================================
6063 12:43:51.888095 DLL_ASYNC_EN = 0
6064 12:43:51.891333 ALL_SLAVE_EN = 1
6065 12:43:51.894567 NEW_RANK_MODE = 1
6066 12:43:51.895002 DLL_IDLE_MODE = 1
6067 12:43:51.898493 LP45_APHY_COMB_EN = 1
6068 12:43:51.901169 TX_ODT_DIS = 1
6069 12:43:51.904591 NEW_8X_MODE = 1
6070 12:43:51.907568 ===================================
6071 12:43:51.911194 ===================================
6072 12:43:51.914644 data_rate = 800
6073 12:43:51.917972 CKR = 1
6074 12:43:51.918504 DQ_P2S_RATIO = 4
6075 12:43:51.921188 ===================================
6076 12:43:51.924268 CA_P2S_RATIO = 4
6077 12:43:51.927644 DQ_CA_OPEN = 0
6078 12:43:51.930854 DQ_SEMI_OPEN = 1
6079 12:43:51.934039 CA_SEMI_OPEN = 1
6080 12:43:51.937359 CA_FULL_RATE = 0
6081 12:43:51.937787 DQ_CKDIV4_EN = 0
6082 12:43:51.940881 CA_CKDIV4_EN = 1
6083 12:43:51.943985 CA_PREDIV_EN = 0
6084 12:43:51.947132 PH8_DLY = 0
6085 12:43:51.950796 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6086 12:43:51.954101 DQ_AAMCK_DIV = 0
6087 12:43:51.954532 CA_AAMCK_DIV = 0
6088 12:43:51.957137 CA_ADMCK_DIV = 4
6089 12:43:51.960732 DQ_TRACK_CA_EN = 0
6090 12:43:51.963794 CA_PICK = 800
6091 12:43:51.967324 CA_MCKIO = 400
6092 12:43:51.970341 MCKIO_SEMI = 400
6093 12:43:51.973637 PLL_FREQ = 3016
6094 12:43:51.974146 DQ_UI_PI_RATIO = 32
6095 12:43:51.977102 CA_UI_PI_RATIO = 32
6096 12:43:51.980176 ===================================
6097 12:43:51.984119 ===================================
6098 12:43:51.986618 memory_type:LPDDR4
6099 12:43:51.990611 GP_NUM : 10
6100 12:43:51.991225 SRAM_EN : 1
6101 12:43:51.994012 MD32_EN : 0
6102 12:43:51.996581 ===================================
6103 12:43:51.999960 [ANA_INIT] >>>>>>>>>>>>>>
6104 12:43:52.003505 <<<<<< [CONFIGURE PHASE]: ANA_TX
6105 12:43:52.006730 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6106 12:43:52.010176 ===================================
6107 12:43:52.010603 data_rate = 800,PCW = 0X7400
6108 12:43:52.013892 ===================================
6109 12:43:52.017450 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6110 12:43:52.023744 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6111 12:43:52.033181 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6112 12:43:52.040313 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6113 12:43:52.043494 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6114 12:43:52.046894 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6115 12:43:52.050095 [ANA_INIT] flow start
6116 12:43:52.050657 [ANA_INIT] PLL >>>>>>>>
6117 12:43:52.053383 [ANA_INIT] PLL <<<<<<<<
6118 12:43:52.056492 [ANA_INIT] MIDPI >>>>>>>>
6119 12:43:52.057081 [ANA_INIT] MIDPI <<<<<<<<
6120 12:43:52.059652 [ANA_INIT] DLL >>>>>>>>
6121 12:43:52.063142 [ANA_INIT] flow end
6122 12:43:52.066544 ============ LP4 DIFF to SE enter ============
6123 12:43:52.070138 ============ LP4 DIFF to SE exit ============
6124 12:43:52.073291 [ANA_INIT] <<<<<<<<<<<<<
6125 12:43:52.076857 [Flow] Enable top DCM control >>>>>
6126 12:43:52.079568 [Flow] Enable top DCM control <<<<<
6127 12:43:52.083506 Enable DLL master slave shuffle
6128 12:43:52.086388 ==============================================================
6129 12:43:52.089651 Gating Mode config
6130 12:43:52.096453 ==============================================================
6131 12:43:52.097031 Config description:
6132 12:43:52.106742 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6133 12:43:52.113501 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6134 12:43:52.116350 SELPH_MODE 0: By rank 1: By Phase
6135 12:43:52.122897 ==============================================================
6136 12:43:52.126462 GAT_TRACK_EN = 0
6137 12:43:52.129987 RX_GATING_MODE = 2
6138 12:43:52.133063 RX_GATING_TRACK_MODE = 2
6139 12:43:52.136364 SELPH_MODE = 1
6140 12:43:52.139948 PICG_EARLY_EN = 1
6141 12:43:52.142485 VALID_LAT_VALUE = 1
6142 12:43:52.146225 ==============================================================
6143 12:43:52.149477 Enter into Gating configuration >>>>
6144 12:43:52.152851 Exit from Gating configuration <<<<
6145 12:43:52.156328 Enter into DVFS_PRE_config >>>>>
6146 12:43:52.169441 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6147 12:43:52.170064 Exit from DVFS_PRE_config <<<<<
6148 12:43:52.172534 Enter into PICG configuration >>>>
6149 12:43:52.176101 Exit from PICG configuration <<<<
6150 12:43:52.179065 [RX_INPUT] configuration >>>>>
6151 12:43:52.182366 [RX_INPUT] configuration <<<<<
6152 12:43:52.189379 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6153 12:43:52.192573 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6154 12:43:52.199186 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6155 12:43:52.206121 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6156 12:43:52.212809 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6157 12:43:52.219141 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6158 12:43:52.222641 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6159 12:43:52.226041 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6160 12:43:52.228970 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6161 12:43:52.235481 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6162 12:43:52.239420 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6163 12:43:52.242357 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6164 12:43:52.245702 ===================================
6165 12:43:52.249186 LPDDR4 DRAM CONFIGURATION
6166 12:43:52.252392 ===================================
6167 12:43:52.252961 EX_ROW_EN[0] = 0x0
6168 12:43:52.255730 EX_ROW_EN[1] = 0x0
6169 12:43:52.259005 LP4Y_EN = 0x0
6170 12:43:52.259576 WORK_FSP = 0x0
6171 12:43:52.262406 WL = 0x2
6172 12:43:52.262980 RL = 0x2
6173 12:43:52.265700 BL = 0x2
6174 12:43:52.266307 RPST = 0x0
6175 12:43:52.269140 RD_PRE = 0x0
6176 12:43:52.269708 WR_PRE = 0x1
6177 12:43:52.272037 WR_PST = 0x0
6178 12:43:52.272511 DBI_WR = 0x0
6179 12:43:52.275429 DBI_RD = 0x0
6180 12:43:52.275901 OTF = 0x1
6181 12:43:52.279291 ===================================
6182 12:43:52.283342 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6183 12:43:52.288827 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6184 12:43:52.292144 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6185 12:43:52.295367 ===================================
6186 12:43:52.298666 LPDDR4 DRAM CONFIGURATION
6187 12:43:52.302062 ===================================
6188 12:43:52.302584 EX_ROW_EN[0] = 0x10
6189 12:43:52.305596 EX_ROW_EN[1] = 0x0
6190 12:43:52.306197 LP4Y_EN = 0x0
6191 12:43:52.308622 WORK_FSP = 0x0
6192 12:43:52.312212 WL = 0x2
6193 12:43:52.312781 RL = 0x2
6194 12:43:52.315520 BL = 0x2
6195 12:43:52.316093 RPST = 0x0
6196 12:43:52.318622 RD_PRE = 0x0
6197 12:43:52.319183 WR_PRE = 0x1
6198 12:43:52.322026 WR_PST = 0x0
6199 12:43:52.322499 DBI_WR = 0x0
6200 12:43:52.325585 DBI_RD = 0x0
6201 12:43:52.326183 OTF = 0x1
6202 12:43:52.328830 ===================================
6203 12:43:52.335377 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6204 12:43:52.339170 nWR fixed to 30
6205 12:43:52.342668 [ModeRegInit_LP4] CH0 RK0
6206 12:43:52.343138 [ModeRegInit_LP4] CH0 RK1
6207 12:43:52.346107 [ModeRegInit_LP4] CH1 RK0
6208 12:43:52.349339 [ModeRegInit_LP4] CH1 RK1
6209 12:43:52.349908 match AC timing 19
6210 12:43:52.356303 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6211 12:43:52.359561 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6212 12:43:52.362771 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6213 12:43:52.369044 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6214 12:43:52.372457 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6215 12:43:52.373119 ==
6216 12:43:52.375540 Dram Type= 6, Freq= 0, CH_0, rank 0
6217 12:43:52.378996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6218 12:43:52.379689 ==
6219 12:43:52.385828 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6220 12:43:52.392194 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6221 12:43:52.395662 [CA 0] Center 36 (8~64) winsize 57
6222 12:43:52.399087 [CA 1] Center 36 (8~64) winsize 57
6223 12:43:52.402391 [CA 2] Center 36 (8~64) winsize 57
6224 12:43:52.402819 [CA 3] Center 36 (8~64) winsize 57
6225 12:43:52.405936 [CA 4] Center 36 (8~64) winsize 57
6226 12:43:52.408840 [CA 5] Center 36 (8~64) winsize 57
6227 12:43:52.409271
6228 12:43:52.415692 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6229 12:43:52.416224
6230 12:43:52.419485 [CATrainingPosCal] consider 1 rank data
6231 12:43:52.422256 u2DelayCellTimex100 = 270/100 ps
6232 12:43:52.425805 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 12:43:52.429232 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 12:43:52.432295 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 12:43:52.435998 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 12:43:52.439256 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 12:43:52.442600 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 12:43:52.443127
6239 12:43:52.446045 CA PerBit enable=1, Macro0, CA PI delay=36
6240 12:43:52.446575
6241 12:43:52.449148 [CBTSetCACLKResult] CA Dly = 36
6242 12:43:52.452153 CS Dly: 1 (0~32)
6243 12:43:52.452579 ==
6244 12:43:52.455477 Dram Type= 6, Freq= 0, CH_0, rank 1
6245 12:43:52.459563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6246 12:43:52.460092 ==
6247 12:43:52.465701 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6248 12:43:52.469163 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6249 12:43:52.472510 [CA 0] Center 36 (8~64) winsize 57
6250 12:43:52.475901 [CA 1] Center 36 (8~64) winsize 57
6251 12:43:52.478697 [CA 2] Center 36 (8~64) winsize 57
6252 12:43:52.482511 [CA 3] Center 36 (8~64) winsize 57
6253 12:43:52.485366 [CA 4] Center 36 (8~64) winsize 57
6254 12:43:52.488674 [CA 5] Center 36 (8~64) winsize 57
6255 12:43:52.489098
6256 12:43:52.492246 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6257 12:43:52.492769
6258 12:43:52.495378 [CATrainingPosCal] consider 2 rank data
6259 12:43:52.498241 u2DelayCellTimex100 = 270/100 ps
6260 12:43:52.502122 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 12:43:52.505167 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 12:43:52.511847 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 12:43:52.515283 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 12:43:52.518416 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 12:43:52.522015 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 12:43:52.522543
6267 12:43:52.525243 CA PerBit enable=1, Macro0, CA PI delay=36
6268 12:43:52.525769
6269 12:43:52.528361 [CBTSetCACLKResult] CA Dly = 36
6270 12:43:52.528942 CS Dly: 1 (0~32)
6271 12:43:52.529285
6272 12:43:52.531659 ----->DramcWriteLeveling(PI) begin...
6273 12:43:52.534990 ==
6274 12:43:52.538364 Dram Type= 6, Freq= 0, CH_0, rank 0
6275 12:43:52.541494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6276 12:43:52.542046 ==
6277 12:43:52.544921 Write leveling (Byte 0): 40 => 8
6278 12:43:52.548121 Write leveling (Byte 1): 32 => 0
6279 12:43:52.551749 DramcWriteLeveling(PI) end<-----
6280 12:43:52.552273
6281 12:43:52.552610 ==
6282 12:43:52.554820 Dram Type= 6, Freq= 0, CH_0, rank 0
6283 12:43:52.558441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6284 12:43:52.558969 ==
6285 12:43:52.561282 [Gating] SW mode calibration
6286 12:43:52.568048 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6287 12:43:52.575030 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6288 12:43:52.577925 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6289 12:43:52.581467 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6290 12:43:52.584825 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6291 12:43:52.591332 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6292 12:43:52.594713 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6293 12:43:52.598036 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6294 12:43:52.604943 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6295 12:43:52.607832 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6296 12:43:52.611339 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6297 12:43:52.614868 Total UI for P1: 0, mck2ui 16
6298 12:43:52.618109 best dqsien dly found for B0: ( 0, 14, 24)
6299 12:43:52.621003 Total UI for P1: 0, mck2ui 16
6300 12:43:52.624526 best dqsien dly found for B1: ( 0, 14, 24)
6301 12:43:52.627821 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6302 12:43:52.631302 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6303 12:43:52.634310
6304 12:43:52.637602 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6305 12:43:52.641109 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6306 12:43:52.644420 [Gating] SW calibration Done
6307 12:43:52.644838 ==
6308 12:43:52.647939 Dram Type= 6, Freq= 0, CH_0, rank 0
6309 12:43:52.651174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6310 12:43:52.651598 ==
6311 12:43:52.651857 RX Vref Scan: 0
6312 12:43:52.652093
6313 12:43:52.654365 RX Vref 0 -> 0, step: 1
6314 12:43:52.654687
6315 12:43:52.657802 RX Delay -410 -> 252, step: 16
6316 12:43:52.661042 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6317 12:43:52.667740 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6318 12:43:52.671081 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6319 12:43:52.674779 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6320 12:43:52.677914 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6321 12:43:52.684164 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6322 12:43:52.687717 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6323 12:43:52.690758 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6324 12:43:52.694054 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6325 12:43:52.701060 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6326 12:43:52.704448 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6327 12:43:52.707588 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6328 12:43:52.710746 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6329 12:43:52.717308 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6330 12:43:52.721114 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6331 12:43:52.724429 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6332 12:43:52.724979 ==
6333 12:43:52.727403 Dram Type= 6, Freq= 0, CH_0, rank 0
6334 12:43:52.734341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6335 12:43:52.734886 ==
6336 12:43:52.735246 DQS Delay:
6337 12:43:52.735587 DQS0 = 27, DQS1 = 43
6338 12:43:52.737364 DQM Delay:
6339 12:43:52.737822 DQM0 = 12, DQM1 = 13
6340 12:43:52.740966 DQ Delay:
6341 12:43:52.744296 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =8
6342 12:43:52.744850 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6343 12:43:52.747842 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6344 12:43:52.750912 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6345 12:43:52.751369
6346 12:43:52.754524
6347 12:43:52.755073 ==
6348 12:43:52.757789 Dram Type= 6, Freq= 0, CH_0, rank 0
6349 12:43:52.760669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 12:43:52.761222 ==
6351 12:43:52.761587
6352 12:43:52.761925
6353 12:43:52.764130 TX Vref Scan disable
6354 12:43:52.764680 == TX Byte 0 ==
6355 12:43:52.767476 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6356 12:43:52.774112 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6357 12:43:52.774664 == TX Byte 1 ==
6358 12:43:52.777798 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6359 12:43:52.784133 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6360 12:43:52.784679 ==
6361 12:43:52.787016 Dram Type= 6, Freq= 0, CH_0, rank 0
6362 12:43:52.790405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6363 12:43:52.790865 ==
6364 12:43:52.791225
6365 12:43:52.791560
6366 12:43:52.794229 TX Vref Scan disable
6367 12:43:52.794685 == TX Byte 0 ==
6368 12:43:52.797351 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6369 12:43:52.804178 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6370 12:43:52.804733 == TX Byte 1 ==
6371 12:43:52.807439 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6372 12:43:52.814113 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6373 12:43:52.814850
6374 12:43:52.815249 [DATLAT]
6375 12:43:52.817421 Freq=400, CH0 RK0
6376 12:43:52.818006
6377 12:43:52.818372 DATLAT Default: 0xf
6378 12:43:52.821068 0, 0xFFFF, sum = 0
6379 12:43:52.821626 1, 0xFFFF, sum = 0
6380 12:43:52.823580 2, 0xFFFF, sum = 0
6381 12:43:52.824043 3, 0xFFFF, sum = 0
6382 12:43:52.826940 4, 0xFFFF, sum = 0
6383 12:43:52.827402 5, 0xFFFF, sum = 0
6384 12:43:52.830470 6, 0xFFFF, sum = 0
6385 12:43:52.830935 7, 0xFFFF, sum = 0
6386 12:43:52.834121 8, 0xFFFF, sum = 0
6387 12:43:52.834586 9, 0xFFFF, sum = 0
6388 12:43:52.837038 10, 0xFFFF, sum = 0
6389 12:43:52.837594 11, 0xFFFF, sum = 0
6390 12:43:52.840337 12, 0xFFFF, sum = 0
6391 12:43:52.840898 13, 0x0, sum = 1
6392 12:43:52.843516 14, 0x0, sum = 2
6393 12:43:52.843980 15, 0x0, sum = 3
6394 12:43:52.846788 16, 0x0, sum = 4
6395 12:43:52.847253 best_step = 14
6396 12:43:52.847613
6397 12:43:52.847946 ==
6398 12:43:52.850325 Dram Type= 6, Freq= 0, CH_0, rank 0
6399 12:43:52.856904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6400 12:43:52.857462 ==
6401 12:43:52.857822 RX Vref Scan: 1
6402 12:43:52.858196
6403 12:43:52.860566 RX Vref 0 -> 0, step: 1
6404 12:43:52.861115
6405 12:43:52.863872 RX Delay -327 -> 252, step: 8
6406 12:43:52.864423
6407 12:43:52.866976 Set Vref, RX VrefLevel [Byte0]: 61
6408 12:43:52.870557 [Byte1]: 49
6409 12:43:52.871108
6410 12:43:52.873726 Final RX Vref Byte 0 = 61 to rank0
6411 12:43:52.876954 Final RX Vref Byte 1 = 49 to rank0
6412 12:43:52.880378 Final RX Vref Byte 0 = 61 to rank1
6413 12:43:52.883876 Final RX Vref Byte 1 = 49 to rank1==
6414 12:43:52.886574 Dram Type= 6, Freq= 0, CH_0, rank 0
6415 12:43:52.890232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 12:43:52.893406 ==
6417 12:43:52.893991 DQS Delay:
6418 12:43:52.894390 DQS0 = 24, DQS1 = 48
6419 12:43:52.896881 DQM Delay:
6420 12:43:52.897447 DQM0 = 8, DQM1 = 15
6421 12:43:52.900239 DQ Delay:
6422 12:43:52.900803 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6423 12:43:52.903731 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6424 12:43:52.906729 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6425 12:43:52.910072 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6426 12:43:52.910635
6427 12:43:52.911007
6428 12:43:52.920170 [DQSOSCAuto] RK0, (LSB)MR18= 0xb3ab, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6429 12:43:52.923396 CH0 RK0: MR19=C0C, MR18=B3AB
6430 12:43:52.930062 CH0_RK0: MR19=0xC0C, MR18=0xB3AB, DQSOSC=387, MR23=63, INC=394, DEC=262
6431 12:43:52.930641 ==
6432 12:43:52.933258 Dram Type= 6, Freq= 0, CH_0, rank 1
6433 12:43:52.936521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6434 12:43:52.936996 ==
6435 12:43:52.939744 [Gating] SW mode calibration
6436 12:43:52.946247 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6437 12:43:52.949575 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6438 12:43:52.956532 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6439 12:43:52.959707 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6440 12:43:52.963076 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6441 12:43:52.969884 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6442 12:43:52.973209 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6443 12:43:52.976336 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6444 12:43:52.983099 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6445 12:43:52.986448 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6446 12:43:52.989921 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6447 12:43:52.993121 Total UI for P1: 0, mck2ui 16
6448 12:43:52.996243 best dqsien dly found for B0: ( 0, 14, 24)
6449 12:43:52.999447 Total UI for P1: 0, mck2ui 16
6450 12:43:53.003124 best dqsien dly found for B1: ( 0, 14, 24)
6451 12:43:53.006150 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6452 12:43:53.009795 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6453 12:43:53.010404
6454 12:43:53.016470 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6455 12:43:53.019494 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6456 12:43:53.023059 [Gating] SW calibration Done
6457 12:43:53.023633 ==
6458 12:43:53.026289 Dram Type= 6, Freq= 0, CH_0, rank 1
6459 12:43:53.029821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6460 12:43:53.030449 ==
6461 12:43:53.030830 RX Vref Scan: 0
6462 12:43:53.031176
6463 12:43:53.032878 RX Vref 0 -> 0, step: 1
6464 12:43:53.033366
6465 12:43:53.035918 RX Delay -410 -> 252, step: 16
6466 12:43:53.039251 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6467 12:43:53.046080 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6468 12:43:53.049550 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6469 12:43:53.052973 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6470 12:43:53.056063 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6471 12:43:53.062674 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6472 12:43:53.066289 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6473 12:43:53.069229 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6474 12:43:53.072478 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6475 12:43:53.076058 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6476 12:43:53.082335 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6477 12:43:53.085815 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6478 12:43:53.089100 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6479 12:43:53.096017 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6480 12:43:53.099142 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6481 12:43:53.102564 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6482 12:43:53.103040 ==
6483 12:43:53.106094 Dram Type= 6, Freq= 0, CH_0, rank 1
6484 12:43:53.109460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 12:43:53.112875 ==
6486 12:43:53.113440 DQS Delay:
6487 12:43:53.113818 DQS0 = 27, DQS1 = 43
6488 12:43:53.116164 DQM Delay:
6489 12:43:53.116721 DQM0 = 9, DQM1 = 15
6490 12:43:53.119141 DQ Delay:
6491 12:43:53.119708 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6492 12:43:53.122805 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6493 12:43:53.125759 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6494 12:43:53.129629 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6495 12:43:53.130239
6496 12:43:53.130618
6497 12:43:53.130963 ==
6498 12:43:53.132805 Dram Type= 6, Freq= 0, CH_0, rank 1
6499 12:43:53.139154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 12:43:53.139649 ==
6501 12:43:53.140026
6502 12:43:53.140372
6503 12:43:53.140702 TX Vref Scan disable
6504 12:43:53.142731 == TX Byte 0 ==
6505 12:43:53.145791 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6506 12:43:53.149142 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6507 12:43:53.152804 == TX Byte 1 ==
6508 12:43:53.156018 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6509 12:43:53.159334 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6510 12:43:53.159810 ==
6511 12:43:53.162655 Dram Type= 6, Freq= 0, CH_0, rank 1
6512 12:43:53.169020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6513 12:43:53.169577 ==
6514 12:43:53.169990
6515 12:43:53.170358
6516 12:43:53.170693 TX Vref Scan disable
6517 12:43:53.172743 == TX Byte 0 ==
6518 12:43:53.175636 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6519 12:43:53.179199 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6520 12:43:53.182594 == TX Byte 1 ==
6521 12:43:53.186066 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6522 12:43:53.189250 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6523 12:43:53.189821
6524 12:43:53.192765 [DATLAT]
6525 12:43:53.193330 Freq=400, CH0 RK1
6526 12:43:53.193706
6527 12:43:53.195499 DATLAT Default: 0xe
6528 12:43:53.196017 0, 0xFFFF, sum = 0
6529 12:43:53.198953 1, 0xFFFF, sum = 0
6530 12:43:53.199537 2, 0xFFFF, sum = 0
6531 12:43:53.202495 3, 0xFFFF, sum = 0
6532 12:43:53.203071 4, 0xFFFF, sum = 0
6533 12:43:53.205678 5, 0xFFFF, sum = 0
6534 12:43:53.206309 6, 0xFFFF, sum = 0
6535 12:43:53.209340 7, 0xFFFF, sum = 0
6536 12:43:53.209910 8, 0xFFFF, sum = 0
6537 12:43:53.212070 9, 0xFFFF, sum = 0
6538 12:43:53.212549 10, 0xFFFF, sum = 0
6539 12:43:53.215802 11, 0xFFFF, sum = 0
6540 12:43:53.219473 12, 0xFFFF, sum = 0
6541 12:43:53.220048 13, 0x0, sum = 1
6542 12:43:53.220430 14, 0x0, sum = 2
6543 12:43:53.222256 15, 0x0, sum = 3
6544 12:43:53.222735 16, 0x0, sum = 4
6545 12:43:53.225984 best_step = 14
6546 12:43:53.226547
6547 12:43:53.226923 ==
6548 12:43:53.229334 Dram Type= 6, Freq= 0, CH_0, rank 1
6549 12:43:53.232368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6550 12:43:53.232939 ==
6551 12:43:53.235797 RX Vref Scan: 0
6552 12:43:53.236270
6553 12:43:53.236642 RX Vref 0 -> 0, step: 1
6554 12:43:53.236992
6555 12:43:53.238789 RX Delay -327 -> 252, step: 8
6556 12:43:53.247111 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6557 12:43:53.250693 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6558 12:43:53.254066 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6559 12:43:53.257095 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6560 12:43:53.263776 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6561 12:43:53.267183 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6562 12:43:53.270024 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6563 12:43:53.273777 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6564 12:43:53.280121 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6565 12:43:53.283491 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6566 12:43:53.287162 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6567 12:43:53.290231 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6568 12:43:53.297142 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6569 12:43:53.300185 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6570 12:43:53.303689 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6571 12:43:53.310260 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6572 12:43:53.310829 ==
6573 12:43:53.313875 Dram Type= 6, Freq= 0, CH_0, rank 1
6574 12:43:53.317284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6575 12:43:53.317855 ==
6576 12:43:53.318326 DQS Delay:
6577 12:43:53.320598 DQS0 = 28, DQS1 = 40
6578 12:43:53.321166 DQM Delay:
6579 12:43:53.323962 DQM0 = 9, DQM1 = 12
6580 12:43:53.324537 DQ Delay:
6581 12:43:53.327294 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6582 12:43:53.330156 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6583 12:43:53.333398 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6584 12:43:53.336518 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =16
6585 12:43:53.337191
6586 12:43:53.337585
6587 12:43:53.343647 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe71, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6588 12:43:53.346800 CH0 RK1: MR19=C0C, MR18=BE71
6589 12:43:53.353309 CH0_RK1: MR19=0xC0C, MR18=0xBE71, DQSOSC=386, MR23=63, INC=396, DEC=264
6590 12:43:53.356609 [RxdqsGatingPostProcess] freq 400
6591 12:43:53.360020 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6592 12:43:53.363246 best DQS0 dly(2T, 0.5T) = (0, 10)
6593 12:43:53.366946 best DQS1 dly(2T, 0.5T) = (0, 10)
6594 12:43:53.370424 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6595 12:43:53.373076 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6596 12:43:53.376456 best DQS0 dly(2T, 0.5T) = (0, 10)
6597 12:43:53.379993 best DQS1 dly(2T, 0.5T) = (0, 10)
6598 12:43:53.383333 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6599 12:43:53.386372 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6600 12:43:53.390031 Pre-setting of DQS Precalculation
6601 12:43:53.393087 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6602 12:43:53.396740 ==
6603 12:43:53.397210 Dram Type= 6, Freq= 0, CH_1, rank 0
6604 12:43:53.403575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6605 12:43:53.404004 ==
6606 12:43:53.406828 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6607 12:43:53.413478 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6608 12:43:53.416876 [CA 0] Center 36 (8~64) winsize 57
6609 12:43:53.419777 [CA 1] Center 36 (8~64) winsize 57
6610 12:43:53.423505 [CA 2] Center 36 (8~64) winsize 57
6611 12:43:53.426437 [CA 3] Center 36 (8~64) winsize 57
6612 12:43:53.430020 [CA 4] Center 36 (8~64) winsize 57
6613 12:43:53.433224 [CA 5] Center 36 (8~64) winsize 57
6614 12:43:53.433669
6615 12:43:53.436719 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6616 12:43:53.437145
6617 12:43:53.440015 [CATrainingPosCal] consider 1 rank data
6618 12:43:53.442770 u2DelayCellTimex100 = 270/100 ps
6619 12:43:53.446451 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 12:43:53.449373 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 12:43:53.452787 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 12:43:53.455863 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 12:43:53.459573 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 12:43:53.465780 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 12:43:53.465868
6626 12:43:53.469619 CA PerBit enable=1, Macro0, CA PI delay=36
6627 12:43:53.469701
6628 12:43:53.472847 [CBTSetCACLKResult] CA Dly = 36
6629 12:43:53.472920 CS Dly: 1 (0~32)
6630 12:43:53.472982 ==
6631 12:43:53.476094 Dram Type= 6, Freq= 0, CH_1, rank 1
6632 12:43:53.479684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6633 12:43:53.482660 ==
6634 12:43:53.486100 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6635 12:43:53.492744 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6636 12:43:53.496155 [CA 0] Center 36 (8~64) winsize 57
6637 12:43:53.499265 [CA 1] Center 36 (8~64) winsize 57
6638 12:43:53.502917 [CA 2] Center 36 (8~64) winsize 57
6639 12:43:53.506071 [CA 3] Center 36 (8~64) winsize 57
6640 12:43:53.509472 [CA 4] Center 36 (8~64) winsize 57
6641 12:43:53.512811 [CA 5] Center 36 (8~64) winsize 57
6642 12:43:53.512996
6643 12:43:53.516342 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6644 12:43:53.516544
6645 12:43:53.519735 [CATrainingPosCal] consider 2 rank data
6646 12:43:53.523244 u2DelayCellTimex100 = 270/100 ps
6647 12:43:53.526124 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 12:43:53.529838 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 12:43:53.533082 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 12:43:53.536332 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 12:43:53.539719 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 12:43:53.543003 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 12:43:53.543466
6654 12:43:53.546127 CA PerBit enable=1, Macro0, CA PI delay=36
6655 12:43:53.546649
6656 12:43:53.549753 [CBTSetCACLKResult] CA Dly = 36
6657 12:43:53.552859 CS Dly: 1 (0~32)
6658 12:43:53.553322
6659 12:43:53.556508 ----->DramcWriteLeveling(PI) begin...
6660 12:43:53.557085 ==
6661 12:43:53.559835 Dram Type= 6, Freq= 0, CH_1, rank 0
6662 12:43:53.563378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6663 12:43:53.563948 ==
6664 12:43:53.566834 Write leveling (Byte 0): 40 => 8
6665 12:43:53.569577 Write leveling (Byte 1): 32 => 0
6666 12:43:53.573305 DramcWriteLeveling(PI) end<-----
6667 12:43:53.573871
6668 12:43:53.574302 ==
6669 12:43:53.576162 Dram Type= 6, Freq= 0, CH_1, rank 0
6670 12:43:53.579565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6671 12:43:53.580132 ==
6672 12:43:53.582787 [Gating] SW mode calibration
6673 12:43:53.589589 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6674 12:43:53.596090 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6675 12:43:53.599538 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6676 12:43:53.605869 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6677 12:43:53.609652 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6678 12:43:53.612474 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6679 12:43:53.619302 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6680 12:43:53.622794 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6681 12:43:53.626116 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6682 12:43:53.629560 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6683 12:43:53.635856 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6684 12:43:53.639164 Total UI for P1: 0, mck2ui 16
6685 12:43:53.642708 best dqsien dly found for B0: ( 0, 14, 24)
6686 12:43:53.645997 Total UI for P1: 0, mck2ui 16
6687 12:43:53.649330 best dqsien dly found for B1: ( 0, 14, 24)
6688 12:43:53.652659 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6689 12:43:53.655977 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6690 12:43:53.656552
6691 12:43:53.659423 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6692 12:43:53.662802 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6693 12:43:53.665657 [Gating] SW calibration Done
6694 12:43:53.666262 ==
6695 12:43:53.669238 Dram Type= 6, Freq= 0, CH_1, rank 0
6696 12:43:53.672886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6697 12:43:53.673465 ==
6698 12:43:53.675969 RX Vref Scan: 0
6699 12:43:53.676439
6700 12:43:53.679222 RX Vref 0 -> 0, step: 1
6701 12:43:53.679790
6702 12:43:53.680169 RX Delay -410 -> 252, step: 16
6703 12:43:53.685845 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6704 12:43:53.689173 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6705 12:43:53.692534 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6706 12:43:53.695618 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6707 12:43:53.702466 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6708 12:43:53.705600 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6709 12:43:53.709026 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6710 12:43:53.712442 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6711 12:43:53.718931 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6712 12:43:53.722545 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6713 12:43:53.725787 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6714 12:43:53.729132 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6715 12:43:53.735887 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6716 12:43:53.739244 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6717 12:43:53.742075 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6718 12:43:53.748966 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6719 12:43:53.749535 ==
6720 12:43:53.752216 Dram Type= 6, Freq= 0, CH_1, rank 0
6721 12:43:53.755608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6722 12:43:53.756198 ==
6723 12:43:53.756578 DQS Delay:
6724 12:43:53.758463 DQS0 = 19, DQS1 = 43
6725 12:43:53.758932 DQM Delay:
6726 12:43:53.762396 DQM0 = 2, DQM1 = 20
6727 12:43:53.762960 DQ Delay:
6728 12:43:53.765714 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6729 12:43:53.769057 DQ4 =0, DQ5 =8, DQ6 =8, DQ7 =0
6730 12:43:53.772173 DQ8 =0, DQ9 =0, DQ10 =24, DQ11 =24
6731 12:43:53.775618 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6732 12:43:53.776201
6733 12:43:53.776573
6734 12:43:53.776918 ==
6735 12:43:53.778541 Dram Type= 6, Freq= 0, CH_1, rank 0
6736 12:43:53.782184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 12:43:53.782753 ==
6738 12:43:53.783132
6739 12:43:53.783478
6740 12:43:53.785419 TX Vref Scan disable
6741 12:43:53.786012 == TX Byte 0 ==
6742 12:43:53.791928 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6743 12:43:53.795081 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6744 12:43:53.795553 == TX Byte 1 ==
6745 12:43:53.802026 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6746 12:43:53.805419 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6747 12:43:53.806036 ==
6748 12:43:53.808603 Dram Type= 6, Freq= 0, CH_1, rank 0
6749 12:43:53.811579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6750 12:43:53.812053 ==
6751 12:43:53.812427
6752 12:43:53.812770
6753 12:43:53.815004 TX Vref Scan disable
6754 12:43:53.815471 == TX Byte 0 ==
6755 12:43:53.821825 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6756 12:43:53.825069 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6757 12:43:53.825648 == TX Byte 1 ==
6758 12:43:53.832060 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6759 12:43:53.835225 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6760 12:43:53.835792
6761 12:43:53.836164 [DATLAT]
6762 12:43:53.838329 Freq=400, CH1 RK0
6763 12:43:53.838797
6764 12:43:53.839183 DATLAT Default: 0xf
6765 12:43:53.841537 0, 0xFFFF, sum = 0
6766 12:43:53.842184 1, 0xFFFF, sum = 0
6767 12:43:53.845091 2, 0xFFFF, sum = 0
6768 12:43:53.845664 3, 0xFFFF, sum = 0
6769 12:43:53.848506 4, 0xFFFF, sum = 0
6770 12:43:53.851674 5, 0xFFFF, sum = 0
6771 12:43:53.852153 6, 0xFFFF, sum = 0
6772 12:43:53.855289 7, 0xFFFF, sum = 0
6773 12:43:53.855860 8, 0xFFFF, sum = 0
6774 12:43:53.858541 9, 0xFFFF, sum = 0
6775 12:43:53.859125 10, 0xFFFF, sum = 0
6776 12:43:53.861513 11, 0xFFFF, sum = 0
6777 12:43:53.862007 12, 0xFFFF, sum = 0
6778 12:43:53.865145 13, 0x0, sum = 1
6779 12:43:53.865725 14, 0x0, sum = 2
6780 12:43:53.868146 15, 0x0, sum = 3
6781 12:43:53.868619 16, 0x0, sum = 4
6782 12:43:53.871671 best_step = 14
6783 12:43:53.872238
6784 12:43:53.872610 ==
6785 12:43:53.874621 Dram Type= 6, Freq= 0, CH_1, rank 0
6786 12:43:53.878279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6787 12:43:53.878848 ==
6788 12:43:53.879220 RX Vref Scan: 1
6789 12:43:53.881662
6790 12:43:53.882265 RX Vref 0 -> 0, step: 1
6791 12:43:53.882641
6792 12:43:53.884784 RX Delay -327 -> 252, step: 8
6793 12:43:53.885327
6794 12:43:53.888396 Set Vref, RX VrefLevel [Byte0]: 53
6795 12:43:53.891190 [Byte1]: 56
6796 12:43:53.895423
6797 12:43:53.895883 Final RX Vref Byte 0 = 53 to rank0
6798 12:43:53.898967 Final RX Vref Byte 1 = 56 to rank0
6799 12:43:53.902243 Final RX Vref Byte 0 = 53 to rank1
6800 12:43:53.905480 Final RX Vref Byte 1 = 56 to rank1==
6801 12:43:53.908671 Dram Type= 6, Freq= 0, CH_1, rank 0
6802 12:43:53.914998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 12:43:53.915600 ==
6804 12:43:53.916157 DQS Delay:
6805 12:43:53.918705 DQS0 = 32, DQS1 = 40
6806 12:43:53.919181 DQM Delay:
6807 12:43:53.919624 DQM0 = 11, DQM1 = 12
6808 12:43:53.922072 DQ Delay:
6809 12:43:53.924972 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6810 12:43:53.925444 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6811 12:43:53.929151 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =4
6812 12:43:53.932151 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =16
6813 12:43:53.932734
6814 12:43:53.935209
6815 12:43:53.942036 [DQSOSCAuto] RK0, (LSB)MR18= 0x94ce, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6816 12:43:53.945654 CH1 RK0: MR19=C0C, MR18=94CE
6817 12:43:53.951973 CH1_RK0: MR19=0xC0C, MR18=0x94CE, DQSOSC=384, MR23=63, INC=400, DEC=267
6818 12:43:53.952445 ==
6819 12:43:53.955515 Dram Type= 6, Freq= 0, CH_1, rank 1
6820 12:43:53.958782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6821 12:43:53.959349 ==
6822 12:43:53.962372 [Gating] SW mode calibration
6823 12:43:53.968519 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6824 12:43:53.975355 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6825 12:43:53.978586 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6826 12:43:53.981780 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6827 12:43:53.984773 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6828 12:43:53.991674 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6829 12:43:53.994963 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6830 12:43:53.998325 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6831 12:43:54.005442 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6832 12:43:54.008462 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6833 12:43:54.011923 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6834 12:43:54.014857 Total UI for P1: 0, mck2ui 16
6835 12:43:54.018235 best dqsien dly found for B0: ( 0, 14, 24)
6836 12:43:54.021748 Total UI for P1: 0, mck2ui 16
6837 12:43:54.024657 best dqsien dly found for B1: ( 0, 14, 24)
6838 12:43:54.028187 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6839 12:43:54.031739 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6840 12:43:54.034955
6841 12:43:54.038086 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6842 12:43:54.041170 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6843 12:43:54.044896 [Gating] SW calibration Done
6844 12:43:54.045471 ==
6845 12:43:54.048347 Dram Type= 6, Freq= 0, CH_1, rank 1
6846 12:43:54.051855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6847 12:43:54.052438 ==
6848 12:43:54.052810 RX Vref Scan: 0
6849 12:43:54.055119
6850 12:43:54.055686 RX Vref 0 -> 0, step: 1
6851 12:43:54.056061
6852 12:43:54.057840 RX Delay -410 -> 252, step: 16
6853 12:43:54.061556 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6854 12:43:54.068218 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6855 12:43:54.071671 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6856 12:43:54.074504 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6857 12:43:54.078458 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6858 12:43:54.084767 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6859 12:43:54.088233 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6860 12:43:54.091432 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6861 12:43:54.094757 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6862 12:43:54.098438 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6863 12:43:54.105023 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6864 12:43:54.107830 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6865 12:43:54.111827 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6866 12:43:54.118314 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6867 12:43:54.121164 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6868 12:43:54.124497 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6869 12:43:54.124968 ==
6870 12:43:54.128070 Dram Type= 6, Freq= 0, CH_1, rank 1
6871 12:43:54.131453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 12:43:54.134346 ==
6873 12:43:54.134816 DQS Delay:
6874 12:43:54.135184 DQS0 = 35, DQS1 = 43
6875 12:43:54.137893 DQM Delay:
6876 12:43:54.138390 DQM0 = 18, DQM1 = 18
6877 12:43:54.141057 DQ Delay:
6878 12:43:54.144485 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6879 12:43:54.144959 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6880 12:43:54.148286 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6881 12:43:54.151129 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6882 12:43:54.151695
6883 12:43:54.154526
6884 12:43:54.155089 ==
6885 12:43:54.158084 Dram Type= 6, Freq= 0, CH_1, rank 1
6886 12:43:54.161340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 12:43:54.161910 ==
6888 12:43:54.162328
6889 12:43:54.162676
6890 12:43:54.164488 TX Vref Scan disable
6891 12:43:54.164958 == TX Byte 0 ==
6892 12:43:54.167987 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6893 12:43:54.174762 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6894 12:43:54.175332 == TX Byte 1 ==
6895 12:43:54.177983 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6896 12:43:54.184419 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6897 12:43:54.184989 ==
6898 12:43:54.187793 Dram Type= 6, Freq= 0, CH_1, rank 1
6899 12:43:54.190958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6900 12:43:54.191430 ==
6901 12:43:54.191801
6902 12:43:54.192145
6903 12:43:54.194227 TX Vref Scan disable
6904 12:43:54.194694 == TX Byte 0 ==
6905 12:43:54.197795 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6906 12:43:54.204362 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6907 12:43:54.204929 == TX Byte 1 ==
6908 12:43:54.207597 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6909 12:43:54.214245 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6910 12:43:54.214799
6911 12:43:54.215169 [DATLAT]
6912 12:43:54.215515 Freq=400, CH1 RK1
6913 12:43:54.215849
6914 12:43:54.217580 DATLAT Default: 0xe
6915 12:43:54.220470 0, 0xFFFF, sum = 0
6916 12:43:54.220948 1, 0xFFFF, sum = 0
6917 12:43:54.224361 2, 0xFFFF, sum = 0
6918 12:43:54.224937 3, 0xFFFF, sum = 0
6919 12:43:54.227519 4, 0xFFFF, sum = 0
6920 12:43:54.227997 5, 0xFFFF, sum = 0
6921 12:43:54.230404 6, 0xFFFF, sum = 0
6922 12:43:54.230881 7, 0xFFFF, sum = 0
6923 12:43:54.233910 8, 0xFFFF, sum = 0
6924 12:43:54.234411 9, 0xFFFF, sum = 0
6925 12:43:54.237309 10, 0xFFFF, sum = 0
6926 12:43:54.237784 11, 0xFFFF, sum = 0
6927 12:43:54.240803 12, 0xFFFF, sum = 0
6928 12:43:54.241376 13, 0x0, sum = 1
6929 12:43:54.244026 14, 0x0, sum = 2
6930 12:43:54.244501 15, 0x0, sum = 3
6931 12:43:54.247356 16, 0x0, sum = 4
6932 12:43:54.247924 best_step = 14
6933 12:43:54.248299
6934 12:43:54.248644 ==
6935 12:43:54.250852 Dram Type= 6, Freq= 0, CH_1, rank 1
6936 12:43:54.254323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6937 12:43:54.257276 ==
6938 12:43:54.257842 RX Vref Scan: 0
6939 12:43:54.258274
6940 12:43:54.260829 RX Vref 0 -> 0, step: 1
6941 12:43:54.261388
6942 12:43:54.264045 RX Delay -327 -> 252, step: 8
6943 12:43:54.270422 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6944 12:43:54.274069 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6945 12:43:54.277099 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6946 12:43:54.280293 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6947 12:43:54.287449 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6948 12:43:54.290793 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6949 12:43:54.293872 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6950 12:43:54.297199 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6951 12:43:54.300172 iDelay=217, Bit 8, Center -40 (-271 ~ 192) 464
6952 12:43:54.307228 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6953 12:43:54.310657 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6954 12:43:54.313835 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6955 12:43:54.320650 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6956 12:43:54.323675 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6957 12:43:54.327168 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6958 12:43:54.330089 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6959 12:43:54.330570 ==
6960 12:43:54.333385 Dram Type= 6, Freq= 0, CH_1, rank 1
6961 12:43:54.340359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6962 12:43:54.340935 ==
6963 12:43:54.341481 DQS Delay:
6964 12:43:54.343508 DQS0 = 32, DQS1 = 40
6965 12:43:54.343983 DQM Delay:
6966 12:43:54.347390 DQM0 = 13, DQM1 = 14
6967 12:43:54.347972 DQ Delay:
6968 12:43:54.350273 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
6969 12:43:54.353550 DQ4 =16, DQ5 =24, DQ6 =16, DQ7 =8
6970 12:43:54.356856 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =12
6971 12:43:54.360227 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =24
6972 12:43:54.360808
6973 12:43:54.361179
6974 12:43:54.367046 [DQSOSCAuto] RK1, (LSB)MR18= 0xa64f, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 389 ps
6975 12:43:54.370253 CH1 RK1: MR19=C0C, MR18=A64F
6976 12:43:54.376839 CH1_RK1: MR19=0xC0C, MR18=0xA64F, DQSOSC=389, MR23=63, INC=390, DEC=260
6977 12:43:54.380118 [RxdqsGatingPostProcess] freq 400
6978 12:43:54.383669 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6979 12:43:54.386748 best DQS0 dly(2T, 0.5T) = (0, 10)
6980 12:43:54.390541 best DQS1 dly(2T, 0.5T) = (0, 10)
6981 12:43:54.393743 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6982 12:43:54.396537 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6983 12:43:54.400078 best DQS0 dly(2T, 0.5T) = (0, 10)
6984 12:43:54.403172 best DQS1 dly(2T, 0.5T) = (0, 10)
6985 12:43:54.406775 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6986 12:43:54.410268 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6987 12:43:54.413685 Pre-setting of DQS Precalculation
6988 12:43:54.416553 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6989 12:43:54.426635 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6990 12:43:54.433186 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6991 12:43:54.433766
6992 12:43:54.434175
6993 12:43:54.436661 [Calibration Summary] 800 Mbps
6994 12:43:54.437288 CH 0, Rank 0
6995 12:43:54.439583 SW Impedance : PASS
6996 12:43:54.440112 DUTY Scan : NO K
6997 12:43:54.443104 ZQ Calibration : PASS
6998 12:43:54.446200 Jitter Meter : NO K
6999 12:43:54.446667 CBT Training : PASS
7000 12:43:54.449584 Write leveling : PASS
7001 12:43:54.453086 RX DQS gating : PASS
7002 12:43:54.453732 RX DQ/DQS(RDDQC) : PASS
7003 12:43:54.456136 TX DQ/DQS : PASS
7004 12:43:54.459490 RX DATLAT : PASS
7005 12:43:54.459999 RX DQ/DQS(Engine): PASS
7006 12:43:54.463198 TX OE : NO K
7007 12:43:54.463695 All Pass.
7008 12:43:54.464091
7009 12:43:54.466321 CH 0, Rank 1
7010 12:43:54.466924 SW Impedance : PASS
7011 12:43:54.469753 DUTY Scan : NO K
7012 12:43:54.470248 ZQ Calibration : PASS
7013 12:43:54.472882 Jitter Meter : NO K
7014 12:43:54.475945 CBT Training : PASS
7015 12:43:54.476409 Write leveling : NO K
7016 12:43:54.479345 RX DQS gating : PASS
7017 12:43:54.483065 RX DQ/DQS(RDDQC) : PASS
7018 12:43:54.483631 TX DQ/DQS : PASS
7019 12:43:54.486430 RX DATLAT : PASS
7020 12:43:54.489906 RX DQ/DQS(Engine): PASS
7021 12:43:54.490556 TX OE : NO K
7022 12:43:54.492846 All Pass.
7023 12:43:54.493510
7024 12:43:54.493914 CH 1, Rank 0
7025 12:43:54.496188 SW Impedance : PASS
7026 12:43:54.496812 DUTY Scan : NO K
7027 12:43:54.499709 ZQ Calibration : PASS
7028 12:43:54.502775 Jitter Meter : NO K
7029 12:43:54.503242 CBT Training : PASS
7030 12:43:54.505995 Write leveling : PASS
7031 12:43:54.509275 RX DQS gating : PASS
7032 12:43:54.509841 RX DQ/DQS(RDDQC) : PASS
7033 12:43:54.512688 TX DQ/DQS : PASS
7034 12:43:54.516156 RX DATLAT : PASS
7035 12:43:54.516724 RX DQ/DQS(Engine): PASS
7036 12:43:54.519553 TX OE : NO K
7037 12:43:54.520121 All Pass.
7038 12:43:54.520492
7039 12:43:54.522552 CH 1, Rank 1
7040 12:43:54.523016 SW Impedance : PASS
7041 12:43:54.526103 DUTY Scan : NO K
7042 12:43:54.529368 ZQ Calibration : PASS
7043 12:43:54.529934 Jitter Meter : NO K
7044 12:43:54.532699 CBT Training : PASS
7045 12:43:54.533260 Write leveling : NO K
7046 12:43:54.535942 RX DQS gating : PASS
7047 12:43:54.538998 RX DQ/DQS(RDDQC) : PASS
7048 12:43:54.539462 TX DQ/DQS : PASS
7049 12:43:54.542409 RX DATLAT : PASS
7050 12:43:54.545503 RX DQ/DQS(Engine): PASS
7051 12:43:54.546005 TX OE : NO K
7052 12:43:54.549238 All Pass.
7053 12:43:54.549704
7054 12:43:54.550117 DramC Write-DBI off
7055 12:43:54.552141 PER_BANK_REFRESH: Hybrid Mode
7056 12:43:54.555780 TX_TRACKING: ON
7057 12:43:54.562398 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7058 12:43:54.565800 [FAST_K] Save calibration result to emmc
7059 12:43:54.568843 dramc_set_vcore_voltage set vcore to 725000
7060 12:43:54.572253 Read voltage for 1600, 0
7061 12:43:54.572721 Vio18 = 0
7062 12:43:54.575390 Vcore = 725000
7063 12:43:54.575857 Vdram = 0
7064 12:43:54.576222 Vddq = 0
7065 12:43:54.578460 Vmddr = 0
7066 12:43:54.582077 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7067 12:43:54.588834 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7068 12:43:54.589408 MEM_TYPE=3, freq_sel=13
7069 12:43:54.592042 sv_algorithm_assistance_LP4_3733
7070 12:43:54.598589 ============ PULL DRAM RESETB DOWN ============
7071 12:43:54.602068 ========== PULL DRAM RESETB DOWN end =========
7072 12:43:54.605300 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7073 12:43:54.608469 ===================================
7074 12:43:54.611742 LPDDR4 DRAM CONFIGURATION
7075 12:43:54.614780 ===================================
7076 12:43:54.618442 EX_ROW_EN[0] = 0x0
7077 12:43:54.619018 EX_ROW_EN[1] = 0x0
7078 12:43:54.621855 LP4Y_EN = 0x0
7079 12:43:54.622473 WORK_FSP = 0x1
7080 12:43:54.625300 WL = 0x5
7081 12:43:54.625878 RL = 0x5
7082 12:43:54.628588 BL = 0x2
7083 12:43:54.629162 RPST = 0x0
7084 12:43:54.631832 RD_PRE = 0x0
7085 12:43:54.632404 WR_PRE = 0x1
7086 12:43:54.634998 WR_PST = 0x1
7087 12:43:54.635470 DBI_WR = 0x0
7088 12:43:54.638624 DBI_RD = 0x0
7089 12:43:54.639199 OTF = 0x1
7090 12:43:54.641714 ===================================
7091 12:43:54.644793 ===================================
7092 12:43:54.648214 ANA top config
7093 12:43:54.651645 ===================================
7094 12:43:54.654709 DLL_ASYNC_EN = 0
7095 12:43:54.655185 ALL_SLAVE_EN = 0
7096 12:43:54.658214 NEW_RANK_MODE = 1
7097 12:43:54.661629 DLL_IDLE_MODE = 1
7098 12:43:54.664975 LP45_APHY_COMB_EN = 1
7099 12:43:54.665517 TX_ODT_DIS = 0
7100 12:43:54.668253 NEW_8X_MODE = 1
7101 12:43:54.671403 ===================================
7102 12:43:54.675098 ===================================
7103 12:43:54.678139 data_rate = 3200
7104 12:43:54.681393 CKR = 1
7105 12:43:54.684942 DQ_P2S_RATIO = 8
7106 12:43:54.688280 ===================================
7107 12:43:54.691413 CA_P2S_RATIO = 8
7108 12:43:54.691887 DQ_CA_OPEN = 0
7109 12:43:54.694998 DQ_SEMI_OPEN = 0
7110 12:43:54.697816 CA_SEMI_OPEN = 0
7111 12:43:54.701335 CA_FULL_RATE = 0
7112 12:43:54.704839 DQ_CKDIV4_EN = 0
7113 12:43:54.708199 CA_CKDIV4_EN = 0
7114 12:43:54.708770 CA_PREDIV_EN = 0
7115 12:43:54.711598 PH8_DLY = 12
7116 12:43:54.714540 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7117 12:43:54.718290 DQ_AAMCK_DIV = 4
7118 12:43:54.721544 CA_AAMCK_DIV = 4
7119 12:43:54.724840 CA_ADMCK_DIV = 4
7120 12:43:54.725408 DQ_TRACK_CA_EN = 0
7121 12:43:54.728217 CA_PICK = 1600
7122 12:43:54.731479 CA_MCKIO = 1600
7123 12:43:54.734837 MCKIO_SEMI = 0
7124 12:43:54.738278 PLL_FREQ = 3068
7125 12:43:54.741579 DQ_UI_PI_RATIO = 32
7126 12:43:54.744754 CA_UI_PI_RATIO = 0
7127 12:43:54.748220 ===================================
7128 12:43:54.751417 ===================================
7129 12:43:54.751980 memory_type:LPDDR4
7130 12:43:54.754719 GP_NUM : 10
7131 12:43:54.757803 SRAM_EN : 1
7132 12:43:54.758302 MD32_EN : 0
7133 12:43:54.761420 ===================================
7134 12:43:54.764358 [ANA_INIT] >>>>>>>>>>>>>>
7135 12:43:54.768035 <<<<<< [CONFIGURE PHASE]: ANA_TX
7136 12:43:54.771117 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7137 12:43:54.774693 ===================================
7138 12:43:54.777870 data_rate = 3200,PCW = 0X7600
7139 12:43:54.781329 ===================================
7140 12:43:54.784307 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7141 12:43:54.788002 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7142 12:43:54.794704 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7143 12:43:54.798149 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7144 12:43:54.801161 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7145 12:43:54.804306 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7146 12:43:54.808113 [ANA_INIT] flow start
7147 12:43:54.811418 [ANA_INIT] PLL >>>>>>>>
7148 12:43:54.811984 [ANA_INIT] PLL <<<<<<<<
7149 12:43:54.814458 [ANA_INIT] MIDPI >>>>>>>>
7150 12:43:54.818257 [ANA_INIT] MIDPI <<<<<<<<
7151 12:43:54.821719 [ANA_INIT] DLL >>>>>>>>
7152 12:43:54.822389 [ANA_INIT] DLL <<<<<<<<
7153 12:43:54.824735 [ANA_INIT] flow end
7154 12:43:54.827622 ============ LP4 DIFF to SE enter ============
7155 12:43:54.830968 ============ LP4 DIFF to SE exit ============
7156 12:43:54.834523 [ANA_INIT] <<<<<<<<<<<<<
7157 12:43:54.837706 [Flow] Enable top DCM control >>>>>
7158 12:43:54.841116 [Flow] Enable top DCM control <<<<<
7159 12:43:54.844375 Enable DLL master slave shuffle
7160 12:43:54.851259 ==============================================================
7161 12:43:54.851827 Gating Mode config
7162 12:43:54.857786 ==============================================================
7163 12:43:54.858383 Config description:
7164 12:43:54.867759 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7165 12:43:54.874102 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7166 12:43:54.881208 SELPH_MODE 0: By rank 1: By Phase
7167 12:43:54.884119 ==============================================================
7168 12:43:54.887590 GAT_TRACK_EN = 1
7169 12:43:54.890716 RX_GATING_MODE = 2
7170 12:43:54.894310 RX_GATING_TRACK_MODE = 2
7171 12:43:54.897537 SELPH_MODE = 1
7172 12:43:54.901136 PICG_EARLY_EN = 1
7173 12:43:54.903858 VALID_LAT_VALUE = 1
7174 12:43:54.907615 ==============================================================
7175 12:43:54.910727 Enter into Gating configuration >>>>
7176 12:43:54.914099 Exit from Gating configuration <<<<
7177 12:43:54.917210 Enter into DVFS_PRE_config >>>>>
7178 12:43:54.930800 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7179 12:43:54.934126 Exit from DVFS_PRE_config <<<<<
7180 12:43:54.937235 Enter into PICG configuration >>>>
7181 12:43:54.937705 Exit from PICG configuration <<<<
7182 12:43:54.940923 [RX_INPUT] configuration >>>>>
7183 12:43:54.943713 [RX_INPUT] configuration <<<<<
7184 12:43:54.950512 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7185 12:43:54.954084 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7186 12:43:54.960822 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7187 12:43:54.967550 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7188 12:43:54.973703 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7189 12:43:54.980617 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7190 12:43:54.983836 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7191 12:43:54.986859 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7192 12:43:54.990769 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7193 12:43:54.997012 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7194 12:43:55.000431 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7195 12:43:55.003689 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7196 12:43:55.007271 ===================================
7197 12:43:55.010553 LPDDR4 DRAM CONFIGURATION
7198 12:43:55.013932 ===================================
7199 12:43:55.016907 EX_ROW_EN[0] = 0x0
7200 12:43:55.017379 EX_ROW_EN[1] = 0x0
7201 12:43:55.020860 LP4Y_EN = 0x0
7202 12:43:55.021434 WORK_FSP = 0x1
7203 12:43:55.023568 WL = 0x5
7204 12:43:55.024040 RL = 0x5
7205 12:43:55.026922 BL = 0x2
7206 12:43:55.027476 RPST = 0x0
7207 12:43:55.030836 RD_PRE = 0x0
7208 12:43:55.031408 WR_PRE = 0x1
7209 12:43:55.034090 WR_PST = 0x1
7210 12:43:55.034659 DBI_WR = 0x0
7211 12:43:55.037253 DBI_RD = 0x0
7212 12:43:55.037719 OTF = 0x1
7213 12:43:55.040852 ===================================
7214 12:43:55.043803 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7215 12:43:55.050795 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7216 12:43:55.054106 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7217 12:43:55.057374 ===================================
7218 12:43:55.060605 LPDDR4 DRAM CONFIGURATION
7219 12:43:55.063761 ===================================
7220 12:43:55.064340 EX_ROW_EN[0] = 0x10
7221 12:43:55.066977 EX_ROW_EN[1] = 0x0
7222 12:43:55.070373 LP4Y_EN = 0x0
7223 12:43:55.071007 WORK_FSP = 0x1
7224 12:43:55.073728 WL = 0x5
7225 12:43:55.074250 RL = 0x5
7226 12:43:55.077045 BL = 0x2
7227 12:43:55.077517 RPST = 0x0
7228 12:43:55.080343 RD_PRE = 0x0
7229 12:43:55.080905 WR_PRE = 0x1
7230 12:43:55.083520 WR_PST = 0x1
7231 12:43:55.083995 DBI_WR = 0x0
7232 12:43:55.086636 DBI_RD = 0x0
7233 12:43:55.087107 OTF = 0x1
7234 12:43:55.090034 ===================================
7235 12:43:55.096722 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7236 12:43:55.097284 ==
7237 12:43:55.099836 Dram Type= 6, Freq= 0, CH_0, rank 0
7238 12:43:55.103394 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7239 12:43:55.106619 ==
7240 12:43:55.107083 [Duty_Offset_Calibration]
7241 12:43:55.110298 B0:2 B1:0 CA:1
7242 12:43:55.110924
7243 12:43:55.113246 [DutyScan_Calibration_Flow] k_type=0
7244 12:43:55.121518
7245 12:43:55.122122 ==CLK 0==
7246 12:43:55.124740 Final CLK duty delay cell = -4
7247 12:43:55.128267 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7248 12:43:55.131131 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7249 12:43:55.134737 [-4] AVG Duty = 4922%(X100)
7250 12:43:55.135300
7251 12:43:55.138162 CH0 CLK Duty spec in!! Max-Min= 156%
7252 12:43:55.141494 [DutyScan_Calibration_Flow] ====Done====
7253 12:43:55.142112
7254 12:43:55.144414 [DutyScan_Calibration_Flow] k_type=1
7255 12:43:55.160856
7256 12:43:55.161415 ==DQS 0 ==
7257 12:43:55.164140 Final DQS duty delay cell = 0
7258 12:43:55.167487 [0] MAX Duty = 5249%(X100), DQS PI = 32
7259 12:43:55.170810 [0] MIN Duty = 4969%(X100), DQS PI = 0
7260 12:43:55.174195 [0] AVG Duty = 5109%(X100)
7261 12:43:55.174754
7262 12:43:55.175124 ==DQS 1 ==
7263 12:43:55.177712 Final DQS duty delay cell = -4
7264 12:43:55.180870 [-4] MAX Duty = 5125%(X100), DQS PI = 46
7265 12:43:55.184472 [-4] MIN Duty = 4844%(X100), DQS PI = 4
7266 12:43:55.187500 [-4] AVG Duty = 4984%(X100)
7267 12:43:55.187984
7268 12:43:55.190619 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7269 12:43:55.191117
7270 12:43:55.193770 CH0 DQS 1 Duty spec in!! Max-Min= 281%
7271 12:43:55.197094 [DutyScan_Calibration_Flow] ====Done====
7272 12:43:55.197715
7273 12:43:55.200327 [DutyScan_Calibration_Flow] k_type=3
7274 12:43:55.218237
7275 12:43:55.218806 ==DQM 0 ==
7276 12:43:55.221500 Final DQM duty delay cell = 0
7277 12:43:55.224815 [0] MAX Duty = 5093%(X100), DQS PI = 26
7278 12:43:55.228490 [0] MIN Duty = 4844%(X100), DQS PI = 2
7279 12:43:55.229054 [0] AVG Duty = 4968%(X100)
7280 12:43:55.231798
7281 12:43:55.232363 ==DQM 1 ==
7282 12:43:55.235091 Final DQM duty delay cell = 0
7283 12:43:55.238432 [0] MAX Duty = 5249%(X100), DQS PI = 30
7284 12:43:55.241792 [0] MIN Duty = 5000%(X100), DQS PI = 20
7285 12:43:55.245278 [0] AVG Duty = 5124%(X100)
7286 12:43:55.245848
7287 12:43:55.247821 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7288 12:43:55.248287
7289 12:43:55.251332 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7290 12:43:55.254817 [DutyScan_Calibration_Flow] ====Done====
7291 12:43:55.255387
7292 12:43:55.258088 [DutyScan_Calibration_Flow] k_type=2
7293 12:43:55.275642
7294 12:43:55.276223 ==DQ 0 ==
7295 12:43:55.278667 Final DQ duty delay cell = 0
7296 12:43:55.281995 [0] MAX Duty = 5156%(X100), DQS PI = 36
7297 12:43:55.285365 [0] MIN Duty = 5000%(X100), DQS PI = 0
7298 12:43:55.285933 [0] AVG Duty = 5078%(X100)
7299 12:43:55.286359
7300 12:43:55.288461 ==DQ 1 ==
7301 12:43:55.291809 Final DQ duty delay cell = 0
7302 12:43:55.295423 [0] MAX Duty = 4969%(X100), DQS PI = 42
7303 12:43:55.298799 [0] MIN Duty = 4875%(X100), DQS PI = 10
7304 12:43:55.299273 [0] AVG Duty = 4922%(X100)
7305 12:43:55.299657
7306 12:43:55.302002 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7307 12:43:55.305105
7308 12:43:55.305559 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7309 12:43:55.311848 [DutyScan_Calibration_Flow] ====Done====
7310 12:43:55.312306 ==
7311 12:43:55.315262 Dram Type= 6, Freq= 0, CH_1, rank 0
7312 12:43:55.318341 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7313 12:43:55.318799 ==
7314 12:43:55.321668 [Duty_Offset_Calibration]
7315 12:43:55.322245 B0:0 B1:-1 CA:2
7316 12:43:55.322611
7317 12:43:55.325363 [DutyScan_Calibration_Flow] k_type=0
7318 12:43:55.335411
7319 12:43:55.335961 ==CLK 0==
7320 12:43:55.338579 Final CLK duty delay cell = 0
7321 12:43:55.342149 [0] MAX Duty = 5156%(X100), DQS PI = 10
7322 12:43:55.345559 [0] MIN Duty = 4906%(X100), DQS PI = 44
7323 12:43:55.346160 [0] AVG Duty = 5031%(X100)
7324 12:43:55.349022
7325 12:43:55.352198 CH1 CLK Duty spec in!! Max-Min= 250%
7326 12:43:55.355374 [DutyScan_Calibration_Flow] ====Done====
7327 12:43:55.355830
7328 12:43:55.358566 [DutyScan_Calibration_Flow] k_type=1
7329 12:43:55.375368
7330 12:43:55.375921 ==DQS 0 ==
7331 12:43:55.378435 Final DQS duty delay cell = 0
7332 12:43:55.382305 [0] MAX Duty = 5093%(X100), DQS PI = 24
7333 12:43:55.385159 [0] MIN Duty = 5000%(X100), DQS PI = 0
7334 12:43:55.385715 [0] AVG Duty = 5046%(X100)
7335 12:43:55.388501
7336 12:43:55.389052 ==DQS 1 ==
7337 12:43:55.391906 Final DQS duty delay cell = 0
7338 12:43:55.395272 [0] MAX Duty = 5156%(X100), DQS PI = 0
7339 12:43:55.398305 [0] MIN Duty = 4844%(X100), DQS PI = 32
7340 12:43:55.398839 [0] AVG Duty = 5000%(X100)
7341 12:43:55.401889
7342 12:43:55.405255 CH1 DQS 0 Duty spec in!! Max-Min= 93%
7343 12:43:55.405709
7344 12:43:55.408490 CH1 DQS 1 Duty spec in!! Max-Min= 312%
7345 12:43:55.411950 [DutyScan_Calibration_Flow] ====Done====
7346 12:43:55.412571
7347 12:43:55.414906 [DutyScan_Calibration_Flow] k_type=3
7348 12:43:55.432736
7349 12:43:55.433285 ==DQM 0 ==
7350 12:43:55.435996 Final DQM duty delay cell = 4
7351 12:43:55.439327 [4] MAX Duty = 5125%(X100), DQS PI = 8
7352 12:43:55.442798 [4] MIN Duty = 4969%(X100), DQS PI = 46
7353 12:43:55.443362 [4] AVG Duty = 5047%(X100)
7354 12:43:55.446011
7355 12:43:55.446559 ==DQM 1 ==
7356 12:43:55.449334 Final DQM duty delay cell = 0
7357 12:43:55.452992 [0] MAX Duty = 5281%(X100), DQS PI = 58
7358 12:43:55.456127 [0] MIN Duty = 4876%(X100), DQS PI = 34
7359 12:43:55.456583 [0] AVG Duty = 5078%(X100)
7360 12:43:55.459715
7361 12:43:55.462437 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7362 12:43:55.462894
7363 12:43:55.466234 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7364 12:43:55.469328 [DutyScan_Calibration_Flow] ====Done====
7365 12:43:55.469889
7366 12:43:55.472453 [DutyScan_Calibration_Flow] k_type=2
7367 12:43:55.489607
7368 12:43:55.490216 ==DQ 0 ==
7369 12:43:55.492796 Final DQ duty delay cell = 0
7370 12:43:55.495984 [0] MAX Duty = 5093%(X100), DQS PI = 20
7371 12:43:55.499474 [0] MIN Duty = 4969%(X100), DQS PI = 46
7372 12:43:55.500132 [0] AVG Duty = 5031%(X100)
7373 12:43:55.502726
7374 12:43:55.503237 ==DQ 1 ==
7375 12:43:55.506051 Final DQ duty delay cell = 0
7376 12:43:55.509518 [0] MAX Duty = 5062%(X100), DQS PI = 0
7377 12:43:55.512999 [0] MIN Duty = 4813%(X100), DQS PI = 34
7378 12:43:55.513569 [0] AVG Duty = 4937%(X100)
7379 12:43:55.513971
7380 12:43:55.516209 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7381 12:43:55.519723
7382 12:43:55.522908 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7383 12:43:55.526264 [DutyScan_Calibration_Flow] ====Done====
7384 12:43:55.529256 nWR fixed to 30
7385 12:43:55.529724 [ModeRegInit_LP4] CH0 RK0
7386 12:43:55.532648 [ModeRegInit_LP4] CH0 RK1
7387 12:43:55.535808 [ModeRegInit_LP4] CH1 RK0
7388 12:43:55.539226 [ModeRegInit_LP4] CH1 RK1
7389 12:43:55.539721 match AC timing 5
7390 12:43:55.542328 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7391 12:43:55.549099 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7392 12:43:55.552387 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7393 12:43:55.559500 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7394 12:43:55.562640 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7395 12:43:55.563105 [MiockJmeterHQA]
7396 12:43:55.563469
7397 12:43:55.566150 [DramcMiockJmeter] u1RxGatingPI = 0
7398 12:43:55.569440 0 : 4252, 4027
7399 12:43:55.570059 4 : 4253, 4026
7400 12:43:55.572761 8 : 4253, 4026
7401 12:43:55.573325 12 : 4252, 4027
7402 12:43:55.573700 16 : 4252, 4027
7403 12:43:55.576280 20 : 4252, 4027
7404 12:43:55.576854 24 : 4254, 4029
7405 12:43:55.579037 28 : 4363, 4137
7406 12:43:55.579507 32 : 4253, 4027
7407 12:43:55.582495 36 : 4252, 4026
7408 12:43:55.582963 40 : 4250, 4027
7409 12:43:55.583332 44 : 4255, 4029
7410 12:43:55.585855 48 : 4250, 4027
7411 12:43:55.586431 52 : 4363, 4138
7412 12:43:55.589046 56 : 4360, 4137
7413 12:43:55.589613 60 : 4250, 4027
7414 12:43:55.592436 64 : 4250, 4027
7415 12:43:55.593008 68 : 4250, 4026
7416 12:43:55.595704 72 : 4250, 4027
7417 12:43:55.596271 76 : 4252, 4029
7418 12:43:55.596646 80 : 4361, 4137
7419 12:43:55.599010 84 : 4250, 4027
7420 12:43:55.599483 88 : 4250, 3282
7421 12:43:55.602354 92 : 4250, 0
7422 12:43:55.602828 96 : 4361, 0
7423 12:43:55.603202 100 : 4250, 0
7424 12:43:55.605605 104 : 4360, 0
7425 12:43:55.606118 108 : 4250, 0
7426 12:43:55.608955 112 : 4250, 0
7427 12:43:55.609522 116 : 4250, 0
7428 12:43:55.609897 120 : 4252, 0
7429 12:43:55.612360 124 : 4250, 0
7430 12:43:55.612931 128 : 4360, 0
7431 12:43:55.615420 132 : 4250, 0
7432 12:43:55.615892 136 : 4250, 0
7433 12:43:55.616263 140 : 4250, 0
7434 12:43:55.619014 144 : 4250, 0
7435 12:43:55.619594 148 : 4250, 0
7436 12:43:55.622483 152 : 4361, 0
7437 12:43:55.623059 156 : 4360, 0
7438 12:43:55.623438 160 : 4250, 0
7439 12:43:55.625613 164 : 4250, 0
7440 12:43:55.626253 168 : 4252, 0
7441 12:43:55.626638 172 : 4360, 0
7442 12:43:55.628811 176 : 4252, 0
7443 12:43:55.629382 180 : 4250, 0
7444 12:43:55.632039 184 : 4250, 0
7445 12:43:55.632513 188 : 4250, 0
7446 12:43:55.632891 192 : 4360, 0
7447 12:43:55.635491 196 : 4250, 0
7448 12:43:55.636127 200 : 4252, 1
7449 12:43:55.638419 204 : 4250, 2315
7450 12:43:55.638891 208 : 4250, 4027
7451 12:43:55.641990 212 : 4360, 4138
7452 12:43:55.642596 216 : 4250, 4027
7453 12:43:55.645422 220 : 4250, 4026
7454 12:43:55.646087 224 : 4360, 4138
7455 12:43:55.646482 228 : 4252, 4029
7456 12:43:55.648585 232 : 4253, 4029
7457 12:43:55.649079 236 : 4363, 4140
7458 12:43:55.652184 240 : 4250, 4027
7459 12:43:55.652664 244 : 4250, 4027
7460 12:43:55.655104 248 : 4250, 4026
7461 12:43:55.655585 252 : 4250, 4027
7462 12:43:55.658592 256 : 4250, 4026
7463 12:43:55.659073 260 : 4252, 4029
7464 12:43:55.661860 264 : 4363, 4140
7465 12:43:55.662382 268 : 4249, 4027
7466 12:43:55.665440 272 : 4250, 4027
7467 12:43:55.666078 276 : 4361, 4137
7468 12:43:55.668979 280 : 4252, 4029
7469 12:43:55.669559 284 : 4250, 4027
7470 12:43:55.669995 288 : 4363, 4140
7471 12:43:55.672217 292 : 4250, 4026
7472 12:43:55.672732 296 : 4250, 4027
7473 12:43:55.675100 300 : 4250, 4027
7474 12:43:55.675580 304 : 4253, 4029
7475 12:43:55.678411 308 : 4250, 4026
7476 12:43:55.678916 312 : 4250, 3928
7477 12:43:55.682140 316 : 4360, 2068
7478 12:43:55.682721
7479 12:43:55.683098 MIOCK jitter meter ch=0
7480 12:43:55.685040
7481 12:43:55.685513 1T = (316-92) = 224 dly cells
7482 12:43:55.692085 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7483 12:43:55.692669 ==
7484 12:43:55.695562 Dram Type= 6, Freq= 0, CH_0, rank 0
7485 12:43:55.698476 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7486 12:43:55.699063 ==
7487 12:43:55.705239 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7488 12:43:55.708944 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7489 12:43:55.715293 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7490 12:43:55.718454 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7491 12:43:55.728805 [CA 0] Center 43 (13~73) winsize 61
7492 12:43:55.731947 [CA 1] Center 43 (13~73) winsize 61
7493 12:43:55.735187 [CA 2] Center 38 (8~68) winsize 61
7494 12:43:55.738347 [CA 3] Center 37 (8~67) winsize 60
7495 12:43:55.741711 [CA 4] Center 36 (6~66) winsize 61
7496 12:43:55.745103 [CA 5] Center 35 (5~65) winsize 61
7497 12:43:55.745688
7498 12:43:55.748300 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7499 12:43:55.748800
7500 12:43:55.751761 [CATrainingPosCal] consider 1 rank data
7501 12:43:55.755152 u2DelayCellTimex100 = 290/100 ps
7502 12:43:55.758082 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7503 12:43:55.764975 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7504 12:43:55.768606 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7505 12:43:55.772046 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7506 12:43:55.775235 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7507 12:43:55.778481 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7508 12:43:55.779131
7509 12:43:55.781546 CA PerBit enable=1, Macro0, CA PI delay=35
7510 12:43:55.782050
7511 12:43:55.784870 [CBTSetCACLKResult] CA Dly = 35
7512 12:43:55.788335 CS Dly: 9 (0~40)
7513 12:43:55.791733 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7514 12:43:55.794757 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7515 12:43:55.795263 ==
7516 12:43:55.798592 Dram Type= 6, Freq= 0, CH_0, rank 1
7517 12:43:55.801790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7518 12:43:55.802325 ==
7519 12:43:55.808708 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7520 12:43:55.811519 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7521 12:43:55.818487 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7522 12:43:55.821237 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7523 12:43:55.831787 [CA 0] Center 43 (13~73) winsize 61
7524 12:43:55.835204 [CA 1] Center 43 (13~73) winsize 61
7525 12:43:55.838520 [CA 2] Center 37 (8~67) winsize 60
7526 12:43:55.841450 [CA 3] Center 37 (8~67) winsize 60
7527 12:43:55.845044 [CA 4] Center 36 (6~66) winsize 61
7528 12:43:55.848481 [CA 5] Center 36 (6~66) winsize 61
7529 12:43:55.849112
7530 12:43:55.852204 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7531 12:43:55.852774
7532 12:43:55.855049 [CATrainingPosCal] consider 2 rank data
7533 12:43:55.858272 u2DelayCellTimex100 = 290/100 ps
7534 12:43:55.861683 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7535 12:43:55.868263 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7536 12:43:55.871647 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7537 12:43:55.874934 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7538 12:43:55.878392 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7539 12:43:55.881377 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7540 12:43:55.881857
7541 12:43:55.885105 CA PerBit enable=1, Macro0, CA PI delay=35
7542 12:43:55.885686
7543 12:43:55.887835 [CBTSetCACLKResult] CA Dly = 35
7544 12:43:55.891311 CS Dly: 10 (0~43)
7545 12:43:55.894688 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7546 12:43:55.898294 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7547 12:43:55.898874
7548 12:43:55.901527 ----->DramcWriteLeveling(PI) begin...
7549 12:43:55.902398 ==
7550 12:43:55.904726 Dram Type= 6, Freq= 0, CH_0, rank 0
7551 12:43:55.911073 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7552 12:43:55.911557 ==
7553 12:43:55.914280 Write leveling (Byte 0): 34 => 34
7554 12:43:55.914754 Write leveling (Byte 1): 30 => 30
7555 12:43:55.917764 DramcWriteLeveling(PI) end<-----
7556 12:43:55.918306
7557 12:43:55.918681 ==
7558 12:43:55.921587 Dram Type= 6, Freq= 0, CH_0, rank 0
7559 12:43:55.927706 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7560 12:43:55.928296 ==
7561 12:43:55.931329 [Gating] SW mode calibration
7562 12:43:55.938119 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7563 12:43:55.941471 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7564 12:43:55.947858 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7565 12:43:55.951440 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 12:43:55.954615 1 4 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7567 12:43:55.961178 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7568 12:43:55.964751 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7569 12:43:55.968020 1 4 20 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
7570 12:43:55.974556 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7571 12:43:55.977687 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7572 12:43:55.981301 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7573 12:43:55.984715 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7574 12:43:55.991344 1 5 8 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
7575 12:43:55.994777 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7576 12:43:55.997793 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7577 12:43:56.004493 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
7578 12:43:56.007590 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7579 12:43:56.011261 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 12:43:56.017881 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 12:43:56.021245 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7582 12:43:56.024657 1 6 8 | B1->B0 | 2323 3c3c | 0 1 | (0 0) (0 0)
7583 12:43:56.031027 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7584 12:43:56.034588 1 6 16 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
7585 12:43:56.037985 1 6 20 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
7586 12:43:56.044627 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7587 12:43:56.047460 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7588 12:43:56.050965 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7589 12:43:56.057438 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7590 12:43:56.060767 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7591 12:43:56.064306 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7592 12:43:56.070817 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7593 12:43:56.074038 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7594 12:43:56.077590 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 12:43:56.083680 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 12:43:56.087208 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 12:43:56.090668 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 12:43:56.096981 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 12:43:56.100372 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 12:43:56.103676 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 12:43:56.110574 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 12:43:56.113780 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 12:43:56.117185 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 12:43:56.123776 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 12:43:56.126977 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 12:43:56.130780 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7607 12:43:56.137291 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7608 12:43:56.140644 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7609 12:43:56.143526 Total UI for P1: 0, mck2ui 16
7610 12:43:56.147062 best dqsien dly found for B0: ( 1, 9, 10)
7611 12:43:56.150527 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7612 12:43:56.153598 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 12:43:56.157274 Total UI for P1: 0, mck2ui 16
7614 12:43:56.160476 best dqsien dly found for B1: ( 1, 9, 20)
7615 12:43:56.163717 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7616 12:43:56.166927 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7617 12:43:56.170355
7618 12:43:56.173841 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7619 12:43:56.177216 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7620 12:43:56.180185 [Gating] SW calibration Done
7621 12:43:56.180671 ==
7622 12:43:56.183598 Dram Type= 6, Freq= 0, CH_0, rank 0
7623 12:43:56.186761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7624 12:43:56.187338 ==
7625 12:43:56.189993 RX Vref Scan: 0
7626 12:43:56.190477
7627 12:43:56.190959 RX Vref 0 -> 0, step: 1
7628 12:43:56.191413
7629 12:43:56.193591 RX Delay 0 -> 252, step: 8
7630 12:43:56.196936 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7631 12:43:56.200227 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7632 12:43:56.206831 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7633 12:43:56.209922 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7634 12:43:56.213832 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7635 12:43:56.216803 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7636 12:43:56.220139 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7637 12:43:56.223508 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7638 12:43:56.230333 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7639 12:43:56.233700 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7640 12:43:56.236691 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7641 12:43:56.240212 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7642 12:43:56.247177 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7643 12:43:56.250051 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7644 12:43:56.253243 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7645 12:43:56.257109 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7646 12:43:56.257698 ==
7647 12:43:56.260439 Dram Type= 6, Freq= 0, CH_0, rank 0
7648 12:43:56.263329 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7649 12:43:56.267120 ==
7650 12:43:56.267699 DQS Delay:
7651 12:43:56.268189 DQS0 = 0, DQS1 = 0
7652 12:43:56.270107 DQM Delay:
7653 12:43:56.270585 DQM0 = 137, DQM1 = 127
7654 12:43:56.273540 DQ Delay:
7655 12:43:56.276451 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7656 12:43:56.279810 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7657 12:43:56.283107 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7658 12:43:56.286617 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7659 12:43:56.287193
7660 12:43:56.287685
7661 12:43:56.288139 ==
7662 12:43:56.290139 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 12:43:56.293821 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 12:43:56.294463 ==
7665 12:43:56.294958
7666 12:43:56.295413
7667 12:43:56.296468 TX Vref Scan disable
7668 12:43:56.299959 == TX Byte 0 ==
7669 12:43:56.303321 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7670 12:43:56.306691 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7671 12:43:56.309718 == TX Byte 1 ==
7672 12:43:56.313518 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7673 12:43:56.316567 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7674 12:43:56.317150 ==
7675 12:43:56.320016 Dram Type= 6, Freq= 0, CH_0, rank 0
7676 12:43:56.326667 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7677 12:43:56.327245 ==
7678 12:43:56.338475
7679 12:43:56.341342 TX Vref early break, caculate TX vref
7680 12:43:56.344545 TX Vref=16, minBit 5, minWin=22, winSum=376
7681 12:43:56.348195 TX Vref=18, minBit 7, minWin=23, winSum=390
7682 12:43:56.351597 TX Vref=20, minBit 12, minWin=23, winSum=396
7683 12:43:56.354641 TX Vref=22, minBit 4, minWin=24, winSum=404
7684 12:43:56.358514 TX Vref=24, minBit 1, minWin=25, winSum=417
7685 12:43:56.364590 TX Vref=26, minBit 12, minWin=25, winSum=427
7686 12:43:56.367959 TX Vref=28, minBit 0, minWin=26, winSum=432
7687 12:43:56.371207 TX Vref=30, minBit 0, minWin=26, winSum=427
7688 12:43:56.374685 TX Vref=32, minBit 1, minWin=25, winSum=411
7689 12:43:56.378170 TX Vref=34, minBit 0, minWin=24, winSum=402
7690 12:43:56.384623 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 28
7691 12:43:56.385222
7692 12:43:56.387798 Final TX Range 0 Vref 28
7693 12:43:56.388381
7694 12:43:56.388869 ==
7695 12:43:56.391061 Dram Type= 6, Freq= 0, CH_0, rank 0
7696 12:43:56.394883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7697 12:43:56.395469 ==
7698 12:43:56.395958
7699 12:43:56.396410
7700 12:43:56.397611 TX Vref Scan disable
7701 12:43:56.404513 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7702 12:43:56.405015 == TX Byte 0 ==
7703 12:43:56.407906 u2DelayCellOfst[0]=13 cells (4 PI)
7704 12:43:56.411164 u2DelayCellOfst[1]=16 cells (5 PI)
7705 12:43:56.414262 u2DelayCellOfst[2]=13 cells (4 PI)
7706 12:43:56.417834 u2DelayCellOfst[3]=13 cells (4 PI)
7707 12:43:56.420844 u2DelayCellOfst[4]=10 cells (3 PI)
7708 12:43:56.424071 u2DelayCellOfst[5]=0 cells (0 PI)
7709 12:43:56.427551 u2DelayCellOfst[6]=16 cells (5 PI)
7710 12:43:56.430677 u2DelayCellOfst[7]=16 cells (5 PI)
7711 12:43:56.434576 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7712 12:43:56.437330 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7713 12:43:56.440561 == TX Byte 1 ==
7714 12:43:56.444251 u2DelayCellOfst[8]=0 cells (0 PI)
7715 12:43:56.447338 u2DelayCellOfst[9]=0 cells (0 PI)
7716 12:43:56.447827 u2DelayCellOfst[10]=10 cells (3 PI)
7717 12:43:56.450646 u2DelayCellOfst[11]=3 cells (1 PI)
7718 12:43:56.454116 u2DelayCellOfst[12]=10 cells (3 PI)
7719 12:43:56.457342 u2DelayCellOfst[13]=10 cells (3 PI)
7720 12:43:56.460381 u2DelayCellOfst[14]=16 cells (5 PI)
7721 12:43:56.463815 u2DelayCellOfst[15]=10 cells (3 PI)
7722 12:43:56.470881 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7723 12:43:56.474155 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7724 12:43:56.474726 DramC Write-DBI on
7725 12:43:56.475108 ==
7726 12:43:56.477182 Dram Type= 6, Freq= 0, CH_0, rank 0
7727 12:43:56.484079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7728 12:43:56.484645 ==
7729 12:43:56.485024
7730 12:43:56.485370
7731 12:43:56.485696 TX Vref Scan disable
7732 12:43:56.487718 == TX Byte 0 ==
7733 12:43:56.491084 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7734 12:43:56.494818 == TX Byte 1 ==
7735 12:43:56.498368 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7736 12:43:56.498972 DramC Write-DBI off
7737 12:43:56.501279
7738 12:43:56.501797 [DATLAT]
7739 12:43:56.502221 Freq=1600, CH0 RK0
7740 12:43:56.502805
7741 12:43:56.504595 DATLAT Default: 0xf
7742 12:43:56.505115 0, 0xFFFF, sum = 0
7743 12:43:56.508225 1, 0xFFFF, sum = 0
7744 12:43:56.509074 2, 0xFFFF, sum = 0
7745 12:43:56.511349 3, 0xFFFF, sum = 0
7746 12:43:56.514240 4, 0xFFFF, sum = 0
7747 12:43:56.514720 5, 0xFFFF, sum = 0
7748 12:43:56.517751 6, 0xFFFF, sum = 0
7749 12:43:56.518287 7, 0xFFFF, sum = 0
7750 12:43:56.521085 8, 0xFFFF, sum = 0
7751 12:43:56.521567 9, 0xFFFF, sum = 0
7752 12:43:56.524468 10, 0xFFFF, sum = 0
7753 12:43:56.524946 11, 0xFFFF, sum = 0
7754 12:43:56.527562 12, 0xFFFF, sum = 0
7755 12:43:56.528053 13, 0xFFFF, sum = 0
7756 12:43:56.530828 14, 0x0, sum = 1
7757 12:43:56.531304 15, 0x0, sum = 2
7758 12:43:56.534288 16, 0x0, sum = 3
7759 12:43:56.534764 17, 0x0, sum = 4
7760 12:43:56.537658 best_step = 15
7761 12:43:56.538181
7762 12:43:56.538557 ==
7763 12:43:56.540982 Dram Type= 6, Freq= 0, CH_0, rank 0
7764 12:43:56.544386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7765 12:43:56.544860 ==
7766 12:43:56.545234 RX Vref Scan: 1
7767 12:43:56.547458
7768 12:43:56.547928 Set Vref Range= 24 -> 127
7769 12:43:56.548296
7770 12:43:56.550792 RX Vref 24 -> 127, step: 1
7771 12:43:56.551256
7772 12:43:56.554419 RX Delay 19 -> 252, step: 4
7773 12:43:56.554883
7774 12:43:56.557651 Set Vref, RX VrefLevel [Byte0]: 24
7775 12:43:56.560995 [Byte1]: 24
7776 12:43:56.561565
7777 12:43:56.564364 Set Vref, RX VrefLevel [Byte0]: 25
7778 12:43:56.567678 [Byte1]: 25
7779 12:43:56.568242
7780 12:43:56.570990 Set Vref, RX VrefLevel [Byte0]: 26
7781 12:43:56.574395 [Byte1]: 26
7782 12:43:56.578260
7783 12:43:56.578825 Set Vref, RX VrefLevel [Byte0]: 27
7784 12:43:56.581245 [Byte1]: 27
7785 12:43:56.586150
7786 12:43:56.586715 Set Vref, RX VrefLevel [Byte0]: 28
7787 12:43:56.592398 [Byte1]: 28
7788 12:43:56.592992
7789 12:43:56.595281 Set Vref, RX VrefLevel [Byte0]: 29
7790 12:43:56.598851 [Byte1]: 29
7791 12:43:56.599427
7792 12:43:56.602303 Set Vref, RX VrefLevel [Byte0]: 30
7793 12:43:56.605564 [Byte1]: 30
7794 12:43:56.606093
7795 12:43:56.608674 Set Vref, RX VrefLevel [Byte0]: 31
7796 12:43:56.612049 [Byte1]: 31
7797 12:43:56.616448
7798 12:43:56.617018 Set Vref, RX VrefLevel [Byte0]: 32
7799 12:43:56.619430 [Byte1]: 32
7800 12:43:56.623344
7801 12:43:56.623809 Set Vref, RX VrefLevel [Byte0]: 33
7802 12:43:56.626797 [Byte1]: 33
7803 12:43:56.631158
7804 12:43:56.631727 Set Vref, RX VrefLevel [Byte0]: 34
7805 12:43:56.634461 [Byte1]: 34
7806 12:43:56.638522
7807 12:43:56.638988 Set Vref, RX VrefLevel [Byte0]: 35
7808 12:43:56.642185 [Byte1]: 35
7809 12:43:56.646404
7810 12:43:56.646989 Set Vref, RX VrefLevel [Byte0]: 36
7811 12:43:56.649496 [Byte1]: 36
7812 12:43:56.653717
7813 12:43:56.654229 Set Vref, RX VrefLevel [Byte0]: 37
7814 12:43:56.657561 [Byte1]: 37
7815 12:43:56.661250
7816 12:43:56.661715 Set Vref, RX VrefLevel [Byte0]: 38
7817 12:43:56.664734 [Byte1]: 38
7818 12:43:56.669090
7819 12:43:56.669657 Set Vref, RX VrefLevel [Byte0]: 39
7820 12:43:56.672389 [Byte1]: 39
7821 12:43:56.676547
7822 12:43:56.677117 Set Vref, RX VrefLevel [Byte0]: 40
7823 12:43:56.679982 [Byte1]: 40
7824 12:43:56.684390
7825 12:43:56.685000 Set Vref, RX VrefLevel [Byte0]: 41
7826 12:43:56.687275 [Byte1]: 41
7827 12:43:56.691676
7828 12:43:56.692238 Set Vref, RX VrefLevel [Byte0]: 42
7829 12:43:56.694925 [Byte1]: 42
7830 12:43:56.699321
7831 12:43:56.699904 Set Vref, RX VrefLevel [Byte0]: 43
7832 12:43:56.702690 [Byte1]: 43
7833 12:43:56.707022
7834 12:43:56.707596 Set Vref, RX VrefLevel [Byte0]: 44
7835 12:43:56.709897 [Byte1]: 44
7836 12:43:56.714117
7837 12:43:56.714590 Set Vref, RX VrefLevel [Byte0]: 45
7838 12:43:56.717621 [Byte1]: 45
7839 12:43:56.722382
7840 12:43:56.722962 Set Vref, RX VrefLevel [Byte0]: 46
7841 12:43:56.725831 [Byte1]: 46
7842 12:43:56.729615
7843 12:43:56.730242 Set Vref, RX VrefLevel [Byte0]: 47
7844 12:43:56.732955 [Byte1]: 47
7845 12:43:56.737477
7846 12:43:56.738109 Set Vref, RX VrefLevel [Byte0]: 48
7847 12:43:56.740404 [Byte1]: 48
7848 12:43:56.744618
7849 12:43:56.745258 Set Vref, RX VrefLevel [Byte0]: 49
7850 12:43:56.748004 [Byte1]: 49
7851 12:43:56.752550
7852 12:43:56.753138 Set Vref, RX VrefLevel [Byte0]: 50
7853 12:43:56.755437 [Byte1]: 50
7854 12:43:56.759824
7855 12:43:56.760297 Set Vref, RX VrefLevel [Byte0]: 51
7856 12:43:56.762941 [Byte1]: 51
7857 12:43:56.767312
7858 12:43:56.767889 Set Vref, RX VrefLevel [Byte0]: 52
7859 12:43:56.770590 [Byte1]: 52
7860 12:43:56.774966
7861 12:43:56.775596 Set Vref, RX VrefLevel [Byte0]: 53
7862 12:43:56.778347 [Byte1]: 53
7863 12:43:56.782794
7864 12:43:56.783371 Set Vref, RX VrefLevel [Byte0]: 54
7865 12:43:56.786300 [Byte1]: 54
7866 12:43:56.790071
7867 12:43:56.790643 Set Vref, RX VrefLevel [Byte0]: 55
7868 12:43:56.793621 [Byte1]: 55
7869 12:43:56.797912
7870 12:43:56.798536 Set Vref, RX VrefLevel [Byte0]: 56
7871 12:43:56.800987 [Byte1]: 56
7872 12:43:56.805248
7873 12:43:56.805824 Set Vref, RX VrefLevel [Byte0]: 57
7874 12:43:56.808432 [Byte1]: 57
7875 12:43:56.813203
7876 12:43:56.813784 Set Vref, RX VrefLevel [Byte0]: 58
7877 12:43:56.816060 [Byte1]: 58
7878 12:43:56.820561
7879 12:43:56.821188 Set Vref, RX VrefLevel [Byte0]: 59
7880 12:43:56.823977 [Byte1]: 59
7881 12:43:56.828324
7882 12:43:56.828900 Set Vref, RX VrefLevel [Byte0]: 60
7883 12:43:56.831635 [Byte1]: 60
7884 12:43:56.835891
7885 12:43:56.836471 Set Vref, RX VrefLevel [Byte0]: 61
7886 12:43:56.838761 [Byte1]: 61
7887 12:43:56.843119
7888 12:43:56.843887 Set Vref, RX VrefLevel [Byte0]: 62
7889 12:43:56.846646 [Byte1]: 62
7890 12:43:56.850409
7891 12:43:56.850879 Set Vref, RX VrefLevel [Byte0]: 63
7892 12:43:56.854137 [Byte1]: 63
7893 12:43:56.858434
7894 12:43:56.858907 Set Vref, RX VrefLevel [Byte0]: 64
7895 12:43:56.861629 [Byte1]: 64
7896 12:43:56.865844
7897 12:43:56.866470 Set Vref, RX VrefLevel [Byte0]: 65
7898 12:43:56.868965 [Byte1]: 65
7899 12:43:56.873590
7900 12:43:56.874228 Set Vref, RX VrefLevel [Byte0]: 66
7901 12:43:56.876984 [Byte1]: 66
7902 12:43:56.881515
7903 12:43:56.882130 Set Vref, RX VrefLevel [Byte0]: 67
7904 12:43:56.884383 [Byte1]: 67
7905 12:43:56.888563
7906 12:43:56.889145 Set Vref, RX VrefLevel [Byte0]: 68
7907 12:43:56.891831 [Byte1]: 68
7908 12:43:56.896478
7909 12:43:56.897200 Set Vref, RX VrefLevel [Byte0]: 69
7910 12:43:56.899136 [Byte1]: 69
7911 12:43:56.903646
7912 12:43:56.904229 Set Vref, RX VrefLevel [Byte0]: 70
7913 12:43:56.906850 [Byte1]: 70
7914 12:43:56.911118
7915 12:43:56.911675 Set Vref, RX VrefLevel [Byte0]: 71
7916 12:43:56.914746 [Byte1]: 71
7917 12:43:56.918884
7918 12:43:56.919461 Set Vref, RX VrefLevel [Byte0]: 72
7919 12:43:56.921928 [Byte1]: 72
7920 12:43:56.926447
7921 12:43:56.927025 Set Vref, RX VrefLevel [Byte0]: 73
7922 12:43:56.929850 [Byte1]: 73
7923 12:43:56.934080
7924 12:43:56.934652 Set Vref, RX VrefLevel [Byte0]: 74
7925 12:43:56.937424 [Byte1]: 74
7926 12:43:56.941566
7927 12:43:56.942192 Set Vref, RX VrefLevel [Byte0]: 75
7928 12:43:56.944915 [Byte1]: 75
7929 12:43:56.948799
7930 12:43:56.949273 Set Vref, RX VrefLevel [Byte0]: 76
7931 12:43:56.952757 [Byte1]: 76
7932 12:43:56.956717
7933 12:43:56.957183 Set Vref, RX VrefLevel [Byte0]: 77
7934 12:43:56.959869 [Byte1]: 77
7935 12:43:56.964362
7936 12:43:56.964939 Final RX Vref Byte 0 = 59 to rank0
7937 12:43:56.967720 Final RX Vref Byte 1 = 62 to rank0
7938 12:43:56.970988 Final RX Vref Byte 0 = 59 to rank1
7939 12:43:56.974106 Final RX Vref Byte 1 = 62 to rank1==
7940 12:43:56.978001 Dram Type= 6, Freq= 0, CH_0, rank 0
7941 12:43:56.984446 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7942 12:43:56.985035 ==
7943 12:43:56.985410 DQS Delay:
7944 12:43:56.985756 DQS0 = 0, DQS1 = 0
7945 12:43:56.987826 DQM Delay:
7946 12:43:56.988328 DQM0 = 136, DQM1 = 124
7947 12:43:56.991410 DQ Delay:
7948 12:43:56.994648 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
7949 12:43:56.997580 DQ4 =138, DQ5 =126, DQ6 =142, DQ7 =144
7950 12:43:57.000594 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =118
7951 12:43:57.004572 DQ12 =126, DQ13 =128, DQ14 =136, DQ15 =134
7952 12:43:57.005060
7953 12:43:57.005434
7954 12:43:57.005798
7955 12:43:57.007622 [DramC_TX_OE_Calibration] TA2
7956 12:43:57.010660 Original DQ_B0 (3 6) =30, OEN = 27
7957 12:43:57.014285 Original DQ_B1 (3 6) =30, OEN = 27
7958 12:43:57.017633 24, 0x0, End_B0=24 End_B1=24
7959 12:43:57.018151 25, 0x0, End_B0=25 End_B1=25
7960 12:43:57.020681 26, 0x0, End_B0=26 End_B1=26
7961 12:43:57.023960 27, 0x0, End_B0=27 End_B1=27
7962 12:43:57.027521 28, 0x0, End_B0=28 End_B1=28
7963 12:43:57.027956 29, 0x0, End_B0=29 End_B1=29
7964 12:43:57.030805 30, 0x0, End_B0=30 End_B1=30
7965 12:43:57.034036 31, 0x4141, End_B0=30 End_B1=30
7966 12:43:57.037595 Byte0 end_step=30 best_step=27
7967 12:43:57.040901 Byte1 end_step=30 best_step=27
7968 12:43:57.044328 Byte0 TX OE(2T, 0.5T) = (3, 3)
7969 12:43:57.044801 Byte1 TX OE(2T, 0.5T) = (3, 3)
7970 12:43:57.047269
7971 12:43:57.047852
7972 12:43:57.054073 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
7973 12:43:57.057320 CH0 RK0: MR19=303, MR18=1D1B
7974 12:43:57.063584 CH0_RK0: MR19=0x303, MR18=0x1D1B, DQSOSC=395, MR23=63, INC=23, DEC=15
7975 12:43:57.063669
7976 12:43:57.066722 ----->DramcWriteLeveling(PI) begin...
7977 12:43:57.066811 ==
7978 12:43:57.070301 Dram Type= 6, Freq= 0, CH_0, rank 1
7979 12:43:57.073740 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7980 12:43:57.073842 ==
7981 12:43:57.076954 Write leveling (Byte 0): 38 => 38
7982 12:43:57.080219 Write leveling (Byte 1): 27 => 27
7983 12:43:57.083636 DramcWriteLeveling(PI) end<-----
7984 12:43:57.083756
7985 12:43:57.083860 ==
7986 12:43:57.087135 Dram Type= 6, Freq= 0, CH_0, rank 1
7987 12:43:57.090227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7988 12:43:57.090350 ==
7989 12:43:57.093703 [Gating] SW mode calibration
7990 12:43:57.100670 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7991 12:43:57.106733 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7992 12:43:57.109968 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7993 12:43:57.113321 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7994 12:43:57.120537 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7995 12:43:57.123750 1 4 12 | B1->B0 | 2424 2e2e | 0 1 | (0 0) (1 1)
7996 12:43:57.126784 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7997 12:43:57.133494 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 12:43:57.136791 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7999 12:43:57.140030 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8000 12:43:57.146707 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8001 12:43:57.150110 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8002 12:43:57.153389 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8003 12:43:57.160292 1 5 12 | B1->B0 | 3434 2c2c | 1 1 | (1 0) (0 0)
8004 12:43:57.163642 1 5 16 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
8005 12:43:57.166929 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 12:43:57.173820 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 12:43:57.176941 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 12:43:57.180124 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 12:43:57.186744 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 12:43:57.190065 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8011 12:43:57.193694 1 6 12 | B1->B0 | 2f2f 4242 | 0 0 | (1 1) (0 0)
8012 12:43:57.196437 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 12:43:57.203168 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 12:43:57.206605 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 12:43:57.210233 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 12:43:57.217071 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8017 12:43:57.220076 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8018 12:43:57.223566 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8019 12:43:57.230076 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8020 12:43:57.233462 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8021 12:43:57.236656 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 12:43:57.243450 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 12:43:57.247013 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 12:43:57.250464 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 12:43:57.256455 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 12:43:57.259813 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 12:43:57.263611 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 12:43:57.270230 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 12:43:57.273539 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 12:43:57.276646 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 12:43:57.283370 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 12:43:57.286558 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 12:43:57.290193 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 12:43:57.296543 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8035 12:43:57.300114 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8036 12:43:57.303026 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8037 12:43:57.306669 Total UI for P1: 0, mck2ui 16
8038 12:43:57.309744 best dqsien dly found for B0: ( 1, 9, 10)
8039 12:43:57.316815 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8040 12:43:57.317390 Total UI for P1: 0, mck2ui 16
8041 12:43:57.319610 best dqsien dly found for B1: ( 1, 9, 16)
8042 12:43:57.326395 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8043 12:43:57.330386 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8044 12:43:57.330953
8045 12:43:57.333509 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8046 12:43:57.336403 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8047 12:43:57.339400 [Gating] SW calibration Done
8048 12:43:57.339873 ==
8049 12:43:57.343154 Dram Type= 6, Freq= 0, CH_0, rank 1
8050 12:43:57.346539 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8051 12:43:57.347110 ==
8052 12:43:57.349603 RX Vref Scan: 0
8053 12:43:57.350142
8054 12:43:57.350556 RX Vref 0 -> 0, step: 1
8055 12:43:57.350904
8056 12:43:57.352890 RX Delay 0 -> 252, step: 8
8057 12:43:57.356330 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8058 12:43:57.363178 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8059 12:43:57.366069 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8060 12:43:57.369632 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8061 12:43:57.372904 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8062 12:43:57.376393 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8063 12:43:57.382876 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8064 12:43:57.386052 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8065 12:43:57.389405 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8066 12:43:57.392253 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8067 12:43:57.396162 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8068 12:43:57.402706 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8069 12:43:57.405997 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8070 12:43:57.409073 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8071 12:43:57.412949 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8072 12:43:57.416299 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8073 12:43:57.419384 ==
8074 12:43:57.422551 Dram Type= 6, Freq= 0, CH_0, rank 1
8075 12:43:57.426161 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8076 12:43:57.426732 ==
8077 12:43:57.427105 DQS Delay:
8078 12:43:57.429366 DQS0 = 0, DQS1 = 0
8079 12:43:57.429936 DQM Delay:
8080 12:43:57.432332 DQM0 = 136, DQM1 = 125
8081 12:43:57.432803 DQ Delay:
8082 12:43:57.435956 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8083 12:43:57.439332 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8084 12:43:57.442573 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8085 12:43:57.445808 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
8086 12:43:57.446443
8087 12:43:57.446816
8088 12:43:57.447168 ==
8089 12:43:57.449267 Dram Type= 6, Freq= 0, CH_0, rank 1
8090 12:43:57.456168 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8091 12:43:57.456741 ==
8092 12:43:57.457121
8093 12:43:57.457465
8094 12:43:57.457796 TX Vref Scan disable
8095 12:43:57.459528 == TX Byte 0 ==
8096 12:43:57.462793 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8097 12:43:57.469317 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8098 12:43:57.469890 == TX Byte 1 ==
8099 12:43:57.473075 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8100 12:43:57.479184 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8101 12:43:57.479741 ==
8102 12:43:57.482476 Dram Type= 6, Freq= 0, CH_0, rank 1
8103 12:43:57.486204 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8104 12:43:57.486680 ==
8105 12:43:57.501043
8106 12:43:57.504143 TX Vref early break, caculate TX vref
8107 12:43:57.507483 TX Vref=16, minBit 0, minWin=23, winSum=384
8108 12:43:57.511011 TX Vref=18, minBit 0, minWin=24, winSum=395
8109 12:43:57.514689 TX Vref=20, minBit 0, minWin=24, winSum=399
8110 12:43:57.517419 TX Vref=22, minBit 0, minWin=25, winSum=415
8111 12:43:57.520937 TX Vref=24, minBit 0, minWin=25, winSum=418
8112 12:43:57.528129 TX Vref=26, minBit 12, minWin=25, winSum=426
8113 12:43:57.530603 TX Vref=28, minBit 0, minWin=26, winSum=428
8114 12:43:57.534449 TX Vref=30, minBit 1, minWin=26, winSum=427
8115 12:43:57.537483 TX Vref=32, minBit 0, minWin=25, winSum=417
8116 12:43:57.540916 TX Vref=34, minBit 2, minWin=24, winSum=408
8117 12:43:57.544155 TX Vref=36, minBit 2, minWin=24, winSum=398
8118 12:43:57.550876 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 28
8119 12:43:57.551428
8120 12:43:57.554012 Final TX Range 0 Vref 28
8121 12:43:57.554497
8122 12:43:57.554972 ==
8123 12:43:57.557515 Dram Type= 6, Freq= 0, CH_0, rank 1
8124 12:43:57.560913 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8125 12:43:57.561398 ==
8126 12:43:57.561877
8127 12:43:57.562356
8128 12:43:57.564357 TX Vref Scan disable
8129 12:43:57.570965 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8130 12:43:57.571552 == TX Byte 0 ==
8131 12:43:57.574565 u2DelayCellOfst[0]=13 cells (4 PI)
8132 12:43:57.577559 u2DelayCellOfst[1]=20 cells (6 PI)
8133 12:43:57.581210 u2DelayCellOfst[2]=13 cells (4 PI)
8134 12:43:57.584534 u2DelayCellOfst[3]=13 cells (4 PI)
8135 12:43:57.587862 u2DelayCellOfst[4]=10 cells (3 PI)
8136 12:43:57.590602 u2DelayCellOfst[5]=0 cells (0 PI)
8137 12:43:57.594495 u2DelayCellOfst[6]=20 cells (6 PI)
8138 12:43:57.597598 u2DelayCellOfst[7]=20 cells (6 PI)
8139 12:43:57.601025 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8140 12:43:57.603881 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8141 12:43:57.607681 == TX Byte 1 ==
8142 12:43:57.611044 u2DelayCellOfst[8]=3 cells (1 PI)
8143 12:43:57.611534 u2DelayCellOfst[9]=0 cells (0 PI)
8144 12:43:57.613997 u2DelayCellOfst[10]=6 cells (2 PI)
8145 12:43:57.617309 u2DelayCellOfst[11]=3 cells (1 PI)
8146 12:43:57.620938 u2DelayCellOfst[12]=13 cells (4 PI)
8147 12:43:57.624051 u2DelayCellOfst[13]=13 cells (4 PI)
8148 12:43:57.627627 u2DelayCellOfst[14]=13 cells (4 PI)
8149 12:43:57.630548 u2DelayCellOfst[15]=10 cells (3 PI)
8150 12:43:57.634278 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8151 12:43:57.640918 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8152 12:43:57.641502 DramC Write-DBI on
8153 12:43:57.642010 ==
8154 12:43:57.644119 Dram Type= 6, Freq= 0, CH_0, rank 1
8155 12:43:57.650721 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8156 12:43:57.651327 ==
8157 12:43:57.651742
8158 12:43:57.652090
8159 12:43:57.652421 TX Vref Scan disable
8160 12:43:57.654766 == TX Byte 0 ==
8161 12:43:57.657635 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8162 12:43:57.661251 == TX Byte 1 ==
8163 12:43:57.664873 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8164 12:43:57.667867 DramC Write-DBI off
8165 12:43:57.668434
8166 12:43:57.668809 [DATLAT]
8167 12:43:57.669160 Freq=1600, CH0 RK1
8168 12:43:57.669494
8169 12:43:57.671301 DATLAT Default: 0xf
8170 12:43:57.671869 0, 0xFFFF, sum = 0
8171 12:43:57.674327 1, 0xFFFF, sum = 0
8172 12:43:57.674805 2, 0xFFFF, sum = 0
8173 12:43:57.678251 3, 0xFFFF, sum = 0
8174 12:43:57.681132 4, 0xFFFF, sum = 0
8175 12:43:57.681610 5, 0xFFFF, sum = 0
8176 12:43:57.684482 6, 0xFFFF, sum = 0
8177 12:43:57.684957 7, 0xFFFF, sum = 0
8178 12:43:57.687805 8, 0xFFFF, sum = 0
8179 12:43:57.688283 9, 0xFFFF, sum = 0
8180 12:43:57.691254 10, 0xFFFF, sum = 0
8181 12:43:57.691831 11, 0xFFFF, sum = 0
8182 12:43:57.694596 12, 0xFFFF, sum = 0
8183 12:43:57.695072 13, 0xFFFF, sum = 0
8184 12:43:57.698055 14, 0x0, sum = 1
8185 12:43:57.698531 15, 0x0, sum = 2
8186 12:43:57.700913 16, 0x0, sum = 3
8187 12:43:57.701388 17, 0x0, sum = 4
8188 12:43:57.704880 best_step = 15
8189 12:43:57.705450
8190 12:43:57.705823 ==
8191 12:43:57.707743 Dram Type= 6, Freq= 0, CH_0, rank 1
8192 12:43:57.711265 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8193 12:43:57.711745 ==
8194 12:43:57.712123 RX Vref Scan: 0
8195 12:43:57.712474
8196 12:43:57.714536 RX Vref 0 -> 0, step: 1
8197 12:43:57.715003
8198 12:43:57.718178 RX Delay 11 -> 252, step: 4
8199 12:43:57.721333 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8200 12:43:57.727823 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8201 12:43:57.731455 iDelay=191, Bit 2, Center 128 (79 ~ 178) 100
8202 12:43:57.734381 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8203 12:43:57.738173 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8204 12:43:57.741268 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8205 12:43:57.744747 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8206 12:43:57.751373 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8207 12:43:57.754564 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8208 12:43:57.758070 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8209 12:43:57.761152 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8210 12:43:57.764726 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8211 12:43:57.771471 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8212 12:43:57.774507 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8213 12:43:57.777659 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8214 12:43:57.781111 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8215 12:43:57.781687 ==
8216 12:43:57.784745 Dram Type= 6, Freq= 0, CH_0, rank 1
8217 12:43:57.791636 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8218 12:43:57.792215 ==
8219 12:43:57.792592 DQS Delay:
8220 12:43:57.794073 DQS0 = 0, DQS1 = 0
8221 12:43:57.794544 DQM Delay:
8222 12:43:57.797679 DQM0 = 133, DQM1 = 123
8223 12:43:57.798192 DQ Delay:
8224 12:43:57.801073 DQ0 =132, DQ1 =136, DQ2 =128, DQ3 =130
8225 12:43:57.804711 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
8226 12:43:57.807979 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8227 12:43:57.811090 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =128
8228 12:43:57.811586
8229 12:43:57.811949
8230 12:43:57.812287
8231 12:43:57.814019 [DramC_TX_OE_Calibration] TA2
8232 12:43:57.817467 Original DQ_B0 (3 6) =30, OEN = 27
8233 12:43:57.821259 Original DQ_B1 (3 6) =30, OEN = 27
8234 12:43:57.824105 24, 0x0, End_B0=24 End_B1=24
8235 12:43:57.827825 25, 0x0, End_B0=25 End_B1=25
8236 12:43:57.828426 26, 0x0, End_B0=26 End_B1=26
8237 12:43:57.830644 27, 0x0, End_B0=27 End_B1=27
8238 12:43:57.834080 28, 0x0, End_B0=28 End_B1=28
8239 12:43:57.837642 29, 0x0, End_B0=29 End_B1=29
8240 12:43:57.838153 30, 0x0, End_B0=30 End_B1=30
8241 12:43:57.840795 31, 0x4141, End_B0=30 End_B1=30
8242 12:43:57.844216 Byte0 end_step=30 best_step=27
8243 12:43:57.847540 Byte1 end_step=30 best_step=27
8244 12:43:57.850623 Byte0 TX OE(2T, 0.5T) = (3, 3)
8245 12:43:57.854557 Byte1 TX OE(2T, 0.5T) = (3, 3)
8246 12:43:57.855122
8247 12:43:57.855494
8248 12:43:57.861042 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f0c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 394 ps
8249 12:43:57.864217 CH0 RK1: MR19=303, MR18=1F0C
8250 12:43:57.870835 CH0_RK1: MR19=0x303, MR18=0x1F0C, DQSOSC=394, MR23=63, INC=23, DEC=15
8251 12:43:57.874156 [RxdqsGatingPostProcess] freq 1600
8252 12:43:57.877774 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8253 12:43:57.881128 best DQS0 dly(2T, 0.5T) = (1, 1)
8254 12:43:57.884091 best DQS1 dly(2T, 0.5T) = (1, 1)
8255 12:43:57.887861 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8256 12:43:57.890850 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8257 12:43:57.894295 best DQS0 dly(2T, 0.5T) = (1, 1)
8258 12:43:57.897318 best DQS1 dly(2T, 0.5T) = (1, 1)
8259 12:43:57.900746 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8260 12:43:57.904123 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8261 12:43:57.907384 Pre-setting of DQS Precalculation
8262 12:43:57.910635 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8263 12:43:57.911170 ==
8264 12:43:57.913867 Dram Type= 6, Freq= 0, CH_1, rank 0
8265 12:43:57.917627 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8266 12:43:57.920664 ==
8267 12:43:57.923931 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8268 12:43:57.927236 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8269 12:43:57.933937 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8270 12:43:57.940495 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8271 12:43:57.947932 [CA 0] Center 42 (12~72) winsize 61
8272 12:43:57.950681 [CA 1] Center 42 (12~72) winsize 61
8273 12:43:57.954514 [CA 2] Center 38 (9~68) winsize 60
8274 12:43:57.957741 [CA 3] Center 37 (8~67) winsize 60
8275 12:43:57.960623 [CA 4] Center 37 (8~67) winsize 60
8276 12:43:57.964073 [CA 5] Center 37 (7~67) winsize 61
8277 12:43:57.964634
8278 12:43:57.967331 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8279 12:43:57.967799
8280 12:43:57.970667 [CATrainingPosCal] consider 1 rank data
8281 12:43:57.973990 u2DelayCellTimex100 = 290/100 ps
8282 12:43:57.977349 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8283 12:43:57.984427 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8284 12:43:57.987098 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8285 12:43:57.990992 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8286 12:43:57.993722 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8287 12:43:57.997163 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8288 12:43:57.997731
8289 12:43:58.000637 CA PerBit enable=1, Macro0, CA PI delay=37
8290 12:43:58.001206
8291 12:43:58.004273 [CBTSetCACLKResult] CA Dly = 37
8292 12:43:58.007649 CS Dly: 9 (0~40)
8293 12:43:58.010705 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8294 12:43:58.014002 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8295 12:43:58.014470 ==
8296 12:43:58.017509 Dram Type= 6, Freq= 0, CH_1, rank 1
8297 12:43:58.020623 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8298 12:43:58.023493 ==
8299 12:43:58.026891 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8300 12:43:58.030535 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8301 12:43:58.037119 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8302 12:43:58.040193 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8303 12:43:58.050536 [CA 0] Center 42 (13~72) winsize 60
8304 12:43:58.053743 [CA 1] Center 42 (12~72) winsize 61
8305 12:43:58.056990 [CA 2] Center 39 (10~68) winsize 59
8306 12:43:58.060395 [CA 3] Center 37 (8~67) winsize 60
8307 12:43:58.063790 [CA 4] Center 38 (9~68) winsize 60
8308 12:43:58.067389 [CA 5] Center 37 (8~67) winsize 60
8309 12:43:58.067810
8310 12:43:58.070727 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8311 12:43:58.071148
8312 12:43:58.074102 [CATrainingPosCal] consider 2 rank data
8313 12:43:58.077568 u2DelayCellTimex100 = 290/100 ps
8314 12:43:58.080937 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8315 12:43:58.087558 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8316 12:43:58.091084 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8317 12:43:58.094053 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8318 12:43:58.097187 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8319 12:43:58.100650 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8320 12:43:58.101208
8321 12:43:58.104524 CA PerBit enable=1, Macro0, CA PI delay=37
8322 12:43:58.104980
8323 12:43:58.107592 [CBTSetCACLKResult] CA Dly = 37
8324 12:43:58.110410 CS Dly: 10 (0~43)
8325 12:43:58.114056 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8326 12:43:58.117398 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8327 12:43:58.117980
8328 12:43:58.120667 ----->DramcWriteLeveling(PI) begin...
8329 12:43:58.121126 ==
8330 12:43:58.124518 Dram Type= 6, Freq= 0, CH_1, rank 0
8331 12:43:58.127460 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8332 12:43:58.130841 ==
8333 12:43:58.131396 Write leveling (Byte 0): 24 => 24
8334 12:43:58.134113 Write leveling (Byte 1): 29 => 29
8335 12:43:58.137183 DramcWriteLeveling(PI) end<-----
8336 12:43:58.137749
8337 12:43:58.138162 ==
8338 12:43:58.140366 Dram Type= 6, Freq= 0, CH_1, rank 0
8339 12:43:58.147177 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8340 12:43:58.147826 ==
8341 12:43:58.150350 [Gating] SW mode calibration
8342 12:43:58.157236 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8343 12:43:58.160244 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8344 12:43:58.166799 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 12:43:58.170342 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 12:43:58.173208 1 4 8 | B1->B0 | 2828 2e2e | 1 1 | (1 1) (1 1)
8347 12:43:58.180119 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 12:43:58.183449 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 12:43:58.186842 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 12:43:58.193694 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 12:43:58.196993 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 12:43:58.199890 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 12:43:58.206754 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8354 12:43:58.209998 1 5 8 | B1->B0 | 2a2a 2c2c | 0 0 | (0 0) (1 0)
8355 12:43:58.212864 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8356 12:43:58.219741 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 12:43:58.222978 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 12:43:58.226569 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 12:43:58.233237 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 12:43:58.236459 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 12:43:58.239740 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 12:43:58.246514 1 6 8 | B1->B0 | 3b3b 4242 | 0 0 | (0 0) (1 1)
8363 12:43:58.249619 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 12:43:58.252808 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 12:43:58.256398 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 12:43:58.262822 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 12:43:58.266353 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 12:43:58.269476 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 12:43:58.276129 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8370 12:43:58.279264 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8371 12:43:58.282786 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8372 12:43:58.289879 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8373 12:43:58.292625 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 12:43:58.296157 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 12:43:58.302698 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 12:43:58.305622 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 12:43:58.309285 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 12:43:58.316181 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 12:43:58.319375 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 12:43:58.322686 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 12:43:58.329326 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 12:43:58.332637 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 12:43:58.335993 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 12:43:58.342762 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 12:43:58.345658 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 12:43:58.349182 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8387 12:43:58.356055 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8388 12:43:58.356624 Total UI for P1: 0, mck2ui 16
8389 12:43:58.362533 best dqsien dly found for B0: ( 1, 9, 8)
8390 12:43:58.365897 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 12:43:58.369187 Total UI for P1: 0, mck2ui 16
8392 12:43:58.372767 best dqsien dly found for B1: ( 1, 9, 10)
8393 12:43:58.375805 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8394 12:43:58.378816 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8395 12:43:58.379327
8396 12:43:58.382579 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8397 12:43:58.386054 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8398 12:43:58.389519 [Gating] SW calibration Done
8399 12:43:58.390124 ==
8400 12:43:58.392594 Dram Type= 6, Freq= 0, CH_1, rank 0
8401 12:43:58.395568 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8402 12:43:58.396047 ==
8403 12:43:58.399203 RX Vref Scan: 0
8404 12:43:58.399786
8405 12:43:58.402491 RX Vref 0 -> 0, step: 1
8406 12:43:58.402985
8407 12:43:58.403366 RX Delay 0 -> 252, step: 8
8408 12:43:58.409423 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8409 12:43:58.412097 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8410 12:43:58.415735 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8411 12:43:58.419069 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8412 12:43:58.421917 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8413 12:43:58.429521 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8414 12:43:58.432638 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8415 12:43:58.435792 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8416 12:43:58.439196 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
8417 12:43:58.442637 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8418 12:43:58.445912 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8419 12:43:58.452325 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8420 12:43:58.455600 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8421 12:43:58.459089 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8422 12:43:58.462372 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8423 12:43:58.468817 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8424 12:43:58.469405 ==
8425 12:43:58.472236 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 12:43:58.475353 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8427 12:43:58.475830 ==
8428 12:43:58.476202 DQS Delay:
8429 12:43:58.478596 DQS0 = 0, DQS1 = 0
8430 12:43:58.479070 DQM Delay:
8431 12:43:58.482059 DQM0 = 137, DQM1 = 131
8432 12:43:58.482530 DQ Delay:
8433 12:43:58.485235 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =139
8434 12:43:58.488853 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8435 12:43:58.491743 DQ8 =123, DQ9 =119, DQ10 =131, DQ11 =127
8436 12:43:58.495071 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
8437 12:43:58.495545
8438 12:43:58.495919
8439 12:43:58.498561 ==
8440 12:43:58.501895 Dram Type= 6, Freq= 0, CH_1, rank 0
8441 12:43:58.505384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8442 12:43:58.506012 ==
8443 12:43:58.506405
8444 12:43:58.506752
8445 12:43:58.508517 TX Vref Scan disable
8446 12:43:58.509093 == TX Byte 0 ==
8447 12:43:58.511846 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8448 12:43:58.518393 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8449 12:43:58.518867 == TX Byte 1 ==
8450 12:43:58.521825 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8451 12:43:58.528413 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8452 12:43:58.528994 ==
8453 12:43:58.531701 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 12:43:58.534565 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 12:43:58.535081 ==
8456 12:43:58.548319
8457 12:43:58.551864 TX Vref early break, caculate TX vref
8458 12:43:58.554745 TX Vref=16, minBit 10, minWin=21, winSum=364
8459 12:43:58.558308 TX Vref=18, minBit 10, minWin=21, winSum=375
8460 12:43:58.561452 TX Vref=20, minBit 10, minWin=22, winSum=384
8461 12:43:58.564998 TX Vref=22, minBit 9, minWin=23, winSum=394
8462 12:43:58.567962 TX Vref=24, minBit 9, minWin=23, winSum=401
8463 12:43:58.574524 TX Vref=26, minBit 10, minWin=23, winSum=412
8464 12:43:58.577905 TX Vref=28, minBit 14, minWin=24, winSum=417
8465 12:43:58.581158 TX Vref=30, minBit 9, minWin=23, winSum=404
8466 12:43:58.584403 TX Vref=32, minBit 8, minWin=23, winSum=406
8467 12:43:58.588040 TX Vref=34, minBit 9, minWin=22, winSum=388
8468 12:43:58.594851 [TxChooseVref] Worse bit 14, Min win 24, Win sum 417, Final Vref 28
8469 12:43:58.595328
8470 12:43:58.597795 Final TX Range 0 Vref 28
8471 12:43:58.598327
8472 12:43:58.598700 ==
8473 12:43:58.601291 Dram Type= 6, Freq= 0, CH_1, rank 0
8474 12:43:58.604552 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8475 12:43:58.605028 ==
8476 12:43:58.605407
8477 12:43:58.605756
8478 12:43:58.608222 TX Vref Scan disable
8479 12:43:58.614515 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8480 12:43:58.615111 == TX Byte 0 ==
8481 12:43:58.617719 u2DelayCellOfst[0]=16 cells (5 PI)
8482 12:43:58.621402 u2DelayCellOfst[1]=10 cells (3 PI)
8483 12:43:58.624676 u2DelayCellOfst[2]=0 cells (0 PI)
8484 12:43:58.627498 u2DelayCellOfst[3]=6 cells (2 PI)
8485 12:43:58.631281 u2DelayCellOfst[4]=6 cells (2 PI)
8486 12:43:58.634315 u2DelayCellOfst[5]=16 cells (5 PI)
8487 12:43:58.637715 u2DelayCellOfst[6]=16 cells (5 PI)
8488 12:43:58.641538 u2DelayCellOfst[7]=6 cells (2 PI)
8489 12:43:58.644027 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8490 12:43:58.648003 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8491 12:43:58.651436 == TX Byte 1 ==
8492 12:43:58.654104 u2DelayCellOfst[8]=0 cells (0 PI)
8493 12:43:58.654686 u2DelayCellOfst[9]=6 cells (2 PI)
8494 12:43:58.657666 u2DelayCellOfst[10]=10 cells (3 PI)
8495 12:43:58.661219 u2DelayCellOfst[11]=6 cells (2 PI)
8496 12:43:58.664205 u2DelayCellOfst[12]=16 cells (5 PI)
8497 12:43:58.667553 u2DelayCellOfst[13]=16 cells (5 PI)
8498 12:43:58.670977 u2DelayCellOfst[14]=20 cells (6 PI)
8499 12:43:58.674108 u2DelayCellOfst[15]=20 cells (6 PI)
8500 12:43:58.677583 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8501 12:43:58.684402 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8502 12:43:58.684987 DramC Write-DBI on
8503 12:43:58.685367 ==
8504 12:43:58.687537 Dram Type= 6, Freq= 0, CH_1, rank 0
8505 12:43:58.694206 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8506 12:43:58.694937 ==
8507 12:43:58.695383
8508 12:43:58.695740
8509 12:43:58.696081 TX Vref Scan disable
8510 12:43:58.697799 == TX Byte 0 ==
8511 12:43:58.701474 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8512 12:43:58.704785 == TX Byte 1 ==
8513 12:43:58.708332 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8514 12:43:58.708940 DramC Write-DBI off
8515 12:43:58.711533
8516 12:43:58.712006 [DATLAT]
8517 12:43:58.712377 Freq=1600, CH1 RK0
8518 12:43:58.712727
8519 12:43:58.714645 DATLAT Default: 0xf
8520 12:43:58.715117 0, 0xFFFF, sum = 0
8521 12:43:58.718007 1, 0xFFFF, sum = 0
8522 12:43:58.718485 2, 0xFFFF, sum = 0
8523 12:43:58.721264 3, 0xFFFF, sum = 0
8524 12:43:58.721848 4, 0xFFFF, sum = 0
8525 12:43:58.724666 5, 0xFFFF, sum = 0
8526 12:43:58.727973 6, 0xFFFF, sum = 0
8527 12:43:58.728558 7, 0xFFFF, sum = 0
8528 12:43:58.731591 8, 0xFFFF, sum = 0
8529 12:43:58.732225 9, 0xFFFF, sum = 0
8530 12:43:58.734829 10, 0xFFFF, sum = 0
8531 12:43:58.735409 11, 0xFFFF, sum = 0
8532 12:43:58.737815 12, 0xFFFF, sum = 0
8533 12:43:58.738438 13, 0xFFFF, sum = 0
8534 12:43:58.741184 14, 0x0, sum = 1
8535 12:43:58.741687 15, 0x0, sum = 2
8536 12:43:58.744415 16, 0x0, sum = 3
8537 12:43:58.744998 17, 0x0, sum = 4
8538 12:43:58.747642 best_step = 15
8539 12:43:58.748116
8540 12:43:58.748494 ==
8541 12:43:58.751155 Dram Type= 6, Freq= 0, CH_1, rank 0
8542 12:43:58.754626 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8543 12:43:58.755201 ==
8544 12:43:58.755580 RX Vref Scan: 1
8545 12:43:58.757782
8546 12:43:58.758285 Set Vref Range= 24 -> 127
8547 12:43:58.758660
8548 12:43:58.761407 RX Vref 24 -> 127, step: 1
8549 12:43:58.762021
8550 12:43:58.764161 RX Delay 27 -> 252, step: 4
8551 12:43:58.764902
8552 12:43:58.767696 Set Vref, RX VrefLevel [Byte0]: 24
8553 12:43:58.771188 [Byte1]: 24
8554 12:43:58.771768
8555 12:43:58.774114 Set Vref, RX VrefLevel [Byte0]: 25
8556 12:43:58.777858 [Byte1]: 25
8557 12:43:58.778482
8558 12:43:58.781003 Set Vref, RX VrefLevel [Byte0]: 26
8559 12:43:58.784592 [Byte1]: 26
8560 12:43:58.788150
8561 12:43:58.788721 Set Vref, RX VrefLevel [Byte0]: 27
8562 12:43:58.791081 [Byte1]: 27
8563 12:43:58.795418
8564 12:43:58.795882 Set Vref, RX VrefLevel [Byte0]: 28
8565 12:43:58.798509 [Byte1]: 28
8566 12:43:58.803140
8567 12:43:58.803874 Set Vref, RX VrefLevel [Byte0]: 29
8568 12:43:58.806484 [Byte1]: 29
8569 12:43:58.810930
8570 12:43:58.811514 Set Vref, RX VrefLevel [Byte0]: 30
8571 12:43:58.814144 [Byte1]: 30
8572 12:43:58.818055
8573 12:43:58.818515 Set Vref, RX VrefLevel [Byte0]: 31
8574 12:43:58.821422 [Byte1]: 31
8575 12:43:58.825677
8576 12:43:58.826325 Set Vref, RX VrefLevel [Byte0]: 32
8577 12:43:58.829149 [Byte1]: 32
8578 12:43:58.833634
8579 12:43:58.834314 Set Vref, RX VrefLevel [Byte0]: 33
8580 12:43:58.836617 [Byte1]: 33
8581 12:43:58.840995
8582 12:43:58.841560 Set Vref, RX VrefLevel [Byte0]: 34
8583 12:43:58.844361 [Byte1]: 34
8584 12:43:58.848394
8585 12:43:58.849051 Set Vref, RX VrefLevel [Byte0]: 35
8586 12:43:58.851791 [Byte1]: 35
8587 12:43:58.855909
8588 12:43:58.856488 Set Vref, RX VrefLevel [Byte0]: 36
8589 12:43:58.859221 [Byte1]: 36
8590 12:43:58.863400
8591 12:43:58.863866 Set Vref, RX VrefLevel [Byte0]: 37
8592 12:43:58.869831 [Byte1]: 37
8593 12:43:58.870439
8594 12:43:58.873261 Set Vref, RX VrefLevel [Byte0]: 38
8595 12:43:58.876725 [Byte1]: 38
8596 12:43:58.877294
8597 12:43:58.879913 Set Vref, RX VrefLevel [Byte0]: 39
8598 12:43:58.883043 [Byte1]: 39
8599 12:43:58.883513
8600 12:43:58.886648 Set Vref, RX VrefLevel [Byte0]: 40
8601 12:43:58.889597 [Byte1]: 40
8602 12:43:58.893409
8603 12:43:58.893869 Set Vref, RX VrefLevel [Byte0]: 41
8604 12:43:58.896777 [Byte1]: 41
8605 12:43:58.901116
8606 12:43:58.901684 Set Vref, RX VrefLevel [Byte0]: 42
8607 12:43:58.904418 [Byte1]: 42
8608 12:43:58.908589
8609 12:43:58.909172 Set Vref, RX VrefLevel [Byte0]: 43
8610 12:43:58.912002 [Byte1]: 43
8611 12:43:58.915885
8612 12:43:58.916663 Set Vref, RX VrefLevel [Byte0]: 44
8613 12:43:58.919523 [Byte1]: 44
8614 12:43:58.923455
8615 12:43:58.923917 Set Vref, RX VrefLevel [Byte0]: 45
8616 12:43:58.926701 [Byte1]: 45
8617 12:43:58.931307
8618 12:43:58.931872 Set Vref, RX VrefLevel [Byte0]: 46
8619 12:43:58.934703 [Byte1]: 46
8620 12:43:58.938838
8621 12:43:58.939407 Set Vref, RX VrefLevel [Byte0]: 47
8622 12:43:58.942175 [Byte1]: 47
8623 12:43:58.946138
8624 12:43:58.946604 Set Vref, RX VrefLevel [Byte0]: 48
8625 12:43:58.949489 [Byte1]: 48
8626 12:43:58.953738
8627 12:43:58.954414 Set Vref, RX VrefLevel [Byte0]: 49
8628 12:43:58.957224 [Byte1]: 49
8629 12:43:58.961346
8630 12:43:58.961917 Set Vref, RX VrefLevel [Byte0]: 50
8631 12:43:58.964494 [Byte1]: 50
8632 12:43:58.968660
8633 12:43:58.969122 Set Vref, RX VrefLevel [Byte0]: 51
8634 12:43:58.972217 [Byte1]: 51
8635 12:43:58.976647
8636 12:43:58.977214 Set Vref, RX VrefLevel [Byte0]: 52
8637 12:43:58.979513 [Byte1]: 52
8638 12:43:58.984206
8639 12:43:58.984775 Set Vref, RX VrefLevel [Byte0]: 53
8640 12:43:58.986928 [Byte1]: 53
8641 12:43:58.991523
8642 12:43:58.992087 Set Vref, RX VrefLevel [Byte0]: 54
8643 12:43:58.994441 [Byte1]: 54
8644 12:43:58.998664
8645 12:43:58.999129 Set Vref, RX VrefLevel [Byte0]: 55
8646 12:43:59.001925 [Byte1]: 55
8647 12:43:59.006363
8648 12:43:59.006825 Set Vref, RX VrefLevel [Byte0]: 56
8649 12:43:59.010072 [Byte1]: 56
8650 12:43:59.013904
8651 12:43:59.014403 Set Vref, RX VrefLevel [Byte0]: 57
8652 12:43:59.017155 [Byte1]: 57
8653 12:43:59.021565
8654 12:43:59.022214 Set Vref, RX VrefLevel [Byte0]: 58
8655 12:43:59.024511 [Byte1]: 58
8656 12:43:59.029134
8657 12:43:59.029718 Set Vref, RX VrefLevel [Byte0]: 59
8658 12:43:59.032723 [Byte1]: 59
8659 12:43:59.036866
8660 12:43:59.037432 Set Vref, RX VrefLevel [Byte0]: 60
8661 12:43:59.040015 [Byte1]: 60
8662 12:43:59.044462
8663 12:43:59.045036 Set Vref, RX VrefLevel [Byte0]: 61
8664 12:43:59.047603 [Byte1]: 61
8665 12:43:59.051581
8666 12:43:59.052142 Set Vref, RX VrefLevel [Byte0]: 62
8667 12:43:59.054911 [Byte1]: 62
8668 12:43:59.059061
8669 12:43:59.059620 Set Vref, RX VrefLevel [Byte0]: 63
8670 12:43:59.062592 [Byte1]: 63
8671 12:43:59.066957
8672 12:43:59.067422 Set Vref, RX VrefLevel [Byte0]: 64
8673 12:43:59.069694 [Byte1]: 64
8674 12:43:59.074372
8675 12:43:59.074935 Set Vref, RX VrefLevel [Byte0]: 65
8676 12:43:59.077422 [Byte1]: 65
8677 12:43:59.081771
8678 12:43:59.082395 Set Vref, RX VrefLevel [Byte0]: 66
8679 12:43:59.085015 [Byte1]: 66
8680 12:43:59.089530
8681 12:43:59.090151 Set Vref, RX VrefLevel [Byte0]: 67
8682 12:43:59.092757 [Byte1]: 67
8683 12:43:59.096821
8684 12:43:59.097420 Set Vref, RX VrefLevel [Byte0]: 68
8685 12:43:59.100521 [Byte1]: 68
8686 12:43:59.104658
8687 12:43:59.105229 Set Vref, RX VrefLevel [Byte0]: 69
8688 12:43:59.107506 [Byte1]: 69
8689 12:43:59.111999
8690 12:43:59.112477 Set Vref, RX VrefLevel [Byte0]: 70
8691 12:43:59.115024 [Byte1]: 70
8692 12:43:59.119457
8693 12:43:59.120027 Set Vref, RX VrefLevel [Byte0]: 71
8694 12:43:59.122589 [Byte1]: 71
8695 12:43:59.127132
8696 12:43:59.127707 Set Vref, RX VrefLevel [Byte0]: 72
8697 12:43:59.130190 [Byte1]: 72
8698 12:43:59.134576
8699 12:43:59.135043 Set Vref, RX VrefLevel [Byte0]: 73
8700 12:43:59.138049 [Byte1]: 73
8701 12:43:59.142164
8702 12:43:59.142726 Set Vref, RX VrefLevel [Byte0]: 74
8703 12:43:59.145119 [Byte1]: 74
8704 12:43:59.150096
8705 12:43:59.150838 Set Vref, RX VrefLevel [Byte0]: 75
8706 12:43:59.152590 [Byte1]: 75
8707 12:43:59.157310
8708 12:43:59.157884 Final RX Vref Byte 0 = 53 to rank0
8709 12:43:59.160670 Final RX Vref Byte 1 = 63 to rank0
8710 12:43:59.163812 Final RX Vref Byte 0 = 53 to rank1
8711 12:43:59.167074 Final RX Vref Byte 1 = 63 to rank1==
8712 12:43:59.170474 Dram Type= 6, Freq= 0, CH_1, rank 0
8713 12:43:59.177263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8714 12:43:59.177842 ==
8715 12:43:59.178278 DQS Delay:
8716 12:43:59.178633 DQS0 = 0, DQS1 = 0
8717 12:43:59.180678 DQM Delay:
8718 12:43:59.181251 DQM0 = 133, DQM1 = 129
8719 12:43:59.183800 DQ Delay:
8720 12:43:59.186959 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8721 12:43:59.190335 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8722 12:43:59.193322 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =122
8723 12:43:59.197064 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =134
8724 12:43:59.197638
8725 12:43:59.198043
8726 12:43:59.198391
8727 12:43:59.200131 [DramC_TX_OE_Calibration] TA2
8728 12:43:59.203668 Original DQ_B0 (3 6) =30, OEN = 27
8729 12:43:59.206615 Original DQ_B1 (3 6) =30, OEN = 27
8730 12:43:59.210146 24, 0x0, End_B0=24 End_B1=24
8731 12:43:59.210725 25, 0x0, End_B0=25 End_B1=25
8732 12:43:59.213519 26, 0x0, End_B0=26 End_B1=26
8733 12:43:59.216644 27, 0x0, End_B0=27 End_B1=27
8734 12:43:59.220282 28, 0x0, End_B0=28 End_B1=28
8735 12:43:59.223517 29, 0x0, End_B0=29 End_B1=29
8736 12:43:59.223999 30, 0x0, End_B0=30 End_B1=30
8737 12:43:59.226800 31, 0x5151, End_B0=30 End_B1=30
8738 12:43:59.229914 Byte0 end_step=30 best_step=27
8739 12:43:59.233705 Byte1 end_step=30 best_step=27
8740 12:43:59.236529 Byte0 TX OE(2T, 0.5T) = (3, 3)
8741 12:43:59.239891 Byte1 TX OE(2T, 0.5T) = (3, 3)
8742 12:43:59.240461
8743 12:43:59.240899
8744 12:43:59.246812 [DQSOSCAuto] RK0, (LSB)MR18= 0x1625, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8745 12:43:59.249770 CH1 RK0: MR19=303, MR18=1625
8746 12:43:59.256825 CH1_RK0: MR19=0x303, MR18=0x1625, DQSOSC=391, MR23=63, INC=24, DEC=16
8747 12:43:59.257402
8748 12:43:59.260298 ----->DramcWriteLeveling(PI) begin...
8749 12:43:59.260882 ==
8750 12:43:59.263397 Dram Type= 6, Freq= 0, CH_1, rank 1
8751 12:43:59.266604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8752 12:43:59.267082 ==
8753 12:43:59.269878 Write leveling (Byte 0): 26 => 26
8754 12:43:59.273623 Write leveling (Byte 1): 28 => 28
8755 12:43:59.276835 DramcWriteLeveling(PI) end<-----
8756 12:43:59.277406
8757 12:43:59.277779 ==
8758 12:43:59.280245 Dram Type= 6, Freq= 0, CH_1, rank 1
8759 12:43:59.283299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8760 12:43:59.283777 ==
8761 12:43:59.286595 [Gating] SW mode calibration
8762 12:43:59.293350 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8763 12:43:59.300092 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8764 12:43:59.303792 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 12:43:59.306507 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 12:43:59.313335 1 4 8 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8767 12:43:59.316614 1 4 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
8768 12:43:59.319593 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8769 12:43:59.326302 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8770 12:43:59.329418 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8771 12:43:59.332810 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8772 12:43:59.339620 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 12:43:59.343063 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 12:43:59.346246 1 5 8 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 0)
8775 12:43:59.352818 1 5 12 | B1->B0 | 2323 2d2d | 0 0 | (1 0) (1 0)
8776 12:43:59.355938 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 12:43:59.359755 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 12:43:59.366180 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 12:43:59.369265 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 12:43:59.372963 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 12:43:59.379594 1 6 4 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
8782 12:43:59.382783 1 6 8 | B1->B0 | 4646 2424 | 0 0 | (0 0) (0 0)
8783 12:43:59.386365 1 6 12 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
8784 12:43:59.392920 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 12:43:59.396415 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8786 12:43:59.398877 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 12:43:59.405655 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 12:43:59.409462 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 12:43:59.412186 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 12:43:59.419022 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8791 12:43:59.422530 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8792 12:43:59.425749 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 12:43:59.432543 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 12:43:59.435675 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 12:43:59.438837 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 12:43:59.445540 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 12:43:59.449019 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 12:43:59.452004 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 12:43:59.458774 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 12:43:59.462527 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 12:43:59.465401 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 12:43:59.472435 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 12:43:59.475744 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 12:43:59.479072 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 12:43:59.485782 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 12:43:59.488912 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8807 12:43:59.492261 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8808 12:43:59.495685 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 12:43:59.498496 Total UI for P1: 0, mck2ui 16
8810 12:43:59.502256 best dqsien dly found for B0: ( 1, 9, 10)
8811 12:43:59.505730 Total UI for P1: 0, mck2ui 16
8812 12:43:59.508960 best dqsien dly found for B1: ( 1, 9, 10)
8813 12:43:59.511974 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8814 12:43:59.515512 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8815 12:43:59.518606
8816 12:43:59.522056 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8817 12:43:59.525799 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8818 12:43:59.528645 [Gating] SW calibration Done
8819 12:43:59.529216 ==
8820 12:43:59.532152 Dram Type= 6, Freq= 0, CH_1, rank 1
8821 12:43:59.535543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8822 12:43:59.536114 ==
8823 12:43:59.538870 RX Vref Scan: 0
8824 12:43:59.539436
8825 12:43:59.539808 RX Vref 0 -> 0, step: 1
8826 12:43:59.540156
8827 12:43:59.542140 RX Delay 0 -> 252, step: 8
8828 12:43:59.545146 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8829 12:43:59.548552 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8830 12:43:59.555026 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8831 12:43:59.558258 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8832 12:43:59.562008 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8833 12:43:59.565260 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8834 12:43:59.568556 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8835 12:43:59.571829 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8836 12:43:59.578848 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8837 12:43:59.582276 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8838 12:43:59.585133 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8839 12:43:59.588588 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8840 12:43:59.595256 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8841 12:43:59.598543 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8842 12:43:59.601860 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8843 12:43:59.604700 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8844 12:43:59.605312 ==
8845 12:43:59.607946 Dram Type= 6, Freq= 0, CH_1, rank 1
8846 12:43:59.614657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8847 12:43:59.615279 ==
8848 12:43:59.615717 DQS Delay:
8849 12:43:59.616071 DQS0 = 0, DQS1 = 0
8850 12:43:59.618273 DQM Delay:
8851 12:43:59.618757 DQM0 = 137, DQM1 = 133
8852 12:43:59.621577 DQ Delay:
8853 12:43:59.624887 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =135
8854 12:43:59.628207 DQ4 =139, DQ5 =147, DQ6 =139, DQ7 =139
8855 12:43:59.631616 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8856 12:43:59.634775 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8857 12:43:59.635207
8858 12:43:59.635546
8859 12:43:59.636051 ==
8860 12:43:59.638002 Dram Type= 6, Freq= 0, CH_1, rank 1
8861 12:43:59.641506 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8862 12:43:59.644926 ==
8863 12:43:59.645525
8864 12:43:59.645981
8865 12:43:59.646359 TX Vref Scan disable
8866 12:43:59.647994 == TX Byte 0 ==
8867 12:43:59.651999 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8868 12:43:59.654603 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8869 12:43:59.658107 == TX Byte 1 ==
8870 12:43:59.661648 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8871 12:43:59.664869 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8872 12:43:59.665449 ==
8873 12:43:59.668041 Dram Type= 6, Freq= 0, CH_1, rank 1
8874 12:43:59.674320 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8875 12:43:59.674882 ==
8876 12:43:59.686635
8877 12:43:59.689695 TX Vref early break, caculate TX vref
8878 12:43:59.693025 TX Vref=16, minBit 9, minWin=22, winSum=382
8879 12:43:59.696336 TX Vref=18, minBit 8, minWin=23, winSum=389
8880 12:43:59.699574 TX Vref=20, minBit 10, minWin=23, winSum=399
8881 12:43:59.702809 TX Vref=22, minBit 9, minWin=23, winSum=406
8882 12:43:59.706017 TX Vref=24, minBit 9, minWin=24, winSum=415
8883 12:43:59.712962 TX Vref=26, minBit 8, minWin=25, winSum=420
8884 12:43:59.716139 TX Vref=28, minBit 0, minWin=25, winSum=423
8885 12:43:59.719492 TX Vref=30, minBit 10, minWin=24, winSum=415
8886 12:43:59.722445 TX Vref=32, minBit 10, minWin=24, winSum=406
8887 12:43:59.725748 TX Vref=34, minBit 9, minWin=23, winSum=398
8888 12:43:59.732785 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 28
8889 12:43:59.733354
8890 12:43:59.735860 Final TX Range 0 Vref 28
8891 12:43:59.736334
8892 12:43:59.736702 ==
8893 12:43:59.739384 Dram Type= 6, Freq= 0, CH_1, rank 1
8894 12:43:59.742856 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8895 12:43:59.743426 ==
8896 12:43:59.743803
8897 12:43:59.744149
8898 12:43:59.746378 TX Vref Scan disable
8899 12:43:59.752915 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8900 12:43:59.753487 == TX Byte 0 ==
8901 12:43:59.756095 u2DelayCellOfst[0]=16 cells (5 PI)
8902 12:43:59.759283 u2DelayCellOfst[1]=10 cells (3 PI)
8903 12:43:59.762809 u2DelayCellOfst[2]=0 cells (0 PI)
8904 12:43:59.766183 u2DelayCellOfst[3]=6 cells (2 PI)
8905 12:43:59.769337 u2DelayCellOfst[4]=10 cells (3 PI)
8906 12:43:59.772894 u2DelayCellOfst[5]=20 cells (6 PI)
8907 12:43:59.775965 u2DelayCellOfst[6]=20 cells (6 PI)
8908 12:43:59.778986 u2DelayCellOfst[7]=6 cells (2 PI)
8909 12:43:59.782487 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8910 12:43:59.786098 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8911 12:43:59.789169 == TX Byte 1 ==
8912 12:43:59.792273 u2DelayCellOfst[8]=0 cells (0 PI)
8913 12:43:59.792800 u2DelayCellOfst[9]=3 cells (1 PI)
8914 12:43:59.795803 u2DelayCellOfst[10]=6 cells (2 PI)
8915 12:43:59.799189 u2DelayCellOfst[11]=3 cells (1 PI)
8916 12:43:59.802425 u2DelayCellOfst[12]=10 cells (3 PI)
8917 12:43:59.805915 u2DelayCellOfst[13]=13 cells (4 PI)
8918 12:43:59.809306 u2DelayCellOfst[14]=16 cells (5 PI)
8919 12:43:59.812773 u2DelayCellOfst[15]=16 cells (5 PI)
8920 12:43:59.816256 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8921 12:43:59.822601 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8922 12:43:59.823165 DramC Write-DBI on
8923 12:43:59.823537 ==
8924 12:43:59.825973 Dram Type= 6, Freq= 0, CH_1, rank 1
8925 12:43:59.832535 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8926 12:43:59.833105 ==
8927 12:43:59.833485
8928 12:43:59.833832
8929 12:43:59.834209 TX Vref Scan disable
8930 12:43:59.836127 == TX Byte 0 ==
8931 12:43:59.839504 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8932 12:43:59.842923 == TX Byte 1 ==
8933 12:43:59.845999 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8934 12:43:59.849321 DramC Write-DBI off
8935 12:43:59.849893
8936 12:43:59.850307 [DATLAT]
8937 12:43:59.850653 Freq=1600, CH1 RK1
8938 12:43:59.851007
8939 12:43:59.852559 DATLAT Default: 0xf
8940 12:43:59.853079 0, 0xFFFF, sum = 0
8941 12:43:59.856032 1, 0xFFFF, sum = 0
8942 12:43:59.856530 2, 0xFFFF, sum = 0
8943 12:43:59.859511 3, 0xFFFF, sum = 0
8944 12:43:59.862526 4, 0xFFFF, sum = 0
8945 12:43:59.863098 5, 0xFFFF, sum = 0
8946 12:43:59.865679 6, 0xFFFF, sum = 0
8947 12:43:59.866184 7, 0xFFFF, sum = 0
8948 12:43:59.869256 8, 0xFFFF, sum = 0
8949 12:43:59.869744 9, 0xFFFF, sum = 0
8950 12:43:59.872311 10, 0xFFFF, sum = 0
8951 12:43:59.872788 11, 0xFFFF, sum = 0
8952 12:43:59.875597 12, 0xFFFF, sum = 0
8953 12:43:59.876073 13, 0xFFFF, sum = 0
8954 12:43:59.878882 14, 0x0, sum = 1
8955 12:43:59.879386 15, 0x0, sum = 2
8956 12:43:59.882258 16, 0x0, sum = 3
8957 12:43:59.882737 17, 0x0, sum = 4
8958 12:43:59.885712 best_step = 15
8959 12:43:59.886220
8960 12:43:59.886590 ==
8961 12:43:59.889011 Dram Type= 6, Freq= 0, CH_1, rank 1
8962 12:43:59.892151 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8963 12:43:59.892624 ==
8964 12:43:59.895810 RX Vref Scan: 0
8965 12:43:59.896382
8966 12:43:59.896755 RX Vref 0 -> 0, step: 1
8967 12:43:59.897099
8968 12:43:59.898823 RX Delay 19 -> 252, step: 4
8969 12:43:59.902190 iDelay=195, Bit 0, Center 136 (95 ~ 178) 84
8970 12:43:59.909468 iDelay=195, Bit 1, Center 130 (87 ~ 174) 88
8971 12:43:59.912370 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8972 12:43:59.915338 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8973 12:43:59.919130 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8974 12:43:59.922177 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8975 12:43:59.925422 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8976 12:43:59.932458 iDelay=195, Bit 7, Center 132 (87 ~ 178) 92
8977 12:43:59.935874 iDelay=195, Bit 8, Center 114 (67 ~ 162) 96
8978 12:43:59.939157 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8979 12:43:59.942349 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8980 12:43:59.945864 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8981 12:43:59.952199 iDelay=195, Bit 12, Center 140 (91 ~ 190) 100
8982 12:43:59.955441 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8983 12:43:59.959325 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8984 12:43:59.962211 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8985 12:43:59.962638 ==
8986 12:43:59.965512 Dram Type= 6, Freq= 0, CH_1, rank 1
8987 12:43:59.968925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8988 12:43:59.972061 ==
8989 12:43:59.972488 DQS Delay:
8990 12:43:59.972827 DQS0 = 0, DQS1 = 0
8991 12:43:59.975749 DQM Delay:
8992 12:43:59.976268 DQM0 = 133, DQM1 = 130
8993 12:43:59.978760 DQ Delay:
8994 12:43:59.982143 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =130
8995 12:43:59.985603 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =132
8996 12:43:59.988622 DQ8 =114, DQ9 =118, DQ10 =132, DQ11 =126
8997 12:43:59.991921 DQ12 =140, DQ13 =138, DQ14 =138, DQ15 =140
8998 12:43:59.992371
8999 12:43:59.992704
9000 12:43:59.993019
9001 12:43:59.995173 [DramC_TX_OE_Calibration] TA2
9002 12:43:59.998721 Original DQ_B0 (3 6) =30, OEN = 27
9003 12:44:00.002205 Original DQ_B1 (3 6) =30, OEN = 27
9004 12:44:00.005415 24, 0x0, End_B0=24 End_B1=24
9005 12:44:00.005850 25, 0x0, End_B0=25 End_B1=25
9006 12:44:00.009100 26, 0x0, End_B0=26 End_B1=26
9007 12:44:00.011963 27, 0x0, End_B0=27 End_B1=27
9008 12:44:00.015152 28, 0x0, End_B0=28 End_B1=28
9009 12:44:00.015589 29, 0x0, End_B0=29 End_B1=29
9010 12:44:00.018680 30, 0x0, End_B0=30 End_B1=30
9011 12:44:00.021719 31, 0x4141, End_B0=30 End_B1=30
9012 12:44:00.025215 Byte0 end_step=30 best_step=27
9013 12:44:00.028988 Byte1 end_step=30 best_step=27
9014 12:44:00.031871 Byte0 TX OE(2T, 0.5T) = (3, 3)
9015 12:44:00.035267 Byte1 TX OE(2T, 0.5T) = (3, 3)
9016 12:44:00.035792
9017 12:44:00.036131
9018 12:44:00.041852 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
9019 12:44:00.045306 CH1 RK1: MR19=303, MR18=1C07
9020 12:44:00.051644 CH1_RK1: MR19=0x303, MR18=0x1C07, DQSOSC=395, MR23=63, INC=23, DEC=15
9021 12:44:00.055058 [RxdqsGatingPostProcess] freq 1600
9022 12:44:00.058079 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9023 12:44:00.061774 best DQS0 dly(2T, 0.5T) = (1, 1)
9024 12:44:00.065323 best DQS1 dly(2T, 0.5T) = (1, 1)
9025 12:44:00.068616 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9026 12:44:00.071484 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9027 12:44:00.075006 best DQS0 dly(2T, 0.5T) = (1, 1)
9028 12:44:00.078387 best DQS1 dly(2T, 0.5T) = (1, 1)
9029 12:44:00.082019 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9030 12:44:00.085236 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9031 12:44:00.088165 Pre-setting of DQS Precalculation
9032 12:44:00.091395 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9033 12:44:00.098416 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9034 12:44:00.104723 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9035 12:44:00.108400
9036 12:44:00.108992
9037 12:44:00.109367 [Calibration Summary] 3200 Mbps
9038 12:44:00.111213 CH 0, Rank 0
9039 12:44:00.111677 SW Impedance : PASS
9040 12:44:00.114611 DUTY Scan : NO K
9041 12:44:00.118250 ZQ Calibration : PASS
9042 12:44:00.118830 Jitter Meter : NO K
9043 12:44:00.121146 CBT Training : PASS
9044 12:44:00.124651 Write leveling : PASS
9045 12:44:00.125118 RX DQS gating : PASS
9046 12:44:00.128187 RX DQ/DQS(RDDQC) : PASS
9047 12:44:00.131458 TX DQ/DQS : PASS
9048 12:44:00.132034 RX DATLAT : PASS
9049 12:44:00.134796 RX DQ/DQS(Engine): PASS
9050 12:44:00.137781 TX OE : PASS
9051 12:44:00.138299 All Pass.
9052 12:44:00.138674
9053 12:44:00.139020 CH 0, Rank 1
9054 12:44:00.141335 SW Impedance : PASS
9055 12:44:00.144791 DUTY Scan : NO K
9056 12:44:00.145364 ZQ Calibration : PASS
9057 12:44:00.148164 Jitter Meter : NO K
9058 12:44:00.151454 CBT Training : PASS
9059 12:44:00.151927 Write leveling : PASS
9060 12:44:00.154864 RX DQS gating : PASS
9061 12:44:00.155443 RX DQ/DQS(RDDQC) : PASS
9062 12:44:00.158154 TX DQ/DQS : PASS
9063 12:44:00.161595 RX DATLAT : PASS
9064 12:44:00.162210 RX DQ/DQS(Engine): PASS
9065 12:44:00.164745 TX OE : PASS
9066 12:44:00.165323 All Pass.
9067 12:44:00.165698
9068 12:44:00.168219 CH 1, Rank 0
9069 12:44:00.168803 SW Impedance : PASS
9070 12:44:00.171324 DUTY Scan : NO K
9071 12:44:00.174489 ZQ Calibration : PASS
9072 12:44:00.174958 Jitter Meter : NO K
9073 12:44:00.178419 CBT Training : PASS
9074 12:44:00.181266 Write leveling : PASS
9075 12:44:00.181840 RX DQS gating : PASS
9076 12:44:00.184329 RX DQ/DQS(RDDQC) : PASS
9077 12:44:00.187701 TX DQ/DQS : PASS
9078 12:44:00.188274 RX DATLAT : PASS
9079 12:44:00.191351 RX DQ/DQS(Engine): PASS
9080 12:44:00.194902 TX OE : PASS
9081 12:44:00.195475 All Pass.
9082 12:44:00.195851
9083 12:44:00.196198 CH 1, Rank 1
9084 12:44:00.197851 SW Impedance : PASS
9085 12:44:00.201229 DUTY Scan : NO K
9086 12:44:00.201804 ZQ Calibration : PASS
9087 12:44:00.204788 Jitter Meter : NO K
9088 12:44:00.205364 CBT Training : PASS
9089 12:44:00.207594 Write leveling : PASS
9090 12:44:00.211333 RX DQS gating : PASS
9091 12:44:00.211906 RX DQ/DQS(RDDQC) : PASS
9092 12:44:00.214416 TX DQ/DQS : PASS
9093 12:44:00.217646 RX DATLAT : PASS
9094 12:44:00.218270 RX DQ/DQS(Engine): PASS
9095 12:44:00.221321 TX OE : PASS
9096 12:44:00.221910 All Pass.
9097 12:44:00.222340
9098 12:44:00.224336 DramC Write-DBI on
9099 12:44:00.227913 PER_BANK_REFRESH: Hybrid Mode
9100 12:44:00.228490 TX_TRACKING: ON
9101 12:44:00.238092 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9102 12:44:00.244741 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9103 12:44:00.251177 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9104 12:44:00.254589 [FAST_K] Save calibration result to emmc
9105 12:44:00.257487 sync common calibartion params.
9106 12:44:00.260976 sync cbt_mode0:1, 1:1
9107 12:44:00.264720 dram_init: ddr_geometry: 2
9108 12:44:00.265305 dram_init: ddr_geometry: 2
9109 12:44:00.267873 dram_init: ddr_geometry: 2
9110 12:44:00.271295 0:dram_rank_size:100000000
9111 12:44:00.274283 1:dram_rank_size:100000000
9112 12:44:00.278122 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9113 12:44:00.281220 DFS_SHUFFLE_HW_MODE: ON
9114 12:44:00.284175 dramc_set_vcore_voltage set vcore to 725000
9115 12:44:00.287788 Read voltage for 1600, 0
9116 12:44:00.288365 Vio18 = 0
9117 12:44:00.288738 Vcore = 725000
9118 12:44:00.291120 Vdram = 0
9119 12:44:00.291586 Vddq = 0
9120 12:44:00.291953 Vmddr = 0
9121 12:44:00.294444 switch to 3200 Mbps bootup
9122 12:44:00.297755 [DramcRunTimeConfig]
9123 12:44:00.298364 PHYPLL
9124 12:44:00.298758 DPM_CONTROL_AFTERK: ON
9125 12:44:00.300934 PER_BANK_REFRESH: ON
9126 12:44:00.304441 REFRESH_OVERHEAD_REDUCTION: ON
9127 12:44:00.305007 CMD_PICG_NEW_MODE: OFF
9128 12:44:00.307330 XRTWTW_NEW_MODE: ON
9129 12:44:00.307799 XRTRTR_NEW_MODE: ON
9130 12:44:00.311272 TX_TRACKING: ON
9131 12:44:00.311871 RDSEL_TRACKING: OFF
9132 12:44:00.314410 DQS Precalculation for DVFS: ON
9133 12:44:00.317472 RX_TRACKING: OFF
9134 12:44:00.317962 HW_GATING DBG: ON
9135 12:44:00.321231 ZQCS_ENABLE_LP4: ON
9136 12:44:00.321816 RX_PICG_NEW_MODE: ON
9137 12:44:00.324298 TX_PICG_NEW_MODE: ON
9138 12:44:00.327964 ENABLE_RX_DCM_DPHY: ON
9139 12:44:00.328539 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9140 12:44:00.330941 DUMMY_READ_FOR_TRACKING: OFF
9141 12:44:00.334220 !!! SPM_CONTROL_AFTERK: OFF
9142 12:44:00.337383 !!! SPM could not control APHY
9143 12:44:00.337859 IMPEDANCE_TRACKING: ON
9144 12:44:00.340987 TEMP_SENSOR: ON
9145 12:44:00.341562 HW_SAVE_FOR_SR: OFF
9146 12:44:00.344178 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9147 12:44:00.350875 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9148 12:44:00.351455 Read ODT Tracking: ON
9149 12:44:00.354319 Refresh Rate DeBounce: ON
9150 12:44:00.354898 DFS_NO_QUEUE_FLUSH: ON
9151 12:44:00.357369 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9152 12:44:00.360747 ENABLE_DFS_RUNTIME_MRW: OFF
9153 12:44:00.363983 DDR_RESERVE_NEW_MODE: ON
9154 12:44:00.364561 MR_CBT_SWITCH_FREQ: ON
9155 12:44:00.366910 =========================
9156 12:44:00.386813 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9157 12:44:00.389884 dram_init: ddr_geometry: 2
9158 12:44:00.408138 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9159 12:44:00.411559 dram_init: dram init end (result: 0)
9160 12:44:00.418517 DRAM-K: Full calibration passed in 24510 msecs
9161 12:44:00.421421 MRC: failed to locate region type 0.
9162 12:44:00.422031 DRAM rank0 size:0x100000000,
9163 12:44:00.425133 DRAM rank1 size=0x100000000
9164 12:44:00.435190 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9165 12:44:00.441404 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9166 12:44:00.447952 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9167 12:44:00.454725 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9168 12:44:00.457870 DRAM rank0 size:0x100000000,
9169 12:44:00.461473 DRAM rank1 size=0x100000000
9170 12:44:00.462096 CBMEM:
9171 12:44:00.464780 IMD: root @ 0xfffff000 254 entries.
9172 12:44:00.468116 IMD: root @ 0xffffec00 62 entries.
9173 12:44:00.471316 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9174 12:44:00.477677 WARNING: RO_VPD is uninitialized or empty.
9175 12:44:00.481010 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9176 12:44:00.488196 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9177 12:44:00.501192 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9178 12:44:00.512354 BS: romstage times (exec / console): total (unknown) / 24016 ms
9179 12:44:00.512939
9180 12:44:00.513315
9181 12:44:00.522801 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9182 12:44:00.526006 ARM64: Exception handlers installed.
9183 12:44:00.529421 ARM64: Testing exception
9184 12:44:00.532379 ARM64: Done test exception
9185 12:44:00.532955 Enumerating buses...
9186 12:44:00.535863 Show all devs... Before device enumeration.
9187 12:44:00.538845 Root Device: enabled 1
9188 12:44:00.542618 CPU_CLUSTER: 0: enabled 1
9189 12:44:00.543223 CPU: 00: enabled 1
9190 12:44:00.545854 Compare with tree...
9191 12:44:00.546479 Root Device: enabled 1
9192 12:44:00.549140 CPU_CLUSTER: 0: enabled 1
9193 12:44:00.552344 CPU: 00: enabled 1
9194 12:44:00.552926 Root Device scanning...
9195 12:44:00.555666 scan_static_bus for Root Device
9196 12:44:00.558969 CPU_CLUSTER: 0 enabled
9197 12:44:00.562539 scan_static_bus for Root Device done
9198 12:44:00.565639 scan_bus: bus Root Device finished in 8 msecs
9199 12:44:00.566155 done
9200 12:44:00.572093 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9201 12:44:00.575404 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9202 12:44:00.582377 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9203 12:44:00.585319 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9204 12:44:00.588883 Allocating resources...
9205 12:44:00.591978 Reading resources...
9206 12:44:00.595590 Root Device read_resources bus 0 link: 0
9207 12:44:00.596197 DRAM rank0 size:0x100000000,
9208 12:44:00.598811 DRAM rank1 size=0x100000000
9209 12:44:00.602286 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9210 12:44:00.605586 CPU: 00 missing read_resources
9211 12:44:00.608954 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9212 12:44:00.615462 Root Device read_resources bus 0 link: 0 done
9213 12:44:00.616042 Done reading resources.
9214 12:44:00.622098 Show resources in subtree (Root Device)...After reading.
9215 12:44:00.625429 Root Device child on link 0 CPU_CLUSTER: 0
9216 12:44:00.628615 CPU_CLUSTER: 0 child on link 0 CPU: 00
9217 12:44:00.638623 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9218 12:44:00.639110 CPU: 00
9219 12:44:00.641721 Root Device assign_resources, bus 0 link: 0
9220 12:44:00.645193 CPU_CLUSTER: 0 missing set_resources
9221 12:44:00.648171 Root Device assign_resources, bus 0 link: 0 done
9222 12:44:00.651837 Done setting resources.
9223 12:44:00.658398 Show resources in subtree (Root Device)...After assigning values.
9224 12:44:00.661659 Root Device child on link 0 CPU_CLUSTER: 0
9225 12:44:00.665188 CPU_CLUSTER: 0 child on link 0 CPU: 00
9226 12:44:00.675190 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9227 12:44:00.675684 CPU: 00
9228 12:44:00.678351 Done allocating resources.
9229 12:44:00.681776 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9230 12:44:00.685103 Enabling resources...
9231 12:44:00.685663 done.
9232 12:44:00.691692 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9233 12:44:00.692032 Initializing devices...
9234 12:44:00.695092 Root Device init
9235 12:44:00.695425 init hardware done!
9236 12:44:00.698037 0x00000018: ctrlr->caps
9237 12:44:00.701740 52.000 MHz: ctrlr->f_max
9238 12:44:00.702248 0.400 MHz: ctrlr->f_min
9239 12:44:00.705068 0x40ff8080: ctrlr->voltages
9240 12:44:00.705512 sclk: 390625
9241 12:44:00.708449 Bus Width = 1
9242 12:44:00.708889 sclk: 390625
9243 12:44:00.709163 Bus Width = 1
9244 12:44:00.712021 Early init status = 3
9245 12:44:00.714876 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9246 12:44:00.720789 in-header: 03 fc 00 00 01 00 00 00
9247 12:44:00.724138 in-data: 00
9248 12:44:00.726950 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9249 12:44:00.732600 in-header: 03 fd 00 00 00 00 00 00
9250 12:44:00.735967 in-data:
9251 12:44:00.739178 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9252 12:44:00.743625 in-header: 03 fc 00 00 01 00 00 00
9253 12:44:00.746847 in-data: 00
9254 12:44:00.750039 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9255 12:44:00.756243 in-header: 03 fd 00 00 00 00 00 00
9256 12:44:00.759031 in-data:
9257 12:44:00.762347 [SSUSB] Setting up USB HOST controller...
9258 12:44:00.765727 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9259 12:44:00.768874 [SSUSB] phy power-on done.
9260 12:44:00.772570 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9261 12:44:00.779072 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9262 12:44:00.782483 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9263 12:44:00.789056 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9264 12:44:00.795757 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9265 12:44:00.802419 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9266 12:44:00.808720 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9267 12:44:00.815569 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9268 12:44:00.818567 SPM: binary array size = 0x9dc
9269 12:44:00.822502 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9270 12:44:00.829036 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9271 12:44:00.835453 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9272 12:44:00.838688 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9273 12:44:00.845454 configure_display: Starting display init
9274 12:44:00.879082 anx7625_power_on_init: Init interface.
9275 12:44:00.882431 anx7625_disable_pd_protocol: Disabled PD feature.
9276 12:44:00.885607 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9277 12:44:00.913790 anx7625_start_dp_work: Secure OCM version=00
9278 12:44:00.916454 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9279 12:44:00.931587 sp_tx_get_edid_block: EDID Block = 1
9280 12:44:01.033905 Extracted contents:
9281 12:44:01.037265 header: 00 ff ff ff ff ff ff 00
9282 12:44:01.040459 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9283 12:44:01.044206 version: 01 04
9284 12:44:01.047536 basic params: 95 1f 11 78 0a
9285 12:44:01.050808 chroma info: 76 90 94 55 54 90 27 21 50 54
9286 12:44:01.054115 established: 00 00 00
9287 12:44:01.060541 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9288 12:44:01.063814 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9289 12:44:01.070586 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9290 12:44:01.077095 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9291 12:44:01.084002 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9292 12:44:01.086844 extensions: 00
9293 12:44:01.087177 checksum: fb
9294 12:44:01.087442
9295 12:44:01.090322 Manufacturer: IVO Model 57d Serial Number 0
9296 12:44:01.093585 Made week 0 of 2020
9297 12:44:01.093918 EDID version: 1.4
9298 12:44:01.096972 Digital display
9299 12:44:01.100404 6 bits per primary color channel
9300 12:44:01.100780 DisplayPort interface
9301 12:44:01.103501 Maximum image size: 31 cm x 17 cm
9302 12:44:01.106997 Gamma: 220%
9303 12:44:01.107517 Check DPMS levels
9304 12:44:01.109931 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9305 12:44:01.113556 First detailed timing is preferred timing
9306 12:44:01.117029 Established timings supported:
9307 12:44:01.120427 Standard timings supported:
9308 12:44:01.123920 Detailed timings
9309 12:44:01.127302 Hex of detail: 383680a07038204018303c0035ae10000019
9310 12:44:01.130014 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9311 12:44:01.137046 0780 0798 07c8 0820 hborder 0
9312 12:44:01.140329 0438 043b 0447 0458 vborder 0
9313 12:44:01.143689 -hsync -vsync
9314 12:44:01.144237 Did detailed timing
9315 12:44:01.147059 Hex of detail: 000000000000000000000000000000000000
9316 12:44:01.150038 Manufacturer-specified data, tag 0
9317 12:44:01.157030 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9318 12:44:01.157583 ASCII string: InfoVision
9319 12:44:01.163847 Hex of detail: 000000fe00523134304e574635205248200a
9320 12:44:01.167297 ASCII string: R140NWF5 RH
9321 12:44:01.167849 Checksum
9322 12:44:01.168215 Checksum: 0xfb (valid)
9323 12:44:01.173833 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9324 12:44:01.177218 DSI data_rate: 832800000 bps
9325 12:44:01.180247 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9326 12:44:01.184098 anx7625_parse_edid: pixelclock(138800).
9327 12:44:01.190090 hactive(1920), hsync(48), hfp(24), hbp(88)
9328 12:44:01.193847 vactive(1080), vsync(12), vfp(3), vbp(17)
9329 12:44:01.197058 anx7625_dsi_config: config dsi.
9330 12:44:01.203763 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9331 12:44:01.216051 anx7625_dsi_config: success to config DSI
9332 12:44:01.219589 anx7625_dp_start: MIPI phy setup OK.
9333 12:44:01.223069 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9334 12:44:01.226591 mtk_ddp_mode_set invalid vrefresh 60
9335 12:44:01.229839 main_disp_path_setup
9336 12:44:01.230434 ovl_layer_smi_id_en
9337 12:44:01.232687 ovl_layer_smi_id_en
9338 12:44:01.233243 ccorr_config
9339 12:44:01.233603 aal_config
9340 12:44:01.236231 gamma_config
9341 12:44:01.236785 postmask_config
9342 12:44:01.239432 dither_config
9343 12:44:01.243000 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9344 12:44:01.249773 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9345 12:44:01.252875 Root Device init finished in 555 msecs
9346 12:44:01.253431 CPU_CLUSTER: 0 init
9347 12:44:01.262853 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9348 12:44:01.266351 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9349 12:44:01.269638 APU_MBOX 0x190000b0 = 0x10001
9350 12:44:01.272947 APU_MBOX 0x190001b0 = 0x10001
9351 12:44:01.276317 APU_MBOX 0x190005b0 = 0x10001
9352 12:44:01.279594 APU_MBOX 0x190006b0 = 0x10001
9353 12:44:01.282885 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9354 12:44:01.295370 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9355 12:44:01.307573 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9356 12:44:01.314299 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9357 12:44:01.326129 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9358 12:44:01.335044 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9359 12:44:01.338573 CPU_CLUSTER: 0 init finished in 81 msecs
9360 12:44:01.341655 Devices initialized
9361 12:44:01.345302 Show all devs... After init.
9362 12:44:01.345776 Root Device: enabled 1
9363 12:44:01.348219 CPU_CLUSTER: 0: enabled 1
9364 12:44:01.351420 CPU: 00: enabled 1
9365 12:44:01.354972 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9366 12:44:01.358689 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9367 12:44:01.362081 ELOG: NV offset 0x57f000 size 0x1000
9368 12:44:01.368300 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9369 12:44:01.375216 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9370 12:44:01.378757 ELOG: Event(17) added with size 13 at 2024-02-05 12:43:21 UTC
9371 12:44:01.381382 out: cmd=0x121: 03 db 21 01 00 00 00 00
9372 12:44:01.385265 in-header: 03 2a 00 00 2c 00 00 00
9373 12:44:01.398524 in-data: 35 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9374 12:44:01.405105 ELOG: Event(A1) added with size 10 at 2024-02-05 12:43:21 UTC
9375 12:44:01.411406 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9376 12:44:01.418163 ELOG: Event(A0) added with size 9 at 2024-02-05 12:43:21 UTC
9377 12:44:01.421630 elog_add_boot_reason: Logged dev mode boot
9378 12:44:01.425150 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9379 12:44:01.428595 Finalize devices...
9380 12:44:01.429081 Devices finalized
9381 12:44:01.435484 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9382 12:44:01.438520 Writing coreboot table at 0xffe64000
9383 12:44:01.441437 0. 000000000010a000-0000000000113fff: RAMSTAGE
9384 12:44:01.444735 1. 0000000040000000-00000000400fffff: RAM
9385 12:44:01.448385 2. 0000000040100000-000000004032afff: RAMSTAGE
9386 12:44:01.455137 3. 000000004032b000-00000000545fffff: RAM
9387 12:44:01.458400 4. 0000000054600000-000000005465ffff: BL31
9388 12:44:01.461718 5. 0000000054660000-00000000ffe63fff: RAM
9389 12:44:01.465059 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9390 12:44:01.471469 7. 0000000100000000-000000023fffffff: RAM
9391 12:44:01.471959 Passing 5 GPIOs to payload:
9392 12:44:01.478118 NAME | PORT | POLARITY | VALUE
9393 12:44:01.481503 EC in RW | 0x000000aa | low | undefined
9394 12:44:01.487927 EC interrupt | 0x00000005 | low | undefined
9395 12:44:01.491427 TPM interrupt | 0x000000ab | high | undefined
9396 12:44:01.494885 SD card detect | 0x00000011 | high | undefined
9397 12:44:01.501400 speaker enable | 0x00000093 | high | undefined
9398 12:44:01.504445 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9399 12:44:01.507826 in-header: 03 f9 00 00 02 00 00 00
9400 12:44:01.508281 in-data: 02 00
9401 12:44:01.511473 ADC[4]: Raw value=901032 ID=7
9402 12:44:01.514674 ADC[3]: Raw value=213179 ID=1
9403 12:44:01.515112 RAM Code: 0x71
9404 12:44:01.517968 ADC[6]: Raw value=74502 ID=0
9405 12:44:01.521150 ADC[5]: Raw value=212072 ID=1
9406 12:44:01.521581 SKU Code: 0x1
9407 12:44:01.527951 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum d248
9408 12:44:01.531488 coreboot table: 964 bytes.
9409 12:44:01.534342 IMD ROOT 0. 0xfffff000 0x00001000
9410 12:44:01.537672 IMD SMALL 1. 0xffffe000 0x00001000
9411 12:44:01.541383 RO MCACHE 2. 0xffffc000 0x00001104
9412 12:44:01.544757 CONSOLE 3. 0xfff7c000 0x00080000
9413 12:44:01.547549 FMAP 4. 0xfff7b000 0x00000452
9414 12:44:01.550865 TIME STAMP 5. 0xfff7a000 0x00000910
9415 12:44:01.554660 VBOOT WORK 6. 0xfff66000 0x00014000
9416 12:44:01.557499 RAMOOPS 7. 0xffe66000 0x00100000
9417 12:44:01.560830 COREBOOT 8. 0xffe64000 0x00002000
9418 12:44:01.561273 IMD small region:
9419 12:44:01.564496 IMD ROOT 0. 0xffffec00 0x00000400
9420 12:44:01.567690 VPD 1. 0xffffeb80 0x0000006c
9421 12:44:01.570993 MMC STATUS 2. 0xffffeb60 0x00000004
9422 12:44:01.577207 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9423 12:44:01.581010 Probing TPM: done!
9424 12:44:01.584717 Connected to device vid:did:rid of 1ae0:0028:00
9425 12:44:01.594428 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9426 12:44:01.598014 Initialized TPM device CR50 revision 0
9427 12:44:01.601761 Checking cr50 for pending updates
9428 12:44:01.604567 Reading cr50 TPM mode
9429 12:44:01.613619 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9430 12:44:01.619586 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9431 12:44:01.660307 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9432 12:44:01.663182 Checking segment from ROM address 0x40100000
9433 12:44:01.666895 Checking segment from ROM address 0x4010001c
9434 12:44:01.673139 Loading segment from ROM address 0x40100000
9435 12:44:01.673689 code (compression=0)
9436 12:44:01.683543 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9437 12:44:01.690066 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9438 12:44:01.690654 it's not compressed!
9439 12:44:01.696595 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9440 12:44:01.700111 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9441 12:44:01.720222 Loading segment from ROM address 0x4010001c
9442 12:44:01.720691 Entry Point 0x80000000
9443 12:44:01.724023 Loaded segments
9444 12:44:01.727203 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9445 12:44:01.733596 Jumping to boot code at 0x80000000(0xffe64000)
9446 12:44:01.740434 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9447 12:44:01.746762 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9448 12:44:01.754586 read SPI 0x8eb68 0x74a8: 3222 us, 9268 KB/s, 74.144 Mbps
9449 12:44:01.758037 Checking segment from ROM address 0x40100000
9450 12:44:01.761663 Checking segment from ROM address 0x4010001c
9451 12:44:01.768359 Loading segment from ROM address 0x40100000
9452 12:44:01.768932 code (compression=1)
9453 12:44:01.775356 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9454 12:44:01.784961 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9455 12:44:01.785535 using LZMA
9456 12:44:01.793502 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9457 12:44:01.800252 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9458 12:44:01.803638 Loading segment from ROM address 0x4010001c
9459 12:44:01.804209 Entry Point 0x54601000
9460 12:44:01.806414 Loaded segments
9461 12:44:01.810249 NOTICE: MT8192 bl31_setup
9462 12:44:01.817010 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9463 12:44:01.820159 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9464 12:44:01.823496 WARNING: region 0:
9465 12:44:01.826822 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9466 12:44:01.827399 WARNING: region 1:
9467 12:44:01.833481 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9468 12:44:01.837083 WARNING: region 2:
9469 12:44:01.840231 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9470 12:44:01.843359 WARNING: region 3:
9471 12:44:01.847061 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9472 12:44:01.850502 WARNING: region 4:
9473 12:44:01.853226 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9474 12:44:01.856924 WARNING: region 5:
9475 12:44:01.860383 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9476 12:44:01.863239 WARNING: region 6:
9477 12:44:01.866609 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9478 12:44:01.867113 WARNING: region 7:
9479 12:44:01.873735 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9480 12:44:01.880182 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9481 12:44:01.884043 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9482 12:44:01.887277 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9483 12:44:01.894093 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9484 12:44:01.896937 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9485 12:44:01.900263 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9486 12:44:01.906804 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9487 12:44:01.910493 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9488 12:44:01.916804 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9489 12:44:01.920232 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9490 12:44:01.923460 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9491 12:44:01.930495 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9492 12:44:01.933739 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9493 12:44:01.937504 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9494 12:44:01.944036 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9495 12:44:01.947086 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9496 12:44:01.950063 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9497 12:44:01.957091 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9498 12:44:01.960596 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9499 12:44:01.967202 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9500 12:44:01.970108 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9501 12:44:01.973378 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9502 12:44:01.980638 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9503 12:44:01.983580 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9504 12:44:01.990627 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9505 12:44:01.993910 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9506 12:44:01.997212 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9507 12:44:02.003749 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9508 12:44:02.007199 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9509 12:44:02.010869 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9510 12:44:02.017424 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9511 12:44:02.020261 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9512 12:44:02.023796 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9513 12:44:02.030722 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9514 12:44:02.033653 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9515 12:44:02.037119 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9516 12:44:02.040558 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9517 12:44:02.046947 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9518 12:44:02.050602 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9519 12:44:02.053996 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9520 12:44:02.057427 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9521 12:44:02.064098 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9522 12:44:02.067306 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9523 12:44:02.070814 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9524 12:44:02.074080 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9525 12:44:02.080772 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9526 12:44:02.084011 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9527 12:44:02.087086 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9528 12:44:02.094100 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9529 12:44:02.097602 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9530 12:44:02.100924 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9531 12:44:02.107666 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9532 12:44:02.110869 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9533 12:44:02.117340 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9534 12:44:02.120743 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9535 12:44:02.126985 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9536 12:44:02.130800 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9537 12:44:02.133694 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9538 12:44:02.140723 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9539 12:44:02.144330 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9540 12:44:02.150725 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9541 12:44:02.153901 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9542 12:44:02.160876 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9543 12:44:02.163810 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9544 12:44:02.167743 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9545 12:44:02.174052 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9546 12:44:02.177402 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9547 12:44:02.184026 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9548 12:44:02.187491 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9549 12:44:02.194069 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9550 12:44:02.197588 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9551 12:44:02.201194 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9552 12:44:02.207458 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9553 12:44:02.211231 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9554 12:44:02.217493 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9555 12:44:02.220913 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9556 12:44:02.227381 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9557 12:44:02.230666 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9558 12:44:02.234124 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9559 12:44:02.240903 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9560 12:44:02.244658 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9561 12:44:02.251176 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9562 12:44:02.254591 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9563 12:44:02.261084 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9564 12:44:02.264564 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9565 12:44:02.267925 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9566 12:44:02.274431 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9567 12:44:02.277694 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9568 12:44:02.284377 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9569 12:44:02.287974 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9570 12:44:02.290953 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9571 12:44:02.297587 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9572 12:44:02.300968 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9573 12:44:02.307739 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9574 12:44:02.310854 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9575 12:44:02.318094 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9576 12:44:02.320801 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9577 12:44:02.324154 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9578 12:44:02.327742 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9579 12:44:02.334269 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9580 12:44:02.337917 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9581 12:44:02.341329 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9582 12:44:02.347878 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9583 12:44:02.350920 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9584 12:44:02.357785 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9585 12:44:02.361497 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9586 12:44:02.364761 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9587 12:44:02.371123 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9588 12:44:02.374751 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9589 12:44:02.381400 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9590 12:44:02.385121 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9591 12:44:02.387929 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9592 12:44:02.394194 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9593 12:44:02.397809 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9594 12:44:02.404652 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9595 12:44:02.407971 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9596 12:44:02.410977 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9597 12:44:02.414448 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9598 12:44:02.421409 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9599 12:44:02.424718 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9600 12:44:02.427795 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9601 12:44:02.431098 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9602 12:44:02.438149 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9603 12:44:02.441029 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9604 12:44:02.444608 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9605 12:44:02.451093 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9606 12:44:02.454768 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9607 12:44:02.461036 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9608 12:44:02.464370 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9609 12:44:02.467759 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9610 12:44:02.474422 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9611 12:44:02.477878 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9612 12:44:02.480991 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9613 12:44:02.488053 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9614 12:44:02.491237 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9615 12:44:02.497528 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9616 12:44:02.500685 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9617 12:44:02.504325 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9618 12:44:02.510888 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9619 12:44:02.514270 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9620 12:44:02.520646 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9621 12:44:02.524150 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9622 12:44:02.527733 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9623 12:44:02.534609 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9624 12:44:02.537613 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9625 12:44:02.541016 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9626 12:44:02.547618 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9627 12:44:02.551154 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9628 12:44:02.558078 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9629 12:44:02.561255 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9630 12:44:02.564829 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9631 12:44:02.571318 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9632 12:44:02.574204 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9633 12:44:02.581130 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9634 12:44:02.584693 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9635 12:44:02.587982 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9636 12:44:02.594250 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9637 12:44:02.597922 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9638 12:44:02.601255 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9639 12:44:02.607834 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9640 12:44:02.610764 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9641 12:44:02.617757 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9642 12:44:02.620876 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9643 12:44:02.624235 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9644 12:44:02.630800 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9645 12:44:02.634330 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9646 12:44:02.641261 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9647 12:44:02.644681 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9648 12:44:02.647913 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9649 12:44:02.654519 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9650 12:44:02.657504 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9651 12:44:02.664244 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9652 12:44:02.667338 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9653 12:44:02.670684 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9654 12:44:02.677365 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9655 12:44:02.681068 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9656 12:44:02.687402 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9657 12:44:02.690701 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9658 12:44:02.693781 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9659 12:44:02.700335 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9660 12:44:02.703917 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9661 12:44:02.707308 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9662 12:44:02.714086 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9663 12:44:02.717386 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9664 12:44:02.723951 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9665 12:44:02.727076 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9666 12:44:02.730231 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9667 12:44:02.736994 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9668 12:44:02.740414 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9669 12:44:02.747205 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9670 12:44:02.750594 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9671 12:44:02.753759 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9672 12:44:02.760582 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9673 12:44:02.763741 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9674 12:44:02.770882 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9675 12:44:02.774301 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9676 12:44:02.780564 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9677 12:44:02.784025 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9678 12:44:02.787108 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9679 12:44:02.793617 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9680 12:44:02.796921 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9681 12:44:02.803652 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9682 12:44:02.806812 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9683 12:44:02.810396 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9684 12:44:02.817181 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9685 12:44:02.820327 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9686 12:44:02.826987 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9687 12:44:02.830076 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9688 12:44:02.836776 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9689 12:44:02.839833 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9690 12:44:02.843000 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9691 12:44:02.849920 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9692 12:44:02.853349 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9693 12:44:02.860089 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9694 12:44:02.862875 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9695 12:44:02.866501 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9696 12:44:02.873221 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9697 12:44:02.876500 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9698 12:44:02.883269 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9699 12:44:02.886799 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9700 12:44:02.893160 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9701 12:44:02.896621 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9702 12:44:02.899812 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9703 12:44:02.906216 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9704 12:44:02.909871 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9705 12:44:02.916192 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9706 12:44:02.919336 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9707 12:44:02.922823 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9708 12:44:02.929673 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9709 12:44:02.933178 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9710 12:44:02.936360 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9711 12:44:02.939952 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9712 12:44:02.946344 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9713 12:44:02.949872 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9714 12:44:02.953006 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9715 12:44:02.959669 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9716 12:44:02.963129 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9717 12:44:02.969901 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9718 12:44:02.973038 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9719 12:44:02.976163 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9720 12:44:02.983077 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9721 12:44:02.986523 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9722 12:44:02.989468 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9723 12:44:02.996430 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9724 12:44:02.999529 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9725 12:44:03.003162 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9726 12:44:03.009730 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9727 12:44:03.013218 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9728 12:44:03.016565 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9729 12:44:03.022754 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9730 12:44:03.026277 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9731 12:44:03.032509 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9732 12:44:03.035995 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9733 12:44:03.039049 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9734 12:44:03.045581 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9735 12:44:03.049450 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9736 12:44:03.055544 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9737 12:44:03.058979 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9738 12:44:03.062000 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9739 12:44:03.069354 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9740 12:44:03.072441 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9741 12:44:03.075672 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9742 12:44:03.082381 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9743 12:44:03.085833 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9744 12:44:03.089006 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9745 12:44:03.095253 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9746 12:44:03.098848 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9747 12:44:03.105185 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9748 12:44:03.108263 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9749 12:44:03.112357 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9750 12:44:03.115203 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9751 12:44:03.121799 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9752 12:44:03.124910 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9753 12:44:03.128349 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9754 12:44:03.131645 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9755 12:44:03.135106 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9756 12:44:03.141723 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9757 12:44:03.145177 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9758 12:44:03.148209 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9759 12:44:03.151393 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9760 12:44:03.158168 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9761 12:44:03.161599 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9762 12:44:03.168302 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9763 12:44:03.171320 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9764 12:44:03.174658 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9765 12:44:03.181718 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9766 12:44:03.184796 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9767 12:44:03.191417 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9768 12:44:03.195014 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9769 12:44:03.198252 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9770 12:44:03.205057 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9771 12:44:03.208440 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9772 12:44:03.214810 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9773 12:44:03.218199 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9774 12:44:03.221534 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9775 12:44:03.227985 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9776 12:44:03.231321 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9777 12:44:03.238052 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9778 12:44:03.241470 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9779 12:44:03.244802 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9780 12:44:03.251495 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9781 12:44:03.254475 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9782 12:44:03.261253 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9783 12:44:03.264789 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9784 12:44:03.271568 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9785 12:44:03.274678 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9786 12:44:03.277574 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9787 12:44:03.284636 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9788 12:44:03.287847 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9789 12:44:03.294113 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9790 12:44:03.297559 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9791 12:44:03.300789 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9792 12:44:03.307943 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9793 12:44:03.310645 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9794 12:44:03.317442 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9795 12:44:03.320644 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9796 12:44:03.324433 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9797 12:44:03.331202 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9798 12:44:03.334188 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9799 12:44:03.341112 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9800 12:44:03.344167 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9801 12:44:03.347578 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9802 12:44:03.354080 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9803 12:44:03.357431 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9804 12:44:03.364201 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9805 12:44:03.367290 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9806 12:44:03.374460 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9807 12:44:03.377515 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9808 12:44:03.380878 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9809 12:44:03.387323 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9810 12:44:03.390540 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9811 12:44:03.397168 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9812 12:44:03.400750 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9813 12:44:03.403863 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9814 12:44:03.410743 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9815 12:44:03.414234 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9816 12:44:03.420217 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9817 12:44:03.423530 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9818 12:44:03.426885 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9819 12:44:03.433771 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9820 12:44:03.437159 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9821 12:44:03.443823 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9822 12:44:03.447211 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9823 12:44:03.453428 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9824 12:44:03.456733 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9825 12:44:03.460132 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9826 12:44:03.466882 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9827 12:44:03.470159 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9828 12:44:03.476625 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9829 12:44:03.480175 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9830 12:44:03.483210 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9831 12:44:03.490071 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9832 12:44:03.493164 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9833 12:44:03.499992 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9834 12:44:03.503503 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9835 12:44:03.506376 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9836 12:44:03.513263 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9837 12:44:03.516494 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9838 12:44:03.522842 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9839 12:44:03.526183 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9840 12:44:03.533575 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9841 12:44:03.536975 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9842 12:44:03.539740 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9843 12:44:03.546517 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9844 12:44:03.549755 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9845 12:44:03.556923 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9846 12:44:03.559489 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9847 12:44:03.566605 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9848 12:44:03.569902 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9849 12:44:03.573063 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9850 12:44:03.580008 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9851 12:44:03.583024 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9852 12:44:03.589898 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9853 12:44:03.592918 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9854 12:44:03.599668 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9855 12:44:03.602939 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9856 12:44:03.609159 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9857 12:44:03.612468 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9858 12:44:03.615792 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9859 12:44:03.622640 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9860 12:44:03.626060 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9861 12:44:03.632444 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9862 12:44:03.635878 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9863 12:44:03.642664 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9864 12:44:03.645630 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9865 12:44:03.649327 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9866 12:44:03.656218 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9867 12:44:03.658853 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9868 12:44:03.665862 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9869 12:44:03.669268 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9870 12:44:03.675443 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9871 12:44:03.679390 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9872 12:44:03.686101 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9873 12:44:03.689294 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9874 12:44:03.692515 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9875 12:44:03.699601 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9876 12:44:03.702614 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9877 12:44:03.709102 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9878 12:44:03.712914 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9879 12:44:03.718939 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9880 12:44:03.722449 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9881 12:44:03.725412 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9882 12:44:03.732115 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9883 12:44:03.735661 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9884 12:44:03.741912 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9885 12:44:03.745688 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9886 12:44:03.752382 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9887 12:44:03.755566 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9888 12:44:03.761883 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9889 12:44:03.765433 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9890 12:44:03.771927 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9891 12:44:03.775173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9892 12:44:03.782302 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9893 12:44:03.784888 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9894 12:44:03.791497 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9895 12:44:03.794951 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9896 12:44:03.798650 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9897 12:44:03.805402 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9898 12:44:03.808641 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9899 12:44:03.815122 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9900 12:44:03.818314 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9901 12:44:03.824800 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9902 12:44:03.828019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9903 12:44:03.834529 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9904 12:44:03.837711 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9905 12:44:03.844845 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9906 12:44:03.848119 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9907 12:44:03.854203 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9908 12:44:03.861016 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9909 12:44:03.864634 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9910 12:44:03.871295 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9911 12:44:03.874823 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9912 12:44:03.881132 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9913 12:44:03.884387 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9914 12:44:03.888117 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9915 12:44:03.891166 INFO: [APUAPC] vio 0
9916 12:44:03.894239 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9917 12:44:03.901286 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9918 12:44:03.904673 INFO: [APUAPC] D0_APC_0: 0x400510
9919 12:44:03.907976 INFO: [APUAPC] D0_APC_1: 0x0
9920 12:44:03.911487 INFO: [APUAPC] D0_APC_2: 0x1540
9921 12:44:03.912059 INFO: [APUAPC] D0_APC_3: 0x0
9922 12:44:03.914245 INFO: [APUAPC] D1_APC_0: 0xffffffff
9923 12:44:03.917617 INFO: [APUAPC] D1_APC_1: 0xffffffff
9924 12:44:03.920731 INFO: [APUAPC] D1_APC_2: 0x3fffff
9925 12:44:03.924731 INFO: [APUAPC] D1_APC_3: 0x0
9926 12:44:03.927783 INFO: [APUAPC] D2_APC_0: 0xffffffff
9927 12:44:03.930684 INFO: [APUAPC] D2_APC_1: 0xffffffff
9928 12:44:03.934218 INFO: [APUAPC] D2_APC_2: 0x3fffff
9929 12:44:03.937813 INFO: [APUAPC] D2_APC_3: 0x0
9930 12:44:03.941064 INFO: [APUAPC] D3_APC_0: 0xffffffff
9931 12:44:03.944653 INFO: [APUAPC] D3_APC_1: 0xffffffff
9932 12:44:03.947610 INFO: [APUAPC] D3_APC_2: 0x3fffff
9933 12:44:03.951010 INFO: [APUAPC] D3_APC_3: 0x0
9934 12:44:03.954290 INFO: [APUAPC] D4_APC_0: 0xffffffff
9935 12:44:03.957661 INFO: [APUAPC] D4_APC_1: 0xffffffff
9936 12:44:03.960554 INFO: [APUAPC] D4_APC_2: 0x3fffff
9937 12:44:03.964172 INFO: [APUAPC] D4_APC_3: 0x0
9938 12:44:03.967369 INFO: [APUAPC] D5_APC_0: 0xffffffff
9939 12:44:03.970824 INFO: [APUAPC] D5_APC_1: 0xffffffff
9940 12:44:03.974573 INFO: [APUAPC] D5_APC_2: 0x3fffff
9941 12:44:03.977544 INFO: [APUAPC] D5_APC_3: 0x0
9942 12:44:03.981351 INFO: [APUAPC] D6_APC_0: 0xffffffff
9943 12:44:03.984300 INFO: [APUAPC] D6_APC_1: 0xffffffff
9944 12:44:03.987639 INFO: [APUAPC] D6_APC_2: 0x3fffff
9945 12:44:03.990544 INFO: [APUAPC] D6_APC_3: 0x0
9946 12:44:03.994249 INFO: [APUAPC] D7_APC_0: 0xffffffff
9947 12:44:03.997280 INFO: [APUAPC] D7_APC_1: 0xffffffff
9948 12:44:04.000436 INFO: [APUAPC] D7_APC_2: 0x3fffff
9949 12:44:04.004293 INFO: [APUAPC] D7_APC_3: 0x0
9950 12:44:04.006989 INFO: [APUAPC] D8_APC_0: 0xffffffff
9951 12:44:04.010753 INFO: [APUAPC] D8_APC_1: 0xffffffff
9952 12:44:04.013989 INFO: [APUAPC] D8_APC_2: 0x3fffff
9953 12:44:04.017345 INFO: [APUAPC] D8_APC_3: 0x0
9954 12:44:04.020657 INFO: [APUAPC] D9_APC_0: 0xffffffff
9955 12:44:04.023773 INFO: [APUAPC] D9_APC_1: 0xffffffff
9956 12:44:04.027180 INFO: [APUAPC] D9_APC_2: 0x3fffff
9957 12:44:04.030808 INFO: [APUAPC] D9_APC_3: 0x0
9958 12:44:04.033654 INFO: [APUAPC] D10_APC_0: 0xffffffff
9959 12:44:04.036872 INFO: [APUAPC] D10_APC_1: 0xffffffff
9960 12:44:04.040280 INFO: [APUAPC] D10_APC_2: 0x3fffff
9961 12:44:04.043860 INFO: [APUAPC] D10_APC_3: 0x0
9962 12:44:04.047233 INFO: [APUAPC] D11_APC_0: 0xffffffff
9963 12:44:04.050236 INFO: [APUAPC] D11_APC_1: 0xffffffff
9964 12:44:04.053749 INFO: [APUAPC] D11_APC_2: 0x3fffff
9965 12:44:04.056961 INFO: [APUAPC] D11_APC_3: 0x0
9966 12:44:04.060554 INFO: [APUAPC] D12_APC_0: 0xffffffff
9967 12:44:04.063748 INFO: [APUAPC] D12_APC_1: 0xffffffff
9968 12:44:04.066738 INFO: [APUAPC] D12_APC_2: 0x3fffff
9969 12:44:04.070439 INFO: [APUAPC] D12_APC_3: 0x0
9970 12:44:04.073616 INFO: [APUAPC] D13_APC_0: 0xffffffff
9971 12:44:04.077122 INFO: [APUAPC] D13_APC_1: 0xffffffff
9972 12:44:04.080613 INFO: [APUAPC] D13_APC_2: 0x3fffff
9973 12:44:04.084038 INFO: [APUAPC] D13_APC_3: 0x0
9974 12:44:04.087093 INFO: [APUAPC] D14_APC_0: 0xffffffff
9975 12:44:04.090466 INFO: [APUAPC] D14_APC_1: 0xffffffff
9976 12:44:04.093462 INFO: [APUAPC] D14_APC_2: 0x3fffff
9977 12:44:04.096718 INFO: [APUAPC] D14_APC_3: 0x0
9978 12:44:04.100181 INFO: [APUAPC] D15_APC_0: 0xffffffff
9979 12:44:04.103311 INFO: [APUAPC] D15_APC_1: 0xffffffff
9980 12:44:04.107019 INFO: [APUAPC] D15_APC_2: 0x3fffff
9981 12:44:04.110280 INFO: [APUAPC] D15_APC_3: 0x0
9982 12:44:04.113491 INFO: [APUAPC] APC_CON: 0x4
9983 12:44:04.117039 INFO: [NOCDAPC] D0_APC_0: 0x0
9984 12:44:04.117628 INFO: [NOCDAPC] D0_APC_1: 0x0
9985 12:44:04.120301 INFO: [NOCDAPC] D1_APC_0: 0x0
9986 12:44:04.123332 INFO: [NOCDAPC] D1_APC_1: 0xfff
9987 12:44:04.126642 INFO: [NOCDAPC] D2_APC_0: 0x0
9988 12:44:04.130217 INFO: [NOCDAPC] D2_APC_1: 0xfff
9989 12:44:04.133482 INFO: [NOCDAPC] D3_APC_0: 0x0
9990 12:44:04.136850 INFO: [NOCDAPC] D3_APC_1: 0xfff
9991 12:44:04.140183 INFO: [NOCDAPC] D4_APC_0: 0x0
9992 12:44:04.143854 INFO: [NOCDAPC] D4_APC_1: 0xfff
9993 12:44:04.146977 INFO: [NOCDAPC] D5_APC_0: 0x0
9994 12:44:04.147465 INFO: [NOCDAPC] D5_APC_1: 0xfff
9995 12:44:04.150110 INFO: [NOCDAPC] D6_APC_0: 0x0
9996 12:44:04.153722 INFO: [NOCDAPC] D6_APC_1: 0xfff
9997 12:44:04.157115 INFO: [NOCDAPC] D7_APC_0: 0x0
9998 12:44:04.159948 INFO: [NOCDAPC] D7_APC_1: 0xfff
9999 12:44:04.163715 INFO: [NOCDAPC] D8_APC_0: 0x0
10000 12:44:04.166560 INFO: [NOCDAPC] D8_APC_1: 0xfff
10001 12:44:04.170196 INFO: [NOCDAPC] D9_APC_0: 0x0
10002 12:44:04.173671 INFO: [NOCDAPC] D9_APC_1: 0xfff
10003 12:44:04.176992 INFO: [NOCDAPC] D10_APC_0: 0x0
10004 12:44:04.180351 INFO: [NOCDAPC] D10_APC_1: 0xfff
10005 12:44:04.180947 INFO: [NOCDAPC] D11_APC_0: 0x0
10006 12:44:04.183669 INFO: [NOCDAPC] D11_APC_1: 0xfff
10007 12:44:04.186886 INFO: [NOCDAPC] D12_APC_0: 0x0
10008 12:44:04.190528 INFO: [NOCDAPC] D12_APC_1: 0xfff
10009 12:44:04.193720 INFO: [NOCDAPC] D13_APC_0: 0x0
10010 12:44:04.196662 INFO: [NOCDAPC] D13_APC_1: 0xfff
10011 12:44:04.200287 INFO: [NOCDAPC] D14_APC_0: 0x0
10012 12:44:04.203228 INFO: [NOCDAPC] D14_APC_1: 0xfff
10013 12:44:04.206482 INFO: [NOCDAPC] D15_APC_0: 0x0
10014 12:44:04.210160 INFO: [NOCDAPC] D15_APC_1: 0xfff
10015 12:44:04.213548 INFO: [NOCDAPC] APC_CON: 0x4
10016 12:44:04.217050 INFO: [APUAPC] set_apusys_apc done
10017 12:44:04.220510 INFO: [DEVAPC] devapc_init done
10018 12:44:04.223026 INFO: GICv3 without legacy support detected.
10019 12:44:04.226583 INFO: ARM GICv3 driver initialized in EL3
10020 12:44:04.230039 INFO: Maximum SPI INTID supported: 639
10021 12:44:04.236740 INFO: BL31: Initializing runtime services
10022 12:44:04.239798 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10023 12:44:04.243210 INFO: SPM: enable CPC mode
10024 12:44:04.249541 INFO: mcdi ready for mcusys-off-idle and system suspend
10025 12:44:04.253378 INFO: BL31: Preparing for EL3 exit to normal world
10026 12:44:04.256209 INFO: Entry point address = 0x80000000
10027 12:44:04.259917 INFO: SPSR = 0x8
10028 12:44:04.264747
10029 12:44:04.265232
10030 12:44:04.265719
10031 12:44:04.267902 Starting depthcharge on Spherion...
10032 12:44:04.268388
10033 12:44:04.268870 Wipe memory regions:
10034 12:44:04.269326
10035 12:44:04.271753 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10036 12:44:04.272360 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10037 12:44:04.272877 Setting prompt string to ['asurada:']
10038 12:44:04.273403 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10039 12:44:04.274276 [0x00000040000000, 0x00000054600000)
10040 12:44:04.393672
10041 12:44:04.394310 [0x00000054660000, 0x00000080000000)
10042 12:44:04.654177
10043 12:44:04.654756 [0x000000821a7280, 0x000000ffe64000)
10044 12:44:05.399075
10045 12:44:05.401904 [0x00000100000000, 0x00000240000000)
10046 12:44:07.289873
10047 12:44:07.292626 Initializing XHCI USB controller at 0x11200000.
10048 12:44:08.330971
10049 12:44:08.334252 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10050 12:44:08.334726
10051 12:44:08.335097
10052 12:44:08.335448
10053 12:44:08.336249 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10055 12:44:08.437531 asurada: tftpboot 192.168.201.1 12703558/tftp-deploy-so37e02b/kernel/image.itb 12703558/tftp-deploy-so37e02b/kernel/cmdline
10056 12:44:08.438279 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10057 12:44:08.438790 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10058 12:44:08.443213 tftpboot 192.168.201.1 12703558/tftp-deploy-so37e02b/kernel/image.ittp-deploy-so37e02b/kernel/cmdline
10059 12:44:08.443694
10060 12:44:08.444066 Waiting for link
10061 12:44:08.604014
10062 12:44:08.604591 R8152: Initializing
10063 12:44:08.604964
10064 12:44:08.607051 Version 9 (ocp_data = 6010)
10065 12:44:08.607520
10066 12:44:08.610147 R8152: Done initializing
10067 12:44:08.610618
10068 12:44:08.610990 Adding net device
10069 12:44:10.479213
10070 12:44:10.479773 done.
10071 12:44:10.480143
10072 12:44:10.480488 MAC: 00:e0:4c:72:2d:d6
10073 12:44:10.480884
10074 12:44:10.482229 Sending DHCP discover... done.
10075 12:44:10.482700
10076 12:44:20.197440 Waiting for reply... R8152: Bulk read error 0xffffffbf
10077 12:44:20.198239
10078 12:44:20.200700 Receive failed.
10079 12:44:20.201326
10080 12:44:20.202051 done.
10081 12:44:20.202436
10082 12:44:20.204072 Sending DHCP request... done.
10083 12:44:20.204540
10084 12:44:20.211777 Waiting for reply... done.
10085 12:44:20.212342
10086 12:44:20.212715 My ip is 192.168.201.21
10087 12:44:20.213060
10088 12:44:20.215262 The DHCP server ip is 192.168.201.1
10089 12:44:20.215823
10090 12:44:20.221798 TFTP server IP predefined by user: 192.168.201.1
10091 12:44:20.222394
10092 12:44:20.228084 Bootfile predefined by user: 12703558/tftp-deploy-so37e02b/kernel/image.itb
10093 12:44:20.228807
10094 12:44:20.229193 Sending tftp read request... done.
10095 12:44:20.231628
10096 12:44:20.235952 Waiting for the transfer...
10097 12:44:20.236615
10098 12:44:20.575367 00000000 ################################################################
10099 12:44:20.575523
10100 12:44:20.859627 00080000 ################################################################
10101 12:44:20.859766
10102 12:44:21.156465 00100000 ################################################################
10103 12:44:21.156595
10104 12:44:21.448293 00180000 ################################################################
10105 12:44:21.448426
10106 12:44:21.720539 00200000 ################################################################
10107 12:44:21.720668
10108 12:44:22.017288 00280000 ################################################################
10109 12:44:22.017419
10110 12:44:22.313526 00300000 ################################################################
10111 12:44:22.313655
10112 12:44:22.575383 00380000 ################################################################
10113 12:44:22.575520
10114 12:44:22.872256 00400000 ################################################################
10115 12:44:22.872387
10116 12:44:23.142643 00480000 ################################################################
10117 12:44:23.142769
10118 12:44:23.407295 00500000 ################################################################
10119 12:44:23.407431
10120 12:44:23.674351 00580000 ################################################################
10121 12:44:23.674482
10122 12:44:23.966501 00600000 ################################################################
10123 12:44:23.966621
10124 12:44:24.260790 00680000 ################################################################
10125 12:44:24.260921
10126 12:44:24.547548 00700000 ################################################################
10127 12:44:24.547689
10128 12:44:24.843829 00780000 ################################################################
10129 12:44:24.843957
10130 12:44:25.138147 00800000 ################################################################
10131 12:44:25.138274
10132 12:44:25.411197 00880000 ################################################################
10133 12:44:25.411326
10134 12:44:25.659632 00900000 ################################################################
10135 12:44:25.659773
10136 12:44:25.916813 00980000 ################################################################
10137 12:44:25.916940
10138 12:44:26.213681 00a00000 ################################################################
10139 12:44:26.213850
10140 12:44:26.503014 00a80000 ################################################################
10141 12:44:26.503156
10142 12:44:26.752994 00b00000 ################################################################
10143 12:44:26.753118
10144 12:44:27.023739 00b80000 ################################################################
10145 12:44:27.023862
10146 12:44:27.304860 00c00000 ################################################################
10147 12:44:27.304985
10148 12:44:27.585370 00c80000 ################################################################
10149 12:44:27.585502
10150 12:44:27.833992 00d00000 ################################################################
10151 12:44:27.834119
10152 12:44:28.082985 00d80000 ################################################################
10153 12:44:28.083109
10154 12:44:28.372174 00e00000 ################################################################
10155 12:44:28.372301
10156 12:44:28.628947 00e80000 ################################################################
10157 12:44:28.629074
10158 12:44:28.924480 00f00000 ################################################################
10159 12:44:28.924611
10160 12:44:29.219286 00f80000 ################################################################
10161 12:44:29.219417
10162 12:44:29.515770 01000000 ################################################################
10163 12:44:29.515897
10164 12:44:29.799062 01080000 ################################################################
10165 12:44:29.799198
10166 12:44:30.070534 01100000 ################################################################
10167 12:44:30.070658
10168 12:44:30.357475 01180000 ################################################################
10169 12:44:30.357597
10170 12:44:30.646394 01200000 ################################################################
10171 12:44:30.646908
10172 12:44:30.920333 01280000 ################################################################
10173 12:44:30.920464
10174 12:44:31.184442 01300000 ################################################################
10175 12:44:31.184571
10176 12:44:31.440819 01380000 ################################################################
10177 12:44:31.440939
10178 12:44:31.712621 01400000 ################################################################
10179 12:44:31.712764
10180 12:44:31.978147 01480000 ################################################################
10181 12:44:31.978276
10182 12:44:32.232275 01500000 ################################################################
10183 12:44:32.232395
10184 12:44:32.483516 01580000 ################################################################
10185 12:44:32.483635
10186 12:44:32.751341 01600000 ################################################################
10187 12:44:32.751469
10188 12:44:33.038375 01680000 ################################################################
10189 12:44:33.038504
10190 12:44:33.314788 01700000 ################################################################
10191 12:44:33.314908
10192 12:44:33.610194 01780000 ################################################################
10193 12:44:33.610317
10194 12:44:33.886154 01800000 ################################################################
10195 12:44:33.886286
10196 12:44:34.181896 01880000 ################################################################
10197 12:44:34.182040
10198 12:44:34.479366 01900000 ################################################################
10199 12:44:34.479518
10200 12:44:34.764382 01980000 ################################################################
10201 12:44:34.764544
10202 12:44:35.025851 01a00000 ################################################################
10203 12:44:35.026034
10204 12:44:35.317277 01a80000 ################################################################
10205 12:44:35.317404
10206 12:44:35.610941 01b00000 ################################################################
10207 12:44:35.611067
10208 12:44:35.891058 01b80000 ################################################################
10209 12:44:35.891188
10210 12:44:36.183780 01c00000 ################################################################
10211 12:44:36.183903
10212 12:44:36.456552 01c80000 ################################################################
10213 12:44:36.456684
10214 12:44:36.730322 01d00000 ################################################################
10215 12:44:36.730445
10216 12:44:37.024745 01d80000 ################################################################
10217 12:44:37.024881
10218 12:44:37.320765 01e00000 ################################################################
10219 12:44:37.320893
10220 12:44:37.617243 01e80000 ################################################################
10221 12:44:37.617370
10222 12:44:37.913104 01f00000 ################################################################
10223 12:44:37.913244
10224 12:44:38.210532 01f80000 ################################################################
10225 12:44:38.210659
10226 12:44:38.505797 02000000 ################################################################
10227 12:44:38.505928
10228 12:44:38.802407 02080000 ################################################################
10229 12:44:38.802543
10230 12:44:39.065288 02100000 ################################################################
10231 12:44:39.065419
10232 12:44:39.353023 02180000 ################################################################
10233 12:44:39.353152
10234 12:44:39.641419 02200000 ################################################################
10235 12:44:39.641574
10236 12:44:39.894791 02280000 ################################################################
10237 12:44:39.894928
10238 12:44:40.143995 02300000 ################################################################
10239 12:44:40.144159
10240 12:44:40.392779 02380000 ################################################################
10241 12:44:40.392935
10242 12:44:40.642383 02400000 ################################################################
10243 12:44:40.642511
10244 12:44:40.888839 02480000 ################################################################
10245 12:44:40.888973
10246 12:44:41.145816 02500000 ################################################################
10247 12:44:41.145999
10248 12:44:41.448504 02580000 ################################################################
10249 12:44:41.448643
10250 12:44:41.709571 02600000 ################################################################
10251 12:44:41.709701
10252 12:44:41.986384 02680000 ################################################################
10253 12:44:41.986515
10254 12:44:42.277897 02700000 ################################################################
10255 12:44:42.278074
10256 12:44:42.542531 02780000 ################################################################
10257 12:44:42.542683
10258 12:44:42.837099 02800000 ################################################################
10259 12:44:42.837254
10260 12:44:43.122594 02880000 ################################################################
10261 12:44:43.122750
10262 12:44:43.412319 02900000 ################################################################
10263 12:44:43.412448
10264 12:44:43.709569 02980000 ################################################################
10265 12:44:43.709700
10266 12:44:44.003913 02a00000 ################################################################
10267 12:44:44.004040
10268 12:44:44.291552 02a80000 ################################################################
10269 12:44:44.291677
10270 12:44:44.542603 02b00000 ################################################################
10271 12:44:44.542718
10272 12:44:44.803488 02b80000 ################################################################
10273 12:44:44.803629
10274 12:44:45.081873 02c00000 ################################################################
10275 12:44:45.082020
10276 12:44:45.356620 02c80000 ################################################################
10277 12:44:45.356767
10278 12:44:45.651315 02d00000 ################################################################
10279 12:44:45.651447
10280 12:44:45.947344 02d80000 ################################################################
10281 12:44:45.947503
10282 12:44:46.241651 02e00000 ################################################################
10283 12:44:46.241778
10284 12:44:46.537890 02e80000 ################################################################
10285 12:44:46.538046
10286 12:44:46.833865 02f00000 ################################################################
10287 12:44:46.834065
10288 12:44:47.091009 02f80000 ################################################################
10289 12:44:47.091141
10290 12:44:47.356173 03000000 ################################################################
10291 12:44:47.356298
10292 12:44:47.647013 03080000 ################################################################
10293 12:44:47.647136
10294 12:44:47.927225 03100000 ################################################################
10295 12:44:47.927351
10296 12:44:48.205854 03180000 ################################################################
10297 12:44:48.206037
10298 12:44:48.496399 03200000 ################################################################
10299 12:44:48.496522
10300 12:44:48.793879 03280000 ################################################################
10301 12:44:48.794060
10302 12:44:49.088648 03300000 ################################################################
10303 12:44:49.088821
10304 12:44:49.338251 03380000 ################################################################
10305 12:44:49.338381
10306 12:44:49.586758 03400000 ################################################################
10307 12:44:49.586877
10308 12:44:49.835817 03480000 ################################################################
10309 12:44:49.835938
10310 12:44:50.084901 03500000 ################################################################
10311 12:44:50.085018
10312 12:44:50.333027 03580000 ################################################################
10313 12:44:50.333155
10314 12:44:50.581311 03600000 ################################################################
10315 12:44:50.581438
10316 12:44:50.845198 03680000 ################################################################
10317 12:44:50.845322
10318 12:44:51.114310 03700000 ################################################################
10319 12:44:51.114433
10320 12:44:51.366720 03780000 ################################################################
10321 12:44:51.366856
10322 12:44:51.615659 03800000 ################################################################
10323 12:44:51.615781
10324 12:44:51.892774 03880000 ################################################################
10325 12:44:51.892936
10326 12:44:52.187168 03900000 ################################################################
10327 12:44:52.187304
10328 12:44:52.454585 03980000 ################################################################
10329 12:44:52.454733
10330 12:44:52.736030 03a00000 ################################################################
10331 12:44:52.736181
10332 12:44:53.034582 03a80000 ################################################################
10333 12:44:53.034732
10334 12:44:53.320507 03b00000 ################################################################
10335 12:44:53.320681
10336 12:44:53.612744 03b80000 ################################################################
10337 12:44:53.612896
10338 12:44:53.904795 03c00000 ################################################################
10339 12:44:53.904944
10340 12:44:54.197033 03c80000 ################################################################
10341 12:44:54.197157
10342 12:44:54.473279 03d00000 ################################################################
10343 12:44:54.473444
10344 12:44:54.745033 03d80000 ################################################################
10345 12:44:54.745160
10346 12:44:55.037161 03e00000 ################################################################
10347 12:44:55.037285
10348 12:44:55.293633 03e80000 ################################################################
10349 12:44:55.293801
10350 12:44:55.575671 03f00000 ################################################################
10351 12:44:55.575803
10352 12:44:55.868389 03f80000 ################################################################
10353 12:44:55.868536
10354 12:44:56.158040 04000000 ################################################################
10355 12:44:56.158166
10356 12:44:56.421915 04080000 ################################################################
10357 12:44:56.422047
10358 12:44:56.696107 04100000 ################################################################
10359 12:44:56.696260
10360 12:44:56.986819 04180000 ################################################################
10361 12:44:56.986947
10362 12:44:57.279094 04200000 ################################################################
10363 12:44:57.279217
10364 12:44:57.542306 04280000 ################################################################
10365 12:44:57.542457
10366 12:44:57.811380 04300000 ################################################################
10367 12:44:57.811502
10368 12:44:58.095277 04380000 ################################################################
10369 12:44:58.095403
10370 12:44:58.376668 04400000 ################################################################
10371 12:44:58.376804
10372 12:44:58.674151 04480000 ################################################################
10373 12:44:58.674282
10374 12:44:58.932903 04500000 ################################################################
10375 12:44:58.933045
10376 12:44:59.230644 04580000 ################################################################
10377 12:44:59.230769
10378 12:44:59.502481 04600000 ################################################################
10379 12:44:59.502617
10380 12:44:59.750845 04680000 ################################################################
10381 12:44:59.750967
10382 12:45:00.034367 04700000 ################################################################
10383 12:45:00.034492
10384 12:45:00.283146 04780000 ################################################################
10385 12:45:00.283275
10386 12:45:00.577650 04800000 ################################################################
10387 12:45:00.578185
10388 12:45:00.922613 04880000 ################################################################
10389 12:45:00.923117
10390 12:45:01.238341 04900000 ################################################################
10391 12:45:01.238499
10392 12:45:01.523480 04980000 ################################################################
10393 12:45:01.523631
10394 12:45:01.785486 04a00000 ################################################################
10395 12:45:01.785648
10396 12:45:02.035019 04a80000 ################################################################
10397 12:45:02.035177
10398 12:45:02.296620 04b00000 ################################################################
10399 12:45:02.296766
10400 12:45:02.573481 04b80000 ################################################################
10401 12:45:02.573620
10402 12:45:02.836065 04c00000 ################################################################
10403 12:45:02.836187
10404 12:45:03.133864 04c80000 ################################################################
10405 12:45:03.134021
10406 12:45:03.432140 04d00000 ################################################################
10407 12:45:03.432263
10408 12:45:03.726366 04d80000 ################################################################
10409 12:45:03.726513
10410 12:45:04.024690 04e00000 ################################################################
10411 12:45:04.024815
10412 12:45:04.321385 04e80000 ################################################################
10413 12:45:04.321514
10414 12:45:04.601848 04f00000 ################################################################
10415 12:45:04.602006
10416 12:45:04.852888 04f80000 ################################################################
10417 12:45:04.853015
10418 12:45:05.131260 05000000 ################################################################
10419 12:45:05.131391
10420 12:45:05.408086 05080000 ################################################################
10421 12:45:05.408212
10422 12:45:05.672988 05100000 ################################################################
10423 12:45:05.673132
10424 12:45:05.924251 05180000 ################################################################
10425 12:45:05.924370
10426 12:45:06.219711 05200000 ################################################################
10427 12:45:06.219837
10428 12:45:06.516893 05280000 ################################################################
10429 12:45:06.517018
10430 12:45:06.770960 05300000 ################################################################
10431 12:45:06.771094
10432 12:45:07.019190 05380000 ################################################################
10433 12:45:07.019316
10434 12:45:07.299150 05400000 ################################################################
10435 12:45:07.299286
10436 12:45:07.588885 05480000 ################################################################
10437 12:45:07.589010
10438 12:45:07.884494 05500000 ################################################################
10439 12:45:07.884624
10440 12:45:08.181438 05580000 ################################################################
10441 12:45:08.181563
10442 12:45:08.478836 05600000 ################################################################
10443 12:45:08.478960
10444 12:45:08.748271 05680000 ################################################################
10445 12:45:08.748404
10446 12:45:08.996906 05700000 ################################################################
10447 12:45:08.997033
10448 12:45:09.247314 05780000 ################################################################
10449 12:45:09.247450
10450 12:45:09.544604 05800000 ################################################################
10451 12:45:09.544730
10452 12:45:09.810160 05880000 ################################################################
10453 12:45:09.810325
10454 12:45:10.059277 05900000 ################################################################
10455 12:45:10.059399
10456 12:45:10.307891 05980000 ################################################################
10457 12:45:10.308011
10458 12:45:10.557042 05a00000 ################################################################
10459 12:45:10.557167
10460 12:45:10.844322 05a80000 ################################################################
10461 12:45:10.844453
10462 12:45:11.143166 05b00000 ################################################################
10463 12:45:11.143296
10464 12:45:11.431595 05b80000 ################################################################
10465 12:45:11.431745
10466 12:45:11.702220 05c00000 ################################################################
10467 12:45:11.702373
10468 12:45:11.995974 05c80000 ################################################################
10469 12:45:11.996129
10470 12:45:12.291629 05d00000 ################################################################
10471 12:45:12.291782
10472 12:45:12.584092 05d80000 ################################################################
10473 12:45:12.584252
10474 12:45:12.877031 05e00000 ################################################################
10475 12:45:12.877166
10476 12:45:13.174406 05e80000 ################################################################
10477 12:45:13.174557
10478 12:45:13.471771 05f00000 ################################################################
10479 12:45:13.471922
10480 12:45:13.765598 05f80000 ################################################################
10481 12:45:13.765754
10482 12:45:14.061822 06000000 ################################################################
10483 12:45:14.062023
10484 12:45:14.353731 06080000 ################################################################
10485 12:45:14.353888
10486 12:45:14.624526 06100000 ################################################################
10487 12:45:14.624679
10488 12:45:14.879756 06180000 ################################################################
10489 12:45:14.879921
10490 12:45:15.137428 06200000 ################################################################
10491 12:45:15.137567
10492 12:45:15.427008 06280000 ################################################################
10493 12:45:15.427145
10494 12:45:15.686383 06300000 ################################################################
10495 12:45:15.686504
10496 12:45:15.953031 06380000 ################################################################
10497 12:45:15.953165
10498 12:45:16.201692 06400000 ################################################################
10499 12:45:16.201814
10500 12:45:16.472711 06480000 ################################################################
10501 12:45:16.472835
10502 12:45:16.769868 06500000 ################################################################
10503 12:45:16.770025
10504 12:45:17.030121 06580000 ################################################################
10505 12:45:17.030252
10506 12:45:17.305183 06600000 ################################################################
10507 12:45:17.305305
10508 12:45:17.601769 06680000 ################################################################
10509 12:45:17.601905
10510 12:45:17.896278 06700000 ################################################################
10511 12:45:17.896456
10512 12:45:18.192427 06780000 ################################################################
10513 12:45:18.192561
10514 12:45:18.489707 06800000 ################################################################
10515 12:45:18.489833
10516 12:45:18.785818 06880000 ################################################################
10517 12:45:18.785970
10518 12:45:18.983173 06900000 ############################################## done.
10519 12:45:18.983302
10520 12:45:18.986510 The bootfile was 110473886 bytes long.
10521 12:45:18.986593
10522 12:45:18.989785 Sending tftp read request... done.
10523 12:45:18.989872
10524 12:45:18.993474 Waiting for the transfer...
10525 12:45:18.994061
10526 12:45:18.996754 00000000 # done.
10527 12:45:18.997225
10528 12:45:19.003194 Command line loaded dynamically from TFTP file: 12703558/tftp-deploy-so37e02b/kernel/cmdline
10529 12:45:19.003788
10530 12:45:19.016764 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10531 12:45:19.017277
10532 12:45:19.017606 Loading FIT.
10533 12:45:19.017998
10534 12:45:19.019944 Image ramdisk-1 has 98371715 bytes.
10535 12:45:19.020362
10536 12:45:19.023174 Image fdt-1 has 47278 bytes.
10537 12:45:19.023589
10538 12:45:19.026744 Image kernel-1 has 12052857 bytes.
10539 12:45:19.027160
10540 12:45:19.036475 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10541 12:45:19.036894
10542 12:45:19.053800 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10543 12:45:19.054407
10544 12:45:19.059973 Choosing best match conf-1 for compat google,spherion-rev2.
10545 12:45:19.060495
10546 12:45:19.067905 Connected to device vid:did:rid of 1ae0:0028:00
10547 12:45:19.075995
10548 12:45:19.078876 tpm_get_response: command 0x17b, return code 0x0
10549 12:45:19.079302
10550 12:45:19.082370 ec_init: CrosEC protocol v3 supported (256, 248)
10551 12:45:19.086628
10552 12:45:19.089608 tpm_cleanup: add release locality here.
10553 12:45:19.090056
10554 12:45:19.090392 Shutting down all USB controllers.
10555 12:45:19.092875
10556 12:45:19.093349 Removing current net device
10557 12:45:19.093709
10558 12:45:19.099720 Exiting depthcharge with code 4 at timestamp: 104142892
10559 12:45:19.100290
10560 12:45:19.102904 LZMA decompressing kernel-1 to 0x821a6718
10561 12:45:19.103368
10562 12:45:19.106084 LZMA decompressing kernel-1 to 0x40000000
10563 12:45:20.606241
10564 12:45:20.606804 jumping to kernel
10565 12:45:20.609108 end: 2.2.4 bootloader-commands (duration 00:01:16) [common]
10566 12:45:20.609644 start: 2.2.5 auto-login-action (timeout 00:03:09) [common]
10567 12:45:20.610078 Setting prompt string to ['Linux version [0-9]']
10568 12:45:20.610462 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10569 12:45:20.610837 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10570 12:45:20.688113
10571 12:45:20.691310 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10572 12:45:20.695083 start: 2.2.5.1 login-action (timeout 00:03:09) [common]
10573 12:45:20.695602 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10574 12:45:20.695999 Setting prompt string to []
10575 12:45:20.696445 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10576 12:45:20.696846 Using line separator: #'\n'#
10577 12:45:20.697185 No login prompt set.
10578 12:45:20.697530 Parsing kernel messages
10579 12:45:20.697843 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10580 12:45:20.698455 [login-action] Waiting for messages, (timeout 00:03:09)
10581 12:45:20.698814 Waiting using forced prompt support (timeout 00:01:34)
10582 12:45:20.714661 [ 0.000000] Linux version 6.1.75-cip14 (KernelCI@build-j98433-arm64-gcc-10-defconfig-arm64-chromebook-89n64) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Feb 5 12:20:06 UTC 2024
10583 12:45:20.717875 [ 0.000000] random: crng init done
10584 12:45:20.724393 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10585 12:45:20.727511 [ 0.000000] efi: UEFI not found.
10586 12:45:20.735009 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10587 12:45:20.741112 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10588 12:45:20.751075 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10589 12:45:20.761212 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10590 12:45:20.767640 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10591 12:45:20.770859 [ 0.000000] printk: bootconsole [mtk8250] enabled
10592 12:45:20.780249 [ 0.000000] NUMA: No NUMA configuration found
10593 12:45:20.786598 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10594 12:45:20.793158 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10595 12:45:20.793729 [ 0.000000] Zone ranges:
10596 12:45:20.800065 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10597 12:45:20.803146 [ 0.000000] DMA32 empty
10598 12:45:20.809812 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10599 12:45:20.813068 [ 0.000000] Movable zone start for each node
10600 12:45:20.816035 [ 0.000000] Early memory node ranges
10601 12:45:20.822809 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10602 12:45:20.829574 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10603 12:45:20.836014 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10604 12:45:20.842795 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10605 12:45:20.849743 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10606 12:45:20.856044 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10607 12:45:20.912626 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10608 12:45:20.919030 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10609 12:45:20.926029 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10610 12:45:20.929422 [ 0.000000] psci: probing for conduit method from DT.
10611 12:45:20.935576 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10612 12:45:20.938544 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10613 12:45:20.945444 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10614 12:45:20.948736 [ 0.000000] psci: SMC Calling Convention v1.2
10615 12:45:20.955197 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10616 12:45:20.958406 [ 0.000000] Detected VIPT I-cache on CPU0
10617 12:45:20.965254 [ 0.000000] CPU features: detected: GIC system register CPU interface
10618 12:45:20.971912 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10619 12:45:20.978396 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10620 12:45:20.985520 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10621 12:45:20.992103 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10622 12:45:21.002051 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10623 12:45:21.005616 [ 0.000000] alternatives: applying boot alternatives
10624 12:45:21.012122 [ 0.000000] Fallback order for Node 0: 0
10625 12:45:21.018569 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10626 12:45:21.019035 [ 0.000000] Policy zone: Normal
10627 12:45:21.035307 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10628 12:45:21.045338 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10629 12:45:21.057056 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10630 12:45:21.066852 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10631 12:45:21.073564 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10632 12:45:21.076908 <6>[ 0.000000] software IO TLB: area num 8.
10633 12:45:21.133703 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10634 12:45:21.282552 <6>[ 0.000000] Memory: 7871192K/8385536K available (17984K kernel code, 4118K rwdata, 19612K rodata, 8448K init, 616K bss, 481576K reserved, 32768K cma-reserved)
10635 12:45:21.288562 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10636 12:45:21.295166 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10637 12:45:21.298826 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10638 12:45:21.305495 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10639 12:45:21.312029 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10640 12:45:21.315201 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10641 12:45:21.325351 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10642 12:45:21.332317 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10643 12:45:21.335657 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10644 12:45:21.343196 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10645 12:45:21.346642 <6>[ 0.000000] GICv3: 608 SPIs implemented
10646 12:45:21.353447 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10647 12:45:21.357020 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10648 12:45:21.360375 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10649 12:45:21.370337 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10650 12:45:21.379575 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10651 12:45:21.392989 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10652 12:45:21.399609 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10653 12:45:21.408922 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10654 12:45:21.421893 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10655 12:45:21.428655 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10656 12:45:21.435179 <6>[ 0.009185] Console: colour dummy device 80x25
10657 12:45:21.445490 <6>[ 0.013912] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10658 12:45:21.452432 <6>[ 0.024355] pid_max: default: 32768 minimum: 301
10659 12:45:21.455391 <6>[ 0.029257] LSM: Security Framework initializing
10660 12:45:21.462037 <6>[ 0.034198] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10661 12:45:21.472109 <6>[ 0.042012] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10662 12:45:21.478546 <6>[ 0.051434] cblist_init_generic: Setting adjustable number of callback queues.
10663 12:45:21.485298 <6>[ 0.058923] cblist_init_generic: Setting shift to 3 and lim to 1.
10664 12:45:21.495081 <6>[ 0.065262] cblist_init_generic: Setting adjustable number of callback queues.
10665 12:45:21.498833 <6>[ 0.072689] cblist_init_generic: Setting shift to 3 and lim to 1.
10666 12:45:21.505510 <6>[ 0.079090] rcu: Hierarchical SRCU implementation.
10667 12:45:21.511960 <6>[ 0.084104] rcu: Max phase no-delay instances is 1000.
10668 12:45:21.518414 <6>[ 0.091169] EFI services will not be available.
10669 12:45:21.521987 <6>[ 0.096131] smp: Bringing up secondary CPUs ...
10670 12:45:21.529473 <6>[ 0.101181] Detected VIPT I-cache on CPU1
10671 12:45:21.536654 <6>[ 0.101252] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10672 12:45:21.542907 <6>[ 0.101281] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10673 12:45:21.546477 <6>[ 0.101624] Detected VIPT I-cache on CPU2
10674 12:45:21.552860 <6>[ 0.101676] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10675 12:45:21.560136 <6>[ 0.101695] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10676 12:45:21.566599 <6>[ 0.101956] Detected VIPT I-cache on CPU3
10677 12:45:21.572814 <6>[ 0.102006] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10678 12:45:21.579960 <6>[ 0.102021] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10679 12:45:21.582958 <6>[ 0.102328] CPU features: detected: Spectre-v4
10680 12:45:21.589843 <6>[ 0.102333] CPU features: detected: Spectre-BHB
10681 12:45:21.593028 <6>[ 0.102338] Detected PIPT I-cache on CPU4
10682 12:45:21.599451 <6>[ 0.102395] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10683 12:45:21.606566 <6>[ 0.102412] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10684 12:45:21.613465 <6>[ 0.102703] Detected PIPT I-cache on CPU5
10685 12:45:21.619376 <6>[ 0.102766] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10686 12:45:21.626115 <6>[ 0.102783] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10687 12:45:21.629346 <6>[ 0.103062] Detected PIPT I-cache on CPU6
10688 12:45:21.635651 <6>[ 0.103126] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10689 12:45:21.642445 <6>[ 0.103142] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10690 12:45:21.648771 <6>[ 0.103438] Detected PIPT I-cache on CPU7
10691 12:45:21.655904 <6>[ 0.103502] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10692 12:45:21.662824 <6>[ 0.103519] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10693 12:45:21.665408 <6>[ 0.103565] smp: Brought up 1 node, 8 CPUs
10694 12:45:21.672210 <6>[ 0.244890] SMP: Total of 8 processors activated.
10695 12:45:21.675294 <6>[ 0.249811] CPU features: detected: 32-bit EL0 Support
10696 12:45:21.685201 <6>[ 0.255173] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10697 12:45:21.692020 <6>[ 0.263973] CPU features: detected: Common not Private translations
10698 12:45:21.695493 <6>[ 0.270448] CPU features: detected: CRC32 instructions
10699 12:45:21.702110 <6>[ 0.275799] CPU features: detected: RCpc load-acquire (LDAPR)
10700 12:45:21.708668 <6>[ 0.281796] CPU features: detected: LSE atomic instructions
10701 12:45:21.715360 <6>[ 0.287613] CPU features: detected: Privileged Access Never
10702 12:45:21.718616 <6>[ 0.293393] CPU features: detected: RAS Extension Support
10703 12:45:21.728432 <6>[ 0.299036] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10704 12:45:21.732225 <6>[ 0.306258] CPU: All CPU(s) started at EL2
10705 12:45:21.738717 <6>[ 0.310574] alternatives: applying system-wide alternatives
10706 12:45:21.747149 <6>[ 0.321296] devtmpfs: initialized
10707 12:45:21.763280 <6>[ 0.330205] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10708 12:45:21.769657 <6>[ 0.340165] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10709 12:45:21.776400 <6>[ 0.348175] pinctrl core: initialized pinctrl subsystem
10710 12:45:21.779633 <6>[ 0.354810] DMI not present or invalid.
10711 12:45:21.786373 <6>[ 0.359220] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10712 12:45:21.796236 <6>[ 0.366064] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10713 12:45:21.802508 <6>[ 0.373656] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10714 12:45:21.812900 <6>[ 0.381872] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10715 12:45:21.816011 <6>[ 0.390113] audit: initializing netlink subsys (disabled)
10716 12:45:21.825988 <5>[ 0.395808] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10717 12:45:21.832314 <6>[ 0.396510] thermal_sys: Registered thermal governor 'step_wise'
10718 12:45:21.839413 <6>[ 0.403779] thermal_sys: Registered thermal governor 'power_allocator'
10719 12:45:21.842506 <6>[ 0.410035] cpuidle: using governor menu
10720 12:45:21.849072 <6>[ 0.420996] NET: Registered PF_QIPCRTR protocol family
10721 12:45:21.855440 <6>[ 0.426471] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10722 12:45:21.859089 <6>[ 0.433574] ASID allocator initialised with 32768 entries
10723 12:45:21.866440 <6>[ 0.440094] Serial: AMBA PL011 UART driver
10724 12:45:21.874842 <4>[ 0.448858] Trying to register duplicate clock ID: 134
10725 12:45:21.929705 <6>[ 0.506551] KASLR enabled
10726 12:45:21.943928 <6>[ 0.514258] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10727 12:45:21.950445 <6>[ 0.521272] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10728 12:45:21.956917 <6>[ 0.527761] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10729 12:45:21.963454 <6>[ 0.534767] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10730 12:45:21.970267 <6>[ 0.541256] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10731 12:45:21.976628 <6>[ 0.548260] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10732 12:45:21.982995 <6>[ 0.554745] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10733 12:45:21.990002 <6>[ 0.561750] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10734 12:45:21.993101 <6>[ 0.569279] ACPI: Interpreter disabled.
10735 12:45:22.001722 <6>[ 0.575696] iommu: Default domain type: Translated
10736 12:45:22.008560 <6>[ 0.580808] iommu: DMA domain TLB invalidation policy: strict mode
10737 12:45:22.011769 <5>[ 0.587466] SCSI subsystem initialized
10738 12:45:22.018434 <6>[ 0.591632] usbcore: registered new interface driver usbfs
10739 12:45:22.024860 <6>[ 0.597363] usbcore: registered new interface driver hub
10740 12:45:22.028347 <6>[ 0.602914] usbcore: registered new device driver usb
10741 12:45:22.035130 <6>[ 0.609016] pps_core: LinuxPPS API ver. 1 registered
10742 12:45:22.044963 <6>[ 0.614210] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10743 12:45:22.048268 <6>[ 0.623562] PTP clock support registered
10744 12:45:22.051639 <6>[ 0.627807] EDAC MC: Ver: 3.0.0
10745 12:45:22.058922 <6>[ 0.632964] FPGA manager framework
10746 12:45:22.065626 <6>[ 0.636644] Advanced Linux Sound Architecture Driver Initialized.
10747 12:45:22.069003 <6>[ 0.643429] vgaarb: loaded
10748 12:45:22.075371 <6>[ 0.646570] clocksource: Switched to clocksource arch_sys_counter
10749 12:45:22.079313 <5>[ 0.653008] VFS: Disk quotas dquot_6.6.0
10750 12:45:22.085683 <6>[ 0.657189] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10751 12:45:22.088534 <6>[ 0.664378] pnp: PnP ACPI: disabled
10752 12:45:22.097364 <6>[ 0.671027] NET: Registered PF_INET protocol family
10753 12:45:22.107327 <6>[ 0.676621] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10754 12:45:22.118585 <6>[ 0.688948] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10755 12:45:22.128711 <6>[ 0.697762] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10756 12:45:22.135274 <6>[ 0.705738] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10757 12:45:22.142095 <6>[ 0.714440] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10758 12:45:22.154131 <6>[ 0.724198] TCP: Hash tables configured (established 65536 bind 65536)
10759 12:45:22.160145 <6>[ 0.731062] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10760 12:45:22.166622 <6>[ 0.738261] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10761 12:45:22.173677 <6>[ 0.745966] NET: Registered PF_UNIX/PF_LOCAL protocol family
10762 12:45:22.179960 <6>[ 0.752116] RPC: Registered named UNIX socket transport module.
10763 12:45:22.183201 <6>[ 0.758268] RPC: Registered udp transport module.
10764 12:45:22.190121 <6>[ 0.763201] RPC: Registered tcp transport module.
10765 12:45:22.197451 <6>[ 0.768133] RPC: Registered tcp NFSv4.1 backchannel transport module.
10766 12:45:22.199614 <6>[ 0.774797] PCI: CLS 0 bytes, default 64
10767 12:45:22.203205 <6>[ 0.779134] Unpacking initramfs...
10768 12:45:22.228227 <6>[ 0.798678] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10769 12:45:22.238064 <6>[ 0.807328] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10770 12:45:22.241315 <6>[ 0.816186] kvm [1]: IPA Size Limit: 40 bits
10771 12:45:22.248026 <6>[ 0.820715] kvm [1]: GICv3: no GICV resource entry
10772 12:45:22.251259 <6>[ 0.825736] kvm [1]: disabling GICv2 emulation
10773 12:45:22.257768 <6>[ 0.830422] kvm [1]: GIC system register CPU interface enabled
10774 12:45:22.261480 <6>[ 0.836584] kvm [1]: vgic interrupt IRQ18
10775 12:45:22.267701 <6>[ 0.840940] kvm [1]: VHE mode initialized successfully
10776 12:45:22.274200 <5>[ 0.847440] Initialise system trusted keyrings
10777 12:45:22.280655 <6>[ 0.852278] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10778 12:45:22.288288 <6>[ 0.862317] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10779 12:45:22.295145 <5>[ 0.868694] NFS: Registering the id_resolver key type
10780 12:45:22.298534 <5>[ 0.873998] Key type id_resolver registered
10781 12:45:22.305054 <5>[ 0.878415] Key type id_legacy registered
10782 12:45:22.311464 <6>[ 0.882699] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10783 12:45:22.318061 <6>[ 0.889619] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10784 12:45:22.324896 <6>[ 0.897339] 9p: Installing v9fs 9p2000 file system support
10785 12:45:22.362108 <5>[ 0.935582] Key type asymmetric registered
10786 12:45:22.364849 <5>[ 0.939913] Asymmetric key parser 'x509' registered
10787 12:45:22.374877 <6>[ 0.945061] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10788 12:45:22.377991 <6>[ 0.952679] io scheduler mq-deadline registered
10789 12:45:22.381170 <6>[ 0.957460] io scheduler kyber registered
10790 12:45:22.397578 <6>[ 0.974681] EINJ: ACPI disabled.
10791 12:45:22.433393 <4>[ 1.000509] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10792 12:45:22.443245 <4>[ 1.011150] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10793 12:45:22.458381 <6>[ 1.032140] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10794 12:45:22.466425 <6>[ 1.040212] printk: console [ttyS0] disabled
10795 12:45:22.494219 <6>[ 1.064839] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10796 12:45:22.500687 <6>[ 1.074316] printk: console [ttyS0] enabled
10797 12:45:22.504212 <6>[ 1.074316] printk: console [ttyS0] enabled
10798 12:45:22.510805 <6>[ 1.083208] printk: bootconsole [mtk8250] disabled
10799 12:45:22.513893 <6>[ 1.083208] printk: bootconsole [mtk8250] disabled
10800 12:45:22.520334 <6>[ 1.094492] SuperH (H)SCI(F) driver initialized
10801 12:45:22.524002 <6>[ 1.099782] msm_serial: driver initialized
10802 12:45:22.537987 <6>[ 1.108757] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10803 12:45:22.547726 <6>[ 1.117312] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10804 12:45:22.554620 <6>[ 1.125853] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10805 12:45:22.564323 <6>[ 1.134483] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10806 12:45:22.574635 <6>[ 1.143189] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10807 12:45:22.580881 <6>[ 1.151902] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10808 12:45:22.591054 <6>[ 1.160450] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10809 12:45:22.597696 <6>[ 1.169253] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10810 12:45:22.607303 <6>[ 1.177797] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10811 12:45:22.619129 <6>[ 1.193351] loop: module loaded
10812 12:45:22.625867 <6>[ 1.199344] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10813 12:45:22.648285 <4>[ 1.222693] mtk-pmic-keys: Failed to locate of_node [id: -1]
10814 12:45:22.655376 <6>[ 1.229680] megasas: 07.719.03.00-rc1
10815 12:45:22.665311 <6>[ 1.239343] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10816 12:45:22.671995 <6>[ 1.245949] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10817 12:45:22.688647 <6>[ 1.262713] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10818 12:45:22.745448 <6>[ 1.312933] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10819 12:45:26.237984 <6>[ 4.811608] Freeing initrd memory: 96060K
10820 12:45:26.247943 <6>[ 4.822263] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10821 12:45:26.259028 <6>[ 4.833403] tun: Universal TUN/TAP device driver, 1.6
10822 12:45:26.262393 <6>[ 4.839492] thunder_xcv, ver 1.0
10823 12:45:26.265663 <6>[ 4.843003] thunder_bgx, ver 1.0
10824 12:45:26.268670 <6>[ 4.846494] nicpf, ver 1.0
10825 12:45:26.279225 <6>[ 4.850511] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10826 12:45:26.282600 <6>[ 4.857989] hns3: Copyright (c) 2017 Huawei Corporation.
10827 12:45:26.288998 <6>[ 4.863579] hclge is initializing
10828 12:45:26.292622 <6>[ 4.867159] e1000: Intel(R) PRO/1000 Network Driver
10829 12:45:26.299260 <6>[ 4.872288] e1000: Copyright (c) 1999-2006 Intel Corporation.
10830 12:45:26.302667 <6>[ 4.878301] e1000e: Intel(R) PRO/1000 Network Driver
10831 12:45:26.309497 <6>[ 4.883516] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10832 12:45:26.316137 <6>[ 4.889705] igb: Intel(R) Gigabit Ethernet Network Driver
10833 12:45:26.322537 <6>[ 4.895355] igb: Copyright (c) 2007-2014 Intel Corporation.
10834 12:45:26.329151 <6>[ 4.901191] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10835 12:45:26.335790 <6>[ 4.907709] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10836 12:45:26.338994 <6>[ 4.914168] sky2: driver version 1.30
10837 12:45:26.345535 <6>[ 4.919166] VFIO - User Level meta-driver version: 0.3
10838 12:45:26.353066 <6>[ 4.927435] usbcore: registered new interface driver usb-storage
10839 12:45:26.359918 <6>[ 4.933882] usbcore: registered new device driver onboard-usb-hub
10840 12:45:26.368695 <6>[ 4.943067] mt6397-rtc mt6359-rtc: registered as rtc0
10841 12:45:26.378529 <6>[ 4.948533] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-05T12:44:46 UTC (1707137086)
10842 12:45:26.382136 <6>[ 4.958103] i2c_dev: i2c /dev entries driver
10843 12:45:26.398764 <6>[ 4.969810] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10844 12:45:26.419405 <6>[ 4.993831] cpu cpu0: EM: created perf domain
10845 12:45:26.422296 <6>[ 4.998766] cpu cpu4: EM: created perf domain
10846 12:45:26.430006 <6>[ 5.004394] sdhci: Secure Digital Host Controller Interface driver
10847 12:45:26.436826 <6>[ 5.010830] sdhci: Copyright(c) Pierre Ossman
10848 12:45:26.443605 <6>[ 5.015791] Synopsys Designware Multimedia Card Interface Driver
10849 12:45:26.449885 <6>[ 5.022418] sdhci-pltfm: SDHCI platform and OF driver helper
10850 12:45:26.453170 <6>[ 5.022461] mmc0: CQHCI version 5.10
10851 12:45:26.460057 <6>[ 5.032769] ledtrig-cpu: registered to indicate activity on CPUs
10852 12:45:26.466560 <6>[ 5.039799] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10853 12:45:26.473080 <6>[ 5.046853] usbcore: registered new interface driver usbhid
10854 12:45:26.476157 <6>[ 5.052674] usbhid: USB HID core driver
10855 12:45:26.486523 <6>[ 5.056879] spi_master spi0: will run message pump with realtime priority
10856 12:45:26.526901 <6>[ 5.094650] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10857 12:45:26.546677 <6>[ 5.110278] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10858 12:45:26.553424 <6>[ 5.126192] cros-ec-spi spi0.0: Chrome EC device registered
10859 12:45:26.556935 <6>[ 5.132202] mmc0: Command Queue Engine enabled
10860 12:45:26.563299 <6>[ 5.136981] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10861 12:45:26.570060 <6>[ 5.144604] mmcblk0: mmc0:0001 DA4128 116 GiB
10862 12:45:26.581102 <6>[ 5.155348] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10863 12:45:26.590783 <6>[ 5.159815] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10864 12:45:26.597545 <6>[ 5.162474] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10865 12:45:26.600587 <6>[ 5.171796] NET: Registered PF_PACKET protocol family
10866 12:45:26.607177 <6>[ 5.176611] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10867 12:45:26.610526 <6>[ 5.181194] 9pnet: Installing 9P2000 support
10868 12:45:26.617525 <6>[ 5.187065] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10869 12:45:26.623536 <5>[ 5.190889] Key type dns_resolver registered
10870 12:45:26.627230 <6>[ 5.202304] registered taskstats version 1
10871 12:45:26.633812 <5>[ 5.206691] Loading compiled-in X.509 certificates
10872 12:45:26.661614 <4>[ 5.229418] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10873 12:45:26.671653 <4>[ 5.240153] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10874 12:45:26.678371 <3>[ 5.250712] debugfs: File 'uA_load' in directory '/' already present!
10875 12:45:26.685040 <3>[ 5.257429] debugfs: File 'min_uV' in directory '/' already present!
10876 12:45:26.691507 <3>[ 5.264092] debugfs: File 'max_uV' in directory '/' already present!
10877 12:45:26.698239 <3>[ 5.270719] debugfs: File 'constraint_flags' in directory '/' already present!
10878 12:45:26.709380 <3>[ 5.280578] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10879 12:45:26.718408 <6>[ 5.292850] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10880 12:45:26.725126 <6>[ 5.299684] xhci-mtk 11200000.usb: xHCI Host Controller
10881 12:45:26.731750 <6>[ 5.305170] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10882 12:45:26.741991 <6>[ 5.313007] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10883 12:45:26.748467 <6>[ 5.322422] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10884 12:45:26.755166 <6>[ 5.328478] xhci-mtk 11200000.usb: xHCI Host Controller
10885 12:45:26.761741 <6>[ 5.333953] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10886 12:45:26.768394 <6>[ 5.341599] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10887 12:45:26.774770 <6>[ 5.349230] hub 1-0:1.0: USB hub found
10888 12:45:26.778220 <6>[ 5.353240] hub 1-0:1.0: 1 port detected
10889 12:45:26.784879 <6>[ 5.357501] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10890 12:45:26.791735 <6>[ 5.366054] hub 2-0:1.0: USB hub found
10891 12:45:26.794782 <6>[ 5.370056] hub 2-0:1.0: 1 port detected
10892 12:45:26.803625 <6>[ 5.378056] mtk-msdc 11f70000.mmc: Got CD GPIO
10893 12:45:26.814176 <6>[ 5.385297] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10894 12:45:26.820701 <6>[ 5.393331] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10895 12:45:26.830298 <4>[ 5.401308] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10896 12:45:26.840606 <6>[ 5.410842] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10897 12:45:26.847115 <6>[ 5.418938] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10898 12:45:26.857534 <6>[ 5.427075] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10899 12:45:26.863814 <6>[ 5.435007] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10900 12:45:26.870845 <6>[ 5.442827] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10901 12:45:26.880719 <6>[ 5.450651] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10902 12:45:26.890487 <6>[ 5.461109] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10903 12:45:26.896900 <6>[ 5.469491] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10904 12:45:26.907143 <6>[ 5.477831] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10905 12:45:26.916812 <6>[ 5.486171] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10906 12:45:26.923309 <6>[ 5.494509] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10907 12:45:26.933646 <6>[ 5.502850] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10908 12:45:26.939709 <6>[ 5.511188] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10909 12:45:26.949578 <6>[ 5.519526] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10910 12:45:26.956198 <6>[ 5.527868] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10911 12:45:26.966359 <6>[ 5.536207] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10912 12:45:26.972696 <6>[ 5.544546] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10913 12:45:26.982596 <6>[ 5.552885] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10914 12:45:26.989261 <6>[ 5.561223] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10915 12:45:26.999300 <6>[ 5.569562] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10916 12:45:27.006165 <6>[ 5.577902] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10917 12:45:27.012292 <6>[ 5.586639] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10918 12:45:27.019398 <6>[ 5.593765] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10919 12:45:27.025754 <6>[ 5.600521] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10920 12:45:27.035980 <6>[ 5.607287] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10921 12:45:27.042739 <6>[ 5.614221] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10922 12:45:27.049266 <6>[ 5.621063] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10923 12:45:27.059164 <6>[ 5.630191] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10924 12:45:27.069631 <6>[ 5.639310] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10925 12:45:27.078992 <6>[ 5.648604] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10926 12:45:27.089128 <6>[ 5.658071] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10927 12:45:27.095337 <6>[ 5.667536] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10928 12:45:27.105706 <6>[ 5.676663] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10929 12:45:27.115607 <6>[ 5.686130] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10930 12:45:27.125182 <6>[ 5.695248] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10931 12:45:27.135102 <6>[ 5.704541] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10932 12:45:27.144671 <6>[ 5.714703] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10933 12:45:27.155296 <6>[ 5.726756] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10934 12:45:27.183796 <6>[ 5.755109] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10935 12:45:27.211968 <6>[ 5.786199] hub 2-1:1.0: USB hub found
10936 12:45:27.215240 <6>[ 5.790660] hub 2-1:1.0: 3 ports detected
10937 12:45:27.223129 <6>[ 5.797555] hub 2-1:1.0: USB hub found
10938 12:45:27.226331 <6>[ 5.801919] hub 2-1:1.0: 3 ports detected
10939 12:45:27.335433 <6>[ 5.906884] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10940 12:45:27.490157 <6>[ 6.064977] hub 1-1:1.0: USB hub found
10941 12:45:27.493811 <6>[ 6.069429] hub 1-1:1.0: 4 ports detected
10942 12:45:27.503451 <6>[ 6.077689] hub 1-1:1.0: USB hub found
10943 12:45:27.506588 <6>[ 6.082048] hub 1-1:1.0: 4 ports detected
10944 12:45:27.575988 <6>[ 6.147050] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10945 12:45:27.828179 <6>[ 6.398886] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10946 12:45:27.960221 <6>[ 6.534637] hub 1-1.4:1.0: USB hub found
10947 12:45:27.963668 <6>[ 6.539299] hub 1-1.4:1.0: 2 ports detected
10948 12:45:27.973472 <6>[ 6.547687] hub 1-1.4:1.0: USB hub found
10949 12:45:27.976327 <6>[ 6.552265] hub 1-1.4:1.0: 2 ports detected
10950 12:45:28.275872 <6>[ 6.846860] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10951 12:45:28.467604 <6>[ 7.038858] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10952 12:45:39.453100 <6>[ 18.031893] ALSA device list:
10953 12:45:39.459178 <6>[ 18.035188] No soundcards found.
10954 12:45:39.467255 <6>[ 18.043197] Freeing unused kernel memory: 8448K
10955 12:45:39.470267 <6>[ 18.048187] Run /init as init process
10956 12:45:39.519230 <6>[ 18.095096] NET: Registered PF_INET6 protocol family
10957 12:45:39.525821 <6>[ 18.101325] Segment Routing with IPv6
10958 12:45:39.529030 <6>[ 18.105275] In-situ OAM (IOAM) with IPv6
10959 12:45:39.559970 <30>[ 18.119317] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10960 12:45:39.567108 <30>[ 18.143141] systemd[1]: Detected architecture arm64.
10961 12:45:39.567677
10962 12:45:39.574115 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10963 12:45:39.574678
10964 12:45:39.586708 <30>[ 18.162873] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10965 12:45:39.726806 <30>[ 18.299533] systemd[1]: Queued start job for default target Graphical Interface.
10966 12:45:39.763592 <30>[ 18.339516] systemd[1]: Created slice system-getty.slice.
10967 12:45:39.770106 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10968 12:45:39.787507 <30>[ 18.363449] systemd[1]: Created slice system-modprobe.slice.
10969 12:45:39.794206 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10970 12:45:39.812299 <30>[ 18.388129] systemd[1]: Created slice system-serial\x2dgetty.slice.
10971 12:45:39.822464 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10972 12:45:39.835264 <30>[ 18.411209] systemd[1]: Created slice User and Session Slice.
10973 12:45:39.841980 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10974 12:45:39.862682 <30>[ 18.435524] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10975 12:45:39.872992 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10976 12:45:39.890794 <30>[ 18.462934] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10977 12:45:39.896975 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10978 12:45:39.917561 <30>[ 18.486889] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10979 12:45:39.924554 <30>[ 18.499003] systemd[1]: Reached target Local Encrypted Volumes.
10980 12:45:39.930820 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10981 12:45:39.947137 <30>[ 18.523327] systemd[1]: Reached target Paths.
10982 12:45:39.950654 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10983 12:45:39.966783 <30>[ 18.542830] systemd[1]: Reached target Remote File Systems.
10984 12:45:39.973468 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10985 12:45:39.987209 <30>[ 18.562818] systemd[1]: Reached target Slices.
10986 12:45:39.990034 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10987 12:45:40.007096 <30>[ 18.582847] systemd[1]: Reached target Swap.
10988 12:45:40.009854 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10989 12:45:40.030537 <30>[ 18.603311] systemd[1]: Listening on initctl Compatibility Named Pipe.
10990 12:45:40.037407 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10991 12:45:40.052228 <30>[ 18.628230] systemd[1]: Listening on Journal Audit Socket.
10992 12:45:40.058645 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10993 12:45:40.075711 <30>[ 18.651959] systemd[1]: Listening on Journal Socket (/dev/log).
10994 12:45:40.082622 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10995 12:45:40.100482 <30>[ 18.676054] systemd[1]: Listening on Journal Socket.
10996 12:45:40.107144 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10997 12:45:40.119455 <30>[ 18.695386] systemd[1]: Listening on udev Control Socket.
10998 12:45:40.125971 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10999 12:45:40.143924 <30>[ 18.719823] systemd[1]: Listening on udev Kernel Socket.
11000 12:45:40.150391 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
11001 12:45:40.190990 <30>[ 18.766927] systemd[1]: Mounting Huge Pages File System...
11002 12:45:40.198032 Mounting [0;1;39mHuge Pages File System[0m...
11003 12:45:40.214571 <30>[ 18.790446] systemd[1]: Mounting POSIX Message Queue File System...
11004 12:45:40.221678 Mounting [0;1;39mPOSIX Message Queue File System[0m...
11005 12:45:40.242663 <30>[ 18.818449] systemd[1]: Mounting Kernel Debug File System...
11006 12:45:40.249172 Mounting [0;1;39mKernel Debug File System[0m...
11007 12:45:40.266377 <30>[ 18.839257] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
11008 12:45:40.279133 <30>[ 18.851985] systemd[1]: Starting Create list of static device nodes for the current kernel...
11009 12:45:40.285655 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
11010 12:45:40.323425 <30>[ 18.899111] systemd[1]: Starting Load Kernel Module configfs...
11011 12:45:40.329632 Starting [0;1;39mLoad Kernel Module configfs[0m...
11012 12:45:40.346304 <30>[ 18.922598] systemd[1]: Starting Load Kernel Module drm...
11013 12:45:40.353808 Starting [0;1;39mLoad Kernel Module drm[0m...
11014 12:45:40.370358 <30>[ 18.943108] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
11015 12:45:40.407246 <30>[ 18.983311] systemd[1]: Starting Journal Service...
11016 12:45:40.410534 Starting [0;1;39mJournal Service[0m...
11017 12:45:40.429937 <30>[ 19.005880] systemd[1]: Starting Load Kernel Modules...
11018 12:45:40.436599 Starting [0;1;39mLoad Kernel Modules[0m...
11019 12:45:40.456791 <30>[ 19.029598] systemd[1]: Starting Remount Root and Kernel File Systems...
11020 12:45:40.463564 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
11021 12:45:40.483505 <30>[ 19.059309] systemd[1]: Starting Coldplug All udev Devices...
11022 12:45:40.490406 Starting [0;1;39mColdplug All udev Devices[0m...
11023 12:45:40.505320 <30>[ 19.081776] systemd[1]: Started Journal Service.
11024 12:45:40.511919 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
11025 12:45:40.529901 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
11026 12:45:40.547724 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
11027 12:45:40.564118 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
11028 12:45:40.584209 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
11029 12:45:40.602265 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
11030 12:45:40.621700 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
11031 12:45:40.641078 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
11032 12:45:40.660740 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
11033 12:45:40.674751 See 'systemctl status systemd-remount-fs.service' for details.
11034 12:45:40.728805 Mounting [0;1;39mKernel Configuration File System[0m...
11035 12:45:40.751097 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11036 12:45:40.764482 <46>[ 19.337376] systemd-journald[177]: Received client request to flush runtime journal.
11037 12:45:40.774507 Starting [0;1;39mLoad/Save Random Seed[0m...
11038 12:45:40.799581 Starting [0;1;39mApply Kernel Variables[0m...
11039 12:45:40.824360 Starting [0;1;39mCreate System Users[0m...
11040 12:45:40.848789 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
11041 12:45:40.867437 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
11042 12:45:40.892320 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11043 12:45:40.908596 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11044 12:45:40.928759 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11045 12:45:40.948275 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11046 12:45:41.019714 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11047 12:45:41.044065 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11048 12:45:41.058787 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11049 12:45:41.074855 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11050 12:45:41.111952 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11051 12:45:41.136773 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11052 12:45:41.162397 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11053 12:45:41.184334 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11054 12:45:41.233651 Starting [0;1;39mNetwork Time Synchronization[0m...
11055 12:45:41.256815 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11056 12:45:41.302859 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11057 12:45:41.329069 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11058 12:45:41.343473 <6>[ 19.916326] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11059 12:45:41.350363 <6>[ 19.917547] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11060 12:45:41.359700 [[0;32m OK [<6>[ 19.931812] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11061 12:45:41.370147 0m] Reached targ<3>[ 19.932094] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11062 12:45:41.379935 et [0;1;39mSyst<6>[ 19.941778] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11063 12:45:41.386202 em Time Set[0m.<6>[ 19.945014] remoteproc remoteproc0: scp is available
11064 12:45:41.386672
11065 12:45:41.396614 <3>[ 19.951374] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11066 12:45:41.399654 <6>[ 19.961517] remoteproc remoteproc0: powering up scp
11067 12:45:41.410105 <3>[ 19.968043] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11068 12:45:41.416339 <6>[ 19.976216] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11069 12:45:41.426559 <3>[ 19.985136] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11070 12:45:41.429715 <6>[ 19.989533] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11071 12:45:41.439635 <6>[ 19.997785] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11072 12:45:41.446074 <3>[ 19.998075] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11073 12:45:41.456275 <3>[ 20.027599] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11074 12:45:41.462416 <3>[ 20.035726] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11075 12:45:41.469517 <3>[ 20.043818] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11076 12:45:41.479259 [[0;32m OK [<4>[ 20.048946] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11077 12:45:41.486305 <4>[ 20.048946] Fallback method does not support PEC.
11078 12:45:41.492241 0m] Reached targ<6>[ 20.050540] mc: Linux media interface: v0.10
11079 12:45:41.498737 <3>[ 20.051971] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11080 12:45:41.505745 <6>[ 20.059968] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11081 12:45:41.512347 et [0;1;39mSyst<6>[ 20.059976] pci_bus 0000:00: root bus resource [bus 00-ff]
11082 12:45:41.522067 em Time Synchron<6>[ 20.059982] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11083 12:45:41.522624 ized[0m.
11084 12:45:41.532781 <6>[ 20.059988] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11085 12:45:41.539745 <6>[ 20.060019] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11086 12:45:41.546555 <6>[ 20.060039] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11087 12:45:41.553085 <6>[ 20.060118] pci 0000:00:00.0: supports D1 D2
11088 12:45:41.559371 <6>[ 20.060122] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11089 12:45:41.566129 <6>[ 20.061730] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11090 12:45:41.572480 <6>[ 20.061861] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11091 12:45:41.579355 <6>[ 20.061893] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11092 12:45:41.589974 <6>[ 20.061914] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11093 12:45:41.596822 <6>[ 20.061932] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11094 12:45:41.600443 <6>[ 20.062052] pci 0000:01:00.0: supports D1 D2
11095 12:45:41.607402 <6>[ 20.062055] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11096 12:45:41.613866 <6>[ 20.082194] videodev: Linux video capture interface: v2.00
11097 12:45:41.620860 <3>[ 20.095597] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11098 12:45:41.627375 <6>[ 20.095807] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11099 12:45:41.637176 <6>[ 20.095877] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11100 12:45:41.644022 <6>[ 20.095886] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11101 12:45:41.650547 <6>[ 20.095989] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11102 12:45:41.660208 <6>[ 20.096008] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11103 12:45:41.667860 <6>[ 20.096024] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11104 12:45:41.671068 <6>[ 20.096042] pci 0000:00:00.0: PCI bridge to [bus 01]
11105 12:45:41.681713 <6>[ 20.096051] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11106 12:45:41.688403 <6>[ 20.096597] usbcore: registered new device driver r8152-cfgselector
11107 12:45:41.695287 <6>[ 20.098820] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11108 12:45:41.701636 <4>[ 20.099999] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11109 12:45:41.708157 <4>[ 20.100122] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11110 12:45:41.714944 <6>[ 20.100585] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11111 12:45:41.721922 <6>[ 20.100821] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11112 12:45:41.728687 <6>[ 20.115197] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11113 12:45:41.735541 <6>[ 20.115203] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11114 12:45:41.742623 <3>[ 20.120593] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11115 12:45:41.752671 <3>[ 20.120602] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11116 12:45:41.762905 <3>[ 20.123329] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11117 12:45:41.769467 <6>[ 20.128318] remoteproc remoteproc0: remote processor scp is now up
11118 12:45:41.775725 <3>[ 20.129114] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11119 12:45:41.782530 <3>[ 20.129140] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11120 12:45:41.792066 <3>[ 20.129144] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11121 12:45:41.798872 <3>[ 20.129149] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11122 12:45:41.808639 <3>[ 20.129152] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11123 12:45:41.815376 <3>[ 20.129189] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11124 12:45:41.825805 <3>[ 20.180196] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11125 12:45:41.832297 <3>[ 20.182851] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
11126 12:45:41.842607 <6>[ 20.214738] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11127 12:45:41.850052 <6>[ 20.225805] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11128 12:45:41.859855 <6>[ 20.258968] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
11129 12:45:41.869814 <6>[ 20.301562] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11130 12:45:41.876668 <6>[ 20.310850] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11131 12:45:41.886929 <3>[ 20.313358] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11132 12:45:41.893608 <6>[ 20.313732] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11133 12:45:41.903708 <3>[ 20.313941] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11134 12:45:41.913864 <3>[ 20.322753] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11135 12:45:41.916747 <6>[ 20.349443] Bluetooth: Core ver 2.22
11136 12:45:41.927596 <4>[ 20.363255] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
11137 12:45:41.930848 <6>[ 20.364878] NET: Registered PF_BLUETOOTH protocol family
11138 12:45:41.941080 <5>[ 20.368597] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11139 12:45:41.947360 <4>[ 20.372955] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
11140 12:45:41.954551 <5>[ 20.378421] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11141 12:45:41.961172 <5>[ 20.378758] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11142 12:45:41.971418 <4>[ 20.378812] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11143 12:45:41.978680 <6>[ 20.378817] cfg80211: failed to load regulatory.db
11144 12:45:41.981852 <6>[ 20.380977] Bluetooth: HCI device and connection manager initialized
11145 12:45:41.988747 <6>[ 20.380995] Bluetooth: HCI socket layer initialized
11146 12:45:41.996077 <6>[ 20.399554] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11147 12:45:42.002463 <3>[ 20.405256] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11148 12:45:42.009527 <6>[ 20.405924] Bluetooth: L2CAP socket layer initialized
11149 12:45:42.012998 <6>[ 20.405936] Bluetooth: SCO socket layer initialized
11150 12:45:42.022844 <3>[ 20.427207] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11151 12:45:42.030016 <6>[ 20.433203] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11152 12:45:42.043795 <6>[ 20.452131] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11153 12:45:42.047299 <6>[ 20.463065] r8152 2-1.3:1.0 eth0: v1.12.13
11154 12:45:42.053727 <3>[ 20.467936] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11155 12:45:42.060537 <6>[ 20.468493] usbcore: registered new interface driver uvcvideo
11156 12:45:42.066855 <6>[ 20.469621] usbcore: registered new interface driver btusb
11157 12:45:42.073503 <6>[ 20.476660] usbcore: registered new interface driver r8152
11158 12:45:42.083383 <4>[ 20.485703] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11159 12:45:42.090241 <6>[ 20.490605] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11160 12:45:42.097057 <6>[ 20.490730] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11161 12:45:42.106524 <3>[ 20.508847] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11162 12:45:42.110195 <6>[ 20.510670] mt7921e 0000:01:00.0: ASIC revision: 79610010
11163 12:45:42.116737 <3>[ 20.512679] Bluetooth: hci0: Failed to load firmware file (-2)
11164 12:45:42.123159 <6>[ 20.512882] usbcore: registered new interface driver cdc_ether
11165 12:45:42.129764 <6>[ 20.520913] usbcore: registered new interface driver r8153_ecm
11166 12:45:42.136193 <3>[ 20.528816] Bluetooth: hci0: Failed to set up firmware (-2)
11167 12:45:42.143186 <6>[ 20.558935] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
11168 12:45:42.152916 <4>[ 20.564514] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11169 12:45:42.159698 <6>[ 20.609052] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
11170 12:45:42.162850 <6>[ 20.609052]
11171 12:45:42.169646 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11172 12:45:42.191343 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11173 12:45:42.212083 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11174 12:45:42.237509 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11175 12:45:42.400646 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11176 12:45:42.414746 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11177 12:45:42.428517 <6>[ 21.001339] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
11178 12:45:42.435298 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11179 12:45:42.453888 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11180 12:45:42.466662 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11181 12:45:42.486903 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11182 12:45:42.498755 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11183 12:45:42.514802 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11184 12:45:42.534775 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11185 12:45:42.571038 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11186 12:45:42.599387 Starting [0;1;39mUser Login Management[0m...
11187 12:45:42.619969 Starting [0;1;39mPermit User Sessions[0m...
11188 12:45:42.638817 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11189 12:45:42.650154 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11190 12:45:42.665725 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11191 12:45:42.682999 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11192 12:45:42.703322 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11193 12:45:42.719784 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11194 12:45:42.735530 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11195 12:45:42.753116 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11196 12:45:42.771628 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11197 12:45:42.831635 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11198 12:45:42.861436 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11199 12:45:42.897651
11200 12:45:42.898271
11201 12:45:42.900836 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11202 12:45:42.901307
11203 12:45:42.903835 debian-bullseye-arm64 login: root (automatic login)
11204 12:45:42.904405
11205 12:45:42.904784
11206 12:45:42.925420 Linux debian-bullseye-arm64 6.1.75-cip14 #1 SMP PREEMPT Mon Feb 5 12:20:06 UTC 2024 aarch64
11207 12:45:42.926028
11208 12:45:42.932083 The programs included with the Debian GNU/Linux system are free software;
11209 12:45:42.938860 the exact distribution terms for each program are described in the
11210 12:45:42.941990 individual files in /usr/share/doc/*/copyright.
11211 12:45:42.942570
11212 12:45:42.948579 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11213 12:45:42.951487 permitted by applicable law.
11214 12:45:42.952889 Matched prompt #10: / #
11216 12:45:42.954048 Setting prompt string to ['/ #']
11217 12:45:42.954534 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11219 12:45:42.955614 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11220 12:45:42.956134 start: 2.2.6 expect-shell-connection (timeout 00:02:47) [common]
11221 12:45:42.956544 Setting prompt string to ['/ #']
11222 12:45:42.956897 Forcing a shell prompt, looking for ['/ #']
11224 12:45:43.007776 / #
11225 12:45:43.008441 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11226 12:45:43.008906 Waiting using forced prompt support (timeout 00:02:30)
11227 12:45:43.014213
11228 12:45:43.015192 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11229 12:45:43.015754 start: 2.2.7 export-device-env (timeout 00:02:46) [common]
11230 12:45:43.016268 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11231 12:45:43.016768 end: 2.2 depthcharge-retry (duration 00:02:14) [common]
11232 12:45:43.017252 end: 2 depthcharge-action (duration 00:02:14) [common]
11233 12:45:43.017723 start: 3 lava-test-retry (timeout 00:05:00) [common]
11234 12:45:43.018237 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11235 12:45:43.018636 Using namespace: common
11237 12:45:43.119852 / # #
11238 12:45:43.120504 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11239 12:45:43.126395 #
11240 12:45:43.127284 Using /lava-12703558
11242 12:45:43.228446 / # export SHELL=/bin/sh
11243 12:45:43.234908 export SHELL=/bin/sh
11245 12:45:43.336582 / # . /lava-12703558/environment
11246 12:45:43.337365 <6>[ 21.852411] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11247 12:45:43.343057 . /lava-12703558/environment
11249 12:45:43.444973 / # /lava-12703558/bin/lava-test-runner /lava-12703558/0
11250 12:45:43.445607 Test shell timeout: 10s (minimum of the action and connection timeout)
11251 12:45:43.451539 /lava-12703558/bin/lava-test-runner /lava-12703558/0
11252 12:45:43.470622 + export TESTRUN_ID=0_sleep
11253 12:45:43.474050 + cd /lava-12703558/0/tests/0_sleep
11254 12:45:43.477287 + cat uuid
11255 12:45:43.477860 + UUID=12703558_1.5.2.3.1
11256 12:45:43.480736 + set +x
11257 12:45:43.483928 <LAVA_SIGNAL_STARTRUN 0_sleep 12703558_1.5.2.3.1>
11258 12:45:43.484802 Received signal: <STARTRUN> 0_sleep 12703558_1.5.2.3.1
11259 12:45:43.485225 Starting test lava.0_sleep (12703558_1.5.2.3.1)
11260 12:45:43.485726 Skipping test definition patterns.
11261 12:45:43.487222 + ./config/lava/sleep/sleep.sh mem
11262 12:45:43.490463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11263 12:45:43.491191 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11265 12:45:43.497130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11266 12:45:43.498011 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11268 12:45:43.500513 rtcwake: assuming RTC uses UTC ...
11269 12:45:43.510170 rtcwake: wakeup from "mem" using rtc0 at Mon Feb 5 1<6>[ 22.086094] PM: suspend entry (deep)
11270 12:45:43.510720 2:45:10 2024
11271 12:45:43.513443 <6>[ 22.090472] Filesystems sync: 0.000 seconds
11272 12:45:43.521844 <6>[ 22.097984] Freezing user space processes
11273 12:45:43.528352 <6>[ 22.104036] Freezing user space processes completed (elapsed 0.001 seconds)
11274 12:45:43.531654 <6>[ 22.111279] OOM killer disabled.
11275 12:45:43.538683 <6>[ 22.114792] Freezing remaining freezable tasks
11276 12:45:43.548661 <6>[ 22.120846] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11277 12:45:43.555204 <6>[ 22.128514] printk: Suspending console(s) (use no_console_suspend to debug)
11278 12:45:49.840098 <6>[ 22.274095] Disabling non-boot CPUs ...
11279 12:45:49.843050 <4>[ 22.274742] IRQ282: set affinity failed(-22).
11280 12:45:49.846510 <4>[ 22.274753] IRQ284: set affinity failed(-22).
11281 12:45:49.853024 <6>[ 22.274802] psci: CPU1 killed (polled 0 ms)
11282 12:45:49.856596 <4>[ 22.275596] IRQ282: set affinity failed(-22).
11283 12:45:49.863195 <4>[ 22.275602] IRQ284: set affinity failed(-22).
11284 12:45:49.866474 <6>[ 22.275639] psci: CPU2 killed (polled 0 ms)
11285 12:45:49.869889 <4>[ 22.276226] IRQ282: set affinity failed(-22).
11286 12:45:49.876545 <4>[ 22.276232] IRQ284: set affinity failed(-22).
11287 12:45:49.880062 <6>[ 22.276264] psci: CPU3 killed (polled 0 ms)
11288 12:45:49.883401 <4>[ 22.276820] IRQ282: set affinity failed(-22).
11289 12:45:49.889662 <4>[ 22.276825] IRQ284: set affinity failed(-22).
11290 12:45:49.892824 <6>[ 22.277864] psci: CPU4 killed (polled 0 ms)
11291 12:45:49.899476 <4>[ 22.278601] IRQ282: set affinity failed(-22).
11292 12:45:49.902991 <4>[ 22.278609] IRQ284: set affinity failed(-22).
11293 12:45:49.906590 <6>[ 22.278661] psci: CPU5 killed (polled 0 ms)
11294 12:45:49.912911 <6>[ 22.279458] psci: CPU6 killed (polled 0 ms)
11295 12:45:49.916399 <6>[ 22.281163] psci: CPU7 killed (polled 0 ms)
11296 12:45:49.919681 <6>[ 22.281627] Enabling non-boot CPUs ...
11297 12:45:49.923029 <6>[ 22.281806] Detected VIPT I-cache on CPU1
11298 12:45:49.933255 <6>[ 22.281867] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11299 12:45:49.939642 <6>[ 22.281911] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11300 12:45:49.940211 <6>[ 22.282281] CPU1 is up
11301 12:45:49.946646 <6>[ 22.282371] Detected VIPT I-cache on CPU2
11302 12:45:49.953528 <6>[ 22.282403] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11303 12:45:49.959736 <6>[ 22.282424] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11304 12:45:49.962787 <6>[ 22.282694] CPU2 is up
11305 12:45:49.966555 <6>[ 22.282783] Detected VIPT I-cache on CPU3
11306 12:45:49.973563 <6>[ 22.282814] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11307 12:45:49.979636 <6>[ 22.282835] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11308 12:45:49.982774 <6>[ 22.283104] CPU3 is up
11309 12:45:49.989568 <6>[ 22.283198] CPU features: detected: Hardware dirty bit management
11310 12:45:49.993270 <6>[ 22.283220] Detected PIPT I-cache on CPU4
11311 12:45:49.999510 <6>[ 22.283248] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11312 12:45:50.006104 <6>[ 22.283268] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11313 12:45:50.009495 <6>[ 22.283572] CPU4 is up
11314 12:45:50.016037 <6>[ 22.283689] Detected PIPT I-cache on CPU5
11315 12:45:50.022428 <6>[ 22.283719] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11316 12:45:50.029429 <6>[ 22.283739] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11317 12:45:50.032929 <6>[ 22.284022] CPU5 is up
11318 12:45:50.036300 <6>[ 22.284131] Detected PIPT I-cache on CPU6
11319 12:45:50.042653 <6>[ 22.284168] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11320 12:45:50.050016 <6>[ 22.284188] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11321 12:45:50.053174 <6>[ 22.284478] CPU6 is up
11322 12:45:50.056116 <6>[ 22.284586] Detected PIPT I-cache on CPU7
11323 12:45:50.063064 <6>[ 22.284624] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11324 12:45:50.069638 <6>[ 22.284643] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11325 12:45:50.072885 <6>[ 22.284942] CPU7 is up
11326 12:45:50.079523 <4>[ 22.423921] typec port0-partner: PM: parent port0 should not be sleeping
11327 12:45:50.083041 <6>[ 22.881653] OOM killer enabled.
11328 12:45:50.089548 <6>[ 22.885044] Restarting tasks ... done.
11329 12:45:50.092731 <5>[ 22.889423] random: crng reseeded on system resumption
11330 12:45:50.096562 <6>[ 22.895686] PM: suspend exit
11331 12:45:50.106981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=pass>
11332 12:45:50.107860 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=pass
11334 12:45:50.110098 rtcwake: assuming RTC uses UTC ...
11335 12:45:50.116867 rtcwake: wakeup from "mem" using rtc0 at Mon Feb 5 12:45:16 2024
11336 12:45:50.129245 <6>[ 22.925991] PM: suspend entry (deep)
11337 12:45:50.133340 <6>[ 22.929855] Filesystems sync: 0.000 seconds
11338 12:45:50.136362 <6>[ 22.934610] Freezing user space processes
11339 12:45:50.147189 <6>[ 22.940205] Freezing user space processes completed (elapsed 0.001 seconds)
11340 12:45:50.150856 <6>[ 22.947452] OOM killer disabled.
11341 12:45:50.154112 <6>[ 22.950933] Freezing remaining freezable tasks
11342 12:45:50.164066 <6>[ 22.956757] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11343 12:45:50.170530 <6>[ 22.964408] printk: Suspending console(s) (use no_console_suspend to debug)
11344 12:45:55.844394 <6>[ 23.039916] Disabling non-boot CPUs ...
11345 12:45:55.847497 <6>[ 23.041905] psci: CPU1 killed (polled 0 ms)
11346 12:45:55.850689 <6>[ 23.044024] psci: CPU2 killed (polled 0 ms)
11347 12:45:55.857551 <6>[ 23.046037] psci: CPU3 killed (polled 0 ms)
11348 12:45:55.861185 <6>[ 23.046684] psci: CPU4 killed (polled 0 ms)
11349 12:45:55.864147 <6>[ 23.047283] psci: CPU5 killed (polled 0 ms)
11350 12:45:55.870847 <6>[ 23.047866] psci: CPU6 killed (polled 0 ms)
11351 12:45:55.874252 <6>[ 23.048411] psci: CPU7 killed (polled 0 ms)
11352 12:45:55.877501 <6>[ 23.048845] Enabling non-boot CPUs ...
11353 12:45:55.884367 <6>[ 23.049076] Detected VIPT I-cache on CPU1
11354 12:45:55.890975 <6>[ 23.049167] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11355 12:45:55.897421 <6>[ 23.049228] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11356 12:45:55.900880 <6>[ 23.049878] CPU1 is up
11357 12:45:55.903967 <6>[ 23.050019] Detected VIPT I-cache on CPU2
11358 12:45:55.910683 <6>[ 23.050075] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11359 12:45:55.917144 <6>[ 23.050112] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11360 12:45:55.920451 <6>[ 23.050650] CPU2 is up
11361 12:45:55.923727 <6>[ 23.050787] Detected VIPT I-cache on CPU3
11362 12:45:55.930573 <6>[ 23.050843] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11363 12:45:55.937421 <6>[ 23.050880] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11364 12:45:55.940734 <6>[ 23.051404] CPU3 is up
11365 12:45:55.943962 <6>[ 23.051530] Detected PIPT I-cache on CPU4
11366 12:45:55.954158 <6>[ 23.051553] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11367 12:45:55.960644 <6>[ 23.051568] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11368 12:45:55.961211 <6>[ 23.051844] CPU4 is up
11369 12:45:55.967583 <6>[ 23.051965] Detected PIPT I-cache on CPU5
11370 12:45:55.974078 <6>[ 23.051988] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11371 12:45:55.980736 <6>[ 23.052003] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11372 12:45:55.984310 <6>[ 23.052257] CPU5 is up
11373 12:45:55.987570 <6>[ 23.052390] Detected PIPT I-cache on CPU6
11374 12:45:55.994329 <6>[ 23.052420] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11375 12:45:56.000778 <6>[ 23.052434] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11376 12:45:56.003719 <6>[ 23.052681] CPU6 is up
11377 12:45:56.007690 <6>[ 23.052805] Detected PIPT I-cache on CPU7
11378 12:45:56.017139 <6>[ 23.052834] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11379 12:45:56.024134 <6>[ 23.052848] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11380 12:45:56.024711 <6>[ 23.053101] CPU7 is up
11381 12:45:56.027230 <6>[ 23.594635] OOM killer enabled.
11382 12:45:56.034167 <6>[ 23.598025] Restarting tasks ... done.
11383 12:45:56.037119 <5>[ 23.602431] random: crng reseeded on system resumption
11384 12:45:56.041810 <6>[ 23.609589] PM: suspend exit
11385 12:45:56.051558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=pass>
11386 12:45:56.052404 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=pass
11388 12:45:56.054729 rtcwake: assuming RTC uses UTC ...
11389 12:45:56.061682 rtcwake: wakeup from "mem" using rtc0 at Mon Feb 5 12:45:22 2024
11390 12:45:56.074077 <6>[ 23.638339] PM: suspend entry (deep)
11391 12:45:56.077465 <6>[ 23.642202] Filesystems sync: 0.000 seconds
11392 12:45:56.080480 <6>[ 23.646927] Freezing user space processes
11393 12:45:56.091373 <6>[ 23.652459] Freezing user space processes completed (elapsed 0.001 seconds)
11394 12:45:56.094747 <6>[ 23.659705] OOM killer disabled.
11395 12:45:56.097678 <6>[ 23.663184] Freezing remaining freezable tasks
11396 12:45:56.108039 <6>[ 23.669086] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11397 12:45:56.114490 <6>[ 23.676749] printk: Suspending console(s) (use no_console_suspend to debug)
11398 12:46:01.841812 <6>[ 23.751161] Disabling non-boot CPUs ...
11399 12:46:01.844797 <6>[ 23.752005] psci: CPU1 killed (polled 0 ms)
11400 12:46:01.848368 <6>[ 23.753891] psci: CPU2 killed (polled 0 ms)
11401 12:46:01.854772 <6>[ 23.755749] psci: CPU3 killed (polled 0 ms)
11402 12:46:01.857923 <6>[ 23.756197] psci: CPU4 killed (polled 0 ms)
11403 12:46:01.861519 <6>[ 23.756728] psci: CPU5 killed (polled 0 ms)
11404 12:46:01.868496 <6>[ 23.757289] psci: CPU6 killed (polled 0 ms)
11405 12:46:01.871532 <6>[ 23.757827] psci: CPU7 killed (polled 0 ms)
11406 12:46:01.874823 <6>[ 23.758149] Enabling non-boot CPUs ...
11407 12:46:01.881866 <6>[ 23.758356] Detected VIPT I-cache on CPU1
11408 12:46:01.888526 <6>[ 23.758435] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11409 12:46:01.894784 <6>[ 23.758487] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11410 12:46:01.898046 <6>[ 23.759030] CPU1 is up
11411 12:46:01.901491 <6>[ 23.759149] Detected VIPT I-cache on CPU2
11412 12:46:01.908039 <6>[ 23.759195] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11413 12:46:01.914990 <6>[ 23.759225] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11414 12:46:01.918146 <6>[ 23.759636] CPU2 is up
11415 12:46:01.921106 <6>[ 23.759753] Detected VIPT I-cache on CPU3
11416 12:46:01.928096 <6>[ 23.759798] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11417 12:46:01.934925 <6>[ 23.759828] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11418 12:46:01.938109 <6>[ 23.760250] CPU3 is up
11419 12:46:01.944425 <6>[ 23.760361] Detected PIPT I-cache on CPU4
11420 12:46:01.951140 <6>[ 23.760382] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11421 12:46:01.957672 <6>[ 23.760395] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11422 12:46:01.961377 <6>[ 23.760634] CPU4 is up
11423 12:46:01.964695 <6>[ 23.760740] Detected PIPT I-cache on CPU5
11424 12:46:01.971075 <6>[ 23.760761] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11425 12:46:01.977808 <6>[ 23.760774] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11426 12:46:01.981069 <6>[ 23.760977] CPU5 is up
11427 12:46:01.984557 <6>[ 23.761084] Detected PIPT I-cache on CPU6
11428 12:46:01.990908 <6>[ 23.761109] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11429 12:46:01.997721 <6>[ 23.761122] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11430 12:46:02.001138 <6>[ 23.761340] CPU6 is up
11431 12:46:02.004568 <6>[ 23.761448] Detected PIPT I-cache on CPU7
11432 12:46:02.014792 <6>[ 23.761473] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11433 12:46:02.021303 <6>[ 23.761486] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11434 12:46:02.021907 <6>[ 23.761730] CPU7 is up
11435 12:46:02.024348 <6>[ 24.302362] OOM killer enabled.
11436 12:46:02.031245 <6>[ 24.305754] Restarting tasks ... done.
11437 12:46:02.034554 <5>[ 24.310097] random: crng reseeded on system resumption
11438 12:46:02.038265 <6>[ 24.316389] PM: suspend exit
11439 12:46:02.048858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=pass>
11440 12:46:02.049708 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=pass
11442 12:46:02.052162 rtcwake: assuming RTC uses UTC ...
11443 12:46:02.058767 rtcwake: wakeup from "mem" using rtc0 at Mon Feb 5 12:45:28 2024
11444 12:46:02.071874 <6>[ 24.346635] PM: suspend entry (deep)
11445 12:46:02.075343 <6>[ 24.350497] Filesystems sync: 0.000 seconds
11446 12:46:02.078581 <6>[ 24.355230] Freezing user space processes
11447 12:46:02.089896 <6>[ 24.360893] Freezing user space processes completed (elapsed 0.001 seconds)
11448 12:46:02.093066 <6>[ 24.368120] OOM killer disabled.
11449 12:46:02.096440 <6>[ 24.371603] Freezing remaining freezable tasks
11450 12:46:02.106316 <6>[ 24.377525] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11451 12:46:02.112714 <6>[ 24.385195] printk: Suspending console(s) (use no_console_suspend to debug)
11452 12:46:07.844253 <6>[ 24.459458] Disabling non-boot CPUs ...
11453 12:46:07.847867 <6>[ 24.460304] psci: CPU1 killed (polled 0 ms)
11454 12:46:07.851231 <6>[ 24.462224] psci: CPU2 killed (polled 0 ms)
11455 12:46:07.857722 <6>[ 24.464138] psci: CPU3 killed (polled 0 ms)
11456 12:46:07.860880 <6>[ 24.464736] psci: CPU4 killed (polled 0 ms)
11457 12:46:07.864262 <6>[ 24.465326] psci: CPU5 killed (polled 0 ms)
11458 12:46:07.870983 <6>[ 24.465876] psci: CPU6 killed (polled 0 ms)
11459 12:46:07.874261 <6>[ 24.466477] psci: CPU7 killed (polled 0 ms)
11460 12:46:07.877593 <6>[ 24.466779] Enabling non-boot CPUs ...
11461 12:46:07.884264 <6>[ 24.467001] Detected VIPT I-cache on CPU1
11462 12:46:07.890716 <6>[ 24.467080] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11463 12:46:07.897264 <6>[ 24.467137] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11464 12:46:07.900781 <6>[ 24.467733] CPU1 is up
11465 12:46:07.904107 <6>[ 24.467861] Detected VIPT I-cache on CPU2
11466 12:46:07.910701 <6>[ 24.467911] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11467 12:46:07.917316 <6>[ 24.467944] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11468 12:46:07.920870 <6>[ 24.468398] CPU2 is up
11469 12:46:07.923941 <6>[ 24.468521] Detected VIPT I-cache on CPU3
11470 12:46:07.930481 <6>[ 24.468572] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11471 12:46:07.940417 <6>[ 24.468605] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11472 12:46:07.941012 <6>[ 24.469065] CPU3 is up
11473 12:46:07.947166 <6>[ 24.469183] Detected PIPT I-cache on CPU4
11474 12:46:07.953610 <6>[ 24.469205] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11475 12:46:07.959972 <6>[ 24.469219] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11476 12:46:07.963760 <6>[ 24.469485] CPU4 is up
11477 12:46:07.967044 <6>[ 24.469611] Detected PIPT I-cache on CPU5
11478 12:46:07.973974 <6>[ 24.469633] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11479 12:46:07.980217 <6>[ 24.469647] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11480 12:46:07.983766 <6>[ 24.469884] CPU5 is up
11481 12:46:07.987251 <6>[ 24.470001] Detected PIPT I-cache on CPU6
11482 12:46:07.993918 <6>[ 24.470028] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11483 12:46:08.000935 <6>[ 24.470041] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11484 12:46:08.004344 <6>[ 24.470285] CPU6 is up
11485 12:46:08.007217 <6>[ 24.470400] Detected PIPT I-cache on CPU7
11486 12:46:08.017429 <6>[ 24.470427] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11487 12:46:08.024210 <6>[ 24.470441] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11488 12:46:08.024780 <6>[ 24.470687] CPU7 is up
11489 12:46:08.027043 <6>[ 25.014496] OOM killer enabled.
11490 12:46:08.034379 <6>[ 25.017886] Restarting tasks ... done.
11491 12:46:08.037518 <5>[ 25.022262] random: crng reseeded on system resumption
11492 12:46:08.041075 <6>[ 25.028685] PM: suspend exit
11493 12:46:08.052070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=pass>
11494 12:46:08.052944 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=pass
11496 12:46:08.054796 rtcwake: assuming RTC uses UTC ...
11497 12:46:08.061416 rtcwake: wakeup from "mem" using rtc0 at Mon Feb 5 12:45:34 2024
11498 12:46:08.074486 <6>[ 25.058657] PM: suspend entry (deep)
11499 12:46:08.077858 <6>[ 25.062522] Filesystems sync: 0.000 seconds
11500 12:46:08.081029 <6>[ 25.067274] Freezing user space processes
11501 12:46:08.092028 <6>[ 25.072921] Freezing user space processes completed (elapsed 0.001 seconds)
11502 12:46:08.095429 <6>[ 25.080147] OOM killer disabled.
11503 12:46:08.098620 <6>[ 25.083656] Freezing remaining freezable tasks
11504 12:46:08.109046 <6>[ 25.089572] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11505 12:46:08.115167 <6>[ 25.097249] printk: Suspending console(s) (use no_console_suspend to debug)
11506 12:46:13.842580 <6>[ 25.169485] Disabling non-boot CPUs ...
11507 12:46:13.845250 <6>[ 25.170347] psci: CPU1 killed (polled 0 ms)
11508 12:46:13.848699 <6>[ 25.171252] psci: CPU2 killed (polled 0 ms)
11509 12:46:13.855424 <6>[ 25.173113] psci: CPU3 killed (polled 0 ms)
11510 12:46:13.858875 <6>[ 25.173716] psci: CPU4 killed (polled 0 ms)
11511 12:46:13.862053 <6>[ 25.174267] psci: CPU5 killed (polled 0 ms)
11512 12:46:13.868770 <6>[ 25.174824] psci: CPU6 killed (polled 0 ms)
11513 12:46:13.872070 <6>[ 25.175356] psci: CPU7 killed (polled 0 ms)
11514 12:46:13.875317 <6>[ 25.175675] Enabling non-boot CPUs ...
11515 12:46:13.882045 <6>[ 25.175884] Detected VIPT I-cache on CPU1
11516 12:46:13.888814 <6>[ 25.175961] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11517 12:46:13.895336 <6>[ 25.176015] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11518 12:46:13.898449 <6>[ 25.176573] CPU1 is up
11519 12:46:13.901851 <6>[ 25.176694] Detected VIPT I-cache on CPU2
11520 12:46:13.908415 <6>[ 25.176741] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11521 12:46:13.915159 <6>[ 25.176772] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11522 12:46:13.918838 <6>[ 25.177189] CPU2 is up
11523 12:46:13.921701 <6>[ 25.177306] Detected VIPT I-cache on CPU3
11524 12:46:13.928674 <6>[ 25.177353] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11525 12:46:13.935384 <6>[ 25.177383] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11526 12:46:13.938295 <6>[ 25.177809] CPU3 is up
11527 12:46:13.944978 <6>[ 25.177927] Detected PIPT I-cache on CPU4
11528 12:46:13.951503 <6>[ 25.177950] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11529 12:46:13.958342 <6>[ 25.177965] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11530 12:46:13.961604 <6>[ 25.178243] CPU4 is up
11531 12:46:13.965026 <6>[ 25.178366] Detected PIPT I-cache on CPU5
11532 12:46:13.971643 <6>[ 25.178388] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11533 12:46:13.978253 <6>[ 25.178403] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11534 12:46:13.982058 <6>[ 25.178639] CPU5 is up
11535 12:46:13.985528 <6>[ 25.178755] Detected PIPT I-cache on CPU6
11536 12:46:13.991671 <6>[ 25.178784] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11537 12:46:13.998470 <6>[ 25.178799] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11538 12:46:14.001292 <6>[ 25.179042] CPU6 is up
11539 12:46:14.005045 <6>[ 25.179153] Detected PIPT I-cache on CPU7
11540 12:46:14.015435 <6>[ 25.179182] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11541 12:46:14.021601 <6>[ 25.179197] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11542 12:46:14.022288 <6>[ 25.179441] CPU7 is up
11543 12:46:14.028068 <6>[ 25.722224] OOM killer enabled.
11544 12:46:14.031622 <6>[ 25.725615] Restarting tasks ... done.
11545 12:46:14.034881 <5>[ 25.729989] random: crng reseeded on system resumption
11546 12:46:14.038888 <6>[ 25.736337] PM: suspend exit
11547 12:46:14.049649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=pass>
11548 12:46:14.050598 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=pass
11550 12:46:14.052980 rtcwake: assuming RTC uses UTC ...
11551 12:46:14.059600 rtcwake: wakeup from "mem" using rtc0 at Mon Feb 5 12:45:40 2024
11552 12:46:14.072214 <6>[ 25.766255] PM: suspend entry (deep)
11553 12:46:14.075748 <6>[ 25.770114] Filesystems sync: 0.000 seconds
11554 12:46:14.078609 <6>[ 25.774868] Freezing user space processes
11555 12:46:14.090066 <6>[ 25.780556] Freezing user space processes completed (elapsed 0.001 seconds)
11556 12:46:14.093295 <6>[ 25.787787] OOM killer disabled.
11557 12:46:14.096361 <6>[ 25.791268] Freezing remaining freezable tasks
11558 12:46:14.106238 <6>[ 25.797189] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11559 12:46:14.113352 <6>[ 25.804861] printk: Suspending console(s) (use no_console_suspend to debug)
11560 12:46:19.842255 <6>[ 25.877038] Disabling non-boot CPUs ...
11561 12:46:19.845142 <6>[ 25.877840] psci: CPU1 killed (polled 0 ms)
11562 12:46:19.848529 <6>[ 25.878857] psci: CPU2 killed (polled 0 ms)
11563 12:46:19.855439 <6>[ 25.880661] psci: CPU3 killed (polled 0 ms)
11564 12:46:19.859188 <6>[ 25.881189] psci: CPU4 killed (polled 0 ms)
11565 12:46:19.861983 <6>[ 25.881732] psci: CPU5 killed (polled 0 ms)
11566 12:46:19.868725 <6>[ 25.882287] psci: CPU6 killed (polled 0 ms)
11567 12:46:19.872059 <6>[ 25.882847] psci: CPU7 killed (polled 0 ms)
11568 12:46:19.875666 <6>[ 25.883184] Enabling non-boot CPUs ...
11569 12:46:19.882508 <6>[ 25.883396] Detected VIPT I-cache on CPU1
11570 12:46:19.888911 <6>[ 25.883474] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11571 12:46:19.895841 <6>[ 25.883526] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11572 12:46:19.898806 <6>[ 25.884080] CPU1 is up
11573 12:46:19.901827 <6>[ 25.884202] Detected VIPT I-cache on CPU2
11574 12:46:19.908771 <6>[ 25.884248] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11575 12:46:19.915631 <6>[ 25.884279] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11576 12:46:19.918889 <6>[ 25.884691] CPU2 is up
11577 12:46:19.922288 <6>[ 25.884806] Detected VIPT I-cache on CPU3
11578 12:46:19.928972 <6>[ 25.884852] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11579 12:46:19.935277 <6>[ 25.884883] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11580 12:46:19.938579 <6>[ 25.885310] CPU3 is up
11581 12:46:19.942166 <6>[ 25.885423] Detected PIPT I-cache on CPU4
11582 12:46:19.952148 <6>[ 25.885445] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11583 12:46:19.958690 <6>[ 25.885459] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11584 12:46:19.959273 <6>[ 25.885732] CPU4 is up
11585 12:46:19.965588 <6>[ 25.885852] Detected PIPT I-cache on CPU5
11586 12:46:19.972133 <6>[ 25.885874] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11587 12:46:19.978805 <6>[ 25.885888] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11588 12:46:19.982096 <6>[ 25.886109] CPU5 is up
11589 12:46:19.985349 <6>[ 25.886219] Detected PIPT I-cache on CPU6
11590 12:46:19.992024 <6>[ 25.886247] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11591 12:46:19.998622 <6>[ 25.886261] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11592 12:46:20.001922 <6>[ 25.886513] CPU6 is up
11593 12:46:20.005316 <6>[ 25.886625] Detected PIPT I-cache on CPU7
11594 12:46:20.011959 <6>[ 25.886653] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11595 12:46:20.022208 <6>[ 25.886666] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11596 12:46:20.022784 <6>[ 25.886906] CPU7 is up
11597 12:46:20.025202 <6>[ 26.430418] OOM killer enabled.
11598 12:46:20.032024 <6>[ 26.433808] Restarting tasks ... done.
11599 12:46:20.035305 <5>[ 26.438200] random: crng reseeded on system resumption
11600 12:46:20.038334 <6>[ 26.444449] PM: suspend exit
11601 12:46:20.049579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=pass>
11602 12:46:20.050523 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=pass
11604 12:46:20.052459 rtcwake: assuming RTC uses UTC ...
11605 12:46:20.059603 rtcwake: wakeup from "mem" using rtc0 at Mon Feb 5 12:45:46 2024
11606 12:46:20.071929 <6>[ 26.474073] PM: suspend entry (deep)
11607 12:46:20.074975 <6>[ 26.477963] Filesystems sync: 0.000 seconds
11608 12:46:20.078117 <6>[ 26.482688] Freezing user space processes
11609 12:46:20.089198 <6>[ 26.488323] Freezing user space processes completed (elapsed 0.001 seconds)
11610 12:46:20.092591 <6>[ 26.495549] OOM killer disabled.
11611 12:46:20.095913 <6>[ 26.499030] Freezing remaining freezable tasks
11612 12:46:20.105803 <6>[ 26.504941] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11613 12:46:20.112482 <6>[ 26.512604] printk: Suspending console(s) (use no_console_suspend to debug)
11614 12:46:25.833659 <6>[ 26.596712] Disabling non-boot CPUs ...
11615 12:46:25.837204 <6>[ 26.597526] psci: CPU1 killed (polled 0 ms)
11616 12:46:25.840010 <6>[ 26.599555] psci: CPU2 killed (polled 0 ms)
11617 12:46:25.846900 <6>[ 26.600322] psci: CPU3 killed (polled 0 ms)
11618 12:46:25.850131 <6>[ 26.600628] psci: CPU4 killed (polled 0 ms)
11619 12:46:25.853378 <6>[ 26.601015] psci: CPU5 killed (polled 0 ms)
11620 12:46:25.859692 <6>[ 26.601551] psci: CPU6 killed (polled 0 ms)
11621 12:46:25.863379 <6>[ 26.602062] psci: CPU7 killed (polled 0 ms)
11622 12:46:25.866958 <6>[ 26.602436] Enabling non-boot CPUs ...
11623 12:46:25.873271 <6>[ 26.602649] Detected VIPT I-cache on CPU1
11624 12:46:25.879867 <6>[ 26.602727] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11625 12:46:25.886337 <6>[ 26.602779] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11626 12:46:25.890043 <6>[ 26.603336] CPU1 is up
11627 12:46:25.893168 <6>[ 26.603456] Detected VIPT I-cache on CPU2
11628 12:46:25.899910 <6>[ 26.603502] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11629 12:46:25.906637 <6>[ 26.603533] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11630 12:46:25.909803 <6>[ 26.603950] CPU2 is up
11631 12:46:25.913250 <6>[ 26.604065] Detected VIPT I-cache on CPU3
11632 12:46:25.922785 <6>[ 26.604111] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11633 12:46:25.929651 <6>[ 26.604142] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11634 12:46:25.930270 <6>[ 26.604558] CPU3 is up
11635 12:46:25.936301 <6>[ 26.604671] Detected PIPT I-cache on CPU4
11636 12:46:25.943189 <6>[ 26.604693] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11637 12:46:25.949411 <6>[ 26.604707] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11638 12:46:25.952650 <6>[ 26.604987] CPU4 is up
11639 12:46:25.955971 <6>[ 26.605107] Detected PIPT I-cache on CPU5
11640 12:46:25.962598 <6>[ 26.605129] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11641 12:46:25.969479 <6>[ 26.605143] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11642 12:46:25.972745 <6>[ 26.605370] CPU5 is up
11643 12:46:25.976232 <6>[ 26.605483] Detected PIPT I-cache on CPU6
11644 12:46:25.982898 <6>[ 26.605510] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11645 12:46:25.989654 <6>[ 26.605524] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11646 12:46:25.992779 <6>[ 26.605759] CPU6 is up
11647 12:46:25.996093 <6>[ 26.605869] Detected PIPT I-cache on CPU7
11648 12:46:26.006064 <6>[ 26.605896] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11649 12:46:26.012763 <6>[ 26.605909] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11650 12:46:26.016228 <6>[ 26.606149] CPU7 is up
11651 12:46:26.019645 <6>[ 27.142187] OOM killer enabled.
11652 12:46:26.022581 <6>[ 27.145578] Restarting tasks ... done.
11653 12:46:26.029651 <5>[ 27.149966] random: crng reseeded on system resumption
11654 12:46:26.032805 <6>[ 27.156563] PM: suspend exit
11655 12:46:26.040717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=pass>
11656 12:46:26.041574 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=pass
11658 12:46:26.044152 rtcwake: assuming RTC uses UTC ...
11659 12:46:26.050913 rtcwake: wakeup from "mem" using rtc0 at Mon Feb 5 12:45:52 2024
11660 12:46:26.063789 <6>[ 27.186363] PM: suspend entry (deep)
11661 12:46:26.066791 <6>[ 27.190218] Filesystems sync: 0.000 seconds
11662 12:46:26.070364 <6>[ 27.194977] Freezing user space processes
11663 12:46:26.081200 <6>[ 27.200686] Freezing user space processes completed (elapsed 0.001 seconds)
11664 12:46:26.084463 <6>[ 27.207924] OOM killer disabled.
11665 12:46:26.088227 <6>[ 27.211405] Freezing remaining freezable tasks
11666 12:46:26.098051 <6>[ 27.217342] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11667 12:46:26.104463 <6>[ 27.225013] printk: Suspending console(s) (use no_console_suspend to debug)
11668 12:46:31.838934 <6>[ 27.305394] Disabling non-boot CPUs ...
11669 12:46:31.842779 <4>[ 27.306176] migrate_one_irq: 88 callbacks suppressed
11670 12:46:31.849016 <4>[ 27.306186] IRQ282: set affinity failed(-22).
11671 12:46:31.852312 <4>[ 27.306194] IRQ284: set affinity failed(-22).
11672 12:46:31.855382 <6>[ 27.307263] psci: CPU1 killed (polled 4 ms)
11673 12:46:31.862427 <4>[ 27.308176] IRQ282: set affinity failed(-22).
11674 12:46:31.865589 <4>[ 27.308185] IRQ284: set affinity failed(-22).
11675 12:46:31.869041 <6>[ 27.309240] psci: CPU2 killed (polled 0 ms)
11676 12:46:31.875584 <4>[ 27.309951] IRQ282: set affinity failed(-22).
11677 12:46:31.878790 <4>[ 27.309961] IRQ284: set affinity failed(-22).
11678 12:46:31.885698 <6>[ 27.310001] psci: CPU3 killed (polled 0 ms)
11679 12:46:31.889094 <4>[ 27.310311] IRQ282: set affinity failed(-22).
11680 12:46:31.892354 <4>[ 27.310315] IRQ284: set affinity failed(-22).
11681 12:46:31.898726 <6>[ 27.310340] psci: CPU4 killed (polled 0 ms)
11682 12:46:31.902361 <4>[ 27.310867] IRQ282: set affinity failed(-22).
11683 12:46:31.905527 <4>[ 27.310872] IRQ284: set affinity failed(-22).
11684 12:46:31.912016 <6>[ 27.310902] psci: CPU5 killed (polled 0 ms)
11685 12:46:31.915739 <6>[ 27.311437] psci: CPU6 killed (polled 0 ms)
11686 12:46:31.918990 <6>[ 27.312044] psci: CPU7 killed (polled 0 ms)
11687 12:46:31.925573 <6>[ 27.312398] Enabling non-boot CPUs ...
11688 12:46:31.929163 <6>[ 27.312611] Detected VIPT I-cache on CPU1
11689 12:46:31.935388 <6>[ 27.312689] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11690 12:46:31.942075 <6>[ 27.312742] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11691 12:46:31.945453 <6>[ 27.313302] CPU1 is up
11692 12:46:31.948994 <6>[ 27.313425] Detected VIPT I-cache on CPU2
11693 12:46:31.955754 <6>[ 27.313471] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11694 12:46:31.965307 <6>[ 27.313502] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11695 12:46:31.965880 <6>[ 27.313926] CPU2 is up
11696 12:46:31.972197 <6>[ 27.314041] Detected VIPT I-cache on CPU3
11697 12:46:31.978541 <6>[ 27.314087] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11698 12:46:31.985818 <6>[ 27.314117] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11699 12:46:31.988872 <6>[ 27.314563] CPU3 is up
11700 12:46:31.991951 <6>[ 27.314680] Detected PIPT I-cache on CPU4
11701 12:46:31.998744 <6>[ 27.314702] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11702 12:46:32.005896 <6>[ 27.314716] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11703 12:46:32.008484 <6>[ 27.314971] CPU4 is up
11704 12:46:32.011854 <6>[ 27.315092] Detected PIPT I-cache on CPU5
11705 12:46:32.018811 <6>[ 27.315113] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11706 12:46:32.025736 <6>[ 27.315128] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11707 12:46:32.029192 <6>[ 27.315358] CPU5 is up
11708 12:46:32.032359 <6>[ 27.315469] Detected PIPT I-cache on CPU6
11709 12:46:32.042209 <6>[ 27.315496] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11710 12:46:32.049105 <6>[ 27.315511] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11711 12:46:32.049684 <6>[ 27.315744] CPU6 is up
11712 12:46:32.055607 <6>[ 27.315856] Detected PIPT I-cache on CPU7
11713 12:46:32.062154 <6>[ 27.315884] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11714 12:46:32.069157 <6>[ 27.315897] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11715 12:46:32.072368 <6>[ 27.316142] CPU7 is up
11716 12:46:32.075575 <6>[ 27.909598] OOM killer enabled.
11717 12:46:32.078487 <6>[ 27.912990] Restarting tasks ... done.
11718 12:46:32.085632 <5>[ 27.917380] random: crng reseeded on system resumption
11719 12:46:32.089146 <6>[ 27.923666] PM: suspend exit
11720 12:46:32.097289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=pass>
11721 12:46:32.098179 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=pass
11723 12:46:32.101005 rtcwake: assuming RTC uses UTC ...
11724 12:46:32.107456 rtcwake: wakeup from "mem" using rtc0 at Mon Feb 5 12:45:58 2024
11725 12:46:32.120346 <6>[ 27.953669] PM: suspend entry (deep)
11726 12:46:32.123871 <6>[ 27.957579] Filesystems sync: 0.000 seconds
11727 12:46:32.126591 <6>[ 27.962324] Freezing user space processes
11728 12:46:32.137744 <6>[ 27.968003] Freezing user space processes completed (elapsed 0.001 seconds)
11729 12:46:32.141252 <6>[ 27.975234] OOM killer disabled.
11730 12:46:32.144348 <6>[ 27.978715] Freezing remaining freezable tasks
11731 12:46:32.154846 <6>[ 27.984642] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11732 12:46:32.161113 <6>[ 27.992305] printk: Suspending console(s) (use no_console_suspend to debug)
11733 12:46:37.841067 <6>[ 28.066493] Disabling non-boot CPUs ...
11734 12:46:37.844589 <6>[ 28.067486] psci: CPU1 killed (polled 0 ms)
11735 12:46:37.847700 <6>[ 28.068610] psci: CPU2 killed (polled 0 ms)
11736 12:46:37.854345 <6>[ 28.070651] psci: CPU3 killed (polled 4 ms)
11737 12:46:37.857715 <6>[ 28.071125] psci: CPU4 killed (polled 0 ms)
11738 12:46:37.860718 <6>[ 28.071725] psci: CPU5 killed (polled 0 ms)
11739 12:46:37.867785 <6>[ 28.072316] psci: CPU6 killed (polled 0 ms)
11740 12:46:37.871012 <6>[ 28.072830] psci: CPU7 killed (polled 0 ms)
11741 12:46:37.874225 <6>[ 28.073172] Enabling non-boot CPUs ...
11742 12:46:37.881083 <6>[ 28.073405] Detected VIPT I-cache on CPU1
11743 12:46:37.887425 <6>[ 28.073492] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11744 12:46:37.894077 <6>[ 28.073552] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11745 12:46:37.897406 <6>[ 28.074293] CPU1 is up
11746 12:46:37.900743 <6>[ 28.074439] Detected VIPT I-cache on CPU2
11747 12:46:37.907316 <6>[ 28.074494] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11748 12:46:37.913725 <6>[ 28.074531] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11749 12:46:37.917340 <6>[ 28.075042] CPU2 is up
11750 12:46:37.920865 <6>[ 28.075179] Detected VIPT I-cache on CPU3
11751 12:46:37.927221 <6>[ 28.075235] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11752 12:46:37.933888 <6>[ 28.075272] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11753 12:46:37.937375 <6>[ 28.075803] CPU3 is up
11754 12:46:37.944070 <6>[ 28.075927] Detected PIPT I-cache on CPU4
11755 12:46:37.950651 <6>[ 28.075949] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11756 12:46:37.957370 <6>[ 28.075963] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11757 12:46:37.960895 <6>[ 28.076231] CPU4 is up
11758 12:46:37.964091 <6>[ 28.076351] Detected PIPT I-cache on CPU5
11759 12:46:37.970684 <6>[ 28.076373] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11760 12:46:37.977178 <6>[ 28.076386] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11761 12:46:37.980386 <6>[ 28.076616] CPU5 is up
11762 12:46:37.983412 <6>[ 28.076738] Detected PIPT I-cache on CPU6
11763 12:46:37.990484 <6>[ 28.076766] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11764 12:46:37.996906 <6>[ 28.076780] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11765 12:46:38.000506 <6>[ 28.077017] CPU6 is up
11766 12:46:38.006728 <6>[ 28.077136] Detected PIPT I-cache on CPU7
11767 12:46:38.013202 <6>[ 28.077164] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11768 12:46:38.020020 <6>[ 28.077178] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11769 12:46:38.023608 <6>[ 28.077424] CPU7 is up
11770 12:46:38.026661 <6>[ 28.622059] OOM killer enabled.
11771 12:46:38.029728 <6>[ 28.625451] Restarting tasks ... done.
11772 12:46:38.036769 <5>[ 28.629850] random: crng reseeded on system resumption
11773 12:46:38.040038 <6>[ 28.636156] PM: suspend exit
11774 12:46:38.047636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=pass>
11775 12:46:38.048578 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=pass
11777 12:46:38.050865 rtcwake: assuming RTC uses UTC ...
11778 12:46:38.057688 rtcwake: wakeup from "mem" using rtc0 at Mon Feb 5 12:46:04 2024
11779 12:46:38.070909 <6>[ 28.665622] PM: suspend entry (deep)
11780 12:46:38.074307 <6>[ 28.669485] Filesystems sync: 0.000 seconds
11781 12:46:38.077606 <6>[ 28.674245] Freezing user space processes
11782 12:46:38.088413 <6>[ 28.679920] Freezing user space processes completed (elapsed 0.001 seconds)
11783 12:46:38.091778 <6>[ 28.687147] OOM killer disabled.
11784 12:46:38.095334 <6>[ 28.690629] Freezing remaining freezable tasks
11785 12:46:38.104852 <6>[ 28.696565] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11786 12:46:38.111556 <6>[ 28.704227] printk: Suspending console(s) (use no_console_suspend to debug)
11787 12:46:43.832756 <6>[ 28.780776] Disabling non-boot CPUs ...
11788 12:46:43.836095 <6>[ 28.782626] psci: CPU1 killed (polled 4 ms)
11789 12:46:43.839269 <6>[ 28.784492] psci: CPU2 killed (polled 0 ms)
11790 12:46:43.846156 <6>[ 28.786216] psci: CPU3 killed (polled 4 ms)
11791 12:46:43.849376 <6>[ 28.786658] psci: CPU4 killed (polled 0 ms)
11792 12:46:43.852210 <6>[ 28.787202] psci: CPU5 killed (polled 0 ms)
11793 12:46:43.859149 <6>[ 28.787735] psci: CPU6 killed (polled 0 ms)
11794 12:46:43.862578 <6>[ 28.788327] psci: CPU7 killed (polled 0 ms)
11795 12:46:43.866086 <6>[ 28.788659] Enabling non-boot CPUs ...
11796 12:46:43.872872 <6>[ 28.788868] Detected VIPT I-cache on CPU1
11797 12:46:43.879345 <6>[ 28.788946] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11798 12:46:43.885761 <6>[ 28.788999] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11799 12:46:43.889561 <6>[ 28.789564] CPU1 is up
11800 12:46:43.892755 <6>[ 28.789684] Detected VIPT I-cache on CPU2
11801 12:46:43.899348 <6>[ 28.789731] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11802 12:46:43.906140 <6>[ 28.789761] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11803 12:46:43.909573 <6>[ 28.790209] CPU2 is up
11804 12:46:43.913069 <6>[ 28.790327] Detected VIPT I-cache on CPU3
11805 12:46:43.919664 <6>[ 28.790373] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11806 12:46:43.926112 <6>[ 28.790404] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11807 12:46:43.929762 <6>[ 28.790826] CPU3 is up
11808 12:46:43.932455 <6>[ 28.790939] Detected PIPT I-cache on CPU4
11809 12:46:43.942798 <6>[ 28.790961] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11810 12:46:43.949185 <6>[ 28.790975] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11811 12:46:43.949748 <6>[ 28.791237] CPU4 is up
11812 12:46:43.955621 <6>[ 28.791358] Detected PIPT I-cache on CPU5
11813 12:46:43.962573 <6>[ 28.791379] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11814 12:46:43.969624 <6>[ 28.791394] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11815 12:46:43.972517 <6>[ 28.791631] CPU5 is up
11816 12:46:43.975840 <6>[ 28.791741] Detected PIPT I-cache on CPU6
11817 12:46:43.982744 <6>[ 28.791768] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11818 12:46:43.989432 <6>[ 28.791782] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11819 12:46:43.992282 <6>[ 28.792014] CPU6 is up
11820 12:46:43.996072 <6>[ 28.792124] Detected PIPT I-cache on CPU7
11821 12:46:44.002624 <6>[ 28.792152] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11822 12:46:44.009620 <6>[ 28.792166] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11823 12:46:44.012541 <6>[ 28.792406] CPU7 is up
11824 12:46:44.015960 <6>[ 29.330143] OOM killer enabled.
11825 12:46:44.022896 <6>[ 29.333533] Restarting tasks ... done.
11826 12:46:44.026032 <5>[ 29.337881] random: crng reseeded on system resumption
11827 12:46:44.028986 <6>[ 29.344138] PM: suspend exit
11828 12:46:44.041188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=pass>
11829 12:46:44.041755 + set +x
11830 12:46:44.042499 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=pass
11832 12:46:44.047460 <LAVA_SIGNAL_ENDRUN 0_sleep 12703558_1.5.2.3.1>
11833 12:46:44.047933 <LAVA_TEST_RUNNER EXIT>
11834 12:46:44.048559 Received signal: <ENDRUN> 0_sleep 12703558_1.5.2.3.1
11835 12:46:44.048982 Ending use of test pattern.
11836 12:46:44.049321 Ending test lava.0_sleep (12703558_1.5.2.3.1), duration 60.56
11838 12:46:44.050566 ok: lava_test_shell seems to have completed
11839 12:46:44.051325 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-mem-1: pass
rtcwake-mem-10: pass
rtcwake-mem-2: pass
rtcwake-mem-3: pass
rtcwake-mem-4: pass
rtcwake-mem-5: pass
rtcwake-mem-6: pass
rtcwake-mem-7: pass
rtcwake-mem-8: pass
rtcwake-mem-9: pass
11840 12:46:44.051792 end: 3.1 lava-test-shell (duration 00:01:01) [common]
11841 12:46:44.052235 end: 3 lava-test-retry (duration 00:01:01) [common]
11842 12:46:44.052696 start: 4 finalize (timeout 00:06:16) [common]
11843 12:46:44.053155 start: 4.1 power-off (timeout 00:00:30) [common]
11844 12:46:44.054013 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11845 12:46:44.173626 >> Command sent successfully.
11846 12:46:44.177195 Returned 0 in 0 seconds
11847 12:46:44.278175 end: 4.1 power-off (duration 00:00:00) [common]
11849 12:46:44.279760 start: 4.2 read-feedback (timeout 00:06:16) [common]
11850 12:46:44.280940 Listened to connection for namespace 'common' for up to 1s
11851 12:46:45.281793 Finalising connection for namespace 'common'
11852 12:46:45.282562 Disconnecting from shell: Finalise
11853 12:46:45.283000 / #
11854 12:46:45.383995 end: 4.2 read-feedback (duration 00:00:01) [common]
11855 12:46:45.384663 end: 4 finalize (duration 00:00:01) [common]
11856 12:46:45.385228 Cleaning after the job
11857 12:46:45.385744 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703558/tftp-deploy-so37e02b/ramdisk
11858 12:46:45.426048 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703558/tftp-deploy-so37e02b/kernel
11859 12:46:45.451796 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703558/tftp-deploy-so37e02b/dtb
11860 12:46:45.452032 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703558/tftp-deploy-so37e02b/modules
11861 12:46:45.457742 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12703558
11862 12:46:45.595971 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12703558
11863 12:46:45.596146 Job finished correctly