Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 1
- Kernel Warnings: 16
- Kernel Errors: 35
1 12:39:27.712245 lava-dispatcher, installed at version: 2024.01
2 12:39:27.712501 start: 0 validate
3 12:39:27.712636 Start time: 2024-02-05 12:39:27.712628+00:00 (UTC)
4 12:39:27.712770 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:39:27.712902 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 12:39:27.987978 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:39:27.988187 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:39:43.253642 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:39:43.253802 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:39:43.517524 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:39:43.517697 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:39:46.281103 validate duration: 18.57
14 12:39:46.281372 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:39:46.281473 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:39:46.281556 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:39:46.281679 Not decompressing ramdisk as can be used compressed.
18 12:39:46.281760 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 12:39:46.281822 saving as /var/lib/lava/dispatcher/tmp/12703534/tftp-deploy-o6tibqjn/ramdisk/rootfs.cpio.gz
20 12:39:46.281882 total size: 26246609 (25 MB)
21 12:39:46.544544 progress 0 % (0 MB)
22 12:39:46.551770 progress 5 % (1 MB)
23 12:39:46.558733 progress 10 % (2 MB)
24 12:39:46.565601 progress 15 % (3 MB)
25 12:39:46.572395 progress 20 % (5 MB)
26 12:39:46.579320 progress 25 % (6 MB)
27 12:39:46.586203 progress 30 % (7 MB)
28 12:39:46.593212 progress 35 % (8 MB)
29 12:39:46.600171 progress 40 % (10 MB)
30 12:39:46.607000 progress 45 % (11 MB)
31 12:39:46.613926 progress 50 % (12 MB)
32 12:39:46.620865 progress 55 % (13 MB)
33 12:39:46.627662 progress 60 % (15 MB)
34 12:39:46.634522 progress 65 % (16 MB)
35 12:39:46.641927 progress 70 % (17 MB)
36 12:39:46.649108 progress 75 % (18 MB)
37 12:39:46.657554 progress 80 % (20 MB)
38 12:39:46.665127 progress 85 % (21 MB)
39 12:39:46.671899 progress 90 % (22 MB)
40 12:39:46.678758 progress 95 % (23 MB)
41 12:39:46.685607 progress 100 % (25 MB)
42 12:39:46.685878 25 MB downloaded in 0.40 s (61.96 MB/s)
43 12:39:46.686031 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:39:46.686270 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:39:46.686355 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:39:46.686436 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:39:46.686570 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:39:46.686637 saving as /var/lib/lava/dispatcher/tmp/12703534/tftp-deploy-o6tibqjn/kernel/Image
50 12:39:46.686698 total size: 51534336 (49 MB)
51 12:39:46.686757 No compression specified
52 12:39:46.687851 progress 0 % (0 MB)
53 12:39:46.701208 progress 5 % (2 MB)
54 12:39:46.715049 progress 10 % (4 MB)
55 12:39:46.728740 progress 15 % (7 MB)
56 12:39:46.742049 progress 20 % (9 MB)
57 12:39:46.755497 progress 25 % (12 MB)
58 12:39:46.768879 progress 30 % (14 MB)
59 12:39:46.782344 progress 35 % (17 MB)
60 12:39:46.795875 progress 40 % (19 MB)
61 12:39:46.809655 progress 45 % (22 MB)
62 12:39:46.824078 progress 50 % (24 MB)
63 12:39:46.838130 progress 55 % (27 MB)
64 12:39:46.851974 progress 60 % (29 MB)
65 12:39:46.865663 progress 65 % (31 MB)
66 12:39:46.879041 progress 70 % (34 MB)
67 12:39:46.892603 progress 75 % (36 MB)
68 12:39:46.906235 progress 80 % (39 MB)
69 12:39:46.919908 progress 85 % (41 MB)
70 12:39:46.933903 progress 90 % (44 MB)
71 12:39:46.947646 progress 95 % (46 MB)
72 12:39:46.961231 progress 100 % (49 MB)
73 12:39:46.961536 49 MB downloaded in 0.27 s (178.82 MB/s)
74 12:39:46.961691 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:39:46.961930 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:39:46.962019 start: 1.3 download-retry (timeout 00:09:59) [common]
78 12:39:46.962103 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 12:39:46.962248 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:39:46.962324 saving as /var/lib/lava/dispatcher/tmp/12703534/tftp-deploy-o6tibqjn/dtb/mt8192-asurada-spherion-r0.dtb
81 12:39:46.962385 total size: 47278 (0 MB)
82 12:39:46.962446 No compression specified
83 12:39:46.963669 progress 69 % (0 MB)
84 12:39:46.963947 progress 100 % (0 MB)
85 12:39:46.964109 0 MB downloaded in 0.00 s (26.20 MB/s)
86 12:39:46.964234 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:39:46.964473 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:39:46.964558 start: 1.4 download-retry (timeout 00:09:59) [common]
90 12:39:46.964640 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 12:39:46.964754 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:39:46.964822 saving as /var/lib/lava/dispatcher/tmp/12703534/tftp-deploy-o6tibqjn/modules/modules.tar
93 12:39:46.964882 total size: 8639964 (8 MB)
94 12:39:46.964943 Using unxz to decompress xz
95 12:39:46.969503 progress 0 % (0 MB)
96 12:39:46.990962 progress 5 % (0 MB)
97 12:39:47.014941 progress 10 % (0 MB)
98 12:39:47.039903 progress 15 % (1 MB)
99 12:39:47.064397 progress 20 % (1 MB)
100 12:39:47.089693 progress 25 % (2 MB)
101 12:39:47.119182 progress 30 % (2 MB)
102 12:39:47.145484 progress 35 % (2 MB)
103 12:39:47.170422 progress 40 % (3 MB)
104 12:39:47.196305 progress 45 % (3 MB)
105 12:39:47.222492 progress 50 % (4 MB)
106 12:39:47.249887 progress 55 % (4 MB)
107 12:39:47.276261 progress 60 % (4 MB)
108 12:39:47.303091 progress 65 % (5 MB)
109 12:39:47.329281 progress 70 % (5 MB)
110 12:39:47.354435 progress 75 % (6 MB)
111 12:39:47.385202 progress 80 % (6 MB)
112 12:39:47.416136 progress 85 % (7 MB)
113 12:39:47.444126 progress 90 % (7 MB)
114 12:39:47.475820 progress 95 % (7 MB)
115 12:39:47.504693 progress 100 % (8 MB)
116 12:39:47.510901 8 MB downloaded in 0.55 s (15.09 MB/s)
117 12:39:47.511256 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:39:47.511663 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:39:47.511799 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:39:47.511936 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:39:47.512060 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:39:47.512192 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:39:47.512511 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2
125 12:39:47.512710 makedir: /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2/lava-12703534/bin
126 12:39:47.512864 makedir: /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2/lava-12703534/tests
127 12:39:47.513013 makedir: /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2/lava-12703534/results
128 12:39:47.513182 Creating /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2/lava-12703534/bin/lava-add-keys
129 12:39:47.513401 Creating /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2/lava-12703534/bin/lava-add-sources
130 12:39:47.513587 Creating /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2/lava-12703534/bin/lava-background-process-start
131 12:39:47.513777 Creating /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2/lava-12703534/bin/lava-background-process-stop
132 12:39:47.513964 Creating /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2/lava-12703534/bin/lava-common-functions
133 12:39:47.514147 Creating /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2/lava-12703534/bin/lava-echo-ipv4
134 12:39:47.514333 Creating /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2/lava-12703534/bin/lava-install-packages
135 12:39:47.514515 Creating /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2/lava-12703534/bin/lava-installed-packages
136 12:39:47.514700 Creating /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2/lava-12703534/bin/lava-os-build
137 12:39:47.514888 Creating /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2/lava-12703534/bin/lava-probe-channel
138 12:39:47.515071 Creating /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2/lava-12703534/bin/lava-probe-ip
139 12:39:47.515260 Creating /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2/lava-12703534/bin/lava-target-ip
140 12:39:47.515443 Creating /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2/lava-12703534/bin/lava-target-mac
141 12:39:47.515625 Creating /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2/lava-12703534/bin/lava-target-storage
142 12:39:47.515815 Creating /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2/lava-12703534/bin/lava-test-case
143 12:39:47.516001 Creating /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2/lava-12703534/bin/lava-test-event
144 12:39:47.516186 Creating /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2/lava-12703534/bin/lava-test-feedback
145 12:39:47.516386 Creating /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2/lava-12703534/bin/lava-test-raise
146 12:39:47.516571 Creating /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2/lava-12703534/bin/lava-test-reference
147 12:39:47.516757 Creating /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2/lava-12703534/bin/lava-test-runner
148 12:39:47.516952 Creating /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2/lava-12703534/bin/lava-test-set
149 12:39:47.517140 Creating /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2/lava-12703534/bin/lava-test-shell
150 12:39:47.517326 Updating /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2/lava-12703534/bin/lava-install-packages (oe)
151 12:39:47.517544 Updating /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2/lava-12703534/bin/lava-installed-packages (oe)
152 12:39:47.517729 Creating /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2/lava-12703534/environment
153 12:39:47.517878 LAVA metadata
154 12:39:47.517997 - LAVA_JOB_ID=12703534
155 12:39:47.518096 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:39:47.518252 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:39:47.518352 skipped lava-vland-overlay
158 12:39:47.518471 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:39:47.518596 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:39:47.518691 skipped lava-multinode-overlay
161 12:39:47.518800 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:39:47.518922 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:39:47.519039 Loading test definitions
164 12:39:47.519186 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:39:47.519297 Using /lava-12703534 at stage 0
166 12:39:47.519738 uuid=12703534_1.5.2.3.1 testdef=None
167 12:39:47.519862 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:39:47.519984 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:39:47.520755 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:39:47.521089 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:39:47.521986 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:39:47.522340 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:39:47.523221 runner path: /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2/lava-12703534/0/tests/0_v4l2-compliance-uvc test_uuid 12703534_1.5.2.3.1
176 12:39:47.523439 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:39:47.523753 Creating lava-test-runner.conf files
179 12:39:47.523852 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12703534/lava-overlay-7jwng1c2/lava-12703534/0 for stage 0
180 12:39:47.523980 - 0_v4l2-compliance-uvc
181 12:39:47.524115 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:39:47.524241 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 12:39:47.534338 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:39:47.534527 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 12:39:47.534653 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:39:47.534776 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:39:47.534899 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 12:39:48.290623 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:39:48.291103 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 12:39:48.291275 extracting modules file /var/lib/lava/dispatcher/tmp/12703534/tftp-deploy-o6tibqjn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12703534/extract-overlay-ramdisk-nm39sf2o/ramdisk
191 12:39:48.548803 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:39:48.548978 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 12:39:48.549074 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12703534/compress-overlay-34_e6a4d/overlay-1.5.2.4.tar.gz to ramdisk
194 12:39:48.549150 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12703534/compress-overlay-34_e6a4d/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12703534/extract-overlay-ramdisk-nm39sf2o/ramdisk
195 12:39:48.556065 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:39:48.556205 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 12:39:48.556312 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:39:48.556408 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 12:39:48.556491 Building ramdisk /var/lib/lava/dispatcher/tmp/12703534/extract-overlay-ramdisk-nm39sf2o/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12703534/extract-overlay-ramdisk-nm39sf2o/ramdisk
200 12:39:49.168199 >> 228459 blocks
201 12:39:53.250852 rename /var/lib/lava/dispatcher/tmp/12703534/extract-overlay-ramdisk-nm39sf2o/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12703534/tftp-deploy-o6tibqjn/ramdisk/ramdisk.cpio.gz
202 12:39:53.251539 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 12:39:53.251784 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 12:39:53.251983 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 12:39:53.252202 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12703534/tftp-deploy-o6tibqjn/kernel/Image'
206 12:40:06.620433 Returned 0 in 13 seconds
207 12:40:06.721155 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12703534/tftp-deploy-o6tibqjn/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12703534/tftp-deploy-o6tibqjn/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12703534/tftp-deploy-o6tibqjn/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12703534/tftp-deploy-o6tibqjn/kernel/image.itb
208 12:40:07.365912 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:40:07.366325 output: Created: Mon Feb 5 12:40:07 2024
210 12:40:07.366416 output: Image 0 (kernel-1)
211 12:40:07.366488 output: Description:
212 12:40:07.366551 output: Created: Mon Feb 5 12:40:07 2024
213 12:40:07.366615 output: Type: Kernel Image
214 12:40:07.366675 output: Compression: lzma compressed
215 12:40:07.366736 output: Data Size: 12052857 Bytes = 11770.37 KiB = 11.49 MiB
216 12:40:07.366794 output: Architecture: AArch64
217 12:40:07.366851 output: OS: Linux
218 12:40:07.366906 output: Load Address: 0x00000000
219 12:40:07.366960 output: Entry Point: 0x00000000
220 12:40:07.367013 output: Hash algo: crc32
221 12:40:07.367065 output: Hash value: 8a14336a
222 12:40:07.367117 output: Image 1 (fdt-1)
223 12:40:07.367184 output: Description: mt8192-asurada-spherion-r0
224 12:40:07.367241 output: Created: Mon Feb 5 12:40:07 2024
225 12:40:07.367307 output: Type: Flat Device Tree
226 12:40:07.367364 output: Compression: uncompressed
227 12:40:07.367417 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 12:40:07.367470 output: Architecture: AArch64
229 12:40:07.367532 output: Hash algo: crc32
230 12:40:07.367602 output: Hash value: cc4352de
231 12:40:07.367661 output: Image 2 (ramdisk-1)
232 12:40:07.367727 output: Description: unavailable
233 12:40:07.367799 output: Created: Mon Feb 5 12:40:07 2024
234 12:40:07.367876 output: Type: RAMDisk Image
235 12:40:07.367939 output: Compression: Unknown Compression
236 12:40:07.367995 output: Data Size: 39360831 Bytes = 38438.31 KiB = 37.54 MiB
237 12:40:07.368049 output: Architecture: AArch64
238 12:40:07.368101 output: OS: Linux
239 12:40:07.368153 output: Load Address: unavailable
240 12:40:07.368205 output: Entry Point: unavailable
241 12:40:07.368263 output: Hash algo: crc32
242 12:40:07.368365 output: Hash value: 8f7fdfc5
243 12:40:07.368451 output: Default Configuration: 'conf-1'
244 12:40:07.368519 output: Configuration 0 (conf-1)
245 12:40:07.368572 output: Description: mt8192-asurada-spherion-r0
246 12:40:07.368623 output: Kernel: kernel-1
247 12:40:07.368712 output: Init Ramdisk: ramdisk-1
248 12:40:07.368794 output: FDT: fdt-1
249 12:40:07.368875 output: Loadables: kernel-1
250 12:40:07.368929 output:
251 12:40:07.369149 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 12:40:07.369252 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 12:40:07.369364 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 12:40:07.369475 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 12:40:07.369562 No LXC device requested
256 12:40:07.369644 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:40:07.369748 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 12:40:07.369830 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:40:07.369920 Checking files for TFTP limit of 4294967296 bytes.
260 12:40:07.370448 end: 1 tftp-deploy (duration 00:00:21) [common]
261 12:40:07.370554 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:40:07.370645 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:40:07.370770 substitutions:
264 12:40:07.370846 - {DTB}: 12703534/tftp-deploy-o6tibqjn/dtb/mt8192-asurada-spherion-r0.dtb
265 12:40:07.370926 - {INITRD}: 12703534/tftp-deploy-o6tibqjn/ramdisk/ramdisk.cpio.gz
266 12:40:07.370991 - {KERNEL}: 12703534/tftp-deploy-o6tibqjn/kernel/Image
267 12:40:07.371049 - {LAVA_MAC}: None
268 12:40:07.371105 - {PRESEED_CONFIG}: None
269 12:40:07.371169 - {PRESEED_LOCAL}: None
270 12:40:07.371246 - {RAMDISK}: 12703534/tftp-deploy-o6tibqjn/ramdisk/ramdisk.cpio.gz
271 12:40:07.371304 - {ROOT_PART}: None
272 12:40:07.371365 - {ROOT}: None
273 12:40:07.371422 - {SERVER_IP}: 192.168.201.1
274 12:40:07.371476 - {TEE}: None
275 12:40:07.371530 Parsed boot commands:
276 12:40:07.371586 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:40:07.371796 Parsed boot commands: tftpboot 192.168.201.1 12703534/tftp-deploy-o6tibqjn/kernel/image.itb 12703534/tftp-deploy-o6tibqjn/kernel/cmdline
278 12:40:07.371901 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:40:07.371997 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:40:07.372105 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:40:07.372192 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:40:07.372264 Not connected, no need to disconnect.
283 12:40:07.372400 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:40:07.372482 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:40:07.372572 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 12:40:07.376906 Setting prompt string to ['lava-test: # ']
287 12:40:07.377326 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:40:07.377441 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:40:07.377553 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:40:07.377645 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:40:07.377881 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 12:40:12.515970 >> Command sent successfully.
293 12:40:12.518410 Returned 0 in 5 seconds
294 12:40:12.618777 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:40:12.619157 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:40:12.619271 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:40:12.619360 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:40:12.619427 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:40:12.619493 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:40:12.619766 [Enter `^Ec?' for help]
302 12:40:12.792344
303 12:40:12.792494
304 12:40:12.792559 F0: 102B 0000
305 12:40:12.792621
306 12:40:12.792681 F3: 1001 0000 [0200]
307 12:40:12.795304
308 12:40:12.795433 F3: 1001 0000
309 12:40:12.795498
310 12:40:12.795557 F7: 102D 0000
311 12:40:12.795614
312 12:40:12.799021 F1: 0000 0000
313 12:40:12.799103
314 12:40:12.799176 V0: 0000 0000 [0001]
315 12:40:12.799260
316 12:40:12.802071 00: 0007 8000
317 12:40:12.802156
318 12:40:12.802220 01: 0000 0000
319 12:40:12.802298
320 12:40:12.805329 BP: 0C00 0209 [0000]
321 12:40:12.805410
322 12:40:12.805474 G0: 1182 0000
323 12:40:12.805533
324 12:40:12.809131 EC: 0000 0021 [4000]
325 12:40:12.809214
326 12:40:12.809320 S7: 0000 0000 [0000]
327 12:40:12.809414
328 12:40:12.812617 CC: 0000 0000 [0001]
329 12:40:12.812707
330 12:40:12.812799 T0: 0000 0040 [010F]
331 12:40:12.812862
332 12:40:12.812921 Jump to BL
333 12:40:12.812978
334 12:40:12.838887
335 12:40:12.839069
336 12:40:12.839141
337 12:40:12.846471 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:40:12.849606 ARM64: Exception handlers installed.
339 12:40:12.853730 ARM64: Testing exception
340 12:40:12.857117 ARM64: Done test exception
341 12:40:12.863865 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:40:12.874113 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:40:12.880628 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:40:12.890789 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:40:12.897333 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:40:12.904152 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:40:12.915660 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:40:12.923016 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:40:12.941768 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:40:12.945228 WDT: Last reset was cold boot
351 12:40:12.948589 SPI1(PAD0) initialized at 2873684 Hz
352 12:40:12.951858 SPI5(PAD0) initialized at 992727 Hz
353 12:40:12.955339 VBOOT: Loading verstage.
354 12:40:12.961983 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:40:12.966118 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:40:12.969506 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:40:12.972131 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:40:12.979618 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:40:12.986412 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:40:12.996987 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 12:40:12.997158
362 12:40:12.997269
363 12:40:13.007476 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:40:13.011129 ARM64: Exception handlers installed.
365 12:40:13.014522 ARM64: Testing exception
366 12:40:13.014657 ARM64: Done test exception
367 12:40:13.020954 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:40:13.024276 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:40:13.038264 Probing TPM: . done!
370 12:40:13.038439 TPM ready after 0 ms
371 12:40:13.045105 Connected to device vid:did:rid of 1ae0:0028:00
372 12:40:13.051953 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 12:40:13.111102 Initialized TPM device CR50 revision 0
374 12:40:13.122561 tlcl_send_startup: Startup return code is 0
375 12:40:13.122701 TPM: setup succeeded
376 12:40:13.133803 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:40:13.143076 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:40:13.154960 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:40:13.165480 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:40:13.169217 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:40:13.172503 in-header: 03 07 00 00 08 00 00 00
382 12:40:13.176757 in-data: aa e4 47 04 13 02 00 00
383 12:40:13.176887 Chrome EC: UHEPI supported
384 12:40:13.184043 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:40:13.187595 in-header: 03 95 00 00 08 00 00 00
386 12:40:13.191591 in-data: 18 20 20 08 00 00 00 00
387 12:40:13.191720 Phase 1
388 12:40:13.195184 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:40:13.202474 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:40:13.209819 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:40:13.209993 Recovery requested (1009000e)
392 12:40:13.220708 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:40:13.225331 tlcl_extend: response is 0
394 12:40:13.235064 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:40:13.240184 tlcl_extend: response is 0
396 12:40:13.247433 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:40:13.267422 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 12:40:13.274191 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 12:40:13.274306
400 12:40:13.274374
401 12:40:13.283756 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:40:13.286905 ARM64: Exception handlers installed.
403 12:40:13.290295 ARM64: Testing exception
404 12:40:13.290443 ARM64: Done test exception
405 12:40:13.312937 pmic_efuse_setting: Set efuses in 11 msecs
406 12:40:13.316238 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:40:13.322453 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:40:13.326452 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:40:13.333344 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:40:13.336738 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:40:13.340675 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:40:13.347796 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:40:13.351699 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:40:13.355411 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:40:13.358596 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:40:13.365463 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:40:13.369457 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:40:13.372883 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:40:13.380261 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:40:13.384472 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:40:13.391772 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:40:13.395154 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:40:13.402569 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:40:13.406034 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:40:13.414112 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:40:13.418004 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:40:13.425461 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:40:13.428676 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:40:13.436399 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:40:13.440267 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:40:13.447700 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:40:13.451659 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:40:13.458712 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:40:13.462500 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:40:13.466298 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:40:13.473509 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:40:13.476970 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:40:13.480963 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:40:13.488392 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:40:13.491731 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:40:13.495174 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:40:13.503430 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:40:13.506876 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:40:13.510933 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:40:13.517551 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:40:13.521661 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:40:13.525161 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:40:13.529033 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:40:13.532414 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:40:13.540200 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:40:13.543929 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:40:13.547780 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:40:13.551734 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:40:13.555273 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:40:13.558986 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:40:13.562791 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:40:13.566485 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:40:13.576999 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:40:13.585249 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:40:13.588195 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:40:13.596170 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:40:13.607109 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:40:13.610701 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:40:13.614811 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:40:13.618218 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:40:13.625881 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x38
467 12:40:13.633234 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:40:13.636421 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 12:40:13.639919 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:40:13.650640 [RTC]rtc_get_frequency_meter,154: input=15, output=759
471 12:40:13.659909 [RTC]rtc_get_frequency_meter,154: input=23, output=942
472 12:40:13.669842 [RTC]rtc_get_frequency_meter,154: input=19, output=851
473 12:40:13.679163 [RTC]rtc_get_frequency_meter,154: input=17, output=804
474 12:40:13.688676 [RTC]rtc_get_frequency_meter,154: input=16, output=783
475 12:40:13.698148 [RTC]rtc_get_frequency_meter,154: input=16, output=783
476 12:40:13.707923 [RTC]rtc_get_frequency_meter,154: input=17, output=804
477 12:40:13.711331 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 12:40:13.718622 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 12:40:13.722784 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 12:40:13.726258 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 12:40:13.730273 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 12:40:13.733707 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 12:40:13.737635 ADC[4]: Raw value=905834 ID=7
484 12:40:13.737718 ADC[3]: Raw value=213441 ID=1
485 12:40:13.740893 RAM Code: 0x71
486 12:40:13.745003 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 12:40:13.751901 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 12:40:13.758590 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 12:40:13.766431 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 12:40:13.769748 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 12:40:13.773430 in-header: 03 07 00 00 08 00 00 00
492 12:40:13.777325 in-data: aa e4 47 04 13 02 00 00
493 12:40:13.777405 Chrome EC: UHEPI supported
494 12:40:13.784911 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 12:40:13.788134 in-header: 03 95 00 00 08 00 00 00
496 12:40:13.791419 in-data: 18 20 20 08 00 00 00 00
497 12:40:13.795628 MRC: failed to locate region type 0.
498 12:40:13.803095 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 12:40:13.806478 DRAM-K: Running full calibration
500 12:40:13.810634 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 12:40:13.814267 header.status = 0x0
502 12:40:13.817891 header.version = 0x6 (expected: 0x6)
503 12:40:13.817973 header.size = 0xd00 (expected: 0xd00)
504 12:40:13.821661 header.flags = 0x0
505 12:40:13.828942 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 12:40:13.845464 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 12:40:13.853431 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 12:40:13.856793 dram_init: ddr_geometry: 2
509 12:40:13.856903 [EMI] MDL number = 2
510 12:40:13.860907 [EMI] Get MDL freq = 0
511 12:40:13.861006 dram_init: ddr_type: 0
512 12:40:13.864895 is_discrete_lpddr4: 1
513 12:40:13.868139 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 12:40:13.868249
515 12:40:13.868384
516 12:40:13.868461 [Bian_co] ETT version 0.0.0.1
517 12:40:13.875607 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 12:40:13.875692
519 12:40:13.879195 dramc_set_vcore_voltage set vcore to 650000
520 12:40:13.879277 Read voltage for 800, 4
521 12:40:13.883129 Vio18 = 0
522 12:40:13.883226 Vcore = 650000
523 12:40:13.883304 Vdram = 0
524 12:40:13.883365 Vddq = 0
525 12:40:13.887233 Vmddr = 0
526 12:40:13.887313 dram_init: config_dvfs: 1
527 12:40:13.894104 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 12:40:13.898087 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 12:40:13.901955 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 12:40:13.905971 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 12:40:13.910057 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 12:40:13.913339 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 12:40:13.917422 MEM_TYPE=3, freq_sel=18
534 12:40:13.917507 sv_algorithm_assistance_LP4_1600
535 12:40:13.924036 ============ PULL DRAM RESETB DOWN ============
536 12:40:13.926953 ========== PULL DRAM RESETB DOWN end =========
537 12:40:13.930434 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 12:40:13.933573 ===================================
539 12:40:13.937634 LPDDR4 DRAM CONFIGURATION
540 12:40:13.941011 ===================================
541 12:40:13.941115 EX_ROW_EN[0] = 0x0
542 12:40:13.945265 EX_ROW_EN[1] = 0x0
543 12:40:13.945375 LP4Y_EN = 0x0
544 12:40:13.948496 WORK_FSP = 0x0
545 12:40:13.948580 WL = 0x2
546 12:40:13.952258 RL = 0x2
547 12:40:13.952418 BL = 0x2
548 12:40:13.955950 RPST = 0x0
549 12:40:13.956034 RD_PRE = 0x0
550 12:40:13.959801 WR_PRE = 0x1
551 12:40:13.959884 WR_PST = 0x0
552 12:40:13.963047 DBI_WR = 0x0
553 12:40:13.963131 DBI_RD = 0x0
554 12:40:13.966426 OTF = 0x1
555 12:40:13.969700 ===================================
556 12:40:13.973104 ===================================
557 12:40:13.973212 ANA top config
558 12:40:13.976500 ===================================
559 12:40:13.979723 DLL_ASYNC_EN = 0
560 12:40:13.979807 ALL_SLAVE_EN = 1
561 12:40:13.982876 NEW_RANK_MODE = 1
562 12:40:13.986235 DLL_IDLE_MODE = 1
563 12:40:13.989617 LP45_APHY_COMB_EN = 1
564 12:40:13.992988 TX_ODT_DIS = 1
565 12:40:13.993073 NEW_8X_MODE = 1
566 12:40:13.996967 ===================================
567 12:40:14.000452 ===================================
568 12:40:14.003740 data_rate = 1600
569 12:40:14.006917 CKR = 1
570 12:40:14.010401 DQ_P2S_RATIO = 8
571 12:40:14.013807 ===================================
572 12:40:14.017189 CA_P2S_RATIO = 8
573 12:40:14.017295 DQ_CA_OPEN = 0
574 12:40:14.019990 DQ_SEMI_OPEN = 0
575 12:40:14.023372 CA_SEMI_OPEN = 0
576 12:40:14.026618 CA_FULL_RATE = 0
577 12:40:14.030628 DQ_CKDIV4_EN = 1
578 12:40:14.030712 CA_CKDIV4_EN = 1
579 12:40:14.033279 CA_PREDIV_EN = 0
580 12:40:14.037117 PH8_DLY = 0
581 12:40:14.040238 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 12:40:14.043543 DQ_AAMCK_DIV = 4
583 12:40:14.046753 CA_AAMCK_DIV = 4
584 12:40:14.046835 CA_ADMCK_DIV = 4
585 12:40:14.050008 DQ_TRACK_CA_EN = 0
586 12:40:14.053383 CA_PICK = 800
587 12:40:14.056641 CA_MCKIO = 800
588 12:40:14.060270 MCKIO_SEMI = 0
589 12:40:14.063870 PLL_FREQ = 3068
590 12:40:14.063953 DQ_UI_PI_RATIO = 32
591 12:40:14.067977 CA_UI_PI_RATIO = 0
592 12:40:14.071745 ===================================
593 12:40:14.075450 ===================================
594 12:40:14.079116 memory_type:LPDDR4
595 12:40:14.079232 GP_NUM : 10
596 12:40:14.082589 SRAM_EN : 1
597 12:40:14.082673 MD32_EN : 0
598 12:40:14.086560 ===================================
599 12:40:14.091135 [ANA_INIT] >>>>>>>>>>>>>>
600 12:40:14.091248 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 12:40:14.094593 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 12:40:14.097969 ===================================
603 12:40:14.101362 data_rate = 1600,PCW = 0X7600
604 12:40:14.104683 ===================================
605 12:40:14.108015 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 12:40:14.114604 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 12:40:14.118096 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 12:40:14.124864 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 12:40:14.127592 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 12:40:14.131001 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 12:40:14.131084 [ANA_INIT] flow start
612 12:40:14.134364 [ANA_INIT] PLL >>>>>>>>
613 12:40:14.137767 [ANA_INIT] PLL <<<<<<<<
614 12:40:14.141190 [ANA_INIT] MIDPI >>>>>>>>
615 12:40:14.141273 [ANA_INIT] MIDPI <<<<<<<<
616 12:40:14.144550 [ANA_INIT] DLL >>>>>>>>
617 12:40:14.144636 [ANA_INIT] flow end
618 12:40:14.150898 ============ LP4 DIFF to SE enter ============
619 12:40:14.154735 ============ LP4 DIFF to SE exit ============
620 12:40:14.158119 [ANA_INIT] <<<<<<<<<<<<<
621 12:40:14.161110 [Flow] Enable top DCM control >>>>>
622 12:40:14.164498 [Flow] Enable top DCM control <<<<<
623 12:40:14.167871 Enable DLL master slave shuffle
624 12:40:14.171134 ==============================================================
625 12:40:14.174720 Gating Mode config
626 12:40:14.177738 ==============================================================
627 12:40:14.181428 Config description:
628 12:40:14.191459 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 12:40:14.198035 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 12:40:14.201329 SELPH_MODE 0: By rank 1: By Phase
631 12:40:14.208424 ==============================================================
632 12:40:14.211727 GAT_TRACK_EN = 1
633 12:40:14.215074 RX_GATING_MODE = 2
634 12:40:14.218280 RX_GATING_TRACK_MODE = 2
635 12:40:14.218365 SELPH_MODE = 1
636 12:40:14.221553 PICG_EARLY_EN = 1
637 12:40:14.224936 VALID_LAT_VALUE = 1
638 12:40:14.231904 ==============================================================
639 12:40:14.235170 Enter into Gating configuration >>>>
640 12:40:14.238421 Exit from Gating configuration <<<<
641 12:40:14.241822 Enter into DVFS_PRE_config >>>>>
642 12:40:14.251899 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 12:40:14.255017 Exit from DVFS_PRE_config <<<<<
644 12:40:14.258358 Enter into PICG configuration >>>>
645 12:40:14.261674 Exit from PICG configuration <<<<
646 12:40:14.264735 [RX_INPUT] configuration >>>>>
647 12:40:14.268139 [RX_INPUT] configuration <<<<<
648 12:40:14.271702 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 12:40:14.278229 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 12:40:14.284906 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 12:40:14.291808 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 12:40:14.295261 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 12:40:14.301321 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 12:40:14.305149 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 12:40:14.311801 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 12:40:14.314757 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 12:40:14.318249 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 12:40:14.321384 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 12:40:14.328553 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 12:40:14.332015 ===================================
661 12:40:14.332109 LPDDR4 DRAM CONFIGURATION
662 12:40:14.335419 ===================================
663 12:40:14.338688 EX_ROW_EN[0] = 0x0
664 12:40:14.338780 EX_ROW_EN[1] = 0x0
665 12:40:14.342019 LP4Y_EN = 0x0
666 12:40:14.345270 WORK_FSP = 0x0
667 12:40:14.345355 WL = 0x2
668 12:40:14.348588 RL = 0x2
669 12:40:14.348674 BL = 0x2
670 12:40:14.351997 RPST = 0x0
671 12:40:14.352080 RD_PRE = 0x0
672 12:40:14.355395 WR_PRE = 0x1
673 12:40:14.355503 WR_PST = 0x0
674 12:40:14.358786 DBI_WR = 0x0
675 12:40:14.358870 DBI_RD = 0x0
676 12:40:14.361780 OTF = 0x1
677 12:40:14.365125 ===================================
678 12:40:14.368539 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 12:40:14.371981 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 12:40:14.375275 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 12:40:14.378518 ===================================
682 12:40:14.382194 LPDDR4 DRAM CONFIGURATION
683 12:40:14.385035 ===================================
684 12:40:14.388763 EX_ROW_EN[0] = 0x10
685 12:40:14.388884 EX_ROW_EN[1] = 0x0
686 12:40:14.391843 LP4Y_EN = 0x0
687 12:40:14.391929 WORK_FSP = 0x0
688 12:40:14.394933 WL = 0x2
689 12:40:14.395017 RL = 0x2
690 12:40:14.398701 BL = 0x2
691 12:40:14.398784 RPST = 0x0
692 12:40:14.402177 RD_PRE = 0x0
693 12:40:14.402260 WR_PRE = 0x1
694 12:40:14.404934 WR_PST = 0x0
695 12:40:14.408317 DBI_WR = 0x0
696 12:40:14.408415 DBI_RD = 0x0
697 12:40:14.411699 OTF = 0x1
698 12:40:14.415058 ===================================
699 12:40:14.418493 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 12:40:14.423541 nWR fixed to 40
701 12:40:14.427318 [ModeRegInit_LP4] CH0 RK0
702 12:40:14.427402 [ModeRegInit_LP4] CH0 RK1
703 12:40:14.430177 [ModeRegInit_LP4] CH1 RK0
704 12:40:14.433658 [ModeRegInit_LP4] CH1 RK1
705 12:40:14.433744 match AC timing 13
706 12:40:14.440043 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 12:40:14.443376 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 12:40:14.446674 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 12:40:14.453945 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 12:40:14.456647 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 12:40:14.456733 [EMI DOE] emi_dcm 0
712 12:40:14.463596 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 12:40:14.463709 ==
714 12:40:14.466693 Dram Type= 6, Freq= 0, CH_0, rank 0
715 12:40:14.470648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 12:40:14.470736 ==
717 12:40:14.476819 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 12:40:14.483621 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 12:40:14.490886 [CA 0] Center 36 (6~67) winsize 62
720 12:40:14.494505 [CA 1] Center 36 (6~67) winsize 62
721 12:40:14.497777 [CA 2] Center 34 (3~65) winsize 63
722 12:40:14.501397 [CA 3] Center 33 (3~64) winsize 62
723 12:40:14.504565 [CA 4] Center 33 (3~64) winsize 62
724 12:40:14.508081 [CA 5] Center 32 (3~62) winsize 60
725 12:40:14.508164
726 12:40:14.511015 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 12:40:14.511098
728 12:40:14.514619 [CATrainingPosCal] consider 1 rank data
729 12:40:14.518114 u2DelayCellTimex100 = 270/100 ps
730 12:40:14.521621 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 12:40:14.524559 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 12:40:14.527894 CA2 delay=34 (3~65),Diff = 2 PI (14 cell)
733 12:40:14.534614 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
734 12:40:14.537859 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
735 12:40:14.541110 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
736 12:40:14.541215
737 12:40:14.544899 CA PerBit enable=1, Macro0, CA PI delay=32
738 12:40:14.545096
739 12:40:14.548057 [CBTSetCACLKResult] CA Dly = 32
740 12:40:14.548160 CS Dly: 5 (0~36)
741 12:40:14.548237 ==
742 12:40:14.551317 Dram Type= 6, Freq= 0, CH_0, rank 1
743 12:40:14.558089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 12:40:14.558231 ==
745 12:40:14.561087 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 12:40:14.568134 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 12:40:14.577522 [CA 0] Center 36 (6~67) winsize 62
748 12:40:14.580888 [CA 1] Center 36 (6~67) winsize 62
749 12:40:14.583544 [CA 2] Center 34 (4~65) winsize 62
750 12:40:14.586945 [CA 3] Center 34 (4~65) winsize 62
751 12:40:14.590368 [CA 4] Center 32 (2~63) winsize 62
752 12:40:14.593841 [CA 5] Center 32 (2~63) winsize 62
753 12:40:14.593928
754 12:40:14.597094 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 12:40:14.597197
756 12:40:14.600936 [CATrainingPosCal] consider 2 rank data
757 12:40:14.604114 u2DelayCellTimex100 = 270/100 ps
758 12:40:14.607443 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 12:40:14.610720 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 12:40:14.617491 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 12:40:14.620801 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
762 12:40:14.623858 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
763 12:40:14.627324 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
764 12:40:14.627446
765 12:40:14.630577 CA PerBit enable=1, Macro0, CA PI delay=32
766 12:40:14.630689
767 12:40:14.634099 [CBTSetCACLKResult] CA Dly = 32
768 12:40:14.634182 CS Dly: 5 (0~36)
769 12:40:14.634268
770 12:40:14.637436 ----->DramcWriteLeveling(PI) begin...
771 12:40:14.637510 ==
772 12:40:14.641312 Dram Type= 6, Freq= 0, CH_0, rank 0
773 12:40:14.644793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 12:40:14.648871 ==
775 12:40:14.649003 Write leveling (Byte 0): 33 => 33
776 12:40:14.652680 Write leveling (Byte 1): 32 => 32
777 12:40:14.656137 DramcWriteLeveling(PI) end<-----
778 12:40:14.656244
779 12:40:14.656340 ==
780 12:40:14.659532 Dram Type= 6, Freq= 0, CH_0, rank 0
781 12:40:14.662846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 12:40:14.662956 ==
783 12:40:14.666082 [Gating] SW mode calibration
784 12:40:14.673435 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 12:40:14.680363 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 12:40:14.683325 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 12:40:14.686670 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 12:40:14.693116 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 12:40:14.696544 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 12:40:14.699955 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:40:14.706567 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:40:14.710391 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:40:14.713625 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:40:14.716992 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:40:14.723683 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:40:14.727233 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:40:14.730289 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:40:14.736779 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:40:14.740049 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:40:14.743711 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:40:14.750160 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:40:14.753661 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:40:14.756893 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
804 12:40:14.763633 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 12:40:14.767025 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:40:14.770365 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:40:14.777084 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:40:14.780262 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:40:14.783997 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 12:40:14.786976 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 12:40:14.793748 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:40:14.797363 0 9 8 | B1->B0 | 2323 2d2d | 1 1 | (1 1) (0 0)
813 12:40:14.800156 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
814 12:40:14.807293 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 12:40:14.810596 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 12:40:14.813890 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 12:40:14.820231 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 12:40:14.823527 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 12:40:14.827638 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
820 12:40:14.833827 0 10 8 | B1->B0 | 2f2f 2424 | 1 0 | (1 0) (1 0)
821 12:40:14.837112 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
822 12:40:14.840457 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:40:14.843775 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:40:14.850715 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 12:40:14.854007 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 12:40:14.857538 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:40:14.863994 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 12:40:14.867432 0 11 8 | B1->B0 | 2828 3f3f | 0 0 | (0 0) (0 0)
829 12:40:14.870799 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 12:40:14.877619 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 12:40:14.881003 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 12:40:14.884279 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 12:40:14.890837 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 12:40:14.894004 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 12:40:14.898015 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 12:40:14.904021 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
837 12:40:14.907404 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 12:40:14.911254 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 12:40:14.914347 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:40:14.921389 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:40:14.924239 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:40:14.927574 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:40:14.934256 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:40:14.938170 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:40:14.940936 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:40:14.947562 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:40:14.950873 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:40:14.954175 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 12:40:14.961304 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 12:40:14.964567 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 12:40:14.967694 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 12:40:14.974147 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
853 12:40:14.974283 Total UI for P1: 0, mck2ui 16
854 12:40:14.981123 best dqsien dly found for B0: ( 0, 14, 4)
855 12:40:14.984404 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
856 12:40:14.987690 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 12:40:14.991824 Total UI for P1: 0, mck2ui 16
858 12:40:14.995241 best dqsien dly found for B1: ( 0, 14, 12)
859 12:40:14.998306 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
860 12:40:15.001555 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
861 12:40:15.001674
862 12:40:15.004830 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
863 12:40:15.008151 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
864 12:40:15.011625 [Gating] SW calibration Done
865 12:40:15.011746 ==
866 12:40:15.015014 Dram Type= 6, Freq= 0, CH_0, rank 0
867 12:40:15.018371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 12:40:15.021647 ==
869 12:40:15.021764 RX Vref Scan: 0
870 12:40:15.021858
871 12:40:15.024885 RX Vref 0 -> 0, step: 1
872 12:40:15.024996
873 12:40:15.028220 RX Delay -130 -> 252, step: 16
874 12:40:15.031613 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
875 12:40:15.035099 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
876 12:40:15.038229 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
877 12:40:15.041795 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
878 12:40:15.048148 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
879 12:40:15.051759 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
880 12:40:15.054946 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
881 12:40:15.058637 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
882 12:40:15.062021 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
883 12:40:15.065263 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
884 12:40:15.071863 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
885 12:40:15.075334 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
886 12:40:15.078552 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
887 12:40:15.081648 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
888 12:40:15.088382 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
889 12:40:15.091655 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
890 12:40:15.091738 ==
891 12:40:15.095643 Dram Type= 6, Freq= 0, CH_0, rank 0
892 12:40:15.098487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 12:40:15.098564 ==
894 12:40:15.098628 DQS Delay:
895 12:40:15.102426 DQS0 = 0, DQS1 = 0
896 12:40:15.102502 DQM Delay:
897 12:40:15.105669 DQM0 = 91, DQM1 = 86
898 12:40:15.105778 DQ Delay:
899 12:40:15.108929 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
900 12:40:15.112130 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
901 12:40:15.115547 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
902 12:40:15.118907 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
903 12:40:15.118991
904 12:40:15.119085
905 12:40:15.119165 ==
906 12:40:15.122319 Dram Type= 6, Freq= 0, CH_0, rank 0
907 12:40:15.125024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 12:40:15.128999 ==
909 12:40:15.129081
910 12:40:15.129165
911 12:40:15.129273 TX Vref Scan disable
912 12:40:15.131746 == TX Byte 0 ==
913 12:40:15.135138 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
914 12:40:15.138436 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
915 12:40:15.141876 == TX Byte 1 ==
916 12:40:15.145317 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
917 12:40:15.148660 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
918 12:40:15.148740 ==
919 12:40:15.152195 Dram Type= 6, Freq= 0, CH_0, rank 0
920 12:40:15.158539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 12:40:15.158661 ==
922 12:40:15.170761 TX Vref=22, minBit 10, minWin=27, winSum=448
923 12:40:15.174232 TX Vref=24, minBit 11, minWin=27, winSum=453
924 12:40:15.177655 TX Vref=26, minBit 5, minWin=28, winSum=455
925 12:40:15.180517 TX Vref=28, minBit 10, minWin=27, winSum=454
926 12:40:15.184243 TX Vref=30, minBit 7, minWin=28, winSum=457
927 12:40:15.190840 TX Vref=32, minBit 15, minWin=27, winSum=452
928 12:40:15.194321 [TxChooseVref] Worse bit 7, Min win 28, Win sum 457, Final Vref 30
929 12:40:15.194432
930 12:40:15.197637 Final TX Range 1 Vref 30
931 12:40:15.197733
932 12:40:15.197814 ==
933 12:40:15.200731 Dram Type= 6, Freq= 0, CH_0, rank 0
934 12:40:15.203925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 12:40:15.207221 ==
936 12:40:15.207343
937 12:40:15.207479
938 12:40:15.207578 TX Vref Scan disable
939 12:40:15.211230 == TX Byte 0 ==
940 12:40:15.214516 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
941 12:40:15.220936 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
942 12:40:15.221053 == TX Byte 1 ==
943 12:40:15.224305 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
944 12:40:15.227670 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
945 12:40:15.231091
946 12:40:15.231195 [DATLAT]
947 12:40:15.231292 Freq=800, CH0 RK0
948 12:40:15.231370
949 12:40:15.234236 DATLAT Default: 0xa
950 12:40:15.234331 0, 0xFFFF, sum = 0
951 12:40:15.237529 1, 0xFFFF, sum = 0
952 12:40:15.237627 2, 0xFFFF, sum = 0
953 12:40:15.240864 3, 0xFFFF, sum = 0
954 12:40:15.240977 4, 0xFFFF, sum = 0
955 12:40:15.244192 5, 0xFFFF, sum = 0
956 12:40:15.244305 6, 0xFFFF, sum = 0
957 12:40:15.247586 7, 0xFFFF, sum = 0
958 12:40:15.251072 8, 0xFFFF, sum = 0
959 12:40:15.251151 9, 0x0, sum = 1
960 12:40:15.251235 10, 0x0, sum = 2
961 12:40:15.254503 11, 0x0, sum = 3
962 12:40:15.254580 12, 0x0, sum = 4
963 12:40:15.258002 best_step = 10
964 12:40:15.258078
965 12:40:15.258160 ==
966 12:40:15.260858 Dram Type= 6, Freq= 0, CH_0, rank 0
967 12:40:15.264747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 12:40:15.264824 ==
969 12:40:15.268131 RX Vref Scan: 1
970 12:40:15.268241
971 12:40:15.268339 Set Vref Range= 32 -> 127
972 12:40:15.268423
973 12:40:15.271438 RX Vref 32 -> 127, step: 1
974 12:40:15.271514
975 12:40:15.274746 RX Delay -79 -> 252, step: 8
976 12:40:15.274849
977 12:40:15.278069 Set Vref, RX VrefLevel [Byte0]: 32
978 12:40:15.281295 [Byte1]: 32
979 12:40:15.281368
980 12:40:15.284572 Set Vref, RX VrefLevel [Byte0]: 33
981 12:40:15.287880 [Byte1]: 33
982 12:40:15.291203
983 12:40:15.291275 Set Vref, RX VrefLevel [Byte0]: 34
984 12:40:15.294509 [Byte1]: 34
985 12:40:15.298877
986 12:40:15.298949 Set Vref, RX VrefLevel [Byte0]: 35
987 12:40:15.302354 [Byte1]: 35
988 12:40:15.306630
989 12:40:15.306712 Set Vref, RX VrefLevel [Byte0]: 36
990 12:40:15.310228 [Byte1]: 36
991 12:40:15.314380
992 12:40:15.314468 Set Vref, RX VrefLevel [Byte0]: 37
993 12:40:15.318130 [Byte1]: 37
994 12:40:15.321820
995 12:40:15.321906 Set Vref, RX VrefLevel [Byte0]: 38
996 12:40:15.325417 [Byte1]: 38
997 12:40:15.329294
998 12:40:15.329374 Set Vref, RX VrefLevel [Byte0]: 39
999 12:40:15.332809 [Byte1]: 39
1000 12:40:15.337045
1001 12:40:15.337168 Set Vref, RX VrefLevel [Byte0]: 40
1002 12:40:15.340385 [Byte1]: 40
1003 12:40:15.344234
1004 12:40:15.344354 Set Vref, RX VrefLevel [Byte0]: 41
1005 12:40:15.347704 [Byte1]: 41
1006 12:40:15.351788
1007 12:40:15.351902 Set Vref, RX VrefLevel [Byte0]: 42
1008 12:40:15.355098 [Byte1]: 42
1009 12:40:15.359173
1010 12:40:15.359286 Set Vref, RX VrefLevel [Byte0]: 43
1011 12:40:15.362618 [Byte1]: 43
1012 12:40:15.367027
1013 12:40:15.367147 Set Vref, RX VrefLevel [Byte0]: 44
1014 12:40:15.370391 [Byte1]: 44
1015 12:40:15.374479
1016 12:40:15.374621 Set Vref, RX VrefLevel [Byte0]: 45
1017 12:40:15.377926 [Byte1]: 45
1018 12:40:15.381596
1019 12:40:15.381723 Set Vref, RX VrefLevel [Byte0]: 46
1020 12:40:15.384984 [Byte1]: 46
1021 12:40:15.389561
1022 12:40:15.389703 Set Vref, RX VrefLevel [Byte0]: 47
1023 12:40:15.392871 [Byte1]: 47
1024 12:40:15.396829
1025 12:40:15.396976 Set Vref, RX VrefLevel [Byte0]: 48
1026 12:40:15.400198 [Byte1]: 48
1027 12:40:15.404331
1028 12:40:15.404454 Set Vref, RX VrefLevel [Byte0]: 49
1029 12:40:15.407518 [Byte1]: 49
1030 12:40:15.412174
1031 12:40:15.412310 Set Vref, RX VrefLevel [Byte0]: 50
1032 12:40:15.415425 [Byte1]: 50
1033 12:40:15.419805
1034 12:40:15.419952 Set Vref, RX VrefLevel [Byte0]: 51
1035 12:40:15.422998 [Byte1]: 51
1036 12:40:15.426933
1037 12:40:15.427087 Set Vref, RX VrefLevel [Byte0]: 52
1038 12:40:15.430187 [Byte1]: 52
1039 12:40:15.434931
1040 12:40:15.435040 Set Vref, RX VrefLevel [Byte0]: 53
1041 12:40:15.438158 [Byte1]: 53
1042 12:40:15.442593
1043 12:40:15.442728 Set Vref, RX VrefLevel [Byte0]: 54
1044 12:40:15.445626 [Byte1]: 54
1045 12:40:15.450020
1046 12:40:15.450162 Set Vref, RX VrefLevel [Byte0]: 55
1047 12:40:15.452747 [Byte1]: 55
1048 12:40:15.457158
1049 12:40:15.457269 Set Vref, RX VrefLevel [Byte0]: 56
1050 12:40:15.460786 [Byte1]: 56
1051 12:40:15.464872
1052 12:40:15.464981 Set Vref, RX VrefLevel [Byte0]: 57
1053 12:40:15.468235 [Byte1]: 57
1054 12:40:15.472083
1055 12:40:15.472187 Set Vref, RX VrefLevel [Byte0]: 58
1056 12:40:15.475518 [Byte1]: 58
1057 12:40:15.479590
1058 12:40:15.479667 Set Vref, RX VrefLevel [Byte0]: 59
1059 12:40:15.483502 [Byte1]: 59
1060 12:40:15.487407
1061 12:40:15.487488 Set Vref, RX VrefLevel [Byte0]: 60
1062 12:40:15.490615 [Byte1]: 60
1063 12:40:15.495292
1064 12:40:15.495376 Set Vref, RX VrefLevel [Byte0]: 61
1065 12:40:15.498482 [Byte1]: 61
1066 12:40:15.502572
1067 12:40:15.502653 Set Vref, RX VrefLevel [Byte0]: 62
1068 12:40:15.505899 [Byte1]: 62
1069 12:40:15.509925
1070 12:40:15.510014 Set Vref, RX VrefLevel [Byte0]: 63
1071 12:40:15.513304 [Byte1]: 63
1072 12:40:15.517949
1073 12:40:15.518031 Set Vref, RX VrefLevel [Byte0]: 64
1074 12:40:15.521246 [Byte1]: 64
1075 12:40:15.525169
1076 12:40:15.525246 Set Vref, RX VrefLevel [Byte0]: 65
1077 12:40:15.528301 [Byte1]: 65
1078 12:40:15.532638
1079 12:40:15.532719 Set Vref, RX VrefLevel [Byte0]: 66
1080 12:40:15.535873 [Byte1]: 66
1081 12:40:15.540513
1082 12:40:15.540602 Set Vref, RX VrefLevel [Byte0]: 67
1083 12:40:15.543952 [Byte1]: 67
1084 12:40:15.547942
1085 12:40:15.548023 Set Vref, RX VrefLevel [Byte0]: 68
1086 12:40:15.551301 [Byte1]: 68
1087 12:40:15.555433
1088 12:40:15.555535 Set Vref, RX VrefLevel [Byte0]: 69
1089 12:40:15.558753 [Byte1]: 69
1090 12:40:15.562781
1091 12:40:15.562856 Set Vref, RX VrefLevel [Byte0]: 70
1092 12:40:15.566574 [Byte1]: 70
1093 12:40:15.570430
1094 12:40:15.570510 Set Vref, RX VrefLevel [Byte0]: 71
1095 12:40:15.573942 [Byte1]: 71
1096 12:40:15.577824
1097 12:40:15.577911 Set Vref, RX VrefLevel [Byte0]: 72
1098 12:40:15.581440 [Byte1]: 72
1099 12:40:15.585310
1100 12:40:15.585424 Set Vref, RX VrefLevel [Byte0]: 73
1101 12:40:15.588955 [Byte1]: 73
1102 12:40:15.593404
1103 12:40:15.593526 Set Vref, RX VrefLevel [Byte0]: 74
1104 12:40:15.596642 [Byte1]: 74
1105 12:40:15.600618
1106 12:40:15.600756 Set Vref, RX VrefLevel [Byte0]: 75
1107 12:40:15.603883 [Byte1]: 75
1108 12:40:15.608680
1109 12:40:15.608804 Set Vref, RX VrefLevel [Byte0]: 76
1110 12:40:15.611349 [Byte1]: 76
1111 12:40:15.616151
1112 12:40:15.616265 Set Vref, RX VrefLevel [Byte0]: 77
1113 12:40:15.619502 [Byte1]: 77
1114 12:40:15.623352
1115 12:40:15.623492 Final RX Vref Byte 0 = 55 to rank0
1116 12:40:15.626796 Final RX Vref Byte 1 = 61 to rank0
1117 12:40:15.630219 Final RX Vref Byte 0 = 55 to rank1
1118 12:40:15.633550 Final RX Vref Byte 1 = 61 to rank1==
1119 12:40:15.636645 Dram Type= 6, Freq= 0, CH_0, rank 0
1120 12:40:15.643622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1121 12:40:15.643753 ==
1122 12:40:15.643864 DQS Delay:
1123 12:40:15.643954 DQS0 = 0, DQS1 = 0
1124 12:40:15.646820 DQM Delay:
1125 12:40:15.646956 DQM0 = 91, DQM1 = 86
1126 12:40:15.650151 DQ Delay:
1127 12:40:15.653532 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1128 12:40:15.653667 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1129 12:40:15.656877 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =80
1130 12:40:15.660260 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1131 12:40:15.663655
1132 12:40:15.663766
1133 12:40:15.670536 [DQSOSCAuto] RK0, (LSB)MR18= 0x5047, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 389 ps
1134 12:40:15.673949 CH0 RK0: MR19=606, MR18=5047
1135 12:40:15.680109 CH0_RK0: MR19=0x606, MR18=0x5047, DQSOSC=389, MR23=63, INC=97, DEC=65
1136 12:40:15.680231
1137 12:40:15.683439 ----->DramcWriteLeveling(PI) begin...
1138 12:40:15.683550 ==
1139 12:40:15.686920 Dram Type= 6, Freq= 0, CH_0, rank 1
1140 12:40:15.690524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1141 12:40:15.690632 ==
1142 12:40:15.693695 Write leveling (Byte 0): 33 => 33
1143 12:40:15.696798 Write leveling (Byte 1): 31 => 31
1144 12:40:15.700382 DramcWriteLeveling(PI) end<-----
1145 12:40:15.700491
1146 12:40:15.700585 ==
1147 12:40:15.703408 Dram Type= 6, Freq= 0, CH_0, rank 1
1148 12:40:15.706635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1149 12:40:15.706747 ==
1150 12:40:15.710077 [Gating] SW mode calibration
1151 12:40:15.758036 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1152 12:40:15.758435 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1153 12:40:15.758548 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1154 12:40:15.758643 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1155 12:40:15.758736 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1156 12:40:15.758843 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 12:40:15.759233 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 12:40:15.759920 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 12:40:15.760026 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 12:40:15.760607 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 12:40:15.802078 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 12:40:15.802470 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 12:40:15.802578 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:40:15.802676 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:40:15.802783 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:40:15.802876 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:40:15.803392 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 12:40:15.804131 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:40:15.804238 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 12:40:15.804537 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1171 12:40:15.845638 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1172 12:40:15.846034 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 12:40:15.846159 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 12:40:15.846256 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 12:40:15.846362 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:40:15.846457 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:40:15.846569 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:40:15.846665 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1179 12:40:15.846758 0 9 8 | B1->B0 | 3030 2d2d | 1 1 | (1 1) (1 1)
1180 12:40:15.846869 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 12:40:15.861925 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 12:40:15.862525 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 12:40:15.865479 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 12:40:15.865598 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 12:40:15.868806 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 12:40:15.871775 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 12:40:15.875051 0 10 8 | B1->B0 | 2525 2626 | 0 0 | (0 0) (0 0)
1188 12:40:15.881825 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 12:40:15.885794 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 12:40:15.890024 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 12:40:15.893456 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 12:40:15.897396 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 12:40:15.904268 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 12:40:15.907678 0 11 4 | B1->B0 | 2727 2626 | 0 1 | (0 0) (0 0)
1195 12:40:15.911144 0 11 8 | B1->B0 | 4141 3e3e | 0 0 | (0 0) (0 0)
1196 12:40:15.914498 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 12:40:15.921304 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 12:40:15.924658 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 12:40:15.928037 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 12:40:15.934876 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 12:40:15.938296 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 12:40:15.941692 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 12:40:15.947841 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1204 12:40:15.951162 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1205 12:40:15.954459 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 12:40:15.961457 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 12:40:15.964821 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 12:40:15.967891 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 12:40:15.974621 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 12:40:15.978212 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 12:40:15.981482 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 12:40:15.984599 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 12:40:15.991024 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 12:40:15.994621 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 12:40:15.998011 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 12:40:16.004487 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 12:40:16.007978 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 12:40:16.011375 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1219 12:40:16.018117 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1220 12:40:16.021268 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1221 12:40:16.025075 Total UI for P1: 0, mck2ui 16
1222 12:40:16.028456 best dqsien dly found for B0: ( 0, 14, 6)
1223 12:40:16.031849 Total UI for P1: 0, mck2ui 16
1224 12:40:16.035318 best dqsien dly found for B1: ( 0, 14, 6)
1225 12:40:16.037988 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1226 12:40:16.041362 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1227 12:40:16.041447
1228 12:40:16.044846 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1229 12:40:16.048176 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1230 12:40:16.051410 [Gating] SW calibration Done
1231 12:40:16.051493 ==
1232 12:40:16.054861 Dram Type= 6, Freq= 0, CH_0, rank 1
1233 12:40:16.058171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1234 12:40:16.058254 ==
1235 12:40:16.061581 RX Vref Scan: 0
1236 12:40:16.061663
1237 12:40:16.061729 RX Vref 0 -> 0, step: 1
1238 12:40:16.065231
1239 12:40:16.065314 RX Delay -130 -> 252, step: 16
1240 12:40:16.071877 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1241 12:40:16.075428 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1242 12:40:16.078071 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1243 12:40:16.081399 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1244 12:40:16.084981 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1245 12:40:16.091856 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1246 12:40:16.095168 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1247 12:40:16.098504 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
1248 12:40:16.101643 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1249 12:40:16.104943 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1250 12:40:16.108301 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1251 12:40:16.114848 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1252 12:40:16.118412 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1253 12:40:16.122113 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1254 12:40:16.125521 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1255 12:40:16.128899 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1256 12:40:16.131885 ==
1257 12:40:16.135276 Dram Type= 6, Freq= 0, CH_0, rank 1
1258 12:40:16.138666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1259 12:40:16.138749 ==
1260 12:40:16.138817 DQS Delay:
1261 12:40:16.141824 DQS0 = 0, DQS1 = 0
1262 12:40:16.141907 DQM Delay:
1263 12:40:16.145287 DQM0 = 93, DQM1 = 84
1264 12:40:16.145370 DQ Delay:
1265 12:40:16.148581 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1266 12:40:16.151899 DQ4 =93, DQ5 =85, DQ6 =101, DQ7 =109
1267 12:40:16.155121 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1268 12:40:16.158410 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =93
1269 12:40:16.158483
1270 12:40:16.158559
1271 12:40:16.158635 ==
1272 12:40:16.161845 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 12:40:16.165167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1274 12:40:16.165241 ==
1275 12:40:16.165303
1276 12:40:16.165360
1277 12:40:16.168439 TX Vref Scan disable
1278 12:40:16.171489 == TX Byte 0 ==
1279 12:40:16.175287 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1280 12:40:16.178595 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1281 12:40:16.181982 == TX Byte 1 ==
1282 12:40:16.185189 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1283 12:40:16.188541 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1284 12:40:16.188733 ==
1285 12:40:16.191916 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 12:40:16.198597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 12:40:16.198698 ==
1288 12:40:16.210511 TX Vref=22, minBit 8, minWin=27, winSum=448
1289 12:40:16.213206 TX Vref=24, minBit 1, minWin=28, winSum=453
1290 12:40:16.216644 TX Vref=26, minBit 1, minWin=28, winSum=456
1291 12:40:16.219990 TX Vref=28, minBit 5, minWin=28, winSum=457
1292 12:40:16.223190 TX Vref=30, minBit 7, minWin=28, winSum=459
1293 12:40:16.229911 TX Vref=32, minBit 11, minWin=27, winSum=452
1294 12:40:16.233144 [TxChooseVref] Worse bit 7, Min win 28, Win sum 459, Final Vref 30
1295 12:40:16.233223
1296 12:40:16.236483 Final TX Range 1 Vref 30
1297 12:40:16.236581
1298 12:40:16.236643 ==
1299 12:40:16.239915 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 12:40:16.243888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 12:40:16.243989 ==
1302 12:40:16.244079
1303 12:40:16.247023
1304 12:40:16.247109 TX Vref Scan disable
1305 12:40:16.250057 == TX Byte 0 ==
1306 12:40:16.253490 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1307 12:40:16.256997 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1308 12:40:16.260076 == TX Byte 1 ==
1309 12:40:16.263388 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1310 12:40:16.267448 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1311 12:40:16.267525
1312 12:40:16.270383 [DATLAT]
1313 12:40:16.270461 Freq=800, CH0 RK1
1314 12:40:16.270531
1315 12:40:16.273799 DATLAT Default: 0xa
1316 12:40:16.273900 0, 0xFFFF, sum = 0
1317 12:40:16.276990 1, 0xFFFF, sum = 0
1318 12:40:16.277068 2, 0xFFFF, sum = 0
1319 12:40:16.280052 3, 0xFFFF, sum = 0
1320 12:40:16.280158 4, 0xFFFF, sum = 0
1321 12:40:16.283905 5, 0xFFFF, sum = 0
1322 12:40:16.284011 6, 0xFFFF, sum = 0
1323 12:40:16.287357 7, 0xFFFF, sum = 0
1324 12:40:16.287437 8, 0xFFFF, sum = 0
1325 12:40:16.290569 9, 0x0, sum = 1
1326 12:40:16.290651 10, 0x0, sum = 2
1327 12:40:16.293743 11, 0x0, sum = 3
1328 12:40:16.293822 12, 0x0, sum = 4
1329 12:40:16.296995 best_step = 10
1330 12:40:16.297077
1331 12:40:16.297142 ==
1332 12:40:16.300358 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 12:40:16.303637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 12:40:16.303710 ==
1335 12:40:16.306977 RX Vref Scan: 0
1336 12:40:16.307051
1337 12:40:16.307112 RX Vref 0 -> 0, step: 1
1338 12:40:16.307174
1339 12:40:16.310197 RX Delay -79 -> 252, step: 8
1340 12:40:16.316879 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1341 12:40:16.320297 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1342 12:40:16.323633 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1343 12:40:16.327070 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1344 12:40:16.330402 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1345 12:40:16.337117 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1346 12:40:16.340489 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1347 12:40:16.343648 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1348 12:40:16.347005 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1349 12:40:16.350450 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1350 12:40:16.353842 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1351 12:40:16.360521 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1352 12:40:16.363867 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1353 12:40:16.367248 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1354 12:40:16.370511 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1355 12:40:16.376975 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1356 12:40:16.377058 ==
1357 12:40:16.380652 Dram Type= 6, Freq= 0, CH_0, rank 1
1358 12:40:16.383688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1359 12:40:16.383763 ==
1360 12:40:16.383825 DQS Delay:
1361 12:40:16.387246 DQS0 = 0, DQS1 = 0
1362 12:40:16.387321 DQM Delay:
1363 12:40:16.390595 DQM0 = 93, DQM1 = 84
1364 12:40:16.390676 DQ Delay:
1365 12:40:16.393570 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1366 12:40:16.396972 DQ4 =96, DQ5 =88, DQ6 =100, DQ7 =100
1367 12:40:16.400276 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1368 12:40:16.403707 DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =92
1369 12:40:16.403780
1370 12:40:16.403846
1371 12:40:16.410691 [DQSOSCAuto] RK1, (LSB)MR18= 0x4314, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
1372 12:40:16.413984 CH0 RK1: MR19=606, MR18=4314
1373 12:40:16.420416 CH0_RK1: MR19=0x606, MR18=0x4314, DQSOSC=393, MR23=63, INC=95, DEC=63
1374 12:40:16.423878 [RxdqsGatingPostProcess] freq 800
1375 12:40:16.430634 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1376 12:40:16.430711 Pre-setting of DQS Precalculation
1377 12:40:16.437365 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1378 12:40:16.437445 ==
1379 12:40:16.440772 Dram Type= 6, Freq= 0, CH_1, rank 0
1380 12:40:16.443686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1381 12:40:16.443765 ==
1382 12:40:16.450286 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1383 12:40:16.456962 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1384 12:40:16.465523 [CA 0] Center 36 (6~67) winsize 62
1385 12:40:16.468226 [CA 1] Center 36 (6~67) winsize 62
1386 12:40:16.471597 [CA 2] Center 34 (4~65) winsize 62
1387 12:40:16.474896 [CA 3] Center 34 (4~65) winsize 62
1388 12:40:16.478268 [CA 4] Center 35 (5~65) winsize 61
1389 12:40:16.481706 [CA 5] Center 34 (4~64) winsize 61
1390 12:40:16.481787
1391 12:40:16.485091 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1392 12:40:16.485196
1393 12:40:16.488469 [CATrainingPosCal] consider 1 rank data
1394 12:40:16.491948 u2DelayCellTimex100 = 270/100 ps
1395 12:40:16.495375 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1396 12:40:16.498721 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1397 12:40:16.505049 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1398 12:40:16.508839 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1399 12:40:16.512136 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1400 12:40:16.514831 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1401 12:40:16.514912
1402 12:40:16.518326 CA PerBit enable=1, Macro0, CA PI delay=34
1403 12:40:16.518406
1404 12:40:16.521587 [CBTSetCACLKResult] CA Dly = 34
1405 12:40:16.521667 CS Dly: 5 (0~36)
1406 12:40:16.521732 ==
1407 12:40:16.525252 Dram Type= 6, Freq= 0, CH_1, rank 1
1408 12:40:16.531532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1409 12:40:16.531614 ==
1410 12:40:16.534948 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1411 12:40:16.541690 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1412 12:40:16.551626 [CA 0] Center 36 (6~67) winsize 62
1413 12:40:16.554865 [CA 1] Center 36 (6~67) winsize 62
1414 12:40:16.558654 [CA 2] Center 35 (4~66) winsize 63
1415 12:40:16.562888 [CA 3] Center 34 (4~65) winsize 62
1416 12:40:16.566338 [CA 4] Center 35 (5~65) winsize 61
1417 12:40:16.570114 [CA 5] Center 34 (4~65) winsize 62
1418 12:40:16.570280
1419 12:40:16.574147 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1420 12:40:16.574321
1421 12:40:16.578074 [CATrainingPosCal] consider 2 rank data
1422 12:40:16.578237 u2DelayCellTimex100 = 270/100 ps
1423 12:40:16.581625 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1424 12:40:16.585070 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1425 12:40:16.588385 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1426 12:40:16.595368 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1427 12:40:16.598083 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1428 12:40:16.601446 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1429 12:40:16.601551
1430 12:40:16.604858 CA PerBit enable=1, Macro0, CA PI delay=34
1431 12:40:16.605016
1432 12:40:16.608134 [CBTSetCACLKResult] CA Dly = 34
1433 12:40:16.608225 CS Dly: 6 (0~38)
1434 12:40:16.608316
1435 12:40:16.612005 ----->DramcWriteLeveling(PI) begin...
1436 12:40:16.612147 ==
1437 12:40:16.615390 Dram Type= 6, Freq= 0, CH_1, rank 0
1438 12:40:16.621553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 12:40:16.621677 ==
1440 12:40:16.624923 Write leveling (Byte 0): 26 => 26
1441 12:40:16.625016 Write leveling (Byte 1): 26 => 26
1442 12:40:16.628189 DramcWriteLeveling(PI) end<-----
1443 12:40:16.628353
1444 12:40:16.631910 ==
1445 12:40:16.632050 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 12:40:16.638835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 12:40:16.638990 ==
1448 12:40:16.641636 [Gating] SW mode calibration
1449 12:40:16.648317 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1450 12:40:16.652094 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1451 12:40:16.658536 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1452 12:40:16.662038 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1453 12:40:16.665279 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 12:40:16.671849 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 12:40:16.675222 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 12:40:16.678338 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 12:40:16.681833 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 12:40:16.688487 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:40:16.692199 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 12:40:16.695619 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 12:40:16.702285 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:40:16.705637 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:40:16.709133 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:40:16.715654 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 12:40:16.719036 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:40:16.722476 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 12:40:16.729266 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 12:40:16.732044 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1469 12:40:16.735519 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 12:40:16.739254 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 12:40:16.745532 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 12:40:16.748665 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:40:16.752105 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:40:16.758971 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:40:16.762272 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 12:40:16.765645 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1477 12:40:16.772259 0 9 8 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
1478 12:40:16.775397 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 12:40:16.778807 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 12:40:16.785244 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 12:40:16.789071 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 12:40:16.791857 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 12:40:16.798880 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 12:40:16.802321 0 10 4 | B1->B0 | 3333 2c2c | 1 0 | (1 0) (0 0)
1485 12:40:16.805364 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 12:40:16.812214 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 12:40:16.815197 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 12:40:16.818989 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 12:40:16.825468 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 12:40:16.829002 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 12:40:16.832418 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 12:40:16.838588 0 11 4 | B1->B0 | 2525 3838 | 0 0 | (0 0) (1 1)
1493 12:40:16.842017 0 11 8 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1494 12:40:16.845339 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 12:40:16.849240 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 12:40:16.855547 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 12:40:16.858910 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 12:40:16.862190 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 12:40:16.869110 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 12:40:16.872545 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1501 12:40:16.875890 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 12:40:16.882238 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 12:40:16.885587 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 12:40:16.889085 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 12:40:16.895940 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 12:40:16.899248 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 12:40:16.901994 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 12:40:16.908563 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 12:40:16.912544 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 12:40:16.915607 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 12:40:16.922297 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 12:40:16.925414 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 12:40:16.928913 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 12:40:16.932420 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 12:40:16.939207 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 12:40:16.942574 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1517 12:40:16.945935 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1518 12:40:16.949137 Total UI for P1: 0, mck2ui 16
1519 12:40:16.952378 best dqsien dly found for B1: ( 0, 14, 4)
1520 12:40:16.959011 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1521 12:40:16.959094 Total UI for P1: 0, mck2ui 16
1522 12:40:16.965391 best dqsien dly found for B0: ( 0, 14, 6)
1523 12:40:16.969418 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1524 12:40:16.972203 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1525 12:40:16.972316
1526 12:40:16.975654 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1527 12:40:16.979076 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1528 12:40:16.982352 [Gating] SW calibration Done
1529 12:40:16.982435 ==
1530 12:40:16.985655 Dram Type= 6, Freq= 0, CH_1, rank 0
1531 12:40:16.988858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1532 12:40:16.988941 ==
1533 12:40:16.992258 RX Vref Scan: 0
1534 12:40:16.992346
1535 12:40:16.992411 RX Vref 0 -> 0, step: 1
1536 12:40:16.992472
1537 12:40:16.995683 RX Delay -130 -> 252, step: 16
1538 12:40:16.998948 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1539 12:40:17.005472 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1540 12:40:17.008850 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1541 12:40:17.012308 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1542 12:40:17.015681 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1543 12:40:17.019006 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1544 12:40:17.025677 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1545 12:40:17.029141 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1546 12:40:17.032578 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1547 12:40:17.035939 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1548 12:40:17.039351 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1549 12:40:17.042680 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1550 12:40:17.049125 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1551 12:40:17.052702 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1552 12:40:17.056409 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1553 12:40:17.059005 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1554 12:40:17.059105 ==
1555 12:40:17.062442 Dram Type= 6, Freq= 0, CH_1, rank 0
1556 12:40:17.069510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1557 12:40:17.069594 ==
1558 12:40:17.069665 DQS Delay:
1559 12:40:17.072821 DQS0 = 0, DQS1 = 0
1560 12:40:17.072899 DQM Delay:
1561 12:40:17.072965 DQM0 = 92, DQM1 = 87
1562 12:40:17.075827 DQ Delay:
1563 12:40:17.079631 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1564 12:40:17.082855 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1565 12:40:17.086268 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1566 12:40:17.089639 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1567 12:40:17.089723
1568 12:40:17.089788
1569 12:40:17.089849 ==
1570 12:40:17.092948 Dram Type= 6, Freq= 0, CH_1, rank 0
1571 12:40:17.096141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1572 12:40:17.096223 ==
1573 12:40:17.096298
1574 12:40:17.096361
1575 12:40:17.099212 TX Vref Scan disable
1576 12:40:17.099295 == TX Byte 0 ==
1577 12:40:17.105941 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1578 12:40:17.109901 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1579 12:40:17.109985 == TX Byte 1 ==
1580 12:40:17.116504 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1581 12:40:17.119299 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1582 12:40:17.119383 ==
1583 12:40:17.122682 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 12:40:17.125995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 12:40:17.126081 ==
1586 12:40:17.139948 TX Vref=22, minBit 1, minWin=26, winSum=435
1587 12:40:17.143312 TX Vref=24, minBit 1, minWin=26, winSum=440
1588 12:40:17.146800 TX Vref=26, minBit 3, minWin=26, winSum=446
1589 12:40:17.150192 TX Vref=28, minBit 0, minWin=27, winSum=446
1590 12:40:17.153579 TX Vref=30, minBit 1, minWin=27, winSum=446
1591 12:40:17.156954 TX Vref=32, minBit 7, minWin=26, winSum=444
1592 12:40:17.163475 [TxChooseVref] Worse bit 0, Min win 27, Win sum 446, Final Vref 28
1593 12:40:17.163585
1594 12:40:17.166789 Final TX Range 1 Vref 28
1595 12:40:17.166890
1596 12:40:17.166980 ==
1597 12:40:17.170049 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 12:40:17.173263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 12:40:17.173368 ==
1600 12:40:17.173460
1601 12:40:17.173566
1602 12:40:17.176431 TX Vref Scan disable
1603 12:40:17.179992 == TX Byte 0 ==
1604 12:40:17.183543 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1605 12:40:17.186414 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1606 12:40:17.189994 == TX Byte 1 ==
1607 12:40:17.193557 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1608 12:40:17.196393 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1609 12:40:17.196472
1610 12:40:17.200009 [DATLAT]
1611 12:40:17.200096 Freq=800, CH1 RK0
1612 12:40:17.200162
1613 12:40:17.203083 DATLAT Default: 0xa
1614 12:40:17.203165 0, 0xFFFF, sum = 0
1615 12:40:17.206883 1, 0xFFFF, sum = 0
1616 12:40:17.206967 2, 0xFFFF, sum = 0
1617 12:40:17.209967 3, 0xFFFF, sum = 0
1618 12:40:17.210050 4, 0xFFFF, sum = 0
1619 12:40:17.213227 5, 0xFFFF, sum = 0
1620 12:40:17.213311 6, 0xFFFF, sum = 0
1621 12:40:17.217143 7, 0xFFFF, sum = 0
1622 12:40:17.217227 8, 0xFFFF, sum = 0
1623 12:40:17.219940 9, 0x0, sum = 1
1624 12:40:17.220024 10, 0x0, sum = 2
1625 12:40:17.223322 11, 0x0, sum = 3
1626 12:40:17.223404 12, 0x0, sum = 4
1627 12:40:17.226722 best_step = 10
1628 12:40:17.226805
1629 12:40:17.226870 ==
1630 12:40:17.230111 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 12:40:17.233511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 12:40:17.233599 ==
1633 12:40:17.236798 RX Vref Scan: 1
1634 12:40:17.236904
1635 12:40:17.236970 Set Vref Range= 32 -> 127
1636 12:40:17.237031
1637 12:40:17.240506 RX Vref 32 -> 127, step: 1
1638 12:40:17.240600
1639 12:40:17.243944 RX Delay -79 -> 252, step: 8
1640 12:40:17.244026
1641 12:40:17.247075 Set Vref, RX VrefLevel [Byte0]: 32
1642 12:40:17.250441 [Byte1]: 32
1643 12:40:17.250522
1644 12:40:17.253790 Set Vref, RX VrefLevel [Byte0]: 33
1645 12:40:17.257204 [Byte1]: 33
1646 12:40:17.257278
1647 12:40:17.260628 Set Vref, RX VrefLevel [Byte0]: 34
1648 12:40:17.263878 [Byte1]: 34
1649 12:40:17.267804
1650 12:40:17.267905 Set Vref, RX VrefLevel [Byte0]: 35
1651 12:40:17.270534 [Byte1]: 35
1652 12:40:17.275297
1653 12:40:17.275380 Set Vref, RX VrefLevel [Byte0]: 36
1654 12:40:17.278562 [Byte1]: 36
1655 12:40:17.282640
1656 12:40:17.282721 Set Vref, RX VrefLevel [Byte0]: 37
1657 12:40:17.285833 [Byte1]: 37
1658 12:40:17.289909
1659 12:40:17.289990 Set Vref, RX VrefLevel [Byte0]: 38
1660 12:40:17.293197 [Byte1]: 38
1661 12:40:17.297615
1662 12:40:17.297714 Set Vref, RX VrefLevel [Byte0]: 39
1663 12:40:17.300891 [Byte1]: 39
1664 12:40:17.305230
1665 12:40:17.305312 Set Vref, RX VrefLevel [Byte0]: 40
1666 12:40:17.308403 [Byte1]: 40
1667 12:40:17.312506
1668 12:40:17.316135 Set Vref, RX VrefLevel [Byte0]: 41
1669 12:40:17.316242 [Byte1]: 41
1670 12:40:17.320066
1671 12:40:17.320148 Set Vref, RX VrefLevel [Byte0]: 42
1672 12:40:17.323343 [Byte1]: 42
1673 12:40:17.328052
1674 12:40:17.328136 Set Vref, RX VrefLevel [Byte0]: 43
1675 12:40:17.331059 [Byte1]: 43
1676 12:40:17.335915
1677 12:40:17.335994 Set Vref, RX VrefLevel [Byte0]: 44
1678 12:40:17.338544 [Byte1]: 44
1679 12:40:17.343244
1680 12:40:17.343327 Set Vref, RX VrefLevel [Byte0]: 45
1681 12:40:17.346562 [Byte1]: 45
1682 12:40:17.350629
1683 12:40:17.350723 Set Vref, RX VrefLevel [Byte0]: 46
1684 12:40:17.353719 [Byte1]: 46
1685 12:40:17.358115
1686 12:40:17.358207 Set Vref, RX VrefLevel [Byte0]: 47
1687 12:40:17.361580 [Byte1]: 47
1688 12:40:17.365638
1689 12:40:17.365747 Set Vref, RX VrefLevel [Byte0]: 48
1690 12:40:17.368947 [Byte1]: 48
1691 12:40:17.373020
1692 12:40:17.373107 Set Vref, RX VrefLevel [Byte0]: 49
1693 12:40:17.376482 [Byte1]: 49
1694 12:40:17.380478
1695 12:40:17.380561 Set Vref, RX VrefLevel [Byte0]: 50
1696 12:40:17.383899 [Byte1]: 50
1697 12:40:17.388082
1698 12:40:17.388189 Set Vref, RX VrefLevel [Byte0]: 51
1699 12:40:17.391287 [Byte1]: 51
1700 12:40:17.395975
1701 12:40:17.396083 Set Vref, RX VrefLevel [Byte0]: 52
1702 12:40:17.399204 [Byte1]: 52
1703 12:40:17.403092
1704 12:40:17.403195 Set Vref, RX VrefLevel [Byte0]: 53
1705 12:40:17.406526 [Byte1]: 53
1706 12:40:17.411098
1707 12:40:17.411217 Set Vref, RX VrefLevel [Byte0]: 54
1708 12:40:17.414453 [Byte1]: 54
1709 12:40:17.418515
1710 12:40:17.418640 Set Vref, RX VrefLevel [Byte0]: 55
1711 12:40:17.421812 [Byte1]: 55
1712 12:40:17.425677
1713 12:40:17.425805 Set Vref, RX VrefLevel [Byte0]: 56
1714 12:40:17.428855 [Byte1]: 56
1715 12:40:17.433346
1716 12:40:17.433449 Set Vref, RX VrefLevel [Byte0]: 57
1717 12:40:17.436948 [Byte1]: 57
1718 12:40:17.441104
1719 12:40:17.441213 Set Vref, RX VrefLevel [Byte0]: 58
1720 12:40:17.444059 [Byte1]: 58
1721 12:40:17.448875
1722 12:40:17.448957 Set Vref, RX VrefLevel [Byte0]: 59
1723 12:40:17.451845 [Byte1]: 59
1724 12:40:17.456145
1725 12:40:17.456250 Set Vref, RX VrefLevel [Byte0]: 60
1726 12:40:17.459474 [Byte1]: 60
1727 12:40:17.463851
1728 12:40:17.463956 Set Vref, RX VrefLevel [Byte0]: 61
1729 12:40:17.466935 [Byte1]: 61
1730 12:40:17.470919
1731 12:40:17.471031 Set Vref, RX VrefLevel [Byte0]: 62
1732 12:40:17.474221 [Byte1]: 62
1733 12:40:17.478942
1734 12:40:17.479053 Set Vref, RX VrefLevel [Byte0]: 63
1735 12:40:17.482358 [Byte1]: 63
1736 12:40:17.486464
1737 12:40:17.486569 Set Vref, RX VrefLevel [Byte0]: 64
1738 12:40:17.489802 [Byte1]: 64
1739 12:40:17.493885
1740 12:40:17.494000 Set Vref, RX VrefLevel [Byte0]: 65
1741 12:40:17.497096 [Byte1]: 65
1742 12:40:17.501464
1743 12:40:17.501568 Set Vref, RX VrefLevel [Byte0]: 66
1744 12:40:17.504686 [Byte1]: 66
1745 12:40:17.509204
1746 12:40:17.509278 Set Vref, RX VrefLevel [Byte0]: 67
1747 12:40:17.511880 [Byte1]: 67
1748 12:40:17.516481
1749 12:40:17.516556 Set Vref, RX VrefLevel [Byte0]: 68
1750 12:40:17.519919 [Byte1]: 68
1751 12:40:17.523939
1752 12:40:17.524039 Set Vref, RX VrefLevel [Byte0]: 69
1753 12:40:17.527394 [Byte1]: 69
1754 12:40:17.531335
1755 12:40:17.531435 Set Vref, RX VrefLevel [Byte0]: 70
1756 12:40:17.534621 [Byte1]: 70
1757 12:40:17.538785
1758 12:40:17.538893 Set Vref, RX VrefLevel [Byte0]: 71
1759 12:40:17.542593 [Byte1]: 71
1760 12:40:17.546448
1761 12:40:17.546556 Set Vref, RX VrefLevel [Byte0]: 72
1762 12:40:17.549793 [Byte1]: 72
1763 12:40:17.554235
1764 12:40:17.554345 Final RX Vref Byte 0 = 57 to rank0
1765 12:40:17.557461 Final RX Vref Byte 1 = 57 to rank0
1766 12:40:17.560716 Final RX Vref Byte 0 = 57 to rank1
1767 12:40:17.563844 Final RX Vref Byte 1 = 57 to rank1==
1768 12:40:17.567549 Dram Type= 6, Freq= 0, CH_1, rank 0
1769 12:40:17.574292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1770 12:40:17.574403 ==
1771 12:40:17.574499 DQS Delay:
1772 12:40:17.574587 DQS0 = 0, DQS1 = 0
1773 12:40:17.577256 DQM Delay:
1774 12:40:17.577330 DQM0 = 96, DQM1 = 89
1775 12:40:17.580879 DQ Delay:
1776 12:40:17.583895 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =92
1777 12:40:17.587738 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1778 12:40:17.591133 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1779 12:40:17.594562 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1780 12:40:17.594662
1781 12:40:17.594752
1782 12:40:17.600766 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d4a, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1783 12:40:17.604181 CH1 RK0: MR19=606, MR18=2D4A
1784 12:40:17.611268 CH1_RK0: MR19=0x606, MR18=0x2D4A, DQSOSC=391, MR23=63, INC=96, DEC=64
1785 12:40:17.611375
1786 12:40:17.614300 ----->DramcWriteLeveling(PI) begin...
1787 12:40:17.614405 ==
1788 12:40:17.617616 Dram Type= 6, Freq= 0, CH_1, rank 1
1789 12:40:17.621059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1790 12:40:17.621136 ==
1791 12:40:17.624255 Write leveling (Byte 0): 28 => 28
1792 12:40:17.627606 Write leveling (Byte 1): 28 => 28
1793 12:40:17.631055 DramcWriteLeveling(PI) end<-----
1794 12:40:17.631164
1795 12:40:17.631320 ==
1796 12:40:17.634451 Dram Type= 6, Freq= 0, CH_1, rank 1
1797 12:40:17.637670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1798 12:40:17.637768 ==
1799 12:40:17.640978 [Gating] SW mode calibration
1800 12:40:17.647675 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1801 12:40:17.654179 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1802 12:40:17.658109 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1803 12:40:17.661117 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1804 12:40:17.667899 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 12:40:17.671212 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 12:40:17.674675 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 12:40:17.681589 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 12:40:17.684529 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 12:40:17.688346 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 12:40:17.691397 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 12:40:17.698077 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 12:40:17.701352 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 12:40:17.704827 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 12:40:17.711778 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 12:40:17.715110 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 12:40:17.718529 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 12:40:17.724694 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 12:40:17.728421 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 12:40:17.731903 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1820 12:40:17.738079 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 12:40:17.741367 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 12:40:17.745302 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 12:40:17.751377 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 12:40:17.754636 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 12:40:17.758532 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 12:40:17.761853 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 12:40:17.768366 0 9 4 | B1->B0 | 2d2d 2323 | 1 0 | (0 0) (0 0)
1828 12:40:17.771675 0 9 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
1829 12:40:17.775118 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 12:40:17.781929 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 12:40:17.785109 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 12:40:17.788309 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 12:40:17.795041 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 12:40:17.798353 0 10 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1835 12:40:17.801364 0 10 4 | B1->B0 | 2828 2f2f | 0 0 | (0 0) (0 1)
1836 12:40:17.808185 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1837 12:40:17.811808 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 12:40:17.815114 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 12:40:17.821887 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 12:40:17.824645 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 12:40:17.828529 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 12:40:17.834972 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1843 12:40:17.838115 0 11 4 | B1->B0 | 3d3d 2c2c | 0 0 | (0 0) (0 0)
1844 12:40:17.841506 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 12:40:17.848235 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 12:40:17.851492 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 12:40:17.854887 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 12:40:17.858239 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 12:40:17.864796 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 12:40:17.868602 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1851 12:40:17.871888 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1852 12:40:17.878422 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 12:40:17.881815 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 12:40:17.885094 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 12:40:17.891721 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 12:40:17.895015 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 12:40:17.898249 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 12:40:17.905450 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 12:40:17.909043 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 12:40:17.912241 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 12:40:17.918225 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 12:40:17.922167 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 12:40:17.925325 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 12:40:17.928598 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 12:40:17.935174 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 12:40:17.938480 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1867 12:40:17.941792 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1868 12:40:17.945016 Total UI for P1: 0, mck2ui 16
1869 12:40:17.948882 best dqsien dly found for B0: ( 0, 14, 0)
1870 12:40:17.955474 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 12:40:17.955561 Total UI for P1: 0, mck2ui 16
1872 12:40:17.962313 best dqsien dly found for B1: ( 0, 14, 4)
1873 12:40:17.964973 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1874 12:40:17.968338 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1875 12:40:17.968438
1876 12:40:17.972383 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1877 12:40:17.975031 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1878 12:40:17.978682 [Gating] SW calibration Done
1879 12:40:17.978775 ==
1880 12:40:17.981753 Dram Type= 6, Freq= 0, CH_1, rank 1
1881 12:40:17.985674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1882 12:40:17.985821 ==
1883 12:40:17.988297 RX Vref Scan: 0
1884 12:40:17.988406
1885 12:40:17.988499 RX Vref 0 -> 0, step: 1
1886 12:40:17.988588
1887 12:40:17.991715 RX Delay -130 -> 252, step: 16
1888 12:40:17.995085 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1889 12:40:18.002011 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1890 12:40:18.004974 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1891 12:40:18.008461 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1892 12:40:18.011788 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1893 12:40:18.015213 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1894 12:40:18.022141 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1895 12:40:18.025471 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1896 12:40:18.028631 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1897 12:40:18.032138 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1898 12:40:18.035191 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1899 12:40:18.042207 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1900 12:40:18.045252 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1901 12:40:18.049135 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1902 12:40:18.052434 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1903 12:40:18.055624 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1904 12:40:18.055726 ==
1905 12:40:18.058817 Dram Type= 6, Freq= 0, CH_1, rank 1
1906 12:40:18.065606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1907 12:40:18.065693 ==
1908 12:40:18.065787 DQS Delay:
1909 12:40:18.068991 DQS0 = 0, DQS1 = 0
1910 12:40:18.069091 DQM Delay:
1911 12:40:18.072196 DQM0 = 92, DQM1 = 86
1912 12:40:18.072311 DQ Delay:
1913 12:40:18.075684 DQ0 =93, DQ1 =93, DQ2 =77, DQ3 =85
1914 12:40:18.079095 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1915 12:40:18.081862 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1916 12:40:18.085445 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1917 12:40:18.085553
1918 12:40:18.085653
1919 12:40:18.085742 ==
1920 12:40:18.088505 Dram Type= 6, Freq= 0, CH_1, rank 1
1921 12:40:18.092581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1922 12:40:18.092694 ==
1923 12:40:18.092798
1924 12:40:18.092893
1925 12:40:18.095689 TX Vref Scan disable
1926 12:40:18.099105 == TX Byte 0 ==
1927 12:40:18.101882 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1928 12:40:18.105321 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1929 12:40:18.109186 == TX Byte 1 ==
1930 12:40:18.111967 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1931 12:40:18.115246 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1932 12:40:18.115352 ==
1933 12:40:18.118596 Dram Type= 6, Freq= 0, CH_1, rank 1
1934 12:40:18.122110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1935 12:40:18.122212 ==
1936 12:40:18.136296 TX Vref=22, minBit 1, minWin=26, winSum=441
1937 12:40:18.139501 TX Vref=24, minBit 0, minWin=27, winSum=448
1938 12:40:18.142749 TX Vref=26, minBit 1, minWin=27, winSum=449
1939 12:40:18.146525 TX Vref=28, minBit 2, minWin=27, winSum=454
1940 12:40:18.149215 TX Vref=30, minBit 2, minWin=27, winSum=451
1941 12:40:18.156055 TX Vref=32, minBit 2, minWin=27, winSum=448
1942 12:40:18.159999 [TxChooseVref] Worse bit 2, Min win 27, Win sum 454, Final Vref 28
1943 12:40:18.160128
1944 12:40:18.162769 Final TX Range 1 Vref 28
1945 12:40:18.162896
1946 12:40:18.163015 ==
1947 12:40:18.166378 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 12:40:18.169417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 12:40:18.169545 ==
1950 12:40:18.172688
1951 12:40:18.172818
1952 12:40:18.172935 TX Vref Scan disable
1953 12:40:18.176489 == TX Byte 0 ==
1954 12:40:18.179461 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1955 12:40:18.186003 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1956 12:40:18.186124 == TX Byte 1 ==
1957 12:40:18.189413 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1958 12:40:18.192768 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1959 12:40:18.196203
1960 12:40:18.196316 [DATLAT]
1961 12:40:18.196413 Freq=800, CH1 RK1
1962 12:40:18.196506
1963 12:40:18.199447 DATLAT Default: 0xa
1964 12:40:18.199548 0, 0xFFFF, sum = 0
1965 12:40:18.203315 1, 0xFFFF, sum = 0
1966 12:40:18.203422 2, 0xFFFF, sum = 0
1967 12:40:18.206662 3, 0xFFFF, sum = 0
1968 12:40:18.206764 4, 0xFFFF, sum = 0
1969 12:40:18.209902 5, 0xFFFF, sum = 0
1970 12:40:18.210005 6, 0xFFFF, sum = 0
1971 12:40:18.213176 7, 0xFFFF, sum = 0
1972 12:40:18.216471 8, 0xFFFF, sum = 0
1973 12:40:18.216577 9, 0x0, sum = 1
1974 12:40:18.216673 10, 0x0, sum = 2
1975 12:40:18.219820 11, 0x0, sum = 3
1976 12:40:18.219918 12, 0x0, sum = 4
1977 12:40:18.223130 best_step = 10
1978 12:40:18.223215
1979 12:40:18.223280 ==
1980 12:40:18.226488 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 12:40:18.229973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 12:40:18.230078 ==
1983 12:40:18.233323 RX Vref Scan: 0
1984 12:40:18.233428
1985 12:40:18.233496 RX Vref 0 -> 0, step: 1
1986 12:40:18.233557
1987 12:40:18.236803 RX Delay -79 -> 252, step: 8
1988 12:40:18.243489 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1989 12:40:18.246300 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1990 12:40:18.250019 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1991 12:40:18.253414 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1992 12:40:18.256969 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1993 12:40:18.259662 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
1994 12:40:18.266457 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1995 12:40:18.269683 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1996 12:40:18.273033 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1997 12:40:18.276701 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1998 12:40:18.279885 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
1999 12:40:18.286882 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2000 12:40:18.290058 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2001 12:40:18.293206 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2002 12:40:18.296934 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2003 12:40:18.300108 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2004 12:40:18.300231 ==
2005 12:40:18.303517 Dram Type= 6, Freq= 0, CH_1, rank 1
2006 12:40:18.310003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2007 12:40:18.310141 ==
2008 12:40:18.310288 DQS Delay:
2009 12:40:18.313368 DQS0 = 0, DQS1 = 0
2010 12:40:18.313496 DQM Delay:
2011 12:40:18.313606 DQM0 = 97, DQM1 = 90
2012 12:40:18.316623 DQ Delay:
2013 12:40:18.319922 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2014 12:40:18.323267 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
2015 12:40:18.326533 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
2016 12:40:18.329972 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2017 12:40:18.330068
2018 12:40:18.330160
2019 12:40:18.336835 [DQSOSCAuto] RK1, (LSB)MR18= 0x450f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2020 12:40:18.340384 CH1 RK1: MR19=606, MR18=450F
2021 12:40:18.346516 CH1_RK1: MR19=0x606, MR18=0x450F, DQSOSC=392, MR23=63, INC=96, DEC=64
2022 12:40:18.349891 [RxdqsGatingPostProcess] freq 800
2023 12:40:18.353153 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2024 12:40:18.356842 Pre-setting of DQS Precalculation
2025 12:40:18.363387 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2026 12:40:18.370324 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2027 12:40:18.376994 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2028 12:40:18.377100
2029 12:40:18.377193
2030 12:40:18.380381 [Calibration Summary] 1600 Mbps
2031 12:40:18.380478 CH 0, Rank 0
2032 12:40:18.383657 SW Impedance : PASS
2033 12:40:18.386602 DUTY Scan : NO K
2034 12:40:18.386699 ZQ Calibration : PASS
2035 12:40:18.389986 Jitter Meter : NO K
2036 12:40:18.393359 CBT Training : PASS
2037 12:40:18.393482 Write leveling : PASS
2038 12:40:18.396490 RX DQS gating : PASS
2039 12:40:18.399974 RX DQ/DQS(RDDQC) : PASS
2040 12:40:18.400094 TX DQ/DQS : PASS
2041 12:40:18.403153 RX DATLAT : PASS
2042 12:40:18.403257 RX DQ/DQS(Engine): PASS
2043 12:40:18.407085 TX OE : NO K
2044 12:40:18.407212 All Pass.
2045 12:40:18.407331
2046 12:40:18.410164 CH 0, Rank 1
2047 12:40:18.410267 SW Impedance : PASS
2048 12:40:18.413322 DUTY Scan : NO K
2049 12:40:18.416570 ZQ Calibration : PASS
2050 12:40:18.416670 Jitter Meter : NO K
2051 12:40:18.419805 CBT Training : PASS
2052 12:40:18.423104 Write leveling : PASS
2053 12:40:18.423231 RX DQS gating : PASS
2054 12:40:18.426661 RX DQ/DQS(RDDQC) : PASS
2055 12:40:18.430250 TX DQ/DQS : PASS
2056 12:40:18.430356 RX DATLAT : PASS
2057 12:40:18.433469 RX DQ/DQS(Engine): PASS
2058 12:40:18.436883 TX OE : NO K
2059 12:40:18.436985 All Pass.
2060 12:40:18.437080
2061 12:40:18.437203 CH 1, Rank 0
2062 12:40:18.440226 SW Impedance : PASS
2063 12:40:18.443581 DUTY Scan : NO K
2064 12:40:18.443706 ZQ Calibration : PASS
2065 12:40:18.447146 Jitter Meter : NO K
2066 12:40:18.450388 CBT Training : PASS
2067 12:40:18.450537 Write leveling : PASS
2068 12:40:18.453166 RX DQS gating : PASS
2069 12:40:18.453327 RX DQ/DQS(RDDQC) : PASS
2070 12:40:18.456725 TX DQ/DQS : PASS
2071 12:40:18.459983 RX DATLAT : PASS
2072 12:40:18.460067 RX DQ/DQS(Engine): PASS
2073 12:40:18.463132 TX OE : NO K
2074 12:40:18.463215 All Pass.
2075 12:40:18.463280
2076 12:40:18.466939 CH 1, Rank 1
2077 12:40:18.467022 SW Impedance : PASS
2078 12:40:18.470208 DUTY Scan : NO K
2079 12:40:18.473676 ZQ Calibration : PASS
2080 12:40:18.473762 Jitter Meter : NO K
2081 12:40:18.477099 CBT Training : PASS
2082 12:40:18.479921 Write leveling : PASS
2083 12:40:18.480002 RX DQS gating : PASS
2084 12:40:18.483155 RX DQ/DQS(RDDQC) : PASS
2085 12:40:18.486658 TX DQ/DQS : PASS
2086 12:40:18.486770 RX DATLAT : PASS
2087 12:40:18.489917 RX DQ/DQS(Engine): PASS
2088 12:40:18.490044 TX OE : NO K
2089 12:40:18.493180 All Pass.
2090 12:40:18.493259
2091 12:40:18.493322 DramC Write-DBI off
2092 12:40:18.496760 PER_BANK_REFRESH: Hybrid Mode
2093 12:40:18.500006 TX_TRACKING: ON
2094 12:40:18.503468 [GetDramInforAfterCalByMRR] Vendor 6.
2095 12:40:18.506742 [GetDramInforAfterCalByMRR] Revision 606.
2096 12:40:18.510132 [GetDramInforAfterCalByMRR] Revision 2 0.
2097 12:40:18.510213 MR0 0x3b3b
2098 12:40:18.513716 MR8 0x5151
2099 12:40:18.516911 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2100 12:40:18.517020
2101 12:40:18.517087 MR0 0x3b3b
2102 12:40:18.517146 MR8 0x5151
2103 12:40:18.520155 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2104 12:40:18.520235
2105 12:40:18.530258 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2106 12:40:18.533825 [FAST_K] Save calibration result to emmc
2107 12:40:18.537133 [FAST_K] Save calibration result to emmc
2108 12:40:18.539994 dram_init: config_dvfs: 1
2109 12:40:18.543123 dramc_set_vcore_voltage set vcore to 662500
2110 12:40:18.547009 Read voltage for 1200, 2
2111 12:40:18.547104 Vio18 = 0
2112 12:40:18.547168 Vcore = 662500
2113 12:40:18.550227 Vdram = 0
2114 12:40:18.550307 Vddq = 0
2115 12:40:18.550371 Vmddr = 0
2116 12:40:18.557123 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2117 12:40:18.560560 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2118 12:40:18.563353 MEM_TYPE=3, freq_sel=15
2119 12:40:18.567037 sv_algorithm_assistance_LP4_1600
2120 12:40:18.570211 ============ PULL DRAM RESETB DOWN ============
2121 12:40:18.573468 ========== PULL DRAM RESETB DOWN end =========
2122 12:40:18.580011 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2123 12:40:18.583512 ===================================
2124 12:40:18.583593 LPDDR4 DRAM CONFIGURATION
2125 12:40:18.586918 ===================================
2126 12:40:18.590405 EX_ROW_EN[0] = 0x0
2127 12:40:18.593888 EX_ROW_EN[1] = 0x0
2128 12:40:18.593968 LP4Y_EN = 0x0
2129 12:40:18.597172 WORK_FSP = 0x0
2130 12:40:18.597252 WL = 0x4
2131 12:40:18.600636 RL = 0x4
2132 12:40:18.600715 BL = 0x2
2133 12:40:18.603899 RPST = 0x0
2134 12:40:18.603979 RD_PRE = 0x0
2135 12:40:18.606973 WR_PRE = 0x1
2136 12:40:18.607053 WR_PST = 0x0
2137 12:40:18.610716 DBI_WR = 0x0
2138 12:40:18.610798 DBI_RD = 0x0
2139 12:40:18.614009 OTF = 0x1
2140 12:40:18.617361 ===================================
2141 12:40:18.620687 ===================================
2142 12:40:18.620830 ANA top config
2143 12:40:18.624048 ===================================
2144 12:40:18.627540 DLL_ASYNC_EN = 0
2145 12:40:18.630557 ALL_SLAVE_EN = 0
2146 12:40:18.630692 NEW_RANK_MODE = 1
2147 12:40:18.633616 DLL_IDLE_MODE = 1
2148 12:40:18.637437 LP45_APHY_COMB_EN = 1
2149 12:40:18.640641 TX_ODT_DIS = 1
2150 12:40:18.643914 NEW_8X_MODE = 1
2151 12:40:18.647171 ===================================
2152 12:40:18.647255 ===================================
2153 12:40:18.651022 data_rate = 2400
2154 12:40:18.654222 CKR = 1
2155 12:40:18.657550 DQ_P2S_RATIO = 8
2156 12:40:18.660974 ===================================
2157 12:40:18.664222 CA_P2S_RATIO = 8
2158 12:40:18.667609 DQ_CA_OPEN = 0
2159 12:40:18.667685 DQ_SEMI_OPEN = 0
2160 12:40:18.670892 CA_SEMI_OPEN = 0
2161 12:40:18.674249 CA_FULL_RATE = 0
2162 12:40:18.677535 DQ_CKDIV4_EN = 0
2163 12:40:18.680750 CA_CKDIV4_EN = 0
2164 12:40:18.684166 CA_PREDIV_EN = 0
2165 12:40:18.684262 PH8_DLY = 17
2166 12:40:18.687578 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2167 12:40:18.691083 DQ_AAMCK_DIV = 4
2168 12:40:18.694546 CA_AAMCK_DIV = 4
2169 12:40:18.697294 CA_ADMCK_DIV = 4
2170 12:40:18.700952 DQ_TRACK_CA_EN = 0
2171 12:40:18.704047 CA_PICK = 1200
2172 12:40:18.704127 CA_MCKIO = 1200
2173 12:40:18.707433 MCKIO_SEMI = 0
2174 12:40:18.710757 PLL_FREQ = 2366
2175 12:40:18.714059 DQ_UI_PI_RATIO = 32
2176 12:40:18.717272 CA_UI_PI_RATIO = 0
2177 12:40:18.720626 ===================================
2178 12:40:18.723883 ===================================
2179 12:40:18.727809 memory_type:LPDDR4
2180 12:40:18.727908 GP_NUM : 10
2181 12:40:18.731153 SRAM_EN : 1
2182 12:40:18.731277 MD32_EN : 0
2183 12:40:18.734596 ===================================
2184 12:40:18.737410 [ANA_INIT] >>>>>>>>>>>>>>
2185 12:40:18.740753 <<<<<< [CONFIGURE PHASE]: ANA_TX
2186 12:40:18.744532 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2187 12:40:18.747851 ===================================
2188 12:40:18.751086 data_rate = 2400,PCW = 0X5b00
2189 12:40:18.754095 ===================================
2190 12:40:18.757350 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2191 12:40:18.760622 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2192 12:40:18.767844 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2193 12:40:18.770818 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2194 12:40:18.773814 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2195 12:40:18.781024 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2196 12:40:18.781134 [ANA_INIT] flow start
2197 12:40:18.784427 [ANA_INIT] PLL >>>>>>>>
2198 12:40:18.784530 [ANA_INIT] PLL <<<<<<<<
2199 12:40:18.787696 [ANA_INIT] MIDPI >>>>>>>>
2200 12:40:18.790945 [ANA_INIT] MIDPI <<<<<<<<
2201 12:40:18.794129 [ANA_INIT] DLL >>>>>>>>
2202 12:40:18.794207 [ANA_INIT] DLL <<<<<<<<
2203 12:40:18.797538 [ANA_INIT] flow end
2204 12:40:18.800951 ============ LP4 DIFF to SE enter ============
2205 12:40:18.804280 ============ LP4 DIFF to SE exit ============
2206 12:40:18.807618 [ANA_INIT] <<<<<<<<<<<<<
2207 12:40:18.810429 [Flow] Enable top DCM control >>>>>
2208 12:40:18.813819 [Flow] Enable top DCM control <<<<<
2209 12:40:18.817146 Enable DLL master slave shuffle
2210 12:40:18.824411 ==============================================================
2211 12:40:18.824486 Gating Mode config
2212 12:40:18.830879 ==============================================================
2213 12:40:18.830954 Config description:
2214 12:40:18.841066 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2215 12:40:18.847826 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2216 12:40:18.854267 SELPH_MODE 0: By rank 1: By Phase
2217 12:40:18.858121 ==============================================================
2218 12:40:18.861395 GAT_TRACK_EN = 1
2219 12:40:18.864616 RX_GATING_MODE = 2
2220 12:40:18.867841 RX_GATING_TRACK_MODE = 2
2221 12:40:18.871102 SELPH_MODE = 1
2222 12:40:18.874634 PICG_EARLY_EN = 1
2223 12:40:18.877995 VALID_LAT_VALUE = 1
2224 12:40:18.881008 ==============================================================
2225 12:40:18.884456 Enter into Gating configuration >>>>
2226 12:40:18.887962 Exit from Gating configuration <<<<
2227 12:40:18.890902 Enter into DVFS_PRE_config >>>>>
2228 12:40:18.904624 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2229 12:40:18.904711 Exit from DVFS_PRE_config <<<<<
2230 12:40:18.907413 Enter into PICG configuration >>>>
2231 12:40:18.910799 Exit from PICG configuration <<<<
2232 12:40:18.914229 [RX_INPUT] configuration >>>>>
2233 12:40:18.917581 [RX_INPUT] configuration <<<<<
2234 12:40:18.924365 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2235 12:40:18.927832 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2236 12:40:18.934380 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2237 12:40:18.941191 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2238 12:40:18.947368 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2239 12:40:18.954198 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2240 12:40:18.957695 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2241 12:40:18.960978 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2242 12:40:18.964248 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2243 12:40:18.970967 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2244 12:40:18.974317 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2245 12:40:18.977442 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2246 12:40:18.980633 ===================================
2247 12:40:18.984164 LPDDR4 DRAM CONFIGURATION
2248 12:40:18.987625 ===================================
2249 12:40:18.987706 EX_ROW_EN[0] = 0x0
2250 12:40:18.990998 EX_ROW_EN[1] = 0x0
2251 12:40:18.994384 LP4Y_EN = 0x0
2252 12:40:18.994464 WORK_FSP = 0x0
2253 12:40:18.997528 WL = 0x4
2254 12:40:18.997647 RL = 0x4
2255 12:40:19.001306 BL = 0x2
2256 12:40:19.001386 RPST = 0x0
2257 12:40:19.004363 RD_PRE = 0x0
2258 12:40:19.004444 WR_PRE = 0x1
2259 12:40:19.007197 WR_PST = 0x0
2260 12:40:19.007277 DBI_WR = 0x0
2261 12:40:19.011011 DBI_RD = 0x0
2262 12:40:19.011091 OTF = 0x1
2263 12:40:19.014449 ===================================
2264 12:40:19.017654 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2265 12:40:19.023945 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2266 12:40:19.027286 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2267 12:40:19.030821 ===================================
2268 12:40:19.033978 LPDDR4 DRAM CONFIGURATION
2269 12:40:19.037855 ===================================
2270 12:40:19.037931 EX_ROW_EN[0] = 0x10
2271 12:40:19.040545 EX_ROW_EN[1] = 0x0
2272 12:40:19.040616 LP4Y_EN = 0x0
2273 12:40:19.043904 WORK_FSP = 0x0
2274 12:40:19.043972 WL = 0x4
2275 12:40:19.047144 RL = 0x4
2276 12:40:19.047215 BL = 0x2
2277 12:40:19.050582 RPST = 0x0
2278 12:40:19.054095 RD_PRE = 0x0
2279 12:40:19.054163 WR_PRE = 0x1
2280 12:40:19.057496 WR_PST = 0x0
2281 12:40:19.057566 DBI_WR = 0x0
2282 12:40:19.060887 DBI_RD = 0x0
2283 12:40:19.060976 OTF = 0x1
2284 12:40:19.064190 ===================================
2285 12:40:19.070892 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2286 12:40:19.070963 ==
2287 12:40:19.074232 Dram Type= 6, Freq= 0, CH_0, rank 0
2288 12:40:19.077533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2289 12:40:19.077610 ==
2290 12:40:19.080873 [Duty_Offset_Calibration]
2291 12:40:19.080944 B0:2 B1:1 CA:1
2292 12:40:19.081008
2293 12:40:19.084147 [DutyScan_Calibration_Flow] k_type=0
2294 12:40:19.094864
2295 12:40:19.094940 ==CLK 0==
2296 12:40:19.098310 Final CLK duty delay cell = 0
2297 12:40:19.101627 [0] MAX Duty = 5218%(X100), DQS PI = 24
2298 12:40:19.104993 [0] MIN Duty = 4844%(X100), DQS PI = 48
2299 12:40:19.105062 [0] AVG Duty = 5031%(X100)
2300 12:40:19.108131
2301 12:40:19.111524 CH0 CLK Duty spec in!! Max-Min= 374%
2302 12:40:19.115256 [DutyScan_Calibration_Flow] ====Done====
2303 12:40:19.115325
2304 12:40:19.118441 [DutyScan_Calibration_Flow] k_type=1
2305 12:40:19.132765
2306 12:40:19.132855 ==DQS 0 ==
2307 12:40:19.136682 Final DQS duty delay cell = -4
2308 12:40:19.139378 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2309 12:40:19.143286 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2310 12:40:19.146042 [-4] AVG Duty = 4953%(X100)
2311 12:40:19.146109
2312 12:40:19.146180 ==DQS 1 ==
2313 12:40:19.150060 Final DQS duty delay cell = -4
2314 12:40:19.153353 [-4] MAX Duty = 5000%(X100), DQS PI = 62
2315 12:40:19.156161 [-4] MIN Duty = 4844%(X100), DQS PI = 32
2316 12:40:19.159598 [-4] AVG Duty = 4922%(X100)
2317 12:40:19.159667
2318 12:40:19.163077 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2319 12:40:19.163144
2320 12:40:19.166417 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2321 12:40:19.170007 [DutyScan_Calibration_Flow] ====Done====
2322 12:40:19.170074
2323 12:40:19.173238 [DutyScan_Calibration_Flow] k_type=3
2324 12:40:19.190624
2325 12:40:19.190703 ==DQM 0 ==
2326 12:40:19.193816 Final DQM duty delay cell = 0
2327 12:40:19.197592 [0] MAX Duty = 5156%(X100), DQS PI = 28
2328 12:40:19.200543 [0] MIN Duty = 4907%(X100), DQS PI = 58
2329 12:40:19.200617 [0] AVG Duty = 5031%(X100)
2330 12:40:19.203599
2331 12:40:19.203674 ==DQM 1 ==
2332 12:40:19.206911 Final DQM duty delay cell = 0
2333 12:40:19.210464 [0] MAX Duty = 5124%(X100), DQS PI = 6
2334 12:40:19.213548 [0] MIN Duty = 5031%(X100), DQS PI = 14
2335 12:40:19.213628 [0] AVG Duty = 5077%(X100)
2336 12:40:19.216897
2337 12:40:19.220387 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2338 12:40:19.220466
2339 12:40:19.223585 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2340 12:40:19.226958 [DutyScan_Calibration_Flow] ====Done====
2341 12:40:19.227039
2342 12:40:19.230326 [DutyScan_Calibration_Flow] k_type=2
2343 12:40:19.246551
2344 12:40:19.246662 ==DQ 0 ==
2345 12:40:19.250059 Final DQ duty delay cell = 0
2346 12:40:19.253044 [0] MAX Duty = 5062%(X100), DQS PI = 32
2347 12:40:19.256692 [0] MIN Duty = 4906%(X100), DQS PI = 0
2348 12:40:19.256767 [0] AVG Duty = 4984%(X100)
2349 12:40:19.256828
2350 12:40:19.259878 ==DQ 1 ==
2351 12:40:19.263240 Final DQ duty delay cell = 0
2352 12:40:19.266659 [0] MAX Duty = 5093%(X100), DQS PI = 24
2353 12:40:19.270157 [0] MIN Duty = 4969%(X100), DQS PI = 2
2354 12:40:19.270226 [0] AVG Duty = 5031%(X100)
2355 12:40:19.270290
2356 12:40:19.273504 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2357 12:40:19.273571
2358 12:40:19.276905 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2359 12:40:19.283015 [DutyScan_Calibration_Flow] ====Done====
2360 12:40:19.283091 ==
2361 12:40:19.287025 Dram Type= 6, Freq= 0, CH_1, rank 0
2362 12:40:19.289777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2363 12:40:19.289850 ==
2364 12:40:19.293194 [Duty_Offset_Calibration]
2365 12:40:19.293263 B0:1 B1:0 CA:0
2366 12:40:19.293321
2367 12:40:19.296590 [DutyScan_Calibration_Flow] k_type=0
2368 12:40:19.305481
2369 12:40:19.305601 ==CLK 0==
2370 12:40:19.308680 Final CLK duty delay cell = -4
2371 12:40:19.312543 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2372 12:40:19.316090 [-4] MIN Duty = 4907%(X100), DQS PI = 50
2373 12:40:19.319234 [-4] AVG Duty = 4969%(X100)
2374 12:40:19.319336
2375 12:40:19.322515 CH1 CLK Duty spec in!! Max-Min= 124%
2376 12:40:19.325677 [DutyScan_Calibration_Flow] ====Done====
2377 12:40:19.325772
2378 12:40:19.328982 [DutyScan_Calibration_Flow] k_type=1
2379 12:40:19.345296
2380 12:40:19.345378 ==DQS 0 ==
2381 12:40:19.348769 Final DQS duty delay cell = 0
2382 12:40:19.352151 [0] MAX Duty = 5094%(X100), DQS PI = 26
2383 12:40:19.355357 [0] MIN Duty = 4875%(X100), DQS PI = 0
2384 12:40:19.355442 [0] AVG Duty = 4984%(X100)
2385 12:40:19.355524
2386 12:40:19.358599 ==DQS 1 ==
2387 12:40:19.362473 Final DQS duty delay cell = 0
2388 12:40:19.365637 [0] MAX Duty = 5187%(X100), DQS PI = 20
2389 12:40:19.368695 [0] MIN Duty = 4938%(X100), DQS PI = 12
2390 12:40:19.368777 [0] AVG Duty = 5062%(X100)
2391 12:40:19.368861
2392 12:40:19.375610 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2393 12:40:19.375709
2394 12:40:19.378952 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2395 12:40:19.382420 [DutyScan_Calibration_Flow] ====Done====
2396 12:40:19.382503
2397 12:40:19.385889 [DutyScan_Calibration_Flow] k_type=3
2398 12:40:19.402005
2399 12:40:19.402103 ==DQM 0 ==
2400 12:40:19.405526 Final DQM duty delay cell = 0
2401 12:40:19.408393 [0] MAX Duty = 5156%(X100), DQS PI = 6
2402 12:40:19.411792 [0] MIN Duty = 5031%(X100), DQS PI = 0
2403 12:40:19.411876 [0] AVG Duty = 5093%(X100)
2404 12:40:19.415428
2405 12:40:19.415534 ==DQM 1 ==
2406 12:40:19.418747 Final DQM duty delay cell = 0
2407 12:40:19.422012 [0] MAX Duty = 5031%(X100), DQS PI = 16
2408 12:40:19.425056 [0] MIN Duty = 4907%(X100), DQS PI = 36
2409 12:40:19.425172 [0] AVG Duty = 4969%(X100)
2410 12:40:19.425270
2411 12:40:19.432368 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2412 12:40:19.432486
2413 12:40:19.435619 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2414 12:40:19.438860 [DutyScan_Calibration_Flow] ====Done====
2415 12:40:19.438941
2416 12:40:19.441785 [DutyScan_Calibration_Flow] k_type=2
2417 12:40:19.457637
2418 12:40:19.457724 ==DQ 0 ==
2419 12:40:19.461088 Final DQ duty delay cell = -4
2420 12:40:19.464530 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2421 12:40:19.467674 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2422 12:40:19.471163 [-4] AVG Duty = 4984%(X100)
2423 12:40:19.471244
2424 12:40:19.471308 ==DQ 1 ==
2425 12:40:19.474352 Final DQ duty delay cell = 0
2426 12:40:19.477518 [0] MAX Duty = 5125%(X100), DQS PI = 20
2427 12:40:19.480815 [0] MIN Duty = 4969%(X100), DQS PI = 12
2428 12:40:19.480896 [0] AVG Duty = 5047%(X100)
2429 12:40:19.484599
2430 12:40:19.487728 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2431 12:40:19.487808
2432 12:40:19.491057 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2433 12:40:19.494305 [DutyScan_Calibration_Flow] ====Done====
2434 12:40:19.497734 nWR fixed to 30
2435 12:40:19.497814 [ModeRegInit_LP4] CH0 RK0
2436 12:40:19.500921 [ModeRegInit_LP4] CH0 RK1
2437 12:40:19.504469 [ModeRegInit_LP4] CH1 RK0
2438 12:40:19.507908 [ModeRegInit_LP4] CH1 RK1
2439 12:40:19.507988 match AC timing 7
2440 12:40:19.511408 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2441 12:40:19.517581 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2442 12:40:19.521076 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2443 12:40:19.524528 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2444 12:40:19.531168 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2445 12:40:19.531248 ==
2446 12:40:19.534281 Dram Type= 6, Freq= 0, CH_0, rank 0
2447 12:40:19.538155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2448 12:40:19.538243 ==
2449 12:40:19.551411 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2450 12:40:19.551533 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2451 12:40:19.558208 [CA 0] Center 39 (8~70) winsize 63
2452 12:40:19.561571 [CA 1] Center 39 (8~70) winsize 63
2453 12:40:19.564954 [CA 2] Center 35 (5~66) winsize 62
2454 12:40:19.568212 [CA 3] Center 34 (4~65) winsize 62
2455 12:40:19.571020 [CA 4] Center 33 (3~64) winsize 62
2456 12:40:19.574415 [CA 5] Center 32 (3~62) winsize 60
2457 12:40:19.574513
2458 12:40:19.577919 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2459 12:40:19.578026
2460 12:40:19.581277 [CATrainingPosCal] consider 1 rank data
2461 12:40:19.584646 u2DelayCellTimex100 = 270/100 ps
2462 12:40:19.588054 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2463 12:40:19.591339 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2464 12:40:19.597664 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2465 12:40:19.601512 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2466 12:40:19.604940 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2467 12:40:19.608159 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2468 12:40:19.608265
2469 12:40:19.611596 CA PerBit enable=1, Macro0, CA PI delay=32
2470 12:40:19.611698
2471 12:40:19.614321 [CBTSetCACLKResult] CA Dly = 32
2472 12:40:19.614394 CS Dly: 6 (0~37)
2473 12:40:19.614453 ==
2474 12:40:19.617729 Dram Type= 6, Freq= 0, CH_0, rank 1
2475 12:40:19.624624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2476 12:40:19.624700 ==
2477 12:40:19.628178 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2478 12:40:19.634319 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2479 12:40:19.643564 [CA 0] Center 38 (8~69) winsize 62
2480 12:40:19.646865 [CA 1] Center 38 (8~69) winsize 62
2481 12:40:19.650455 [CA 2] Center 35 (4~66) winsize 63
2482 12:40:19.653753 [CA 3] Center 34 (4~65) winsize 62
2483 12:40:19.657367 [CA 4] Center 33 (3~63) winsize 61
2484 12:40:19.660604 [CA 5] Center 32 (3~62) winsize 60
2485 12:40:19.660695
2486 12:40:19.663748 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2487 12:40:19.663832
2488 12:40:19.666919 [CATrainingPosCal] consider 2 rank data
2489 12:40:19.670596 u2DelayCellTimex100 = 270/100 ps
2490 12:40:19.673862 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2491 12:40:19.677209 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2492 12:40:19.680440 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2493 12:40:19.687159 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2494 12:40:19.690552 CA4 delay=33 (3~63),Diff = 1 PI (4 cell)
2495 12:40:19.694004 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2496 12:40:19.694084
2497 12:40:19.697590 CA PerBit enable=1, Macro0, CA PI delay=32
2498 12:40:19.697671
2499 12:40:19.700783 [CBTSetCACLKResult] CA Dly = 32
2500 12:40:19.700868 CS Dly: 6 (0~38)
2501 12:40:19.700967
2502 12:40:19.703907 ----->DramcWriteLeveling(PI) begin...
2503 12:40:19.703989 ==
2504 12:40:19.707121 Dram Type= 6, Freq= 0, CH_0, rank 0
2505 12:40:19.713574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2506 12:40:19.713657 ==
2507 12:40:19.717337 Write leveling (Byte 0): 33 => 33
2508 12:40:19.720567 Write leveling (Byte 1): 26 => 26
2509 12:40:19.720648 DramcWriteLeveling(PI) end<-----
2510 12:40:19.723844
2511 12:40:19.723923 ==
2512 12:40:19.727288 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 12:40:19.730820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 12:40:19.730900 ==
2515 12:40:19.734140 [Gating] SW mode calibration
2516 12:40:19.740264 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2517 12:40:19.743704 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2518 12:40:19.750951 0 15 0 | B1->B0 | 2525 3232 | 0 1 | (0 0) (1 1)
2519 12:40:19.754214 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2520 12:40:19.757456 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 12:40:19.764188 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 12:40:19.767259 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 12:40:19.770725 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 12:40:19.777377 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
2525 12:40:19.781306 0 15 28 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
2526 12:40:19.784173 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
2527 12:40:19.790576 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 12:40:19.794321 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 12:40:19.797639 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 12:40:19.801135 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 12:40:19.807682 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 12:40:19.810928 1 0 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2533 12:40:19.814178 1 0 28 | B1->B0 | 2929 4545 | 0 0 | (0 0) (0 0)
2534 12:40:19.821053 1 1 0 | B1->B0 | 3737 4545 | 1 0 | (0 0) (0 0)
2535 12:40:19.823762 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 12:40:19.827545 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 12:40:19.833935 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 12:40:19.837437 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 12:40:19.840683 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 12:40:19.847796 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2541 12:40:19.851136 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2542 12:40:19.853824 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2543 12:40:19.860633 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 12:40:19.863964 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 12:40:19.867399 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 12:40:19.874116 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 12:40:19.877298 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 12:40:19.880577 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 12:40:19.887313 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 12:40:19.890799 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 12:40:19.894161 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 12:40:19.897436 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 12:40:19.903847 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 12:40:19.907538 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 12:40:19.910878 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 12:40:19.917628 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 12:40:19.921027 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2558 12:40:19.924322 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2559 12:40:19.927662 Total UI for P1: 0, mck2ui 16
2560 12:40:19.931104 best dqsien dly found for B0: ( 1, 3, 28)
2561 12:40:19.937751 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 12:40:19.937828 Total UI for P1: 0, mck2ui 16
2563 12:40:19.944156 best dqsien dly found for B1: ( 1, 4, 0)
2564 12:40:19.947266 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2565 12:40:19.950876 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2566 12:40:19.950974
2567 12:40:19.954295 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2568 12:40:19.957647 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2569 12:40:19.960979 [Gating] SW calibration Done
2570 12:40:19.961058 ==
2571 12:40:19.964321 Dram Type= 6, Freq= 0, CH_0, rank 0
2572 12:40:19.967635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2573 12:40:19.967715 ==
2574 12:40:19.967778 RX Vref Scan: 0
2575 12:40:19.970929
2576 12:40:19.971027 RX Vref 0 -> 0, step: 1
2577 12:40:19.971117
2578 12:40:19.974354 RX Delay -40 -> 252, step: 8
2579 12:40:19.977872 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2580 12:40:19.981167 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2581 12:40:19.987494 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2582 12:40:19.991428 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2583 12:40:19.994643 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2584 12:40:19.997761 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2585 12:40:20.001106 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2586 12:40:20.007882 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2587 12:40:20.011009 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2588 12:40:20.014947 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2589 12:40:20.018108 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2590 12:40:20.021538 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2591 12:40:20.028065 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2592 12:40:20.031462 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2593 12:40:20.034854 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2594 12:40:20.038158 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2595 12:40:20.038228 ==
2596 12:40:20.041583 Dram Type= 6, Freq= 0, CH_0, rank 0
2597 12:40:20.044943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2598 12:40:20.048418 ==
2599 12:40:20.048512 DQS Delay:
2600 12:40:20.048600 DQS0 = 0, DQS1 = 0
2601 12:40:20.051793 DQM Delay:
2602 12:40:20.051886 DQM0 = 121, DQM1 = 113
2603 12:40:20.055043 DQ Delay:
2604 12:40:20.058151 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2605 12:40:20.061714 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2606 12:40:20.065138 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2607 12:40:20.067844 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2608 12:40:20.067915
2609 12:40:20.067974
2610 12:40:20.068037 ==
2611 12:40:20.071273 Dram Type= 6, Freq= 0, CH_0, rank 0
2612 12:40:20.074590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2613 12:40:20.074663 ==
2614 12:40:20.074721
2615 12:40:20.074777
2616 12:40:20.077982 TX Vref Scan disable
2617 12:40:20.081394 == TX Byte 0 ==
2618 12:40:20.084814 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2619 12:40:20.088023 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2620 12:40:20.091343 == TX Byte 1 ==
2621 12:40:20.094805 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2622 12:40:20.098165 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2623 12:40:20.098262 ==
2624 12:40:20.101493 Dram Type= 6, Freq= 0, CH_0, rank 0
2625 12:40:20.104503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2626 12:40:20.108208 ==
2627 12:40:20.118781 TX Vref=22, minBit 0, minWin=25, winSum=414
2628 12:40:20.122270 TX Vref=24, minBit 0, minWin=25, winSum=418
2629 12:40:20.125323 TX Vref=26, minBit 3, minWin=25, winSum=425
2630 12:40:20.128912 TX Vref=28, minBit 0, minWin=26, winSum=426
2631 12:40:20.132124 TX Vref=30, minBit 1, minWin=26, winSum=430
2632 12:40:20.135425 TX Vref=32, minBit 0, minWin=26, winSum=427
2633 12:40:20.142039 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30
2634 12:40:20.142120
2635 12:40:20.145400 Final TX Range 1 Vref 30
2636 12:40:20.145480
2637 12:40:20.145542 ==
2638 12:40:20.148906 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 12:40:20.152224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 12:40:20.152327 ==
2641 12:40:20.152391
2642 12:40:20.152449
2643 12:40:20.155793 TX Vref Scan disable
2644 12:40:20.159164 == TX Byte 0 ==
2645 12:40:20.162504 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2646 12:40:20.165753 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2647 12:40:20.169012 == TX Byte 1 ==
2648 12:40:20.172123 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2649 12:40:20.175662 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2650 12:40:20.175793
2651 12:40:20.179069 [DATLAT]
2652 12:40:20.179148 Freq=1200, CH0 RK0
2653 12:40:20.179211
2654 12:40:20.182385 DATLAT Default: 0xd
2655 12:40:20.182468 0, 0xFFFF, sum = 0
2656 12:40:20.185810 1, 0xFFFF, sum = 0
2657 12:40:20.185892 2, 0xFFFF, sum = 0
2658 12:40:20.189122 3, 0xFFFF, sum = 0
2659 12:40:20.189204 4, 0xFFFF, sum = 0
2660 12:40:20.192507 5, 0xFFFF, sum = 0
2661 12:40:20.192588 6, 0xFFFF, sum = 0
2662 12:40:20.195798 7, 0xFFFF, sum = 0
2663 12:40:20.195879 8, 0xFFFF, sum = 0
2664 12:40:20.199274 9, 0xFFFF, sum = 0
2665 12:40:20.199386 10, 0xFFFF, sum = 0
2666 12:40:20.202546 11, 0xFFFF, sum = 0
2667 12:40:20.202627 12, 0x0, sum = 1
2668 12:40:20.206041 13, 0x0, sum = 2
2669 12:40:20.206122 14, 0x0, sum = 3
2670 12:40:20.209344 15, 0x0, sum = 4
2671 12:40:20.209424 best_step = 13
2672 12:40:20.209488
2673 12:40:20.209546 ==
2674 12:40:20.212556 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 12:40:20.218941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 12:40:20.219021 ==
2677 12:40:20.219085 RX Vref Scan: 1
2678 12:40:20.219143
2679 12:40:20.222083 Set Vref Range= 32 -> 127
2680 12:40:20.222161
2681 12:40:20.225899 RX Vref 32 -> 127, step: 1
2682 12:40:20.225978
2683 12:40:20.229272 RX Delay -13 -> 252, step: 4
2684 12:40:20.229351
2685 12:40:20.232517 Set Vref, RX VrefLevel [Byte0]: 32
2686 12:40:20.235743 [Byte1]: 32
2687 12:40:20.235823
2688 12:40:20.239224 Set Vref, RX VrefLevel [Byte0]: 33
2689 12:40:20.242546 [Byte1]: 33
2690 12:40:20.242625
2691 12:40:20.245826 Set Vref, RX VrefLevel [Byte0]: 34
2692 12:40:20.249023 [Byte1]: 34
2693 12:40:20.253092
2694 12:40:20.253170 Set Vref, RX VrefLevel [Byte0]: 35
2695 12:40:20.256509 [Byte1]: 35
2696 12:40:20.260671
2697 12:40:20.260749 Set Vref, RX VrefLevel [Byte0]: 36
2698 12:40:20.264228 [Byte1]: 36
2699 12:40:20.268414
2700 12:40:20.268507 Set Vref, RX VrefLevel [Byte0]: 37
2701 12:40:20.271651 [Byte1]: 37
2702 12:40:20.276252
2703 12:40:20.276364 Set Vref, RX VrefLevel [Byte0]: 38
2704 12:40:20.279671 [Byte1]: 38
2705 12:40:20.284276
2706 12:40:20.284379 Set Vref, RX VrefLevel [Byte0]: 39
2707 12:40:20.287541 [Byte1]: 39
2708 12:40:20.292379
2709 12:40:20.292457 Set Vref, RX VrefLevel [Byte0]: 40
2710 12:40:20.295343 [Byte1]: 40
2711 12:40:20.300216
2712 12:40:20.300340 Set Vref, RX VrefLevel [Byte0]: 41
2713 12:40:20.303707 [Byte1]: 41
2714 12:40:20.308409
2715 12:40:20.308490 Set Vref, RX VrefLevel [Byte0]: 42
2716 12:40:20.311073 [Byte1]: 42
2717 12:40:20.315857
2718 12:40:20.315955 Set Vref, RX VrefLevel [Byte0]: 43
2719 12:40:20.319554 [Byte1]: 43
2720 12:40:20.323738
2721 12:40:20.323818 Set Vref, RX VrefLevel [Byte0]: 44
2722 12:40:20.327481 [Byte1]: 44
2723 12:40:20.331733
2724 12:40:20.331812 Set Vref, RX VrefLevel [Byte0]: 45
2725 12:40:20.334963 [Byte1]: 45
2726 12:40:20.339759
2727 12:40:20.339839 Set Vref, RX VrefLevel [Byte0]: 46
2728 12:40:20.342955 [Byte1]: 46
2729 12:40:20.347626
2730 12:40:20.347731 Set Vref, RX VrefLevel [Byte0]: 47
2731 12:40:20.350922 [Byte1]: 47
2732 12:40:20.355418
2733 12:40:20.355497 Set Vref, RX VrefLevel [Byte0]: 48
2734 12:40:20.358571 [Byte1]: 48
2735 12:40:20.363593
2736 12:40:20.363673 Set Vref, RX VrefLevel [Byte0]: 49
2737 12:40:20.366925 [Byte1]: 49
2738 12:40:20.371103
2739 12:40:20.371183 Set Vref, RX VrefLevel [Byte0]: 50
2740 12:40:20.374502 [Byte1]: 50
2741 12:40:20.379288
2742 12:40:20.379368 Set Vref, RX VrefLevel [Byte0]: 51
2743 12:40:20.382665 [Byte1]: 51
2744 12:40:20.386709
2745 12:40:20.386795 Set Vref, RX VrefLevel [Byte0]: 52
2746 12:40:20.390065 [Byte1]: 52
2747 12:40:20.394904
2748 12:40:20.394983 Set Vref, RX VrefLevel [Byte0]: 53
2749 12:40:20.398320 [Byte1]: 53
2750 12:40:20.402920
2751 12:40:20.402998 Set Vref, RX VrefLevel [Byte0]: 54
2752 12:40:20.406044 [Byte1]: 54
2753 12:40:20.410740
2754 12:40:20.410820 Set Vref, RX VrefLevel [Byte0]: 55
2755 12:40:20.414095 [Byte1]: 55
2756 12:40:20.418594
2757 12:40:20.418677 Set Vref, RX VrefLevel [Byte0]: 56
2758 12:40:20.421673 [Byte1]: 56
2759 12:40:20.426114
2760 12:40:20.426196 Set Vref, RX VrefLevel [Byte0]: 57
2761 12:40:20.429549 [Byte1]: 57
2762 12:40:20.434422
2763 12:40:20.434503 Set Vref, RX VrefLevel [Byte0]: 58
2764 12:40:20.437700 [Byte1]: 58
2765 12:40:20.442490
2766 12:40:20.442571 Set Vref, RX VrefLevel [Byte0]: 59
2767 12:40:20.445627 [Byte1]: 59
2768 12:40:20.449955
2769 12:40:20.450071 Set Vref, RX VrefLevel [Byte0]: 60
2770 12:40:20.453501 [Byte1]: 60
2771 12:40:20.457990
2772 12:40:20.458128 Set Vref, RX VrefLevel [Byte0]: 61
2773 12:40:20.461263 [Byte1]: 61
2774 12:40:20.465922
2775 12:40:20.466100 Set Vref, RX VrefLevel [Byte0]: 62
2776 12:40:20.469035 [Byte1]: 62
2777 12:40:20.473867
2778 12:40:20.473949 Set Vref, RX VrefLevel [Byte0]: 63
2779 12:40:20.477337 [Byte1]: 63
2780 12:40:20.481515
2781 12:40:20.481597 Set Vref, RX VrefLevel [Byte0]: 64
2782 12:40:20.484874 [Byte1]: 64
2783 12:40:20.489613
2784 12:40:20.489695 Set Vref, RX VrefLevel [Byte0]: 65
2785 12:40:20.492967 [Byte1]: 65
2786 12:40:20.497785
2787 12:40:20.497865 Set Vref, RX VrefLevel [Byte0]: 66
2788 12:40:20.501057 [Byte1]: 66
2789 12:40:20.505024
2790 12:40:20.505105 Set Vref, RX VrefLevel [Byte0]: 67
2791 12:40:20.508295 [Byte1]: 67
2792 12:40:20.513187
2793 12:40:20.513268 Set Vref, RX VrefLevel [Byte0]: 68
2794 12:40:20.516678 [Byte1]: 68
2795 12:40:20.521440
2796 12:40:20.521520 Final RX Vref Byte 0 = 55 to rank0
2797 12:40:20.524570 Final RX Vref Byte 1 = 47 to rank0
2798 12:40:20.527594 Final RX Vref Byte 0 = 55 to rank1
2799 12:40:20.531125 Final RX Vref Byte 1 = 47 to rank1==
2800 12:40:20.534488 Dram Type= 6, Freq= 0, CH_0, rank 0
2801 12:40:20.537645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2802 12:40:20.540951 ==
2803 12:40:20.541051 DQS Delay:
2804 12:40:20.541140 DQS0 = 0, DQS1 = 0
2805 12:40:20.544490 DQM Delay:
2806 12:40:20.544559 DQM0 = 120, DQM1 = 111
2807 12:40:20.547699 DQ Delay:
2808 12:40:20.551473 DQ0 =120, DQ1 =120, DQ2 =120, DQ3 =120
2809 12:40:20.554500 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2810 12:40:20.557520 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =106
2811 12:40:20.561216 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =120
2812 12:40:20.561296
2813 12:40:20.561357
2814 12:40:20.567649 [DQSOSCAuto] RK0, (LSB)MR18= 0x1812, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 400 ps
2815 12:40:20.571599 CH0 RK0: MR19=404, MR18=1812
2816 12:40:20.577748 CH0_RK0: MR19=0x404, MR18=0x1812, DQSOSC=400, MR23=63, INC=40, DEC=27
2817 12:40:20.577868
2818 12:40:20.581564 ----->DramcWriteLeveling(PI) begin...
2819 12:40:20.581645 ==
2820 12:40:20.584512 Dram Type= 6, Freq= 0, CH_0, rank 1
2821 12:40:20.587919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2822 12:40:20.588000 ==
2823 12:40:20.591306 Write leveling (Byte 0): 31 => 31
2824 12:40:20.594600 Write leveling (Byte 1): 30 => 30
2825 12:40:20.597975 DramcWriteLeveling(PI) end<-----
2826 12:40:20.598056
2827 12:40:20.598120 ==
2828 12:40:20.601438 Dram Type= 6, Freq= 0, CH_0, rank 1
2829 12:40:20.608157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2830 12:40:20.608264 ==
2831 12:40:20.608409 [Gating] SW mode calibration
2832 12:40:20.617828 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2833 12:40:20.621335 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2834 12:40:20.624782 0 15 0 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (0 0)
2835 12:40:20.630937 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2836 12:40:20.634409 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2837 12:40:20.637742 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2838 12:40:20.644400 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 12:40:20.647639 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 12:40:20.651421 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 12:40:20.657910 0 15 28 | B1->B0 | 3131 2e2e | 1 1 | (1 0) (1 0)
2842 12:40:20.661222 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
2843 12:40:20.664596 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2844 12:40:20.671410 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 12:40:20.674498 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 12:40:20.678103 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 12:40:20.684558 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 12:40:20.688026 1 0 24 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
2849 12:40:20.690814 1 0 28 | B1->B0 | 3f3f 3e3e | 0 0 | (1 1) (1 1)
2850 12:40:20.697639 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2851 12:40:20.700958 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 12:40:20.704270 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 12:40:20.711308 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 12:40:20.714660 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 12:40:20.717510 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 12:40:20.720988 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 12:40:20.727855 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2858 12:40:20.731244 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 12:40:20.734714 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 12:40:20.740872 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 12:40:20.744197 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 12:40:20.747591 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 12:40:20.754494 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 12:40:20.757893 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 12:40:20.761211 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 12:40:20.767907 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 12:40:20.771187 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 12:40:20.774302 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 12:40:20.781089 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 12:40:20.784297 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 12:40:20.788023 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 12:40:20.794567 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 12:40:20.797677 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2874 12:40:20.800923 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 12:40:20.804368 Total UI for P1: 0, mck2ui 16
2876 12:40:20.807804 best dqsien dly found for B0: ( 1, 3, 28)
2877 12:40:20.811107 Total UI for P1: 0, mck2ui 16
2878 12:40:20.814563 best dqsien dly found for B1: ( 1, 3, 28)
2879 12:40:20.818043 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2880 12:40:20.821323 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2881 12:40:20.821478
2882 12:40:20.824674 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2883 12:40:20.827593 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2884 12:40:20.831265 [Gating] SW calibration Done
2885 12:40:20.831347 ==
2886 12:40:20.834653 Dram Type= 6, Freq= 0, CH_0, rank 1
2887 12:40:20.840884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2888 12:40:20.840961 ==
2889 12:40:20.841023 RX Vref Scan: 0
2890 12:40:20.841089
2891 12:40:20.844959 RX Vref 0 -> 0, step: 1
2892 12:40:20.845034
2893 12:40:20.847620 RX Delay -40 -> 252, step: 8
2894 12:40:20.851115 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2895 12:40:20.854506 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2896 12:40:20.858011 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2897 12:40:20.861399 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2898 12:40:20.868075 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2899 12:40:20.871364 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2900 12:40:20.874789 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2901 12:40:20.877692 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2902 12:40:20.881086 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2903 12:40:20.887527 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2904 12:40:20.891233 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2905 12:40:20.894393 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2906 12:40:20.897657 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2907 12:40:20.900764 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2908 12:40:20.907612 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2909 12:40:20.911220 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2910 12:40:20.911301 ==
2911 12:40:20.914289 Dram Type= 6, Freq= 0, CH_0, rank 1
2912 12:40:20.917666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2913 12:40:20.917747 ==
2914 12:40:20.920971 DQS Delay:
2915 12:40:20.921051 DQS0 = 0, DQS1 = 0
2916 12:40:20.921113 DQM Delay:
2917 12:40:20.924949 DQM0 = 122, DQM1 = 112
2918 12:40:20.925029 DQ Delay:
2919 12:40:20.927606 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2920 12:40:20.931082 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2921 12:40:20.934547 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2922 12:40:20.938341 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2923 12:40:20.941551
2924 12:40:20.941636
2925 12:40:20.941732 ==
2926 12:40:20.944805 Dram Type= 6, Freq= 0, CH_0, rank 1
2927 12:40:20.948341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2928 12:40:20.948448 ==
2929 12:40:20.948628
2930 12:40:20.948733
2931 12:40:20.951115 TX Vref Scan disable
2932 12:40:20.951212 == TX Byte 0 ==
2933 12:40:20.957928 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2934 12:40:20.961308 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2935 12:40:20.961403 == TX Byte 1 ==
2936 12:40:20.968171 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2937 12:40:20.971491 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2938 12:40:20.971571 ==
2939 12:40:20.974731 Dram Type= 6, Freq= 0, CH_0, rank 1
2940 12:40:20.978114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2941 12:40:20.978198 ==
2942 12:40:20.990409 TX Vref=22, minBit 2, minWin=25, winSum=416
2943 12:40:20.993710 TX Vref=24, minBit 1, minWin=25, winSum=424
2944 12:40:20.997136 TX Vref=26, minBit 1, minWin=25, winSum=423
2945 12:40:21.000067 TX Vref=28, minBit 1, minWin=26, winSum=430
2946 12:40:21.003925 TX Vref=30, minBit 0, minWin=26, winSum=430
2947 12:40:21.007215 TX Vref=32, minBit 0, minWin=26, winSum=425
2948 12:40:21.013932 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 28
2949 12:40:21.014038
2950 12:40:21.017212 Final TX Range 1 Vref 28
2951 12:40:21.017305
2952 12:40:21.017385 ==
2953 12:40:21.020448 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 12:40:21.024149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 12:40:21.024234 ==
2956 12:40:21.024311
2957 12:40:21.024420
2958 12:40:21.027391 TX Vref Scan disable
2959 12:40:21.030473 == TX Byte 0 ==
2960 12:40:21.033796 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2961 12:40:21.037077 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2962 12:40:21.040570 == TX Byte 1 ==
2963 12:40:21.043987 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2964 12:40:21.047534 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2965 12:40:21.047633
2966 12:40:21.050871 [DATLAT]
2967 12:40:21.050943 Freq=1200, CH0 RK1
2968 12:40:21.051009
2969 12:40:21.054338 DATLAT Default: 0xd
2970 12:40:21.054412 0, 0xFFFF, sum = 0
2971 12:40:21.057385 1, 0xFFFF, sum = 0
2972 12:40:21.057461 2, 0xFFFF, sum = 0
2973 12:40:21.060587 3, 0xFFFF, sum = 0
2974 12:40:21.060699 4, 0xFFFF, sum = 0
2975 12:40:21.064067 5, 0xFFFF, sum = 0
2976 12:40:21.064151 6, 0xFFFF, sum = 0
2977 12:40:21.067469 7, 0xFFFF, sum = 0
2978 12:40:21.067553 8, 0xFFFF, sum = 0
2979 12:40:21.070950 9, 0xFFFF, sum = 0
2980 12:40:21.071061 10, 0xFFFF, sum = 0
2981 12:40:21.074354 11, 0xFFFF, sum = 0
2982 12:40:21.074437 12, 0x0, sum = 1
2983 12:40:21.077840 13, 0x0, sum = 2
2984 12:40:21.077940 14, 0x0, sum = 3
2985 12:40:21.081196 15, 0x0, sum = 4
2986 12:40:21.081308 best_step = 13
2987 12:40:21.081401
2988 12:40:21.081495 ==
2989 12:40:21.084294 Dram Type= 6, Freq= 0, CH_0, rank 1
2990 12:40:21.090478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2991 12:40:21.090586 ==
2992 12:40:21.090681 RX Vref Scan: 0
2993 12:40:21.090770
2994 12:40:21.093955 RX Vref 0 -> 0, step: 1
2995 12:40:21.094037
2996 12:40:21.097365 RX Delay -13 -> 252, step: 4
2997 12:40:21.100854 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
2998 12:40:21.104259 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
2999 12:40:21.110609 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3000 12:40:21.114575 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3001 12:40:21.117789 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3002 12:40:21.121118 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3003 12:40:21.123929 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3004 12:40:21.127245 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3005 12:40:21.134464 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3006 12:40:21.137867 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3007 12:40:21.141074 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3008 12:40:21.144495 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3009 12:40:21.147726 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3010 12:40:21.154055 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3011 12:40:21.157506 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3012 12:40:21.160834 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3013 12:40:21.160917 ==
3014 12:40:21.164241 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 12:40:21.167766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 12:40:21.167850 ==
3017 12:40:21.170983 DQS Delay:
3018 12:40:21.171100 DQS0 = 0, DQS1 = 0
3019 12:40:21.174207 DQM Delay:
3020 12:40:21.174288 DQM0 = 121, DQM1 = 109
3021 12:40:21.174382 DQ Delay:
3022 12:40:21.181095 DQ0 =118, DQ1 =120, DQ2 =118, DQ3 =118
3023 12:40:21.184504 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =128
3024 12:40:21.187716 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =100
3025 12:40:21.191057 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =118
3026 12:40:21.191141
3027 12:40:21.191205
3028 12:40:21.197419 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 403 ps
3029 12:40:21.201458 CH0 RK1: MR19=403, MR18=10F2
3030 12:40:21.208070 CH0_RK1: MR19=0x403, MR18=0x10F2, DQSOSC=403, MR23=63, INC=40, DEC=26
3031 12:40:21.210972 [RxdqsGatingPostProcess] freq 1200
3032 12:40:21.214920 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3033 12:40:21.218114 best DQS0 dly(2T, 0.5T) = (0, 11)
3034 12:40:21.221109 best DQS1 dly(2T, 0.5T) = (0, 12)
3035 12:40:21.224824 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3036 12:40:21.228015 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3037 12:40:21.231324 best DQS0 dly(2T, 0.5T) = (0, 11)
3038 12:40:21.234628 best DQS1 dly(2T, 0.5T) = (0, 11)
3039 12:40:21.238120 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3040 12:40:21.241473 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3041 12:40:21.244816 Pre-setting of DQS Precalculation
3042 12:40:21.248186 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3043 12:40:21.248276 ==
3044 12:40:21.251412 Dram Type= 6, Freq= 0, CH_1, rank 0
3045 12:40:21.258280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3046 12:40:21.258378 ==
3047 12:40:21.261670 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3048 12:40:21.267941 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3049 12:40:21.276960 [CA 0] Center 37 (7~68) winsize 62
3050 12:40:21.280221 [CA 1] Center 37 (7~68) winsize 62
3051 12:40:21.283692 [CA 2] Center 35 (5~65) winsize 61
3052 12:40:21.286486 [CA 3] Center 34 (4~64) winsize 61
3053 12:40:21.289970 [CA 4] Center 34 (4~64) winsize 61
3054 12:40:21.293860 [CA 5] Center 33 (3~63) winsize 61
3055 12:40:21.293944
3056 12:40:21.296755 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3057 12:40:21.296842
3058 12:40:21.299860 [CATrainingPosCal] consider 1 rank data
3059 12:40:21.303322 u2DelayCellTimex100 = 270/100 ps
3060 12:40:21.306714 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3061 12:40:21.310075 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3062 12:40:21.313497 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3063 12:40:21.320393 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3064 12:40:21.323811 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3065 12:40:21.326879 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3066 12:40:21.326964
3067 12:40:21.330006 CA PerBit enable=1, Macro0, CA PI delay=33
3068 12:40:21.330091
3069 12:40:21.333754 [CBTSetCACLKResult] CA Dly = 33
3070 12:40:21.333838 CS Dly: 8 (0~39)
3071 12:40:21.333924 ==
3072 12:40:21.337004 Dram Type= 6, Freq= 0, CH_1, rank 1
3073 12:40:21.343571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 12:40:21.343658 ==
3075 12:40:21.346981 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3076 12:40:21.353439 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3077 12:40:21.361922 [CA 0] Center 37 (7~68) winsize 62
3078 12:40:21.365361 [CA 1] Center 37 (7~68) winsize 62
3079 12:40:21.368775 [CA 2] Center 35 (5~65) winsize 61
3080 12:40:21.372139 [CA 3] Center 35 (5~65) winsize 61
3081 12:40:21.375568 [CA 4] Center 34 (4~65) winsize 62
3082 12:40:21.378938 [CA 5] Center 34 (4~64) winsize 61
3083 12:40:21.379044
3084 12:40:21.382281 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3085 12:40:21.382384
3086 12:40:21.385723 [CATrainingPosCal] consider 2 rank data
3087 12:40:21.389111 u2DelayCellTimex100 = 270/100 ps
3088 12:40:21.392626 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3089 12:40:21.396117 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3090 12:40:21.398924 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3091 12:40:21.405841 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3092 12:40:21.409161 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3093 12:40:21.412554 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3094 12:40:21.412628
3095 12:40:21.415774 CA PerBit enable=1, Macro0, CA PI delay=33
3096 12:40:21.415846
3097 12:40:21.418976 [CBTSetCACLKResult] CA Dly = 33
3098 12:40:21.419048 CS Dly: 9 (0~41)
3099 12:40:21.419106
3100 12:40:21.422348 ----->DramcWriteLeveling(PI) begin...
3101 12:40:21.422418 ==
3102 12:40:21.425541 Dram Type= 6, Freq= 0, CH_1, rank 0
3103 12:40:21.432259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3104 12:40:21.432379 ==
3105 12:40:21.435812 Write leveling (Byte 0): 25 => 25
3106 12:40:21.439159 Write leveling (Byte 1): 27 => 27
3107 12:40:21.439239 DramcWriteLeveling(PI) end<-----
3108 12:40:21.442427
3109 12:40:21.442500 ==
3110 12:40:21.445715 Dram Type= 6, Freq= 0, CH_1, rank 0
3111 12:40:21.449318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3112 12:40:21.449416 ==
3113 12:40:21.452278 [Gating] SW mode calibration
3114 12:40:21.458876 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3115 12:40:21.462314 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3116 12:40:21.468920 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3117 12:40:21.472566 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3118 12:40:21.475610 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 12:40:21.482523 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 12:40:21.486025 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 12:40:21.489404 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 12:40:21.496033 0 15 24 | B1->B0 | 3030 2929 | 0 1 | (0 1) (1 0)
3123 12:40:21.498834 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
3124 12:40:21.502210 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 12:40:21.509101 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 12:40:21.512509 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 12:40:21.515973 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 12:40:21.519406 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 12:40:21.525981 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 12:40:21.529356 1 0 24 | B1->B0 | 3333 4242 | 0 0 | (0 0) (0 0)
3131 12:40:21.532761 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3132 12:40:21.539624 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 12:40:21.543013 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 12:40:21.546447 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 12:40:21.552553 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 12:40:21.556301 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 12:40:21.559713 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 12:40:21.565834 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3139 12:40:21.569467 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3140 12:40:21.572905 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 12:40:21.579584 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 12:40:21.582647 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 12:40:21.585955 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 12:40:21.592479 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 12:40:21.596185 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 12:40:21.599139 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 12:40:21.602768 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 12:40:21.609520 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 12:40:21.612901 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 12:40:21.616349 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 12:40:21.622529 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 12:40:21.625916 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 12:40:21.629210 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 12:40:21.635899 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3155 12:40:21.639344 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3156 12:40:21.642892 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 12:40:21.646199 Total UI for P1: 0, mck2ui 16
3158 12:40:21.649541 best dqsien dly found for B0: ( 1, 3, 26)
3159 12:40:21.652925 Total UI for P1: 0, mck2ui 16
3160 12:40:21.656405 best dqsien dly found for B1: ( 1, 3, 26)
3161 12:40:21.659315 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3162 12:40:21.662656 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3163 12:40:21.662725
3164 12:40:21.669290 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3165 12:40:21.672679 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3166 12:40:21.672753 [Gating] SW calibration Done
3167 12:40:21.676214 ==
3168 12:40:21.679509 Dram Type= 6, Freq= 0, CH_1, rank 0
3169 12:40:21.682624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3170 12:40:21.682714 ==
3171 12:40:21.682781 RX Vref Scan: 0
3172 12:40:21.682860
3173 12:40:21.686023 RX Vref 0 -> 0, step: 1
3174 12:40:21.686105
3175 12:40:21.689182 RX Delay -40 -> 252, step: 8
3176 12:40:21.692474 iDelay=200, Bit 0, Center 127 (56 ~ 199) 144
3177 12:40:21.696396 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3178 12:40:21.699542 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3179 12:40:21.706108 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3180 12:40:21.709630 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3181 12:40:21.712627 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3182 12:40:21.716035 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3183 12:40:21.719518 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3184 12:40:21.726294 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3185 12:40:21.729713 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3186 12:40:21.733060 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3187 12:40:21.736202 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3188 12:40:21.739280 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3189 12:40:21.746114 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3190 12:40:21.749454 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3191 12:40:21.752883 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3192 12:40:21.752966 ==
3193 12:40:21.756208 Dram Type= 6, Freq= 0, CH_1, rank 0
3194 12:40:21.759673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3195 12:40:21.759746 ==
3196 12:40:21.763080 DQS Delay:
3197 12:40:21.763148 DQS0 = 0, DQS1 = 0
3198 12:40:21.763207 DQM Delay:
3199 12:40:21.766487 DQM0 = 120, DQM1 = 116
3200 12:40:21.766553 DQ Delay:
3201 12:40:21.769730 DQ0 =127, DQ1 =115, DQ2 =107, DQ3 =119
3202 12:40:21.773193 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3203 12:40:21.779954 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3204 12:40:21.783301 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3205 12:40:21.783384
3206 12:40:21.783452
3207 12:40:21.783510 ==
3208 12:40:21.786698 Dram Type= 6, Freq= 0, CH_1, rank 0
3209 12:40:21.789841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3210 12:40:21.789914 ==
3211 12:40:21.789972
3212 12:40:21.790028
3213 12:40:21.793285 TX Vref Scan disable
3214 12:40:21.793355 == TX Byte 0 ==
3215 12:40:21.800030 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3216 12:40:21.803203 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3217 12:40:21.803308 == TX Byte 1 ==
3218 12:40:21.810028 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3219 12:40:21.813437 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3220 12:40:21.813516 ==
3221 12:40:21.816861 Dram Type= 6, Freq= 0, CH_1, rank 0
3222 12:40:21.820090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3223 12:40:21.820192 ==
3224 12:40:21.832557 TX Vref=22, minBit 9, minWin=24, winSum=410
3225 12:40:21.836197 TX Vref=24, minBit 10, minWin=25, winSum=418
3226 12:40:21.838923 TX Vref=26, minBit 10, minWin=25, winSum=422
3227 12:40:21.842176 TX Vref=28, minBit 9, minWin=25, winSum=425
3228 12:40:21.845997 TX Vref=30, minBit 10, minWin=26, winSum=433
3229 12:40:21.852568 TX Vref=32, minBit 10, minWin=26, winSum=428
3230 12:40:21.855799 [TxChooseVref] Worse bit 10, Min win 26, Win sum 433, Final Vref 30
3231 12:40:21.855880
3232 12:40:21.858963 Final TX Range 1 Vref 30
3233 12:40:21.859068
3234 12:40:21.859159 ==
3235 12:40:21.862648 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 12:40:21.866109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 12:40:21.868977 ==
3238 12:40:21.869057
3239 12:40:21.869161
3240 12:40:21.869219 TX Vref Scan disable
3241 12:40:21.872256 == TX Byte 0 ==
3242 12:40:21.875673 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3243 12:40:21.882540 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3244 12:40:21.882623 == TX Byte 1 ==
3245 12:40:21.885950 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3246 12:40:21.889329 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3247 12:40:21.892702
3248 12:40:21.892782 [DATLAT]
3249 12:40:21.892845 Freq=1200, CH1 RK0
3250 12:40:21.892905
3251 12:40:21.895881 DATLAT Default: 0xd
3252 12:40:21.895961 0, 0xFFFF, sum = 0
3253 12:40:21.899377 1, 0xFFFF, sum = 0
3254 12:40:21.899476 2, 0xFFFF, sum = 0
3255 12:40:21.902822 3, 0xFFFF, sum = 0
3256 12:40:21.902903 4, 0xFFFF, sum = 0
3257 12:40:21.905589 5, 0xFFFF, sum = 0
3258 12:40:21.909570 6, 0xFFFF, sum = 0
3259 12:40:21.909651 7, 0xFFFF, sum = 0
3260 12:40:21.912642 8, 0xFFFF, sum = 0
3261 12:40:21.912723 9, 0xFFFF, sum = 0
3262 12:40:21.916131 10, 0xFFFF, sum = 0
3263 12:40:21.916211 11, 0xFFFF, sum = 0
3264 12:40:21.919548 12, 0x0, sum = 1
3265 12:40:21.919627 13, 0x0, sum = 2
3266 12:40:21.922219 14, 0x0, sum = 3
3267 12:40:21.922289 15, 0x0, sum = 4
3268 12:40:21.922350 best_step = 13
3269 12:40:21.922411
3270 12:40:21.925692 ==
3271 12:40:21.929083 Dram Type= 6, Freq= 0, CH_1, rank 0
3272 12:40:21.932394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3273 12:40:21.932470 ==
3274 12:40:21.932529 RX Vref Scan: 1
3275 12:40:21.932584
3276 12:40:21.935835 Set Vref Range= 32 -> 127
3277 12:40:21.935908
3278 12:40:21.939058 RX Vref 32 -> 127, step: 1
3279 12:40:21.939147
3280 12:40:21.942443 RX Delay -5 -> 252, step: 4
3281 12:40:21.942525
3282 12:40:21.946139 Set Vref, RX VrefLevel [Byte0]: 32
3283 12:40:21.949227 [Byte1]: 32
3284 12:40:21.949307
3285 12:40:21.952296 Set Vref, RX VrefLevel [Byte0]: 33
3286 12:40:21.956199 [Byte1]: 33
3287 12:40:21.956326
3288 12:40:21.959664 Set Vref, RX VrefLevel [Byte0]: 34
3289 12:40:21.962829 [Byte1]: 34
3290 12:40:21.966645
3291 12:40:21.966724 Set Vref, RX VrefLevel [Byte0]: 35
3292 12:40:21.969834 [Byte1]: 35
3293 12:40:21.974495
3294 12:40:21.974590 Set Vref, RX VrefLevel [Byte0]: 36
3295 12:40:21.977969 [Byte1]: 36
3296 12:40:21.982279
3297 12:40:21.982362 Set Vref, RX VrefLevel [Byte0]: 37
3298 12:40:21.985421 [Byte1]: 37
3299 12:40:21.989963
3300 12:40:21.990046 Set Vref, RX VrefLevel [Byte0]: 38
3301 12:40:21.993313 [Byte1]: 38
3302 12:40:21.998083
3303 12:40:21.998162 Set Vref, RX VrefLevel [Byte0]: 39
3304 12:40:22.001535 [Byte1]: 39
3305 12:40:22.006071
3306 12:40:22.006150 Set Vref, RX VrefLevel [Byte0]: 40
3307 12:40:22.009510 [Byte1]: 40
3308 12:40:22.013770
3309 12:40:22.013842 Set Vref, RX VrefLevel [Byte0]: 41
3310 12:40:22.017169 [Byte1]: 41
3311 12:40:22.021872
3312 12:40:22.021942 Set Vref, RX VrefLevel [Byte0]: 42
3313 12:40:22.025153 [Byte1]: 42
3314 12:40:22.029335
3315 12:40:22.029406 Set Vref, RX VrefLevel [Byte0]: 43
3316 12:40:22.032688 [Byte1]: 43
3317 12:40:22.037391
3318 12:40:22.037475 Set Vref, RX VrefLevel [Byte0]: 44
3319 12:40:22.040691 [Byte1]: 44
3320 12:40:22.045368
3321 12:40:22.045447 Set Vref, RX VrefLevel [Byte0]: 45
3322 12:40:22.048134 [Byte1]: 45
3323 12:40:22.052892
3324 12:40:22.052962 Set Vref, RX VrefLevel [Byte0]: 46
3325 12:40:22.056190 [Byte1]: 46
3326 12:40:22.060585
3327 12:40:22.060662 Set Vref, RX VrefLevel [Byte0]: 47
3328 12:40:22.064214 [Byte1]: 47
3329 12:40:22.068872
3330 12:40:22.068981 Set Vref, RX VrefLevel [Byte0]: 48
3331 12:40:22.072143 [Byte1]: 48
3332 12:40:22.076280
3333 12:40:22.076384 Set Vref, RX VrefLevel [Byte0]: 49
3334 12:40:22.079719 [Byte1]: 49
3335 12:40:22.084277
3336 12:40:22.084411 Set Vref, RX VrefLevel [Byte0]: 50
3337 12:40:22.087587 [Byte1]: 50
3338 12:40:22.092282
3339 12:40:22.092385 Set Vref, RX VrefLevel [Byte0]: 51
3340 12:40:22.095309 [Byte1]: 51
3341 12:40:22.099820
3342 12:40:22.099913 Set Vref, RX VrefLevel [Byte0]: 52
3343 12:40:22.103271 [Byte1]: 52
3344 12:40:22.107642
3345 12:40:22.107715 Set Vref, RX VrefLevel [Byte0]: 53
3346 12:40:22.111275 [Byte1]: 53
3347 12:40:22.115595
3348 12:40:22.115671 Set Vref, RX VrefLevel [Byte0]: 54
3349 12:40:22.119022 [Byte1]: 54
3350 12:40:22.123650
3351 12:40:22.123726 Set Vref, RX VrefLevel [Byte0]: 55
3352 12:40:22.127159 [Byte1]: 55
3353 12:40:22.131712
3354 12:40:22.131811 Set Vref, RX VrefLevel [Byte0]: 56
3355 12:40:22.134497 [Byte1]: 56
3356 12:40:22.139179
3357 12:40:22.139260 Set Vref, RX VrefLevel [Byte0]: 57
3358 12:40:22.142629 [Byte1]: 57
3359 12:40:22.147326
3360 12:40:22.147425 Set Vref, RX VrefLevel [Byte0]: 58
3361 12:40:22.150903 [Byte1]: 58
3362 12:40:22.154950
3363 12:40:22.155037 Set Vref, RX VrefLevel [Byte0]: 59
3364 12:40:22.158322 [Byte1]: 59
3365 12:40:22.163115
3366 12:40:22.163187 Set Vref, RX VrefLevel [Byte0]: 60
3367 12:40:22.166573 [Byte1]: 60
3368 12:40:22.170540
3369 12:40:22.170637 Set Vref, RX VrefLevel [Byte0]: 61
3370 12:40:22.174373 [Byte1]: 61
3371 12:40:22.178609
3372 12:40:22.178691 Set Vref, RX VrefLevel [Byte0]: 62
3373 12:40:22.182166 [Byte1]: 62
3374 12:40:22.186170
3375 12:40:22.186253 Set Vref, RX VrefLevel [Byte0]: 63
3376 12:40:22.189666 [Byte1]: 63
3377 12:40:22.194494
3378 12:40:22.194578 Set Vref, RX VrefLevel [Byte0]: 64
3379 12:40:22.197772 [Byte1]: 64
3380 12:40:22.201793
3381 12:40:22.201865 Set Vref, RX VrefLevel [Byte0]: 65
3382 12:40:22.205082 [Byte1]: 65
3383 12:40:22.210249
3384 12:40:22.210324 Set Vref, RX VrefLevel [Byte0]: 66
3385 12:40:22.213358 [Byte1]: 66
3386 12:40:22.217546
3387 12:40:22.217623 Set Vref, RX VrefLevel [Byte0]: 67
3388 12:40:22.221114 [Byte1]: 67
3389 12:40:22.225540
3390 12:40:22.225620 Set Vref, RX VrefLevel [Byte0]: 68
3391 12:40:22.228888 [Byte1]: 68
3392 12:40:22.233214
3393 12:40:22.233283 Final RX Vref Byte 0 = 52 to rank0
3394 12:40:22.237136 Final RX Vref Byte 1 = 54 to rank0
3395 12:40:22.239881 Final RX Vref Byte 0 = 52 to rank1
3396 12:40:22.243717 Final RX Vref Byte 1 = 54 to rank1==
3397 12:40:22.246892 Dram Type= 6, Freq= 0, CH_1, rank 0
3398 12:40:22.250071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3399 12:40:22.254003 ==
3400 12:40:22.254087 DQS Delay:
3401 12:40:22.254172 DQS0 = 0, DQS1 = 0
3402 12:40:22.257434 DQM Delay:
3403 12:40:22.257517 DQM0 = 120, DQM1 = 118
3404 12:40:22.260195 DQ Delay:
3405 12:40:22.263775 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3406 12:40:22.267139 DQ4 =120, DQ5 =128, DQ6 =130, DQ7 =120
3407 12:40:22.270584 DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112
3408 12:40:22.273985 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3409 12:40:22.274060
3410 12:40:22.274122
3411 12:40:22.280124 [DQSOSCAuto] RK0, (LSB)MR18= 0x316, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3412 12:40:22.283535 CH1 RK0: MR19=404, MR18=316
3413 12:40:22.290158 CH1_RK0: MR19=0x404, MR18=0x316, DQSOSC=401, MR23=63, INC=40, DEC=27
3414 12:40:22.290241
3415 12:40:22.293670 ----->DramcWriteLeveling(PI) begin...
3416 12:40:22.293741 ==
3417 12:40:22.297175 Dram Type= 6, Freq= 0, CH_1, rank 1
3418 12:40:22.300040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3419 12:40:22.300110 ==
3420 12:40:22.303428 Write leveling (Byte 0): 26 => 26
3421 12:40:22.306817 Write leveling (Byte 1): 29 => 29
3422 12:40:22.310177 DramcWriteLeveling(PI) end<-----
3423 12:40:22.310280
3424 12:40:22.310378 ==
3425 12:40:22.313548 Dram Type= 6, Freq= 0, CH_1, rank 1
3426 12:40:22.320468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3427 12:40:22.320555 ==
3428 12:40:22.320618 [Gating] SW mode calibration
3429 12:40:22.330279 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3430 12:40:22.333533 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3431 12:40:22.337003 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3432 12:40:22.343764 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3433 12:40:22.347011 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3434 12:40:22.350308 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3435 12:40:22.357059 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3436 12:40:22.360860 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
3437 12:40:22.363704 0 15 24 | B1->B0 | 2525 3333 | 0 0 | (1 0) (0 1)
3438 12:40:22.370440 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 0)
3439 12:40:22.374007 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3440 12:40:22.377263 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3441 12:40:22.380701 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3442 12:40:22.387594 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3443 12:40:22.390963 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3444 12:40:22.394402 1 0 20 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3445 12:40:22.401029 1 0 24 | B1->B0 | 4444 2c2b | 0 1 | (0 0) (0 0)
3446 12:40:22.404233 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3447 12:40:22.407237 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3448 12:40:22.414228 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3449 12:40:22.417489 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3450 12:40:22.420991 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 12:40:22.427144 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 12:40:22.430486 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3453 12:40:22.433879 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3454 12:40:22.440993 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3455 12:40:22.444111 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 12:40:22.447439 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 12:40:22.454270 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 12:40:22.457757 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 12:40:22.460438 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 12:40:22.467168 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 12:40:22.470461 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 12:40:22.473700 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 12:40:22.480516 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 12:40:22.483756 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 12:40:22.486997 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 12:40:22.490324 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 12:40:22.496892 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 12:40:22.500252 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3469 12:40:22.503658 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3470 12:40:22.506980 Total UI for P1: 0, mck2ui 16
3471 12:40:22.510365 best dqsien dly found for B1: ( 1, 3, 20)
3472 12:40:22.516854 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 12:40:22.520095 Total UI for P1: 0, mck2ui 16
3474 12:40:22.523179 best dqsien dly found for B0: ( 1, 3, 24)
3475 12:40:22.526870 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3476 12:40:22.530259 best DQS1 dly(MCK, UI, PI) = (1, 3, 20)
3477 12:40:22.530361
3478 12:40:22.533711 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3479 12:40:22.537143 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 20)
3480 12:40:22.539871 [Gating] SW calibration Done
3481 12:40:22.539954 ==
3482 12:40:22.543251 Dram Type= 6, Freq= 0, CH_1, rank 1
3483 12:40:22.546560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3484 12:40:22.546644 ==
3485 12:40:22.549853 RX Vref Scan: 0
3486 12:40:22.549936
3487 12:40:22.553041 RX Vref 0 -> 0, step: 1
3488 12:40:22.553125
3489 12:40:22.553209 RX Delay -40 -> 252, step: 8
3490 12:40:22.559576 iDelay=200, Bit 0, Center 127 (64 ~ 191) 128
3491 12:40:22.563009 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3492 12:40:22.566533 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3493 12:40:22.569997 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3494 12:40:22.573467 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3495 12:40:22.579669 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3496 12:40:22.582894 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3497 12:40:22.586371 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3498 12:40:22.589817 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3499 12:40:22.593161 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3500 12:40:22.599555 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3501 12:40:22.602895 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3502 12:40:22.606482 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3503 12:40:22.609882 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3504 12:40:22.613149 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3505 12:40:22.619927 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3506 12:40:22.620013 ==
3507 12:40:22.623378 Dram Type= 6, Freq= 0, CH_1, rank 1
3508 12:40:22.626929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3509 12:40:22.627014 ==
3510 12:40:22.627099 DQS Delay:
3511 12:40:22.630096 DQS0 = 0, DQS1 = 0
3512 12:40:22.630179 DQM Delay:
3513 12:40:22.633399 DQM0 = 120, DQM1 = 117
3514 12:40:22.633482 DQ Delay:
3515 12:40:22.636546 DQ0 =127, DQ1 =115, DQ2 =107, DQ3 =115
3516 12:40:22.640120 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =119
3517 12:40:22.643122 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =115
3518 12:40:22.646262 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3519 12:40:22.646349
3520 12:40:22.646434
3521 12:40:22.649721 ==
3522 12:40:22.653150 Dram Type= 6, Freq= 0, CH_1, rank 1
3523 12:40:22.656633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3524 12:40:22.656717 ==
3525 12:40:22.656801
3526 12:40:22.656932
3527 12:40:22.660090 TX Vref Scan disable
3528 12:40:22.660173 == TX Byte 0 ==
3529 12:40:22.663360 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3530 12:40:22.669988 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3531 12:40:22.670072 == TX Byte 1 ==
3532 12:40:22.672890 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3533 12:40:22.679707 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3534 12:40:22.679791 ==
3535 12:40:22.683029 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 12:40:22.686444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 12:40:22.686529 ==
3538 12:40:22.698648 TX Vref=22, minBit 9, minWin=25, winSum=420
3539 12:40:22.702118 TX Vref=24, minBit 1, minWin=26, winSum=426
3540 12:40:22.705270 TX Vref=26, minBit 2, minWin=26, winSum=430
3541 12:40:22.708470 TX Vref=28, minBit 9, minWin=26, winSum=435
3542 12:40:22.711713 TX Vref=30, minBit 1, minWin=27, winSum=438
3543 12:40:22.718439 TX Vref=32, minBit 9, minWin=26, winSum=437
3544 12:40:22.721804 [TxChooseVref] Worse bit 1, Min win 27, Win sum 438, Final Vref 30
3545 12:40:22.721893
3546 12:40:22.725196 Final TX Range 1 Vref 30
3547 12:40:22.725280
3548 12:40:22.725365 ==
3549 12:40:22.728036 Dram Type= 6, Freq= 0, CH_1, rank 1
3550 12:40:22.731360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3551 12:40:22.734713 ==
3552 12:40:22.734786
3553 12:40:22.734846
3554 12:40:22.734903 TX Vref Scan disable
3555 12:40:22.738061 == TX Byte 0 ==
3556 12:40:22.741439 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3557 12:40:22.747987 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3558 12:40:22.748069 == TX Byte 1 ==
3559 12:40:22.751538 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3560 12:40:22.757772 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3561 12:40:22.757854
3562 12:40:22.757916 [DATLAT]
3563 12:40:22.757975 Freq=1200, CH1 RK1
3564 12:40:22.758031
3565 12:40:22.761032 DATLAT Default: 0xd
3566 12:40:22.761112 0, 0xFFFF, sum = 0
3567 12:40:22.764513 1, 0xFFFF, sum = 0
3568 12:40:22.764594 2, 0xFFFF, sum = 0
3569 12:40:22.768170 3, 0xFFFF, sum = 0
3570 12:40:22.771439 4, 0xFFFF, sum = 0
3571 12:40:22.771520 5, 0xFFFF, sum = 0
3572 12:40:22.774789 6, 0xFFFF, sum = 0
3573 12:40:22.774871 7, 0xFFFF, sum = 0
3574 12:40:22.777871 8, 0xFFFF, sum = 0
3575 12:40:22.777957 9, 0xFFFF, sum = 0
3576 12:40:22.781748 10, 0xFFFF, sum = 0
3577 12:40:22.781833 11, 0xFFFF, sum = 0
3578 12:40:22.784576 12, 0x0, sum = 1
3579 12:40:22.784664 13, 0x0, sum = 2
3580 12:40:22.788066 14, 0x0, sum = 3
3581 12:40:22.788149 15, 0x0, sum = 4
3582 12:40:22.788213 best_step = 13
3583 12:40:22.791424
3584 12:40:22.791504 ==
3585 12:40:22.794773 Dram Type= 6, Freq= 0, CH_1, rank 1
3586 12:40:22.798228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3587 12:40:22.798310 ==
3588 12:40:22.798391 RX Vref Scan: 0
3589 12:40:22.798465
3590 12:40:22.800984 RX Vref 0 -> 0, step: 1
3591 12:40:22.801062
3592 12:40:22.804308 RX Delay -5 -> 252, step: 4
3593 12:40:22.807651 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3594 12:40:22.814933 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3595 12:40:22.818219 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3596 12:40:22.821528 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3597 12:40:22.824219 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3598 12:40:22.827934 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3599 12:40:22.834534 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3600 12:40:22.837868 iDelay=195, Bit 7, Center 118 (55 ~ 182) 128
3601 12:40:22.841357 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3602 12:40:22.844650 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3603 12:40:22.847977 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3604 12:40:22.854962 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3605 12:40:22.857778 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3606 12:40:22.861416 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3607 12:40:22.864516 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3608 12:40:22.867757 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3609 12:40:22.867836 ==
3610 12:40:22.871198 Dram Type= 6, Freq= 0, CH_1, rank 1
3611 12:40:22.877953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3612 12:40:22.878038 ==
3613 12:40:22.878101 DQS Delay:
3614 12:40:22.881037 DQS0 = 0, DQS1 = 0
3615 12:40:22.881116 DQM Delay:
3616 12:40:22.884262 DQM0 = 120, DQM1 = 118
3617 12:40:22.884380 DQ Delay:
3618 12:40:22.887740 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3619 12:40:22.891183 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =118
3620 12:40:22.894569 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3621 12:40:22.897547 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3622 12:40:22.897626
3623 12:40:22.897688
3624 12:40:22.907828 [DQSOSCAuto] RK1, (LSB)MR18= 0x12ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3625 12:40:22.907914 CH1 RK1: MR19=403, MR18=12EE
3626 12:40:22.914357 CH1_RK1: MR19=0x403, MR18=0x12EE, DQSOSC=403, MR23=63, INC=40, DEC=26
3627 12:40:22.917745 [RxdqsGatingPostProcess] freq 1200
3628 12:40:22.924263 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3629 12:40:22.927671 best DQS0 dly(2T, 0.5T) = (0, 11)
3630 12:40:22.931080 best DQS1 dly(2T, 0.5T) = (0, 11)
3631 12:40:22.934555 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3632 12:40:22.937990 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3633 12:40:22.941274 best DQS0 dly(2T, 0.5T) = (0, 11)
3634 12:40:22.944031 best DQS1 dly(2T, 0.5T) = (0, 11)
3635 12:40:22.947411 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3636 12:40:22.950856 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3637 12:40:22.950936 Pre-setting of DQS Precalculation
3638 12:40:22.957650 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3639 12:40:22.963914 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3640 12:40:22.970792 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3641 12:40:22.970873
3642 12:40:22.970936
3643 12:40:22.973842 [Calibration Summary] 2400 Mbps
3644 12:40:22.977708 CH 0, Rank 0
3645 12:40:22.977787 SW Impedance : PASS
3646 12:40:22.980492 DUTY Scan : NO K
3647 12:40:22.983900 ZQ Calibration : PASS
3648 12:40:22.984022 Jitter Meter : NO K
3649 12:40:22.987258 CBT Training : PASS
3650 12:40:22.990662 Write leveling : PASS
3651 12:40:22.990741 RX DQS gating : PASS
3652 12:40:22.993941 RX DQ/DQS(RDDQC) : PASS
3653 12:40:22.994033 TX DQ/DQS : PASS
3654 12:40:22.997291 RX DATLAT : PASS
3655 12:40:23.001017 RX DQ/DQS(Engine): PASS
3656 12:40:23.001096 TX OE : NO K
3657 12:40:23.003744 All Pass.
3658 12:40:23.003823
3659 12:40:23.003885 CH 0, Rank 1
3660 12:40:23.007629 SW Impedance : PASS
3661 12:40:23.007708 DUTY Scan : NO K
3662 12:40:23.010739 ZQ Calibration : PASS
3663 12:40:23.013884 Jitter Meter : NO K
3664 12:40:23.013963 CBT Training : PASS
3665 12:40:23.017349 Write leveling : PASS
3666 12:40:23.020414 RX DQS gating : PASS
3667 12:40:23.020493 RX DQ/DQS(RDDQC) : PASS
3668 12:40:23.023969 TX DQ/DQS : PASS
3669 12:40:23.027550 RX DATLAT : PASS
3670 12:40:23.027629 RX DQ/DQS(Engine): PASS
3671 12:40:23.030435 TX OE : NO K
3672 12:40:23.030514 All Pass.
3673 12:40:23.030576
3674 12:40:23.033879 CH 1, Rank 0
3675 12:40:23.033972 SW Impedance : PASS
3676 12:40:23.037272 DUTY Scan : NO K
3677 12:40:23.037351 ZQ Calibration : PASS
3678 12:40:23.040526 Jitter Meter : NO K
3679 12:40:23.044173 CBT Training : PASS
3680 12:40:23.044271 Write leveling : PASS
3681 12:40:23.047268 RX DQS gating : PASS
3682 12:40:23.050676 RX DQ/DQS(RDDQC) : PASS
3683 12:40:23.050753 TX DQ/DQS : PASS
3684 12:40:23.054129 RX DATLAT : PASS
3685 12:40:23.056946 RX DQ/DQS(Engine): PASS
3686 12:40:23.057025 TX OE : NO K
3687 12:40:23.060391 All Pass.
3688 12:40:23.060470
3689 12:40:23.060561 CH 1, Rank 1
3690 12:40:23.063748 SW Impedance : PASS
3691 12:40:23.063831 DUTY Scan : NO K
3692 12:40:23.067155 ZQ Calibration : PASS
3693 12:40:23.070625 Jitter Meter : NO K
3694 12:40:23.070704 CBT Training : PASS
3695 12:40:23.074087 Write leveling : PASS
3696 12:40:23.077385 RX DQS gating : PASS
3697 12:40:23.077464 RX DQ/DQS(RDDQC) : PASS
3698 12:40:23.080637 TX DQ/DQS : PASS
3699 12:40:23.080759 RX DATLAT : PASS
3700 12:40:23.083902 RX DQ/DQS(Engine): PASS
3701 12:40:23.087064 TX OE : NO K
3702 12:40:23.087158 All Pass.
3703 12:40:23.087249
3704 12:40:23.090638 DramC Write-DBI off
3705 12:40:23.090721 PER_BANK_REFRESH: Hybrid Mode
3706 12:40:23.094026 TX_TRACKING: ON
3707 12:40:23.104158 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3708 12:40:23.107270 [FAST_K] Save calibration result to emmc
3709 12:40:23.110615 dramc_set_vcore_voltage set vcore to 650000
3710 12:40:23.110696 Read voltage for 600, 5
3711 12:40:23.114114 Vio18 = 0
3712 12:40:23.114194 Vcore = 650000
3713 12:40:23.114258 Vdram = 0
3714 12:40:23.116831 Vddq = 0
3715 12:40:23.116964 Vmddr = 0
3716 12:40:23.120243 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3717 12:40:23.127086 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3718 12:40:23.130219 MEM_TYPE=3, freq_sel=19
3719 12:40:23.134060 sv_algorithm_assistance_LP4_1600
3720 12:40:23.137123 ============ PULL DRAM RESETB DOWN ============
3721 12:40:23.140561 ========== PULL DRAM RESETB DOWN end =========
3722 12:40:23.147495 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3723 12:40:23.150876 ===================================
3724 12:40:23.150959 LPDDR4 DRAM CONFIGURATION
3725 12:40:23.154080 ===================================
3726 12:40:23.157251 EX_ROW_EN[0] = 0x0
3727 12:40:23.157332 EX_ROW_EN[1] = 0x0
3728 12:40:23.160250 LP4Y_EN = 0x0
3729 12:40:23.160357 WORK_FSP = 0x0
3730 12:40:23.163959 WL = 0x2
3731 12:40:23.164040 RL = 0x2
3732 12:40:23.167230 BL = 0x2
3733 12:40:23.170561 RPST = 0x0
3734 12:40:23.170672 RD_PRE = 0x0
3735 12:40:23.173610 WR_PRE = 0x1
3736 12:40:23.173760 WR_PST = 0x0
3737 12:40:23.176874 DBI_WR = 0x0
3738 12:40:23.176956 DBI_RD = 0x0
3739 12:40:23.180930 OTF = 0x1
3740 12:40:23.183658 ===================================
3741 12:40:23.186920 ===================================
3742 12:40:23.187020 ANA top config
3743 12:40:23.190786 ===================================
3744 12:40:23.193505 DLL_ASYNC_EN = 0
3745 12:40:23.197041 ALL_SLAVE_EN = 1
3746 12:40:23.197122 NEW_RANK_MODE = 1
3747 12:40:23.200414 DLL_IDLE_MODE = 1
3748 12:40:23.203871 LP45_APHY_COMB_EN = 1
3749 12:40:23.207225 TX_ODT_DIS = 1
3750 12:40:23.207308 NEW_8X_MODE = 1
3751 12:40:23.210630 ===================================
3752 12:40:23.214099 ===================================
3753 12:40:23.217029 data_rate = 1200
3754 12:40:23.220215 CKR = 1
3755 12:40:23.223723 DQ_P2S_RATIO = 8
3756 12:40:23.227181 ===================================
3757 12:40:23.230497 CA_P2S_RATIO = 8
3758 12:40:23.233973 DQ_CA_OPEN = 0
3759 12:40:23.234051 DQ_SEMI_OPEN = 0
3760 12:40:23.237197 CA_SEMI_OPEN = 0
3761 12:40:23.240512 CA_FULL_RATE = 0
3762 12:40:23.243628 DQ_CKDIV4_EN = 1
3763 12:40:23.247024 CA_CKDIV4_EN = 1
3764 12:40:23.250330 CA_PREDIV_EN = 0
3765 12:40:23.250436 PH8_DLY = 0
3766 12:40:23.253658 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3767 12:40:23.257006 DQ_AAMCK_DIV = 4
3768 12:40:23.260444 CA_AAMCK_DIV = 4
3769 12:40:23.263835 CA_ADMCK_DIV = 4
3770 12:40:23.267365 DQ_TRACK_CA_EN = 0
3771 12:40:23.267454 CA_PICK = 600
3772 12:40:23.270104 CA_MCKIO = 600
3773 12:40:23.273507 MCKIO_SEMI = 0
3774 12:40:23.277397 PLL_FREQ = 2288
3775 12:40:23.280577 DQ_UI_PI_RATIO = 32
3776 12:40:23.283553 CA_UI_PI_RATIO = 0
3777 12:40:23.287089 ===================================
3778 12:40:23.290492 ===================================
3779 12:40:23.290579 memory_type:LPDDR4
3780 12:40:23.293921 GP_NUM : 10
3781 12:40:23.297093 SRAM_EN : 1
3782 12:40:23.297177 MD32_EN : 0
3783 12:40:23.300538 ===================================
3784 12:40:23.303837 [ANA_INIT] >>>>>>>>>>>>>>
3785 12:40:23.306771 <<<<<< [CONFIGURE PHASE]: ANA_TX
3786 12:40:23.310421 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3787 12:40:23.313946 ===================================
3788 12:40:23.316866 data_rate = 1200,PCW = 0X5800
3789 12:40:23.320439 ===================================
3790 12:40:23.323577 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3791 12:40:23.326620 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3792 12:40:23.333560 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3793 12:40:23.336976 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3794 12:40:23.339924 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3795 12:40:23.343245 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3796 12:40:23.346602 [ANA_INIT] flow start
3797 12:40:23.350047 [ANA_INIT] PLL >>>>>>>>
3798 12:40:23.350157 [ANA_INIT] PLL <<<<<<<<
3799 12:40:23.353211 [ANA_INIT] MIDPI >>>>>>>>
3800 12:40:23.356411 [ANA_INIT] MIDPI <<<<<<<<
3801 12:40:23.360145 [ANA_INIT] DLL >>>>>>>>
3802 12:40:23.360268 [ANA_INIT] flow end
3803 12:40:23.363197 ============ LP4 DIFF to SE enter ============
3804 12:40:23.370150 ============ LP4 DIFF to SE exit ============
3805 12:40:23.370252 [ANA_INIT] <<<<<<<<<<<<<
3806 12:40:23.373425 [Flow] Enable top DCM control >>>>>
3807 12:40:23.376936 [Flow] Enable top DCM control <<<<<
3808 12:40:23.380245 Enable DLL master slave shuffle
3809 12:40:23.386523 ==============================================================
3810 12:40:23.386641 Gating Mode config
3811 12:40:23.393526 ==============================================================
3812 12:40:23.396192 Config description:
3813 12:40:23.406772 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3814 12:40:23.412938 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3815 12:40:23.416587 SELPH_MODE 0: By rank 1: By Phase
3816 12:40:23.423058 ==============================================================
3817 12:40:23.426590 GAT_TRACK_EN = 1
3818 12:40:23.426712 RX_GATING_MODE = 2
3819 12:40:23.429817 RX_GATING_TRACK_MODE = 2
3820 12:40:23.433414 SELPH_MODE = 1
3821 12:40:23.436562 PICG_EARLY_EN = 1
3822 12:40:23.439946 VALID_LAT_VALUE = 1
3823 12:40:23.446811 ==============================================================
3824 12:40:23.449555 Enter into Gating configuration >>>>
3825 12:40:23.453063 Exit from Gating configuration <<<<
3826 12:40:23.456554 Enter into DVFS_PRE_config >>>>>
3827 12:40:23.466617 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3828 12:40:23.469863 Exit from DVFS_PRE_config <<<<<
3829 12:40:23.472888 Enter into PICG configuration >>>>
3830 12:40:23.476563 Exit from PICG configuration <<<<
3831 12:40:23.479208 [RX_INPUT] configuration >>>>>
3832 12:40:23.482742 [RX_INPUT] configuration <<<<<
3833 12:40:23.486227 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3834 12:40:23.492934 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3835 12:40:23.499384 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3836 12:40:23.502821 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3837 12:40:23.509581 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3838 12:40:23.516311 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3839 12:40:23.519780 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3840 12:40:23.523211 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3841 12:40:23.529548 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3842 12:40:23.532703 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3843 12:40:23.536644 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3844 12:40:23.543068 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3845 12:40:23.546069 ===================================
3846 12:40:23.546175 LPDDR4 DRAM CONFIGURATION
3847 12:40:23.549687 ===================================
3848 12:40:23.552448 EX_ROW_EN[0] = 0x0
3849 12:40:23.555829 EX_ROW_EN[1] = 0x0
3850 12:40:23.555944 LP4Y_EN = 0x0
3851 12:40:23.559219 WORK_FSP = 0x0
3852 12:40:23.559305 WL = 0x2
3853 12:40:23.562607 RL = 0x2
3854 12:40:23.562693 BL = 0x2
3855 12:40:23.565997 RPST = 0x0
3856 12:40:23.566083 RD_PRE = 0x0
3857 12:40:23.569429 WR_PRE = 0x1
3858 12:40:23.569541 WR_PST = 0x0
3859 12:40:23.572742 DBI_WR = 0x0
3860 12:40:23.572829 DBI_RD = 0x0
3861 12:40:23.576249 OTF = 0x1
3862 12:40:23.578960 ===================================
3863 12:40:23.582293 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3864 12:40:23.586066 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3865 12:40:23.592223 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3866 12:40:23.595653 ===================================
3867 12:40:23.595773 LPDDR4 DRAM CONFIGURATION
3868 12:40:23.599216 ===================================
3869 12:40:23.602325 EX_ROW_EN[0] = 0x10
3870 12:40:23.602419 EX_ROW_EN[1] = 0x0
3871 12:40:23.605843 LP4Y_EN = 0x0
3872 12:40:23.605929 WORK_FSP = 0x0
3873 12:40:23.609217 WL = 0x2
3874 12:40:23.612588 RL = 0x2
3875 12:40:23.612679 BL = 0x2
3876 12:40:23.616042 RPST = 0x0
3877 12:40:23.616158 RD_PRE = 0x0
3878 12:40:23.619432 WR_PRE = 0x1
3879 12:40:23.619515 WR_PST = 0x0
3880 12:40:23.622879 DBI_WR = 0x0
3881 12:40:23.622962 DBI_RD = 0x0
3882 12:40:23.625677 OTF = 0x1
3883 12:40:23.628926 ===================================
3884 12:40:23.632361 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3885 12:40:23.637638 nWR fixed to 30
3886 12:40:23.640984 [ModeRegInit_LP4] CH0 RK0
3887 12:40:23.641097 [ModeRegInit_LP4] CH0 RK1
3888 12:40:23.644879 [ModeRegInit_LP4] CH1 RK0
3889 12:40:23.647950 [ModeRegInit_LP4] CH1 RK1
3890 12:40:23.648063 match AC timing 17
3891 12:40:23.654977 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3892 12:40:23.658145 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3893 12:40:23.660847 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3894 12:40:23.668040 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3895 12:40:23.671317 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3896 12:40:23.671472 ==
3897 12:40:23.674579 Dram Type= 6, Freq= 0, CH_0, rank 0
3898 12:40:23.677732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3899 12:40:23.677842 ==
3900 12:40:23.684610 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3901 12:40:23.690782 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3902 12:40:23.694607 [CA 0] Center 35 (5~66) winsize 62
3903 12:40:23.697839 [CA 1] Center 35 (5~66) winsize 62
3904 12:40:23.701007 [CA 2] Center 33 (3~64) winsize 62
3905 12:40:23.704034 [CA 3] Center 33 (2~64) winsize 63
3906 12:40:23.707568 [CA 4] Center 33 (2~64) winsize 63
3907 12:40:23.710581 [CA 5] Center 32 (2~63) winsize 62
3908 12:40:23.710700
3909 12:40:23.713891 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3910 12:40:23.714003
3911 12:40:23.717310 [CATrainingPosCal] consider 1 rank data
3912 12:40:23.720731 u2DelayCellTimex100 = 270/100 ps
3913 12:40:23.724076 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3914 12:40:23.727442 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3915 12:40:23.730932 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3916 12:40:23.734342 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3917 12:40:23.737554 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3918 12:40:23.744246 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3919 12:40:23.744406
3920 12:40:23.747581 CA PerBit enable=1, Macro0, CA PI delay=32
3921 12:40:23.747690
3922 12:40:23.750952 [CBTSetCACLKResult] CA Dly = 32
3923 12:40:23.751061 CS Dly: 4 (0~35)
3924 12:40:23.751187 ==
3925 12:40:23.754117 Dram Type= 6, Freq= 0, CH_0, rank 1
3926 12:40:23.757534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3927 12:40:23.760270 ==
3928 12:40:23.763808 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3929 12:40:23.770701 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3930 12:40:23.773904 [CA 0] Center 35 (5~66) winsize 62
3931 12:40:23.777128 [CA 1] Center 35 (5~66) winsize 62
3932 12:40:23.780591 [CA 2] Center 34 (3~65) winsize 63
3933 12:40:23.784058 [CA 3] Center 33 (3~64) winsize 62
3934 12:40:23.787278 [CA 4] Center 32 (2~63) winsize 62
3935 12:40:23.790715 [CA 5] Center 32 (2~63) winsize 62
3936 12:40:23.790835
3937 12:40:23.793874 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3938 12:40:23.793985
3939 12:40:23.797313 [CATrainingPosCal] consider 2 rank data
3940 12:40:23.800597 u2DelayCellTimex100 = 270/100 ps
3941 12:40:23.803938 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3942 12:40:23.807278 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3943 12:40:23.810727 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3944 12:40:23.814089 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3945 12:40:23.817251 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3946 12:40:23.823656 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3947 12:40:23.823830
3948 12:40:23.826969 CA PerBit enable=1, Macro0, CA PI delay=32
3949 12:40:23.827091
3950 12:40:23.830695 [CBTSetCACLKResult] CA Dly = 32
3951 12:40:23.830812 CS Dly: 4 (0~35)
3952 12:40:23.830909
3953 12:40:23.834062 ----->DramcWriteLeveling(PI) begin...
3954 12:40:23.834174 ==
3955 12:40:23.837458 Dram Type= 6, Freq= 0, CH_0, rank 0
3956 12:40:23.844106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3957 12:40:23.844240 ==
3958 12:40:23.846838 Write leveling (Byte 0): 32 => 32
3959 12:40:23.846948 Write leveling (Byte 1): 31 => 31
3960 12:40:23.850847 DramcWriteLeveling(PI) end<-----
3961 12:40:23.850959
3962 12:40:23.853515 ==
3963 12:40:23.853625 Dram Type= 6, Freq= 0, CH_0, rank 0
3964 12:40:23.860554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3965 12:40:23.860702 ==
3966 12:40:23.863994 [Gating] SW mode calibration
3967 12:40:23.870105 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3968 12:40:23.873561 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3969 12:40:23.880430 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3970 12:40:23.883875 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3971 12:40:23.887266 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3972 12:40:23.894005 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
3973 12:40:23.897493 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
3974 12:40:23.900519 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 12:40:23.906686 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 12:40:23.910548 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 12:40:23.913189 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 12:40:23.919890 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 12:40:23.923278 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 12:40:23.926722 0 10 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
3981 12:40:23.930206 0 10 16 | B1->B0 | 3434 4646 | 0 0 | (1 1) (0 0)
3982 12:40:23.936623 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 12:40:23.940416 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 12:40:23.943445 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 12:40:23.950002 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 12:40:23.953674 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 12:40:23.956545 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 12:40:23.963567 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3989 12:40:23.966518 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3990 12:40:23.970378 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 12:40:23.976638 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 12:40:23.980229 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 12:40:23.983499 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 12:40:23.990323 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 12:40:23.993683 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 12:40:23.996948 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 12:40:24.003698 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 12:40:24.007142 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 12:40:24.010666 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 12:40:24.016656 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 12:40:24.020244 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 12:40:24.023393 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 12:40:24.027159 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 12:40:24.033206 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4005 12:40:24.036627 Total UI for P1: 0, mck2ui 16
4006 12:40:24.040021 best dqsien dly found for B0: ( 0, 13, 10)
4007 12:40:24.043617 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 12:40:24.046872 Total UI for P1: 0, mck2ui 16
4009 12:40:24.050200 best dqsien dly found for B1: ( 0, 13, 14)
4010 12:40:24.053310 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4011 12:40:24.056547 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4012 12:40:24.056678
4013 12:40:24.059792 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4014 12:40:24.066950 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4015 12:40:24.067107 [Gating] SW calibration Done
4016 12:40:24.067209 ==
4017 12:40:24.070234 Dram Type= 6, Freq= 0, CH_0, rank 0
4018 12:40:24.076824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4019 12:40:24.076956 ==
4020 12:40:24.077060 RX Vref Scan: 0
4021 12:40:24.077159
4022 12:40:24.080205 RX Vref 0 -> 0, step: 1
4023 12:40:24.080345
4024 12:40:24.083177 RX Delay -230 -> 252, step: 16
4025 12:40:24.086860 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4026 12:40:24.090217 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4027 12:40:24.093432 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4028 12:40:24.100007 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4029 12:40:24.103411 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4030 12:40:24.106672 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4031 12:40:24.109994 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4032 12:40:24.116207 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4033 12:40:24.119764 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4034 12:40:24.123079 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4035 12:40:24.126474 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4036 12:40:24.129820 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4037 12:40:24.136733 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4038 12:40:24.140171 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4039 12:40:24.143535 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4040 12:40:24.146336 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4041 12:40:24.149872 ==
4042 12:40:24.149969 Dram Type= 6, Freq= 0, CH_0, rank 0
4043 12:40:24.156603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4044 12:40:24.156707 ==
4045 12:40:24.156798 DQS Delay:
4046 12:40:24.159821 DQS0 = 0, DQS1 = 0
4047 12:40:24.159930 DQM Delay:
4048 12:40:24.163096 DQM0 = 51, DQM1 = 45
4049 12:40:24.163203 DQ Delay:
4050 12:40:24.166448 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4051 12:40:24.169690 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4052 12:40:24.173108 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4053 12:40:24.176540 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4054 12:40:24.176635
4055 12:40:24.176701
4056 12:40:24.176782 ==
4057 12:40:24.179969 Dram Type= 6, Freq= 0, CH_0, rank 0
4058 12:40:24.182798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4059 12:40:24.182951 ==
4060 12:40:24.183047
4061 12:40:24.183130
4062 12:40:24.186722 TX Vref Scan disable
4063 12:40:24.190083 == TX Byte 0 ==
4064 12:40:24.193011 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4065 12:40:24.196106 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4066 12:40:24.199686 == TX Byte 1 ==
4067 12:40:24.203119 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4068 12:40:24.206437 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4069 12:40:24.206539 ==
4070 12:40:24.209725 Dram Type= 6, Freq= 0, CH_0, rank 0
4071 12:40:24.212927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4072 12:40:24.216318 ==
4073 12:40:24.216419
4074 12:40:24.216488
4075 12:40:24.216550 TX Vref Scan disable
4076 12:40:24.219984 == TX Byte 0 ==
4077 12:40:24.223403 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4078 12:40:24.226984 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4079 12:40:24.230320 == TX Byte 1 ==
4080 12:40:24.233731 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4081 12:40:24.236961 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4082 12:40:24.240293
4083 12:40:24.240380 [DATLAT]
4084 12:40:24.240444 Freq=600, CH0 RK0
4085 12:40:24.240509
4086 12:40:24.243611 DATLAT Default: 0x9
4087 12:40:24.243709 0, 0xFFFF, sum = 0
4088 12:40:24.246629 1, 0xFFFF, sum = 0
4089 12:40:24.246740 2, 0xFFFF, sum = 0
4090 12:40:24.250093 3, 0xFFFF, sum = 0
4091 12:40:24.250212 4, 0xFFFF, sum = 0
4092 12:40:24.253539 5, 0xFFFF, sum = 0
4093 12:40:24.256897 6, 0xFFFF, sum = 0
4094 12:40:24.256985 7, 0xFFFF, sum = 0
4095 12:40:24.257053 8, 0x0, sum = 1
4096 12:40:24.260297 9, 0x0, sum = 2
4097 12:40:24.260386 10, 0x0, sum = 3
4098 12:40:24.263677 11, 0x0, sum = 4
4099 12:40:24.263816 best_step = 9
4100 12:40:24.263934
4101 12:40:24.264043 ==
4102 12:40:24.266955 Dram Type= 6, Freq= 0, CH_0, rank 0
4103 12:40:24.273366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4104 12:40:24.273473 ==
4105 12:40:24.273543 RX Vref Scan: 1
4106 12:40:24.273610
4107 12:40:24.276694 RX Vref 0 -> 0, step: 1
4108 12:40:24.276769
4109 12:40:24.279964 RX Delay -163 -> 252, step: 8
4110 12:40:24.280044
4111 12:40:24.283366 Set Vref, RX VrefLevel [Byte0]: 55
4112 12:40:24.286745 [Byte1]: 47
4113 12:40:24.286840
4114 12:40:24.290141 Final RX Vref Byte 0 = 55 to rank0
4115 12:40:24.293650 Final RX Vref Byte 1 = 47 to rank0
4116 12:40:24.296964 Final RX Vref Byte 0 = 55 to rank1
4117 12:40:24.300382 Final RX Vref Byte 1 = 47 to rank1==
4118 12:40:24.303134 Dram Type= 6, Freq= 0, CH_0, rank 0
4119 12:40:24.307051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4120 12:40:24.307143 ==
4121 12:40:24.309691 DQS Delay:
4122 12:40:24.309778 DQS0 = 0, DQS1 = 0
4123 12:40:24.309860 DQM Delay:
4124 12:40:24.313140 DQM0 = 53, DQM1 = 46
4125 12:40:24.313225 DQ Delay:
4126 12:40:24.316562 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4127 12:40:24.320010 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4128 12:40:24.323254 DQ8 =36, DQ9 =36, DQ10 =52, DQ11 =40
4129 12:40:24.326750 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4130 12:40:24.326843
4131 12:40:24.326908
4132 12:40:24.336174 [DQSOSCAuto] RK0, (LSB)MR18= 0x7568, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 387 ps
4133 12:40:24.339425 CH0 RK0: MR19=808, MR18=7568
4134 12:40:24.343059 CH0_RK0: MR19=0x808, MR18=0x7568, DQSOSC=387, MR23=63, INC=175, DEC=116
4135 12:40:24.343185
4136 12:40:24.346150 ----->DramcWriteLeveling(PI) begin...
4137 12:40:24.349489 ==
4138 12:40:24.353245 Dram Type= 6, Freq= 0, CH_0, rank 1
4139 12:40:24.356385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 12:40:24.356480 ==
4141 12:40:24.359624 Write leveling (Byte 0): 34 => 34
4142 12:40:24.363056 Write leveling (Byte 1): 31 => 31
4143 12:40:24.366513 DramcWriteLeveling(PI) end<-----
4144 12:40:24.366609
4145 12:40:24.366678 ==
4146 12:40:24.369985 Dram Type= 6, Freq= 0, CH_0, rank 1
4147 12:40:24.373362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 12:40:24.373453 ==
4149 12:40:24.376549 [Gating] SW mode calibration
4150 12:40:24.383019 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4151 12:40:24.389601 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4152 12:40:24.393060 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4153 12:40:24.396473 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4154 12:40:24.402580 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4155 12:40:24.406020 0 9 12 | B1->B0 | 3434 3232 | 0 0 | (0 1) (0 0)
4156 12:40:24.409486 0 9 16 | B1->B0 | 2b2b 2424 | 1 0 | (1 0) (0 0)
4157 12:40:24.412731 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4158 12:40:24.419413 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4159 12:40:24.422870 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4160 12:40:24.426306 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4161 12:40:24.433020 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4162 12:40:24.436419 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 12:40:24.439769 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 12:40:24.446250 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4165 12:40:24.449342 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4166 12:40:24.453032 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4167 12:40:24.459196 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4168 12:40:24.462915 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4169 12:40:24.466303 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4170 12:40:24.472859 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 12:40:24.476054 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4172 12:40:24.479677 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 12:40:24.486304 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 12:40:24.489429 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 12:40:24.492713 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 12:40:24.499171 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 12:40:24.502547 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 12:40:24.505963 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 12:40:24.512812 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 12:40:24.516241 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 12:40:24.519618 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 12:40:24.522880 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 12:40:24.529705 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 12:40:24.532441 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 12:40:24.536391 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 12:40:24.542519 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 12:40:24.552586 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 12:40:24.552913 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4189 12:40:24.556263 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 12:40:24.556356 Total UI for P1: 0, mck2ui 16
4191 12:40:24.562842 best dqsien dly found for B0: ( 0, 13, 16)
4192 12:40:24.562973 Total UI for P1: 0, mck2ui 16
4193 12:40:24.569054 best dqsien dly found for B1: ( 0, 13, 16)
4194 12:40:24.572396 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4195 12:40:24.575676 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4196 12:40:24.575807
4197 12:40:24.578996 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4198 12:40:24.582253 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4199 12:40:24.585953 [Gating] SW calibration Done
4200 12:40:24.586103 ==
4201 12:40:24.588941 Dram Type= 6, Freq= 0, CH_0, rank 1
4202 12:40:24.592804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4203 12:40:24.592926 ==
4204 12:40:24.595760 RX Vref Scan: 0
4205 12:40:24.595871
4206 12:40:24.595967 RX Vref 0 -> 0, step: 1
4207 12:40:24.596060
4208 12:40:24.599282 RX Delay -230 -> 252, step: 16
4209 12:40:24.606018 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4210 12:40:24.608922 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4211 12:40:24.612851 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4212 12:40:24.615417 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4213 12:40:24.618973 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4214 12:40:24.625676 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4215 12:40:24.629016 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4216 12:40:24.632389 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4217 12:40:24.635749 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4218 12:40:24.642345 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4219 12:40:24.645872 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4220 12:40:24.649150 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4221 12:40:24.652580 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4222 12:40:24.659239 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4223 12:40:24.662605 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4224 12:40:24.666056 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4225 12:40:24.666151 ==
4226 12:40:24.669390 Dram Type= 6, Freq= 0, CH_0, rank 1
4227 12:40:24.672682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4228 12:40:24.672775 ==
4229 12:40:24.675375 DQS Delay:
4230 12:40:24.675459 DQS0 = 0, DQS1 = 0
4231 12:40:24.678725 DQM Delay:
4232 12:40:24.678811 DQM0 = 51, DQM1 = 43
4233 12:40:24.678876 DQ Delay:
4234 12:40:24.682643 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4235 12:40:24.685408 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4236 12:40:24.688743 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4237 12:40:24.692639 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4238 12:40:24.692742
4239 12:40:24.692830
4240 12:40:24.692893 ==
4241 12:40:24.695924 Dram Type= 6, Freq= 0, CH_0, rank 1
4242 12:40:24.702551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4243 12:40:24.702686 ==
4244 12:40:24.702781
4245 12:40:24.702878
4246 12:40:24.702966 TX Vref Scan disable
4247 12:40:24.706014 == TX Byte 0 ==
4248 12:40:24.709389 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4249 12:40:24.716356 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4250 12:40:24.716505 == TX Byte 1 ==
4251 12:40:24.719459 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4252 12:40:24.722954 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4253 12:40:24.726306 ==
4254 12:40:24.729729 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 12:40:24.732708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 12:40:24.732829 ==
4257 12:40:24.732924
4258 12:40:24.733013
4259 12:40:24.736266 TX Vref Scan disable
4260 12:40:24.739659 == TX Byte 0 ==
4261 12:40:24.742949 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4262 12:40:24.746084 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4263 12:40:24.749424 == TX Byte 1 ==
4264 12:40:24.752932 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4265 12:40:24.756310 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4266 12:40:24.756436
4267 12:40:24.756536 [DATLAT]
4268 12:40:24.759110 Freq=600, CH0 RK1
4269 12:40:24.759221
4270 12:40:24.759317 DATLAT Default: 0x9
4271 12:40:24.762493 0, 0xFFFF, sum = 0
4272 12:40:24.765834 1, 0xFFFF, sum = 0
4273 12:40:24.765948 2, 0xFFFF, sum = 0
4274 12:40:24.769144 3, 0xFFFF, sum = 0
4275 12:40:24.769260 4, 0xFFFF, sum = 0
4276 12:40:24.772607 5, 0xFFFF, sum = 0
4277 12:40:24.772720 6, 0xFFFF, sum = 0
4278 12:40:24.776055 7, 0xFFFF, sum = 0
4279 12:40:24.776167 8, 0x0, sum = 1
4280 12:40:24.776266 9, 0x0, sum = 2
4281 12:40:24.779378 10, 0x0, sum = 3
4282 12:40:24.779489 11, 0x0, sum = 4
4283 12:40:24.782849 best_step = 9
4284 12:40:24.782976
4285 12:40:24.783074 ==
4286 12:40:24.786346 Dram Type= 6, Freq= 0, CH_0, rank 1
4287 12:40:24.789102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4288 12:40:24.789216 ==
4289 12:40:24.792441 RX Vref Scan: 0
4290 12:40:24.792552
4291 12:40:24.792647 RX Vref 0 -> 0, step: 1
4292 12:40:24.792740
4293 12:40:24.795670 RX Delay -163 -> 252, step: 8
4294 12:40:24.803128 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4295 12:40:24.806304 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4296 12:40:24.809742 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4297 12:40:24.813349 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4298 12:40:24.816869 iDelay=197, Bit 4, Center 52 (-91 ~ 196) 288
4299 12:40:24.822881 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4300 12:40:24.826311 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4301 12:40:24.829698 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4302 12:40:24.833387 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4303 12:40:24.836398 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4304 12:40:24.842901 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4305 12:40:24.846540 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4306 12:40:24.849654 iDelay=197, Bit 12, Center 48 (-91 ~ 188) 280
4307 12:40:24.853484 iDelay=197, Bit 13, Center 48 (-91 ~ 188) 280
4308 12:40:24.860005 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4309 12:40:24.863187 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4310 12:40:24.863317 ==
4311 12:40:24.866596 Dram Type= 6, Freq= 0, CH_0, rank 1
4312 12:40:24.869922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4313 12:40:24.870048 ==
4314 12:40:24.870144 DQS Delay:
4315 12:40:24.872919 DQS0 = 0, DQS1 = 0
4316 12:40:24.873027 DQM Delay:
4317 12:40:24.876936 DQM0 = 52, DQM1 = 45
4318 12:40:24.877046 DQ Delay:
4319 12:40:24.880094 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4320 12:40:24.883403 DQ4 =52, DQ5 =44, DQ6 =56, DQ7 =56
4321 12:40:24.886735 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4322 12:40:24.890134 DQ12 =48, DQ13 =48, DQ14 =56, DQ15 =52
4323 12:40:24.890255
4324 12:40:24.890350
4325 12:40:24.899868 [DQSOSCAuto] RK1, (LSB)MR18= 0x6828, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4326 12:40:24.900011 CH0 RK1: MR19=808, MR18=6828
4327 12:40:24.906550 CH0_RK1: MR19=0x808, MR18=0x6828, DQSOSC=390, MR23=63, INC=172, DEC=114
4328 12:40:24.909935 [RxdqsGatingPostProcess] freq 600
4329 12:40:24.916698 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4330 12:40:24.920078 Pre-setting of DQS Precalculation
4331 12:40:24.922856 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4332 12:40:24.922972 ==
4333 12:40:24.926394 Dram Type= 6, Freq= 0, CH_1, rank 0
4334 12:40:24.929894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4335 12:40:24.930011 ==
4336 12:40:24.936181 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4337 12:40:24.943070 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4338 12:40:24.946301 [CA 0] Center 35 (5~66) winsize 62
4339 12:40:24.949700 [CA 1] Center 36 (5~67) winsize 63
4340 12:40:24.952886 [CA 2] Center 34 (4~65) winsize 62
4341 12:40:24.956352 [CA 3] Center 34 (3~65) winsize 63
4342 12:40:24.959847 [CA 4] Center 34 (4~65) winsize 62
4343 12:40:24.963149 [CA 5] Center 34 (4~64) winsize 61
4344 12:40:24.963267
4345 12:40:24.966237 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4346 12:40:24.966352
4347 12:40:24.969592 [CATrainingPosCal] consider 1 rank data
4348 12:40:24.972930 u2DelayCellTimex100 = 270/100 ps
4349 12:40:24.976335 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4350 12:40:24.979421 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4351 12:40:24.982991 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4352 12:40:24.986351 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4353 12:40:24.992592 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4354 12:40:24.995838 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4355 12:40:24.995962
4356 12:40:24.999143 CA PerBit enable=1, Macro0, CA PI delay=34
4357 12:40:24.999258
4358 12:40:25.002541 [CBTSetCACLKResult] CA Dly = 34
4359 12:40:25.002658 CS Dly: 4 (0~35)
4360 12:40:25.002754 ==
4361 12:40:25.006246 Dram Type= 6, Freq= 0, CH_1, rank 1
4362 12:40:25.012931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4363 12:40:25.013081 ==
4364 12:40:25.016386 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4365 12:40:25.023069 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4366 12:40:25.025826 [CA 0] Center 36 (5~67) winsize 63
4367 12:40:25.029298 [CA 1] Center 36 (5~67) winsize 63
4368 12:40:25.032620 [CA 2] Center 34 (4~65) winsize 62
4369 12:40:25.036108 [CA 3] Center 34 (4~65) winsize 62
4370 12:40:25.039610 [CA 4] Center 35 (4~66) winsize 63
4371 12:40:25.042989 [CA 5] Center 34 (3~65) winsize 63
4372 12:40:25.043113
4373 12:40:25.046379 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4374 12:40:25.046496
4375 12:40:25.049842 [CATrainingPosCal] consider 2 rank data
4376 12:40:25.052704 u2DelayCellTimex100 = 270/100 ps
4377 12:40:25.056074 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4378 12:40:25.059436 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4379 12:40:25.062755 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4380 12:40:25.066050 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4381 12:40:25.072798 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4382 12:40:25.075957 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4383 12:40:25.076082
4384 12:40:25.079320 CA PerBit enable=1, Macro0, CA PI delay=34
4385 12:40:25.079434
4386 12:40:25.082677 [CBTSetCACLKResult] CA Dly = 34
4387 12:40:25.082794 CS Dly: 5 (0~37)
4388 12:40:25.082887
4389 12:40:25.086094 ----->DramcWriteLeveling(PI) begin...
4390 12:40:25.086247 ==
4391 12:40:25.089359 Dram Type= 6, Freq= 0, CH_1, rank 0
4392 12:40:25.096236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4393 12:40:25.096397 ==
4394 12:40:25.099650 Write leveling (Byte 0): 31 => 31
4395 12:40:25.102463 Write leveling (Byte 1): 30 => 30
4396 12:40:25.102581 DramcWriteLeveling(PI) end<-----
4397 12:40:25.102676
4398 12:40:25.105949 ==
4399 12:40:25.106055 Dram Type= 6, Freq= 0, CH_1, rank 0
4400 12:40:25.112647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 12:40:25.112770 ==
4402 12:40:25.115792 [Gating] SW mode calibration
4403 12:40:25.122845 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4404 12:40:25.126111 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4405 12:40:25.132597 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4406 12:40:25.136040 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4407 12:40:25.139389 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4408 12:40:25.146317 0 9 12 | B1->B0 | 2f2f 2e2e | 1 1 | (1 0) (0 0)
4409 12:40:25.149478 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 12:40:25.152633 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 12:40:25.158863 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4412 12:40:25.162960 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 12:40:25.166206 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 12:40:25.169455 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 12:40:25.176314 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 12:40:25.179029 0 10 12 | B1->B0 | 3535 3f3f | 0 0 | (0 0) (0 0)
4417 12:40:25.182828 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 12:40:25.189395 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 12:40:25.192161 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 12:40:25.195598 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 12:40:25.202350 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 12:40:25.205912 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 12:40:25.209333 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 12:40:25.215621 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4425 12:40:25.219086 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 12:40:25.222577 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 12:40:25.229394 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 12:40:25.232157 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 12:40:25.235696 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 12:40:25.242471 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 12:40:25.245530 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 12:40:25.248773 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 12:40:25.255693 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 12:40:25.259487 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 12:40:25.262617 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 12:40:25.265605 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 12:40:25.272588 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 12:40:25.275996 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 12:40:25.279422 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4440 12:40:25.286216 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4441 12:40:25.289562 Total UI for P1: 0, mck2ui 16
4442 12:40:25.292424 best dqsien dly found for B0: ( 0, 13, 8)
4443 12:40:25.295821 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 12:40:25.299302 Total UI for P1: 0, mck2ui 16
4445 12:40:25.302470 best dqsien dly found for B1: ( 0, 13, 12)
4446 12:40:25.306122 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4447 12:40:25.308863 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4448 12:40:25.308974
4449 12:40:25.312299 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4450 12:40:25.315799 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4451 12:40:25.319200 [Gating] SW calibration Done
4452 12:40:25.319308 ==
4453 12:40:25.322683 Dram Type= 6, Freq= 0, CH_1, rank 0
4454 12:40:25.328862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4455 12:40:25.328996 ==
4456 12:40:25.329067 RX Vref Scan: 0
4457 12:40:25.329128
4458 12:40:25.332343 RX Vref 0 -> 0, step: 1
4459 12:40:25.332447
4460 12:40:25.335822 RX Delay -230 -> 252, step: 16
4461 12:40:25.339206 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4462 12:40:25.341972 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4463 12:40:25.345456 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4464 12:40:25.352401 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4465 12:40:25.355858 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4466 12:40:25.359142 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4467 12:40:25.361911 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4468 12:40:25.365917 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4469 12:40:25.372641 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4470 12:40:25.375688 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4471 12:40:25.378734 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4472 12:40:25.382458 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4473 12:40:25.388948 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4474 12:40:25.392166 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4475 12:40:25.395634 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4476 12:40:25.398975 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4477 12:40:25.399127 ==
4478 12:40:25.402232 Dram Type= 6, Freq= 0, CH_1, rank 0
4479 12:40:25.408648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4480 12:40:25.408771 ==
4481 12:40:25.408866 DQS Delay:
4482 12:40:25.412307 DQS0 = 0, DQS1 = 0
4483 12:40:25.412414 DQM Delay:
4484 12:40:25.412497 DQM0 = 48, DQM1 = 46
4485 12:40:25.415393 DQ Delay:
4486 12:40:25.418578 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4487 12:40:25.422056 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =41
4488 12:40:25.425152 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4489 12:40:25.428620 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4490 12:40:25.428721
4491 12:40:25.428783
4492 12:40:25.428839 ==
4493 12:40:25.431703 Dram Type= 6, Freq= 0, CH_1, rank 0
4494 12:40:25.435424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4495 12:40:25.435540 ==
4496 12:40:25.435607
4497 12:40:25.435666
4498 12:40:25.438880 TX Vref Scan disable
4499 12:40:25.442454 == TX Byte 0 ==
4500 12:40:25.445860 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4501 12:40:25.448617 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4502 12:40:25.452138 == TX Byte 1 ==
4503 12:40:25.455790 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4504 12:40:25.459129 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4505 12:40:25.459243 ==
4506 12:40:25.462523 Dram Type= 6, Freq= 0, CH_1, rank 0
4507 12:40:25.465411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4508 12:40:25.465520 ==
4509 12:40:25.468715
4510 12:40:25.468814
4511 12:40:25.468903 TX Vref Scan disable
4512 12:40:25.472210 == TX Byte 0 ==
4513 12:40:25.475737 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4514 12:40:25.482485 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4515 12:40:25.482623 == TX Byte 1 ==
4516 12:40:25.485689 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4517 12:40:25.492296 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4518 12:40:25.492430
4519 12:40:25.492524 [DATLAT]
4520 12:40:25.492607 Freq=600, CH1 RK0
4521 12:40:25.492687
4522 12:40:25.495325 DATLAT Default: 0x9
4523 12:40:25.495428 0, 0xFFFF, sum = 0
4524 12:40:25.498975 1, 0xFFFF, sum = 0
4525 12:40:25.502256 2, 0xFFFF, sum = 0
4526 12:40:25.502373 3, 0xFFFF, sum = 0
4527 12:40:25.505432 4, 0xFFFF, sum = 0
4528 12:40:25.505535 5, 0xFFFF, sum = 0
4529 12:40:25.508866 6, 0xFFFF, sum = 0
4530 12:40:25.508967 7, 0xFFFF, sum = 0
4531 12:40:25.512400 8, 0x0, sum = 1
4532 12:40:25.512503 9, 0x0, sum = 2
4533 12:40:25.512593 10, 0x0, sum = 3
4534 12:40:25.515047 11, 0x0, sum = 4
4535 12:40:25.515137 best_step = 9
4536 12:40:25.515224
4537 12:40:25.515306 ==
4538 12:40:25.518501 Dram Type= 6, Freq= 0, CH_1, rank 0
4539 12:40:25.525245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4540 12:40:25.525379 ==
4541 12:40:25.525445 RX Vref Scan: 1
4542 12:40:25.525504
4543 12:40:25.528437 RX Vref 0 -> 0, step: 1
4544 12:40:25.528518
4545 12:40:25.531597 RX Delay -163 -> 252, step: 8
4546 12:40:25.531687
4547 12:40:25.535000 Set Vref, RX VrefLevel [Byte0]: 52
4548 12:40:25.538804 [Byte1]: 54
4549 12:40:25.538922
4550 12:40:25.541809 Final RX Vref Byte 0 = 52 to rank0
4551 12:40:25.544951 Final RX Vref Byte 1 = 54 to rank0
4552 12:40:25.548404 Final RX Vref Byte 0 = 52 to rank1
4553 12:40:25.551661 Final RX Vref Byte 1 = 54 to rank1==
4554 12:40:25.555502 Dram Type= 6, Freq= 0, CH_1, rank 0
4555 12:40:25.558259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4556 12:40:25.558395 ==
4557 12:40:25.561657 DQS Delay:
4558 12:40:25.561755 DQS0 = 0, DQS1 = 0
4559 12:40:25.565141 DQM Delay:
4560 12:40:25.565244 DQM0 = 48, DQM1 = 45
4561 12:40:25.565307 DQ Delay:
4562 12:40:25.568550 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4563 12:40:25.571847 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4564 12:40:25.575340 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4565 12:40:25.578834 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4566 12:40:25.578976
4567 12:40:25.579058
4568 12:40:25.588528 [DQSOSCAuto] RK0, (LSB)MR18= 0x476c, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4569 12:40:25.591936 CH1 RK0: MR19=808, MR18=476C
4570 12:40:25.595228 CH1_RK0: MR19=0x808, MR18=0x476C, DQSOSC=389, MR23=63, INC=173, DEC=115
4571 12:40:25.598576
4572 12:40:25.601822 ----->DramcWriteLeveling(PI) begin...
4573 12:40:25.601946 ==
4574 12:40:25.605057 Dram Type= 6, Freq= 0, CH_1, rank 1
4575 12:40:25.608080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 12:40:25.608185 ==
4577 12:40:25.611482 Write leveling (Byte 0): 29 => 29
4578 12:40:25.614702 Write leveling (Byte 1): 33 => 33
4579 12:40:25.618417 DramcWriteLeveling(PI) end<-----
4580 12:40:25.618563
4581 12:40:25.618655 ==
4582 12:40:25.621863 Dram Type= 6, Freq= 0, CH_1, rank 1
4583 12:40:25.625180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 12:40:25.625286 ==
4585 12:40:25.627987 [Gating] SW mode calibration
4586 12:40:25.634903 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4587 12:40:25.641747 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4588 12:40:25.645207 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4589 12:40:25.648643 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4590 12:40:25.654638 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4591 12:40:25.658094 0 9 12 | B1->B0 | 2e2e 2e2e | 1 1 | (1 0) (1 0)
4592 12:40:25.661236 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4593 12:40:25.668214 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4594 12:40:25.671533 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4595 12:40:25.674730 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4596 12:40:25.680962 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4597 12:40:25.684578 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 12:40:25.687938 0 10 8 | B1->B0 | 2727 2424 | 1 1 | (0 0) (0 0)
4599 12:40:25.694213 0 10 12 | B1->B0 | 3939 3737 | 0 0 | (0 0) (0 0)
4600 12:40:25.697549 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4601 12:40:25.700924 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4602 12:40:25.707989 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4603 12:40:25.710854 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4604 12:40:25.714563 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 12:40:25.717978 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 12:40:25.724171 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 12:40:25.727714 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4608 12:40:25.730949 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 12:40:25.737903 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 12:40:25.740665 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 12:40:25.743970 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 12:40:25.750542 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 12:40:25.754082 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 12:40:25.757479 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 12:40:25.764193 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 12:40:25.767542 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 12:40:25.770823 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 12:40:25.777528 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 12:40:25.780947 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 12:40:25.784177 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 12:40:25.791049 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 12:40:25.794463 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4623 12:40:25.797799 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 12:40:25.801069 Total UI for P1: 0, mck2ui 16
4625 12:40:25.804214 best dqsien dly found for B0: ( 0, 13, 10)
4626 12:40:25.807137 Total UI for P1: 0, mck2ui 16
4627 12:40:25.810747 best dqsien dly found for B1: ( 0, 13, 8)
4628 12:40:25.814149 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4629 12:40:25.817565 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4630 12:40:25.817685
4631 12:40:25.823687 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4632 12:40:25.827007 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4633 12:40:25.827136 [Gating] SW calibration Done
4634 12:40:25.830550 ==
4635 12:40:25.830657 Dram Type= 6, Freq= 0, CH_1, rank 1
4636 12:40:25.837315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4637 12:40:25.837445 ==
4638 12:40:25.837516 RX Vref Scan: 0
4639 12:40:25.837577
4640 12:40:25.840424 RX Vref 0 -> 0, step: 1
4641 12:40:25.840520
4642 12:40:25.843928 RX Delay -230 -> 252, step: 16
4643 12:40:25.847286 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4644 12:40:25.850683 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4645 12:40:25.857203 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4646 12:40:25.860610 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4647 12:40:25.864039 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4648 12:40:25.867468 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4649 12:40:25.870817 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4650 12:40:25.877472 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4651 12:40:25.881050 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4652 12:40:25.883797 iDelay=218, Bit 9, Center 49 (-102 ~ 201) 304
4653 12:40:25.887193 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4654 12:40:25.893821 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4655 12:40:25.897062 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4656 12:40:25.900499 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4657 12:40:25.904051 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4658 12:40:25.910386 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4659 12:40:25.910516 ==
4660 12:40:25.913862 Dram Type= 6, Freq= 0, CH_1, rank 1
4661 12:40:25.917116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4662 12:40:25.917232 ==
4663 12:40:25.917303 DQS Delay:
4664 12:40:25.920368 DQS0 = 0, DQS1 = 0
4665 12:40:25.920465 DQM Delay:
4666 12:40:25.923569 DQM0 = 51, DQM1 = 50
4667 12:40:25.923663 DQ Delay:
4668 12:40:25.927288 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4669 12:40:25.930267 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4670 12:40:25.933696 DQ8 =33, DQ9 =49, DQ10 =49, DQ11 =49
4671 12:40:25.937145 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4672 12:40:25.937273
4673 12:40:25.937341
4674 12:40:25.937402 ==
4675 12:40:25.940547 Dram Type= 6, Freq= 0, CH_1, rank 1
4676 12:40:25.943501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4677 12:40:25.943615 ==
4678 12:40:25.943681
4679 12:40:25.943740
4680 12:40:25.946926 TX Vref Scan disable
4681 12:40:25.950115 == TX Byte 0 ==
4682 12:40:25.953342 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4683 12:40:25.957087 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4684 12:40:25.960225 == TX Byte 1 ==
4685 12:40:25.963553 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4686 12:40:25.967058 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4687 12:40:25.967171 ==
4688 12:40:25.970405 Dram Type= 6, Freq= 0, CH_1, rank 1
4689 12:40:25.976654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4690 12:40:25.976797 ==
4691 12:40:25.976872
4692 12:40:25.976932
4693 12:40:25.976989 TX Vref Scan disable
4694 12:40:25.981226 == TX Byte 0 ==
4695 12:40:25.984654 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4696 12:40:25.990884 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4697 12:40:25.991016 == TX Byte 1 ==
4698 12:40:25.994247 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4699 12:40:26.000747 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4700 12:40:26.000880
4701 12:40:26.000949 [DATLAT]
4702 12:40:26.001009 Freq=600, CH1 RK1
4703 12:40:26.001079
4704 12:40:26.004724 DATLAT Default: 0x9
4705 12:40:26.004827 0, 0xFFFF, sum = 0
4706 12:40:26.007379 1, 0xFFFF, sum = 0
4707 12:40:26.007473 2, 0xFFFF, sum = 0
4708 12:40:26.011008 3, 0xFFFF, sum = 0
4709 12:40:26.014410 4, 0xFFFF, sum = 0
4710 12:40:26.014515 5, 0xFFFF, sum = 0
4711 12:40:26.017858 6, 0xFFFF, sum = 0
4712 12:40:26.017962 7, 0xFFFF, sum = 0
4713 12:40:26.021329 8, 0x0, sum = 1
4714 12:40:26.021431 9, 0x0, sum = 2
4715 12:40:26.021498 10, 0x0, sum = 3
4716 12:40:26.023889 11, 0x0, sum = 4
4717 12:40:26.023975 best_step = 9
4718 12:40:26.024039
4719 12:40:26.024099 ==
4720 12:40:26.027346 Dram Type= 6, Freq= 0, CH_1, rank 1
4721 12:40:26.034330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4722 12:40:26.034463 ==
4723 12:40:26.034532 RX Vref Scan: 0
4724 12:40:26.034593
4725 12:40:26.037674 RX Vref 0 -> 0, step: 1
4726 12:40:26.037783
4727 12:40:26.040982 RX Delay -163 -> 252, step: 8
4728 12:40:26.044305 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4729 12:40:26.051027 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4730 12:40:26.053867 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4731 12:40:26.057446 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4732 12:40:26.060583 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4733 12:40:26.064270 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4734 12:40:26.070999 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4735 12:40:26.073878 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4736 12:40:26.077406 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4737 12:40:26.080758 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4738 12:40:26.084248 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4739 12:40:26.090537 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4740 12:40:26.093898 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4741 12:40:26.097386 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4742 12:40:26.101018 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4743 12:40:26.104223 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4744 12:40:26.107637 ==
4745 12:40:26.110602 Dram Type= 6, Freq= 0, CH_1, rank 1
4746 12:40:26.114171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4747 12:40:26.114286 ==
4748 12:40:26.114354 DQS Delay:
4749 12:40:26.117361 DQS0 = 0, DQS1 = 0
4750 12:40:26.117462 DQM Delay:
4751 12:40:26.120842 DQM0 = 48, DQM1 = 45
4752 12:40:26.120939 DQ Delay:
4753 12:40:26.124174 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4754 12:40:26.127450 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4755 12:40:26.130813 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4756 12:40:26.134330 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4757 12:40:26.134442
4758 12:40:26.134508
4759 12:40:26.140312 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a20, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4760 12:40:26.143775 CH1 RK1: MR19=808, MR18=6A20
4761 12:40:26.151031 CH1_RK1: MR19=0x808, MR18=0x6A20, DQSOSC=389, MR23=63, INC=173, DEC=115
4762 12:40:26.153772 [RxdqsGatingPostProcess] freq 600
4763 12:40:26.160479 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4764 12:40:26.160639 Pre-setting of DQS Precalculation
4765 12:40:26.167299 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4766 12:40:26.174000 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4767 12:40:26.180546 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4768 12:40:26.180689
4769 12:40:26.180756
4770 12:40:26.184214 [Calibration Summary] 1200 Mbps
4771 12:40:26.187385 CH 0, Rank 0
4772 12:40:26.187499 SW Impedance : PASS
4773 12:40:26.190657 DUTY Scan : NO K
4774 12:40:26.193595 ZQ Calibration : PASS
4775 12:40:26.193702 Jitter Meter : NO K
4776 12:40:26.197098 CBT Training : PASS
4777 12:40:26.197222 Write leveling : PASS
4778 12:40:26.200343 RX DQS gating : PASS
4779 12:40:26.203600 RX DQ/DQS(RDDQC) : PASS
4780 12:40:26.203705 TX DQ/DQS : PASS
4781 12:40:26.206987 RX DATLAT : PASS
4782 12:40:26.210344 RX DQ/DQS(Engine): PASS
4783 12:40:26.210453 TX OE : NO K
4784 12:40:26.213722 All Pass.
4785 12:40:26.213822
4786 12:40:26.213887 CH 0, Rank 1
4787 12:40:26.216542 SW Impedance : PASS
4788 12:40:26.216633 DUTY Scan : NO K
4789 12:40:26.220461 ZQ Calibration : PASS
4790 12:40:26.223615 Jitter Meter : NO K
4791 12:40:26.223720 CBT Training : PASS
4792 12:40:26.227149 Write leveling : PASS
4793 12:40:26.230415 RX DQS gating : PASS
4794 12:40:26.230524 RX DQ/DQS(RDDQC) : PASS
4795 12:40:26.233092 TX DQ/DQS : PASS
4796 12:40:26.236588 RX DATLAT : PASS
4797 12:40:26.236695 RX DQ/DQS(Engine): PASS
4798 12:40:26.240053 TX OE : NO K
4799 12:40:26.240174 All Pass.
4800 12:40:26.240271
4801 12:40:26.243519 CH 1, Rank 0
4802 12:40:26.243611 SW Impedance : PASS
4803 12:40:26.247024 DUTY Scan : NO K
4804 12:40:26.250370 ZQ Calibration : PASS
4805 12:40:26.250476 Jitter Meter : NO K
4806 12:40:26.253650 CBT Training : PASS
4807 12:40:26.253745 Write leveling : PASS
4808 12:40:26.256355 RX DQS gating : PASS
4809 12:40:26.259926 RX DQ/DQS(RDDQC) : PASS
4810 12:40:26.260066 TX DQ/DQS : PASS
4811 12:40:26.263247 RX DATLAT : PASS
4812 12:40:26.266632 RX DQ/DQS(Engine): PASS
4813 12:40:26.266740 TX OE : NO K
4814 12:40:26.270005 All Pass.
4815 12:40:26.270104
4816 12:40:26.270169 CH 1, Rank 1
4817 12:40:26.273429 SW Impedance : PASS
4818 12:40:26.273523 DUTY Scan : NO K
4819 12:40:26.276674 ZQ Calibration : PASS
4820 12:40:26.280168 Jitter Meter : NO K
4821 12:40:26.280317 CBT Training : PASS
4822 12:40:26.283494 Write leveling : PASS
4823 12:40:26.286810 RX DQS gating : PASS
4824 12:40:26.286944 RX DQ/DQS(RDDQC) : PASS
4825 12:40:26.290424 TX DQ/DQS : PASS
4826 12:40:26.293181 RX DATLAT : PASS
4827 12:40:26.293289 RX DQ/DQS(Engine): PASS
4828 12:40:26.296717 TX OE : NO K
4829 12:40:26.296816 All Pass.
4830 12:40:26.296882
4831 12:40:26.300124 DramC Write-DBI off
4832 12:40:26.303500 PER_BANK_REFRESH: Hybrid Mode
4833 12:40:26.303626 TX_TRACKING: ON
4834 12:40:26.313535 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4835 12:40:26.316768 [FAST_K] Save calibration result to emmc
4836 12:40:26.319972 dramc_set_vcore_voltage set vcore to 662500
4837 12:40:26.320107 Read voltage for 933, 3
4838 12:40:26.323843 Vio18 = 0
4839 12:40:26.323946 Vcore = 662500
4840 12:40:26.324011 Vdram = 0
4841 12:40:26.326776 Vddq = 0
4842 12:40:26.326865 Vmddr = 0
4843 12:40:26.329847 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4844 12:40:26.336525 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4845 12:40:26.339803 MEM_TYPE=3, freq_sel=17
4846 12:40:26.343604 sv_algorithm_assistance_LP4_1600
4847 12:40:26.346471 ============ PULL DRAM RESETB DOWN ============
4848 12:40:26.349772 ========== PULL DRAM RESETB DOWN end =========
4849 12:40:26.356661 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4850 12:40:26.359886 ===================================
4851 12:40:26.360004 LPDDR4 DRAM CONFIGURATION
4852 12:40:26.363346 ===================================
4853 12:40:26.366795 EX_ROW_EN[0] = 0x0
4854 12:40:26.366902 EX_ROW_EN[1] = 0x0
4855 12:40:26.370200 LP4Y_EN = 0x0
4856 12:40:26.370299 WORK_FSP = 0x0
4857 12:40:26.373520 WL = 0x3
4858 12:40:26.373615 RL = 0x3
4859 12:40:26.376899 BL = 0x2
4860 12:40:26.376992 RPST = 0x0
4861 12:40:26.380256 RD_PRE = 0x0
4862 12:40:26.383624 WR_PRE = 0x1
4863 12:40:26.383733 WR_PST = 0x0
4864 12:40:26.387030 DBI_WR = 0x0
4865 12:40:26.387155 DBI_RD = 0x0
4866 12:40:26.390238 OTF = 0x1
4867 12:40:26.393601 ===================================
4868 12:40:26.396917 ===================================
4869 12:40:26.397034 ANA top config
4870 12:40:26.400177 ===================================
4871 12:40:26.403714 DLL_ASYNC_EN = 0
4872 12:40:26.406603 ALL_SLAVE_EN = 1
4873 12:40:26.406709 NEW_RANK_MODE = 1
4874 12:40:26.410043 DLL_IDLE_MODE = 1
4875 12:40:26.413373 LP45_APHY_COMB_EN = 1
4876 12:40:26.416682 TX_ODT_DIS = 1
4877 12:40:26.416793 NEW_8X_MODE = 1
4878 12:40:26.420064 ===================================
4879 12:40:26.423477 ===================================
4880 12:40:26.426797 data_rate = 1866
4881 12:40:26.430164 CKR = 1
4882 12:40:26.432987 DQ_P2S_RATIO = 8
4883 12:40:26.436956 ===================================
4884 12:40:26.440212 CA_P2S_RATIO = 8
4885 12:40:26.443219 DQ_CA_OPEN = 0
4886 12:40:26.443328 DQ_SEMI_OPEN = 0
4887 12:40:26.446691 CA_SEMI_OPEN = 0
4888 12:40:26.450243 CA_FULL_RATE = 0
4889 12:40:26.453406 DQ_CKDIV4_EN = 1
4890 12:40:26.456336 CA_CKDIV4_EN = 1
4891 12:40:26.459884 CA_PREDIV_EN = 0
4892 12:40:26.459999 PH8_DLY = 0
4893 12:40:26.463299 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4894 12:40:26.466466 DQ_AAMCK_DIV = 4
4895 12:40:26.469430 CA_AAMCK_DIV = 4
4896 12:40:26.473043 CA_ADMCK_DIV = 4
4897 12:40:26.476101 DQ_TRACK_CA_EN = 0
4898 12:40:26.476241 CA_PICK = 933
4899 12:40:26.479890 CA_MCKIO = 933
4900 12:40:26.482804 MCKIO_SEMI = 0
4901 12:40:26.486290 PLL_FREQ = 3732
4902 12:40:26.489473 DQ_UI_PI_RATIO = 32
4903 12:40:26.492837 CA_UI_PI_RATIO = 0
4904 12:40:26.496197 ===================================
4905 12:40:26.499284 ===================================
4906 12:40:26.502590 memory_type:LPDDR4
4907 12:40:26.502705 GP_NUM : 10
4908 12:40:26.506009 SRAM_EN : 1
4909 12:40:26.506104 MD32_EN : 0
4910 12:40:26.509488 ===================================
4911 12:40:26.512762 [ANA_INIT] >>>>>>>>>>>>>>
4912 12:40:26.516102 <<<<<< [CONFIGURE PHASE]: ANA_TX
4913 12:40:26.519504 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4914 12:40:26.522942 ===================================
4915 12:40:26.526282 data_rate = 1866,PCW = 0X8f00
4916 12:40:26.529656 ===================================
4917 12:40:26.532966 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4918 12:40:26.536460 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4919 12:40:26.542755 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4920 12:40:26.546119 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4921 12:40:26.549338 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4922 12:40:26.556127 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4923 12:40:26.556270 [ANA_INIT] flow start
4924 12:40:26.559432 [ANA_INIT] PLL >>>>>>>>
4925 12:40:26.559527 [ANA_INIT] PLL <<<<<<<<
4926 12:40:26.563013 [ANA_INIT] MIDPI >>>>>>>>
4927 12:40:26.566304 [ANA_INIT] MIDPI <<<<<<<<
4928 12:40:26.569729 [ANA_INIT] DLL >>>>>>>>
4929 12:40:26.569844 [ANA_INIT] flow end
4930 12:40:26.572922 ============ LP4 DIFF to SE enter ============
4931 12:40:26.579195 ============ LP4 DIFF to SE exit ============
4932 12:40:26.579322 [ANA_INIT] <<<<<<<<<<<<<
4933 12:40:26.582729 [Flow] Enable top DCM control >>>>>
4934 12:40:26.585954 [Flow] Enable top DCM control <<<<<
4935 12:40:26.589555 Enable DLL master slave shuffle
4936 12:40:26.596023 ==============================================================
4937 12:40:26.596205 Gating Mode config
4938 12:40:26.602390 ==============================================================
4939 12:40:26.606098 Config description:
4940 12:40:26.615949 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4941 12:40:26.622731 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4942 12:40:26.625515 SELPH_MODE 0: By rank 1: By Phase
4943 12:40:26.632508 ==============================================================
4944 12:40:26.635640 GAT_TRACK_EN = 1
4945 12:40:26.639126 RX_GATING_MODE = 2
4946 12:40:26.639240 RX_GATING_TRACK_MODE = 2
4947 12:40:26.642735 SELPH_MODE = 1
4948 12:40:26.646048 PICG_EARLY_EN = 1
4949 12:40:26.648761 VALID_LAT_VALUE = 1
4950 12:40:26.655581 ==============================================================
4951 12:40:26.659022 Enter into Gating configuration >>>>
4952 12:40:26.662424 Exit from Gating configuration <<<<
4953 12:40:26.665910 Enter into DVFS_PRE_config >>>>>
4954 12:40:26.675952 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4955 12:40:26.679228 Exit from DVFS_PRE_config <<<<<
4956 12:40:26.682711 Enter into PICG configuration >>>>
4957 12:40:26.686301 Exit from PICG configuration <<<<
4958 12:40:26.689224 [RX_INPUT] configuration >>>>>
4959 12:40:26.692148 [RX_INPUT] configuration <<<<<
4960 12:40:26.695541 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4961 12:40:26.702224 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4962 12:40:26.708694 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4963 12:40:26.712504 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4964 12:40:26.718742 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4965 12:40:26.725325 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4966 12:40:26.728887 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4967 12:40:26.735116 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4968 12:40:26.738663 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4969 12:40:26.742035 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4970 12:40:26.745190 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4971 12:40:26.752153 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4972 12:40:26.755590 ===================================
4973 12:40:26.755708 LPDDR4 DRAM CONFIGURATION
4974 12:40:26.758314 ===================================
4975 12:40:26.761680 EX_ROW_EN[0] = 0x0
4976 12:40:26.765169 EX_ROW_EN[1] = 0x0
4977 12:40:26.765283 LP4Y_EN = 0x0
4978 12:40:26.768721 WORK_FSP = 0x0
4979 12:40:26.768818 WL = 0x3
4980 12:40:26.772170 RL = 0x3
4981 12:40:26.772267 BL = 0x2
4982 12:40:26.775584 RPST = 0x0
4983 12:40:26.775687 RD_PRE = 0x0
4984 12:40:26.778323 WR_PRE = 0x1
4985 12:40:26.778412 WR_PST = 0x0
4986 12:40:26.782327 DBI_WR = 0x0
4987 12:40:26.782427 DBI_RD = 0x0
4988 12:40:26.785060 OTF = 0x1
4989 12:40:26.788342 ===================================
4990 12:40:26.791886 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4991 12:40:26.795283 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4992 12:40:26.802025 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4993 12:40:26.805320 ===================================
4994 12:40:26.805432 LPDDR4 DRAM CONFIGURATION
4995 12:40:26.808515 ===================================
4996 12:40:26.811839 EX_ROW_EN[0] = 0x10
4997 12:40:26.811951 EX_ROW_EN[1] = 0x0
4998 12:40:26.815316 LP4Y_EN = 0x0
4999 12:40:26.818657 WORK_FSP = 0x0
5000 12:40:26.818768 WL = 0x3
5001 12:40:26.822063 RL = 0x3
5002 12:40:26.822180 BL = 0x2
5003 12:40:26.825410 RPST = 0x0
5004 12:40:26.825507 RD_PRE = 0x0
5005 12:40:26.828252 WR_PRE = 0x1
5006 12:40:26.828372 WR_PST = 0x0
5007 12:40:26.831650 DBI_WR = 0x0
5008 12:40:26.831745 DBI_RD = 0x0
5009 12:40:26.834947 OTF = 0x1
5010 12:40:26.838325 ===================================
5011 12:40:26.845051 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5012 12:40:26.848258 nWR fixed to 30
5013 12:40:26.848446 [ModeRegInit_LP4] CH0 RK0
5014 12:40:26.851634 [ModeRegInit_LP4] CH0 RK1
5015 12:40:26.854934 [ModeRegInit_LP4] CH1 RK0
5016 12:40:26.858114 [ModeRegInit_LP4] CH1 RK1
5017 12:40:26.858236 match AC timing 9
5018 12:40:26.861666 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5019 12:40:26.864716 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5020 12:40:26.871404 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5021 12:40:26.874605 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5022 12:40:26.881536 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5023 12:40:26.881678 ==
5024 12:40:26.884940 Dram Type= 6, Freq= 0, CH_0, rank 0
5025 12:40:26.888153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5026 12:40:26.888305 ==
5027 12:40:26.894463 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5028 12:40:26.901187 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5029 12:40:26.904633 [CA 0] Center 37 (7~68) winsize 62
5030 12:40:26.908093 [CA 1] Center 37 (7~68) winsize 62
5031 12:40:26.910851 [CA 2] Center 34 (4~65) winsize 62
5032 12:40:26.914119 [CA 3] Center 34 (3~65) winsize 63
5033 12:40:26.917509 [CA 4] Center 33 (3~64) winsize 62
5034 12:40:26.921036 [CA 5] Center 32 (2~62) winsize 61
5035 12:40:26.921154
5036 12:40:26.924424 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5037 12:40:26.924524
5038 12:40:26.927715 [CATrainingPosCal] consider 1 rank data
5039 12:40:26.931034 u2DelayCellTimex100 = 270/100 ps
5040 12:40:26.934499 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5041 12:40:26.937875 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5042 12:40:26.940681 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5043 12:40:26.944035 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5044 12:40:26.947949 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5045 12:40:26.950673 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5046 12:40:26.950774
5047 12:40:26.957477 CA PerBit enable=1, Macro0, CA PI delay=32
5048 12:40:26.957609
5049 12:40:26.957677 [CBTSetCACLKResult] CA Dly = 32
5050 12:40:26.961001 CS Dly: 5 (0~36)
5051 12:40:26.961096 ==
5052 12:40:26.964283 Dram Type= 6, Freq= 0, CH_0, rank 1
5053 12:40:26.967664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5054 12:40:26.967773 ==
5055 12:40:26.974396 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5056 12:40:26.980992 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5057 12:40:26.983658 [CA 0] Center 37 (6~68) winsize 63
5058 12:40:26.987572 [CA 1] Center 37 (6~68) winsize 63
5059 12:40:26.990875 [CA 2] Center 34 (4~65) winsize 62
5060 12:40:26.993959 [CA 3] Center 34 (3~65) winsize 63
5061 12:40:26.996959 [CA 4] Center 33 (3~63) winsize 61
5062 12:40:27.000343 [CA 5] Center 32 (2~62) winsize 61
5063 12:40:27.000451
5064 12:40:27.004110 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5065 12:40:27.004239
5066 12:40:27.007556 [CATrainingPosCal] consider 2 rank data
5067 12:40:27.010685 u2DelayCellTimex100 = 270/100 ps
5068 12:40:27.014121 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5069 12:40:27.017202 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5070 12:40:27.020848 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5071 12:40:27.023882 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5072 12:40:27.027212 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5073 12:40:27.030668 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5074 12:40:27.030781
5075 12:40:27.037440 CA PerBit enable=1, Macro0, CA PI delay=32
5076 12:40:27.037577
5077 12:40:27.040684 [CBTSetCACLKResult] CA Dly = 32
5078 12:40:27.040809 CS Dly: 5 (0~37)
5079 12:40:27.040901
5080 12:40:27.044084 ----->DramcWriteLeveling(PI) begin...
5081 12:40:27.044196 ==
5082 12:40:27.047549 Dram Type= 6, Freq= 0, CH_0, rank 0
5083 12:40:27.050865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5084 12:40:27.050969 ==
5085 12:40:27.054244 Write leveling (Byte 0): 32 => 32
5086 12:40:27.057022 Write leveling (Byte 1): 30 => 30
5087 12:40:27.060370 DramcWriteLeveling(PI) end<-----
5088 12:40:27.060493
5089 12:40:27.060574 ==
5090 12:40:27.063883 Dram Type= 6, Freq= 0, CH_0, rank 0
5091 12:40:27.070609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5092 12:40:27.070744 ==
5093 12:40:27.070811 [Gating] SW mode calibration
5094 12:40:27.080741 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5095 12:40:27.083365 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5096 12:40:27.087219 0 14 0 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
5097 12:40:27.093424 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5098 12:40:27.096889 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5099 12:40:27.100276 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5100 12:40:27.106924 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5101 12:40:27.110380 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5102 12:40:27.113634 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
5103 12:40:27.120107 0 14 28 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
5104 12:40:27.123906 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
5105 12:40:27.127308 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5106 12:40:27.133829 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5107 12:40:27.137039 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5108 12:40:27.140259 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5109 12:40:27.147245 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5110 12:40:27.150100 0 15 24 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
5111 12:40:27.153482 0 15 28 | B1->B0 | 2424 3d3d | 0 0 | (1 1) (0 0)
5112 12:40:27.160094 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5113 12:40:27.163255 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 12:40:27.166574 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5115 12:40:27.173298 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5116 12:40:27.176573 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 12:40:27.180063 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 12:40:27.186910 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5119 12:40:27.190404 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5120 12:40:27.193828 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5121 12:40:27.200364 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5122 12:40:27.203731 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 12:40:27.206551 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 12:40:27.209909 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 12:40:27.216718 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 12:40:27.220114 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 12:40:27.223572 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 12:40:27.229924 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 12:40:27.233514 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 12:40:27.237030 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 12:40:27.243140 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 12:40:27.246689 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 12:40:27.249897 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 12:40:27.256807 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5135 12:40:27.259909 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5136 12:40:27.262989 Total UI for P1: 0, mck2ui 16
5137 12:40:27.266688 best dqsien dly found for B0: ( 1, 2, 24)
5138 12:40:27.270099 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 12:40:27.273414 Total UI for P1: 0, mck2ui 16
5140 12:40:27.276631 best dqsien dly found for B1: ( 1, 2, 30)
5141 12:40:27.279773 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5142 12:40:27.283237 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5143 12:40:27.283347
5144 12:40:27.289590 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5145 12:40:27.293083 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5146 12:40:27.293203 [Gating] SW calibration Done
5147 12:40:27.296162 ==
5148 12:40:27.299807 Dram Type= 6, Freq= 0, CH_0, rank 0
5149 12:40:27.302815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5150 12:40:27.302927 ==
5151 12:40:27.302993 RX Vref Scan: 0
5152 12:40:27.303053
5153 12:40:27.306042 RX Vref 0 -> 0, step: 1
5154 12:40:27.306163
5155 12:40:27.310072 RX Delay -80 -> 252, step: 8
5156 12:40:27.312884 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5157 12:40:27.316321 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5158 12:40:27.319770 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5159 12:40:27.326522 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5160 12:40:27.329746 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5161 12:40:27.333002 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5162 12:40:27.336302 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5163 12:40:27.339669 iDelay=208, Bit 7, Center 111 (24 ~ 199) 176
5164 12:40:27.343040 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5165 12:40:27.349729 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5166 12:40:27.353166 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5167 12:40:27.356578 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5168 12:40:27.359320 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5169 12:40:27.363181 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5170 12:40:27.366448 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5171 12:40:27.372657 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5172 12:40:27.372789 ==
5173 12:40:27.376115 Dram Type= 6, Freq= 0, CH_0, rank 0
5174 12:40:27.379552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5175 12:40:27.379665 ==
5176 12:40:27.379730 DQS Delay:
5177 12:40:27.382955 DQS0 = 0, DQS1 = 0
5178 12:40:27.383049 DQM Delay:
5179 12:40:27.386264 DQM0 = 104, DQM1 = 94
5180 12:40:27.386363 DQ Delay:
5181 12:40:27.389461 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5182 12:40:27.393175 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =111
5183 12:40:27.396109 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5184 12:40:27.399257 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5185 12:40:27.399391
5186 12:40:27.399483
5187 12:40:27.399570 ==
5188 12:40:27.403024 Dram Type= 6, Freq= 0, CH_0, rank 0
5189 12:40:27.409187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5190 12:40:27.409314 ==
5191 12:40:27.409399
5192 12:40:27.409472
5193 12:40:27.409528 TX Vref Scan disable
5194 12:40:27.412990 == TX Byte 0 ==
5195 12:40:27.416025 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5196 12:40:27.422541 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5197 12:40:27.422708 == TX Byte 1 ==
5198 12:40:27.426242 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5199 12:40:27.432601 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5200 12:40:27.432771 ==
5201 12:40:27.436265 Dram Type= 6, Freq= 0, CH_0, rank 0
5202 12:40:27.439477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5203 12:40:27.439589 ==
5204 12:40:27.439656
5205 12:40:27.439715
5206 12:40:27.442491 TX Vref Scan disable
5207 12:40:27.442597 == TX Byte 0 ==
5208 12:40:27.449161 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5209 12:40:27.452623 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5210 12:40:27.452744 == TX Byte 1 ==
5211 12:40:27.459448 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5212 12:40:27.462815 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5213 12:40:27.462926
5214 12:40:27.462991 [DATLAT]
5215 12:40:27.466172 Freq=933, CH0 RK0
5216 12:40:27.466269
5217 12:40:27.466334 DATLAT Default: 0xd
5218 12:40:27.469464 0, 0xFFFF, sum = 0
5219 12:40:27.469559 1, 0xFFFF, sum = 0
5220 12:40:27.472661 2, 0xFFFF, sum = 0
5221 12:40:27.472757 3, 0xFFFF, sum = 0
5222 12:40:27.476167 4, 0xFFFF, sum = 0
5223 12:40:27.476266 5, 0xFFFF, sum = 0
5224 12:40:27.478864 6, 0xFFFF, sum = 0
5225 12:40:27.482342 7, 0xFFFF, sum = 0
5226 12:40:27.482450 8, 0xFFFF, sum = 0
5227 12:40:27.485635 9, 0xFFFF, sum = 0
5228 12:40:27.485733 10, 0x0, sum = 1
5229 12:40:27.485800 11, 0x0, sum = 2
5230 12:40:27.489027 12, 0x0, sum = 3
5231 12:40:27.489119 13, 0x0, sum = 4
5232 12:40:27.492676 best_step = 11
5233 12:40:27.492804
5234 12:40:27.492906 ==
5235 12:40:27.496116 Dram Type= 6, Freq= 0, CH_0, rank 0
5236 12:40:27.499415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5237 12:40:27.499521 ==
5238 12:40:27.502435 RX Vref Scan: 1
5239 12:40:27.502533
5240 12:40:27.502597 RX Vref 0 -> 0, step: 1
5241 12:40:27.502657
5242 12:40:27.505721 RX Delay -53 -> 252, step: 4
5243 12:40:27.505811
5244 12:40:27.508961 Set Vref, RX VrefLevel [Byte0]: 55
5245 12:40:27.512201 [Byte1]: 47
5246 12:40:27.517100
5247 12:40:27.517247 Final RX Vref Byte 0 = 55 to rank0
5248 12:40:27.519773 Final RX Vref Byte 1 = 47 to rank0
5249 12:40:27.523238 Final RX Vref Byte 0 = 55 to rank1
5250 12:40:27.526704 Final RX Vref Byte 1 = 47 to rank1==
5251 12:40:27.530137 Dram Type= 6, Freq= 0, CH_0, rank 0
5252 12:40:27.533500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5253 12:40:27.536682 ==
5254 12:40:27.536793 DQS Delay:
5255 12:40:27.536911 DQS0 = 0, DQS1 = 0
5256 12:40:27.540022 DQM Delay:
5257 12:40:27.540119 DQM0 = 104, DQM1 = 95
5258 12:40:27.543470 DQ Delay:
5259 12:40:27.547071 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5260 12:40:27.550365 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5261 12:40:27.553668 DQ8 =84, DQ9 =84, DQ10 =98, DQ11 =88
5262 12:40:27.556968 DQ12 =100, DQ13 =100, DQ14 =106, DQ15 =104
5263 12:40:27.557092
5264 12:40:27.557158
5265 12:40:27.563055 [DQSOSCAuto] RK0, (LSB)MR18= 0x3129, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5266 12:40:27.566450 CH0 RK0: MR19=505, MR18=3129
5267 12:40:27.573052 CH0_RK0: MR19=0x505, MR18=0x3129, DQSOSC=406, MR23=63, INC=65, DEC=43
5268 12:40:27.573220
5269 12:40:27.576432 ----->DramcWriteLeveling(PI) begin...
5270 12:40:27.576538 ==
5271 12:40:27.579914 Dram Type= 6, Freq= 0, CH_0, rank 1
5272 12:40:27.583040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 12:40:27.583180 ==
5274 12:40:27.586383 Write leveling (Byte 0): 33 => 33
5275 12:40:27.589998 Write leveling (Byte 1): 30 => 30
5276 12:40:27.593429 DramcWriteLeveling(PI) end<-----
5277 12:40:27.593534
5278 12:40:27.593597 ==
5279 12:40:27.596229 Dram Type= 6, Freq= 0, CH_0, rank 1
5280 12:40:27.603031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5281 12:40:27.603184 ==
5282 12:40:27.603318 [Gating] SW mode calibration
5283 12:40:27.612742 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5284 12:40:27.616649 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5285 12:40:27.620063 0 14 0 | B1->B0 | 3333 3333 | 1 0 | (1 1) (0 0)
5286 12:40:27.626257 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5287 12:40:27.629899 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5288 12:40:27.633341 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5289 12:40:27.639448 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5290 12:40:27.643464 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5291 12:40:27.646313 0 14 24 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 1)
5292 12:40:27.652985 0 14 28 | B1->B0 | 2c2c 2929 | 0 0 | (0 1) (0 1)
5293 12:40:27.656378 0 15 0 | B1->B0 | 2525 2626 | 0 0 | (0 0) (0 0)
5294 12:40:27.659697 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5295 12:40:27.666608 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5296 12:40:27.669419 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5297 12:40:27.672823 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5298 12:40:27.679646 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5299 12:40:27.682978 0 15 24 | B1->B0 | 2b2b 2626 | 0 0 | (0 0) (0 0)
5300 12:40:27.686223 0 15 28 | B1->B0 | 4242 3f3f | 0 1 | (0 0) (0 0)
5301 12:40:27.689998 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5302 12:40:27.696743 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5303 12:40:27.700056 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5304 12:40:27.702748 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5305 12:40:27.709540 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5306 12:40:27.713023 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5307 12:40:27.716621 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 12:40:27.722829 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5309 12:40:27.726616 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 12:40:27.729450 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 12:40:27.736671 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 12:40:27.740029 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 12:40:27.743372 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 12:40:27.749411 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 12:40:27.752885 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 12:40:27.756384 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 12:40:27.763285 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 12:40:27.766022 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 12:40:27.769354 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 12:40:27.776334 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 12:40:27.779615 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 12:40:27.783047 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 12:40:27.789092 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5324 12:40:27.792573 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5325 12:40:27.796043 Total UI for P1: 0, mck2ui 16
5326 12:40:27.799329 best dqsien dly found for B0: ( 1, 2, 24)
5327 12:40:27.802991 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 12:40:27.806059 Total UI for P1: 0, mck2ui 16
5329 12:40:27.809555 best dqsien dly found for B1: ( 1, 2, 26)
5330 12:40:27.812361 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5331 12:40:27.816205 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5332 12:40:27.816339
5333 12:40:27.818904 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5334 12:40:27.826094 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5335 12:40:27.826258 [Gating] SW calibration Done
5336 12:40:27.826355 ==
5337 12:40:27.829299 Dram Type= 6, Freq= 0, CH_0, rank 1
5338 12:40:27.836092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5339 12:40:27.836250 ==
5340 12:40:27.836347 RX Vref Scan: 0
5341 12:40:27.836409
5342 12:40:27.838929 RX Vref 0 -> 0, step: 1
5343 12:40:27.839036
5344 12:40:27.842425 RX Delay -80 -> 252, step: 8
5345 12:40:27.845623 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5346 12:40:27.849076 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5347 12:40:27.852724 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5348 12:40:27.859033 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5349 12:40:27.862329 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5350 12:40:27.865676 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5351 12:40:27.869103 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5352 12:40:27.872429 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5353 12:40:27.875863 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5354 12:40:27.882533 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5355 12:40:27.885331 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5356 12:40:27.888735 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5357 12:40:27.892118 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5358 12:40:27.895594 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5359 12:40:27.899030 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5360 12:40:27.905746 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5361 12:40:27.905896 ==
5362 12:40:27.909051 Dram Type= 6, Freq= 0, CH_0, rank 1
5363 12:40:27.912453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5364 12:40:27.912568 ==
5365 12:40:27.912649 DQS Delay:
5366 12:40:27.915131 DQS0 = 0, DQS1 = 0
5367 12:40:27.915234 DQM Delay:
5368 12:40:27.918671 DQM0 = 105, DQM1 = 94
5369 12:40:27.918799 DQ Delay:
5370 12:40:27.922176 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5371 12:40:27.925390 DQ4 =107, DQ5 =99, DQ6 =111, DQ7 =115
5372 12:40:27.928879 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5373 12:40:27.932257 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =99
5374 12:40:27.932400
5375 12:40:27.932504
5376 12:40:27.932604 ==
5377 12:40:27.935532 Dram Type= 6, Freq= 0, CH_0, rank 1
5378 12:40:27.938945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5379 12:40:27.942352 ==
5380 12:40:27.942471
5381 12:40:27.942539
5382 12:40:27.942599 TX Vref Scan disable
5383 12:40:27.945733 == TX Byte 0 ==
5384 12:40:27.949136 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5385 12:40:27.952306 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5386 12:40:27.955643 == TX Byte 1 ==
5387 12:40:27.959047 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5388 12:40:27.962331 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5389 12:40:27.965528 ==
5390 12:40:27.968800 Dram Type= 6, Freq= 0, CH_0, rank 1
5391 12:40:27.971961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5392 12:40:27.972088 ==
5393 12:40:27.972190
5394 12:40:27.972306
5395 12:40:27.975540 TX Vref Scan disable
5396 12:40:27.975643 == TX Byte 0 ==
5397 12:40:27.982165 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5398 12:40:27.985370 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5399 12:40:27.985495 == TX Byte 1 ==
5400 12:40:27.991630 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5401 12:40:27.995207 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5402 12:40:27.995362
5403 12:40:27.995431 [DATLAT]
5404 12:40:27.998288 Freq=933, CH0 RK1
5405 12:40:27.998419
5406 12:40:27.998517 DATLAT Default: 0xb
5407 12:40:28.001641 0, 0xFFFF, sum = 0
5408 12:40:28.001768 1, 0xFFFF, sum = 0
5409 12:40:28.005005 2, 0xFFFF, sum = 0
5410 12:40:28.005110 3, 0xFFFF, sum = 0
5411 12:40:28.008403 4, 0xFFFF, sum = 0
5412 12:40:28.008535 5, 0xFFFF, sum = 0
5413 12:40:28.011834 6, 0xFFFF, sum = 0
5414 12:40:28.011929 7, 0xFFFF, sum = 0
5415 12:40:28.015141 8, 0xFFFF, sum = 0
5416 12:40:28.018728 9, 0xFFFF, sum = 0
5417 12:40:28.018840 10, 0x0, sum = 1
5418 12:40:28.018910 11, 0x0, sum = 2
5419 12:40:28.022159 12, 0x0, sum = 3
5420 12:40:28.022264 13, 0x0, sum = 4
5421 12:40:28.025013 best_step = 11
5422 12:40:28.025135
5423 12:40:28.025232 ==
5424 12:40:28.028156 Dram Type= 6, Freq= 0, CH_0, rank 1
5425 12:40:28.031622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5426 12:40:28.031770 ==
5427 12:40:28.035162 RX Vref Scan: 0
5428 12:40:28.035266
5429 12:40:28.035333 RX Vref 0 -> 0, step: 1
5430 12:40:28.035392
5431 12:40:28.038736 RX Delay -45 -> 252, step: 4
5432 12:40:28.045532 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5433 12:40:28.048953 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5434 12:40:28.052199 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5435 12:40:28.055657 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5436 12:40:28.058984 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5437 12:40:28.065642 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5438 12:40:28.069103 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5439 12:40:28.071813 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5440 12:40:28.075257 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5441 12:40:28.078735 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5442 12:40:28.085422 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5443 12:40:28.088893 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5444 12:40:28.092226 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5445 12:40:28.095566 iDelay=199, Bit 13, Center 100 (19 ~ 182) 164
5446 12:40:28.098868 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5447 12:40:28.105261 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5448 12:40:28.105397 ==
5449 12:40:28.108490 Dram Type= 6, Freq= 0, CH_0, rank 1
5450 12:40:28.112251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5451 12:40:28.112379 ==
5452 12:40:28.112446 DQS Delay:
5453 12:40:28.115342 DQS0 = 0, DQS1 = 0
5454 12:40:28.115462 DQM Delay:
5455 12:40:28.118573 DQM0 = 104, DQM1 = 94
5456 12:40:28.118673 DQ Delay:
5457 12:40:28.121819 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102
5458 12:40:28.125059 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112
5459 12:40:28.128470 DQ8 =86, DQ9 =82, DQ10 =94, DQ11 =88
5460 12:40:28.132042 DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =102
5461 12:40:28.132188
5462 12:40:28.132302
5463 12:40:28.142022 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5464 12:40:28.142187 CH0 RK1: MR19=505, MR18=2A03
5465 12:40:28.148581 CH0_RK1: MR19=0x505, MR18=0x2A03, DQSOSC=408, MR23=63, INC=65, DEC=43
5466 12:40:28.152140 [RxdqsGatingPostProcess] freq 933
5467 12:40:28.158923 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5468 12:40:28.162305 best DQS0 dly(2T, 0.5T) = (0, 10)
5469 12:40:28.165695 best DQS1 dly(2T, 0.5T) = (0, 10)
5470 12:40:28.168891 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5471 12:40:28.172208 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5472 12:40:28.175073 best DQS0 dly(2T, 0.5T) = (0, 10)
5473 12:40:28.175175 best DQS1 dly(2T, 0.5T) = (0, 10)
5474 12:40:28.178490 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5475 12:40:28.182020 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5476 12:40:28.185307 Pre-setting of DQS Precalculation
5477 12:40:28.192113 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5478 12:40:28.192254 ==
5479 12:40:28.195400 Dram Type= 6, Freq= 0, CH_1, rank 0
5480 12:40:28.198822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5481 12:40:28.198933 ==
5482 12:40:28.205687 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5483 12:40:28.211702 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5484 12:40:28.215146 [CA 0] Center 36 (6~67) winsize 62
5485 12:40:28.218489 [CA 1] Center 36 (6~67) winsize 62
5486 12:40:28.221961 [CA 2] Center 34 (4~65) winsize 62
5487 12:40:28.224800 [CA 3] Center 34 (4~65) winsize 62
5488 12:40:28.228217 [CA 4] Center 34 (4~65) winsize 62
5489 12:40:28.231485 [CA 5] Center 33 (3~64) winsize 62
5490 12:40:28.231593
5491 12:40:28.234777 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5492 12:40:28.234898
5493 12:40:28.238068 [CATrainingPosCal] consider 1 rank data
5494 12:40:28.241904 u2DelayCellTimex100 = 270/100 ps
5495 12:40:28.245155 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5496 12:40:28.248749 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5497 12:40:28.251557 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5498 12:40:28.254990 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5499 12:40:28.258418 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5500 12:40:28.261711 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5501 12:40:28.261824
5502 12:40:28.265266 CA PerBit enable=1, Macro0, CA PI delay=33
5503 12:40:28.265390
5504 12:40:28.268474 [CBTSetCACLKResult] CA Dly = 33
5505 12:40:28.271776 CS Dly: 7 (0~38)
5506 12:40:28.271878 ==
5507 12:40:28.274789 Dram Type= 6, Freq= 0, CH_1, rank 1
5508 12:40:28.278712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5509 12:40:28.278834 ==
5510 12:40:28.285389 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5511 12:40:28.291685 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5512 12:40:28.295133 [CA 0] Center 37 (6~68) winsize 63
5513 12:40:28.298436 [CA 1] Center 37 (6~68) winsize 63
5514 12:40:28.301935 [CA 2] Center 35 (4~66) winsize 63
5515 12:40:28.305195 [CA 3] Center 34 (4~65) winsize 62
5516 12:40:28.308600 [CA 4] Center 34 (4~65) winsize 62
5517 12:40:28.311998 [CA 5] Center 34 (4~64) winsize 61
5518 12:40:28.312126
5519 12:40:28.314784 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5520 12:40:28.314902
5521 12:40:28.318228 [CATrainingPosCal] consider 2 rank data
5522 12:40:28.321540 u2DelayCellTimex100 = 270/100 ps
5523 12:40:28.324970 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5524 12:40:28.328422 CA1 delay=36 (6~67),Diff = 2 PI (12 cell)
5525 12:40:28.331728 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
5526 12:40:28.334489 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5527 12:40:28.338349 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5528 12:40:28.341669 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5529 12:40:28.341789
5530 12:40:28.347873 CA PerBit enable=1, Macro0, CA PI delay=34
5531 12:40:28.347998
5532 12:40:28.348072 [CBTSetCACLKResult] CA Dly = 34
5533 12:40:28.351375 CS Dly: 8 (0~40)
5534 12:40:28.351495
5535 12:40:28.354746 ----->DramcWriteLeveling(PI) begin...
5536 12:40:28.354874 ==
5537 12:40:28.358219 Dram Type= 6, Freq= 0, CH_1, rank 0
5538 12:40:28.360934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5539 12:40:28.361031 ==
5540 12:40:28.364231 Write leveling (Byte 0): 26 => 26
5541 12:40:28.367708 Write leveling (Byte 1): 28 => 28
5542 12:40:28.370971 DramcWriteLeveling(PI) end<-----
5543 12:40:28.371105
5544 12:40:28.371203 ==
5545 12:40:28.374404 Dram Type= 6, Freq= 0, CH_1, rank 0
5546 12:40:28.381324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5547 12:40:28.381489 ==
5548 12:40:28.381590 [Gating] SW mode calibration
5549 12:40:28.391080 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5550 12:40:28.394373 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5551 12:40:28.398106 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5552 12:40:28.404431 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5553 12:40:28.407458 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5554 12:40:28.411303 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5555 12:40:28.417822 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5556 12:40:28.420590 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5557 12:40:28.424077 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
5558 12:40:28.430905 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5559 12:40:28.434345 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 12:40:28.437845 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5561 12:40:28.443848 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5562 12:40:28.447752 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5563 12:40:28.450550 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5564 12:40:28.457435 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5565 12:40:28.460906 0 15 24 | B1->B0 | 2525 3333 | 0 0 | (0 0) (1 1)
5566 12:40:28.464269 0 15 28 | B1->B0 | 3a39 4646 | 1 0 | (0 0) (0 0)
5567 12:40:28.470951 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 12:40:28.474209 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 12:40:28.477537 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 12:40:28.483767 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5571 12:40:28.487258 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5572 12:40:28.490691 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5573 12:40:28.497461 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5574 12:40:28.500815 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 12:40:28.503860 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 12:40:28.510346 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 12:40:28.513978 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 12:40:28.517397 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 12:40:28.520416 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 12:40:28.527267 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 12:40:28.530812 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 12:40:28.533919 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 12:40:28.540521 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 12:40:28.544080 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 12:40:28.546784 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 12:40:28.553929 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 12:40:28.557187 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 12:40:28.560565 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 12:40:28.567389 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5590 12:40:28.570012 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5591 12:40:28.573863 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 12:40:28.577058 Total UI for P1: 0, mck2ui 16
5593 12:40:28.580363 best dqsien dly found for B0: ( 1, 2, 26)
5594 12:40:28.583649 Total UI for P1: 0, mck2ui 16
5595 12:40:28.587096 best dqsien dly found for B1: ( 1, 2, 26)
5596 12:40:28.589858 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5597 12:40:28.593363 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5598 12:40:28.593505
5599 12:40:28.600158 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5600 12:40:28.603565 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5601 12:40:28.606968 [Gating] SW calibration Done
5602 12:40:28.607104 ==
5603 12:40:28.609976 Dram Type= 6, Freq= 0, CH_1, rank 0
5604 12:40:28.613689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5605 12:40:28.613826 ==
5606 12:40:28.613923 RX Vref Scan: 0
5607 12:40:28.614015
5608 12:40:28.617017 RX Vref 0 -> 0, step: 1
5609 12:40:28.617104
5610 12:40:28.620148 RX Delay -80 -> 252, step: 8
5611 12:40:28.623455 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5612 12:40:28.626869 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5613 12:40:28.630354 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5614 12:40:28.636564 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5615 12:40:28.640016 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5616 12:40:28.643575 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5617 12:40:28.646528 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5618 12:40:28.650172 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5619 12:40:28.653089 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5620 12:40:28.660329 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5621 12:40:28.663236 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5622 12:40:28.666648 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5623 12:40:28.670024 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5624 12:40:28.673048 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5625 12:40:28.679932 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5626 12:40:28.682997 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5627 12:40:28.683133 ==
5628 12:40:28.686264 Dram Type= 6, Freq= 0, CH_1, rank 0
5629 12:40:28.689627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5630 12:40:28.689757 ==
5631 12:40:28.692943 DQS Delay:
5632 12:40:28.693070 DQS0 = 0, DQS1 = 0
5633 12:40:28.693165 DQM Delay:
5634 12:40:28.696508 DQM0 = 103, DQM1 = 98
5635 12:40:28.696621 DQ Delay:
5636 12:40:28.699918 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5637 12:40:28.703459 DQ4 =99, DQ5 =119, DQ6 =111, DQ7 =103
5638 12:40:28.706890 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5639 12:40:28.709544 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5640 12:40:28.709667
5641 12:40:28.709761
5642 12:40:28.713056 ==
5643 12:40:28.713171 Dram Type= 6, Freq= 0, CH_1, rank 0
5644 12:40:28.719622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5645 12:40:28.719777 ==
5646 12:40:28.719876
5647 12:40:28.719963
5648 12:40:28.720048 TX Vref Scan disable
5649 12:40:28.723600 == TX Byte 0 ==
5650 12:40:28.726848 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5651 12:40:28.733721 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5652 12:40:28.733877 == TX Byte 1 ==
5653 12:40:28.737134 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5654 12:40:28.743891 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5655 12:40:28.744019 ==
5656 12:40:28.746543 Dram Type= 6, Freq= 0, CH_1, rank 0
5657 12:40:28.750004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5658 12:40:28.750107 ==
5659 12:40:28.750172
5660 12:40:28.750231
5661 12:40:28.753449 TX Vref Scan disable
5662 12:40:28.753537 == TX Byte 0 ==
5663 12:40:28.760330 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5664 12:40:28.763551 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5665 12:40:28.763661 == TX Byte 1 ==
5666 12:40:28.770346 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5667 12:40:28.773406 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5668 12:40:28.773515
5669 12:40:28.773580 [DATLAT]
5670 12:40:28.776530 Freq=933, CH1 RK0
5671 12:40:28.776637
5672 12:40:28.776725 DATLAT Default: 0xd
5673 12:40:28.779787 0, 0xFFFF, sum = 0
5674 12:40:28.779897 1, 0xFFFF, sum = 0
5675 12:40:28.783334 2, 0xFFFF, sum = 0
5676 12:40:28.783445 3, 0xFFFF, sum = 0
5677 12:40:28.786900 4, 0xFFFF, sum = 0
5678 12:40:28.790322 5, 0xFFFF, sum = 0
5679 12:40:28.790465 6, 0xFFFF, sum = 0
5680 12:40:28.793418 7, 0xFFFF, sum = 0
5681 12:40:28.793552 8, 0xFFFF, sum = 0
5682 12:40:28.796378 9, 0xFFFF, sum = 0
5683 12:40:28.796468 10, 0x0, sum = 1
5684 12:40:28.799845 11, 0x0, sum = 2
5685 12:40:28.799970 12, 0x0, sum = 3
5686 12:40:28.800066 13, 0x0, sum = 4
5687 12:40:28.803498 best_step = 11
5688 12:40:28.803587
5689 12:40:28.803650 ==
5690 12:40:28.806656 Dram Type= 6, Freq= 0, CH_1, rank 0
5691 12:40:28.809630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5692 12:40:28.809732 ==
5693 12:40:28.813031 RX Vref Scan: 1
5694 12:40:28.813164
5695 12:40:28.813260 RX Vref 0 -> 0, step: 1
5696 12:40:28.816876
5697 12:40:28.816983 RX Delay -45 -> 252, step: 4
5698 12:40:28.817076
5699 12:40:28.820158 Set Vref, RX VrefLevel [Byte0]: 52
5700 12:40:28.822922 [Byte1]: 54
5701 12:40:28.827415
5702 12:40:28.827550 Final RX Vref Byte 0 = 52 to rank0
5703 12:40:28.830673 Final RX Vref Byte 1 = 54 to rank0
5704 12:40:28.834058 Final RX Vref Byte 0 = 52 to rank1
5705 12:40:28.837465 Final RX Vref Byte 1 = 54 to rank1==
5706 12:40:28.840884 Dram Type= 6, Freq= 0, CH_1, rank 0
5707 12:40:28.847737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5708 12:40:28.847879 ==
5709 12:40:28.847952 DQS Delay:
5710 12:40:28.848012 DQS0 = 0, DQS1 = 0
5711 12:40:28.850557 DQM Delay:
5712 12:40:28.850649 DQM0 = 103, DQM1 = 99
5713 12:40:28.853954 DQ Delay:
5714 12:40:28.857395 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5715 12:40:28.860922 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =102
5716 12:40:28.864228 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =94
5717 12:40:28.867026 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =106
5718 12:40:28.867150
5719 12:40:28.867258
5720 12:40:28.873850 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c34, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
5721 12:40:28.877201 CH1 RK0: MR19=505, MR18=1C34
5722 12:40:28.883459 CH1_RK0: MR19=0x505, MR18=0x1C34, DQSOSC=405, MR23=63, INC=66, DEC=44
5723 12:40:28.883606
5724 12:40:28.886889 ----->DramcWriteLeveling(PI) begin...
5725 12:40:28.887006 ==
5726 12:40:28.890455 Dram Type= 6, Freq= 0, CH_1, rank 1
5727 12:40:28.893632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 12:40:28.896969 ==
5729 12:40:28.897084 Write leveling (Byte 0): 23 => 23
5730 12:40:28.900513 Write leveling (Byte 1): 28 => 28
5731 12:40:28.903235 DramcWriteLeveling(PI) end<-----
5732 12:40:28.903353
5733 12:40:28.903446 ==
5734 12:40:28.906641 Dram Type= 6, Freq= 0, CH_1, rank 1
5735 12:40:28.913847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5736 12:40:28.913998 ==
5737 12:40:28.914094 [Gating] SW mode calibration
5738 12:40:28.923443 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5739 12:40:28.926848 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5740 12:40:28.933214 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5741 12:40:28.936670 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5742 12:40:28.939874 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5743 12:40:28.946832 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5744 12:40:28.950106 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5745 12:40:28.953302 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5746 12:40:28.956533 0 14 24 | B1->B0 | 2727 3232 | 0 0 | (0 1) (0 1)
5747 12:40:28.963570 0 14 28 | B1->B0 | 2323 2424 | 0 0 | (1 0) (1 0)
5748 12:40:28.966910 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5749 12:40:28.969722 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5750 12:40:28.976391 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5751 12:40:28.980083 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5752 12:40:28.983486 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5753 12:40:28.990149 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5754 12:40:28.993480 0 15 24 | B1->B0 | 3737 2a2a | 1 1 | (0 0) (0 0)
5755 12:40:28.996947 0 15 28 | B1->B0 | 4646 3d3d | 0 0 | (0 0) (0 0)
5756 12:40:29.003353 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5757 12:40:29.006807 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5758 12:40:29.009552 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5759 12:40:29.016510 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5760 12:40:29.019972 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5761 12:40:29.023774 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5762 12:40:29.029918 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5763 12:40:29.033279 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5764 12:40:29.036638 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 12:40:29.043288 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 12:40:29.046679 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 12:40:29.050090 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 12:40:29.056785 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 12:40:29.060128 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 12:40:29.062852 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 12:40:29.069471 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 12:40:29.073040 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 12:40:29.076301 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 12:40:29.083143 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 12:40:29.086160 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 12:40:29.089983 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 12:40:29.092998 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 12:40:29.099934 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5779 12:40:29.102874 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5780 12:40:29.106053 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 12:40:29.109830 Total UI for P1: 0, mck2ui 16
5782 12:40:29.113179 best dqsien dly found for B0: ( 1, 2, 28)
5783 12:40:29.115953 Total UI for P1: 0, mck2ui 16
5784 12:40:29.120045 best dqsien dly found for B1: ( 1, 2, 26)
5785 12:40:29.122781 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5786 12:40:29.126143 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5787 12:40:29.126277
5788 12:40:29.132979 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5789 12:40:29.136269 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5790 12:40:29.139493 [Gating] SW calibration Done
5791 12:40:29.139602 ==
5792 12:40:29.142921 Dram Type= 6, Freq= 0, CH_1, rank 1
5793 12:40:29.146290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5794 12:40:29.146417 ==
5795 12:40:29.146510 RX Vref Scan: 0
5796 12:40:29.146599
5797 12:40:29.149376 RX Vref 0 -> 0, step: 1
5798 12:40:29.149468
5799 12:40:29.152617 RX Delay -80 -> 252, step: 8
5800 12:40:29.156118 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5801 12:40:29.159525 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5802 12:40:29.162898 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5803 12:40:29.169626 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5804 12:40:29.173048 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5805 12:40:29.175944 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5806 12:40:29.179153 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5807 12:40:29.182564 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5808 12:40:29.186004 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5809 12:40:29.192481 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5810 12:40:29.196006 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5811 12:40:29.199438 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5812 12:40:29.202359 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5813 12:40:29.205869 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5814 12:40:29.212551 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5815 12:40:29.215939 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5816 12:40:29.216071 ==
5817 12:40:29.218964 Dram Type= 6, Freq= 0, CH_1, rank 1
5818 12:40:29.222688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5819 12:40:29.222803 ==
5820 12:40:29.226039 DQS Delay:
5821 12:40:29.226146 DQS0 = 0, DQS1 = 0
5822 12:40:29.226212 DQM Delay:
5823 12:40:29.229519 DQM0 = 101, DQM1 = 99
5824 12:40:29.229614 DQ Delay:
5825 12:40:29.232777 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =95
5826 12:40:29.235619 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =99
5827 12:40:29.239024 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5828 12:40:29.242352 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5829 12:40:29.242475
5830 12:40:29.242540
5831 12:40:29.245825 ==
5832 12:40:29.245920 Dram Type= 6, Freq= 0, CH_1, rank 1
5833 12:40:29.252663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5834 12:40:29.252794 ==
5835 12:40:29.252866
5836 12:40:29.252926
5837 12:40:29.255960 TX Vref Scan disable
5838 12:40:29.256051 == TX Byte 0 ==
5839 12:40:29.259216 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5840 12:40:29.265947 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5841 12:40:29.266081 == TX Byte 1 ==
5842 12:40:29.269366 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5843 12:40:29.275504 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5844 12:40:29.275629 ==
5845 12:40:29.278954 Dram Type= 6, Freq= 0, CH_1, rank 1
5846 12:40:29.282329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5847 12:40:29.282429 ==
5848 12:40:29.282493
5849 12:40:29.282551
5850 12:40:29.285739 TX Vref Scan disable
5851 12:40:29.289044 == TX Byte 0 ==
5852 12:40:29.292424 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5853 12:40:29.295938 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5854 12:40:29.299325 == TX Byte 1 ==
5855 12:40:29.302680 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5856 12:40:29.305866 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5857 12:40:29.305981
5858 12:40:29.306064 [DATLAT]
5859 12:40:29.309302 Freq=933, CH1 RK1
5860 12:40:29.309413
5861 12:40:29.309478 DATLAT Default: 0xb
5862 12:40:29.312581 0, 0xFFFF, sum = 0
5863 12:40:29.316051 1, 0xFFFF, sum = 0
5864 12:40:29.316190 2, 0xFFFF, sum = 0
5865 12:40:29.318832 3, 0xFFFF, sum = 0
5866 12:40:29.318924 4, 0xFFFF, sum = 0
5867 12:40:29.322956 5, 0xFFFF, sum = 0
5868 12:40:29.323065 6, 0xFFFF, sum = 0
5869 12:40:29.325974 7, 0xFFFF, sum = 0
5870 12:40:29.326079 8, 0xFFFF, sum = 0
5871 12:40:29.329079 9, 0xFFFF, sum = 0
5872 12:40:29.329178 10, 0x0, sum = 1
5873 12:40:29.332389 11, 0x0, sum = 2
5874 12:40:29.332502 12, 0x0, sum = 3
5875 12:40:29.332594 13, 0x0, sum = 4
5876 12:40:29.335806 best_step = 11
5877 12:40:29.335896
5878 12:40:29.335987 ==
5879 12:40:29.339319 Dram Type= 6, Freq= 0, CH_1, rank 1
5880 12:40:29.342591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5881 12:40:29.342700 ==
5882 12:40:29.346195 RX Vref Scan: 0
5883 12:40:29.346302
5884 12:40:29.346391 RX Vref 0 -> 0, step: 1
5885 12:40:29.349054
5886 12:40:29.349134 RX Delay -45 -> 252, step: 4
5887 12:40:29.356686 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5888 12:40:29.359914 iDelay=203, Bit 1, Center 98 (15 ~ 182) 168
5889 12:40:29.363177 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5890 12:40:29.366459 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5891 12:40:29.369798 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5892 12:40:29.376398 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5893 12:40:29.379710 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5894 12:40:29.383227 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5895 12:40:29.386816 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5896 12:40:29.390102 iDelay=203, Bit 9, Center 90 (3 ~ 178) 176
5897 12:40:29.393423 iDelay=203, Bit 10, Center 102 (19 ~ 186) 168
5898 12:40:29.400441 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5899 12:40:29.403162 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5900 12:40:29.406670 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5901 12:40:29.410080 iDelay=203, Bit 14, Center 106 (27 ~ 186) 160
5902 12:40:29.416705 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5903 12:40:29.416836 ==
5904 12:40:29.419979 Dram Type= 6, Freq= 0, CH_1, rank 1
5905 12:40:29.423569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5906 12:40:29.423678 ==
5907 12:40:29.423768 DQS Delay:
5908 12:40:29.426927 DQS0 = 0, DQS1 = 0
5909 12:40:29.427022 DQM Delay:
5910 12:40:29.429679 DQM0 = 104, DQM1 = 100
5911 12:40:29.429804 DQ Delay:
5912 12:40:29.433002 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =100
5913 12:40:29.436324 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =102
5914 12:40:29.439826 DQ8 =88, DQ9 =90, DQ10 =102, DQ11 =92
5915 12:40:29.443234 DQ12 =110, DQ13 =106, DQ14 =106, DQ15 =108
5916 12:40:29.443350
5917 12:40:29.443448
5918 12:40:29.453035 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d00, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 407 ps
5919 12:40:29.456577 CH1 RK1: MR19=505, MR18=2D00
5920 12:40:29.460030 CH1_RK1: MR19=0x505, MR18=0x2D00, DQSOSC=407, MR23=63, INC=65, DEC=43
5921 12:40:29.463474 [RxdqsGatingPostProcess] freq 933
5922 12:40:29.469415 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5923 12:40:29.472923 best DQS0 dly(2T, 0.5T) = (0, 10)
5924 12:40:29.476279 best DQS1 dly(2T, 0.5T) = (0, 10)
5925 12:40:29.479554 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5926 12:40:29.482745 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5927 12:40:29.486001 best DQS0 dly(2T, 0.5T) = (0, 10)
5928 12:40:29.489341 best DQS1 dly(2T, 0.5T) = (0, 10)
5929 12:40:29.493185 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5930 12:40:29.496296 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5931 12:40:29.496426 Pre-setting of DQS Precalculation
5932 12:40:29.502679 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5933 12:40:29.509808 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5934 12:40:29.515956 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5935 12:40:29.516127
5936 12:40:29.516227
5937 12:40:29.519856 [Calibration Summary] 1866 Mbps
5938 12:40:29.523165 CH 0, Rank 0
5939 12:40:29.523304 SW Impedance : PASS
5940 12:40:29.526489 DUTY Scan : NO K
5941 12:40:29.526594 ZQ Calibration : PASS
5942 12:40:29.529372 Jitter Meter : NO K
5943 12:40:29.532673 CBT Training : PASS
5944 12:40:29.532780 Write leveling : PASS
5945 12:40:29.535887 RX DQS gating : PASS
5946 12:40:29.539254 RX DQ/DQS(RDDQC) : PASS
5947 12:40:29.539377 TX DQ/DQS : PASS
5948 12:40:29.542744 RX DATLAT : PASS
5949 12:40:29.546075 RX DQ/DQS(Engine): PASS
5950 12:40:29.546187 TX OE : NO K
5951 12:40:29.549528 All Pass.
5952 12:40:29.549634
5953 12:40:29.549717 CH 0, Rank 1
5954 12:40:29.552926 SW Impedance : PASS
5955 12:40:29.553067 DUTY Scan : NO K
5956 12:40:29.556274 ZQ Calibration : PASS
5957 12:40:29.559390 Jitter Meter : NO K
5958 12:40:29.559522 CBT Training : PASS
5959 12:40:29.562693 Write leveling : PASS
5960 12:40:29.566233 RX DQS gating : PASS
5961 12:40:29.566348 RX DQ/DQS(RDDQC) : PASS
5962 12:40:29.569625 TX DQ/DQS : PASS
5963 12:40:29.569720 RX DATLAT : PASS
5964 12:40:29.573054 RX DQ/DQS(Engine): PASS
5965 12:40:29.575740 TX OE : NO K
5966 12:40:29.575844 All Pass.
5967 12:40:29.575934
5968 12:40:29.576015 CH 1, Rank 0
5969 12:40:29.579087 SW Impedance : PASS
5970 12:40:29.583075 DUTY Scan : NO K
5971 12:40:29.583196 ZQ Calibration : PASS
5972 12:40:29.585780 Jitter Meter : NO K
5973 12:40:29.589074 CBT Training : PASS
5974 12:40:29.589191 Write leveling : PASS
5975 12:40:29.592463 RX DQS gating : PASS
5976 12:40:29.595771 RX DQ/DQS(RDDQC) : PASS
5977 12:40:29.595892 TX DQ/DQS : PASS
5978 12:40:29.599334 RX DATLAT : PASS
5979 12:40:29.603142 RX DQ/DQS(Engine): PASS
5980 12:40:29.603282 TX OE : NO K
5981 12:40:29.606039 All Pass.
5982 12:40:29.606133
5983 12:40:29.606199 CH 1, Rank 1
5984 12:40:29.609539 SW Impedance : PASS
5985 12:40:29.609639 DUTY Scan : NO K
5986 12:40:29.612725 ZQ Calibration : PASS
5987 12:40:29.616139 Jitter Meter : NO K
5988 12:40:29.616300 CBT Training : PASS
5989 12:40:29.619493 Write leveling : PASS
5990 12:40:29.619629 RX DQS gating : PASS
5991 12:40:29.622718 RX DQ/DQS(RDDQC) : PASS
5992 12:40:29.626269 TX DQ/DQS : PASS
5993 12:40:29.626429 RX DATLAT : PASS
5994 12:40:29.629486 RX DQ/DQS(Engine): PASS
5995 12:40:29.632916 TX OE : NO K
5996 12:40:29.633053 All Pass.
5997 12:40:29.633162
5998 12:40:29.636069 DramC Write-DBI off
5999 12:40:29.636192 PER_BANK_REFRESH: Hybrid Mode
6000 12:40:29.639277 TX_TRACKING: ON
6001 12:40:29.648965 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6002 12:40:29.652386 [FAST_K] Save calibration result to emmc
6003 12:40:29.655832 dramc_set_vcore_voltage set vcore to 650000
6004 12:40:29.655977 Read voltage for 400, 6
6005 12:40:29.659164 Vio18 = 0
6006 12:40:29.659289 Vcore = 650000
6007 12:40:29.659387 Vdram = 0
6008 12:40:29.662484 Vddq = 0
6009 12:40:29.662601 Vmddr = 0
6010 12:40:29.666017 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6011 12:40:29.672671 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6012 12:40:29.676119 MEM_TYPE=3, freq_sel=20
6013 12:40:29.678817 sv_algorithm_assistance_LP4_800
6014 12:40:29.682287 ============ PULL DRAM RESETB DOWN ============
6015 12:40:29.685686 ========== PULL DRAM RESETB DOWN end =========
6016 12:40:29.692267 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6017 12:40:29.692452 ===================================
6018 12:40:29.696205 LPDDR4 DRAM CONFIGURATION
6019 12:40:29.698990 ===================================
6020 12:40:29.702569 EX_ROW_EN[0] = 0x0
6021 12:40:29.702731 EX_ROW_EN[1] = 0x0
6022 12:40:29.705906 LP4Y_EN = 0x0
6023 12:40:29.706034 WORK_FSP = 0x0
6024 12:40:29.709357 WL = 0x2
6025 12:40:29.709477 RL = 0x2
6026 12:40:29.712700 BL = 0x2
6027 12:40:29.712799 RPST = 0x0
6028 12:40:29.716129 RD_PRE = 0x0
6029 12:40:29.718923 WR_PRE = 0x1
6030 12:40:29.719059 WR_PST = 0x0
6031 12:40:29.722317 DBI_WR = 0x0
6032 12:40:29.722467 DBI_RD = 0x0
6033 12:40:29.725715 OTF = 0x1
6034 12:40:29.728948 ===================================
6035 12:40:29.732900 ===================================
6036 12:40:29.733083 ANA top config
6037 12:40:29.736394 ===================================
6038 12:40:29.739184 DLL_ASYNC_EN = 0
6039 12:40:29.739338 ALL_SLAVE_EN = 1
6040 12:40:29.742656 NEW_RANK_MODE = 1
6041 12:40:29.745701 DLL_IDLE_MODE = 1
6042 12:40:29.749538 LP45_APHY_COMB_EN = 1
6043 12:40:29.752368 TX_ODT_DIS = 1
6044 12:40:29.752475 NEW_8X_MODE = 1
6045 12:40:29.756030 ===================================
6046 12:40:29.758920 ===================================
6047 12:40:29.762559 data_rate = 800
6048 12:40:29.765554 CKR = 1
6049 12:40:29.768954 DQ_P2S_RATIO = 4
6050 12:40:29.772242 ===================================
6051 12:40:29.775358 CA_P2S_RATIO = 4
6052 12:40:29.779098 DQ_CA_OPEN = 0
6053 12:40:29.779247 DQ_SEMI_OPEN = 1
6054 12:40:29.782283 CA_SEMI_OPEN = 1
6055 12:40:29.785810 CA_FULL_RATE = 0
6056 12:40:29.789167 DQ_CKDIV4_EN = 0
6057 12:40:29.792554 CA_CKDIV4_EN = 1
6058 12:40:29.795937 CA_PREDIV_EN = 0
6059 12:40:29.796089 PH8_DLY = 0
6060 12:40:29.799284 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6061 12:40:29.802690 DQ_AAMCK_DIV = 0
6062 12:40:29.805488 CA_AAMCK_DIV = 0
6063 12:40:29.808988 CA_ADMCK_DIV = 4
6064 12:40:29.812420 DQ_TRACK_CA_EN = 0
6065 12:40:29.812550 CA_PICK = 800
6066 12:40:29.815917 CA_MCKIO = 400
6067 12:40:29.819503 MCKIO_SEMI = 400
6068 12:40:29.822248 PLL_FREQ = 3016
6069 12:40:29.825527 DQ_UI_PI_RATIO = 32
6070 12:40:29.829160 CA_UI_PI_RATIO = 32
6071 12:40:29.832468 ===================================
6072 12:40:29.835743 ===================================
6073 12:40:29.835891 memory_type:LPDDR4
6074 12:40:29.839196 GP_NUM : 10
6075 12:40:29.842637 SRAM_EN : 1
6076 12:40:29.842768 MD32_EN : 0
6077 12:40:29.845969 ===================================
6078 12:40:29.849315 [ANA_INIT] >>>>>>>>>>>>>>
6079 12:40:29.852561 <<<<<< [CONFIGURE PHASE]: ANA_TX
6080 12:40:29.855803 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6081 12:40:29.859104 ===================================
6082 12:40:29.862487 data_rate = 800,PCW = 0X7400
6083 12:40:29.865942 ===================================
6084 12:40:29.868692 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6085 12:40:29.872104 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6086 12:40:29.885319 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6087 12:40:29.888724 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6088 12:40:29.892164 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6089 12:40:29.895451 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6090 12:40:29.898745 [ANA_INIT] flow start
6091 12:40:29.902153 [ANA_INIT] PLL >>>>>>>>
6092 12:40:29.902305 [ANA_INIT] PLL <<<<<<<<
6093 12:40:29.905326 [ANA_INIT] MIDPI >>>>>>>>
6094 12:40:29.908818 [ANA_INIT] MIDPI <<<<<<<<
6095 12:40:29.908949 [ANA_INIT] DLL >>>>>>>>
6096 12:40:29.912160 [ANA_INIT] flow end
6097 12:40:29.915223 ============ LP4 DIFF to SE enter ============
6098 12:40:29.918638 ============ LP4 DIFF to SE exit ============
6099 12:40:29.922140 [ANA_INIT] <<<<<<<<<<<<<
6100 12:40:29.925513 [Flow] Enable top DCM control >>>>>
6101 12:40:29.929016 [Flow] Enable top DCM control <<<<<
6102 12:40:29.932279 Enable DLL master slave shuffle
6103 12:40:29.938483 ==============================================================
6104 12:40:29.938645 Gating Mode config
6105 12:40:29.945380 ==============================================================
6106 12:40:29.945518 Config description:
6107 12:40:29.955685 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6108 12:40:29.962323 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6109 12:40:29.969047 SELPH_MODE 0: By rank 1: By Phase
6110 12:40:29.971792 ==============================================================
6111 12:40:29.975289 GAT_TRACK_EN = 0
6112 12:40:29.978714 RX_GATING_MODE = 2
6113 12:40:29.982130 RX_GATING_TRACK_MODE = 2
6114 12:40:29.985430 SELPH_MODE = 1
6115 12:40:29.988722 PICG_EARLY_EN = 1
6116 12:40:29.992157 VALID_LAT_VALUE = 1
6117 12:40:29.998426 ==============================================================
6118 12:40:30.001709 Enter into Gating configuration >>>>
6119 12:40:30.005087 Exit from Gating configuration <<<<
6120 12:40:30.005220 Enter into DVFS_PRE_config >>>>>
6121 12:40:30.018663 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6122 12:40:30.022024 Exit from DVFS_PRE_config <<<<<
6123 12:40:30.024807 Enter into PICG configuration >>>>
6124 12:40:30.028611 Exit from PICG configuration <<<<
6125 12:40:30.028736 [RX_INPUT] configuration >>>>>
6126 12:40:30.031630 [RX_INPUT] configuration <<<<<
6127 12:40:30.038359 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6128 12:40:30.045045 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6129 12:40:30.048357 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6130 12:40:30.055066 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6131 12:40:30.061290 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6132 12:40:30.068239 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6133 12:40:30.071547 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6134 12:40:30.074955 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6135 12:40:30.080996 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6136 12:40:30.084355 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6137 12:40:30.087876 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6138 12:40:30.094811 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6139 12:40:30.097467 ===================================
6140 12:40:30.097608 LPDDR4 DRAM CONFIGURATION
6141 12:40:30.100926 ===================================
6142 12:40:30.104217 EX_ROW_EN[0] = 0x0
6143 12:40:30.104395 EX_ROW_EN[1] = 0x0
6144 12:40:30.107481 LP4Y_EN = 0x0
6145 12:40:30.107599 WORK_FSP = 0x0
6146 12:40:30.110864 WL = 0x2
6147 12:40:30.114141 RL = 0x2
6148 12:40:30.114301 BL = 0x2
6149 12:40:30.117563 RPST = 0x0
6150 12:40:30.117705 RD_PRE = 0x0
6151 12:40:30.120906 WR_PRE = 0x1
6152 12:40:30.121034 WR_PST = 0x0
6153 12:40:30.124303 DBI_WR = 0x0
6154 12:40:30.124426 DBI_RD = 0x0
6155 12:40:30.127736 OTF = 0x1
6156 12:40:30.130949 ===================================
6157 12:40:30.134303 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6158 12:40:30.137705 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6159 12:40:30.141149 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6160 12:40:30.143930 ===================================
6161 12:40:30.147183 LPDDR4 DRAM CONFIGURATION
6162 12:40:30.150413 ===================================
6163 12:40:30.153880 EX_ROW_EN[0] = 0x10
6164 12:40:30.154030 EX_ROW_EN[1] = 0x0
6165 12:40:30.157510 LP4Y_EN = 0x0
6166 12:40:30.157652 WORK_FSP = 0x0
6167 12:40:30.160611 WL = 0x2
6168 12:40:30.160740 RL = 0x2
6169 12:40:30.163707 BL = 0x2
6170 12:40:30.167595 RPST = 0x0
6171 12:40:30.167740 RD_PRE = 0x0
6172 12:40:30.170670 WR_PRE = 0x1
6173 12:40:30.170794 WR_PST = 0x0
6174 12:40:30.174150 DBI_WR = 0x0
6175 12:40:30.174307 DBI_RD = 0x0
6176 12:40:30.176830 OTF = 0x1
6177 12:40:30.180569 ===================================
6178 12:40:30.183698 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6179 12:40:30.189664 nWR fixed to 30
6180 12:40:30.192349 [ModeRegInit_LP4] CH0 RK0
6181 12:40:30.192455 [ModeRegInit_LP4] CH0 RK1
6182 12:40:30.195909 [ModeRegInit_LP4] CH1 RK0
6183 12:40:30.199094 [ModeRegInit_LP4] CH1 RK1
6184 12:40:30.199232 match AC timing 19
6185 12:40:30.206016 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6186 12:40:30.209173 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6187 12:40:30.212569 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6188 12:40:30.219235 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6189 12:40:30.222574 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6190 12:40:30.222742 ==
6191 12:40:30.226030 Dram Type= 6, Freq= 0, CH_0, rank 0
6192 12:40:30.229587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6193 12:40:30.229746 ==
6194 12:40:30.236182 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6195 12:40:30.242830 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6196 12:40:30.246266 [CA 0] Center 36 (8~64) winsize 57
6197 12:40:30.248989 [CA 1] Center 36 (8~64) winsize 57
6198 12:40:30.249138 [CA 2] Center 36 (8~64) winsize 57
6199 12:40:30.252498 [CA 3] Center 36 (8~64) winsize 57
6200 12:40:30.255759 [CA 4] Center 36 (8~64) winsize 57
6201 12:40:30.258908 [CA 5] Center 36 (8~64) winsize 57
6202 12:40:30.259067
6203 12:40:30.262311 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6204 12:40:30.265637
6205 12:40:30.268931 [CATrainingPosCal] consider 1 rank data
6206 12:40:30.269094 u2DelayCellTimex100 = 270/100 ps
6207 12:40:30.275683 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6208 12:40:30.278993 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6209 12:40:30.282386 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6210 12:40:30.285765 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6211 12:40:30.289300 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6212 12:40:30.292669 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 12:40:30.292835
6214 12:40:30.295955 CA PerBit enable=1, Macro0, CA PI delay=36
6215 12:40:30.296083
6216 12:40:30.299235 [CBTSetCACLKResult] CA Dly = 36
6217 12:40:30.302874 CS Dly: 1 (0~32)
6218 12:40:30.303007 ==
6219 12:40:30.306008 Dram Type= 6, Freq= 0, CH_0, rank 1
6220 12:40:30.308890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6221 12:40:30.309014 ==
6222 12:40:30.315615 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6223 12:40:30.319336 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6224 12:40:30.322691 [CA 0] Center 36 (8~64) winsize 57
6225 12:40:30.325805 [CA 1] Center 36 (8~64) winsize 57
6226 12:40:30.329231 [CA 2] Center 36 (8~64) winsize 57
6227 12:40:30.332266 [CA 3] Center 36 (8~64) winsize 57
6228 12:40:30.335487 [CA 4] Center 36 (8~64) winsize 57
6229 12:40:30.338908 [CA 5] Center 36 (8~64) winsize 57
6230 12:40:30.339044
6231 12:40:30.342045 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6232 12:40:30.342137
6233 12:40:30.345400 [CATrainingPosCal] consider 2 rank data
6234 12:40:30.348813 u2DelayCellTimex100 = 270/100 ps
6235 12:40:30.352271 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6236 12:40:30.355738 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6237 12:40:30.359160 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6238 12:40:30.365768 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 12:40:30.369063 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 12:40:30.372487 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 12:40:30.372662
6242 12:40:30.375860 CA PerBit enable=1, Macro0, CA PI delay=36
6243 12:40:30.376010
6244 12:40:30.379333 [CBTSetCACLKResult] CA Dly = 36
6245 12:40:30.379459 CS Dly: 1 (0~32)
6246 12:40:30.379553
6247 12:40:30.381993 ----->DramcWriteLeveling(PI) begin...
6248 12:40:30.382120 ==
6249 12:40:30.385934 Dram Type= 6, Freq= 0, CH_0, rank 0
6250 12:40:30.392054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6251 12:40:30.392230 ==
6252 12:40:30.395483 Write leveling (Byte 0): 40 => 8
6253 12:40:30.395653 Write leveling (Byte 1): 40 => 8
6254 12:40:30.398911 DramcWriteLeveling(PI) end<-----
6255 12:40:30.399063
6256 12:40:30.399171 ==
6257 12:40:30.402474 Dram Type= 6, Freq= 0, CH_0, rank 0
6258 12:40:30.408667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6259 12:40:30.408802 ==
6260 12:40:30.412129 [Gating] SW mode calibration
6261 12:40:30.418810 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6262 12:40:30.422277 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6263 12:40:30.428831 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6264 12:40:30.432027 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6265 12:40:30.435149 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6266 12:40:30.441834 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6267 12:40:30.445426 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6268 12:40:30.448801 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6269 12:40:30.455320 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6270 12:40:30.458752 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6271 12:40:30.461909 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6272 12:40:30.465147 Total UI for P1: 0, mck2ui 16
6273 12:40:30.468775 best dqsien dly found for B0: ( 0, 14, 24)
6274 12:40:30.471834 Total UI for P1: 0, mck2ui 16
6275 12:40:30.475559 best dqsien dly found for B1: ( 0, 14, 24)
6276 12:40:30.478901 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6277 12:40:30.482262 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6278 12:40:30.482390
6279 12:40:30.485142 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6280 12:40:30.491680 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6281 12:40:30.491826 [Gating] SW calibration Done
6282 12:40:30.491926 ==
6283 12:40:30.495022 Dram Type= 6, Freq= 0, CH_0, rank 0
6284 12:40:30.501853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6285 12:40:30.501993 ==
6286 12:40:30.502093 RX Vref Scan: 0
6287 12:40:30.502176
6288 12:40:30.505290 RX Vref 0 -> 0, step: 1
6289 12:40:30.505390
6290 12:40:30.508581 RX Delay -410 -> 252, step: 16
6291 12:40:30.511395 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6292 12:40:30.514735 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6293 12:40:30.521555 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6294 12:40:30.524953 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6295 12:40:30.528544 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6296 12:40:30.531828 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6297 12:40:30.538593 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6298 12:40:30.541976 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6299 12:40:30.545268 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6300 12:40:30.548042 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6301 12:40:30.554911 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6302 12:40:30.558169 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6303 12:40:30.561481 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6304 12:40:30.564896 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6305 12:40:30.571796 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6306 12:40:30.574882 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6307 12:40:30.574989 ==
6308 12:40:30.578475 Dram Type= 6, Freq= 0, CH_0, rank 0
6309 12:40:30.581623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6310 12:40:30.581722 ==
6311 12:40:30.584935 DQS Delay:
6312 12:40:30.585026 DQS0 = 27, DQS1 = 35
6313 12:40:30.587897 DQM Delay:
6314 12:40:30.587980 DQM0 = 10, DQM1 = 11
6315 12:40:30.588042 DQ Delay:
6316 12:40:30.591411 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6317 12:40:30.594869 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =16
6318 12:40:30.598057 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6319 12:40:30.601345 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6320 12:40:30.601461
6321 12:40:30.601527
6322 12:40:30.601586 ==
6323 12:40:30.604490 Dram Type= 6, Freq= 0, CH_0, rank 0
6324 12:40:30.611268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 12:40:30.611408 ==
6326 12:40:30.611479
6327 12:40:30.611539
6328 12:40:30.611596 TX Vref Scan disable
6329 12:40:30.614650 == TX Byte 0 ==
6330 12:40:30.618006 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6331 12:40:30.621534 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6332 12:40:30.624857 == TX Byte 1 ==
6333 12:40:30.628227 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6334 12:40:30.631003 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6335 12:40:30.631110 ==
6336 12:40:30.634485 Dram Type= 6, Freq= 0, CH_0, rank 0
6337 12:40:30.641190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6338 12:40:30.641330 ==
6339 12:40:30.641398
6340 12:40:30.641458
6341 12:40:30.641514 TX Vref Scan disable
6342 12:40:30.644695 == TX Byte 0 ==
6343 12:40:30.648063 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6344 12:40:30.651436 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6345 12:40:30.654996 == TX Byte 1 ==
6346 12:40:30.658317 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6347 12:40:30.661649 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6348 12:40:30.661749
6349 12:40:30.665066 [DATLAT]
6350 12:40:30.665155 Freq=400, CH0 RK0
6351 12:40:30.665221
6352 12:40:30.668237 DATLAT Default: 0xf
6353 12:40:30.668338 0, 0xFFFF, sum = 0
6354 12:40:30.671582 1, 0xFFFF, sum = 0
6355 12:40:30.671671 2, 0xFFFF, sum = 0
6356 12:40:30.674367 3, 0xFFFF, sum = 0
6357 12:40:30.674454 4, 0xFFFF, sum = 0
6358 12:40:30.677766 5, 0xFFFF, sum = 0
6359 12:40:30.677852 6, 0xFFFF, sum = 0
6360 12:40:30.681147 7, 0xFFFF, sum = 0
6361 12:40:30.681235 8, 0xFFFF, sum = 0
6362 12:40:30.684618 9, 0xFFFF, sum = 0
6363 12:40:30.684710 10, 0xFFFF, sum = 0
6364 12:40:30.688092 11, 0xFFFF, sum = 0
6365 12:40:30.691505 12, 0xFFFF, sum = 0
6366 12:40:30.691601 13, 0x0, sum = 1
6367 12:40:30.691668 14, 0x0, sum = 2
6368 12:40:30.694765 15, 0x0, sum = 3
6369 12:40:30.694853 16, 0x0, sum = 4
6370 12:40:30.697525 best_step = 14
6371 12:40:30.697615
6372 12:40:30.697681 ==
6373 12:40:30.701441 Dram Type= 6, Freq= 0, CH_0, rank 0
6374 12:40:30.704598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6375 12:40:30.704688 ==
6376 12:40:30.707629 RX Vref Scan: 1
6377 12:40:30.707717
6378 12:40:30.707799 RX Vref 0 -> 0, step: 1
6379 12:40:30.707862
6380 12:40:30.710803 RX Delay -311 -> 252, step: 8
6381 12:40:30.710914
6382 12:40:30.714270 Set Vref, RX VrefLevel [Byte0]: 55
6383 12:40:30.717471 [Byte1]: 47
6384 12:40:30.722661
6385 12:40:30.722783 Final RX Vref Byte 0 = 55 to rank0
6386 12:40:30.725940 Final RX Vref Byte 1 = 47 to rank0
6387 12:40:30.729008 Final RX Vref Byte 0 = 55 to rank1
6388 12:40:30.732722 Final RX Vref Byte 1 = 47 to rank1==
6389 12:40:30.735797 Dram Type= 6, Freq= 0, CH_0, rank 0
6390 12:40:30.742585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6391 12:40:30.742708 ==
6392 12:40:30.742776 DQS Delay:
6393 12:40:30.745939 DQS0 = 28, DQS1 = 36
6394 12:40:30.746027 DQM Delay:
6395 12:40:30.746092 DQM0 = 11, DQM1 = 12
6396 12:40:30.749229 DQ Delay:
6397 12:40:30.752709 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6398 12:40:30.752805 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6399 12:40:30.755993 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6400 12:40:30.759296 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6401 12:40:30.759392
6402 12:40:30.759458
6403 12:40:30.769318 [DQSOSCAuto] RK0, (LSB)MR18= 0xd0bc, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6404 12:40:30.772786 CH0 RK0: MR19=C0C, MR18=D0BC
6405 12:40:30.779425 CH0_RK0: MR19=0xC0C, MR18=0xD0BC, DQSOSC=384, MR23=63, INC=400, DEC=267
6406 12:40:30.779569 ==
6407 12:40:30.782856 Dram Type= 6, Freq= 0, CH_0, rank 1
6408 12:40:30.785595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6409 12:40:30.785687 ==
6410 12:40:30.788933 [Gating] SW mode calibration
6411 12:40:30.795878 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6412 12:40:30.799276 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6413 12:40:30.805970 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6414 12:40:30.809188 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6415 12:40:30.812541 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6416 12:40:30.819420 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6417 12:40:30.822074 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6418 12:40:30.825525 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6419 12:40:30.832244 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6420 12:40:30.835566 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6421 12:40:30.838739 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6422 12:40:30.842523 Total UI for P1: 0, mck2ui 16
6423 12:40:30.845748 best dqsien dly found for B0: ( 0, 14, 24)
6424 12:40:30.848745 Total UI for P1: 0, mck2ui 16
6425 12:40:30.852340 best dqsien dly found for B1: ( 0, 14, 24)
6426 12:40:30.855923 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6427 12:40:30.859024 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6428 12:40:30.862236
6429 12:40:30.865410 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6430 12:40:30.868647 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6431 12:40:30.871943 [Gating] SW calibration Done
6432 12:40:30.872035 ==
6433 12:40:30.875412 Dram Type= 6, Freq= 0, CH_0, rank 1
6434 12:40:30.878821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6435 12:40:30.878929 ==
6436 12:40:30.879004 RX Vref Scan: 0
6437 12:40:30.879064
6438 12:40:30.881966 RX Vref 0 -> 0, step: 1
6439 12:40:30.882058
6440 12:40:30.885551 RX Delay -410 -> 252, step: 16
6441 12:40:30.888781 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6442 12:40:30.895472 iDelay=230, Bit 1, Center -11 (-234 ~ 213) 448
6443 12:40:30.898995 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6444 12:40:30.901843 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6445 12:40:30.905277 iDelay=230, Bit 4, Center -3 (-234 ~ 229) 464
6446 12:40:30.912040 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6447 12:40:30.915319 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6448 12:40:30.918687 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6449 12:40:30.922259 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6450 12:40:30.925541 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6451 12:40:30.932150 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6452 12:40:30.935693 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6453 12:40:30.939047 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6454 12:40:30.942430 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6455 12:40:30.948561 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6456 12:40:30.952064 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6457 12:40:30.952169 ==
6458 12:40:30.955459 Dram Type= 6, Freq= 0, CH_0, rank 1
6459 12:40:30.958740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6460 12:40:30.958836 ==
6461 12:40:30.962148 DQS Delay:
6462 12:40:30.962238 DQS0 = 19, DQS1 = 35
6463 12:40:30.965479 DQM Delay:
6464 12:40:30.965574 DQM0 = 7, DQM1 = 13
6465 12:40:30.965663 DQ Delay:
6466 12:40:30.968898 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6467 12:40:30.972212 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6468 12:40:30.975526 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6469 12:40:30.978691 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6470 12:40:30.978784
6471 12:40:30.978848
6472 12:40:30.978907 ==
6473 12:40:30.981895 Dram Type= 6, Freq= 0, CH_0, rank 1
6474 12:40:30.988341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 12:40:30.988453 ==
6476 12:40:30.988521
6477 12:40:30.988581
6478 12:40:30.988639 TX Vref Scan disable
6479 12:40:30.991520 == TX Byte 0 ==
6480 12:40:30.995242 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6481 12:40:30.998332 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6482 12:40:31.001696 == TX Byte 1 ==
6483 12:40:31.005040 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6484 12:40:31.008567 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6485 12:40:31.011608 ==
6486 12:40:31.015061 Dram Type= 6, Freq= 0, CH_0, rank 1
6487 12:40:31.018321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6488 12:40:31.018435 ==
6489 12:40:31.018537
6490 12:40:31.018637
6491 12:40:31.021626 TX Vref Scan disable
6492 12:40:31.021731 == TX Byte 0 ==
6493 12:40:31.025140 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6494 12:40:31.031325 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6495 12:40:31.031462 == TX Byte 1 ==
6496 12:40:31.034714 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6497 12:40:31.041618 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6498 12:40:31.041757
6499 12:40:31.041857 [DATLAT]
6500 12:40:31.041959 Freq=400, CH0 RK1
6501 12:40:31.042057
6502 12:40:31.045065 DATLAT Default: 0xe
6503 12:40:31.048419 0, 0xFFFF, sum = 0
6504 12:40:31.048505 1, 0xFFFF, sum = 0
6505 12:40:31.051833 2, 0xFFFF, sum = 0
6506 12:40:31.051922 3, 0xFFFF, sum = 0
6507 12:40:31.054560 4, 0xFFFF, sum = 0
6508 12:40:31.054658 5, 0xFFFF, sum = 0
6509 12:40:31.058129 6, 0xFFFF, sum = 0
6510 12:40:31.058236 7, 0xFFFF, sum = 0
6511 12:40:31.061459 8, 0xFFFF, sum = 0
6512 12:40:31.061567 9, 0xFFFF, sum = 0
6513 12:40:31.064834 10, 0xFFFF, sum = 0
6514 12:40:31.064915 11, 0xFFFF, sum = 0
6515 12:40:31.068226 12, 0xFFFF, sum = 0
6516 12:40:31.068371 13, 0x0, sum = 1
6517 12:40:31.071349 14, 0x0, sum = 2
6518 12:40:31.071459 15, 0x0, sum = 3
6519 12:40:31.074567 16, 0x0, sum = 4
6520 12:40:31.074667 best_step = 14
6521 12:40:31.074750
6522 12:40:31.074826 ==
6523 12:40:31.078432 Dram Type= 6, Freq= 0, CH_0, rank 1
6524 12:40:31.081762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6525 12:40:31.084556 ==
6526 12:40:31.084648 RX Vref Scan: 0
6527 12:40:31.084731
6528 12:40:31.088080 RX Vref 0 -> 0, step: 1
6529 12:40:31.088188
6530 12:40:31.091237 RX Delay -311 -> 252, step: 8
6531 12:40:31.094631 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6532 12:40:31.101610 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6533 12:40:31.105037 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6534 12:40:31.108214 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6535 12:40:31.111593 iDelay=217, Bit 4, Center -12 (-231 ~ 208) 440
6536 12:40:31.117874 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6537 12:40:31.121101 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6538 12:40:31.125007 iDelay=217, Bit 7, Center -4 (-223 ~ 216) 440
6539 12:40:31.127703 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6540 12:40:31.134850 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6541 12:40:31.138168 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6542 12:40:31.141333 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6543 12:40:31.144724 iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432
6544 12:40:31.151079 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6545 12:40:31.154459 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6546 12:40:31.157849 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6547 12:40:31.157943 ==
6548 12:40:31.161278 Dram Type= 6, Freq= 0, CH_0, rank 1
6549 12:40:31.168030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6550 12:40:31.168137 ==
6551 12:40:31.168203 DQS Delay:
6552 12:40:31.168264 DQS0 = 24, DQS1 = 36
6553 12:40:31.171480 DQM Delay:
6554 12:40:31.171598 DQM0 = 9, DQM1 = 14
6555 12:40:31.174799 DQ Delay:
6556 12:40:31.174887 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6557 12:40:31.178097 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =20
6558 12:40:31.181424 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6559 12:40:31.184725 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6560 12:40:31.184822
6561 12:40:31.184890
6562 12:40:31.194712 [DQSOSCAuto] RK1, (LSB)MR18= 0xbc5c, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6563 12:40:31.198197 CH0 RK1: MR19=C0C, MR18=BC5C
6564 12:40:31.204978 CH0_RK1: MR19=0xC0C, MR18=0xBC5C, DQSOSC=386, MR23=63, INC=396, DEC=264
6565 12:40:31.205104 [RxdqsGatingPostProcess] freq 400
6566 12:40:31.211090 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6567 12:40:31.214507 best DQS0 dly(2T, 0.5T) = (0, 10)
6568 12:40:31.217985 best DQS1 dly(2T, 0.5T) = (0, 10)
6569 12:40:31.221297 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6570 12:40:31.224057 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6571 12:40:31.227448 best DQS0 dly(2T, 0.5T) = (0, 10)
6572 12:40:31.230951 best DQS1 dly(2T, 0.5T) = (0, 10)
6573 12:40:31.234234 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6574 12:40:31.237449 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6575 12:40:31.240736 Pre-setting of DQS Precalculation
6576 12:40:31.243878 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6577 12:40:31.244014 ==
6578 12:40:31.247624 Dram Type= 6, Freq= 0, CH_1, rank 0
6579 12:40:31.250746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6580 12:40:31.254252 ==
6581 12:40:31.257807 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6582 12:40:31.263860 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6583 12:40:31.267511 [CA 0] Center 36 (8~64) winsize 57
6584 12:40:31.271041 [CA 1] Center 36 (8~64) winsize 57
6585 12:40:31.274230 [CA 2] Center 36 (8~64) winsize 57
6586 12:40:31.277866 [CA 3] Center 36 (8~64) winsize 57
6587 12:40:31.281072 [CA 4] Center 36 (8~64) winsize 57
6588 12:40:31.284455 [CA 5] Center 36 (8~64) winsize 57
6589 12:40:31.284566
6590 12:40:31.287637 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6591 12:40:31.287725
6592 12:40:31.290945 [CATrainingPosCal] consider 1 rank data
6593 12:40:31.294122 u2DelayCellTimex100 = 270/100 ps
6594 12:40:31.297340 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6595 12:40:31.300672 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6596 12:40:31.304040 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6597 12:40:31.307526 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6598 12:40:31.310953 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6599 12:40:31.314252 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 12:40:31.314367
6601 12:40:31.317653 CA PerBit enable=1, Macro0, CA PI delay=36
6602 12:40:31.317736
6603 12:40:31.321052 [CBTSetCACLKResult] CA Dly = 36
6604 12:40:31.323775 CS Dly: 1 (0~32)
6605 12:40:31.323879 ==
6606 12:40:31.327551 Dram Type= 6, Freq= 0, CH_1, rank 1
6607 12:40:31.330949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6608 12:40:31.331071 ==
6609 12:40:31.337223 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6610 12:40:31.344044 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6611 12:40:31.347470 [CA 0] Center 36 (8~64) winsize 57
6612 12:40:31.350743 [CA 1] Center 36 (8~64) winsize 57
6613 12:40:31.350867 [CA 2] Center 36 (8~64) winsize 57
6614 12:40:31.354069 [CA 3] Center 36 (8~64) winsize 57
6615 12:40:31.357556 [CA 4] Center 36 (8~64) winsize 57
6616 12:40:31.360974 [CA 5] Center 36 (8~64) winsize 57
6617 12:40:31.361093
6618 12:40:31.363668 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6619 12:40:31.363767
6620 12:40:31.370383 [CATrainingPosCal] consider 2 rank data
6621 12:40:31.370516 u2DelayCellTimex100 = 270/100 ps
6622 12:40:31.377105 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6623 12:40:31.380395 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6624 12:40:31.383766 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6625 12:40:31.387274 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 12:40:31.390232 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 12:40:31.393788 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 12:40:31.393902
6629 12:40:31.397351 CA PerBit enable=1, Macro0, CA PI delay=36
6630 12:40:31.397499
6631 12:40:31.400412 [CBTSetCACLKResult] CA Dly = 36
6632 12:40:31.403914 CS Dly: 1 (0~32)
6633 12:40:31.404016
6634 12:40:31.407020 ----->DramcWriteLeveling(PI) begin...
6635 12:40:31.407108 ==
6636 12:40:31.410268 Dram Type= 6, Freq= 0, CH_1, rank 0
6637 12:40:31.413478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6638 12:40:31.413575 ==
6639 12:40:31.416727 Write leveling (Byte 0): 40 => 8
6640 12:40:31.420171 Write leveling (Byte 1): 40 => 8
6641 12:40:31.423480 DramcWriteLeveling(PI) end<-----
6642 12:40:31.423577
6643 12:40:31.423642 ==
6644 12:40:31.426968 Dram Type= 6, Freq= 0, CH_1, rank 0
6645 12:40:31.430264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6646 12:40:31.430365 ==
6647 12:40:31.433799 [Gating] SW mode calibration
6648 12:40:31.440005 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6649 12:40:31.446951 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6650 12:40:31.450324 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6651 12:40:31.453680 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6652 12:40:31.460091 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6653 12:40:31.463597 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6654 12:40:31.466958 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6655 12:40:31.473612 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6656 12:40:31.476788 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6657 12:40:31.480266 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6658 12:40:31.486344 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6659 12:40:31.486473 Total UI for P1: 0, mck2ui 16
6660 12:40:31.493255 best dqsien dly found for B0: ( 0, 14, 24)
6661 12:40:31.493377 Total UI for P1: 0, mck2ui 16
6662 12:40:31.500010 best dqsien dly found for B1: ( 0, 14, 24)
6663 12:40:31.503367 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6664 12:40:31.506147 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6665 12:40:31.506249
6666 12:40:31.509519 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6667 12:40:31.512864 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6668 12:40:31.516233 [Gating] SW calibration Done
6669 12:40:31.516368 ==
6670 12:40:31.519622 Dram Type= 6, Freq= 0, CH_1, rank 0
6671 12:40:31.523135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6672 12:40:31.523246 ==
6673 12:40:31.526136 RX Vref Scan: 0
6674 12:40:31.526224
6675 12:40:31.526290 RX Vref 0 -> 0, step: 1
6676 12:40:31.526353
6677 12:40:31.529339 RX Delay -410 -> 252, step: 16
6678 12:40:31.536338 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6679 12:40:31.539439 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6680 12:40:31.543118 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6681 12:40:31.546173 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6682 12:40:31.552940 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6683 12:40:31.556430 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6684 12:40:31.559336 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6685 12:40:31.562656 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6686 12:40:31.569178 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6687 12:40:31.572601 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6688 12:40:31.576008 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6689 12:40:31.579331 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6690 12:40:31.586092 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6691 12:40:31.589602 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6692 12:40:31.593140 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6693 12:40:31.596482 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6694 12:40:31.596608 ==
6695 12:40:31.599268 Dram Type= 6, Freq= 0, CH_1, rank 0
6696 12:40:31.606069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6697 12:40:31.606217 ==
6698 12:40:31.606288 DQS Delay:
6699 12:40:31.609445 DQS0 = 35, DQS1 = 35
6700 12:40:31.609550 DQM Delay:
6701 12:40:31.612909 DQM0 = 17, DQM1 = 13
6702 12:40:31.613024 DQ Delay:
6703 12:40:31.616144 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6704 12:40:31.619336 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6705 12:40:31.622623 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6706 12:40:31.626102 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6707 12:40:31.626224
6708 12:40:31.626292
6709 12:40:31.626349 ==
6710 12:40:31.629393 Dram Type= 6, Freq= 0, CH_1, rank 0
6711 12:40:31.632890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 12:40:31.633017 ==
6713 12:40:31.633098
6714 12:40:31.633167
6715 12:40:31.636317 TX Vref Scan disable
6716 12:40:31.636421 == TX Byte 0 ==
6717 12:40:31.642454 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6718 12:40:31.645881 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6719 12:40:31.646007 == TX Byte 1 ==
6720 12:40:31.649546 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6721 12:40:31.655986 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6722 12:40:31.656125 ==
6723 12:40:31.659182 Dram Type= 6, Freq= 0, CH_1, rank 0
6724 12:40:31.662614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6725 12:40:31.662740 ==
6726 12:40:31.662823
6727 12:40:31.662911
6728 12:40:31.666225 TX Vref Scan disable
6729 12:40:31.666337 == TX Byte 0 ==
6730 12:40:31.672786 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6731 12:40:31.675699 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6732 12:40:31.675849 == TX Byte 1 ==
6733 12:40:31.682373 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6734 12:40:31.686124 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6735 12:40:31.686271
6736 12:40:31.686342 [DATLAT]
6737 12:40:31.689040 Freq=400, CH1 RK0
6738 12:40:31.689153
6739 12:40:31.689256 DATLAT Default: 0xf
6740 12:40:31.692840 0, 0xFFFF, sum = 0
6741 12:40:31.692947 1, 0xFFFF, sum = 0
6742 12:40:31.695917 2, 0xFFFF, sum = 0
6743 12:40:31.696037 3, 0xFFFF, sum = 0
6744 12:40:31.699283 4, 0xFFFF, sum = 0
6745 12:40:31.699405 5, 0xFFFF, sum = 0
6746 12:40:31.702846 6, 0xFFFF, sum = 0
6747 12:40:31.702955 7, 0xFFFF, sum = 0
6748 12:40:31.706153 8, 0xFFFF, sum = 0
6749 12:40:31.706234 9, 0xFFFF, sum = 0
6750 12:40:31.709609 10, 0xFFFF, sum = 0
6751 12:40:31.709686 11, 0xFFFF, sum = 0
6752 12:40:31.712295 12, 0xFFFF, sum = 0
6753 12:40:31.712398 13, 0x0, sum = 1
6754 12:40:31.715856 14, 0x0, sum = 2
6755 12:40:31.715971 15, 0x0, sum = 3
6756 12:40:31.719141 16, 0x0, sum = 4
6757 12:40:31.719256 best_step = 14
6758 12:40:31.719349
6759 12:40:31.719437 ==
6760 12:40:31.722536 Dram Type= 6, Freq= 0, CH_1, rank 0
6761 12:40:31.729130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6762 12:40:31.729246 ==
6763 12:40:31.729314 RX Vref Scan: 1
6764 12:40:31.729374
6765 12:40:31.732518 RX Vref 0 -> 0, step: 1
6766 12:40:31.732615
6767 12:40:31.735922 RX Delay -311 -> 252, step: 8
6768 12:40:31.736043
6769 12:40:31.739336 Set Vref, RX VrefLevel [Byte0]: 52
6770 12:40:31.742143 [Byte1]: 54
6771 12:40:31.742269
6772 12:40:31.745611 Final RX Vref Byte 0 = 52 to rank0
6773 12:40:31.748941 Final RX Vref Byte 1 = 54 to rank0
6774 12:40:31.752336 Final RX Vref Byte 0 = 52 to rank1
6775 12:40:31.755918 Final RX Vref Byte 1 = 54 to rank1==
6776 12:40:31.758610 Dram Type= 6, Freq= 0, CH_1, rank 0
6777 12:40:31.762000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6778 12:40:31.765399 ==
6779 12:40:31.765493 DQS Delay:
6780 12:40:31.765601 DQS0 = 32, DQS1 = 32
6781 12:40:31.768824 DQM Delay:
6782 12:40:31.768915 DQM0 = 14, DQM1 = 11
6783 12:40:31.772276 DQ Delay:
6784 12:40:31.772382 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16
6785 12:40:31.775739 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =12
6786 12:40:31.778872 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6787 12:40:31.782150 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6788 12:40:31.782254
6789 12:40:31.782323
6790 12:40:31.792283 [DQSOSCAuto] RK0, (LSB)MR18= 0x97cf, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 390 ps
6791 12:40:31.795329 CH1 RK0: MR19=C0C, MR18=97CF
6792 12:40:31.802188 CH1_RK0: MR19=0xC0C, MR18=0x97CF, DQSOSC=384, MR23=63, INC=400, DEC=267
6793 12:40:31.802336 ==
6794 12:40:31.805406 Dram Type= 6, Freq= 0, CH_1, rank 1
6795 12:40:31.808882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6796 12:40:31.809017 ==
6797 12:40:31.811997 [Gating] SW mode calibration
6798 12:40:31.818852 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6799 12:40:31.821972 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6800 12:40:31.828611 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6801 12:40:31.832085 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6802 12:40:31.835374 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6803 12:40:31.842016 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6804 12:40:31.845494 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6805 12:40:31.848815 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6806 12:40:31.855617 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6807 12:40:31.858964 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6808 12:40:31.862182 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6809 12:40:31.865633 Total UI for P1: 0, mck2ui 16
6810 12:40:31.868373 best dqsien dly found for B0: ( 0, 14, 24)
6811 12:40:31.872454 Total UI for P1: 0, mck2ui 16
6812 12:40:31.875099 best dqsien dly found for B1: ( 0, 14, 24)
6813 12:40:31.878478 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6814 12:40:31.881974 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6815 12:40:31.882067
6816 12:40:31.888169 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6817 12:40:31.891896 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6818 12:40:31.895203 [Gating] SW calibration Done
6819 12:40:31.895331 ==
6820 12:40:31.898644 Dram Type= 6, Freq= 0, CH_1, rank 1
6821 12:40:31.902038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6822 12:40:31.902160 ==
6823 12:40:31.902254 RX Vref Scan: 0
6824 12:40:31.902341
6825 12:40:31.904802 RX Vref 0 -> 0, step: 1
6826 12:40:31.904887
6827 12:40:31.908158 RX Delay -410 -> 252, step: 16
6828 12:40:31.911525 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6829 12:40:31.918443 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6830 12:40:31.921578 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6831 12:40:31.924984 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6832 12:40:31.928037 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6833 12:40:31.934843 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6834 12:40:31.938306 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6835 12:40:31.941313 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6836 12:40:31.944534 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6837 12:40:31.947991 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6838 12:40:31.954713 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6839 12:40:31.958122 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6840 12:40:31.961594 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6841 12:40:31.968407 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6842 12:40:31.971923 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6843 12:40:31.974614 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6844 12:40:31.974732 ==
6845 12:40:31.977910 Dram Type= 6, Freq= 0, CH_1, rank 1
6846 12:40:31.981363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6847 12:40:31.984790 ==
6848 12:40:31.984888 DQS Delay:
6849 12:40:31.984954 DQS0 = 35, DQS1 = 35
6850 12:40:31.988112 DQM Delay:
6851 12:40:31.988214 DQM0 = 17, DQM1 = 14
6852 12:40:31.991395 DQ Delay:
6853 12:40:31.991470 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6854 12:40:31.994768 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6855 12:40:31.998137 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6856 12:40:32.001468 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6857 12:40:32.001597
6858 12:40:32.001692
6859 12:40:32.004280 ==
6860 12:40:32.007791 Dram Type= 6, Freq= 0, CH_1, rank 1
6861 12:40:32.011231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 12:40:32.011345 ==
6863 12:40:32.011442
6864 12:40:32.011528
6865 12:40:32.014637 TX Vref Scan disable
6866 12:40:32.014742 == TX Byte 0 ==
6867 12:40:32.018104 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6868 12:40:32.024691 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6869 12:40:32.024808 == TX Byte 1 ==
6870 12:40:32.027903 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6871 12:40:32.034615 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6872 12:40:32.034755 ==
6873 12:40:32.038138 Dram Type= 6, Freq= 0, CH_1, rank 1
6874 12:40:32.041494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6875 12:40:32.041598 ==
6876 12:40:32.041666
6877 12:40:32.041724
6878 12:40:32.044235 TX Vref Scan disable
6879 12:40:32.044363 == TX Byte 0 ==
6880 12:40:32.047588 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6881 12:40:32.054388 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6882 12:40:32.054505 == TX Byte 1 ==
6883 12:40:32.057891 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6884 12:40:32.064511 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6885 12:40:32.064643
6886 12:40:32.064710 [DATLAT]
6887 12:40:32.067606 Freq=400, CH1 RK1
6888 12:40:32.067686
6889 12:40:32.067754 DATLAT Default: 0xe
6890 12:40:32.071001 0, 0xFFFF, sum = 0
6891 12:40:32.071084 1, 0xFFFF, sum = 0
6892 12:40:32.074342 2, 0xFFFF, sum = 0
6893 12:40:32.074450 3, 0xFFFF, sum = 0
6894 12:40:32.077655 4, 0xFFFF, sum = 0
6895 12:40:32.077732 5, 0xFFFF, sum = 0
6896 12:40:32.080886 6, 0xFFFF, sum = 0
6897 12:40:32.080997 7, 0xFFFF, sum = 0
6898 12:40:32.084221 8, 0xFFFF, sum = 0
6899 12:40:32.084335 9, 0xFFFF, sum = 0
6900 12:40:32.087879 10, 0xFFFF, sum = 0
6901 12:40:32.087997 11, 0xFFFF, sum = 0
6902 12:40:32.091267 12, 0xFFFF, sum = 0
6903 12:40:32.091375 13, 0x0, sum = 1
6904 12:40:32.094720 14, 0x0, sum = 2
6905 12:40:32.094828 15, 0x0, sum = 3
6906 12:40:32.097834 16, 0x0, sum = 4
6907 12:40:32.097920 best_step = 14
6908 12:40:32.097982
6909 12:40:32.098041 ==
6910 12:40:32.101194 Dram Type= 6, Freq= 0, CH_1, rank 1
6911 12:40:32.107717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6912 12:40:32.107857 ==
6913 12:40:32.107959 RX Vref Scan: 0
6914 12:40:32.108063
6915 12:40:32.111155 RX Vref 0 -> 0, step: 1
6916 12:40:32.111230
6917 12:40:32.114586 RX Delay -311 -> 252, step: 8
6918 12:40:32.120833 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6919 12:40:32.124134 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6920 12:40:32.127625 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6921 12:40:32.130921 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6922 12:40:32.138155 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6923 12:40:32.141099 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6924 12:40:32.144516 iDelay=217, Bit 6, Center -4 (-223 ~ 216) 440
6925 12:40:32.147259 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6926 12:40:32.154268 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6927 12:40:32.157644 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6928 12:40:32.160989 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6929 12:40:32.164256 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6930 12:40:32.170757 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6931 12:40:32.174167 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6932 12:40:32.177569 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6933 12:40:32.180482 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6934 12:40:32.184383 ==
6935 12:40:32.184509 Dram Type= 6, Freq= 0, CH_1, rank 1
6936 12:40:32.190672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6937 12:40:32.190806 ==
6938 12:40:32.190901 DQS Delay:
6939 12:40:32.193792 DQS0 = 28, DQS1 = 32
6940 12:40:32.193872 DQM Delay:
6941 12:40:32.197465 DQM0 = 12, DQM1 = 11
6942 12:40:32.197594 DQ Delay:
6943 12:40:32.200584 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6944 12:40:32.203962 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6945 12:40:32.207225 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6946 12:40:32.210376 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6947 12:40:32.210493
6948 12:40:32.210588
6949 12:40:32.217304 [DQSOSCAuto] RK1, (LSB)MR18= 0xc454, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
6950 12:40:32.220635 CH1 RK1: MR19=C0C, MR18=C454
6951 12:40:32.227064 CH1_RK1: MR19=0xC0C, MR18=0xC454, DQSOSC=385, MR23=63, INC=398, DEC=265
6952 12:40:32.230559 [RxdqsGatingPostProcess] freq 400
6953 12:40:32.233967 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6954 12:40:32.237367 best DQS0 dly(2T, 0.5T) = (0, 10)
6955 12:40:32.240160 best DQS1 dly(2T, 0.5T) = (0, 10)
6956 12:40:32.243387 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6957 12:40:32.246706 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6958 12:40:32.250392 best DQS0 dly(2T, 0.5T) = (0, 10)
6959 12:40:32.253934 best DQS1 dly(2T, 0.5T) = (0, 10)
6960 12:40:32.256753 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6961 12:40:32.260071 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6962 12:40:32.263505 Pre-setting of DQS Precalculation
6963 12:40:32.266973 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6964 12:40:32.276550 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6965 12:40:32.283420 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6966 12:40:32.283546
6967 12:40:32.283616
6968 12:40:32.286950 [Calibration Summary] 800 Mbps
6969 12:40:32.287025 CH 0, Rank 0
6970 12:40:32.290300 SW Impedance : PASS
6971 12:40:32.290379 DUTY Scan : NO K
6972 12:40:32.293675 ZQ Calibration : PASS
6973 12:40:32.297121 Jitter Meter : NO K
6974 12:40:32.297235 CBT Training : PASS
6975 12:40:32.300054 Write leveling : PASS
6976 12:40:32.303421 RX DQS gating : PASS
6977 12:40:32.303508 RX DQ/DQS(RDDQC) : PASS
6978 12:40:32.306929 TX DQ/DQS : PASS
6979 12:40:32.307034 RX DATLAT : PASS
6980 12:40:32.310457 RX DQ/DQS(Engine): PASS
6981 12:40:32.313813 TX OE : NO K
6982 12:40:32.313924 All Pass.
6983 12:40:32.314016
6984 12:40:32.314103 CH 0, Rank 1
6985 12:40:32.317159 SW Impedance : PASS
6986 12:40:32.320232 DUTY Scan : NO K
6987 12:40:32.320342 ZQ Calibration : PASS
6988 12:40:32.323886 Jitter Meter : NO K
6989 12:40:32.326765 CBT Training : PASS
6990 12:40:32.326876 Write leveling : NO K
6991 12:40:32.330266 RX DQS gating : PASS
6992 12:40:32.333330 RX DQ/DQS(RDDQC) : PASS
6993 12:40:32.333450 TX DQ/DQS : PASS
6994 12:40:32.337079 RX DATLAT : PASS
6995 12:40:32.339978 RX DQ/DQS(Engine): PASS
6996 12:40:32.340088 TX OE : NO K
6997 12:40:32.340183 All Pass.
6998 12:40:32.343524
6999 12:40:32.343607 CH 1, Rank 0
7000 12:40:32.346923 SW Impedance : PASS
7001 12:40:32.347034 DUTY Scan : NO K
7002 12:40:32.350344 ZQ Calibration : PASS
7003 12:40:32.350461 Jitter Meter : NO K
7004 12:40:32.353469 CBT Training : PASS
7005 12:40:32.356790 Write leveling : PASS
7006 12:40:32.356887 RX DQS gating : PASS
7007 12:40:32.359954 RX DQ/DQS(RDDQC) : PASS
7008 12:40:32.363706 TX DQ/DQS : PASS
7009 12:40:32.363799 RX DATLAT : PASS
7010 12:40:32.367020 RX DQ/DQS(Engine): PASS
7011 12:40:32.369734 TX OE : NO K
7012 12:40:32.369843 All Pass.
7013 12:40:32.369933
7014 12:40:32.370022 CH 1, Rank 1
7015 12:40:32.373221 SW Impedance : PASS
7016 12:40:32.376450 DUTY Scan : NO K
7017 12:40:32.376559 ZQ Calibration : PASS
7018 12:40:32.379865 Jitter Meter : NO K
7019 12:40:32.383093 CBT Training : PASS
7020 12:40:32.383201 Write leveling : NO K
7021 12:40:32.386519 RX DQS gating : PASS
7022 12:40:32.390115 RX DQ/DQS(RDDQC) : PASS
7023 12:40:32.390217 TX DQ/DQS : PASS
7024 12:40:32.393526 RX DATLAT : PASS
7025 12:40:32.396847 RX DQ/DQS(Engine): PASS
7026 12:40:32.396963 TX OE : NO K
7027 12:40:32.399629 All Pass.
7028 12:40:32.399708
7029 12:40:32.399789 DramC Write-DBI off
7030 12:40:32.403130 PER_BANK_REFRESH: Hybrid Mode
7031 12:40:32.403228 TX_TRACKING: ON
7032 12:40:32.413348 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7033 12:40:32.416762 [FAST_K] Save calibration result to emmc
7034 12:40:32.419539 dramc_set_vcore_voltage set vcore to 725000
7035 12:40:32.422979 Read voltage for 1600, 0
7036 12:40:32.423089 Vio18 = 0
7037 12:40:32.426390 Vcore = 725000
7038 12:40:32.426493 Vdram = 0
7039 12:40:32.426581 Vddq = 0
7040 12:40:32.426697 Vmddr = 0
7041 12:40:32.432905 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7042 12:40:32.440234 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7043 12:40:32.440408 MEM_TYPE=3, freq_sel=13
7044 12:40:32.443533 sv_algorithm_assistance_LP4_3733
7045 12:40:32.446391 ============ PULL DRAM RESETB DOWN ============
7046 12:40:32.452979 ========== PULL DRAM RESETB DOWN end =========
7047 12:40:32.456239 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7048 12:40:32.460015 ===================================
7049 12:40:32.463032 LPDDR4 DRAM CONFIGURATION
7050 12:40:32.466685 ===================================
7051 12:40:32.466806 EX_ROW_EN[0] = 0x0
7052 12:40:32.469964 EX_ROW_EN[1] = 0x0
7053 12:40:32.470070 LP4Y_EN = 0x0
7054 12:40:32.473512 WORK_FSP = 0x1
7055 12:40:32.473628 WL = 0x5
7056 12:40:32.476336 RL = 0x5
7057 12:40:32.476443 BL = 0x2
7058 12:40:32.480054 RPST = 0x0
7059 12:40:32.480160 RD_PRE = 0x0
7060 12:40:32.483288 WR_PRE = 0x1
7061 12:40:32.486943 WR_PST = 0x1
7062 12:40:32.487057 DBI_WR = 0x0
7063 12:40:32.489713 DBI_RD = 0x0
7064 12:40:32.489798 OTF = 0x1
7065 12:40:32.492897 ===================================
7066 12:40:32.496818 ===================================
7067 12:40:32.496919 ANA top config
7068 12:40:32.500128 ===================================
7069 12:40:32.503467 DLL_ASYNC_EN = 0
7070 12:40:32.506339 ALL_SLAVE_EN = 0
7071 12:40:32.509538 NEW_RANK_MODE = 1
7072 12:40:32.512903 DLL_IDLE_MODE = 1
7073 12:40:32.512999 LP45_APHY_COMB_EN = 1
7074 12:40:32.516223 TX_ODT_DIS = 0
7075 12:40:32.519814 NEW_8X_MODE = 1
7076 12:40:32.522958 ===================================
7077 12:40:32.526316 ===================================
7078 12:40:32.529768 data_rate = 3200
7079 12:40:32.533096 CKR = 1
7080 12:40:32.533221 DQ_P2S_RATIO = 8
7081 12:40:32.536558 ===================================
7082 12:40:32.539844 CA_P2S_RATIO = 8
7083 12:40:32.542577 DQ_CA_OPEN = 0
7084 12:40:32.545967 DQ_SEMI_OPEN = 0
7085 12:40:32.549211 CA_SEMI_OPEN = 0
7086 12:40:32.552607 CA_FULL_RATE = 0
7087 12:40:32.552706 DQ_CKDIV4_EN = 0
7088 12:40:32.556093 CA_CKDIV4_EN = 0
7089 12:40:32.559550 CA_PREDIV_EN = 0
7090 12:40:32.562844 PH8_DLY = 12
7091 12:40:32.566066 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7092 12:40:32.569600 DQ_AAMCK_DIV = 4
7093 12:40:32.569697 CA_AAMCK_DIV = 4
7094 12:40:32.572311 CA_ADMCK_DIV = 4
7095 12:40:32.575826 DQ_TRACK_CA_EN = 0
7096 12:40:32.579172 CA_PICK = 1600
7097 12:40:32.582590 CA_MCKIO = 1600
7098 12:40:32.585960 MCKIO_SEMI = 0
7099 12:40:32.589119 PLL_FREQ = 3068
7100 12:40:32.592806 DQ_UI_PI_RATIO = 32
7101 12:40:32.592924 CA_UI_PI_RATIO = 0
7102 12:40:32.595701 ===================================
7103 12:40:32.599268 ===================================
7104 12:40:32.602893 memory_type:LPDDR4
7105 12:40:32.605948 GP_NUM : 10
7106 12:40:32.606063 SRAM_EN : 1
7107 12:40:32.609357 MD32_EN : 0
7108 12:40:32.612405 ===================================
7109 12:40:32.615781 [ANA_INIT] >>>>>>>>>>>>>>
7110 12:40:32.619121 <<<<<< [CONFIGURE PHASE]: ANA_TX
7111 12:40:32.622537 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7112 12:40:32.625785 ===================================
7113 12:40:32.625889 data_rate = 3200,PCW = 0X7600
7114 12:40:32.629308 ===================================
7115 12:40:32.632541 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7116 12:40:32.639229 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7117 12:40:32.645363 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7118 12:40:32.648839 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7119 12:40:32.652165 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7120 12:40:32.655365 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7121 12:40:32.658809 [ANA_INIT] flow start
7122 12:40:32.658944 [ANA_INIT] PLL >>>>>>>>
7123 12:40:32.662300 [ANA_INIT] PLL <<<<<<<<
7124 12:40:32.665737 [ANA_INIT] MIDPI >>>>>>>>
7125 12:40:32.669138 [ANA_INIT] MIDPI <<<<<<<<
7126 12:40:32.669248 [ANA_INIT] DLL >>>>>>>>
7127 12:40:32.672421 [ANA_INIT] DLL <<<<<<<<
7128 12:40:32.672506 [ANA_INIT] flow end
7129 12:40:32.679285 ============ LP4 DIFF to SE enter ============
7130 12:40:32.681968 ============ LP4 DIFF to SE exit ============
7131 12:40:32.685469 [ANA_INIT] <<<<<<<<<<<<<
7132 12:40:32.688865 [Flow] Enable top DCM control >>>>>
7133 12:40:32.692216 [Flow] Enable top DCM control <<<<<
7134 12:40:32.695676 Enable DLL master slave shuffle
7135 12:40:32.698968 ==============================================================
7136 12:40:32.702399 Gating Mode config
7137 12:40:32.705815 ==============================================================
7138 12:40:32.709083 Config description:
7139 12:40:32.718959 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7140 12:40:32.725606 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7141 12:40:32.728844 SELPH_MODE 0: By rank 1: By Phase
7142 12:40:32.735353 ==============================================================
7143 12:40:32.738902 GAT_TRACK_EN = 1
7144 12:40:32.741988 RX_GATING_MODE = 2
7145 12:40:32.745364 RX_GATING_TRACK_MODE = 2
7146 12:40:32.748734 SELPH_MODE = 1
7147 12:40:32.752136 PICG_EARLY_EN = 1
7148 12:40:32.752212 VALID_LAT_VALUE = 1
7149 12:40:32.758456 ==============================================================
7150 12:40:32.761666 Enter into Gating configuration >>>>
7151 12:40:32.765076 Exit from Gating configuration <<<<
7152 12:40:32.768484 Enter into DVFS_PRE_config >>>>>
7153 12:40:32.778525 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7154 12:40:32.781972 Exit from DVFS_PRE_config <<<<<
7155 12:40:32.785374 Enter into PICG configuration >>>>
7156 12:40:32.788829 Exit from PICG configuration <<<<
7157 12:40:32.792231 [RX_INPUT] configuration >>>>>
7158 12:40:32.795037 [RX_INPUT] configuration <<<<<
7159 12:40:32.798478 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7160 12:40:32.805175 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7161 12:40:32.812017 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7162 12:40:32.818654 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7163 12:40:32.825371 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7164 12:40:32.828785 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7165 12:40:32.834825 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7166 12:40:32.838180 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7167 12:40:32.841666 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7168 12:40:32.845121 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7169 12:40:32.851488 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7170 12:40:32.854933 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7171 12:40:32.858413 ===================================
7172 12:40:32.861733 LPDDR4 DRAM CONFIGURATION
7173 12:40:32.865164 ===================================
7174 12:40:32.865271 EX_ROW_EN[0] = 0x0
7175 12:40:32.868134 EX_ROW_EN[1] = 0x0
7176 12:40:32.868217 LP4Y_EN = 0x0
7177 12:40:32.871717 WORK_FSP = 0x1
7178 12:40:32.871803 WL = 0x5
7179 12:40:32.874957 RL = 0x5
7180 12:40:32.875073 BL = 0x2
7181 12:40:32.878345 RPST = 0x0
7182 12:40:32.878432 RD_PRE = 0x0
7183 12:40:32.881600 WR_PRE = 0x1
7184 12:40:32.885210 WR_PST = 0x1
7185 12:40:32.885301 DBI_WR = 0x0
7186 12:40:32.888425 DBI_RD = 0x0
7187 12:40:32.888508 OTF = 0x1
7188 12:40:32.891320 ===================================
7189 12:40:32.894785 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7190 12:40:32.898168 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7191 12:40:32.905074 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7192 12:40:32.907861 ===================================
7193 12:40:32.911127 LPDDR4 DRAM CONFIGURATION
7194 12:40:32.914677 ===================================
7195 12:40:32.914760 EX_ROW_EN[0] = 0x10
7196 12:40:32.918026 EX_ROW_EN[1] = 0x0
7197 12:40:32.918100 LP4Y_EN = 0x0
7198 12:40:32.921516 WORK_FSP = 0x1
7199 12:40:32.921594 WL = 0x5
7200 12:40:32.924814 RL = 0x5
7201 12:40:32.924891 BL = 0x2
7202 12:40:32.928130 RPST = 0x0
7203 12:40:32.928205 RD_PRE = 0x0
7204 12:40:32.931259 WR_PRE = 0x1
7205 12:40:32.931367 WR_PST = 0x1
7206 12:40:32.934703 DBI_WR = 0x0
7207 12:40:32.934793 DBI_RD = 0x0
7208 12:40:32.938058 OTF = 0x1
7209 12:40:32.941522 ===================================
7210 12:40:32.947792 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7211 12:40:32.947897 ==
7212 12:40:32.951149 Dram Type= 6, Freq= 0, CH_0, rank 0
7213 12:40:32.954503 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7214 12:40:32.954599 ==
7215 12:40:32.957824 [Duty_Offset_Calibration]
7216 12:40:32.957906 B0:2 B1:1 CA:1
7217 12:40:32.957987
7218 12:40:32.961205 [DutyScan_Calibration_Flow] k_type=0
7219 12:40:32.972416
7220 12:40:32.972526 ==CLK 0==
7221 12:40:32.975708 Final CLK duty delay cell = 0
7222 12:40:32.978898 [0] MAX Duty = 5156%(X100), DQS PI = 22
7223 12:40:32.982201 [0] MIN Duty = 4907%(X100), DQS PI = 0
7224 12:40:32.982295 [0] AVG Duty = 5031%(X100)
7225 12:40:32.985560
7226 12:40:32.988836 CH0 CLK Duty spec in!! Max-Min= 249%
7227 12:40:32.992678 [DutyScan_Calibration_Flow] ====Done====
7228 12:40:32.992765
7229 12:40:32.996123 [DutyScan_Calibration_Flow] k_type=1
7230 12:40:33.011441
7231 12:40:33.011560 ==DQS 0 ==
7232 12:40:33.014845 Final DQS duty delay cell = -4
7233 12:40:33.017788 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7234 12:40:33.021544 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7235 12:40:33.024967 [-4] AVG Duty = 4891%(X100)
7236 12:40:33.025082
7237 12:40:33.025145 ==DQS 1 ==
7238 12:40:33.028310 Final DQS duty delay cell = 0
7239 12:40:33.031676 [0] MAX Duty = 5187%(X100), DQS PI = 2
7240 12:40:33.035071 [0] MIN Duty = 5062%(X100), DQS PI = 30
7241 12:40:33.038378 [0] AVG Duty = 5124%(X100)
7242 12:40:33.038467
7243 12:40:33.041745 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7244 12:40:33.041832
7245 12:40:33.045005 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7246 12:40:33.047734 [DutyScan_Calibration_Flow] ====Done====
7247 12:40:33.047849
7248 12:40:33.051116 [DutyScan_Calibration_Flow] k_type=3
7249 12:40:33.068018
7250 12:40:33.068160 ==DQM 0 ==
7251 12:40:33.071281 Final DQM duty delay cell = 0
7252 12:40:33.074587 [0] MAX Duty = 5218%(X100), DQS PI = 32
7253 12:40:33.077972 [0] MIN Duty = 4907%(X100), DQS PI = 54
7254 12:40:33.081162 [0] AVG Duty = 5062%(X100)
7255 12:40:33.081250
7256 12:40:33.081316 ==DQM 1 ==
7257 12:40:33.084509 Final DQM duty delay cell = -4
7258 12:40:33.087950 [-4] MAX Duty = 4969%(X100), DQS PI = 60
7259 12:40:33.091313 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7260 12:40:33.094649 [-4] AVG Duty = 4906%(X100)
7261 12:40:33.094735
7262 12:40:33.098005 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7263 12:40:33.098088
7264 12:40:33.101662 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7265 12:40:33.105059 [DutyScan_Calibration_Flow] ====Done====
7266 12:40:33.105148
7267 12:40:33.107781 [DutyScan_Calibration_Flow] k_type=2
7268 12:40:33.125963
7269 12:40:33.126092 ==DQ 0 ==
7270 12:40:33.128671 Final DQ duty delay cell = 0
7271 12:40:33.132318 [0] MAX Duty = 5062%(X100), DQS PI = 24
7272 12:40:33.135295 [0] MIN Duty = 4907%(X100), DQS PI = 0
7273 12:40:33.135384 [0] AVG Duty = 4984%(X100)
7274 12:40:33.139124
7275 12:40:33.139235 ==DQ 1 ==
7276 12:40:33.142104 Final DQ duty delay cell = 0
7277 12:40:33.145758 [0] MAX Duty = 5094%(X100), DQS PI = 6
7278 12:40:33.148654 [0] MIN Duty = 4907%(X100), DQS PI = 34
7279 12:40:33.148740 [0] AVG Duty = 5000%(X100)
7280 12:40:33.148805
7281 12:40:33.152397 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7282 12:40:33.155804
7283 12:40:33.158593 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7284 12:40:33.162039 [DutyScan_Calibration_Flow] ====Done====
7285 12:40:33.162126 ==
7286 12:40:33.165379 Dram Type= 6, Freq= 0, CH_1, rank 0
7287 12:40:33.168750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7288 12:40:33.168839 ==
7289 12:40:33.172111 [Duty_Offset_Calibration]
7290 12:40:33.172222 B0:1 B1:0 CA:0
7291 12:40:33.172324
7292 12:40:33.175602 [DutyScan_Calibration_Flow] k_type=0
7293 12:40:33.184839
7294 12:40:33.184969 ==CLK 0==
7295 12:40:33.188063 Final CLK duty delay cell = -4
7296 12:40:33.191454 [-4] MAX Duty = 4969%(X100), DQS PI = 28
7297 12:40:33.195029 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7298 12:40:33.198491 [-4] AVG Duty = 4906%(X100)
7299 12:40:33.198580
7300 12:40:33.201241 CH1 CLK Duty spec in!! Max-Min= 125%
7301 12:40:33.205139 [DutyScan_Calibration_Flow] ====Done====
7302 12:40:33.205247
7303 12:40:33.207878 [DutyScan_Calibration_Flow] k_type=1
7304 12:40:33.225093
7305 12:40:33.225240 ==DQS 0 ==
7306 12:40:33.228354 Final DQS duty delay cell = 0
7307 12:40:33.231384 [0] MAX Duty = 5094%(X100), DQS PI = 26
7308 12:40:33.235242 [0] MIN Duty = 4844%(X100), DQS PI = 14
7309 12:40:33.238460 [0] AVG Duty = 4969%(X100)
7310 12:40:33.238545
7311 12:40:33.238617 ==DQS 1 ==
7312 12:40:33.241542 Final DQS duty delay cell = 0
7313 12:40:33.245218 [0] MAX Duty = 5249%(X100), DQS PI = 48
7314 12:40:33.248026 [0] MIN Duty = 4938%(X100), DQS PI = 40
7315 12:40:33.251237 [0] AVG Duty = 5093%(X100)
7316 12:40:33.251333
7317 12:40:33.254576 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7318 12:40:33.254655
7319 12:40:33.257897 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7320 12:40:33.261455 [DutyScan_Calibration_Flow] ====Done====
7321 12:40:33.261531
7322 12:40:33.264426 [DutyScan_Calibration_Flow] k_type=3
7323 12:40:33.281679
7324 12:40:33.281811 ==DQM 0 ==
7325 12:40:33.285091 Final DQM duty delay cell = 0
7326 12:40:33.288426 [0] MAX Duty = 5187%(X100), DQS PI = 38
7327 12:40:33.291707 [0] MIN Duty = 5031%(X100), DQS PI = 16
7328 12:40:33.294904 [0] AVG Duty = 5109%(X100)
7329 12:40:33.294993
7330 12:40:33.295056 ==DQM 1 ==
7331 12:40:33.298913 Final DQM duty delay cell = 0
7332 12:40:33.301656 [0] MAX Duty = 5093%(X100), DQS PI = 8
7333 12:40:33.305036 [0] MIN Duty = 4907%(X100), DQS PI = 2
7334 12:40:33.305135 [0] AVG Duty = 5000%(X100)
7335 12:40:33.305201
7336 12:40:33.312148 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7337 12:40:33.312278
7338 12:40:33.315370 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7339 12:40:33.318872 [DutyScan_Calibration_Flow] ====Done====
7340 12:40:33.318967
7341 12:40:33.321597 [DutyScan_Calibration_Flow] k_type=2
7342 12:40:33.338020
7343 12:40:33.338146 ==DQ 0 ==
7344 12:40:33.341413 Final DQ duty delay cell = -4
7345 12:40:33.344115 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7346 12:40:33.348031 [-4] MIN Duty = 4875%(X100), DQS PI = 12
7347 12:40:33.351254 [-4] AVG Duty = 4953%(X100)
7348 12:40:33.351347
7349 12:40:33.351411 ==DQ 1 ==
7350 12:40:33.354346 Final DQ duty delay cell = 0
7351 12:40:33.357703 [0] MAX Duty = 5093%(X100), DQS PI = 8
7352 12:40:33.360844 [0] MIN Duty = 4938%(X100), DQS PI = 0
7353 12:40:33.364219 [0] AVG Duty = 5015%(X100)
7354 12:40:33.364368
7355 12:40:33.367606 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7356 12:40:33.367689
7357 12:40:33.371011 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7358 12:40:33.374384 [DutyScan_Calibration_Flow] ====Done====
7359 12:40:33.377634 nWR fixed to 30
7360 12:40:33.380922 [ModeRegInit_LP4] CH0 RK0
7361 12:40:33.381011 [ModeRegInit_LP4] CH0 RK1
7362 12:40:33.383896 [ModeRegInit_LP4] CH1 RK0
7363 12:40:33.387540 [ModeRegInit_LP4] CH1 RK1
7364 12:40:33.387629 match AC timing 5
7365 12:40:33.394238 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7366 12:40:33.397588 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7367 12:40:33.400836 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7368 12:40:33.407187 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7369 12:40:33.410851 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7370 12:40:33.410993 [MiockJmeterHQA]
7371 12:40:33.411117
7372 12:40:33.414232 [DramcMiockJmeter] u1RxGatingPI = 0
7373 12:40:33.417223 0 : 4252, 4027
7374 12:40:33.417347 4 : 4368, 4140
7375 12:40:33.420325 8 : 4252, 4027
7376 12:40:33.420459 12 : 4252, 4027
7377 12:40:33.420526 16 : 4253, 4026
7378 12:40:33.424229 20 : 4363, 4138
7379 12:40:33.424348 24 : 4252, 4026
7380 12:40:33.427047 28 : 4252, 4027
7381 12:40:33.427147 32 : 4252, 4027
7382 12:40:33.430403 36 : 4255, 4029
7383 12:40:33.430493 40 : 4253, 4027
7384 12:40:33.433938 44 : 4360, 4137
7385 12:40:33.434030 48 : 4363, 4137
7386 12:40:33.434096 52 : 4249, 4027
7387 12:40:33.437319 56 : 4252, 4026
7388 12:40:33.437440 60 : 4252, 4027
7389 12:40:33.440731 64 : 4249, 4027
7390 12:40:33.440838 68 : 4253, 4029
7391 12:40:33.444231 72 : 4361, 4137
7392 12:40:33.444353 76 : 4250, 4026
7393 12:40:33.447191 80 : 4250, 4027
7394 12:40:33.447279 84 : 4250, 4025
7395 12:40:33.447345 88 : 4253, 33
7396 12:40:33.450588 92 : 4250, 0
7397 12:40:33.450694 96 : 4255, 0
7398 12:40:33.450759 100 : 4250, 0
7399 12:40:33.453921 104 : 4250, 0
7400 12:40:33.454041 108 : 4362, 0
7401 12:40:33.457702 112 : 4360, 0
7402 12:40:33.457839 116 : 4363, 0
7403 12:40:33.457979 120 : 4250, 0
7404 12:40:33.460652 124 : 4250, 0
7405 12:40:33.460735 128 : 4250, 0
7406 12:40:33.464125 132 : 4250, 0
7407 12:40:33.464233 136 : 4249, 0
7408 12:40:33.464364 140 : 4250, 0
7409 12:40:33.467399 144 : 4253, 0
7410 12:40:33.467493 148 : 4249, 0
7411 12:40:33.470766 152 : 4249, 0
7412 12:40:33.470864 156 : 4253, 0
7413 12:40:33.470938 160 : 4362, 0
7414 12:40:33.474185 164 : 4360, 0
7415 12:40:33.474281 168 : 4363, 0
7416 12:40:33.474349 172 : 4361, 0
7417 12:40:33.477372 176 : 4361, 0
7418 12:40:33.477463 180 : 4250, 0
7419 12:40:33.480706 184 : 4250, 0
7420 12:40:33.480799 188 : 4250, 0
7421 12:40:33.480866 192 : 4250, 0
7422 12:40:33.484077 196 : 4253, 0
7423 12:40:33.484169 200 : 4250, 0
7424 12:40:33.487521 204 : 4361, 1364
7425 12:40:33.487613 208 : 4250, 4014
7426 12:40:33.490318 212 : 4250, 4027
7427 12:40:33.490408 216 : 4250, 4026
7428 12:40:33.490475 220 : 4250, 4027
7429 12:40:33.493815 224 : 4249, 4027
7430 12:40:33.493906 228 : 4361, 4137
7431 12:40:33.497086 232 : 4250, 4026
7432 12:40:33.497181 236 : 4250, 4027
7433 12:40:33.500426 240 : 4360, 4138
7434 12:40:33.500519 244 : 4249, 4027
7435 12:40:33.503661 248 : 4250, 4026
7436 12:40:33.503757 252 : 4363, 4140
7437 12:40:33.507414 256 : 4250, 4027
7438 12:40:33.507511 260 : 4250, 4027
7439 12:40:33.510448 264 : 4250, 4026
7440 12:40:33.510543 268 : 4253, 4029
7441 12:40:33.513715 272 : 4250, 4027
7442 12:40:33.513805 276 : 4250, 4027
7443 12:40:33.513871 280 : 4361, 4137
7444 12:40:33.516870 284 : 4250, 4026
7445 12:40:33.516974 288 : 4250, 4027
7446 12:40:33.520322 292 : 4360, 4138
7447 12:40:33.520430 296 : 4249, 4027
7448 12:40:33.523825 300 : 4250, 4026
7449 12:40:33.523928 304 : 4363, 4140
7450 12:40:33.527187 308 : 4250, 3922
7451 12:40:33.527293 312 : 4249, 1949
7452 12:40:33.527361
7453 12:40:33.530656 MIOCK jitter meter ch=0
7454 12:40:33.530766
7455 12:40:33.533895 1T = (312-88) = 224 dly cells
7456 12:40:33.540275 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7457 12:40:33.540462 ==
7458 12:40:33.543681 Dram Type= 6, Freq= 0, CH_0, rank 0
7459 12:40:33.547075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7460 12:40:33.547243 ==
7461 12:40:33.553293 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7462 12:40:33.556680 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7463 12:40:33.559953 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7464 12:40:33.566596 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7465 12:40:33.575414 [CA 0] Center 43 (12~74) winsize 63
7466 12:40:33.578496 [CA 1] Center 43 (13~74) winsize 62
7467 12:40:33.581711 [CA 2] Center 38 (9~68) winsize 60
7468 12:40:33.585049 [CA 3] Center 38 (8~68) winsize 61
7469 12:40:33.588474 [CA 4] Center 36 (7~66) winsize 60
7470 12:40:33.591825 [CA 5] Center 35 (6~65) winsize 60
7471 12:40:33.591948
7472 12:40:33.595252 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7473 12:40:33.595360
7474 12:40:33.598660 [CATrainingPosCal] consider 1 rank data
7475 12:40:33.602000 u2DelayCellTimex100 = 290/100 ps
7476 12:40:33.604806 CA0 delay=43 (12~74),Diff = 8 PI (26 cell)
7477 12:40:33.611588 CA1 delay=43 (13~74),Diff = 8 PI (26 cell)
7478 12:40:33.614845 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7479 12:40:33.618095 CA3 delay=38 (8~68),Diff = 3 PI (10 cell)
7480 12:40:33.621963 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7481 12:40:33.625210 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7482 12:40:33.625316
7483 12:40:33.628019 CA PerBit enable=1, Macro0, CA PI delay=35
7484 12:40:33.628106
7485 12:40:33.631299 [CBTSetCACLKResult] CA Dly = 35
7486 12:40:33.635099 CS Dly: 9 (0~40)
7487 12:40:33.638316 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7488 12:40:33.641628 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7489 12:40:33.641720 ==
7490 12:40:33.645311 Dram Type= 6, Freq= 0, CH_0, rank 1
7491 12:40:33.648322 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7492 12:40:33.651871 ==
7493 12:40:33.654831 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7494 12:40:33.658107 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7495 12:40:33.664945 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7496 12:40:33.671328 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7497 12:40:33.679057 [CA 0] Center 42 (12~73) winsize 62
7498 12:40:33.681765 [CA 1] Center 42 (12~73) winsize 62
7499 12:40:33.685158 [CA 2] Center 38 (8~68) winsize 61
7500 12:40:33.688895 [CA 3] Center 37 (7~67) winsize 61
7501 12:40:33.692245 [CA 4] Center 36 (6~66) winsize 61
7502 12:40:33.695021 [CA 5] Center 35 (5~65) winsize 61
7503 12:40:33.695109
7504 12:40:33.698539 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7505 12:40:33.698620
7506 12:40:33.701987 [CATrainingPosCal] consider 2 rank data
7507 12:40:33.705361 u2DelayCellTimex100 = 290/100 ps
7508 12:40:33.708857 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7509 12:40:33.715610 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7510 12:40:33.719048 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7511 12:40:33.721737 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7512 12:40:33.725148 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7513 12:40:33.728471 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7514 12:40:33.728565
7515 12:40:33.731845 CA PerBit enable=1, Macro0, CA PI delay=35
7516 12:40:33.731941
7517 12:40:33.735785 [CBTSetCACLKResult] CA Dly = 35
7518 12:40:33.738841 CS Dly: 10 (0~42)
7519 12:40:33.742049 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7520 12:40:33.745393 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7521 12:40:33.745484
7522 12:40:33.748866 ----->DramcWriteLeveling(PI) begin...
7523 12:40:33.748956 ==
7524 12:40:33.752215 Dram Type= 6, Freq= 0, CH_0, rank 0
7525 12:40:33.755658 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7526 12:40:33.758462 ==
7527 12:40:33.758543 Write leveling (Byte 0): 34 => 34
7528 12:40:33.761726 Write leveling (Byte 1): 28 => 28
7529 12:40:33.765410 DramcWriteLeveling(PI) end<-----
7530 12:40:33.765493
7531 12:40:33.765575 ==
7532 12:40:33.768381 Dram Type= 6, Freq= 0, CH_0, rank 0
7533 12:40:33.775609 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7534 12:40:33.775727 ==
7535 12:40:33.775817 [Gating] SW mode calibration
7536 12:40:33.785093 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7537 12:40:33.788640 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7538 12:40:33.795289 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7539 12:40:33.798670 1 4 4 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7540 12:40:33.801736 1 4 8 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7541 12:40:33.808315 1 4 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (1 1)
7542 12:40:33.811820 1 4 16 | B1->B0 | 2323 3636 | 0 1 | (1 1) (1 1)
7543 12:40:33.815192 1 4 20 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
7544 12:40:33.818653 1 4 24 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
7545 12:40:33.824863 1 4 28 | B1->B0 | 3434 3635 | 1 1 | (1 1) (1 1)
7546 12:40:33.828216 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7547 12:40:33.831659 1 5 4 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7548 12:40:33.838283 1 5 8 | B1->B0 | 3434 3938 | 1 1 | (1 1) (0 0)
7549 12:40:33.841569 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 1)
7550 12:40:33.844626 1 5 16 | B1->B0 | 3333 2929 | 1 0 | (1 0) (0 0)
7551 12:40:33.851551 1 5 20 | B1->B0 | 2626 2a29 | 0 1 | (1 0) (0 0)
7552 12:40:33.854682 1 5 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7553 12:40:33.858032 1 5 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7554 12:40:33.864975 1 6 0 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7555 12:40:33.867777 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7556 12:40:33.871317 1 6 8 | B1->B0 | 2323 302f | 0 1 | (0 0) (0 0)
7557 12:40:33.877784 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7558 12:40:33.881517 1 6 16 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7559 12:40:33.884735 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7560 12:40:33.891326 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7561 12:40:33.894926 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7562 12:40:33.897743 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7563 12:40:33.904487 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7564 12:40:33.907798 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7565 12:40:33.911660 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7566 12:40:33.918086 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7567 12:40:33.921542 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7568 12:40:33.924988 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7569 12:40:33.931199 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7570 12:40:33.934720 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 12:40:33.938127 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 12:40:33.941528 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 12:40:33.948249 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 12:40:33.950971 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 12:40:33.954285 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 12:40:33.961130 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 12:40:33.964159 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 12:40:33.967920 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 12:40:33.974123 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 12:40:33.977536 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7581 12:40:33.980945 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7582 12:40:33.987604 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7583 12:40:33.991101 Total UI for P1: 0, mck2ui 16
7584 12:40:33.994608 best dqsien dly found for B0: ( 1, 9, 10)
7585 12:40:33.997861 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7586 12:40:34.001208 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7587 12:40:34.004477 Total UI for P1: 0, mck2ui 16
7588 12:40:34.007480 best dqsien dly found for B1: ( 1, 9, 18)
7589 12:40:34.010642 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7590 12:40:34.013950 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7591 12:40:34.014059
7592 12:40:34.021011 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7593 12:40:34.024339 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7594 12:40:34.027275 [Gating] SW calibration Done
7595 12:40:34.027380 ==
7596 12:40:34.030551 Dram Type= 6, Freq= 0, CH_0, rank 0
7597 12:40:34.033768 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7598 12:40:34.033881 ==
7599 12:40:34.033974 RX Vref Scan: 0
7600 12:40:34.037194
7601 12:40:34.037300 RX Vref 0 -> 0, step: 1
7602 12:40:34.037392
7603 12:40:34.040561 RX Delay 0 -> 252, step: 8
7604 12:40:34.044052 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7605 12:40:34.047467 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7606 12:40:34.054155 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7607 12:40:34.057511 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7608 12:40:34.060929 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7609 12:40:34.063731 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7610 12:40:34.067160 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7611 12:40:34.073967 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7612 12:40:34.077081 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7613 12:40:34.080405 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7614 12:40:34.083791 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7615 12:40:34.087072 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7616 12:40:34.093996 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7617 12:40:34.097155 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7618 12:40:34.100441 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7619 12:40:34.103797 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7620 12:40:34.103908 ==
7621 12:40:34.107221 Dram Type= 6, Freq= 0, CH_0, rank 0
7622 12:40:34.113900 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7623 12:40:34.114012 ==
7624 12:40:34.114102 DQS Delay:
7625 12:40:34.114188 DQS0 = 0, DQS1 = 0
7626 12:40:34.116909 DQM Delay:
7627 12:40:34.117011 DQM0 = 136, DQM1 = 130
7628 12:40:34.120806 DQ Delay:
7629 12:40:34.123968 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =131
7630 12:40:34.126957 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7631 12:40:34.130293 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7632 12:40:34.133663 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
7633 12:40:34.133767
7634 12:40:34.133855
7635 12:40:34.133939 ==
7636 12:40:34.137114 Dram Type= 6, Freq= 0, CH_0, rank 0
7637 12:40:34.140280 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7638 12:40:34.140419 ==
7639 12:40:34.140507
7640 12:40:34.143790
7641 12:40:34.143890 TX Vref Scan disable
7642 12:40:34.147054 == TX Byte 0 ==
7643 12:40:34.150491 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7644 12:40:34.153950 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7645 12:40:34.157296 == TX Byte 1 ==
7646 12:40:34.160522 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7647 12:40:34.163815 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7648 12:40:34.163922 ==
7649 12:40:34.167300 Dram Type= 6, Freq= 0, CH_0, rank 0
7650 12:40:34.173421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7651 12:40:34.173528 ==
7652 12:40:34.184416
7653 12:40:34.187589 TX Vref early break, caculate TX vref
7654 12:40:34.191070 TX Vref=16, minBit 1, minWin=22, winSum=377
7655 12:40:34.194495 TX Vref=18, minBit 7, minWin=23, winSum=389
7656 12:40:34.197803 TX Vref=20, minBit 0, minWin=24, winSum=400
7657 12:40:34.201246 TX Vref=22, minBit 5, minWin=25, winSum=413
7658 12:40:34.204558 TX Vref=24, minBit 6, minWin=25, winSum=418
7659 12:40:34.210979 TX Vref=26, minBit 6, minWin=25, winSum=428
7660 12:40:34.214363 TX Vref=28, minBit 1, minWin=25, winSum=424
7661 12:40:34.217675 TX Vref=30, minBit 1, minWin=25, winSum=415
7662 12:40:34.220368 TX Vref=32, minBit 6, minWin=24, winSum=405
7663 12:40:34.227355 [TxChooseVref] Worse bit 6, Min win 25, Win sum 428, Final Vref 26
7664 12:40:34.227466
7665 12:40:34.230754 Final TX Range 0 Vref 26
7666 12:40:34.230859
7667 12:40:34.230948 ==
7668 12:40:34.233919 Dram Type= 6, Freq= 0, CH_0, rank 0
7669 12:40:34.237017 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7670 12:40:34.237119 ==
7671 12:40:34.237210
7672 12:40:34.237297
7673 12:40:34.240243 TX Vref Scan disable
7674 12:40:34.246949 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7675 12:40:34.247059 == TX Byte 0 ==
7676 12:40:34.250492 u2DelayCellOfst[0]=10 cells (3 PI)
7677 12:40:34.254227 u2DelayCellOfst[1]=16 cells (5 PI)
7678 12:40:34.257228 u2DelayCellOfst[2]=10 cells (3 PI)
7679 12:40:34.260391 u2DelayCellOfst[3]=10 cells (3 PI)
7680 12:40:34.263558 u2DelayCellOfst[4]=6 cells (2 PI)
7681 12:40:34.266816 u2DelayCellOfst[5]=0 cells (0 PI)
7682 12:40:34.270079 u2DelayCellOfst[6]=16 cells (5 PI)
7683 12:40:34.273468 u2DelayCellOfst[7]=16 cells (5 PI)
7684 12:40:34.276879 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7685 12:40:34.280171 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7686 12:40:34.283583 == TX Byte 1 ==
7687 12:40:34.283690 u2DelayCellOfst[8]=0 cells (0 PI)
7688 12:40:34.287012 u2DelayCellOfst[9]=3 cells (1 PI)
7689 12:40:34.290756 u2DelayCellOfst[10]=6 cells (2 PI)
7690 12:40:34.293988 u2DelayCellOfst[11]=6 cells (2 PI)
7691 12:40:34.297345 u2DelayCellOfst[12]=10 cells (3 PI)
7692 12:40:34.300904 u2DelayCellOfst[13]=10 cells (3 PI)
7693 12:40:34.304181 u2DelayCellOfst[14]=13 cells (4 PI)
7694 12:40:34.307585 u2DelayCellOfst[15]=10 cells (3 PI)
7695 12:40:34.310334 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7696 12:40:34.313600 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7697 12:40:34.316884 DramC Write-DBI on
7698 12:40:34.316984 ==
7699 12:40:34.320205 Dram Type= 6, Freq= 0, CH_0, rank 0
7700 12:40:34.323612 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7701 12:40:34.323718 ==
7702 12:40:34.323801
7703 12:40:34.326994
7704 12:40:34.327093 TX Vref Scan disable
7705 12:40:34.330425 == TX Byte 0 ==
7706 12:40:34.333899 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7707 12:40:34.337306 == TX Byte 1 ==
7708 12:40:34.340667 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7709 12:40:34.340769 DramC Write-DBI off
7710 12:40:34.340856
7711 12:40:34.344048 [DATLAT]
7712 12:40:34.344148 Freq=1600, CH0 RK0
7713 12:40:34.344237
7714 12:40:34.347401 DATLAT Default: 0xf
7715 12:40:34.347499 0, 0xFFFF, sum = 0
7716 12:40:34.350592 1, 0xFFFF, sum = 0
7717 12:40:34.350753 2, 0xFFFF, sum = 0
7718 12:40:34.353849 3, 0xFFFF, sum = 0
7719 12:40:34.353953 4, 0xFFFF, sum = 0
7720 12:40:34.357204 5, 0xFFFF, sum = 0
7721 12:40:34.357307 6, 0xFFFF, sum = 0
7722 12:40:34.360669 7, 0xFFFF, sum = 0
7723 12:40:34.360770 8, 0xFFFF, sum = 0
7724 12:40:34.363883 9, 0xFFFF, sum = 0
7725 12:40:34.367010 10, 0xFFFF, sum = 0
7726 12:40:34.367119 11, 0xFFFF, sum = 0
7727 12:40:34.370274 12, 0xFFFF, sum = 0
7728 12:40:34.370379 13, 0xFFFF, sum = 0
7729 12:40:34.373524 14, 0x0, sum = 1
7730 12:40:34.373630 15, 0x0, sum = 2
7731 12:40:34.376801 16, 0x0, sum = 3
7732 12:40:34.376917 17, 0x0, sum = 4
7733 12:40:34.377034 best_step = 15
7734 12:40:34.380429
7735 12:40:34.380526 ==
7736 12:40:34.383428 Dram Type= 6, Freq= 0, CH_0, rank 0
7737 12:40:34.386783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7738 12:40:34.386887 ==
7739 12:40:34.386977 RX Vref Scan: 1
7740 12:40:34.387063
7741 12:40:34.390240 Set Vref Range= 24 -> 127
7742 12:40:34.390342
7743 12:40:34.393485 RX Vref 24 -> 127, step: 1
7744 12:40:34.393588
7745 12:40:34.396642 RX Delay 27 -> 252, step: 4
7746 12:40:34.396760
7747 12:40:34.400522 Set Vref, RX VrefLevel [Byte0]: 24
7748 12:40:34.403335 [Byte1]: 24
7749 12:40:34.403446
7750 12:40:34.406860 Set Vref, RX VrefLevel [Byte0]: 25
7751 12:40:34.410363 [Byte1]: 25
7752 12:40:34.410472
7753 12:40:34.413702 Set Vref, RX VrefLevel [Byte0]: 26
7754 12:40:34.417065 [Byte1]: 26
7755 12:40:34.420368
7756 12:40:34.420496 Set Vref, RX VrefLevel [Byte0]: 27
7757 12:40:34.423528 [Byte1]: 27
7758 12:40:34.428012
7759 12:40:34.428121 Set Vref, RX VrefLevel [Byte0]: 28
7760 12:40:34.431392 [Byte1]: 28
7761 12:40:34.435515
7762 12:40:34.435696 Set Vref, RX VrefLevel [Byte0]: 29
7763 12:40:34.438988 [Byte1]: 29
7764 12:40:34.442935
7765 12:40:34.443040 Set Vref, RX VrefLevel [Byte0]: 30
7766 12:40:34.446488 [Byte1]: 30
7767 12:40:34.450556
7768 12:40:34.450682 Set Vref, RX VrefLevel [Byte0]: 31
7769 12:40:34.453990 [Byte1]: 31
7770 12:40:34.458129
7771 12:40:34.458236 Set Vref, RX VrefLevel [Byte0]: 32
7772 12:40:34.461227 [Byte1]: 32
7773 12:40:34.465678
7774 12:40:34.465797 Set Vref, RX VrefLevel [Byte0]: 33
7775 12:40:34.469117 [Byte1]: 33
7776 12:40:34.472907
7777 12:40:34.473015 Set Vref, RX VrefLevel [Byte0]: 34
7778 12:40:34.476142 [Byte1]: 34
7779 12:40:34.480668
7780 12:40:34.480782 Set Vref, RX VrefLevel [Byte0]: 35
7781 12:40:34.484173 [Byte1]: 35
7782 12:40:34.488113
7783 12:40:34.488219 Set Vref, RX VrefLevel [Byte0]: 36
7784 12:40:34.491433 [Byte1]: 36
7785 12:40:34.495723
7786 12:40:34.495833 Set Vref, RX VrefLevel [Byte0]: 37
7787 12:40:34.498769 [Byte1]: 37
7788 12:40:34.502978
7789 12:40:34.503094 Set Vref, RX VrefLevel [Byte0]: 38
7790 12:40:34.506273 [Byte1]: 38
7791 12:40:34.510505
7792 12:40:34.510621 Set Vref, RX VrefLevel [Byte0]: 39
7793 12:40:34.513836 [Byte1]: 39
7794 12:40:34.518515
7795 12:40:34.518629 Set Vref, RX VrefLevel [Byte0]: 40
7796 12:40:34.521762 [Byte1]: 40
7797 12:40:34.525955
7798 12:40:34.526046 Set Vref, RX VrefLevel [Byte0]: 41
7799 12:40:34.529176 [Byte1]: 41
7800 12:40:34.533077
7801 12:40:34.533162 Set Vref, RX VrefLevel [Byte0]: 42
7802 12:40:34.536989 [Byte1]: 42
7803 12:40:34.540747
7804 12:40:34.540841 Set Vref, RX VrefLevel [Byte0]: 43
7805 12:40:34.544014 [Byte1]: 43
7806 12:40:34.548788
7807 12:40:34.548874 Set Vref, RX VrefLevel [Byte0]: 44
7808 12:40:34.551446 [Byte1]: 44
7809 12:40:34.556264
7810 12:40:34.556361 Set Vref, RX VrefLevel [Byte0]: 45
7811 12:40:34.559045 [Byte1]: 45
7812 12:40:34.563370
7813 12:40:34.563490 Set Vref, RX VrefLevel [Byte0]: 46
7814 12:40:34.566851 [Byte1]: 46
7815 12:40:34.571117
7816 12:40:34.571240 Set Vref, RX VrefLevel [Byte0]: 47
7817 12:40:34.574228 [Byte1]: 47
7818 12:40:34.578226
7819 12:40:34.578350 Set Vref, RX VrefLevel [Byte0]: 48
7820 12:40:34.581590 [Byte1]: 48
7821 12:40:34.586102
7822 12:40:34.586242 Set Vref, RX VrefLevel [Byte0]: 49
7823 12:40:34.589354 [Byte1]: 49
7824 12:40:34.593505
7825 12:40:34.593631 Set Vref, RX VrefLevel [Byte0]: 50
7826 12:40:34.596965 [Byte1]: 50
7827 12:40:34.600807
7828 12:40:34.600927 Set Vref, RX VrefLevel [Byte0]: 51
7829 12:40:34.604256 [Byte1]: 51
7830 12:40:34.608880
7831 12:40:34.609014 Set Vref, RX VrefLevel [Byte0]: 52
7832 12:40:34.612121 [Byte1]: 52
7833 12:40:34.615955
7834 12:40:34.619049 Set Vref, RX VrefLevel [Byte0]: 53
7835 12:40:34.622287 [Byte1]: 53
7836 12:40:34.622410
7837 12:40:34.626334 Set Vref, RX VrefLevel [Byte0]: 54
7838 12:40:34.629533 [Byte1]: 54
7839 12:40:34.629660
7840 12:40:34.632983 Set Vref, RX VrefLevel [Byte0]: 55
7841 12:40:34.635718 [Byte1]: 55
7842 12:40:34.635829
7843 12:40:34.639050 Set Vref, RX VrefLevel [Byte0]: 56
7844 12:40:34.642129 [Byte1]: 56
7845 12:40:34.646068
7846 12:40:34.646191 Set Vref, RX VrefLevel [Byte0]: 57
7847 12:40:34.649520 [Byte1]: 57
7848 12:40:34.653659
7849 12:40:34.653775 Set Vref, RX VrefLevel [Byte0]: 58
7850 12:40:34.656935 [Byte1]: 58
7851 12:40:34.661722
7852 12:40:34.661840 Set Vref, RX VrefLevel [Byte0]: 59
7853 12:40:34.664541 [Byte1]: 59
7854 12:40:34.668709
7855 12:40:34.668826 Set Vref, RX VrefLevel [Byte0]: 60
7856 12:40:34.672129 [Byte1]: 60
7857 12:40:34.676493
7858 12:40:34.676612 Set Vref, RX VrefLevel [Byte0]: 61
7859 12:40:34.679880 [Byte1]: 61
7860 12:40:34.683957
7861 12:40:34.684075 Set Vref, RX VrefLevel [Byte0]: 62
7862 12:40:34.687057 [Byte1]: 62
7863 12:40:34.691290
7864 12:40:34.691414 Set Vref, RX VrefLevel [Byte0]: 63
7865 12:40:34.694981 [Byte1]: 63
7866 12:40:34.698791
7867 12:40:34.698904 Set Vref, RX VrefLevel [Byte0]: 64
7868 12:40:34.702565 [Byte1]: 64
7869 12:40:34.706578
7870 12:40:34.706707 Set Vref, RX VrefLevel [Byte0]: 65
7871 12:40:34.710024 [Byte1]: 65
7872 12:40:34.714145
7873 12:40:34.714263 Set Vref, RX VrefLevel [Byte0]: 66
7874 12:40:34.717459 [Byte1]: 66
7875 12:40:34.721476
7876 12:40:34.721593 Set Vref, RX VrefLevel [Byte0]: 67
7877 12:40:34.724832 [Byte1]: 67
7878 12:40:34.729065
7879 12:40:34.729190 Set Vref, RX VrefLevel [Byte0]: 68
7880 12:40:34.732491 [Byte1]: 68
7881 12:40:34.736864
7882 12:40:34.736987 Set Vref, RX VrefLevel [Byte0]: 69
7883 12:40:34.739867 [Byte1]: 69
7884 12:40:34.744547
7885 12:40:34.744671 Set Vref, RX VrefLevel [Byte0]: 70
7886 12:40:34.747931 [Byte1]: 70
7887 12:40:34.751841
7888 12:40:34.751960 Set Vref, RX VrefLevel [Byte0]: 71
7889 12:40:34.755026 [Byte1]: 71
7890 12:40:34.759126
7891 12:40:34.759243 Set Vref, RX VrefLevel [Byte0]: 72
7892 12:40:34.762383 [Byte1]: 72
7893 12:40:34.766513
7894 12:40:34.766627 Set Vref, RX VrefLevel [Byte0]: 73
7895 12:40:34.769916 [Byte1]: 73
7896 12:40:34.774701
7897 12:40:34.774816 Final RX Vref Byte 0 = 55 to rank0
7898 12:40:34.777403 Final RX Vref Byte 1 = 63 to rank0
7899 12:40:34.780849 Final RX Vref Byte 0 = 55 to rank1
7900 12:40:34.784209 Final RX Vref Byte 1 = 63 to rank1==
7901 12:40:34.787812 Dram Type= 6, Freq= 0, CH_0, rank 0
7902 12:40:34.794722 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7903 12:40:34.794851 ==
7904 12:40:34.794953 DQS Delay:
7905 12:40:34.795046 DQS0 = 0, DQS1 = 0
7906 12:40:34.798070 DQM Delay:
7907 12:40:34.798177 DQM0 = 133, DQM1 = 127
7908 12:40:34.801232 DQ Delay:
7909 12:40:34.804220 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130
7910 12:40:34.807661 DQ4 =132, DQ5 =124, DQ6 =142, DQ7 =138
7911 12:40:34.810851 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7912 12:40:34.814106 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7913 12:40:34.814229
7914 12:40:34.814323
7915 12:40:34.814413
7916 12:40:34.817734 [DramC_TX_OE_Calibration] TA2
7917 12:40:34.820748 Original DQ_B0 (3 6) =30, OEN = 27
7918 12:40:34.824396 Original DQ_B1 (3 6) =30, OEN = 27
7919 12:40:34.827620 24, 0x0, End_B0=24 End_B1=24
7920 12:40:34.827743 25, 0x0, End_B0=25 End_B1=25
7921 12:40:34.831007 26, 0x0, End_B0=26 End_B1=26
7922 12:40:34.834372 27, 0x0, End_B0=27 End_B1=27
7923 12:40:34.837522 28, 0x0, End_B0=28 End_B1=28
7924 12:40:34.837643 29, 0x0, End_B0=29 End_B1=29
7925 12:40:34.840668 30, 0x0, End_B0=30 End_B1=30
7926 12:40:34.844414 31, 0x4141, End_B0=30 End_B1=30
7927 12:40:34.847810 Byte0 end_step=30 best_step=27
7928 12:40:34.850773 Byte1 end_step=30 best_step=27
7929 12:40:34.854385 Byte0 TX OE(2T, 0.5T) = (3, 3)
7930 12:40:34.854503 Byte1 TX OE(2T, 0.5T) = (3, 3)
7931 12:40:34.857394
7932 12:40:34.857502
7933 12:40:34.864230 [DQSOSCAuto] RK0, (LSB)MR18= 0x2722, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
7934 12:40:34.867640 CH0 RK0: MR19=303, MR18=2722
7935 12:40:34.873914 CH0_RK0: MR19=0x303, MR18=0x2722, DQSOSC=390, MR23=63, INC=24, DEC=16
7936 12:40:34.874048
7937 12:40:34.877301 ----->DramcWriteLeveling(PI) begin...
7938 12:40:34.877419 ==
7939 12:40:34.880771 Dram Type= 6, Freq= 0, CH_0, rank 1
7940 12:40:34.884180 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7941 12:40:34.884303 ==
7942 12:40:34.887500 Write leveling (Byte 0): 35 => 35
7943 12:40:34.891018 Write leveling (Byte 1): 27 => 27
7944 12:40:34.893781 DramcWriteLeveling(PI) end<-----
7945 12:40:34.893896
7946 12:40:34.893991 ==
7947 12:40:34.897178 Dram Type= 6, Freq= 0, CH_0, rank 1
7948 12:40:34.900665 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7949 12:40:34.900781 ==
7950 12:40:34.904133 [Gating] SW mode calibration
7951 12:40:34.910926 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7952 12:40:34.917369 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7953 12:40:34.920641 1 4 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7954 12:40:34.923968 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7955 12:40:34.930516 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7956 12:40:34.933788 1 4 12 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7957 12:40:34.936904 1 4 16 | B1->B0 | 2d2d 3837 | 0 1 | (0 0) (0 0)
7958 12:40:34.943739 1 4 20 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
7959 12:40:34.947061 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7960 12:40:34.950328 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7961 12:40:34.956914 1 5 0 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
7962 12:40:34.960466 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7963 12:40:34.963585 1 5 8 | B1->B0 | 3434 3636 | 1 1 | (1 1) (0 0)
7964 12:40:34.970537 1 5 12 | B1->B0 | 3434 3737 | 1 0 | (1 0) (0 0)
7965 12:40:34.973974 1 5 16 | B1->B0 | 2d2d 2626 | 0 0 | (0 0) (0 0)
7966 12:40:34.976989 1 5 20 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
7967 12:40:34.983738 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7968 12:40:34.987145 1 5 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7969 12:40:34.990603 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7970 12:40:34.996728 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7971 12:40:35.000131 1 6 8 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7972 12:40:35.003901 1 6 12 | B1->B0 | 2929 3838 | 0 0 | (0 0) (0 0)
7973 12:40:35.010505 1 6 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7974 12:40:35.013969 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7975 12:40:35.017303 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7976 12:40:35.020036 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7977 12:40:35.026992 1 7 0 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7978 12:40:35.030074 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7979 12:40:35.033282 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7980 12:40:35.040034 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7981 12:40:35.043391 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7982 12:40:35.046815 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7983 12:40:35.053199 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7984 12:40:35.056849 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7985 12:40:35.060462 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7986 12:40:35.066683 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7987 12:40:35.069968 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7988 12:40:35.073447 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 12:40:35.079956 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 12:40:35.083319 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 12:40:35.086680 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 12:40:35.093301 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 12:40:35.096949 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 12:40:35.100237 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 12:40:35.106562 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 12:40:35.109915 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7997 12:40:35.113460 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7998 12:40:35.119871 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7999 12:40:35.120003 Total UI for P1: 0, mck2ui 16
8000 12:40:35.126653 best dqsien dly found for B0: ( 1, 9, 14)
8001 12:40:35.126778 Total UI for P1: 0, mck2ui 16
8002 12:40:35.130171 best dqsien dly found for B1: ( 1, 9, 14)
8003 12:40:35.136695 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8004 12:40:35.140272 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8005 12:40:35.140408
8006 12:40:35.142840 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8007 12:40:35.146557 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8008 12:40:35.149823 [Gating] SW calibration Done
8009 12:40:35.149945 ==
8010 12:40:35.153251 Dram Type= 6, Freq= 0, CH_0, rank 1
8011 12:40:35.156484 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8012 12:40:35.156603 ==
8013 12:40:35.159893 RX Vref Scan: 0
8014 12:40:35.160012
8015 12:40:35.160108 RX Vref 0 -> 0, step: 1
8016 12:40:35.160199
8017 12:40:35.163240 RX Delay 0 -> 252, step: 8
8018 12:40:35.166435 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8019 12:40:35.173173 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8020 12:40:35.176213 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8021 12:40:35.179314 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8022 12:40:35.182563 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8023 12:40:35.185897 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8024 12:40:35.192698 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8025 12:40:35.196107 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8026 12:40:35.199357 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8027 12:40:35.203370 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8028 12:40:35.206311 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8029 12:40:35.212491 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8030 12:40:35.215997 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8031 12:40:35.219505 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8032 12:40:35.223000 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8033 12:40:35.226361 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8034 12:40:35.229113 ==
8035 12:40:35.232580 Dram Type= 6, Freq= 0, CH_0, rank 1
8036 12:40:35.235995 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8037 12:40:35.236085 ==
8038 12:40:35.236152 DQS Delay:
8039 12:40:35.239412 DQS0 = 0, DQS1 = 0
8040 12:40:35.239498 DQM Delay:
8041 12:40:35.242977 DQM0 = 137, DQM1 = 130
8042 12:40:35.243064 DQ Delay:
8043 12:40:35.245993 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8044 12:40:35.249186 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8045 12:40:35.252470 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8046 12:40:35.256263 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8047 12:40:35.256372
8048 12:40:35.256439
8049 12:40:35.256500 ==
8050 12:40:35.259318 Dram Type= 6, Freq= 0, CH_0, rank 1
8051 12:40:35.266076 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8052 12:40:35.266190 ==
8053 12:40:35.266259
8054 12:40:35.266320
8055 12:40:35.266377 TX Vref Scan disable
8056 12:40:35.269463 == TX Byte 0 ==
8057 12:40:35.272843 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8058 12:40:35.279257 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8059 12:40:35.279365 == TX Byte 1 ==
8060 12:40:35.282449 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8061 12:40:35.289438 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8062 12:40:35.289581 ==
8063 12:40:35.292561 Dram Type= 6, Freq= 0, CH_0, rank 1
8064 12:40:35.295573 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8065 12:40:35.295689 ==
8066 12:40:35.310386
8067 12:40:35.314232 TX Vref early break, caculate TX vref
8068 12:40:35.317480 TX Vref=16, minBit 1, minWin=22, winSum=386
8069 12:40:35.320609 TX Vref=18, minBit 0, minWin=24, winSum=403
8070 12:40:35.324196 TX Vref=20, minBit 7, minWin=23, winSum=405
8071 12:40:35.327419 TX Vref=22, minBit 1, minWin=24, winSum=413
8072 12:40:35.330832 TX Vref=24, minBit 3, minWin=25, winSum=423
8073 12:40:35.337579 TX Vref=26, minBit 3, minWin=25, winSum=426
8074 12:40:35.340948 TX Vref=28, minBit 3, minWin=24, winSum=422
8075 12:40:35.343729 TX Vref=30, minBit 1, minWin=25, winSum=417
8076 12:40:35.347212 TX Vref=32, minBit 4, minWin=24, winSum=409
8077 12:40:35.350533 TX Vref=34, minBit 0, minWin=24, winSum=404
8078 12:40:35.353825 TX Vref=36, minBit 0, minWin=24, winSum=390
8079 12:40:35.360614 [TxChooseVref] Worse bit 3, Min win 25, Win sum 426, Final Vref 26
8080 12:40:35.360761
8081 12:40:35.363939 Final TX Range 0 Vref 26
8082 12:40:35.364055
8083 12:40:35.364149 ==
8084 12:40:35.367284 Dram Type= 6, Freq= 0, CH_0, rank 1
8085 12:40:35.370752 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8086 12:40:35.370868 ==
8087 12:40:35.370961
8088 12:40:35.371054
8089 12:40:35.373457 TX Vref Scan disable
8090 12:40:35.380254 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8091 12:40:35.380401 == TX Byte 0 ==
8092 12:40:35.383503 u2DelayCellOfst[0]=13 cells (4 PI)
8093 12:40:35.386725 u2DelayCellOfst[1]=13 cells (4 PI)
8094 12:40:35.390145 u2DelayCellOfst[2]=6 cells (2 PI)
8095 12:40:35.393521 u2DelayCellOfst[3]=6 cells (2 PI)
8096 12:40:35.396802 u2DelayCellOfst[4]=6 cells (2 PI)
8097 12:40:35.400660 u2DelayCellOfst[5]=0 cells (0 PI)
8098 12:40:35.403884 u2DelayCellOfst[6]=13 cells (4 PI)
8099 12:40:35.406903 u2DelayCellOfst[7]=13 cells (4 PI)
8100 12:40:35.410212 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8101 12:40:35.413572 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8102 12:40:35.416874 == TX Byte 1 ==
8103 12:40:35.420401 u2DelayCellOfst[8]=0 cells (0 PI)
8104 12:40:35.420520 u2DelayCellOfst[9]=0 cells (0 PI)
8105 12:40:35.423648 u2DelayCellOfst[10]=6 cells (2 PI)
8106 12:40:35.426915 u2DelayCellOfst[11]=3 cells (1 PI)
8107 12:40:35.430081 u2DelayCellOfst[12]=10 cells (3 PI)
8108 12:40:35.433869 u2DelayCellOfst[13]=10 cells (3 PI)
8109 12:40:35.437000 u2DelayCellOfst[14]=13 cells (4 PI)
8110 12:40:35.440214 u2DelayCellOfst[15]=10 cells (3 PI)
8111 12:40:35.443706 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8112 12:40:35.449938 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8113 12:40:35.450091 DramC Write-DBI on
8114 12:40:35.450191 ==
8115 12:40:35.453366 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 12:40:35.460062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 12:40:35.460208 ==
8118 12:40:35.460316
8119 12:40:35.460409
8120 12:40:35.460500 TX Vref Scan disable
8121 12:40:35.464164 == TX Byte 0 ==
8122 12:40:35.466934 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8123 12:40:35.470485 == TX Byte 1 ==
8124 12:40:35.473828 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8125 12:40:35.477166 DramC Write-DBI off
8126 12:40:35.477286
8127 12:40:35.477381 [DATLAT]
8128 12:40:35.477472 Freq=1600, CH0 RK1
8129 12:40:35.477561
8130 12:40:35.480636 DATLAT Default: 0xf
8131 12:40:35.480744 0, 0xFFFF, sum = 0
8132 12:40:35.483852 1, 0xFFFF, sum = 0
8133 12:40:35.487142 2, 0xFFFF, sum = 0
8134 12:40:35.487264 3, 0xFFFF, sum = 0
8135 12:40:35.490337 4, 0xFFFF, sum = 0
8136 12:40:35.490454 5, 0xFFFF, sum = 0
8137 12:40:35.493471 6, 0xFFFF, sum = 0
8138 12:40:35.493586 7, 0xFFFF, sum = 0
8139 12:40:35.497246 8, 0xFFFF, sum = 0
8140 12:40:35.497371 9, 0xFFFF, sum = 0
8141 12:40:35.500524 10, 0xFFFF, sum = 0
8142 12:40:35.500643 11, 0xFFFF, sum = 0
8143 12:40:35.503865 12, 0xFFFF, sum = 0
8144 12:40:35.503985 13, 0xFFFF, sum = 0
8145 12:40:35.507201 14, 0x0, sum = 1
8146 12:40:35.507328 15, 0x0, sum = 2
8147 12:40:35.510461 16, 0x0, sum = 3
8148 12:40:35.510581 17, 0x0, sum = 4
8149 12:40:35.513742 best_step = 15
8150 12:40:35.513857
8151 12:40:35.513950 ==
8152 12:40:35.516913 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 12:40:35.520184 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 12:40:35.520313 ==
8155 12:40:35.520410 RX Vref Scan: 0
8156 12:40:35.523564
8157 12:40:35.523677 RX Vref 0 -> 0, step: 1
8158 12:40:35.523771
8159 12:40:35.527059 RX Delay 19 -> 252, step: 4
8160 12:40:35.530407 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8161 12:40:35.536988 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8162 12:40:35.540240 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8163 12:40:35.543554 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8164 12:40:35.546730 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8165 12:40:35.550358 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8166 12:40:35.556960 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8167 12:40:35.560445 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8168 12:40:35.563583 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8169 12:40:35.566809 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8170 12:40:35.569935 iDelay=191, Bit 10, Center 130 (79 ~ 182) 104
8171 12:40:35.576883 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8172 12:40:35.580308 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8173 12:40:35.583637 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8174 12:40:35.586440 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8175 12:40:35.589805 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8176 12:40:35.593074 ==
8177 12:40:35.593196 Dram Type= 6, Freq= 0, CH_0, rank 1
8178 12:40:35.599955 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8179 12:40:35.600105 ==
8180 12:40:35.600208 DQS Delay:
8181 12:40:35.603071 DQS0 = 0, DQS1 = 0
8182 12:40:35.603183 DQM Delay:
8183 12:40:35.606708 DQM0 = 134, DQM1 = 127
8184 12:40:35.606834 DQ Delay:
8185 12:40:35.609926 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =132
8186 12:40:35.613543 DQ4 =136, DQ5 =124, DQ6 =138, DQ7 =140
8187 12:40:35.616677 DQ8 =118, DQ9 =116, DQ10 =130, DQ11 =118
8188 12:40:35.619875 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =134
8189 12:40:35.620005
8190 12:40:35.620103
8191 12:40:35.620195
8192 12:40:35.623030 [DramC_TX_OE_Calibration] TA2
8193 12:40:35.626282 Original DQ_B0 (3 6) =30, OEN = 27
8194 12:40:35.630323 Original DQ_B1 (3 6) =30, OEN = 27
8195 12:40:35.633736 24, 0x0, End_B0=24 End_B1=24
8196 12:40:35.636539 25, 0x0, End_B0=25 End_B1=25
8197 12:40:35.636665 26, 0x0, End_B0=26 End_B1=26
8198 12:40:35.640001 27, 0x0, End_B0=27 End_B1=27
8199 12:40:35.643240 28, 0x0, End_B0=28 End_B1=28
8200 12:40:35.646509 29, 0x0, End_B0=29 End_B1=29
8201 12:40:35.646636 30, 0x0, End_B0=30 End_B1=30
8202 12:40:35.649910 31, 0x4141, End_B0=30 End_B1=30
8203 12:40:35.653363 Byte0 end_step=30 best_step=27
8204 12:40:35.656739 Byte1 end_step=30 best_step=27
8205 12:40:35.660063 Byte0 TX OE(2T, 0.5T) = (3, 3)
8206 12:40:35.663244 Byte1 TX OE(2T, 0.5T) = (3, 3)
8207 12:40:35.663363
8208 12:40:35.663458
8209 12:40:35.669772 [DQSOSCAuto] RK1, (LSB)MR18= 0x220a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8210 12:40:35.673026 CH0 RK1: MR19=303, MR18=220A
8211 12:40:35.680067 CH0_RK1: MR19=0x303, MR18=0x220A, DQSOSC=392, MR23=63, INC=24, DEC=16
8212 12:40:35.683477 [RxdqsGatingPostProcess] freq 1600
8213 12:40:35.686829 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8214 12:40:35.689579 best DQS0 dly(2T, 0.5T) = (1, 1)
8215 12:40:35.693139 best DQS1 dly(2T, 0.5T) = (1, 1)
8216 12:40:35.696601 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8217 12:40:35.699931 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8218 12:40:35.703356 best DQS0 dly(2T, 0.5T) = (1, 1)
8219 12:40:35.706728 best DQS1 dly(2T, 0.5T) = (1, 1)
8220 12:40:35.709966 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8221 12:40:35.712791 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8222 12:40:35.716734 Pre-setting of DQS Precalculation
8223 12:40:35.719485 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8224 12:40:35.719597 ==
8225 12:40:35.723207 Dram Type= 6, Freq= 0, CH_1, rank 0
8226 12:40:35.726184 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8227 12:40:35.729861 ==
8228 12:40:35.732887 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8229 12:40:35.736522 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8230 12:40:35.743027 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8231 12:40:35.749552 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8232 12:40:35.756475 [CA 0] Center 43 (14~72) winsize 59
8233 12:40:35.759901 [CA 1] Center 42 (13~72) winsize 60
8234 12:40:35.763309 [CA 2] Center 39 (10~68) winsize 59
8235 12:40:35.766882 [CA 3] Center 39 (10~68) winsize 59
8236 12:40:35.770230 [CA 4] Center 38 (9~68) winsize 60
8237 12:40:35.773388 [CA 5] Center 37 (8~67) winsize 60
8238 12:40:35.773511
8239 12:40:35.776473 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8240 12:40:35.776588
8241 12:40:35.780200 [CATrainingPosCal] consider 1 rank data
8242 12:40:35.783247 u2DelayCellTimex100 = 290/100 ps
8243 12:40:35.790097 CA0 delay=43 (14~72),Diff = 6 PI (20 cell)
8244 12:40:35.793453 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8245 12:40:35.796592 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8246 12:40:35.800143 CA3 delay=39 (10~68),Diff = 2 PI (6 cell)
8247 12:40:35.803347 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8248 12:40:35.806720 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8249 12:40:35.806854
8250 12:40:35.810082 CA PerBit enable=1, Macro0, CA PI delay=37
8251 12:40:35.810198
8252 12:40:35.812765 [CBTSetCACLKResult] CA Dly = 37
8253 12:40:35.816093 CS Dly: 11 (0~42)
8254 12:40:35.819510 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8255 12:40:35.822963 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8256 12:40:35.823072 ==
8257 12:40:35.826468 Dram Type= 6, Freq= 0, CH_1, rank 1
8258 12:40:35.833022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8259 12:40:35.833155 ==
8260 12:40:35.836426 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8261 12:40:35.842919 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8262 12:40:35.846145 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8263 12:40:35.852796 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8264 12:40:35.860206 [CA 0] Center 42 (13~72) winsize 60
8265 12:40:35.863384 [CA 1] Center 42 (13~72) winsize 60
8266 12:40:35.866671 [CA 2] Center 39 (10~69) winsize 60
8267 12:40:35.870026 [CA 3] Center 38 (9~68) winsize 60
8268 12:40:35.873475 [CA 4] Center 39 (9~69) winsize 61
8269 12:40:35.876910 [CA 5] Center 38 (9~68) winsize 60
8270 12:40:35.877028
8271 12:40:35.880311 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8272 12:40:35.880422
8273 12:40:35.883555 [CATrainingPosCal] consider 2 rank data
8274 12:40:35.886929 u2DelayCellTimex100 = 290/100 ps
8275 12:40:35.890123 CA0 delay=43 (14~72),Diff = 5 PI (16 cell)
8276 12:40:35.896582 CA1 delay=42 (13~72),Diff = 4 PI (13 cell)
8277 12:40:35.900344 CA2 delay=39 (10~68),Diff = 1 PI (3 cell)
8278 12:40:35.903497 CA3 delay=39 (10~68),Diff = 1 PI (3 cell)
8279 12:40:35.906831 CA4 delay=38 (9~68),Diff = 0 PI (0 cell)
8280 12:40:35.910117 CA5 delay=38 (9~67),Diff = 0 PI (0 cell)
8281 12:40:35.910245
8282 12:40:35.913612 CA PerBit enable=1, Macro0, CA PI delay=38
8283 12:40:35.913726
8284 12:40:35.917031 [CBTSetCACLKResult] CA Dly = 38
8285 12:40:35.919774 CS Dly: 12 (0~44)
8286 12:40:35.923143 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8287 12:40:35.926776 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8288 12:40:35.926895
8289 12:40:35.930320 ----->DramcWriteLeveling(PI) begin...
8290 12:40:35.930433 ==
8291 12:40:35.933030 Dram Type= 6, Freq= 0, CH_1, rank 0
8292 12:40:35.939844 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8293 12:40:35.940001 ==
8294 12:40:35.943089 Write leveling (Byte 0): 25 => 25
8295 12:40:35.946402 Write leveling (Byte 1): 27 => 27
8296 12:40:35.946524 DramcWriteLeveling(PI) end<-----
8297 12:40:35.946622
8298 12:40:35.949846 ==
8299 12:40:35.953079 Dram Type= 6, Freq= 0, CH_1, rank 0
8300 12:40:35.956478 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8301 12:40:35.956596 ==
8302 12:40:35.959600 [Gating] SW mode calibration
8303 12:40:35.966545 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8304 12:40:35.969977 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8305 12:40:35.976232 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8306 12:40:35.979653 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8307 12:40:35.983016 1 4 8 | B1->B0 | 2323 2d2d | 1 0 | (1 1) (0 0)
8308 12:40:35.989828 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8309 12:40:35.993308 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8310 12:40:35.996616 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8311 12:40:36.002836 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8312 12:40:36.006064 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8313 12:40:36.010016 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8314 12:40:36.016074 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8315 12:40:36.019965 1 5 8 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
8316 12:40:36.022955 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8317 12:40:36.029846 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8318 12:40:36.033231 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8319 12:40:36.035985 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8320 12:40:36.039495 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8321 12:40:36.046183 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8322 12:40:36.049514 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 12:40:36.052916 1 6 8 | B1->B0 | 2424 3737 | 0 1 | (0 0) (0 0)
8324 12:40:36.059795 1 6 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
8325 12:40:36.063182 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8326 12:40:36.065983 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8327 12:40:36.072897 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8328 12:40:36.076178 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8329 12:40:36.079650 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8330 12:40:36.086074 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8331 12:40:36.089878 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8332 12:40:36.092638 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8333 12:40:36.099548 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8334 12:40:36.102876 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8335 12:40:36.106183 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8336 12:40:36.112951 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8337 12:40:36.116271 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8338 12:40:36.119602 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8339 12:40:36.126176 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 12:40:36.129294 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 12:40:36.132889 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 12:40:36.139303 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 12:40:36.142811 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 12:40:36.146281 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 12:40:36.149589 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 12:40:36.156124 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8347 12:40:36.159513 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8348 12:40:36.162846 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8349 12:40:36.169548 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8350 12:40:36.172385 Total UI for P1: 0, mck2ui 16
8351 12:40:36.175837 best dqsien dly found for B0: ( 1, 9, 8)
8352 12:40:36.179123 Total UI for P1: 0, mck2ui 16
8353 12:40:36.182432 best dqsien dly found for B1: ( 1, 9, 10)
8354 12:40:36.186240 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8355 12:40:36.188967 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8356 12:40:36.189046
8357 12:40:36.192361 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8358 12:40:36.196179 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8359 12:40:36.199384 [Gating] SW calibration Done
8360 12:40:36.199456 ==
8361 12:40:36.202621 Dram Type= 6, Freq= 0, CH_1, rank 0
8362 12:40:36.205941 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8363 12:40:36.206020 ==
8364 12:40:36.209271 RX Vref Scan: 0
8365 12:40:36.209355
8366 12:40:36.209421 RX Vref 0 -> 0, step: 1
8367 12:40:36.209484
8368 12:40:36.212565 RX Delay 0 -> 252, step: 8
8369 12:40:36.216035 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8370 12:40:36.222738 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8371 12:40:36.226145 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8372 12:40:36.229091 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8373 12:40:36.232650 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8374 12:40:36.236100 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8375 12:40:36.242899 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8376 12:40:36.245910 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8377 12:40:36.248965 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8378 12:40:36.252900 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8379 12:40:36.255656 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8380 12:40:36.262418 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8381 12:40:36.265597 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8382 12:40:36.269360 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8383 12:40:36.272643 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8384 12:40:36.275410 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8385 12:40:36.278893 ==
8386 12:40:36.282332 Dram Type= 6, Freq= 0, CH_1, rank 0
8387 12:40:36.285527 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8388 12:40:36.285610 ==
8389 12:40:36.285678 DQS Delay:
8390 12:40:36.288844 DQS0 = 0, DQS1 = 0
8391 12:40:36.288916 DQM Delay:
8392 12:40:36.292668 DQM0 = 136, DQM1 = 132
8393 12:40:36.292750 DQ Delay:
8394 12:40:36.295997 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8395 12:40:36.298866 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8396 12:40:36.302199 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8397 12:40:36.305598 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8398 12:40:36.305718
8399 12:40:36.305813
8400 12:40:36.305901 ==
8401 12:40:36.308870 Dram Type= 6, Freq= 0, CH_1, rank 0
8402 12:40:36.315816 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8403 12:40:36.315908 ==
8404 12:40:36.315975
8405 12:40:36.316035
8406 12:40:36.316110 TX Vref Scan disable
8407 12:40:36.319473 == TX Byte 0 ==
8408 12:40:36.322643 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8409 12:40:36.329130 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8410 12:40:36.329250 == TX Byte 1 ==
8411 12:40:36.332634 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8412 12:40:36.336069 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8413 12:40:36.338898 ==
8414 12:40:36.342286 Dram Type= 6, Freq= 0, CH_1, rank 0
8415 12:40:36.345693 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8416 12:40:36.345780 ==
8417 12:40:36.359204
8418 12:40:36.362295 TX Vref early break, caculate TX vref
8419 12:40:36.365297 TX Vref=16, minBit 0, minWin=23, winSum=380
8420 12:40:36.368657 TX Vref=18, minBit 0, minWin=23, winSum=387
8421 12:40:36.372033 TX Vref=20, minBit 0, minWin=24, winSum=399
8422 12:40:36.375220 TX Vref=22, minBit 0, minWin=24, winSum=408
8423 12:40:36.378963 TX Vref=24, minBit 1, minWin=25, winSum=415
8424 12:40:36.385605 TX Vref=26, minBit 0, minWin=25, winSum=425
8425 12:40:36.388891 TX Vref=28, minBit 2, minWin=25, winSum=429
8426 12:40:36.392268 TX Vref=30, minBit 0, minWin=25, winSum=423
8427 12:40:36.395000 TX Vref=32, minBit 0, minWin=24, winSum=413
8428 12:40:36.398634 TX Vref=34, minBit 2, minWin=24, winSum=407
8429 12:40:36.401918 TX Vref=36, minBit 0, minWin=22, winSum=392
8430 12:40:36.408934 [TxChooseVref] Worse bit 2, Min win 25, Win sum 429, Final Vref 28
8431 12:40:36.409064
8432 12:40:36.411637 Final TX Range 0 Vref 28
8433 12:40:36.411717
8434 12:40:36.411781 ==
8435 12:40:36.415008 Dram Type= 6, Freq= 0, CH_1, rank 0
8436 12:40:36.418471 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8437 12:40:36.418557 ==
8438 12:40:36.418623
8439 12:40:36.421917
8440 12:40:36.421996 TX Vref Scan disable
8441 12:40:36.428354 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8442 12:40:36.428454 == TX Byte 0 ==
8443 12:40:36.431500 u2DelayCellOfst[0]=13 cells (4 PI)
8444 12:40:36.435096 u2DelayCellOfst[1]=10 cells (3 PI)
8445 12:40:36.438276 u2DelayCellOfst[2]=0 cells (0 PI)
8446 12:40:36.441610 u2DelayCellOfst[3]=6 cells (2 PI)
8447 12:40:36.445030 u2DelayCellOfst[4]=6 cells (2 PI)
8448 12:40:36.448493 u2DelayCellOfst[5]=16 cells (5 PI)
8449 12:40:36.451871 u2DelayCellOfst[6]=16 cells (5 PI)
8450 12:40:36.455238 u2DelayCellOfst[7]=6 cells (2 PI)
8451 12:40:36.458656 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8452 12:40:36.461947 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8453 12:40:36.465349 == TX Byte 1 ==
8454 12:40:36.468152 u2DelayCellOfst[8]=0 cells (0 PI)
8455 12:40:36.468264 u2DelayCellOfst[9]=3 cells (1 PI)
8456 12:40:36.471793 u2DelayCellOfst[10]=13 cells (4 PI)
8457 12:40:36.474966 u2DelayCellOfst[11]=6 cells (2 PI)
8458 12:40:36.478140 u2DelayCellOfst[12]=16 cells (5 PI)
8459 12:40:36.481541 u2DelayCellOfst[13]=16 cells (5 PI)
8460 12:40:36.484925 u2DelayCellOfst[14]=16 cells (5 PI)
8461 12:40:36.488325 u2DelayCellOfst[15]=16 cells (5 PI)
8462 12:40:36.491433 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8463 12:40:36.498187 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8464 12:40:36.498289 DramC Write-DBI on
8465 12:40:36.498362 ==
8466 12:40:36.501594 Dram Type= 6, Freq= 0, CH_1, rank 0
8467 12:40:36.508019 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8468 12:40:36.508153 ==
8469 12:40:36.508247
8470 12:40:36.508344
8471 12:40:36.508405 TX Vref Scan disable
8472 12:40:36.511795 == TX Byte 0 ==
8473 12:40:36.515316 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8474 12:40:36.518702 == TX Byte 1 ==
8475 12:40:36.522136 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8476 12:40:36.522226 DramC Write-DBI off
8477 12:40:36.525514
8478 12:40:36.525623 [DATLAT]
8479 12:40:36.525714 Freq=1600, CH1 RK0
8480 12:40:36.525804
8481 12:40:36.528931 DATLAT Default: 0xf
8482 12:40:36.529013 0, 0xFFFF, sum = 0
8483 12:40:36.532249 1, 0xFFFF, sum = 0
8484 12:40:36.532357 2, 0xFFFF, sum = 0
8485 12:40:36.535116 3, 0xFFFF, sum = 0
8486 12:40:36.538596 4, 0xFFFF, sum = 0
8487 12:40:36.538720 5, 0xFFFF, sum = 0
8488 12:40:36.541959 6, 0xFFFF, sum = 0
8489 12:40:36.542071 7, 0xFFFF, sum = 0
8490 12:40:36.545124 8, 0xFFFF, sum = 0
8491 12:40:36.545209 9, 0xFFFF, sum = 0
8492 12:40:36.548243 10, 0xFFFF, sum = 0
8493 12:40:36.548372 11, 0xFFFF, sum = 0
8494 12:40:36.551621 12, 0xFFFF, sum = 0
8495 12:40:36.551702 13, 0xFFFF, sum = 0
8496 12:40:36.555031 14, 0x0, sum = 1
8497 12:40:36.555139 15, 0x0, sum = 2
8498 12:40:36.558256 16, 0x0, sum = 3
8499 12:40:36.558333 17, 0x0, sum = 4
8500 12:40:36.562258 best_step = 15
8501 12:40:36.562351
8502 12:40:36.562416 ==
8503 12:40:36.565312 Dram Type= 6, Freq= 0, CH_1, rank 0
8504 12:40:36.568750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8505 12:40:36.568838 ==
8506 12:40:36.568903 RX Vref Scan: 1
8507 12:40:36.571562
8508 12:40:36.571644 Set Vref Range= 24 -> 127
8509 12:40:36.571706
8510 12:40:36.575020 RX Vref 24 -> 127, step: 1
8511 12:40:36.575105
8512 12:40:36.578415 RX Delay 27 -> 252, step: 4
8513 12:40:36.578501
8514 12:40:36.581584 Set Vref, RX VrefLevel [Byte0]: 24
8515 12:40:36.584722 [Byte1]: 24
8516 12:40:36.584832
8517 12:40:36.588477 Set Vref, RX VrefLevel [Byte0]: 25
8518 12:40:36.591898 [Byte1]: 25
8519 12:40:36.591988
8520 12:40:36.595277 Set Vref, RX VrefLevel [Byte0]: 26
8521 12:40:36.598589 [Byte1]: 26
8522 12:40:36.601934
8523 12:40:36.602034 Set Vref, RX VrefLevel [Byte0]: 27
8524 12:40:36.605281 [Byte1]: 27
8525 12:40:36.609353
8526 12:40:36.609477 Set Vref, RX VrefLevel [Byte0]: 28
8527 12:40:36.613234 [Byte1]: 28
8528 12:40:36.616844
8529 12:40:36.616930 Set Vref, RX VrefLevel [Byte0]: 29
8530 12:40:36.620168 [Byte1]: 29
8531 12:40:36.625678
8532 12:40:36.625771 Set Vref, RX VrefLevel [Byte0]: 30
8533 12:40:36.629125 [Byte1]: 30
8534 12:40:36.632542
8535 12:40:36.632631 Set Vref, RX VrefLevel [Byte0]: 31
8536 12:40:36.635323 [Byte1]: 31
8537 12:40:36.640076
8538 12:40:36.640186 Set Vref, RX VrefLevel [Byte0]: 32
8539 12:40:36.642952 [Byte1]: 32
8540 12:40:36.647572
8541 12:40:36.647656 Set Vref, RX VrefLevel [Byte0]: 33
8542 12:40:36.650350 [Byte1]: 33
8543 12:40:36.655017
8544 12:40:36.655111 Set Vref, RX VrefLevel [Byte0]: 34
8545 12:40:36.658418 [Byte1]: 34
8546 12:40:36.662188
8547 12:40:36.662298 Set Vref, RX VrefLevel [Byte0]: 35
8548 12:40:36.665930 [Byte1]: 35
8549 12:40:36.669732
8550 12:40:36.669853 Set Vref, RX VrefLevel [Byte0]: 36
8551 12:40:36.673320 [Byte1]: 36
8552 12:40:36.677437
8553 12:40:36.677526 Set Vref, RX VrefLevel [Byte0]: 37
8554 12:40:36.680591 [Byte1]: 37
8555 12:40:36.685048
8556 12:40:36.685165 Set Vref, RX VrefLevel [Byte0]: 38
8557 12:40:36.688437 [Byte1]: 38
8558 12:40:36.692245
8559 12:40:36.692341 Set Vref, RX VrefLevel [Byte0]: 39
8560 12:40:36.695539 [Byte1]: 39
8561 12:40:36.699831
8562 12:40:36.699949 Set Vref, RX VrefLevel [Byte0]: 40
8563 12:40:36.703792 [Byte1]: 40
8564 12:40:36.707638
8565 12:40:36.707753 Set Vref, RX VrefLevel [Byte0]: 41
8566 12:40:36.710795 [Byte1]: 41
8567 12:40:36.715192
8568 12:40:36.715314 Set Vref, RX VrefLevel [Byte0]: 42
8569 12:40:36.718676 [Byte1]: 42
8570 12:40:36.722666
8571 12:40:36.722780 Set Vref, RX VrefLevel [Byte0]: 43
8572 12:40:36.725630 [Byte1]: 43
8573 12:40:36.730245
8574 12:40:36.730353 Set Vref, RX VrefLevel [Byte0]: 44
8575 12:40:36.733777 [Byte1]: 44
8576 12:40:36.737781
8577 12:40:36.737885 Set Vref, RX VrefLevel [Byte0]: 45
8578 12:40:36.741084 [Byte1]: 45
8579 12:40:36.745179
8580 12:40:36.745298 Set Vref, RX VrefLevel [Byte0]: 46
8581 12:40:36.748602 [Byte1]: 46
8582 12:40:36.752838
8583 12:40:36.752946 Set Vref, RX VrefLevel [Byte0]: 47
8584 12:40:36.756191 [Byte1]: 47
8585 12:40:36.760372
8586 12:40:36.760476 Set Vref, RX VrefLevel [Byte0]: 48
8587 12:40:36.763746 [Byte1]: 48
8588 12:40:36.767898
8589 12:40:36.768003 Set Vref, RX VrefLevel [Byte0]: 49
8590 12:40:36.771146 [Byte1]: 49
8591 12:40:36.775402
8592 12:40:36.775508 Set Vref, RX VrefLevel [Byte0]: 50
8593 12:40:36.778751 [Byte1]: 50
8594 12:40:36.782749
8595 12:40:36.782863 Set Vref, RX VrefLevel [Byte0]: 51
8596 12:40:36.785961 [Byte1]: 51
8597 12:40:36.790646
8598 12:40:36.790755 Set Vref, RX VrefLevel [Byte0]: 52
8599 12:40:36.793960 [Byte1]: 52
8600 12:40:36.797721
8601 12:40:36.797824 Set Vref, RX VrefLevel [Byte0]: 53
8602 12:40:36.801167 [Byte1]: 53
8603 12:40:36.805247
8604 12:40:36.805330 Set Vref, RX VrefLevel [Byte0]: 54
8605 12:40:36.808895 [Byte1]: 54
8606 12:40:36.813110
8607 12:40:36.813212 Set Vref, RX VrefLevel [Byte0]: 55
8608 12:40:36.816162 [Byte1]: 55
8609 12:40:36.820386
8610 12:40:36.820470 Set Vref, RX VrefLevel [Byte0]: 56
8611 12:40:36.823815 [Byte1]: 56
8612 12:40:36.828545
8613 12:40:36.828635 Set Vref, RX VrefLevel [Byte0]: 57
8614 12:40:36.831194 [Byte1]: 57
8615 12:40:36.835748
8616 12:40:36.835833 Set Vref, RX VrefLevel [Byte0]: 58
8617 12:40:36.839091 [Byte1]: 58
8618 12:40:36.842916
8619 12:40:36.843033 Set Vref, RX VrefLevel [Byte0]: 59
8620 12:40:36.846331 [Byte1]: 59
8621 12:40:36.850920
8622 12:40:36.851035 Set Vref, RX VrefLevel [Byte0]: 60
8623 12:40:36.853716 [Byte1]: 60
8624 12:40:36.858410
8625 12:40:36.858522 Set Vref, RX VrefLevel [Byte0]: 61
8626 12:40:36.861201 [Byte1]: 61
8627 12:40:36.865943
8628 12:40:36.866048 Set Vref, RX VrefLevel [Byte0]: 62
8629 12:40:36.868711 [Byte1]: 62
8630 12:40:36.873502
8631 12:40:36.873636 Set Vref, RX VrefLevel [Byte0]: 63
8632 12:40:36.876908 [Byte1]: 63
8633 12:40:36.881141
8634 12:40:36.881274 Set Vref, RX VrefLevel [Byte0]: 64
8635 12:40:36.883850 [Byte1]: 64
8636 12:40:36.888522
8637 12:40:36.888643 Set Vref, RX VrefLevel [Byte0]: 65
8638 12:40:36.891850 [Byte1]: 65
8639 12:40:36.895847
8640 12:40:36.895955 Set Vref, RX VrefLevel [Byte0]: 66
8641 12:40:36.899204 [Byte1]: 66
8642 12:40:36.903291
8643 12:40:36.903408 Set Vref, RX VrefLevel [Byte0]: 67
8644 12:40:36.906651 [Byte1]: 67
8645 12:40:36.910872
8646 12:40:36.910985 Set Vref, RX VrefLevel [Byte0]: 68
8647 12:40:36.913893 [Byte1]: 68
8648 12:40:36.918723
8649 12:40:36.918847 Set Vref, RX VrefLevel [Byte0]: 69
8650 12:40:36.921859 [Byte1]: 69
8651 12:40:36.925894
8652 12:40:36.926015 Set Vref, RX VrefLevel [Byte0]: 70
8653 12:40:36.929212 [Byte1]: 70
8654 12:40:36.933798
8655 12:40:36.933921 Set Vref, RX VrefLevel [Byte0]: 71
8656 12:40:36.937054 [Byte1]: 71
8657 12:40:36.941368
8658 12:40:36.941486 Set Vref, RX VrefLevel [Byte0]: 72
8659 12:40:36.944667 [Byte1]: 72
8660 12:40:36.948388
8661 12:40:36.948497 Set Vref, RX VrefLevel [Byte0]: 73
8662 12:40:36.952052 [Byte1]: 73
8663 12:40:36.956176
8664 12:40:36.956301 Set Vref, RX VrefLevel [Byte0]: 74
8665 12:40:36.959287 [Byte1]: 74
8666 12:40:36.963260
8667 12:40:36.963346 Set Vref, RX VrefLevel [Byte0]: 75
8668 12:40:36.966986 [Byte1]: 75
8669 12:40:36.971510
8670 12:40:36.971628 Set Vref, RX VrefLevel [Byte0]: 76
8671 12:40:36.974900 [Byte1]: 76
8672 12:40:36.978703
8673 12:40:36.978825 Set Vref, RX VrefLevel [Byte0]: 77
8674 12:40:36.982134 [Byte1]: 77
8675 12:40:36.986288
8676 12:40:36.986417 Set Vref, RX VrefLevel [Byte0]: 78
8677 12:40:36.989621 [Byte1]: 78
8678 12:40:36.993819
8679 12:40:36.993941 Set Vref, RX VrefLevel [Byte0]: 79
8680 12:40:36.997207 [Byte1]: 79
8681 12:40:37.001043
8682 12:40:37.001156 Final RX Vref Byte 0 = 58 to rank0
8683 12:40:37.004494 Final RX Vref Byte 1 = 55 to rank0
8684 12:40:37.007899 Final RX Vref Byte 0 = 58 to rank1
8685 12:40:37.011288 Final RX Vref Byte 1 = 55 to rank1==
8686 12:40:37.014746 Dram Type= 6, Freq= 0, CH_1, rank 0
8687 12:40:37.021388 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8688 12:40:37.021510 ==
8689 12:40:37.021605 DQS Delay:
8690 12:40:37.021692 DQS0 = 0, DQS1 = 0
8691 12:40:37.024733 DQM Delay:
8692 12:40:37.024846 DQM0 = 134, DQM1 = 131
8693 12:40:37.027948 DQ Delay:
8694 12:40:37.031404 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8695 12:40:37.034903 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =134
8696 12:40:37.038022 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8697 12:40:37.041478 DQ12 =138, DQ13 =138, DQ14 =140, DQ15 =140
8698 12:40:37.041600
8699 12:40:37.041691
8700 12:40:37.041803
8701 12:40:37.044844 [DramC_TX_OE_Calibration] TA2
8702 12:40:37.048227 Original DQ_B0 (3 6) =30, OEN = 27
8703 12:40:37.051517 Original DQ_B1 (3 6) =30, OEN = 27
8704 12:40:37.055079 24, 0x0, End_B0=24 End_B1=24
8705 12:40:37.055166 25, 0x0, End_B0=25 End_B1=25
8706 12:40:37.058354 26, 0x0, End_B0=26 End_B1=26
8707 12:40:37.061834 27, 0x0, End_B0=27 End_B1=27
8708 12:40:37.064393 28, 0x0, End_B0=28 End_B1=28
8709 12:40:37.064471 29, 0x0, End_B0=29 End_B1=29
8710 12:40:37.067949 30, 0x0, End_B0=30 End_B1=30
8711 12:40:37.071294 31, 0x4141, End_B0=30 End_B1=30
8712 12:40:37.074473 Byte0 end_step=30 best_step=27
8713 12:40:37.078097 Byte1 end_step=30 best_step=27
8714 12:40:37.081041 Byte0 TX OE(2T, 0.5T) = (3, 3)
8715 12:40:37.081157 Byte1 TX OE(2T, 0.5T) = (3, 3)
8716 12:40:37.084679
8717 12:40:37.084762
8718 12:40:37.090865 [DQSOSCAuto] RK0, (LSB)MR18= 0x1825, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 397 ps
8719 12:40:37.094742 CH1 RK0: MR19=303, MR18=1825
8720 12:40:37.100836 CH1_RK0: MR19=0x303, MR18=0x1825, DQSOSC=391, MR23=63, INC=24, DEC=16
8721 12:40:37.100943
8722 12:40:37.104644 ----->DramcWriteLeveling(PI) begin...
8723 12:40:37.104730 ==
8724 12:40:37.107872 Dram Type= 6, Freq= 0, CH_1, rank 1
8725 12:40:37.111387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8726 12:40:37.111477 ==
8727 12:40:37.114142 Write leveling (Byte 0): 25 => 25
8728 12:40:37.117418 Write leveling (Byte 1): 28 => 28
8729 12:40:37.121570 DramcWriteLeveling(PI) end<-----
8730 12:40:37.121651
8731 12:40:37.121734 ==
8732 12:40:37.124764 Dram Type= 6, Freq= 0, CH_1, rank 1
8733 12:40:37.128028 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8734 12:40:37.128111 ==
8735 12:40:37.130833 [Gating] SW mode calibration
8736 12:40:37.137586 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8737 12:40:37.144186 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8738 12:40:37.147900 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8739 12:40:37.151041 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8740 12:40:37.157331 1 4 8 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
8741 12:40:37.160777 1 4 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 1)
8742 12:40:37.164123 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8743 12:40:37.170819 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8744 12:40:37.174207 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8745 12:40:37.177618 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8746 12:40:37.184439 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8747 12:40:37.187193 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8748 12:40:37.190554 1 5 8 | B1->B0 | 3030 3434 | 0 1 | (0 1) (1 1)
8749 12:40:37.197154 1 5 12 | B1->B0 | 2828 2f2f | 0 0 | (0 0) (0 1)
8750 12:40:37.200489 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8751 12:40:37.203923 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8752 12:40:37.210273 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8753 12:40:37.214176 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 12:40:37.217150 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 12:40:37.223748 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 12:40:37.227432 1 6 8 | B1->B0 | 3d3d 2626 | 0 0 | (0 0) (1 1)
8757 12:40:37.230766 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8758 12:40:37.237627 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8759 12:40:37.240590 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8760 12:40:37.243730 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8761 12:40:37.247459 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8762 12:40:37.254101 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8763 12:40:37.257472 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8764 12:40:37.260224 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8765 12:40:37.267010 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8766 12:40:37.270340 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8767 12:40:37.273852 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 12:40:37.280667 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 12:40:37.283573 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 12:40:37.287064 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 12:40:37.294017 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 12:40:37.297266 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 12:40:37.300502 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 12:40:37.307251 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 12:40:37.309991 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 12:40:37.313392 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 12:40:37.320278 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 12:40:37.323742 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 12:40:37.326522 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 12:40:37.333811 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8781 12:40:37.336934 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8782 12:40:37.339973 Total UI for P1: 0, mck2ui 16
8783 12:40:37.343341 best dqsien dly found for B1: ( 1, 9, 8)
8784 12:40:37.347002 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 12:40:37.349910 Total UI for P1: 0, mck2ui 16
8786 12:40:37.353466 best dqsien dly found for B0: ( 1, 9, 12)
8787 12:40:37.356844 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8788 12:40:37.360109 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8789 12:40:37.360198
8790 12:40:37.366348 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8791 12:40:37.369895 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8792 12:40:37.369980 [Gating] SW calibration Done
8793 12:40:37.372932 ==
8794 12:40:37.376546 Dram Type= 6, Freq= 0, CH_1, rank 1
8795 12:40:37.379666 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8796 12:40:37.379749 ==
8797 12:40:37.379834 RX Vref Scan: 0
8798 12:40:37.379916
8799 12:40:37.383252 RX Vref 0 -> 0, step: 1
8800 12:40:37.383332
8801 12:40:37.386558 RX Delay 0 -> 252, step: 8
8802 12:40:37.390034 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8803 12:40:37.393434 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8804 12:40:37.396165 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8805 12:40:37.402823 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8806 12:40:37.406744 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8807 12:40:37.410006 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8808 12:40:37.413376 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8809 12:40:37.416053 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8810 12:40:37.423313 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8811 12:40:37.426101 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8812 12:40:37.429514 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8813 12:40:37.432878 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8814 12:40:37.436295 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8815 12:40:37.442773 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8816 12:40:37.446214 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8817 12:40:37.449688 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8818 12:40:37.449772 ==
8819 12:40:37.452953 Dram Type= 6, Freq= 0, CH_1, rank 1
8820 12:40:37.456235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8821 12:40:37.456342 ==
8822 12:40:37.459661 DQS Delay:
8823 12:40:37.459769 DQS0 = 0, DQS1 = 0
8824 12:40:37.463090 DQM Delay:
8825 12:40:37.463205 DQM0 = 136, DQM1 = 133
8826 12:40:37.466558 DQ Delay:
8827 12:40:37.469366 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8828 12:40:37.472787 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8829 12:40:37.476087 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8830 12:40:37.479949 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8831 12:40:37.480030
8832 12:40:37.480114
8833 12:40:37.480218 ==
8834 12:40:37.483092 Dram Type= 6, Freq= 0, CH_1, rank 1
8835 12:40:37.486566 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8836 12:40:37.486648 ==
8837 12:40:37.486730
8838 12:40:37.486809
8839 12:40:37.489552 TX Vref Scan disable
8840 12:40:37.492781 == TX Byte 0 ==
8841 12:40:37.496069 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8842 12:40:37.499787 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8843 12:40:37.503001 == TX Byte 1 ==
8844 12:40:37.506200 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8845 12:40:37.509769 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8846 12:40:37.509859 ==
8847 12:40:37.512803 Dram Type= 6, Freq= 0, CH_1, rank 1
8848 12:40:37.519046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8849 12:40:37.519145 ==
8850 12:40:37.530553
8851 12:40:37.534049 TX Vref early break, caculate TX vref
8852 12:40:37.537497 TX Vref=16, minBit 0, minWin=23, winSum=383
8853 12:40:37.540238 TX Vref=18, minBit 0, minWin=23, winSum=392
8854 12:40:37.543847 TX Vref=20, minBit 0, minWin=24, winSum=403
8855 12:40:37.547012 TX Vref=22, minBit 0, minWin=25, winSum=413
8856 12:40:37.550431 TX Vref=24, minBit 0, minWin=25, winSum=421
8857 12:40:37.557292 TX Vref=26, minBit 0, minWin=25, winSum=423
8858 12:40:37.560525 TX Vref=28, minBit 1, minWin=25, winSum=430
8859 12:40:37.563887 TX Vref=30, minBit 0, minWin=25, winSum=419
8860 12:40:37.567369 TX Vref=32, minBit 0, minWin=25, winSum=414
8861 12:40:37.570833 TX Vref=34, minBit 0, minWin=24, winSum=403
8862 12:40:37.577252 [TxChooseVref] Worse bit 1, Min win 25, Win sum 430, Final Vref 28
8863 12:40:37.577379
8864 12:40:37.580884 Final TX Range 0 Vref 28
8865 12:40:37.580982
8866 12:40:37.581051 ==
8867 12:40:37.583709 Dram Type= 6, Freq= 0, CH_1, rank 1
8868 12:40:37.586920 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8869 12:40:37.587041 ==
8870 12:40:37.587137
8871 12:40:37.587236
8872 12:40:37.590219 TX Vref Scan disable
8873 12:40:37.597112 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8874 12:40:37.597240 == TX Byte 0 ==
8875 12:40:37.600597 u2DelayCellOfst[0]=16 cells (5 PI)
8876 12:40:37.603963 u2DelayCellOfst[1]=13 cells (4 PI)
8877 12:40:37.607198 u2DelayCellOfst[2]=0 cells (0 PI)
8878 12:40:37.610612 u2DelayCellOfst[3]=6 cells (2 PI)
8879 12:40:37.613426 u2DelayCellOfst[4]=10 cells (3 PI)
8880 12:40:37.616629 u2DelayCellOfst[5]=16 cells (5 PI)
8881 12:40:37.620559 u2DelayCellOfst[6]=16 cells (5 PI)
8882 12:40:37.620647 u2DelayCellOfst[7]=6 cells (2 PI)
8883 12:40:37.626722 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8884 12:40:37.630283 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8885 12:40:37.633698 == TX Byte 1 ==
8886 12:40:37.633784 u2DelayCellOfst[8]=0 cells (0 PI)
8887 12:40:37.637093 u2DelayCellOfst[9]=3 cells (1 PI)
8888 12:40:37.639982 u2DelayCellOfst[10]=10 cells (3 PI)
8889 12:40:37.643300 u2DelayCellOfst[11]=3 cells (1 PI)
8890 12:40:37.646947 u2DelayCellOfst[12]=13 cells (4 PI)
8891 12:40:37.650126 u2DelayCellOfst[13]=13 cells (4 PI)
8892 12:40:37.653272 u2DelayCellOfst[14]=16 cells (5 PI)
8893 12:40:37.656559 u2DelayCellOfst[15]=16 cells (5 PI)
8894 12:40:37.660034 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8895 12:40:37.666806 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8896 12:40:37.666922 DramC Write-DBI on
8897 12:40:37.667017 ==
8898 12:40:37.670281 Dram Type= 6, Freq= 0, CH_1, rank 1
8899 12:40:37.673736 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8900 12:40:37.676544 ==
8901 12:40:37.676619
8902 12:40:37.676682
8903 12:40:37.676741 TX Vref Scan disable
8904 12:40:37.680045 == TX Byte 0 ==
8905 12:40:37.683784 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8906 12:40:37.686946 == TX Byte 1 ==
8907 12:40:37.689789 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8908 12:40:37.693133 DramC Write-DBI off
8909 12:40:37.693233
8910 12:40:37.693324 [DATLAT]
8911 12:40:37.693410 Freq=1600, CH1 RK1
8912 12:40:37.693496
8913 12:40:37.696439 DATLAT Default: 0xf
8914 12:40:37.696511 0, 0xFFFF, sum = 0
8915 12:40:37.699884 1, 0xFFFF, sum = 0
8916 12:40:37.699990 2, 0xFFFF, sum = 0
8917 12:40:37.703336 3, 0xFFFF, sum = 0
8918 12:40:37.706837 4, 0xFFFF, sum = 0
8919 12:40:37.706941 5, 0xFFFF, sum = 0
8920 12:40:37.710325 6, 0xFFFF, sum = 0
8921 12:40:37.710433 7, 0xFFFF, sum = 0
8922 12:40:37.713825 8, 0xFFFF, sum = 0
8923 12:40:37.713902 9, 0xFFFF, sum = 0
8924 12:40:37.716439 10, 0xFFFF, sum = 0
8925 12:40:37.716511 11, 0xFFFF, sum = 0
8926 12:40:37.719797 12, 0xFFFF, sum = 0
8927 12:40:37.719872 13, 0xFFFF, sum = 0
8928 12:40:37.723359 14, 0x0, sum = 1
8929 12:40:37.723435 15, 0x0, sum = 2
8930 12:40:37.726874 16, 0x0, sum = 3
8931 12:40:37.726976 17, 0x0, sum = 4
8932 12:40:37.730274 best_step = 15
8933 12:40:37.730351
8934 12:40:37.730413 ==
8935 12:40:37.733028 Dram Type= 6, Freq= 0, CH_1, rank 1
8936 12:40:37.736620 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8937 12:40:37.736700 ==
8938 12:40:37.736784 RX Vref Scan: 0
8939 12:40:37.736848
8940 12:40:37.740123 RX Vref 0 -> 0, step: 1
8941 12:40:37.740221
8942 12:40:37.743413 RX Delay 19 -> 252, step: 4
8943 12:40:37.746626 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8944 12:40:37.749960 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8945 12:40:37.756486 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8946 12:40:37.760138 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8947 12:40:37.763046 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8948 12:40:37.766424 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8949 12:40:37.770038 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8950 12:40:37.776590 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8951 12:40:37.780170 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8952 12:40:37.783006 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8953 12:40:37.786554 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8954 12:40:37.789930 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8955 12:40:37.796833 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8956 12:40:37.799532 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8957 12:40:37.803590 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8958 12:40:37.806313 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8959 12:40:37.806423 ==
8960 12:40:37.809742 Dram Type= 6, Freq= 0, CH_1, rank 1
8961 12:40:37.816834 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8962 12:40:37.816929 ==
8963 12:40:37.817005 DQS Delay:
8964 12:40:37.820124 DQS0 = 0, DQS1 = 0
8965 12:40:37.820232 DQM Delay:
8966 12:40:37.820328 DQM0 = 134, DQM1 = 130
8967 12:40:37.822896 DQ Delay:
8968 12:40:37.826295 DQ0 =138, DQ1 =132, DQ2 =122, DQ3 =130
8969 12:40:37.829674 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8970 12:40:37.833211 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
8971 12:40:37.836600 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =138
8972 12:40:37.836683
8973 12:40:37.836748
8974 12:40:37.836809
8975 12:40:37.840044 [DramC_TX_OE_Calibration] TA2
8976 12:40:37.842856 Original DQ_B0 (3 6) =30, OEN = 27
8977 12:40:37.846303 Original DQ_B1 (3 6) =30, OEN = 27
8978 12:40:37.849754 24, 0x0, End_B0=24 End_B1=24
8979 12:40:37.849836 25, 0x0, End_B0=25 End_B1=25
8980 12:40:37.853207 26, 0x0, End_B0=26 End_B1=26
8981 12:40:37.856421 27, 0x0, End_B0=27 End_B1=27
8982 12:40:37.859617 28, 0x0, End_B0=28 End_B1=28
8983 12:40:37.859750 29, 0x0, End_B0=29 End_B1=29
8984 12:40:37.863112 30, 0x0, End_B0=30 End_B1=30
8985 12:40:37.866645 31, 0x4141, End_B0=30 End_B1=30
8986 12:40:37.869941 Byte0 end_step=30 best_step=27
8987 12:40:37.873317 Byte1 end_step=30 best_step=27
8988 12:40:37.876044 Byte0 TX OE(2T, 0.5T) = (3, 3)
8989 12:40:37.879598 Byte1 TX OE(2T, 0.5T) = (3, 3)
8990 12:40:37.879684
8991 12:40:37.879787
8992 12:40:37.886389 [DQSOSCAuto] RK1, (LSB)MR18= 0x2207, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
8993 12:40:37.889836 CH1 RK1: MR19=303, MR18=2207
8994 12:40:37.896526 CH1_RK1: MR19=0x303, MR18=0x2207, DQSOSC=392, MR23=63, INC=24, DEC=16
8995 12:40:37.899966 [RxdqsGatingPostProcess] freq 1600
8996 12:40:37.902922 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8997 12:40:37.906263 best DQS0 dly(2T, 0.5T) = (1, 1)
8998 12:40:37.909765 best DQS1 dly(2T, 0.5T) = (1, 1)
8999 12:40:37.913177 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9000 12:40:37.916256 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9001 12:40:37.919479 best DQS0 dly(2T, 0.5T) = (1, 1)
9002 12:40:37.922846 best DQS1 dly(2T, 0.5T) = (1, 1)
9003 12:40:37.926291 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9004 12:40:37.929669 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9005 12:40:37.933141 Pre-setting of DQS Precalculation
9006 12:40:37.935962 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9007 12:40:37.942913 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9008 12:40:37.949210 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9009 12:40:37.949402
9010 12:40:37.952646
9011 12:40:37.952751 [Calibration Summary] 3200 Mbps
9012 12:40:37.956045 CH 0, Rank 0
9013 12:40:37.956159 SW Impedance : PASS
9014 12:40:37.959493 DUTY Scan : NO K
9015 12:40:37.962975 ZQ Calibration : PASS
9016 12:40:37.963081 Jitter Meter : NO K
9017 12:40:37.966278 CBT Training : PASS
9018 12:40:37.969592 Write leveling : PASS
9019 12:40:37.969701 RX DQS gating : PASS
9020 12:40:37.972812 RX DQ/DQS(RDDQC) : PASS
9021 12:40:37.976165 TX DQ/DQS : PASS
9022 12:40:37.976282 RX DATLAT : PASS
9023 12:40:37.979453 RX DQ/DQS(Engine): PASS
9024 12:40:37.982587 TX OE : PASS
9025 12:40:37.982696 All Pass.
9026 12:40:37.982790
9027 12:40:37.982882 CH 0, Rank 1
9028 12:40:37.986171 SW Impedance : PASS
9029 12:40:37.989547 DUTY Scan : NO K
9030 12:40:37.989656 ZQ Calibration : PASS
9031 12:40:37.993054 Jitter Meter : NO K
9032 12:40:37.993130 CBT Training : PASS
9033 12:40:37.995892 Write leveling : PASS
9034 12:40:37.999282 RX DQS gating : PASS
9035 12:40:37.999391 RX DQ/DQS(RDDQC) : PASS
9036 12:40:38.002638 TX DQ/DQS : PASS
9037 12:40:38.006010 RX DATLAT : PASS
9038 12:40:38.006113 RX DQ/DQS(Engine): PASS
9039 12:40:38.009449 TX OE : PASS
9040 12:40:38.009551 All Pass.
9041 12:40:38.009645
9042 12:40:38.013144 CH 1, Rank 0
9043 12:40:38.013247 SW Impedance : PASS
9044 12:40:38.016291 DUTY Scan : NO K
9045 12:40:38.019405 ZQ Calibration : PASS
9046 12:40:38.019481 Jitter Meter : NO K
9047 12:40:38.022268 CBT Training : PASS
9048 12:40:38.026179 Write leveling : PASS
9049 12:40:38.026261 RX DQS gating : PASS
9050 12:40:38.029091 RX DQ/DQS(RDDQC) : PASS
9051 12:40:38.032471 TX DQ/DQS : PASS
9052 12:40:38.032552 RX DATLAT : PASS
9053 12:40:38.035885 RX DQ/DQS(Engine): PASS
9054 12:40:38.035958 TX OE : PASS
9055 12:40:38.039518 All Pass.
9056 12:40:38.039591
9057 12:40:38.039656 CH 1, Rank 1
9058 12:40:38.042371 SW Impedance : PASS
9059 12:40:38.042495 DUTY Scan : NO K
9060 12:40:38.045772 ZQ Calibration : PASS
9061 12:40:38.048798 Jitter Meter : NO K
9062 12:40:38.048887 CBT Training : PASS
9063 12:40:38.052167 Write leveling : PASS
9064 12:40:38.055725 RX DQS gating : PASS
9065 12:40:38.055812 RX DQ/DQS(RDDQC) : PASS
9066 12:40:38.059045 TX DQ/DQS : PASS
9067 12:40:38.062592 RX DATLAT : PASS
9068 12:40:38.062679 RX DQ/DQS(Engine): PASS
9069 12:40:38.065980 TX OE : PASS
9070 12:40:38.066062 All Pass.
9071 12:40:38.066126
9072 12:40:38.069522 DramC Write-DBI on
9073 12:40:38.072238 PER_BANK_REFRESH: Hybrid Mode
9074 12:40:38.072339 TX_TRACKING: ON
9075 12:40:38.082841 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9076 12:40:38.088845 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9077 12:40:38.095393 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9078 12:40:38.098739 [FAST_K] Save calibration result to emmc
9079 12:40:38.102185 sync common calibartion params.
9080 12:40:38.105828 sync cbt_mode0:1, 1:1
9081 12:40:38.109115 dram_init: ddr_geometry: 2
9082 12:40:38.109205 dram_init: ddr_geometry: 2
9083 12:40:38.112406 dram_init: ddr_geometry: 2
9084 12:40:38.115838 0:dram_rank_size:100000000
9085 12:40:38.115932 1:dram_rank_size:100000000
9086 12:40:38.122097 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9087 12:40:38.125531 DFS_SHUFFLE_HW_MODE: ON
9088 12:40:38.129018 dramc_set_vcore_voltage set vcore to 725000
9089 12:40:38.132448 Read voltage for 1600, 0
9090 12:40:38.132574 Vio18 = 0
9091 12:40:38.132666 Vcore = 725000
9092 12:40:38.135864 Vdram = 0
9093 12:40:38.135979 Vddq = 0
9094 12:40:38.136082 Vmddr = 0
9095 12:40:38.139301 switch to 3200 Mbps bootup
9096 12:40:38.139412 [DramcRunTimeConfig]
9097 12:40:38.142675 PHYPLL
9098 12:40:38.142791 DPM_CONTROL_AFTERK: ON
9099 12:40:38.146094 PER_BANK_REFRESH: ON
9100 12:40:38.149190 REFRESH_OVERHEAD_REDUCTION: ON
9101 12:40:38.149273 CMD_PICG_NEW_MODE: OFF
9102 12:40:38.152520 XRTWTW_NEW_MODE: ON
9103 12:40:38.152622 XRTRTR_NEW_MODE: ON
9104 12:40:38.155626 TX_TRACKING: ON
9105 12:40:38.155710 RDSEL_TRACKING: OFF
9106 12:40:38.159212 DQS Precalculation for DVFS: ON
9107 12:40:38.162564 RX_TRACKING: OFF
9108 12:40:38.162667 HW_GATING DBG: ON
9109 12:40:38.165782 ZQCS_ENABLE_LP4: ON
9110 12:40:38.165861 RX_PICG_NEW_MODE: ON
9111 12:40:38.168750 TX_PICG_NEW_MODE: ON
9112 12:40:38.168838 ENABLE_RX_DCM_DPHY: ON
9113 12:40:38.172574 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9114 12:40:38.175355 DUMMY_READ_FOR_TRACKING: OFF
9115 12:40:38.178830 !!! SPM_CONTROL_AFTERK: OFF
9116 12:40:38.182294 !!! SPM could not control APHY
9117 12:40:38.182404 IMPEDANCE_TRACKING: ON
9118 12:40:38.185840 TEMP_SENSOR: ON
9119 12:40:38.185955 HW_SAVE_FOR_SR: OFF
9120 12:40:38.189323 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9121 12:40:38.192100 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9122 12:40:38.195487 Read ODT Tracking: ON
9123 12:40:38.199355 Refresh Rate DeBounce: ON
9124 12:40:38.199469 DFS_NO_QUEUE_FLUSH: ON
9125 12:40:38.202418 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9126 12:40:38.205528 ENABLE_DFS_RUNTIME_MRW: OFF
9127 12:40:38.209276 DDR_RESERVE_NEW_MODE: ON
9128 12:40:38.209374 MR_CBT_SWITCH_FREQ: ON
9129 12:40:38.212084 =========================
9130 12:40:38.231009 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9131 12:40:38.234269 dram_init: ddr_geometry: 2
9132 12:40:38.252620 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9133 12:40:38.256071 dram_init: dram init end (result: 0)
9134 12:40:38.262341 DRAM-K: Full calibration passed in 24445 msecs
9135 12:40:38.265915 MRC: failed to locate region type 0.
9136 12:40:38.265996 DRAM rank0 size:0x100000000,
9137 12:40:38.269297 DRAM rank1 size=0x100000000
9138 12:40:38.279113 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9139 12:40:38.285742 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9140 12:40:38.292090 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9141 12:40:38.299041 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9142 12:40:38.302540 DRAM rank0 size:0x100000000,
9143 12:40:38.305293 DRAM rank1 size=0x100000000
9144 12:40:38.305384 CBMEM:
9145 12:40:38.308772 IMD: root @ 0xfffff000 254 entries.
9146 12:40:38.312257 IMD: root @ 0xffffec00 62 entries.
9147 12:40:38.315290 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9148 12:40:38.322211 WARNING: RO_VPD is uninitialized or empty.
9149 12:40:38.325140 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9150 12:40:38.332796 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9151 12:40:38.345165 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9152 12:40:38.356685 BS: romstage times (exec / console): total (unknown) / 23982 ms
9153 12:40:38.356809
9154 12:40:38.356875
9155 12:40:38.367089 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9156 12:40:38.369969 ARM64: Exception handlers installed.
9157 12:40:38.373513 ARM64: Testing exception
9158 12:40:38.376927 ARM64: Done test exception
9159 12:40:38.377018 Enumerating buses...
9160 12:40:38.379731 Show all devs... Before device enumeration.
9161 12:40:38.383091 Root Device: enabled 1
9162 12:40:38.386512 CPU_CLUSTER: 0: enabled 1
9163 12:40:38.386605 CPU: 00: enabled 1
9164 12:40:38.389860 Compare with tree...
9165 12:40:38.389937 Root Device: enabled 1
9166 12:40:38.393085 CPU_CLUSTER: 0: enabled 1
9167 12:40:38.396338 CPU: 00: enabled 1
9168 12:40:38.396419 Root Device scanning...
9169 12:40:38.399532 scan_static_bus for Root Device
9170 12:40:38.403231 CPU_CLUSTER: 0 enabled
9171 12:40:38.406701 scan_static_bus for Root Device done
9172 12:40:38.410157 scan_bus: bus Root Device finished in 8 msecs
9173 12:40:38.410235 done
9174 12:40:38.416252 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9175 12:40:38.419752 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9176 12:40:38.426519 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9177 12:40:38.429918 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9178 12:40:38.433165 Allocating resources...
9179 12:40:38.436340 Reading resources...
9180 12:40:38.439548 Root Device read_resources bus 0 link: 0
9181 12:40:38.439630 DRAM rank0 size:0x100000000,
9182 12:40:38.443342 DRAM rank1 size=0x100000000
9183 12:40:38.446587 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9184 12:40:38.449721 CPU: 00 missing read_resources
9185 12:40:38.456522 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9186 12:40:38.459701 Root Device read_resources bus 0 link: 0 done
9187 12:40:38.459791 Done reading resources.
9188 12:40:38.465979 Show resources in subtree (Root Device)...After reading.
9189 12:40:38.469865 Root Device child on link 0 CPU_CLUSTER: 0
9190 12:40:38.472782 CPU_CLUSTER: 0 child on link 0 CPU: 00
9191 12:40:38.482706 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9192 12:40:38.482807 CPU: 00
9193 12:40:38.486167 Root Device assign_resources, bus 0 link: 0
9194 12:40:38.489711 CPU_CLUSTER: 0 missing set_resources
9195 12:40:38.495876 Root Device assign_resources, bus 0 link: 0 done
9196 12:40:38.495957 Done setting resources.
9197 12:40:38.502858 Show resources in subtree (Root Device)...After assigning values.
9198 12:40:38.506324 Root Device child on link 0 CPU_CLUSTER: 0
9199 12:40:38.509427 CPU_CLUSTER: 0 child on link 0 CPU: 00
9200 12:40:38.519391 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9201 12:40:38.519519 CPU: 00
9202 12:40:38.522771 Done allocating resources.
9203 12:40:38.525574 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9204 12:40:38.529033 Enabling resources...
9205 12:40:38.529107 done.
9206 12:40:38.536146 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9207 12:40:38.536248 Initializing devices...
9208 12:40:38.539312 Root Device init
9209 12:40:38.539405 init hardware done!
9210 12:40:38.542800 0x00000018: ctrlr->caps
9211 12:40:38.545473 52.000 MHz: ctrlr->f_max
9212 12:40:38.545589 0.400 MHz: ctrlr->f_min
9213 12:40:38.549414 0x40ff8080: ctrlr->voltages
9214 12:40:38.552135 sclk: 390625
9215 12:40:38.552237 Bus Width = 1
9216 12:40:38.552335 sclk: 390625
9217 12:40:38.555768 Bus Width = 1
9218 12:40:38.555873 Early init status = 3
9219 12:40:38.562486 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9220 12:40:38.565651 in-header: 03 fc 00 00 01 00 00 00
9221 12:40:38.565726 in-data: 00
9222 12:40:38.571985 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9223 12:40:38.576163 in-header: 03 fd 00 00 00 00 00 00
9224 12:40:38.579162 in-data:
9225 12:40:38.582907 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9226 12:40:38.586819 in-header: 03 fc 00 00 01 00 00 00
9227 12:40:38.590185 in-data: 00
9228 12:40:38.593522 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9229 12:40:38.599049 in-header: 03 fd 00 00 00 00 00 00
9230 12:40:38.601825 in-data:
9231 12:40:38.605253 [SSUSB] Setting up USB HOST controller...
9232 12:40:38.608580 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9233 12:40:38.611963 [SSUSB] phy power-on done.
9234 12:40:38.615420 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9235 12:40:38.622419 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9236 12:40:38.625389 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9237 12:40:38.632277 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9238 12:40:38.639295 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9239 12:40:38.645327 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9240 12:40:38.652307 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9241 12:40:38.658895 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9242 12:40:38.658995 SPM: binary array size = 0x9dc
9243 12:40:38.665889 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9244 12:40:38.672001 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9245 12:40:38.678881 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9246 12:40:38.682252 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9247 12:40:38.685664 configure_display: Starting display init
9248 12:40:38.722155 anx7625_power_on_init: Init interface.
9249 12:40:38.725726 anx7625_disable_pd_protocol: Disabled PD feature.
9250 12:40:38.728459 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9251 12:40:38.756235 anx7625_start_dp_work: Secure OCM version=00
9252 12:40:38.759534 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9253 12:40:38.774392 sp_tx_get_edid_block: EDID Block = 1
9254 12:40:38.877204 Extracted contents:
9255 12:40:38.880570 header: 00 ff ff ff ff ff ff 00
9256 12:40:38.884128 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9257 12:40:38.886909 version: 01 04
9258 12:40:38.890591 basic params: 95 1f 11 78 0a
9259 12:40:38.893977 chroma info: 76 90 94 55 54 90 27 21 50 54
9260 12:40:38.897257 established: 00 00 00
9261 12:40:38.903262 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9262 12:40:38.906630 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9263 12:40:38.913236 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9264 12:40:38.919991 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9265 12:40:38.926921 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9266 12:40:38.930186 extensions: 00
9267 12:40:38.930301 checksum: fb
9268 12:40:38.930385
9269 12:40:38.933382 Manufacturer: IVO Model 57d Serial Number 0
9270 12:40:38.936410 Made week 0 of 2020
9271 12:40:38.940112 EDID version: 1.4
9272 12:40:38.940218 Digital display
9273 12:40:38.943304 6 bits per primary color channel
9274 12:40:38.943389 DisplayPort interface
9275 12:40:38.946818 Maximum image size: 31 cm x 17 cm
9276 12:40:38.949690 Gamma: 220%
9277 12:40:38.949774 Check DPMS levels
9278 12:40:38.953227 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9279 12:40:38.959461 First detailed timing is preferred timing
9280 12:40:38.959544 Established timings supported:
9281 12:40:38.962836 Standard timings supported:
9282 12:40:38.966135 Detailed timings
9283 12:40:38.969454 Hex of detail: 383680a07038204018303c0035ae10000019
9284 12:40:38.973060 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9285 12:40:38.979918 0780 0798 07c8 0820 hborder 0
9286 12:40:38.982945 0438 043b 0447 0458 vborder 0
9287 12:40:38.986157 -hsync -vsync
9288 12:40:38.986232 Did detailed timing
9289 12:40:38.992849 Hex of detail: 000000000000000000000000000000000000
9290 12:40:38.992930 Manufacturer-specified data, tag 0
9291 12:40:38.999832 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9292 12:40:39.003252 ASCII string: InfoVision
9293 12:40:39.006657 Hex of detail: 000000fe00523134304e574635205248200a
9294 12:40:39.009874 ASCII string: R140NWF5 RH
9295 12:40:39.009953 Checksum
9296 12:40:39.013269 Checksum: 0xfb (valid)
9297 12:40:39.016676 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9298 12:40:39.019956 DSI data_rate: 832800000 bps
9299 12:40:39.026120 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9300 12:40:39.029555 anx7625_parse_edid: pixelclock(138800).
9301 12:40:39.033166 hactive(1920), hsync(48), hfp(24), hbp(88)
9302 12:40:39.036514 vactive(1080), vsync(12), vfp(3), vbp(17)
9303 12:40:39.039376 anx7625_dsi_config: config dsi.
9304 12:40:39.045952 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9305 12:40:39.059185 anx7625_dsi_config: success to config DSI
9306 12:40:39.062773 anx7625_dp_start: MIPI phy setup OK.
9307 12:40:39.065507 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9308 12:40:39.068928 mtk_ddp_mode_set invalid vrefresh 60
9309 12:40:39.072557 main_disp_path_setup
9310 12:40:39.072662 ovl_layer_smi_id_en
9311 12:40:39.075989 ovl_layer_smi_id_en
9312 12:40:39.076078 ccorr_config
9313 12:40:39.076142 aal_config
9314 12:40:39.079331 gamma_config
9315 12:40:39.079429 postmask_config
9316 12:40:39.082542 dither_config
9317 12:40:39.085759 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9318 12:40:39.092362 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9319 12:40:39.095863 Root Device init finished in 553 msecs
9320 12:40:39.095961 CPU_CLUSTER: 0 init
9321 12:40:39.105715 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9322 12:40:39.109396 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9323 12:40:39.112785 APU_MBOX 0x190000b0 = 0x10001
9324 12:40:39.116034 APU_MBOX 0x190001b0 = 0x10001
9325 12:40:39.119427 APU_MBOX 0x190005b0 = 0x10001
9326 12:40:39.122221 APU_MBOX 0x190006b0 = 0x10001
9327 12:40:39.125481 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9328 12:40:39.138423 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9329 12:40:39.150706 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9330 12:40:39.156951 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9331 12:40:39.169103 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9332 12:40:39.177838 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9333 12:40:39.181417 CPU_CLUSTER: 0 init finished in 81 msecs
9334 12:40:39.184836 Devices initialized
9335 12:40:39.188095 Show all devs... After init.
9336 12:40:39.188200 Root Device: enabled 1
9337 12:40:39.191421 CPU_CLUSTER: 0: enabled 1
9338 12:40:39.194702 CPU: 00: enabled 1
9339 12:40:39.197843 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9340 12:40:39.201278 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9341 12:40:39.204843 ELOG: NV offset 0x57f000 size 0x1000
9342 12:40:39.211058 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9343 12:40:39.218074 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9344 12:40:39.221456 ELOG: Event(17) added with size 13 at 2024-02-05 12:37:59 UTC
9345 12:40:39.224747 out: cmd=0x121: 03 db 21 01 00 00 00 00
9346 12:40:39.228004 in-header: 03 ea 00 00 2c 00 00 00
9347 12:40:39.241825 in-data: 75 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9348 12:40:39.248083 ELOG: Event(A1) added with size 10 at 2024-02-05 12:37:59 UTC
9349 12:40:39.254419 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9350 12:40:39.261387 ELOG: Event(A0) added with size 9 at 2024-02-05 12:37:59 UTC
9351 12:40:39.264905 elog_add_boot_reason: Logged dev mode boot
9352 12:40:39.268497 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9353 12:40:39.271201 Finalize devices...
9354 12:40:39.271291 Devices finalized
9355 12:40:39.278470 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9356 12:40:39.281695 Writing coreboot table at 0xffe64000
9357 12:40:39.284908 0. 000000000010a000-0000000000113fff: RAMSTAGE
9358 12:40:39.288040 1. 0000000040000000-00000000400fffff: RAM
9359 12:40:39.291393 2. 0000000040100000-000000004032afff: RAMSTAGE
9360 12:40:39.297789 3. 000000004032b000-00000000545fffff: RAM
9361 12:40:39.301667 4. 0000000054600000-000000005465ffff: BL31
9362 12:40:39.304902 5. 0000000054660000-00000000ffe63fff: RAM
9363 12:40:39.308008 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9364 12:40:39.315023 7. 0000000100000000-000000023fffffff: RAM
9365 12:40:39.315133 Passing 5 GPIOs to payload:
9366 12:40:39.321329 NAME | PORT | POLARITY | VALUE
9367 12:40:39.324595 EC in RW | 0x000000aa | low | undefined
9368 12:40:39.331555 EC interrupt | 0x00000005 | low | undefined
9369 12:40:39.334779 TPM interrupt | 0x000000ab | high | undefined
9370 12:40:39.338010 SD card detect | 0x00000011 | high | undefined
9371 12:40:39.344545 speaker enable | 0x00000093 | high | undefined
9372 12:40:39.347797 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9373 12:40:39.351096 in-header: 03 f9 00 00 02 00 00 00
9374 12:40:39.351205 in-data: 02 00
9375 12:40:39.354520 ADC[4]: Raw value=904726 ID=7
9376 12:40:39.358003 ADC[3]: Raw value=213072 ID=1
9377 12:40:39.358076 RAM Code: 0x71
9378 12:40:39.361434 ADC[6]: Raw value=75332 ID=0
9379 12:40:39.364210 ADC[5]: Raw value=213072 ID=1
9380 12:40:39.364317 SKU Code: 0x1
9381 12:40:39.371218 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 6c95
9382 12:40:39.374630 coreboot table: 964 bytes.
9383 12:40:39.378120 IMD ROOT 0. 0xfffff000 0x00001000
9384 12:40:39.380868 IMD SMALL 1. 0xffffe000 0x00001000
9385 12:40:39.384243 RO MCACHE 2. 0xffffc000 0x00001104
9386 12:40:39.387563 CONSOLE 3. 0xfff7c000 0x00080000
9387 12:40:39.390964 FMAP 4. 0xfff7b000 0x00000452
9388 12:40:39.394246 TIME STAMP 5. 0xfff7a000 0x00000910
9389 12:40:39.397446 VBOOT WORK 6. 0xfff66000 0x00014000
9390 12:40:39.400812 RAMOOPS 7. 0xffe66000 0x00100000
9391 12:40:39.404595 COREBOOT 8. 0xffe64000 0x00002000
9392 12:40:39.404697 IMD small region:
9393 12:40:39.407694 IMD ROOT 0. 0xffffec00 0x00000400
9394 12:40:39.411080 VPD 1. 0xffffeb80 0x0000006c
9395 12:40:39.414507 MMC STATUS 2. 0xffffeb60 0x00000004
9396 12:40:39.420561 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9397 12:40:39.424737 Probing TPM: done!
9398 12:40:39.427991 Connected to device vid:did:rid of 1ae0:0028:00
9399 12:40:39.437971 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9400 12:40:39.441306 Initialized TPM device CR50 revision 0
9401 12:40:39.444509 Checking cr50 for pending updates
9402 12:40:39.447928 Reading cr50 TPM mode
9403 12:40:39.456670 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9404 12:40:39.463507 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9405 12:40:39.503004 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9406 12:40:39.506441 Checking segment from ROM address 0x40100000
9407 12:40:39.510064 Checking segment from ROM address 0x4010001c
9408 12:40:39.516573 Loading segment from ROM address 0x40100000
9409 12:40:39.516687 code (compression=0)
9410 12:40:39.523384 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9411 12:40:39.533351 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9412 12:40:39.533432 it's not compressed!
9413 12:40:39.540183 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9414 12:40:39.543283 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9415 12:40:39.563756 Loading segment from ROM address 0x4010001c
9416 12:40:39.563847 Entry Point 0x80000000
9417 12:40:39.567009 Loaded segments
9418 12:40:39.574216 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9419 12:40:39.577277 Jumping to boot code at 0x80000000(0xffe64000)
9420 12:40:39.583619 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9421 12:40:39.590659 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9422 12:40:39.597801 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9423 12:40:39.601313 Checking segment from ROM address 0x40100000
9424 12:40:39.604652 Checking segment from ROM address 0x4010001c
9425 12:40:39.611466 Loading segment from ROM address 0x40100000
9426 12:40:39.611551 code (compression=1)
9427 12:40:39.617855 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9428 12:40:39.627695 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9429 12:40:39.627777 using LZMA
9430 12:40:39.636626 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9431 12:40:39.643276 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9432 12:40:39.646584 Loading segment from ROM address 0x4010001c
9433 12:40:39.646726 Entry Point 0x54601000
9434 12:40:39.649851 Loaded segments
9435 12:40:39.653141 NOTICE: MT8192 bl31_setup
9436 12:40:39.660232 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9437 12:40:39.663163 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9438 12:40:39.666512 WARNING: region 0:
9439 12:40:39.670133 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9440 12:40:39.670227 WARNING: region 1:
9441 12:40:39.676736 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9442 12:40:39.680049 WARNING: region 2:
9443 12:40:39.683243 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9444 12:40:39.686647 WARNING: region 3:
9445 12:40:39.690195 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9446 12:40:39.693577 WARNING: region 4:
9447 12:40:39.697186 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9448 12:40:39.700038 WARNING: region 5:
9449 12:40:39.703498 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9450 12:40:39.707142 WARNING: region 6:
9451 12:40:39.710765 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9452 12:40:39.710841 WARNING: region 7:
9453 12:40:39.717004 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9454 12:40:39.723310 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9455 12:40:39.726902 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9456 12:40:39.730357 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9457 12:40:39.736913 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9458 12:40:39.740115 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9459 12:40:39.743896 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9460 12:40:39.750264 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9461 12:40:39.753787 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9462 12:40:39.757325 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9463 12:40:39.763617 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9464 12:40:39.767218 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9465 12:40:39.770439 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9466 12:40:39.777078 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9467 12:40:39.780753 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9468 12:40:39.787233 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9469 12:40:39.790701 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9470 12:40:39.793687 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9471 12:40:39.800409 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9472 12:40:39.803760 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9473 12:40:39.806994 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9474 12:40:39.813906 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9475 12:40:39.817284 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9476 12:40:39.824091 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9477 12:40:39.827501 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9478 12:40:39.830958 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9479 12:40:39.837318 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9480 12:40:39.840896 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9481 12:40:39.847560 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9482 12:40:39.850854 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9483 12:40:39.853917 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9484 12:40:39.861352 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9485 12:40:39.864177 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9486 12:40:39.867595 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9487 12:40:39.874504 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9488 12:40:39.877336 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9489 12:40:39.880940 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9490 12:40:39.884398 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9491 12:40:39.887800 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9492 12:40:39.894396 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9493 12:40:39.897953 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9494 12:40:39.901260 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9495 12:40:39.904540 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9496 12:40:39.910944 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9497 12:40:39.914374 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9498 12:40:39.917790 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9499 12:40:39.920980 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9500 12:40:39.927600 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9501 12:40:39.930855 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9502 12:40:39.934502 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9503 12:40:39.941200 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9504 12:40:39.944688 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9505 12:40:39.950942 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9506 12:40:39.954708 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9507 12:40:39.960849 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9508 12:40:39.964104 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9509 12:40:39.967887 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9510 12:40:39.974732 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9511 12:40:39.977529 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9512 12:40:39.984547 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9513 12:40:39.988013 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9514 12:40:39.994183 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9515 12:40:39.997561 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9516 12:40:40.000807 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9517 12:40:40.007735 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9518 12:40:40.011126 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9519 12:40:40.018142 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9520 12:40:40.020907 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9521 12:40:40.027550 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9522 12:40:40.030910 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9523 12:40:40.034788 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9524 12:40:40.040848 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9525 12:40:40.044212 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9526 12:40:40.051199 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9527 12:40:40.054447 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9528 12:40:40.057877 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9529 12:40:40.064880 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9530 12:40:40.067608 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9531 12:40:40.074442 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9532 12:40:40.077914 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9533 12:40:40.084468 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9534 12:40:40.088281 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9535 12:40:40.095001 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9536 12:40:40.097912 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9537 12:40:40.101279 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9538 12:40:40.108005 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9539 12:40:40.111730 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9540 12:40:40.117850 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9541 12:40:40.121277 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9542 12:40:40.124784 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9543 12:40:40.131758 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9544 12:40:40.134487 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9545 12:40:40.141779 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9546 12:40:40.144572 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9547 12:40:40.151676 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9548 12:40:40.154538 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9549 12:40:40.161230 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9550 12:40:40.164498 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9551 12:40:40.168106 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9552 12:40:40.171470 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9553 12:40:40.178172 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9554 12:40:40.181726 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9555 12:40:40.184557 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9556 12:40:40.191430 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9557 12:40:40.194856 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9558 12:40:40.198043 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9559 12:40:40.205127 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9560 12:40:40.208429 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9561 12:40:40.215098 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9562 12:40:40.218612 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9563 12:40:40.221949 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9564 12:40:40.228298 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9565 12:40:40.231779 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9566 12:40:40.235273 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9567 12:40:40.241549 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9568 12:40:40.245067 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9569 12:40:40.251718 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9570 12:40:40.255130 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9571 12:40:40.258711 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9572 12:40:40.264906 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9573 12:40:40.268556 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9574 12:40:40.272060 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9575 12:40:40.275386 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9576 12:40:40.278731 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9577 12:40:40.285065 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9578 12:40:40.288816 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9579 12:40:40.291804 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9580 12:40:40.298604 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9581 12:40:40.302028 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9582 12:40:40.308373 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9583 12:40:40.311709 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9584 12:40:40.315627 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9585 12:40:40.321849 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9586 12:40:40.325087 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9587 12:40:40.331905 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9588 12:40:40.335494 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9589 12:40:40.339023 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9590 12:40:40.345339 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9591 12:40:40.348637 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9592 12:40:40.352180 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9593 12:40:40.358389 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9594 12:40:40.361790 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9595 12:40:40.368902 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9596 12:40:40.371681 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9597 12:40:40.375066 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9598 12:40:40.382240 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9599 12:40:40.384997 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9600 12:40:40.392006 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9601 12:40:40.395222 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9602 12:40:40.398502 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9603 12:40:40.405240 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9604 12:40:40.408497 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9605 12:40:40.411612 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9606 12:40:40.418310 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9607 12:40:40.421692 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9608 12:40:40.428992 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9609 12:40:40.432157 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9610 12:40:40.435547 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9611 12:40:40.441813 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9612 12:40:40.445713 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9613 12:40:40.451821 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9614 12:40:40.455234 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9615 12:40:40.458649 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9616 12:40:40.465512 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9617 12:40:40.468931 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9618 12:40:40.472327 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9619 12:40:40.478806 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9620 12:40:40.482160 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9621 12:40:40.488458 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9622 12:40:40.492049 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9623 12:40:40.495552 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9624 12:40:40.501673 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9625 12:40:40.505055 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9626 12:40:40.512186 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9627 12:40:40.514816 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9628 12:40:40.518298 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9629 12:40:40.524887 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9630 12:40:40.528146 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9631 12:40:40.535332 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9632 12:40:40.538560 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9633 12:40:40.541907 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9634 12:40:40.548470 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9635 12:40:40.551675 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9636 12:40:40.555276 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9637 12:40:40.561691 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9638 12:40:40.565493 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9639 12:40:40.571975 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9640 12:40:40.575352 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9641 12:40:40.578192 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9642 12:40:40.585225 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9643 12:40:40.588659 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9644 12:40:40.595123 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9645 12:40:40.598582 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9646 12:40:40.602013 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9647 12:40:40.608161 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9648 12:40:40.611504 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9649 12:40:40.618474 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9650 12:40:40.621253 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9651 12:40:40.628086 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9652 12:40:40.631456 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9653 12:40:40.634886 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9654 12:40:40.641463 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9655 12:40:40.644776 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9656 12:40:40.651298 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9657 12:40:40.654599 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9658 12:40:40.661368 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9659 12:40:40.664606 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9660 12:40:40.667887 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9661 12:40:40.674276 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9662 12:40:40.677583 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9663 12:40:40.684399 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9664 12:40:40.687742 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9665 12:40:40.691270 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9666 12:40:40.697609 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9667 12:40:40.701093 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9668 12:40:40.708014 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9669 12:40:40.710762 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9670 12:40:40.717492 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9671 12:40:40.721417 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9672 12:40:40.724184 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9673 12:40:40.730712 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9674 12:40:40.734236 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9675 12:40:40.741118 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9676 12:40:40.744457 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9677 12:40:40.747811 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9678 12:40:40.753924 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9679 12:40:40.757789 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9680 12:40:40.764054 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9681 12:40:40.767563 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9682 12:40:40.774190 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9683 12:40:40.777582 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9684 12:40:40.780318 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9685 12:40:40.783796 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9686 12:40:40.787145 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9687 12:40:40.793894 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9688 12:40:40.797152 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9689 12:40:40.800392 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9690 12:40:40.807753 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9691 12:40:40.810489 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9692 12:40:40.813988 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9693 12:40:40.821035 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9694 12:40:40.823847 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9695 12:40:40.830386 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9696 12:40:40.833998 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9697 12:40:40.837570 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9698 12:40:40.843733 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9699 12:40:40.847341 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9700 12:40:40.850912 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9701 12:40:40.857146 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9702 12:40:40.860690 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9703 12:40:40.864177 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9704 12:40:40.870182 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9705 12:40:40.873955 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9706 12:40:40.880251 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9707 12:40:40.883458 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9708 12:40:40.887512 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9709 12:40:40.893645 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9710 12:40:40.897020 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9711 12:40:40.900368 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9712 12:40:40.907330 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9713 12:40:40.910815 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9714 12:40:40.913939 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9715 12:40:40.920333 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9716 12:40:40.923802 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9717 12:40:40.930001 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9718 12:40:40.933286 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9719 12:40:40.936661 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9720 12:40:40.943603 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9721 12:40:40.947076 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9722 12:40:40.949910 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9723 12:40:40.956700 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9724 12:40:40.960094 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9725 12:40:40.963358 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9726 12:40:40.966929 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9727 12:40:40.969778 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9728 12:40:40.976801 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9729 12:40:40.979571 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9730 12:40:40.983022 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9731 12:40:40.986801 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9732 12:40:40.993307 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9733 12:40:40.996551 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9734 12:40:40.999786 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9735 12:40:41.006748 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9736 12:40:41.010010 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9737 12:40:41.013377 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9738 12:40:41.019581 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9739 12:40:41.023011 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9740 12:40:41.029854 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9741 12:40:41.033267 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9742 12:40:41.039442 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9743 12:40:41.042886 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9744 12:40:41.046198 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9745 12:40:41.053242 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9746 12:40:41.056048 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9747 12:40:41.063025 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9748 12:40:41.066302 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9749 12:40:41.069919 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9750 12:40:41.076233 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9751 12:40:41.079714 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9752 12:40:41.085956 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9753 12:40:41.089405 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9754 12:40:41.092806 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9755 12:40:41.099892 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9756 12:40:41.103021 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9757 12:40:41.109234 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9758 12:40:41.112603 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9759 12:40:41.116067 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9760 12:40:41.122908 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9761 12:40:41.125967 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9762 12:40:41.132906 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9763 12:40:41.136093 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9764 12:40:41.142826 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9765 12:40:41.145875 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9766 12:40:41.149004 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9767 12:40:41.155944 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9768 12:40:41.159176 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9769 12:40:41.166032 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9770 12:40:41.168857 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9771 12:40:41.172199 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9772 12:40:41.179087 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9773 12:40:41.182607 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9774 12:40:41.188958 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9775 12:40:41.192306 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9776 12:40:41.195802 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9777 12:40:41.202726 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9778 12:40:41.205524 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9779 12:40:41.212207 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9780 12:40:41.215625 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9781 12:40:41.219160 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9782 12:40:41.226020 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9783 12:40:41.228800 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9784 12:40:41.235654 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9785 12:40:41.239312 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9786 12:40:41.242408 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9787 12:40:41.248748 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9788 12:40:41.252091 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9789 12:40:41.259198 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9790 12:40:41.262550 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9791 12:40:41.265676 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9792 12:40:41.272135 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9793 12:40:41.275897 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9794 12:40:41.282043 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9795 12:40:41.285561 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9796 12:40:41.288918 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9797 12:40:41.295901 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9798 12:40:41.298740 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9799 12:40:41.305731 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9800 12:40:41.309226 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9801 12:40:41.312056 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9802 12:40:41.318837 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9803 12:40:41.322297 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9804 12:40:41.328915 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9805 12:40:41.332470 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9806 12:40:41.338814 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9807 12:40:41.342214 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9808 12:40:41.345608 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9809 12:40:41.352429 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9810 12:40:41.355557 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9811 12:40:41.362076 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9812 12:40:41.365748 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9813 12:40:41.372524 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9814 12:40:41.375321 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9815 12:40:41.378602 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9816 12:40:41.385281 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9817 12:40:41.388999 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9818 12:40:41.395436 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9819 12:40:41.398557 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9820 12:40:41.405139 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9821 12:40:41.408558 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9822 12:40:41.412107 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9823 12:40:41.418357 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9824 12:40:41.421818 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9825 12:40:41.432904 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9826 12:40:41.433035 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9827 12:40:41.439097 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9828 12:40:41.441880 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9829 12:40:41.445353 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9830 12:40:41.451808 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9831 12:40:41.455321 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9832 12:40:41.462100 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9833 12:40:41.465554 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9834 12:40:41.471590 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9835 12:40:41.474937 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9836 12:40:41.478495 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9837 12:40:41.485377 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9838 12:40:41.488822 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9839 12:40:41.495467 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9840 12:40:41.499008 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9841 12:40:41.504790 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9842 12:40:41.508656 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9843 12:40:41.511678 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9844 12:40:41.518326 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9845 12:40:41.522046 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9846 12:40:41.528194 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9847 12:40:41.531926 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9848 12:40:41.538096 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9849 12:40:41.541682 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9850 12:40:41.545199 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9851 12:40:41.551584 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9852 12:40:41.555050 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9853 12:40:41.561257 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9854 12:40:41.564743 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9855 12:40:41.571549 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9856 12:40:41.574923 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9857 12:40:41.577787 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9858 12:40:41.584771 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9859 12:40:41.588109 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9860 12:40:41.594956 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9861 12:40:41.598134 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9862 12:40:41.604456 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9863 12:40:41.608314 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9864 12:40:41.614474 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9865 12:40:41.617876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9866 12:40:41.624474 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9867 12:40:41.627648 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9868 12:40:41.634769 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9869 12:40:41.637881 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9870 12:40:41.644668 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9871 12:40:41.647818 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9872 12:40:41.654713 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9873 12:40:41.657572 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9874 12:40:41.664552 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9875 12:40:41.668061 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9876 12:40:41.674319 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9877 12:40:41.677825 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9878 12:40:41.684629 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9879 12:40:41.687434 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9880 12:40:41.694263 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9881 12:40:41.697750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9882 12:40:41.703935 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9883 12:40:41.707181 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9884 12:40:41.714202 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9885 12:40:41.717491 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9886 12:40:41.723717 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9887 12:40:41.727183 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9888 12:40:41.730593 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9889 12:40:41.734079 INFO: [APUAPC] vio 0
9890 12:40:41.737526 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9891 12:40:41.744432 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9892 12:40:41.747625 INFO: [APUAPC] D0_APC_0: 0x400510
9893 12:40:41.750876 INFO: [APUAPC] D0_APC_1: 0x0
9894 12:40:41.754339 INFO: [APUAPC] D0_APC_2: 0x1540
9895 12:40:41.754416 INFO: [APUAPC] D0_APC_3: 0x0
9896 12:40:41.757588 INFO: [APUAPC] D1_APC_0: 0xffffffff
9897 12:40:41.760755 INFO: [APUAPC] D1_APC_1: 0xffffffff
9898 12:40:41.764031 INFO: [APUAPC] D1_APC_2: 0x3fffff
9899 12:40:41.767406 INFO: [APUAPC] D1_APC_3: 0x0
9900 12:40:41.770945 INFO: [APUAPC] D2_APC_0: 0xffffffff
9901 12:40:41.774468 INFO: [APUAPC] D2_APC_1: 0xffffffff
9902 12:40:41.777260 INFO: [APUAPC] D2_APC_2: 0x3fffff
9903 12:40:41.780836 INFO: [APUAPC] D2_APC_3: 0x0
9904 12:40:41.784329 INFO: [APUAPC] D3_APC_0: 0xffffffff
9905 12:40:41.787621 INFO: [APUAPC] D3_APC_1: 0xffffffff
9906 12:40:41.791008 INFO: [APUAPC] D3_APC_2: 0x3fffff
9907 12:40:41.794508 INFO: [APUAPC] D3_APC_3: 0x0
9908 12:40:41.797353 INFO: [APUAPC] D4_APC_0: 0xffffffff
9909 12:40:41.800779 INFO: [APUAPC] D4_APC_1: 0xffffffff
9910 12:40:41.804213 INFO: [APUAPC] D4_APC_2: 0x3fffff
9911 12:40:41.807062 INFO: [APUAPC] D4_APC_3: 0x0
9912 12:40:41.810470 INFO: [APUAPC] D5_APC_0: 0xffffffff
9913 12:40:41.813995 INFO: [APUAPC] D5_APC_1: 0xffffffff
9914 12:40:41.817644 INFO: [APUAPC] D5_APC_2: 0x3fffff
9915 12:40:41.820306 INFO: [APUAPC] D5_APC_3: 0x0
9916 12:40:41.824264 INFO: [APUAPC] D6_APC_0: 0xffffffff
9917 12:40:41.827495 INFO: [APUAPC] D6_APC_1: 0xffffffff
9918 12:40:41.830728 INFO: [APUAPC] D6_APC_2: 0x3fffff
9919 12:40:41.833834 INFO: [APUAPC] D6_APC_3: 0x0
9920 12:40:41.837384 INFO: [APUAPC] D7_APC_0: 0xffffffff
9921 12:40:41.840392 INFO: [APUAPC] D7_APC_1: 0xffffffff
9922 12:40:41.843898 INFO: [APUAPC] D7_APC_2: 0x3fffff
9923 12:40:41.847093 INFO: [APUAPC] D7_APC_3: 0x0
9924 12:40:41.850312 INFO: [APUAPC] D8_APC_0: 0xffffffff
9925 12:40:41.854086 INFO: [APUAPC] D8_APC_1: 0xffffffff
9926 12:40:41.856835 INFO: [APUAPC] D8_APC_2: 0x3fffff
9927 12:40:41.860510 INFO: [APUAPC] D8_APC_3: 0x0
9928 12:40:41.863959 INFO: [APUAPC] D9_APC_0: 0xffffffff
9929 12:40:41.867401 INFO: [APUAPC] D9_APC_1: 0xffffffff
9930 12:40:41.870736 INFO: [APUAPC] D9_APC_2: 0x3fffff
9931 12:40:41.873847 INFO: [APUAPC] D9_APC_3: 0x0
9932 12:40:41.877153 INFO: [APUAPC] D10_APC_0: 0xffffffff
9933 12:40:41.880435 INFO: [APUAPC] D10_APC_1: 0xffffffff
9934 12:40:41.883959 INFO: [APUAPC] D10_APC_2: 0x3fffff
9935 12:40:41.886834 INFO: [APUAPC] D10_APC_3: 0x0
9936 12:40:41.890255 INFO: [APUAPC] D11_APC_0: 0xffffffff
9937 12:40:41.893734 INFO: [APUAPC] D11_APC_1: 0xffffffff
9938 12:40:41.896979 INFO: [APUAPC] D11_APC_2: 0x3fffff
9939 12:40:41.900397 INFO: [APUAPC] D11_APC_3: 0x0
9940 12:40:41.903923 INFO: [APUAPC] D12_APC_0: 0xffffffff
9941 12:40:41.907226 INFO: [APUAPC] D12_APC_1: 0xffffffff
9942 12:40:41.910025 INFO: [APUAPC] D12_APC_2: 0x3fffff
9943 12:40:41.913650 INFO: [APUAPC] D12_APC_3: 0x0
9944 12:40:41.917107 INFO: [APUAPC] D13_APC_0: 0xffffffff
9945 12:40:41.919874 INFO: [APUAPC] D13_APC_1: 0xffffffff
9946 12:40:41.923315 INFO: [APUAPC] D13_APC_2: 0x3fffff
9947 12:40:41.926848 INFO: [APUAPC] D13_APC_3: 0x0
9948 12:40:41.930338 INFO: [APUAPC] D14_APC_0: 0xffffffff
9949 12:40:41.933833 INFO: [APUAPC] D14_APC_1: 0xffffffff
9950 12:40:41.936622 INFO: [APUAPC] D14_APC_2: 0x3fffff
9951 12:40:41.940105 INFO: [APUAPC] D14_APC_3: 0x0
9952 12:40:41.943602 INFO: [APUAPC] D15_APC_0: 0xffffffff
9953 12:40:41.946999 INFO: [APUAPC] D15_APC_1: 0xffffffff
9954 12:40:41.950422 INFO: [APUAPC] D15_APC_2: 0x3fffff
9955 12:40:41.953530 INFO: [APUAPC] D15_APC_3: 0x0
9956 12:40:41.956703 INFO: [APUAPC] APC_CON: 0x4
9957 12:40:41.960196 INFO: [NOCDAPC] D0_APC_0: 0x0
9958 12:40:41.960323 INFO: [NOCDAPC] D0_APC_1: 0x0
9959 12:40:41.963466 INFO: [NOCDAPC] D1_APC_0: 0x0
9960 12:40:41.966577 INFO: [NOCDAPC] D1_APC_1: 0xfff
9961 12:40:41.970091 INFO: [NOCDAPC] D2_APC_0: 0x0
9962 12:40:41.973281 INFO: [NOCDAPC] D2_APC_1: 0xfff
9963 12:40:41.976915 INFO: [NOCDAPC] D3_APC_0: 0x0
9964 12:40:41.979864 INFO: [NOCDAPC] D3_APC_1: 0xfff
9965 12:40:41.983080 INFO: [NOCDAPC] D4_APC_0: 0x0
9966 12:40:41.986375 INFO: [NOCDAPC] D4_APC_1: 0xfff
9967 12:40:41.989741 INFO: [NOCDAPC] D5_APC_0: 0x0
9968 12:40:41.993474 INFO: [NOCDAPC] D5_APC_1: 0xfff
9969 12:40:41.993558 INFO: [NOCDAPC] D6_APC_0: 0x0
9970 12:40:41.996718 INFO: [NOCDAPC] D6_APC_1: 0xfff
9971 12:40:41.999947 INFO: [NOCDAPC] D7_APC_0: 0x0
9972 12:40:42.003280 INFO: [NOCDAPC] D7_APC_1: 0xfff
9973 12:40:42.006593 INFO: [NOCDAPC] D8_APC_0: 0x0
9974 12:40:42.010126 INFO: [NOCDAPC] D8_APC_1: 0xfff
9975 12:40:42.012932 INFO: [NOCDAPC] D9_APC_0: 0x0
9976 12:40:42.016399 INFO: [NOCDAPC] D9_APC_1: 0xfff
9977 12:40:42.019894 INFO: [NOCDAPC] D10_APC_0: 0x0
9978 12:40:42.023402 INFO: [NOCDAPC] D10_APC_1: 0xfff
9979 12:40:42.026288 INFO: [NOCDAPC] D11_APC_0: 0x0
9980 12:40:42.029826 INFO: [NOCDAPC] D11_APC_1: 0xfff
9981 12:40:42.029929 INFO: [NOCDAPC] D12_APC_0: 0x0
9982 12:40:42.033275 INFO: [NOCDAPC] D12_APC_1: 0xfff
9983 12:40:42.036044 INFO: [NOCDAPC] D13_APC_0: 0x0
9984 12:40:42.039491 INFO: [NOCDAPC] D13_APC_1: 0xfff
9985 12:40:42.042850 INFO: [NOCDAPC] D14_APC_0: 0x0
9986 12:40:42.046390 INFO: [NOCDAPC] D14_APC_1: 0xfff
9987 12:40:42.049880 INFO: [NOCDAPC] D15_APC_0: 0x0
9988 12:40:42.053365 INFO: [NOCDAPC] D15_APC_1: 0xfff
9989 12:40:42.056099 INFO: [NOCDAPC] APC_CON: 0x4
9990 12:40:42.059615 INFO: [APUAPC] set_apusys_apc done
9991 12:40:42.063081 INFO: [DEVAPC] devapc_init done
9992 12:40:42.066037 INFO: GICv3 without legacy support detected.
9993 12:40:42.069244 INFO: ARM GICv3 driver initialized in EL3
9994 12:40:42.072627 INFO: Maximum SPI INTID supported: 639
9995 12:40:42.079543 INFO: BL31: Initializing runtime services
9996 12:40:42.082925 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9997 12:40:42.086229 INFO: SPM: enable CPC mode
9998 12:40:42.092998 INFO: mcdi ready for mcusys-off-idle and system suspend
9999 12:40:42.096323 INFO: BL31: Preparing for EL3 exit to normal world
10000 12:40:42.099848 INFO: Entry point address = 0x80000000
10001 12:40:42.103042 INFO: SPSR = 0x8
10002 12:40:42.108139
10003 12:40:42.108252
10004 12:40:42.108367
10005 12:40:42.111405 Starting depthcharge on Spherion...
10006 12:40:42.111478
10007 12:40:42.111538 Wipe memory regions:
10008 12:40:42.111595
10009 12:40:42.112536 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10010 12:40:42.112642 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10011 12:40:42.112721 Setting prompt string to ['asurada:']
10012 12:40:42.112798 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10013 12:40:42.114349 [0x00000040000000, 0x00000054600000)
10014 12:40:42.236815
10015 12:40:42.236978 [0x00000054660000, 0x00000080000000)
10016 12:40:42.497245
10017 12:40:42.497379 [0x000000821a7280, 0x000000ffe64000)
10018 12:40:43.241797
10019 12:40:43.241939 [0x00000100000000, 0x00000240000000)
10020 12:40:45.131598
10021 12:40:45.135156 Initializing XHCI USB controller at 0x11200000.
10022 12:40:46.173041
10023 12:40:46.175733 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10024 12:40:46.175827
10025 12:40:46.175891
10026 12:40:46.175949
10027 12:40:46.176232 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10029 12:40:46.276602 asurada: tftpboot 192.168.201.1 12703534/tftp-deploy-o6tibqjn/kernel/image.itb 12703534/tftp-deploy-o6tibqjn/kernel/cmdline
10030 12:40:46.276746 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10031 12:40:46.276861 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10032 12:40:46.281230 tftpboot 192.168.201.1 12703534/tftp-deploy-o6tibqjn/kernel/image.itp-deploy-o6tibqjn/kernel/cmdline
10033 12:40:46.281313
10034 12:40:46.281375 Waiting for link
10035 12:40:46.441618
10036 12:40:46.441748 R8152: Initializing
10037 12:40:46.441822
10038 12:40:46.445293 Version 9 (ocp_data = 6010)
10039 12:40:46.445378
10040 12:40:46.448059 R8152: Done initializing
10041 12:40:46.448181
10042 12:40:46.448295 Adding net device
10043 12:40:48.394612
10044 12:40:48.394749 done.
10045 12:40:48.394817
10046 12:40:48.394877 MAC: 00:e0:4c:78:7a:aa
10047 12:40:48.394935
10048 12:40:48.398180 Sending DHCP discover... done.
10049 12:40:48.398260
10050 12:40:48.401222 Waiting for reply... done.
10051 12:40:48.401305
10052 12:40:48.404396 Sending DHCP request... done.
10053 12:40:48.404468
10054 12:40:48.404543 Waiting for reply... done.
10055 12:40:48.407834
10056 12:40:48.407901 My ip is 192.168.201.12
10057 12:40:48.407960
10058 12:40:48.410796 The DHCP server ip is 192.168.201.1
10059 12:40:48.410869
10060 12:40:48.414413 TFTP server IP predefined by user: 192.168.201.1
10061 12:40:48.414483
10062 12:40:48.420671 Bootfile predefined by user: 12703534/tftp-deploy-o6tibqjn/kernel/image.itb
10063 12:40:48.420743
10064 12:40:48.423952 Sending tftp read request... done.
10065 12:40:48.424046
10066 12:40:48.427467 Waiting for the transfer...
10067 12:40:48.427556
10068 12:40:48.686507 00000000 ################################################################
10069 12:40:48.686644
10070 12:40:48.943880 00080000 ################################################################
10071 12:40:48.944036
10072 12:40:49.195867 00100000 ################################################################
10073 12:40:49.196038
10074 12:40:49.448492 00180000 ################################################################
10075 12:40:49.448661
10076 12:40:49.707831 00200000 ################################################################
10077 12:40:49.707994
10078 12:40:49.981061 00280000 ################################################################
10079 12:40:49.981227
10080 12:40:50.250294 00300000 ################################################################
10081 12:40:50.250425
10082 12:40:50.510028 00380000 ################################################################
10083 12:40:50.510167
10084 12:40:50.760769 00400000 ################################################################
10085 12:40:50.760899
10086 12:40:51.012749 00480000 ################################################################
10087 12:40:51.012886
10088 12:40:51.263278 00500000 ################################################################
10089 12:40:51.263415
10090 12:40:51.510986 00580000 ################################################################
10091 12:40:51.511119
10092 12:40:51.762307 00600000 ################################################################
10093 12:40:51.762467
10094 12:40:52.008062 00680000 ################################################################
10095 12:40:52.008199
10096 12:40:52.261585 00700000 ################################################################
10097 12:40:52.261747
10098 12:40:52.515291 00780000 ################################################################
10099 12:40:52.515450
10100 12:40:52.767899 00800000 ################################################################
10101 12:40:52.768059
10102 12:40:53.035919 00880000 ################################################################
10103 12:40:53.036064
10104 12:40:53.304239 00900000 ################################################################
10105 12:40:53.304395
10106 12:40:53.568638 00980000 ################################################################
10107 12:40:53.568780
10108 12:40:53.821891 00a00000 ################################################################
10109 12:40:53.822049
10110 12:40:54.076241 00a80000 ################################################################
10111 12:40:54.076384
10112 12:40:54.324972 00b00000 ################################################################
10113 12:40:54.325112
10114 12:40:54.578710 00b80000 ################################################################
10115 12:40:54.578845
10116 12:40:54.828544 00c00000 ################################################################
10117 12:40:54.828700
10118 12:40:55.082788 00c80000 ################################################################
10119 12:40:55.082951
10120 12:40:55.331513 00d00000 ################################################################
10121 12:40:55.331699
10122 12:40:55.593385 00d80000 ################################################################
10123 12:40:55.593518
10124 12:40:55.862137 00e00000 ################################################################
10125 12:40:55.862308
10126 12:40:56.125357 00e80000 ################################################################
10127 12:40:56.125490
10128 12:40:56.382890 00f00000 ################################################################
10129 12:40:56.383054
10130 12:40:56.640172 00f80000 ################################################################
10131 12:40:56.640348
10132 12:40:56.895263 01000000 ################################################################
10133 12:40:56.895427
10134 12:40:57.144886 01080000 ################################################################
10135 12:40:57.145050
10136 12:40:57.394381 01100000 ################################################################
10137 12:40:57.394542
10138 12:40:57.647766 01180000 ################################################################
10139 12:40:57.647922
10140 12:40:57.898412 01200000 ################################################################
10141 12:40:57.898539
10142 12:40:58.150800 01280000 ################################################################
10143 12:40:58.150940
10144 12:40:58.405511 01300000 ################################################################
10145 12:40:58.405677
10146 12:40:58.655278 01380000 ################################################################
10147 12:40:58.655409
10148 12:40:58.907579 01400000 ################################################################
10149 12:40:58.907735
10150 12:40:59.169804 01480000 ################################################################
10151 12:40:59.169963
10152 12:40:59.443892 01500000 ################################################################
10153 12:40:59.444057
10154 12:40:59.709268 01580000 ################################################################
10155 12:40:59.709410
10156 12:40:59.962961 01600000 ################################################################
10157 12:40:59.963091
10158 12:41:00.213567 01680000 ################################################################
10159 12:41:00.213707
10160 12:41:00.460767 01700000 ################################################################
10161 12:41:00.460922
10162 12:41:00.710138 01780000 ################################################################
10163 12:41:00.710302
10164 12:41:00.962672 01800000 ################################################################
10165 12:41:00.962836
10166 12:41:01.216076 01880000 ################################################################
10167 12:41:01.216242
10168 12:41:01.476921 01900000 ################################################################
10169 12:41:01.477085
10170 12:41:01.743351 01980000 ################################################################
10171 12:41:01.743514
10172 12:41:02.011179 01a00000 ################################################################
10173 12:41:02.011322
10174 12:41:02.282575 01a80000 ################################################################
10175 12:41:02.282733
10176 12:41:02.542388 01b00000 ################################################################
10177 12:41:02.542543
10178 12:41:02.794761 01b80000 ################################################################
10179 12:41:02.794919
10180 12:41:03.047248 01c00000 ################################################################
10181 12:41:03.047373
10182 12:41:03.304248 01c80000 ################################################################
10183 12:41:03.304414
10184 12:41:03.558896 01d00000 ################################################################
10185 12:41:03.559061
10186 12:41:03.820753 01d80000 ################################################################
10187 12:41:03.820901
10188 12:41:04.070985 01e00000 ################################################################
10189 12:41:04.071151
10190 12:41:04.323229 01e80000 ################################################################
10191 12:41:04.323374
10192 12:41:04.574203 01f00000 ################################################################
10193 12:41:04.574340
10194 12:41:04.829619 01f80000 ################################################################
10195 12:41:04.829748
10196 12:41:05.094494 02000000 ################################################################
10197 12:41:05.094628
10198 12:41:05.355503 02080000 ################################################################
10199 12:41:05.355665
10200 12:41:05.613168 02100000 ################################################################
10201 12:41:05.613305
10202 12:41:05.861681 02180000 ################################################################
10203 12:41:05.861812
10204 12:41:06.110801 02200000 ################################################################
10205 12:41:06.110933
10206 12:41:06.364426 02280000 ################################################################
10207 12:41:06.364561
10208 12:41:06.615965 02300000 ################################################################
10209 12:41:06.616146
10210 12:41:06.869053 02380000 ################################################################
10211 12:41:06.869182
10212 12:41:07.121901 02400000 ################################################################
10213 12:41:07.122058
10214 12:41:07.372060 02480000 ################################################################
10215 12:41:07.372193
10216 12:41:07.629889 02500000 ################################################################
10217 12:41:07.630022
10218 12:41:07.876880 02580000 ################################################################
10219 12:41:07.877014
10220 12:41:08.125712 02600000 ################################################################
10221 12:41:08.125887
10222 12:41:08.373942 02680000 ################################################################
10223 12:41:08.374097
10224 12:41:08.624777 02700000 ################################################################
10225 12:41:08.624918
10226 12:41:08.883316 02780000 ################################################################
10227 12:41:08.883461
10228 12:41:09.132817 02800000 ################################################################
10229 12:41:09.132957
10230 12:41:09.391473 02880000 ################################################################
10231 12:41:09.391606
10232 12:41:09.638643 02900000 ################################################################
10233 12:41:09.638838
10234 12:41:09.887983 02980000 ################################################################
10235 12:41:09.888118
10236 12:41:10.150712 02a00000 ################################################################
10237 12:41:10.150842
10238 12:41:10.406509 02a80000 ################################################################
10239 12:41:10.406647
10240 12:41:10.665029 02b00000 ################################################################
10241 12:41:10.665158
10242 12:41:10.923925 02b80000 ################################################################
10243 12:41:10.924057
10244 12:41:11.177437 02c00000 ################################################################
10245 12:41:11.177565
10246 12:41:11.429839 02c80000 ################################################################
10247 12:41:11.429983
10248 12:41:11.681955 02d00000 ################################################################
10249 12:41:11.682084
10250 12:41:11.937224 02d80000 ################################################################
10251 12:41:11.937352
10252 12:41:12.196965 02e00000 ################################################################
10253 12:41:12.197095
10254 12:41:12.461387 02e80000 ################################################################
10255 12:41:12.461516
10256 12:41:12.712141 02f00000 ################################################################
10257 12:41:12.712272
10258 12:41:12.965360 02f80000 ################################################################
10259 12:41:12.965505
10260 12:41:13.223344 03000000 ################################################################
10261 12:41:13.223495
10262 12:41:13.488225 03080000 ################################################################
10263 12:41:13.488362
10264 12:41:13.530837 03100000 ########### done.
10265 12:41:13.530973
10266 12:41:13.534509 The bootfile was 51463002 bytes long.
10267 12:41:13.534590
10268 12:41:13.537483 Sending tftp read request... done.
10269 12:41:13.537563
10270 12:41:13.537628 Waiting for the transfer...
10271 12:41:13.541445
10272 12:41:13.541527 00000000 # done.
10273 12:41:13.541595
10274 12:41:13.547642 Command line loaded dynamically from TFTP file: 12703534/tftp-deploy-o6tibqjn/kernel/cmdline
10275 12:41:13.547724
10276 12:41:13.561310 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10277 12:41:13.561395
10278 12:41:13.564562 Loading FIT.
10279 12:41:13.564645
10280 12:41:13.567825 Image ramdisk-1 has 39360831 bytes.
10281 12:41:13.567932
10282 12:41:13.571334 Image fdt-1 has 47278 bytes.
10283 12:41:13.571415
10284 12:41:13.571479 Image kernel-1 has 12052857 bytes.
10285 12:41:13.574285
10286 12:41:13.580926 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10287 12:41:13.581010
10288 12:41:13.597565 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10289 12:41:13.597676
10290 12:41:13.604457 Choosing best match conf-1 for compat google,spherion-rev2.
10291 12:41:13.608596
10292 12:41:13.613237 Connected to device vid:did:rid of 1ae0:0028:00
10293 12:41:13.621326
10294 12:41:13.624862 tpm_get_response: command 0x17b, return code 0x0
10295 12:41:13.624944
10296 12:41:13.628241 ec_init: CrosEC protocol v3 supported (256, 248)
10297 12:41:13.631629
10298 12:41:13.635087 tpm_cleanup: add release locality here.
10299 12:41:13.635168
10300 12:41:13.635232 Shutting down all USB controllers.
10301 12:41:13.638305
10302 12:41:13.638385 Removing current net device
10303 12:41:13.638449
10304 12:41:13.645550 Exiting depthcharge with code 4 at timestamp: 60802107
10305 12:41:13.645631
10306 12:41:13.648487 LZMA decompressing kernel-1 to 0x821a6718
10307 12:41:13.648568
10308 12:41:13.651788 LZMA decompressing kernel-1 to 0x40000000
10309 12:41:15.151613
10310 12:41:15.151755 jumping to kernel
10311 12:41:15.152260 end: 2.2.4 bootloader-commands (duration 00:00:33) [common]
10312 12:41:15.152396 start: 2.2.5 auto-login-action (timeout 00:03:52) [common]
10313 12:41:15.152470 Setting prompt string to ['Linux version [0-9]']
10314 12:41:15.152537 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10315 12:41:15.152602 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10316 12:41:15.234201
10317 12:41:15.237299 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10318 12:41:15.241147 start: 2.2.5.1 login-action (timeout 00:03:52) [common]
10319 12:41:15.241241 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10320 12:41:15.241311 Setting prompt string to []
10321 12:41:15.241388 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10322 12:41:15.241464 Using line separator: #'\n'#
10323 12:41:15.241563 No login prompt set.
10324 12:41:15.241655 Parsing kernel messages
10325 12:41:15.241725 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10326 12:41:15.241852 [login-action] Waiting for messages, (timeout 00:03:52)
10327 12:41:15.241919 Waiting using forced prompt support (timeout 00:01:56)
10328 12:41:15.260315 [ 0.000000] Linux version 6.1.75-cip14 (KernelCI@build-j98433-arm64-gcc-10-defconfig-arm64-chromebook-89n64) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Feb 5 12:20:06 UTC 2024
10329 12:41:15.263916 [ 0.000000] random: crng init done
10330 12:41:15.267274 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10331 12:41:15.270756 [ 0.000000] efi: UEFI not found.
10332 12:41:15.280259 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10333 12:41:15.287089 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10334 12:41:15.296846 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10335 12:41:15.306918 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10336 12:41:15.313715 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10337 12:41:15.317115 [ 0.000000] printk: bootconsole [mtk8250] enabled
10338 12:41:15.325485 [ 0.000000] NUMA: No NUMA configuration found
10339 12:41:15.332576 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10340 12:41:15.339377 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10341 12:41:15.339460 [ 0.000000] Zone ranges:
10342 12:41:15.345650 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10343 12:41:15.348944 [ 0.000000] DMA32 empty
10344 12:41:15.355801 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10345 12:41:15.359230 [ 0.000000] Movable zone start for each node
10346 12:41:15.362308 [ 0.000000] Early memory node ranges
10347 12:41:15.368733 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10348 12:41:15.375632 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10349 12:41:15.381870 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10350 12:41:15.389018 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10351 12:41:15.395211 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10352 12:41:15.402063 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10353 12:41:15.458393 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10354 12:41:15.465059 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10355 12:41:15.471455 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10356 12:41:15.475254 [ 0.000000] psci: probing for conduit method from DT.
10357 12:41:15.481295 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10358 12:41:15.484697 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10359 12:41:15.491575 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10360 12:41:15.495065 [ 0.000000] psci: SMC Calling Convention v1.2
10361 12:41:15.501626 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10362 12:41:15.505151 [ 0.000000] Detected VIPT I-cache on CPU0
10363 12:41:15.511263 [ 0.000000] CPU features: detected: GIC system register CPU interface
10364 12:41:15.518069 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10365 12:41:15.524581 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10366 12:41:15.530993 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10367 12:41:15.538015 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10368 12:41:15.544825 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10369 12:41:15.551151 [ 0.000000] alternatives: applying boot alternatives
10370 12:41:15.557555 [ 0.000000] Fallback order for Node 0: 0
10371 12:41:15.564515 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10372 12:41:15.564596 [ 0.000000] Policy zone: Normal
10373 12:41:15.581373 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10374 12:41:15.590887 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10375 12:41:15.602864 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10376 12:41:15.612253 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10377 12:41:15.618939 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10378 12:41:15.622201 <6>[ 0.000000] software IO TLB: area num 8.
10379 12:41:15.679165 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10380 12:41:15.828165 <6>[ 0.000000] Memory: 7928816K/8385536K available (17984K kernel code, 4118K rwdata, 19612K rodata, 8448K init, 616K bss, 423952K reserved, 32768K cma-reserved)
10381 12:41:15.834856 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10382 12:41:15.841362 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10383 12:41:15.844595 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10384 12:41:15.851032 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10385 12:41:15.858029 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10386 12:41:15.860893 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10387 12:41:15.871485 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10388 12:41:15.877891 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10389 12:41:15.881376 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10390 12:41:15.889038 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10391 12:41:15.892564 <6>[ 0.000000] GICv3: 608 SPIs implemented
10392 12:41:15.898955 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10393 12:41:15.901920 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10394 12:41:15.905905 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10395 12:41:15.915802 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10396 12:41:15.925546 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10397 12:41:15.938861 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10398 12:41:15.945506 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10399 12:41:15.954222 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10400 12:41:15.967556 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10401 12:41:15.973898 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10402 12:41:15.981035 <6>[ 0.009179] Console: colour dummy device 80x25
10403 12:41:15.990927 <6>[ 0.013909] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10404 12:41:15.994401 <6>[ 0.024352] pid_max: default: 32768 minimum: 301
10405 12:41:16.001389 <6>[ 0.029253] LSM: Security Framework initializing
10406 12:41:16.007936 <6>[ 0.034222] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10407 12:41:16.017377 <6>[ 0.042085] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10408 12:41:16.024533 <6>[ 0.051508] cblist_init_generic: Setting adjustable number of callback queues.
10409 12:41:16.031117 <6>[ 0.058999] cblist_init_generic: Setting shift to 3 and lim to 1.
10410 12:41:16.040978 <6>[ 0.065338] cblist_init_generic: Setting adjustable number of callback queues.
10411 12:41:16.047570 <6>[ 0.072765] cblist_init_generic: Setting shift to 3 and lim to 1.
10412 12:41:16.051094 <6>[ 0.079204] rcu: Hierarchical SRCU implementation.
10413 12:41:16.057123 <6>[ 0.084250] rcu: Max phase no-delay instances is 1000.
10414 12:41:16.063911 <6>[ 0.091314] EFI services will not be available.
10415 12:41:16.067187 <6>[ 0.096272] smp: Bringing up secondary CPUs ...
10416 12:41:16.075209 <6>[ 0.101324] Detected VIPT I-cache on CPU1
10417 12:41:16.082461 <6>[ 0.101393] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10418 12:41:16.088353 <6>[ 0.101424] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10419 12:41:16.091831 <6>[ 0.101768] Detected VIPT I-cache on CPU2
10420 12:41:16.098815 <6>[ 0.101821] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10421 12:41:16.105137 <6>[ 0.101839] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10422 12:41:16.111861 <6>[ 0.102099] Detected VIPT I-cache on CPU3
10423 12:41:16.118567 <6>[ 0.102145] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10424 12:41:16.125474 <6>[ 0.102160] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10425 12:41:16.128878 <6>[ 0.102465] CPU features: detected: Spectre-v4
10426 12:41:16.135317 <6>[ 0.102470] CPU features: detected: Spectre-BHB
10427 12:41:16.138638 <6>[ 0.102475] Detected PIPT I-cache on CPU4
10428 12:41:16.145140 <6>[ 0.102526] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10429 12:41:16.151795 <6>[ 0.102542] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10430 12:41:16.158854 <6>[ 0.102819] Detected PIPT I-cache on CPU5
10431 12:41:16.165108 <6>[ 0.102876] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10432 12:41:16.172044 <6>[ 0.102892] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10433 12:41:16.175115 <6>[ 0.103174] Detected PIPT I-cache on CPU6
10434 12:41:16.181447 <6>[ 0.103240] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10435 12:41:16.188471 <6>[ 0.103256] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10436 12:41:16.194898 <6>[ 0.103557] Detected PIPT I-cache on CPU7
10437 12:41:16.201280 <6>[ 0.103624] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10438 12:41:16.208508 <6>[ 0.103640] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10439 12:41:16.211371 <6>[ 0.103688] smp: Brought up 1 node, 8 CPUs
10440 12:41:16.218299 <6>[ 0.245069] SMP: Total of 8 processors activated.
10441 12:41:16.221391 <6>[ 0.249990] CPU features: detected: 32-bit EL0 Support
10442 12:41:16.231440 <6>[ 0.255385] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10443 12:41:16.238140 <6>[ 0.264240] CPU features: detected: Common not Private translations
10444 12:41:16.241421 <6>[ 0.270716] CPU features: detected: CRC32 instructions
10445 12:41:16.248157 <6>[ 0.276067] CPU features: detected: RCpc load-acquire (LDAPR)
10446 12:41:16.255110 <6>[ 0.282064] CPU features: detected: LSE atomic instructions
10447 12:41:16.261819 <6>[ 0.287881] CPU features: detected: Privileged Access Never
10448 12:41:16.264708 <6>[ 0.293697] CPU features: detected: RAS Extension Support
10449 12:41:16.274501 <6>[ 0.299306] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10450 12:41:16.278093 <6>[ 0.306526] CPU: All CPU(s) started at EL2
10451 12:41:16.284735 <6>[ 0.310843] alternatives: applying system-wide alternatives
10452 12:41:16.293269 <6>[ 0.321597] devtmpfs: initialized
10453 12:41:16.305939 <6>[ 0.330724] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10454 12:41:16.315635 <6>[ 0.340684] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10455 12:41:16.322223 <6>[ 0.348928] pinctrl core: initialized pinctrl subsystem
10456 12:41:16.325687 <6>[ 0.355718] DMI not present or invalid.
10457 12:41:16.332041 <6>[ 0.360132] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10458 12:41:16.342129 <6>[ 0.367016] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10459 12:41:16.348666 <6>[ 0.374605] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10460 12:41:16.359091 <6>[ 0.382831] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10461 12:41:16.361655 <6>[ 0.391075] audit: initializing netlink subsys (disabled)
10462 12:41:16.371957 <5>[ 0.396768] audit: type=2000 audit(0.284:1): state=initialized audit_enabled=0 res=1
10463 12:41:16.378093 <6>[ 0.397520] thermal_sys: Registered thermal governor 'step_wise'
10464 12:41:16.384898 <6>[ 0.404737] thermal_sys: Registered thermal governor 'power_allocator'
10465 12:41:16.388382 <6>[ 0.410990] cpuidle: using governor menu
10466 12:41:16.395356 <6>[ 0.421949] NET: Registered PF_QIPCRTR protocol family
10467 12:41:16.401988 <6>[ 0.427422] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10468 12:41:16.408051 <6>[ 0.434523] ASID allocator initialised with 32768 entries
10469 12:41:16.411789 <6>[ 0.441150] Serial: AMBA PL011 UART driver
10470 12:41:16.421746 <4>[ 0.450264] Trying to register duplicate clock ID: 134
10471 12:41:16.478622 <6>[ 0.510265] KASLR enabled
10472 12:41:16.492739 <6>[ 0.517963] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10473 12:41:16.499792 <6>[ 0.524976] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10474 12:41:16.506067 <6>[ 0.531468] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10475 12:41:16.513007 <6>[ 0.538471] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10476 12:41:16.519208 <6>[ 0.544958] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10477 12:41:16.526223 <6>[ 0.551963] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10478 12:41:16.533103 <6>[ 0.558450] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10479 12:41:16.539265 <6>[ 0.565454] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10480 12:41:16.543068 <6>[ 0.572912] ACPI: Interpreter disabled.
10481 12:41:16.551024 <6>[ 0.579424] iommu: Default domain type: Translated
10482 12:41:16.557809 <6>[ 0.584538] iommu: DMA domain TLB invalidation policy: strict mode
10483 12:41:16.561346 <5>[ 0.591201] SCSI subsystem initialized
10484 12:41:16.567415 <6>[ 0.595449] usbcore: registered new interface driver usbfs
10485 12:41:16.574417 <6>[ 0.601180] usbcore: registered new interface driver hub
10486 12:41:16.577735 <6>[ 0.606731] usbcore: registered new device driver usb
10487 12:41:16.584501 <6>[ 0.612895] pps_core: LinuxPPS API ver. 1 registered
10488 12:41:16.594454 <6>[ 0.618089] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10489 12:41:16.597855 <6>[ 0.627434] PTP clock support registered
10490 12:41:16.601250 <6>[ 0.631679] EDAC MC: Ver: 3.0.0
10491 12:41:16.608849 <6>[ 0.636917] FPGA manager framework
10492 12:41:16.614991 <6>[ 0.640592] Advanced Linux Sound Architecture Driver Initialized.
10493 12:41:16.618420 <6>[ 0.647368] vgaarb: loaded
10494 12:41:16.625332 <6>[ 0.650511] clocksource: Switched to clocksource arch_sys_counter
10495 12:41:16.628709 <5>[ 0.656955] VFS: Disk quotas dquot_6.6.0
10496 12:41:16.635270 <6>[ 0.661142] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10497 12:41:16.638549 <6>[ 0.668334] pnp: PnP ACPI: disabled
10498 12:41:16.646841 <6>[ 0.674964] NET: Registered PF_INET protocol family
10499 12:41:16.656101 <6>[ 0.680554] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10500 12:41:16.667585 <6>[ 0.692874] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10501 12:41:16.677895 <6>[ 0.701692] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10502 12:41:16.684307 <6>[ 0.709663] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10503 12:41:16.691265 <6>[ 0.718364] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10504 12:41:16.703443 <6>[ 0.728119] TCP: Hash tables configured (established 65536 bind 65536)
10505 12:41:16.709690 <6>[ 0.734990] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10506 12:41:16.716444 <6>[ 0.742191] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10507 12:41:16.723329 <6>[ 0.749898] NET: Registered PF_UNIX/PF_LOCAL protocol family
10508 12:41:16.729669 <6>[ 0.756033] RPC: Registered named UNIX socket transport module.
10509 12:41:16.733361 <6>[ 0.762187] RPC: Registered udp transport module.
10510 12:41:16.740081 <6>[ 0.767119] RPC: Registered tcp transport module.
10511 12:41:16.746536 <6>[ 0.772052] RPC: Registered tcp NFSv4.1 backchannel transport module.
10512 12:41:16.750058 <6>[ 0.778716] PCI: CLS 0 bytes, default 64
10513 12:41:16.753460 <6>[ 0.783049] Unpacking initramfs...
10514 12:41:16.763116 <6>[ 0.786818] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10515 12:41:16.769912 <6>[ 0.795450] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10516 12:41:16.776503 <6>[ 0.804279] kvm [1]: IPA Size Limit: 40 bits
10517 12:41:16.779791 <6>[ 0.808807] kvm [1]: GICv3: no GICV resource entry
10518 12:41:16.786027 <6>[ 0.813828] kvm [1]: disabling GICv2 emulation
10519 12:41:16.792694 <6>[ 0.818513] kvm [1]: GIC system register CPU interface enabled
10520 12:41:16.796231 <6>[ 0.824683] kvm [1]: vgic interrupt IRQ18
10521 12:41:16.803205 <6>[ 0.830601] kvm [1]: VHE mode initialized successfully
10522 12:41:16.809328 <5>[ 0.836951] Initialise system trusted keyrings
10523 12:41:16.815954 <6>[ 0.841741] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10524 12:41:16.823426 <6>[ 0.851737] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10525 12:41:16.830407 <5>[ 0.858113] NFS: Registering the id_resolver key type
10526 12:41:16.833265 <5>[ 0.863415] Key type id_resolver registered
10527 12:41:16.840223 <5>[ 0.867828] Key type id_legacy registered
10528 12:41:16.846326 <6>[ 0.872106] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10529 12:41:16.852864 <6>[ 0.879024] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10530 12:41:16.859752 <6>[ 0.886730] 9p: Installing v9fs 9p2000 file system support
10531 12:41:16.896206 <5>[ 0.924262] Key type asymmetric registered
10532 12:41:16.899629 <5>[ 0.928592] Asymmetric key parser 'x509' registered
10533 12:41:16.909187 <6>[ 0.933728] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10534 12:41:16.912628 <6>[ 0.941343] io scheduler mq-deadline registered
10535 12:41:16.915587 <6>[ 0.946104] io scheduler kyber registered
10536 12:41:16.935459 <6>[ 0.963664] EINJ: ACPI disabled.
10537 12:41:16.968396 <4>[ 0.989826] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10538 12:41:16.978193 <4>[ 1.000474] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10539 12:41:16.992818 <6>[ 1.021323] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10540 12:41:17.000963 <6>[ 1.029381] printk: console [ttyS0] disabled
10541 12:41:17.029351 <6>[ 1.054013] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10542 12:41:17.035938 <6>[ 1.063488] printk: console [ttyS0] enabled
10543 12:41:17.039260 <6>[ 1.063488] printk: console [ttyS0] enabled
10544 12:41:17.045603 <6>[ 1.072382] printk: bootconsole [mtk8250] disabled
10545 12:41:17.048620 <6>[ 1.072382] printk: bootconsole [mtk8250] disabled
10546 12:41:17.055496 <6>[ 1.083526] SuperH (H)SCI(F) driver initialized
10547 12:41:17.058685 <6>[ 1.088844] msm_serial: driver initialized
10548 12:41:17.072673 <6>[ 1.097944] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10549 12:41:17.082492 <6>[ 1.106490] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10550 12:41:17.089691 <6>[ 1.115032] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10551 12:41:17.099325 <6>[ 1.123661] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10552 12:41:17.106115 <6>[ 1.132368] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10553 12:41:17.116324 <6>[ 1.141084] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10554 12:41:17.126174 <6>[ 1.149625] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10555 12:41:17.132852 <6>[ 1.158415] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10556 12:41:17.142524 <6>[ 1.166961] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10557 12:41:17.153909 <6>[ 1.182582] loop: module loaded
10558 12:41:17.160636 <6>[ 1.188594] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10559 12:41:17.183461 <4>[ 1.211883] mtk-pmic-keys: Failed to locate of_node [id: -1]
10560 12:41:17.190432 <6>[ 1.218662] megasas: 07.719.03.00-rc1
10561 12:41:17.200088 <6>[ 1.228304] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10562 12:41:17.209832 <6>[ 1.237892] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10563 12:41:17.225560 <6>[ 1.253889] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10564 12:41:17.282676 <6>[ 1.304054] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10565 12:41:18.356967 <6>[ 2.385770] Freeing initrd memory: 38432K
10566 12:41:18.367484 <6>[ 2.396260] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10567 12:41:18.378587 <6>[ 2.407189] tun: Universal TUN/TAP device driver, 1.6
10568 12:41:18.381825 <6>[ 2.413276] thunder_xcv, ver 1.0
10569 12:41:18.385119 <6>[ 2.416781] thunder_bgx, ver 1.0
10570 12:41:18.388413 <6>[ 2.420278] nicpf, ver 1.0
10571 12:41:18.399019 <6>[ 2.424329] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10572 12:41:18.402457 <6>[ 2.431804] hns3: Copyright (c) 2017 Huawei Corporation.
10573 12:41:18.409258 <6>[ 2.437390] hclge is initializing
10574 12:41:18.412504 <6>[ 2.440964] e1000: Intel(R) PRO/1000 Network Driver
10575 12:41:18.418580 <6>[ 2.446092] e1000: Copyright (c) 1999-2006 Intel Corporation.
10576 12:41:18.422019 <6>[ 2.452105] e1000e: Intel(R) PRO/1000 Network Driver
10577 12:41:18.428504 <6>[ 2.457320] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10578 12:41:18.435408 <6>[ 2.463510] igb: Intel(R) Gigabit Ethernet Network Driver
10579 12:41:18.442395 <6>[ 2.469161] igb: Copyright (c) 2007-2014 Intel Corporation.
10580 12:41:18.449111 <6>[ 2.474996] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10581 12:41:18.455416 <6>[ 2.481513] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10582 12:41:18.458840 <6>[ 2.487981] sky2: driver version 1.30
10583 12:41:18.465126 <6>[ 2.493009] VFIO - User Level meta-driver version: 0.3
10584 12:41:18.472689 <6>[ 2.501342] usbcore: registered new interface driver usb-storage
10585 12:41:18.479334 <6>[ 2.507795] usbcore: registered new device driver onboard-usb-hub
10586 12:41:18.488613 <6>[ 2.517001] mt6397-rtc mt6359-rtc: registered as rtc0
10587 12:41:18.498568 <6>[ 2.522470] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-05T12:38:38 UTC (1707136718)
10588 12:41:18.502388 <6>[ 2.532060] i2c_dev: i2c /dev entries driver
10589 12:41:18.518932 <6>[ 2.544085] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10590 12:41:18.538724 <6>[ 2.567091] cpu cpu0: EM: created perf domain
10591 12:41:18.541927 <6>[ 2.572023] cpu cpu4: EM: created perf domain
10592 12:41:18.549039 <6>[ 2.577658] sdhci: Secure Digital Host Controller Interface driver
10593 12:41:18.556087 <6>[ 2.584092] sdhci: Copyright(c) Pierre Ossman
10594 12:41:18.562128 <6>[ 2.589060] Synopsys Designware Multimedia Card Interface Driver
10595 12:41:18.569071 <6>[ 2.595707] sdhci-pltfm: SDHCI platform and OF driver helper
10596 12:41:18.572434 <6>[ 2.595749] mmc0: CQHCI version 5.10
10597 12:41:18.579351 <6>[ 2.605620] ledtrig-cpu: registered to indicate activity on CPUs
10598 12:41:18.585566 <6>[ 2.612613] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10599 12:41:18.592271 <6>[ 2.619671] usbcore: registered new interface driver usbhid
10600 12:41:18.595478 <6>[ 2.625492] usbhid: USB HID core driver
10601 12:41:18.602378 <6>[ 2.629685] spi_master spi0: will run message pump with realtime priority
10602 12:41:18.650886 <6>[ 2.672681] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10603 12:41:18.669906 <6>[ 2.688091] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10604 12:41:18.673199 <6>[ 2.702799] mmc0: Command Queue Engine enabled
10605 12:41:18.680219 <6>[ 2.703026] cros-ec-spi spi0.0: Chrome EC device registered
10606 12:41:18.686830 <6>[ 2.707536] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10607 12:41:18.693255 <6>[ 2.720650] mmcblk0: mmc0:0001 DA4128 116 GiB
10608 12:41:18.703481 <6>[ 2.727115] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10609 12:41:18.709792 <6>[ 2.733427] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10610 12:41:18.713072 <6>[ 2.737577] NET: Registered PF_PACKET protocol family
10611 12:41:18.719794 <6>[ 2.743655] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10612 12:41:18.723027 <6>[ 2.747719] 9pnet: Installing 9P2000 support
10613 12:41:18.729892 <6>[ 2.753469] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10614 12:41:18.733008 <5>[ 2.757421] Key type dns_resolver registered
10615 12:41:18.739579 <6>[ 2.763253] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10616 12:41:18.743023 <6>[ 2.767377] registered taskstats version 1
10617 12:41:18.749273 <5>[ 2.778020] Loading compiled-in X.509 certificates
10618 12:41:18.777234 <4>[ 2.799223] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10619 12:41:18.787344 <4>[ 2.809942] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10620 12:41:18.793579 <3>[ 2.820474] debugfs: File 'uA_load' in directory '/' already present!
10621 12:41:18.800600 <3>[ 2.827172] debugfs: File 'min_uV' in directory '/' already present!
10622 12:41:18.807297 <3>[ 2.833780] debugfs: File 'max_uV' in directory '/' already present!
10623 12:41:18.813585 <3>[ 2.840442] debugfs: File 'constraint_flags' in directory '/' already present!
10624 12:41:18.824510 <3>[ 2.849832] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10625 12:41:18.833878 <6>[ 2.862803] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10626 12:41:18.841177 <6>[ 2.869594] xhci-mtk 11200000.usb: xHCI Host Controller
10627 12:41:18.847795 <6>[ 2.875096] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10628 12:41:18.857501 <6>[ 2.882962] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10629 12:41:18.864355 <6>[ 2.892381] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10630 12:41:18.871101 <6>[ 2.898460] xhci-mtk 11200000.usb: xHCI Host Controller
10631 12:41:18.877502 <6>[ 2.903939] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10632 12:41:18.884276 <6>[ 2.911588] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10633 12:41:18.890915 <6>[ 2.919298] hub 1-0:1.0: USB hub found
10634 12:41:18.893979 <6>[ 2.923309] hub 1-0:1.0: 1 port detected
10635 12:41:18.900801 <6>[ 2.927585] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10636 12:41:18.907809 <6>[ 2.936189] hub 2-0:1.0: USB hub found
10637 12:41:18.911124 <6>[ 2.940196] hub 2-0:1.0: 1 port detected
10638 12:41:18.919357 <6>[ 2.948264] mtk-msdc 11f70000.mmc: Got CD GPIO
10639 12:41:18.931672 <6>[ 2.956710] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10640 12:41:18.937740 <6>[ 2.964730] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10641 12:41:18.947745 <4>[ 2.972633] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10642 12:41:18.958115 <6>[ 2.982165] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10643 12:41:18.964474 <6>[ 2.990243] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10644 12:41:18.971329 <6>[ 2.998327] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10645 12:41:18.981403 <6>[ 3.006248] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10646 12:41:18.987445 <6>[ 3.014066] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10647 12:41:18.997912 <6>[ 3.021883] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10648 12:41:19.007671 <6>[ 3.032290] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10649 12:41:19.014038 <6>[ 3.040652] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10650 12:41:19.023998 <6>[ 3.048993] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10651 12:41:19.031028 <6>[ 3.057336] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10652 12:41:19.041035 <6>[ 3.065675] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10653 12:41:19.047694 <6>[ 3.074014] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10654 12:41:19.057257 <6>[ 3.082366] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10655 12:41:19.063913 <6>[ 3.090705] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10656 12:41:19.074040 <6>[ 3.099044] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10657 12:41:19.080314 <6>[ 3.107383] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10658 12:41:19.090382 <6>[ 3.115722] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10659 12:41:19.100277 <6>[ 3.124061] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10660 12:41:19.107273 <6>[ 3.132399] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10661 12:41:19.117109 <6>[ 3.140738] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10662 12:41:19.123939 <6>[ 3.149078] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10663 12:41:19.130024 <6>[ 3.157891] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10664 12:41:19.136882 <6>[ 3.165192] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10665 12:41:19.146322 <6>[ 3.172120] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10666 12:41:19.153221 <6>[ 3.179002] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10667 12:41:19.160022 <6>[ 3.186047] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10668 12:41:19.169881 <6>[ 3.192943] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10669 12:41:19.176068 <6>[ 3.202073] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10670 12:41:19.186213 <6>[ 3.211192] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10671 12:41:19.196519 <6>[ 3.220489] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10672 12:41:19.205939 <6>[ 3.229957] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10673 12:41:19.216217 <6>[ 3.239424] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10674 12:41:19.226335 <6>[ 3.248565] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10675 12:41:19.232913 <6>[ 3.258035] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10676 12:41:19.242610 <6>[ 3.267153] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10677 12:41:19.252697 <6>[ 3.276446] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10678 12:41:19.262851 <6>[ 3.286606] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10679 12:41:19.273401 <6>[ 3.298680] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10680 12:41:19.305400 <6>[ 3.330838] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10681 12:41:19.334003 <6>[ 3.362316] hub 2-1:1.0: USB hub found
10682 12:41:19.337366 <6>[ 3.366782] hub 2-1:1.0: 3 ports detected
10683 12:41:19.345338 <6>[ 3.374144] hub 2-1:1.0: USB hub found
10684 12:41:19.348880 <6>[ 3.378474] hub 2-1:1.0: 3 ports detected
10685 12:41:19.457340 <6>[ 3.482783] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10686 12:41:19.611871 <6>[ 3.640724] hub 1-1:1.0: USB hub found
10687 12:41:19.615131 <6>[ 3.645159] hub 1-1:1.0: 4 ports detected
10688 12:41:19.624807 <6>[ 3.653112] hub 1-1:1.0: USB hub found
10689 12:41:19.627443 <6>[ 3.657593] hub 1-1:1.0: 4 ports detected
10690 12:41:19.697809 <6>[ 3.722876] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10691 12:41:19.949244 <6>[ 3.974871] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10692 12:41:20.081799 <6>[ 4.110408] hub 1-1.4:1.0: USB hub found
10693 12:41:20.085139 <6>[ 4.115146] hub 1-1.4:1.0: 2 ports detected
10694 12:41:20.094790 <6>[ 4.123303] hub 1-1.4:1.0: USB hub found
10695 12:41:20.097577 <6>[ 4.127891] hub 1-1.4:1.0: 2 ports detected
10696 12:41:20.397127 <6>[ 4.422806] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10697 12:41:20.589436 <6>[ 4.614805] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10698 12:41:31.567144 <6>[ 15.599828] ALSA device list:
10699 12:41:31.573369 <6>[ 15.603125] No soundcards found.
10700 12:41:31.581791 <6>[ 15.611140] Freeing unused kernel memory: 8448K
10701 12:41:31.584559 <6>[ 15.616125] Run /init as init process
10702 12:41:31.633481 <6>[ 15.663115] NET: Registered PF_INET6 protocol family
10703 12:41:31.639977 <6>[ 15.669648] Segment Routing with IPv6
10704 12:41:31.643333 <6>[ 15.673603] In-situ OAM (IOAM) with IPv6
10705 12:41:31.674429 <30>[ 15.687442] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10706 12:41:31.681919 <30>[ 15.711206] systemd[1]: Detected architecture arm64.
10707 12:41:31.682341
10708 12:41:31.688271 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10709 12:41:31.688846
10710 12:41:31.701174 <30>[ 15.730817] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10711 12:41:31.844046 <30>[ 15.870394] systemd[1]: Queued start job for default target Graphical Interface.
10712 12:41:31.877967 <30>[ 15.907586] systemd[1]: Created slice system-getty.slice.
10713 12:41:31.884393 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10714 12:41:31.901201 <30>[ 15.931145] systemd[1]: Created slice system-modprobe.slice.
10715 12:41:31.908322 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10716 12:41:31.925617 <30>[ 15.955362] systemd[1]: Created slice system-serial\x2dgetty.slice.
10717 12:41:31.936045 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10718 12:41:31.949872 <30>[ 15.979298] systemd[1]: Created slice User and Session Slice.
10719 12:41:31.956265 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10720 12:41:31.976595 <30>[ 16.003388] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10721 12:41:31.986375 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10722 12:41:32.004531 <30>[ 16.031377] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10723 12:41:32.011462 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10724 12:41:32.031591 <30>[ 16.054840] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10725 12:41:32.038660 <30>[ 16.066972] systemd[1]: Reached target Local Encrypted Volumes.
10726 12:41:32.044825 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10727 12:41:32.061755 <30>[ 16.091361] systemd[1]: Reached target Paths.
10728 12:41:32.068269 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10729 12:41:32.081312 <30>[ 16.110785] systemd[1]: Reached target Remote File Systems.
10730 12:41:32.087438 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10731 12:41:32.105763 <30>[ 16.135195] systemd[1]: Reached target Slices.
10732 12:41:32.112088 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10733 12:41:32.125528 <30>[ 16.154825] systemd[1]: Reached target Swap.
10734 12:41:32.128161 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10735 12:41:32.148966 <30>[ 16.175311] systemd[1]: Listening on initctl Compatibility Named Pipe.
10736 12:41:32.155862 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10737 12:41:32.162307 <30>[ 16.190535] systemd[1]: Listening on Journal Audit Socket.
10738 12:41:32.168739 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10739 12:41:32.181900 <30>[ 16.211284] systemd[1]: Listening on Journal Socket (/dev/log).
10740 12:41:32.188138 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10741 12:41:32.206261 <30>[ 16.236034] systemd[1]: Listening on Journal Socket.
10742 12:41:32.212727 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10743 12:41:32.225870 <30>[ 16.255499] systemd[1]: Listening on Network Service Netlink Socket.
10744 12:41:32.236256 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10745 12:41:32.249835 <30>[ 16.279351] systemd[1]: Listening on udev Control Socket.
10746 12:41:32.256036 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10747 12:41:32.274609 <30>[ 16.303888] systemd[1]: Listening on udev Kernel Socket.
10748 12:41:32.280650 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10749 12:41:32.333474 <30>[ 16.362839] systemd[1]: Mounting Huge Pages File System...
10750 12:41:32.339848 Mounting [0;1;39mHuge Pages File System[0m...
10751 12:41:32.355796 <30>[ 16.385319] systemd[1]: Mounting POSIX Message Queue File System...
10752 12:41:32.362753 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10753 12:41:32.379224 <30>[ 16.408645] systemd[1]: Mounting Kernel Debug File System...
10754 12:41:32.385284 Mounting [0;1;39mKernel Debug File System[0m...
10755 12:41:32.404583 <30>[ 16.430952] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10756 12:41:32.415775 <30>[ 16.441958] systemd[1]: Starting Create list of static device nodes for the current kernel...
10757 12:41:32.422076 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10758 12:41:32.439327 <30>[ 16.468966] systemd[1]: Starting Load Kernel Module configfs...
10759 12:41:32.445622 Starting [0;1;39mLoad Kernel Module configfs[0m...
10760 12:41:32.465535 <30>[ 16.495295] systemd[1]: Starting Load Kernel Module drm...
10761 12:41:32.472375 Starting [0;1;39mLoad Kernel Module drm[0m...
10762 12:41:32.488897 <30>[ 16.515178] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10763 12:41:32.502634 <30>[ 16.532361] systemd[1]: Starting Journal Service...
10764 12:41:32.506165 Starting [0;1;39mJournal Service[0m...
10765 12:41:32.530679 <30>[ 16.560336] systemd[1]: Starting Load Kernel Modules...
10766 12:41:32.537215 Starting [0;1;39mLoad Kernel Modules[0m...
10767 12:41:32.560987 <30>[ 16.587443] systemd[1]: Starting Remount Root and Kernel File Systems...
10768 12:41:32.567832 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10769 12:41:32.583776 <30>[ 16.613713] systemd[1]: Starting Coldplug All udev Devices...
10770 12:41:32.590386 Starting [0;1;39mColdplug All udev Devices[0m...
10771 12:41:32.607736 <30>[ 16.637562] systemd[1]: Started Journal Service.
10772 12:41:32.614685 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10773 12:41:32.635732 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10774 12:41:32.654255 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10775 12:41:32.669532 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10776 12:41:32.690421 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10777 12:41:32.712470 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10778 12:41:32.735700 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10779 12:41:32.758981 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10780 12:41:32.783558 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10781 12:41:32.796870 See 'systemctl status systemd-remount-fs.service' for details.
10782 12:41:32.853943 Mounting [0;1;39mKernel Configuration File System[0m...
10783 12:41:32.875662 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10784 12:41:32.894095 <46>[ 16.920472] systemd-journald[178]: Received client request to flush runtime journal.
10785 12:41:32.938872 Starting [0;1;39mLoad/Save Random Seed[0m...
10786 12:41:32.957468 Starting [0;1;39mApply Kernel Variables[0m...
10787 12:41:32.975810 Starting [0;1;39mCreate System Users[0m...
10788 12:41:32.998265 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10789 12:41:33.017784 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10790 12:41:33.042057 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10791 12:41:33.058538 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10792 12:41:33.074779 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10793 12:41:33.094171 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10794 12:41:33.149553 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10795 12:41:33.172943 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10796 12:41:33.184832 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10797 12:41:33.200358 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10798 12:41:33.253180 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10799 12:41:33.280646 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10800 12:41:33.299221 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10801 12:41:33.318421 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10802 12:41:33.371016 Starting [0;1;39mNetwork Service[0m...
10803 12:41:33.394292 Starting [0;1;39mNetwork Time Synchronization[0m...
10804 12:41:33.418692 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10805 12:41:33.462334 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10806 12:41:33.477442 <6>[ 17.504539] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10807 12:41:33.485053 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10808 12:41:33.507070 <3>[ 17.534152] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10809 12:41:33.513724 <6>[ 17.536053] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10810 12:41:33.524000 <3>[ 17.542941] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10811 12:41:33.530291 <6>[ 17.550064] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10812 12:41:33.537405 <6>[ 17.552895] remoteproc remoteproc0: scp is available
10813 12:41:33.540689 <6>[ 17.553010] remoteproc remoteproc0: powering up scp
10814 12:41:33.550294 <6>[ 17.553018] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10815 12:41:33.556968 <6>[ 17.553048] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10816 12:41:33.563921 <3>[ 17.558235] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10817 12:41:33.573578 <6>[ 17.566711] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10818 12:41:33.580577 <3>[ 17.572468] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10819 12:41:33.587104 <4>[ 17.606767] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10820 12:41:33.596895 <3>[ 17.607939] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10821 12:41:33.600469 <6>[ 17.611169] mc: Linux media interface: v0.10
10822 12:41:33.606997 <6>[ 17.616299] usbcore: registered new device driver r8152-cfgselector
10823 12:41:33.616855 <3>[ 17.623316] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10824 12:41:33.623147 <3>[ 17.623325] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10825 12:41:33.630137 <4>[ 17.626681] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10826 12:41:33.636916 <6>[ 17.653960] videodev: Linux video capture interface: v2.00
10827 12:41:33.643319 <3>[ 17.658619] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10828 12:41:33.653259 <6>[ 17.678454] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10829 12:41:33.659635 <6>[ 17.678454] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10830 12:41:33.669709 <3>[ 17.680025] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10831 12:41:33.676654 <6>[ 17.680258] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10832 12:41:33.682883 <6>[ 17.688306] remoteproc remoteproc0: remote processor scp is now up
10833 12:41:33.689574 <3>[ 17.695456] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10834 12:41:33.699248 <3>[ 17.695467] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10835 12:41:33.706443 <3>[ 17.695471] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10836 12:41:33.716114 <3>[ 17.695869] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10837 12:41:33.722521 <6>[ 17.696061] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10838 12:41:33.725932 <6>[ 17.696069] pci_bus 0000:00: root bus resource [bus 00-ff]
10839 12:41:33.736076 <6>[ 17.696110] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10840 12:41:33.746080 <6>[ 17.696118] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10841 12:41:33.749439 <6>[ 17.696187] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10842 12:41:33.759767 <6>[ 17.696210] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10843 12:41:33.763190 <6>[ 17.696310] pci 0000:00:00.0: supports D1 D2
10844 12:41:33.769220 <6>[ 17.696316] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10845 12:41:33.779415 <6>[ 17.700102] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10846 12:41:33.782906 <6>[ 17.700969] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10847 12:41:33.792721 <6>[ 17.701006] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10848 12:41:33.799513 <6>[ 17.701024] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10849 12:41:33.805953 <6>[ 17.701039] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10850 12:41:33.813052 <6>[ 17.701196] pci 0000:01:00.0: supports D1 D2
10851 12:41:33.819358 <6>[ 17.701198] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10852 12:41:33.825927 <6>[ 17.714704] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10853 12:41:33.832590 <3>[ 17.717886] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10854 12:41:33.843567 <6>[ 17.725951] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10855 12:41:33.849390 <3>[ 17.734048] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10856 12:41:33.859257 <6>[ 17.743018] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10857 12:41:33.865848 <3>[ 17.750214] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10858 12:41:33.876248 <6>[ 17.750583] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10859 12:41:33.882949 <6>[ 17.757085] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10860 12:41:33.893009 <6>[ 17.759201] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10861 12:41:33.899995 <3>[ 17.762830] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10862 12:41:33.910723 <6>[ 17.763387] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10863 12:41:33.917847 <6>[ 17.766099] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10864 12:41:33.927517 <6>[ 17.769959] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10865 12:41:33.933759 <3>[ 17.789320] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10866 12:41:33.944333 <4>[ 17.790924] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10867 12:41:33.951592 <4>[ 17.790936] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10868 12:41:33.958813 <6>[ 17.793616] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10869 12:41:33.965965 <6>[ 17.794281] Bluetooth: Core ver 2.22
10870 12:41:33.968690 <6>[ 17.794340] NET: Registered PF_BLUETOOTH protocol family
10871 12:41:33.975320 <6>[ 17.794342] Bluetooth: HCI device and connection manager initialized
10872 12:41:33.982414 <6>[ 17.794357] Bluetooth: HCI socket layer initialized
10873 12:41:33.985711 <6>[ 17.794361] Bluetooth: L2CAP socket layer initialized
10874 12:41:33.992349 <6>[ 17.794373] Bluetooth: SCO socket layer initialized
10875 12:41:33.998305 <6>[ 17.800398] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10876 12:41:34.005152 <6>[ 17.805023] pci 0000:00:00.0: PCI bridge to [bus 01]
10877 12:41:34.012269 <6>[ 17.805030] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10878 12:41:34.022013 <6>[ 17.816852] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10879 12:41:34.028354 <6>[ 17.819747] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10880 12:41:34.031803 <6>[ 17.829292] usbcore: registered new interface driver btusb
10881 12:41:34.038760 <6>[ 17.835165] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10882 12:41:34.051574 <4>[ 17.835463] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10883 12:41:34.054889 <3>[ 17.835478] Bluetooth: hci0: Failed to load firmware file (-2)
10884 12:41:34.061566 <3>[ 17.835483] Bluetooth: hci0: Failed to set up firmware (-2)
10885 12:41:34.071556 <4>[ 17.835486] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10886 12:41:34.077714 <6>[ 17.835591] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10887 12:41:34.091777 <6>[ 17.837022] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10888 12:41:34.097734 <6>[ 17.837152] usbcore: registered new interface driver uvcvideo
10889 12:41:34.100927 <6>[ 17.844100] r8152 2-1.3:1.0 eth0: v1.12.13
10890 12:41:34.107551 <6>[ 17.847605] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10891 12:41:34.114187 <6>[ 17.853751] usbcore: registered new interface driver r8152
10892 12:41:34.121434 <6>[ 17.854321] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10893 12:41:34.127736 <4>[ 17.863658] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10894 12:41:34.134777 <4>[ 17.863658] Fallback method does not support PEC.
10895 12:41:34.141128 <5>[ 17.879364] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10896 12:41:34.147977 <6>[ 17.893038] usbcore: registered new interface driver cdc_ether
10897 12:41:34.154076 <5>[ 17.911913] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10898 12:41:34.160963 <6>[ 17.928550] usbcore: registered new interface driver r8153_ecm
10899 12:41:34.170623 <5>[ 17.936747] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10900 12:41:34.177611 <3>[ 17.939064] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10901 12:41:34.187142 <3>[ 17.941557] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10902 12:41:34.193943 <3>[ 17.951465] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 12:41:34.203580 <4>[ 17.953883] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10904 12:41:34.210365 <6>[ 17.957058] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10905 12:41:34.220612 <3>[ 17.989632] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 12:41:34.226862 <3>[ 17.990337] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10907 12:41:34.233144 <6>[ 17.994981] cfg80211: failed to load regulatory.db
10908 12:41:34.240206 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10909 12:41:34.263293 <3>[ 18.289500] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10910 12:41:34.269235 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10911 12:41:34.281925 <6>[ 18.307905] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10912 12:41:34.285399 <6>[ 18.315419] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10913 12:41:34.296017 <3>[ 18.322762] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 12:41:34.308468 <6>[ 18.338752] mt7921e 0000:01:00.0: ASIC revision: 79610010
10915 12:41:34.326982 <3>[ 18.353729] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 12:41:34.356052 <3>[ 18.383217] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10917 12:41:34.390118 <3>[ 18.416824] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 12:41:34.425284 [[0;32m OK [<6>[ 18.452044] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10919 12:41:34.428656 <6>[ 18.452044]
10920 12:41:34.435087 0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10921 12:41:34.449128 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10922 12:41:34.464661 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10923 12:41:34.481092 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10924 12:41:34.500639 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10925 12:41:34.552688 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10926 12:41:34.576245 Starting [0;1;39mNetwork Name Resolution[0m...
10927 12:41:34.598588 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10928 12:41:34.613687 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10929 12:41:34.631890 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10930 12:41:34.652443 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10931 12:41:34.664964 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10932 12:41:34.685115 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10933 12:41:34.697370 <6>[ 18.723694] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10934 12:41:34.704078 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10935 12:41:34.717420 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10936 12:41:34.782123 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10937 12:41:34.841561 Starting [0;1;39mUser Login Management[0m...
10938 12:41:34.860066 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10939 12:41:34.877890 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10940 12:41:34.893583 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10941 12:41:34.910165 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10942 12:41:34.928173 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10943 12:41:34.981511 Starting [0;1;39mPermit User Sessions[0m...
10944 12:41:34.999115 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10945 12:41:35.019484 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10946 12:41:35.074706 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10947 12:41:35.094840 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10948 12:41:35.109688 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10949 12:41:35.125765 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10950 12:41:35.141089 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10951 12:41:35.177374 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10952 12:41:35.212786 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10953 12:41:35.245820
10954 12:41:35.246314
10955 12:41:35.249302 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10956 12:41:35.249905
10957 12:41:35.252676 debian-bullseye-arm64 login: root (automatic login)
10958 12:41:35.253258
10959 12:41:35.253792
10960 12:41:35.269870 Linux debian-bullseye-arm64 6.1.75-cip14 #1 SMP PREEMPT Mon Feb 5 12:20:06 UTC 2024 aarch64
10961 12:41:35.270439
10962 12:41:35.276923 The programs included with the Debian GNU/Linux system are free software;
10963 12:41:35.283217 the exact distribution terms for each program are described in the
10964 12:41:35.286383 individual files in /usr/share/doc/*/copyright.
10965 12:41:35.287012
10966 12:41:35.293269 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10967 12:41:35.296735 permitted by applicable law.
10968 12:41:35.298055 Matched prompt #10: / #
10970 12:41:35.299493 Setting prompt string to ['/ #']
10971 12:41:35.300201 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10973 12:41:35.301893 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10974 12:41:35.302480 start: 2.2.6 expect-shell-connection (timeout 00:03:32) [common]
10975 12:41:35.302977 Setting prompt string to ['/ #']
10976 12:41:35.303420 Forcing a shell prompt, looking for ['/ #']
10978 12:41:35.354243 / #
10979 12:41:35.354801 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10980 12:41:35.355248 Waiting using forced prompt support (timeout 00:02:30)
10981 12:41:35.360744
10982 12:41:35.361597 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10983 12:41:35.362106 start: 2.2.7 export-device-env (timeout 00:03:32) [common]
10984 12:41:35.362560 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10985 12:41:35.362991 end: 2.2 depthcharge-retry (duration 00:01:28) [common]
10986 12:41:35.363405 end: 2 depthcharge-action (duration 00:01:28) [common]
10987 12:41:35.363914 start: 3 lava-test-retry (timeout 00:08:11) [common]
10988 12:41:35.364557 start: 3.1 lava-test-shell (timeout 00:08:11) [common]
10989 12:41:35.364953 Using namespace: common
10991 12:41:35.465949 / # #
10992 12:41:35.466527 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10993 12:41:35.467086 <6>[ 19.436652] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c787aaa: link becomes ready
10994 12:41:35.467574 <6>[ 19.444694] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10995 12:41:35.472404 #
10996 12:41:35.473193 Using /lava-12703534
10998 12:41:35.574117 / # export SHELL=/bin/sh
10999 12:41:35.574287 export SHELL=/bin/sh<6>[ 19.582218] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11000 12:41:35.579281
11002 12:41:35.679802 / # . /lava-12703534/environment
11003 12:41:35.685112 . /lava-12703534/environment
11005 12:41:35.785868 / # /lava-12703534/bin/lava-test-runner /lava-12703534/0
11006 12:41:35.786594 Test shell timeout: 10s (minimum of the action and connection timeout)
11007 12:41:35.792127 /lava-12703534/bin/lava-test-runner /lava-12703534/0
11008 12:41:35.814140 + export TESTRUN_ID=0_v4l2-compliance-uvc
11009 12:41:35.817289 + cd /lava-12703534/0/tests/0_v4l2-compliance-uvc
11010 12:41:35.817371 + cat uuid
11011 12:41:35.820412 + UUID=12703534_1.5.2.3.1
11012 12:41:35.820492 + set +x
11013 12:41:35.826922 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 12703534_1.5.2.3.1>
11014 12:41:35.827181 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 12703534_1.5.2.3.1
11015 12:41:35.827256 Starting test lava.0_v4l2-compliance-uvc (12703534_1.5.2.3.1)
11016 12:41:35.827345 Skipping test definition patterns.
11017 12:41:35.830884 + /usr/bin/v4l2-parser.sh -d uvcvideo
11018 12:41:35.836983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11019 12:41:35.837063 device: /dev/video0
11020 12:41:35.837295 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11022 12:41:42.329449 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11023 12:41:42.342465 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11024 12:41:42.351337
11025 12:41:42.367724 Compliance test for uvcvideo device /dev/video0:
11026 12:41:42.376816
11027 12:41:42.386573 Driver Info:
11028 12:41:42.396911 Driver name : uvcvideo
11029 12:41:42.411801 Card type : HD User Facing: HD User Facing
11030 12:41:42.422426 Bus info : usb-11200000.usb-1.4.1
11031 12:41:42.430692 Driver version : 6.1.75
11032 12:41:42.444485 Capabilities : 0x84a00001
11033 12:41:42.461135 Metadata Capture
11034 12:41:42.472642 Streaming
11035 12:41:42.483278 Extended Pix Format
11036 12:41:42.494197 Device Capabilities
11037 12:41:42.507623 Device Caps : 0x04200001
11038 12:41:42.523110 Streaming
11039 12:41:42.537757 Extended Pix Format
11040 12:41:42.548862 Media Driver Info:
11041 12:41:42.563792 Driver name : uvcvideo
11042 12:41:42.577907 Model : HD User Facing: HD User Facing
11043 12:41:42.585827 Serial : 200901010001
11044 12:41:42.603172 Bus info : usb-11200000.usb-1.4.1
11045 12:41:42.611946 Media version : 6.1.75
11046 12:41:42.625638 Hardware revision: 0x00009758 (38744)
11047 12:41:42.633292 Driver version : 6.1.75
11048 12:41:42.647502 Interface Info:
11049 12:41:42.665238 <LAVA_SIGNAL_TESTSET START Interface-Info>
11050 12:41:42.665357 ID : 0x03000002
11051 12:41:42.665599 Received signal: <TESTSET> START Interface-Info
11052 12:41:42.665670 Starting test_set Interface-Info
11053 12:41:42.674312 Type : V4L Video
11054 12:41:42.685847 Entity Info:
11055 12:41:42.693754 <LAVA_SIGNAL_TESTSET STOP>
11056 12:41:42.694003 Received signal: <TESTSET> STOP
11057 12:41:42.694072 Closing test_set Interface-Info
11058 12:41:42.706818 <LAVA_SIGNAL_TESTSET START Entity-Info>
11059 12:41:42.707087 Received signal: <TESTSET> START Entity-Info
11060 12:41:42.707165 Starting test_set Entity-Info
11061 12:41:42.709617 ID : 0x00000001 (1)
11062 12:41:42.720831 Name : HD User Facing: HD User Facing
11063 12:41:42.727909 Function : V4L2 I/O
11064 12:41:42.739037 Flags : default
11065 12:41:42.748006 Pad 0x01000007 : 0: Sink
11066 12:41:42.768621 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11067 12:41:42.772841
11068 12:41:42.786120 Required ioctls:
11069 12:41:42.796065 <LAVA_SIGNAL_TESTSET STOP>
11070 12:41:42.796690 Received signal: <TESTSET> STOP
11071 12:41:42.796938 Closing test_set Entity-Info
11072 12:41:42.807266 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11073 12:41:42.808196 Received signal: <TESTSET> START Required-ioctls
11074 12:41:42.808976 Starting test_set Required-ioctls
11075 12:41:42.810650 test MC information (see 'Media Driver Info' above): OK
11076 12:41:42.836825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11077 12:41:42.837740 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11079 12:41:42.839680 test VIDIOC_QUERYCAP: OK
11080 12:41:42.862389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11081 12:41:42.863095 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11083 12:41:42.865883 test invalid ioctls: OK
11084 12:41:42.893047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11085 12:41:42.893354
11086 12:41:42.893808 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11088 12:41:42.904969 Allow for multiple opens:
11089 12:41:42.911164 <LAVA_SIGNAL_TESTSET STOP>
11090 12:41:42.911675 Received signal: <TESTSET> STOP
11091 12:41:42.911914 Closing test_set Required-ioctls
11092 12:41:42.921041 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11093 12:41:42.921557 Received signal: <TESTSET> START Allow-for-multiple-opens
11094 12:41:42.921800 Starting test_set Allow-for-multiple-opens
11095 12:41:42.924271 test second /dev/video0 open: OK
11096 12:41:42.949718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11097 12:41:42.950274 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11099 12:41:42.952669 test VIDIOC_QUERYCAP: OK
11100 12:41:42.975853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11101 12:41:42.976503 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11103 12:41:42.979468 test VIDIOC_G/S_PRIORITY: OK
11104 12:41:43.000316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11105 12:41:43.000899 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11107 12:41:43.003763 test for unlimited opens: OK
11108 12:41:43.032799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11109 12:41:43.033182
11110 12:41:43.033724 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11112 12:41:43.043140 Debug ioctls:
11113 12:41:43.053829 <LAVA_SIGNAL_TESTSET STOP>
11114 12:41:43.054523 Received signal: <TESTSET> STOP
11115 12:41:43.054895 Closing test_set Allow-for-multiple-opens
11116 12:41:43.063847 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11117 12:41:43.064511 Received signal: <TESTSET> START Debug-ioctls
11118 12:41:43.064859 Starting test_set Debug-ioctls
11119 12:41:43.067048 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11120 12:41:43.090353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11121 12:41:43.091081 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11123 12:41:43.097015 test VIDIOC_LOG_STATUS: OK (Not Supported)
11124 12:41:43.120661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11125 12:41:43.121144
11126 12:41:43.121829 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11128 12:41:43.130785 Input ioctls:
11129 12:41:43.138612 <LAVA_SIGNAL_TESTSET STOP>
11130 12:41:43.139491 Received signal: <TESTSET> STOP
11131 12:41:43.139945 Closing test_set Debug-ioctls
11132 12:41:43.147588 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11133 12:41:43.148428 Received signal: <TESTSET> START Input-ioctls
11134 12:41:43.148871 Starting test_set Input-ioctls
11135 12:41:43.151063 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11136 12:41:43.177441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11137 12:41:43.178128 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11139 12:41:43.181115 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11140 12:41:43.200914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11141 12:41:43.201602 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11143 12:41:43.207279 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11144 12:41:43.228442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11145 12:41:43.229153 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11147 12:41:43.231453 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11148 12:41:43.252717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11149 12:41:43.253399 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11151 12:41:43.256186 test VIDIOC_G/S/ENUMINPUT: OK
11152 12:41:43.283190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11153 12:41:43.283886 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11155 12:41:43.286565 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11156 12:41:43.309002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11157 12:41:43.309720 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11159 12:41:43.312371 Inputs: 1 Audio Inputs: 0 Tuners: 0
11160 12:41:43.319302
11161 12:41:43.336610 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11162 12:41:43.363453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11163 12:41:43.364338 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11165 12:41:43.370275 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11166 12:41:43.389982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11167 12:41:43.390856 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11169 12:41:43.396356 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11170 12:41:43.415026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11171 12:41:43.415814 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11173 12:41:43.418435 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11174 12:41:43.446531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11175 12:41:43.447422 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11177 12:41:43.453279 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11178 12:41:43.477062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11179 12:41:43.477785 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11181 12:41:43.480004
11182 12:41:43.497721 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11183 12:41:43.519271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11184 12:41:43.519983 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11186 12:41:43.526183 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11187 12:41:43.549193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11188 12:41:43.549774 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11190 12:41:43.551978 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11191 12:41:43.570068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11192 12:41:43.570600 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11194 12:41:43.573257 test VIDIOC_G/S_EDID: OK (Not Supported)
11195 12:41:43.597957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11196 12:41:43.598190
11197 12:41:43.598573 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11199 12:41:43.610780 Control ioctls (Input 0):
11200 12:41:43.618485 <LAVA_SIGNAL_TESTSET STOP>
11201 12:41:43.619001 Received signal: <TESTSET> STOP
11202 12:41:43.619292 Closing test_set Input-ioctls
11203 12:41:43.627949 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11204 12:41:43.628438 Received signal: <TESTSET> START Control-ioctls-Input-0
11205 12:41:43.628669 Starting test_set Control-ioctls-Input-0
11206 12:41:43.631228 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11207 12:41:43.658111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11208 12:41:43.658564 test VIDIOC_QUERYCTRL: OK
11209 12:41:43.659152 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11211 12:41:43.681158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11212 12:41:43.681844 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11214 12:41:43.684691 test VIDIOC_G/S_CTRL: OK
11215 12:41:43.710697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11216 12:41:43.711376 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11218 12:41:43.713222 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11219 12:41:43.740195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11220 12:41:43.740998 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11222 12:41:43.746781 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11223 12:41:43.767416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11224 12:41:43.768111 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11226 12:41:43.770815 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11227 12:41:43.791200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11228 12:41:43.791914 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11230 12:41:43.794384 Standard Controls: 16 Private Controls: 0
11231 12:41:43.802020
11232 12:41:43.818376 Format ioctls (Input 0):
11233 12:41:43.824742 <LAVA_SIGNAL_TESTSET STOP>
11234 12:41:43.825649 Received signal: <TESTSET> STOP
11235 12:41:43.826040 Closing test_set Control-ioctls-Input-0
11236 12:41:43.834563 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11237 12:41:43.835237 Received signal: <TESTSET> START Format-ioctls-Input-0
11238 12:41:43.835588 Starting test_set Format-ioctls-Input-0
11239 12:41:43.837973 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11240 12:41:43.864563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11241 12:41:43.865326 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11243 12:41:43.867595 test VIDIOC_G/S_PARM: OK
11244 12:41:43.889117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11245 12:41:43.889831 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11247 12:41:43.892723 test VIDIOC_G_FBUF: OK (Not Supported)
11248 12:41:43.918443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11249 12:41:43.919177 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11251 12:41:43.921528 test VIDIOC_G_FMT: OK
11252 12:41:43.943786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11253 12:41:43.944474 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11255 12:41:43.947206 test VIDIOC_TRY_FMT: OK
11256 12:41:43.969654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11257 12:41:43.970357 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11259 12:41:43.976404 warn: ../utils/v4l2-compliance/v4l2-test-formats.cpp(1046): Could not set fmt2
11260 12:41:43.983802 test VIDIOC_S_FMT: OK
11261 12:41:44.009255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11262 12:41:44.009933 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11264 12:41:44.012756 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11265 12:41:44.034193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11266 12:41:44.034877 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11268 12:41:44.037427 test Cropping: OK (Not Supported)
11269 12:41:44.065192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11270 12:41:44.065961 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11272 12:41:44.068501 test Composing: OK (Not Supported)
11273 12:41:44.091996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11274 12:41:44.092773 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11276 12:41:44.095443 test Scaling: OK (Not Supported)
11277 12:41:44.124251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11278 12:41:44.124712
11279 12:41:44.125289 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11281 12:41:44.139783 Codec ioctls (Input 0):
11282 12:41:44.147538 <LAVA_SIGNAL_TESTSET STOP>
11283 12:41:44.148431 Received signal: <TESTSET> STOP
11284 12:41:44.148962 Closing test_set Format-ioctls-Input-0
11285 12:41:44.157668 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11286 12:41:44.158331 Received signal: <TESTSET> START Codec-ioctls-Input-0
11287 12:41:44.158679 Starting test_set Codec-ioctls-Input-0
11288 12:41:44.160868 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11289 12:41:44.183010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11290 12:41:44.183706 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11292 12:41:44.189345 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11293 12:41:44.209492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11294 12:41:44.210296 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11296 12:41:44.216361 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11297 12:41:44.236811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11298 12:41:44.237282
11299 12:41:44.237963 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11301 12:41:44.247136 Buffer ioctls (Input 0):
11302 12:41:44.254438 <LAVA_SIGNAL_TESTSET STOP>
11303 12:41:44.255122 Received signal: <TESTSET> STOP
11304 12:41:44.255495 Closing test_set Codec-ioctls-Input-0
11305 12:41:44.263214 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11306 12:41:44.263963 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11307 12:41:44.264362 Starting test_set Buffer-ioctls-Input-0
11308 12:41:44.266629 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11309 12:41:44.291151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11310 12:41:44.291569 test VIDIOC_EXPBUF: OK
11311 12:41:44.292150 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11313 12:41:44.320351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11314 12:41:44.321028 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11316 12:41:44.323691 test Requests: OK (Not Supported)
11317 12:41:44.346311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11318 12:41:44.346723
11319 12:41:44.347299 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11321 12:41:44.358342 Test input 0:
11322 12:41:44.368234
11323 12:41:44.380050 Streaming ioctls:
11324 12:41:44.386343 <LAVA_SIGNAL_TESTSET STOP>
11325 12:41:44.387193 Received signal: <TESTSET> STOP
11326 12:41:44.387698 Closing test_set Buffer-ioctls-Input-0
11327 12:41:44.396123 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11328 12:41:44.396974 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11329 12:41:44.397489 Starting test_set Streaming-ioctls_Test-input-0
11330 12:41:44.399262 test read/write: OK (Not Supported)
11331 12:41:44.420676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11332 12:41:44.421216 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11334 12:41:44.423390 test blocking wait: OK
11335 12:41:44.448636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11336 12:41:44.449155 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11338 12:41:44.458335 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11339 12:41:44.458627 test MMAP (no poll): FAIL
11340 12:41:44.484220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11341 12:41:44.484827 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11343 12:41:44.494236 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11344 12:41:44.497630 test MMAP (select): FAIL
11345 12:41:44.520533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11346 12:41:44.521282 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11348 12:41:44.530321 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11349 12:41:44.530639 test MMAP (epoll): FAIL
11350 12:41:44.556764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11351 12:41:44.556885
11352 12:41:44.557160 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11354 12:41:44.569950
11355 12:41:44.766769
11356 12:41:44.774681 test USERPTR (no poll): OK
11357 12:41:44.799016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11358 12:41:44.799131
11359 12:41:44.799407 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11361 12:41:44.812301
11362 12:41:45.012832
11363 12:41:45.020955 test USERPTR (select): OK
11364 12:41:45.052018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11365 12:41:45.052346 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11367 12:41:45.058862 test DMABUF: Cannot test, specify --expbuf-device
11368 12:41:45.062745
11369 12:41:45.084004 Total for uvcvideo device /dev/video0: 53, Succeeded: 50, Failed: 3, Warnings: 3
11370 12:41:45.088297 <LAVA_TEST_RUNNER EXIT>
11371 12:41:45.088612 ok: lava_test_shell seems to have completed
11372 12:41:45.088710 Marking unfinished test run as failed
11374 12:41:45.090123 Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11375 12:41:45.090320 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11376 12:41:45.090456 end: 3 lava-test-retry (duration 00:00:10) [common]
11377 12:41:45.090584 start: 4 finalize (timeout 00:08:01) [common]
11378 12:41:45.090727 start: 4.1 power-off (timeout 00:00:30) [common]
11379 12:41:45.091089 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11380 12:41:45.168690 >> Command sent successfully.
11381 12:41:45.171348 Returned 0 in 0 seconds
11382 12:41:45.271808 end: 4.1 power-off (duration 00:00:00) [common]
11384 12:41:45.272147 start: 4.2 read-feedback (timeout 00:08:01) [common]
11385 12:41:45.272483 Listened to connection for namespace 'common' for up to 1s
11386 12:41:46.273419 Finalising connection for namespace 'common'
11387 12:41:46.273582 Disconnecting from shell: Finalise
11388 12:41:46.273670 / #
11389 12:41:46.373993 end: 4.2 read-feedback (duration 00:00:01) [common]
11390 12:41:46.374154 end: 4 finalize (duration 00:00:01) [common]
11391 12:41:46.374277 Cleaning after the job
11392 12:41:46.374377 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703534/tftp-deploy-o6tibqjn/ramdisk
11393 12:41:46.380399 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703534/tftp-deploy-o6tibqjn/kernel
11394 12:41:46.396500 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703534/tftp-deploy-o6tibqjn/dtb
11395 12:41:46.396695 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703534/tftp-deploy-o6tibqjn/modules
11396 12:41:46.403633 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12703534
11397 12:41:46.476561 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12703534
11398 12:41:46.476749 Job finished correctly