Boot log: mt8192-asurada-spherion-r0

    1 12:39:58.822594  lava-dispatcher, installed at version: 2024.01
    2 12:39:58.822791  start: 0 validate
    3 12:39:58.822920  Start time: 2024-02-05 12:39:58.822912+00:00 (UTC)
    4 12:39:58.823035  Using caching service: 'http://localhost/cache/?uri=%s'
    5 12:39:58.823203  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
    6 12:39:59.105261  Using caching service: 'http://localhost/cache/?uri=%s'
    7 12:39:59.106047  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
    8 12:39:59.375485  Using caching service: 'http://localhost/cache/?uri=%s'
    9 12:39:59.376225  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
   10 12:39:59.644028  Using caching service: 'http://localhost/cache/?uri=%s'
   11 12:39:59.644805  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
   12 12:39:59.912653  Using caching service: 'http://localhost/cache/?uri=%s'
   13 12:39:59.913433  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
   14 12:40:00.198177  validate duration: 1.38
   16 12:40:00.199378  start: 1 tftp-deploy (timeout 00:10:00) [common]
   17 12:40:00.199921  start: 1.1 download-retry (timeout 00:10:00) [common]
   18 12:40:00.200407  start: 1.1.1 http-download (timeout 00:10:00) [common]
   19 12:40:00.200995  Not decompressing ramdisk as can be used compressed.
   20 12:40:00.201430  downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/initrd.cpio.gz
   21 12:40:00.201799  saving as /var/lib/lava/dispatcher/tmp/12703575/tftp-deploy-50eelh8k/ramdisk/initrd.cpio.gz
   22 12:40:00.202220  total size: 4665412 (4 MB)
   23 12:40:00.207165  progress   0 % (0 MB)
   24 12:40:00.213373  progress   5 % (0 MB)
   25 12:40:00.217664  progress  10 % (0 MB)
   26 12:40:00.221263  progress  15 % (0 MB)
   27 12:40:00.224050  progress  20 % (0 MB)
   28 12:40:00.226823  progress  25 % (1 MB)
   29 12:40:00.229138  progress  30 % (1 MB)
   30 12:40:00.231460  progress  35 % (1 MB)
   31 12:40:00.233585  progress  40 % (1 MB)
   32 12:40:00.235966  progress  45 % (2 MB)
   33 12:40:00.237270  progress  50 % (2 MB)
   34 12:40:00.238597  progress  55 % (2 MB)
   35 12:40:00.239829  progress  60 % (2 MB)
   36 12:40:00.241093  progress  65 % (2 MB)
   37 12:40:00.242430  progress  70 % (3 MB)
   38 12:40:00.243639  progress  75 % (3 MB)
   39 12:40:00.244898  progress  80 % (3 MB)
   40 12:40:00.246365  progress  85 % (3 MB)
   41 12:40:00.247600  progress  90 % (4 MB)
   42 12:40:00.248871  progress  95 % (4 MB)
   43 12:40:00.250154  progress 100 % (4 MB)
   44 12:40:00.250316  4 MB downloaded in 0.05 s (92.47 MB/s)
   45 12:40:00.250467  end: 1.1.1 http-download (duration 00:00:00) [common]
   47 12:40:00.250717  end: 1.1 download-retry (duration 00:00:00) [common]
   48 12:40:00.250803  start: 1.2 download-retry (timeout 00:10:00) [common]
   49 12:40:00.250888  start: 1.2.1 http-download (timeout 00:10:00) [common]
   50 12:40:00.251012  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
   51 12:40:00.251081  saving as /var/lib/lava/dispatcher/tmp/12703575/tftp-deploy-50eelh8k/kernel/Image
   52 12:40:00.251142  total size: 51534336 (49 MB)
   53 12:40:00.251203  No compression specified
   54 12:40:00.252314  progress   0 % (0 MB)
   55 12:40:00.265277  progress   5 % (2 MB)
   56 12:40:00.278417  progress  10 % (4 MB)
   57 12:40:00.291422  progress  15 % (7 MB)
   58 12:40:00.304755  progress  20 % (9 MB)
   59 12:40:00.317998  progress  25 % (12 MB)
   60 12:40:00.330983  progress  30 % (14 MB)
   61 12:40:00.344213  progress  35 % (17 MB)
   62 12:40:00.357410  progress  40 % (19 MB)
   63 12:40:00.370362  progress  45 % (22 MB)
   64 12:40:00.383847  progress  50 % (24 MB)
   65 12:40:00.396775  progress  55 % (27 MB)
   66 12:40:00.409808  progress  60 % (29 MB)
   67 12:40:00.422841  progress  65 % (31 MB)
   68 12:40:00.435831  progress  70 % (34 MB)
   69 12:40:00.449064  progress  75 % (36 MB)
   70 12:40:00.462259  progress  80 % (39 MB)
   71 12:40:00.475176  progress  85 % (41 MB)
   72 12:40:00.488350  progress  90 % (44 MB)
   73 12:40:00.501325  progress  95 % (46 MB)
   74 12:40:00.514008  progress 100 % (49 MB)
   75 12:40:00.514221  49 MB downloaded in 0.26 s (186.82 MB/s)
   76 12:40:00.514372  end: 1.2.1 http-download (duration 00:00:00) [common]
   78 12:40:00.514614  end: 1.2 download-retry (duration 00:00:00) [common]
   79 12:40:00.514704  start: 1.3 download-retry (timeout 00:10:00) [common]
   80 12:40:00.514790  start: 1.3.1 http-download (timeout 00:10:00) [common]
   81 12:40:00.514925  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
   82 12:40:00.514997  saving as /var/lib/lava/dispatcher/tmp/12703575/tftp-deploy-50eelh8k/dtb/mt8192-asurada-spherion-r0.dtb
   83 12:40:00.515058  total size: 47278 (0 MB)
   84 12:40:00.515120  No compression specified
   85 12:40:00.516284  progress  69 % (0 MB)
   86 12:40:00.516560  progress 100 % (0 MB)
   87 12:40:00.516713  0 MB downloaded in 0.00 s (27.28 MB/s)
   88 12:40:00.516836  end: 1.3.1 http-download (duration 00:00:00) [common]
   90 12:40:00.517060  end: 1.3 download-retry (duration 00:00:00) [common]
   91 12:40:00.517144  start: 1.4 download-retry (timeout 00:10:00) [common]
   92 12:40:00.517244  start: 1.4.1 http-download (timeout 00:10:00) [common]
   93 12:40:00.517354  downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/full.rootfs.tar.xz
   94 12:40:00.517422  saving as /var/lib/lava/dispatcher/tmp/12703575/tftp-deploy-50eelh8k/nfsrootfs/full.rootfs.tar
   95 12:40:00.517481  total size: 125290964 (119 MB)
   96 12:40:00.517542  Using unxz to decompress xz
   97 12:40:00.521063  progress   0 % (0 MB)
   98 12:40:00.839906  progress   5 % (6 MB)
   99 12:40:01.166558  progress  10 % (11 MB)
  100 12:40:01.491653  progress  15 % (17 MB)
  101 12:40:01.672827  progress  20 % (23 MB)
  102 12:40:01.844322  progress  25 % (29 MB)
  103 12:40:02.179402  progress  30 % (35 MB)
  104 12:40:02.519911  progress  35 % (41 MB)
  105 12:40:02.895206  progress  40 % (47 MB)
  106 12:40:03.260372  progress  45 % (53 MB)
  107 12:40:03.632447  progress  50 % (59 MB)
  108 12:40:03.969945  progress  55 % (65 MB)
  109 12:40:04.326410  progress  60 % (71 MB)
  110 12:40:04.650852  progress  65 % (77 MB)
  111 12:40:04.999844  progress  70 % (83 MB)
  112 12:40:05.366306  progress  75 % (89 MB)
  113 12:40:05.767685  progress  80 % (95 MB)
  114 12:40:06.174361  progress  85 % (101 MB)
  115 12:40:06.412704  progress  90 % (107 MB)
  116 12:40:06.738843  progress  95 % (113 MB)
  117 12:40:07.098559  progress 100 % (119 MB)
  118 12:40:07.104183  119 MB downloaded in 6.59 s (18.14 MB/s)
  119 12:40:07.104516  end: 1.4.1 http-download (duration 00:00:07) [common]
  121 12:40:07.104778  end: 1.4 download-retry (duration 00:00:07) [common]
  122 12:40:07.104868  start: 1.5 download-retry (timeout 00:09:53) [common]
  123 12:40:07.104954  start: 1.5.1 http-download (timeout 00:09:53) [common]
  124 12:40:07.105096  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
  125 12:40:07.105167  saving as /var/lib/lava/dispatcher/tmp/12703575/tftp-deploy-50eelh8k/modules/modules.tar
  126 12:40:07.105227  total size: 8639964 (8 MB)
  127 12:40:07.105290  Using unxz to decompress xz
  128 12:40:07.109075  progress   0 % (0 MB)
  129 12:40:07.129829  progress   5 % (0 MB)
  130 12:40:07.152685  progress  10 % (0 MB)
  131 12:40:07.175305  progress  15 % (1 MB)
  132 12:40:07.198229  progress  20 % (1 MB)
  133 12:40:07.221767  progress  25 % (2 MB)
  134 12:40:07.248590  progress  30 % (2 MB)
  135 12:40:07.271955  progress  35 % (2 MB)
  136 12:40:07.294533  progress  40 % (3 MB)
  137 12:40:07.317997  progress  45 % (3 MB)
  138 12:40:07.342676  progress  50 % (4 MB)
  139 12:40:07.368015  progress  55 % (4 MB)
  140 12:40:07.393705  progress  60 % (4 MB)
  141 12:40:07.418554  progress  65 % (5 MB)
  142 12:40:07.442797  progress  70 % (5 MB)
  143 12:40:07.465785  progress  75 % (6 MB)
  144 12:40:07.492089  progress  80 % (6 MB)
  145 12:40:07.519121  progress  85 % (7 MB)
  146 12:40:07.543353  progress  90 % (7 MB)
  147 12:40:07.572087  progress  95 % (7 MB)
  148 12:40:07.598784  progress 100 % (8 MB)
  149 12:40:07.604533  8 MB downloaded in 0.50 s (16.50 MB/s)
  150 12:40:07.604778  end: 1.5.1 http-download (duration 00:00:00) [common]
  152 12:40:07.605047  end: 1.5 download-retry (duration 00:00:01) [common]
  153 12:40:07.605141  start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
  154 12:40:07.605234  start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
  155 12:40:09.535985  Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12703575/extract-nfsrootfs-nzirnmiu
  156 12:40:09.536193  end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
  157 12:40:09.536297  start: 1.6.2 lava-overlay (timeout 00:09:51) [common]
  158 12:40:09.536451  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb
  159 12:40:09.536579  makedir: /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/bin
  160 12:40:09.536679  makedir: /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/tests
  161 12:40:09.536772  makedir: /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/results
  162 12:40:09.536871  Creating /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/bin/lava-add-keys
  163 12:40:09.537010  Creating /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/bin/lava-add-sources
  164 12:40:09.537134  Creating /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/bin/lava-background-process-start
  165 12:40:09.537257  Creating /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/bin/lava-background-process-stop
  166 12:40:09.537378  Creating /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/bin/lava-common-functions
  167 12:40:09.537497  Creating /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/bin/lava-echo-ipv4
  168 12:40:09.537621  Creating /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/bin/lava-install-packages
  169 12:40:09.537739  Creating /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/bin/lava-installed-packages
  170 12:40:09.537855  Creating /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/bin/lava-os-build
  171 12:40:09.538002  Creating /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/bin/lava-probe-channel
  172 12:40:09.538132  Creating /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/bin/lava-probe-ip
  173 12:40:09.538248  Creating /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/bin/lava-target-ip
  174 12:40:09.538366  Creating /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/bin/lava-target-mac
  175 12:40:09.538483  Creating /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/bin/lava-target-storage
  176 12:40:09.538602  Creating /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/bin/lava-test-case
  177 12:40:09.538721  Creating /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/bin/lava-test-event
  178 12:40:09.538836  Creating /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/bin/lava-test-feedback
  179 12:40:09.538951  Creating /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/bin/lava-test-raise
  180 12:40:09.539067  Creating /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/bin/lava-test-reference
  181 12:40:09.539183  Creating /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/bin/lava-test-runner
  182 12:40:09.539299  Creating /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/bin/lava-test-set
  183 12:40:09.539414  Creating /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/bin/lava-test-shell
  184 12:40:09.539532  Updating /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/bin/lava-install-packages (oe)
  185 12:40:09.539683  Updating /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/bin/lava-installed-packages (oe)
  186 12:40:09.539799  Creating /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/environment
  187 12:40:09.539890  LAVA metadata
  188 12:40:09.539958  - LAVA_JOB_ID=12703575
  189 12:40:09.540019  - LAVA_DISPATCHER_IP=192.168.201.1
  190 12:40:09.540115  start: 1.6.2.1 lava-vland-overlay (timeout 00:09:51) [common]
  191 12:40:09.540181  skipped lava-vland-overlay
  192 12:40:09.540253  end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
  193 12:40:09.540329  start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:51) [common]
  194 12:40:09.540390  skipped lava-multinode-overlay
  195 12:40:09.540460  end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
  196 12:40:09.540536  start: 1.6.2.3 test-definition (timeout 00:09:51) [common]
  197 12:40:09.540616  Loading test definitions
  198 12:40:09.540705  start: 1.6.2.3.1 inline-repo-action (timeout 00:09:51) [common]
  199 12:40:09.540775  Using /lava-12703575 at stage 0
  200 12:40:09.541062  uuid=12703575_1.6.2.3.1 testdef=None
  201 12:40:09.541148  end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
  202 12:40:09.541231  start: 1.6.2.3.2 test-overlay (timeout 00:09:51) [common]
  203 12:40:09.541725  end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
  205 12:40:09.542088  start: 1.6.2.3.3 test-install-overlay (timeout 00:09:51) [common]
  206 12:40:09.542718  end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
  208 12:40:09.542946  start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:51) [common]
  209 12:40:09.543550  runner path: /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/0/tests/0_dmesg test_uuid 12703575_1.6.2.3.1
  210 12:40:09.543701  end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
  212 12:40:09.543924  start: 1.6.2.3.5 inline-repo-action (timeout 00:09:51) [common]
  213 12:40:09.543995  Using /lava-12703575 at stage 1
  214 12:40:09.544275  uuid=12703575_1.6.2.3.5 testdef=None
  215 12:40:09.544361  end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
  216 12:40:09.544444  start: 1.6.2.3.6 test-overlay (timeout 00:09:51) [common]
  217 12:40:09.544897  end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
  219 12:40:09.545110  start: 1.6.2.3.7 test-install-overlay (timeout 00:09:51) [common]
  220 12:40:09.545732  end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
  222 12:40:09.545961  start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:51) [common]
  223 12:40:09.546607  runner path: /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/1/tests/1_bootrr test_uuid 12703575_1.6.2.3.5
  224 12:40:09.546754  end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
  226 12:40:09.546957  Creating lava-test-runner.conf files
  227 12:40:09.547018  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/0 for stage 0
  228 12:40:09.547105  - 0_dmesg
  229 12:40:09.547182  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12703575/lava-overlay-bu2v3zxb/lava-12703575/1 for stage 1
  230 12:40:09.547270  - 1_bootrr
  231 12:40:09.547360  end: 1.6.2.3 test-definition (duration 00:00:00) [common]
  232 12:40:09.547444  start: 1.6.2.4 compress-overlay (timeout 00:09:51) [common]
  233 12:40:09.554574  end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
  234 12:40:09.554674  start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:51) [common]
  235 12:40:09.554759  end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
  236 12:40:09.554841  end: 1.6.2 lava-overlay (duration 00:00:00) [common]
  237 12:40:09.554924  start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:51) [common]
  238 12:40:09.666359  end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
  239 12:40:09.666716  start: 1.6.4 extract-modules (timeout 00:09:51) [common]
  240 12:40:09.666826  extracting modules file /var/lib/lava/dispatcher/tmp/12703575/tftp-deploy-50eelh8k/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12703575/extract-nfsrootfs-nzirnmiu
  241 12:40:09.864074  extracting modules file /var/lib/lava/dispatcher/tmp/12703575/tftp-deploy-50eelh8k/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12703575/extract-overlay-ramdisk-rvn1voon/ramdisk
  242 12:40:10.067494  end: 1.6.4 extract-modules (duration 00:00:00) [common]
  243 12:40:10.067674  start: 1.6.5 apply-overlay-tftp (timeout 00:09:50) [common]
  244 12:40:10.067770  [common] Applying overlay to NFS
  245 12:40:10.067842  [common] Applying overlay /var/lib/lava/dispatcher/tmp/12703575/compress-overlay-w_5zb_wb/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12703575/extract-nfsrootfs-nzirnmiu
  246 12:40:10.075305  end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
  247 12:40:10.075415  start: 1.6.6 configure-preseed-file (timeout 00:09:50) [common]
  248 12:40:10.075504  end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
  249 12:40:10.075592  start: 1.6.7 compress-ramdisk (timeout 00:09:50) [common]
  250 12:40:10.075667  Building ramdisk /var/lib/lava/dispatcher/tmp/12703575/extract-overlay-ramdisk-rvn1voon/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12703575/extract-overlay-ramdisk-rvn1voon/ramdisk
  251 12:40:10.333435  >> 119430 blocks

  252 12:40:12.209123  rename /var/lib/lava/dispatcher/tmp/12703575/extract-overlay-ramdisk-rvn1voon/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12703575/tftp-deploy-50eelh8k/ramdisk/ramdisk.cpio.gz
  253 12:40:12.209537  end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
  254 12:40:12.209659  start: 1.6.8 prepare-kernel (timeout 00:09:48) [common]
  255 12:40:12.209766  start: 1.6.8.1 prepare-fit (timeout 00:09:48) [common]
  256 12:40:12.209875  Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12703575/tftp-deploy-50eelh8k/kernel/Image'
  257 12:40:24.533534  Returned 0 in 12 seconds
  258 12:40:24.634108  mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12703575/tftp-deploy-50eelh8k/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12703575/tftp-deploy-50eelh8k/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12703575/tftp-deploy-50eelh8k/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12703575/tftp-deploy-50eelh8k/kernel/image.itb
  259 12:40:24.976505  output: FIT description: Kernel Image image with one or more FDT blobs
  260 12:40:24.976856  output: Created:         Mon Feb  5 12:40:24 2024
  261 12:40:24.976929  output:  Image 0 (kernel-1)
  262 12:40:24.976995  output:   Description:  
  263 12:40:24.977056  output:   Created:      Mon Feb  5 12:40:24 2024
  264 12:40:24.977121  output:   Type:         Kernel Image
  265 12:40:24.977196  output:   Compression:  lzma compressed
  266 12:40:24.977272  output:   Data Size:    12052857 Bytes = 11770.37 KiB = 11.49 MiB
  267 12:40:24.977343  output:   Architecture: AArch64
  268 12:40:24.977399  output:   OS:           Linux
  269 12:40:24.977455  output:   Load Address: 0x00000000
  270 12:40:24.977512  output:   Entry Point:  0x00000000
  271 12:40:24.977567  output:   Hash algo:    crc32
  272 12:40:24.977623  output:   Hash value:   8a14336a
  273 12:40:24.977678  output:  Image 1 (fdt-1)
  274 12:40:24.977735  output:   Description:  mt8192-asurada-spherion-r0
  275 12:40:24.977789  output:   Created:      Mon Feb  5 12:40:24 2024
  276 12:40:24.977842  output:   Type:         Flat Device Tree
  277 12:40:24.977895  output:   Compression:  uncompressed
  278 12:40:24.977956  output:   Data Size:    47278 Bytes = 46.17 KiB = 0.05 MiB
  279 12:40:24.978045  output:   Architecture: AArch64
  280 12:40:24.978098  output:   Hash algo:    crc32
  281 12:40:24.978150  output:   Hash value:   cc4352de
  282 12:40:24.978203  output:  Image 2 (ramdisk-1)
  283 12:40:24.978256  output:   Description:  unavailable
  284 12:40:24.978307  output:   Created:      Mon Feb  5 12:40:24 2024
  285 12:40:24.978359  output:   Type:         RAMDisk Image
  286 12:40:24.978411  output:   Compression:  Unknown Compression
  287 12:40:24.978464  output:   Data Size:    17808901 Bytes = 17391.50 KiB = 16.98 MiB
  288 12:40:24.978516  output:   Architecture: AArch64
  289 12:40:24.978568  output:   OS:           Linux
  290 12:40:24.978623  output:   Load Address: unavailable
  291 12:40:24.978676  output:   Entry Point:  unavailable
  292 12:40:24.978728  output:   Hash algo:    crc32
  293 12:40:24.978779  output:   Hash value:   222f7256
  294 12:40:24.978830  output:  Default Configuration: 'conf-1'
  295 12:40:24.978883  output:  Configuration 0 (conf-1)
  296 12:40:24.978934  output:   Description:  mt8192-asurada-spherion-r0
  297 12:40:24.978987  output:   Kernel:       kernel-1
  298 12:40:24.979039  output:   Init Ramdisk: ramdisk-1
  299 12:40:24.979091  output:   FDT:          fdt-1
  300 12:40:24.979147  output:   Loadables:    kernel-1
  301 12:40:24.979212  output: 
  302 12:40:24.979405  end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
  303 12:40:24.979500  end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
  304 12:40:24.979603  end: 1.6 prepare-tftp-overlay (duration 00:00:17) [common]
  305 12:40:24.979696  start: 1.7 lxc-create-udev-rule-action (timeout 00:09:35) [common]
  306 12:40:24.979776  No LXC device requested
  307 12:40:24.979852  end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
  308 12:40:24.979937  start: 1.8 deploy-device-env (timeout 00:09:35) [common]
  309 12:40:24.980014  end: 1.8 deploy-device-env (duration 00:00:00) [common]
  310 12:40:24.980084  Checking files for TFTP limit of 4294967296 bytes.
  311 12:40:24.980577  end: 1 tftp-deploy (duration 00:00:25) [common]
  312 12:40:24.980681  start: 2 depthcharge-action (timeout 00:05:00) [common]
  313 12:40:24.980772  start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
  314 12:40:24.980895  substitutions:
  315 12:40:24.980962  - {DTB}: 12703575/tftp-deploy-50eelh8k/dtb/mt8192-asurada-spherion-r0.dtb
  316 12:40:24.981025  - {INITRD}: 12703575/tftp-deploy-50eelh8k/ramdisk/ramdisk.cpio.gz
  317 12:40:24.981085  - {KERNEL}: 12703575/tftp-deploy-50eelh8k/kernel/Image
  318 12:40:24.981147  - {LAVA_MAC}: None
  319 12:40:24.981215  - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12703575/extract-nfsrootfs-nzirnmiu
  320 12:40:24.981270  - {NFS_SERVER_IP}: 192.168.201.1
  321 12:40:24.981325  - {PRESEED_CONFIG}: None
  322 12:40:24.981379  - {PRESEED_LOCAL}: None
  323 12:40:24.981433  - {RAMDISK}: 12703575/tftp-deploy-50eelh8k/ramdisk/ramdisk.cpio.gz
  324 12:40:24.981487  - {ROOT_PART}: None
  325 12:40:24.981540  - {ROOT}: None
  326 12:40:24.981593  - {SERVER_IP}: 192.168.201.1
  327 12:40:24.981647  - {TEE}: None
  328 12:40:24.981699  Parsed boot commands:
  329 12:40:24.981752  - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
  330 12:40:24.981928  Parsed boot commands: tftpboot 192.168.201.1 12703575/tftp-deploy-50eelh8k/kernel/image.itb 12703575/tftp-deploy-50eelh8k/kernel/cmdline 
  331 12:40:24.982060  end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
  332 12:40:24.982145  start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
  333 12:40:24.982235  start: 2.2.1 reset-connection (timeout 00:05:00) [common]
  334 12:40:24.982319  start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
  335 12:40:24.982388  Not connected, no need to disconnect.
  336 12:40:24.982462  end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
  337 12:40:24.982540  start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
  338 12:40:24.982610  [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
  339 12:40:24.986007  Setting prompt string to ['lava-test: # ']
  340 12:40:24.986344  end: 2.2.1.2 connect-device (duration 00:00:00) [common]
  341 12:40:24.986453  end: 2.2.1 reset-connection (duration 00:00:00) [common]
  342 12:40:24.986549  start: 2.2.2 reset-device (timeout 00:05:00) [common]
  343 12:40:24.986670  start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
  344 12:40:24.986866  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
  345 12:40:30.120806  >> Command sent successfully.

  346 12:40:30.123088  Returned 0 in 5 seconds
  347 12:40:30.223472  end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
  349 12:40:30.223791  end: 2.2.2 reset-device (duration 00:00:05) [common]
  350 12:40:30.223893  start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
  351 12:40:30.223981  Setting prompt string to 'Starting depthcharge on Spherion...'
  352 12:40:30.224050  Changing prompt to 'Starting depthcharge on Spherion...'
  353 12:40:30.224121  depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
  354 12:40:30.224378  [Enter `^Ec?' for help]

  355 12:40:30.396727  

  356 12:40:30.396867  

  357 12:40:30.396940  F0: 102B 0000

  358 12:40:30.397005  

  359 12:40:30.397066  F3: 1001 0000 [0200]

  360 12:40:30.397125  

  361 12:40:30.400164  F3: 1001 0000

  362 12:40:30.400247  

  363 12:40:30.400312  F7: 102D 0000

  364 12:40:30.400373  

  365 12:40:30.400431  F1: 0000 0000

  366 12:40:30.400488  

  367 12:40:30.404137  V0: 0000 0000 [0001]

  368 12:40:30.404220  

  369 12:40:30.404286  00: 0007 8000

  370 12:40:30.404348  

  371 12:40:30.407853  01: 0000 0000

  372 12:40:30.407937  

  373 12:40:30.408001  BP: 0C00 0209 [0000]

  374 12:40:30.408067  

  375 12:40:30.408126  G0: 1182 0000

  376 12:40:30.412108  

  377 12:40:30.412190  EC: 0000 0021 [4000]

  378 12:40:30.412256  

  379 12:40:30.415237  S7: 0000 0000 [0000]

  380 12:40:30.415320  

  381 12:40:30.415386  CC: 0000 0000 [0001]

  382 12:40:30.415446  

  383 12:40:30.418624  T0: 0000 0040 [010F]

  384 12:40:30.418707  

  385 12:40:30.418772  Jump to BL

  386 12:40:30.418832  

  387 12:40:30.443899  

  388 12:40:30.444029  

  389 12:40:30.444096  

  390 12:40:30.451069  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...

  391 12:40:30.454786  ARM64: Exception handlers installed.

  392 12:40:30.458358  ARM64: Testing exception

  393 12:40:30.462455  ARM64: Done test exception

  394 12:40:30.465956  Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000

  395 12:40:30.477519  Mapping address range [0x00000000:0x200000000) as     cacheable | read-write |     secure | device

  396 12:40:30.484373  Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000

  397 12:40:30.494863  Mapping address range [0x00100000:0x00120000) as     cacheable | read-write |     secure | normal

  398 12:40:30.501235  Backing address range [0x00000000:0x40000000) with new page table @0x0010f000

  399 12:40:30.507974  Backing address range [0x00000000:0x00200000) with new page table @0x00110000

  400 12:40:30.520018  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | normal

  401 12:40:30.527261  Backing address range [0x00200000:0x00400000) with new page table @0x00111000

  402 12:40:30.546135  Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write |     secure | normal

  403 12:40:30.549492  WDT: Last reset was cold boot

  404 12:40:30.553193  SPI1(PAD0) initialized at 2873684 Hz

  405 12:40:30.556252  SPI5(PAD0) initialized at 992727 Hz

  406 12:40:30.559647  VBOOT: Loading verstage.

  407 12:40:30.566295  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  408 12:40:30.569819  FMAP: Found "FLASH" version 1.1 at 0x20000.

  409 12:40:30.572965  FMAP: base = 0x0 size = 0x800000 #areas = 25

  410 12:40:30.576054  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  411 12:40:30.583530  CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes

  412 12:40:30.590131  CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150

  413 12:40:30.601512  read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps

  414 12:40:30.601604  

  415 12:40:30.601673  

  416 12:40:30.611436  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...

  417 12:40:30.614629  ARM64: Exception handlers installed.

  418 12:40:30.617794  ARM64: Testing exception

  419 12:40:30.617881  ARM64: Done test exception

  420 12:40:30.624802  FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)

  421 12:40:30.628167  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  422 12:40:30.642203  Probing TPM: . done!

  423 12:40:30.642297  TPM ready after 0 ms

  424 12:40:30.648753  Connected to device vid:did:rid of 1ae0:0028:00

  425 12:40:30.655978  Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c

  426 12:40:30.712678  Initialized TPM device CR50 revision 0

  427 12:40:30.725165  tlcl_send_startup: Startup return code is 0

  428 12:40:30.725303  TPM: setup succeeded

  429 12:40:30.736221  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0

  430 12:40:30.745128  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  431 12:40:30.755181  VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)

  432 12:40:30.765054  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  433 12:40:30.768257  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  434 12:40:30.776112  in-header: 03 07 00 00 08 00 00 00 

  435 12:40:30.779532  in-data: aa e4 47 04 13 02 00 00 

  436 12:40:30.783781  Chrome EC: UHEPI supported

  437 12:40:30.790632  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  438 12:40:30.794371  in-header: 03 ad 00 00 08 00 00 00 

  439 12:40:30.797580  in-data: 00 20 20 08 00 00 00 00 

  440 12:40:30.797665  Phase 1

  441 12:40:30.801634  FMAP: area GBB found @ 3f5000 (12032 bytes)

  442 12:40:30.808647  VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7

  443 12:40:30.812363  VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7

  444 12:40:30.816929  Recovery requested (1009000e)

  445 12:40:30.825504  TPM: Extending digest for VBOOT: boot mode into PCR 0

  446 12:40:30.831480  tlcl_extend: response is 0

  447 12:40:30.840742  TPM: Extending digest for VBOOT: GBB HWID into PCR 1

  448 12:40:30.846364  tlcl_extend: response is 0

  449 12:40:30.853493  CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c

  450 12:40:30.873716  read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps

  451 12:40:30.880626  BS: bootblock times (exec / console): total (unknown) / 148 ms

  452 12:40:30.880716  

  453 12:40:30.880785  

  454 12:40:30.890732  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...

  455 12:40:30.893973  ARM64: Exception handlers installed.

  456 12:40:30.894075  ARM64: Testing exception

  457 12:40:30.897138  ARM64: Done test exception

  458 12:40:30.918954  pmic_efuse_setting: Set efuses in 11 msecs

  459 12:40:30.922375  pmwrap_interface_init: Select PMIF_VLD_RDY

  460 12:40:30.929030  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a

  461 12:40:30.932567  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a

  462 12:40:30.936270  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a

  463 12:40:30.943067  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a

  464 12:40:30.946180  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a

  465 12:40:30.954200  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a

  466 12:40:30.957275  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a

  467 12:40:30.961266  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a

  468 12:40:30.964960  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c

  469 12:40:30.972119  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a

  470 12:40:30.975800  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a

  471 12:40:30.979451  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c

  472 12:40:30.982673  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c

  473 12:40:30.989879  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a

  474 12:40:30.996731  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a

  475 12:40:31.003902  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a

  476 12:40:31.007710  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a

  477 12:40:31.015419  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a

  478 12:40:31.019191  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a

  479 12:40:31.025523  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a

  480 12:40:31.029029  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c

  481 12:40:31.036234  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a

  482 12:40:31.043147  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a

  483 12:40:31.046092  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c

  484 12:40:31.052740  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c

  485 12:40:31.059603  [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa

  486 12:40:31.063013  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92

  487 12:40:31.066178  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2

  488 12:40:31.072813  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82

  489 12:40:31.076206  [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10

  490 12:40:31.083332  [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425

  491 12:40:31.086249  [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010

  492 12:40:31.093353  [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f

  493 12:40:31.096614  [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000

  494 12:40:31.103304  [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8

  495 12:40:31.106709  [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb

  496 12:40:31.113207  [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698

  497 12:40:31.116903  [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3

  498 12:40:31.123055  [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92

  499 12:40:31.127232  [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a

  500 12:40:31.129952  [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2

  501 12:40:31.133457  [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a

  502 12:40:31.139979  [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a

  503 12:40:31.143850  [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a

  504 12:40:31.147087  [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a

  505 12:40:31.154039  [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82

  506 12:40:31.157468  [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c

  507 12:40:31.160859  [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a

  508 12:40:31.164240  [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a

  509 12:40:31.170886  [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c

  510 12:40:31.174440  [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c

  511 12:40:31.180917  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248

  512 12:40:31.190905  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1

  513 12:40:31.194263  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  514 12:40:31.201689  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248

  515 12:40:31.211105  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0

  516 12:40:31.214395  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  517 12:40:31.221134  [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  518 12:40:31.224378  [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  519 12:40:31.231183  [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x18

  520 12:40:31.237976  [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2

  521 12:40:31.241147  [RTC]rtc_osc_init,62: osc32con val = 0xde70

  522 12:40:31.244595  [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a

  523 12:40:31.256329  [RTC]rtc_get_frequency_meter,154: input=15, output=773

  524 12:40:31.265453  [RTC]rtc_get_frequency_meter,154: input=23, output=957

  525 12:40:31.275096  [RTC]rtc_get_frequency_meter,154: input=19, output=865

  526 12:40:31.284180  [RTC]rtc_get_frequency_meter,154: input=17, output=818

  527 12:40:31.293807  [RTC]rtc_get_frequency_meter,154: input=16, output=795

  528 12:40:31.297043  [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70

  529 12:40:31.304189  [RTC]rtc_boot_common,202: RTC_STATE_REBOOT

  530 12:40:31.307027  [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486

  531 12:40:31.310852  [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1

  532 12:40:31.313854  [RTC]rtc_bbpu_power_on,300: done BBPU=0x81

  533 12:40:31.317262  ADC[4]: Raw value=902139 ID=7

  534 12:40:31.320813  ADC[3]: Raw value=213179 ID=1

  535 12:40:31.320900  RAM Code: 0x71

  536 12:40:31.327281  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  537 12:40:31.330460  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  538 12:40:31.340884  CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014

  539 12:40:31.347238  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  540 12:40:31.350691  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  541 12:40:31.353919  in-header: 03 07 00 00 08 00 00 00 

  542 12:40:31.357235  in-data: aa e4 47 04 13 02 00 00 

  543 12:40:31.360890  Chrome EC: UHEPI supported

  544 12:40:31.367462  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  545 12:40:31.370583  in-header: 03 ed 00 00 08 00 00 00 

  546 12:40:31.374074  in-data: 80 20 60 08 00 00 00 00 

  547 12:40:31.377443  MRC: failed to locate region type 0.

  548 12:40:31.384977  DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)

  549 12:40:31.385070  DRAM-K: Running full calibration

  550 12:40:31.391821  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  551 12:40:31.395756  header.status = 0x0

  552 12:40:31.399626  header.version = 0x6 (expected: 0x6)

  553 12:40:31.403308  header.size = 0xd00 (expected: 0xd00)

  554 12:40:31.403397  header.flags = 0x0

  555 12:40:31.409997  CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40

  556 12:40:31.427338  read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps

  557 12:40:31.434336  dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6

  558 12:40:31.438137  dram_init: ddr_geometry: 2

  559 12:40:31.438291  [EMI] MDL number = 2

  560 12:40:31.442396  [EMI] Get MDL freq = 0

  561 12:40:31.442481  dram_init: ddr_type: 0

  562 12:40:31.445706  is_discrete_lpddr4: 1

  563 12:40:31.448694  [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0

  564 12:40:31.448781  

  565 12:40:31.448849  

  566 12:40:31.452064  [Bian_co] ETT version 0.0.0.1

  567 12:40:31.455631   dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6

  568 12:40:31.455718  

  569 12:40:31.458794  dramc_set_vcore_voltage set vcore to 650000

  570 12:40:31.462316  Read voltage for 800, 4

  571 12:40:31.462402  Vio18 = 0

  572 12:40:31.462471  Vcore = 650000

  573 12:40:31.466056  Vdram = 0

  574 12:40:31.466147  Vddq = 0

  575 12:40:31.466216  Vmddr = 0

  576 12:40:31.469196  dram_init: config_dvfs: 1

  577 12:40:31.472390  [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0

  578 12:40:31.479344  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

  579 12:40:31.482370  [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9

  580 12:40:31.485516  freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9

  581 12:40:31.492301  [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9

  582 12:40:31.495694  freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9

  583 12:40:31.495795  MEM_TYPE=3, freq_sel=18

  584 12:40:31.499550  sv_algorithm_assistance_LP4_1600 

  585 12:40:31.503477  ============ PULL DRAM RESETB DOWN ============

  586 12:40:31.506832  ========== PULL DRAM RESETB DOWN end =========

  587 12:40:31.514735  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  588 12:40:31.514859  =================================== 

  589 12:40:31.518406  LPDDR4 DRAM CONFIGURATION

  590 12:40:31.521921  =================================== 

  591 12:40:31.525907  EX_ROW_EN[0]    = 0x0

  592 12:40:31.526049  EX_ROW_EN[1]    = 0x0

  593 12:40:31.526118  LP4Y_EN      = 0x0

  594 12:40:31.529204  WORK_FSP     = 0x0

  595 12:40:31.532646  WL           = 0x2

  596 12:40:31.532740  RL           = 0x2

  597 12:40:31.536020  BL           = 0x2

  598 12:40:31.536123  RPST         = 0x0

  599 12:40:31.539266  RD_PRE       = 0x0

  600 12:40:31.539357  WR_PRE       = 0x1

  601 12:40:31.542502  WR_PST       = 0x0

  602 12:40:31.542592  DBI_WR       = 0x0

  603 12:40:31.545966  DBI_RD       = 0x0

  604 12:40:31.546057  OTF          = 0x1

  605 12:40:31.549590  =================================== 

  606 12:40:31.552787  =================================== 

  607 12:40:31.556051  ANA top config

  608 12:40:31.559255  =================================== 

  609 12:40:31.559357  DLL_ASYNC_EN            =  0

  610 12:40:31.562570  ALL_SLAVE_EN            =  1

  611 12:40:31.566075  NEW_RANK_MODE           =  1

  612 12:40:31.569576  DLL_IDLE_MODE           =  1

  613 12:40:31.569680  LP45_APHY_COMB_EN       =  1

  614 12:40:31.572740  TX_ODT_DIS              =  1

  615 12:40:31.576076  NEW_8X_MODE             =  1

  616 12:40:31.579295  =================================== 

  617 12:40:31.582481  =================================== 

  618 12:40:31.586541  data_rate                  = 1600

  619 12:40:31.589230  CKR                        = 1

  620 12:40:31.589317  DQ_P2S_RATIO               = 8

  621 12:40:31.592831  =================================== 

  622 12:40:31.596542  CA_P2S_RATIO               = 8

  623 12:40:31.599452  DQ_CA_OPEN                 = 0

  624 12:40:31.602729  DQ_SEMI_OPEN               = 0

  625 12:40:31.606165  CA_SEMI_OPEN               = 0

  626 12:40:31.609772  CA_FULL_RATE               = 0

  627 12:40:31.609859  DQ_CKDIV4_EN               = 1

  628 12:40:31.613070  CA_CKDIV4_EN               = 1

  629 12:40:31.616237  CA_PREDIV_EN               = 0

  630 12:40:31.619532  PH8_DLY                    = 0

  631 12:40:31.622708  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

  632 12:40:31.626158  DQ_AAMCK_DIV               = 4

  633 12:40:31.626255  CA_AAMCK_DIV               = 4

  634 12:40:31.629445  CA_ADMCK_DIV               = 4

  635 12:40:31.632857  DQ_TRACK_CA_EN             = 0

  636 12:40:31.636012  CA_PICK                    = 800

  637 12:40:31.639369  CA_MCKIO                   = 800

  638 12:40:31.642748  MCKIO_SEMI                 = 0

  639 12:40:31.642848  PLL_FREQ                   = 3068

  640 12:40:31.645927  DQ_UI_PI_RATIO             = 32

  641 12:40:31.649357  CA_UI_PI_RATIO             = 0

  642 12:40:31.652730  =================================== 

  643 12:40:31.656003  =================================== 

  644 12:40:31.659716  memory_type:LPDDR4         

  645 12:40:31.659802  GP_NUM     : 10       

  646 12:40:31.662536  SRAM_EN    : 1       

  647 12:40:31.666469  MD32_EN    : 0       

  648 12:40:31.669680  =================================== 

  649 12:40:31.669793  [ANA_INIT] >>>>>>>>>>>>>> 

  650 12:40:31.673845  <<<<<< [CONFIGURE PHASE]: ANA_TX

  651 12:40:31.677352  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

  652 12:40:31.680742  =================================== 

  653 12:40:31.684711  data_rate = 1600,PCW = 0X7600

  654 12:40:31.684804  =================================== 

  655 12:40:31.688453  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

  656 12:40:31.696028  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  657 12:40:31.699654  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  658 12:40:31.706639  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

  659 12:40:31.710367  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

  660 12:40:31.713371  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

  661 12:40:31.713458  [ANA_INIT] flow start 

  662 12:40:31.716455  [ANA_INIT] PLL >>>>>>>> 

  663 12:40:31.719898  [ANA_INIT] PLL <<<<<<<< 

  664 12:40:31.719999  [ANA_INIT] MIDPI >>>>>>>> 

  665 12:40:31.723182  [ANA_INIT] MIDPI <<<<<<<< 

  666 12:40:31.726664  [ANA_INIT] DLL >>>>>>>> 

  667 12:40:31.726757  [ANA_INIT] flow end 

  668 12:40:31.733175  ============ LP4 DIFF to SE enter ============

  669 12:40:31.736369  ============ LP4 DIFF to SE exit  ============

  670 12:40:31.739810  [ANA_INIT] <<<<<<<<<<<<< 

  671 12:40:31.743024  [Flow] Enable top DCM control >>>>> 

  672 12:40:31.746626  [Flow] Enable top DCM control <<<<< 

  673 12:40:31.746716  Enable DLL master slave shuffle 

  674 12:40:31.753124  ============================================================== 

  675 12:40:31.756710  Gating Mode config

  676 12:40:31.759767  ============================================================== 

  677 12:40:31.763240  Config description: 

  678 12:40:31.773500  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

  679 12:40:31.779908  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

  680 12:40:31.783418  SELPH_MODE            0: By rank         1: By Phase 

  681 12:40:31.790219  ============================================================== 

  682 12:40:31.793518  GAT_TRACK_EN                 =  1

  683 12:40:31.796735  RX_GATING_MODE               =  2

  684 12:40:31.796837  RX_GATING_TRACK_MODE         =  2

  685 12:40:31.800269  SELPH_MODE                   =  1

  686 12:40:31.803744  PICG_EARLY_EN                =  1

  687 12:40:31.806603  VALID_LAT_VALUE              =  1

  688 12:40:31.813250  ============================================================== 

  689 12:40:31.816936  Enter into Gating configuration >>>> 

  690 12:40:31.819937  Exit from Gating configuration <<<< 

  691 12:40:31.823294  Enter into  DVFS_PRE_config >>>>> 

  692 12:40:31.833154  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

  693 12:40:31.836444  Exit from  DVFS_PRE_config <<<<< 

  694 12:40:31.839858  Enter into PICG configuration >>>> 

  695 12:40:31.843604  Exit from PICG configuration <<<< 

  696 12:40:31.846748  [RX_INPUT] configuration >>>>> 

  697 12:40:31.850094  [RX_INPUT] configuration <<<<< 

  698 12:40:31.853427  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

  699 12:40:31.860188  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

  700 12:40:31.866892  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

  701 12:40:31.870065  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

  702 12:40:31.877074  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

  703 12:40:31.883436  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

  704 12:40:31.886608  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

  705 12:40:31.889930  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

  706 12:40:31.896852  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

  707 12:40:31.901077  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

  708 12:40:31.904085  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

  709 12:40:31.907121  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  710 12:40:31.910484  =================================== 

  711 12:40:31.914130  LPDDR4 DRAM CONFIGURATION

  712 12:40:31.917429  =================================== 

  713 12:40:31.920464  EX_ROW_EN[0]    = 0x0

  714 12:40:31.920550  EX_ROW_EN[1]    = 0x0

  715 12:40:31.923763  LP4Y_EN      = 0x0

  716 12:40:31.923850  WORK_FSP     = 0x0

  717 12:40:31.927450  WL           = 0x2

  718 12:40:31.927539  RL           = 0x2

  719 12:40:31.930844  BL           = 0x2

  720 12:40:31.930930  RPST         = 0x0

  721 12:40:31.934065  RD_PRE       = 0x0

  722 12:40:31.934151  WR_PRE       = 0x1

  723 12:40:31.937662  WR_PST       = 0x0

  724 12:40:31.937748  DBI_WR       = 0x0

  725 12:40:31.940766  DBI_RD       = 0x0

  726 12:40:31.940851  OTF          = 0x1

  727 12:40:31.944040  =================================== 

  728 12:40:31.950519  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

  729 12:40:31.954125  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

  730 12:40:31.957444  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  731 12:40:31.960577  =================================== 

  732 12:40:31.963875  LPDDR4 DRAM CONFIGURATION

  733 12:40:31.967468  =================================== 

  734 12:40:31.970820  EX_ROW_EN[0]    = 0x10

  735 12:40:31.970928  EX_ROW_EN[1]    = 0x0

  736 12:40:31.974183  LP4Y_EN      = 0x0

  737 12:40:31.974280  WORK_FSP     = 0x0

  738 12:40:31.978161  WL           = 0x2

  739 12:40:31.978260  RL           = 0x2

  740 12:40:31.981171  BL           = 0x2

  741 12:40:31.981266  RPST         = 0x0

  742 12:40:31.984791  RD_PRE       = 0x0

  743 12:40:31.984890  WR_PRE       = 0x1

  744 12:40:31.988332  WR_PST       = 0x0

  745 12:40:31.988432  DBI_WR       = 0x0

  746 12:40:31.988501  DBI_RD       = 0x0

  747 12:40:31.991960  OTF          = 0x1

  748 12:40:31.995552  =================================== 

  749 12:40:32.003127  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

  750 12:40:32.006062  nWR fixed to 40

  751 12:40:32.006149  [ModeRegInit_LP4] CH0 RK0

  752 12:40:32.010063  [ModeRegInit_LP4] CH0 RK1

  753 12:40:32.013541  [ModeRegInit_LP4] CH1 RK0

  754 12:40:32.013627  [ModeRegInit_LP4] CH1 RK1

  755 12:40:32.017395  match AC timing 13

  756 12:40:32.020691  dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1

  757 12:40:32.024220  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

  758 12:40:32.027679  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

  759 12:40:32.035074  [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17

  760 12:40:32.039172  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

  761 12:40:32.039260  [EMI DOE] emi_dcm 0

  762 12:40:32.046293  [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600

  763 12:40:32.046386  ==

  764 12:40:32.046454  Dram Type= 6, Freq= 0, CH_0, rank 0

  765 12:40:32.053797  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  766 12:40:32.053904  ==

  767 12:40:32.056887  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  768 12:40:32.063867  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  769 12:40:32.073199  [CA 0] Center 37 (7~68) winsize 62

  770 12:40:32.077170  [CA 1] Center 38 (7~69) winsize 63

  771 12:40:32.080701  [CA 2] Center 35 (5~66) winsize 62

  772 12:40:32.084535  [CA 3] Center 35 (5~66) winsize 62

  773 12:40:32.088363  [CA 4] Center 35 (4~66) winsize 63

  774 12:40:32.092233  [CA 5] Center 34 (4~64) winsize 61

  775 12:40:32.092605  

  776 12:40:32.095427  [CmdBusTrainingLP45] Vref(ca) range 1: 32

  777 12:40:32.095513  

  778 12:40:32.099039  [CATrainingPosCal] consider 1 rank data

  779 12:40:32.099126  u2DelayCellTimex100 = 270/100 ps

  780 12:40:32.102595  CA0 delay=37 (7~68),Diff = 3 PI (21 cell)

  781 12:40:32.106739  CA1 delay=38 (7~69),Diff = 4 PI (28 cell)

  782 12:40:32.110114  CA2 delay=35 (5~66),Diff = 1 PI (7 cell)

  783 12:40:32.113617  CA3 delay=35 (5~66),Diff = 1 PI (7 cell)

  784 12:40:32.117962  CA4 delay=35 (4~66),Diff = 1 PI (7 cell)

  785 12:40:32.121723  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

  786 12:40:32.121891  

  787 12:40:32.125463  CA PerBit enable=1, Macro0, CA PI delay=34

  788 12:40:32.125633  

  789 12:40:32.129078  [CBTSetCACLKResult] CA Dly = 34

  790 12:40:32.129250  CS Dly: 6 (0~37)

  791 12:40:32.132723  ==

  792 12:40:32.132872  Dram Type= 6, Freq= 0, CH_0, rank 1

  793 12:40:32.140750  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  794 12:40:32.140924  ==

  795 12:40:32.144533  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  796 12:40:32.151502  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  797 12:40:32.159810  [CA 0] Center 38 (7~69) winsize 63

  798 12:40:32.163212  [CA 1] Center 38 (7~69) winsize 63

  799 12:40:32.167351  [CA 2] Center 36 (6~67) winsize 62

  800 12:40:32.170480  [CA 3] Center 35 (5~66) winsize 62

  801 12:40:32.174536  [CA 4] Center 35 (4~66) winsize 63

  802 12:40:32.178214  [CA 5] Center 34 (4~65) winsize 62

  803 12:40:32.178724  

  804 12:40:32.181837  [CmdBusTrainingLP45] Vref(ca) range 1: 32

  805 12:40:32.182264  

  806 12:40:32.185563  [CATrainingPosCal] consider 2 rank data

  807 12:40:32.185990  u2DelayCellTimex100 = 270/100 ps

  808 12:40:32.189244  CA0 delay=37 (7~68),Diff = 3 PI (21 cell)

  809 12:40:32.192633  CA1 delay=38 (7~69),Diff = 4 PI (28 cell)

  810 12:40:32.196369  CA2 delay=36 (6~66),Diff = 2 PI (14 cell)

  811 12:40:32.200572  CA3 delay=35 (5~66),Diff = 1 PI (7 cell)

  812 12:40:32.204489  CA4 delay=35 (4~66),Diff = 1 PI (7 cell)

  813 12:40:32.207847  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

  814 12:40:32.208347  

  815 12:40:32.211855  CA PerBit enable=1, Macro0, CA PI delay=34

  816 12:40:32.212353  

  817 12:40:32.215243  [CBTSetCACLKResult] CA Dly = 34

  818 12:40:32.218947  CS Dly: 6 (0~38)

  819 12:40:32.219440  

  820 12:40:32.222537  ----->DramcWriteLeveling(PI) begin...

  821 12:40:32.222951  ==

  822 12:40:32.226069  Dram Type= 6, Freq= 0, CH_0, rank 0

  823 12:40:32.230087  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  824 12:40:32.230591  ==

  825 12:40:32.234117  Write leveling (Byte 0): 31 => 31

  826 12:40:32.234641  Write leveling (Byte 1): 32 => 32

  827 12:40:32.237761  DramcWriteLeveling(PI) end<-----

  828 12:40:32.238205  

  829 12:40:32.238560  ==

  830 12:40:32.241515  Dram Type= 6, Freq= 0, CH_0, rank 0

  831 12:40:32.244958  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  832 12:40:32.245500  ==

  833 12:40:32.249217  [Gating] SW mode calibration

  834 12:40:32.256824  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

  835 12:40:32.260859  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

  836 12:40:32.263998   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

  837 12:40:32.272029   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)

  838 12:40:32.275944   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)

  839 12:40:32.279518   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  840 12:40:32.283740   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  841 12:40:32.287100   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  842 12:40:32.290616   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  843 12:40:32.294202   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  844 12:40:32.301572   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  845 12:40:32.305697   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  846 12:40:32.308760   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  847 12:40:32.312444   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  848 12:40:32.319300   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  849 12:40:32.322039   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  850 12:40:32.325393   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  851 12:40:32.332220   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  852 12:40:32.336019   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  853 12:40:32.338746   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)

  854 12:40:32.345906   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)

  855 12:40:32.349156   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  856 12:40:32.352482   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  857 12:40:32.359124   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  858 12:40:32.361934   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  859 12:40:32.365703   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  860 12:40:32.372107   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  861 12:40:32.375430   0  9  4 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)

  862 12:40:32.378800   0  9  8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)

  863 12:40:32.382253   0  9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)

  864 12:40:32.388962   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  865 12:40:32.392125   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  866 12:40:32.395505   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  867 12:40:32.402561   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  868 12:40:32.406052   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  869 12:40:32.409081   0 10  4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)

  870 12:40:32.415748   0 10  8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)

  871 12:40:32.418741   0 10 12 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)

  872 12:40:32.422072   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  873 12:40:32.429268   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  874 12:40:32.432019   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  875 12:40:32.436063   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  876 12:40:32.442457   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  877 12:40:32.445808   0 11  4 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)

  878 12:40:32.449029   0 11  8 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)

  879 12:40:32.452020   0 11 12 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)

  880 12:40:32.458997   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  881 12:40:32.462302   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  882 12:40:32.465369   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  883 12:40:32.472583   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  884 12:40:32.476138   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  885 12:40:32.479345   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

  886 12:40:32.486146   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

  887 12:40:32.489285   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  888 12:40:32.492839   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  889 12:40:32.499086   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  890 12:40:32.502591   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  891 12:40:32.505860   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  892 12:40:32.512389   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  893 12:40:32.516242   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  894 12:40:32.519419   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  895 12:40:32.522941   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  896 12:40:32.529639   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  897 12:40:32.533019   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  898 12:40:32.536404   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  899 12:40:32.543058   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  900 12:40:32.546631   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  901 12:40:32.549643   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

  902 12:40:32.557057   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  903 12:40:32.559863  Total UI for P1: 0, mck2ui 16

  904 12:40:32.563017  best dqsien dly found for B0: ( 0, 14,  4)

  905 12:40:32.563565  Total UI for P1: 0, mck2ui 16

  906 12:40:32.569381  best dqsien dly found for B1: ( 0, 14,  6)

  907 12:40:32.572447  best DQS0 dly(MCK, UI, PI) = (0, 14, 4)

  908 12:40:32.575762  best DQS1 dly(MCK, UI, PI) = (0, 14, 6)

  909 12:40:32.576203  

  910 12:40:32.579480  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)

  911 12:40:32.582859  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)

  912 12:40:32.585841  [Gating] SW calibration Done

  913 12:40:32.586428  ==

  914 12:40:32.589892  Dram Type= 6, Freq= 0, CH_0, rank 0

  915 12:40:32.592773  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  916 12:40:32.593211  ==

  917 12:40:32.596526  RX Vref Scan: 0

  918 12:40:32.597084  

  919 12:40:32.597434  RX Vref 0 -> 0, step: 1

  920 12:40:32.597757  

  921 12:40:32.599324  RX Delay -130 -> 252, step: 16

  922 12:40:32.602860  iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224

  923 12:40:32.609616  iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224

  924 12:40:32.613250  iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224

  925 12:40:32.616027  iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224

  926 12:40:32.619289  iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224

  927 12:40:32.622585  iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224

  928 12:40:32.629315  iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240

  929 12:40:32.632611  iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240

  930 12:40:32.635767  iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224

  931 12:40:32.639408  iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208

  932 12:40:32.642802  iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208

  933 12:40:32.649705  iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224

  934 12:40:32.652728  iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208

  935 12:40:32.655992  iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208

  936 12:40:32.659314  iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224

  937 12:40:32.662776  iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208

  938 12:40:32.665829  ==

  939 12:40:32.669252  Dram Type= 6, Freq= 0, CH_0, rank 0

  940 12:40:32.672558  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  941 12:40:32.673179  ==

  942 12:40:32.673545  DQS Delay:

  943 12:40:32.675993  DQS0 = 0, DQS1 = 0

  944 12:40:32.676432  DQM Delay:

  945 12:40:32.679855  DQM0 = 93, DQM1 = 82

  946 12:40:32.680394  DQ Delay:

  947 12:40:32.683154  DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93

  948 12:40:32.685921  DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101

  949 12:40:32.690029  DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =77

  950 12:40:32.692975  DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85

  951 12:40:32.693516  

  952 12:40:32.693865  

  953 12:40:32.694294  ==

  954 12:40:32.696464  Dram Type= 6, Freq= 0, CH_0, rank 0

  955 12:40:32.699924  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  956 12:40:32.700462  ==

  957 12:40:32.700818  

  958 12:40:32.701142  

  959 12:40:32.702933  	TX Vref Scan disable

  960 12:40:32.706440   == TX Byte 0 ==

  961 12:40:32.709381  Update DQ  dly =581 (2 ,1, 37)  DQ  OEN =(1 ,6)

  962 12:40:32.712520  Update DQM dly =581 (2 ,1, 37)  DQM OEN =(1 ,6)

  963 12:40:32.716243   == TX Byte 1 ==

  964 12:40:32.719250  Update DQ  dly =581 (2 ,1, 37)  DQ  OEN =(1 ,6)

  965 12:40:32.722467  Update DQM dly =581 (2 ,1, 37)  DQM OEN =(1 ,6)

  966 12:40:32.722906  ==

  967 12:40:32.725627  Dram Type= 6, Freq= 0, CH_0, rank 0

  968 12:40:32.732307  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  969 12:40:32.732837  ==

  970 12:40:32.743901  TX Vref=22, minBit 6, minWin=27, winSum=441

  971 12:40:32.746958  TX Vref=24, minBit 6, minWin=27, winSum=443

  972 12:40:32.750214  TX Vref=26, minBit 8, minWin=27, winSum=449

  973 12:40:32.753687  TX Vref=28, minBit 8, minWin=27, winSum=452

  974 12:40:32.757236  TX Vref=30, minBit 8, minWin=27, winSum=457

  975 12:40:32.760797  TX Vref=32, minBit 3, minWin=28, winSum=457

  976 12:40:32.767442  [TxChooseVref] Worse bit 3, Min win 28, Win sum 457, Final Vref 32

  977 12:40:32.767977  

  978 12:40:32.770298  Final TX Range 1 Vref 32

  979 12:40:32.770835  

  980 12:40:32.771180  ==

  981 12:40:32.773603  Dram Type= 6, Freq= 0, CH_0, rank 0

  982 12:40:32.777584  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  983 12:40:32.778163  ==

  984 12:40:32.778516  

  985 12:40:32.780914  

  986 12:40:32.781444  	TX Vref Scan disable

  987 12:40:32.783938   == TX Byte 0 ==

  988 12:40:32.787439  Update DQ  dly =581 (2 ,1, 37)  DQ  OEN =(1 ,6)

  989 12:40:32.793731  Update DQM dly =581 (2 ,1, 37)  DQM OEN =(1 ,6)

  990 12:40:32.794327   == TX Byte 1 ==

  991 12:40:32.797269  Update DQ  dly =581 (2 ,1, 37)  DQ  OEN =(1 ,6)

  992 12:40:32.803479  Update DQM dly =581 (2 ,1, 37)  DQM OEN =(1 ,6)

  993 12:40:32.804025  

  994 12:40:32.804374  [DATLAT]

  995 12:40:32.804696  Freq=800, CH0 RK0

  996 12:40:32.805010  

  997 12:40:32.807435  DATLAT Default: 0xa

  998 12:40:32.807981  0, 0xFFFF, sum = 0

  999 12:40:32.810748  1, 0xFFFF, sum = 0

 1000 12:40:32.814014  2, 0xFFFF, sum = 0

 1001 12:40:32.814562  3, 0xFFFF, sum = 0

 1002 12:40:32.817376  4, 0xFFFF, sum = 0

 1003 12:40:32.817924  5, 0xFFFF, sum = 0

 1004 12:40:32.820436  6, 0xFFFF, sum = 0

 1005 12:40:32.820979  7, 0xFFFF, sum = 0

 1006 12:40:32.823687  8, 0xFFFF, sum = 0

 1007 12:40:32.824130  9, 0x0, sum = 1

 1008 12:40:32.826840  10, 0x0, sum = 2

 1009 12:40:32.827283  11, 0x0, sum = 3

 1010 12:40:32.827638  12, 0x0, sum = 4

 1011 12:40:32.830288  best_step = 10

 1012 12:40:32.830870  

 1013 12:40:32.831365  ==

 1014 12:40:32.833067  Dram Type= 6, Freq= 0, CH_0, rank 0

 1015 12:40:32.836648  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1016 12:40:32.837102  ==

 1017 12:40:32.840061  RX Vref Scan: 1

 1018 12:40:32.840495  

 1019 12:40:32.843507  Set Vref Range= 32 -> 127

 1020 12:40:32.843942  

 1021 12:40:32.844290  RX Vref 32 -> 127, step: 1

 1022 12:40:32.844615  

 1023 12:40:32.846641  RX Delay -79 -> 252, step: 8

 1024 12:40:32.847078  

 1025 12:40:32.850473  Set Vref, RX VrefLevel [Byte0]: 32

 1026 12:40:32.853769                           [Byte1]: 32

 1027 12:40:32.854330  

 1028 12:40:32.856684  Set Vref, RX VrefLevel [Byte0]: 33

 1029 12:40:32.860045                           [Byte1]: 33

 1030 12:40:32.864168  

 1031 12:40:32.864595  Set Vref, RX VrefLevel [Byte0]: 34

 1032 12:40:32.867426                           [Byte1]: 34

 1033 12:40:32.871570  

 1034 12:40:32.871996  Set Vref, RX VrefLevel [Byte0]: 35

 1035 12:40:32.874724                           [Byte1]: 35

 1036 12:40:32.879148  

 1037 12:40:32.879677  Set Vref, RX VrefLevel [Byte0]: 36

 1038 12:40:32.882305                           [Byte1]: 36

 1039 12:40:32.886710  

 1040 12:40:32.887234  Set Vref, RX VrefLevel [Byte0]: 37

 1041 12:40:32.890143                           [Byte1]: 37

 1042 12:40:32.894117  

 1043 12:40:32.894637  Set Vref, RX VrefLevel [Byte0]: 38

 1044 12:40:32.897591                           [Byte1]: 38

 1045 12:40:32.901852  

 1046 12:40:32.902414  Set Vref, RX VrefLevel [Byte0]: 39

 1047 12:40:32.905413                           [Byte1]: 39

 1048 12:40:32.909832  

 1049 12:40:32.910388  Set Vref, RX VrefLevel [Byte0]: 40

 1050 12:40:32.912688                           [Byte1]: 40

 1051 12:40:32.916622  

 1052 12:40:32.917063  Set Vref, RX VrefLevel [Byte0]: 41

 1053 12:40:32.920065                           [Byte1]: 41

 1054 12:40:32.924320  

 1055 12:40:32.924757  Set Vref, RX VrefLevel [Byte0]: 42

 1056 12:40:32.927649                           [Byte1]: 42

 1057 12:40:32.932247  

 1058 12:40:32.932716  Set Vref, RX VrefLevel [Byte0]: 43

 1059 12:40:32.935437                           [Byte1]: 43

 1060 12:40:32.939678  

 1061 12:40:32.940108  Set Vref, RX VrefLevel [Byte0]: 44

 1062 12:40:32.942999                           [Byte1]: 44

 1063 12:40:32.946956  

 1064 12:40:32.950426  Set Vref, RX VrefLevel [Byte0]: 45

 1065 12:40:32.950856                           [Byte1]: 45

 1066 12:40:32.954743  

 1067 12:40:32.955171  Set Vref, RX VrefLevel [Byte0]: 46

 1068 12:40:32.958010                           [Byte1]: 46

 1069 12:40:32.962175  

 1070 12:40:32.962695  Set Vref, RX VrefLevel [Byte0]: 47

 1071 12:40:32.965466                           [Byte1]: 47

 1072 12:40:32.969456  

 1073 12:40:32.969882  Set Vref, RX VrefLevel [Byte0]: 48

 1074 12:40:32.973170                           [Byte1]: 48

 1075 12:40:32.978031  

 1076 12:40:32.978550  Set Vref, RX VrefLevel [Byte0]: 49

 1077 12:40:32.980674                           [Byte1]: 49

 1078 12:40:32.984900  

 1079 12:40:32.985426  Set Vref, RX VrefLevel [Byte0]: 50

 1080 12:40:32.988088                           [Byte1]: 50

 1081 12:40:32.992331  

 1082 12:40:32.992860  Set Vref, RX VrefLevel [Byte0]: 51

 1083 12:40:32.995744                           [Byte1]: 51

 1084 12:40:32.999613  

 1085 12:40:33.000282  Set Vref, RX VrefLevel [Byte0]: 52

 1086 12:40:33.002993                           [Byte1]: 52

 1087 12:40:33.007344  

 1088 12:40:33.007771  Set Vref, RX VrefLevel [Byte0]: 53

 1089 12:40:33.010464                           [Byte1]: 53

 1090 12:40:33.014860  

 1091 12:40:33.015386  Set Vref, RX VrefLevel [Byte0]: 54

 1092 12:40:33.018161                           [Byte1]: 54

 1093 12:40:33.022340  

 1094 12:40:33.022862  Set Vref, RX VrefLevel [Byte0]: 55

 1095 12:40:33.025817                           [Byte1]: 55

 1096 12:40:33.030115  

 1097 12:40:33.030640  Set Vref, RX VrefLevel [Byte0]: 56

 1098 12:40:33.033213                           [Byte1]: 56

 1099 12:40:33.038055  

 1100 12:40:33.038575  Set Vref, RX VrefLevel [Byte0]: 57

 1101 12:40:33.041537                           [Byte1]: 57

 1102 12:40:33.045072  

 1103 12:40:33.045498  Set Vref, RX VrefLevel [Byte0]: 58

 1104 12:40:33.048663                           [Byte1]: 58

 1105 12:40:33.052930  

 1106 12:40:33.053458  Set Vref, RX VrefLevel [Byte0]: 59

 1107 12:40:33.055708                           [Byte1]: 59

 1108 12:40:33.060411  

 1109 12:40:33.060943  Set Vref, RX VrefLevel [Byte0]: 60

 1110 12:40:33.063572                           [Byte1]: 60

 1111 12:40:33.067800  

 1112 12:40:33.068336  Set Vref, RX VrefLevel [Byte0]: 61

 1113 12:40:33.071033                           [Byte1]: 61

 1114 12:40:33.075232  

 1115 12:40:33.075685  Set Vref, RX VrefLevel [Byte0]: 62

 1116 12:40:33.079055                           [Byte1]: 62

 1117 12:40:33.082938  

 1118 12:40:33.083559  Set Vref, RX VrefLevel [Byte0]: 63

 1119 12:40:33.086107                           [Byte1]: 63

 1120 12:40:33.090992  

 1121 12:40:33.091451  Set Vref, RX VrefLevel [Byte0]: 64

 1122 12:40:33.093505                           [Byte1]: 64

 1123 12:40:33.097859  

 1124 12:40:33.098622  Set Vref, RX VrefLevel [Byte0]: 65

 1125 12:40:33.101312                           [Byte1]: 65

 1126 12:40:33.105172  

 1127 12:40:33.105629  Set Vref, RX VrefLevel [Byte0]: 66

 1128 12:40:33.108658                           [Byte1]: 66

 1129 12:40:33.113424  

 1130 12:40:33.113856  Set Vref, RX VrefLevel [Byte0]: 67

 1131 12:40:33.116646                           [Byte1]: 67

 1132 12:40:33.121127  

 1133 12:40:33.121554  Set Vref, RX VrefLevel [Byte0]: 68

 1134 12:40:33.123713                           [Byte1]: 68

 1135 12:40:33.127964  

 1136 12:40:33.128391  Set Vref, RX VrefLevel [Byte0]: 69

 1137 12:40:33.131285                           [Byte1]: 69

 1138 12:40:33.135945  

 1139 12:40:33.136504  Set Vref, RX VrefLevel [Byte0]: 70

 1140 12:40:33.139481                           [Byte1]: 70

 1141 12:40:33.143413  

 1142 12:40:33.143957  Set Vref, RX VrefLevel [Byte0]: 71

 1143 12:40:33.146535                           [Byte1]: 71

 1144 12:40:33.150766  

 1145 12:40:33.151290  Set Vref, RX VrefLevel [Byte0]: 72

 1146 12:40:33.154084                           [Byte1]: 72

 1147 12:40:33.158728  

 1148 12:40:33.159157  Set Vref, RX VrefLevel [Byte0]: 73

 1149 12:40:33.161755                           [Byte1]: 73

 1150 12:40:33.165840  

 1151 12:40:33.166408  Set Vref, RX VrefLevel [Byte0]: 74

 1152 12:40:33.169371                           [Byte1]: 74

 1153 12:40:33.173061  

 1154 12:40:33.173487  Set Vref, RX VrefLevel [Byte0]: 75

 1155 12:40:33.176667                           [Byte1]: 75

 1156 12:40:33.180855  

 1157 12:40:33.181282  Set Vref, RX VrefLevel [Byte0]: 76

 1158 12:40:33.184562                           [Byte1]: 76

 1159 12:40:33.188650  

 1160 12:40:33.189178  Final RX Vref Byte 0 = 60 to rank0

 1161 12:40:33.191749  Final RX Vref Byte 1 = 59 to rank0

 1162 12:40:33.195108  Final RX Vref Byte 0 = 60 to rank1

 1163 12:40:33.199328  Final RX Vref Byte 1 = 59 to rank1==

 1164 12:40:33.202358  Dram Type= 6, Freq= 0, CH_0, rank 0

 1165 12:40:33.205314  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1166 12:40:33.208991  ==

 1167 12:40:33.209519  DQS Delay:

 1168 12:40:33.209861  DQS0 = 0, DQS1 = 0

 1169 12:40:33.212255  DQM Delay:

 1170 12:40:33.212783  DQM0 = 93, DQM1 = 82

 1171 12:40:33.215438  DQ Delay:

 1172 12:40:33.215972  DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88

 1173 12:40:33.219134  DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104

 1174 12:40:33.222163  DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80

 1175 12:40:33.225461  DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =92

 1176 12:40:33.228520  

 1177 12:40:33.228945  

 1178 12:40:33.235445  [DQSOSCAuto] RK0, (LSB)MR18= 0x3b37, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps

 1179 12:40:33.238859  CH0 RK0: MR19=606, MR18=3B37

 1180 12:40:33.245620  CH0_RK0: MR19=0x606, MR18=0x3B37, DQSOSC=394, MR23=63, INC=95, DEC=63

 1181 12:40:33.246189  

 1182 12:40:33.248732  ----->DramcWriteLeveling(PI) begin...

 1183 12:40:33.249181  ==

 1184 12:40:33.252140  Dram Type= 6, Freq= 0, CH_0, rank 1

 1185 12:40:33.255526  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1186 12:40:33.256034  ==

 1187 12:40:33.258786  Write leveling (Byte 0): 30 => 30

 1188 12:40:33.262493  Write leveling (Byte 1): 30 => 30

 1189 12:40:33.265495  DramcWriteLeveling(PI) end<-----

 1190 12:40:33.265923  

 1191 12:40:33.266291  ==

 1192 12:40:33.268906  Dram Type= 6, Freq= 0, CH_0, rank 1

 1193 12:40:33.272541  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1194 12:40:33.272979  ==

 1195 12:40:33.275471  [Gating] SW mode calibration

 1196 12:40:33.282360  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1197 12:40:33.288958  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1198 12:40:33.292320   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1199 12:40:33.295766   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)

 1200 12:40:33.302457   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1201 12:40:33.306384   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1202 12:40:33.309090   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1203 12:40:33.312318   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1204 12:40:33.319469   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1205 12:40:33.322627   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1206 12:40:33.366562   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1207 12:40:33.367189   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1208 12:40:33.368081   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1209 12:40:33.368483   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1210 12:40:33.368896   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1211 12:40:33.369371   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1212 12:40:33.369746   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1213 12:40:33.370294   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1214 12:40:33.370797   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1215 12:40:33.371194   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)

 1216 12:40:33.410768   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 1217 12:40:33.411408   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1218 12:40:33.412249   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1219 12:40:33.412657   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1220 12:40:33.413068   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1221 12:40:33.413466   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1222 12:40:33.413854   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1223 12:40:33.414370   0  9  4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 1224 12:40:33.414735   0  9  8 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)

 1225 12:40:33.415218   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1226 12:40:33.454874   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1227 12:40:33.455837   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1228 12:40:33.456259   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1229 12:40:33.456682   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1230 12:40:33.457082   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1231 12:40:33.457475   0 10  4 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)

 1232 12:40:33.457866   0 10  8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)

 1233 12:40:33.458396   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1234 12:40:33.458761   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1235 12:40:33.459244   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1236 12:40:33.460226   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1237 12:40:33.463718   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1238 12:40:33.467039   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1239 12:40:33.473349   0 11  4 | B1->B0 | 2424 3939 | 0 0 | (0 0) (0 0)

 1240 12:40:33.476841   0 11  8 | B1->B0 | 3c3c 4444 | 0 0 | (0 0) (0 0)

 1241 12:40:33.480328   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1242 12:40:33.483625   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1243 12:40:33.490803   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1244 12:40:33.493749   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1245 12:40:33.497087   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1246 12:40:33.504333   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1247 12:40:33.508128   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 1248 12:40:33.511686   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1249 12:40:33.515381   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1250 12:40:33.521843   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1251 12:40:33.525455   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1252 12:40:33.529334   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1253 12:40:33.532796   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1254 12:40:33.539345   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1255 12:40:33.543056   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1256 12:40:33.546324   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1257 12:40:33.550391   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1258 12:40:33.556502   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1259 12:40:33.559564   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1260 12:40:33.563440   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1261 12:40:33.570207   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1262 12:40:33.573518   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1263 12:40:33.577090   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 1264 12:40:33.583849   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 1265 12:40:33.584383  Total UI for P1: 0, mck2ui 16

 1266 12:40:33.589696  best dqsien dly found for B0: ( 0, 14,  4)

 1267 12:40:33.593402   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1268 12:40:33.597270  Total UI for P1: 0, mck2ui 16

 1269 12:40:33.600022  best dqsien dly found for B1: ( 0, 14,  6)

 1270 12:40:33.603028  best DQS0 dly(MCK, UI, PI) = (0, 14, 4)

 1271 12:40:33.606431  best DQS1 dly(MCK, UI, PI) = (0, 14, 6)

 1272 12:40:33.606914  

 1273 12:40:33.609883  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1274 12:40:33.613581  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)

 1275 12:40:33.616969  [Gating] SW calibration Done

 1276 12:40:33.617505  ==

 1277 12:40:33.619692  Dram Type= 6, Freq= 0, CH_0, rank 1

 1278 12:40:33.623189  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1279 12:40:33.623629  ==

 1280 12:40:33.626468  RX Vref Scan: 0

 1281 12:40:33.626920  

 1282 12:40:33.630024  RX Vref 0 -> 0, step: 1

 1283 12:40:33.630473  

 1284 12:40:33.630808  RX Delay -130 -> 252, step: 16

 1285 12:40:33.637386  iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240

 1286 12:40:33.639973  iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224

 1287 12:40:33.643720  iDelay=206, Bit 2, Center 93 (-18 ~ 205) 224

 1288 12:40:33.646998  iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224

 1289 12:40:33.650370  iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224

 1290 12:40:33.657025  iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224

 1291 12:40:33.660462  iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224

 1292 12:40:33.663846  iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224

 1293 12:40:33.666934  iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224

 1294 12:40:33.670273  iDelay=206, Bit 9, Center 69 (-34 ~ 173) 208

 1295 12:40:33.673679  iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224

 1296 12:40:33.680018  iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224

 1297 12:40:33.683596  iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224

 1298 12:40:33.686725  iDelay=206, Bit 13, Center 85 (-18 ~ 189) 208

 1299 12:40:33.690192  iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224

 1300 12:40:33.696885  iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224

 1301 12:40:33.697736  ==

 1302 12:40:33.700094  Dram Type= 6, Freq= 0, CH_0, rank 1

 1303 12:40:33.703344  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1304 12:40:33.703778  ==

 1305 12:40:33.704118  DQS Delay:

 1306 12:40:33.706568  DQS0 = 0, DQS1 = 0

 1307 12:40:33.706998  DQM Delay:

 1308 12:40:33.710282  DQM0 = 88, DQM1 = 81

 1309 12:40:33.710712  DQ Delay:

 1310 12:40:33.713694  DQ0 =85, DQ1 =93, DQ2 =93, DQ3 =77

 1311 12:40:33.716909  DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93

 1312 12:40:33.720299  DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77

 1313 12:40:33.723535  DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =93

 1314 12:40:33.724088  

 1315 12:40:33.724442  

 1316 12:40:33.724758  ==

 1317 12:40:33.726569  Dram Type= 6, Freq= 0, CH_0, rank 1

 1318 12:40:33.729918  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1319 12:40:33.730379  ==

 1320 12:40:33.730722  

 1321 12:40:33.731038  

 1322 12:40:33.733485  	TX Vref Scan disable

 1323 12:40:33.737100   == TX Byte 0 ==

 1324 12:40:33.740060  Update DQ  dly =581 (2 ,1, 37)  DQ  OEN =(1 ,6)

 1325 12:40:33.743551  Update DQM dly =581 (2 ,1, 37)  DQM OEN =(1 ,6)

 1326 12:40:33.746505   == TX Byte 1 ==

 1327 12:40:33.750599  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1328 12:40:33.753783  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1329 12:40:33.754244  ==

 1330 12:40:33.756939  Dram Type= 6, Freq= 0, CH_0, rank 1

 1331 12:40:33.760256  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1332 12:40:33.763507  ==

 1333 12:40:33.774531  TX Vref=22, minBit 8, minWin=27, winSum=444

 1334 12:40:33.778056  TX Vref=24, minBit 3, minWin=27, winSum=446

 1335 12:40:33.781546  TX Vref=26, minBit 3, minWin=27, winSum=446

 1336 12:40:33.785034  TX Vref=28, minBit 10, minWin=27, winSum=451

 1337 12:40:33.787941  TX Vref=30, minBit 8, minWin=27, winSum=452

 1338 12:40:33.791580  TX Vref=32, minBit 8, minWin=27, winSum=453

 1339 12:40:33.798248  [TxChooseVref] Worse bit 8, Min win 27, Win sum 453, Final Vref 32

 1340 12:40:33.798679  

 1341 12:40:33.801585  Final TX Range 1 Vref 32

 1342 12:40:33.802157  

 1343 12:40:33.802504  ==

 1344 12:40:33.804921  Dram Type= 6, Freq= 0, CH_0, rank 1

 1345 12:40:33.808227  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1346 12:40:33.808650  ==

 1347 12:40:33.808978  

 1348 12:40:33.811133  

 1349 12:40:33.811549  	TX Vref Scan disable

 1350 12:40:33.814403   == TX Byte 0 ==

 1351 12:40:33.817917  Update DQ  dly =581 (2 ,1, 37)  DQ  OEN =(1 ,6)

 1352 12:40:33.821326  Update DQM dly =581 (2 ,1, 37)  DQM OEN =(1 ,6)

 1353 12:40:33.824716   == TX Byte 1 ==

 1354 12:40:33.827902  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1355 12:40:33.831274  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1356 12:40:33.831639  

 1357 12:40:33.834742  [DATLAT]

 1358 12:40:33.835039  Freq=800, CH0 RK1

 1359 12:40:33.835275  

 1360 12:40:33.838061  DATLAT Default: 0xa

 1361 12:40:33.838362  0, 0xFFFF, sum = 0

 1362 12:40:33.841019  1, 0xFFFF, sum = 0

 1363 12:40:33.841325  2, 0xFFFF, sum = 0

 1364 12:40:33.844809  3, 0xFFFF, sum = 0

 1365 12:40:33.845200  4, 0xFFFF, sum = 0

 1366 12:40:33.848136  5, 0xFFFF, sum = 0

 1367 12:40:33.848439  6, 0xFFFF, sum = 0

 1368 12:40:33.851568  7, 0xFFFF, sum = 0

 1369 12:40:33.851984  8, 0xFFFF, sum = 0

 1370 12:40:33.855286  9, 0x0, sum = 1

 1371 12:40:33.855955  10, 0x0, sum = 2

 1372 12:40:33.857936  11, 0x0, sum = 3

 1373 12:40:33.858292  12, 0x0, sum = 4

 1374 12:40:33.861598  best_step = 10

 1375 12:40:33.861903  

 1376 12:40:33.862168  ==

 1377 12:40:33.864572  Dram Type= 6, Freq= 0, CH_0, rank 1

 1378 12:40:33.868036  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1379 12:40:33.868462  ==

 1380 12:40:33.871304  RX Vref Scan: 0

 1381 12:40:33.871722  

 1382 12:40:33.872046  RX Vref 0 -> 0, step: 1

 1383 12:40:33.872350  

 1384 12:40:33.875064  RX Delay -79 -> 252, step: 8

 1385 12:40:33.881757  iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224

 1386 12:40:33.885080  iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216

 1387 12:40:33.888191  iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224

 1388 12:40:33.891912  iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216

 1389 12:40:33.895011  iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216

 1390 12:40:33.901837  iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224

 1391 12:40:33.904989  iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216

 1392 12:40:33.908316  iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216

 1393 12:40:33.911844  iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208

 1394 12:40:33.915027  iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216

 1395 12:40:33.921570  iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208

 1396 12:40:33.924812  iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208

 1397 12:40:33.927953  iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216

 1398 12:40:33.931386  iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216

 1399 12:40:33.935584  iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216

 1400 12:40:33.941592  iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224

 1401 12:40:33.942486  ==

 1402 12:40:33.944815  Dram Type= 6, Freq= 0, CH_0, rank 1

 1403 12:40:33.948177  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1404 12:40:33.948596  ==

 1405 12:40:33.948926  DQS Delay:

 1406 12:40:33.951618  DQS0 = 0, DQS1 = 0

 1407 12:40:33.952133  DQM Delay:

 1408 12:40:33.955219  DQM0 = 90, DQM1 = 81

 1409 12:40:33.955736  DQ Delay:

 1410 12:40:33.958480  DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84

 1411 12:40:33.961852  DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100

 1412 12:40:33.965047  DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =80

 1413 12:40:33.968698  DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88

 1414 12:40:33.969216  

 1415 12:40:33.969548  

 1416 12:40:33.975186  [DQSOSCAuto] RK1, (LSB)MR18= 0x4720, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps

 1417 12:40:33.978799  CH0 RK1: MR19=606, MR18=4720

 1418 12:40:33.985266  CH0_RK1: MR19=0x606, MR18=0x4720, DQSOSC=392, MR23=63, INC=96, DEC=64

 1419 12:40:33.988539  [RxdqsGatingPostProcess] freq 800

 1420 12:40:33.995535  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 1421 12:40:33.996058  Pre-setting of DQS Precalculation

 1422 12:40:34.002630  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 1423 12:40:34.003161  ==

 1424 12:40:34.005426  Dram Type= 6, Freq= 0, CH_1, rank 0

 1425 12:40:34.008856  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1426 12:40:34.009378  ==

 1427 12:40:34.015507  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1428 12:40:34.021468  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1429 12:40:34.029444  [CA 0] Center 36 (6~67) winsize 62

 1430 12:40:34.033340  [CA 1] Center 36 (6~67) winsize 62

 1431 12:40:34.036432  [CA 2] Center 35 (5~65) winsize 61

 1432 12:40:34.039820  [CA 3] Center 34 (3~65) winsize 63

 1433 12:40:34.043206  [CA 4] Center 34 (4~65) winsize 62

 1434 12:40:34.046529  [CA 5] Center 33 (3~64) winsize 62

 1435 12:40:34.046958  

 1436 12:40:34.050054  [CmdBusTrainingLP45] Vref(ca) range 1: 30

 1437 12:40:34.050583  

 1438 12:40:34.053296  [CATrainingPosCal] consider 1 rank data

 1439 12:40:34.056530  u2DelayCellTimex100 = 270/100 ps

 1440 12:40:34.059856  CA0 delay=36 (6~67),Diff = 3 PI (21 cell)

 1441 12:40:34.063382  CA1 delay=36 (6~67),Diff = 3 PI (21 cell)

 1442 12:40:34.070565  CA2 delay=35 (5~65),Diff = 2 PI (14 cell)

 1443 12:40:34.073590  CA3 delay=34 (3~65),Diff = 1 PI (7 cell)

 1444 12:40:34.076774  CA4 delay=34 (4~65),Diff = 1 PI (7 cell)

 1445 12:40:34.079876  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 1446 12:40:34.080312  

 1447 12:40:34.083381  CA PerBit enable=1, Macro0, CA PI delay=33

 1448 12:40:34.083812  

 1449 12:40:34.086509  [CBTSetCACLKResult] CA Dly = 33

 1450 12:40:34.086936  CS Dly: 5 (0~36)

 1451 12:40:34.087276  ==

 1452 12:40:34.089808  Dram Type= 6, Freq= 0, CH_1, rank 1

 1453 12:40:34.096375  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1454 12:40:34.096896  ==

 1455 12:40:34.100080  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1456 12:40:34.106574  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1457 12:40:34.116085  [CA 0] Center 36 (6~67) winsize 62

 1458 12:40:34.118855  [CA 1] Center 37 (6~68) winsize 63

 1459 12:40:34.122454  [CA 2] Center 35 (5~66) winsize 62

 1460 12:40:34.125810  [CA 3] Center 34 (4~65) winsize 62

 1461 12:40:34.129171  [CA 4] Center 34 (4~65) winsize 62

 1462 12:40:34.132599  [CA 5] Center 34 (4~65) winsize 62

 1463 12:40:34.133057  

 1464 12:40:34.135887  [CmdBusTrainingLP45] Vref(ca) range 1: 32

 1465 12:40:34.136325  

 1466 12:40:34.139428  [CATrainingPosCal] consider 2 rank data

 1467 12:40:34.142522  u2DelayCellTimex100 = 270/100 ps

 1468 12:40:34.146213  CA0 delay=36 (6~67),Diff = 2 PI (14 cell)

 1469 12:40:34.149441  CA1 delay=36 (6~67),Diff = 2 PI (14 cell)

 1470 12:40:34.155592  CA2 delay=35 (5~65),Diff = 1 PI (7 cell)

 1471 12:40:34.158960  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 1472 12:40:34.162416  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 1473 12:40:34.166067  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 1474 12:40:34.166630  

 1475 12:40:34.169712  CA PerBit enable=1, Macro0, CA PI delay=34

 1476 12:40:34.170304  

 1477 12:40:34.173139  [CBTSetCACLKResult] CA Dly = 34

 1478 12:40:34.173562  CS Dly: 6 (0~38)

 1479 12:40:34.173897  

 1480 12:40:34.177125  ----->DramcWriteLeveling(PI) begin...

 1481 12:40:34.177693  ==

 1482 12:40:34.180739  Dram Type= 6, Freq= 0, CH_1, rank 0

 1483 12:40:34.184533  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1484 12:40:34.184962  ==

 1485 12:40:34.188856  Write leveling (Byte 0): 27 => 27

 1486 12:40:34.192089  Write leveling (Byte 1): 29 => 29

 1487 12:40:34.196087  DramcWriteLeveling(PI) end<-----

 1488 12:40:34.196528  

 1489 12:40:34.197032  ==

 1490 12:40:34.199634  Dram Type= 6, Freq= 0, CH_1, rank 0

 1491 12:40:34.203342  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1492 12:40:34.203769  ==

 1493 12:40:34.206516  [Gating] SW mode calibration

 1494 12:40:34.213492  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1495 12:40:34.216811  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1496 12:40:34.223595   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1497 12:40:34.226621   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1498 12:40:34.230195   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1499 12:40:34.233361   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1500 12:40:34.240590   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1501 12:40:34.243524   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1502 12:40:34.246723   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1503 12:40:34.253357   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1504 12:40:34.257006   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1505 12:40:34.260256   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1506 12:40:34.266330   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1507 12:40:34.270094   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1508 12:40:34.272991   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1509 12:40:34.279654   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1510 12:40:34.282982   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1511 12:40:34.286636   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

 1512 12:40:34.293538   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)

 1513 12:40:34.296533   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)

 1514 12:40:34.300377   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1515 12:40:34.303554   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1516 12:40:34.310321   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1517 12:40:34.313990   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1518 12:40:34.316887   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1519 12:40:34.323717   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1520 12:40:34.327077   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1521 12:40:34.329898   0  9  4 | B1->B0 | 2424 2727 | 0 0 | (1 1) (0 0)

 1522 12:40:34.336845   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1523 12:40:34.339958   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1524 12:40:34.343487   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1525 12:40:34.350152   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1526 12:40:34.353192   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1527 12:40:34.356629   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1528 12:40:34.363535   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 1529 12:40:34.366804   0 10  4 | B1->B0 | 2f2f 2c2c | 0 0 | (0 1) (1 1)

 1530 12:40:34.369930   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1531 12:40:34.376790   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1532 12:40:34.380415   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1533 12:40:34.383835   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1534 12:40:34.386882   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1535 12:40:34.393290   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1536 12:40:34.397313   0 11  0 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)

 1537 12:40:34.400558   0 11  4 | B1->B0 | 2d2d 3c3c | 0 0 | (1 1) (0 0)

 1538 12:40:34.407577   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1539 12:40:34.410398   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1540 12:40:34.413821   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1541 12:40:34.420404   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1542 12:40:34.424022   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1543 12:40:34.427086   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1544 12:40:34.433977   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1545 12:40:34.437799   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1546 12:40:34.440596   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1547 12:40:34.447427   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1548 12:40:34.450668   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1549 12:40:34.454100   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1550 12:40:34.457368   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1551 12:40:34.463838   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1552 12:40:34.467223   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1553 12:40:34.470823   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1554 12:40:34.477064   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1555 12:40:34.480653   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1556 12:40:34.483745   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1557 12:40:34.490317   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1558 12:40:34.493710   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1559 12:40:34.497247   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1560 12:40:34.503743   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 1561 12:40:34.507093   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1562 12:40:34.510569   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1563 12:40:34.514266  Total UI for P1: 0, mck2ui 16

 1564 12:40:34.517107  best dqsien dly found for B0: ( 0, 14,  6)

 1565 12:40:34.520650  Total UI for P1: 0, mck2ui 16

 1566 12:40:34.524034  best dqsien dly found for B1: ( 0, 14,  6)

 1567 12:40:34.527244  best DQS0 dly(MCK, UI, PI) = (0, 14, 6)

 1568 12:40:34.530781  best DQS1 dly(MCK, UI, PI) = (0, 14, 6)

 1569 12:40:34.530884  

 1570 12:40:34.533673  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)

 1571 12:40:34.540361  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)

 1572 12:40:34.540485  [Gating] SW calibration Done

 1573 12:40:34.540581  ==

 1574 12:40:34.543675  Dram Type= 6, Freq= 0, CH_1, rank 0

 1575 12:40:34.550674  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1576 12:40:34.550835  ==

 1577 12:40:34.550953  RX Vref Scan: 0

 1578 12:40:34.551064  

 1579 12:40:34.554408  RX Vref 0 -> 0, step: 1

 1580 12:40:34.554839  

 1581 12:40:34.557601  RX Delay -130 -> 252, step: 16

 1582 12:40:34.560675  iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224

 1583 12:40:34.563952  iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224

 1584 12:40:34.567409  iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224

 1585 12:40:34.574636  iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240

 1586 12:40:34.577427  iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224

 1587 12:40:34.580606  iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208

 1588 12:40:34.584275  iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240

 1589 12:40:34.587779  iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240

 1590 12:40:34.590836  iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240

 1591 12:40:34.597721  iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224

 1592 12:40:34.601059  iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240

 1593 12:40:34.604345  iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224

 1594 12:40:34.607872  iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240

 1595 12:40:34.610861  iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240

 1596 12:40:34.617547  iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240

 1597 12:40:34.621161  iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240

 1598 12:40:34.621596  ==

 1599 12:40:34.624131  Dram Type= 6, Freq= 0, CH_1, rank 0

 1600 12:40:34.627282  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1601 12:40:34.627593  ==

 1602 12:40:34.631202  DQS Delay:

 1603 12:40:34.631435  DQS0 = 0, DQS1 = 0

 1604 12:40:34.631618  DQM Delay:

 1605 12:40:34.634290  DQM0 = 89, DQM1 = 81

 1606 12:40:34.634567  DQ Delay:

 1607 12:40:34.637136  DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85

 1608 12:40:34.640895  DQ4 =93, DQ5 =101, DQ6 =101, DQ7 =85

 1609 12:40:34.644108  DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77

 1610 12:40:34.647244  DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85

 1611 12:40:34.647380  

 1612 12:40:34.647487  

 1613 12:40:34.647586  ==

 1614 12:40:34.650687  Dram Type= 6, Freq= 0, CH_1, rank 0

 1615 12:40:34.657416  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1616 12:40:34.657601  ==

 1617 12:40:34.657701  

 1618 12:40:34.657777  

 1619 12:40:34.657846  	TX Vref Scan disable

 1620 12:40:34.661133   == TX Byte 0 ==

 1621 12:40:34.664214  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 1622 12:40:34.667731  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 1623 12:40:34.671137   == TX Byte 1 ==

 1624 12:40:34.674884  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1625 12:40:34.677981  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1626 12:40:34.681573  ==

 1627 12:40:34.684714  Dram Type= 6, Freq= 0, CH_1, rank 0

 1628 12:40:34.687840  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1629 12:40:34.688292  ==

 1630 12:40:34.700165  TX Vref=22, minBit 8, minWin=27, winSum=447

 1631 12:40:34.703717  TX Vref=24, minBit 10, minWin=27, winSum=451

 1632 12:40:34.707127  TX Vref=26, minBit 15, minWin=27, winSum=454

 1633 12:40:34.710243  TX Vref=28, minBit 15, minWin=27, winSum=457

 1634 12:40:34.713821  TX Vref=30, minBit 8, minWin=28, winSum=457

 1635 12:40:34.720674  TX Vref=32, minBit 12, minWin=27, winSum=458

 1636 12:40:34.723768  [TxChooseVref] Worse bit 8, Min win 28, Win sum 457, Final Vref 30

 1637 12:40:34.724451  

 1638 12:40:34.727116  Final TX Range 1 Vref 30

 1639 12:40:34.727547  

 1640 12:40:34.727953  ==

 1641 12:40:34.730530  Dram Type= 6, Freq= 0, CH_1, rank 0

 1642 12:40:34.733618  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1643 12:40:34.734346  ==

 1644 12:40:34.737113  

 1645 12:40:34.737540  

 1646 12:40:34.737972  	TX Vref Scan disable

 1647 12:40:34.740728   == TX Byte 0 ==

 1648 12:40:34.744128  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 1649 12:40:34.747327  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 1650 12:40:34.751192   == TX Byte 1 ==

 1651 12:40:34.754763  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1652 12:40:34.757917  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1653 12:40:34.758382  

 1654 12:40:34.761513  [DATLAT]

 1655 12:40:34.761967  Freq=800, CH1 RK0

 1656 12:40:34.762322  

 1657 12:40:34.764811  DATLAT Default: 0xa

 1658 12:40:34.765236  0, 0xFFFF, sum = 0

 1659 12:40:34.767959  1, 0xFFFF, sum = 0

 1660 12:40:34.768268  2, 0xFFFF, sum = 0

 1661 12:40:34.771232  3, 0xFFFF, sum = 0

 1662 12:40:34.771538  4, 0xFFFF, sum = 0

 1663 12:40:34.774668  5, 0xFFFF, sum = 0

 1664 12:40:34.774901  6, 0xFFFF, sum = 0

 1665 12:40:34.777871  7, 0xFFFF, sum = 0

 1666 12:40:34.778085  8, 0xFFFF, sum = 0

 1667 12:40:34.781228  9, 0x0, sum = 1

 1668 12:40:34.781415  10, 0x0, sum = 2

 1669 12:40:34.784600  11, 0x0, sum = 3

 1670 12:40:34.784759  12, 0x0, sum = 4

 1671 12:40:34.788072  best_step = 10

 1672 12:40:34.788205  

 1673 12:40:34.788308  ==

 1674 12:40:34.791491  Dram Type= 6, Freq= 0, CH_1, rank 0

 1675 12:40:34.794289  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1676 12:40:34.794408  ==

 1677 12:40:34.794500  RX Vref Scan: 1

 1678 12:40:34.794586  

 1679 12:40:34.797970  Set Vref Range= 32 -> 127

 1680 12:40:34.798087  

 1681 12:40:34.801211  RX Vref 32 -> 127, step: 1

 1682 12:40:34.801327  

 1683 12:40:34.804566  RX Delay -95 -> 252, step: 8

 1684 12:40:34.804684  

 1685 12:40:34.808051  Set Vref, RX VrefLevel [Byte0]: 32

 1686 12:40:34.811445                           [Byte1]: 32

 1687 12:40:34.811562  

 1688 12:40:34.815018  Set Vref, RX VrefLevel [Byte0]: 33

 1689 12:40:34.817814                           [Byte1]: 33

 1690 12:40:34.817931  

 1691 12:40:34.821470  Set Vref, RX VrefLevel [Byte0]: 34

 1692 12:40:34.824599                           [Byte1]: 34

 1693 12:40:34.828408  

 1694 12:40:34.828551  Set Vref, RX VrefLevel [Byte0]: 35

 1695 12:40:34.831555                           [Byte1]: 35

 1696 12:40:34.835677  

 1697 12:40:34.835849  Set Vref, RX VrefLevel [Byte0]: 36

 1698 12:40:34.839019                           [Byte1]: 36

 1699 12:40:34.843347  

 1700 12:40:34.843569  Set Vref, RX VrefLevel [Byte0]: 37

 1701 12:40:34.847104                           [Byte1]: 37

 1702 12:40:34.851296  

 1703 12:40:34.851580  Set Vref, RX VrefLevel [Byte0]: 38

 1704 12:40:34.854842                           [Byte1]: 38

 1705 12:40:34.859362  

 1706 12:40:34.859961  Set Vref, RX VrefLevel [Byte0]: 39

 1707 12:40:34.862425                           [Byte1]: 39

 1708 12:40:34.866562  

 1709 12:40:34.867113  Set Vref, RX VrefLevel [Byte0]: 40

 1710 12:40:34.870193                           [Byte1]: 40

 1711 12:40:34.873985  

 1712 12:40:34.874433  Set Vref, RX VrefLevel [Byte0]: 41

 1713 12:40:34.877509                           [Byte1]: 41

 1714 12:40:34.881650  

 1715 12:40:34.882125  Set Vref, RX VrefLevel [Byte0]: 42

 1716 12:40:34.885009                           [Byte1]: 42

 1717 12:40:34.889028  

 1718 12:40:34.889468  Set Vref, RX VrefLevel [Byte0]: 43

 1719 12:40:34.892565                           [Byte1]: 43

 1720 12:40:34.896764  

 1721 12:40:34.897210  Set Vref, RX VrefLevel [Byte0]: 44

 1722 12:40:34.900574                           [Byte1]: 44

 1723 12:40:34.904492  

 1724 12:40:34.905014  Set Vref, RX VrefLevel [Byte0]: 45

 1725 12:40:34.907949                           [Byte1]: 45

 1726 12:40:34.912323  

 1727 12:40:34.912878  Set Vref, RX VrefLevel [Byte0]: 46

 1728 12:40:34.915178                           [Byte1]: 46

 1729 12:40:34.919504  

 1730 12:40:34.919933  Set Vref, RX VrefLevel [Byte0]: 47

 1731 12:40:34.923480                           [Byte1]: 47

 1732 12:40:34.927373  

 1733 12:40:34.927921  Set Vref, RX VrefLevel [Byte0]: 48

 1734 12:40:34.930372                           [Byte1]: 48

 1735 12:40:34.935132  

 1736 12:40:34.935749  Set Vref, RX VrefLevel [Byte0]: 49

 1737 12:40:34.938065                           [Byte1]: 49

 1738 12:40:34.942587  

 1739 12:40:34.943154  Set Vref, RX VrefLevel [Byte0]: 50

 1740 12:40:34.945670                           [Byte1]: 50

 1741 12:40:34.950001  

 1742 12:40:34.950532  Set Vref, RX VrefLevel [Byte0]: 51

 1743 12:40:34.954110                           [Byte1]: 51

 1744 12:40:34.958025  

 1745 12:40:34.958759  Set Vref, RX VrefLevel [Byte0]: 52

 1746 12:40:34.961156                           [Byte1]: 52

 1747 12:40:34.964990  

 1748 12:40:34.965877  Set Vref, RX VrefLevel [Byte0]: 53

 1749 12:40:34.968463                           [Byte1]: 53

 1750 12:40:34.972903  

 1751 12:40:34.973461  Set Vref, RX VrefLevel [Byte0]: 54

 1752 12:40:34.975783                           [Byte1]: 54

 1753 12:40:34.980621  

 1754 12:40:34.981201  Set Vref, RX VrefLevel [Byte0]: 55

 1755 12:40:34.984079                           [Byte1]: 55

 1756 12:40:34.988112  

 1757 12:40:34.988541  Set Vref, RX VrefLevel [Byte0]: 56

 1758 12:40:34.991619                           [Byte1]: 56

 1759 12:40:34.995528  

 1760 12:40:34.995952  Set Vref, RX VrefLevel [Byte0]: 57

 1761 12:40:34.999125                           [Byte1]: 57

 1762 12:40:35.003885  

 1763 12:40:35.004422  Set Vref, RX VrefLevel [Byte0]: 58

 1764 12:40:35.006582                           [Byte1]: 58

 1765 12:40:35.011003  

 1766 12:40:35.011527  Set Vref, RX VrefLevel [Byte0]: 59

 1767 12:40:35.014266                           [Byte1]: 59

 1768 12:40:35.018576  

 1769 12:40:35.019105  Set Vref, RX VrefLevel [Byte0]: 60

 1770 12:40:35.021879                           [Byte1]: 60

 1771 12:40:35.026245  

 1772 12:40:35.026773  Set Vref, RX VrefLevel [Byte0]: 61

 1773 12:40:35.029264                           [Byte1]: 61

 1774 12:40:35.033671  

 1775 12:40:35.034234  Set Vref, RX VrefLevel [Byte0]: 62

 1776 12:40:35.037256                           [Byte1]: 62

 1777 12:40:35.041279  

 1778 12:40:35.041806  Set Vref, RX VrefLevel [Byte0]: 63

 1779 12:40:35.044443                           [Byte1]: 63

 1780 12:40:35.049041  

 1781 12:40:35.049560  Set Vref, RX VrefLevel [Byte0]: 64

 1782 12:40:35.052192                           [Byte1]: 64

 1783 12:40:35.056699  

 1784 12:40:35.057119  Set Vref, RX VrefLevel [Byte0]: 65

 1785 12:40:35.059442                           [Byte1]: 65

 1786 12:40:35.064088  

 1787 12:40:35.064569  Set Vref, RX VrefLevel [Byte0]: 66

 1788 12:40:35.067096                           [Byte1]: 66

 1789 12:40:35.071534  

 1790 12:40:35.071849  Set Vref, RX VrefLevel [Byte0]: 67

 1791 12:40:35.074545                           [Byte1]: 67

 1792 12:40:35.079073  

 1793 12:40:35.079254  Set Vref, RX VrefLevel [Byte0]: 68

 1794 12:40:35.082326                           [Byte1]: 68

 1795 12:40:35.086783  

 1796 12:40:35.087050  Set Vref, RX VrefLevel [Byte0]: 69

 1797 12:40:35.090319                           [Byte1]: 69

 1798 12:40:35.094397  

 1799 12:40:35.094669  Set Vref, RX VrefLevel [Byte0]: 70

 1800 12:40:35.097575                           [Byte1]: 70

 1801 12:40:35.101904  

 1802 12:40:35.102196  Set Vref, RX VrefLevel [Byte0]: 71

 1803 12:40:35.105283                           [Byte1]: 71

 1804 12:40:35.109244  

 1805 12:40:35.109470  Set Vref, RX VrefLevel [Byte0]: 72

 1806 12:40:35.113181                           [Byte1]: 72

 1807 12:40:35.117211  

 1808 12:40:35.117561  Set Vref, RX VrefLevel [Byte0]: 73

 1809 12:40:35.120375                           [Byte1]: 73

 1810 12:40:35.124745  

 1811 12:40:35.125257  Set Vref, RX VrefLevel [Byte0]: 74

 1812 12:40:35.128202                           [Byte1]: 74

 1813 12:40:35.132604  

 1814 12:40:35.133031  Set Vref, RX VrefLevel [Byte0]: 75

 1815 12:40:35.135360                           [Byte1]: 75

 1816 12:40:35.139677  

 1817 12:40:35.140100  Set Vref, RX VrefLevel [Byte0]: 76

 1818 12:40:35.143348                           [Byte1]: 76

 1819 12:40:35.147498  

 1820 12:40:35.147999  Set Vref, RX VrefLevel [Byte0]: 77

 1821 12:40:35.150246                           [Byte1]: 77

 1822 12:40:35.154639  

 1823 12:40:35.154722  Set Vref, RX VrefLevel [Byte0]: 78

 1824 12:40:35.158239                           [Byte1]: 78

 1825 12:40:35.162507  

 1826 12:40:35.163097  Final RX Vref Byte 0 = 51 to rank0

 1827 12:40:35.166211  Final RX Vref Byte 1 = 63 to rank0

 1828 12:40:35.169486  Final RX Vref Byte 0 = 51 to rank1

 1829 12:40:35.172942  Final RX Vref Byte 1 = 63 to rank1==

 1830 12:40:35.175953  Dram Type= 6, Freq= 0, CH_1, rank 0

 1831 12:40:35.182853  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1832 12:40:35.183410  ==

 1833 12:40:35.183857  DQS Delay:

 1834 12:40:35.184308  DQS0 = 0, DQS1 = 0

 1835 12:40:35.186370  DQM Delay:

 1836 12:40:35.186792  DQM0 = 92, DQM1 = 83

 1837 12:40:35.189730  DQ Delay:

 1838 12:40:35.193080  DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88

 1839 12:40:35.193602  DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =88

 1840 12:40:35.196398  DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80

 1841 12:40:35.202676  DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88

 1842 12:40:35.203197  

 1843 12:40:35.203532  

 1844 12:40:35.210298  [DQSOSCAuto] RK0, (LSB)MR18= 0x3452, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps

 1845 12:40:35.214116  CH1 RK0: MR19=606, MR18=3452

 1846 12:40:35.219647  CH1_RK0: MR19=0x606, MR18=0x3452, DQSOSC=389, MR23=63, INC=97, DEC=65

 1847 12:40:35.220121  

 1848 12:40:35.222815  ----->DramcWriteLeveling(PI) begin...

 1849 12:40:35.223289  ==

 1850 12:40:35.226386  Dram Type= 6, Freq= 0, CH_1, rank 1

 1851 12:40:35.229702  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1852 12:40:35.230207  ==

 1853 12:40:35.232968  Write leveling (Byte 0): 27 => 27

 1854 12:40:35.236162  Write leveling (Byte 1): 28 => 28

 1855 12:40:35.239756  DramcWriteLeveling(PI) end<-----

 1856 12:40:35.240183  

 1857 12:40:35.240519  ==

 1858 12:40:35.242820  Dram Type= 6, Freq= 0, CH_1, rank 1

 1859 12:40:35.246420  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1860 12:40:35.246725  ==

 1861 12:40:35.249535  [Gating] SW mode calibration

 1862 12:40:35.256770  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1863 12:40:35.263600  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1864 12:40:35.266496   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1865 12:40:35.269625   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1866 12:40:35.276672   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1867 12:40:35.280151   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1868 12:40:35.283255   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1869 12:40:35.290057   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1870 12:40:35.293831   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1871 12:40:35.296871   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1872 12:40:35.299803   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1873 12:40:35.306373   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1874 12:40:35.309468   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1875 12:40:35.313223   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1876 12:40:35.319881   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1877 12:40:35.322984   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1878 12:40:35.326273   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1879 12:40:35.333228   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1880 12:40:35.336419   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

 1881 12:40:35.340198   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1882 12:40:35.346468   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1883 12:40:35.350013   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1884 12:40:35.353475   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1885 12:40:35.359942   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1886 12:40:35.363209   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1887 12:40:35.366799   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1888 12:40:35.373648   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1889 12:40:35.376765   0  9  4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 1890 12:40:35.380054   0  9  8 | B1->B0 | 3333 3333 | 1 0 | (1 1) (0 0)

 1891 12:40:35.383289   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1892 12:40:35.389806   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1893 12:40:35.393411   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1894 12:40:35.396277   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1895 12:40:35.403539   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1896 12:40:35.406833   0 10  0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)

 1897 12:40:35.410027   0 10  4 | B1->B0 | 2f2f 2f2f | 1 0 | (1 1) (0 0)

 1898 12:40:35.416978   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

 1899 12:40:35.420318   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1900 12:40:35.423436   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1901 12:40:35.430124   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1902 12:40:35.433442   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1903 12:40:35.436859   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1904 12:40:35.443630   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1905 12:40:35.446665   0 11  4 | B1->B0 | 2c2c 3131 | 0 0 | (0 0) (0 0)

 1906 12:40:35.450951   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1907 12:40:35.456585   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1908 12:40:35.460096   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1909 12:40:35.463247   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1910 12:40:35.470098   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1911 12:40:35.473278   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1912 12:40:35.476463   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1913 12:40:35.479772   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 1914 12:40:35.486522   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1915 12:40:35.490024   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1916 12:40:35.493343   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1917 12:40:35.500143   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1918 12:40:35.503153   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1919 12:40:35.506992   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1920 12:40:35.513214   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1921 12:40:35.517174   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1922 12:40:35.520138   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1923 12:40:35.526660   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1924 12:40:35.529986   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1925 12:40:35.533420   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1926 12:40:35.540747   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1927 12:40:35.543400   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1928 12:40:35.547261   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1929 12:40:35.550275   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 1930 12:40:35.554110  Total UI for P1: 0, mck2ui 16

 1931 12:40:35.556903  best dqsien dly found for B0: ( 0, 14,  2)

 1932 12:40:35.563522   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 1933 12:40:35.567129   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1934 12:40:35.570128  Total UI for P1: 0, mck2ui 16

 1935 12:40:35.573542  best dqsien dly found for B1: ( 0, 14,  6)

 1936 12:40:35.577523  best DQS0 dly(MCK, UI, PI) = (0, 14, 2)

 1937 12:40:35.580438  best DQS1 dly(MCK, UI, PI) = (0, 14, 6)

 1938 12:40:35.580872  

 1939 12:40:35.583526  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)

 1940 12:40:35.587253  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)

 1941 12:40:35.590475  [Gating] SW calibration Done

 1942 12:40:35.590806  ==

 1943 12:40:35.593472  Dram Type= 6, Freq= 0, CH_1, rank 1

 1944 12:40:35.597175  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1945 12:40:35.597409  ==

 1946 12:40:35.600265  RX Vref Scan: 0

 1947 12:40:35.600451  

 1948 12:40:35.603877  RX Vref 0 -> 0, step: 1

 1949 12:40:35.604151  

 1950 12:40:35.607153  RX Delay -130 -> 252, step: 16

 1951 12:40:35.610755  iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224

 1952 12:40:35.613806  iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208

 1953 12:40:35.617393  iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224

 1954 12:40:35.620560  iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224

 1955 12:40:35.623948  iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224

 1956 12:40:35.630452  iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224

 1957 12:40:35.634145  iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224

 1958 12:40:35.637581  iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208

 1959 12:40:35.640919  iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240

 1960 12:40:35.644059  iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224

 1961 12:40:35.650591  iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240

 1962 12:40:35.654095  iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224

 1963 12:40:35.657668  iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224

 1964 12:40:35.661215  iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224

 1965 12:40:35.663781  iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240

 1966 12:40:35.670603  iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224

 1967 12:40:35.670689  ==

 1968 12:40:35.673852  Dram Type= 6, Freq= 0, CH_1, rank 1

 1969 12:40:35.677392  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1970 12:40:35.677828  ==

 1971 12:40:35.678214  DQS Delay:

 1972 12:40:35.680904  DQS0 = 0, DQS1 = 0

 1973 12:40:35.681452  DQM Delay:

 1974 12:40:35.684024  DQM0 = 89, DQM1 = 84

 1975 12:40:35.684455  DQ Delay:

 1976 12:40:35.687475  DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93

 1977 12:40:35.690620  DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85

 1978 12:40:35.694119  DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77

 1979 12:40:35.697849  DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93

 1980 12:40:35.698418  

 1981 12:40:35.698763  

 1982 12:40:35.699080  ==

 1983 12:40:35.700707  Dram Type= 6, Freq= 0, CH_1, rank 1

 1984 12:40:35.704406  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1985 12:40:35.704947  ==

 1986 12:40:35.705294  

 1987 12:40:35.707492  

 1988 12:40:35.708029  	TX Vref Scan disable

 1989 12:40:35.711175   == TX Byte 0 ==

 1990 12:40:35.714448  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1991 12:40:35.717818  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1992 12:40:35.720840   == TX Byte 1 ==

 1993 12:40:35.724042  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1994 12:40:35.728010  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1995 12:40:35.728624  ==

 1996 12:40:35.730699  Dram Type= 6, Freq= 0, CH_1, rank 1

 1997 12:40:35.737119  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1998 12:40:35.737599  ==

 1999 12:40:35.749086  TX Vref=22, minBit 13, minWin=27, winSum=455

 2000 12:40:35.752220  TX Vref=24, minBit 1, minWin=28, winSum=455

 2001 12:40:35.755647  TX Vref=26, minBit 9, minWin=28, winSum=458

 2002 12:40:35.758796  TX Vref=28, minBit 8, minWin=28, winSum=461

 2003 12:40:35.762163  TX Vref=30, minBit 8, minWin=28, winSum=458

 2004 12:40:35.765471  TX Vref=32, minBit 8, minWin=28, winSum=458

 2005 12:40:35.772234  [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 28

 2006 12:40:35.772435  

 2007 12:40:35.775387  Final TX Range 1 Vref 28

 2008 12:40:35.775558  

 2009 12:40:35.775682  ==

 2010 12:40:35.778773  Dram Type= 6, Freq= 0, CH_1, rank 1

 2011 12:40:35.782265  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2012 12:40:35.782439  ==

 2013 12:40:35.782565  

 2014 12:40:35.782679  

 2015 12:40:35.785492  	TX Vref Scan disable

 2016 12:40:35.789155   == TX Byte 0 ==

 2017 12:40:35.792503  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 2018 12:40:35.796046  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 2019 12:40:35.799041   == TX Byte 1 ==

 2020 12:40:35.802302  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 2021 12:40:35.806447  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 2022 12:40:35.806716  

 2023 12:40:35.809402  [DATLAT]

 2024 12:40:35.809701  Freq=800, CH1 RK1

 2025 12:40:35.809878  

 2026 12:40:35.812513  DATLAT Default: 0xa

 2027 12:40:35.812857  0, 0xFFFF, sum = 0

 2028 12:40:35.815785  1, 0xFFFF, sum = 0

 2029 12:40:35.816049  2, 0xFFFF, sum = 0

 2030 12:40:35.818826  3, 0xFFFF, sum = 0

 2031 12:40:35.818912  4, 0xFFFF, sum = 0

 2032 12:40:35.822297  5, 0xFFFF, sum = 0

 2033 12:40:35.822383  6, 0xFFFF, sum = 0

 2034 12:40:35.825464  7, 0xFFFF, sum = 0

 2035 12:40:35.825550  8, 0xFFFF, sum = 0

 2036 12:40:35.829453  9, 0x0, sum = 1

 2037 12:40:35.829539  10, 0x0, sum = 2

 2038 12:40:35.832288  11, 0x0, sum = 3

 2039 12:40:35.832374  12, 0x0, sum = 4

 2040 12:40:35.835511  best_step = 10

 2041 12:40:35.835595  

 2042 12:40:35.835662  ==

 2043 12:40:35.838900  Dram Type= 6, Freq= 0, CH_1, rank 1

 2044 12:40:35.842327  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2045 12:40:35.842411  ==

 2046 12:40:35.846019  RX Vref Scan: 0

 2047 12:40:35.846184  

 2048 12:40:35.846259  RX Vref 0 -> 0, step: 1

 2049 12:40:35.846328  

 2050 12:40:35.849661  RX Delay -95 -> 252, step: 8

 2051 12:40:35.855574  iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208

 2052 12:40:35.859467  iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208

 2053 12:40:35.862879  iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208

 2054 12:40:35.865782  iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208

 2055 12:40:35.869082  iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216

 2056 12:40:35.872616  iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216

 2057 12:40:35.879641  iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208

 2058 12:40:35.882387  iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208

 2059 12:40:35.885790  iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216

 2060 12:40:35.889013  iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216

 2061 12:40:35.892724  iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224

 2062 12:40:35.899365  iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224

 2063 12:40:35.902386  iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216

 2064 12:40:35.905667  iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224

 2065 12:40:35.908849  iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224

 2066 12:40:35.912419  iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224

 2067 12:40:35.915594  ==

 2068 12:40:35.919022  Dram Type= 6, Freq= 0, CH_1, rank 1

 2069 12:40:35.922444  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2070 12:40:35.922533  ==

 2071 12:40:35.922601  DQS Delay:

 2072 12:40:35.925723  DQS0 = 0, DQS1 = 0

 2073 12:40:35.925807  DQM Delay:

 2074 12:40:35.929173  DQM0 = 91, DQM1 = 84

 2075 12:40:35.929259  DQ Delay:

 2076 12:40:35.933063  DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88

 2077 12:40:35.935568  DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88

 2078 12:40:35.939162  DQ8 =68, DQ9 =76, DQ10 =88, DQ11 =80

 2079 12:40:35.942319  DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =96

 2080 12:40:35.942482  

 2081 12:40:35.942571  

 2082 12:40:35.949390  [DQSOSCAuto] RK1, (LSB)MR18= 0x370d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps

 2083 12:40:35.952504  CH1 RK1: MR19=606, MR18=370D

 2084 12:40:35.959348  CH1_RK1: MR19=0x606, MR18=0x370D, DQSOSC=395, MR23=63, INC=94, DEC=63

 2085 12:40:35.962886  [RxdqsGatingPostProcess] freq 800

 2086 12:40:35.966220  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 2087 12:40:35.969253  Pre-setting of DQS Precalculation

 2088 12:40:35.975697  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 2089 12:40:35.982276  sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4

 2090 12:40:35.989398  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 2091 12:40:35.989892  

 2092 12:40:35.990268  

 2093 12:40:35.993092  [Calibration Summary] 1600 Mbps

 2094 12:40:35.993567  CH 0, Rank 0

 2095 12:40:35.996170  SW Impedance     : PASS

 2096 12:40:35.999298  DUTY Scan        : NO K

 2097 12:40:35.999776  ZQ Calibration   : PASS

 2098 12:40:36.002648  Jitter Meter     : NO K

 2099 12:40:36.005691  CBT Training     : PASS

 2100 12:40:36.006197  Write leveling   : PASS

 2101 12:40:36.009122  RX DQS gating    : PASS

 2102 12:40:36.012681  RX DQ/DQS(RDDQC) : PASS

 2103 12:40:36.013112  TX DQ/DQS        : PASS

 2104 12:40:36.015882  RX DATLAT        : PASS

 2105 12:40:36.019122  RX DQ/DQS(Engine): PASS

 2106 12:40:36.019431  TX OE            : NO K

 2107 12:40:36.022487  All Pass.

 2108 12:40:36.022772  

 2109 12:40:36.022953  CH 0, Rank 1

 2110 12:40:36.025931  SW Impedance     : PASS

 2111 12:40:36.026180  DUTY Scan        : NO K

 2112 12:40:36.029350  ZQ Calibration   : PASS

 2113 12:40:36.032495  Jitter Meter     : NO K

 2114 12:40:36.032876  CBT Training     : PASS

 2115 12:40:36.035585  Write leveling   : PASS

 2116 12:40:36.039214  RX DQS gating    : PASS

 2117 12:40:36.039562  RX DQ/DQS(RDDQC) : PASS

 2118 12:40:36.042209  TX DQ/DQS        : PASS

 2119 12:40:36.042469  RX DATLAT        : PASS

 2120 12:40:36.045781  RX DQ/DQS(Engine): PASS

 2121 12:40:36.049583  TX OE            : NO K

 2122 12:40:36.049928  All Pass.

 2123 12:40:36.050171  

 2124 12:40:36.050362  CH 1, Rank 0

 2125 12:40:36.053205  SW Impedance     : PASS

 2126 12:40:36.055840  DUTY Scan        : NO K

 2127 12:40:36.056184  ZQ Calibration   : PASS

 2128 12:40:36.059315  Jitter Meter     : NO K

 2129 12:40:36.062511  CBT Training     : PASS

 2130 12:40:36.062911  Write leveling   : PASS

 2131 12:40:36.066288  RX DQS gating    : PASS

 2132 12:40:36.069893  RX DQ/DQS(RDDQC) : PASS

 2133 12:40:36.070915  TX DQ/DQS        : PASS

 2134 12:40:36.073201  RX DATLAT        : PASS

 2135 12:40:36.073979  RX DQ/DQS(Engine): PASS

 2136 12:40:36.076420  TX OE            : NO K

 2137 12:40:36.076987  All Pass.

 2138 12:40:36.077380  

 2139 12:40:36.079506  CH 1, Rank 1

 2140 12:40:36.080104  SW Impedance     : PASS

 2141 12:40:36.082700  DUTY Scan        : NO K

 2142 12:40:36.086092  ZQ Calibration   : PASS

 2143 12:40:36.086677  Jitter Meter     : NO K

 2144 12:40:36.089383  CBT Training     : PASS

 2145 12:40:36.092955  Write leveling   : PASS

 2146 12:40:36.093548  RX DQS gating    : PASS

 2147 12:40:36.096270  RX DQ/DQS(RDDQC) : PASS

 2148 12:40:36.099646  TX DQ/DQS        : PASS

 2149 12:40:36.099981  RX DATLAT        : PASS

 2150 12:40:36.102946  RX DQ/DQS(Engine): PASS

 2151 12:40:36.106276  TX OE            : NO K

 2152 12:40:36.106523  All Pass.

 2153 12:40:36.106717  

 2154 12:40:36.106901  DramC Write-DBI off

 2155 12:40:36.109527  	PER_BANK_REFRESH: Hybrid Mode

 2156 12:40:36.112686  TX_TRACKING: ON

 2157 12:40:36.116093  [GetDramInforAfterCalByMRR] Vendor 6.

 2158 12:40:36.120136  [GetDramInforAfterCalByMRR] Revision 606.

 2159 12:40:36.122982  [GetDramInforAfterCalByMRR] Revision 2 0.

 2160 12:40:36.123165  MR0 0x3b3b

 2161 12:40:36.123286  MR8 0x5151

 2162 12:40:36.129781  RK0, DieNum 2, Density 16Gb, RKsize 32Gb.

 2163 12:40:36.130011  

 2164 12:40:36.130136  MR0 0x3b3b

 2165 12:40:36.130246  MR8 0x5151

 2166 12:40:36.133256  RK1, DieNum 2, Density 16Gb, RKsize 32Gb.

 2167 12:40:36.133739  

 2168 12:40:36.143151  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 2169 12:40:36.146476  [FAST_K] Save calibration result to emmc

 2170 12:40:36.150039  [FAST_K] Save calibration result to emmc

 2171 12:40:36.153219  dram_init: config_dvfs: 1

 2172 12:40:36.156393  dramc_set_vcore_voltage set vcore to 662500

 2173 12:40:36.159891  Read voltage for 1200, 2

 2174 12:40:36.160368  Vio18 = 0

 2175 12:40:36.160743  Vcore = 662500

 2176 12:40:36.163430  Vdram = 0

 2177 12:40:36.163902  Vddq = 0

 2178 12:40:36.164277  Vmddr = 0

 2179 12:40:36.169801  [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0

 2180 12:40:36.173242  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 2181 12:40:36.176393  MEM_TYPE=3, freq_sel=15

 2182 12:40:36.179608  sv_algorithm_assistance_LP4_1600 

 2183 12:40:36.182845  ============ PULL DRAM RESETB DOWN ============

 2184 12:40:36.189277  ========== PULL DRAM RESETB DOWN end =========

 2185 12:40:36.192845  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2186 12:40:36.196023  =================================== 

 2187 12:40:36.199477  LPDDR4 DRAM CONFIGURATION

 2188 12:40:36.203230  =================================== 

 2189 12:40:36.203395  EX_ROW_EN[0]    = 0x0

 2190 12:40:36.206122  EX_ROW_EN[1]    = 0x0

 2191 12:40:36.206261  LP4Y_EN      = 0x0

 2192 12:40:36.210288  WORK_FSP     = 0x0

 2193 12:40:36.210724  WL           = 0x4

 2194 12:40:36.213548  RL           = 0x4

 2195 12:40:36.214137  BL           = 0x2

 2196 12:40:36.216567  RPST         = 0x0

 2197 12:40:36.216999  RD_PRE       = 0x0

 2198 12:40:36.219959  WR_PRE       = 0x1

 2199 12:40:36.220510  WR_PST       = 0x0

 2200 12:40:36.223105  DBI_WR       = 0x0

 2201 12:40:36.223540  DBI_RD       = 0x0

 2202 12:40:36.226808  OTF          = 0x1

 2203 12:40:36.230178  =================================== 

 2204 12:40:36.233325  =================================== 

 2205 12:40:36.233760  ANA top config

 2206 12:40:36.236936  =================================== 

 2207 12:40:36.240191  DLL_ASYNC_EN            =  0

 2208 12:40:36.243349  ALL_SLAVE_EN            =  0

 2209 12:40:36.246698  NEW_RANK_MODE           =  1

 2210 12:40:36.247134  DLL_IDLE_MODE           =  1

 2211 12:40:36.249859  LP45_APHY_COMB_EN       =  1

 2212 12:40:36.253234  TX_ODT_DIS              =  1

 2213 12:40:36.256892  NEW_8X_MODE             =  1

 2214 12:40:36.259909  =================================== 

 2215 12:40:36.263722  =================================== 

 2216 12:40:36.264156  data_rate                  = 2400

 2217 12:40:36.266633  CKR                        = 1

 2218 12:40:36.269625  DQ_P2S_RATIO               = 8

 2219 12:40:36.272962  =================================== 

 2220 12:40:36.276496  CA_P2S_RATIO               = 8

 2221 12:40:36.279787  DQ_CA_OPEN                 = 0

 2222 12:40:36.283101  DQ_SEMI_OPEN               = 0

 2223 12:40:36.283258  CA_SEMI_OPEN               = 0

 2224 12:40:36.286436  CA_FULL_RATE               = 0

 2225 12:40:36.289841  DQ_CKDIV4_EN               = 0

 2226 12:40:36.293113  CA_CKDIV4_EN               = 0

 2227 12:40:36.296171  CA_PREDIV_EN               = 0

 2228 12:40:36.299339  PH8_DLY                    = 17

 2229 12:40:36.303113  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 2230 12:40:36.303328  DQ_AAMCK_DIV               = 4

 2231 12:40:36.306725  CA_AAMCK_DIV               = 4

 2232 12:40:36.309933  CA_ADMCK_DIV               = 4

 2233 12:40:36.312786  DQ_TRACK_CA_EN             = 0

 2234 12:40:36.316277  CA_PICK                    = 1200

 2235 12:40:36.319553  CA_MCKIO                   = 1200

 2236 12:40:36.319801  MCKIO_SEMI                 = 0

 2237 12:40:36.323324  PLL_FREQ                   = 2366

 2238 12:40:36.326160  DQ_UI_PI_RATIO             = 32

 2239 12:40:36.329643  CA_UI_PI_RATIO             = 0

 2240 12:40:36.332893  =================================== 

 2241 12:40:36.335987  =================================== 

 2242 12:40:36.339494  memory_type:LPDDR4         

 2243 12:40:36.339727  GP_NUM     : 10       

 2244 12:40:36.342825  SRAM_EN    : 1       

 2245 12:40:36.345895  MD32_EN    : 0       

 2246 12:40:36.349335  =================================== 

 2247 12:40:36.349568  [ANA_INIT] >>>>>>>>>>>>>> 

 2248 12:40:36.352633  <<<<<< [CONFIGURE PHASE]: ANA_TX

 2249 12:40:36.356107  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 2250 12:40:36.359233  =================================== 

 2251 12:40:36.362577  data_rate = 2400,PCW = 0X5b00

 2252 12:40:36.366280  =================================== 

 2253 12:40:36.369727  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 2254 12:40:36.376709  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2255 12:40:36.379930  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2256 12:40:36.386866  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 2257 12:40:36.389754  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 2258 12:40:36.393461  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 2259 12:40:36.393967  [ANA_INIT] flow start 

 2260 12:40:36.396866  [ANA_INIT] PLL >>>>>>>> 

 2261 12:40:36.400064  [ANA_INIT] PLL <<<<<<<< 

 2262 12:40:36.400654  [ANA_INIT] MIDPI >>>>>>>> 

 2263 12:40:36.403292  [ANA_INIT] MIDPI <<<<<<<< 

 2264 12:40:36.406807  [ANA_INIT] DLL >>>>>>>> 

 2265 12:40:36.407281  [ANA_INIT] DLL <<<<<<<< 

 2266 12:40:36.409922  [ANA_INIT] flow end 

 2267 12:40:36.413510  ============ LP4 DIFF to SE enter ============

 2268 12:40:36.416728  ============ LP4 DIFF to SE exit  ============

 2269 12:40:36.419915  [ANA_INIT] <<<<<<<<<<<<< 

 2270 12:40:36.423298  [Flow] Enable top DCM control >>>>> 

 2271 12:40:36.426534  [Flow] Enable top DCM control <<<<< 

 2272 12:40:36.429905  Enable DLL master slave shuffle 

 2273 12:40:36.436471  ============================================================== 

 2274 12:40:36.436909  Gating Mode config

 2275 12:40:36.442601  ============================================================== 

 2276 12:40:36.442687  Config description: 

 2277 12:40:36.453142  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 2278 12:40:36.460166  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 2279 12:40:36.466849  SELPH_MODE            0: By rank         1: By Phase 

 2280 12:40:36.470315  ============================================================== 

 2281 12:40:36.473296  GAT_TRACK_EN                 =  1

 2282 12:40:36.477029  RX_GATING_MODE               =  2

 2283 12:40:36.480064  RX_GATING_TRACK_MODE         =  2

 2284 12:40:36.483436  SELPH_MODE                   =  1

 2285 12:40:36.487431  PICG_EARLY_EN                =  1

 2286 12:40:36.490182  VALID_LAT_VALUE              =  1

 2287 12:40:36.496744  ============================================================== 

 2288 12:40:36.499772  Enter into Gating configuration >>>> 

 2289 12:40:36.503191  Exit from Gating configuration <<<< 

 2290 12:40:36.503669  Enter into  DVFS_PRE_config >>>>> 

 2291 12:40:36.516984  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 2292 12:40:36.519921  Exit from  DVFS_PRE_config <<<<< 

 2293 12:40:36.523647  Enter into PICG configuration >>>> 

 2294 12:40:36.526553  Exit from PICG configuration <<<< 

 2295 12:40:36.526894  [RX_INPUT] configuration >>>>> 

 2296 12:40:36.530128  [RX_INPUT] configuration <<<<< 

 2297 12:40:36.536428  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 2298 12:40:36.539598  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 2299 12:40:36.546212  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 2300 12:40:36.553250  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 2301 12:40:36.560275  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 2302 12:40:36.566811  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 2303 12:40:36.570535  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 2304 12:40:36.573410  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 2305 12:40:36.576830  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 2306 12:40:36.583839  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 2307 12:40:36.587008  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 2308 12:40:36.589927  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2309 12:40:36.593544  =================================== 

 2310 12:40:36.596509  LPDDR4 DRAM CONFIGURATION

 2311 12:40:36.599644  =================================== 

 2312 12:40:36.603643  EX_ROW_EN[0]    = 0x0

 2313 12:40:36.604076  EX_ROW_EN[1]    = 0x0

 2314 12:40:36.606813  LP4Y_EN      = 0x0

 2315 12:40:36.607237  WORK_FSP     = 0x0

 2316 12:40:36.610154  WL           = 0x4

 2317 12:40:36.610578  RL           = 0x4

 2318 12:40:36.613273  BL           = 0x2

 2319 12:40:36.613696  RPST         = 0x0

 2320 12:40:36.616979  RD_PRE       = 0x0

 2321 12:40:36.617398  WR_PRE       = 0x1

 2322 12:40:36.620256  WR_PST       = 0x0

 2323 12:40:36.620680  DBI_WR       = 0x0

 2324 12:40:36.623534  DBI_RD       = 0x0

 2325 12:40:36.624017  OTF          = 0x1

 2326 12:40:36.626848  =================================== 

 2327 12:40:36.630089  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 2328 12:40:36.636606  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 2329 12:40:36.639972  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2330 12:40:36.643755  =================================== 

 2331 12:40:36.646563  LPDDR4 DRAM CONFIGURATION

 2332 12:40:36.650177  =================================== 

 2333 12:40:36.650425  EX_ROW_EN[0]    = 0x10

 2334 12:40:36.653420  EX_ROW_EN[1]    = 0x0

 2335 12:40:36.653618  LP4Y_EN      = 0x0

 2336 12:40:36.657096  WORK_FSP     = 0x0

 2337 12:40:36.660385  WL           = 0x4

 2338 12:40:36.660627  RL           = 0x4

 2339 12:40:36.663869  BL           = 0x2

 2340 12:40:36.664124  RPST         = 0x0

 2341 12:40:36.666926  RD_PRE       = 0x0

 2342 12:40:36.667152  WR_PRE       = 0x1

 2343 12:40:36.670230  WR_PST       = 0x0

 2344 12:40:36.670413  DBI_WR       = 0x0

 2345 12:40:36.673469  DBI_RD       = 0x0

 2346 12:40:36.673621  OTF          = 0x1

 2347 12:40:36.676935  =================================== 

 2348 12:40:36.683425  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 2349 12:40:36.683581  ==

 2350 12:40:36.687146  Dram Type= 6, Freq= 0, CH_0, rank 0

 2351 12:40:36.690475  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2352 12:40:36.690631  ==

 2353 12:40:36.693477  [Duty_Offset_Calibration]

 2354 12:40:36.693628  	B0:2	B1:0	CA:1

 2355 12:40:36.693747  

 2356 12:40:36.696758  [DutyScan_Calibration_Flow] k_type=0

 2357 12:40:36.706834  

 2358 12:40:36.706985  ==CLK 0==

 2359 12:40:36.710687  Final CLK duty delay cell = -4

 2360 12:40:36.714250  [-4] MAX Duty = 5031%(X100), DQS PI = 22

 2361 12:40:36.717205  [-4] MIN Duty = 4875%(X100), DQS PI = 0

 2362 12:40:36.720697  [-4] AVG Duty = 4953%(X100)

 2363 12:40:36.721118  

 2364 12:40:36.723529  CH0 CLK Duty spec in!! Max-Min= 156%

 2365 12:40:36.726949  [DutyScan_Calibration_Flow] ====Done====

 2366 12:40:36.727250  

 2367 12:40:36.730312  [DutyScan_Calibration_Flow] k_type=1

 2368 12:40:36.746455  

 2369 12:40:36.746880  ==DQS 0 ==

 2370 12:40:36.749573  Final DQS duty delay cell = 0

 2371 12:40:36.753195  [0] MAX Duty = 5187%(X100), DQS PI = 30

 2372 12:40:36.755907  [0] MIN Duty = 4938%(X100), DQS PI = 0

 2373 12:40:36.756301  [0] AVG Duty = 5062%(X100)

 2374 12:40:36.759297  

 2375 12:40:36.759683  ==DQS 1 ==

 2376 12:40:36.762688  Final DQS duty delay cell = -4

 2377 12:40:36.766003  [-4] MAX Duty = 5124%(X100), DQS PI = 32

 2378 12:40:36.769583  [-4] MIN Duty = 4938%(X100), DQS PI = 8

 2379 12:40:36.772843  [-4] AVG Duty = 5031%(X100)

 2380 12:40:36.773229  

 2381 12:40:36.776325  CH0 DQS 0 Duty spec in!! Max-Min= 249%

 2382 12:40:36.776712  

 2383 12:40:36.779549  CH0 DQS 1 Duty spec in!! Max-Min= 186%

 2384 12:40:36.782463  [DutyScan_Calibration_Flow] ====Done====

 2385 12:40:36.782716  

 2386 12:40:36.785920  [DutyScan_Calibration_Flow] k_type=3

 2387 12:40:36.802708  

 2388 12:40:36.802826  ==DQM 0 ==

 2389 12:40:36.805961  Final DQM duty delay cell = 0

 2390 12:40:36.809567  [0] MAX Duty = 5062%(X100), DQS PI = 24

 2391 12:40:36.812689  [0] MIN Duty = 4813%(X100), DQS PI = 0

 2392 12:40:36.812800  [0] AVG Duty = 4937%(X100)

 2393 12:40:36.816058  

 2394 12:40:36.816168  ==DQM 1 ==

 2395 12:40:36.819732  Final DQM duty delay cell = 0

 2396 12:40:36.823142  [0] MAX Duty = 5187%(X100), DQS PI = 48

 2397 12:40:36.826665  [0] MIN Duty = 5000%(X100), DQS PI = 12

 2398 12:40:36.829346  [0] AVG Duty = 5093%(X100)

 2399 12:40:36.829789  

 2400 12:40:36.832817  CH0 DQM 0 Duty spec in!! Max-Min= 249%

 2401 12:40:36.833238  

 2402 12:40:36.836339  CH0 DQM 1 Duty spec in!! Max-Min= 187%

 2403 12:40:36.839439  [DutyScan_Calibration_Flow] ====Done====

 2404 12:40:36.839862  

 2405 12:40:36.842543  [DutyScan_Calibration_Flow] k_type=2

 2406 12:40:36.859321  

 2407 12:40:36.859746  ==DQ 0 ==

 2408 12:40:36.862551  Final DQ duty delay cell = -4

 2409 12:40:36.866290  [-4] MAX Duty = 5031%(X100), DQS PI = 34

 2410 12:40:36.869861  [-4] MIN Duty = 4875%(X100), DQS PI = 14

 2411 12:40:36.872808  [-4] AVG Duty = 4953%(X100)

 2412 12:40:36.873230  

 2413 12:40:36.873560  ==DQ 1 ==

 2414 12:40:36.876124  Final DQ duty delay cell = 4

 2415 12:40:36.879282  [4] MAX Duty = 5093%(X100), DQS PI = 4

 2416 12:40:36.882522  [4] MIN Duty = 5031%(X100), DQS PI = 0

 2417 12:40:36.882779  [4] AVG Duty = 5062%(X100)

 2418 12:40:36.885705  

 2419 12:40:36.889512  CH0 DQ 0 Duty spec in!! Max-Min= 156%

 2420 12:40:36.889770  

 2421 12:40:36.892514  CH0 DQ 1 Duty spec in!! Max-Min= 62%

 2422 12:40:36.895866  [DutyScan_Calibration_Flow] ====Done====

 2423 12:40:36.896016  ==

 2424 12:40:36.899247  Dram Type= 6, Freq= 0, CH_1, rank 0

 2425 12:40:36.902541  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2426 12:40:36.902677  ==

 2427 12:40:36.906082  [Duty_Offset_Calibration]

 2428 12:40:36.906194  	B0:0	B1:-1	CA:2

 2429 12:40:36.906283  

 2430 12:40:36.909823  [DutyScan_Calibration_Flow] k_type=0

 2431 12:40:36.920128  

 2432 12:40:36.920323  ==CLK 0==

 2433 12:40:36.922981  Final CLK duty delay cell = 0

 2434 12:40:36.926524  [0] MAX Duty = 5156%(X100), DQS PI = 16

 2435 12:40:36.929617  [0] MIN Duty = 4938%(X100), DQS PI = 44

 2436 12:40:36.929781  [0] AVG Duty = 5047%(X100)

 2437 12:40:36.933013  

 2438 12:40:36.936009  CH1 CLK Duty spec in!! Max-Min= 218%

 2439 12:40:36.940053  [DutyScan_Calibration_Flow] ====Done====

 2440 12:40:36.940265  

 2441 12:40:36.942547  [DutyScan_Calibration_Flow] k_type=1

 2442 12:40:36.958822  

 2443 12:40:36.958920  ==DQS 0 ==

 2444 12:40:36.961834  Final DQS duty delay cell = 0

 2445 12:40:36.965408  [0] MAX Duty = 5093%(X100), DQS PI = 24

 2446 12:40:36.968714  [0] MIN Duty = 4969%(X100), DQS PI = 0

 2447 12:40:36.968805  [0] AVG Duty = 5031%(X100)

 2448 12:40:36.972027  

 2449 12:40:36.972116  ==DQS 1 ==

 2450 12:40:36.975118  Final DQS duty delay cell = 0

 2451 12:40:36.978595  [0] MAX Duty = 5156%(X100), DQS PI = 0

 2452 12:40:36.982116  [0] MIN Duty = 4875%(X100), DQS PI = 34

 2453 12:40:36.982243  [0] AVG Duty = 5015%(X100)

 2454 12:40:36.985309  

 2455 12:40:36.988861  CH1 DQS 0 Duty spec in!! Max-Min= 124%

 2456 12:40:36.988945  

 2457 12:40:36.992263  CH1 DQS 1 Duty spec in!! Max-Min= 281%

 2458 12:40:36.995194  [DutyScan_Calibration_Flow] ====Done====

 2459 12:40:36.995278  

 2460 12:40:36.998967  [DutyScan_Calibration_Flow] k_type=3

 2461 12:40:37.015289  

 2462 12:40:37.015455  ==DQM 0 ==

 2463 12:40:37.018570  Final DQM duty delay cell = 4

 2464 12:40:37.022102  [4] MAX Duty = 5093%(X100), DQS PI = 20

 2465 12:40:37.025327  [4] MIN Duty = 4938%(X100), DQS PI = 44

 2466 12:40:37.028386  [4] AVG Duty = 5015%(X100)

 2467 12:40:37.028499  

 2468 12:40:37.028588  ==DQM 1 ==

 2469 12:40:37.031632  Final DQM duty delay cell = -4

 2470 12:40:37.035269  [-4] MAX Duty = 5031%(X100), DQS PI = 62

 2471 12:40:37.038419  [-4] MIN Duty = 4751%(X100), DQS PI = 36

 2472 12:40:37.042010  [-4] AVG Duty = 4891%(X100)

 2473 12:40:37.042094  

 2474 12:40:37.044989  CH1 DQM 0 Duty spec in!! Max-Min= 155%

 2475 12:40:37.045080  

 2476 12:40:37.048563  CH1 DQM 1 Duty spec in!! Max-Min= 280%

 2477 12:40:37.051911  [DutyScan_Calibration_Flow] ====Done====

 2478 12:40:37.051995  

 2479 12:40:37.055270  [DutyScan_Calibration_Flow] k_type=2

 2480 12:40:37.072504  

 2481 12:40:37.072594  ==DQ 0 ==

 2482 12:40:37.075335  Final DQ duty delay cell = 0

 2483 12:40:37.078781  [0] MAX Duty = 5062%(X100), DQS PI = 22

 2484 12:40:37.082126  [0] MIN Duty = 4938%(X100), DQS PI = 0

 2485 12:40:37.082250  [0] AVG Duty = 5000%(X100)

 2486 12:40:37.082317  

 2487 12:40:37.085473  ==DQ 1 ==

 2488 12:40:37.088779  Final DQ duty delay cell = 0

 2489 12:40:37.092150  [0] MAX Duty = 5031%(X100), DQS PI = 2

 2490 12:40:37.095528  [0] MIN Duty = 4813%(X100), DQS PI = 34

 2491 12:40:37.095626  [0] AVG Duty = 4922%(X100)

 2492 12:40:37.095703  

 2493 12:40:37.098656  CH1 DQ 0 Duty spec in!! Max-Min= 124%

 2494 12:40:37.098761  

 2495 12:40:37.101952  CH1 DQ 1 Duty spec in!! Max-Min= 218%

 2496 12:40:37.108850  [DutyScan_Calibration_Flow] ====Done====

 2497 12:40:37.112174  nWR fixed to 30

 2498 12:40:37.112301  [ModeRegInit_LP4] CH0 RK0

 2499 12:40:37.115515  [ModeRegInit_LP4] CH0 RK1

 2500 12:40:37.118937  [ModeRegInit_LP4] CH1 RK0

 2501 12:40:37.119092  [ModeRegInit_LP4] CH1 RK1

 2502 12:40:37.122322  match AC timing 7

 2503 12:40:37.125345  dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1

 2504 12:40:37.129204  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 2505 12:40:37.135827  [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12

 2506 12:40:37.138913  [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25

 2507 12:40:37.145606  [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)

 2508 12:40:37.146058  ==

 2509 12:40:37.149050  Dram Type= 6, Freq= 0, CH_0, rank 0

 2510 12:40:37.152553  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2511 12:40:37.152992  ==

 2512 12:40:37.159162  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2513 12:40:37.162058  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37

 2514 12:40:37.172005  [CA 0] Center 38 (7~69) winsize 63

 2515 12:40:37.175422  [CA 1] Center 38 (8~69) winsize 62

 2516 12:40:37.178349  [CA 2] Center 35 (5~66) winsize 62

 2517 12:40:37.181727  [CA 3] Center 35 (4~66) winsize 63

 2518 12:40:37.185110  [CA 4] Center 34 (4~65) winsize 62

 2519 12:40:37.188601  [CA 5] Center 33 (3~63) winsize 61

 2520 12:40:37.188723  

 2521 12:40:37.191763  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 2522 12:40:37.191885  

 2523 12:40:37.195485  [CATrainingPosCal] consider 1 rank data

 2524 12:40:37.198553  u2DelayCellTimex100 = 270/100 ps

 2525 12:40:37.201804  CA0 delay=38 (7~69),Diff = 5 PI (24 cell)

 2526 12:40:37.205232  CA1 delay=38 (8~69),Diff = 5 PI (24 cell)

 2527 12:40:37.211847  CA2 delay=35 (5~66),Diff = 2 PI (9 cell)

 2528 12:40:37.215099  CA3 delay=35 (4~66),Diff = 2 PI (9 cell)

 2529 12:40:37.218722  CA4 delay=34 (4~65),Diff = 1 PI (4 cell)

 2530 12:40:37.222012  CA5 delay=33 (3~63),Diff = 0 PI (0 cell)

 2531 12:40:37.222471  

 2532 12:40:37.225191  CA PerBit enable=1, Macro0, CA PI delay=33

 2533 12:40:37.225636  

 2534 12:40:37.228703  [CBTSetCACLKResult] CA Dly = 33

 2535 12:40:37.229148  CS Dly: 6 (0~37)

 2536 12:40:37.229584  ==

 2537 12:40:37.231849  Dram Type= 6, Freq= 0, CH_0, rank 1

 2538 12:40:37.238812  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2539 12:40:37.239261  ==

 2540 12:40:37.242202  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2541 12:40:37.248612  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37

 2542 12:40:37.257788  [CA 0] Center 39 (8~70) winsize 63

 2543 12:40:37.261098  [CA 1] Center 38 (8~69) winsize 62

 2544 12:40:37.264783  [CA 2] Center 35 (5~66) winsize 62

 2545 12:40:37.267964  [CA 3] Center 35 (5~66) winsize 62

 2546 12:40:37.271089  [CA 4] Center 34 (4~65) winsize 62

 2547 12:40:37.274615  [CA 5] Center 34 (4~64) winsize 61

 2548 12:40:37.274761  

 2549 12:40:37.278314  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 2550 12:40:37.278452  

 2551 12:40:37.281233  [CATrainingPosCal] consider 2 rank data

 2552 12:40:37.284349  u2DelayCellTimex100 = 270/100 ps

 2553 12:40:37.287762  CA0 delay=38 (8~69),Diff = 5 PI (24 cell)

 2554 12:40:37.291409  CA1 delay=38 (8~69),Diff = 5 PI (24 cell)

 2555 12:40:37.294686  CA2 delay=35 (5~66),Diff = 2 PI (9 cell)

 2556 12:40:37.301399  CA3 delay=35 (5~66),Diff = 2 PI (9 cell)

 2557 12:40:37.304754  CA4 delay=34 (4~65),Diff = 1 PI (4 cell)

 2558 12:40:37.308017  CA5 delay=33 (4~63),Diff = 0 PI (0 cell)

 2559 12:40:37.308152  

 2560 12:40:37.311215  CA PerBit enable=1, Macro0, CA PI delay=33

 2561 12:40:37.311349  

 2562 12:40:37.314802  [CBTSetCACLKResult] CA Dly = 33

 2563 12:40:37.314936  CS Dly: 7 (0~39)

 2564 12:40:37.315043  

 2565 12:40:37.318246  ----->DramcWriteLeveling(PI) begin...

 2566 12:40:37.318387  ==

 2567 12:40:37.321112  Dram Type= 6, Freq= 0, CH_0, rank 0

 2568 12:40:37.328155  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2569 12:40:37.328290  ==

 2570 12:40:37.331598  Write leveling (Byte 0): 36 => 36

 2571 12:40:37.334682  Write leveling (Byte 1): 32 => 32

 2572 12:40:37.334817  DramcWriteLeveling(PI) end<-----

 2573 12:40:37.334922  

 2574 12:40:37.338076  ==

 2575 12:40:37.338209  Dram Type= 6, Freq= 0, CH_0, rank 0

 2576 12:40:37.344994  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2577 12:40:37.345129  ==

 2578 12:40:37.348449  [Gating] SW mode calibration

 2579 12:40:37.354827  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2580 12:40:37.358245  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2581 12:40:37.365038   0 15  0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)

 2582 12:40:37.368725   0 15  4 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)

 2583 12:40:37.371789   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2584 12:40:37.375121   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2585 12:40:37.381588   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2586 12:40:37.384840   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2587 12:40:37.388686   0 15 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)

 2588 12:40:37.395179   0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 0) (1 0)

 2589 12:40:37.398785   1  0  0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)

 2590 12:40:37.402079   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2591 12:40:37.408550   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2592 12:40:37.411933   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2593 12:40:37.415367   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2594 12:40:37.421850   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2595 12:40:37.425295   1  0 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)

 2596 12:40:37.428722   1  0 28 | B1->B0 | 2827 4646 | 1 0 | (0 0) (0 0)

 2597 12:40:37.435188   1  1  0 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)

 2598 12:40:37.438841   1  1  4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)

 2599 12:40:37.442306   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2600 12:40:37.448758   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2601 12:40:37.452260   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2602 12:40:37.455414   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2603 12:40:37.458626   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2604 12:40:37.465493   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 2605 12:40:37.469087   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 2606 12:40:37.471970   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2607 12:40:37.478784   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2608 12:40:37.482069   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2609 12:40:37.485383   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2610 12:40:37.492477   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2611 12:40:37.495707   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2612 12:40:37.498898   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2613 12:40:37.505394   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2614 12:40:37.509173   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2615 12:40:37.512306   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2616 12:40:37.518646   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2617 12:40:37.521973   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2618 12:40:37.525641   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2619 12:40:37.528722   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2620 12:40:37.535734   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 2621 12:40:37.539047   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 2622 12:40:37.542435  Total UI for P1: 0, mck2ui 16

 2623 12:40:37.545986  best dqsien dly found for B0: ( 1,  3, 26)

 2624 12:40:37.548967   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2625 12:40:37.552501  Total UI for P1: 0, mck2ui 16

 2626 12:40:37.555706  best dqsien dly found for B1: ( 1,  3, 30)

 2627 12:40:37.559069  best DQS0 dly(MCK, UI, PI) = (1, 3, 26)

 2628 12:40:37.562301  best DQS1 dly(MCK, UI, PI) = (1, 3, 30)

 2629 12:40:37.562532  

 2630 12:40:37.569100  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)

 2631 12:40:37.572292  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)

 2632 12:40:37.572496  [Gating] SW calibration Done

 2633 12:40:37.575778  ==

 2634 12:40:37.579014  Dram Type= 6, Freq= 0, CH_0, rank 0

 2635 12:40:37.582509  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2636 12:40:37.582704  ==

 2637 12:40:37.582885  RX Vref Scan: 0

 2638 12:40:37.583045  

 2639 12:40:37.585859  RX Vref 0 -> 0, step: 1

 2640 12:40:37.586055  

 2641 12:40:37.588978  RX Delay -40 -> 252, step: 8

 2642 12:40:37.592598  iDelay=208, Bit 0, Center 123 (56 ~ 191) 136

 2643 12:40:37.595768  iDelay=208, Bit 1, Center 127 (56 ~ 199) 144

 2644 12:40:37.599254  iDelay=208, Bit 2, Center 119 (48 ~ 191) 144

 2645 12:40:37.605672  iDelay=208, Bit 3, Center 119 (48 ~ 191) 144

 2646 12:40:37.609206  iDelay=208, Bit 4, Center 127 (56 ~ 199) 144

 2647 12:40:37.612560  iDelay=208, Bit 5, Center 115 (48 ~ 183) 136

 2648 12:40:37.615823  iDelay=208, Bit 6, Center 131 (56 ~ 207) 152

 2649 12:40:37.619205  iDelay=208, Bit 7, Center 127 (56 ~ 199) 144

 2650 12:40:37.625883  iDelay=208, Bit 8, Center 103 (40 ~ 167) 128

 2651 12:40:37.629179  iDelay=208, Bit 9, Center 99 (32 ~ 167) 136

 2652 12:40:37.632409  iDelay=208, Bit 10, Center 107 (40 ~ 175) 136

 2653 12:40:37.635972  iDelay=208, Bit 11, Center 107 (40 ~ 175) 136

 2654 12:40:37.639246  iDelay=208, Bit 12, Center 115 (48 ~ 183) 136

 2655 12:40:37.645752  iDelay=208, Bit 13, Center 115 (48 ~ 183) 136

 2656 12:40:37.649049  iDelay=208, Bit 14, Center 123 (56 ~ 191) 136

 2657 12:40:37.652550  iDelay=208, Bit 15, Center 115 (48 ~ 183) 136

 2658 12:40:37.652620  ==

 2659 12:40:37.656018  Dram Type= 6, Freq= 0, CH_0, rank 0

 2660 12:40:37.659912  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2661 12:40:37.659980  ==

 2662 12:40:37.662755  DQS Delay:

 2663 12:40:37.662822  DQS0 = 0, DQS1 = 0

 2664 12:40:37.665803  DQM Delay:

 2665 12:40:37.665871  DQM0 = 123, DQM1 = 110

 2666 12:40:37.665930  DQ Delay:

 2667 12:40:37.669260  DQ0 =123, DQ1 =127, DQ2 =119, DQ3 =119

 2668 12:40:37.672946  DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127

 2669 12:40:37.679863  DQ8 =103, DQ9 =99, DQ10 =107, DQ11 =107

 2670 12:40:37.683052  DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115

 2671 12:40:37.683121  

 2672 12:40:37.683180  

 2673 12:40:37.683236  ==

 2674 12:40:37.686299  Dram Type= 6, Freq= 0, CH_0, rank 0

 2675 12:40:37.689262  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2676 12:40:37.689330  ==

 2677 12:40:37.689391  

 2678 12:40:37.689449  

 2679 12:40:37.692787  	TX Vref Scan disable

 2680 12:40:37.692887   == TX Byte 0 ==

 2681 12:40:37.699553  Update DQ  dly =853 (3 ,2, 21)  DQ  OEN =(2 ,7)

 2682 12:40:37.702986  Update DQM dly =853 (3 ,2, 21)  DQM OEN =(2 ,7)

 2683 12:40:37.703076   == TX Byte 1 ==

 2684 12:40:37.709419  Update DQ  dly =848 (3 ,2, 16)  DQ  OEN =(2 ,7)

 2685 12:40:37.712856  Update DQM dly =848 (3 ,2, 16)  DQM OEN =(2 ,7)

 2686 12:40:37.712928  ==

 2687 12:40:37.716250  Dram Type= 6, Freq= 0, CH_0, rank 0

 2688 12:40:37.719350  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2689 12:40:37.719424  ==

 2690 12:40:37.732554  TX Vref=22, minBit 4, minWin=23, winSum=407

 2691 12:40:37.736066  TX Vref=24, minBit 2, minWin=24, winSum=415

 2692 12:40:37.739184  TX Vref=26, minBit 5, minWin=24, winSum=420

 2693 12:40:37.742254  TX Vref=28, minBit 0, minWin=25, winSum=424

 2694 12:40:37.745469  TX Vref=30, minBit 0, minWin=26, winSum=420

 2695 12:40:37.749530  TX Vref=32, minBit 5, minWin=25, winSum=428

 2696 12:40:37.755513  [TxChooseVref] Worse bit 0, Min win 26, Win sum 420, Final Vref 30

 2697 12:40:37.755599  

 2698 12:40:37.759437  Final TX Range 1 Vref 30

 2699 12:40:37.759527  

 2700 12:40:37.759598  ==

 2701 12:40:37.762476  Dram Type= 6, Freq= 0, CH_0, rank 0

 2702 12:40:37.765865  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2703 12:40:37.765971  ==

 2704 12:40:37.766049  

 2705 12:40:37.769116  

 2706 12:40:37.769221  	TX Vref Scan disable

 2707 12:40:37.772567   == TX Byte 0 ==

 2708 12:40:37.776062  Update DQ  dly =853 (3 ,2, 21)  DQ  OEN =(2 ,7)

 2709 12:40:37.779012  Update DQM dly =853 (3 ,2, 21)  DQM OEN =(2 ,7)

 2710 12:40:37.782294   == TX Byte 1 ==

 2711 12:40:37.785802  Update DQ  dly =848 (3 ,2, 16)  DQ  OEN =(2 ,7)

 2712 12:40:37.789090  Update DQM dly =848 (3 ,2, 16)  DQM OEN =(2 ,7)

 2713 12:40:37.789246  

 2714 12:40:37.792424  [DATLAT]

 2715 12:40:37.792596  Freq=1200, CH0 RK0

 2716 12:40:37.792737  

 2717 12:40:37.795602  DATLAT Default: 0xd

 2718 12:40:37.795779  0, 0xFFFF, sum = 0

 2719 12:40:37.799470  1, 0xFFFF, sum = 0

 2720 12:40:37.799679  2, 0xFFFF, sum = 0

 2721 12:40:37.802934  3, 0xFFFF, sum = 0

 2722 12:40:37.803198  4, 0xFFFF, sum = 0

 2723 12:40:37.805786  5, 0xFFFF, sum = 0

 2724 12:40:37.806056  6, 0xFFFF, sum = 0

 2725 12:40:37.809746  7, 0xFFFF, sum = 0

 2726 12:40:37.810078  8, 0xFFFF, sum = 0

 2727 12:40:37.812809  9, 0xFFFF, sum = 0

 2728 12:40:37.815893  10, 0xFFFF, sum = 0

 2729 12:40:37.816206  11, 0xFFFF, sum = 0

 2730 12:40:37.819314  12, 0x0, sum = 1

 2731 12:40:37.819754  13, 0x0, sum = 2

 2732 12:40:37.820048  14, 0x0, sum = 3

 2733 12:40:37.822783  15, 0x0, sum = 4

 2734 12:40:37.823100  best_step = 13

 2735 12:40:37.823344  

 2736 12:40:37.826230  ==

 2737 12:40:37.826542  Dram Type= 6, Freq= 0, CH_0, rank 0

 2738 12:40:37.832728  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2739 12:40:37.833039  ==

 2740 12:40:37.833281  RX Vref Scan: 1

 2741 12:40:37.833515  

 2742 12:40:37.836136  Set Vref Range= 32 -> 127

 2743 12:40:37.836444  

 2744 12:40:37.839262  RX Vref 32 -> 127, step: 1

 2745 12:40:37.839570  

 2746 12:40:37.842913  RX Delay -13 -> 252, step: 4

 2747 12:40:37.843224  

 2748 12:40:37.845883  Set Vref, RX VrefLevel [Byte0]: 32

 2749 12:40:37.849376                           [Byte1]: 32

 2750 12:40:37.849685  

 2751 12:40:37.853282  Set Vref, RX VrefLevel [Byte0]: 33

 2752 12:40:37.856052                           [Byte1]: 33

 2753 12:40:37.856360  

 2754 12:40:37.859309  Set Vref, RX VrefLevel [Byte0]: 34

 2755 12:40:37.862771                           [Byte1]: 34

 2756 12:40:37.866426  

 2757 12:40:37.866510  Set Vref, RX VrefLevel [Byte0]: 35

 2758 12:40:37.869588                           [Byte1]: 35

 2759 12:40:37.874760  

 2760 12:40:37.874844  Set Vref, RX VrefLevel [Byte0]: 36

 2761 12:40:37.878100                           [Byte1]: 36

 2762 12:40:37.882462  

 2763 12:40:37.882547  Set Vref, RX VrefLevel [Byte0]: 37

 2764 12:40:37.885490                           [Byte1]: 37

 2765 12:40:37.890272  

 2766 12:40:37.890356  Set Vref, RX VrefLevel [Byte0]: 38

 2767 12:40:37.893903                           [Byte1]: 38

 2768 12:40:37.898279  

 2769 12:40:37.898363  Set Vref, RX VrefLevel [Byte0]: 39

 2770 12:40:37.901433                           [Byte1]: 39

 2771 12:40:37.906157  

 2772 12:40:37.906241  Set Vref, RX VrefLevel [Byte0]: 40

 2773 12:40:37.909826                           [Byte1]: 40

 2774 12:40:37.914067  

 2775 12:40:37.914153  Set Vref, RX VrefLevel [Byte0]: 41

 2776 12:40:37.917205                           [Byte1]: 41

 2777 12:40:37.921935  

 2778 12:40:37.922041  Set Vref, RX VrefLevel [Byte0]: 42

 2779 12:40:37.924932                           [Byte1]: 42

 2780 12:40:37.929493  

 2781 12:40:37.929576  Set Vref, RX VrefLevel [Byte0]: 43

 2782 12:40:37.932942                           [Byte1]: 43

 2783 12:40:37.937546  

 2784 12:40:37.937630  Set Vref, RX VrefLevel [Byte0]: 44

 2785 12:40:37.940681                           [Byte1]: 44

 2786 12:40:37.945699  

 2787 12:40:37.945783  Set Vref, RX VrefLevel [Byte0]: 45

 2788 12:40:37.949172                           [Byte1]: 45

 2789 12:40:37.953490  

 2790 12:40:37.953574  Set Vref, RX VrefLevel [Byte0]: 46

 2791 12:40:37.956813                           [Byte1]: 46

 2792 12:40:37.961445  

 2793 12:40:37.961529  Set Vref, RX VrefLevel [Byte0]: 47

 2794 12:40:37.964555                           [Byte1]: 47

 2795 12:40:37.968938  

 2796 12:40:37.969022  Set Vref, RX VrefLevel [Byte0]: 48

 2797 12:40:37.972181                           [Byte1]: 48

 2798 12:40:37.977058  

 2799 12:40:37.977142  Set Vref, RX VrefLevel [Byte0]: 49

 2800 12:40:37.980447                           [Byte1]: 49

 2801 12:40:37.984579  

 2802 12:40:37.984663  Set Vref, RX VrefLevel [Byte0]: 50

 2803 12:40:37.988241                           [Byte1]: 50

 2804 12:40:37.992826  

 2805 12:40:37.992911  Set Vref, RX VrefLevel [Byte0]: 51

 2806 12:40:37.995992                           [Byte1]: 51

 2807 12:40:38.000621  

 2808 12:40:38.000705  Set Vref, RX VrefLevel [Byte0]: 52

 2809 12:40:38.003892                           [Byte1]: 52

 2810 12:40:38.008658  

 2811 12:40:38.008741  Set Vref, RX VrefLevel [Byte0]: 53

 2812 12:40:38.011945                           [Byte1]: 53

 2813 12:40:38.016121  

 2814 12:40:38.020114  Set Vref, RX VrefLevel [Byte0]: 54

 2815 12:40:38.020199                           [Byte1]: 54

 2816 12:40:38.024124  

 2817 12:40:38.024207  Set Vref, RX VrefLevel [Byte0]: 55

 2818 12:40:38.027463                           [Byte1]: 55

 2819 12:40:38.031976  

 2820 12:40:38.032066  Set Vref, RX VrefLevel [Byte0]: 56

 2821 12:40:38.035218                           [Byte1]: 56

 2822 12:40:38.040163  

 2823 12:40:38.040267  Set Vref, RX VrefLevel [Byte0]: 57

 2824 12:40:38.043236                           [Byte1]: 57

 2825 12:40:38.048184  

 2826 12:40:38.048310  Set Vref, RX VrefLevel [Byte0]: 58

 2827 12:40:38.051576                           [Byte1]: 58

 2828 12:40:38.056125  

 2829 12:40:38.056264  Set Vref, RX VrefLevel [Byte0]: 59

 2830 12:40:38.059451                           [Byte1]: 59

 2831 12:40:38.063736  

 2832 12:40:38.063912  Set Vref, RX VrefLevel [Byte0]: 60

 2833 12:40:38.067138                           [Byte1]: 60

 2834 12:40:38.071708  

 2835 12:40:38.071916  Set Vref, RX VrefLevel [Byte0]: 61

 2836 12:40:38.075404                           [Byte1]: 61

 2837 12:40:38.079646  

 2838 12:40:38.079961  Set Vref, RX VrefLevel [Byte0]: 62

 2839 12:40:38.086302                           [Byte1]: 62

 2840 12:40:38.086607  

 2841 12:40:38.089568  Set Vref, RX VrefLevel [Byte0]: 63

 2842 12:40:38.092790                           [Byte1]: 63

 2843 12:40:38.093098  

 2844 12:40:38.096394  Set Vref, RX VrefLevel [Byte0]: 64

 2845 12:40:38.099053                           [Byte1]: 64

 2846 12:40:38.103316  

 2847 12:40:38.103400  Set Vref, RX VrefLevel [Byte0]: 65

 2848 12:40:38.106654                           [Byte1]: 65

 2849 12:40:38.111011  

 2850 12:40:38.111092  Set Vref, RX VrefLevel [Byte0]: 66

 2851 12:40:38.114694                           [Byte1]: 66

 2852 12:40:38.119518  

 2853 12:40:38.119968  Set Vref, RX VrefLevel [Byte0]: 67

 2854 12:40:38.122603                           [Byte1]: 67

 2855 12:40:38.127348  

 2856 12:40:38.127720  Set Vref, RX VrefLevel [Byte0]: 68

 2857 12:40:38.130226                           [Byte1]: 68

 2858 12:40:38.135167  

 2859 12:40:38.135596  Set Vref, RX VrefLevel [Byte0]: 69

 2860 12:40:38.138436                           [Byte1]: 69

 2861 12:40:38.142812  

 2862 12:40:38.143369  Set Vref, RX VrefLevel [Byte0]: 70

 2863 12:40:38.146150                           [Byte1]: 70

 2864 12:40:38.150675  

 2865 12:40:38.151199  Final RX Vref Byte 0 = 59 to rank0

 2866 12:40:38.154226  Final RX Vref Byte 1 = 50 to rank0

 2867 12:40:38.157259  Final RX Vref Byte 0 = 59 to rank1

 2868 12:40:38.160278  Final RX Vref Byte 1 = 50 to rank1==

 2869 12:40:38.164175  Dram Type= 6, Freq= 0, CH_0, rank 0

 2870 12:40:38.167217  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2871 12:40:38.170682  ==

 2872 12:40:38.170777  DQS Delay:

 2873 12:40:38.170844  DQS0 = 0, DQS1 = 0

 2874 12:40:38.174122  DQM Delay:

 2875 12:40:38.174208  DQM0 = 123, DQM1 = 109

 2876 12:40:38.177344  DQ Delay:

 2877 12:40:38.180665  DQ0 =122, DQ1 =122, DQ2 =120, DQ3 =120

 2878 12:40:38.183831  DQ4 =126, DQ5 =116, DQ6 =132, DQ7 =128

 2879 12:40:38.187401  DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =108

 2880 12:40:38.190929  DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116

 2881 12:40:38.191013  

 2882 12:40:38.191078  

 2883 12:40:38.197575  [DQSOSCAuto] RK0, (LSB)MR18= 0xd0a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps

 2884 12:40:38.200520  CH0 RK0: MR19=404, MR18=D0A

 2885 12:40:38.207367  CH0_RK0: MR19=0x404, MR18=0xD0A, DQSOSC=405, MR23=63, INC=39, DEC=26

 2886 12:40:38.207468  

 2887 12:40:38.210676  ----->DramcWriteLeveling(PI) begin...

 2888 12:40:38.210786  ==

 2889 12:40:38.213946  Dram Type= 6, Freq= 0, CH_0, rank 1

 2890 12:40:38.217377  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2891 12:40:38.217536  ==

 2892 12:40:38.220654  Write leveling (Byte 0): 36 => 36

 2893 12:40:38.224189  Write leveling (Byte 1): 30 => 30

 2894 12:40:38.227196  DramcWriteLeveling(PI) end<-----

 2895 12:40:38.227377  

 2896 12:40:38.227508  ==

 2897 12:40:38.230716  Dram Type= 6, Freq= 0, CH_0, rank 1

 2898 12:40:38.234018  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2899 12:40:38.237569  ==

 2900 12:40:38.237742  [Gating] SW mode calibration

 2901 12:40:38.244042  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2902 12:40:38.250318  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2903 12:40:38.253798   0 15  0 | B1->B0 | 3232 3333 | 1 1 | (1 1) (1 1)

 2904 12:40:38.260299   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2905 12:40:38.263917   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2906 12:40:38.267014   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2907 12:40:38.273581   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2908 12:40:38.277219   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2909 12:40:38.280373   0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)

 2910 12:40:38.288111   0 15 28 | B1->B0 | 3030 3030 | 1 1 | (1 1) (0 0)

 2911 12:40:38.290456   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

 2912 12:40:38.294236   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2913 12:40:38.300861   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2914 12:40:38.304149   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2915 12:40:38.307648   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2916 12:40:38.311320   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2917 12:40:38.317665   1  0 24 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)

 2918 12:40:38.320871   1  0 28 | B1->B0 | 3737 4040 | 0 0 | (0 0) (0 0)

 2919 12:40:38.324332   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2920 12:40:38.331101   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2921 12:40:38.334582   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2922 12:40:38.337565   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2923 12:40:38.344572   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2924 12:40:38.348003   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2925 12:40:38.351269   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2926 12:40:38.358237   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 2927 12:40:38.361072   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2928 12:40:38.364361   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2929 12:40:38.371604   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2930 12:40:38.374370   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2931 12:40:38.378209   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2932 12:40:38.384475   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2933 12:40:38.387826   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2934 12:40:38.390989   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2935 12:40:38.394495   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2936 12:40:38.401056   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2937 12:40:38.404605   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2938 12:40:38.407615   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2939 12:40:38.414414   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2940 12:40:38.417640   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2941 12:40:38.420702   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2942 12:40:38.427967   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 2943 12:40:38.430935   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2944 12:40:38.433901  Total UI for P1: 0, mck2ui 16

 2945 12:40:38.437393  best dqsien dly found for B0: ( 1,  3, 28)

 2946 12:40:38.440567  Total UI for P1: 0, mck2ui 16

 2947 12:40:38.444496  best dqsien dly found for B1: ( 1,  3, 28)

 2948 12:40:38.447515  best DQS0 dly(MCK, UI, PI) = (1, 3, 28)

 2949 12:40:38.450658  best DQS1 dly(MCK, UI, PI) = (1, 3, 28)

 2950 12:40:38.450753  

 2951 12:40:38.454123  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)

 2952 12:40:38.457360  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)

 2953 12:40:38.460810  [Gating] SW calibration Done

 2954 12:40:38.460895  ==

 2955 12:40:38.463986  Dram Type= 6, Freq= 0, CH_0, rank 1

 2956 12:40:38.467502  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2957 12:40:38.470936  ==

 2958 12:40:38.471022  RX Vref Scan: 0

 2959 12:40:38.471088  

 2960 12:40:38.473882  RX Vref 0 -> 0, step: 1

 2961 12:40:38.474002  

 2962 12:40:38.477215  RX Delay -40 -> 252, step: 8

 2963 12:40:38.480713  iDelay=200, Bit 0, Center 119 (48 ~ 191) 144

 2964 12:40:38.484178  iDelay=200, Bit 1, Center 119 (48 ~ 191) 144

 2965 12:40:38.487421  iDelay=200, Bit 2, Center 119 (48 ~ 191) 144

 2966 12:40:38.490862  iDelay=200, Bit 3, Center 115 (48 ~ 183) 136

 2967 12:40:38.497266  iDelay=200, Bit 4, Center 119 (48 ~ 191) 144

 2968 12:40:38.500586  iDelay=200, Bit 5, Center 115 (48 ~ 183) 136

 2969 12:40:38.504109  iDelay=200, Bit 6, Center 127 (56 ~ 199) 144

 2970 12:40:38.507361  iDelay=200, Bit 7, Center 127 (56 ~ 199) 144

 2971 12:40:38.510923  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 2972 12:40:38.514446  iDelay=200, Bit 9, Center 95 (24 ~ 167) 144

 2973 12:40:38.520999  iDelay=200, Bit 10, Center 107 (40 ~ 175) 136

 2974 12:40:38.524167  iDelay=200, Bit 11, Center 107 (40 ~ 175) 136

 2975 12:40:38.527504  iDelay=200, Bit 12, Center 111 (40 ~ 183) 144

 2976 12:40:38.531294  iDelay=200, Bit 13, Center 115 (48 ~ 183) 136

 2977 12:40:38.534113  iDelay=200, Bit 14, Center 119 (48 ~ 191) 144

 2978 12:40:38.541104  iDelay=200, Bit 15, Center 111 (48 ~ 175) 128

 2979 12:40:38.541189  ==

 2980 12:40:38.544664  Dram Type= 6, Freq= 0, CH_0, rank 1

 2981 12:40:38.548375  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2982 12:40:38.548462  ==

 2983 12:40:38.548527  DQS Delay:

 2984 12:40:38.550925  DQS0 = 0, DQS1 = 0

 2985 12:40:38.551008  DQM Delay:

 2986 12:40:38.554272  DQM0 = 120, DQM1 = 108

 2987 12:40:38.554353  DQ Delay:

 2988 12:40:38.557627  DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115

 2989 12:40:38.561032  DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127

 2990 12:40:38.564368  DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107

 2991 12:40:38.567654  DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111

 2992 12:40:38.567737  

 2993 12:40:38.567801  

 2994 12:40:38.567860  ==

 2995 12:40:38.571129  Dram Type= 6, Freq= 0, CH_0, rank 1

 2996 12:40:38.577714  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2997 12:40:38.577834  ==

 2998 12:40:38.577927  

 2999 12:40:38.578056  

 3000 12:40:38.580759  	TX Vref Scan disable

 3001 12:40:38.580841   == TX Byte 0 ==

 3002 12:40:38.584266  Update DQ  dly =855 (3 ,2, 23)  DQ  OEN =(2 ,7)

 3003 12:40:38.591016  Update DQM dly =855 (3 ,2, 23)  DQM OEN =(2 ,7)

 3004 12:40:38.591101   == TX Byte 1 ==

 3005 12:40:38.593914  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 3006 12:40:38.600764  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 3007 12:40:38.600849  ==

 3008 12:40:38.604058  Dram Type= 6, Freq= 0, CH_0, rank 1

 3009 12:40:38.607727  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3010 12:40:38.607815  ==

 3011 12:40:38.619838  TX Vref=22, minBit 0, minWin=25, winSum=415

 3012 12:40:38.623001  TX Vref=24, minBit 1, minWin=24, winSum=421

 3013 12:40:38.626471  TX Vref=26, minBit 2, minWin=25, winSum=426

 3014 12:40:38.630102  TX Vref=28, minBit 1, minWin=26, winSum=428

 3015 12:40:38.633584  TX Vref=30, minBit 0, minWin=26, winSum=434

 3016 12:40:38.636692  TX Vref=32, minBit 5, minWin=25, winSum=427

 3017 12:40:38.650508  [TxChooseVref] Worse bit 0, Min win 26, Win sum 434, Final Vref 30

 3018 12:40:38.650644  

 3019 12:40:38.650711  Final TX Range 1 Vref 30

 3020 12:40:38.650772  

 3021 12:40:38.650830  ==

 3022 12:40:38.650888  Dram Type= 6, Freq= 0, CH_0, rank 1

 3023 12:40:38.653528  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3024 12:40:38.653613  ==

 3025 12:40:38.653679  

 3026 12:40:38.653739  

 3027 12:40:38.656871  	TX Vref Scan disable

 3028 12:40:38.660399   == TX Byte 0 ==

 3029 12:40:38.663302  Update DQ  dly =854 (3 ,2, 22)  DQ  OEN =(2 ,7)

 3030 12:40:38.666952  Update DQM dly =854 (3 ,2, 22)  DQM OEN =(2 ,7)

 3031 12:40:38.672248   == TX Byte 1 ==

 3032 12:40:38.673438  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 3033 12:40:38.676794  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 3034 12:40:38.676912  

 3035 12:40:38.680367  [DATLAT]

 3036 12:40:38.680479  Freq=1200, CH0 RK1

 3037 12:40:38.680573  

 3038 12:40:38.683602  DATLAT Default: 0xd

 3039 12:40:38.683710  0, 0xFFFF, sum = 0

 3040 12:40:38.686861  1, 0xFFFF, sum = 0

 3041 12:40:38.686952  2, 0xFFFF, sum = 0

 3042 12:40:38.690361  3, 0xFFFF, sum = 0

 3043 12:40:38.690451  4, 0xFFFF, sum = 0

 3044 12:40:38.693634  5, 0xFFFF, sum = 0

 3045 12:40:38.693748  6, 0xFFFF, sum = 0

 3046 12:40:38.697080  7, 0xFFFF, sum = 0

 3047 12:40:38.697200  8, 0xFFFF, sum = 0

 3048 12:40:38.700665  9, 0xFFFF, sum = 0

 3049 12:40:38.700756  10, 0xFFFF, sum = 0

 3050 12:40:38.704025  11, 0xFFFF, sum = 0

 3051 12:40:38.704118  12, 0x0, sum = 1

 3052 12:40:38.707218  13, 0x0, sum = 2

 3053 12:40:38.707309  14, 0x0, sum = 3

 3054 12:40:38.710299  15, 0x0, sum = 4

 3055 12:40:38.710387  best_step = 13

 3056 12:40:38.710472  

 3057 12:40:38.710552  ==

 3058 12:40:38.713636  Dram Type= 6, Freq= 0, CH_0, rank 1

 3059 12:40:38.720524  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3060 12:40:38.720615  ==

 3061 12:40:38.720683  RX Vref Scan: 0

 3062 12:40:38.720744  

 3063 12:40:38.723545  RX Vref 0 -> 0, step: 1

 3064 12:40:38.723637  

 3065 12:40:38.727137  RX Delay -21 -> 252, step: 4

 3066 12:40:38.730350  iDelay=195, Bit 0, Center 118 (51 ~ 186) 136

 3067 12:40:38.734100  iDelay=195, Bit 1, Center 122 (55 ~ 190) 136

 3068 12:40:38.740446  iDelay=195, Bit 2, Center 116 (51 ~ 182) 132

 3069 12:40:38.743907  iDelay=195, Bit 3, Center 112 (47 ~ 178) 132

 3070 12:40:38.747082  iDelay=195, Bit 4, Center 120 (55 ~ 186) 132

 3071 12:40:38.750408  iDelay=195, Bit 5, Center 114 (51 ~ 178) 128

 3072 12:40:38.753837  iDelay=195, Bit 6, Center 126 (59 ~ 194) 136

 3073 12:40:38.757023  iDelay=195, Bit 7, Center 124 (55 ~ 194) 140

 3074 12:40:38.763897  iDelay=195, Bit 8, Center 98 (35 ~ 162) 128

 3075 12:40:38.767338  iDelay=195, Bit 9, Center 94 (31 ~ 158) 128

 3076 12:40:38.770529  iDelay=195, Bit 10, Center 108 (47 ~ 170) 124

 3077 12:40:38.773873  iDelay=195, Bit 11, Center 104 (43 ~ 166) 124

 3078 12:40:38.777214  iDelay=195, Bit 12, Center 114 (51 ~ 178) 128

 3079 12:40:38.784229  iDelay=195, Bit 13, Center 110 (47 ~ 174) 128

 3080 12:40:38.787713  iDelay=195, Bit 14, Center 118 (55 ~ 182) 128

 3081 12:40:38.790502  iDelay=195, Bit 15, Center 114 (51 ~ 178) 128

 3082 12:40:38.790588  ==

 3083 12:40:38.793920  Dram Type= 6, Freq= 0, CH_0, rank 1

 3084 12:40:38.797607  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3085 12:40:38.797698  ==

 3086 12:40:38.800641  DQS Delay:

 3087 12:40:38.800730  DQS0 = 0, DQS1 = 0

 3088 12:40:38.804244  DQM Delay:

 3089 12:40:38.804333  DQM0 = 119, DQM1 = 107

 3090 12:40:38.804400  DQ Delay:

 3091 12:40:38.810571  DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =112

 3092 12:40:38.813875  DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124

 3093 12:40:38.817127  DQ8 =98, DQ9 =94, DQ10 =108, DQ11 =104

 3094 12:40:38.820644  DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114

 3095 12:40:38.820732  

 3096 12:40:38.820797  

 3097 12:40:38.827289  [DQSOSCAuto] RK1, (LSB)MR18= 0xff6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 404 ps

 3098 12:40:38.830444  CH0 RK1: MR19=403, MR18=FF6

 3099 12:40:38.837224  CH0_RK1: MR19=0x403, MR18=0xFF6, DQSOSC=404, MR23=63, INC=40, DEC=26

 3100 12:40:38.840951  [RxdqsGatingPostProcess] freq 1200

 3101 12:40:38.844003  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3102 12:40:38.847348  best DQS0 dly(2T, 0.5T) = (0, 11)

 3103 12:40:38.850686  best DQS1 dly(2T, 0.5T) = (0, 11)

 3104 12:40:38.853874  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3105 12:40:38.857136  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3106 12:40:38.860676  best DQS0 dly(2T, 0.5T) = (0, 11)

 3107 12:40:38.864224  best DQS1 dly(2T, 0.5T) = (0, 11)

 3108 12:40:38.867190  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3109 12:40:38.870917  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3110 12:40:38.873911  Pre-setting of DQS Precalculation

 3111 12:40:38.877302  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3112 12:40:38.877386  ==

 3113 12:40:38.880410  Dram Type= 6, Freq= 0, CH_1, rank 0

 3114 12:40:38.887038  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3115 12:40:38.887122  ==

 3116 12:40:38.890495  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3117 12:40:38.896889  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35

 3118 12:40:38.905877  [CA 0] Center 37 (7~68) winsize 62

 3119 12:40:38.909113  [CA 1] Center 37 (7~68) winsize 62

 3120 12:40:38.913030  [CA 2] Center 35 (5~65) winsize 61

 3121 12:40:38.915693  [CA 3] Center 34 (4~65) winsize 62

 3122 12:40:38.919347  [CA 4] Center 34 (4~65) winsize 62

 3123 12:40:38.922660  [CA 5] Center 33 (3~64) winsize 62

 3124 12:40:38.922743  

 3125 12:40:38.925760  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 3126 12:40:38.925844  

 3127 12:40:38.929124  [CATrainingPosCal] consider 1 rank data

 3128 12:40:38.932656  u2DelayCellTimex100 = 270/100 ps

 3129 12:40:38.935809  CA0 delay=37 (7~68),Diff = 4 PI (19 cell)

 3130 12:40:38.939678  CA1 delay=37 (7~68),Diff = 4 PI (19 cell)

 3131 12:40:38.945777  CA2 delay=35 (5~65),Diff = 2 PI (9 cell)

 3132 12:40:38.949176  CA3 delay=34 (4~65),Diff = 1 PI (4 cell)

 3133 12:40:38.952609  CA4 delay=34 (4~65),Diff = 1 PI (4 cell)

 3134 12:40:38.955800  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 3135 12:40:38.955883  

 3136 12:40:38.959495  CA PerBit enable=1, Macro0, CA PI delay=33

 3137 12:40:38.959577  

 3138 12:40:38.962514  [CBTSetCACLKResult] CA Dly = 33

 3139 12:40:38.962597  CS Dly: 5 (0~36)

 3140 12:40:38.962660  ==

 3141 12:40:38.966475  Dram Type= 6, Freq= 0, CH_1, rank 1

 3142 12:40:38.972657  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3143 12:40:38.972740  ==

 3144 12:40:38.975977  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3145 12:40:38.982731  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37

 3146 12:40:38.991569  [CA 0] Center 38 (8~68) winsize 61

 3147 12:40:38.994875  [CA 1] Center 37 (7~68) winsize 62

 3148 12:40:38.998165  [CA 2] Center 35 (5~66) winsize 62

 3149 12:40:39.001421  [CA 3] Center 34 (4~65) winsize 62

 3150 12:40:39.004748  [CA 4] Center 35 (5~65) winsize 61

 3151 12:40:39.007936  [CA 5] Center 34 (4~64) winsize 61

 3152 12:40:39.008019  

 3153 12:40:39.011749  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3154 12:40:39.011832  

 3155 12:40:39.014522  [CATrainingPosCal] consider 2 rank data

 3156 12:40:39.017893  u2DelayCellTimex100 = 270/100 ps

 3157 12:40:39.021279  CA0 delay=38 (8~68),Diff = 4 PI (19 cell)

 3158 12:40:39.024642  CA1 delay=37 (7~68),Diff = 3 PI (14 cell)

 3159 12:40:39.031445  CA2 delay=35 (5~65),Diff = 1 PI (4 cell)

 3160 12:40:39.034894  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 3161 12:40:39.038048  CA4 delay=35 (5~65),Diff = 1 PI (4 cell)

 3162 12:40:39.041618  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 3163 12:40:39.041692  

 3164 12:40:39.044731  CA PerBit enable=1, Macro0, CA PI delay=34

 3165 12:40:39.044816  

 3166 12:40:39.047903  [CBTSetCACLKResult] CA Dly = 34

 3167 12:40:39.047987  CS Dly: 6 (0~39)

 3168 12:40:39.048053  

 3169 12:40:39.051351  ----->DramcWriteLeveling(PI) begin...

 3170 12:40:39.054734  ==

 3171 12:40:39.058388  Dram Type= 6, Freq= 0, CH_1, rank 0

 3172 12:40:39.061585  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3173 12:40:39.061670  ==

 3174 12:40:39.065072  Write leveling (Byte 0): 24 => 24

 3175 12:40:39.068812  Write leveling (Byte 1): 28 => 28

 3176 12:40:39.071523  DramcWriteLeveling(PI) end<-----

 3177 12:40:39.071608  

 3178 12:40:39.071673  ==

 3179 12:40:39.074725  Dram Type= 6, Freq= 0, CH_1, rank 0

 3180 12:40:39.078506  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3181 12:40:39.078591  ==

 3182 12:40:39.081182  [Gating] SW mode calibration

 3183 12:40:39.088269  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3184 12:40:39.091650  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3185 12:40:39.097933   0 15  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3186 12:40:39.101227   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3187 12:40:39.105027   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3188 12:40:39.111483   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3189 12:40:39.115104   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3190 12:40:39.118281   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 3191 12:40:39.125273   0 15 24 | B1->B0 | 2b2b 2424 | 0 0 | (0 0) (1 0)

 3192 12:40:39.128268   0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3193 12:40:39.131811   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3194 12:40:39.138240   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3195 12:40:39.141492   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3196 12:40:39.144853   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3197 12:40:39.152000   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3198 12:40:39.155150   1  0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 3199 12:40:39.158255   1  0 24 | B1->B0 | 3b3b 4444 | 0 0 | (0 0) (0 0)

 3200 12:40:39.161944   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3201 12:40:39.168731   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3202 12:40:39.172048   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3203 12:40:39.175150   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3204 12:40:39.181983   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3205 12:40:39.185681   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3206 12:40:39.188621   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3207 12:40:39.195554   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3208 12:40:39.198366   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3209 12:40:39.201776   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3210 12:40:39.208331   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3211 12:40:39.212248   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3212 12:40:39.215008   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3213 12:40:39.221645   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3214 12:40:39.225222   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3215 12:40:39.228341   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3216 12:40:39.235052   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3217 12:40:39.238387   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3218 12:40:39.241862   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3219 12:40:39.248523   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3220 12:40:39.251678   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3221 12:40:39.255265   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3222 12:40:39.258549   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 3223 12:40:39.265573   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3224 12:40:39.268563   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3225 12:40:39.271916  Total UI for P1: 0, mck2ui 16

 3226 12:40:39.275403  best dqsien dly found for B0: ( 1,  3, 22)

 3227 12:40:39.278572  Total UI for P1: 0, mck2ui 16

 3228 12:40:39.281922  best dqsien dly found for B1: ( 1,  3, 24)

 3229 12:40:39.285298  best DQS0 dly(MCK, UI, PI) = (1, 3, 22)

 3230 12:40:39.288656  best DQS1 dly(MCK, UI, PI) = (1, 3, 24)

 3231 12:40:39.288737  

 3232 12:40:39.292027  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)

 3233 12:40:39.295455  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)

 3234 12:40:39.298823  [Gating] SW calibration Done

 3235 12:40:39.298905  ==

 3236 12:40:39.301889  Dram Type= 6, Freq= 0, CH_1, rank 0

 3237 12:40:39.305127  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3238 12:40:39.308508  ==

 3239 12:40:39.308590  RX Vref Scan: 0

 3240 12:40:39.308655  

 3241 12:40:39.312170  RX Vref 0 -> 0, step: 1

 3242 12:40:39.312252  

 3243 12:40:39.312317  RX Delay -40 -> 252, step: 8

 3244 12:40:39.318804  iDelay=200, Bit 0, Center 123 (56 ~ 191) 136

 3245 12:40:39.322204  iDelay=200, Bit 1, Center 115 (48 ~ 183) 136

 3246 12:40:39.325508  iDelay=200, Bit 2, Center 107 (40 ~ 175) 136

 3247 12:40:39.329071  iDelay=200, Bit 3, Center 123 (56 ~ 191) 136

 3248 12:40:39.332305  iDelay=200, Bit 4, Center 119 (56 ~ 183) 128

 3249 12:40:39.338984  iDelay=200, Bit 5, Center 127 (64 ~ 191) 128

 3250 12:40:39.342323  iDelay=200, Bit 6, Center 127 (56 ~ 199) 144

 3251 12:40:39.345546  iDelay=200, Bit 7, Center 119 (56 ~ 183) 128

 3252 12:40:39.348719  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 3253 12:40:39.352239  iDelay=200, Bit 9, Center 99 (32 ~ 167) 136

 3254 12:40:39.358984  iDelay=200, Bit 10, Center 115 (48 ~ 183) 136

 3255 12:40:39.362259  iDelay=200, Bit 11, Center 107 (40 ~ 175) 136

 3256 12:40:39.365861  iDelay=200, Bit 12, Center 123 (56 ~ 191) 136

 3257 12:40:39.368926  iDelay=200, Bit 13, Center 119 (48 ~ 191) 144

 3258 12:40:39.372481  iDelay=200, Bit 14, Center 119 (48 ~ 191) 144

 3259 12:40:39.378953  iDelay=200, Bit 15, Center 119 (48 ~ 191) 144

 3260 12:40:39.379036  ==

 3261 12:40:39.382678  Dram Type= 6, Freq= 0, CH_1, rank 0

 3262 12:40:39.385780  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3263 12:40:39.385864  ==

 3264 12:40:39.385931  DQS Delay:

 3265 12:40:39.388890  DQS0 = 0, DQS1 = 0

 3266 12:40:39.388974  DQM Delay:

 3267 12:40:39.392176  DQM0 = 120, DQM1 = 112

 3268 12:40:39.392285  DQ Delay:

 3269 12:40:39.395637  DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123

 3270 12:40:39.398893  DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119

 3271 12:40:39.402106  DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107

 3272 12:40:39.405643  DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119

 3273 12:40:39.405726  

 3274 12:40:39.405791  

 3275 12:40:39.405851  ==

 3276 12:40:39.409048  Dram Type= 6, Freq= 0, CH_1, rank 0

 3277 12:40:39.415658  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3278 12:40:39.415742  ==

 3279 12:40:39.415807  

 3280 12:40:39.415868  

 3281 12:40:39.415926  	TX Vref Scan disable

 3282 12:40:39.419865   == TX Byte 0 ==

 3283 12:40:39.422531  Update DQ  dly =842 (3 ,2, 10)  DQ  OEN =(2 ,7)

 3284 12:40:39.425893  Update DQM dly =842 (3 ,2, 10)  DQM OEN =(2 ,7)

 3285 12:40:39.429181   == TX Byte 1 ==

 3286 12:40:39.432684  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3287 12:40:39.435980  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3288 12:40:39.439647  ==

 3289 12:40:39.439731  Dram Type= 6, Freq= 0, CH_1, rank 0

 3290 12:40:39.446444  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3291 12:40:39.446526  ==

 3292 12:40:39.456953  TX Vref=22, minBit 1, minWin=24, winSum=404

 3293 12:40:39.460409  TX Vref=24, minBit 1, minWin=25, winSum=409

 3294 12:40:39.464160  TX Vref=26, minBit 8, minWin=25, winSum=414

 3295 12:40:39.466978  TX Vref=28, minBit 10, minWin=25, winSum=420

 3296 12:40:39.470653  TX Vref=30, minBit 10, minWin=25, winSum=422

 3297 12:40:39.476951  TX Vref=32, minBit 11, minWin=25, winSum=423

 3298 12:40:39.480350  [TxChooseVref] Worse bit 11, Min win 25, Win sum 423, Final Vref 32

 3299 12:40:39.480433  

 3300 12:40:39.484378  Final TX Range 1 Vref 32

 3301 12:40:39.484459  

 3302 12:40:39.484524  ==

 3303 12:40:39.486984  Dram Type= 6, Freq= 0, CH_1, rank 0

 3304 12:40:39.490565  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3305 12:40:39.493750  ==

 3306 12:40:39.493832  

 3307 12:40:39.493895  

 3308 12:40:39.493984  	TX Vref Scan disable

 3309 12:40:39.497093   == TX Byte 0 ==

 3310 12:40:39.500698  Update DQ  dly =842 (3 ,2, 10)  DQ  OEN =(2 ,7)

 3311 12:40:39.503962  Update DQM dly =842 (3 ,2, 10)  DQM OEN =(2 ,7)

 3312 12:40:39.507254   == TX Byte 1 ==

 3313 12:40:39.510840  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3314 12:40:39.514081  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3315 12:40:39.517167  

 3316 12:40:39.517248  [DATLAT]

 3317 12:40:39.517312  Freq=1200, CH1 RK0

 3318 12:40:39.517372  

 3319 12:40:39.520489  DATLAT Default: 0xd

 3320 12:40:39.520571  0, 0xFFFF, sum = 0

 3321 12:40:39.524107  1, 0xFFFF, sum = 0

 3322 12:40:39.524190  2, 0xFFFF, sum = 0

 3323 12:40:39.527396  3, 0xFFFF, sum = 0

 3324 12:40:39.527479  4, 0xFFFF, sum = 0

 3325 12:40:39.530554  5, 0xFFFF, sum = 0

 3326 12:40:39.530637  6, 0xFFFF, sum = 0

 3327 12:40:39.533855  7, 0xFFFF, sum = 0

 3328 12:40:39.537312  8, 0xFFFF, sum = 0

 3329 12:40:39.537396  9, 0xFFFF, sum = 0

 3330 12:40:39.540865  10, 0xFFFF, sum = 0

 3331 12:40:39.540964  11, 0xFFFF, sum = 0

 3332 12:40:39.544071  12, 0x0, sum = 1

 3333 12:40:39.544154  13, 0x0, sum = 2

 3334 12:40:39.547782  14, 0x0, sum = 3

 3335 12:40:39.547865  15, 0x0, sum = 4

 3336 12:40:39.547930  best_step = 13

 3337 12:40:39.547989  

 3338 12:40:39.550742  ==

 3339 12:40:39.550827  Dram Type= 6, Freq= 0, CH_1, rank 0

 3340 12:40:39.557281  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3341 12:40:39.557363  ==

 3342 12:40:39.557428  RX Vref Scan: 1

 3343 12:40:39.557488  

 3344 12:40:39.560575  Set Vref Range= 32 -> 127

 3345 12:40:39.560656  

 3346 12:40:39.564348  RX Vref 32 -> 127, step: 1

 3347 12:40:39.564428  

 3348 12:40:39.567600  RX Delay -13 -> 252, step: 4

 3349 12:40:39.567688  

 3350 12:40:39.570698  Set Vref, RX VrefLevel [Byte0]: 32

 3351 12:40:39.573972                           [Byte1]: 32

 3352 12:40:39.574066  

 3353 12:40:39.577276  Set Vref, RX VrefLevel [Byte0]: 33

 3354 12:40:39.580811                           [Byte1]: 33

 3355 12:40:39.580891  

 3356 12:40:39.584154  Set Vref, RX VrefLevel [Byte0]: 34

 3357 12:40:39.587372                           [Byte1]: 34

 3358 12:40:39.591501  

 3359 12:40:39.591582  Set Vref, RX VrefLevel [Byte0]: 35

 3360 12:40:39.594747                           [Byte1]: 35

 3361 12:40:39.599315  

 3362 12:40:39.599394  Set Vref, RX VrefLevel [Byte0]: 36

 3363 12:40:39.603123                           [Byte1]: 36

 3364 12:40:39.607184  

 3365 12:40:39.607264  Set Vref, RX VrefLevel [Byte0]: 37

 3366 12:40:39.610554                           [Byte1]: 37

 3367 12:40:39.615075  

 3368 12:40:39.615155  Set Vref, RX VrefLevel [Byte0]: 38

 3369 12:40:39.618983                           [Byte1]: 38

 3370 12:40:39.622915  

 3371 12:40:39.622995  Set Vref, RX VrefLevel [Byte0]: 39

 3372 12:40:39.626362                           [Byte1]: 39

 3373 12:40:39.631045  

 3374 12:40:39.631125  Set Vref, RX VrefLevel [Byte0]: 40

 3375 12:40:39.634337                           [Byte1]: 40

 3376 12:40:39.638740  

 3377 12:40:39.638819  Set Vref, RX VrefLevel [Byte0]: 41

 3378 12:40:39.641913                           [Byte1]: 41

 3379 12:40:39.646635  

 3380 12:40:39.646714  Set Vref, RX VrefLevel [Byte0]: 42

 3381 12:40:39.650094                           [Byte1]: 42

 3382 12:40:39.654401  

 3383 12:40:39.654480  Set Vref, RX VrefLevel [Byte0]: 43

 3384 12:40:39.657892                           [Byte1]: 43

 3385 12:40:39.662392  

 3386 12:40:39.662472  Set Vref, RX VrefLevel [Byte0]: 44

 3387 12:40:39.665722                           [Byte1]: 44

 3388 12:40:39.670217  

 3389 12:40:39.670297  Set Vref, RX VrefLevel [Byte0]: 45

 3390 12:40:39.673916                           [Byte1]: 45

 3391 12:40:39.678219  

 3392 12:40:39.678299  Set Vref, RX VrefLevel [Byte0]: 46

 3393 12:40:39.681371                           [Byte1]: 46

 3394 12:40:39.686270  

 3395 12:40:39.686350  Set Vref, RX VrefLevel [Byte0]: 47

 3396 12:40:39.689339                           [Byte1]: 47

 3397 12:40:39.693784  

 3398 12:40:39.693863  Set Vref, RX VrefLevel [Byte0]: 48

 3399 12:40:39.697324                           [Byte1]: 48

 3400 12:40:39.702220  

 3401 12:40:39.702299  Set Vref, RX VrefLevel [Byte0]: 49

 3402 12:40:39.705377                           [Byte1]: 49

 3403 12:40:39.709710  

 3404 12:40:39.709789  Set Vref, RX VrefLevel [Byte0]: 50

 3405 12:40:39.713088                           [Byte1]: 50

 3406 12:40:39.717563  

 3407 12:40:39.717643  Set Vref, RX VrefLevel [Byte0]: 51

 3408 12:40:39.721342                           [Byte1]: 51

 3409 12:40:39.725795  

 3410 12:40:39.725876  Set Vref, RX VrefLevel [Byte0]: 52

 3411 12:40:39.728813                           [Byte1]: 52

 3412 12:40:39.733450  

 3413 12:40:39.733532  Set Vref, RX VrefLevel [Byte0]: 53

 3414 12:40:39.736796                           [Byte1]: 53

 3415 12:40:39.741493  

 3416 12:40:39.741575  Set Vref, RX VrefLevel [Byte0]: 54

 3417 12:40:39.744531                           [Byte1]: 54

 3418 12:40:39.749286  

 3419 12:40:39.749382  Set Vref, RX VrefLevel [Byte0]: 55

 3420 12:40:39.752650                           [Byte1]: 55

 3421 12:40:39.757172  

 3422 12:40:39.757254  Set Vref, RX VrefLevel [Byte0]: 56

 3423 12:40:39.760342                           [Byte1]: 56

 3424 12:40:39.764879  

 3425 12:40:39.764960  Set Vref, RX VrefLevel [Byte0]: 57

 3426 12:40:39.768683                           [Byte1]: 57

 3427 12:40:39.773101  

 3428 12:40:39.773182  Set Vref, RX VrefLevel [Byte0]: 58

 3429 12:40:39.776254                           [Byte1]: 58

 3430 12:40:39.780814  

 3431 12:40:39.780895  Set Vref, RX VrefLevel [Byte0]: 59

 3432 12:40:39.784012                           [Byte1]: 59

 3433 12:40:39.789401  

 3434 12:40:39.789482  Set Vref, RX VrefLevel [Byte0]: 60

 3435 12:40:39.792068                           [Byte1]: 60

 3436 12:40:39.796733  

 3437 12:40:39.796815  Set Vref, RX VrefLevel [Byte0]: 61

 3438 12:40:39.799891                           [Byte1]: 61

 3439 12:40:39.804547  

 3440 12:40:39.804629  Set Vref, RX VrefLevel [Byte0]: 62

 3441 12:40:39.807766                           [Byte1]: 62

 3442 12:40:39.812226  

 3443 12:40:39.812308  Set Vref, RX VrefLevel [Byte0]: 63

 3444 12:40:39.816064                           [Byte1]: 63

 3445 12:40:39.820399  

 3446 12:40:39.820490  Set Vref, RX VrefLevel [Byte0]: 64

 3447 12:40:39.823454                           [Byte1]: 64

 3448 12:40:39.828135  

 3449 12:40:39.828223  Set Vref, RX VrefLevel [Byte0]: 65

 3450 12:40:39.831376                           [Byte1]: 65

 3451 12:40:39.835841  

 3452 12:40:39.835925  Set Vref, RX VrefLevel [Byte0]: 66

 3453 12:40:39.839400                           [Byte1]: 66

 3454 12:40:39.843790  

 3455 12:40:39.843874  Set Vref, RX VrefLevel [Byte0]: 67

 3456 12:40:39.847324                           [Byte1]: 67

 3457 12:40:39.851860  

 3458 12:40:39.852003  Final RX Vref Byte 0 = 54 to rank0

 3459 12:40:39.855218  Final RX Vref Byte 1 = 53 to rank0

 3460 12:40:39.858340  Final RX Vref Byte 0 = 54 to rank1

 3461 12:40:39.862243  Final RX Vref Byte 1 = 53 to rank1==

 3462 12:40:39.864965  Dram Type= 6, Freq= 0, CH_1, rank 0

 3463 12:40:39.871933  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3464 12:40:39.872063  ==

 3465 12:40:39.872131  DQS Delay:

 3466 12:40:39.872193  DQS0 = 0, DQS1 = 0

 3467 12:40:39.875193  DQM Delay:

 3468 12:40:39.875318  DQM0 = 119, DQM1 = 112

 3469 12:40:39.878474  DQ Delay:

 3470 12:40:39.881981  DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118

 3471 12:40:39.884998  DQ4 =118, DQ5 =126, DQ6 =130, DQ7 =116

 3472 12:40:39.888490  DQ8 =102, DQ9 =98, DQ10 =114, DQ11 =106

 3473 12:40:39.891669  DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =118

 3474 12:40:39.891814  

 3475 12:40:39.891927  

 3476 12:40:39.898434  [DQSOSCAuto] RK0, (LSB)MR18= 0x317, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps

 3477 12:40:39.902101  CH1 RK0: MR19=404, MR18=317

 3478 12:40:39.908369  CH1_RK0: MR19=0x404, MR18=0x317, DQSOSC=401, MR23=63, INC=40, DEC=27

 3479 12:40:39.908479  

 3480 12:40:39.912091  ----->DramcWriteLeveling(PI) begin...

 3481 12:40:39.912196  ==

 3482 12:40:39.915078  Dram Type= 6, Freq= 0, CH_1, rank 1

 3483 12:40:39.918417  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3484 12:40:39.918524  ==

 3485 12:40:39.921779  Write leveling (Byte 0): 24 => 24

 3486 12:40:39.925051  Write leveling (Byte 1): 28 => 28

 3487 12:40:39.928491  DramcWriteLeveling(PI) end<-----

 3488 12:40:39.928623  

 3489 12:40:39.928721  ==

 3490 12:40:39.931681  Dram Type= 6, Freq= 0, CH_1, rank 1

 3491 12:40:39.938651  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3492 12:40:39.938767  ==

 3493 12:40:39.938856  [Gating] SW mode calibration

 3494 12:40:39.948442  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3495 12:40:39.951574  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3496 12:40:39.955483   0 15  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3497 12:40:39.961590   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3498 12:40:39.965077   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3499 12:40:39.967931   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3500 12:40:39.974721   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3501 12:40:39.978212   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)

 3502 12:40:39.981824   0 15 24 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 0)

 3503 12:40:39.988140   0 15 28 | B1->B0 | 2323 2727 | 0 0 | (1 0) (0 0)

 3504 12:40:39.991399   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3505 12:40:39.994923   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3506 12:40:40.001685   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3507 12:40:40.004958   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3508 12:40:40.008204   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3509 12:40:40.014732   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3510 12:40:40.018161   1  0 24 | B1->B0 | 3c3c 2727 | 0 0 | (0 0) (0 0)

 3511 12:40:40.021724   1  0 28 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)

 3512 12:40:40.028478   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3513 12:40:40.031578   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3514 12:40:40.034974   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3515 12:40:40.038668   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3516 12:40:40.044979   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3517 12:40:40.048080   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3518 12:40:40.051661   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3519 12:40:40.058326   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3520 12:40:40.061608   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3521 12:40:40.064981   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3522 12:40:40.071404   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3523 12:40:40.074621   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3524 12:40:40.078094   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3525 12:40:40.084912   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3526 12:40:40.088689   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3527 12:40:40.091362   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3528 12:40:40.098293   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3529 12:40:40.101692   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3530 12:40:40.105018   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3531 12:40:40.111592   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3532 12:40:40.115080   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3533 12:40:40.118162   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 3534 12:40:40.124977   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3535 12:40:40.128449   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3536 12:40:40.131615  Total UI for P1: 0, mck2ui 16

 3537 12:40:40.134889  best dqsien dly found for B0: ( 1,  3, 22)

 3538 12:40:40.138252  Total UI for P1: 0, mck2ui 16

 3539 12:40:40.141669  best dqsien dly found for B1: ( 1,  3, 24)

 3540 12:40:40.145007  best DQS0 dly(MCK, UI, PI) = (1, 3, 22)

 3541 12:40:40.148176  best DQS1 dly(MCK, UI, PI) = (1, 3, 24)

 3542 12:40:40.148261  

 3543 12:40:40.151902  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)

 3544 12:40:40.154978  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)

 3545 12:40:40.158042  [Gating] SW calibration Done

 3546 12:40:40.158126  ==

 3547 12:40:40.161359  Dram Type= 6, Freq= 0, CH_1, rank 1

 3548 12:40:40.164601  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3549 12:40:40.164685  ==

 3550 12:40:40.168230  RX Vref Scan: 0

 3551 12:40:40.168315  

 3552 12:40:40.171288  RX Vref 0 -> 0, step: 1

 3553 12:40:40.171371  

 3554 12:40:40.171437  RX Delay -40 -> 252, step: 8

 3555 12:40:40.178079  iDelay=200, Bit 0, Center 127 (64 ~ 191) 128

 3556 12:40:40.181386  iDelay=200, Bit 1, Center 115 (48 ~ 183) 136

 3557 12:40:40.184767  iDelay=200, Bit 2, Center 107 (40 ~ 175) 136

 3558 12:40:40.187802  iDelay=200, Bit 3, Center 119 (48 ~ 191) 144

 3559 12:40:40.191455  iDelay=200, Bit 4, Center 123 (56 ~ 191) 136

 3560 12:40:40.197905  iDelay=200, Bit 5, Center 131 (64 ~ 199) 136

 3561 12:40:40.201404  iDelay=200, Bit 6, Center 127 (64 ~ 191) 128

 3562 12:40:40.204433  iDelay=200, Bit 7, Center 119 (48 ~ 191) 144

 3563 12:40:40.208143  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 3564 12:40:40.211077  iDelay=200, Bit 9, Center 99 (32 ~ 167) 136

 3565 12:40:40.217723  iDelay=200, Bit 10, Center 115 (48 ~ 183) 136

 3566 12:40:40.221029  iDelay=200, Bit 11, Center 107 (40 ~ 175) 136

 3567 12:40:40.224331  iDelay=200, Bit 12, Center 119 (48 ~ 191) 144

 3568 12:40:40.227820  iDelay=200, Bit 13, Center 119 (48 ~ 191) 144

 3569 12:40:40.230996  iDelay=200, Bit 14, Center 119 (48 ~ 191) 144

 3570 12:40:40.237349  iDelay=200, Bit 15, Center 123 (48 ~ 199) 152

 3571 12:40:40.237434  ==

 3572 12:40:40.240831  Dram Type= 6, Freq= 0, CH_1, rank 1

 3573 12:40:40.244317  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3574 12:40:40.244401  ==

 3575 12:40:40.244466  DQS Delay:

 3576 12:40:40.247406  DQS0 = 0, DQS1 = 0

 3577 12:40:40.247489  DQM Delay:

 3578 12:40:40.250827  DQM0 = 121, DQM1 = 112

 3579 12:40:40.250911  DQ Delay:

 3580 12:40:40.253910  DQ0 =127, DQ1 =115, DQ2 =107, DQ3 =119

 3581 12:40:40.258054  DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =119

 3582 12:40:40.261116  DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107

 3583 12:40:40.264296  DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =123

 3584 12:40:40.264379  

 3585 12:40:40.264444  

 3586 12:40:40.267723  ==

 3587 12:40:40.270850  Dram Type= 6, Freq= 0, CH_1, rank 1

 3588 12:40:40.274008  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3589 12:40:40.274125  ==

 3590 12:40:40.274225  

 3591 12:40:40.274318  

 3592 12:40:40.277746  	TX Vref Scan disable

 3593 12:40:40.277877   == TX Byte 0 ==

 3594 12:40:40.280777  Update DQ  dly =843 (3 ,2, 11)  DQ  OEN =(2 ,7)

 3595 12:40:40.287946  Update DQM dly =843 (3 ,2, 11)  DQM OEN =(2 ,7)

 3596 12:40:40.288096   == TX Byte 1 ==

 3597 12:40:40.291006  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3598 12:40:40.297617  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3599 12:40:40.297743  ==

 3600 12:40:40.300810  Dram Type= 6, Freq= 0, CH_1, rank 1

 3601 12:40:40.303939  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3602 12:40:40.304054  ==

 3603 12:40:40.316064  TX Vref=22, minBit 1, minWin=25, winSum=415

 3604 12:40:40.319496  TX Vref=24, minBit 3, minWin=25, winSum=423

 3605 12:40:40.322861  TX Vref=26, minBit 1, minWin=25, winSum=423

 3606 12:40:40.326227  TX Vref=28, minBit 3, minWin=26, winSum=426

 3607 12:40:40.329586  TX Vref=30, minBit 1, minWin=26, winSum=427

 3608 12:40:40.333060  TX Vref=32, minBit 9, minWin=25, winSum=425

 3609 12:40:40.339949  [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 30

 3610 12:40:40.340072  

 3611 12:40:40.343226  Final TX Range 1 Vref 30

 3612 12:40:40.343338  

 3613 12:40:40.343436  ==

 3614 12:40:40.346464  Dram Type= 6, Freq= 0, CH_1, rank 1

 3615 12:40:40.350032  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3616 12:40:40.350148  ==

 3617 12:40:40.350246  

 3618 12:40:40.352945  

 3619 12:40:40.353050  	TX Vref Scan disable

 3620 12:40:40.356337   == TX Byte 0 ==

 3621 12:40:40.359773  Update DQ  dly =842 (3 ,2, 10)  DQ  OEN =(2 ,7)

 3622 12:40:40.362697  Update DQM dly =842 (3 ,2, 10)  DQM OEN =(2 ,7)

 3623 12:40:40.366395   == TX Byte 1 ==

 3624 12:40:40.369454  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3625 12:40:40.373335  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3626 12:40:40.373446  

 3627 12:40:40.376363  [DATLAT]

 3628 12:40:40.376471  Freq=1200, CH1 RK1

 3629 12:40:40.376570  

 3630 12:40:40.379378  DATLAT Default: 0xd

 3631 12:40:40.379489  0, 0xFFFF, sum = 0

 3632 12:40:40.382866  1, 0xFFFF, sum = 0

 3633 12:40:40.382979  2, 0xFFFF, sum = 0

 3634 12:40:40.386171  3, 0xFFFF, sum = 0

 3635 12:40:40.386281  4, 0xFFFF, sum = 0

 3636 12:40:40.389807  5, 0xFFFF, sum = 0

 3637 12:40:40.389915  6, 0xFFFF, sum = 0

 3638 12:40:40.393089  7, 0xFFFF, sum = 0

 3639 12:40:40.396213  8, 0xFFFF, sum = 0

 3640 12:40:40.396326  9, 0xFFFF, sum = 0

 3641 12:40:40.399395  10, 0xFFFF, sum = 0

 3642 12:40:40.399503  11, 0xFFFF, sum = 0

 3643 12:40:40.402709  12, 0x0, sum = 1

 3644 12:40:40.402827  13, 0x0, sum = 2

 3645 12:40:40.406132  14, 0x0, sum = 3

 3646 12:40:40.406244  15, 0x0, sum = 4

 3647 12:40:40.406342  best_step = 13

 3648 12:40:40.406438  

 3649 12:40:40.409176  ==

 3650 12:40:40.412765  Dram Type= 6, Freq= 0, CH_1, rank 1

 3651 12:40:40.416136  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3652 12:40:40.416258  ==

 3653 12:40:40.416368  RX Vref Scan: 0

 3654 12:40:40.416473  

 3655 12:40:40.419428  RX Vref 0 -> 0, step: 1

 3656 12:40:40.419545  

 3657 12:40:40.422618  RX Delay -13 -> 252, step: 4

 3658 12:40:40.426093  iDelay=195, Bit 0, Center 122 (63 ~ 182) 120

 3659 12:40:40.432476  iDelay=195, Bit 1, Center 114 (55 ~ 174) 120

 3660 12:40:40.435899  iDelay=195, Bit 2, Center 108 (51 ~ 166) 116

 3661 12:40:40.439265  iDelay=195, Bit 3, Center 120 (59 ~ 182) 124

 3662 12:40:40.442526  iDelay=195, Bit 4, Center 122 (63 ~ 182) 120

 3663 12:40:40.445874  iDelay=195, Bit 5, Center 130 (67 ~ 194) 128

 3664 12:40:40.449717  iDelay=195, Bit 6, Center 128 (67 ~ 190) 124

 3665 12:40:40.456323  iDelay=195, Bit 7, Center 116 (55 ~ 178) 124

 3666 12:40:40.459241  iDelay=195, Bit 8, Center 98 (35 ~ 162) 128

 3667 12:40:40.462730  iDelay=195, Bit 9, Center 102 (39 ~ 166) 128

 3668 12:40:40.465849  iDelay=195, Bit 10, Center 112 (47 ~ 178) 132

 3669 12:40:40.472760  iDelay=195, Bit 11, Center 108 (43 ~ 174) 132

 3670 12:40:40.475626  iDelay=195, Bit 12, Center 122 (59 ~ 186) 128

 3671 12:40:40.479366  iDelay=195, Bit 13, Center 118 (55 ~ 182) 128

 3672 12:40:40.482610  iDelay=195, Bit 14, Center 122 (59 ~ 186) 128

 3673 12:40:40.486209  iDelay=195, Bit 15, Center 124 (59 ~ 190) 132

 3674 12:40:40.486293  ==

 3675 12:40:40.489032  Dram Type= 6, Freq= 0, CH_1, rank 1

 3676 12:40:40.495749  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3677 12:40:40.495833  ==

 3678 12:40:40.495899  DQS Delay:

 3679 12:40:40.499282  DQS0 = 0, DQS1 = 0

 3680 12:40:40.499366  DQM Delay:

 3681 12:40:40.502843  DQM0 = 120, DQM1 = 113

 3682 12:40:40.502927  DQ Delay:

 3683 12:40:40.506108  DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =120

 3684 12:40:40.509469  DQ4 =122, DQ5 =130, DQ6 =128, DQ7 =116

 3685 12:40:40.512360  DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =108

 3686 12:40:40.515980  DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124

 3687 12:40:40.516064  

 3688 12:40:40.516129  

 3689 12:40:40.525763  [DQSOSCAuto] RK1, (LSB)MR18= 0xcf0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 405 ps

 3690 12:40:40.525848  CH1 RK1: MR19=403, MR18=CF0

 3691 12:40:40.532723  CH1_RK1: MR19=0x403, MR18=0xCF0, DQSOSC=405, MR23=63, INC=39, DEC=26

 3692 12:40:40.535990  [RxdqsGatingPostProcess] freq 1200

 3693 12:40:40.542429  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3694 12:40:40.545895  best DQS0 dly(2T, 0.5T) = (0, 11)

 3695 12:40:40.549096  best DQS1 dly(2T, 0.5T) = (0, 11)

 3696 12:40:40.552462  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3697 12:40:40.555871  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3698 12:40:40.555955  best DQS0 dly(2T, 0.5T) = (0, 11)

 3699 12:40:40.559968  best DQS1 dly(2T, 0.5T) = (0, 11)

 3700 12:40:40.562791  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3701 12:40:40.566088  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3702 12:40:40.569734  Pre-setting of DQS Precalculation

 3703 12:40:40.575997  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3704 12:40:40.583065  sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2

 3705 12:40:40.589235  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 3706 12:40:40.589320  

 3707 12:40:40.589390  

 3708 12:40:40.592533  [Calibration Summary] 2400 Mbps

 3709 12:40:40.592619  CH 0, Rank 0

 3710 12:40:40.596058  SW Impedance     : PASS

 3711 12:40:40.599119  DUTY Scan        : NO K

 3712 12:40:40.599203  ZQ Calibration   : PASS

 3713 12:40:40.602362  Jitter Meter     : NO K

 3714 12:40:40.605764  CBT Training     : PASS

 3715 12:40:40.605847  Write leveling   : PASS

 3716 12:40:40.608955  RX DQS gating    : PASS

 3717 12:40:40.612387  RX DQ/DQS(RDDQC) : PASS

 3718 12:40:40.612470  TX DQ/DQS        : PASS

 3719 12:40:40.615763  RX DATLAT        : PASS

 3720 12:40:40.615846  RX DQ/DQS(Engine): PASS

 3721 12:40:40.619133  TX OE            : NO K

 3722 12:40:40.619217  All Pass.

 3723 12:40:40.619281  

 3724 12:40:40.622417  CH 0, Rank 1

 3725 12:40:40.622500  SW Impedance     : PASS

 3726 12:40:40.625704  DUTY Scan        : NO K

 3727 12:40:40.628899  ZQ Calibration   : PASS

 3728 12:40:40.628982  Jitter Meter     : NO K

 3729 12:40:40.632323  CBT Training     : PASS

 3730 12:40:40.635760  Write leveling   : PASS

 3731 12:40:40.635843  RX DQS gating    : PASS

 3732 12:40:40.638895  RX DQ/DQS(RDDQC) : PASS

 3733 12:40:40.642083  TX DQ/DQS        : PASS

 3734 12:40:40.642168  RX DATLAT        : PASS

 3735 12:40:40.645497  RX DQ/DQS(Engine): PASS

 3736 12:40:40.648891  TX OE            : NO K

 3737 12:40:40.648975  All Pass.

 3738 12:40:40.649040  

 3739 12:40:40.649100  CH 1, Rank 0

 3740 12:40:40.652242  SW Impedance     : PASS

 3741 12:40:40.655535  DUTY Scan        : NO K

 3742 12:40:40.655618  ZQ Calibration   : PASS

 3743 12:40:40.658957  Jitter Meter     : NO K

 3744 12:40:40.661958  CBT Training     : PASS

 3745 12:40:40.662059  Write leveling   : PASS

 3746 12:40:40.665683  RX DQS gating    : PASS

 3747 12:40:40.668947  RX DQ/DQS(RDDQC) : PASS

 3748 12:40:40.669030  TX DQ/DQS        : PASS

 3749 12:40:40.671925  RX DATLAT        : PASS

 3750 12:40:40.675363  RX DQ/DQS(Engine): PASS

 3751 12:40:40.675446  TX OE            : NO K

 3752 12:40:40.675513  All Pass.

 3753 12:40:40.678917  

 3754 12:40:40.679000  CH 1, Rank 1

 3755 12:40:40.681906  SW Impedance     : PASS

 3756 12:40:40.682033  DUTY Scan        : NO K

 3757 12:40:40.685672  ZQ Calibration   : PASS

 3758 12:40:40.685755  Jitter Meter     : NO K

 3759 12:40:40.688739  CBT Training     : PASS

 3760 12:40:40.691624  Write leveling   : PASS

 3761 12:40:40.691708  RX DQS gating    : PASS

 3762 12:40:40.695083  RX DQ/DQS(RDDQC) : PASS

 3763 12:40:40.698507  TX DQ/DQS        : PASS

 3764 12:40:40.698591  RX DATLAT        : PASS

 3765 12:40:40.701546  RX DQ/DQS(Engine): PASS

 3766 12:40:40.705370  TX OE            : NO K

 3767 12:40:40.705455  All Pass.

 3768 12:40:40.705519  

 3769 12:40:40.708333  DramC Write-DBI off

 3770 12:40:40.708416  	PER_BANK_REFRESH: Hybrid Mode

 3771 12:40:40.711550  TX_TRACKING: ON

 3772 12:40:40.721728  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1

 3773 12:40:40.724951  [FAST_K] Save calibration result to emmc

 3774 12:40:40.728200  dramc_set_vcore_voltage set vcore to 650000

 3775 12:40:40.728284  Read voltage for 600, 5

 3776 12:40:40.731274  Vio18 = 0

 3777 12:40:40.731358  Vcore = 650000

 3778 12:40:40.731423  Vdram = 0

 3779 12:40:40.734696  Vddq = 0

 3780 12:40:40.734796  Vmddr = 0

 3781 12:40:40.741178  [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0

 3782 12:40:40.744584  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 3783 12:40:40.747973  MEM_TYPE=3, freq_sel=19

 3784 12:40:40.751116  sv_algorithm_assistance_LP4_1600 

 3785 12:40:40.754366  ============ PULL DRAM RESETB DOWN ============

 3786 12:40:40.758239  ========== PULL DRAM RESETB DOWN end =========

 3787 12:40:40.764627  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3788 12:40:40.767551  =================================== 

 3789 12:40:40.767636  LPDDR4 DRAM CONFIGURATION

 3790 12:40:40.771009  =================================== 

 3791 12:40:40.774317  EX_ROW_EN[0]    = 0x0

 3792 12:40:40.777485  EX_ROW_EN[1]    = 0x0

 3793 12:40:40.777569  LP4Y_EN      = 0x0

 3794 12:40:40.781030  WORK_FSP     = 0x0

 3795 12:40:40.781113  WL           = 0x2

 3796 12:40:40.784527  RL           = 0x2

 3797 12:40:40.784610  BL           = 0x2

 3798 12:40:40.787591  RPST         = 0x0

 3799 12:40:40.787675  RD_PRE       = 0x0

 3800 12:40:40.790936  WR_PRE       = 0x1

 3801 12:40:40.791020  WR_PST       = 0x0

 3802 12:40:40.793965  DBI_WR       = 0x0

 3803 12:40:40.794063  DBI_RD       = 0x0

 3804 12:40:40.797393  OTF          = 0x1

 3805 12:40:40.800905  =================================== 

 3806 12:40:40.804018  =================================== 

 3807 12:40:40.804102  ANA top config

 3808 12:40:40.807381  =================================== 

 3809 12:40:40.810842  DLL_ASYNC_EN            =  0

 3810 12:40:40.814136  ALL_SLAVE_EN            =  1

 3811 12:40:40.817537  NEW_RANK_MODE           =  1

 3812 12:40:40.817623  DLL_IDLE_MODE           =  1

 3813 12:40:40.820750  LP45_APHY_COMB_EN       =  1

 3814 12:40:40.823896  TX_ODT_DIS              =  1

 3815 12:40:40.827000  NEW_8X_MODE             =  1

 3816 12:40:40.830430  =================================== 

 3817 12:40:40.833910  =================================== 

 3818 12:40:40.836989  data_rate                  = 1200

 3819 12:40:40.837073  CKR                        = 1

 3820 12:40:40.840405  DQ_P2S_RATIO               = 8

 3821 12:40:40.843798  =================================== 

 3822 12:40:40.846984  CA_P2S_RATIO               = 8

 3823 12:40:40.850522  DQ_CA_OPEN                 = 0

 3824 12:40:40.853639  DQ_SEMI_OPEN               = 0

 3825 12:40:40.857141  CA_SEMI_OPEN               = 0

 3826 12:40:40.857228  CA_FULL_RATE               = 0

 3827 12:40:40.860282  DQ_CKDIV4_EN               = 1

 3828 12:40:40.863896  CA_CKDIV4_EN               = 1

 3829 12:40:40.866845  CA_PREDIV_EN               = 0

 3830 12:40:40.869977  PH8_DLY                    = 0

 3831 12:40:40.873632  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 3832 12:40:40.873739  DQ_AAMCK_DIV               = 4

 3833 12:40:40.877224  CA_AAMCK_DIV               = 4

 3834 12:40:40.879955  CA_ADMCK_DIV               = 4

 3835 12:40:40.883270  DQ_TRACK_CA_EN             = 0

 3836 12:40:40.886919  CA_PICK                    = 600

 3837 12:40:40.889965  CA_MCKIO                   = 600

 3838 12:40:40.893675  MCKIO_SEMI                 = 0

 3839 12:40:40.893758  PLL_FREQ                   = 2288

 3840 12:40:40.896800  DQ_UI_PI_RATIO             = 32

 3841 12:40:40.899952  CA_UI_PI_RATIO             = 0

 3842 12:40:40.903144  =================================== 

 3843 12:40:40.906748  =================================== 

 3844 12:40:40.910047  memory_type:LPDDR4         

 3845 12:40:40.910130  GP_NUM     : 10       

 3846 12:40:40.913434  SRAM_EN    : 1       

 3847 12:40:40.916476  MD32_EN    : 0       

 3848 12:40:40.919993  =================================== 

 3849 12:40:40.920076  [ANA_INIT] >>>>>>>>>>>>>> 

 3850 12:40:40.923309  <<<<<< [CONFIGURE PHASE]: ANA_TX

 3851 12:40:40.926953  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 3852 12:40:40.930215  =================================== 

 3853 12:40:40.933342  data_rate = 1200,PCW = 0X5800

 3854 12:40:40.936602  =================================== 

 3855 12:40:40.939841  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 3856 12:40:40.946659  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3857 12:40:40.949857  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3858 12:40:40.956227  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 3859 12:40:40.959588  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 3860 12:40:40.963018  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 3861 12:40:40.966352  [ANA_INIT] flow start 

 3862 12:40:40.966437  [ANA_INIT] PLL >>>>>>>> 

 3863 12:40:40.969351  [ANA_INIT] PLL <<<<<<<< 

 3864 12:40:40.972725  [ANA_INIT] MIDPI >>>>>>>> 

 3865 12:40:40.972829  [ANA_INIT] MIDPI <<<<<<<< 

 3866 12:40:40.976194  [ANA_INIT] DLL >>>>>>>> 

 3867 12:40:40.979572  [ANA_INIT] flow end 

 3868 12:40:40.982916  ============ LP4 DIFF to SE enter ============

 3869 12:40:40.985978  ============ LP4 DIFF to SE exit  ============

 3870 12:40:40.989471  [ANA_INIT] <<<<<<<<<<<<< 

 3871 12:40:40.992267  [Flow] Enable top DCM control >>>>> 

 3872 12:40:40.995820  [Flow] Enable top DCM control <<<<< 

 3873 12:40:40.999058  Enable DLL master slave shuffle 

 3874 12:40:41.002364  ============================================================== 

 3875 12:40:41.005642  Gating Mode config

 3876 12:40:41.012509  ============================================================== 

 3877 12:40:41.012598  Config description: 

 3878 12:40:41.022130  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 3879 12:40:41.029150  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 3880 12:40:41.035593  SELPH_MODE            0: By rank         1: By Phase 

 3881 12:40:41.039046  ============================================================== 

 3882 12:40:41.042278  GAT_TRACK_EN                 =  1

 3883 12:40:41.045312  RX_GATING_MODE               =  2

 3884 12:40:41.048906  RX_GATING_TRACK_MODE         =  2

 3885 12:40:41.052258  SELPH_MODE                   =  1

 3886 12:40:41.055594  PICG_EARLY_EN                =  1

 3887 12:40:41.059046  VALID_LAT_VALUE              =  1

 3888 12:40:41.062077  ============================================================== 

 3889 12:40:41.065470  Enter into Gating configuration >>>> 

 3890 12:40:41.069004  Exit from Gating configuration <<<< 

 3891 12:40:41.072226  Enter into  DVFS_PRE_config >>>>> 

 3892 12:40:41.085383  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 3893 12:40:41.085471  Exit from  DVFS_PRE_config <<<<< 

 3894 12:40:41.088715  Enter into PICG configuration >>>> 

 3895 12:40:41.091992  Exit from PICG configuration <<<< 

 3896 12:40:41.095715  [RX_INPUT] configuration >>>>> 

 3897 12:40:41.098881  [RX_INPUT] configuration <<<<< 

 3898 12:40:41.105638  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 3899 12:40:41.108887  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 3900 12:40:41.115440  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 3901 12:40:41.122352  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 3902 12:40:41.128684  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 3903 12:40:41.135373  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 3904 12:40:41.138736  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 3905 12:40:41.141871  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 3906 12:40:41.145573  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 3907 12:40:41.152125  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 3908 12:40:41.155451  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 3909 12:40:41.158708  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3910 12:40:41.161915  =================================== 

 3911 12:40:41.165375  LPDDR4 DRAM CONFIGURATION

 3912 12:40:41.168658  =================================== 

 3913 12:40:41.168735  EX_ROW_EN[0]    = 0x0

 3914 12:40:41.171793  EX_ROW_EN[1]    = 0x0

 3915 12:40:41.175099  LP4Y_EN      = 0x0

 3916 12:40:41.175174  WORK_FSP     = 0x0

 3917 12:40:41.178398  WL           = 0x2

 3918 12:40:41.178472  RL           = 0x2

 3919 12:40:41.181711  BL           = 0x2

 3920 12:40:41.181788  RPST         = 0x0

 3921 12:40:41.185551  RD_PRE       = 0x0

 3922 12:40:41.185628  WR_PRE       = 0x1

 3923 12:40:41.188599  WR_PST       = 0x0

 3924 12:40:41.188674  DBI_WR       = 0x0

 3925 12:40:41.191904  DBI_RD       = 0x0

 3926 12:40:41.191998  OTF          = 0x1

 3927 12:40:41.195059  =================================== 

 3928 12:40:41.198207  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 3929 12:40:41.205157  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 3930 12:40:41.208599  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3931 12:40:41.212113  =================================== 

 3932 12:40:41.215446  LPDDR4 DRAM CONFIGURATION

 3933 12:40:41.218702  =================================== 

 3934 12:40:41.218779  EX_ROW_EN[0]    = 0x10

 3935 12:40:41.221934  EX_ROW_EN[1]    = 0x0

 3936 12:40:41.222047  LP4Y_EN      = 0x0

 3937 12:40:41.225435  WORK_FSP     = 0x0

 3938 12:40:41.228265  WL           = 0x2

 3939 12:40:41.228340  RL           = 0x2

 3940 12:40:41.231659  BL           = 0x2

 3941 12:40:41.231731  RPST         = 0x0

 3942 12:40:41.234882  RD_PRE       = 0x0

 3943 12:40:41.234966  WR_PRE       = 0x1

 3944 12:40:41.238573  WR_PST       = 0x0

 3945 12:40:41.238657  DBI_WR       = 0x0

 3946 12:40:41.241578  DBI_RD       = 0x0

 3947 12:40:41.241663  OTF          = 0x1

 3948 12:40:41.245062  =================================== 

 3949 12:40:41.251548  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 3950 12:40:41.255895  nWR fixed to 30

 3951 12:40:41.258968  [ModeRegInit_LP4] CH0 RK0

 3952 12:40:41.259053  [ModeRegInit_LP4] CH0 RK1

 3953 12:40:41.262395  [ModeRegInit_LP4] CH1 RK0

 3954 12:40:41.265870  [ModeRegInit_LP4] CH1 RK1

 3955 12:40:41.266011  match AC timing 17

 3956 12:40:41.272161  dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1

 3957 12:40:41.275692  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 3958 12:40:41.278710  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 3959 12:40:41.285564  [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17

 3960 12:40:41.288983  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

 3961 12:40:41.289068  ==

 3962 12:40:41.292105  Dram Type= 6, Freq= 0, CH_0, rank 0

 3963 12:40:41.295969  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3964 12:40:41.296097  ==

 3965 12:40:41.302119  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3966 12:40:41.308693  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 3967 12:40:41.312061  [CA 0] Center 36 (6~67) winsize 62

 3968 12:40:41.315537  [CA 1] Center 36 (6~67) winsize 62

 3969 12:40:41.318708  [CA 2] Center 34 (4~65) winsize 62

 3970 12:40:41.322127  [CA 3] Center 34 (4~65) winsize 62

 3971 12:40:41.325242  [CA 4] Center 34 (4~65) winsize 62

 3972 12:40:41.328595  [CA 5] Center 33 (3~64) winsize 62

 3973 12:40:41.328679  

 3974 12:40:41.331888  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3975 12:40:41.331972  

 3976 12:40:41.335319  [CATrainingPosCal] consider 1 rank data

 3977 12:40:41.338617  u2DelayCellTimex100 = 270/100 ps

 3978 12:40:41.341885  CA0 delay=36 (6~67),Diff = 3 PI (28 cell)

 3979 12:40:41.345498  CA1 delay=36 (6~67),Diff = 3 PI (28 cell)

 3980 12:40:41.348699  CA2 delay=34 (4~65),Diff = 1 PI (9 cell)

 3981 12:40:41.351934  CA3 delay=34 (4~65),Diff = 1 PI (9 cell)

 3982 12:40:41.355608  CA4 delay=34 (4~65),Diff = 1 PI (9 cell)

 3983 12:40:41.358688  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 3984 12:40:41.361990  

 3985 12:40:41.365382  CA PerBit enable=1, Macro0, CA PI delay=33

 3986 12:40:41.365457  

 3987 12:40:41.368879  [CBTSetCACLKResult] CA Dly = 33

 3988 12:40:41.368954  CS Dly: 4 (0~35)

 3989 12:40:41.369045  ==

 3990 12:40:41.372033  Dram Type= 6, Freq= 0, CH_0, rank 1

 3991 12:40:41.375350  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3992 12:40:41.375425  ==

 3993 12:40:41.381794  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3994 12:40:41.388253  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33

 3995 12:40:41.391863  [CA 0] Center 36 (6~67) winsize 62

 3996 12:40:41.395083  [CA 1] Center 37 (7~67) winsize 61

 3997 12:40:41.398414  [CA 2] Center 35 (5~66) winsize 62

 3998 12:40:41.401613  [CA 3] Center 35 (4~66) winsize 63

 3999 12:40:41.404756  [CA 4] Center 34 (4~65) winsize 62

 4000 12:40:41.408093  [CA 5] Center 34 (3~65) winsize 63

 4001 12:40:41.408178  

 4002 12:40:41.411598  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 4003 12:40:41.411682  

 4004 12:40:41.414998  [CATrainingPosCal] consider 2 rank data

 4005 12:40:41.417913  u2DelayCellTimex100 = 270/100 ps

 4006 12:40:41.421578  CA0 delay=36 (6~67),Diff = 3 PI (28 cell)

 4007 12:40:41.424562  CA1 delay=37 (7~67),Diff = 4 PI (38 cell)

 4008 12:40:41.428192  CA2 delay=35 (5~65),Diff = 2 PI (19 cell)

 4009 12:40:41.434500  CA3 delay=34 (4~65),Diff = 1 PI (9 cell)

 4010 12:40:41.438176  CA4 delay=34 (4~65),Diff = 1 PI (9 cell)

 4011 12:40:41.441453  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 4012 12:40:41.441537  

 4013 12:40:41.444453  CA PerBit enable=1, Macro0, CA PI delay=33

 4014 12:40:41.444537  

 4015 12:40:41.447730  [CBTSetCACLKResult] CA Dly = 33

 4016 12:40:41.447814  CS Dly: 5 (0~37)

 4017 12:40:41.447881  

 4018 12:40:41.451307  ----->DramcWriteLeveling(PI) begin...

 4019 12:40:41.454486  ==

 4020 12:40:41.454570  Dram Type= 6, Freq= 0, CH_0, rank 0

 4021 12:40:41.460956  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4022 12:40:41.461041  ==

 4023 12:40:41.464427  Write leveling (Byte 0): 31 => 31

 4024 12:40:41.467698  Write leveling (Byte 1): 31 => 31

 4025 12:40:41.470964  DramcWriteLeveling(PI) end<-----

 4026 12:40:41.471047  

 4027 12:40:41.471113  ==

 4028 12:40:41.474318  Dram Type= 6, Freq= 0, CH_0, rank 0

 4029 12:40:41.477470  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4030 12:40:41.477554  ==

 4031 12:40:41.480934  [Gating] SW mode calibration

 4032 12:40:41.487466  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4033 12:40:41.494194  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4034 12:40:41.497425   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4035 12:40:41.500745   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4036 12:40:41.503939   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4037 12:40:41.510780   0  9 12 | B1->B0 | 3434 2d2d | 1 1 | (0 0) (0 0)

 4038 12:40:41.513881   0  9 16 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)

 4039 12:40:41.517066   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4040 12:40:41.523748   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4041 12:40:41.527101   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4042 12:40:41.530460   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4043 12:40:41.536884   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4044 12:40:41.540303   0 10  8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 4045 12:40:41.543631   0 10 12 | B1->B0 | 2626 3838 | 0 0 | (0 0) (0 0)

 4046 12:40:41.550477   0 10 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)

 4047 12:40:41.553683   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4048 12:40:41.556702   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4049 12:40:41.563757   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4050 12:40:41.566711   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4051 12:40:41.570063   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4052 12:40:41.576721   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4053 12:40:41.579985   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 4054 12:40:41.583307   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 4055 12:40:41.590089   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4056 12:40:41.593250   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4057 12:40:41.596561   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4058 12:40:41.603240   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4059 12:40:41.606456   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4060 12:40:41.609868   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4061 12:40:41.616590   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4062 12:40:41.619696   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4063 12:40:41.623169   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4064 12:40:41.629714   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4065 12:40:41.632935   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4066 12:40:41.636390   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4067 12:40:41.643139   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4068 12:40:41.646409   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 4069 12:40:41.649630   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 4070 12:40:41.656239   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4071 12:40:41.656326  Total UI for P1: 0, mck2ui 16

 4072 12:40:41.662995  best dqsien dly found for B0: ( 0, 13, 10)

 4073 12:40:41.666355   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4074 12:40:41.669621  Total UI for P1: 0, mck2ui 16

 4075 12:40:41.673169  best dqsien dly found for B1: ( 0, 13, 16)

 4076 12:40:41.676543  best DQS0 dly(MCK, UI, PI) = (0, 13, 10)

 4077 12:40:41.679748  best DQS1 dly(MCK, UI, PI) = (0, 13, 16)

 4078 12:40:41.679834  

 4079 12:40:41.683152  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4080 12:40:41.686074  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)

 4081 12:40:41.689459  [Gating] SW calibration Done

 4082 12:40:41.689544  ==

 4083 12:40:41.692821  Dram Type= 6, Freq= 0, CH_0, rank 0

 4084 12:40:41.696139  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4085 12:40:41.699518  ==

 4086 12:40:41.699648  RX Vref Scan: 0

 4087 12:40:41.699744  

 4088 12:40:41.702874  RX Vref 0 -> 0, step: 1

 4089 12:40:41.702962  

 4090 12:40:41.706234  RX Delay -230 -> 252, step: 16

 4091 12:40:41.709302  iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320

 4092 12:40:41.712530  iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320

 4093 12:40:41.715547  iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320

 4094 12:40:41.722485  iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304

 4095 12:40:41.725625  iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320

 4096 12:40:41.729195  iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320

 4097 12:40:41.732568  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4098 12:40:41.736015  iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320

 4099 12:40:41.742511  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4100 12:40:41.746320  iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320

 4101 12:40:41.749161  iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320

 4102 12:40:41.752474  iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304

 4103 12:40:41.759134  iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320

 4104 12:40:41.762411  iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304

 4105 12:40:41.766063  iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320

 4106 12:40:41.768929  iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304

 4107 12:40:41.769019  ==

 4108 12:40:41.772320  Dram Type= 6, Freq= 0, CH_0, rank 0

 4109 12:40:41.778973  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4110 12:40:41.779059  ==

 4111 12:40:41.779126  DQS Delay:

 4112 12:40:41.782677  DQS0 = 0, DQS1 = 0

 4113 12:40:41.782762  DQM Delay:

 4114 12:40:41.782829  DQM0 = 50, DQM1 = 41

 4115 12:40:41.785795  DQ Delay:

 4116 12:40:41.789604  DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =49

 4117 12:40:41.792482  DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57

 4118 12:40:41.795918  DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33

 4119 12:40:41.799020  DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49

 4120 12:40:41.799131  

 4121 12:40:41.799222  

 4122 12:40:41.799289  ==

 4123 12:40:41.802827  Dram Type= 6, Freq= 0, CH_0, rank 0

 4124 12:40:41.806146  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4125 12:40:41.806246  ==

 4126 12:40:41.806313  

 4127 12:40:41.806375  

 4128 12:40:41.808981  	TX Vref Scan disable

 4129 12:40:41.809092   == TX Byte 0 ==

 4130 12:40:41.815662  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4131 12:40:41.819136  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4132 12:40:41.819221   == TX Byte 1 ==

 4133 12:40:41.825677  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4134 12:40:41.828878  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4135 12:40:41.828996  ==

 4136 12:40:41.832568  Dram Type= 6, Freq= 0, CH_0, rank 0

 4137 12:40:41.835687  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4138 12:40:41.835765  ==

 4139 12:40:41.835831  

 4140 12:40:41.839166  

 4141 12:40:41.839252  	TX Vref Scan disable

 4142 12:40:41.842510   == TX Byte 0 ==

 4143 12:40:41.845606  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4144 12:40:41.848979  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4145 12:40:41.852453   == TX Byte 1 ==

 4146 12:40:41.855612  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4147 12:40:41.859072  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4148 12:40:41.862614  

 4149 12:40:41.862700  [DATLAT]

 4150 12:40:41.862785  Freq=600, CH0 RK0

 4151 12:40:41.862866  

 4152 12:40:41.865729  DATLAT Default: 0x9

 4153 12:40:41.865815  0, 0xFFFF, sum = 0

 4154 12:40:41.868961  1, 0xFFFF, sum = 0

 4155 12:40:41.869084  2, 0xFFFF, sum = 0

 4156 12:40:41.872617  3, 0xFFFF, sum = 0

 4157 12:40:41.872725  4, 0xFFFF, sum = 0

 4158 12:40:41.875770  5, 0xFFFF, sum = 0

 4159 12:40:41.879095  6, 0xFFFF, sum = 0

 4160 12:40:41.879203  7, 0xFFFF, sum = 0

 4161 12:40:41.879298  8, 0x0, sum = 1

 4162 12:40:41.882580  9, 0x0, sum = 2

 4163 12:40:41.882691  10, 0x0, sum = 3

 4164 12:40:41.885571  11, 0x0, sum = 4

 4165 12:40:41.885677  best_step = 9

 4166 12:40:41.885769  

 4167 12:40:41.885858  ==

 4168 12:40:41.889082  Dram Type= 6, Freq= 0, CH_0, rank 0

 4169 12:40:41.895732  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4170 12:40:41.895841  ==

 4171 12:40:41.895932  RX Vref Scan: 1

 4172 12:40:41.896023  

 4173 12:40:41.899185  RX Vref 0 -> 0, step: 1

 4174 12:40:41.899290  

 4175 12:40:41.902156  RX Delay -179 -> 252, step: 8

 4176 12:40:41.902262  

 4177 12:40:41.905435  Set Vref, RX VrefLevel [Byte0]: 59

 4178 12:40:41.908836                           [Byte1]: 50

 4179 12:40:41.908944  

 4180 12:40:41.912185  Final RX Vref Byte 0 = 59 to rank0

 4181 12:40:41.915710  Final RX Vref Byte 1 = 50 to rank0

 4182 12:40:41.918754  Final RX Vref Byte 0 = 59 to rank1

 4183 12:40:41.921977  Final RX Vref Byte 1 = 50 to rank1==

 4184 12:40:41.925401  Dram Type= 6, Freq= 0, CH_0, rank 0

 4185 12:40:41.928861  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4186 12:40:41.928970  ==

 4187 12:40:41.932388  DQS Delay:

 4188 12:40:41.932499  DQS0 = 0, DQS1 = 0

 4189 12:40:41.932594  DQM Delay:

 4190 12:40:41.935577  DQM0 = 49, DQM1 = 40

 4191 12:40:41.935687  DQ Delay:

 4192 12:40:41.938719  DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44

 4193 12:40:41.942304  DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56

 4194 12:40:41.945574  DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =32

 4195 12:40:41.948904  DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48

 4196 12:40:41.949011  

 4197 12:40:41.949103  

 4198 12:40:41.958766  [DQSOSCAuto] RK0, (LSB)MR18= 0x5b55, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps

 4199 12:40:41.958879  CH0 RK0: MR19=808, MR18=5B55

 4200 12:40:41.965443  CH0_RK0: MR19=0x808, MR18=0x5B55, DQSOSC=392, MR23=63, INC=170, DEC=113

 4201 12:40:41.965551  

 4202 12:40:41.968932  ----->DramcWriteLeveling(PI) begin...

 4203 12:40:41.971844  ==

 4204 12:40:41.975257  Dram Type= 6, Freq= 0, CH_0, rank 1

 4205 12:40:41.978923  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4206 12:40:41.979042  ==

 4207 12:40:41.981887  Write leveling (Byte 0): 32 => 32

 4208 12:40:41.985401  Write leveling (Byte 1): 30 => 30

 4209 12:40:41.988720  DramcWriteLeveling(PI) end<-----

 4210 12:40:41.988830  

 4211 12:40:41.988921  ==

 4212 12:40:41.992246  Dram Type= 6, Freq= 0, CH_0, rank 1

 4213 12:40:41.995468  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4214 12:40:41.995581  ==

 4215 12:40:41.998919  [Gating] SW mode calibration

 4216 12:40:42.005312  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4217 12:40:42.008911  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4218 12:40:42.015478   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4219 12:40:42.018641   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4220 12:40:42.021899   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4221 12:40:42.028606   0  9 12 | B1->B0 | 3232 2f2f | 1 1 | (1 1) (1 1)

 4222 12:40:42.031998   0  9 16 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)

 4223 12:40:42.035361   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4224 12:40:42.041673   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4225 12:40:42.044890   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4226 12:40:42.048289   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4227 12:40:42.055276   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4228 12:40:42.058418   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4229 12:40:42.061515   0 10 12 | B1->B0 | 2d2d 3434 | 0 0 | (0 0) (0 0)

 4230 12:40:42.068514   0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)

 4231 12:40:42.071944   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4232 12:40:42.074743   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4233 12:40:42.081796   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4234 12:40:42.085184   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4235 12:40:42.088174   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4236 12:40:42.094658   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4237 12:40:42.098352   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4238 12:40:42.101337   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 4239 12:40:42.108136   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4240 12:40:42.111517   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4241 12:40:42.114616   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4242 12:40:42.121382   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4243 12:40:42.124899   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4244 12:40:42.128107   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4245 12:40:42.134478   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4246 12:40:42.137944   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4247 12:40:42.141651   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4248 12:40:42.147914   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4249 12:40:42.151312   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4250 12:40:42.154908   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4251 12:40:42.157852   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4252 12:40:42.164913   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 4253 12:40:42.168151   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 4254 12:40:42.171268   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4255 12:40:42.174947  Total UI for P1: 0, mck2ui 16

 4256 12:40:42.177692  best dqsien dly found for B0: ( 0, 13, 12)

 4257 12:40:42.181183  Total UI for P1: 0, mck2ui 16

 4258 12:40:42.184795  best dqsien dly found for B1: ( 0, 13, 10)

 4259 12:40:42.191021  best DQS0 dly(MCK, UI, PI) = (0, 13, 12)

 4260 12:40:42.194360  best DQS1 dly(MCK, UI, PI) = (0, 13, 10)

 4261 12:40:42.194445  

 4262 12:40:42.197504  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4263 12:40:42.200994  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4264 12:40:42.204053  [Gating] SW calibration Done

 4265 12:40:42.204137  ==

 4266 12:40:42.207733  Dram Type= 6, Freq= 0, CH_0, rank 1

 4267 12:40:42.210504  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4268 12:40:42.210589  ==

 4269 12:40:42.214114  RX Vref Scan: 0

 4270 12:40:42.214198  

 4271 12:40:42.214263  RX Vref 0 -> 0, step: 1

 4272 12:40:42.214324  

 4273 12:40:42.217257  RX Delay -230 -> 252, step: 16

 4274 12:40:42.220663  iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320

 4275 12:40:42.227388  iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304

 4276 12:40:42.230584  iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320

 4277 12:40:42.234072  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4278 12:40:42.237229  iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304

 4279 12:40:42.243737  iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320

 4280 12:40:42.247130  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4281 12:40:42.250699  iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320

 4282 12:40:42.254124  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4283 12:40:42.257591  iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320

 4284 12:40:42.264016  iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320

 4285 12:40:42.267013  iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320

 4286 12:40:42.270633  iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320

 4287 12:40:42.273928  iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304

 4288 12:40:42.280466  iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320

 4289 12:40:42.283862  iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304

 4290 12:40:42.283947  ==

 4291 12:40:42.287118  Dram Type= 6, Freq= 0, CH_0, rank 1

 4292 12:40:42.290473  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4293 12:40:42.290558  ==

 4294 12:40:42.293639  DQS Delay:

 4295 12:40:42.293723  DQS0 = 0, DQS1 = 0

 4296 12:40:42.293791  DQM Delay:

 4297 12:40:42.297132  DQM0 = 47, DQM1 = 42

 4298 12:40:42.297217  DQ Delay:

 4299 12:40:42.300695  DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41

 4300 12:40:42.303801  DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57

 4301 12:40:42.307100  DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41

 4302 12:40:42.310412  DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49

 4303 12:40:42.310497  

 4304 12:40:42.310563  

 4305 12:40:42.310623  ==

 4306 12:40:42.313676  Dram Type= 6, Freq= 0, CH_0, rank 1

 4307 12:40:42.320389  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4308 12:40:42.320475  ==

 4309 12:40:42.320541  

 4310 12:40:42.320602  

 4311 12:40:42.320661  	TX Vref Scan disable

 4312 12:40:42.324233   == TX Byte 0 ==

 4313 12:40:42.327383  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 4314 12:40:42.330663  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 4315 12:40:42.334165   == TX Byte 1 ==

 4316 12:40:42.337344  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4317 12:40:42.340849  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4318 12:40:42.344303  ==

 4319 12:40:42.347311  Dram Type= 6, Freq= 0, CH_0, rank 1

 4320 12:40:42.350940  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4321 12:40:42.351026  ==

 4322 12:40:42.351092  

 4323 12:40:42.351152  

 4324 12:40:42.353988  	TX Vref Scan disable

 4325 12:40:42.354072   == TX Byte 0 ==

 4326 12:40:42.360682  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 4327 12:40:42.363718  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 4328 12:40:42.367480   == TX Byte 1 ==

 4329 12:40:42.370385  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4330 12:40:42.374212  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4331 12:40:42.374298  

 4332 12:40:42.374364  [DATLAT]

 4333 12:40:42.377219  Freq=600, CH0 RK1

 4334 12:40:42.377304  

 4335 12:40:42.377369  DATLAT Default: 0x9

 4336 12:40:42.380482  0, 0xFFFF, sum = 0

 4337 12:40:42.384117  1, 0xFFFF, sum = 0

 4338 12:40:42.384203  2, 0xFFFF, sum = 0

 4339 12:40:42.387617  3, 0xFFFF, sum = 0

 4340 12:40:42.387703  4, 0xFFFF, sum = 0

 4341 12:40:42.390557  5, 0xFFFF, sum = 0

 4342 12:40:42.390644  6, 0xFFFF, sum = 0

 4343 12:40:42.393823  7, 0xFFFF, sum = 0

 4344 12:40:42.393909  8, 0x0, sum = 1

 4345 12:40:42.393985  9, 0x0, sum = 2

 4346 12:40:42.397602  10, 0x0, sum = 3

 4347 12:40:42.397685  11, 0x0, sum = 4

 4348 12:40:42.400411  best_step = 9

 4349 12:40:42.400494  

 4350 12:40:42.400558  ==

 4351 12:40:42.403771  Dram Type= 6, Freq= 0, CH_0, rank 1

 4352 12:40:42.407598  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4353 12:40:42.407681  ==

 4354 12:40:42.410703  RX Vref Scan: 0

 4355 12:40:42.410785  

 4356 12:40:42.410850  RX Vref 0 -> 0, step: 1

 4357 12:40:42.410910  

 4358 12:40:42.413786  RX Delay -179 -> 252, step: 8

 4359 12:40:42.421213  iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296

 4360 12:40:42.424300  iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296

 4361 12:40:42.427528  iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288

 4362 12:40:42.431382  iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288

 4363 12:40:42.434419  iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296

 4364 12:40:42.441261  iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296

 4365 12:40:42.444345  iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296

 4366 12:40:42.447601  iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296

 4367 12:40:42.451113  iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296

 4368 12:40:42.457466  iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288

 4369 12:40:42.460939  iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296

 4370 12:40:42.464219  iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296

 4371 12:40:42.467456  iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296

 4372 12:40:42.470708  iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288

 4373 12:40:42.477544  iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296

 4374 12:40:42.480782  iDelay=205, Bit 15, Center 48 (-99 ~ 196) 296

 4375 12:40:42.480866  ==

 4376 12:40:42.484170  Dram Type= 6, Freq= 0, CH_0, rank 1

 4377 12:40:42.487612  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4378 12:40:42.487696  ==

 4379 12:40:42.491001  DQS Delay:

 4380 12:40:42.491083  DQS0 = 0, DQS1 = 0

 4381 12:40:42.491149  DQM Delay:

 4382 12:40:42.494536  DQM0 = 48, DQM1 = 40

 4383 12:40:42.494619  DQ Delay:

 4384 12:40:42.497474  DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44

 4385 12:40:42.500822  DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56

 4386 12:40:42.504297  DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32

 4387 12:40:42.507461  DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48

 4388 12:40:42.507544  

 4389 12:40:42.507609  

 4390 12:40:42.517769  [DQSOSCAuto] RK1, (LSB)MR18= 0x6532, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps

 4391 12:40:42.517853  CH0 RK1: MR19=808, MR18=6532

 4392 12:40:42.524132  CH0_RK1: MR19=0x808, MR18=0x6532, DQSOSC=390, MR23=63, INC=172, DEC=114

 4393 12:40:42.527481  [RxdqsGatingPostProcess] freq 600

 4394 12:40:42.534097  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4395 12:40:42.537292  Pre-setting of DQS Precalculation

 4396 12:40:42.540663  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4397 12:40:42.540747  ==

 4398 12:40:42.543964  Dram Type= 6, Freq= 0, CH_1, rank 0

 4399 12:40:42.551040  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4400 12:40:42.551123  ==

 4401 12:40:42.554010  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4402 12:40:42.560695  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33

 4403 12:40:42.563809  [CA 0] Center 35 (5~66) winsize 62

 4404 12:40:42.567311  [CA 1] Center 35 (5~66) winsize 62

 4405 12:40:42.570673  [CA 2] Center 34 (4~65) winsize 62

 4406 12:40:42.573903  [CA 3] Center 34 (3~65) winsize 63

 4407 12:40:42.577232  [CA 4] Center 34 (4~65) winsize 62

 4408 12:40:42.580309  [CA 5] Center 33 (3~64) winsize 62

 4409 12:40:42.580411  

 4410 12:40:42.583458  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 4411 12:40:42.583539  

 4412 12:40:42.586956  [CATrainingPosCal] consider 1 rank data

 4413 12:40:42.590423  u2DelayCellTimex100 = 270/100 ps

 4414 12:40:42.593923  CA0 delay=35 (5~66),Diff = 2 PI (19 cell)

 4415 12:40:42.597236  CA1 delay=35 (5~66),Diff = 2 PI (19 cell)

 4416 12:40:42.603770  CA2 delay=34 (4~65),Diff = 1 PI (9 cell)

 4417 12:40:42.607088  CA3 delay=34 (3~65),Diff = 1 PI (9 cell)

 4418 12:40:42.610695  CA4 delay=34 (4~65),Diff = 1 PI (9 cell)

 4419 12:40:42.613582  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 4420 12:40:42.613663  

 4421 12:40:42.616677  CA PerBit enable=1, Macro0, CA PI delay=33

 4422 12:40:42.616759  

 4423 12:40:42.620326  [CBTSetCACLKResult] CA Dly = 33

 4424 12:40:42.620409  CS Dly: 4 (0~35)

 4425 12:40:42.623316  ==

 4426 12:40:42.623398  Dram Type= 6, Freq= 0, CH_1, rank 1

 4427 12:40:42.629874  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4428 12:40:42.629964  ==

 4429 12:40:42.633353  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4430 12:40:42.639929  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 4431 12:40:42.643953  [CA 0] Center 35 (5~66) winsize 62

 4432 12:40:42.647357  [CA 1] Center 35 (5~66) winsize 62

 4433 12:40:42.650487  [CA 2] Center 34 (4~65) winsize 62

 4434 12:40:42.653564  [CA 3] Center 34 (4~65) winsize 62

 4435 12:40:42.657486  [CA 4] Center 34 (4~65) winsize 62

 4436 12:40:42.660847  [CA 5] Center 34 (4~65) winsize 62

 4437 12:40:42.660929  

 4438 12:40:42.663780  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 4439 12:40:42.663862  

 4440 12:40:42.667289  [CATrainingPosCal] consider 2 rank data

 4441 12:40:42.670472  u2DelayCellTimex100 = 270/100 ps

 4442 12:40:42.673803  CA0 delay=35 (5~66),Diff = 1 PI (9 cell)

 4443 12:40:42.677369  CA1 delay=35 (5~66),Diff = 1 PI (9 cell)

 4444 12:40:42.683985  CA2 delay=34 (4~65),Diff = 0 PI (0 cell)

 4445 12:40:42.686861  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 4446 12:40:42.690202  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 4447 12:40:42.693715  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 4448 12:40:42.693797  

 4449 12:40:42.697111  CA PerBit enable=1, Macro0, CA PI delay=34

 4450 12:40:42.697192  

 4451 12:40:42.700517  [CBTSetCACLKResult] CA Dly = 34

 4452 12:40:42.700599  CS Dly: 4 (0~36)

 4453 12:40:42.700663  

 4454 12:40:42.703570  ----->DramcWriteLeveling(PI) begin...

 4455 12:40:42.707043  ==

 4456 12:40:42.707125  Dram Type= 6, Freq= 0, CH_1, rank 0

 4457 12:40:42.714175  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4458 12:40:42.714262  ==

 4459 12:40:42.717189  Write leveling (Byte 0): 31 => 31

 4460 12:40:42.720598  Write leveling (Byte 1): 29 => 29

 4461 12:40:42.723560  DramcWriteLeveling(PI) end<-----

 4462 12:40:42.723642  

 4463 12:40:42.723706  ==

 4464 12:40:42.727052  Dram Type= 6, Freq= 0, CH_1, rank 0

 4465 12:40:42.730336  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4466 12:40:42.730421  ==

 4467 12:40:42.733746  [Gating] SW mode calibration

 4468 12:40:42.740069  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4469 12:40:42.743555  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4470 12:40:42.750139   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4471 12:40:42.753372   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4472 12:40:42.757077   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)

 4473 12:40:42.763297   0  9 12 | B1->B0 | 2d2d 2626 | 0 0 | (1 1) (1 1)

 4474 12:40:42.766882   0  9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4475 12:40:42.770221   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4476 12:40:42.776912   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4477 12:40:42.780324   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4478 12:40:42.783406   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4479 12:40:42.789881   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4480 12:40:42.793509   0 10  8 | B1->B0 | 2727 2525 | 0 0 | (0 0) (0 0)

 4481 12:40:42.797134   0 10 12 | B1->B0 | 3a3a 3c3c | 1 0 | (0 0) (0 0)

 4482 12:40:42.803363   0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4483 12:40:42.806644   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4484 12:40:42.810253   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4485 12:40:42.816665   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4486 12:40:42.819934   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4487 12:40:42.823547   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4488 12:40:42.830264   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 4489 12:40:42.833380   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 4490 12:40:42.836498   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4491 12:40:42.843154   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4492 12:40:42.846635   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4493 12:40:42.850012   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4494 12:40:42.856574   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4495 12:40:42.859713   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4496 12:40:42.863336   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4497 12:40:42.866591   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4498 12:40:42.873177   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4499 12:40:42.876349   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4500 12:40:42.879951   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4501 12:40:42.886285   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4502 12:40:42.889845   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4503 12:40:42.893360   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4504 12:40:42.900233   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 4505 12:40:42.903256   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 4506 12:40:42.906768   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4507 12:40:42.909810  Total UI for P1: 0, mck2ui 16

 4508 12:40:42.912853  best dqsien dly found for B0: ( 0, 13, 10)

 4509 12:40:42.916307  Total UI for P1: 0, mck2ui 16

 4510 12:40:42.919674  best dqsien dly found for B1: ( 0, 13, 12)

 4511 12:40:42.923292  best DQS0 dly(MCK, UI, PI) = (0, 13, 10)

 4512 12:40:42.926316  best DQS1 dly(MCK, UI, PI) = (0, 13, 12)

 4513 12:40:42.926399  

 4514 12:40:42.933172  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4515 12:40:42.936327  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4516 12:40:42.939619  [Gating] SW calibration Done

 4517 12:40:42.939703  ==

 4518 12:40:42.943158  Dram Type= 6, Freq= 0, CH_1, rank 0

 4519 12:40:42.946202  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4520 12:40:42.946286  ==

 4521 12:40:42.946351  RX Vref Scan: 0

 4522 12:40:42.946412  

 4523 12:40:42.949758  RX Vref 0 -> 0, step: 1

 4524 12:40:42.949841  

 4525 12:40:42.953323  RX Delay -230 -> 252, step: 16

 4526 12:40:42.956185  iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304

 4527 12:40:42.959754  iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304

 4528 12:40:42.966152  iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304

 4529 12:40:42.969790  iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304

 4530 12:40:42.972718  iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304

 4531 12:40:42.976573  iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288

 4532 12:40:42.982734  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4533 12:40:42.985942  iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304

 4534 12:40:42.989317  iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320

 4535 12:40:42.992737  iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320

 4536 12:40:42.996403  iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320

 4537 12:40:43.002994  iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304

 4538 12:40:43.006038  iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336

 4539 12:40:43.009841  iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336

 4540 12:40:43.012714  iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320

 4541 12:40:43.019316  iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320

 4542 12:40:43.019397  ==

 4543 12:40:43.022620  Dram Type= 6, Freq= 0, CH_1, rank 0

 4544 12:40:43.026122  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4545 12:40:43.026204  ==

 4546 12:40:43.026267  DQS Delay:

 4547 12:40:43.029580  DQS0 = 0, DQS1 = 0

 4548 12:40:43.029657  DQM Delay:

 4549 12:40:43.032464  DQM0 = 49, DQM1 = 38

 4550 12:40:43.032547  DQ Delay:

 4551 12:40:43.035899  DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49

 4552 12:40:43.039227  DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49

 4553 12:40:43.042473  DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33

 4554 12:40:43.045870  DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41

 4555 12:40:43.045962  

 4556 12:40:43.046030  

 4557 12:40:43.046091  ==

 4558 12:40:43.049323  Dram Type= 6, Freq= 0, CH_1, rank 0

 4559 12:40:43.052438  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4560 12:40:43.056118  ==

 4561 12:40:43.056203  

 4562 12:40:43.056267  

 4563 12:40:43.056328  	TX Vref Scan disable

 4564 12:40:43.059209   == TX Byte 0 ==

 4565 12:40:43.062514  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4566 12:40:43.065825  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4567 12:40:43.068864   == TX Byte 1 ==

 4568 12:40:43.072465  Update DQ  dly =573 (2 ,1, 29)  DQ  OEN =(1 ,6)

 4569 12:40:43.075698  Update DQM dly =573 (2 ,1, 29)  DQM OEN =(1 ,6)

 4570 12:40:43.078930  ==

 4571 12:40:43.079014  Dram Type= 6, Freq= 0, CH_1, rank 0

 4572 12:40:43.086066  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4573 12:40:43.086151  ==

 4574 12:40:43.086217  

 4575 12:40:43.086277  

 4576 12:40:43.089031  	TX Vref Scan disable

 4577 12:40:43.089115   == TX Byte 0 ==

 4578 12:40:43.095514  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4579 12:40:43.098965  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4580 12:40:43.099048   == TX Byte 1 ==

 4581 12:40:43.105565  Update DQ  dly =573 (2 ,1, 29)  DQ  OEN =(1 ,6)

 4582 12:40:43.109245  Update DQM dly =573 (2 ,1, 29)  DQM OEN =(1 ,6)

 4583 12:40:43.109331  

 4584 12:40:43.109396  [DATLAT]

 4585 12:40:43.112407  Freq=600, CH1 RK0

 4586 12:40:43.112492  

 4587 12:40:43.112558  DATLAT Default: 0x9

 4588 12:40:43.115763  0, 0xFFFF, sum = 0

 4589 12:40:43.115848  1, 0xFFFF, sum = 0

 4590 12:40:43.119218  2, 0xFFFF, sum = 0

 4591 12:40:43.119303  3, 0xFFFF, sum = 0

 4592 12:40:43.122455  4, 0xFFFF, sum = 0

 4593 12:40:43.122540  5, 0xFFFF, sum = 0

 4594 12:40:43.125664  6, 0xFFFF, sum = 0

 4595 12:40:43.129183  7, 0xFFFF, sum = 0

 4596 12:40:43.129268  8, 0x0, sum = 1

 4597 12:40:43.129335  9, 0x0, sum = 2

 4598 12:40:43.132657  10, 0x0, sum = 3

 4599 12:40:43.132742  11, 0x0, sum = 4

 4600 12:40:43.135389  best_step = 9

 4601 12:40:43.135472  

 4602 12:40:43.135538  ==

 4603 12:40:43.138955  Dram Type= 6, Freq= 0, CH_1, rank 0

 4604 12:40:43.141974  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4605 12:40:43.142073  ==

 4606 12:40:43.145487  RX Vref Scan: 1

 4607 12:40:43.145570  

 4608 12:40:43.145635  RX Vref 0 -> 0, step: 1

 4609 12:40:43.145694  

 4610 12:40:43.149036  RX Delay -179 -> 252, step: 8

 4611 12:40:43.149120  

 4612 12:40:43.152295  Set Vref, RX VrefLevel [Byte0]: 54

 4613 12:40:43.155235                           [Byte1]: 53

 4614 12:40:43.159339  

 4615 12:40:43.159422  Final RX Vref Byte 0 = 54 to rank0

 4616 12:40:43.162465  Final RX Vref Byte 1 = 53 to rank0

 4617 12:40:43.166375  Final RX Vref Byte 0 = 54 to rank1

 4618 12:40:43.169406  Final RX Vref Byte 1 = 53 to rank1==

 4619 12:40:43.172311  Dram Type= 6, Freq= 0, CH_1, rank 0

 4620 12:40:43.179200  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4621 12:40:43.179285  ==

 4622 12:40:43.179351  DQS Delay:

 4623 12:40:43.183041  DQS0 = 0, DQS1 = 0

 4624 12:40:43.183124  DQM Delay:

 4625 12:40:43.183190  DQM0 = 47, DQM1 = 40

 4626 12:40:43.185814  DQ Delay:

 4627 12:40:43.189241  DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44

 4628 12:40:43.192250  DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =44

 4629 12:40:43.195730  DQ8 =28, DQ9 =24, DQ10 =44, DQ11 =32

 4630 12:40:43.199465  DQ12 =52, DQ13 =48, DQ14 =44, DQ15 =48

 4631 12:40:43.199550  

 4632 12:40:43.199615  

 4633 12:40:43.206006  [DQSOSCAuto] RK0, (LSB)MR18= 0x5077, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps

 4634 12:40:43.208962  CH1 RK0: MR19=808, MR18=5077

 4635 12:40:43.215576  CH1_RK0: MR19=0x808, MR18=0x5077, DQSOSC=387, MR23=63, INC=175, DEC=116

 4636 12:40:43.215660  

 4637 12:40:43.219068  ----->DramcWriteLeveling(PI) begin...

 4638 12:40:43.219153  ==

 4639 12:40:43.222482  Dram Type= 6, Freq= 0, CH_1, rank 1

 4640 12:40:43.225496  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4641 12:40:43.225581  ==

 4642 12:40:43.229128  Write leveling (Byte 0): 29 => 29

 4643 12:40:43.232184  Write leveling (Byte 1): 30 => 30

 4644 12:40:43.235954  DramcWriteLeveling(PI) end<-----

 4645 12:40:43.236038  

 4646 12:40:43.236103  ==

 4647 12:40:43.238908  Dram Type= 6, Freq= 0, CH_1, rank 1

 4648 12:40:43.242393  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4649 12:40:43.242478  ==

 4650 12:40:43.245597  [Gating] SW mode calibration

 4651 12:40:43.252621  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4652 12:40:43.258957  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4653 12:40:43.262148   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4654 12:40:43.265449   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4655 12:40:43.272225   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4656 12:40:43.275720   0  9 12 | B1->B0 | 2929 3131 | 0 1 | (0 1) (1 0)

 4657 12:40:43.279488   0  9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4658 12:40:43.285913   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4659 12:40:43.288954   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4660 12:40:43.292503   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4661 12:40:43.299214   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4662 12:40:43.302043   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4663 12:40:43.305557   0 10  8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)

 4664 12:40:43.312371   0 10 12 | B1->B0 | 4141 2e2e | 0 0 | (1 1) (0 0)

 4665 12:40:43.315507   0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4666 12:40:43.318934   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4667 12:40:43.325502   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4668 12:40:43.328820   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4669 12:40:43.332065   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4670 12:40:43.339041   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4671 12:40:43.342195   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 4672 12:40:43.345689   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 4673 12:40:43.352097   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4674 12:40:43.355431   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4675 12:40:43.358843   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4676 12:40:43.365277   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4677 12:40:43.368687   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4678 12:40:43.372128   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4679 12:40:43.378735   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4680 12:40:43.382112   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4681 12:40:43.385106   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4682 12:40:43.391974   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4683 12:40:43.394977   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4684 12:40:43.398700   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4685 12:40:43.402234   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4686 12:40:43.408532   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4687 12:40:43.412205   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4688 12:40:43.414960   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4689 12:40:43.418358  Total UI for P1: 0, mck2ui 16

 4690 12:40:43.422069  best dqsien dly found for B0: ( 0, 13, 10)

 4691 12:40:43.428640   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4692 12:40:43.431529  Total UI for P1: 0, mck2ui 16

 4693 12:40:43.434881  best dqsien dly found for B1: ( 0, 13, 12)

 4694 12:40:43.438627  best DQS0 dly(MCK, UI, PI) = (0, 13, 10)

 4695 12:40:43.441771  best DQS1 dly(MCK, UI, PI) = (0, 13, 12)

 4696 12:40:43.441855  

 4697 12:40:43.445200  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4698 12:40:43.448400  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4699 12:40:43.451536  [Gating] SW calibration Done

 4700 12:40:43.451620  ==

 4701 12:40:43.455451  Dram Type= 6, Freq= 0, CH_1, rank 1

 4702 12:40:43.458611  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4703 12:40:43.458696  ==

 4704 12:40:43.461439  RX Vref Scan: 0

 4705 12:40:43.461522  

 4706 12:40:43.465376  RX Vref 0 -> 0, step: 1

 4707 12:40:43.465460  

 4708 12:40:43.465526  RX Delay -230 -> 252, step: 16

 4709 12:40:43.471556  iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288

 4710 12:40:43.474945  iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304

 4711 12:40:43.478105  iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304

 4712 12:40:43.481462  iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304

 4713 12:40:43.484877  iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288

 4714 12:40:43.491309  iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304

 4715 12:40:43.495194  iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304

 4716 12:40:43.498325  iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304

 4717 12:40:43.501740  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4718 12:40:43.504921  iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304

 4719 12:40:43.511659  iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320

 4720 12:40:43.514995  iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320

 4721 12:40:43.518304  iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320

 4722 12:40:43.521571  iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304

 4723 12:40:43.528185  iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320

 4724 12:40:43.531539  iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304

 4725 12:40:43.531623  ==

 4726 12:40:43.535416  Dram Type= 6, Freq= 0, CH_1, rank 1

 4727 12:40:43.538318  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4728 12:40:43.538403  ==

 4729 12:40:43.541534  DQS Delay:

 4730 12:40:43.541618  DQS0 = 0, DQS1 = 0

 4731 12:40:43.541683  DQM Delay:

 4732 12:40:43.544969  DQM0 = 53, DQM1 = 45

 4733 12:40:43.545053  DQ Delay:

 4734 12:40:43.548163  DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49

 4735 12:40:43.551718  DQ4 =57, DQ5 =65, DQ6 =65, DQ7 =49

 4736 12:40:43.554986  DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41

 4737 12:40:43.558132  DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =65

 4738 12:40:43.558217  

 4739 12:40:43.558282  

 4740 12:40:43.558344  ==

 4741 12:40:43.561556  Dram Type= 6, Freq= 0, CH_1, rank 1

 4742 12:40:43.568299  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4743 12:40:43.568384  ==

 4744 12:40:43.568448  

 4745 12:40:43.568511  

 4746 12:40:43.568568  	TX Vref Scan disable

 4747 12:40:43.571617   == TX Byte 0 ==

 4748 12:40:43.575346  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4749 12:40:43.578499  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4750 12:40:43.582154   == TX Byte 1 ==

 4751 12:40:43.585164  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4752 12:40:43.588511  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4753 12:40:43.591840  ==

 4754 12:40:43.595478  Dram Type= 6, Freq= 0, CH_1, rank 1

 4755 12:40:43.598617  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4756 12:40:43.598702  ==

 4757 12:40:43.598768  

 4758 12:40:43.598828  

 4759 12:40:43.601654  	TX Vref Scan disable

 4760 12:40:43.601737   == TX Byte 0 ==

 4761 12:40:43.608368  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4762 12:40:43.611923  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4763 12:40:43.612008   == TX Byte 1 ==

 4764 12:40:43.618360  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4765 12:40:43.622039  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4766 12:40:43.622123  

 4767 12:40:43.622189  [DATLAT]

 4768 12:40:43.624859  Freq=600, CH1 RK1

 4769 12:40:43.624943  

 4770 12:40:43.625008  DATLAT Default: 0x9

 4771 12:40:43.628153  0, 0xFFFF, sum = 0

 4772 12:40:43.628238  1, 0xFFFF, sum = 0

 4773 12:40:43.631625  2, 0xFFFF, sum = 0

 4774 12:40:43.631709  3, 0xFFFF, sum = 0

 4775 12:40:43.635079  4, 0xFFFF, sum = 0

 4776 12:40:43.638518  5, 0xFFFF, sum = 0

 4777 12:40:43.638619  6, 0xFFFF, sum = 0

 4778 12:40:43.641655  7, 0xFFFF, sum = 0

 4779 12:40:43.641740  8, 0x0, sum = 1

 4780 12:40:43.641805  9, 0x0, sum = 2

 4781 12:40:43.644900  10, 0x0, sum = 3

 4782 12:40:43.645025  11, 0x0, sum = 4

 4783 12:40:43.648309  best_step = 9

 4784 12:40:43.648392  

 4785 12:40:43.648457  ==

 4786 12:40:43.651328  Dram Type= 6, Freq= 0, CH_1, rank 1

 4787 12:40:43.655370  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4788 12:40:43.655454  ==

 4789 12:40:43.657965  RX Vref Scan: 0

 4790 12:40:43.658063  

 4791 12:40:43.658129  RX Vref 0 -> 0, step: 1

 4792 12:40:43.658191  

 4793 12:40:43.661259  RX Delay -163 -> 252, step: 8

 4794 12:40:43.668596  iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280

 4795 12:40:43.672028  iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280

 4796 12:40:43.675336  iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288

 4797 12:40:43.678701  iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288

 4798 12:40:43.685481  iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288

 4799 12:40:43.688669  iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288

 4800 12:40:43.692067  iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280

 4801 12:40:43.695420  iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288

 4802 12:40:43.698395  iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296

 4803 12:40:43.705083  iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296

 4804 12:40:43.708505  iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296

 4805 12:40:43.711955  iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296

 4806 12:40:43.715971  iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296

 4807 12:40:43.718413  iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296

 4808 12:40:43.725229  iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296

 4809 12:40:43.728345  iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304

 4810 12:40:43.728428  ==

 4811 12:40:43.731688  Dram Type= 6, Freq= 0, CH_1, rank 1

 4812 12:40:43.735047  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4813 12:40:43.735132  ==

 4814 12:40:43.738670  DQS Delay:

 4815 12:40:43.738764  DQS0 = 0, DQS1 = 0

 4816 12:40:43.738830  DQM Delay:

 4817 12:40:43.741890  DQM0 = 48, DQM1 = 42

 4818 12:40:43.742023  DQ Delay:

 4819 12:40:43.744905  DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =44

 4820 12:40:43.748254  DQ4 =52, DQ5 =60, DQ6 =56, DQ7 =44

 4821 12:40:43.751830  DQ8 =32, DQ9 =32, DQ10 =40, DQ11 =40

 4822 12:40:43.755192  DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =52

 4823 12:40:43.755276  

 4824 12:40:43.755341  

 4825 12:40:43.765580  [DQSOSCAuto] RK1, (LSB)MR18= 0x5d22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps

 4826 12:40:43.768236  CH1 RK1: MR19=808, MR18=5D22

 4827 12:40:43.771597  CH1_RK1: MR19=0x808, MR18=0x5D22, DQSOSC=392, MR23=63, INC=170, DEC=113

 4828 12:40:43.774997  [RxdqsGatingPostProcess] freq 600

 4829 12:40:43.781371  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4830 12:40:43.784653  Pre-setting of DQS Precalculation

 4831 12:40:43.787969  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4832 12:40:43.797854  sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5

 4833 12:40:43.804566  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 4834 12:40:43.804653  

 4835 12:40:43.804719  

 4836 12:40:43.807856  [Calibration Summary] 1200 Mbps

 4837 12:40:43.807941  CH 0, Rank 0

 4838 12:40:43.811392  SW Impedance     : PASS

 4839 12:40:43.811484  DUTY Scan        : NO K

 4840 12:40:43.814467  ZQ Calibration   : PASS

 4841 12:40:43.817831  Jitter Meter     : NO K

 4842 12:40:43.817914  CBT Training     : PASS

 4843 12:40:43.821147  Write leveling   : PASS

 4844 12:40:43.824570  RX DQS gating    : PASS

 4845 12:40:43.824654  RX DQ/DQS(RDDQC) : PASS

 4846 12:40:43.828002  TX DQ/DQS        : PASS

 4847 12:40:43.828087  RX DATLAT        : PASS

 4848 12:40:43.831236  RX DQ/DQS(Engine): PASS

 4849 12:40:43.834556  TX OE            : NO K

 4850 12:40:43.834640  All Pass.

 4851 12:40:43.834705  

 4852 12:40:43.834765  CH 0, Rank 1

 4853 12:40:43.837851  SW Impedance     : PASS

 4854 12:40:43.841192  DUTY Scan        : NO K

 4855 12:40:43.841289  ZQ Calibration   : PASS

 4856 12:40:43.844676  Jitter Meter     : NO K

 4857 12:40:43.848085  CBT Training     : PASS

 4858 12:40:43.848169  Write leveling   : PASS

 4859 12:40:43.851211  RX DQS gating    : PASS

 4860 12:40:43.854422  RX DQ/DQS(RDDQC) : PASS

 4861 12:40:43.854505  TX DQ/DQS        : PASS

 4862 12:40:43.858091  RX DATLAT        : PASS

 4863 12:40:43.861691  RX DQ/DQS(Engine): PASS

 4864 12:40:43.861774  TX OE            : NO K

 4865 12:40:43.864417  All Pass.

 4866 12:40:43.864501  

 4867 12:40:43.864567  CH 1, Rank 0

 4868 12:40:43.867855  SW Impedance     : PASS

 4869 12:40:43.867939  DUTY Scan        : NO K

 4870 12:40:43.870947  ZQ Calibration   : PASS

 4871 12:40:43.874655  Jitter Meter     : NO K

 4872 12:40:43.874738  CBT Training     : PASS

 4873 12:40:43.877547  Write leveling   : PASS

 4874 12:40:43.881073  RX DQS gating    : PASS

 4875 12:40:43.881156  RX DQ/DQS(RDDQC) : PASS

 4876 12:40:43.884452  TX DQ/DQS        : PASS

 4877 12:40:43.884536  RX DATLAT        : PASS

 4878 12:40:43.887766  RX DQ/DQS(Engine): PASS

 4879 12:40:43.891261  TX OE            : NO K

 4880 12:40:43.891344  All Pass.

 4881 12:40:43.891410  

 4882 12:40:43.891471  CH 1, Rank 1

 4883 12:40:43.894007  SW Impedance     : PASS

 4884 12:40:43.897402  DUTY Scan        : NO K

 4885 12:40:43.897485  ZQ Calibration   : PASS

 4886 12:40:43.900685  Jitter Meter     : NO K

 4887 12:40:43.904331  CBT Training     : PASS

 4888 12:40:43.904414  Write leveling   : PASS

 4889 12:40:43.907270  RX DQS gating    : PASS

 4890 12:40:43.911235  RX DQ/DQS(RDDQC) : PASS

 4891 12:40:43.911318  TX DQ/DQS        : PASS

 4892 12:40:43.914303  RX DATLAT        : PASS

 4893 12:40:43.917555  RX DQ/DQS(Engine): PASS

 4894 12:40:43.917639  TX OE            : NO K

 4895 12:40:43.920936  All Pass.

 4896 12:40:43.921020  

 4897 12:40:43.921085  DramC Write-DBI off

 4898 12:40:43.924570  	PER_BANK_REFRESH: Hybrid Mode

 4899 12:40:43.924654  TX_TRACKING: ON

 4900 12:40:43.933897  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1

 4901 12:40:43.937237  [FAST_K] Save calibration result to emmc

 4902 12:40:43.940818  dramc_set_vcore_voltage set vcore to 662500

 4903 12:40:43.943995  Read voltage for 933, 3

 4904 12:40:43.944079  Vio18 = 0

 4905 12:40:43.947586  Vcore = 662500

 4906 12:40:43.947669  Vdram = 0

 4907 12:40:43.947734  Vddq = 0

 4908 12:40:43.947794  Vmddr = 0

 4909 12:40:43.953912  [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0

 4910 12:40:43.960918  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 4911 12:40:43.961006  MEM_TYPE=3, freq_sel=17

 4912 12:40:43.963857  sv_algorithm_assistance_LP4_1600 

 4913 12:40:43.967404  ============ PULL DRAM RESETB DOWN ============

 4914 12:40:43.974234  ========== PULL DRAM RESETB DOWN end =========

 4915 12:40:43.977516  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 4916 12:40:43.980577  =================================== 

 4917 12:40:43.984056  LPDDR4 DRAM CONFIGURATION

 4918 12:40:43.987432  =================================== 

 4919 12:40:43.987520  EX_ROW_EN[0]    = 0x0

 4920 12:40:43.990861  EX_ROW_EN[1]    = 0x0

 4921 12:40:43.990946  LP4Y_EN      = 0x0

 4922 12:40:43.994062  WORK_FSP     = 0x0

 4923 12:40:43.994146  WL           = 0x3

 4924 12:40:43.997237  RL           = 0x3

 4925 12:40:44.000846  BL           = 0x2

 4926 12:40:44.000930  RPST         = 0x0

 4927 12:40:44.004479  RD_PRE       = 0x0

 4928 12:40:44.004591  WR_PRE       = 0x1

 4929 12:40:44.007222  WR_PST       = 0x0

 4930 12:40:44.007306  DBI_WR       = 0x0

 4931 12:40:44.010649  DBI_RD       = 0x0

 4932 12:40:44.010732  OTF          = 0x1

 4933 12:40:44.013931  =================================== 

 4934 12:40:44.017232  =================================== 

 4935 12:40:44.020981  ANA top config

 4936 12:40:44.023878  =================================== 

 4937 12:40:44.023963  DLL_ASYNC_EN            =  0

 4938 12:40:44.027292  ALL_SLAVE_EN            =  1

 4939 12:40:44.030670  NEW_RANK_MODE           =  1

 4940 12:40:44.033656  DLL_IDLE_MODE           =  1

 4941 12:40:44.033740  LP45_APHY_COMB_EN       =  1

 4942 12:40:44.037135  TX_ODT_DIS              =  1

 4943 12:40:44.040446  NEW_8X_MODE             =  1

 4944 12:40:44.044077  =================================== 

 4945 12:40:44.047000  =================================== 

 4946 12:40:44.050383  data_rate                  = 1866

 4947 12:40:44.053666  CKR                        = 1

 4948 12:40:44.057012  DQ_P2S_RATIO               = 8

 4949 12:40:44.060603  =================================== 

 4950 12:40:44.060688  CA_P2S_RATIO               = 8

 4951 12:40:44.063850  DQ_CA_OPEN                 = 0

 4952 12:40:44.066878  DQ_SEMI_OPEN               = 0

 4953 12:40:44.070210  CA_SEMI_OPEN               = 0

 4954 12:40:44.073633  CA_FULL_RATE               = 0

 4955 12:40:44.076930  DQ_CKDIV4_EN               = 1

 4956 12:40:44.077015  CA_CKDIV4_EN               = 1

 4957 12:40:44.080081  CA_PREDIV_EN               = 0

 4958 12:40:44.083411  PH8_DLY                    = 0

 4959 12:40:44.086763  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 4960 12:40:44.090161  DQ_AAMCK_DIV               = 4

 4961 12:40:44.093687  CA_AAMCK_DIV               = 4

 4962 12:40:44.093772  CA_ADMCK_DIV               = 4

 4963 12:40:44.096536  DQ_TRACK_CA_EN             = 0

 4964 12:40:44.100187  CA_PICK                    = 933

 4965 12:40:44.103253  CA_MCKIO                   = 933

 4966 12:40:44.106722  MCKIO_SEMI                 = 0

 4967 12:40:44.110235  PLL_FREQ                   = 3732

 4968 12:40:44.113337  DQ_UI_PI_RATIO             = 32

 4969 12:40:44.113421  CA_UI_PI_RATIO             = 0

 4970 12:40:44.116742  =================================== 

 4971 12:40:44.120240  =================================== 

 4972 12:40:44.123745  memory_type:LPDDR4         

 4973 12:40:44.126868  GP_NUM     : 10       

 4974 12:40:44.126952  SRAM_EN    : 1       

 4975 12:40:44.129893  MD32_EN    : 0       

 4976 12:40:44.133260  =================================== 

 4977 12:40:44.136456  [ANA_INIT] >>>>>>>>>>>>>> 

 4978 12:40:44.140113  <<<<<< [CONFIGURE PHASE]: ANA_TX

 4979 12:40:44.143645  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 4980 12:40:44.146540  =================================== 

 4981 12:40:44.146625  data_rate = 1866,PCW = 0X8f00

 4982 12:40:44.149921  =================================== 

 4983 12:40:44.153022  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 4984 12:40:44.160052  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4985 12:40:44.166208  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4986 12:40:44.170064  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 4987 12:40:44.173073  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 4988 12:40:44.176754  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 4989 12:40:44.180129  [ANA_INIT] flow start 

 4990 12:40:44.180212  [ANA_INIT] PLL >>>>>>>> 

 4991 12:40:44.183553  [ANA_INIT] PLL <<<<<<<< 

 4992 12:40:44.186647  [ANA_INIT] MIDPI >>>>>>>> 

 4993 12:40:44.189845  [ANA_INIT] MIDPI <<<<<<<< 

 4994 12:40:44.189977  [ANA_INIT] DLL >>>>>>>> 

 4995 12:40:44.193219  [ANA_INIT] flow end 

 4996 12:40:44.196420  ============ LP4 DIFF to SE enter ============

 4997 12:40:44.199750  ============ LP4 DIFF to SE exit  ============

 4998 12:40:44.203298  [ANA_INIT] <<<<<<<<<<<<< 

 4999 12:40:44.206606  [Flow] Enable top DCM control >>>>> 

 5000 12:40:44.210117  [Flow] Enable top DCM control <<<<< 

 5001 12:40:44.213109  Enable DLL master slave shuffle 

 5002 12:40:44.216591  ============================================================== 

 5003 12:40:44.219757  Gating Mode config

 5004 12:40:44.226615  ============================================================== 

 5005 12:40:44.226706  Config description: 

 5006 12:40:44.236453  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 5007 12:40:44.243287  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 5008 12:40:44.249749  SELPH_MODE            0: By rank         1: By Phase 

 5009 12:40:44.252958  ============================================================== 

 5010 12:40:44.256396  GAT_TRACK_EN                 =  1

 5011 12:40:44.259825  RX_GATING_MODE               =  2

 5012 12:40:44.263152  RX_GATING_TRACK_MODE         =  2

 5013 12:40:44.266248  SELPH_MODE                   =  1

 5014 12:40:44.270002  PICG_EARLY_EN                =  1

 5015 12:40:44.272887  VALID_LAT_VALUE              =  1

 5016 12:40:44.276405  ============================================================== 

 5017 12:40:44.279892  Enter into Gating configuration >>>> 

 5018 12:40:44.283131  Exit from Gating configuration <<<< 

 5019 12:40:44.286916  Enter into  DVFS_PRE_config >>>>> 

 5020 12:40:44.299693  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 5021 12:40:44.299786  Exit from  DVFS_PRE_config <<<<< 

 5022 12:40:44.302774  Enter into PICG configuration >>>> 

 5023 12:40:44.306223  Exit from PICG configuration <<<< 

 5024 12:40:44.309866  [RX_INPUT] configuration >>>>> 

 5025 12:40:44.312902  [RX_INPUT] configuration <<<<< 

 5026 12:40:44.319497  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 5027 12:40:44.322631  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 5028 12:40:44.329436  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 5029 12:40:44.336539  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 5030 12:40:44.342591  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 5031 12:40:44.349270  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 5032 12:40:44.352672  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 5033 12:40:44.355915  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 5034 12:40:44.359609  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 5035 12:40:44.365868  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 5036 12:40:44.369372  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 5037 12:40:44.372747  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 5038 12:40:44.375844  =================================== 

 5039 12:40:44.379501  LPDDR4 DRAM CONFIGURATION

 5040 12:40:44.382536  =================================== 

 5041 12:40:44.385637  EX_ROW_EN[0]    = 0x0

 5042 12:40:44.385740  EX_ROW_EN[1]    = 0x0

 5043 12:40:44.389134  LP4Y_EN      = 0x0

 5044 12:40:44.389226  WORK_FSP     = 0x0

 5045 12:40:44.392213  WL           = 0x3

 5046 12:40:44.392296  RL           = 0x3

 5047 12:40:44.395647  BL           = 0x2

 5048 12:40:44.395754  RPST         = 0x0

 5049 12:40:44.399089  RD_PRE       = 0x0

 5050 12:40:44.399171  WR_PRE       = 0x1

 5051 12:40:44.402593  WR_PST       = 0x0

 5052 12:40:44.402699  DBI_WR       = 0x0

 5053 12:40:44.405843  DBI_RD       = 0x0

 5054 12:40:44.405992  OTF          = 0x1

 5055 12:40:44.409499  =================================== 

 5056 12:40:44.412452  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 5057 12:40:44.419185  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 5058 12:40:44.422569  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 5059 12:40:44.426116  =================================== 

 5060 12:40:44.429064  LPDDR4 DRAM CONFIGURATION

 5061 12:40:44.432666  =================================== 

 5062 12:40:44.432751  EX_ROW_EN[0]    = 0x10

 5063 12:40:44.435638  EX_ROW_EN[1]    = 0x0

 5064 12:40:44.439219  LP4Y_EN      = 0x0

 5065 12:40:44.439302  WORK_FSP     = 0x0

 5066 12:40:44.442405  WL           = 0x3

 5067 12:40:44.442488  RL           = 0x3

 5068 12:40:44.445582  BL           = 0x2

 5069 12:40:44.445665  RPST         = 0x0

 5070 12:40:44.448817  RD_PRE       = 0x0

 5071 12:40:44.448901  WR_PRE       = 0x1

 5072 12:40:44.452265  WR_PST       = 0x0

 5073 12:40:44.452348  DBI_WR       = 0x0

 5074 12:40:44.455901  DBI_RD       = 0x0

 5075 12:40:44.455984  OTF          = 0x1

 5076 12:40:44.458982  =================================== 

 5077 12:40:44.465488  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 5078 12:40:44.469748  nWR fixed to 30

 5079 12:40:44.473078  [ModeRegInit_LP4] CH0 RK0

 5080 12:40:44.473161  [ModeRegInit_LP4] CH0 RK1

 5081 12:40:44.476550  [ModeRegInit_LP4] CH1 RK0

 5082 12:40:44.479536  [ModeRegInit_LP4] CH1 RK1

 5083 12:40:44.479620  match AC timing 9

 5084 12:40:44.486209  dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1

 5085 12:40:44.489711  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 5086 12:40:44.493126  [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10

 5087 12:40:44.499530  [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21

 5088 12:40:44.503015  [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)

 5089 12:40:44.503106  ==

 5090 12:40:44.506475  Dram Type= 6, Freq= 0, CH_0, rank 0

 5091 12:40:44.509636  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5092 12:40:44.509725  ==

 5093 12:40:44.516274  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5094 12:40:44.522922  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5095 12:40:44.526374  [CA 0] Center 38 (7~69) winsize 63

 5096 12:40:44.529623  [CA 1] Center 38 (8~69) winsize 62

 5097 12:40:44.533010  [CA 2] Center 35 (5~66) winsize 62

 5098 12:40:44.536291  [CA 3] Center 35 (5~65) winsize 61

 5099 12:40:44.539903  [CA 4] Center 34 (4~65) winsize 62

 5100 12:40:44.542908  [CA 5] Center 33 (3~64) winsize 62

 5101 12:40:44.542996  

 5102 12:40:44.546588  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5103 12:40:44.546675  

 5104 12:40:44.549883  [CATrainingPosCal] consider 1 rank data

 5105 12:40:44.553149  u2DelayCellTimex100 = 270/100 ps

 5106 12:40:44.556146  CA0 delay=38 (7~69),Diff = 5 PI (31 cell)

 5107 12:40:44.559513  CA1 delay=38 (8~69),Diff = 5 PI (31 cell)

 5108 12:40:44.563237  CA2 delay=35 (5~66),Diff = 2 PI (12 cell)

 5109 12:40:44.566353  CA3 delay=35 (5~65),Diff = 2 PI (12 cell)

 5110 12:40:44.569697  CA4 delay=34 (4~65),Diff = 1 PI (6 cell)

 5111 12:40:44.573009  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5112 12:40:44.576335  

 5113 12:40:44.579761  CA PerBit enable=1, Macro0, CA PI delay=33

 5114 12:40:44.579848  

 5115 12:40:44.582936  [CBTSetCACLKResult] CA Dly = 33

 5116 12:40:44.583022  CS Dly: 6 (0~37)

 5117 12:40:44.583109  ==

 5118 12:40:44.586756  Dram Type= 6, Freq= 0, CH_0, rank 1

 5119 12:40:44.589509  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5120 12:40:44.589597  ==

 5121 12:40:44.596163  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5122 12:40:44.602970  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33

 5123 12:40:44.606054  [CA 0] Center 38 (8~69) winsize 62

 5124 12:40:44.609520  [CA 1] Center 38 (8~69) winsize 62

 5125 12:40:44.612633  [CA 2] Center 36 (6~66) winsize 61

 5126 12:40:44.616018  [CA 3] Center 35 (5~66) winsize 62

 5127 12:40:44.619398  [CA 4] Center 34 (4~65) winsize 62

 5128 12:40:44.622601  [CA 5] Center 34 (4~65) winsize 62

 5129 12:40:44.622685  

 5130 12:40:44.626148  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 5131 12:40:44.626232  

 5132 12:40:44.629369  [CATrainingPosCal] consider 2 rank data

 5133 12:40:44.632760  u2DelayCellTimex100 = 270/100 ps

 5134 12:40:44.636327  CA0 delay=38 (8~69),Diff = 4 PI (24 cell)

 5135 12:40:44.639471  CA1 delay=38 (8~69),Diff = 4 PI (24 cell)

 5136 12:40:44.642791  CA2 delay=36 (6~66),Diff = 2 PI (12 cell)

 5137 12:40:44.646056  CA3 delay=35 (5~65),Diff = 1 PI (6 cell)

 5138 12:40:44.649448  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 5139 12:40:44.653014  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 5140 12:40:44.656127  

 5141 12:40:44.659655  CA PerBit enable=1, Macro0, CA PI delay=34

 5142 12:40:44.659739  

 5143 12:40:44.662888  [CBTSetCACLKResult] CA Dly = 34

 5144 12:40:44.662972  CS Dly: 7 (0~39)

 5145 12:40:44.663038  

 5146 12:40:44.666509  ----->DramcWriteLeveling(PI) begin...

 5147 12:40:44.666594  ==

 5148 12:40:44.669568  Dram Type= 6, Freq= 0, CH_0, rank 0

 5149 12:40:44.673205  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5150 12:40:44.676465  ==

 5151 12:40:44.676549  Write leveling (Byte 0): 31 => 31

 5152 12:40:44.679753  Write leveling (Byte 1): 29 => 29

 5153 12:40:44.682716  DramcWriteLeveling(PI) end<-----

 5154 12:40:44.682800  

 5155 12:40:44.682865  ==

 5156 12:40:44.686623  Dram Type= 6, Freq= 0, CH_0, rank 0

 5157 12:40:44.692550  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5158 12:40:44.692638  ==

 5159 12:40:44.696189  [Gating] SW mode calibration

 5160 12:40:44.702679  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5161 12:40:44.705830  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5162 12:40:44.712386   0 14  0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)

 5163 12:40:44.715995   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5164 12:40:44.719053   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5165 12:40:44.725846   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5166 12:40:44.728965   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5167 12:40:44.732452   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5168 12:40:44.735696   0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)

 5169 12:40:44.742567   0 14 28 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)

 5170 12:40:44.746209   0 15  0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 5171 12:40:44.749279   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5172 12:40:44.755653   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5173 12:40:44.758971   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5174 12:40:44.762621   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5175 12:40:44.769025   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5176 12:40:44.772364   0 15 24 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)

 5177 12:40:44.775483   0 15 28 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)

 5178 12:40:44.782515   1  0  0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)

 5179 12:40:44.785521   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5180 12:40:44.789029   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5181 12:40:44.795363   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5182 12:40:44.799171   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5183 12:40:44.802157   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5184 12:40:44.808627   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5185 12:40:44.812027   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)

 5186 12:40:44.815432   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5187 12:40:44.822098   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5188 12:40:44.825582   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5189 12:40:44.828785   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5190 12:40:44.835046   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5191 12:40:44.838822   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5192 12:40:44.841823   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5193 12:40:44.848286   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5194 12:40:44.852131   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5195 12:40:44.855700   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5196 12:40:44.862359   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5197 12:40:44.865460   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5198 12:40:44.868703   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5199 12:40:44.875117   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5200 12:40:44.878299   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5201 12:40:44.881655   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)

 5202 12:40:44.885036  Total UI for P1: 0, mck2ui 16

 5203 12:40:44.888371  best dqsien dly found for B0: ( 1,  2, 24)

 5204 12:40:44.891651   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5205 12:40:44.894894  Total UI for P1: 0, mck2ui 16

 5206 12:40:44.898313  best dqsien dly found for B1: ( 1,  2, 30)

 5207 12:40:44.901491  best DQS0 dly(MCK, UI, PI) = (1, 2, 24)

 5208 12:40:44.908451  best DQS1 dly(MCK, UI, PI) = (1, 2, 30)

 5209 12:40:44.908561  

 5210 12:40:44.911491  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)

 5211 12:40:44.914825  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)

 5212 12:40:44.918003  [Gating] SW calibration Done

 5213 12:40:44.918119  ==

 5214 12:40:44.921803  Dram Type= 6, Freq= 0, CH_0, rank 0

 5215 12:40:44.924641  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5216 12:40:44.924726  ==

 5217 12:40:44.927941  RX Vref Scan: 0

 5218 12:40:44.928025  

 5219 12:40:44.928092  RX Vref 0 -> 0, step: 1

 5220 12:40:44.928160  

 5221 12:40:44.931402  RX Delay -80 -> 252, step: 8

 5222 12:40:44.934779  iDelay=208, Bit 0, Center 107 (16 ~ 199) 184

 5223 12:40:44.941314  iDelay=208, Bit 1, Center 107 (16 ~ 199) 184

 5224 12:40:44.944662  iDelay=208, Bit 2, Center 99 (8 ~ 191) 184

 5225 12:40:44.948054  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5226 12:40:44.951049  iDelay=208, Bit 4, Center 107 (16 ~ 199) 184

 5227 12:40:44.954837  iDelay=208, Bit 5, Center 95 (0 ~ 191) 192

 5228 12:40:44.957883  iDelay=208, Bit 6, Center 115 (24 ~ 207) 184

 5229 12:40:44.964586  iDelay=208, Bit 7, Center 115 (24 ~ 207) 184

 5230 12:40:44.967824  iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184

 5231 12:40:44.971140  iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176

 5232 12:40:44.974499  iDelay=208, Bit 10, Center 91 (0 ~ 183) 184

 5233 12:40:44.977657  iDelay=208, Bit 11, Center 87 (0 ~ 175) 176

 5234 12:40:44.981659  iDelay=208, Bit 12, Center 95 (8 ~ 183) 176

 5235 12:40:44.987566  iDelay=208, Bit 13, Center 95 (8 ~ 183) 176

 5236 12:40:44.991302  iDelay=208, Bit 14, Center 99 (8 ~ 191) 184

 5237 12:40:44.994961  iDelay=208, Bit 15, Center 99 (8 ~ 191) 184

 5238 12:40:44.995046  ==

 5239 12:40:44.997601  Dram Type= 6, Freq= 0, CH_0, rank 0

 5240 12:40:45.001446  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5241 12:40:45.001530  ==

 5242 12:40:45.004513  DQS Delay:

 5243 12:40:45.004597  DQS0 = 0, DQS1 = 0

 5244 12:40:45.004663  DQM Delay:

 5245 12:40:45.007805  DQM0 = 105, DQM1 = 91

 5246 12:40:45.007889  DQ Delay:

 5247 12:40:45.010840  DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99

 5248 12:40:45.014293  DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115

 5249 12:40:45.017481  DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87

 5250 12:40:45.020777  DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =99

 5251 12:40:45.020860  

 5252 12:40:45.020926  

 5253 12:40:45.024158  ==

 5254 12:40:45.027515  Dram Type= 6, Freq= 0, CH_0, rank 0

 5255 12:40:45.030909  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5256 12:40:45.030993  ==

 5257 12:40:45.031058  

 5258 12:40:45.031118  

 5259 12:40:45.034220  	TX Vref Scan disable

 5260 12:40:45.034304   == TX Byte 0 ==

 5261 12:40:45.037661  Update DQ  dly =714 (2 ,6, 10)  DQ  OEN =(2 ,3)

 5262 12:40:45.044329  Update DQM dly =714 (2 ,6, 10)  DQM OEN =(2 ,3)

 5263 12:40:45.044413   == TX Byte 1 ==

 5264 12:40:45.050843  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5265 12:40:45.054224  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5266 12:40:45.054308  ==

 5267 12:40:45.057469  Dram Type= 6, Freq= 0, CH_0, rank 0

 5268 12:40:45.061148  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5269 12:40:45.061237  ==

 5270 12:40:45.061304  

 5271 12:40:45.061367  

 5272 12:40:45.063882  	TX Vref Scan disable

 5273 12:40:45.067391   == TX Byte 0 ==

 5274 12:40:45.070473  Update DQ  dly =714 (2 ,6, 10)  DQ  OEN =(2 ,3)

 5275 12:40:45.073898  Update DQM dly =714 (2 ,6, 10)  DQM OEN =(2 ,3)

 5276 12:40:45.077150   == TX Byte 1 ==

 5277 12:40:45.080724  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5278 12:40:45.083848  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5279 12:40:45.083931  

 5280 12:40:45.087060  [DATLAT]

 5281 12:40:45.087143  Freq=933, CH0 RK0

 5282 12:40:45.087209  

 5283 12:40:45.090483  DATLAT Default: 0xd

 5284 12:40:45.090566  0, 0xFFFF, sum = 0

 5285 12:40:45.093961  1, 0xFFFF, sum = 0

 5286 12:40:45.094060  2, 0xFFFF, sum = 0

 5287 12:40:45.097326  3, 0xFFFF, sum = 0

 5288 12:40:45.097411  4, 0xFFFF, sum = 0

 5289 12:40:45.100944  5, 0xFFFF, sum = 0

 5290 12:40:45.101028  6, 0xFFFF, sum = 0

 5291 12:40:45.103958  7, 0xFFFF, sum = 0

 5292 12:40:45.104043  8, 0xFFFF, sum = 0

 5293 12:40:45.107260  9, 0xFFFF, sum = 0

 5294 12:40:45.107347  10, 0x0, sum = 1

 5295 12:40:45.110413  11, 0x0, sum = 2

 5296 12:40:45.110503  12, 0x0, sum = 3

 5297 12:40:45.114349  13, 0x0, sum = 4

 5298 12:40:45.114433  best_step = 11

 5299 12:40:45.114498  

 5300 12:40:45.114558  ==

 5301 12:40:45.117198  Dram Type= 6, Freq= 0, CH_0, rank 0

 5302 12:40:45.120482  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5303 12:40:45.123917  ==

 5304 12:40:45.124001  RX Vref Scan: 1

 5305 12:40:45.124066  

 5306 12:40:45.127333  RX Vref 0 -> 0, step: 1

 5307 12:40:45.127416  

 5308 12:40:45.130350  RX Delay -53 -> 252, step: 4

 5309 12:40:45.130433  

 5310 12:40:45.133726  Set Vref, RX VrefLevel [Byte0]: 59

 5311 12:40:45.137291                           [Byte1]: 50

 5312 12:40:45.137375  

 5313 12:40:45.140518  Final RX Vref Byte 0 = 59 to rank0

 5314 12:40:45.144116  Final RX Vref Byte 1 = 50 to rank0

 5315 12:40:45.147044  Final RX Vref Byte 0 = 59 to rank1

 5316 12:40:45.150216  Final RX Vref Byte 1 = 50 to rank1==

 5317 12:40:45.153892  Dram Type= 6, Freq= 0, CH_0, rank 0

 5318 12:40:45.157366  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5319 12:40:45.157454  ==

 5320 12:40:45.160318  DQS Delay:

 5321 12:40:45.160406  DQS0 = 0, DQS1 = 0

 5322 12:40:45.160491  DQM Delay:

 5323 12:40:45.163892  DQM0 = 107, DQM1 = 92

 5324 12:40:45.163976  DQ Delay:

 5325 12:40:45.166920  DQ0 =106, DQ1 =106, DQ2 =102, DQ3 =106

 5326 12:40:45.170169  DQ4 =106, DQ5 =98, DQ6 =116, DQ7 =116

 5327 12:40:45.173959  DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =90

 5328 12:40:45.177082  DQ12 =96, DQ13 =96, DQ14 =102, DQ15 =100

 5329 12:40:45.177166  

 5330 12:40:45.177232  

 5331 12:40:45.186624  [DQSOSCAuto] RK0, (LSB)MR18= 0x211d, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps

 5332 12:40:45.190036  CH0 RK0: MR19=505, MR18=211D

 5333 12:40:45.196782  CH0_RK0: MR19=0x505, MR18=0x211D, DQSOSC=411, MR23=63, INC=64, DEC=42

 5334 12:40:45.196869  

 5335 12:40:45.199948  ----->DramcWriteLeveling(PI) begin...

 5336 12:40:45.200034  ==

 5337 12:40:45.203647  Dram Type= 6, Freq= 0, CH_0, rank 1

 5338 12:40:45.206725  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5339 12:40:45.206812  ==

 5340 12:40:45.209970  Write leveling (Byte 0): 32 => 32

 5341 12:40:45.213667  Write leveling (Byte 1): 28 => 28

 5342 12:40:45.216989  DramcWriteLeveling(PI) end<-----

 5343 12:40:45.217074  

 5344 12:40:45.217140  ==

 5345 12:40:45.220287  Dram Type= 6, Freq= 0, CH_0, rank 1

 5346 12:40:45.223609  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5347 12:40:45.223693  ==

 5348 12:40:45.226828  [Gating] SW mode calibration

 5349 12:40:45.233607  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5350 12:40:45.240140  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5351 12:40:45.243476   0 14  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5352 12:40:45.246965   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5353 12:40:45.253601   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5354 12:40:45.256852   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5355 12:40:45.260243   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5356 12:40:45.266873   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5357 12:40:45.270295   0 14 24 | B1->B0 | 3333 3030 | 0 0 | (1 0) (0 0)

 5358 12:40:45.273575   0 14 28 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)

 5359 12:40:45.277147   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

 5360 12:40:45.283323   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5361 12:40:45.286899   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5362 12:40:45.290122   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5363 12:40:45.296628   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5364 12:40:45.299941   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5365 12:40:45.303174   0 15 24 | B1->B0 | 2727 2828 | 0 0 | (0 0) (0 0)

 5366 12:40:45.310010   0 15 28 | B1->B0 | 3737 4141 | 0 0 | (0 0) (0 0)

 5367 12:40:45.313289   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5368 12:40:45.317008   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5369 12:40:45.323306   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5370 12:40:45.326489   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5371 12:40:45.329978   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5372 12:40:45.336453   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5373 12:40:45.340039   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5374 12:40:45.343255   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 5375 12:40:45.349885   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5376 12:40:45.353448   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5377 12:40:45.356974   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5378 12:40:45.363355   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5379 12:40:45.366371   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5380 12:40:45.369959   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5381 12:40:45.376660   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5382 12:40:45.379821   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5383 12:40:45.383135   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5384 12:40:45.389809   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5385 12:40:45.393023   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5386 12:40:45.396401   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5387 12:40:45.403095   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5388 12:40:45.406409   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5389 12:40:45.409823   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5390 12:40:45.413028   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5391 12:40:45.416893  Total UI for P1: 0, mck2ui 16

 5392 12:40:45.419781  best dqsien dly found for B0: ( 1,  2, 24)

 5393 12:40:45.426407   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5394 12:40:45.426490  Total UI for P1: 0, mck2ui 16

 5395 12:40:45.433303  best dqsien dly found for B1: ( 1,  2, 28)

 5396 12:40:45.436563  best DQS0 dly(MCK, UI, PI) = (1, 2, 24)

 5397 12:40:45.439665  best DQS1 dly(MCK, UI, PI) = (1, 2, 28)

 5398 12:40:45.439747  

 5399 12:40:45.443188  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)

 5400 12:40:45.446304  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5401 12:40:45.449608  [Gating] SW calibration Done

 5402 12:40:45.449691  ==

 5403 12:40:45.452986  Dram Type= 6, Freq= 0, CH_0, rank 1

 5404 12:40:45.456570  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5405 12:40:45.456654  ==

 5406 12:40:45.459790  RX Vref Scan: 0

 5407 12:40:45.459873  

 5408 12:40:45.459938  RX Vref 0 -> 0, step: 1

 5409 12:40:45.459998  

 5410 12:40:45.462898  RX Delay -80 -> 252, step: 8

 5411 12:40:45.469629  iDelay=208, Bit 0, Center 103 (8 ~ 199) 192

 5412 12:40:45.473041  iDelay=208, Bit 1, Center 111 (24 ~ 199) 176

 5413 12:40:45.476351  iDelay=208, Bit 2, Center 99 (8 ~ 191) 184

 5414 12:40:45.479362  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5415 12:40:45.482593  iDelay=208, Bit 4, Center 111 (24 ~ 199) 176

 5416 12:40:45.485979  iDelay=208, Bit 5, Center 95 (0 ~ 191) 192

 5417 12:40:45.492571  iDelay=208, Bit 6, Center 115 (24 ~ 207) 184

 5418 12:40:45.495807  iDelay=208, Bit 7, Center 115 (24 ~ 207) 184

 5419 12:40:45.499615  iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184

 5420 12:40:45.502395  iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176

 5421 12:40:45.505659  iDelay=208, Bit 10, Center 91 (0 ~ 183) 184

 5422 12:40:45.509043  iDelay=208, Bit 11, Center 87 (0 ~ 175) 176

 5423 12:40:45.515967  iDelay=208, Bit 12, Center 95 (0 ~ 191) 192

 5424 12:40:45.518958  iDelay=208, Bit 13, Center 91 (0 ~ 183) 184

 5425 12:40:45.522360  iDelay=208, Bit 14, Center 95 (0 ~ 191) 192

 5426 12:40:45.525421  iDelay=208, Bit 15, Center 99 (8 ~ 191) 184

 5427 12:40:45.525504  ==

 5428 12:40:45.528967  Dram Type= 6, Freq= 0, CH_0, rank 1

 5429 12:40:45.532343  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5430 12:40:45.535578  ==

 5431 12:40:45.535660  DQS Delay:

 5432 12:40:45.535725  DQS0 = 0, DQS1 = 0

 5433 12:40:45.538790  DQM Delay:

 5434 12:40:45.538875  DQM0 = 106, DQM1 = 90

 5435 12:40:45.542236  DQ Delay:

 5436 12:40:45.545917  DQ0 =103, DQ1 =111, DQ2 =99, DQ3 =99

 5437 12:40:45.548854  DQ4 =111, DQ5 =95, DQ6 =115, DQ7 =115

 5438 12:40:45.552321  DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87

 5439 12:40:45.555698  DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =99

 5440 12:40:45.555780  

 5441 12:40:45.555845  

 5442 12:40:45.555904  ==

 5443 12:40:45.558882  Dram Type= 6, Freq= 0, CH_0, rank 1

 5444 12:40:45.562123  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5445 12:40:45.562206  ==

 5446 12:40:45.562270  

 5447 12:40:45.562330  

 5448 12:40:45.565453  	TX Vref Scan disable

 5449 12:40:45.565535   == TX Byte 0 ==

 5450 12:40:45.572101  Update DQ  dly =716 (2 ,6, 12)  DQ  OEN =(2 ,3)

 5451 12:40:45.575449  Update DQM dly =716 (2 ,6, 12)  DQM OEN =(2 ,3)

 5452 12:40:45.575532   == TX Byte 1 ==

 5453 12:40:45.582320  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5454 12:40:45.585320  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5455 12:40:45.585406  ==

 5456 12:40:45.589021  Dram Type= 6, Freq= 0, CH_0, rank 1

 5457 12:40:45.592133  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5458 12:40:45.592219  ==

 5459 12:40:45.592286  

 5460 12:40:45.595428  

 5461 12:40:45.595512  	TX Vref Scan disable

 5462 12:40:45.598835   == TX Byte 0 ==

 5463 12:40:45.602084  Update DQ  dly =715 (2 ,6, 11)  DQ  OEN =(2 ,3)

 5464 12:40:45.608721  Update DQM dly =715 (2 ,6, 11)  DQM OEN =(2 ,3)

 5465 12:40:45.608809   == TX Byte 1 ==

 5466 12:40:45.612164  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5467 12:40:45.618848  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5468 12:40:45.618933  

 5469 12:40:45.618999  [DATLAT]

 5470 12:40:45.619058  Freq=933, CH0 RK1

 5471 12:40:45.619118  

 5472 12:40:45.622146  DATLAT Default: 0xb

 5473 12:40:45.622230  0, 0xFFFF, sum = 0

 5474 12:40:45.625449  1, 0xFFFF, sum = 0

 5475 12:40:45.625534  2, 0xFFFF, sum = 0

 5476 12:40:45.628558  3, 0xFFFF, sum = 0

 5477 12:40:45.631766  4, 0xFFFF, sum = 0

 5478 12:40:45.631851  5, 0xFFFF, sum = 0

 5479 12:40:45.635396  6, 0xFFFF, sum = 0

 5480 12:40:45.635481  7, 0xFFFF, sum = 0

 5481 12:40:45.638960  8, 0xFFFF, sum = 0

 5482 12:40:45.639044  9, 0xFFFF, sum = 0

 5483 12:40:45.642251  10, 0x0, sum = 1

 5484 12:40:45.642336  11, 0x0, sum = 2

 5485 12:40:45.642402  12, 0x0, sum = 3

 5486 12:40:45.645401  13, 0x0, sum = 4

 5487 12:40:45.645485  best_step = 11

 5488 12:40:45.645549  

 5489 12:40:45.648884  ==

 5490 12:40:45.648967  Dram Type= 6, Freq= 0, CH_0, rank 1

 5491 12:40:45.655363  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5492 12:40:45.655447  ==

 5493 12:40:45.655512  RX Vref Scan: 0

 5494 12:40:45.655573  

 5495 12:40:45.658338  RX Vref 0 -> 0, step: 1

 5496 12:40:45.658420  

 5497 12:40:45.661975  RX Delay -53 -> 252, step: 4

 5498 12:40:45.665188  iDelay=199, Bit 0, Center 104 (19 ~ 190) 172

 5499 12:40:45.671881  iDelay=199, Bit 1, Center 106 (19 ~ 194) 176

 5500 12:40:45.674951  iDelay=199, Bit 2, Center 102 (19 ~ 186) 168

 5501 12:40:45.678332  iDelay=199, Bit 3, Center 98 (15 ~ 182) 168

 5502 12:40:45.681720  iDelay=199, Bit 4, Center 104 (19 ~ 190) 172

 5503 12:40:45.685123  iDelay=199, Bit 5, Center 98 (11 ~ 186) 176

 5504 12:40:45.691947  iDelay=199, Bit 6, Center 112 (27 ~ 198) 172

 5505 12:40:45.695686  iDelay=199, Bit 7, Center 110 (23 ~ 198) 176

 5506 12:40:45.698307  iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172

 5507 12:40:45.701680  iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164

 5508 12:40:45.705088  iDelay=199, Bit 10, Center 94 (11 ~ 178) 168

 5509 12:40:45.708329  iDelay=199, Bit 11, Center 90 (7 ~ 174) 168

 5510 12:40:45.714728  iDelay=199, Bit 12, Center 98 (15 ~ 182) 168

 5511 12:40:45.718287  iDelay=199, Bit 13, Center 94 (11 ~ 178) 168

 5512 12:40:45.721900  iDelay=199, Bit 14, Center 102 (15 ~ 190) 176

 5513 12:40:45.724851  iDelay=199, Bit 15, Center 98 (15 ~ 182) 168

 5514 12:40:45.724934  ==

 5515 12:40:45.728109  Dram Type= 6, Freq= 0, CH_0, rank 1

 5516 12:40:45.735001  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5517 12:40:45.735086  ==

 5518 12:40:45.735151  DQS Delay:

 5519 12:40:45.735211  DQS0 = 0, DQS1 = 0

 5520 12:40:45.738514  DQM Delay:

 5521 12:40:45.738596  DQM0 = 104, DQM1 = 92

 5522 12:40:45.741742  DQ Delay:

 5523 12:40:45.745021  DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =98

 5524 12:40:45.748071  DQ4 =104, DQ5 =98, DQ6 =112, DQ7 =110

 5525 12:40:45.751721  DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =90

 5526 12:40:45.754810  DQ12 =98, DQ13 =94, DQ14 =102, DQ15 =98

 5527 12:40:45.754893  

 5528 12:40:45.754957  

 5529 12:40:45.761343  [DQSOSCAuto] RK1, (LSB)MR18= 0x2d0d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps

 5530 12:40:45.764787  CH0 RK1: MR19=505, MR18=2D0D

 5531 12:40:45.771278  CH0_RK1: MR19=0x505, MR18=0x2D0D, DQSOSC=407, MR23=63, INC=65, DEC=43

 5532 12:40:45.774515  [RxdqsGatingPostProcess] freq 933

 5533 12:40:45.781264  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5534 12:40:45.781348  best DQS0 dly(2T, 0.5T) = (0, 10)

 5535 12:40:45.784420  best DQS1 dly(2T, 0.5T) = (0, 10)

 5536 12:40:45.788408  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5537 12:40:45.791321  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5538 12:40:45.794398  best DQS0 dly(2T, 0.5T) = (0, 10)

 5539 12:40:45.797787  best DQS1 dly(2T, 0.5T) = (0, 10)

 5540 12:40:45.801253  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5541 12:40:45.804468  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5542 12:40:45.808287  Pre-setting of DQS Precalculation

 5543 12:40:45.811271  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5544 12:40:45.814291  ==

 5545 12:40:45.817832  Dram Type= 6, Freq= 0, CH_1, rank 0

 5546 12:40:45.820989  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5547 12:40:45.821079  ==

 5548 12:40:45.824322  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5549 12:40:45.831520  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33

 5550 12:40:45.834834  [CA 0] Center 37 (7~68) winsize 62

 5551 12:40:45.838193  [CA 1] Center 37 (7~68) winsize 62

 5552 12:40:45.841317  [CA 2] Center 36 (6~66) winsize 61

 5553 12:40:45.844841  [CA 3] Center 34 (4~65) winsize 62

 5554 12:40:45.848285  [CA 4] Center 35 (5~65) winsize 61

 5555 12:40:45.851305  [CA 5] Center 34 (4~65) winsize 62

 5556 12:40:45.851390  

 5557 12:40:45.854708  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 5558 12:40:45.854792  

 5559 12:40:45.858405  [CATrainingPosCal] consider 1 rank data

 5560 12:40:45.861785  u2DelayCellTimex100 = 270/100 ps

 5561 12:40:45.864790  CA0 delay=37 (7~68),Diff = 3 PI (18 cell)

 5562 12:40:45.868428  CA1 delay=37 (7~68),Diff = 3 PI (18 cell)

 5563 12:40:45.874992  CA2 delay=36 (6~66),Diff = 2 PI (12 cell)

 5564 12:40:45.878149  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 5565 12:40:45.881693  CA4 delay=35 (5~65),Diff = 1 PI (6 cell)

 5566 12:40:45.885217  CA5 delay=34 (4~65),Diff = 0 PI (0 cell)

 5567 12:40:45.885302  

 5568 12:40:45.887976  CA PerBit enable=1, Macro0, CA PI delay=34

 5569 12:40:45.888061  

 5570 12:40:45.891464  [CBTSetCACLKResult] CA Dly = 34

 5571 12:40:45.891574  CS Dly: 7 (0~38)

 5572 12:40:45.894865  ==

 5573 12:40:45.894950  Dram Type= 6, Freq= 0, CH_1, rank 1

 5574 12:40:45.901293  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5575 12:40:45.901379  ==

 5576 12:40:45.904980  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5577 12:40:45.911106  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5578 12:40:45.914917  [CA 0] Center 38 (8~69) winsize 62

 5579 12:40:45.918228  [CA 1] Center 38 (8~69) winsize 62

 5580 12:40:45.921667  [CA 2] Center 36 (6~66) winsize 61

 5581 12:40:45.925261  [CA 3] Center 35 (6~65) winsize 60

 5582 12:40:45.928055  [CA 4] Center 35 (5~65) winsize 61

 5583 12:40:45.931573  [CA 5] Center 35 (5~65) winsize 61

 5584 12:40:45.931658  

 5585 12:40:45.934583  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5586 12:40:45.934668  

 5587 12:40:45.938289  [CATrainingPosCal] consider 2 rank data

 5588 12:40:45.941884  u2DelayCellTimex100 = 270/100 ps

 5589 12:40:45.944946  CA0 delay=38 (8~68),Diff = 3 PI (18 cell)

 5590 12:40:45.948253  CA1 delay=38 (8~68),Diff = 3 PI (18 cell)

 5591 12:40:45.954669  CA2 delay=36 (6~66),Diff = 1 PI (6 cell)

 5592 12:40:45.958246  CA3 delay=35 (6~65),Diff = 0 PI (0 cell)

 5593 12:40:45.961309  CA4 delay=35 (5~65),Diff = 0 PI (0 cell)

 5594 12:40:45.964884  CA5 delay=35 (5~65),Diff = 0 PI (0 cell)

 5595 12:40:45.964969  

 5596 12:40:45.968225  CA PerBit enable=1, Macro0, CA PI delay=35

 5597 12:40:45.968313  

 5598 12:40:45.971599  [CBTSetCACLKResult] CA Dly = 35

 5599 12:40:45.971697  CS Dly: 7 (0~39)

 5600 12:40:45.971763  

 5601 12:40:45.974505  ----->DramcWriteLeveling(PI) begin...

 5602 12:40:45.978206  ==

 5603 12:40:45.981221  Dram Type= 6, Freq= 0, CH_1, rank 0

 5604 12:40:45.984672  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5605 12:40:45.984758  ==

 5606 12:40:45.988410  Write leveling (Byte 0): 27 => 27

 5607 12:40:45.991339  Write leveling (Byte 1): 28 => 28

 5608 12:40:45.994613  DramcWriteLeveling(PI) end<-----

 5609 12:40:45.994697  

 5610 12:40:45.994763  ==

 5611 12:40:45.997959  Dram Type= 6, Freq= 0, CH_1, rank 0

 5612 12:40:46.001408  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5613 12:40:46.001494  ==

 5614 12:40:46.004604  [Gating] SW mode calibration

 5615 12:40:46.011076  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5616 12:40:46.018063  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5617 12:40:46.021115   0 14  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5618 12:40:46.024649   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5619 12:40:46.027840   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5620 12:40:46.034617   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5621 12:40:46.037569   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5622 12:40:46.041402   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 5623 12:40:46.048066   0 14 24 | B1->B0 | 3232 3232 | 1 1 | (1 0) (1 0)

 5624 12:40:46.051178   0 14 28 | B1->B0 | 2b2b 2424 | 0 0 | (1 0) (0 0)

 5625 12:40:46.054376   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5626 12:40:46.061065   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5627 12:40:46.064269   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5628 12:40:46.067604   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5629 12:40:46.074521   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5630 12:40:46.077851   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5631 12:40:46.081105   0 15 24 | B1->B0 | 2c2c 2e2e | 0 0 | (0 0) (0 0)

 5632 12:40:46.087575   0 15 28 | B1->B0 | 3d3d 4444 | 0 0 | (0 0) (0 0)

 5633 12:40:46.091015   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5634 12:40:46.094213   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5635 12:40:46.100939   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5636 12:40:46.104389   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5637 12:40:46.107533   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5638 12:40:46.114209   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5639 12:40:46.117452   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5640 12:40:46.121108   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5641 12:40:46.127796   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5642 12:40:46.130726   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5643 12:40:46.134131   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5644 12:40:46.141472   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5645 12:40:46.144083   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5646 12:40:46.147743   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5647 12:40:46.154007   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5648 12:40:46.157593   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5649 12:40:46.160512   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5650 12:40:46.167145   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5651 12:40:46.170534   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5652 12:40:46.173807   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5653 12:40:46.177217   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5654 12:40:46.184044   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5655 12:40:46.187348   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)

 5656 12:40:46.190574  Total UI for P1: 0, mck2ui 16

 5657 12:40:46.194127  best dqsien dly found for B0: ( 1,  2, 22)

 5658 12:40:46.197287   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5659 12:40:46.203986   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5660 12:40:46.207240  Total UI for P1: 0, mck2ui 16

 5661 12:40:46.210447  best dqsien dly found for B1: ( 1,  2, 28)

 5662 12:40:46.213759  best DQS0 dly(MCK, UI, PI) = (1, 2, 22)

 5663 12:40:46.217035  best DQS1 dly(MCK, UI, PI) = (1, 2, 28)

 5664 12:40:46.217119  

 5665 12:40:46.220454  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)

 5666 12:40:46.223914  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5667 12:40:46.227269  [Gating] SW calibration Done

 5668 12:40:46.227352  ==

 5669 12:40:46.230400  Dram Type= 6, Freq= 0, CH_1, rank 0

 5670 12:40:46.234242  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5671 12:40:46.234345  ==

 5672 12:40:46.237141  RX Vref Scan: 0

 5673 12:40:46.237226  

 5674 12:40:46.237309  RX Vref 0 -> 0, step: 1

 5675 12:40:46.240423  

 5676 12:40:46.240509  RX Delay -80 -> 252, step: 8

 5677 12:40:46.247120  iDelay=208, Bit 0, Center 107 (24 ~ 191) 168

 5678 12:40:46.250591  iDelay=208, Bit 1, Center 99 (16 ~ 183) 168

 5679 12:40:46.253839  iDelay=208, Bit 2, Center 95 (8 ~ 183) 176

 5680 12:40:46.257292  iDelay=208, Bit 3, Center 103 (16 ~ 191) 176

 5681 12:40:46.260381  iDelay=208, Bit 4, Center 103 (16 ~ 191) 176

 5682 12:40:46.263941  iDelay=208, Bit 5, Center 111 (24 ~ 199) 176

 5683 12:40:46.270406  iDelay=208, Bit 6, Center 111 (16 ~ 207) 192

 5684 12:40:46.273769  iDelay=208, Bit 7, Center 103 (16 ~ 191) 176

 5685 12:40:46.276877  iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184

 5686 12:40:46.280144  iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184

 5687 12:40:46.283243  iDelay=208, Bit 10, Center 99 (8 ~ 191) 184

 5688 12:40:46.290438  iDelay=208, Bit 11, Center 91 (0 ~ 183) 184

 5689 12:40:46.293408  iDelay=208, Bit 12, Center 103 (8 ~ 199) 192

 5690 12:40:46.296650  iDelay=208, Bit 13, Center 103 (8 ~ 199) 192

 5691 12:40:46.300037  iDelay=208, Bit 14, Center 103 (8 ~ 199) 192

 5692 12:40:46.303567  iDelay=208, Bit 15, Center 99 (8 ~ 191) 184

 5693 12:40:46.303653  ==

 5694 12:40:46.306991  Dram Type= 6, Freq= 0, CH_1, rank 0

 5695 12:40:46.313312  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5696 12:40:46.313402  ==

 5697 12:40:46.313489  DQS Delay:

 5698 12:40:46.316796  DQS0 = 0, DQS1 = 0

 5699 12:40:46.316883  DQM Delay:

 5700 12:40:46.316968  DQM0 = 104, DQM1 = 95

 5701 12:40:46.320090  DQ Delay:

 5702 12:40:46.323508  DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =103

 5703 12:40:46.326655  DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =103

 5704 12:40:46.329883  DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91

 5705 12:40:46.333379  DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99

 5706 12:40:46.333464  

 5707 12:40:46.333530  

 5708 12:40:46.333590  ==

 5709 12:40:46.336241  Dram Type= 6, Freq= 0, CH_1, rank 0

 5710 12:40:46.339879  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5711 12:40:46.339965  ==

 5712 12:40:46.340031  

 5713 12:40:46.340091  

 5714 12:40:46.343497  	TX Vref Scan disable

 5715 12:40:46.346317   == TX Byte 0 ==

 5716 12:40:46.349718  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5717 12:40:46.353464  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5718 12:40:46.356972   == TX Byte 1 ==

 5719 12:40:46.359775  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5720 12:40:46.363645  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5721 12:40:46.363741  ==

 5722 12:40:46.366466  Dram Type= 6, Freq= 0, CH_1, rank 0

 5723 12:40:46.373127  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5724 12:40:46.373215  ==

 5725 12:40:46.373282  

 5726 12:40:46.373343  

 5727 12:40:46.373402  	TX Vref Scan disable

 5728 12:40:46.377162   == TX Byte 0 ==

 5729 12:40:46.380517  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5730 12:40:46.383587  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5731 12:40:46.387056   == TX Byte 1 ==

 5732 12:40:46.390366  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5733 12:40:46.393730  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5734 12:40:46.396973  

 5735 12:40:46.397058  [DATLAT]

 5736 12:40:46.397125  Freq=933, CH1 RK0

 5737 12:40:46.397199  

 5738 12:40:46.400189  DATLAT Default: 0xd

 5739 12:40:46.400274  0, 0xFFFF, sum = 0

 5740 12:40:46.403835  1, 0xFFFF, sum = 0

 5741 12:40:46.403922  2, 0xFFFF, sum = 0

 5742 12:40:46.407292  3, 0xFFFF, sum = 0

 5743 12:40:46.410151  4, 0xFFFF, sum = 0

 5744 12:40:46.410238  5, 0xFFFF, sum = 0

 5745 12:40:46.413507  6, 0xFFFF, sum = 0

 5746 12:40:46.413594  7, 0xFFFF, sum = 0

 5747 12:40:46.416709  8, 0xFFFF, sum = 0

 5748 12:40:46.416796  9, 0xFFFF, sum = 0

 5749 12:40:46.420389  10, 0x0, sum = 1

 5750 12:40:46.420475  11, 0x0, sum = 2

 5751 12:40:46.420542  12, 0x0, sum = 3

 5752 12:40:46.423420  13, 0x0, sum = 4

 5753 12:40:46.423508  best_step = 11

 5754 12:40:46.423576  

 5755 12:40:46.426796  ==

 5756 12:40:46.426882  Dram Type= 6, Freq= 0, CH_1, rank 0

 5757 12:40:46.433355  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5758 12:40:46.433458  ==

 5759 12:40:46.433607  RX Vref Scan: 1

 5760 12:40:46.433719  

 5761 12:40:46.436934  RX Vref 0 -> 0, step: 1

 5762 12:40:46.437043  

 5763 12:40:46.440152  RX Delay -53 -> 252, step: 4

 5764 12:40:46.440235  

 5765 12:40:46.443786  Set Vref, RX VrefLevel [Byte0]: 54

 5766 12:40:46.446867                           [Byte1]: 53

 5767 12:40:46.446951  

 5768 12:40:46.450421  Final RX Vref Byte 0 = 54 to rank0

 5769 12:40:46.453732  Final RX Vref Byte 1 = 53 to rank0

 5770 12:40:46.457057  Final RX Vref Byte 0 = 54 to rank1

 5771 12:40:46.460708  Final RX Vref Byte 1 = 53 to rank1==

 5772 12:40:46.463642  Dram Type= 6, Freq= 0, CH_1, rank 0

 5773 12:40:46.466855  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5774 12:40:46.466943  ==

 5775 12:40:46.470161  DQS Delay:

 5776 12:40:46.470247  DQS0 = 0, DQS1 = 0

 5777 12:40:46.473239  DQM Delay:

 5778 12:40:46.473325  DQM0 = 104, DQM1 = 97

 5779 12:40:46.473410  DQ Delay:

 5780 12:40:46.476818  DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102

 5781 12:40:46.480184  DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =102

 5782 12:40:46.483511  DQ8 =88, DQ9 =84, DQ10 =100, DQ11 =92

 5783 12:40:46.489913  DQ12 =106, DQ13 =102, DQ14 =106, DQ15 =104

 5784 12:40:46.490008  

 5785 12:40:46.490091  

 5786 12:40:46.496584  [DQSOSCAuto] RK0, (LSB)MR18= 0x1a32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps

 5787 12:40:46.500031  CH1 RK0: MR19=505, MR18=1A32

 5788 12:40:46.506676  CH1_RK0: MR19=0x505, MR18=0x1A32, DQSOSC=406, MR23=63, INC=65, DEC=43

 5789 12:40:46.506763  

 5790 12:40:46.509887  ----->DramcWriteLeveling(PI) begin...

 5791 12:40:46.510017  ==

 5792 12:40:46.512991  Dram Type= 6, Freq= 0, CH_1, rank 1

 5793 12:40:46.516239  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5794 12:40:46.516331  ==

 5795 12:40:46.519772  Write leveling (Byte 0): 25 => 25

 5796 12:40:46.522950  Write leveling (Byte 1): 28 => 28

 5797 12:40:46.526377  DramcWriteLeveling(PI) end<-----

 5798 12:40:46.526466  

 5799 12:40:46.526551  ==

 5800 12:40:46.530134  Dram Type= 6, Freq= 0, CH_1, rank 1

 5801 12:40:46.533200  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5802 12:40:46.533288  ==

 5803 12:40:46.536341  [Gating] SW mode calibration

 5804 12:40:46.543025  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5805 12:40:46.549548  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5806 12:40:46.552950   0 14  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5807 12:40:46.559568   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5808 12:40:46.562909   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5809 12:40:46.566409   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5810 12:40:46.572995   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5811 12:40:46.576177   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5812 12:40:46.579361   0 14 24 | B1->B0 | 3131 3434 | 1 0 | (0 1) (0 1)

 5813 12:40:46.586129   0 14 28 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 0)

 5814 12:40:46.589340   0 15  0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 5815 12:40:46.593233   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5816 12:40:46.596050   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5817 12:40:46.602895   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5818 12:40:46.605948   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5819 12:40:46.609371   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5820 12:40:46.616318   0 15 24 | B1->B0 | 2f2f 2626 | 0 0 | (0 0) (0 0)

 5821 12:40:46.619391   0 15 28 | B1->B0 | 4141 3939 | 0 0 | (0 0) (1 1)

 5822 12:40:46.622611   1  0  0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)

 5823 12:40:46.629403   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5824 12:40:46.632838   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5825 12:40:46.635890   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5826 12:40:46.642824   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5827 12:40:46.646477   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5828 12:40:46.649329   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5829 12:40:46.655897   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5830 12:40:46.659277   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5831 12:40:46.662655   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5832 12:40:46.669213   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5833 12:40:46.672676   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5834 12:40:46.676140   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5835 12:40:46.682444   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5836 12:40:46.685931   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5837 12:40:46.689163   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5838 12:40:46.696089   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5839 12:40:46.698968   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5840 12:40:46.702318   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5841 12:40:46.709168   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5842 12:40:46.712483   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5843 12:40:46.715610   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5844 12:40:46.722346   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5845 12:40:46.725685   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5846 12:40:46.729289   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5847 12:40:46.732510  Total UI for P1: 0, mck2ui 16

 5848 12:40:46.735634  best dqsien dly found for B0: ( 1,  2, 28)

 5849 12:40:46.739056  Total UI for P1: 0, mck2ui 16

 5850 12:40:46.742228  best dqsien dly found for B1: ( 1,  2, 28)

 5851 12:40:46.745708  best DQS0 dly(MCK, UI, PI) = (1, 2, 28)

 5852 12:40:46.748846  best DQS1 dly(MCK, UI, PI) = (1, 2, 28)

 5853 12:40:46.748942  

 5854 12:40:46.752501  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5855 12:40:46.759135  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5856 12:40:46.759243  [Gating] SW calibration Done

 5857 12:40:46.759331  ==

 5858 12:40:46.762243  Dram Type= 6, Freq= 0, CH_1, rank 1

 5859 12:40:46.768784  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5860 12:40:46.768885  ==

 5861 12:40:46.768953  RX Vref Scan: 0

 5862 12:40:46.769015  

 5863 12:40:46.771919  RX Vref 0 -> 0, step: 1

 5864 12:40:46.772004  

 5865 12:40:46.775362  RX Delay -80 -> 252, step: 8

 5866 12:40:46.778613  iDelay=208, Bit 0, Center 103 (16 ~ 191) 176

 5867 12:40:46.782168  iDelay=208, Bit 1, Center 99 (16 ~ 183) 168

 5868 12:40:46.785129  iDelay=208, Bit 2, Center 87 (0 ~ 175) 176

 5869 12:40:46.792247  iDelay=208, Bit 3, Center 103 (16 ~ 191) 176

 5870 12:40:46.795750  iDelay=208, Bit 4, Center 103 (16 ~ 191) 176

 5871 12:40:46.798649  iDelay=208, Bit 5, Center 115 (24 ~ 207) 184

 5872 12:40:46.802114  iDelay=208, Bit 6, Center 107 (16 ~ 199) 184

 5873 12:40:46.805364  iDelay=208, Bit 7, Center 103 (16 ~ 191) 176

 5874 12:40:46.808797  iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184

 5875 12:40:46.815079  iDelay=208, Bit 9, Center 87 (0 ~ 175) 176

 5876 12:40:46.818315  iDelay=208, Bit 10, Center 99 (8 ~ 191) 184

 5877 12:40:46.821900  iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192

 5878 12:40:46.825163  iDelay=208, Bit 12, Center 107 (16 ~ 199) 184

 5879 12:40:46.828444  iDelay=208, Bit 13, Center 107 (16 ~ 199) 184

 5880 12:40:46.835037  iDelay=208, Bit 14, Center 103 (8 ~ 199) 192

 5881 12:40:46.838320  iDelay=208, Bit 15, Center 107 (16 ~ 199) 184

 5882 12:40:46.838407  ==

 5883 12:40:46.841826  Dram Type= 6, Freq= 0, CH_1, rank 1

 5884 12:40:46.845441  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5885 12:40:46.845526  ==

 5886 12:40:46.848555  DQS Delay:

 5887 12:40:46.848640  DQS0 = 0, DQS1 = 0

 5888 12:40:46.848706  DQM Delay:

 5889 12:40:46.852001  DQM0 = 102, DQM1 = 97

 5890 12:40:46.852086  DQ Delay:

 5891 12:40:46.855020  DQ0 =103, DQ1 =99, DQ2 =87, DQ3 =103

 5892 12:40:46.858216  DQ4 =103, DQ5 =115, DQ6 =107, DQ7 =103

 5893 12:40:46.861658  DQ8 =83, DQ9 =87, DQ10 =99, DQ11 =87

 5894 12:40:46.865103  DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107

 5895 12:40:46.868291  

 5896 12:40:46.868377  

 5897 12:40:46.868443  ==

 5898 12:40:46.871733  Dram Type= 6, Freq= 0, CH_1, rank 1

 5899 12:40:46.875000  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5900 12:40:46.875086  ==

 5901 12:40:46.875153  

 5902 12:40:46.875215  

 5903 12:40:46.878455  	TX Vref Scan disable

 5904 12:40:46.878547   == TX Byte 0 ==

 5905 12:40:46.884928  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5906 12:40:46.888138  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5907 12:40:46.888223   == TX Byte 1 ==

 5908 12:40:46.895177  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5909 12:40:46.898141  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5910 12:40:46.898259  ==

 5911 12:40:46.901546  Dram Type= 6, Freq= 0, CH_1, rank 1

 5912 12:40:46.905077  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5913 12:40:46.905162  ==

 5914 12:40:46.905228  

 5915 12:40:46.905288  

 5916 12:40:46.908063  	TX Vref Scan disable

 5917 12:40:46.911357   == TX Byte 0 ==

 5918 12:40:46.915127  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5919 12:40:46.918500  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5920 12:40:46.921451   == TX Byte 1 ==

 5921 12:40:46.924826  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5922 12:40:46.928145  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5923 12:40:46.928230  

 5924 12:40:46.931479  [DATLAT]

 5925 12:40:46.931563  Freq=933, CH1 RK1

 5926 12:40:46.931635  

 5927 12:40:46.935077  DATLAT Default: 0xb

 5928 12:40:46.935186  0, 0xFFFF, sum = 0

 5929 12:40:46.938288  1, 0xFFFF, sum = 0

 5930 12:40:46.938379  2, 0xFFFF, sum = 0

 5931 12:40:46.941278  3, 0xFFFF, sum = 0

 5932 12:40:46.941364  4, 0xFFFF, sum = 0

 5933 12:40:46.944787  5, 0xFFFF, sum = 0

 5934 12:40:46.944897  6, 0xFFFF, sum = 0

 5935 12:40:46.948602  7, 0xFFFF, sum = 0

 5936 12:40:46.948686  8, 0xFFFF, sum = 0

 5937 12:40:46.951274  9, 0xFFFF, sum = 0

 5938 12:40:46.951361  10, 0x0, sum = 1

 5939 12:40:46.954818  11, 0x0, sum = 2

 5940 12:40:46.954932  12, 0x0, sum = 3

 5941 12:40:46.958065  13, 0x0, sum = 4

 5942 12:40:46.958149  best_step = 11

 5943 12:40:46.958219  

 5944 12:40:46.958280  ==

 5945 12:40:46.961268  Dram Type= 6, Freq= 0, CH_1, rank 1

 5946 12:40:46.964600  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5947 12:40:46.968028  ==

 5948 12:40:46.968112  RX Vref Scan: 0

 5949 12:40:46.968181  

 5950 12:40:46.971475  RX Vref 0 -> 0, step: 1

 5951 12:40:46.971558  

 5952 12:40:46.974724  RX Delay -53 -> 252, step: 4

 5953 12:40:46.978048  iDelay=199, Bit 0, Center 110 (35 ~ 186) 152

 5954 12:40:46.981225  iDelay=199, Bit 1, Center 98 (19 ~ 178) 160

 5955 12:40:46.984793  iDelay=199, Bit 2, Center 94 (15 ~ 174) 160

 5956 12:40:46.991363  iDelay=199, Bit 3, Center 104 (23 ~ 186) 164

 5957 12:40:46.995089  iDelay=199, Bit 4, Center 106 (23 ~ 190) 168

 5958 12:40:46.998162  iDelay=199, Bit 5, Center 116 (35 ~ 198) 164

 5959 12:40:47.001410  iDelay=199, Bit 6, Center 112 (31 ~ 194) 164

 5960 12:40:47.004874  iDelay=199, Bit 7, Center 102 (23 ~ 182) 160

 5961 12:40:47.011724  iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172

 5962 12:40:47.015043  iDelay=199, Bit 9, Center 88 (3 ~ 174) 172

 5963 12:40:47.018301  iDelay=199, Bit 10, Center 98 (15 ~ 182) 168

 5964 12:40:47.021793  iDelay=199, Bit 11, Center 92 (7 ~ 178) 172

 5965 12:40:47.024881  iDelay=199, Bit 12, Center 106 (19 ~ 194) 176

 5966 12:40:47.028211  iDelay=199, Bit 13, Center 104 (19 ~ 190) 172

 5967 12:40:47.034718  iDelay=199, Bit 14, Center 106 (19 ~ 194) 176

 5968 12:40:47.038285  iDelay=199, Bit 15, Center 106 (19 ~ 194) 176

 5969 12:40:47.038375  ==

 5970 12:40:47.041333  Dram Type= 6, Freq= 0, CH_1, rank 1

 5971 12:40:47.044770  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5972 12:40:47.044859  ==

 5973 12:40:47.048074  DQS Delay:

 5974 12:40:47.048160  DQS0 = 0, DQS1 = 0

 5975 12:40:47.048226  DQM Delay:

 5976 12:40:47.051152  DQM0 = 105, DQM1 = 98

 5977 12:40:47.051237  DQ Delay:

 5978 12:40:47.054900  DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =104

 5979 12:40:47.057809  DQ4 =106, DQ5 =116, DQ6 =112, DQ7 =102

 5980 12:40:47.061330  DQ8 =84, DQ9 =88, DQ10 =98, DQ11 =92

 5981 12:40:47.067696  DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =106

 5982 12:40:47.067790  

 5983 12:40:47.067858  

 5984 12:40:47.074394  [DQSOSCAuto] RK1, (LSB)MR18= 0x1ffc, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 412 ps

 5985 12:40:47.077501  CH1 RK1: MR19=504, MR18=1FFC

 5986 12:40:47.084349  CH1_RK1: MR19=0x504, MR18=0x1FFC, DQSOSC=412, MR23=63, INC=63, DEC=42

 5987 12:40:47.087675  [RxdqsGatingPostProcess] freq 933

 5988 12:40:47.090810  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5989 12:40:47.094326  best DQS0 dly(2T, 0.5T) = (0, 10)

 5990 12:40:47.097320  best DQS1 dly(2T, 0.5T) = (0, 10)

 5991 12:40:47.100882  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5992 12:40:47.103904  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5993 12:40:47.107269  best DQS0 dly(2T, 0.5T) = (0, 10)

 5994 12:40:47.111166  best DQS1 dly(2T, 0.5T) = (0, 10)

 5995 12:40:47.113806  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5996 12:40:47.117455  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5997 12:40:47.120645  Pre-setting of DQS Precalculation

 5998 12:40:47.124052  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5999 12:40:47.133710  sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3

 6000 12:40:47.140369  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 6001 12:40:47.140462  

 6002 12:40:47.140557  

 6003 12:40:47.143986  [Calibration Summary] 1866 Mbps

 6004 12:40:47.144062  CH 0, Rank 0

 6005 12:40:47.147280  SW Impedance     : PASS

 6006 12:40:47.147357  DUTY Scan        : NO K

 6007 12:40:47.150365  ZQ Calibration   : PASS

 6008 12:40:47.153805  Jitter Meter     : NO K

 6009 12:40:47.153905  CBT Training     : PASS

 6010 12:40:47.156909  Write leveling   : PASS

 6011 12:40:47.160210  RX DQS gating    : PASS

 6012 12:40:47.160313  RX DQ/DQS(RDDQC) : PASS

 6013 12:40:47.163648  TX DQ/DQS        : PASS

 6014 12:40:47.166637  RX DATLAT        : PASS

 6015 12:40:47.166740  RX DQ/DQS(Engine): PASS

 6016 12:40:47.170121  TX OE            : NO K

 6017 12:40:47.170198  All Pass.

 6018 12:40:47.170263  

 6019 12:40:47.173730  CH 0, Rank 1

 6020 12:40:47.173829  SW Impedance     : PASS

 6021 12:40:47.177005  DUTY Scan        : NO K

 6022 12:40:47.180062  ZQ Calibration   : PASS

 6023 12:40:47.180165  Jitter Meter     : NO K

 6024 12:40:47.183794  CBT Training     : PASS

 6025 12:40:47.187095  Write leveling   : PASS

 6026 12:40:47.187197  RX DQS gating    : PASS

 6027 12:40:47.189812  RX DQ/DQS(RDDQC) : PASS

 6028 12:40:47.189916  TX DQ/DQS        : PASS

 6029 12:40:47.193578  RX DATLAT        : PASS

 6030 12:40:47.196582  RX DQ/DQS(Engine): PASS

 6031 12:40:47.196697  TX OE            : NO K

 6032 12:40:47.200132  All Pass.

 6033 12:40:47.200218  

 6034 12:40:47.200284  CH 1, Rank 0

 6035 12:40:47.203090  SW Impedance     : PASS

 6036 12:40:47.203176  DUTY Scan        : NO K

 6037 12:40:47.206993  ZQ Calibration   : PASS

 6038 12:40:47.209791  Jitter Meter     : NO K

 6039 12:40:47.209895  CBT Training     : PASS

 6040 12:40:47.213317  Write leveling   : PASS

 6041 12:40:47.216655  RX DQS gating    : PASS

 6042 12:40:47.216743  RX DQ/DQS(RDDQC) : PASS

 6043 12:40:47.220036  TX DQ/DQS        : PASS

 6044 12:40:47.223104  RX DATLAT        : PASS

 6045 12:40:47.223190  RX DQ/DQS(Engine): PASS

 6046 12:40:47.226615  TX OE            : NO K

 6047 12:40:47.226703  All Pass.

 6048 12:40:47.226787  

 6049 12:40:47.229721  CH 1, Rank 1

 6050 12:40:47.229830  SW Impedance     : PASS

 6051 12:40:47.233221  DUTY Scan        : NO K

 6052 12:40:47.236413  ZQ Calibration   : PASS

 6053 12:40:47.236499  Jitter Meter     : NO K

 6054 12:40:47.239533  CBT Training     : PASS

 6055 12:40:47.243177  Write leveling   : PASS

 6056 12:40:47.243262  RX DQS gating    : PASS

 6057 12:40:47.246273  RX DQ/DQS(RDDQC) : PASS

 6058 12:40:47.249339  TX DQ/DQS        : PASS

 6059 12:40:47.249424  RX DATLAT        : PASS

 6060 12:40:47.252781  RX DQ/DQS(Engine): PASS

 6061 12:40:47.256330  TX OE            : NO K

 6062 12:40:47.256417  All Pass.

 6063 12:40:47.256502  

 6064 12:40:47.256601  DramC Write-DBI off

 6065 12:40:47.259417  	PER_BANK_REFRESH: Hybrid Mode

 6066 12:40:47.262690  TX_TRACKING: ON

 6067 12:40:47.269190  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0

 6068 12:40:47.273061  [FAST_K] Save calibration result to emmc

 6069 12:40:47.279111  dramc_set_vcore_voltage set vcore to 650000

 6070 12:40:47.279217  Read voltage for 400, 6

 6071 12:40:47.282443  Vio18 = 0

 6072 12:40:47.282534  Vcore = 650000

 6073 12:40:47.282619  Vdram = 0

 6074 12:40:47.282699  Vddq = 0

 6075 12:40:47.285770  Vmddr = 0

 6076 12:40:47.289107  [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0

 6077 12:40:47.295839  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 6078 12:40:47.299329  MEM_TYPE=3, freq_sel=20

 6079 12:40:47.299419  sv_algorithm_assistance_LP4_800 

 6080 12:40:47.305702  ============ PULL DRAM RESETB DOWN ============

 6081 12:40:47.309537  ========== PULL DRAM RESETB DOWN end =========

 6082 12:40:47.312526  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6083 12:40:47.316019  =================================== 

 6084 12:40:47.319696  LPDDR4 DRAM CONFIGURATION

 6085 12:40:47.322173  =================================== 

 6086 12:40:47.326233  EX_ROW_EN[0]    = 0x0

 6087 12:40:47.326319  EX_ROW_EN[1]    = 0x0

 6088 12:40:47.328693  LP4Y_EN      = 0x0

 6089 12:40:47.328777  WORK_FSP     = 0x0

 6090 12:40:47.332076  WL           = 0x2

 6091 12:40:47.332161  RL           = 0x2

 6092 12:40:47.335605  BL           = 0x2

 6093 12:40:47.335689  RPST         = 0x0

 6094 12:40:47.338698  RD_PRE       = 0x0

 6095 12:40:47.338783  WR_PRE       = 0x1

 6096 12:40:47.341927  WR_PST       = 0x0

 6097 12:40:47.342055  DBI_WR       = 0x0

 6098 12:40:47.345485  DBI_RD       = 0x0

 6099 12:40:47.348708  OTF          = 0x1

 6100 12:40:47.352068  =================================== 

 6101 12:40:47.355559  =================================== 

 6102 12:40:47.355647  ANA top config

 6103 12:40:47.358737  =================================== 

 6104 12:40:47.361945  DLL_ASYNC_EN            =  0

 6105 12:40:47.362043  ALL_SLAVE_EN            =  1

 6106 12:40:47.365238  NEW_RANK_MODE           =  1

 6107 12:40:47.368837  DLL_IDLE_MODE           =  1

 6108 12:40:47.371868  LP45_APHY_COMB_EN       =  1

 6109 12:40:47.375453  TX_ODT_DIS              =  1

 6110 12:40:47.375542  NEW_8X_MODE             =  1

 6111 12:40:47.378756  =================================== 

 6112 12:40:47.381849  =================================== 

 6113 12:40:47.385483  data_rate                  =  800

 6114 12:40:47.388667  CKR                        = 1

 6115 12:40:47.392182  DQ_P2S_RATIO               = 4

 6116 12:40:47.395749  =================================== 

 6117 12:40:47.398608  CA_P2S_RATIO               = 4

 6118 12:40:47.401842  DQ_CA_OPEN                 = 0

 6119 12:40:47.401991  DQ_SEMI_OPEN               = 1

 6120 12:40:47.405358  CA_SEMI_OPEN               = 1

 6121 12:40:47.408751  CA_FULL_RATE               = 0

 6122 12:40:47.411813  DQ_CKDIV4_EN               = 0

 6123 12:40:47.415399  CA_CKDIV4_EN               = 1

 6124 12:40:47.415486  CA_PREDIV_EN               = 0

 6125 12:40:47.418800  PH8_DLY                    = 0

 6126 12:40:47.421879  SEMI_OPEN_CA_PICK_MCK_RATIO= 4

 6127 12:40:47.425519  DQ_AAMCK_DIV               = 0

 6128 12:40:47.428475  CA_AAMCK_DIV               = 0

 6129 12:40:47.431839  CA_ADMCK_DIV               = 4

 6130 12:40:47.431923  DQ_TRACK_CA_EN             = 0

 6131 12:40:47.435260  CA_PICK                    = 800

 6132 12:40:47.438516  CA_MCKIO                   = 400

 6133 12:40:47.441817  MCKIO_SEMI                 = 400

 6134 12:40:47.445518  PLL_FREQ                   = 3016

 6135 12:40:47.449037  DQ_UI_PI_RATIO             = 32

 6136 12:40:47.452018  CA_UI_PI_RATIO             = 32

 6137 12:40:47.455301  =================================== 

 6138 12:40:47.458191  =================================== 

 6139 12:40:47.458280  memory_type:LPDDR4         

 6140 12:40:47.461783  GP_NUM     : 10       

 6141 12:40:47.464972  SRAM_EN    : 1       

 6142 12:40:47.465066  MD32_EN    : 0       

 6143 12:40:47.468598  =================================== 

 6144 12:40:47.471858  [ANA_INIT] >>>>>>>>>>>>>> 

 6145 12:40:47.475002  <<<<<< [CONFIGURE PHASE]: ANA_TX

 6146 12:40:47.478319  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 6147 12:40:47.481741  =================================== 

 6148 12:40:47.484767  data_rate = 800,PCW = 0X7400

 6149 12:40:47.488048  =================================== 

 6150 12:40:47.491641  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 6151 12:40:47.495163  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6152 12:40:47.508184  WARN: tr->DQ_AAMCK_DIV=  0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6153 12:40:47.511520  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 6154 12:40:47.515121  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 6155 12:40:47.518193  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 6156 12:40:47.521601  [ANA_INIT] flow start 

 6157 12:40:47.524943  [ANA_INIT] PLL >>>>>>>> 

 6158 12:40:47.525048  [ANA_INIT] PLL <<<<<<<< 

 6159 12:40:47.528070  [ANA_INIT] MIDPI >>>>>>>> 

 6160 12:40:47.531640  [ANA_INIT] MIDPI <<<<<<<< 

 6161 12:40:47.531719  [ANA_INIT] DLL >>>>>>>> 

 6162 12:40:47.534765  [ANA_INIT] flow end 

 6163 12:40:47.537918  ============ LP4 DIFF to SE enter ============

 6164 12:40:47.541336  ============ LP4 DIFF to SE exit  ============

 6165 12:40:47.544592  [ANA_INIT] <<<<<<<<<<<<< 

 6166 12:40:47.548037  [Flow] Enable top DCM control >>>>> 

 6167 12:40:47.551359  [Flow] Enable top DCM control <<<<< 

 6168 12:40:47.554927  Enable DLL master slave shuffle 

 6169 12:40:47.561236  ============================================================== 

 6170 12:40:47.561325  Gating Mode config

 6171 12:40:47.567948  ============================================================== 

 6172 12:40:47.568043  Config description: 

 6173 12:40:47.577880  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 6174 12:40:47.584777  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 6175 12:40:47.591250  SELPH_MODE            0: By rank         1: By Phase 

 6176 12:40:47.594798  ============================================================== 

 6177 12:40:47.598034  GAT_TRACK_EN                 =  0

 6178 12:40:47.601881  RX_GATING_MODE               =  2

 6179 12:40:47.604690  RX_GATING_TRACK_MODE         =  2

 6180 12:40:47.607735  SELPH_MODE                   =  1

 6181 12:40:47.611467  PICG_EARLY_EN                =  1

 6182 12:40:47.614432  VALID_LAT_VALUE              =  1

 6183 12:40:47.621499  ============================================================== 

 6184 12:40:47.624460  Enter into Gating configuration >>>> 

 6185 12:40:47.627890  Exit from Gating configuration <<<< 

 6186 12:40:47.627978  Enter into  DVFS_PRE_config >>>>> 

 6187 12:40:47.641356  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 6188 12:40:47.644320  Exit from  DVFS_PRE_config <<<<< 

 6189 12:40:47.647748  Enter into PICG configuration >>>> 

 6190 12:40:47.651087  Exit from PICG configuration <<<< 

 6191 12:40:47.651177  [RX_INPUT] configuration >>>>> 

 6192 12:40:47.654264  [RX_INPUT] configuration <<<<< 

 6193 12:40:47.660763  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 6194 12:40:47.667578  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 6195 12:40:47.671007  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 6196 12:40:47.677801  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 6197 12:40:47.684319  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 6198 12:40:47.691116  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 6199 12:40:47.694169  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 6200 12:40:47.697572  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 6201 12:40:47.704041  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 6202 12:40:47.707534  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 6203 12:40:47.710774  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 6204 12:40:47.714002  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6205 12:40:47.717340  =================================== 

 6206 12:40:47.720900  LPDDR4 DRAM CONFIGURATION

 6207 12:40:47.724666  =================================== 

 6208 12:40:47.727235  EX_ROW_EN[0]    = 0x0

 6209 12:40:47.727331  EX_ROW_EN[1]    = 0x0

 6210 12:40:47.730489  LP4Y_EN      = 0x0

 6211 12:40:47.730573  WORK_FSP     = 0x0

 6212 12:40:47.733932  WL           = 0x2

 6213 12:40:47.734077  RL           = 0x2

 6214 12:40:47.737462  BL           = 0x2

 6215 12:40:47.737547  RPST         = 0x0

 6216 12:40:47.740499  RD_PRE       = 0x0

 6217 12:40:47.740583  WR_PRE       = 0x1

 6218 12:40:47.743881  WR_PST       = 0x0

 6219 12:40:47.747175  DBI_WR       = 0x0

 6220 12:40:47.747260  DBI_RD       = 0x0

 6221 12:40:47.750787  OTF          = 0x1

 6222 12:40:47.753897  =================================== 

 6223 12:40:47.757675  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 6224 12:40:47.760943  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 6225 12:40:47.764163  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6226 12:40:47.767492  =================================== 

 6227 12:40:47.770742  LPDDR4 DRAM CONFIGURATION

 6228 12:40:47.773864  =================================== 

 6229 12:40:47.777450  EX_ROW_EN[0]    = 0x10

 6230 12:40:47.777537  EX_ROW_EN[1]    = 0x0

 6231 12:40:47.780626  LP4Y_EN      = 0x0

 6232 12:40:47.780712  WORK_FSP     = 0x0

 6233 12:40:47.783949  WL           = 0x2

 6234 12:40:47.784034  RL           = 0x2

 6235 12:40:47.787229  BL           = 0x2

 6236 12:40:47.787314  RPST         = 0x0

 6237 12:40:47.790687  RD_PRE       = 0x0

 6238 12:40:47.790776  WR_PRE       = 0x1

 6239 12:40:47.794052  WR_PST       = 0x0

 6240 12:40:47.794137  DBI_WR       = 0x0

 6241 12:40:47.797523  DBI_RD       = 0x0

 6242 12:40:47.797607  OTF          = 0x1

 6243 12:40:47.801614  =================================== 

 6244 12:40:47.807469  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 6245 12:40:47.812119  nWR fixed to 30

 6246 12:40:47.815487  [ModeRegInit_LP4] CH0 RK0

 6247 12:40:47.815576  [ModeRegInit_LP4] CH0 RK1

 6248 12:40:47.818499  [ModeRegInit_LP4] CH1 RK0

 6249 12:40:47.822190  [ModeRegInit_LP4] CH1 RK1

 6250 12:40:47.822276  match AC timing 19

 6251 12:40:47.828941  dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1

 6252 12:40:47.832385  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 6253 12:40:47.835362  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 6254 12:40:47.842131  [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17

 6255 12:40:47.845171  [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)

 6256 12:40:47.845275  ==

 6257 12:40:47.848644  Dram Type= 6, Freq= 0, CH_0, rank 0

 6258 12:40:47.851890  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6259 12:40:47.851977  ==

 6260 12:40:47.859070  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6261 12:40:47.865274  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6262 12:40:47.868650  [CA 0] Center 36 (8~64) winsize 57

 6263 12:40:47.871950  [CA 1] Center 36 (8~64) winsize 57

 6264 12:40:47.874998  [CA 2] Center 36 (8~64) winsize 57

 6265 12:40:47.875084  [CA 3] Center 36 (8~64) winsize 57

 6266 12:40:47.878669  [CA 4] Center 36 (8~64) winsize 57

 6267 12:40:47.881800  [CA 5] Center 36 (8~64) winsize 57

 6268 12:40:47.881928  

 6269 12:40:47.888277  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6270 12:40:47.888363  

 6271 12:40:47.892067  [CATrainingPosCal] consider 1 rank data

 6272 12:40:47.894977  u2DelayCellTimex100 = 270/100 ps

 6273 12:40:47.898898  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6274 12:40:47.901558  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6275 12:40:47.905120  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6276 12:40:47.908666  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6277 12:40:47.911583  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6278 12:40:47.915005  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6279 12:40:47.915091  

 6280 12:40:47.918561  CA PerBit enable=1, Macro0, CA PI delay=36

 6281 12:40:47.918647  

 6282 12:40:47.921917  [CBTSetCACLKResult] CA Dly = 36

 6283 12:40:47.925163  CS Dly: 1 (0~32)

 6284 12:40:47.925248  ==

 6285 12:40:47.928321  Dram Type= 6, Freq= 0, CH_0, rank 1

 6286 12:40:47.931803  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6287 12:40:47.931894  ==

 6288 12:40:47.938437  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6289 12:40:47.941450  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33

 6290 12:40:47.944878  [CA 0] Center 36 (8~64) winsize 57

 6291 12:40:47.948349  [CA 1] Center 36 (8~64) winsize 57

 6292 12:40:47.951803  [CA 2] Center 36 (8~64) winsize 57

 6293 12:40:47.954965  [CA 3] Center 36 (8~64) winsize 57

 6294 12:40:47.958279  [CA 4] Center 36 (8~64) winsize 57

 6295 12:40:47.961303  [CA 5] Center 36 (8~64) winsize 57

 6296 12:40:47.961414  

 6297 12:40:47.965051  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 6298 12:40:47.965163  

 6299 12:40:47.968062  [CATrainingPosCal] consider 2 rank data

 6300 12:40:47.971554  u2DelayCellTimex100 = 270/100 ps

 6301 12:40:47.974998  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6302 12:40:47.978316  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6303 12:40:47.981586  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6304 12:40:47.988216  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6305 12:40:47.991232  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6306 12:40:47.994538  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6307 12:40:47.994651  

 6308 12:40:47.998144  CA PerBit enable=1, Macro0, CA PI delay=36

 6309 12:40:47.998257  

 6310 12:40:48.001798  [CBTSetCACLKResult] CA Dly = 36

 6311 12:40:48.001909  CS Dly: 1 (0~32)

 6312 12:40:48.002054  

 6313 12:40:48.004447  ----->DramcWriteLeveling(PI) begin...

 6314 12:40:48.004562  ==

 6315 12:40:48.008197  Dram Type= 6, Freq= 0, CH_0, rank 0

 6316 12:40:48.014570  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6317 12:40:48.014685  ==

 6318 12:40:48.018452  Write leveling (Byte 0): 40 => 8

 6319 12:40:48.021370  Write leveling (Byte 1): 32 => 0

 6320 12:40:48.021481  DramcWriteLeveling(PI) end<-----

 6321 12:40:48.021578  

 6322 12:40:48.024902  ==

 6323 12:40:48.028486  Dram Type= 6, Freq= 0, CH_0, rank 0

 6324 12:40:48.031343  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6325 12:40:48.031453  ==

 6326 12:40:48.034672  [Gating] SW mode calibration

 6327 12:40:48.041327  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6328 12:40:48.044643  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6329 12:40:48.051159   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6330 12:40:48.054313   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6331 12:40:48.058119   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6332 12:40:48.064508   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6333 12:40:48.067929   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6334 12:40:48.071117   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6335 12:40:48.077732   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6336 12:40:48.081014   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6337 12:40:48.084663   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6338 12:40:48.087543  Total UI for P1: 0, mck2ui 16

 6339 12:40:48.091442  best dqsien dly found for B0: ( 0, 14, 24)

 6340 12:40:48.094437  Total UI for P1: 0, mck2ui 16

 6341 12:40:48.097608  best dqsien dly found for B1: ( 0, 14, 24)

 6342 12:40:48.100904  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6343 12:40:48.104470  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6344 12:40:48.104581  

 6345 12:40:48.110930  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6346 12:40:48.114167  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6347 12:40:48.114278  [Gating] SW calibration Done

 6348 12:40:48.117428  ==

 6349 12:40:48.120878  Dram Type= 6, Freq= 0, CH_0, rank 0

 6350 12:40:48.124849  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6351 12:40:48.124960  ==

 6352 12:40:48.125056  RX Vref Scan: 0

 6353 12:40:48.125152  

 6354 12:40:48.127630  RX Vref 0 -> 0, step: 1

 6355 12:40:48.127738  

 6356 12:40:48.131306  RX Delay -410 -> 252, step: 16

 6357 12:40:48.134172  iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464

 6358 12:40:48.137883  iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480

 6359 12:40:48.144372  iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464

 6360 12:40:48.147503  iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480

 6361 12:40:48.151221  iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480

 6362 12:40:48.153893  iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480

 6363 12:40:48.160693  iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480

 6364 12:40:48.163838  iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464

 6365 12:40:48.167275  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6366 12:40:48.170516  iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480

 6367 12:40:48.177307  iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480

 6368 12:40:48.180807  iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464

 6369 12:40:48.184435  iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480

 6370 12:40:48.190553  iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480

 6371 12:40:48.194055  iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464

 6372 12:40:48.197356  iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480

 6373 12:40:48.197458  ==

 6374 12:40:48.200556  Dram Type= 6, Freq= 0, CH_0, rank 0

 6375 12:40:48.203910  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6376 12:40:48.203994  ==

 6377 12:40:48.207446  DQS Delay:

 6378 12:40:48.207528  DQS0 = 27, DQS1 = 43

 6379 12:40:48.210490  DQM Delay:

 6380 12:40:48.210571  DQM0 = 11, DQM1 = 13

 6381 12:40:48.213927  DQ Delay:

 6382 12:40:48.214046  DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =0

 6383 12:40:48.217392  DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24

 6384 12:40:48.220929  DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8

 6385 12:40:48.224268  DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16

 6386 12:40:48.224350  

 6387 12:40:48.224413  

 6388 12:40:48.224472  ==

 6389 12:40:48.227942  Dram Type= 6, Freq= 0, CH_0, rank 0

 6390 12:40:48.233903  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6391 12:40:48.234020  ==

 6392 12:40:48.234084  

 6393 12:40:48.234142  

 6394 12:40:48.234199  	TX Vref Scan disable

 6395 12:40:48.237300   == TX Byte 0 ==

 6396 12:40:48.240261  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6397 12:40:48.244086  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6398 12:40:48.247604   == TX Byte 1 ==

 6399 12:40:48.250729  Update DQ  dly =572 (4 ,1, 28)  DQ  OEN =(3 ,2)

 6400 12:40:48.253918  Update DQM dly =572 (4 ,1, 28)  DQM OEN =(3 ,2)

 6401 12:40:48.257185  ==

 6402 12:40:48.257266  Dram Type= 6, Freq= 0, CH_0, rank 0

 6403 12:40:48.263929  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6404 12:40:48.264011  ==

 6405 12:40:48.264074  

 6406 12:40:48.264133  

 6407 12:40:48.267280  	TX Vref Scan disable

 6408 12:40:48.267362   == TX Byte 0 ==

 6409 12:40:48.270736  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6410 12:40:48.273748  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6411 12:40:48.277133   == TX Byte 1 ==

 6412 12:40:48.280430  Update DQ  dly =572 (4 ,1, 28)  DQ  OEN =(3 ,2)

 6413 12:40:48.287618  Update DQM dly =572 (4 ,1, 28)  DQM OEN =(3 ,2)

 6414 12:40:48.287701  

 6415 12:40:48.287764  [DATLAT]

 6416 12:40:48.287823  Freq=400, CH0 RK0

 6417 12:40:48.287881  

 6418 12:40:48.290571  DATLAT Default: 0xf

 6419 12:40:48.290652  0, 0xFFFF, sum = 0

 6420 12:40:48.293605  1, 0xFFFF, sum = 0

 6421 12:40:48.293690  2, 0xFFFF, sum = 0

 6422 12:40:48.296911  3, 0xFFFF, sum = 0

 6423 12:40:48.300617  4, 0xFFFF, sum = 0

 6424 12:40:48.300702  5, 0xFFFF, sum = 0

 6425 12:40:48.303906  6, 0xFFFF, sum = 0

 6426 12:40:48.303991  7, 0xFFFF, sum = 0

 6427 12:40:48.306970  8, 0xFFFF, sum = 0

 6428 12:40:48.307055  9, 0xFFFF, sum = 0

 6429 12:40:48.310189  10, 0xFFFF, sum = 0

 6430 12:40:48.310275  11, 0xFFFF, sum = 0

 6431 12:40:48.313776  12, 0xFFFF, sum = 0

 6432 12:40:48.313862  13, 0x0, sum = 1

 6433 12:40:48.316992  14, 0x0, sum = 2

 6434 12:40:48.317077  15, 0x0, sum = 3

 6435 12:40:48.320427  16, 0x0, sum = 4

 6436 12:40:48.320511  best_step = 14

 6437 12:40:48.320576  

 6438 12:40:48.320637  ==

 6439 12:40:48.323558  Dram Type= 6, Freq= 0, CH_0, rank 0

 6440 12:40:48.327023  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6441 12:40:48.327108  ==

 6442 12:40:48.330259  RX Vref Scan: 1

 6443 12:40:48.330342  

 6444 12:40:48.333447  RX Vref 0 -> 0, step: 1

 6445 12:40:48.333530  

 6446 12:40:48.333596  RX Delay -327 -> 252, step: 8

 6447 12:40:48.337017  

 6448 12:40:48.337100  Set Vref, RX VrefLevel [Byte0]: 59

 6449 12:40:48.340422                           [Byte1]: 50

 6450 12:40:48.345662  

 6451 12:40:48.345744  Final RX Vref Byte 0 = 59 to rank0

 6452 12:40:48.349302  Final RX Vref Byte 1 = 50 to rank0

 6453 12:40:48.352944  Final RX Vref Byte 0 = 59 to rank1

 6454 12:40:48.355631  Final RX Vref Byte 1 = 50 to rank1==

 6455 12:40:48.358994  Dram Type= 6, Freq= 0, CH_0, rank 0

 6456 12:40:48.365781  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6457 12:40:48.365993  ==

 6458 12:40:48.366080  DQS Delay:

 6459 12:40:48.369134  DQS0 = 28, DQS1 = 48

 6460 12:40:48.369218  DQM Delay:

 6461 12:40:48.369283  DQM0 = 12, DQM1 = 15

 6462 12:40:48.372507  DQ Delay:

 6463 12:40:48.375992  DQ0 =12, DQ1 =8, DQ2 =8, DQ3 =8

 6464 12:40:48.376076  DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =20

 6465 12:40:48.379044  DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12

 6466 12:40:48.382384  DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24

 6467 12:40:48.382467  

 6468 12:40:48.382532  

 6469 12:40:48.392476  [DQSOSCAuto] RK0, (LSB)MR18= 0xa9a1, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps

 6470 12:40:48.396143  CH0 RK0: MR19=C0C, MR18=A9A1

 6471 12:40:48.402429  CH0_RK0: MR19=0xC0C, MR18=0xA9A1, DQSOSC=388, MR23=63, INC=392, DEC=261

 6472 12:40:48.402513  ==

 6473 12:40:48.405871  Dram Type= 6, Freq= 0, CH_0, rank 1

 6474 12:40:48.408967  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6475 12:40:48.409050  ==

 6476 12:40:48.412415  [Gating] SW mode calibration

 6477 12:40:48.419062  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6478 12:40:48.425895  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6479 12:40:48.428832   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6480 12:40:48.432337   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6481 12:40:48.439077   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6482 12:40:48.442239   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6483 12:40:48.445375   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6484 12:40:48.448716   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6485 12:40:48.455618   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6486 12:40:48.458922   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6487 12:40:48.462133   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6488 12:40:48.465440  Total UI for P1: 0, mck2ui 16

 6489 12:40:48.468766  best dqsien dly found for B0: ( 0, 14, 24)

 6490 12:40:48.471976  Total UI for P1: 0, mck2ui 16

 6491 12:40:48.475440  best dqsien dly found for B1: ( 0, 14, 24)

 6492 12:40:48.478657  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6493 12:40:48.481964  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6494 12:40:48.485415  

 6495 12:40:48.488840  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6496 12:40:48.492262  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6497 12:40:48.495247  [Gating] SW calibration Done

 6498 12:40:48.495372  ==

 6499 12:40:48.499068  Dram Type= 6, Freq= 0, CH_0, rank 1

 6500 12:40:48.501795  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6501 12:40:48.501881  ==

 6502 12:40:48.501989  RX Vref Scan: 0

 6503 12:40:48.505143  

 6504 12:40:48.505227  RX Vref 0 -> 0, step: 1

 6505 12:40:48.505293  

 6506 12:40:48.508732  RX Delay -410 -> 252, step: 16

 6507 12:40:48.511839  iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464

 6508 12:40:48.518370  iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464

 6509 12:40:48.522250  iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464

 6510 12:40:48.525719  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6511 12:40:48.528599  iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464

 6512 12:40:48.535309  iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480

 6513 12:40:48.538639  iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480

 6514 12:40:48.541743  iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480

 6515 12:40:48.545238  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6516 12:40:48.551861  iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480

 6517 12:40:48.555188  iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480

 6518 12:40:48.558512  iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464

 6519 12:40:48.561826  iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480

 6520 12:40:48.568835  iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464

 6521 12:40:48.572055  iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464

 6522 12:40:48.575429  iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464

 6523 12:40:48.575514  ==

 6524 12:40:48.578501  Dram Type= 6, Freq= 0, CH_0, rank 1

 6525 12:40:48.581879  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6526 12:40:48.585359  ==

 6527 12:40:48.585444  DQS Delay:

 6528 12:40:48.585511  DQS0 = 27, DQS1 = 43

 6529 12:40:48.588665  DQM Delay:

 6530 12:40:48.588749  DQM0 = 9, DQM1 = 15

 6531 12:40:48.591744  DQ Delay:

 6532 12:40:48.591829  DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8

 6533 12:40:48.595121  DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16

 6534 12:40:48.598649  DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8

 6535 12:40:48.601724  DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24

 6536 12:40:48.601808  

 6537 12:40:48.601874  

 6538 12:40:48.601935  ==

 6539 12:40:48.605080  Dram Type= 6, Freq= 0, CH_0, rank 1

 6540 12:40:48.611612  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6541 12:40:48.611698  ==

 6542 12:40:48.611765  

 6543 12:40:48.611825  

 6544 12:40:48.611884  	TX Vref Scan disable

 6545 12:40:48.614840   == TX Byte 0 ==

 6546 12:40:48.618362  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6547 12:40:48.621930  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6548 12:40:48.625089   == TX Byte 1 ==

 6549 12:40:48.628513  Update DQ  dly =577 (4 ,2, 1)  DQ  OEN =(3 ,3)

 6550 12:40:48.631551  Update DQM dly =577 (4 ,2, 1)  DQM OEN =(3 ,3)

 6551 12:40:48.634762  ==

 6552 12:40:48.634851  Dram Type= 6, Freq= 0, CH_0, rank 1

 6553 12:40:48.641636  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6554 12:40:48.641722  ==

 6555 12:40:48.641789  

 6556 12:40:48.641851  

 6557 12:40:48.644717  	TX Vref Scan disable

 6558 12:40:48.644801   == TX Byte 0 ==

 6559 12:40:48.648026  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6560 12:40:48.651340  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6561 12:40:48.655022   == TX Byte 1 ==

 6562 12:40:48.658140  Update DQ  dly =577 (4 ,2, 1)  DQ  OEN =(3 ,3)

 6563 12:40:48.661661  Update DQM dly =577 (4 ,2, 1)  DQM OEN =(3 ,3)

 6564 12:40:48.665336  

 6565 12:40:48.665421  [DATLAT]

 6566 12:40:48.665487  Freq=400, CH0 RK1

 6567 12:40:48.665550  

 6568 12:40:48.668124  DATLAT Default: 0xe

 6569 12:40:48.668209  0, 0xFFFF, sum = 0

 6570 12:40:48.672264  1, 0xFFFF, sum = 0

 6571 12:40:48.672350  2, 0xFFFF, sum = 0

 6572 12:40:48.674658  3, 0xFFFF, sum = 0

 6573 12:40:48.674744  4, 0xFFFF, sum = 0

 6574 12:40:48.678087  5, 0xFFFF, sum = 0

 6575 12:40:48.678173  6, 0xFFFF, sum = 0

 6576 12:40:48.681280  7, 0xFFFF, sum = 0

 6577 12:40:48.684811  8, 0xFFFF, sum = 0

 6578 12:40:48.684897  9, 0xFFFF, sum = 0

 6579 12:40:48.687962  10, 0xFFFF, sum = 0

 6580 12:40:48.688047  11, 0xFFFF, sum = 0

 6581 12:40:48.691239  12, 0xFFFF, sum = 0

 6582 12:40:48.691352  13, 0x0, sum = 1

 6583 12:40:48.694627  14, 0x0, sum = 2

 6584 12:40:48.694712  15, 0x0, sum = 3

 6585 12:40:48.698138  16, 0x0, sum = 4

 6586 12:40:48.698223  best_step = 14

 6587 12:40:48.698290  

 6588 12:40:48.698349  ==

 6589 12:40:48.701654  Dram Type= 6, Freq= 0, CH_0, rank 1

 6590 12:40:48.704693  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6591 12:40:48.704778  ==

 6592 12:40:48.707994  RX Vref Scan: 0

 6593 12:40:48.708077  

 6594 12:40:48.711232  RX Vref 0 -> 0, step: 1

 6595 12:40:48.711355  

 6596 12:40:48.711421  RX Delay -327 -> 252, step: 8

 6597 12:40:48.719851  iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456

 6598 12:40:48.723213  iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448

 6599 12:40:48.726719  iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448

 6600 12:40:48.729738  iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440

 6601 12:40:48.736614  iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448

 6602 12:40:48.739998  iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456

 6603 12:40:48.743165  iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448

 6604 12:40:48.746856  iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456

 6605 12:40:48.753046  iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456

 6606 12:40:48.756520  iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456

 6607 12:40:48.759815  iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456

 6608 12:40:48.763185  iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448

 6609 12:40:48.770266  iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448

 6610 12:40:48.773076  iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448

 6611 12:40:48.776622  iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456

 6612 12:40:48.783309  iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440

 6613 12:40:48.783393  ==

 6614 12:40:48.786763  Dram Type= 6, Freq= 0, CH_0, rank 1

 6615 12:40:48.790042  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6616 12:40:48.790126  ==

 6617 12:40:48.790193  DQS Delay:

 6618 12:40:48.793107  DQS0 = 28, DQS1 = 44

 6619 12:40:48.793191  DQM Delay:

 6620 12:40:48.796900  DQM0 = 10, DQM1 = 15

 6621 12:40:48.796984  DQ Delay:

 6622 12:40:48.799983  DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8

 6623 12:40:48.802996  DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16

 6624 12:40:48.806198  DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12

 6625 12:40:48.809979  DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24

 6626 12:40:48.810063  

 6627 12:40:48.810129  

 6628 12:40:48.816517  [DQSOSCAuto] RK1, (LSB)MR18= 0xc072, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps

 6629 12:40:48.819695  CH0 RK1: MR19=C0C, MR18=C072

 6630 12:40:48.826392  CH0_RK1: MR19=0xC0C, MR18=0xC072, DQSOSC=386, MR23=63, INC=396, DEC=264

 6631 12:40:48.829456  [RxdqsGatingPostProcess] freq 400

 6632 12:40:48.833426  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 6633 12:40:48.836232  best DQS0 dly(2T, 0.5T) = (0, 10)

 6634 12:40:48.839844  best DQS1 dly(2T, 0.5T) = (0, 10)

 6635 12:40:48.843253  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6636 12:40:48.846199  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6637 12:40:48.849628  best DQS0 dly(2T, 0.5T) = (0, 10)

 6638 12:40:48.853154  best DQS1 dly(2T, 0.5T) = (0, 10)

 6639 12:40:48.856262  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6640 12:40:48.859835  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6641 12:40:48.863112  Pre-setting of DQS Precalculation

 6642 12:40:48.866293  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 6643 12:40:48.869528  ==

 6644 12:40:48.869612  Dram Type= 6, Freq= 0, CH_1, rank 0

 6645 12:40:48.876586  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6646 12:40:48.876672  ==

 6647 12:40:48.879754  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6648 12:40:48.886355  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33

 6649 12:40:48.889588  [CA 0] Center 36 (8~64) winsize 57

 6650 12:40:48.892816  [CA 1] Center 36 (8~64) winsize 57

 6651 12:40:48.896291  [CA 2] Center 36 (8~64) winsize 57

 6652 12:40:48.899382  [CA 3] Center 36 (8~64) winsize 57

 6653 12:40:48.902728  [CA 4] Center 36 (8~64) winsize 57

 6654 12:40:48.906064  [CA 5] Center 36 (8~64) winsize 57

 6655 12:40:48.906148  

 6656 12:40:48.909676  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 6657 12:40:48.909761  

 6658 12:40:48.912757  [CATrainingPosCal] consider 1 rank data

 6659 12:40:48.916598  u2DelayCellTimex100 = 270/100 ps

 6660 12:40:48.919749  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6661 12:40:48.923156  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6662 12:40:48.926061  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6663 12:40:48.929569  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6664 12:40:48.932798  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6665 12:40:48.939775  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6666 12:40:48.939860  

 6667 12:40:48.942737  CA PerBit enable=1, Macro0, CA PI delay=36

 6668 12:40:48.942821  

 6669 12:40:48.946181  [CBTSetCACLKResult] CA Dly = 36

 6670 12:40:48.946265  CS Dly: 1 (0~32)

 6671 12:40:48.946332  ==

 6672 12:40:48.949556  Dram Type= 6, Freq= 0, CH_1, rank 1

 6673 12:40:48.952991  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6674 12:40:48.955892  ==

 6675 12:40:48.959310  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6676 12:40:48.966067  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6677 12:40:48.969691  [CA 0] Center 36 (8~64) winsize 57

 6678 12:40:48.972822  [CA 1] Center 36 (8~64) winsize 57

 6679 12:40:48.975933  [CA 2] Center 36 (8~64) winsize 57

 6680 12:40:48.979162  [CA 3] Center 36 (8~64) winsize 57

 6681 12:40:48.982493  [CA 4] Center 36 (8~64) winsize 57

 6682 12:40:48.986147  [CA 5] Center 36 (8~64) winsize 57

 6683 12:40:48.986231  

 6684 12:40:48.989124  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6685 12:40:48.989208  

 6686 12:40:48.992439  [CATrainingPosCal] consider 2 rank data

 6687 12:40:48.995868  u2DelayCellTimex100 = 270/100 ps

 6688 12:40:48.999338  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6689 12:40:49.002447  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6690 12:40:49.006229  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6691 12:40:49.009251  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6692 12:40:49.012422  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6693 12:40:49.015667  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6694 12:40:49.015752  

 6695 12:40:49.019314  CA PerBit enable=1, Macro0, CA PI delay=36

 6696 12:40:49.022345  

 6697 12:40:49.022429  [CBTSetCACLKResult] CA Dly = 36

 6698 12:40:49.025531  CS Dly: 1 (0~32)

 6699 12:40:49.025621  

 6700 12:40:49.029006  ----->DramcWriteLeveling(PI) begin...

 6701 12:40:49.029093  ==

 6702 12:40:49.032482  Dram Type= 6, Freq= 0, CH_1, rank 0

 6703 12:40:49.035431  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6704 12:40:49.035516  ==

 6705 12:40:49.039121  Write leveling (Byte 0): 40 => 8

 6706 12:40:49.042206  Write leveling (Byte 1): 32 => 0

 6707 12:40:49.045882  DramcWriteLeveling(PI) end<-----

 6708 12:40:49.045986  

 6709 12:40:49.046054  ==

 6710 12:40:49.049250  Dram Type= 6, Freq= 0, CH_1, rank 0

 6711 12:40:49.052156  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6712 12:40:49.052241  ==

 6713 12:40:49.055595  [Gating] SW mode calibration

 6714 12:40:49.062241  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6715 12:40:49.068635  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6716 12:40:49.071920   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6717 12:40:49.078828   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6718 12:40:49.082054   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6719 12:40:49.085591   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6720 12:40:49.092327   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6721 12:40:49.095659   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6722 12:40:49.099091   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6723 12:40:49.105438   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6724 12:40:49.109228   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6725 12:40:49.111928  Total UI for P1: 0, mck2ui 16

 6726 12:40:49.115320  best dqsien dly found for B0: ( 0, 14, 24)

 6727 12:40:49.118436  Total UI for P1: 0, mck2ui 16

 6728 12:40:49.122206  best dqsien dly found for B1: ( 0, 14, 24)

 6729 12:40:49.125289  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6730 12:40:49.128468  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6731 12:40:49.128553  

 6732 12:40:49.131979  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6733 12:40:49.135191  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6734 12:40:49.138805  [Gating] SW calibration Done

 6735 12:40:49.138889  ==

 6736 12:40:49.142212  Dram Type= 6, Freq= 0, CH_1, rank 0

 6737 12:40:49.145058  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6738 12:40:49.145142  ==

 6739 12:40:49.148402  RX Vref Scan: 0

 6740 12:40:49.148486  

 6741 12:40:49.151562  RX Vref 0 -> 0, step: 1

 6742 12:40:49.151646  

 6743 12:40:49.155074  RX Delay -410 -> 252, step: 16

 6744 12:40:49.158684  iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464

 6745 12:40:49.161524  iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480

 6746 12:40:49.164890  iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480

 6747 12:40:49.171650  iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480

 6748 12:40:49.174952  iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480

 6749 12:40:49.178109  iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480

 6750 12:40:49.181441  iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480

 6751 12:40:49.188227  iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480

 6752 12:40:49.191651  iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480

 6753 12:40:49.194988  iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480

 6754 12:40:49.198625  iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480

 6755 12:40:49.205184  iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480

 6756 12:40:49.208527  iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496

 6757 12:40:49.211246  iDelay=230, Bit 13, Center -19 (-266 ~ 229) 496

 6758 12:40:49.214626  iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480

 6759 12:40:49.221277  iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480

 6760 12:40:49.221362  ==

 6761 12:40:49.224658  Dram Type= 6, Freq= 0, CH_1, rank 0

 6762 12:40:49.228065  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6763 12:40:49.228173  ==

 6764 12:40:49.228254  DQS Delay:

 6765 12:40:49.231419  DQS0 = 27, DQS1 = 43

 6766 12:40:49.231503  DQM Delay:

 6767 12:40:49.234615  DQM0 = 5, DQM1 = 14

 6768 12:40:49.234699  DQ Delay:

 6769 12:40:49.238278  DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0

 6770 12:40:49.241465  DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0

 6771 12:40:49.244827  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16

 6772 12:40:49.247985  DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16

 6773 12:40:49.248070  

 6774 12:40:49.248136  

 6775 12:40:49.248226  ==

 6776 12:40:49.251396  Dram Type= 6, Freq= 0, CH_1, rank 0

 6777 12:40:49.254899  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6778 12:40:49.254984  ==

 6779 12:40:49.255050  

 6780 12:40:49.255114  

 6781 12:40:49.257900  	TX Vref Scan disable

 6782 12:40:49.261474   == TX Byte 0 ==

 6783 12:40:49.264516  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6784 12:40:49.267864  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6785 12:40:49.267948   == TX Byte 1 ==

 6786 12:40:49.274729  Update DQ  dly =572 (4 ,1, 28)  DQ  OEN =(3 ,2)

 6787 12:40:49.278032  Update DQM dly =572 (4 ,1, 28)  DQM OEN =(3 ,2)

 6788 12:40:49.278117  ==

 6789 12:40:49.281094  Dram Type= 6, Freq= 0, CH_1, rank 0

 6790 12:40:49.284664  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6791 12:40:49.284749  ==

 6792 12:40:49.284815  

 6793 12:40:49.287677  

 6794 12:40:49.287761  	TX Vref Scan disable

 6795 12:40:49.290968   == TX Byte 0 ==

 6796 12:40:49.294547  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6797 12:40:49.297715  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6798 12:40:49.301725   == TX Byte 1 ==

 6799 12:40:49.304580  Update DQ  dly =572 (4 ,1, 28)  DQ  OEN =(3 ,2)

 6800 12:40:49.307824  Update DQM dly =572 (4 ,1, 28)  DQM OEN =(3 ,2)

 6801 12:40:49.307908  

 6802 12:40:49.307974  [DATLAT]

 6803 12:40:49.311243  Freq=400, CH1 RK0

 6804 12:40:49.311327  

 6805 12:40:49.314231  DATLAT Default: 0xf

 6806 12:40:49.314314  0, 0xFFFF, sum = 0

 6807 12:40:49.317854  1, 0xFFFF, sum = 0

 6808 12:40:49.317960  2, 0xFFFF, sum = 0

 6809 12:40:49.321161  3, 0xFFFF, sum = 0

 6810 12:40:49.321246  4, 0xFFFF, sum = 0

 6811 12:40:49.324466  5, 0xFFFF, sum = 0

 6812 12:40:49.324553  6, 0xFFFF, sum = 0

 6813 12:40:49.327969  7, 0xFFFF, sum = 0

 6814 12:40:49.328055  8, 0xFFFF, sum = 0

 6815 12:40:49.331112  9, 0xFFFF, sum = 0

 6816 12:40:49.331197  10, 0xFFFF, sum = 0

 6817 12:40:49.334460  11, 0xFFFF, sum = 0

 6818 12:40:49.334545  12, 0xFFFF, sum = 0

 6819 12:40:49.337840  13, 0x0, sum = 1

 6820 12:40:49.337928  14, 0x0, sum = 2

 6821 12:40:49.340930  15, 0x0, sum = 3

 6822 12:40:49.341015  16, 0x0, sum = 4

 6823 12:40:49.344377  best_step = 14

 6824 12:40:49.344486  

 6825 12:40:49.344581  ==

 6826 12:40:49.347972  Dram Type= 6, Freq= 0, CH_1, rank 0

 6827 12:40:49.351073  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6828 12:40:49.351158  ==

 6829 12:40:49.351225  RX Vref Scan: 1

 6830 12:40:49.354525  

 6831 12:40:49.354609  RX Vref 0 -> 0, step: 1

 6832 12:40:49.354675  

 6833 12:40:49.358108  RX Delay -327 -> 252, step: 8

 6834 12:40:49.358192  

 6835 12:40:49.361191  Set Vref, RX VrefLevel [Byte0]: 54

 6836 12:40:49.364690                           [Byte1]: 53

 6837 12:40:49.368722  

 6838 12:40:49.368806  Final RX Vref Byte 0 = 54 to rank0

 6839 12:40:49.371658  Final RX Vref Byte 1 = 53 to rank0

 6840 12:40:49.374917  Final RX Vref Byte 0 = 54 to rank1

 6841 12:40:49.378458  Final RX Vref Byte 1 = 53 to rank1==

 6842 12:40:49.381705  Dram Type= 6, Freq= 0, CH_1, rank 0

 6843 12:40:49.388262  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6844 12:40:49.388346  ==

 6845 12:40:49.388413  DQS Delay:

 6846 12:40:49.391863  DQS0 = 28, DQS1 = 40

 6847 12:40:49.391947  DQM Delay:

 6848 12:40:49.392014  DQM0 = 8, DQM1 = 13

 6849 12:40:49.395062  DQ Delay:

 6850 12:40:49.398364  DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4

 6851 12:40:49.398448  DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4

 6852 12:40:49.401609  DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =4

 6853 12:40:49.404983  DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =20

 6854 12:40:49.405068  

 6855 12:40:49.405134  

 6856 12:40:49.415000  [DQSOSCAuto] RK0, (LSB)MR18= 0x8fcb, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps

 6857 12:40:49.418322  CH1 RK0: MR19=C0C, MR18=8FCB

 6858 12:40:49.425093  CH1_RK0: MR19=0xC0C, MR18=0x8FCB, DQSOSC=384, MR23=63, INC=400, DEC=267

 6859 12:40:49.425177  ==

 6860 12:40:49.428192  Dram Type= 6, Freq= 0, CH_1, rank 1

 6861 12:40:49.431452  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6862 12:40:49.431537  ==

 6863 12:40:49.434761  [Gating] SW mode calibration

 6864 12:40:49.441703  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6865 12:40:49.444988  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6866 12:40:49.451539   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6867 12:40:49.454970   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6868 12:40:49.458172   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6869 12:40:49.465006   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6870 12:40:49.468489   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6871 12:40:49.471702   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6872 12:40:49.478168   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6873 12:40:49.481813   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6874 12:40:49.484662   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6875 12:40:49.488774  Total UI for P1: 0, mck2ui 16

 6876 12:40:49.491308  best dqsien dly found for B0: ( 0, 14, 24)

 6877 12:40:49.494858  Total UI for P1: 0, mck2ui 16

 6878 12:40:49.498343  best dqsien dly found for B1: ( 0, 14, 24)

 6879 12:40:49.501377  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6880 12:40:49.504587  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6881 12:40:49.504671  

 6882 12:40:49.511253  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6883 12:40:49.514840  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6884 12:40:49.514927  [Gating] SW calibration Done

 6885 12:40:49.517890  ==

 6886 12:40:49.521446  Dram Type= 6, Freq= 0, CH_1, rank 1

 6887 12:40:49.524895  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6888 12:40:49.525006  ==

 6889 12:40:49.525102  RX Vref Scan: 0

 6890 12:40:49.525192  

 6891 12:40:49.528062  RX Vref 0 -> 0, step: 1

 6892 12:40:49.528147  

 6893 12:40:49.531669  RX Delay -410 -> 252, step: 16

 6894 12:40:49.534902  iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464

 6895 12:40:49.538252  iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464

 6896 12:40:49.544924  iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464

 6897 12:40:49.548550  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6898 12:40:49.551705  iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464

 6899 12:40:49.554979  iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480

 6900 12:40:49.561934  iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480

 6901 12:40:49.565246  iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464

 6902 12:40:49.568116  iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480

 6903 12:40:49.572166  iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464

 6904 12:40:49.578140  iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480

 6905 12:40:49.581794  iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480

 6906 12:40:49.584969  iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480

 6907 12:40:49.588181  iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464

 6908 12:40:49.594795  iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480

 6909 12:40:49.597896  iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480

 6910 12:40:49.598020  ==

 6911 12:40:49.601412  Dram Type= 6, Freq= 0, CH_1, rank 1

 6912 12:40:49.605026  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6913 12:40:49.605111  ==

 6914 12:40:49.608274  DQS Delay:

 6915 12:40:49.608358  DQS0 = 35, DQS1 = 43

 6916 12:40:49.611389  DQM Delay:

 6917 12:40:49.611473  DQM0 = 16, DQM1 = 18

 6918 12:40:49.611540  DQ Delay:

 6919 12:40:49.615106  DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16

 6920 12:40:49.618128  DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16

 6921 12:40:49.621493  DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16

 6922 12:40:49.625013  DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32

 6923 12:40:49.625097  

 6924 12:40:49.625163  

 6925 12:40:49.625224  ==

 6926 12:40:49.627835  Dram Type= 6, Freq= 0, CH_1, rank 1

 6927 12:40:49.634525  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6928 12:40:49.634610  ==

 6929 12:40:49.634676  

 6930 12:40:49.634736  

 6931 12:40:49.637768  	TX Vref Scan disable

 6932 12:40:49.637853   == TX Byte 0 ==

 6933 12:40:49.641189  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6934 12:40:49.647996  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6935 12:40:49.648081   == TX Byte 1 ==

 6936 12:40:49.651077  Update DQ  dly =577 (4 ,2, 1)  DQ  OEN =(3 ,3)

 6937 12:40:49.654640  Update DQM dly =577 (4 ,2, 1)  DQM OEN =(3 ,3)

 6938 12:40:49.658210  ==

 6939 12:40:49.661254  Dram Type= 6, Freq= 0, CH_1, rank 1

 6940 12:40:49.664639  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6941 12:40:49.664724  ==

 6942 12:40:49.664791  

 6943 12:40:49.664851  

 6944 12:40:49.667919  	TX Vref Scan disable

 6945 12:40:49.668003   == TX Byte 0 ==

 6946 12:40:49.671226  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6947 12:40:49.678383  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6948 12:40:49.678468   == TX Byte 1 ==

 6949 12:40:49.681169  Update DQ  dly =577 (4 ,2, 1)  DQ  OEN =(3 ,3)

 6950 12:40:49.684423  Update DQM dly =577 (4 ,2, 1)  DQM OEN =(3 ,3)

 6951 12:40:49.687771  

 6952 12:40:49.687855  [DATLAT]

 6953 12:40:49.687921  Freq=400, CH1 RK1

 6954 12:40:49.687983  

 6955 12:40:49.691209  DATLAT Default: 0xe

 6956 12:40:49.691293  0, 0xFFFF, sum = 0

 6957 12:40:49.694346  1, 0xFFFF, sum = 0

 6958 12:40:49.694431  2, 0xFFFF, sum = 0

 6959 12:40:49.697833  3, 0xFFFF, sum = 0

 6960 12:40:49.697918  4, 0xFFFF, sum = 0

 6961 12:40:49.700981  5, 0xFFFF, sum = 0

 6962 12:40:49.704447  6, 0xFFFF, sum = 0

 6963 12:40:49.704533  7, 0xFFFF, sum = 0

 6964 12:40:49.707996  8, 0xFFFF, sum = 0

 6965 12:40:49.708082  9, 0xFFFF, sum = 0

 6966 12:40:49.711279  10, 0xFFFF, sum = 0

 6967 12:40:49.711365  11, 0xFFFF, sum = 0

 6968 12:40:49.714499  12, 0xFFFF, sum = 0

 6969 12:40:49.714585  13, 0x0, sum = 1

 6970 12:40:49.717686  14, 0x0, sum = 2

 6971 12:40:49.717771  15, 0x0, sum = 3

 6972 12:40:49.720961  16, 0x0, sum = 4

 6973 12:40:49.721036  best_step = 14

 6974 12:40:49.721100  

 6975 12:40:49.721160  ==

 6976 12:40:49.724347  Dram Type= 6, Freq= 0, CH_1, rank 1

 6977 12:40:49.727568  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6978 12:40:49.727653  ==

 6979 12:40:49.731204  RX Vref Scan: 0

 6980 12:40:49.731288  

 6981 12:40:49.734468  RX Vref 0 -> 0, step: 1

 6982 12:40:49.734553  

 6983 12:40:49.734619  RX Delay -327 -> 252, step: 8

 6984 12:40:49.743282  iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440

 6985 12:40:49.746597  iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440

 6986 12:40:49.749891  iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448

 6987 12:40:49.752758  iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456

 6988 12:40:49.759623  iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448

 6989 12:40:49.763082  iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448

 6990 12:40:49.766214  iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440

 6991 12:40:49.769913  iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448

 6992 12:40:49.776087  iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456

 6993 12:40:49.779168  iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448

 6994 12:40:49.782845  iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448

 6995 12:40:49.785936  iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456

 6996 12:40:49.792992  iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456

 6997 12:40:49.796037  iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456

 6998 12:40:49.799676  iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456

 6999 12:40:49.805931  iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456

 7000 12:40:49.806051  ==

 7001 12:40:49.809439  Dram Type= 6, Freq= 0, CH_1, rank 1

 7002 12:40:49.812663  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 7003 12:40:49.812750  ==

 7004 12:40:49.812816  DQS Delay:

 7005 12:40:49.815898  DQS0 = 32, DQS1 = 36

 7006 12:40:49.815984  DQM Delay:

 7007 12:40:49.819456  DQM0 = 14, DQM1 = 12

 7008 12:40:49.819540  DQ Delay:

 7009 12:40:49.822392  DQ0 =20, DQ1 =12, DQ2 =0, DQ3 =12

 7010 12:40:49.825786  DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =8

 7011 12:40:49.829109  DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8

 7012 12:40:49.832359  DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24

 7013 12:40:49.832443  

 7014 12:40:49.832509  

 7015 12:40:49.838843  [DQSOSCAuto] RK1, (LSB)MR18= 0xa651, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 389 ps

 7016 12:40:49.842824  CH1 RK1: MR19=C0C, MR18=A651

 7017 12:40:49.848940  CH1_RK1: MR19=0xC0C, MR18=0xA651, DQSOSC=389, MR23=63, INC=390, DEC=260

 7018 12:40:49.852026  [RxdqsGatingPostProcess] freq 400

 7019 12:40:49.858937  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 7020 12:40:49.862191  best DQS0 dly(2T, 0.5T) = (0, 10)

 7021 12:40:49.862276  best DQS1 dly(2T, 0.5T) = (0, 10)

 7022 12:40:49.865575  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 7023 12:40:49.868835  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 7024 12:40:49.872489  best DQS0 dly(2T, 0.5T) = (0, 10)

 7025 12:40:49.875840  best DQS1 dly(2T, 0.5T) = (0, 10)

 7026 12:40:49.878786  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 7027 12:40:49.882368  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 7028 12:40:49.885611  Pre-setting of DQS Precalculation

 7029 12:40:49.892214  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 7030 12:40:49.898727  sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6

 7031 12:40:49.905446  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 7032 12:40:49.905587  

 7033 12:40:49.905658  

 7034 12:40:49.909062  [Calibration Summary] 800 Mbps

 7035 12:40:49.909155  CH 0, Rank 0

 7036 12:40:49.912149  SW Impedance     : PASS

 7037 12:40:49.915733  DUTY Scan        : NO K

 7038 12:40:49.915831  ZQ Calibration   : PASS

 7039 12:40:49.919045  Jitter Meter     : NO K

 7040 12:40:49.919133  CBT Training     : PASS

 7041 12:40:49.922756  Write leveling   : PASS

 7042 12:40:49.925518  RX DQS gating    : PASS

 7043 12:40:49.925605  RX DQ/DQS(RDDQC) : PASS

 7044 12:40:49.928928  TX DQ/DQS        : PASS

 7045 12:40:49.932122  RX DATLAT        : PASS

 7046 12:40:49.932207  RX DQ/DQS(Engine): PASS

 7047 12:40:49.935351  TX OE            : NO K

 7048 12:40:49.935437  All Pass.

 7049 12:40:49.935504  

 7050 12:40:49.938810  CH 0, Rank 1

 7051 12:40:49.938895  SW Impedance     : PASS

 7052 12:40:49.942187  DUTY Scan        : NO K

 7053 12:40:49.945504  ZQ Calibration   : PASS

 7054 12:40:49.945590  Jitter Meter     : NO K

 7055 12:40:49.948984  CBT Training     : PASS

 7056 12:40:49.952401  Write leveling   : NO K

 7057 12:40:49.952487  RX DQS gating    : PASS

 7058 12:40:49.955565  RX DQ/DQS(RDDQC) : PASS

 7059 12:40:49.958700  TX DQ/DQS        : PASS

 7060 12:40:49.958787  RX DATLAT        : PASS

 7061 12:40:49.962358  RX DQ/DQS(Engine): PASS

 7062 12:40:49.962444  TX OE            : NO K

 7063 12:40:49.965351  All Pass.

 7064 12:40:49.965442  

 7065 12:40:49.965517  CH 1, Rank 0

 7066 12:40:49.968719  SW Impedance     : PASS

 7067 12:40:49.968805  DUTY Scan        : NO K

 7068 12:40:49.972058  ZQ Calibration   : PASS

 7069 12:40:49.975249  Jitter Meter     : NO K

 7070 12:40:49.975341  CBT Training     : PASS

 7071 12:40:49.979009  Write leveling   : PASS

 7072 12:40:49.982300  RX DQS gating    : PASS

 7073 12:40:49.982389  RX DQ/DQS(RDDQC) : PASS

 7074 12:40:49.985495  TX DQ/DQS        : PASS

 7075 12:40:49.988656  RX DATLAT        : PASS

 7076 12:40:49.988743  RX DQ/DQS(Engine): PASS

 7077 12:40:49.991914  TX OE            : NO K

 7078 12:40:49.992001  All Pass.

 7079 12:40:49.992068  

 7080 12:40:49.995449  CH 1, Rank 1

 7081 12:40:49.995551  SW Impedance     : PASS

 7082 12:40:49.999070  DUTY Scan        : NO K

 7083 12:40:50.002117  ZQ Calibration   : PASS

 7084 12:40:50.002205  Jitter Meter     : NO K

 7085 12:40:50.005279  CBT Training     : PASS

 7086 12:40:50.008670  Write leveling   : NO K

 7087 12:40:50.008756  RX DQS gating    : PASS

 7088 12:40:50.012084  RX DQ/DQS(RDDQC) : PASS

 7089 12:40:50.012171  TX DQ/DQS        : PASS

 7090 12:40:50.015401  RX DATLAT        : PASS

 7091 12:40:50.018809  RX DQ/DQS(Engine): PASS

 7092 12:40:50.018899  TX OE            : NO K

 7093 12:40:50.022112  All Pass.

 7094 12:40:50.022198  

 7095 12:40:50.022265  DramC Write-DBI off

 7096 12:40:50.025153  	PER_BANK_REFRESH: Hybrid Mode

 7097 12:40:50.028827  TX_TRACKING: ON

 7098 12:40:50.035512  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 7099 12:40:50.038616  [FAST_K] Save calibration result to emmc

 7100 12:40:50.042655  dramc_set_vcore_voltage set vcore to 725000

 7101 12:40:50.045524  Read voltage for 1600, 0

 7102 12:40:50.045617  Vio18 = 0

 7103 12:40:50.048845  Vcore = 725000

 7104 12:40:50.048935  Vdram = 0

 7105 12:40:50.049001  Vddq = 0

 7106 12:40:50.052312  Vmddr = 0

 7107 12:40:50.055214  [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0

 7108 12:40:50.062547  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 7109 12:40:50.062660  MEM_TYPE=3, freq_sel=13

 7110 12:40:50.065264  sv_algorithm_assistance_LP4_3733 

 7111 12:40:50.072193  ============ PULL DRAM RESETB DOWN ============

 7112 12:40:50.075205  ========== PULL DRAM RESETB DOWN end =========

 7113 12:40:50.078628  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7114 12:40:50.081886  =================================== 

 7115 12:40:50.085339  LPDDR4 DRAM CONFIGURATION

 7116 12:40:50.088500  =================================== 

 7117 12:40:50.091869  EX_ROW_EN[0]    = 0x0

 7118 12:40:50.091969  EX_ROW_EN[1]    = 0x0

 7119 12:40:50.095287  LP4Y_EN      = 0x0

 7120 12:40:50.095375  WORK_FSP     = 0x1

 7121 12:40:50.098808  WL           = 0x5

 7122 12:40:50.098899  RL           = 0x5

 7123 12:40:50.102036  BL           = 0x2

 7124 12:40:50.102124  RPST         = 0x0

 7125 12:40:50.105230  RD_PRE       = 0x0

 7126 12:40:50.105317  WR_PRE       = 0x1

 7127 12:40:50.108447  WR_PST       = 0x1

 7128 12:40:50.108536  DBI_WR       = 0x0

 7129 12:40:50.111867  DBI_RD       = 0x0

 7130 12:40:50.111956  OTF          = 0x1

 7131 12:40:50.115656  =================================== 

 7132 12:40:50.118815  =================================== 

 7133 12:40:50.121973  ANA top config

 7134 12:40:50.125509  =================================== 

 7135 12:40:50.125601  DLL_ASYNC_EN            =  0

 7136 12:40:50.128822  ALL_SLAVE_EN            =  0

 7137 12:40:50.132457  NEW_RANK_MODE           =  1

 7138 12:40:50.135339  DLL_IDLE_MODE           =  1

 7139 12:40:50.135431  LP45_APHY_COMB_EN       =  1

 7140 12:40:50.138937  TX_ODT_DIS              =  0

 7141 12:40:50.141884  NEW_8X_MODE             =  1

 7142 12:40:50.145293  =================================== 

 7143 12:40:50.149212  =================================== 

 7144 12:40:50.151920  data_rate                  = 3200

 7145 12:40:50.155755  CKR                        = 1

 7146 12:40:50.158662  DQ_P2S_RATIO               = 8

 7147 12:40:50.161952  =================================== 

 7148 12:40:50.162059  CA_P2S_RATIO               = 8

 7149 12:40:50.165561  DQ_CA_OPEN                 = 0

 7150 12:40:50.168900  DQ_SEMI_OPEN               = 0

 7151 12:40:50.172566  CA_SEMI_OPEN               = 0

 7152 12:40:50.175770  CA_FULL_RATE               = 0

 7153 12:40:50.175863  DQ_CKDIV4_EN               = 0

 7154 12:40:50.178801  CA_CKDIV4_EN               = 0

 7155 12:40:50.182296  CA_PREDIV_EN               = 0

 7156 12:40:50.185528  PH8_DLY                    = 12

 7157 12:40:50.188924  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 7158 12:40:50.192126  DQ_AAMCK_DIV               = 4

 7159 12:40:50.192221  CA_AAMCK_DIV               = 4

 7160 12:40:50.195538  CA_ADMCK_DIV               = 4

 7161 12:40:50.198886  DQ_TRACK_CA_EN             = 0

 7162 12:40:50.201869  CA_PICK                    = 1600

 7163 12:40:50.205498  CA_MCKIO                   = 1600

 7164 12:40:50.208589  MCKIO_SEMI                 = 0

 7165 12:40:50.211868  PLL_FREQ                   = 3068

 7166 12:40:50.215210  DQ_UI_PI_RATIO             = 32

 7167 12:40:50.215313  CA_UI_PI_RATIO             = 0

 7168 12:40:50.218943  =================================== 

 7169 12:40:50.222100  =================================== 

 7170 12:40:50.225544  memory_type:LPDDR4         

 7171 12:40:50.228384  GP_NUM     : 10       

 7172 12:40:50.228479  SRAM_EN    : 1       

 7173 12:40:50.231747  MD32_EN    : 0       

 7174 12:40:50.235163  =================================== 

 7175 12:40:50.238308  [ANA_INIT] >>>>>>>>>>>>>> 

 7176 12:40:50.241766  <<<<<< [CONFIGURE PHASE]: ANA_TX

 7177 12:40:50.245118  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 7178 12:40:50.248634  =================================== 

 7179 12:40:50.248735  data_rate = 3200,PCW = 0X7600

 7180 12:40:50.251753  =================================== 

 7181 12:40:50.254898  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 7182 12:40:50.261817  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7183 12:40:50.268104  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7184 12:40:50.271675  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 7185 12:40:50.275288  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 7186 12:40:50.278593  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 7187 12:40:50.281861  [ANA_INIT] flow start 

 7188 12:40:50.281982  [ANA_INIT] PLL >>>>>>>> 

 7189 12:40:50.285125  [ANA_INIT] PLL <<<<<<<< 

 7190 12:40:50.288173  [ANA_INIT] MIDPI >>>>>>>> 

 7191 12:40:50.291796  [ANA_INIT] MIDPI <<<<<<<< 

 7192 12:40:50.291887  [ANA_INIT] DLL >>>>>>>> 

 7193 12:40:50.294746  [ANA_INIT] DLL <<<<<<<< 

 7194 12:40:50.298683  [ANA_INIT] flow end 

 7195 12:40:50.301269  ============ LP4 DIFF to SE enter ============

 7196 12:40:50.304988  ============ LP4 DIFF to SE exit  ============

 7197 12:40:50.307965  [ANA_INIT] <<<<<<<<<<<<< 

 7198 12:40:50.311907  [Flow] Enable top DCM control >>>>> 

 7199 12:40:50.315022  [Flow] Enable top DCM control <<<<< 

 7200 12:40:50.317954  Enable DLL master slave shuffle 

 7201 12:40:50.321348  ============================================================== 

 7202 12:40:50.326524  Gating Mode config

 7203 12:40:50.327943  ============================================================== 

 7204 12:40:50.331219  Config description: 

 7205 12:40:50.341910  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 7206 12:40:50.348114  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 7207 12:40:50.352009  SELPH_MODE            0: By rank         1: By Phase 

 7208 12:40:50.358205  ============================================================== 

 7209 12:40:50.361684  GAT_TRACK_EN                 =  1

 7210 12:40:50.364929  RX_GATING_MODE               =  2

 7211 12:40:50.367885  RX_GATING_TRACK_MODE         =  2

 7212 12:40:50.371194  SELPH_MODE                   =  1

 7213 12:40:50.374570  PICG_EARLY_EN                =  1

 7214 12:40:50.374667  VALID_LAT_VALUE              =  1

 7215 12:40:50.381642  ============================================================== 

 7216 12:40:50.384732  Enter into Gating configuration >>>> 

 7217 12:40:50.388022  Exit from Gating configuration <<<< 

 7218 12:40:50.391229  Enter into  DVFS_PRE_config >>>>> 

 7219 12:40:50.401217  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 7220 12:40:50.404449  Exit from  DVFS_PRE_config <<<<< 

 7221 12:40:50.407686  Enter into PICG configuration >>>> 

 7222 12:40:50.411137  Exit from PICG configuration <<<< 

 7223 12:40:50.414465  [RX_INPUT] configuration >>>>> 

 7224 12:40:50.417729  [RX_INPUT] configuration <<<<< 

 7225 12:40:50.424345  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 7226 12:40:50.427740  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 7227 12:40:50.434212  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 7228 12:40:50.441087  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 7229 12:40:50.447389  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 7230 12:40:50.454264  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 7231 12:40:50.457563  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 7232 12:40:50.460830  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 7233 12:40:50.464306  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 7234 12:40:50.470675  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 7235 12:40:50.474211  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 7236 12:40:50.477743  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7237 12:40:50.480684  =================================== 

 7238 12:40:50.484303  LPDDR4 DRAM CONFIGURATION

 7239 12:40:50.487582  =================================== 

 7240 12:40:50.487688  EX_ROW_EN[0]    = 0x0

 7241 12:40:50.490938  EX_ROW_EN[1]    = 0x0

 7242 12:40:50.491034  LP4Y_EN      = 0x0

 7243 12:40:50.494625  WORK_FSP     = 0x1

 7244 12:40:50.494724  WL           = 0x5

 7245 12:40:50.497510  RL           = 0x5

 7246 12:40:50.500835  BL           = 0x2

 7247 12:40:50.500932  RPST         = 0x0

 7248 12:40:50.504169  RD_PRE       = 0x0

 7249 12:40:50.504264  WR_PRE       = 0x1

 7250 12:40:50.507938  WR_PST       = 0x1

 7251 12:40:50.508036  DBI_WR       = 0x0

 7252 12:40:50.510846  DBI_RD       = 0x0

 7253 12:40:50.510948  OTF          = 0x1

 7254 12:40:50.514218  =================================== 

 7255 12:40:50.517324  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 7256 12:40:50.524113  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 7257 12:40:50.527243  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7258 12:40:50.530859  =================================== 

 7259 12:40:50.533926  LPDDR4 DRAM CONFIGURATION

 7260 12:40:50.537578  =================================== 

 7261 12:40:50.537698  EX_ROW_EN[0]    = 0x10

 7262 12:40:50.540651  EX_ROW_EN[1]    = 0x0

 7263 12:40:50.540786  LP4Y_EN      = 0x0

 7264 12:40:50.543749  WORK_FSP     = 0x1

 7265 12:40:50.543848  WL           = 0x5

 7266 12:40:50.546985  RL           = 0x5

 7267 12:40:50.550505  BL           = 0x2

 7268 12:40:50.550619  RPST         = 0x0

 7269 12:40:50.553718  RD_PRE       = 0x0

 7270 12:40:50.553818  WR_PRE       = 0x1

 7271 12:40:50.557020  WR_PST       = 0x1

 7272 12:40:50.557118  DBI_WR       = 0x0

 7273 12:40:50.560449  DBI_RD       = 0x0

 7274 12:40:50.560545  OTF          = 0x1

 7275 12:40:50.563603  =================================== 

 7276 12:40:50.570640  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 7277 12:40:50.570796  ==

 7278 12:40:50.573689  Dram Type= 6, Freq= 0, CH_0, rank 0

 7279 12:40:50.577075  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7280 12:40:50.577200  ==

 7281 12:40:50.580402  [Duty_Offset_Calibration]

 7282 12:40:50.583469  	B0:2	B1:0	CA:1

 7283 12:40:50.583574  

 7284 12:40:50.586813  [DutyScan_Calibration_Flow] k_type=0

 7285 12:40:50.594304  

 7286 12:40:50.594468  ==CLK 0==

 7287 12:40:50.597612  Final CLK duty delay cell = -4

 7288 12:40:50.601164  [-4] MAX Duty = 5000%(X100), DQS PI = 22

 7289 12:40:50.604143  [-4] MIN Duty = 4813%(X100), DQS PI = 62

 7290 12:40:50.608034  [-4] AVG Duty = 4906%(X100)

 7291 12:40:50.608150  

 7292 12:40:50.611300  CH0 CLK Duty spec in!! Max-Min= 187%

 7293 12:40:50.614112  [DutyScan_Calibration_Flow] ====Done====

 7294 12:40:50.614206  

 7295 12:40:50.617686  [DutyScan_Calibration_Flow] k_type=1

 7296 12:40:50.633841  

 7297 12:40:50.634040  ==DQS 0 ==

 7298 12:40:50.637732  Final DQS duty delay cell = 0

 7299 12:40:50.640799  [0] MAX Duty = 5249%(X100), DQS PI = 34

 7300 12:40:50.643865  [0] MIN Duty = 4969%(X100), DQS PI = 2

 7301 12:40:50.643965  [0] AVG Duty = 5109%(X100)

 7302 12:40:50.647091  

 7303 12:40:50.647187  ==DQS 1 ==

 7304 12:40:50.650571  Final DQS duty delay cell = -4

 7305 12:40:50.653910  [-4] MAX Duty = 5125%(X100), DQS PI = 46

 7306 12:40:50.657925  [-4] MIN Duty = 4844%(X100), DQS PI = 4

 7307 12:40:50.660640  [-4] AVG Duty = 4984%(X100)

 7308 12:40:50.660738  

 7309 12:40:50.663753  CH0 DQS 0 Duty spec in!! Max-Min= 280%

 7310 12:40:50.663846  

 7311 12:40:50.667210  CH0 DQS 1 Duty spec in!! Max-Min= 281%

 7312 12:40:50.670552  [DutyScan_Calibration_Flow] ====Done====

 7313 12:40:50.670658  

 7314 12:40:50.673534  [DutyScan_Calibration_Flow] k_type=3

 7315 12:40:50.691782  

 7316 12:40:50.691941  ==DQM 0 ==

 7317 12:40:50.694578  Final DQM duty delay cell = 0

 7318 12:40:50.697848  [0] MAX Duty = 5093%(X100), DQS PI = 26

 7319 12:40:50.701222  [0] MIN Duty = 4844%(X100), DQS PI = 0

 7320 12:40:50.704517  [0] AVG Duty = 4968%(X100)

 7321 12:40:50.704627  

 7322 12:40:50.704697  ==DQM 1 ==

 7323 12:40:50.707553  Final DQM duty delay cell = 0

 7324 12:40:50.711046  [0] MAX Duty = 5249%(X100), DQS PI = 30

 7325 12:40:50.714638  [0] MIN Duty = 5000%(X100), DQS PI = 20

 7326 12:40:50.717859  [0] AVG Duty = 5124%(X100)

 7327 12:40:50.718009  

 7328 12:40:50.721001  CH0 DQM 0 Duty spec in!! Max-Min= 249%

 7329 12:40:50.721101  

 7330 12:40:50.724132  CH0 DQM 1 Duty spec in!! Max-Min= 249%

 7331 12:40:50.727562  [DutyScan_Calibration_Flow] ====Done====

 7332 12:40:50.727671  

 7333 12:40:50.730902  [DutyScan_Calibration_Flow] k_type=2

 7334 12:40:50.748311  

 7335 12:40:50.748468  ==DQ 0 ==

 7336 12:40:50.751919  Final DQ duty delay cell = 0

 7337 12:40:50.754843  [0] MAX Duty = 5124%(X100), DQS PI = 34

 7338 12:40:50.758519  [0] MIN Duty = 5000%(X100), DQS PI = 0

 7339 12:40:50.758636  [0] AVG Duty = 5062%(X100)

 7340 12:40:50.761569  

 7341 12:40:50.761667  ==DQ 1 ==

 7342 12:40:50.765360  Final DQ duty delay cell = 0

 7343 12:40:50.768453  [0] MAX Duty = 4969%(X100), DQS PI = 44

 7344 12:40:50.771513  [0] MIN Duty = 4875%(X100), DQS PI = 0

 7345 12:40:50.771616  [0] AVG Duty = 4922%(X100)

 7346 12:40:50.771686  

 7347 12:40:50.774993  CH0 DQ 0 Duty spec in!! Max-Min= 124%

 7348 12:40:50.775084  

 7349 12:40:50.778526  CH0 DQ 1 Duty spec in!! Max-Min= 94%

 7350 12:40:50.784999  [DutyScan_Calibration_Flow] ====Done====

 7351 12:40:50.785125  ==

 7352 12:40:50.788393  Dram Type= 6, Freq= 0, CH_1, rank 0

 7353 12:40:50.791833  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7354 12:40:50.791948  ==

 7355 12:40:50.794912  [Duty_Offset_Calibration]

 7356 12:40:50.795017  	B0:0	B1:-1	CA:2

 7357 12:40:50.795087  

 7358 12:40:50.798585  [DutyScan_Calibration_Flow] k_type=0

 7359 12:40:50.808781  

 7360 12:40:50.808931  ==CLK 0==

 7361 12:40:50.811885  Final CLK duty delay cell = 0

 7362 12:40:50.815182  [0] MAX Duty = 5156%(X100), DQS PI = 10

 7363 12:40:50.818418  [0] MIN Duty = 4938%(X100), DQS PI = 44

 7364 12:40:50.818553  [0] AVG Duty = 5047%(X100)

 7365 12:40:50.821677  

 7366 12:40:50.825096  CH1 CLK Duty spec in!! Max-Min= 218%

 7367 12:40:50.828496  [DutyScan_Calibration_Flow] ====Done====

 7368 12:40:50.828590  

 7369 12:40:50.831658  [DutyScan_Calibration_Flow] k_type=1

 7370 12:40:50.848220  

 7371 12:40:50.848390  ==DQS 0 ==

 7372 12:40:50.851915  Final DQS duty delay cell = 0

 7373 12:40:50.854902  [0] MAX Duty = 5093%(X100), DQS PI = 24

 7374 12:40:50.858148  [0] MIN Duty = 4969%(X100), DQS PI = 4

 7375 12:40:50.858271  [0] AVG Duty = 5031%(X100)

 7376 12:40:50.861466  

 7377 12:40:50.861570  ==DQS 1 ==

 7378 12:40:50.864948  Final DQS duty delay cell = 0

 7379 12:40:50.868264  [0] MAX Duty = 5187%(X100), DQS PI = 0

 7380 12:40:50.871520  [0] MIN Duty = 4844%(X100), DQS PI = 32

 7381 12:40:50.871652  [0] AVG Duty = 5015%(X100)

 7382 12:40:50.874818  

 7383 12:40:50.878169  CH1 DQS 0 Duty spec in!! Max-Min= 124%

 7384 12:40:50.878305  

 7385 12:40:50.881346  CH1 DQS 1 Duty spec in!! Max-Min= 343%

 7386 12:40:50.884670  [DutyScan_Calibration_Flow] ====Done====

 7387 12:40:50.884808  

 7388 12:40:50.888518  [DutyScan_Calibration_Flow] k_type=3

 7389 12:40:50.905845  

 7390 12:40:50.906061  ==DQM 0 ==

 7391 12:40:50.909201  Final DQM duty delay cell = 4

 7392 12:40:50.912240  [4] MAX Duty = 5125%(X100), DQS PI = 22

 7393 12:40:50.915714  [4] MIN Duty = 5000%(X100), DQS PI = 30

 7394 12:40:50.919053  [4] AVG Duty = 5062%(X100)

 7395 12:40:50.919180  

 7396 12:40:50.919248  ==DQM 1 ==

 7397 12:40:50.922431  Final DQM duty delay cell = 0

 7398 12:40:50.925702  [0] MAX Duty = 5281%(X100), DQS PI = 58

 7399 12:40:50.929412  [0] MIN Duty = 4876%(X100), DQS PI = 34

 7400 12:40:50.932745  [0] AVG Duty = 5078%(X100)

 7401 12:40:50.932842  

 7402 12:40:50.935945  CH1 DQM 0 Duty spec in!! Max-Min= 125%

 7403 12:40:50.936035  

 7404 12:40:50.939441  CH1 DQM 1 Duty spec in!! Max-Min= 405%

 7405 12:40:50.942704  [DutyScan_Calibration_Flow] ====Done====

 7406 12:40:50.942811  

 7407 12:40:50.945643  [DutyScan_Calibration_Flow] k_type=2

 7408 12:40:50.963074  

 7409 12:40:50.963235  ==DQ 0 ==

 7410 12:40:50.966138  Final DQ duty delay cell = 0

 7411 12:40:50.969420  [0] MAX Duty = 5093%(X100), DQS PI = 22

 7412 12:40:50.972655  [0] MIN Duty = 4969%(X100), DQS PI = 10

 7413 12:40:50.972785  [0] AVG Duty = 5031%(X100)

 7414 12:40:50.975920  

 7415 12:40:50.976024  ==DQ 1 ==

 7416 12:40:50.979573  Final DQ duty delay cell = 0

 7417 12:40:50.982627  [0] MAX Duty = 5062%(X100), DQS PI = 2

 7418 12:40:50.985978  [0] MIN Duty = 4813%(X100), DQS PI = 34

 7419 12:40:50.986077  [0] AVG Duty = 4937%(X100)

 7420 12:40:50.986145  

 7421 12:40:50.989584  CH1 DQ 0 Duty spec in!! Max-Min= 124%

 7422 12:40:50.992795  

 7423 12:40:50.996329  CH1 DQ 1 Duty spec in!! Max-Min= 249%

 7424 12:40:50.999121  [DutyScan_Calibration_Flow] ====Done====

 7425 12:40:51.002827  nWR fixed to 30

 7426 12:40:51.002930  [ModeRegInit_LP4] CH0 RK0

 7427 12:40:51.006316  [ModeRegInit_LP4] CH0 RK1

 7428 12:40:51.009337  [ModeRegInit_LP4] CH1 RK0

 7429 12:40:51.009448  [ModeRegInit_LP4] CH1 RK1

 7430 12:40:51.012486  match AC timing 5

 7431 12:40:51.015971  dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1

 7432 12:40:51.022435  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 7433 12:40:51.025821  [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14

 7434 12:40:51.032834  [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29

 7435 12:40:51.035846  [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)

 7436 12:40:51.035955  [MiockJmeterHQA]

 7437 12:40:51.036021  

 7438 12:40:51.039569  [DramcMiockJmeter] u1RxGatingPI = 0

 7439 12:40:51.042895  0 : 4255, 4029

 7440 12:40:51.043002  4 : 4368, 4140

 7441 12:40:51.043078  8 : 4368, 4140

 7442 12:40:51.045885  12 : 4252, 4027

 7443 12:40:51.046037  16 : 4253, 4027

 7444 12:40:51.049110  20 : 4255, 4029

 7445 12:40:51.049209  24 : 4363, 4138

 7446 12:40:51.052406  28 : 4252, 4027

 7447 12:40:51.052514  32 : 4252, 4027

 7448 12:40:51.056021  36 : 4253, 4026

 7449 12:40:51.056115  40 : 4252, 4027

 7450 12:40:51.056188  44 : 4252, 4027

 7451 12:40:51.059457  48 : 4363, 4137

 7452 12:40:51.059576  52 : 4366, 4140

 7453 12:40:51.062585  56 : 4250, 4027

 7454 12:40:51.062694  60 : 4252, 4027

 7455 12:40:51.065837  64 : 4249, 4027

 7456 12:40:51.065971  68 : 4250, 4027

 7457 12:40:51.066044  72 : 4250, 4027

 7458 12:40:51.069340  76 : 4360, 4137

 7459 12:40:51.069447  80 : 4250, 4027

 7460 12:40:51.072750  84 : 4250, 4027

 7461 12:40:51.072862  88 : 4250, 3391

 7462 12:40:51.075854  92 : 4250, 0

 7463 12:40:51.075954  96 : 4250, 0

 7464 12:40:51.076023  100 : 4252, 0

 7465 12:40:51.079098  104 : 4252, 0

 7466 12:40:51.079199  108 : 4252, 0

 7467 12:40:51.082713  112 : 4361, 0

 7468 12:40:51.082816  116 : 4361, 0

 7469 12:40:51.082887  120 : 4360, 0

 7470 12:40:51.085997  124 : 4250, 0

 7471 12:40:51.086094  128 : 4250, 0

 7472 12:40:51.086161  132 : 4250, 0

 7473 12:40:51.089266  136 : 4250, 0

 7474 12:40:51.089367  140 : 4250, 0

 7475 12:40:51.092841  144 : 4250, 0

 7476 12:40:51.092943  148 : 4250, 0

 7477 12:40:51.093013  152 : 4250, 0

 7478 12:40:51.096024  156 : 4250, 0

 7479 12:40:51.096121  160 : 4253, 0

 7480 12:40:51.099729  164 : 4361, 0

 7481 12:40:51.099828  168 : 4360, 0

 7482 12:40:51.099897  172 : 4250, 0

 7483 12:40:51.102452  176 : 4250, 0

 7484 12:40:51.102546  180 : 4250, 0

 7485 12:40:51.102613  184 : 4250, 0

 7486 12:40:51.105732  188 : 4250, 0

 7487 12:40:51.105857  192 : 4250, 0

 7488 12:40:51.109110  196 : 4250, 0

 7489 12:40:51.109225  200 : 4252, 0

 7490 12:40:51.112579  204 : 4250, 2392

 7491 12:40:51.112686  208 : 4252, 4029

 7492 12:40:51.112754  212 : 4363, 4139

 7493 12:40:51.115946  216 : 4250, 4027

 7494 12:40:51.116055  220 : 4250, 4026

 7495 12:40:51.119613  224 : 4250, 4027

 7496 12:40:51.119742  228 : 4250, 4027

 7497 12:40:51.122447  232 : 4250, 4027

 7498 12:40:51.122551  236 : 4250, 4027

 7499 12:40:51.125934  240 : 4361, 4138

 7500 12:40:51.126087  244 : 4250, 4027

 7501 12:40:51.129434  248 : 4249, 4027

 7502 12:40:51.129542  252 : 4360, 4137

 7503 12:40:51.132694  256 : 4250, 4027

 7504 12:40:51.132807  260 : 4250, 4027

 7505 12:40:51.132878  264 : 4360, 4138

 7506 12:40:51.135985  268 : 4249, 4027

 7507 12:40:51.136091  272 : 4250, 4026

 7508 12:40:51.139224  276 : 4250, 4027

 7509 12:40:51.139337  280 : 4250, 4027

 7510 12:40:51.142734  284 : 4249, 4027

 7511 12:40:51.142845  288 : 4250, 4026

 7512 12:40:51.145704  292 : 4361, 4137

 7513 12:40:51.145807  296 : 4250, 4027

 7514 12:40:51.149256  300 : 4250, 4027

 7515 12:40:51.149371  304 : 4360, 4137

 7516 12:40:51.152551  308 : 4250, 4027

 7517 12:40:51.152664  312 : 4250, 3980

 7518 12:40:51.155700  316 : 4360, 2180

 7519 12:40:51.155807  320 : 4250, 3

 7520 12:40:51.155877  

 7521 12:40:51.159067  	MIOCK jitter meter	ch=0

 7522 12:40:51.159198  

 7523 12:40:51.162275  1T = (320-92) = 228 dly cells

 7524 12:40:51.165765  Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps

 7525 12:40:51.165885  ==

 7526 12:40:51.168902  Dram Type= 6, Freq= 0, CH_0, rank 0

 7527 12:40:51.175423  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7528 12:40:51.175572  ==

 7529 12:40:51.179147  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7530 12:40:51.185547  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7531 12:40:51.189386  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7532 12:40:51.196100  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7533 12:40:51.202864  [CA 0] Center 43 (13~73) winsize 61

 7534 12:40:51.206350  [CA 1] Center 43 (13~73) winsize 61

 7535 12:40:51.209434  [CA 2] Center 38 (8~68) winsize 61

 7536 12:40:51.212865  [CA 3] Center 37 (8~67) winsize 60

 7537 12:40:51.216189  [CA 4] Center 36 (6~66) winsize 61

 7538 12:40:51.219405  [CA 5] Center 35 (5~65) winsize 61

 7539 12:40:51.219513  

 7540 12:40:51.222803  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 7541 12:40:51.222899  

 7542 12:40:51.226170  [CATrainingPosCal] consider 1 rank data

 7543 12:40:51.229471  u2DelayCellTimex100 = 285/100 ps

 7544 12:40:51.232827  CA0 delay=43 (13~73),Diff = 8 PI (27 cell)

 7545 12:40:51.239376  CA1 delay=43 (13~73),Diff = 8 PI (27 cell)

 7546 12:40:51.243076  CA2 delay=38 (8~68),Diff = 3 PI (10 cell)

 7547 12:40:51.246131  CA3 delay=37 (8~67),Diff = 2 PI (6 cell)

 7548 12:40:51.249474  CA4 delay=36 (6~66),Diff = 1 PI (3 cell)

 7549 12:40:51.252710  CA5 delay=35 (5~65),Diff = 0 PI (0 cell)

 7550 12:40:51.252813  

 7551 12:40:51.256183  CA PerBit enable=1, Macro0, CA PI delay=35

 7552 12:40:51.256281  

 7553 12:40:51.259450  [CBTSetCACLKResult] CA Dly = 35

 7554 12:40:51.262841  CS Dly: 9 (0~40)

 7555 12:40:51.266158  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7556 12:40:51.269673  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7557 12:40:51.269779  ==

 7558 12:40:51.273047  Dram Type= 6, Freq= 0, CH_0, rank 1

 7559 12:40:51.276094  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7560 12:40:51.279269  ==

 7561 12:40:51.282868  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7562 12:40:51.285934  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7563 12:40:51.293044  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7564 12:40:51.295999  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7565 12:40:51.306539  [CA 0] Center 43 (13~73) winsize 61

 7566 12:40:51.309657  [CA 1] Center 43 (13~73) winsize 61

 7567 12:40:51.313281  [CA 2] Center 38 (9~67) winsize 59

 7568 12:40:51.316249  [CA 3] Center 38 (8~68) winsize 61

 7569 12:40:51.319657  [CA 4] Center 37 (7~67) winsize 61

 7570 12:40:51.322780  [CA 5] Center 36 (6~66) winsize 61

 7571 12:40:51.322905  

 7572 12:40:51.326310  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 7573 12:40:51.326426  

 7574 12:40:51.329864  [CATrainingPosCal] consider 2 rank data

 7575 12:40:51.332819  u2DelayCellTimex100 = 285/100 ps

 7576 12:40:51.336213  CA0 delay=43 (13~73),Diff = 8 PI (27 cell)

 7577 12:40:51.342857  CA1 delay=43 (13~73),Diff = 8 PI (27 cell)

 7578 12:40:51.346063  CA2 delay=38 (9~67),Diff = 3 PI (10 cell)

 7579 12:40:51.349340  CA3 delay=37 (8~67),Diff = 2 PI (6 cell)

 7580 12:40:51.352943  CA4 delay=36 (7~66),Diff = 1 PI (3 cell)

 7581 12:40:51.356066  CA5 delay=35 (6~65),Diff = 0 PI (0 cell)

 7582 12:40:51.356162  

 7583 12:40:51.359172  CA PerBit enable=1, Macro0, CA PI delay=35

 7584 12:40:51.359261  

 7585 12:40:51.362516  [CBTSetCACLKResult] CA Dly = 35

 7586 12:40:51.365963  CS Dly: 11 (0~44)

 7587 12:40:51.369732  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7588 12:40:51.372659  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7589 12:40:51.372750  

 7590 12:40:51.376084  ----->DramcWriteLeveling(PI) begin...

 7591 12:40:51.376179  ==

 7592 12:40:51.379298  Dram Type= 6, Freq= 0, CH_0, rank 0

 7593 12:40:51.386261  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7594 12:40:51.386383  ==

 7595 12:40:51.389275  Write leveling (Byte 0): 38 => 38

 7596 12:40:51.389369  Write leveling (Byte 1): 31 => 31

 7597 12:40:51.392578  DramcWriteLeveling(PI) end<-----

 7598 12:40:51.392680  

 7599 12:40:51.392747  ==

 7600 12:40:51.396098  Dram Type= 6, Freq= 0, CH_0, rank 0

 7601 12:40:51.402857  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7602 12:40:51.402998  ==

 7603 12:40:51.403067  [Gating] SW mode calibration

 7604 12:40:51.412826  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 7605 12:40:51.416103  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 7606 12:40:51.420108   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7607 12:40:51.426145   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7608 12:40:51.430052   1  4  8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)

 7609 12:40:51.432712   1  4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)

 7610 12:40:51.439419   1  4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)

 7611 12:40:51.442726   1  4 20 | B1->B0 | 3131 3434 | 0 1 | (1 1) (1 1)

 7612 12:40:51.446133   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7613 12:40:51.453015   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7614 12:40:51.455895   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7615 12:40:51.459568   1  5  4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)

 7616 12:40:51.465794   1  5  8 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)

 7617 12:40:51.469322   1  5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)

 7618 12:40:51.472821   1  5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)

 7619 12:40:51.480064   1  5 20 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)

 7620 12:40:51.482706   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7621 12:40:51.486221   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7622 12:40:51.492624   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7623 12:40:51.495888   1  6  4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)

 7624 12:40:51.499049   1  6  8 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)

 7625 12:40:51.505768   1  6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)

 7626 12:40:51.509590   1  6 16 | B1->B0 | 2b2b 4646 | 1 0 | (0 0) (0 0)

 7627 12:40:51.512514   1  6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)

 7628 12:40:51.519207   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7629 12:40:51.522624   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7630 12:40:51.526102   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7631 12:40:51.532459   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7632 12:40:51.535786   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 7633 12:40:51.539088   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 7634 12:40:51.542286   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7635 12:40:51.549259   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7636 12:40:51.552515   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7637 12:40:51.556106   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7638 12:40:51.562472   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7639 12:40:51.565776   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7640 12:40:51.569522   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7641 12:40:51.575675   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7642 12:40:51.579198   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7643 12:40:51.582577   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7644 12:40:51.588953   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7645 12:40:51.592397   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7646 12:40:51.595764   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7647 12:40:51.602415   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7648 12:40:51.605971   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 7649 12:40:51.609099   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 7650 12:40:51.615642   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)

 7651 12:40:51.615759  Total UI for P1: 0, mck2ui 16

 7652 12:40:51.622253  best dqsien dly found for B0: ( 1,  9, 10)

 7653 12:40:51.625592   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 7654 12:40:51.629025   1  9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7655 12:40:51.632166  Total UI for P1: 0, mck2ui 16

 7656 12:40:51.635779  best dqsien dly found for B1: ( 1,  9, 20)

 7657 12:40:51.638831  best DQS0 dly(MCK, UI, PI) = (1, 9, 10)

 7658 12:40:51.641986  best DQS1 dly(MCK, UI, PI) = (1, 9, 20)

 7659 12:40:51.642078  

 7660 12:40:51.648598  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)

 7661 12:40:51.652090  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)

 7662 12:40:51.655812  [Gating] SW calibration Done

 7663 12:40:51.655906  ==

 7664 12:40:51.658617  Dram Type= 6, Freq= 0, CH_0, rank 0

 7665 12:40:51.661857  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7666 12:40:51.661952  ==

 7667 12:40:51.662023  RX Vref Scan: 0

 7668 12:40:51.662085  

 7669 12:40:51.665707  RX Vref 0 -> 0, step: 1

 7670 12:40:51.665793  

 7671 12:40:51.668674  RX Delay 0 -> 252, step: 8

 7672 12:40:51.671980  iDelay=200, Bit 0, Center 135 (88 ~ 183) 96

 7673 12:40:51.675544  iDelay=200, Bit 1, Center 139 (88 ~ 191) 104

 7674 12:40:51.678842  iDelay=200, Bit 2, Center 135 (88 ~ 183) 96

 7675 12:40:51.685218  iDelay=200, Bit 3, Center 135 (88 ~ 183) 96

 7676 12:40:51.688526  iDelay=200, Bit 4, Center 139 (88 ~ 191) 104

 7677 12:40:51.691970  iDelay=200, Bit 5, Center 123 (72 ~ 175) 104

 7678 12:40:51.695051  iDelay=200, Bit 6, Center 147 (96 ~ 199) 104

 7679 12:40:51.698731  iDelay=200, Bit 7, Center 147 (96 ~ 199) 104

 7680 12:40:51.705026  iDelay=200, Bit 8, Center 119 (64 ~ 175) 112

 7681 12:40:51.708430  iDelay=200, Bit 9, Center 115 (64 ~ 167) 104

 7682 12:40:51.712097  iDelay=200, Bit 10, Center 123 (72 ~ 175) 104

 7683 12:40:51.715157  iDelay=200, Bit 11, Center 123 (72 ~ 175) 104

 7684 12:40:51.718470  iDelay=200, Bit 12, Center 131 (80 ~ 183) 104

 7685 12:40:51.725420  iDelay=200, Bit 13, Center 127 (80 ~ 175) 96

 7686 12:40:51.728693  iDelay=200, Bit 14, Center 139 (88 ~ 191) 104

 7687 12:40:51.731696  iDelay=200, Bit 15, Center 135 (88 ~ 183) 96

 7688 12:40:51.731794  ==

 7689 12:40:51.735116  Dram Type= 6, Freq= 0, CH_0, rank 0

 7690 12:40:51.738662  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7691 12:40:51.738750  ==

 7692 12:40:51.742124  DQS Delay:

 7693 12:40:51.742210  DQS0 = 0, DQS1 = 0

 7694 12:40:51.745296  DQM Delay:

 7695 12:40:51.745384  DQM0 = 137, DQM1 = 126

 7696 12:40:51.745451  DQ Delay:

 7697 12:40:51.748414  DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135

 7698 12:40:51.755139  DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147

 7699 12:40:51.758166  DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123

 7700 12:40:51.762288  DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135

 7701 12:40:51.762382  

 7702 12:40:51.762449  

 7703 12:40:51.762510  ==

 7704 12:40:51.765065  Dram Type= 6, Freq= 0, CH_0, rank 0

 7705 12:40:51.768307  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7706 12:40:51.768394  ==

 7707 12:40:51.768459  

 7708 12:40:51.768520  

 7709 12:40:51.771791  	TX Vref Scan disable

 7710 12:40:51.774930   == TX Byte 0 ==

 7711 12:40:51.778542  Update DQ  dly =993 (3 ,6, 33)  DQ  OEN =(3 ,3)

 7712 12:40:51.781877  Update DQM dly =993 (3 ,6, 33)  DQM OEN =(3 ,3)

 7713 12:40:51.785060   == TX Byte 1 ==

 7714 12:40:51.788956  Update DQ  dly =987 (3 ,6, 27)  DQ  OEN =(3 ,3)

 7715 12:40:51.792058  Update DQM dly =987 (3 ,6, 27)  DQM OEN =(3 ,3)

 7716 12:40:51.792166  ==

 7717 12:40:51.794883  Dram Type= 6, Freq= 0, CH_0, rank 0

 7718 12:40:51.798334  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7719 12:40:51.801531  ==

 7720 12:40:51.812986  

 7721 12:40:51.816301  TX Vref early break, caculate TX vref

 7722 12:40:51.819758  TX Vref=16, minBit 0, minWin=23, winSum=378

 7723 12:40:51.823005  TX Vref=18, minBit 12, minWin=23, winSum=388

 7724 12:40:51.826799  TX Vref=20, minBit 2, minWin=24, winSum=398

 7725 12:40:51.829851  TX Vref=22, minBit 7, minWin=24, winSum=406

 7726 12:40:51.833109  TX Vref=24, minBit 0, minWin=25, winSum=412

 7727 12:40:51.839593  TX Vref=26, minBit 12, minWin=25, winSum=429

 7728 12:40:51.842929  TX Vref=28, minBit 0, minWin=26, winSum=429

 7729 12:40:51.846139  TX Vref=30, minBit 0, minWin=26, winSum=426

 7730 12:40:51.849739  TX Vref=32, minBit 0, minWin=25, winSum=412

 7731 12:40:51.853076  TX Vref=34, minBit 7, minWin=24, winSum=405

 7732 12:40:51.859874  [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 28

 7733 12:40:51.859986  

 7734 12:40:51.863460  Final TX Range 0 Vref 28

 7735 12:40:51.863552  

 7736 12:40:51.863639  ==

 7737 12:40:51.866310  Dram Type= 6, Freq= 0, CH_0, rank 0

 7738 12:40:51.869554  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7739 12:40:51.869644  ==

 7740 12:40:51.869730  

 7741 12:40:51.869831  

 7742 12:40:51.872831  	TX Vref Scan disable

 7743 12:40:51.879967  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps

 7744 12:40:51.880088   == TX Byte 0 ==

 7745 12:40:51.883145  u2DelayCellOfst[0]=13 cells (4 PI)

 7746 12:40:51.886289  u2DelayCellOfst[1]=20 cells (6 PI)

 7747 12:40:51.889535  u2DelayCellOfst[2]=13 cells (4 PI)

 7748 12:40:51.893083  u2DelayCellOfst[3]=13 cells (4 PI)

 7749 12:40:51.896256  u2DelayCellOfst[4]=10 cells (3 PI)

 7750 12:40:51.899438  u2DelayCellOfst[5]=0 cells (0 PI)

 7751 12:40:51.902637  u2DelayCellOfst[6]=20 cells (6 PI)

 7752 12:40:51.906054  u2DelayCellOfst[7]=17 cells (5 PI)

 7753 12:40:51.909501  Update DQ  dly =990 (3 ,6, 30)  DQ  OEN =(3 ,3)

 7754 12:40:51.912874  Update DQM dly =993 (3 ,6, 33)  DQM OEN =(3 ,3)

 7755 12:40:51.916078   == TX Byte 1 ==

 7756 12:40:51.916178  u2DelayCellOfst[8]=0 cells (0 PI)

 7757 12:40:51.919536  u2DelayCellOfst[9]=0 cells (0 PI)

 7758 12:40:51.922510  u2DelayCellOfst[10]=6 cells (2 PI)

 7759 12:40:51.925911  u2DelayCellOfst[11]=3 cells (1 PI)

 7760 12:40:51.929380  u2DelayCellOfst[12]=10 cells (3 PI)

 7761 12:40:51.932608  u2DelayCellOfst[13]=10 cells (3 PI)

 7762 12:40:51.935937  u2DelayCellOfst[14]=13 cells (4 PI)

 7763 12:40:51.939189  u2DelayCellOfst[15]=10 cells (3 PI)

 7764 12:40:51.942502  Update DQ  dly =984 (3 ,6, 24)  DQ  OEN =(3 ,3)

 7765 12:40:51.949137  Update DQM dly =986 (3 ,6, 26)  DQM OEN =(3 ,3)

 7766 12:40:51.949251  DramC Write-DBI on

 7767 12:40:51.949343  ==

 7768 12:40:51.952459  Dram Type= 6, Freq= 0, CH_0, rank 0

 7769 12:40:51.956627  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7770 12:40:51.959019  ==

 7771 12:40:51.959110  

 7772 12:40:51.959198  

 7773 12:40:51.959279  	TX Vref Scan disable

 7774 12:40:51.962994   == TX Byte 0 ==

 7775 12:40:51.966214  Update DQM dly =736 (2 ,6, 32)  DQM OEN =(3 ,3)

 7776 12:40:51.969448   == TX Byte 1 ==

 7777 12:40:51.972942  Update DQM dly =727 (2 ,6, 23)  DQM OEN =(3 ,3)

 7778 12:40:51.973042  DramC Write-DBI off

 7779 12:40:51.976210  

 7780 12:40:51.976307  [DATLAT]

 7781 12:40:51.976396  Freq=1600, CH0 RK0

 7782 12:40:51.976478  

 7783 12:40:51.979357  DATLAT Default: 0xf

 7784 12:40:51.979446  0, 0xFFFF, sum = 0

 7785 12:40:51.983196  1, 0xFFFF, sum = 0

 7786 12:40:51.983288  2, 0xFFFF, sum = 0

 7787 12:40:51.986418  3, 0xFFFF, sum = 0

 7788 12:40:51.986508  4, 0xFFFF, sum = 0

 7789 12:40:51.989567  5, 0xFFFF, sum = 0

 7790 12:40:51.992640  6, 0xFFFF, sum = 0

 7791 12:40:51.992730  7, 0xFFFF, sum = 0

 7792 12:40:51.995999  8, 0xFFFF, sum = 0

 7793 12:40:51.996089  9, 0xFFFF, sum = 0

 7794 12:40:51.999576  10, 0xFFFF, sum = 0

 7795 12:40:51.999666  11, 0xFFFF, sum = 0

 7796 12:40:52.003017  12, 0xFFFF, sum = 0

 7797 12:40:52.003117  13, 0xFFFF, sum = 0

 7798 12:40:52.005960  14, 0x0, sum = 1

 7799 12:40:52.006052  15, 0x0, sum = 2

 7800 12:40:52.009412  16, 0x0, sum = 3

 7801 12:40:52.009520  17, 0x0, sum = 4

 7802 12:40:52.012704  best_step = 15

 7803 12:40:52.012797  

 7804 12:40:52.012884  ==

 7805 12:40:52.016209  Dram Type= 6, Freq= 0, CH_0, rank 0

 7806 12:40:52.019622  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7807 12:40:52.019722  ==

 7808 12:40:52.019811  RX Vref Scan: 1

 7809 12:40:52.019893  

 7810 12:40:52.022717  Set Vref Range= 24 -> 127

 7811 12:40:52.022807  

 7812 12:40:52.026120  RX Vref 24 -> 127, step: 1

 7813 12:40:52.026209  

 7814 12:40:52.029554  RX Delay 19 -> 252, step: 4

 7815 12:40:52.029649  

 7816 12:40:52.032830  Set Vref, RX VrefLevel [Byte0]: 24

 7817 12:40:52.036114                           [Byte1]: 24

 7818 12:40:52.036206  

 7819 12:40:52.039494  Set Vref, RX VrefLevel [Byte0]: 25

 7820 12:40:52.042913                           [Byte1]: 25

 7821 12:40:52.043010  

 7822 12:40:52.045962  Set Vref, RX VrefLevel [Byte0]: 26

 7823 12:40:52.049795                           [Byte1]: 26

 7824 12:40:52.052886  

 7825 12:40:52.052982  Set Vref, RX VrefLevel [Byte0]: 27

 7826 12:40:52.056558                           [Byte1]: 27

 7827 12:40:52.060831  

 7828 12:40:52.060925  Set Vref, RX VrefLevel [Byte0]: 28

 7829 12:40:52.063909                           [Byte1]: 28

 7830 12:40:52.068167  

 7831 12:40:52.068260  Set Vref, RX VrefLevel [Byte0]: 29

 7832 12:40:52.071516                           [Byte1]: 29

 7833 12:40:52.076186  

 7834 12:40:52.076298  Set Vref, RX VrefLevel [Byte0]: 30

 7835 12:40:52.079294                           [Byte1]: 30

 7836 12:40:52.083377  

 7837 12:40:52.083472  Set Vref, RX VrefLevel [Byte0]: 31

 7838 12:40:52.086914                           [Byte1]: 31

 7839 12:40:52.091258  

 7840 12:40:52.091350  Set Vref, RX VrefLevel [Byte0]: 32

 7841 12:40:52.094125                           [Byte1]: 32

 7842 12:40:52.098383  

 7843 12:40:52.098484  Set Vref, RX VrefLevel [Byte0]: 33

 7844 12:40:52.101784                           [Byte1]: 33

 7845 12:40:52.106129  

 7846 12:40:52.106220  Set Vref, RX VrefLevel [Byte0]: 34

 7847 12:40:52.109471                           [Byte1]: 34

 7848 12:40:52.113640  

 7849 12:40:52.113734  Set Vref, RX VrefLevel [Byte0]: 35

 7850 12:40:52.117083                           [Byte1]: 35

 7851 12:40:52.121393  

 7852 12:40:52.121492  Set Vref, RX VrefLevel [Byte0]: 36

 7853 12:40:52.124698                           [Byte1]: 36

 7854 12:40:52.128861  

 7855 12:40:52.128956  Set Vref, RX VrefLevel [Byte0]: 37

 7856 12:40:52.132042                           [Byte1]: 37

 7857 12:40:52.136399  

 7858 12:40:52.136498  Set Vref, RX VrefLevel [Byte0]: 38

 7859 12:40:52.139465                           [Byte1]: 38

 7860 12:40:52.144121  

 7861 12:40:52.144217  Set Vref, RX VrefLevel [Byte0]: 39

 7862 12:40:52.147288                           [Byte1]: 39

 7863 12:40:52.151635  

 7864 12:40:52.151782  Set Vref, RX VrefLevel [Byte0]: 40

 7865 12:40:52.155059                           [Byte1]: 40

 7866 12:40:52.159133  

 7867 12:40:52.159227  Set Vref, RX VrefLevel [Byte0]: 41

 7868 12:40:52.162349                           [Byte1]: 41

 7869 12:40:52.166920  

 7870 12:40:52.167014  Set Vref, RX VrefLevel [Byte0]: 42

 7871 12:40:52.170224                           [Byte1]: 42

 7872 12:40:52.174150  

 7873 12:40:52.174243  Set Vref, RX VrefLevel [Byte0]: 43

 7874 12:40:52.177635                           [Byte1]: 43

 7875 12:40:52.181841  

 7876 12:40:52.181954  Set Vref, RX VrefLevel [Byte0]: 44

 7877 12:40:52.185363                           [Byte1]: 44

 7878 12:40:52.189294  

 7879 12:40:52.189390  Set Vref, RX VrefLevel [Byte0]: 45

 7880 12:40:52.192683                           [Byte1]: 45

 7881 12:40:52.196835  

 7882 12:40:52.196925  Set Vref, RX VrefLevel [Byte0]: 46

 7883 12:40:52.200312                           [Byte1]: 46

 7884 12:40:52.204565  

 7885 12:40:52.204670  Set Vref, RX VrefLevel [Byte0]: 47

 7886 12:40:52.207773                           [Byte1]: 47

 7887 12:40:52.211966  

 7888 12:40:52.212068  Set Vref, RX VrefLevel [Byte0]: 48

 7889 12:40:52.215384                           [Byte1]: 48

 7890 12:40:52.219659  

 7891 12:40:52.219756  Set Vref, RX VrefLevel [Byte0]: 49

 7892 12:40:52.222868                           [Byte1]: 49

 7893 12:40:52.227064  

 7894 12:40:52.227176  Set Vref, RX VrefLevel [Byte0]: 50

 7895 12:40:52.230329                           [Byte1]: 50

 7896 12:40:52.234900  

 7897 12:40:52.234996  Set Vref, RX VrefLevel [Byte0]: 51

 7898 12:40:52.238483                           [Byte1]: 51

 7899 12:40:52.242330  

 7900 12:40:52.242423  Set Vref, RX VrefLevel [Byte0]: 52

 7901 12:40:52.245742                           [Byte1]: 52

 7902 12:40:52.249892  

 7903 12:40:52.250012  Set Vref, RX VrefLevel [Byte0]: 53

 7904 12:40:52.253248                           [Byte1]: 53

 7905 12:40:52.257387  

 7906 12:40:52.257481  Set Vref, RX VrefLevel [Byte0]: 54

 7907 12:40:52.260775                           [Byte1]: 54

 7908 12:40:52.264871  

 7909 12:40:52.265003  Set Vref, RX VrefLevel [Byte0]: 55

 7910 12:40:52.268349                           [Byte1]: 55

 7911 12:40:52.272568  

 7912 12:40:52.272656  Set Vref, RX VrefLevel [Byte0]: 56

 7913 12:40:52.276188                           [Byte1]: 56

 7914 12:40:52.280100  

 7915 12:40:52.280189  Set Vref, RX VrefLevel [Byte0]: 57

 7916 12:40:52.283565                           [Byte1]: 57

 7917 12:40:52.287644  

 7918 12:40:52.287743  Set Vref, RX VrefLevel [Byte0]: 58

 7919 12:40:52.290996                           [Byte1]: 58

 7920 12:40:52.295710  

 7921 12:40:52.295792  Set Vref, RX VrefLevel [Byte0]: 59

 7922 12:40:52.299057                           [Byte1]: 59

 7923 12:40:52.303118  

 7924 12:40:52.303203  Set Vref, RX VrefLevel [Byte0]: 60

 7925 12:40:52.306228                           [Byte1]: 60

 7926 12:40:52.310674  

 7927 12:40:52.310768  Set Vref, RX VrefLevel [Byte0]: 61

 7928 12:40:52.313732                           [Byte1]: 61

 7929 12:40:52.318123  

 7930 12:40:52.318217  Set Vref, RX VrefLevel [Byte0]: 62

 7931 12:40:52.321859                           [Byte1]: 62

 7932 12:40:52.325841  

 7933 12:40:52.325945  Set Vref, RX VrefLevel [Byte0]: 63

 7934 12:40:52.328987                           [Byte1]: 63

 7935 12:40:52.333234  

 7936 12:40:52.333321  Set Vref, RX VrefLevel [Byte0]: 64

 7937 12:40:52.336573                           [Byte1]: 64

 7938 12:40:52.340894  

 7939 12:40:52.341018  Set Vref, RX VrefLevel [Byte0]: 65

 7940 12:40:52.344173                           [Byte1]: 65

 7941 12:40:52.348164  

 7942 12:40:52.351490  Set Vref, RX VrefLevel [Byte0]: 66

 7943 12:40:52.354740                           [Byte1]: 66

 7944 12:40:52.354829  

 7945 12:40:52.358388  Set Vref, RX VrefLevel [Byte0]: 67

 7946 12:40:52.361546                           [Byte1]: 67

 7947 12:40:52.361666  

 7948 12:40:52.365011  Set Vref, RX VrefLevel [Byte0]: 68

 7949 12:40:52.368358                           [Byte1]: 68

 7950 12:40:52.368455  

 7951 12:40:52.371522  Set Vref, RX VrefLevel [Byte0]: 69

 7952 12:40:52.375045                           [Byte1]: 69

 7953 12:40:52.378953  

 7954 12:40:52.379056  Set Vref, RX VrefLevel [Byte0]: 70

 7955 12:40:52.381935                           [Byte1]: 70

 7956 12:40:52.386356  

 7957 12:40:52.386480  Set Vref, RX VrefLevel [Byte0]: 71

 7958 12:40:52.389854                           [Byte1]: 71

 7959 12:40:52.393866  

 7960 12:40:52.394002  Set Vref, RX VrefLevel [Byte0]: 72

 7961 12:40:52.397252                           [Byte1]: 72

 7962 12:40:52.401690  

 7963 12:40:52.401786  Set Vref, RX VrefLevel [Byte0]: 73

 7964 12:40:52.404566                           [Byte1]: 73

 7965 12:40:52.408885  

 7966 12:40:52.408977  Set Vref, RX VrefLevel [Byte0]: 74

 7967 12:40:52.412361                           [Byte1]: 74

 7968 12:40:52.416457  

 7969 12:40:52.416552  Set Vref, RX VrefLevel [Byte0]: 75

 7970 12:40:52.419849                           [Byte1]: 75

 7971 12:40:52.424525  

 7972 12:40:52.424625  Set Vref, RX VrefLevel [Byte0]: 76

 7973 12:40:52.427390                           [Byte1]: 76

 7974 12:40:52.431791  

 7975 12:40:52.431884  Set Vref, RX VrefLevel [Byte0]: 77

 7976 12:40:52.434954                           [Byte1]: 77

 7977 12:40:52.439083  

 7978 12:40:52.439177  Set Vref, RX VrefLevel [Byte0]: 78

 7979 12:40:52.442504                           [Byte1]: 78

 7980 12:40:52.446863  

 7981 12:40:52.446957  Set Vref, RX VrefLevel [Byte0]: 79

 7982 12:40:52.450169                           [Byte1]: 79

 7983 12:40:52.454339  

 7984 12:40:52.454436  Set Vref, RX VrefLevel [Byte0]: 80

 7985 12:40:52.457635                           [Byte1]: 80

 7986 12:40:52.461890  

 7987 12:40:52.462004  Final RX Vref Byte 0 = 58 to rank0

 7988 12:40:52.465215  Final RX Vref Byte 1 = 62 to rank0

 7989 12:40:52.468637  Final RX Vref Byte 0 = 58 to rank1

 7990 12:40:52.471899  Final RX Vref Byte 1 = 62 to rank1==

 7991 12:40:52.475229  Dram Type= 6, Freq= 0, CH_0, rank 0

 7992 12:40:52.481721  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7993 12:40:52.481879  ==

 7994 12:40:52.482020  DQS Delay:

 7995 12:40:52.485226  DQS0 = 0, DQS1 = 0

 7996 12:40:52.485311  DQM Delay:

 7997 12:40:52.485397  DQM0 = 136, DQM1 = 125

 7998 12:40:52.488515  DQ Delay:

 7999 12:40:52.491422  DQ0 =136, DQ1 =140, DQ2 =132, DQ3 =132

 8000 12:40:52.494907  DQ4 =140, DQ5 =124, DQ6 =142, DQ7 =144

 8001 12:40:52.498437  DQ8 =116, DQ9 =114, DQ10 =128, DQ11 =120

 8002 12:40:52.501627  DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =134

 8003 12:40:52.501709  

 8004 12:40:52.501811  

 8005 12:40:52.501909  

 8006 12:40:52.504900  [DramC_TX_OE_Calibration] TA2

 8007 12:40:52.508487  Original DQ_B0 (3 6) =30, OEN = 27

 8008 12:40:52.511421  Original DQ_B1 (3 6) =30, OEN = 27

 8009 12:40:52.514860  24, 0x0, End_B0=24 End_B1=24

 8010 12:40:52.514945  25, 0x0, End_B0=25 End_B1=25

 8011 12:40:52.518192  26, 0x0, End_B0=26 End_B1=26

 8012 12:40:52.521806  27, 0x0, End_B0=27 End_B1=27

 8013 12:40:52.524642  28, 0x0, End_B0=28 End_B1=28

 8014 12:40:52.528188  29, 0x0, End_B0=29 End_B1=29

 8015 12:40:52.528304  30, 0x0, End_B0=30 End_B1=30

 8016 12:40:52.531483  31, 0x5151, End_B0=30 End_B1=30

 8017 12:40:52.534783  Byte0 end_step=30  best_step=27

 8018 12:40:52.538314  Byte1 end_step=30  best_step=27

 8019 12:40:52.541702  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8020 12:40:52.544804  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8021 12:40:52.544888  

 8022 12:40:52.544971  

 8023 12:40:52.552084  [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps

 8024 12:40:52.554804  CH0 RK0: MR19=303, MR18=1C1A

 8025 12:40:52.561140  CH0_RK0: MR19=0x303, MR18=0x1C1A, DQSOSC=395, MR23=63, INC=23, DEC=15

 8026 12:40:52.561272  

 8027 12:40:52.564516  ----->DramcWriteLeveling(PI) begin...

 8028 12:40:52.564606  ==

 8029 12:40:52.568092  Dram Type= 6, Freq= 0, CH_0, rank 1

 8030 12:40:52.571481  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8031 12:40:52.571611  ==

 8032 12:40:52.574527  Write leveling (Byte 0): 36 => 36

 8033 12:40:52.578383  Write leveling (Byte 1): 29 => 29

 8034 12:40:52.581435  DramcWriteLeveling(PI) end<-----

 8035 12:40:52.581565  

 8036 12:40:52.581663  ==

 8037 12:40:52.584739  Dram Type= 6, Freq= 0, CH_0, rank 1

 8038 12:40:52.588165  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8039 12:40:52.588296  ==

 8040 12:40:52.591337  [Gating] SW mode calibration

 8041 12:40:52.597871  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8042 12:40:52.604959  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8043 12:40:52.607743   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8044 12:40:52.614440   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8045 12:40:52.617562   1  4  8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)

 8046 12:40:52.620903   1  4 12 | B1->B0 | 2828 3232 | 0 1 | (0 0) (0 0)

 8047 12:40:52.627516   1  4 16 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)

 8048 12:40:52.630957   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8049 12:40:52.634298   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8050 12:40:52.637473   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8051 12:40:52.644231   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8052 12:40:52.647418   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8053 12:40:52.650794   1  5  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 8054 12:40:52.657461   1  5 12 | B1->B0 | 3434 2b2b | 1 1 | (1 0) (1 0)

 8055 12:40:52.660833   1  5 16 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)

 8056 12:40:52.664248   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8057 12:40:52.670602   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8058 12:40:52.674043   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8059 12:40:52.677604   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8060 12:40:52.684114   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8061 12:40:52.687775   1  6  8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)

 8062 12:40:52.690975   1  6 12 | B1->B0 | 2d2c 4444 | 1 0 | (0 0) (0 0)

 8063 12:40:52.697480   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8064 12:40:52.701188   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8065 12:40:52.703959   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8066 12:40:52.710893   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8067 12:40:52.714014   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8068 12:40:52.717627   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8069 12:40:52.724042   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8070 12:40:52.727290   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8071 12:40:52.730550   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8072 12:40:52.737229   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8073 12:40:52.740589   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8074 12:40:52.743808   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8075 12:40:52.747848   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8076 12:40:52.754367   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8077 12:40:52.757599   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8078 12:40:52.760574   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8079 12:40:52.767150   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8080 12:40:52.770648   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8081 12:40:52.774618   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8082 12:40:52.780802   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8083 12:40:52.784006   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8084 12:40:52.787767   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8085 12:40:52.794200   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8086 12:40:52.797700   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8087 12:40:52.800593   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8088 12:40:52.803962  Total UI for P1: 0, mck2ui 16

 8089 12:40:52.807394  best dqsien dly found for B0: ( 1,  9, 10)

 8090 12:40:52.810571  Total UI for P1: 0, mck2ui 16

 8091 12:40:52.814218  best dqsien dly found for B1: ( 1,  9, 12)

 8092 12:40:52.817637  best DQS0 dly(MCK, UI, PI) = (1, 9, 10)

 8093 12:40:52.820569  best DQS1 dly(MCK, UI, PI) = (1, 9, 12)

 8094 12:40:52.820660  

 8095 12:40:52.827081  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8096 12:40:52.830612  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)

 8097 12:40:52.834200  [Gating] SW calibration Done

 8098 12:40:52.834292  ==

 8099 12:40:52.837103  Dram Type= 6, Freq= 0, CH_0, rank 1

 8100 12:40:52.840928  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8101 12:40:52.841017  ==

 8102 12:40:52.841084  RX Vref Scan: 0

 8103 12:40:52.841145  

 8104 12:40:52.844124  RX Vref 0 -> 0, step: 1

 8105 12:40:52.844210  

 8106 12:40:52.847408  RX Delay 0 -> 252, step: 8

 8107 12:40:52.850717  iDelay=200, Bit 0, Center 135 (80 ~ 191) 112

 8108 12:40:52.854210  iDelay=200, Bit 1, Center 139 (88 ~ 191) 104

 8109 12:40:52.857207  iDelay=200, Bit 2, Center 135 (80 ~ 191) 112

 8110 12:40:52.863827  iDelay=200, Bit 3, Center 131 (80 ~ 183) 104

 8111 12:40:52.867330  iDelay=200, Bit 4, Center 139 (88 ~ 191) 104

 8112 12:40:52.870340  iDelay=200, Bit 5, Center 127 (72 ~ 183) 112

 8113 12:40:52.874206  iDelay=200, Bit 6, Center 143 (88 ~ 199) 112

 8114 12:40:52.876997  iDelay=200, Bit 7, Center 143 (88 ~ 199) 112

 8115 12:40:52.883567  iDelay=200, Bit 8, Center 115 (64 ~ 167) 104

 8116 12:40:52.887020  iDelay=200, Bit 9, Center 111 (56 ~ 167) 112

 8117 12:40:52.890323  iDelay=200, Bit 10, Center 127 (80 ~ 175) 96

 8118 12:40:52.893752  iDelay=200, Bit 11, Center 123 (72 ~ 175) 104

 8119 12:40:52.897309  iDelay=200, Bit 12, Center 127 (72 ~ 183) 112

 8120 12:40:52.903935  iDelay=200, Bit 13, Center 131 (80 ~ 183) 104

 8121 12:40:52.906886  iDelay=200, Bit 14, Center 135 (80 ~ 191) 112

 8122 12:40:52.910387  iDelay=200, Bit 15, Center 135 (80 ~ 191) 112

 8123 12:40:52.910484  ==

 8124 12:40:52.914087  Dram Type= 6, Freq= 0, CH_0, rank 1

 8125 12:40:52.917130  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8126 12:40:52.920617  ==

 8127 12:40:52.920713  DQS Delay:

 8128 12:40:52.920781  DQS0 = 0, DQS1 = 0

 8129 12:40:52.924228  DQM Delay:

 8130 12:40:52.924315  DQM0 = 136, DQM1 = 125

 8131 12:40:52.927655  DQ Delay:

 8132 12:40:52.930528  DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131

 8133 12:40:52.933726  DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143

 8134 12:40:52.936878  DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =123

 8135 12:40:52.940539  DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135

 8136 12:40:52.940633  

 8137 12:40:52.940700  

 8138 12:40:52.940759  ==

 8139 12:40:52.943923  Dram Type= 6, Freq= 0, CH_0, rank 1

 8140 12:40:52.947019  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8141 12:40:52.947111  ==

 8142 12:40:52.947178  

 8143 12:40:52.947239  

 8144 12:40:52.950749  	TX Vref Scan disable

 8145 12:40:52.953440   == TX Byte 0 ==

 8146 12:40:52.956691  Update DQ  dly =992 (3 ,6, 32)  DQ  OEN =(3 ,3)

 8147 12:40:52.960499  Update DQM dly =992 (3 ,6, 32)  DQM OEN =(3 ,3)

 8148 12:40:52.964205   == TX Byte 1 ==

 8149 12:40:52.967258  Update DQ  dly =983 (3 ,6, 23)  DQ  OEN =(3 ,3)

 8150 12:40:52.970369  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8151 12:40:52.970463  ==

 8152 12:40:52.973823  Dram Type= 6, Freq= 0, CH_0, rank 1

 8153 12:40:52.977256  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8154 12:40:52.980397  ==

 8155 12:40:52.993355  

 8156 12:40:52.996970  TX Vref early break, caculate TX vref

 8157 12:40:53.000038  TX Vref=16, minBit 12, minWin=23, winSum=390

 8158 12:40:53.003284  TX Vref=18, minBit 0, minWin=23, winSum=394

 8159 12:40:53.006714  TX Vref=20, minBit 0, minWin=24, winSum=403

 8160 12:40:53.010110  TX Vref=22, minBit 8, minWin=24, winSum=411

 8161 12:40:53.013371  TX Vref=24, minBit 0, minWin=25, winSum=418

 8162 12:40:53.020175  TX Vref=26, minBit 8, minWin=25, winSum=428

 8163 12:40:53.023168  TX Vref=28, minBit 0, minWin=26, winSum=429

 8164 12:40:53.026938  TX Vref=30, minBit 3, minWin=25, winSum=424

 8165 12:40:53.030177  TX Vref=32, minBit 0, minWin=25, winSum=414

 8166 12:40:53.033158  TX Vref=34, minBit 1, minWin=24, winSum=408

 8167 12:40:53.036536  TX Vref=36, minBit 0, minWin=24, winSum=404

 8168 12:40:53.043213  [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 28

 8169 12:40:53.043328  

 8170 12:40:53.046825  Final TX Range 0 Vref 28

 8171 12:40:53.046949  

 8172 12:40:53.047051  ==

 8173 12:40:53.049814  Dram Type= 6, Freq= 0, CH_0, rank 1

 8174 12:40:53.053524  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8175 12:40:53.053616  ==

 8176 12:40:53.053684  

 8177 12:40:53.053745  

 8178 12:40:53.056621  	TX Vref Scan disable

 8179 12:40:53.063161  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps

 8180 12:40:53.063286   == TX Byte 0 ==

 8181 12:40:53.066785  u2DelayCellOfst[0]=10 cells (3 PI)

 8182 12:40:53.070135  u2DelayCellOfst[1]=17 cells (5 PI)

 8183 12:40:53.073095  u2DelayCellOfst[2]=13 cells (4 PI)

 8184 12:40:53.076422  u2DelayCellOfst[3]=13 cells (4 PI)

 8185 12:40:53.079872  u2DelayCellOfst[4]=6 cells (2 PI)

 8186 12:40:53.083301  u2DelayCellOfst[5]=0 cells (0 PI)

 8187 12:40:53.086566  u2DelayCellOfst[6]=17 cells (5 PI)

 8188 12:40:53.089665  u2DelayCellOfst[7]=17 cells (5 PI)

 8189 12:40:53.093309  Update DQ  dly =990 (3 ,6, 30)  DQ  OEN =(3 ,3)

 8190 12:40:53.096429  Update DQM dly =992 (3 ,6, 32)  DQM OEN =(3 ,3)

 8191 12:40:53.099698   == TX Byte 1 ==

 8192 12:40:53.102980  u2DelayCellOfst[8]=0 cells (0 PI)

 8193 12:40:53.106544  u2DelayCellOfst[9]=0 cells (0 PI)

 8194 12:40:53.106642  u2DelayCellOfst[10]=6 cells (2 PI)

 8195 12:40:53.109709  u2DelayCellOfst[11]=3 cells (1 PI)

 8196 12:40:53.113154  u2DelayCellOfst[12]=13 cells (4 PI)

 8197 12:40:53.116327  u2DelayCellOfst[13]=10 cells (3 PI)

 8198 12:40:53.119592  u2DelayCellOfst[14]=17 cells (5 PI)

 8199 12:40:53.122900  u2DelayCellOfst[15]=10 cells (3 PI)

 8200 12:40:53.129802  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 8201 12:40:53.132758  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8202 12:40:53.132846  DramC Write-DBI on

 8203 12:40:53.132932  ==

 8204 12:40:53.136274  Dram Type= 6, Freq= 0, CH_0, rank 1

 8205 12:40:53.142717  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8206 12:40:53.142827  ==

 8207 12:40:53.142916  

 8208 12:40:53.142998  

 8209 12:40:53.143077  	TX Vref Scan disable

 8210 12:40:53.147091   == TX Byte 0 ==

 8211 12:40:53.150567  Update DQM dly =735 (2 ,6, 31)  DQM OEN =(3 ,3)

 8212 12:40:53.153541   == TX Byte 1 ==

 8213 12:40:53.156936  Update DQM dly =725 (2 ,6, 21)  DQM OEN =(3 ,3)

 8214 12:40:53.157033  DramC Write-DBI off

 8215 12:40:53.160330  

 8216 12:40:53.160421  [DATLAT]

 8217 12:40:53.160510  Freq=1600, CH0 RK1

 8218 12:40:53.160592  

 8219 12:40:53.163464  DATLAT Default: 0xf

 8220 12:40:53.163579  0, 0xFFFF, sum = 0

 8221 12:40:53.167085  1, 0xFFFF, sum = 0

 8222 12:40:53.167180  2, 0xFFFF, sum = 0

 8223 12:40:53.170243  3, 0xFFFF, sum = 0

 8224 12:40:53.173676  4, 0xFFFF, sum = 0

 8225 12:40:53.173770  5, 0xFFFF, sum = 0

 8226 12:40:53.177320  6, 0xFFFF, sum = 0

 8227 12:40:53.177422  7, 0xFFFF, sum = 0

 8228 12:40:53.180529  8, 0xFFFF, sum = 0

 8229 12:40:53.180622  9, 0xFFFF, sum = 0

 8230 12:40:53.183824  10, 0xFFFF, sum = 0

 8231 12:40:53.183915  11, 0xFFFF, sum = 0

 8232 12:40:53.187349  12, 0xFFFF, sum = 0

 8233 12:40:53.187445  13, 0xFFFF, sum = 0

 8234 12:40:53.190379  14, 0x0, sum = 1

 8235 12:40:53.190473  15, 0x0, sum = 2

 8236 12:40:53.193693  16, 0x0, sum = 3

 8237 12:40:53.193812  17, 0x0, sum = 4

 8238 12:40:53.196881  best_step = 15

 8239 12:40:53.196971  

 8240 12:40:53.197059  ==

 8241 12:40:53.200609  Dram Type= 6, Freq= 0, CH_0, rank 1

 8242 12:40:53.203639  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8243 12:40:53.203734  ==

 8244 12:40:53.203823  RX Vref Scan: 0

 8245 12:40:53.206640  

 8246 12:40:53.206758  RX Vref 0 -> 0, step: 1

 8247 12:40:53.206847  

 8248 12:40:53.210235  RX Delay 11 -> 252, step: 4

 8249 12:40:53.213617  iDelay=191, Bit 0, Center 132 (83 ~ 182) 100

 8250 12:40:53.220577  iDelay=191, Bit 1, Center 136 (87 ~ 186) 100

 8251 12:40:53.224019  iDelay=191, Bit 2, Center 128 (79 ~ 178) 100

 8252 12:40:53.226699  iDelay=191, Bit 3, Center 130 (83 ~ 178) 96

 8253 12:40:53.230315  iDelay=191, Bit 4, Center 134 (87 ~ 182) 96

 8254 12:40:53.233365  iDelay=191, Bit 5, Center 124 (75 ~ 174) 100

 8255 12:40:53.236946  iDelay=191, Bit 6, Center 140 (91 ~ 190) 100

 8256 12:40:53.243464  iDelay=191, Bit 7, Center 140 (91 ~ 190) 100

 8257 12:40:53.246695  iDelay=191, Bit 8, Center 116 (67 ~ 166) 100

 8258 12:40:53.250064  iDelay=191, Bit 9, Center 110 (59 ~ 162) 104

 8259 12:40:53.253343  iDelay=191, Bit 10, Center 124 (75 ~ 174) 100

 8260 12:40:53.259740  iDelay=191, Bit 11, Center 120 (71 ~ 170) 100

 8261 12:40:53.263193  iDelay=191, Bit 12, Center 128 (75 ~ 182) 108

 8262 12:40:53.266573  iDelay=191, Bit 13, Center 128 (79 ~ 178) 100

 8263 12:40:53.269697  iDelay=191, Bit 14, Center 132 (79 ~ 186) 108

 8264 12:40:53.272897  iDelay=191, Bit 15, Center 130 (79 ~ 182) 104

 8265 12:40:53.276270  ==

 8266 12:40:53.276373  Dram Type= 6, Freq= 0, CH_0, rank 1

 8267 12:40:53.283106  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8268 12:40:53.283217  ==

 8269 12:40:53.283289  DQS Delay:

 8270 12:40:53.286141  DQS0 = 0, DQS1 = 0

 8271 12:40:53.286229  DQM Delay:

 8272 12:40:53.289729  DQM0 = 133, DQM1 = 123

 8273 12:40:53.289820  DQ Delay:

 8274 12:40:53.293077  DQ0 =132, DQ1 =136, DQ2 =128, DQ3 =130

 8275 12:40:53.296179  DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140

 8276 12:40:53.299631  DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120

 8277 12:40:53.303103  DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130

 8278 12:40:53.303200  

 8279 12:40:53.303266  

 8280 12:40:53.303327  

 8281 12:40:53.306114  [DramC_TX_OE_Calibration] TA2

 8282 12:40:53.309537  Original DQ_B0 (3 6) =30, OEN = 27

 8283 12:40:53.312736  Original DQ_B1 (3 6) =30, OEN = 27

 8284 12:40:53.316250  24, 0x0, End_B0=24 End_B1=24

 8285 12:40:53.319463  25, 0x0, End_B0=25 End_B1=25

 8286 12:40:53.319564  26, 0x0, End_B0=26 End_B1=26

 8287 12:40:53.323234  27, 0x0, End_B0=27 End_B1=27

 8288 12:40:53.326134  28, 0x0, End_B0=28 End_B1=28

 8289 12:40:53.329295  29, 0x0, End_B0=29 End_B1=29

 8290 12:40:53.329391  30, 0x0, End_B0=30 End_B1=30

 8291 12:40:53.333005  31, 0x4141, End_B0=30 End_B1=30

 8292 12:40:53.336020  Byte0 end_step=30  best_step=27

 8293 12:40:53.339495  Byte1 end_step=30  best_step=27

 8294 12:40:53.343302  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8295 12:40:53.345876  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8296 12:40:53.346006  

 8297 12:40:53.346074  

 8298 12:40:53.352632  [DQSOSCAuto] RK1, (LSB)MR18= 0x1f0b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 394 ps

 8299 12:40:53.355764  CH0 RK1: MR19=303, MR18=1F0B

 8300 12:40:53.362859  CH0_RK1: MR19=0x303, MR18=0x1F0B, DQSOSC=394, MR23=63, INC=23, DEC=15

 8301 12:40:53.365770  [RxdqsGatingPostProcess] freq 1600

 8302 12:40:53.372658  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 8303 12:40:53.372773  best DQS0 dly(2T, 0.5T) = (1, 1)

 8304 12:40:53.375855  best DQS1 dly(2T, 0.5T) = (1, 1)

 8305 12:40:53.379122  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8306 12:40:53.382187  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8307 12:40:53.385832  best DQS0 dly(2T, 0.5T) = (1, 1)

 8308 12:40:53.388936  best DQS1 dly(2T, 0.5T) = (1, 1)

 8309 12:40:53.392249  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8310 12:40:53.395567  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8311 12:40:53.399207  Pre-setting of DQS Precalculation

 8312 12:40:53.402420  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 8313 12:40:53.402514  ==

 8314 12:40:53.405662  Dram Type= 6, Freq= 0, CH_1, rank 0

 8315 12:40:53.412090  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8316 12:40:53.412199  ==

 8317 12:40:53.415653  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8318 12:40:53.422563  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8319 12:40:53.425356  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8320 12:40:53.432658  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8321 12:40:53.439703  [CA 0] Center 40 (11~70) winsize 60

 8322 12:40:53.443093  [CA 1] Center 41 (11~71) winsize 61

 8323 12:40:53.446667  [CA 2] Center 37 (8~67) winsize 60

 8324 12:40:53.450149  [CA 3] Center 36 (7~66) winsize 60

 8325 12:40:53.452808  [CA 4] Center 36 (7~66) winsize 60

 8326 12:40:53.456493  [CA 5] Center 36 (6~66) winsize 61

 8327 12:40:53.456592  

 8328 12:40:53.459889  [CmdBusTrainingLP45] Vref(ca) range 0: 30

 8329 12:40:53.459982  

 8330 12:40:53.463220  [CATrainingPosCal] consider 1 rank data

 8331 12:40:53.466314  u2DelayCellTimex100 = 285/100 ps

 8332 12:40:53.470070  CA0 delay=40 (11~70),Diff = 4 PI (13 cell)

 8333 12:40:53.476381  CA1 delay=41 (11~71),Diff = 5 PI (17 cell)

 8334 12:40:53.479721  CA2 delay=37 (8~67),Diff = 1 PI (3 cell)

 8335 12:40:53.483431  CA3 delay=36 (7~66),Diff = 0 PI (0 cell)

 8336 12:40:53.486393  CA4 delay=36 (7~66),Diff = 0 PI (0 cell)

 8337 12:40:53.489436  CA5 delay=36 (6~66),Diff = 0 PI (0 cell)

 8338 12:40:53.489531  

 8339 12:40:53.493178  CA PerBit enable=1, Macro0, CA PI delay=36

 8340 12:40:53.493268  

 8341 12:40:53.496276  [CBTSetCACLKResult] CA Dly = 36

 8342 12:40:53.499539  CS Dly: 9 (0~40)

 8343 12:40:53.502963  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8344 12:40:53.506443  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8345 12:40:53.506537  ==

 8346 12:40:53.509752  Dram Type= 6, Freq= 0, CH_1, rank 1

 8347 12:40:53.513068  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8348 12:40:53.513170  ==

 8349 12:40:53.520097  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8350 12:40:53.522921  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8351 12:40:53.529444  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8352 12:40:53.532940  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8353 12:40:53.542812  [CA 0] Center 42 (13~72) winsize 60

 8354 12:40:53.546154  [CA 1] Center 42 (12~72) winsize 61

 8355 12:40:53.549625  [CA 2] Center 38 (9~68) winsize 60

 8356 12:40:53.552806  [CA 3] Center 37 (8~67) winsize 60

 8357 12:40:53.556628  [CA 4] Center 38 (9~68) winsize 60

 8358 12:40:53.559846  [CA 5] Center 37 (8~67) winsize 60

 8359 12:40:53.559971  

 8360 12:40:53.563040  [CmdBusTrainingLP45] Vref(ca) range 0: 30

 8361 12:40:53.563130  

 8362 12:40:53.566224  [CATrainingPosCal] consider 2 rank data

 8363 12:40:53.569797  u2DelayCellTimex100 = 285/100 ps

 8364 12:40:53.572920  CA0 delay=41 (13~70),Diff = 4 PI (13 cell)

 8365 12:40:53.580039  CA1 delay=41 (12~71),Diff = 4 PI (13 cell)

 8366 12:40:53.583301  CA2 delay=38 (9~67),Diff = 1 PI (3 cell)

 8367 12:40:53.586213  CA3 delay=37 (8~66),Diff = 0 PI (0 cell)

 8368 12:40:53.589661  CA4 delay=37 (9~66),Diff = 0 PI (0 cell)

 8369 12:40:53.592772  CA5 delay=37 (8~66),Diff = 0 PI (0 cell)

 8370 12:40:53.592867  

 8371 12:40:53.596233  CA PerBit enable=1, Macro0, CA PI delay=37

 8372 12:40:53.596321  

 8373 12:40:53.599343  [CBTSetCACLKResult] CA Dly = 37

 8374 12:40:53.602603  CS Dly: 10 (0~42)

 8375 12:40:53.606326  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8376 12:40:53.609787  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8377 12:40:53.609911  

 8378 12:40:53.613008  ----->DramcWriteLeveling(PI) begin...

 8379 12:40:53.613098  ==

 8380 12:40:53.616133  Dram Type= 6, Freq= 0, CH_1, rank 0

 8381 12:40:53.619845  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8382 12:40:53.622936  ==

 8383 12:40:53.623057  Write leveling (Byte 0): 24 => 24

 8384 12:40:53.626433  Write leveling (Byte 1): 28 => 28

 8385 12:40:53.629531  DramcWriteLeveling(PI) end<-----

 8386 12:40:53.629646  

 8387 12:40:53.629739  ==

 8388 12:40:53.632908  Dram Type= 6, Freq= 0, CH_1, rank 0

 8389 12:40:53.639073  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8390 12:40:53.639183  ==

 8391 12:40:53.639250  [Gating] SW mode calibration

 8392 12:40:53.649363  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8393 12:40:53.652664  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8394 12:40:53.659294   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8395 12:40:53.662530   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8396 12:40:53.665786   1  4  8 | B1->B0 | 2e2e 3232 | 0 1 | (0 0) (1 1)

 8397 12:40:53.672640   1  4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8398 12:40:53.675783   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8399 12:40:53.679171   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8400 12:40:53.682289   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8401 12:40:53.689094   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8402 12:40:53.692227   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8403 12:40:53.695616   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 8404 12:40:53.702118   1  5  8 | B1->B0 | 2c2c 2525 | 0 0 | (0 1) (1 0)

 8405 12:40:53.705871   1  5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 8406 12:40:53.709334   1  5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8407 12:40:53.715968   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8408 12:40:53.719146   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8409 12:40:53.722672   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8410 12:40:53.728854   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8411 12:40:53.732563   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8412 12:40:53.735424   1  6  8 | B1->B0 | 3939 4444 | 0 0 | (0 0) (0 0)

 8413 12:40:53.742251   1  6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8414 12:40:53.745401   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8415 12:40:53.748908   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8416 12:40:53.755306   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8417 12:40:53.758642   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8418 12:40:53.761918   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8419 12:40:53.768871   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8420 12:40:53.772213   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8421 12:40:53.775130   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8422 12:40:53.781827   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8423 12:40:53.785240   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8424 12:40:53.788514   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8425 12:40:53.795133   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8426 12:40:53.798679   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8427 12:40:53.802259   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8428 12:40:53.809057   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8429 12:40:53.811939   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8430 12:40:53.815618   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8431 12:40:53.822151   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8432 12:40:53.825113   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8433 12:40:53.828289   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8434 12:40:53.831636   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8435 12:40:53.838443   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8436 12:40:53.841951   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8437 12:40:53.845036   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8438 12:40:53.851886   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8439 12:40:53.855279  Total UI for P1: 0, mck2ui 16

 8440 12:40:53.858419  best dqsien dly found for B0: ( 1,  9, 10)

 8441 12:40:53.861551  Total UI for P1: 0, mck2ui 16

 8442 12:40:53.865085  best dqsien dly found for B1: ( 1,  9, 10)

 8443 12:40:53.868385  best DQS0 dly(MCK, UI, PI) = (1, 9, 10)

 8444 12:40:53.871918  best DQS1 dly(MCK, UI, PI) = (1, 9, 10)

 8445 12:40:53.872022  

 8446 12:40:53.875211  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8447 12:40:53.878606  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8448 12:40:53.881761  [Gating] SW calibration Done

 8449 12:40:53.881858  ==

 8450 12:40:53.885075  Dram Type= 6, Freq= 0, CH_1, rank 0

 8451 12:40:53.888017  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8452 12:40:53.888111  ==

 8453 12:40:53.891382  RX Vref Scan: 0

 8454 12:40:53.891474  

 8455 12:40:53.894835  RX Vref 0 -> 0, step: 1

 8456 12:40:53.894934  

 8457 12:40:53.895003  RX Delay 0 -> 252, step: 8

 8458 12:40:53.901627  iDelay=200, Bit 0, Center 143 (96 ~ 191) 96

 8459 12:40:53.904946  iDelay=200, Bit 1, Center 135 (88 ~ 183) 96

 8460 12:40:53.908781  iDelay=200, Bit 2, Center 127 (80 ~ 175) 96

 8461 12:40:53.911320  iDelay=200, Bit 3, Center 139 (88 ~ 191) 104

 8462 12:40:53.914722  iDelay=200, Bit 4, Center 135 (80 ~ 191) 112

 8463 12:40:53.918375  iDelay=200, Bit 5, Center 147 (96 ~ 199) 104

 8464 12:40:53.924790  iDelay=200, Bit 6, Center 147 (96 ~ 199) 104

 8465 12:40:53.928033  iDelay=200, Bit 7, Center 135 (88 ~ 183) 96

 8466 12:40:53.931452  iDelay=200, Bit 8, Center 119 (64 ~ 175) 112

 8467 12:40:53.935152  iDelay=200, Bit 9, Center 123 (80 ~ 167) 88

 8468 12:40:53.938139  iDelay=200, Bit 10, Center 131 (80 ~ 183) 104

 8469 12:40:53.944648  iDelay=200, Bit 11, Center 123 (72 ~ 175) 104

 8470 12:40:53.947980  iDelay=200, Bit 12, Center 139 (88 ~ 191) 104

 8471 12:40:53.951644  iDelay=200, Bit 13, Center 135 (80 ~ 191) 112

 8472 12:40:53.954475  iDelay=200, Bit 14, Center 139 (88 ~ 191) 104

 8473 12:40:53.958030  iDelay=200, Bit 15, Center 135 (80 ~ 191) 112

 8474 12:40:53.961139  ==

 8475 12:40:53.964719  Dram Type= 6, Freq= 0, CH_1, rank 0

 8476 12:40:53.968121  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8477 12:40:53.968262  ==

 8478 12:40:53.968333  DQS Delay:

 8479 12:40:53.971454  DQS0 = 0, DQS1 = 0

 8480 12:40:53.971564  DQM Delay:

 8481 12:40:53.974859  DQM0 = 138, DQM1 = 130

 8482 12:40:53.974966  DQ Delay:

 8483 12:40:53.977801  DQ0 =143, DQ1 =135, DQ2 =127, DQ3 =139

 8484 12:40:53.981385  DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135

 8485 12:40:53.984436  DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123

 8486 12:40:53.988005  DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135

 8487 12:40:53.988089  

 8488 12:40:53.988154  

 8489 12:40:53.988253  ==

 8490 12:40:53.991135  Dram Type= 6, Freq= 0, CH_1, rank 0

 8491 12:40:53.998059  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8492 12:40:53.998168  ==

 8493 12:40:53.998233  

 8494 12:40:53.998293  

 8495 12:40:53.998359  	TX Vref Scan disable

 8496 12:40:54.001566   == TX Byte 0 ==

 8497 12:40:54.004790  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 8498 12:40:54.011293  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8499 12:40:54.011405   == TX Byte 1 ==

 8500 12:40:54.014451  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8501 12:40:54.021240  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8502 12:40:54.021347  ==

 8503 12:40:54.024996  Dram Type= 6, Freq= 0, CH_1, rank 0

 8504 12:40:54.028037  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8505 12:40:54.028121  ==

 8506 12:40:54.040156  

 8507 12:40:54.043753  TX Vref early break, caculate TX vref

 8508 12:40:54.046828  TX Vref=16, minBit 15, minWin=21, winSum=366

 8509 12:40:54.050264  TX Vref=18, minBit 10, minWin=21, winSum=377

 8510 12:40:54.053442  TX Vref=20, minBit 10, minWin=23, winSum=391

 8511 12:40:54.056994  TX Vref=22, minBit 10, minWin=23, winSum=395

 8512 12:40:54.063430  TX Vref=24, minBit 10, minWin=24, winSum=412

 8513 12:40:54.066717  TX Vref=26, minBit 15, minWin=24, winSum=418

 8514 12:40:54.070202  TX Vref=28, minBit 8, minWin=25, winSum=419

 8515 12:40:54.073470  TX Vref=30, minBit 8, minWin=24, winSum=417

 8516 12:40:54.076733  TX Vref=32, minBit 13, minWin=23, winSum=404

 8517 12:40:54.080431  TX Vref=34, minBit 9, minWin=23, winSum=393

 8518 12:40:54.086725  [TxChooseVref] Worse bit 8, Min win 25, Win sum 419, Final Vref 28

 8519 12:40:54.086843  

 8520 12:40:54.090555  Final TX Range 0 Vref 28

 8521 12:40:54.090652  

 8522 12:40:54.090719  ==

 8523 12:40:54.093382  Dram Type= 6, Freq= 0, CH_1, rank 0

 8524 12:40:54.096816  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8525 12:40:54.096911  ==

 8526 12:40:54.096979  

 8527 12:40:54.097039  

 8528 12:40:54.099927  	TX Vref Scan disable

 8529 12:40:54.106573  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps

 8530 12:40:54.106693   == TX Byte 0 ==

 8531 12:40:54.109885  u2DelayCellOfst[0]=17 cells (5 PI)

 8532 12:40:54.113303  u2DelayCellOfst[1]=10 cells (3 PI)

 8533 12:40:54.116937  u2DelayCellOfst[2]=0 cells (0 PI)

 8534 12:40:54.119783  u2DelayCellOfst[3]=6 cells (2 PI)

 8535 12:40:54.123174  u2DelayCellOfst[4]=6 cells (2 PI)

 8536 12:40:54.126932  u2DelayCellOfst[5]=17 cells (5 PI)

 8537 12:40:54.129857  u2DelayCellOfst[6]=17 cells (5 PI)

 8538 12:40:54.133332  u2DelayCellOfst[7]=3 cells (1 PI)

 8539 12:40:54.136662  Update DQ  dly =978 (3 ,6, 18)  DQ  OEN =(3 ,3)

 8540 12:40:54.139992  Update DQM dly =980 (3 ,6, 20)  DQM OEN =(3 ,3)

 8541 12:40:54.143363   == TX Byte 1 ==

 8542 12:40:54.146299  u2DelayCellOfst[8]=0 cells (0 PI)

 8543 12:40:54.146397  u2DelayCellOfst[9]=6 cells (2 PI)

 8544 12:40:54.149631  u2DelayCellOfst[10]=13 cells (4 PI)

 8545 12:40:54.153151  u2DelayCellOfst[11]=6 cells (2 PI)

 8546 12:40:54.156588  u2DelayCellOfst[12]=17 cells (5 PI)

 8547 12:40:54.159789  u2DelayCellOfst[13]=17 cells (5 PI)

 8548 12:40:54.162889  u2DelayCellOfst[14]=20 cells (6 PI)

 8549 12:40:54.166422  u2DelayCellOfst[15]=17 cells (5 PI)

 8550 12:40:54.169821  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8551 12:40:54.176330  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8552 12:40:54.176456  DramC Write-DBI on

 8553 12:40:54.176558  ==

 8554 12:40:54.179774  Dram Type= 6, Freq= 0, CH_1, rank 0

 8555 12:40:54.186596  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8556 12:40:54.186714  ==

 8557 12:40:54.186783  

 8558 12:40:54.186846  

 8559 12:40:54.186906  	TX Vref Scan disable

 8560 12:40:54.189808   == TX Byte 0 ==

 8561 12:40:54.193226  Update DQM dly =721 (2 ,6, 17)  DQM OEN =(3 ,3)

 8562 12:40:54.196566   == TX Byte 1 ==

 8563 12:40:54.199969  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8564 12:40:54.203514  DramC Write-DBI off

 8565 12:40:54.203613  

 8566 12:40:54.203681  [DATLAT]

 8567 12:40:54.203744  Freq=1600, CH1 RK0

 8568 12:40:54.203804  

 8569 12:40:54.206991  DATLAT Default: 0xf

 8570 12:40:54.207081  0, 0xFFFF, sum = 0

 8571 12:40:54.209899  1, 0xFFFF, sum = 0

 8572 12:40:54.209998  2, 0xFFFF, sum = 0

 8573 12:40:54.213413  3, 0xFFFF, sum = 0

 8574 12:40:54.216738  4, 0xFFFF, sum = 0

 8575 12:40:54.216832  5, 0xFFFF, sum = 0

 8576 12:40:54.219783  6, 0xFFFF, sum = 0

 8577 12:40:54.219874  7, 0xFFFF, sum = 0

 8578 12:40:54.223463  8, 0xFFFF, sum = 0

 8579 12:40:54.223562  9, 0xFFFF, sum = 0

 8580 12:40:54.226673  10, 0xFFFF, sum = 0

 8581 12:40:54.226766  11, 0xFFFF, sum = 0

 8582 12:40:54.230055  12, 0xFFFF, sum = 0

 8583 12:40:54.230145  13, 0xFFFF, sum = 0

 8584 12:40:54.233338  14, 0x0, sum = 1

 8585 12:40:54.233430  15, 0x0, sum = 2

 8586 12:40:54.236617  16, 0x0, sum = 3

 8587 12:40:54.236707  17, 0x0, sum = 4

 8588 12:40:54.240104  best_step = 15

 8589 12:40:54.240195  

 8590 12:40:54.240262  ==

 8591 12:40:54.243425  Dram Type= 6, Freq= 0, CH_1, rank 0

 8592 12:40:54.246382  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8593 12:40:54.246475  ==

 8594 12:40:54.246543  RX Vref Scan: 1

 8595 12:40:54.250077  

 8596 12:40:54.250166  Set Vref Range= 24 -> 127

 8597 12:40:54.250233  

 8598 12:40:54.253317  RX Vref 24 -> 127, step: 1

 8599 12:40:54.253405  

 8600 12:40:54.256406  RX Delay 19 -> 252, step: 4

 8601 12:40:54.256495  

 8602 12:40:54.260216  Set Vref, RX VrefLevel [Byte0]: 24

 8603 12:40:54.263232                           [Byte1]: 24

 8604 12:40:54.263324  

 8605 12:40:54.267004  Set Vref, RX VrefLevel [Byte0]: 25

 8606 12:40:54.270031                           [Byte1]: 25

 8607 12:40:54.270126  

 8608 12:40:54.273214  Set Vref, RX VrefLevel [Byte0]: 26

 8609 12:40:54.276414                           [Byte1]: 26

 8610 12:40:54.280147  

 8611 12:40:54.280254  Set Vref, RX VrefLevel [Byte0]: 27

 8612 12:40:54.283985                           [Byte1]: 27

 8613 12:40:54.287893  

 8614 12:40:54.287994  Set Vref, RX VrefLevel [Byte0]: 28

 8615 12:40:54.291106                           [Byte1]: 28

 8616 12:40:54.295339  

 8617 12:40:54.295434  Set Vref, RX VrefLevel [Byte0]: 29

 8618 12:40:54.298489                           [Byte1]: 29

 8619 12:40:54.303100  

 8620 12:40:54.303205  Set Vref, RX VrefLevel [Byte0]: 30

 8621 12:40:54.306193                           [Byte1]: 30

 8622 12:40:54.310652  

 8623 12:40:54.310744  Set Vref, RX VrefLevel [Byte0]: 31

 8624 12:40:54.314212                           [Byte1]: 31

 8625 12:40:54.318198  

 8626 12:40:54.318293  Set Vref, RX VrefLevel [Byte0]: 32

 8627 12:40:54.321502                           [Byte1]: 32

 8628 12:40:54.325867  

 8629 12:40:54.326006  Set Vref, RX VrefLevel [Byte0]: 33

 8630 12:40:54.329029                           [Byte1]: 33

 8631 12:40:54.333573  

 8632 12:40:54.333659  Set Vref, RX VrefLevel [Byte0]: 34

 8633 12:40:54.336719                           [Byte1]: 34

 8634 12:40:54.341153  

 8635 12:40:54.341242  Set Vref, RX VrefLevel [Byte0]: 35

 8636 12:40:54.344289                           [Byte1]: 35

 8637 12:40:54.348356  

 8638 12:40:54.348465  Set Vref, RX VrefLevel [Byte0]: 36

 8639 12:40:54.351923                           [Byte1]: 36

 8640 12:40:54.355832  

 8641 12:40:54.355917  Set Vref, RX VrefLevel [Byte0]: 37

 8642 12:40:54.359352                           [Byte1]: 37

 8643 12:40:54.363766  

 8644 12:40:54.363861  Set Vref, RX VrefLevel [Byte0]: 38

 8645 12:40:54.367008                           [Byte1]: 38

 8646 12:40:54.371089  

 8647 12:40:54.371172  Set Vref, RX VrefLevel [Byte0]: 39

 8648 12:40:54.374490                           [Byte1]: 39

 8649 12:40:54.378934  

 8650 12:40:54.379035  Set Vref, RX VrefLevel [Byte0]: 40

 8651 12:40:54.382269                           [Byte1]: 40

 8652 12:40:54.386209  

 8653 12:40:54.386305  Set Vref, RX VrefLevel [Byte0]: 41

 8654 12:40:54.389951                           [Byte1]: 41

 8655 12:40:54.393834  

 8656 12:40:54.393979  Set Vref, RX VrefLevel [Byte0]: 42

 8657 12:40:54.397122                           [Byte1]: 42

 8658 12:40:54.401380  

 8659 12:40:54.401508  Set Vref, RX VrefLevel [Byte0]: 43

 8660 12:40:54.404766                           [Byte1]: 43

 8661 12:40:54.408861  

 8662 12:40:54.408981  Set Vref, RX VrefLevel [Byte0]: 44

 8663 12:40:54.412336                           [Byte1]: 44

 8664 12:40:54.416758  

 8665 12:40:54.416858  Set Vref, RX VrefLevel [Byte0]: 45

 8666 12:40:54.419969                           [Byte1]: 45

 8667 12:40:54.424270  

 8668 12:40:54.424444  Set Vref, RX VrefLevel [Byte0]: 46

 8669 12:40:54.427174                           [Byte1]: 46

 8670 12:40:54.431491  

 8671 12:40:54.431663  Set Vref, RX VrefLevel [Byte0]: 47

 8672 12:40:54.434830                           [Byte1]: 47

 8673 12:40:54.439289  

 8674 12:40:54.439471  Set Vref, RX VrefLevel [Byte0]: 48

 8675 12:40:54.442604                           [Byte1]: 48

 8676 12:40:54.446682  

 8677 12:40:54.446854  Set Vref, RX VrefLevel [Byte0]: 49

 8678 12:40:54.450038                           [Byte1]: 49

 8679 12:40:54.454449  

 8680 12:40:54.454601  Set Vref, RX VrefLevel [Byte0]: 50

 8681 12:40:54.458027                           [Byte1]: 50

 8682 12:40:54.461851  

 8683 12:40:54.461999  Set Vref, RX VrefLevel [Byte0]: 51

 8684 12:40:54.464979                           [Byte1]: 51

 8685 12:40:54.469663  

 8686 12:40:54.469827  Set Vref, RX VrefLevel [Byte0]: 52

 8687 12:40:54.472628                           [Byte1]: 52

 8688 12:40:54.477327  

 8689 12:40:54.477483  Set Vref, RX VrefLevel [Byte0]: 53

 8690 12:40:54.480381                           [Byte1]: 53

 8691 12:40:54.484438  

 8692 12:40:54.484585  Set Vref, RX VrefLevel [Byte0]: 54

 8693 12:40:54.488125                           [Byte1]: 54

 8694 12:40:54.492153  

 8695 12:40:54.492322  Set Vref, RX VrefLevel [Byte0]: 55

 8696 12:40:54.495908                           [Byte1]: 55

 8697 12:40:54.500096  

 8698 12:40:54.500230  Set Vref, RX VrefLevel [Byte0]: 56

 8699 12:40:54.503121                           [Byte1]: 56

 8700 12:40:54.507467  

 8701 12:40:54.507599  Set Vref, RX VrefLevel [Byte0]: 57

 8702 12:40:54.510584                           [Byte1]: 57

 8703 12:40:54.514908  

 8704 12:40:54.515033  Set Vref, RX VrefLevel [Byte0]: 58

 8705 12:40:54.518213                           [Byte1]: 58

 8706 12:40:54.522347  

 8707 12:40:54.522469  Set Vref, RX VrefLevel [Byte0]: 59

 8708 12:40:54.525835                           [Byte1]: 59

 8709 12:40:54.530363  

 8710 12:40:54.530520  Set Vref, RX VrefLevel [Byte0]: 60

 8711 12:40:54.533516                           [Byte1]: 60

 8712 12:40:54.537908  

 8713 12:40:54.538082  Set Vref, RX VrefLevel [Byte0]: 61

 8714 12:40:54.540798                           [Byte1]: 61

 8715 12:40:54.545437  

 8716 12:40:54.545565  Set Vref, RX VrefLevel [Byte0]: 62

 8717 12:40:54.548557                           [Byte1]: 62

 8718 12:40:54.552839  

 8719 12:40:54.552981  Set Vref, RX VrefLevel [Byte0]: 63

 8720 12:40:54.556229                           [Byte1]: 63

 8721 12:40:54.560298  

 8722 12:40:54.563782  Set Vref, RX VrefLevel [Byte0]: 64

 8723 12:40:54.563911                           [Byte1]: 64

 8724 12:40:54.567810  

 8725 12:40:54.567929  Set Vref, RX VrefLevel [Byte0]: 65

 8726 12:40:54.571470                           [Byte1]: 65

 8727 12:40:54.575480  

 8728 12:40:54.575618  Set Vref, RX VrefLevel [Byte0]: 66

 8729 12:40:54.578650                           [Byte1]: 66

 8730 12:40:54.582939  

 8731 12:40:54.583077  Set Vref, RX VrefLevel [Byte0]: 67

 8732 12:40:54.586443                           [Byte1]: 67

 8733 12:40:54.590519  

 8734 12:40:54.590648  Set Vref, RX VrefLevel [Byte0]: 68

 8735 12:40:54.594444                           [Byte1]: 68

 8736 12:40:54.598223  

 8737 12:40:54.598358  Set Vref, RX VrefLevel [Byte0]: 69

 8738 12:40:54.601778                           [Byte1]: 69

 8739 12:40:54.605799  

 8740 12:40:54.605927  Set Vref, RX VrefLevel [Byte0]: 70

 8741 12:40:54.609067                           [Byte1]: 70

 8742 12:40:54.613529  

 8743 12:40:54.613670  Set Vref, RX VrefLevel [Byte0]: 71

 8744 12:40:54.616770                           [Byte1]: 71

 8745 12:40:54.620987  

 8746 12:40:54.621116  Final RX Vref Byte 0 = 52 to rank0

 8747 12:40:54.624549  Final RX Vref Byte 1 = 63 to rank0

 8748 12:40:54.627444  Final RX Vref Byte 0 = 52 to rank1

 8749 12:40:54.630873  Final RX Vref Byte 1 = 63 to rank1==

 8750 12:40:54.634366  Dram Type= 6, Freq= 0, CH_1, rank 0

 8751 12:40:54.640894  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8752 12:40:54.641073  ==

 8753 12:40:54.641182  DQS Delay:

 8754 12:40:54.641276  DQS0 = 0, DQS1 = 0

 8755 12:40:54.644180  DQM Delay:

 8756 12:40:54.644310  DQM0 = 133, DQM1 = 129

 8757 12:40:54.647701  DQ Delay:

 8758 12:40:54.650759  DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132

 8759 12:40:54.655167  DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130

 8760 12:40:54.657692  DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =122

 8761 12:40:54.660942  DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =134

 8762 12:40:54.661074  

 8763 12:40:54.661171  

 8764 12:40:54.661283  

 8765 12:40:54.664468  [DramC_TX_OE_Calibration] TA2

 8766 12:40:54.667567  Original DQ_B0 (3 6) =30, OEN = 27

 8767 12:40:54.671049  Original DQ_B1 (3 6) =30, OEN = 27

 8768 12:40:54.674202  24, 0x0, End_B0=24 End_B1=24

 8769 12:40:54.674351  25, 0x0, End_B0=25 End_B1=25

 8770 12:40:54.677530  26, 0x0, End_B0=26 End_B1=26

 8771 12:40:54.680889  27, 0x0, End_B0=27 End_B1=27

 8772 12:40:54.684273  28, 0x0, End_B0=28 End_B1=28

 8773 12:40:54.687670  29, 0x0, End_B0=29 End_B1=29

 8774 12:40:54.687780  30, 0x0, End_B0=30 End_B1=30

 8775 12:40:54.690777  31, 0x4545, End_B0=30 End_B1=30

 8776 12:40:54.694121  Byte0 end_step=30  best_step=27

 8777 12:40:54.697541  Byte1 end_step=30  best_step=27

 8778 12:40:54.701021  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8779 12:40:54.701135  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8780 12:40:54.703920  

 8781 12:40:54.704014  

 8782 12:40:54.710844  [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps

 8783 12:40:54.714178  CH1 RK0: MR19=303, MR18=1826

 8784 12:40:54.720722  CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16

 8785 12:40:54.720846  

 8786 12:40:54.724225  ----->DramcWriteLeveling(PI) begin...

 8787 12:40:54.724333  ==

 8788 12:40:54.727565  Dram Type= 6, Freq= 0, CH_1, rank 1

 8789 12:40:54.730708  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8790 12:40:54.730858  ==

 8791 12:40:54.734194  Write leveling (Byte 0): 23 => 23

 8792 12:40:54.737606  Write leveling (Byte 1): 29 => 29

 8793 12:40:54.740730  DramcWriteLeveling(PI) end<-----

 8794 12:40:54.740839  

 8795 12:40:54.740910  ==

 8796 12:40:54.744333  Dram Type= 6, Freq= 0, CH_1, rank 1

 8797 12:40:54.747611  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8798 12:40:54.747739  ==

 8799 12:40:54.750691  [Gating] SW mode calibration

 8800 12:40:54.757434  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8801 12:40:54.764473  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8802 12:40:54.767629   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8803 12:40:54.770928   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8804 12:40:54.777370   1  4  8 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)

 8805 12:40:54.780847   1  4 12 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 1)

 8806 12:40:54.783893   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8807 12:40:54.790878   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8808 12:40:54.794068   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8809 12:40:54.797612   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8810 12:40:54.804488   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8811 12:40:54.807836   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8812 12:40:54.811013   1  5  8 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 0)

 8813 12:40:54.817454   1  5 12 | B1->B0 | 2323 2c2c | 0 0 | (1 0) (1 0)

 8814 12:40:54.821263   1  5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8815 12:40:54.823949   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8816 12:40:54.830419   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8817 12:40:54.833932   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8818 12:40:54.837120   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8819 12:40:54.843647   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8820 12:40:54.847163   1  6  8 | B1->B0 | 4141 2323 | 0 0 | (0 0) (0 0)

 8821 12:40:54.850282   1  6 12 | B1->B0 | 4646 3939 | 0 0 | (0 0) (0 0)

 8822 12:40:54.857067   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8823 12:40:54.860154   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8824 12:40:54.863859   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8825 12:40:54.866919   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8826 12:40:54.873885   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8827 12:40:54.877135   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8828 12:40:54.880243   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8829 12:40:54.886897   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8830 12:40:54.890269   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8831 12:40:54.893755   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8832 12:40:54.900007   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8833 12:40:54.904005   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8834 12:40:54.906680   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8835 12:40:54.913369   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8836 12:40:54.916826   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8837 12:40:54.920325   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8838 12:40:54.926719   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8839 12:40:54.930411   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8840 12:40:54.933466   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8841 12:40:54.940200   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8842 12:40:54.943383   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8843 12:40:54.946596   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8844 12:40:54.953420   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8845 12:40:54.956687   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8846 12:40:54.959902   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8847 12:40:54.963144  Total UI for P1: 0, mck2ui 16

 8848 12:40:54.966710  best dqsien dly found for B0: ( 1,  9, 10)

 8849 12:40:54.969840  Total UI for P1: 0, mck2ui 16

 8850 12:40:54.973390  best dqsien dly found for B1: ( 1,  9, 10)

 8851 12:40:54.976767  best DQS0 dly(MCK, UI, PI) = (1, 9, 10)

 8852 12:40:54.979983  best DQS1 dly(MCK, UI, PI) = (1, 9, 10)

 8853 12:40:54.980081  

 8854 12:40:54.983431  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8855 12:40:54.990035  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8856 12:40:54.990143  [Gating] SW calibration Done

 8857 12:40:54.993443  ==

 8858 12:40:54.993531  Dram Type= 6, Freq= 0, CH_1, rank 1

 8859 12:40:54.999885  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8860 12:40:54.999988  ==

 8861 12:40:55.000057  RX Vref Scan: 0

 8862 12:40:55.000120  

 8863 12:40:55.003544  RX Vref 0 -> 0, step: 1

 8864 12:40:55.003633  

 8865 12:40:55.006733  RX Delay 0 -> 252, step: 8

 8866 12:40:55.009725  iDelay=200, Bit 0, Center 139 (96 ~ 183) 88

 8867 12:40:55.013579  iDelay=200, Bit 1, Center 135 (88 ~ 183) 96

 8868 12:40:55.016502  iDelay=200, Bit 2, Center 123 (72 ~ 175) 104

 8869 12:40:55.023315  iDelay=200, Bit 3, Center 135 (80 ~ 191) 112

 8870 12:40:55.026359  iDelay=200, Bit 4, Center 135 (80 ~ 191) 112

 8871 12:40:55.029896  iDelay=200, Bit 5, Center 147 (96 ~ 199) 104

 8872 12:40:55.033270  iDelay=200, Bit 6, Center 139 (88 ~ 191) 104

 8873 12:40:55.036288  iDelay=200, Bit 7, Center 139 (88 ~ 191) 104

 8874 12:40:55.040111  iDelay=200, Bit 8, Center 115 (64 ~ 167) 104

 8875 12:40:55.046530  iDelay=200, Bit 9, Center 119 (64 ~ 175) 112

 8876 12:40:55.049799  iDelay=200, Bit 10, Center 135 (80 ~ 191) 112

 8877 12:40:55.052802  iDelay=200, Bit 11, Center 127 (72 ~ 183) 112

 8878 12:40:55.056151  iDelay=200, Bit 12, Center 139 (88 ~ 191) 104

 8879 12:40:55.063427  iDelay=200, Bit 13, Center 143 (88 ~ 199) 112

 8880 12:40:55.066205  iDelay=200, Bit 14, Center 139 (88 ~ 191) 104

 8881 12:40:55.069426  iDelay=200, Bit 15, Center 143 (88 ~ 199) 112

 8882 12:40:55.069520  ==

 8883 12:40:55.072933  Dram Type= 6, Freq= 0, CH_1, rank 1

 8884 12:40:55.076375  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8885 12:40:55.076468  ==

 8886 12:40:55.079486  DQS Delay:

 8887 12:40:55.079577  DQS0 = 0, DQS1 = 0

 8888 12:40:55.083007  DQM Delay:

 8889 12:40:55.083096  DQM0 = 136, DQM1 = 132

 8890 12:40:55.085951  DQ Delay:

 8891 12:40:55.089274  DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =135

 8892 12:40:55.092490  DQ4 =135, DQ5 =147, DQ6 =139, DQ7 =139

 8893 12:40:55.095599  DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127

 8894 12:40:55.099532  DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143

 8895 12:40:55.099624  

 8896 12:40:55.099691  

 8897 12:40:55.099751  ==

 8898 12:40:55.102380  Dram Type= 6, Freq= 0, CH_1, rank 1

 8899 12:40:55.105842  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8900 12:40:55.105937  ==

 8901 12:40:55.106013  

 8902 12:40:55.109009  

 8903 12:40:55.109094  	TX Vref Scan disable

 8904 12:40:55.112602   == TX Byte 0 ==

 8905 12:40:55.116049  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8906 12:40:55.119124  Update DQM dly =980 (3 ,6, 20)  DQM OEN =(3 ,3)

 8907 12:40:55.122629   == TX Byte 1 ==

 8908 12:40:55.125455  Update DQ  dly =983 (3 ,6, 23)  DQ  OEN =(3 ,3)

 8909 12:40:55.128918  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8910 12:40:55.129015  ==

 8911 12:40:55.132165  Dram Type= 6, Freq= 0, CH_1, rank 1

 8912 12:40:55.138783  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8913 12:40:55.138889  ==

 8914 12:40:55.151793  

 8915 12:40:55.155062  TX Vref early break, caculate TX vref

 8916 12:40:55.158444  TX Vref=16, minBit 8, minWin=22, winSum=376

 8917 12:40:55.161718  TX Vref=18, minBit 11, minWin=22, winSum=384

 8918 12:40:55.165080  TX Vref=20, minBit 8, minWin=23, winSum=394

 8919 12:40:55.168681  TX Vref=22, minBit 9, minWin=24, winSum=405

 8920 12:40:55.171790  TX Vref=24, minBit 9, minWin=24, winSum=410

 8921 12:40:55.178766  TX Vref=26, minBit 8, minWin=25, winSum=416

 8922 12:40:55.181732  TX Vref=28, minBit 9, minWin=24, winSum=416

 8923 12:40:55.184904  TX Vref=30, minBit 8, minWin=24, winSum=409

 8924 12:40:55.188443  TX Vref=32, minBit 8, minWin=24, winSum=408

 8925 12:40:55.192036  TX Vref=34, minBit 9, minWin=23, winSum=398

 8926 12:40:55.194866  TX Vref=36, minBit 9, minWin=22, winSum=386

 8927 12:40:55.201523  [TxChooseVref] Worse bit 8, Min win 25, Win sum 416, Final Vref 26

 8928 12:40:55.201637  

 8929 12:40:55.205275  Final TX Range 0 Vref 26

 8930 12:40:55.205366  

 8931 12:40:55.205457  ==

 8932 12:40:55.208729  Dram Type= 6, Freq= 0, CH_1, rank 1

 8933 12:40:55.212205  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8934 12:40:55.212300  ==

 8935 12:40:55.212367  

 8936 12:40:55.212428  

 8937 12:40:55.215254  	TX Vref Scan disable

 8938 12:40:55.221482  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps

 8939 12:40:55.221590   == TX Byte 0 ==

 8940 12:40:55.225156  u2DelayCellOfst[0]=13 cells (4 PI)

 8941 12:40:55.228165  u2DelayCellOfst[1]=6 cells (2 PI)

 8942 12:40:55.231770  u2DelayCellOfst[2]=0 cells (0 PI)

 8943 12:40:55.235340  u2DelayCellOfst[3]=3 cells (1 PI)

 8944 12:40:55.238366  u2DelayCellOfst[4]=6 cells (2 PI)

 8945 12:40:55.241614  u2DelayCellOfst[5]=17 cells (5 PI)

 8946 12:40:55.244986  u2DelayCellOfst[6]=13 cells (4 PI)

 8947 12:40:55.248220  u2DelayCellOfst[7]=3 cells (1 PI)

 8948 12:40:55.251800  Update DQ  dly =978 (3 ,6, 18)  DQ  OEN =(3 ,3)

 8949 12:40:55.254805  Update DQM dly =980 (3 ,6, 20)  DQM OEN =(3 ,3)

 8950 12:40:55.258918   == TX Byte 1 ==

 8951 12:40:55.259016  u2DelayCellOfst[8]=0 cells (0 PI)

 8952 12:40:55.261833  u2DelayCellOfst[9]=3 cells (1 PI)

 8953 12:40:55.264950  u2DelayCellOfst[10]=10 cells (3 PI)

 8954 12:40:55.268331  u2DelayCellOfst[11]=3 cells (1 PI)

 8955 12:40:55.271578  u2DelayCellOfst[12]=10 cells (3 PI)

 8956 12:40:55.274700  u2DelayCellOfst[13]=13 cells (4 PI)

 8957 12:40:55.278094  u2DelayCellOfst[14]=17 cells (5 PI)

 8958 12:40:55.281576  u2DelayCellOfst[15]=17 cells (5 PI)

 8959 12:40:55.284602  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 8960 12:40:55.291323  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8961 12:40:55.291438  DramC Write-DBI on

 8962 12:40:55.291506  ==

 8963 12:40:55.295277  Dram Type= 6, Freq= 0, CH_1, rank 1

 8964 12:40:55.301448  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8965 12:40:55.301554  ==

 8966 12:40:55.301622  

 8967 12:40:55.301683  

 8968 12:40:55.301740  	TX Vref Scan disable

 8969 12:40:55.305000   == TX Byte 0 ==

 8970 12:40:55.308863  Update DQM dly =721 (2 ,6, 17)  DQM OEN =(3 ,3)

 8971 12:40:55.311862   == TX Byte 1 ==

 8972 12:40:55.315393  Update DQM dly =724 (2 ,6, 20)  DQM OEN =(3 ,3)

 8973 12:40:55.315489  DramC Write-DBI off

 8974 12:40:55.318366  

 8975 12:40:55.318454  [DATLAT]

 8976 12:40:55.318521  Freq=1600, CH1 RK1

 8977 12:40:55.318581  

 8978 12:40:55.321872  DATLAT Default: 0xf

 8979 12:40:55.321965  0, 0xFFFF, sum = 0

 8980 12:40:55.324797  1, 0xFFFF, sum = 0

 8981 12:40:55.324887  2, 0xFFFF, sum = 0

 8982 12:40:55.328363  3, 0xFFFF, sum = 0

 8983 12:40:55.332098  4, 0xFFFF, sum = 0

 8984 12:40:55.332194  5, 0xFFFF, sum = 0

 8985 12:40:55.335069  6, 0xFFFF, sum = 0

 8986 12:40:55.335157  7, 0xFFFF, sum = 0

 8987 12:40:55.338386  8, 0xFFFF, sum = 0

 8988 12:40:55.338476  9, 0xFFFF, sum = 0

 8989 12:40:55.341613  10, 0xFFFF, sum = 0

 8990 12:40:55.341702  11, 0xFFFF, sum = 0

 8991 12:40:55.345458  12, 0xFFFF, sum = 0

 8992 12:40:55.345547  13, 0xFFFF, sum = 0

 8993 12:40:55.348346  14, 0x0, sum = 1

 8994 12:40:55.348432  15, 0x0, sum = 2

 8995 12:40:55.351541  16, 0x0, sum = 3

 8996 12:40:55.351628  17, 0x0, sum = 4

 8997 12:40:55.355030  best_step = 15

 8998 12:40:55.355118  

 8999 12:40:55.355184  ==

 9000 12:40:55.358649  Dram Type= 6, Freq= 0, CH_1, rank 1

 9001 12:40:55.361759  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 9002 12:40:55.361850  ==

 9003 12:40:55.361917  RX Vref Scan: 0

 9004 12:40:55.361985  

 9005 12:40:55.365203  RX Vref 0 -> 0, step: 1

 9006 12:40:55.365290  

 9007 12:40:55.368165  RX Delay 19 -> 252, step: 4

 9008 12:40:55.371769  iDelay=195, Bit 0, Center 136 (95 ~ 178) 84

 9009 12:40:55.378202  iDelay=195, Bit 1, Center 130 (87 ~ 174) 88

 9010 12:40:55.381777  iDelay=195, Bit 2, Center 120 (71 ~ 170) 100

 9011 12:40:55.384783  iDelay=195, Bit 3, Center 130 (83 ~ 178) 96

 9012 12:40:55.388755  iDelay=195, Bit 4, Center 134 (87 ~ 182) 96

 9013 12:40:55.391803  iDelay=195, Bit 5, Center 146 (99 ~ 194) 96

 9014 12:40:55.394867  iDelay=195, Bit 6, Center 142 (95 ~ 190) 96

 9015 12:40:55.401710  iDelay=195, Bit 7, Center 132 (87 ~ 178) 92

 9016 12:40:55.404908  iDelay=195, Bit 8, Center 112 (63 ~ 162) 100

 9017 12:40:55.408557  iDelay=195, Bit 9, Center 118 (67 ~ 170) 104

 9018 12:40:55.411625  iDelay=195, Bit 10, Center 130 (79 ~ 182) 104

 9019 12:40:55.415040  iDelay=195, Bit 11, Center 126 (75 ~ 178) 104

 9020 12:40:55.421847  iDelay=195, Bit 12, Center 140 (91 ~ 190) 100

 9021 12:40:55.424918  iDelay=195, Bit 13, Center 138 (87 ~ 190) 104

 9022 12:40:55.428682  iDelay=195, Bit 14, Center 138 (91 ~ 186) 96

 9023 12:40:55.431409  iDelay=195, Bit 15, Center 140 (87 ~ 194) 108

 9024 12:40:55.431503  ==

 9025 12:40:55.434713  Dram Type= 6, Freq= 0, CH_1, rank 1

 9026 12:40:55.438310  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 9027 12:40:55.441506  ==

 9028 12:40:55.441598  DQS Delay:

 9029 12:40:55.441665  DQS0 = 0, DQS1 = 0

 9030 12:40:55.444825  DQM Delay:

 9031 12:40:55.444913  DQM0 = 133, DQM1 = 130

 9032 12:40:55.448269  DQ Delay:

 9033 12:40:55.451536  DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =130

 9034 12:40:55.454593  DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =132

 9035 12:40:55.458200  DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =126

 9036 12:40:55.461664  DQ12 =140, DQ13 =138, DQ14 =138, DQ15 =140

 9037 12:40:55.461756  

 9038 12:40:55.461822  

 9039 12:40:55.461884  

 9040 12:40:55.464880  [DramC_TX_OE_Calibration] TA2

 9041 12:40:55.467972  Original DQ_B0 (3 6) =30, OEN = 27

 9042 12:40:55.471222  Original DQ_B1 (3 6) =30, OEN = 27

 9043 12:40:55.474807  24, 0x0, End_B0=24 End_B1=24

 9044 12:40:55.474902  25, 0x0, End_B0=25 End_B1=25

 9045 12:40:55.478111  26, 0x0, End_B0=26 End_B1=26

 9046 12:40:55.481351  27, 0x0, End_B0=27 End_B1=27

 9047 12:40:55.484630  28, 0x0, End_B0=28 End_B1=28

 9048 12:40:55.484726  29, 0x0, End_B0=29 End_B1=29

 9049 12:40:55.487958  30, 0x0, End_B0=30 End_B1=30

 9050 12:40:55.491380  31, 0x4141, End_B0=30 End_B1=30

 9051 12:40:55.494858  Byte0 end_step=30  best_step=27

 9052 12:40:55.498295  Byte1 end_step=30  best_step=27

 9053 12:40:55.501408  Byte0 TX OE(2T, 0.5T) = (3, 3)

 9054 12:40:55.501504  Byte1 TX OE(2T, 0.5T) = (3, 3)

 9055 12:40:55.501570  

 9056 12:40:55.504715  

 9057 12:40:55.511486  [DQSOSCAuto] RK1, (LSB)MR18= 0x1e09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps

 9058 12:40:55.514669  CH1 RK1: MR19=303, MR18=1E09

 9059 12:40:55.521458  CH1_RK1: MR19=0x303, MR18=0x1E09, DQSOSC=394, MR23=63, INC=23, DEC=15

 9060 12:40:55.524777  [RxdqsGatingPostProcess] freq 1600

 9061 12:40:55.527895  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 9062 12:40:55.531436  best DQS0 dly(2T, 0.5T) = (1, 1)

 9063 12:40:55.535026  best DQS1 dly(2T, 0.5T) = (1, 1)

 9064 12:40:55.538150  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9065 12:40:55.541482  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9066 12:40:55.544522  best DQS0 dly(2T, 0.5T) = (1, 1)

 9067 12:40:55.548350  best DQS1 dly(2T, 0.5T) = (1, 1)

 9068 12:40:55.551364  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9069 12:40:55.554383  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9070 12:40:55.554473  Pre-setting of DQS Precalculation

 9071 12:40:55.561592  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 9072 12:40:55.567901  sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0

 9073 12:40:55.574503  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9074 12:40:55.574623  

 9075 12:40:55.574690  

 9076 12:40:55.577768  [Calibration Summary] 3200 Mbps

 9077 12:40:55.581300  CH 0, Rank 0

 9078 12:40:55.581397  SW Impedance     : PASS

 9079 12:40:55.584143  DUTY Scan        : NO K

 9080 12:40:55.587520  ZQ Calibration   : PASS

 9081 12:40:55.587611  Jitter Meter     : NO K

 9082 12:40:55.590797  CBT Training     : PASS

 9083 12:40:55.594749  Write leveling   : PASS

 9084 12:40:55.594842  RX DQS gating    : PASS

 9085 12:40:55.597741  RX DQ/DQS(RDDQC) : PASS

 9086 12:40:55.601001  TX DQ/DQS        : PASS

 9087 12:40:55.601092  RX DATLAT        : PASS

 9088 12:40:55.604395  RX DQ/DQS(Engine): PASS

 9089 12:40:55.604483  TX OE            : PASS

 9090 12:40:55.607574  All Pass.

 9091 12:40:55.607663  

 9092 12:40:55.607729  CH 0, Rank 1

 9093 12:40:55.611042  SW Impedance     : PASS

 9094 12:40:55.611132  DUTY Scan        : NO K

 9095 12:40:55.614115  ZQ Calibration   : PASS

 9096 12:40:55.617657  Jitter Meter     : NO K

 9097 12:40:55.617743  CBT Training     : PASS

 9098 12:40:55.620901  Write leveling   : PASS

 9099 12:40:55.624141  RX DQS gating    : PASS

 9100 12:40:55.624233  RX DQ/DQS(RDDQC) : PASS

 9101 12:40:55.627422  TX DQ/DQS        : PASS

 9102 12:40:55.630977  RX DATLAT        : PASS

 9103 12:40:55.631070  RX DQ/DQS(Engine): PASS

 9104 12:40:55.634080  TX OE            : PASS

 9105 12:40:55.634167  All Pass.

 9106 12:40:55.634233  

 9107 12:40:55.638276  CH 1, Rank 0

 9108 12:40:55.638368  SW Impedance     : PASS

 9109 12:40:55.641128  DUTY Scan        : NO K

 9110 12:40:55.644146  ZQ Calibration   : PASS

 9111 12:40:55.644236  Jitter Meter     : NO K

 9112 12:40:55.647611  CBT Training     : PASS

 9113 12:40:55.650322  Write leveling   : PASS

 9114 12:40:55.650412  RX DQS gating    : PASS

 9115 12:40:55.654067  RX DQ/DQS(RDDQC) : PASS

 9116 12:40:55.657281  TX DQ/DQS        : PASS

 9117 12:40:55.657371  RX DATLAT        : PASS

 9118 12:40:55.660777  RX DQ/DQS(Engine): PASS

 9119 12:40:55.663570  TX OE            : PASS

 9120 12:40:55.663659  All Pass.

 9121 12:40:55.663725  

 9122 12:40:55.663786  CH 1, Rank 1

 9123 12:40:55.667440  SW Impedance     : PASS

 9124 12:40:55.670292  DUTY Scan        : NO K

 9125 12:40:55.670380  ZQ Calibration   : PASS

 9126 12:40:55.673504  Jitter Meter     : NO K

 9127 12:40:55.673590  CBT Training     : PASS

 9128 12:40:55.677160  Write leveling   : PASS

 9129 12:40:55.680264  RX DQS gating    : PASS

 9130 12:40:55.680359  RX DQ/DQS(RDDQC) : PASS

 9131 12:40:55.683410  TX DQ/DQS        : PASS

 9132 12:40:55.686988  RX DATLAT        : PASS

 9133 12:40:55.687138  RX DQ/DQS(Engine): PASS

 9134 12:40:55.690418  TX OE            : PASS

 9135 12:40:55.690545  All Pass.

 9136 12:40:55.690633  

 9137 12:40:55.693527  DramC Write-DBI on

 9138 12:40:55.696903  	PER_BANK_REFRESH: Hybrid Mode

 9139 12:40:55.696995  TX_TRACKING: ON

 9140 12:40:55.706903  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0

 9141 12:40:55.713084  sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1

 9142 12:40:55.723209  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9143 12:40:55.727005  [FAST_K] Save calibration result to emmc

 9144 12:40:55.727121  sync common calibartion params.

 9145 12:40:55.729823  sync cbt_mode0:1, 1:1

 9146 12:40:55.733318  dram_init: ddr_geometry: 2

 9147 12:40:55.736566  dram_init: ddr_geometry: 2

 9148 12:40:55.736663  dram_init: ddr_geometry: 2

 9149 12:40:55.739665  0:dram_rank_size:100000000

 9150 12:40:55.743135  1:dram_rank_size:100000000

 9151 12:40:55.746832  sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000

 9152 12:40:55.749645  DFS_SHUFFLE_HW_MODE: ON

 9153 12:40:55.752832  dramc_set_vcore_voltage set vcore to 725000

 9154 12:40:55.756707  Read voltage for 1600, 0

 9155 12:40:55.756807  Vio18 = 0

 9156 12:40:55.759866  Vcore = 725000

 9157 12:40:55.759957  Vdram = 0

 9158 12:40:55.760044  Vddq = 0

 9159 12:40:55.760125  Vmddr = 0

 9160 12:40:55.762821  switch to 3200 Mbps bootup

 9161 12:40:55.766387  [DramcRunTimeConfig]

 9162 12:40:55.766480  PHYPLL

 9163 12:40:55.769868  DPM_CONTROL_AFTERK: ON

 9164 12:40:55.769998  PER_BANK_REFRESH: ON

 9165 12:40:55.772976  REFRESH_OVERHEAD_REDUCTION: ON

 9166 12:40:55.776190  CMD_PICG_NEW_MODE: OFF

 9167 12:40:55.776285  XRTWTW_NEW_MODE: ON

 9168 12:40:55.779482  XRTRTR_NEW_MODE: ON

 9169 12:40:55.779573  TX_TRACKING: ON

 9170 12:40:55.782752  RDSEL_TRACKING: OFF

 9171 12:40:55.786218  DQS Precalculation for DVFS: ON

 9172 12:40:55.786312  RX_TRACKING: OFF

 9173 12:40:55.786381  HW_GATING DBG: ON

 9174 12:40:55.789731  ZQCS_ENABLE_LP4: ON

 9175 12:40:55.792973  RX_PICG_NEW_MODE: ON

 9176 12:40:55.793064  TX_PICG_NEW_MODE: ON

 9177 12:40:55.796885  ENABLE_RX_DCM_DPHY: ON

 9178 12:40:55.799810  LOWPOWER_GOLDEN_SETTINGS(DCM): ON

 9179 12:40:55.799902  DUMMY_READ_FOR_TRACKING: OFF

 9180 12:40:55.802853  !!! SPM_CONTROL_AFTERK: OFF

 9181 12:40:55.806233  !!! SPM could not control APHY

 9182 12:40:55.809325  IMPEDANCE_TRACKING: ON

 9183 12:40:55.809420  TEMP_SENSOR: ON

 9184 12:40:55.812922  HW_SAVE_FOR_SR: OFF

 9185 12:40:55.816230  CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF

 9186 12:40:55.819286  PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF

 9187 12:40:55.819383  Read ODT Tracking: ON

 9188 12:40:55.823140  Refresh Rate DeBounce: ON

 9189 12:40:55.826138  DFS_NO_QUEUE_FLUSH: ON

 9190 12:40:55.829426  DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF

 9191 12:40:55.829526  ENABLE_DFS_RUNTIME_MRW: OFF

 9192 12:40:55.832716  DDR_RESERVE_NEW_MODE: ON

 9193 12:40:55.835879  MR_CBT_SWITCH_FREQ: ON

 9194 12:40:55.835974  =========================

 9195 12:40:55.856157  [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)

 9196 12:40:55.859167  dram_init: ddr_geometry: 2

 9197 12:40:55.877736  [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)

 9198 12:40:55.880736  dram_init: dram init end (result: 0)

 9199 12:40:55.887705  DRAM-K: Full calibration passed in 24489 msecs

 9200 12:40:55.890997  MRC: failed to locate region type 0.

 9201 12:40:55.891100  DRAM rank0 size:0x100000000,

 9202 12:40:55.894154  DRAM rank1 size=0x100000000

 9203 12:40:55.903924  Mapping address range [0x40000000:0x240000000) as     cacheable | read-write | non-secure | normal

 9204 12:40:55.910633  Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal

 9205 12:40:55.917582  Backing address range [0x40000000:0x80000000) with new page table @0x00112000

 9206 12:40:55.923831  Backing address range [0x40000000:0x40200000) with new page table @0x00113000

 9207 12:40:55.927361  DRAM rank0 size:0x100000000,

 9208 12:40:55.930720  DRAM rank1 size=0x100000000

 9209 12:40:55.930819  CBMEM:

 9210 12:40:55.933858  IMD: root @ 0xfffff000 254 entries.

 9211 12:40:55.937332  IMD: root @ 0xffffec00 62 entries.

 9212 12:40:55.940704  FMAP: area RO_VPD found @ 3f8000 (32768 bytes)

 9213 12:40:55.943811  WARNING: RO_VPD is uninitialized or empty.

 9214 12:40:55.950597  FMAP: area RW_VPD found @ 577000 (16384 bytes)

 9215 12:40:55.957905  CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80

 9216 12:40:55.970159  read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps

 9217 12:40:55.981516  BS: romstage times (exec / console): total (unknown) / 23991 ms

 9218 12:40:55.981661  

 9219 12:40:55.981728  

 9220 12:40:55.991429  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...

 9221 12:40:55.995072  ARM64: Exception handlers installed.

 9222 12:40:55.998316  ARM64: Testing exception

 9223 12:40:56.001534  ARM64: Done test exception

 9224 12:40:56.001629  Enumerating buses...

 9225 12:40:56.004935  Show all devs... Before device enumeration.

 9226 12:40:56.008070  Root Device: enabled 1

 9227 12:40:56.011460  CPU_CLUSTER: 0: enabled 1

 9228 12:40:56.011555  CPU: 00: enabled 1

 9229 12:40:56.014879  Compare with tree...

 9230 12:40:56.014973  Root Device: enabled 1

 9231 12:40:56.018076   CPU_CLUSTER: 0: enabled 1

 9232 12:40:56.021583    CPU: 00: enabled 1

 9233 12:40:56.021679  Root Device scanning...

 9234 12:40:56.024707  scan_static_bus for Root Device

 9235 12:40:56.028944  CPU_CLUSTER: 0 enabled

 9236 12:40:56.031625  scan_static_bus for Root Device done

 9237 12:40:56.035275  scan_bus: bus Root Device finished in 8 msecs

 9238 12:40:56.035373  done

 9239 12:40:56.041594  BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms

 9240 12:40:56.044648  FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)

 9241 12:40:56.051273  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

 9242 12:40:56.054511  BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms

 9243 12:40:56.057906  Allocating resources...

 9244 12:40:56.061556  Reading resources...

 9245 12:40:56.064660  Root Device read_resources bus 0 link: 0

 9246 12:40:56.064757  DRAM rank0 size:0x100000000,

 9247 12:40:56.067800  DRAM rank1 size=0x100000000

 9248 12:40:56.071668  CPU_CLUSTER: 0 read_resources bus 0 link: 0

 9249 12:40:56.074644  CPU: 00 missing read_resources

 9250 12:40:56.077915  CPU_CLUSTER: 0 read_resources bus 0 link: 0 done

 9251 12:40:56.084301  Root Device read_resources bus 0 link: 0 done

 9252 12:40:56.084417  Done reading resources.

 9253 12:40:56.091681  Show resources in subtree (Root Device)...After reading.

 9254 12:40:56.094733   Root Device child on link 0 CPU_CLUSTER: 0

 9255 12:40:56.097514    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9256 12:40:56.107953    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9257 12:40:56.108088     CPU: 00

 9258 12:40:56.110753  Root Device assign_resources, bus 0 link: 0

 9259 12:40:56.114149  CPU_CLUSTER: 0 missing set_resources

 9260 12:40:56.120894  Root Device assign_resources, bus 0 link: 0 done

 9261 12:40:56.121006  Done setting resources.

 9262 12:40:56.127266  Show resources in subtree (Root Device)...After assigning values.

 9263 12:40:56.130954   Root Device child on link 0 CPU_CLUSTER: 0

 9264 12:40:56.134530    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9265 12:40:56.144235    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9266 12:40:56.144363     CPU: 00

 9267 12:40:56.147419  Done allocating resources.

 9268 12:40:56.150939  BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms

 9269 12:40:56.154706  Enabling resources...

 9270 12:40:56.154801  done.

 9271 12:40:56.160895  BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms

 9272 12:40:56.161005  Initializing devices...

 9273 12:40:56.163958  Root Device init

 9274 12:40:56.164048  init hardware done!

 9275 12:40:56.167729  0x00000018: ctrlr->caps

 9276 12:40:56.170718  52.000 MHz: ctrlr->f_max

 9277 12:40:56.170813  0.400 MHz: ctrlr->f_min

 9278 12:40:56.173910  0x40ff8080: ctrlr->voltages

 9279 12:40:56.174036  sclk: 390625

 9280 12:40:56.177233  Bus Width = 1

 9281 12:40:56.177319  sclk: 390625

 9282 12:40:56.181039  Bus Width = 1

 9283 12:40:56.181131  Early init status = 3

 9284 12:40:56.187593  out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00 

 9285 12:40:56.190897  in-header: 03 fc 00 00 01 00 00 00 

 9286 12:40:56.190995  in-data: 00 

 9287 12:40:56.197259  out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01 

 9288 12:40:56.200503  in-header: 03 fd 00 00 00 00 00 00 

 9289 12:40:56.203749  in-data: 

 9290 12:40:56.207037  out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00 

 9291 12:40:56.210596  in-header: 03 fc 00 00 01 00 00 00 

 9292 12:40:56.214200  in-data: 00 

 9293 12:40:56.217651  out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01 

 9294 12:40:56.222182  in-header: 03 fd 00 00 00 00 00 00 

 9295 12:40:56.224951  in-data: 

 9296 12:40:56.228384  [SSUSB] Setting up USB HOST controller...

 9297 12:40:56.231857  [SSUSB] u3phy_ports_enable u2p:1, u3p:1

 9298 12:40:56.235180  [SSUSB] phy power-on done.

 9299 12:40:56.238457  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

 9300 12:40:56.245048  CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c

 9301 12:40:56.248276  mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)

 9302 12:40:56.254742  CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c

 9303 12:40:56.261646  read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps

 9304 12:40:56.268472  mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)

 9305 12:40:56.274933  CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204

 9306 12:40:56.281524  read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps

 9307 12:40:56.284708  SPM: binary array size = 0x9dc

 9308 12:40:56.288025  SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)

 9309 12:40:56.294666  spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18

 9310 12:40:56.301176  mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)

 9311 12:40:56.304875  SPM: spm_init done in 34 msecs, spm pc = 0x3f4

 9312 12:40:56.311285  configure_display: Starting display init

 9313 12:40:56.345019  anx7625_power_on_init: Init interface.

 9314 12:40:56.348241  anx7625_disable_pd_protocol: Disabled PD feature.

 9315 12:40:56.351738  anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.

 9316 12:40:56.379355  anx7625_start_dp_work: Secure OCM version=00

 9317 12:40:56.382660  anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91

 9318 12:40:56.397523  sp_tx_get_edid_block: EDID Block = 1

 9319 12:40:56.499979  Extracted contents:

 9320 12:40:56.503585  header:          00 ff ff ff ff ff ff 00

 9321 12:40:56.507516  serial number:   26 cf 7d 05 00 00 00 00 00 1e

 9322 12:40:56.510249  version:         01 04

 9323 12:40:56.513600  basic params:    95 1f 11 78 0a

 9324 12:40:56.516706  chroma info:     76 90 94 55 54 90 27 21 50 54

 9325 12:40:56.519972  established:     00 00 00

 9326 12:40:56.526966  standard:        01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01

 9327 12:40:56.530007  descriptor 1:    38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19

 9328 12:40:56.536930  descriptor 2:    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

 9329 12:40:56.543568  descriptor 3:    00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20

 9330 12:40:56.550124  descriptor 4:    00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a

 9331 12:40:56.553197  extensions:      00

 9332 12:40:56.553296  checksum:        fb

 9333 12:40:56.553364  

 9334 12:40:56.556834  Manufacturer: IVO Model 57d Serial Number 0

 9335 12:40:56.559991  Made week 0 of 2020

 9336 12:40:56.560082  EDID version: 1.4

 9337 12:40:56.563583  Digital display

 9338 12:40:56.566602  6 bits per primary color channel

 9339 12:40:56.566695  DisplayPort interface

 9340 12:40:56.570105  Maximum image size: 31 cm x 17 cm

 9341 12:40:56.573122  Gamma: 220%

 9342 12:40:56.573211  Check DPMS levels

 9343 12:40:56.576725  Supported color formats: RGB 4:4:4, YCrCb 4:2:2

 9344 12:40:56.580097  First detailed timing is preferred timing

 9345 12:40:56.583403  Established timings supported:

 9346 12:40:56.586388  Standard timings supported:

 9347 12:40:56.586493  Detailed timings

 9348 12:40:56.593439  Hex of detail: 383680a07038204018303c0035ae10000019

 9349 12:40:56.596598  Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm

 9350 12:40:56.603529                 0780 0798 07c8 0820 hborder 0

 9351 12:40:56.606074                 0438 043b 0447 0458 vborder 0

 9352 12:40:56.609682                 -hsync -vsync

 9353 12:40:56.609778  Did detailed timing

 9354 12:40:56.616101  Hex of detail: 000000000000000000000000000000000000

 9355 12:40:56.616206  Manufacturer-specified data, tag 0

 9356 12:40:56.622629  Hex of detail: 000000fe00496e666f566973696f6e0a2020

 9357 12:40:56.625989  ASCII string: InfoVision

 9358 12:40:56.629240  Hex of detail: 000000fe00523134304e574635205248200a

 9359 12:40:56.633104  ASCII string: R140NWF5 RH 

 9360 12:40:56.633203  Checksum

 9361 12:40:56.635895  Checksum: 0xfb (valid)

 9362 12:40:56.639357  configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz

 9363 12:40:56.642640  DSI data_rate: 832800000 bps

 9364 12:40:56.649179  anx7625_parse_edid: detected IVO panel, use k value 0x3b

 9365 12:40:56.652532  anx7625_parse_edid: pixelclock(138800).

 9366 12:40:56.655974   hactive(1920), hsync(48), hfp(24), hbp(88)

 9367 12:40:56.659459   vactive(1080), vsync(12), vfp(3), vbp(17)

 9368 12:40:56.662261  anx7625_dsi_config: config dsi.

 9369 12:40:56.669002  anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).

 9370 12:40:56.681992  anx7625_dsi_config: success to config DSI

 9371 12:40:56.685548  anx7625_dp_start: MIPI phy setup OK.

 9372 12:40:56.689150  mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4

 9373 12:40:56.692079  mtk_ddp_mode_set invalid vrefresh 60

 9374 12:40:56.695351  main_disp_path_setup

 9375 12:40:56.695447  ovl_layer_smi_id_en

 9376 12:40:56.698711  ovl_layer_smi_id_en

 9377 12:40:56.698839  ccorr_config

 9378 12:40:56.698939  aal_config

 9379 12:40:56.702336  gamma_config

 9380 12:40:56.702430  postmask_config

 9381 12:40:56.705176  dither_config

 9382 12:40:56.708846  framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32

 9383 12:40:56.715087                     x_res x y_res: 1920 x 1080, size: 8294400 at 0x0

 9384 12:40:56.718660  Root Device init finished in 551 msecs

 9385 12:40:56.718758  CPU_CLUSTER: 0 init

 9386 12:40:56.728508  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | device

 9387 12:40:56.731930  INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff

 9388 12:40:56.735437  APU_MBOX 0x190000b0 = 0x10001

 9389 12:40:56.738843  APU_MBOX 0x190001b0 = 0x10001

 9390 12:40:56.741912  APU_MBOX 0x190005b0 = 0x10001

 9391 12:40:56.745191  APU_MBOX 0x190006b0 = 0x10001

 9392 12:40:56.748653  CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c

 9393 12:40:56.761100  read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps

 9394 12:40:56.773614  mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)

 9395 12:40:56.780069  CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0

 9396 12:40:56.791798  read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps

 9397 12:40:56.800739  mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)

 9398 12:40:56.804117  CPU_CLUSTER: 0 init finished in 81 msecs

 9399 12:40:56.807855  Devices initialized

 9400 12:40:56.810911  Show all devs... After init.

 9401 12:40:56.811009  Root Device: enabled 1

 9402 12:40:56.814231  CPU_CLUSTER: 0: enabled 1

 9403 12:40:56.817606  CPU: 00: enabled 1

 9404 12:40:56.820730  BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms

 9405 12:40:56.824139  FMAP: area RW_ELOG found @ 57f000 (4096 bytes)

 9406 12:40:56.827467  ELOG: NV offset 0x57f000 size 0x1000

 9407 12:40:56.834682  read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps

 9408 12:40:56.841118  ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024

 9409 12:40:56.844346  ELOG: Event(17) added with size 13 at 2024-02-05 12:40:21 UTC

 9410 12:40:56.847819  out: cmd=0x121: 03 db 21 01 00 00 00 00 

 9411 12:40:56.852448  in-header: 03 41 00 00 2c 00 00 00 

 9412 12:40:56.865634  in-data: 1e 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 

 9413 12:40:56.872584  ELOG: Event(A1) added with size 10 at 2024-02-05 12:40:21 UTC

 9414 12:40:56.879222  elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b

 9415 12:40:56.885511  ELOG: Event(A0) added with size 9 at 2024-02-05 12:40:21 UTC

 9416 12:40:56.889008  elog_add_boot_reason: Logged dev mode boot

 9417 12:40:56.892232  BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms

 9418 12:40:56.895574  Finalize devices...

 9419 12:40:56.895660  Devices finalized

 9420 12:40:56.902076  BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms

 9421 12:40:56.905350  Writing coreboot table at 0xffe64000

 9422 12:40:56.909206   0. 000000000010a000-0000000000113fff: RAMSTAGE

 9423 12:40:56.912183   1. 0000000040000000-00000000400fffff: RAM

 9424 12:40:56.915916   2. 0000000040100000-000000004032afff: RAMSTAGE

 9425 12:40:56.922688   3. 000000004032b000-00000000545fffff: RAM

 9426 12:40:56.925639   4. 0000000054600000-000000005465ffff: BL31

 9427 12:40:56.928955   5. 0000000054660000-00000000ffe63fff: RAM

 9428 12:40:56.932439   6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES

 9429 12:40:56.938918   7. 0000000100000000-000000023fffffff: RAM

 9430 12:40:56.939005  Passing 5 GPIOs to payload:

 9431 12:40:56.945612              NAME |       PORT | POLARITY |     VALUE

 9432 12:40:56.948745          EC in RW | 0x000000aa |      low | undefined

 9433 12:40:56.955504      EC interrupt | 0x00000005 |      low | undefined

 9434 12:40:56.958889     TPM interrupt | 0x000000ab |     high | undefined

 9435 12:40:56.962309    SD card detect | 0x00000011 |     high | undefined

 9436 12:40:56.968855    speaker enable | 0x00000093 |     high | undefined

 9437 12:40:56.971940  out: cmd=0x6: 03 f7 06 00 00 00 00 00 

 9438 12:40:56.975452  in-header: 03 f9 00 00 02 00 00 00 

 9439 12:40:56.975537  in-data: 02 00 

 9440 12:40:56.978385  ADC[4]: Raw value=901032 ID=7

 9441 12:40:56.981868  ADC[3]: Raw value=213179 ID=1

 9442 12:40:56.982016  RAM Code: 0x71

 9443 12:40:56.985497  ADC[6]: Raw value=74502 ID=0

 9444 12:40:56.988274  ADC[5]: Raw value=211703 ID=1

 9445 12:40:56.988358  SKU Code: 0x1

 9446 12:40:56.995228  Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum d248

 9447 12:40:56.998229  coreboot table: 964 bytes.

 9448 12:40:57.001752  IMD ROOT    0. 0xfffff000 0x00001000

 9449 12:40:57.005014  IMD SMALL   1. 0xffffe000 0x00001000

 9450 12:40:57.008475  RO MCACHE   2. 0xffffc000 0x00001104

 9451 12:40:57.011629  CONSOLE     3. 0xfff7c000 0x00080000

 9452 12:40:57.015072  FMAP        4. 0xfff7b000 0x00000452

 9453 12:40:57.018116  TIME STAMP  5. 0xfff7a000 0x00000910

 9454 12:40:57.021551  VBOOT WORK  6. 0xfff66000 0x00014000

 9455 12:40:57.024851  RAMOOPS     7. 0xffe66000 0x00100000

 9456 12:40:57.028699  COREBOOT    8. 0xffe64000 0x00002000

 9457 12:40:57.028785  IMD small region:

 9458 12:40:57.031819    IMD ROOT    0. 0xffffec00 0x00000400

 9459 12:40:57.034918    VPD         1. 0xffffeb80 0x0000006c

 9460 12:40:57.038248    MMC STATUS  2. 0xffffeb60 0x00000004

 9461 12:40:57.044879  BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms

 9462 12:40:57.048234  Probing TPM:  done!

 9463 12:40:57.051943  Connected to device vid:did:rid of 1ae0:0028:00

 9464 12:40:57.061842  Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c

 9465 12:40:57.065470  Initialized TPM device CR50 revision 0

 9466 12:40:57.068864  Checking cr50 for pending updates

 9467 12:40:57.072166  Reading cr50 TPM mode

 9468 12:40:57.080970  BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms

 9469 12:40:57.087462  CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098

 9470 12:40:57.127246  read SPI 0x3990ec 0x4f1b0: 34845 us, 9298 KB/s, 74.384 Mbps

 9471 12:40:57.130754  Checking segment from ROM address 0x40100000

 9472 12:40:57.133745  Checking segment from ROM address 0x4010001c

 9473 12:40:57.140863  Loading segment from ROM address 0x40100000

 9474 12:40:57.140949    code (compression=0)

 9475 12:40:57.147176    New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178

 9476 12:40:57.157081  Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178

 9477 12:40:57.157167  it's not compressed!

 9478 12:40:57.164099  [ 0x80000000, 8004f178, 0x821a7280) <- 40100038

 9479 12:40:57.167219  Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108

 9480 12:40:57.187461  Loading segment from ROM address 0x4010001c

 9481 12:40:57.187559    Entry Point 0x80000000

 9482 12:40:57.191168  Loaded segments

 9483 12:40:57.194142  BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms

 9484 12:40:57.200990  Jumping to boot code at 0x80000000(0xffe64000)

 9485 12:40:57.207846  CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes

 9486 12:40:57.214396  CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290

 9487 12:40:57.222214  read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps

 9488 12:40:57.225350  Checking segment from ROM address 0x40100000

 9489 12:40:57.228932  Checking segment from ROM address 0x4010001c

 9490 12:40:57.235495  Loading segment from ROM address 0x40100000

 9491 12:40:57.235590    code (compression=1)

 9492 12:40:57.242355    New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470

 9493 12:40:57.251984  Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470

 9494 12:40:57.252074  using LZMA

 9495 12:40:57.260235  [ 0x54600000, 54614abc, 0x5462e000) <- 40100038

 9496 12:40:57.267133  Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544

 9497 12:40:57.270538  Loading segment from ROM address 0x4010001c

 9498 12:40:57.270624    Entry Point 0x54601000

 9499 12:40:57.273936  Loaded segments

 9500 12:40:57.277399  NOTICE:  MT8192 bl31_setup

 9501 12:40:57.283997  NOTICE:  BL31: v2.4(debug):v2.4-448-gce3ebc861

 9502 12:40:57.287592  NOTICE:  BL31: Built : Sat Sep 11 09:59:37 UTC 2021

 9503 12:40:57.290786  WARNING: region 0:

 9504 12:40:57.294222  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9505 12:40:57.294306  WARNING: region 1:

 9506 12:40:57.300534  WARNING: 	sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d

 9507 12:40:57.303757  WARNING: region 2:

 9508 12:40:57.307228  WARNING: 	sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d

 9509 12:40:57.310346  WARNING: region 3:

 9510 12:40:57.314097  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9511 12:40:57.316998  WARNING: region 4:

 9512 12:40:57.323852  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9513 12:40:57.323938  WARNING: region 5:

 9514 12:40:57.327065  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9515 12:40:57.330410  WARNING: region 6:

 9516 12:40:57.333910  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9517 12:40:57.337076  WARNING: region 7:

 9518 12:40:57.340362  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9519 12:40:57.346859  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000

 9520 12:40:57.350250  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0

 9521 12:40:57.353644  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff

 9522 12:40:57.360564  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff

 9523 12:40:57.364050  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff

 9524 12:40:57.370177  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00

 9525 12:40:57.373794  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff

 9526 12:40:57.377118  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff

 9527 12:40:57.383549  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff

 9528 12:40:57.386949  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff

 9529 12:40:57.390858  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff

 9530 12:40:57.397246  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff

 9531 12:40:57.400427  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff

 9532 12:40:57.403772  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff

 9533 12:40:57.410182  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff

 9534 12:40:57.413538  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff

 9535 12:40:57.420196  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff

 9536 12:40:57.423505  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff

 9537 12:40:57.426970  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff

 9538 12:40:57.433919  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff

 9539 12:40:57.437158  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff

 9540 12:40:57.440606  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff

 9541 12:40:57.447528  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff

 9542 12:40:57.451239  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff

 9543 12:40:57.457479  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff

 9544 12:40:57.461068  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff

 9545 12:40:57.463984  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff

 9546 12:40:57.470751  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff

 9547 12:40:57.474368  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff

 9548 12:40:57.480904  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff

 9549 12:40:57.484072  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff

 9550 12:40:57.487399  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff

 9551 12:40:57.494071  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0

 9552 12:40:57.497365  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0

 9553 12:40:57.500860  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0

 9554 12:40:57.504391  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0

 9555 12:40:57.507216  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0

 9556 12:40:57.514408  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0

 9557 12:40:57.517664  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0

 9558 12:40:57.520735  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0

 9559 12:40:57.524041  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0

 9560 12:40:57.530866  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0

 9561 12:40:57.534147  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0

 9562 12:40:57.537402  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0

 9563 12:40:57.540667  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0

 9564 12:40:57.547474  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0

 9565 12:40:57.550829  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0

 9566 12:40:57.554493  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0

 9567 12:40:57.561218  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff

 9568 12:40:57.564267  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff

 9569 12:40:57.571069  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff

 9570 12:40:57.574142  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff

 9571 12:40:57.577581  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff

 9572 12:40:57.584366  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff

 9573 12:40:57.587529  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff

 9574 12:40:57.594334  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff

 9575 12:40:57.597689  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff

 9576 12:40:57.600804  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff

 9577 12:40:57.607592  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff

 9578 12:40:57.611267  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff

 9579 12:40:57.618122  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff

 9580 12:40:57.621315  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff

 9581 12:40:57.627588  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff

 9582 12:40:57.631117  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff

 9583 12:40:57.637638  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff

 9584 12:40:57.640911  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff

 9585 12:40:57.644170  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff

 9586 12:40:57.650834  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff

 9587 12:40:57.654364  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff

 9588 12:40:57.660733  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff

 9589 12:40:57.664281  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff

 9590 12:40:57.670995  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff

 9591 12:40:57.674159  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff

 9592 12:40:57.677583  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff

 9593 12:40:57.684286  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff

 9594 12:40:57.687672  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff

 9595 12:40:57.694309  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff

 9596 12:40:57.697774  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff

 9597 12:40:57.704591  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff

 9598 12:40:57.707499  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff

 9599 12:40:57.711045  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff

 9600 12:40:57.717725  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff

 9601 12:40:57.721238  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff

 9602 12:40:57.727431  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff

 9603 12:40:57.731054  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff

 9604 12:40:57.737461  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff

 9605 12:40:57.740950  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff

 9606 12:40:57.744542  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff

 9607 12:40:57.750751  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff

 9608 12:40:57.754573  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff

 9609 12:40:57.760954  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff

 9610 12:40:57.764727  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff

 9611 12:40:57.770845  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff

 9612 12:40:57.774338  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff

 9613 12:40:57.777652  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff

 9614 12:40:57.784534  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff

 9615 12:40:57.787762  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0

 9616 12:40:57.791589  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0

 9617 12:40:57.797841  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0

 9618 12:40:57.800989  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0

 9619 12:40:57.804581  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0

 9620 12:40:57.807763  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff

 9621 12:40:57.814772  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff

 9622 12:40:57.817624  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff

 9623 12:40:57.824356  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff

 9624 12:40:57.827983  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff

 9625 12:40:57.834515  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff

 9626 12:40:57.837502  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff

 9627 12:40:57.841303  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff

 9628 12:40:57.847719  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff

 9629 12:40:57.851126  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff

 9630 12:40:57.854240  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff

 9631 12:40:57.861331  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff

 9632 12:40:57.864283  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff

 9633 12:40:57.870934  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff

 9634 12:40:57.874324  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff

 9635 12:40:57.877818  INFO:    [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18

 9636 12:40:57.884501  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000

 9637 12:40:57.887620  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004

 9638 12:40:57.891109  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0

 9639 12:40:57.894593  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0

 9640 12:40:57.901490  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0

 9641 12:40:57.904621  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0

 9642 12:40:57.907985  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000

 9643 12:40:57.911092  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff

 9644 12:40:57.917851  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff

 9645 12:40:57.921175  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff

 9646 12:40:57.928044  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff

 9647 12:40:57.931327  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff

 9648 12:40:57.934728  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff

 9649 12:40:57.941796  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff

 9650 12:40:57.944621  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc

 9651 12:40:57.951345  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff

 9652 12:40:57.954748  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf

 9653 12:40:57.958138  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff

 9654 12:40:57.964768  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc

 9655 12:40:57.968191  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff

 9656 12:40:57.971319  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff

 9657 12:40:57.977830  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff

 9658 12:40:57.981284  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff

 9659 12:40:57.987885  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff

 9660 12:40:57.991386  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff

 9661 12:40:57.994641  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff

 9662 12:40:58.001139  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff

 9663 12:40:58.004718  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff

 9664 12:40:58.008555  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff

 9665 12:40:58.014728  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff

 9666 12:40:58.017891  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff

 9667 12:40:58.024689  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff

 9668 12:40:58.028296  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff

 9669 12:40:58.031718  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff

 9670 12:40:58.038606  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff

 9671 12:40:58.041568  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff

 9672 12:40:58.048356  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff

 9673 12:40:58.051343  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff

 9674 12:40:58.055084  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff

 9675 12:40:58.061849  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff

 9676 12:40:58.065018  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff

 9677 12:40:58.068337  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff

 9678 12:40:58.074796  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff

 9679 12:40:58.078109  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff

 9680 12:40:58.085309  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff

 9681 12:40:58.087962  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff

 9682 12:40:58.091623  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff

 9683 12:40:58.098385  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff

 9684 12:40:58.101619  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff

 9685 12:40:58.108204  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff

 9686 12:40:58.111462  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff

 9687 12:40:58.114840  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff

 9688 12:40:58.121123  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff

 9689 12:40:58.124407  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff

 9690 12:40:58.131256  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff

 9691 12:40:58.134644  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff

 9692 12:40:58.137793  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff

 9693 12:40:58.144966  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff

 9694 12:40:58.148043  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff

 9695 12:40:58.154612  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff

 9696 12:40:58.157751  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff

 9697 12:40:58.161100  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff

 9698 12:40:58.168208  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff

 9699 12:40:58.171301  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff

 9700 12:40:58.175068  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff

 9701 12:40:58.181356  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff

 9702 12:40:58.184858  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff

 9703 12:40:58.191364  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff

 9704 12:40:58.194393  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff

 9705 12:40:58.198037  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff

 9706 12:40:58.204873  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff

 9707 12:40:58.208132  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff

 9708 12:40:58.214267  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff

 9709 12:40:58.217965  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff

 9710 12:40:58.221022  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff

 9711 12:40:58.227736  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff

 9712 12:40:58.231517  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff

 9713 12:40:58.237577  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff

 9714 12:40:58.241189  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff

 9715 12:40:58.247711  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff

 9716 12:40:58.251121  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff

 9717 12:40:58.254421  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff

 9718 12:40:58.261127  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff

 9719 12:40:58.264403  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff

 9720 12:40:58.270793  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff

 9721 12:40:58.274151  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff

 9722 12:40:58.277345  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff

 9723 12:40:58.284020  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff

 9724 12:40:58.287639  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff

 9725 12:40:58.293883  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff

 9726 12:40:58.297344  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff

 9727 12:40:58.303976  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff

 9728 12:40:58.307243  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff

 9729 12:40:58.310863  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff

 9730 12:40:58.317279  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff

 9731 12:40:58.320780  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff

 9732 12:40:58.327178  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff

 9733 12:40:58.330654  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff

 9734 12:40:58.333704  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff

 9735 12:40:58.341012  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff

 9736 12:40:58.343821  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff

 9737 12:40:58.350522  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff

 9738 12:40:58.353610  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff

 9739 12:40:58.360176  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff

 9740 12:40:58.363786  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff

 9741 12:40:58.366995  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff

 9742 12:40:58.373935  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff

 9743 12:40:58.376963  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff

 9744 12:40:58.383839  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff

 9745 12:40:58.386774  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff

 9746 12:40:58.393190  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff

 9747 12:40:58.396826  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff

 9748 12:40:58.400125  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0

 9749 12:40:58.403348  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0

 9750 12:40:58.409912  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0

 9751 12:40:58.413165  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0

 9752 12:40:58.416615  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0

 9753 12:40:58.419834  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff

 9754 12:40:58.426917  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff

 9755 12:40:58.430002  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff

 9756 12:40:58.436402  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff

 9757 12:40:58.439781  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf

 9758 12:40:58.443019  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff

 9759 12:40:58.449808  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff

 9760 12:40:58.453229  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff

 9761 12:40:58.456770  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff

 9762 12:40:58.462994  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf

 9763 12:40:58.466331  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff

 9764 12:40:58.469839  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff

 9765 12:40:58.476789  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff

 9766 12:40:58.479801  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff

 9767 12:40:58.486596  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf

 9768 12:40:58.489586  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff

 9769 12:40:58.493145  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff

 9770 12:40:58.499559  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff

 9771 12:40:58.502969  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff

 9772 12:40:58.506167  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf

 9773 12:40:58.512773  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff

 9774 12:40:58.516118  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff

 9775 12:40:58.522756  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff

 9776 12:40:58.526161  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff

 9777 12:40:58.529557  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf

 9778 12:40:58.536248  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff

 9779 12:40:58.539447  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff

 9780 12:40:58.542665  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff

 9781 12:40:58.549221  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff

 9782 12:40:58.552877  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf

 9783 12:40:58.555976  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff

 9784 12:40:58.563198  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff

 9785 12:40:58.566065  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff

 9786 12:40:58.572436  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff

 9787 12:40:58.575926  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf

 9788 12:40:58.579491  INFO:    [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0

 9789 12:40:58.582607  INFO:    [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3

 9790 12:40:58.585754  INFO:    [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3

 9791 12:40:58.592469  INFO:    [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3

 9792 12:40:58.595785  INFO:    [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0

 9793 12:40:58.599035  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400

 9794 12:40:58.602562  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0

 9795 12:40:58.609250  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0

 9796 12:40:58.612839  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0

 9797 12:40:58.616310  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0

 9798 12:40:58.618933  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0

 9799 12:40:58.625464  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000

 9800 12:40:58.629188  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0

 9801 12:40:58.632142  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff

 9802 12:40:58.638939  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff

 9803 12:40:58.642098  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff

 9804 12:40:58.648608  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff

 9805 12:40:58.652189  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff

 9806 12:40:58.658756  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff

 9807 12:40:58.662165  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff

 9808 12:40:58.665309  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f

 9809 12:40:58.671838  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3

 9810 12:40:58.675281  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff

 9811 12:40:58.682297  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff

 9812 12:40:58.685374  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff

 9813 12:40:58.689119  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff

 9814 12:40:58.695264  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff

 9815 12:40:58.698597  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff

 9816 12:40:58.705255  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f

 9817 12:40:58.708638  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff

 9818 12:40:58.711988  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff

 9819 12:40:58.718638  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff

 9820 12:40:58.721637  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff

 9821 12:40:58.728215  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff

 9822 12:40:58.731797  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff

 9823 12:40:58.738262  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff

 9824 12:40:58.741591  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f

 9825 12:40:58.744823  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff

 9826 12:40:58.751478  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff

 9827 12:40:58.754917  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff

 9828 12:40:58.761413  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff

 9829 12:40:58.765078  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff

 9830 12:40:58.768058  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff

 9831 12:40:58.774699  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff

 9832 12:40:58.778229  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f

 9833 12:40:58.784470  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff

 9834 12:40:58.788151  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff

 9835 12:40:58.791210  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff

 9836 12:40:58.798270  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff

 9837 12:40:58.801278  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff

 9838 12:40:58.807903  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff

 9839 12:40:58.811242  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff

 9840 12:40:58.814945  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f

 9841 12:40:58.821170  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff

 9842 12:40:58.824633  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff

 9843 12:40:58.831714  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff

 9844 12:40:58.834517  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff

 9845 12:40:58.841096  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff

 9846 12:40:58.844762  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff

 9847 12:40:58.848031  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff

 9848 12:40:58.854662  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f

 9849 12:40:58.858244  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff

 9850 12:40:58.864356  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff

 9851 12:40:58.867845  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff

 9852 12:40:58.871599  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff

 9853 12:40:58.877521  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff

 9854 12:40:58.880913  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff

 9855 12:40:58.887411  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff

 9856 12:40:58.890884  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f

 9857 12:40:58.894587  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff

 9858 12:40:58.900933  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff

 9859 12:40:58.903848  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff

 9860 12:40:58.910748  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff

 9861 12:40:58.914394  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff

 9862 12:40:58.920715  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff

 9863 12:40:58.924244  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff

 9864 12:40:58.927146  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f

 9865 12:40:58.934071  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff

 9866 12:40:58.937181  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff

 9867 12:40:58.943760  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff

 9868 12:40:58.947540  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff

 9869 12:40:58.951352  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff

 9870 12:40:58.957410  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff

 9871 12:40:58.960527  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff

 9872 12:40:58.967283  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f

 9873 12:40:58.970437  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff

 9874 12:40:58.974033  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff

 9875 12:40:58.980618  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff

 9876 12:40:58.983921  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff

 9877 12:40:58.990693  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff

 9878 12:40:58.993902  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff

 9879 12:40:59.000431  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff

 9880 12:40:59.003922  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f

 9881 12:40:59.007140  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff

 9882 12:40:59.013994  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff

 9883 12:40:59.017212  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff

 9884 12:40:59.023710  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff

 9885 12:40:59.026884  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff

 9886 12:40:59.033533  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff

 9887 12:40:59.036802  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff

 9888 12:40:59.043418  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f

 9889 12:40:59.046758  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff

 9890 12:40:59.049828  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff

 9891 12:40:59.056723  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff

 9892 12:40:59.060207  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff

 9893 12:40:59.066379  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff

 9894 12:40:59.069772  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff

 9895 12:40:59.076548  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff

 9896 12:40:59.079911  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f

 9897 12:40:59.086503  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff

 9898 12:40:59.089818  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff

 9899 12:40:59.092894  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff

 9900 12:40:59.099638  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff

 9901 12:40:59.102914  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff

 9902 12:40:59.109679  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff

 9903 12:40:59.113017  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff

 9904 12:40:59.119310  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f

 9905 12:40:59.122906  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff

 9906 12:40:59.125903  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff

 9907 12:40:59.132617  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff

 9908 12:40:59.135876  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff

 9909 12:40:59.142951  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff

 9910 12:40:59.146234  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff

 9911 12:40:59.152411  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff

 9912 12:40:59.155909  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f

 9913 12:40:59.162238  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff

 9914 12:40:59.165812  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff

 9915 12:40:59.169004  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff

 9916 12:40:59.175419  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff

 9917 12:40:59.178798  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff

 9918 12:40:59.185482  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff

 9919 12:40:59.188869  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff

 9920 12:40:59.195459  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f

 9921 12:40:59.198621  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0

 9922 12:40:59.201901  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000

 9923 12:40:59.208713  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff

 9924 12:40:59.212420  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff

 9925 12:40:59.218309  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3

 9926 12:40:59.221654  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff

 9927 12:40:59.228518  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff

 9928 12:40:59.231910  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff

 9929 12:40:59.238342  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff

 9930 12:40:59.242050  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff

 9931 12:40:59.248463  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff

 9932 12:40:59.251748  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff

 9933 12:40:59.258051  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff

 9934 12:40:59.261741  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff

 9935 12:40:59.267976  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff

 9936 12:40:59.271536  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff

 9937 12:40:59.278216  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff

 9938 12:40:59.281251  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff

 9939 12:40:59.287942  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff

 9940 12:40:59.291220  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff

 9941 12:40:59.297930  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff

 9942 12:40:59.301275  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff

 9943 12:40:59.308266  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff

 9944 12:40:59.311334  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff

 9945 12:40:59.318040  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff

 9946 12:40:59.321164  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff

 9947 12:40:59.327728  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff

 9948 12:40:59.331253  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff

 9949 12:40:59.337550  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff

 9950 12:40:59.341029  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff

 9951 12:40:59.347805  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff

 9952 12:40:59.350694  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff

 9953 12:40:59.354745  INFO:    [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0

 9954 12:40:59.357378  INFO:    [APUAPC] vio 0

 9955 12:40:59.364381  INFO:    [APUAPC] set_apusys_ao_apc - SUCCESS!

 9956 12:40:59.367291  INFO:    [APUAPC] set_apusys_noc_dapc - SUCCESS!

 9957 12:40:59.370914  INFO:    [APUAPC] D0_APC_0: 0x400510

 9958 12:40:59.374157  INFO:    [APUAPC] D0_APC_1: 0x0

 9959 12:40:59.377309  INFO:    [APUAPC] D0_APC_2: 0x1540

 9960 12:40:59.380799  INFO:    [APUAPC] D0_APC_3: 0x0

 9961 12:40:59.384240  INFO:    [APUAPC] D1_APC_0: 0xffffffff

 9962 12:40:59.387304  INFO:    [APUAPC] D1_APC_1: 0xffffffff

 9963 12:40:59.390649  INFO:    [APUAPC] D1_APC_2: 0x3fffff

 9964 12:40:59.393841  INFO:    [APUAPC] D1_APC_3: 0x0

 9965 12:40:59.397203  INFO:    [APUAPC] D2_APC_0: 0xffffffff

 9966 12:40:59.400482  INFO:    [APUAPC] D2_APC_1: 0xffffffff

 9967 12:40:59.404133  INFO:    [APUAPC] D2_APC_2: 0x3fffff

 9968 12:40:59.407113  INFO:    [APUAPC] D2_APC_3: 0x0

 9969 12:40:59.410626  INFO:    [APUAPC] D3_APC_0: 0xffffffff

 9970 12:40:59.414125  INFO:    [APUAPC] D3_APC_1: 0xffffffff

 9971 12:40:59.417114  INFO:    [APUAPC] D3_APC_2: 0x3fffff

 9972 12:40:59.417204  INFO:    [APUAPC] D3_APC_3: 0x0

 9973 12:40:59.420869  INFO:    [APUAPC] D4_APC_0: 0xffffffff

 9974 12:40:59.427209  INFO:    [APUAPC] D4_APC_1: 0xffffffff

 9975 12:40:59.427307  INFO:    [APUAPC] D4_APC_2: 0x3fffff

 9976 12:40:59.430436  INFO:    [APUAPC] D4_APC_3: 0x0

 9977 12:40:59.433759  INFO:    [APUAPC] D5_APC_0: 0xffffffff

 9978 12:40:59.437444  INFO:    [APUAPC] D5_APC_1: 0xffffffff

 9979 12:40:59.440584  INFO:    [APUAPC] D5_APC_2: 0x3fffff

 9980 12:40:59.443853  INFO:    [APUAPC] D5_APC_3: 0x0

 9981 12:40:59.447169  INFO:    [APUAPC] D6_APC_0: 0xffffffff

 9982 12:40:59.450281  INFO:    [APUAPC] D6_APC_1: 0xffffffff

 9983 12:40:59.453833  INFO:    [APUAPC] D6_APC_2: 0x3fffff

 9984 12:40:59.457123  INFO:    [APUAPC] D6_APC_3: 0x0

 9985 12:40:59.460401  INFO:    [APUAPC] D7_APC_0: 0xffffffff

 9986 12:40:59.463683  INFO:    [APUAPC] D7_APC_1: 0xffffffff

 9987 12:40:59.466809  INFO:    [APUAPC] D7_APC_2: 0x3fffff

 9988 12:40:59.470228  INFO:    [APUAPC] D7_APC_3: 0x0

 9989 12:40:59.473497  INFO:    [APUAPC] D8_APC_0: 0xffffffff

 9990 12:40:59.477006  INFO:    [APUAPC] D8_APC_1: 0xffffffff

 9991 12:40:59.480350  INFO:    [APUAPC] D8_APC_2: 0x3fffff

 9992 12:40:59.483666  INFO:    [APUAPC] D8_APC_3: 0x0

 9993 12:40:59.486892  INFO:    [APUAPC] D9_APC_0: 0xffffffff

 9994 12:40:59.490090  INFO:    [APUAPC] D9_APC_1: 0xffffffff

 9995 12:40:59.493776  INFO:    [APUAPC] D9_APC_2: 0x3fffff

 9996 12:40:59.497050  INFO:    [APUAPC] D9_APC_3: 0x0

 9997 12:40:59.500668  INFO:    [APUAPC] D10_APC_0: 0xffffffff

 9998 12:40:59.503358  INFO:    [APUAPC] D10_APC_1: 0xffffffff

 9999 12:40:59.506942  INFO:    [APUAPC] D10_APC_2: 0x3fffff

10000 12:40:59.509893  INFO:    [APUAPC] D10_APC_3: 0x0

10001 12:40:59.513340  INFO:    [APUAPC] D11_APC_0: 0xffffffff

10002 12:40:59.516931  INFO:    [APUAPC] D11_APC_1: 0xffffffff

10003 12:40:59.520264  INFO:    [APUAPC] D11_APC_2: 0x3fffff

10004 12:40:59.523763  INFO:    [APUAPC] D11_APC_3: 0x0

10005 12:40:59.526961  INFO:    [APUAPC] D12_APC_0: 0xffffffff

10006 12:40:59.530074  INFO:    [APUAPC] D12_APC_1: 0xffffffff

10007 12:40:59.533309  INFO:    [APUAPC] D12_APC_2: 0x3fffff

10008 12:40:59.537028  INFO:    [APUAPC] D12_APC_3: 0x0

10009 12:40:59.540048  INFO:    [APUAPC] D13_APC_0: 0xffffffff

10010 12:40:59.543496  INFO:    [APUAPC] D13_APC_1: 0xffffffff

10011 12:40:59.546525  INFO:    [APUAPC] D13_APC_2: 0x3fffff

10012 12:40:59.549912  INFO:    [APUAPC] D13_APC_3: 0x0

10013 12:40:59.553400  INFO:    [APUAPC] D14_APC_0: 0xffffffff

10014 12:40:59.556595  INFO:    [APUAPC] D14_APC_1: 0xffffffff

10015 12:40:59.559982  INFO:    [APUAPC] D14_APC_2: 0x3fffff

10016 12:40:59.563286  INFO:    [APUAPC] D14_APC_3: 0x0

10017 12:40:59.566454  INFO:    [APUAPC] D15_APC_0: 0xffffffff

10018 12:40:59.569936  INFO:    [APUAPC] D15_APC_1: 0xffffffff

10019 12:40:59.573362  INFO:    [APUAPC] D15_APC_2: 0x3fffff

10020 12:40:59.576584  INFO:    [APUAPC] D15_APC_3: 0x0

10021 12:40:59.579963  INFO:    [APUAPC] APC_CON: 0x4

10022 12:40:59.583539  INFO:    [NOCDAPC] D0_APC_0: 0x0

10023 12:40:59.586513  INFO:    [NOCDAPC] D0_APC_1: 0x0

10024 12:40:59.589695  INFO:    [NOCDAPC] D1_APC_0: 0x0

10025 12:40:59.592947  INFO:    [NOCDAPC] D1_APC_1: 0xfff

10026 12:40:59.593044  INFO:    [NOCDAPC] D2_APC_0: 0x0

10027 12:40:59.596378  INFO:    [NOCDAPC] D2_APC_1: 0xfff

10028 12:40:59.599689  INFO:    [NOCDAPC] D3_APC_0: 0x0

10029 12:40:59.602982  INFO:    [NOCDAPC] D3_APC_1: 0xfff

10030 12:40:59.606618  INFO:    [NOCDAPC] D4_APC_0: 0x0

10031 12:40:59.609743  INFO:    [NOCDAPC] D4_APC_1: 0xfff

10032 12:40:59.612848  INFO:    [NOCDAPC] D5_APC_0: 0x0

10033 12:40:59.616392  INFO:    [NOCDAPC] D5_APC_1: 0xfff

10034 12:40:59.619854  INFO:    [NOCDAPC] D6_APC_0: 0x0

10035 12:40:59.622855  INFO:    [NOCDAPC] D6_APC_1: 0xfff

10036 12:40:59.626516  INFO:    [NOCDAPC] D7_APC_0: 0x0

10037 12:40:59.626613  INFO:    [NOCDAPC] D7_APC_1: 0xfff

10038 12:40:59.629361  INFO:    [NOCDAPC] D8_APC_0: 0x0

10039 12:40:59.632965  INFO:    [NOCDAPC] D8_APC_1: 0xfff

10040 12:40:59.636452  INFO:    [NOCDAPC] D9_APC_0: 0x0

10041 12:40:59.639428  INFO:    [NOCDAPC] D9_APC_1: 0xfff

10042 12:40:59.643009  INFO:    [NOCDAPC] D10_APC_0: 0x0

10043 12:40:59.646127  INFO:    [NOCDAPC] D10_APC_1: 0xfff

10044 12:40:59.649764  INFO:    [NOCDAPC] D11_APC_0: 0x0

10045 12:40:59.652769  INFO:    [NOCDAPC] D11_APC_1: 0xfff

10046 12:40:59.655907  INFO:    [NOCDAPC] D12_APC_0: 0x0

10047 12:40:59.659156  INFO:    [NOCDAPC] D12_APC_1: 0xfff

10048 12:40:59.662907  INFO:    [NOCDAPC] D13_APC_0: 0x0

10049 12:40:59.665768  INFO:    [NOCDAPC] D13_APC_1: 0xfff

10050 12:40:59.665857  INFO:    [NOCDAPC] D14_APC_0: 0x0

10051 12:40:59.669308  INFO:    [NOCDAPC] D14_APC_1: 0xfff

10052 12:40:59.672436  INFO:    [NOCDAPC] D15_APC_0: 0x0

10053 12:40:59.675695  INFO:    [NOCDAPC] D15_APC_1: 0xfff

10054 12:40:59.679319  INFO:    [NOCDAPC] APC_CON: 0x4

10055 12:40:59.682559  INFO:    [APUAPC] set_apusys_apc done

10056 12:40:59.685666  INFO:    [DEVAPC] devapc_init done

10057 12:40:59.689424  INFO:    GICv3 without legacy support detected.

10058 12:40:59.695888  INFO:    ARM GICv3 driver initialized in EL3

10059 12:40:59.699493  INFO:    Maximum SPI INTID supported: 639

10060 12:40:59.702672  INFO:    BL31: Initializing runtime services

10061 12:40:59.709027  WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!

10062 12:40:59.709122  INFO:    SPM: enable CPC mode

10063 12:40:59.715457  INFO:    mcdi ready for mcusys-off-idle and system suspend

10064 12:40:59.719078  INFO:    BL31: Preparing for EL3 exit to normal world

10065 12:40:59.725633  INFO:    Entry point address = 0x80000000

10066 12:40:59.725730  INFO:    SPSR = 0x8

10067 12:40:59.732047  

10068 12:40:59.732139  

10069 12:40:59.732256  

10070 12:40:59.735056  Starting depthcharge on Spherion...

10071 12:40:59.735146  

10072 12:40:59.735211  Wipe memory regions:

10073 12:40:59.735275  

10074 12:40:59.735893  end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10075 12:40:59.735991  start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10076 12:40:59.736318  Setting prompt string to ['asurada:']
10077 12:40:59.736399  bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10078 12:40:59.738396  	[0x00000040000000, 0x00000054600000)

10079 12:40:59.861011  

10080 12:40:59.861172  	[0x00000054660000, 0x00000080000000)

10081 12:41:00.121740  

10082 12:41:00.121913  	[0x000000821a7280, 0x000000ffe64000)

10083 12:41:00.866356  

10084 12:41:00.866516  	[0x00000100000000, 0x00000240000000)

10085 12:41:02.757115  

10086 12:41:02.759915  Initializing XHCI USB controller at 0x11200000.

10087 12:41:03.797857  

10088 12:41:03.800957  [firmware-asurada-13885.B-collabora] Dec  7 2021 09:38:38

10089 12:41:03.801043  

10090 12:41:03.801108  

10091 12:41:03.801166  

10092 12:41:03.801442  Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10094 12:41:03.901796  asurada: tftpboot 192.168.201.1 12703575/tftp-deploy-50eelh8k/kernel/image.itb 12703575/tftp-deploy-50eelh8k/kernel/cmdline 

10095 12:41:03.901976  Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10096 12:41:03.902091  bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10097 12:41:03.906369  tftpboot 192.168.201.1 12703575/tftp-deploy-50eelh8k/kernel/image.itbtp-deploy-50eelh8k/kernel/cmdline 

10098 12:41:03.906453  

10099 12:41:03.906516  Waiting for link

10100 12:41:04.066965  

10101 12:41:04.067131  R8152: Initializing

10102 12:41:04.067228  

10103 12:41:04.070143  Version 9 (ocp_data = 6010)

10104 12:41:04.070225  

10105 12:41:04.073241  R8152: Done initializing

10106 12:41:04.073330  

10107 12:41:04.073395  Adding net device

10108 12:41:05.946409  

10109 12:41:05.946950  done.

10110 12:41:05.947366  

10111 12:41:05.947685  MAC: 00:e0:4c:72:2d:d6

10112 12:41:05.947988  

10113 12:41:05.949482  Sending DHCP discover... done.

10114 12:41:05.949981  

10115 12:41:05.952603  Waiting for reply... done.

10116 12:41:05.953092  

10117 12:41:05.956382  Sending DHCP request... done.

10118 12:41:05.956923  

10119 12:41:05.957266  Waiting for reply... done.

10120 12:41:05.957588  

10121 12:41:05.958920  My ip is 192.168.201.21

10122 12:41:05.959348  

10123 12:41:05.962700  The DHCP server ip is 192.168.201.1

10124 12:41:05.963134  

10125 12:41:05.965586  TFTP server IP predefined by user: 192.168.201.1

10126 12:41:05.966051  

10127 12:41:05.972788  Bootfile predefined by user: 12703575/tftp-deploy-50eelh8k/kernel/image.itb

10128 12:41:05.973314  

10129 12:41:05.976412  Sending tftp read request... done.

10130 12:41:05.976967  

10131 12:41:05.982719  Waiting for the transfer... 

10132 12:41:05.983150  

10133 12:41:06.278185  00000000 ################################################################

10134 12:41:06.278335  

10135 12:41:06.561481  00080000 ################################################################

10136 12:41:06.561612  

10137 12:41:06.833014  00100000 ################################################################

10138 12:41:06.833166  

10139 12:41:07.106044  00180000 ################################################################

10140 12:41:07.106196  

10141 12:41:07.389828  00200000 ################################################################

10142 12:41:07.389961  

10143 12:41:07.672676  00280000 ################################################################

10144 12:41:07.672797  

10145 12:41:07.955589  00300000 ################################################################

10146 12:41:07.955719  

10147 12:41:08.237602  00380000 ################################################################

10148 12:41:08.237748  

10149 12:41:08.501133  00400000 ################################################################

10150 12:41:08.501299  

10151 12:41:08.750282  00480000 ################################################################

10152 12:41:08.750416  

10153 12:41:08.999054  00500000 ################################################################

10154 12:41:08.999184  

10155 12:41:09.256926  00580000 ################################################################

10156 12:41:09.257060  

10157 12:41:09.511514  00600000 ################################################################

10158 12:41:09.511653  

10159 12:41:09.761474  00680000 ################################################################

10160 12:41:09.761603  

10161 12:41:10.010744  00700000 ################################################################

10162 12:41:10.010884  

10163 12:41:10.266079  00780000 ################################################################

10164 12:41:10.266239  

10165 12:41:10.521739  00800000 ################################################################

10166 12:41:10.521878  

10167 12:41:10.835275  00880000 ################################################################

10168 12:41:10.835777  

10169 12:41:11.131710  00900000 ################################################################

10170 12:41:11.131840  

10171 12:41:11.406950  00980000 ################################################################

10172 12:41:11.407087  

10173 12:41:11.684458  00a00000 ################################################################

10174 12:41:11.684590  

10175 12:41:11.955262  00a80000 ################################################################

10176 12:41:11.955391  

10177 12:41:12.201802  00b00000 ################################################################

10178 12:41:12.201946  

10179 12:41:12.437391  00b80000 ################################################################

10180 12:41:12.437529  

10181 12:41:12.675765  00c00000 ################################################################

10182 12:41:12.675896  

10183 12:41:12.925239  00c80000 ################################################################

10184 12:41:12.925365  

10185 12:41:13.173193  00d00000 ################################################################

10186 12:41:13.173322  

10187 12:41:13.454680  00d80000 ################################################################

10188 12:41:13.454845  

10189 12:41:13.711879  00e00000 ################################################################

10190 12:41:13.711999  

10191 12:41:13.961030  00e80000 ################################################################

10192 12:41:13.961153  

10193 12:41:14.210143  00f00000 ################################################################

10194 12:41:14.210275  

10195 12:41:14.479522  00f80000 ################################################################

10196 12:41:14.479652  

10197 12:41:14.731624  01000000 ################################################################

10198 12:41:14.731749  

10199 12:41:14.985730  01080000 ################################################################

10200 12:41:14.985884  

10201 12:41:15.235085  01100000 ################################################################

10202 12:41:15.235235  

10203 12:41:15.489744  01180000 ################################################################

10204 12:41:15.489876  

10205 12:41:15.739525  01200000 ################################################################

10206 12:41:15.739675  

10207 12:41:15.988656  01280000 ################################################################

10208 12:41:15.988817  

10209 12:41:16.237873  01300000 ################################################################

10210 12:41:16.238065  

10211 12:41:16.487288  01380000 ################################################################

10212 12:41:16.487452  

10213 12:41:16.738943  01400000 ################################################################

10214 12:41:16.739067  

10215 12:41:16.986198  01480000 ################################################################

10216 12:41:16.986324  

10217 12:41:17.233769  01500000 ################################################################

10218 12:41:17.233928  

10219 12:41:17.483410  01580000 ################################################################

10220 12:41:17.483567  

10221 12:41:17.729550  01600000 ################################################################

10222 12:41:17.729729  

10223 12:41:17.969495  01680000 ################################################################

10224 12:41:17.969657  

10225 12:41:18.219506  01700000 ################################################################

10226 12:41:18.219665  

10227 12:41:18.469283  01780000 ################################################################

10228 12:41:18.469423  

10229 12:41:18.718958  01800000 ################################################################

10230 12:41:18.719127  

10231 12:41:18.967778  01880000 ################################################################

10232 12:41:18.967954  

10233 12:41:19.214787  01900000 ################################################################

10234 12:41:19.214914  

10235 12:41:19.463661  01980000 ################################################################

10236 12:41:19.463801  

10237 12:41:19.712772  01a00000 ################################################################

10238 12:41:19.712929  

10239 12:41:19.960593  01a80000 ################################################################

10240 12:41:19.960734  

10241 12:41:20.210575  01b00000 ################################################################

10242 12:41:20.210707  

10243 12:41:20.459999  01b80000 ################################################################

10244 12:41:20.460138  

10245 12:41:20.717594  01c00000 ################################################################

10246 12:41:20.717744  

10247 12:41:20.729925  01c80000 #### done.

10248 12:41:20.730053  

10249 12:41:20.733390  The bootfile was 29911074 bytes long.

10250 12:41:20.733475  

10251 12:41:20.737066  Sending tftp read request... done.

10252 12:41:20.737151  

10253 12:41:20.740242  Waiting for the transfer... 

10254 12:41:20.740326  

10255 12:41:20.740392  00000000 # done.

10256 12:41:20.740455  

10257 12:41:20.750084  Command line loaded dynamically from TFTP file: 12703575/tftp-deploy-50eelh8k/kernel/cmdline

10258 12:41:20.750168  

10259 12:41:20.770077  The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12703575/extract-nfsrootfs-nzirnmiu,tcp,hard ip=dhcp tftpserverip=192.168.201.1

10260 12:41:20.770168  

10261 12:41:20.773317  Loading FIT.

10262 12:41:20.773406  

10263 12:41:20.773471  Image ramdisk-1 has 17808901 bytes.

10264 12:41:20.776585  

10265 12:41:20.776661  Image fdt-1 has 47278 bytes.

10266 12:41:20.776724  

10267 12:41:20.779881  Image kernel-1 has 12052857 bytes.

10268 12:41:20.779954  

10269 12:41:20.790041  Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion

10270 12:41:20.790118  

10271 12:41:20.806601  Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192

10272 12:41:20.806692  

10273 12:41:20.813330  Choosing best match conf-1 for compat google,spherion-rev2.

10274 12:41:20.816672  

10275 12:41:20.821418  Connected to device vid:did:rid of 1ae0:0028:00

10276 12:41:20.829613  

10277 12:41:20.832662  tpm_get_response: command 0x17b, return code 0x0

10278 12:41:20.832739  

10279 12:41:20.836109  ec_init: CrosEC protocol v3 supported (256, 248)

10280 12:41:20.840245  

10281 12:41:20.843547  tpm_cleanup: add release locality here.

10282 12:41:20.843622  

10283 12:41:20.843686  Shutting down all USB controllers.

10284 12:41:20.847053  

10285 12:41:20.847125  Removing current net device

10286 12:41:20.847193  

10287 12:41:20.853509  Exiting depthcharge with code 4 at timestamp: 50406843

10288 12:41:20.853593  

10289 12:41:20.856871  LZMA decompressing kernel-1 to 0x821a6718

10290 12:41:20.856950  

10291 12:41:20.860335  LZMA decompressing kernel-1 to 0x40000000

10292 12:41:22.359795  

10293 12:41:22.359951  jumping to kernel

10294 12:41:22.360414  end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
10295 12:41:22.360523  start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
10296 12:41:22.360611  Setting prompt string to ['Linux version [0-9]']
10297 12:41:22.360684  Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10298 12:41:22.360752  auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10299 12:41:22.441439  

10300 12:41:22.445166  [    0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]

10301 12:41:22.448806  start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10302 12:41:22.448910  The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10303 12:41:22.448986  Setting prompt string to []
10304 12:41:22.449067  Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10305 12:41:22.449148  Using line separator: #'\n'#
10306 12:41:22.449209  No login prompt set.
10307 12:41:22.449270  Parsing kernel messages
10308 12:41:22.449332  ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10309 12:41:22.449439  [login-action] Waiting for messages, (timeout 00:04:03)
10310 12:41:22.449506  Waiting using forced prompt support (timeout 00:02:01)
10311 12:41:22.468025  [    0.000000] Linux version 6.1.75-cip14 (KernelCI@build-j98433-arm64-gcc-10-defconfig-arm64-chromebook-89n64) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Feb  5 12:20:06 UTC 2024

10312 12:41:22.471694  [    0.000000] random: crng init done

10313 12:41:22.478203  [    0.000000] Machine model: Google Spherion (rev0 - 3)

10314 12:41:22.478288  [    0.000000] efi: UEFI not found.

10315 12:41:22.488050  [    0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB

10316 12:41:22.494823  [    0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool

10317 12:41:22.504992  [    0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB

10318 12:41:22.515193  [    0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool

10319 12:41:22.521788  [    0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')

10320 12:41:22.525165  [    0.000000] printk: bootconsole [mtk8250] enabled

10321 12:41:22.533617  [    0.000000] NUMA: No NUMA configuration found

10322 12:41:22.539928  [    0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]

10323 12:41:22.546681  [    0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]

10324 12:41:22.546765  [    0.000000] Zone ranges:

10325 12:41:22.553664  [    0.000000]   DMA      [mem 0x0000000040000000-0x00000000ffffffff]

10326 12:41:22.556791  [    0.000000]   DMA32    empty

10327 12:41:22.563475  [    0.000000]   Normal   [mem 0x0000000100000000-0x000000023fffffff]

10328 12:41:22.566926  [    0.000000] Movable zone start for each node

10329 12:41:22.570131  [    0.000000] Early memory node ranges

10330 12:41:22.576655  [    0.000000]   node   0: [mem 0x0000000040000000-0x000000004fffffff]

10331 12:41:22.583057  [    0.000000]   node   0: [mem 0x0000000050000000-0x00000000528fffff]

10332 12:41:22.589914  [    0.000000]   node   0: [mem 0x0000000052900000-0x00000000545fffff]

10333 12:41:22.596613  [    0.000000]   node   0: [mem 0x0000000054700000-0x00000000ffdfffff]

10334 12:41:22.603217  [    0.000000]   node   0: [mem 0x0000000100000000-0x000000023fffffff]

10335 12:41:22.609907  [    0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]

10336 12:41:22.666063  [    0.000000] On node 0, zone DMA: 256 pages in unavailable ranges

10337 12:41:22.672690  [    0.000000] On node 0, zone Normal: 512 pages in unavailable ranges

10338 12:41:22.679594  [    0.000000] cma: Reserved 32 MiB at 0x00000000fde00000

10339 12:41:22.682687  [    0.000000] psci: probing for conduit method from DT.

10340 12:41:22.689146  [    0.000000] psci: PSCIv1.1 detected in firmware.

10341 12:41:22.692973  [    0.000000] psci: Using standard PSCI v0.2 function IDs

10342 12:41:22.699282  [    0.000000] psci: MIGRATE_INFO_TYPE not supported.

10343 12:41:22.702734  [    0.000000] psci: SMC Calling Convention v1.2

10344 12:41:22.709430  [    0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016

10345 12:41:22.712864  [    0.000000] Detected VIPT I-cache on CPU0

10346 12:41:22.719330  [    0.000000] CPU features: detected: GIC system register CPU interface

10347 12:41:22.725963  [    0.000000] CPU features: detected: Virtualization Host Extensions

10348 12:41:22.732764  [    0.000000] CPU features: kernel page table isolation forced ON by KASLR

10349 12:41:22.738992  [    0.000000] CPU features: detected: Kernel page table isolation (KPTI)

10350 12:41:22.745776  [    0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009

10351 12:41:22.752673  [    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923

10352 12:41:22.759230  [    0.000000] alternatives: applying boot alternatives

10353 12:41:22.762644  [    0.000000] Fallback order for Node 0: 0 

10354 12:41:22.769347  [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 2063616

10355 12:41:22.772857  [    0.000000] Policy zone: Normal

10356 12:41:22.796021  [    0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12703575/extract-nfsrootfs-nzirnmiu,tcp,hard ip=dhcp tftpserverip=192.168.201.1

10357 12:41:22.806064  <5>[    0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.

10358 12:41:22.818667  <6>[    0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)

10359 12:41:22.828686  <6>[    0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)

10360 12:41:22.835521  <6>[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off

10361 12:41:22.838973  <6>[    0.000000] software IO TLB: area num 8.

10362 12:41:22.895175  <6>[    0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)

10363 12:41:23.044522  <6>[    0.000000] Memory: 7949864K/8385536K available (17984K kernel code, 4118K rwdata, 19612K rodata, 8448K init, 616K bss, 402904K reserved, 32768K cma-reserved)

10364 12:41:23.050779  <6>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1

10365 12:41:23.057456  <6>[    0.000000] rcu: Preemptible hierarchical RCU implementation.

10366 12:41:23.061129  <6>[    0.000000] rcu: 	RCU event tracing is enabled.

10367 12:41:23.067463  <6>[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.

10368 12:41:23.073990  <6>[    0.000000] 	Trampoline variant of Tasks RCU enabled.

10369 12:41:23.077695  <6>[    0.000000] 	Tracing variant of Tasks RCU enabled.

10370 12:41:23.087570  <6>[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.

10371 12:41:23.094335  <6>[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8

10372 12:41:23.100452  <6>[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0

10373 12:41:23.107448  <6>[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode

10374 12:41:23.110797  <6>[    0.000000] GICv3: 608 SPIs implemented

10375 12:41:23.114083  <6>[    0.000000] GICv3: 0 Extended SPIs implemented

10376 12:41:23.120442  <6>[    0.000000] Root IRQ handler: gic_handle_irq

10377 12:41:23.123738  <6>[    0.000000] GICv3: GICv3 features: 16 PPIs

10378 12:41:23.130189  <6>[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000

10379 12:41:23.143730  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }

10380 12:41:23.153652  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }

10381 12:41:23.163673  <6>[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.

10382 12:41:23.171339  <6>[    0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).

10383 12:41:23.184377  <6>[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns

10384 12:41:23.190993  <6>[    0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns

10385 12:41:23.197665  <6>[    0.009190] Console: colour dummy device 80x25

10386 12:41:23.207749  <6>[    0.013915] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)

10387 12:41:23.211059  <6>[    0.024358] pid_max: default: 32768 minimum: 301

10388 12:41:23.217586  <6>[    0.029258] LSM: Security Framework initializing

10389 12:41:23.224212  <6>[    0.034227] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10390 12:41:23.234302  <6>[    0.042042] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10391 12:41:23.240678  <6>[    0.051513] cblist_init_generic: Setting adjustable number of callback queues.

10392 12:41:23.247514  <6>[    0.058957] cblist_init_generic: Setting shift to 3 and lim to 1.

10393 12:41:23.257243  <6>[    0.065334] cblist_init_generic: Setting adjustable number of callback queues.

10394 12:41:23.264090  <6>[    0.072761] cblist_init_generic: Setting shift to 3 and lim to 1.

10395 12:41:23.266997  <6>[    0.079164] rcu: Hierarchical SRCU implementation.

10396 12:41:23.273558  <6>[    0.084211] rcu: 	Max phase no-delay instances is 1000.

10397 12:41:23.280326  <6>[    0.091239] EFI services will not be available.

10398 12:41:23.283462  <6>[    0.096195] smp: Bringing up secondary CPUs ...

10399 12:41:23.291735  <6>[    0.101246] Detected VIPT I-cache on CPU1

10400 12:41:23.298487  <6>[    0.101316] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000

10401 12:41:23.304990  <6>[    0.101347] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]

10402 12:41:23.308202  <6>[    0.101693] Detected VIPT I-cache on CPU2

10403 12:41:23.318194  <6>[    0.101745] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000

10404 12:41:23.324851  <6>[    0.101764] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]

10405 12:41:23.328184  <6>[    0.102029] Detected VIPT I-cache on CPU3

10406 12:41:23.334692  <6>[    0.102077] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000

10407 12:41:23.341281  <6>[    0.102094] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]

10408 12:41:23.348068  <6>[    0.102402] CPU features: detected: Spectre-v4

10409 12:41:23.351311  <6>[    0.102408] CPU features: detected: Spectre-BHB

10410 12:41:23.354619  <6>[    0.102414] Detected PIPT I-cache on CPU4

10411 12:41:23.361082  <6>[    0.102471] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000

10412 12:41:23.367757  <6>[    0.102488] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]

10413 12:41:23.374316  <6>[    0.102773] Detected PIPT I-cache on CPU5

10414 12:41:23.381045  <6>[    0.102828] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000

10415 12:41:23.387783  <6>[    0.102844] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]

10416 12:41:23.391179  <6>[    0.103114] Detected PIPT I-cache on CPU6

10417 12:41:23.397847  <6>[    0.103176] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000

10418 12:41:23.404267  <6>[    0.103193] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]

10419 12:41:23.411069  <6>[    0.103491] Detected PIPT I-cache on CPU7

10420 12:41:23.417659  <6>[    0.103555] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000

10421 12:41:23.424363  <6>[    0.103571] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]

10422 12:41:23.427548  <6>[    0.103618] smp: Brought up 1 node, 8 CPUs

10423 12:41:23.434348  <6>[    0.244982] SMP: Total of 8 processors activated.

10424 12:41:23.437677  <6>[    0.249933] CPU features: detected: 32-bit EL0 Support

10425 12:41:23.447593  <6>[    0.255295] CPU features: detected: Data cache clean to the PoU not required for I/D coherence

10426 12:41:23.454070  <6>[    0.264095] CPU features: detected: Common not Private translations

10427 12:41:23.460436  <6>[    0.270611] CPU features: detected: CRC32 instructions

10428 12:41:23.463850  <6>[    0.275962] CPU features: detected: RCpc load-acquire (LDAPR)

10429 12:41:23.470592  <6>[    0.281922] CPU features: detected: LSE atomic instructions

10430 12:41:23.477322  <6>[    0.287703] CPU features: detected: Privileged Access Never

10431 12:41:23.483905  <6>[    0.293519] CPU features: detected: RAS Extension Support

10432 12:41:23.490637  <6>[    0.299128] CPU features: detected: Speculative Store Bypassing Safe (SSBS)

10433 12:41:23.493961  <6>[    0.306391] CPU: All CPU(s) started at EL2

10434 12:41:23.500582  <6>[    0.310735] alternatives: applying system-wide alternatives

10435 12:41:23.509694  <6>[    0.321467] devtmpfs: initialized

10436 12:41:23.521887  <6>[    0.330322] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns

10437 12:41:23.531954  <6>[    0.340283] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)

10438 12:41:23.538345  <6>[    0.348311] pinctrl core: initialized pinctrl subsystem

10439 12:41:23.541628  <6>[    0.354936] DMI not present or invalid.

10440 12:41:23.548313  <6>[    0.359347] NET: Registered PF_NETLINK/PF_ROUTE protocol family

10441 12:41:23.558234  <6>[    0.366215] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations

10442 12:41:23.564689  <6>[    0.373798] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations

10443 12:41:23.574628  <6>[    0.382010] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations

10444 12:41:23.577944  <6>[    0.390255] audit: initializing netlink subsys (disabled)

10445 12:41:23.587875  <5>[    0.395950] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1

10446 12:41:23.594543  <6>[    0.396648] thermal_sys: Registered thermal governor 'step_wise'

10447 12:41:23.600982  <6>[    0.403918] thermal_sys: Registered thermal governor 'power_allocator'

10448 12:41:23.604637  <6>[    0.410173] cpuidle: using governor menu

10449 12:41:23.610955  <6>[    0.421126] NET: Registered PF_QIPCRTR protocol family

10450 12:41:23.617800  <6>[    0.426606] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.

10451 12:41:23.620998  <6>[    0.433707] ASID allocator initialised with 32768 entries

10452 12:41:23.628363  <6>[    0.440253] Serial: AMBA PL011 UART driver

10453 12:41:23.637089  <4>[    0.449012] Trying to register duplicate clock ID: 134

10454 12:41:23.691335  <6>[    0.506302] KASLR enabled

10455 12:41:23.705261  <6>[    0.513945] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages

10456 12:41:23.711888  <6>[    0.520959] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page

10457 12:41:23.718474  <6>[    0.527450] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages

10458 12:41:23.724968  <6>[    0.534453] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page

10459 12:41:23.731777  <6>[    0.540941] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages

10460 12:41:23.738354  <6>[    0.547943] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page

10461 12:41:23.744991  <6>[    0.554429] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages

10462 12:41:23.752010  <6>[    0.561435] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page

10463 12:41:23.755264  <6>[    0.568896] ACPI: Interpreter disabled.

10464 12:41:23.763541  <6>[    0.575332] iommu: Default domain type: Translated 

10465 12:41:23.770149  <6>[    0.580446] iommu: DMA domain TLB invalidation policy: strict mode 

10466 12:41:23.773249  <5>[    0.587112] SCSI subsystem initialized

10467 12:41:23.780015  <6>[    0.591366] usbcore: registered new interface driver usbfs

10468 12:41:23.786709  <6>[    0.597096] usbcore: registered new interface driver hub

10469 12:41:23.790124  <6>[    0.602650] usbcore: registered new device driver usb

10470 12:41:23.796896  <6>[    0.608772] pps_core: LinuxPPS API ver. 1 registered

10471 12:41:23.807010  <6>[    0.613968] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>

10472 12:41:23.810181  <6>[    0.623312] PTP clock support registered

10473 12:41:23.813656  <6>[    0.627556] EDAC MC: Ver: 3.0.0

10474 12:41:23.821107  <6>[    0.632745] FPGA manager framework

10475 12:41:23.827611  <6>[    0.636420] Advanced Linux Sound Architecture Driver Initialized.

10476 12:41:23.830763  <6>[    0.643187] vgaarb: loaded

10477 12:41:23.837115  <6>[    0.646348] clocksource: Switched to clocksource arch_sys_counter

10478 12:41:23.840475  <5>[    0.652792] VFS: Disk quotas dquot_6.6.0

10479 12:41:23.847192  <6>[    0.656980] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)

10480 12:41:23.850428  <6>[    0.664170] pnp: PnP ACPI: disabled

10481 12:41:23.859143  <6>[    0.670797] NET: Registered PF_INET protocol family

10482 12:41:23.868675  <6>[    0.676386] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)

10483 12:41:23.880154  <6>[    0.688713] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)

10484 12:41:23.890147  <6>[    0.697530] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)

10485 12:41:23.896715  <6>[    0.705500] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)

10486 12:41:23.903200  <6>[    0.714198] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)

10487 12:41:23.915682  <6>[    0.723918] TCP: Hash tables configured (established 65536 bind 65536)

10488 12:41:23.922414  <6>[    0.730789] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)

10489 12:41:23.928639  <6>[    0.737991] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)

10490 12:41:23.935221  <6>[    0.745698] NET: Registered PF_UNIX/PF_LOCAL protocol family

10491 12:41:23.941694  <6>[    0.751848] RPC: Registered named UNIX socket transport module.

10492 12:41:23.945243  <6>[    0.758001] RPC: Registered udp transport module.

10493 12:41:23.951633  <6>[    0.762933] RPC: Registered tcp transport module.

10494 12:41:23.958191  <6>[    0.767867] RPC: Registered tcp NFSv4.1 backchannel transport module.

10495 12:41:23.961684  <6>[    0.774530] PCI: CLS 0 bytes, default 64

10496 12:41:23.964944  <6>[    0.778869] Unpacking initramfs...

10497 12:41:23.989774  <6>[    0.798434] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available

10498 12:41:23.999548  <6>[    0.807051] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available

10499 12:41:24.003039  <6>[    0.815893] kvm [1]: IPA Size Limit: 40 bits

10500 12:41:24.009874  <6>[    0.820420] kvm [1]: GICv3: no GICV resource entry

10501 12:41:24.013105  <6>[    0.825442] kvm [1]: disabling GICv2 emulation

10502 12:41:24.019926  <6>[    0.830129] kvm [1]: GIC system register CPU interface enabled

10503 12:41:24.023172  <6>[    0.836289] kvm [1]: vgic interrupt IRQ18

10504 12:41:24.029617  <6>[    0.840644] kvm [1]: VHE mode initialized successfully

10505 12:41:24.036377  <5>[    0.847128] Initialise system trusted keyrings

10506 12:41:24.042704  <6>[    0.851963] workingset: timestamp_bits=42 max_order=21 bucket_order=0

10507 12:41:24.050086  <6>[    0.861912] squashfs: version 4.0 (2009/01/31) Phillip Lougher

10508 12:41:24.056736  <5>[    0.868287] NFS: Registering the id_resolver key type

10509 12:41:24.059930  <5>[    0.873582] Key type id_resolver registered

10510 12:41:24.066454  <5>[    0.877996] Key type id_legacy registered

10511 12:41:24.072987  <6>[    0.882274] nfs4filelayout_init: NFSv4 File Layout Driver Registering...

10512 12:41:24.079621  <6>[    0.889196] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...

10513 12:41:24.086431  <6>[    0.896910] 9p: Installing v9fs 9p2000 file system support

10514 12:41:24.122974  <5>[    0.934964] Key type asymmetric registered

10515 12:41:24.126500  <5>[    0.939294] Asymmetric key parser 'x509' registered

10516 12:41:24.136312  <6>[    0.944450] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)

10517 12:41:24.139710  <6>[    0.952062] io scheduler mq-deadline registered

10518 12:41:24.142721  <6>[    0.956825] io scheduler kyber registered

10519 12:41:24.162030  <6>[    0.973991] EINJ: ACPI disabled.

10520 12:41:24.194659  <4>[    0.999964] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10521 12:41:24.204254  <4>[    1.010602] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10522 12:41:24.219824  <6>[    1.031435] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled

10523 12:41:24.227562  <6>[    1.039495] printk: console [ttyS0] disabled

10524 12:41:24.255353  <6>[    1.064125] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2

10525 12:41:24.262479  <6>[    1.073600] printk: console [ttyS0] enabled

10526 12:41:24.265809  <6>[    1.073600] printk: console [ttyS0] enabled

10527 12:41:24.272264  <6>[    1.082494] printk: bootconsole [mtk8250] disabled

10528 12:41:24.275259  <6>[    1.082494] printk: bootconsole [mtk8250] disabled

10529 12:41:24.282182  <6>[    1.093733] SuperH (H)SCI(F) driver initialized

10530 12:41:24.285490  <6>[    1.099009] msm_serial: driver initialized

10531 12:41:24.299628  <6>[    1.107966] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000

10532 12:41:24.309602  <6>[    1.116514] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000

10533 12:41:24.316072  <6>[    1.125055] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000

10534 12:41:24.326147  <6>[    1.133684] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000

10535 12:41:24.333123  <6>[    1.142392] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000

10536 12:41:24.343223  <6>[    1.151119] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000

10537 12:41:24.352659  <6>[    1.159668] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000

10538 12:41:24.359251  <6>[    1.168474] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000

10539 12:41:24.369286  <6>[    1.177018] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000

10540 12:41:24.380560  <6>[    1.192681] loop: module loaded

10541 12:41:24.387274  <6>[    1.198723] vgpu11_sshub: Bringing 400000uV into 575000-575000uV

10542 12:41:24.410071  <4>[    1.222036] mtk-pmic-keys: Failed to locate of_node [id: -1]

10543 12:41:24.417065  <6>[    1.228972] megasas: 07.719.03.00-rc1

10544 12:41:24.426415  <6>[    1.238523] spi-nor spi2.0: w25q64jwm (8192 Kbytes)

10545 12:41:24.433957  <6>[    1.245716] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2

10546 12:41:24.450861  <6>[    1.262446] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)

10547 12:41:24.507116  <6>[    1.312617] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b

10548 12:41:24.706866  <6>[    1.518706] Freeing initrd memory: 17388K

10549 12:41:24.717204  <6>[    1.529217] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz

10550 12:41:24.728091  <6>[    1.540119] tun: Universal TUN/TAP device driver, 1.6

10551 12:41:24.731635  <6>[    1.546177] thunder_xcv, ver 1.0

10552 12:41:24.735035  <6>[    1.549679] thunder_bgx, ver 1.0

10553 12:41:24.738073  <6>[    1.553175] nicpf, ver 1.0

10554 12:41:24.748589  <6>[    1.557195] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version

10555 12:41:24.752176  <6>[    1.564673] hns3: Copyright (c) 2017 Huawei Corporation.

10556 12:41:24.758657  <6>[    1.570261] hclge is initializing

10557 12:41:24.762006  <6>[    1.573841] e1000: Intel(R) PRO/1000 Network Driver

10558 12:41:24.768340  <6>[    1.578971] e1000: Copyright (c) 1999-2006 Intel Corporation.

10559 12:41:24.771708  <6>[    1.584982] e1000e: Intel(R) PRO/1000 Network Driver

10560 12:41:24.778323  <6>[    1.590198] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.

10561 12:41:24.784960  <6>[    1.596382] igb: Intel(R) Gigabit Ethernet Network Driver

10562 12:41:24.791819  <6>[    1.602031] igb: Copyright (c) 2007-2014 Intel Corporation.

10563 12:41:24.798319  <6>[    1.607868] igbvf: Intel(R) Gigabit Virtual Function Network Driver

10564 12:41:24.804998  <6>[    1.614386] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.

10565 12:41:24.808041  <6>[    1.620849] sky2: driver version 1.30

10566 12:41:24.814943  <6>[    1.625828] VFIO - User Level meta-driver version: 0.3

10567 12:41:24.822248  <6>[    1.634113] usbcore: registered new interface driver usb-storage

10568 12:41:24.828936  <6>[    1.640567] usbcore: registered new device driver onboard-usb-hub

10569 12:41:24.837674  <6>[    1.649701] mt6397-rtc mt6359-rtc: registered as rtc0

10570 12:41:24.847458  <6>[    1.655167] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-05T12:40:49 UTC (1707136849)

10571 12:41:24.851259  <6>[    1.664724] i2c_dev: i2c /dev entries driver

10572 12:41:24.867760  <6>[    1.676443] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)

10573 12:41:24.888488  <6>[    1.700428] cpu cpu0: EM: created perf domain

10574 12:41:24.891923  <6>[    1.705376] cpu cpu4: EM: created perf domain

10575 12:41:24.898778  <6>[    1.710955] sdhci: Secure Digital Host Controller Interface driver

10576 12:41:24.905493  <6>[    1.717387] sdhci: Copyright(c) Pierre Ossman

10577 12:41:24.912263  <6>[    1.722347] Synopsys Designware Multimedia Card Interface Driver

10578 12:41:24.919049  <6>[    1.728973] sdhci-pltfm: SDHCI platform and OF driver helper

10579 12:41:24.922123  <6>[    1.729002] mmc0: CQHCI version 5.10

10580 12:41:24.928972  <6>[    1.739332] ledtrig-cpu: registered to indicate activity on CPUs

10581 12:41:24.935585  <6>[    1.746439] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000

10582 12:41:24.942325  <6>[    1.753503] usbcore: registered new interface driver usbhid

10583 12:41:24.945674  <6>[    1.759325] usbhid: USB HID core driver

10584 12:41:24.952013  <6>[    1.763524] spi_master spi0: will run message pump with realtime priority

10585 12:41:24.996804  <6>[    1.802239] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0

10586 12:41:25.015944  <6>[    1.817995] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1

10587 12:41:25.019600  <6>[    1.831593] mmc0: Command Queue Engine enabled

10588 12:41:25.026017  <6>[    1.836411] mmc0: new HS400 Enhanced strobe MMC card at address 0001

10589 12:41:25.032677  <6>[    1.843708] mmcblk0: mmc0:0001 DA4128 116 GiB 

10590 12:41:25.036107  <6>[    1.848654] cros-ec-spi spi0.0: Chrome EC device registered

10591 12:41:25.042943  <6>[    1.852552]  mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12

10592 12:41:25.050626  <6>[    1.862244] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB 

10593 12:41:25.057186  <6>[    1.868500] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB 

10594 12:41:25.063591  <6>[    1.874543] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)

10595 12:41:25.082450  <6>[    1.891238] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)

10596 12:41:25.089944  <6>[    1.901848] NET: Registered PF_PACKET protocol family

10597 12:41:25.093247  <6>[    1.907277] 9pnet: Installing 9P2000 support

10598 12:41:25.100116  <5>[    1.911851] Key type dns_resolver registered

10599 12:41:25.103430  <6>[    1.916868] registered taskstats version 1

10600 12:41:25.109818  <5>[    1.921255] Loading compiled-in X.509 certificates

10601 12:41:25.140132  <4>[    1.945530] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10602 12:41:25.150636  <4>[    1.956258] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10603 12:41:25.157311  <3>[    1.966795] debugfs: File 'uA_load' in directory '/' already present!

10604 12:41:25.163435  <3>[    1.973493] debugfs: File 'min_uV' in directory '/' already present!

10605 12:41:25.170526  <3>[    1.980100] debugfs: File 'max_uV' in directory '/' already present!

10606 12:41:25.177254  <3>[    1.986707] debugfs: File 'constraint_flags' in directory '/' already present!

10607 12:41:25.187858  <3>[    1.996380] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)

10608 12:41:25.197953  <6>[    2.010228] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102

10609 12:41:25.205165  <6>[    2.016970] xhci-mtk 11200000.usb: xHCI Host Controller

10610 12:41:25.211674  <6>[    2.022488] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1

10611 12:41:25.221790  <6>[    2.030296] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010

10612 12:41:25.228412  <6>[    2.039718] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000

10613 12:41:25.234947  <6>[    2.045788] xhci-mtk 11200000.usb: xHCI Host Controller

10614 12:41:25.241564  <6>[    2.051270] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2

10615 12:41:25.248220  <6>[    2.058922] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed

10616 12:41:25.255247  <6>[    2.066640] hub 1-0:1.0: USB hub found

10617 12:41:25.258353  <6>[    2.070650] hub 1-0:1.0: 1 port detected

10618 12:41:25.264817  <6>[    2.074920] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.

10619 12:41:25.271764  <6>[    2.083505] hub 2-0:1.0: USB hub found

10620 12:41:25.274842  <6>[    2.087511] hub 2-0:1.0: 1 port detected

10621 12:41:25.283371  <6>[    2.095027] mtk-msdc 11f70000.mmc: Got CD GPIO

10622 12:41:25.294796  <6>[    2.103458] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()

10623 12:41:25.301532  <6>[    2.111480] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()

10624 12:41:25.311128  <4>[    2.119449] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW

10625 12:41:25.321388  <6>[    2.128980] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()

10626 12:41:25.327872  <6>[    2.137085] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()

10627 12:41:25.334708  <6>[    2.145232] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()

10628 12:41:25.344636  <6>[    2.153192] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()

10629 12:41:25.351265  <6>[    2.161012] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()

10630 12:41:25.361163  <6>[    2.168830] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39

10631 12:41:25.371258  <6>[    2.179129] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)

10632 12:41:25.377685  <6>[    2.187512] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)

10633 12:41:25.387747  <6>[    2.195851] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)

10634 12:41:25.394773  <6>[    2.204191] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)

10635 12:41:25.404427  <6>[    2.212530] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)

10636 12:41:25.411184  <6>[    2.220869] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)

10637 12:41:25.421137  <6>[    2.229207] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)

10638 12:41:25.427994  <6>[    2.237546] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)

10639 12:41:25.437638  <6>[    2.245886] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)

10640 12:41:25.444472  <6>[    2.254231] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)

10641 12:41:25.454545  <6>[    2.262571] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)

10642 12:41:25.460880  <6>[    2.270910] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)

10643 12:41:25.470557  <6>[    2.279249] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)

10644 12:41:25.477568  <6>[    2.287591] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)

10645 12:41:25.487459  <6>[    2.295930] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)

10646 12:41:25.494217  <6>[    2.304716] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0

10647 12:41:25.500810  <6>[    2.311938] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0

10648 12:41:25.507458  <6>[    2.318786] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0

10649 12:41:25.513811  <6>[    2.325607] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0

10650 12:41:25.524026  <6>[    2.332609] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0

10651 12:41:25.530409  <6>[    2.339500] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)

10652 12:41:25.540376  <6>[    2.348630] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)

10653 12:41:25.550103  <6>[    2.357749] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)

10654 12:41:25.560190  <6>[    2.367042] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)

10655 12:41:25.569844  <6>[    2.376511] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)

10656 12:41:25.576931  <6>[    2.385978] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)

10657 12:41:25.586779  <6>[    2.395097] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)

10658 12:41:25.596849  <6>[    2.404563] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)

10659 12:41:25.606310  <6>[    2.413683] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)

10660 12:41:25.616365  <6>[    2.422977] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing

10661 12:41:25.626223  <6>[    2.433137] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing

10662 12:41:25.636025  <6>[    2.444673] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0

10663 12:41:25.642664  <6>[    2.454462] Trying to probe devices needed for running init ...

10664 12:41:25.665866  <6>[    2.474900] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk

10665 12:41:25.694255  <6>[    2.506360] hub 2-1:1.0: USB hub found

10666 12:41:25.697601  <6>[    2.510818] hub 2-1:1.0: 3 ports detected

10667 12:41:25.706244  <6>[    2.518109] hub 2-1:1.0: USB hub found

10668 12:41:25.709156  <6>[    2.522538] hub 2-1:1.0: 3 ports detected

10669 12:41:25.817656  <6>[    2.626617] usb 1-1: new high-speed USB device number 2 using xhci-mtk

10670 12:41:25.972411  <6>[    2.784631] hub 1-1:1.0: USB hub found

10671 12:41:25.975840  <6>[    2.789113] hub 1-1:1.0: 4 ports detected

10672 12:41:25.984866  <6>[    2.797102] hub 1-1:1.0: USB hub found

10673 12:41:25.988152  <6>[    2.801445] hub 1-1:1.0: 4 ports detected

10674 12:41:26.049829  <6>[    2.858738] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk

10675 12:41:26.309962  <6>[    3.118667] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk

10676 12:41:26.442372  <6>[    3.254620] hub 1-1.4:1.0: USB hub found

10677 12:41:26.445608  <6>[    3.259295] hub 1-1.4:1.0: 2 ports detected

10678 12:41:26.456020  <6>[    3.267773] hub 1-1.4:1.0: USB hub found

10679 12:41:26.458787  <6>[    3.272376] hub 1-1.4:1.0: 2 ports detected

10680 12:41:26.757801  <6>[    3.566646] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk

10681 12:41:26.949909  <6>[    3.758656] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk

10682 12:41:37.919498  <6>[   14.735634] ALSA device list:

10683 12:41:37.925854  <6>[   14.738929]   No soundcards found.

10684 12:41:37.934086  <6>[   14.746945] Freeing unused kernel memory: 8448K

10685 12:41:37.937621  <6>[   14.751939] Run /init as init process

10686 12:41:37.948621  Loading, please wait...

10687 12:41:37.969517  Starting version 247.3-7+deb11u2

10688 12:41:38.210148  <6>[   15.019885] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000

10689 12:41:38.216748  <3>[   15.020699] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10690 12:41:38.226698  <3>[   15.035325] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10691 12:41:38.233168  <6>[   15.042868] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:

10692 12:41:38.240043  <3>[   15.043405] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10693 12:41:38.249600  <6>[   15.050998] mtk-pcie-gen3 11230000.pcie:      MEM 0x0012000000..0x00127fffff -> 0x0012000000

10694 12:41:38.256559  <6>[   15.060825] remoteproc remoteproc0: scp is available

10695 12:41:38.262951  <6>[   15.067828] mtk-pcie-gen3 11230000.pcie:       IO 0x0012800000..0x0012ffffff -> 0x0012800000

10696 12:41:38.269663  <6>[   15.073141] remoteproc remoteproc0: powering up scp

10697 12:41:38.276038  <3>[   15.081995] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10698 12:41:38.285905  <6>[   15.083150] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered

10699 12:41:38.289297  <6>[   15.083967] mc: Linux media interface: v0.10

10700 12:41:38.296063  <6>[   15.086858] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164

10701 12:41:38.302435  <6>[   15.086888] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0

10702 12:41:38.308915  <4>[   15.088094] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator

10703 12:41:38.319828  <3>[   15.094956] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10704 12:41:38.326474  <4>[   15.098332] elants_i2c 4-0010: supply vccio not found, using dummy regulator

10705 12:41:38.332917  <4>[   15.113760] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.

10706 12:41:38.340041  <4>[   15.113760] Fallback method does not support PEC.

10707 12:41:38.346836  <3>[   15.115555] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10708 12:41:38.353505  <6>[   15.130638] usbcore: registered new device driver r8152-cfgselector

10709 12:41:38.359904  <6>[   15.135891] videodev: Linux video capture interface: v2.00

10710 12:41:38.366460  <3>[   15.136599] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10711 12:41:38.376395  <3>[   15.136605] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10712 12:41:38.383164  <3>[   15.136662] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10713 12:41:38.393168  <3>[   15.137975] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10714 12:41:38.403129  <3>[   15.160702] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10715 12:41:38.409728  <3>[   15.165657] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10716 12:41:38.416215  <6>[   15.203678] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00

10717 12:41:38.423137  <3>[   15.210878] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10718 12:41:38.433253  <3>[   15.210883] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10719 12:41:38.439744  <3>[   15.210915] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10720 12:41:38.446498  <6>[   15.219697] pci_bus 0000:00: root bus resource [bus 00-ff]

10721 12:41:38.456158  <3>[   15.227874] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10722 12:41:38.462917  <6>[   15.234763] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk

10723 12:41:38.469622  <6>[   15.234777] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd

10724 12:41:38.479346  <6>[   15.234811] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e

10725 12:41:38.486012  <6>[   15.234822] remoteproc remoteproc0: remote processor scp is now up

10726 12:41:38.493042  <6>[   15.235024] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]

10727 12:41:38.502880  <6>[   15.235034] pci_bus 0000:00: root bus resource [io  0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])

10728 12:41:38.509064  <6>[   15.235083] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400

10729 12:41:38.515601  <6>[   15.235112] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]

10730 12:41:38.518997  <6>[   15.235222] pci 0000:00:00.0: supports D1 D2

10731 12:41:38.529172  <6>[   15.235228] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10732 12:41:38.535520  <6>[   15.237024] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring

10733 12:41:38.542078  <6>[   15.237149] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000

10734 12:41:38.549011  <6>[   15.237182] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]

10735 12:41:38.555530  <6>[   15.237205] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]

10736 12:41:38.565282  <6>[   15.237223] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]

10737 12:41:38.569141  <6>[   15.237349] pci 0000:01:00.0: supports D1 D2

10738 12:41:38.575261  <6>[   15.237353] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10739 12:41:38.585520  <6>[   15.238072] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2

10740 12:41:38.591949  <3>[   15.242779] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10741 12:41:38.601786  <3>[   15.242782] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10742 12:41:38.608368  <3>[   15.242784] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10743 12:41:38.618186  <3>[   15.242811] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10744 12:41:38.628189  <6>[   15.247069] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003

10745 12:41:38.634776  <6>[   15.250433] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01

10746 12:41:38.641475  <6>[   15.250490] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]

10747 12:41:38.651435  <6>[   15.250500] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]

10748 12:41:38.658177  <6>[   15.250514] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]

10749 12:41:38.668129  <6>[   15.250532] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]

10750 12:41:38.674389  <6>[   15.250550] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]

10751 12:41:38.681171  <6>[   15.250567] pci 0000:00:00.0: PCI bridge to [bus 01]

10752 12:41:38.687716  <6>[   15.250576] pci 0000:00:00.0:   bridge window [mem 0x12000000-0x121fffff 64bit pref]

10753 12:41:38.694141  <6>[   15.250728] pcieport 0000:00:00.0: enabling device (0000 -> 0002)

10754 12:41:38.700933  <6>[   15.252144] pcieport 0000:00:00.0: PME: Signaling with IRQ 282

10755 12:41:38.707725  <6>[   15.252862] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected

10756 12:41:38.717560  <6>[   15.254564] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered

10757 12:41:38.724158  <6>[   15.273620] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3

10758 12:41:38.734098  <4>[   15.277576] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2

10759 12:41:38.743841  <4>[   15.277587] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)

10760 12:41:38.747241  <6>[   15.281941] pcieport 0000:00:00.0: AER: enabled with IRQ 282

10761 12:41:38.753821  <6>[   15.326554] r8152 2-1.3:1.0 eth0: v1.12.13

10762 12:41:38.757370  <6>[   15.327861] Bluetooth: Core ver 2.22

10763 12:41:38.764151  <6>[   15.334376] usbcore: registered new interface driver r8152

10764 12:41:38.767204  <6>[   15.338847] NET: Registered PF_BLUETOOTH protocol family

10765 12:41:38.773741  <6>[   15.340777] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)

10766 12:41:38.784092  <5>[   15.341456] cfg80211: Loading compiled-in X.509 certificates for regulatory database

10767 12:41:38.796955  <6>[   15.342062] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4

10768 12:41:38.800226  <6>[   15.342272] usbcore: registered new interface driver uvcvideo

10769 12:41:38.807041  <5>[   15.368759] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'

10770 12:41:38.813417  <6>[   15.375127] Bluetooth: HCI device and connection manager initialized

10771 12:41:38.820162  <6>[   15.375144] Bluetooth: HCI socket layer initialized

10772 12:41:38.827040  <6>[   15.375559] usbcore: registered new interface driver cdc_ether

10773 12:41:38.833250  <6>[   15.375853] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0

10774 12:41:38.839530  <5>[   15.383283] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'

10775 12:41:38.846456  <6>[   15.387133] Bluetooth: L2CAP socket layer initialized

10776 12:41:38.849660  <6>[   15.387145] Bluetooth: SCO socket layer initialized

10777 12:41:38.856066  <6>[   15.387296] usbcore: registered new interface driver r8153_ecm

10778 12:41:38.866237  <4>[   15.394086] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2

10779 12:41:38.872698  <6>[   15.395583] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0

10780 12:41:38.879578  <6>[   15.446327] usbcore: registered new interface driver btusb

10781 12:41:38.889308  <4>[   15.447058] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2

10782 12:41:38.895678  <3>[   15.447066] Bluetooth: hci0: Failed to load firmware file (-2)

10783 12:41:38.899219  <3>[   15.447070] Bluetooth: hci0: Failed to set up firmware (-2)

10784 12:41:38.909231  <4>[   15.447073] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.

10785 12:41:38.915506  <6>[   15.452588] cfg80211: failed to load regulatory.db

10786 12:41:38.980032  <6>[   15.790282] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000

10787 12:41:38.986965  <6>[   15.797783] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)

10788 12:41:39.010683  <6>[   15.824450] mt7921e 0000:01:00.0: ASIC revision: 79610010

10789 12:41:39.112052  <6>[   15.922098] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a

10790 12:41:39.114818  <6>[   15.922098] 

10791 12:41:39.126891  Begin: Loading essential drivers ... done.

10792 12:41:39.129777  Begin: Running /scripts/init-premount ... done.

10793 12:41:39.136782  Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.

10794 12:41:39.146229  Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available

10795 12:41:39.149733  Device /sys/class/net/enx00e04c722dd6 found

10796 12:41:39.149821  done.

10797 12:41:39.188486  IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP

10798 12:41:39.380159  <6>[   16.190316] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959

10799 12:41:40.089711  <6>[   16.903098] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on

10800 12:41:40.223666  <6>[   17.036930] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0

10801 12:41:40.342050  IP-Config: no response after 2 secs - giving up

10802 12:41:40.380823  IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:7b mtu 1500 DHCP

10803 12:41:41.104128  IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP

10804 12:41:41.107388  IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):

10805 12:41:41.114040   address: 192.168.201.21   broadcast: 192.168.201.255  netmask: 255.255.255.0   

10806 12:41:41.120613   gateway: 192.168.201.1    dns0     : 192.168.201.1    dns1   : 0.0.0.0         

10807 12:41:41.127065   host   : mt8192-asurada-spherion-r0-cbg-1                                

10808 12:41:41.133898   domain : lava-rack                                                       

10809 12:41:41.137105   rootserver: 192.168.201.1 rootpath: 

10810 12:41:41.140596   filename  : 

10811 12:41:41.215755  done.

10812 12:41:41.222310  Begin: Running /scripts/nfs-bottom ... done.

10813 12:41:41.240905  Begin: Running /scripts/init-bottom ... done.

10814 12:41:42.403947  <6>[   19.218212] NET: Registered PF_INET6 protocol family

10815 12:41:42.411743  <6>[   19.225847] Segment Routing with IPv6

10816 12:41:42.415217  <6>[   19.229871] In-situ OAM (IOAM) with IPv6

10817 12:41:42.537198  <30>[   19.334614] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)

10818 12:41:42.544941  <30>[   19.359078] systemd[1]: Detected architecture arm64.

10819 12:41:42.565724  

10820 12:41:42.568985  Welcome to Debian GNU/Linux 11 (bullseye)!

10821 12:41:42.569158  

10822 12:41:42.587154  <30>[   19.401141] systemd[1]: Set hostname to <debian-bullseye-arm64>.

10823 12:41:43.418509  <30>[   20.228957] systemd[1]: Queued start job for default target Graphical Interface.

10824 12:41:43.455346  <30>[   20.268959] systemd[1]: Created slice system-getty.slice.

10825 12:41:43.462108  [  OK  ] Created slice system-getty.slice.

10826 12:41:43.478368  <30>[   20.292060] systemd[1]: Created slice system-modprobe.slice.

10827 12:41:43.485011  [  OK  ] Created slice system-modprobe.slice.

10828 12:41:43.502373  <30>[   20.315850] systemd[1]: Created slice system-serial\x2dgetty.slice.

10829 12:41:43.512055  [  OK  ] Created slice system-serial\x2dgetty.slice.

10830 12:41:43.526009  <30>[   20.339718] systemd[1]: Created slice User and Session Slice.

10831 12:41:43.532526  [  OK  ] Created slice User and Session Slice.

10832 12:41:43.553014  <30>[   20.363472] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.

10833 12:41:43.562964  [  OK  ] Started Dispatch Password …ts to Console Directory Watch.

10834 12:41:43.580819  <30>[   20.391301] systemd[1]: Started Forward Password Requests to Wall Directory Watch.

10835 12:41:43.587863  [  OK  ] Started Forward Password R…uests to Wall Directory Watch.

10836 12:41:43.612357  <30>[   20.419245] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.

10837 12:41:43.618996  <30>[   20.431507] systemd[1]: Reached target Local Encrypted Volumes.

10838 12:41:43.625569  [  OK  ] Reached target Local Encrypted Volumes.

10839 12:41:43.641133  <30>[   20.455107] systemd[1]: Reached target Paths.

10840 12:41:43.644433  [  OK  ] Reached target Paths.

10841 12:41:43.660614  <30>[   20.474648] systemd[1]: Reached target Remote File Systems.

10842 12:41:43.666908  [  OK  ] Reached target Remote File Systems.

10843 12:41:43.684709  <30>[   20.498603] systemd[1]: Reached target Slices.

10844 12:41:43.688280  [  OK  ] Reached target Slices.

10845 12:41:43.704768  <30>[   20.518665] systemd[1]: Reached target Swap.

10846 12:41:43.708361  [  OK  ] Reached target Swap.

10847 12:41:43.728467  <30>[   20.539123] systemd[1]: Listening on initctl Compatibility Named Pipe.

10848 12:41:43.734914  [  OK  ] Listening on initctl Compatibility Named Pipe.

10849 12:41:43.741512  <30>[   20.555092] systemd[1]: Listening on Journal Audit Socket.

10850 12:41:43.748181  [  OK  ] Listening on Journal Audit Socket.

10851 12:41:43.765492  <30>[   20.579790] systemd[1]: Listening on Journal Socket (/dev/log).

10852 12:41:43.772156  [  OK  ] Listening on Journal Socket (/dev/log).

10853 12:41:43.789364  <30>[   20.603170] systemd[1]: Listening on Journal Socket.

10854 12:41:43.795472  [  OK  ] Listening on Journal Socket.

10855 12:41:43.813132  <30>[   20.624013] systemd[1]: Listening on Network Service Netlink Socket.

10856 12:41:43.819674  [  OK  ] Listening on Network Service Netlink Socket.

10857 12:41:43.834816  <30>[   20.648999] systemd[1]: Listening on udev Control Socket.

10858 12:41:43.841600  [  OK  ] Listening on udev Control Socket.

10859 12:41:43.856827  <30>[   20.671070] systemd[1]: Listening on udev Kernel Socket.

10860 12:41:43.863424  [  OK  ] Listening on udev Kernel Socket.

10861 12:41:43.904279  <30>[   20.718696] systemd[1]: Mounting Huge Pages File System...

10862 12:41:43.911067           Mounting Huge Pages File System...

10863 12:41:43.928632  <30>[   20.742841] systemd[1]: Mounting POSIX Message Queue File System...

10864 12:41:43.935460           Mounting POSIX Message Queue File System...

10865 12:41:43.956554  <30>[   20.770927] systemd[1]: Mounting Kernel Debug File System...

10866 12:41:43.963112           Mounting Kernel Debug File System...

10867 12:41:43.980038  <30>[   20.791097] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.

10868 12:41:43.994940  <30>[   20.805808] systemd[1]: Starting Create list of static device nodes for the current kernel...

10869 12:41:44.001392           Starting Create list of st…odes for the current kernel...

10870 12:41:44.020872  <30>[   20.835180] systemd[1]: Starting Load Kernel Module configfs...

10871 12:41:44.027655           Starting Load Kernel Module configfs...

10872 12:41:44.044958  <30>[   20.858958] systemd[1]: Starting Load Kernel Module drm...

10873 12:41:44.051291           Starting Load Kernel Module drm...

10874 12:41:44.067455  <30>[   20.881786] systemd[1]: Starting Load Kernel Module fuse...

10875 12:41:44.074213           Starting Load Kernel Module fuse...

10876 12:41:44.109021  <30>[   20.919885] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.

10877 12:41:44.116184  <6>[   20.920374] fuse: init (API version 7.37)

10878 12:41:44.122991  <30>[   20.936594] systemd[1]: Starting Journal Service...

10879 12:41:44.126284           Starting Journal Service...

10880 12:41:44.151800  <30>[   20.965186] systemd[1]: Starting Load Kernel Modules...

10881 12:41:44.157707           Starting Load Kernel Modules...

10882 12:41:44.180739  <30>[   20.990886] systemd[1]: Starting Remount Root and Kernel File Systems...

10883 12:41:44.186896           Starting Remount Root and Kernel File Systems...

10884 12:41:44.204856  <30>[   21.018882] systemd[1]: Starting Coldplug All udev Devices...

10885 12:41:44.211794           Starting Coldplug All udev Devices...

10886 12:41:44.229664  <30>[   21.043230] systemd[1]: Mounted Huge Pages File System.

10887 12:41:44.235835  [  OK  ] Mounted Huge Pages File System.

10888 12:41:44.251842  <3>[   21.062515] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10889 12:41:44.258542  <30>[   21.072220] systemd[1]: Mounted POSIX Message Queue File System.

10890 12:41:44.265132  [  OK  ] Mounted POSIX Message Queue File System.

10891 12:41:44.280406  <30>[   21.094779] systemd[1]: Mounted Kernel Debug File System.

10892 12:41:44.290473  <3>[   21.095456] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10893 12:41:44.297190  [  OK  ] Mounted Kernel Debug File System.

10894 12:41:44.316962  <30>[   21.127875] systemd[1]: Finished Create list of static device nodes for the current kernel.

10895 12:41:44.327036  [  OK  ] Finished Create list of st… nodes for the current kernel.

10896 12:41:44.337269  <3>[   21.148181] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10897 12:41:44.344470  <30>[   21.158449] systemd[1]: modprobe@configfs.service: Succeeded.

10898 12:41:44.351302  <30>[   21.165243] systemd[1]: Finished Load Kernel Module configfs.

10899 12:41:44.358421  [  OK  ] Finished Load Kernel Module configfs.

10900 12:41:44.368141  <3>[   21.178148] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10901 12:41:44.374798  <30>[   21.188168] systemd[1]: modprobe@drm.service: Succeeded.

10902 12:41:44.381479  <30>[   21.194947] systemd[1]: Finished Load Kernel Module drm.

10903 12:41:44.388362  [  OK  ] Finished Load Kernel Module drm.

10904 12:41:44.399239  <3>[   21.209873] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10905 12:41:44.405709  <30>[   21.219729] systemd[1]: modprobe@fuse.service: Succeeded.

10906 12:41:44.412330  <30>[   21.226700] systemd[1]: Finished Load Kernel Module fuse.

10907 12:41:44.419340  [  OK  ] Finished Load Kernel Module fuse.

10908 12:41:44.429577  <3>[   21.240004] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10909 12:41:44.438130  <30>[   21.252558] systemd[1]: Finished Load Kernel Modules.

10910 12:41:44.444869  [  OK  ] Finished Load Kernel Modules.

10911 12:41:44.461267  <3>[   21.272399] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10912 12:41:44.472419  <30>[   21.283324] systemd[1]: Finished Remount Root and Kernel File Systems.

10913 12:41:44.479117  [  OK  ] Finished Remount Root and Kernel File Systems.

10914 12:41:44.492791  <3>[   21.303690] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10915 12:41:44.522818  <3>[   21.333637] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10916 12:41:44.536474  <30>[   21.350749] systemd[1]: Mounting FUSE Control File System...

10917 12:41:44.543560           Mounting FUSE Control File System...

10918 12:41:44.553831  <3>[   21.363624] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10919 12:41:44.563424  <30>[   21.377500] systemd[1]: Mounting Kernel Configuration File System...

10920 12:41:44.570559           Mounting Kernel Configuration File System...

10921 12:41:44.591416  <30>[   21.401751] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.

10922 12:41:44.601496  <30>[   21.410908] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.

10923 12:41:44.641194  <30>[   21.455335] systemd[1]: Starting Load/Save Random Seed...

10924 12:41:44.648293           Starting Load/Save Random Seed...

10925 12:41:44.663451  <30>[   21.477322] systemd[1]: Starting Apply Kernel Variables...

10926 12:41:44.669565           Starting Apply Kernel Variables...

10927 12:41:44.690402  <30>[   21.503408] systemd[1]: Starting Create System Users...

10928 12:41:44.706842  <4>[   21.509013] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent

10929 12:41:44.712942  <3>[   21.524729] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5

10930 12:41:44.719715           Starting Create System Users...

10931 12:41:44.734291  <30>[   21.548363] systemd[1]: Started Journal Service.

10932 12:41:44.740975  [  OK  ] Started Journal Service.

10933 12:41:44.761712  [FAILED] Failed to start Coldplug All udev Devices.

10934 12:41:44.773049  See 'systemctl status systemd-udev-trigger.service' for details.

10935 12:41:44.789926  [  OK  ] Mounted FUSE Control File System.

10936 12:41:44.809432  [  OK  ] Mounted Kernel Configuration File System.

10937 12:41:44.830736  [  OK  ] Finished Load/Save Random Seed.

10938 12:41:44.850975  [  OK  ] Finished Apply Kernel Variables.

10939 12:41:44.866579  [  OK  ] Finished Create System Users.

10940 12:41:44.909531           Starting Flush Journal to Persistent Storage...

10941 12:41:44.927644           Starting Create Static Device Nodes in /dev...

10942 12:41:44.958071  <46>[   21.769027] systemd-journald[295]: Received client request to flush runtime journal.

10943 12:41:45.711899  [  OK  ] Finished Create Static Device Nodes in /dev.

10944 12:41:45.725080  [  OK  ] Reached target Local File Systems (Pre).

10945 12:41:45.740235  [  OK  ] Reached target Local File Systems.

10946 12:41:45.792287           Starting Rule-based Manage…for Device Events and Files...

10947 12:41:46.360370  [  OK  ] Finished Flush Journal to Persistent Storage.

10948 12:41:46.422360           Starting Create Volatile Files and Directories...

10949 12:41:46.461271  [  OK  ] Started Rule-based Manager for Device Events and Files.

10950 12:41:46.511017           Starting Network Service...

10951 12:41:46.811475  [  OK  ] Found device /dev/ttyS0.

10952 12:41:46.830531  [  OK  ] Created slice system-systemd\x2dbacklight.slice.

10953 12:41:46.881326           Starting Load/Save Screen …of leds:white:kbd_backlight...

10954 12:41:47.076189  [  OK  ] Listening on Load/Save RF …itch Status /dev/rfkill Watch.

10955 12:41:47.125338           Starting Load/Save RF Kill Switch Status...

10956 12:41:47.163336  [  OK  ] Reached target Bluetooth.

10957 12:41:47.235319  [  OK  ] Finished Create Volatile Files and Directories.

10958 12:41:47.249926  [  OK  ] Started Load/Save RF Kill Switch Status.

10959 12:41:47.265664  [  OK  ] Started Network Service.

10960 12:41:47.285786  [  OK  ] Finished Load/Save Screen …s of leds:white:kbd_backlight.

10961 12:41:47.333909           Starting Network Name Resolution...

10962 12:41:47.359821           Starting Network Time Synchronization...

10963 12:41:47.377347           Starting Update UTMP about System Boot/Shutdown...

10964 12:41:47.436697  [  OK  ] Finished Update UTMP about System Boot/Shutdown.

10965 12:41:47.576184  [  OK  ] Started Network Time Synchronization.

10966 12:41:47.592801  [  OK  ] Reached target System Initialization.

10967 12:41:47.611563  [  OK  ] Started Daily Cleanup of Temporary Directories.

10968 12:41:47.624711  [  OK  ] Reached target System Time Set.

10969 12:41:47.640679  [  OK  ] Reached target System Time Synchronized.

10970 12:41:47.775420  [  OK  ] Started Daily apt download activities.

10971 12:41:47.810668  [  OK  ] Started Daily apt upgrade and clean activities.

10972 12:41:47.840164  [  OK  ] Started Periodic ext4 Onli…ata Check for All Filesystems.

10973 12:41:47.869738  [  OK  ] Started Discard unused blocks once a week.

10974 12:41:47.884449  [  OK  ] Reached target Timers.

10975 12:41:48.239666  [  OK  ] Listening on D-Bus System Message Bus Socket.

10976 12:41:48.252072  [  OK  ] Reached target Sockets.

10977 12:41:48.268211  [  OK  ] Reached target Basic System.

10978 12:41:48.313052  [  OK  ] Started D-Bus System Message Bus.

10979 12:41:48.636723           Starting Remove Stale Onli…t4 Metadata Check Snapshots...

10980 12:41:49.013655           Starting User Login Management...

10981 12:41:49.030596  [  OK  ] Started Network Name Resolution.

10982 12:41:49.051562  [  OK  ] Reached target Network.

10983 12:41:49.071308  [  OK  ] Reached target Host and Network Name Lookups.

10984 12:41:49.124696           Starting Permit User Sessions...

10985 12:41:49.260741  [  OK  ] Finished Permit User Sessions.

10986 12:41:49.286079  [  OK  ] Finished Remove Stale Onli…ext4 Metadata Check Snapshots.

10987 12:41:49.333356  [  OK  ] Started Getty on tty1.

10988 12:41:49.356998  [  OK  ] Started Serial Getty on ttyS0.

10989 12:41:49.365684  [  OK  ] Reached target Login Prompts.

10990 12:41:49.385159  [  OK  ] Started User Login Management.

10991 12:41:49.403344  [  OK  ] Reached target Multi-User System.

10992 12:41:49.422293  [  OK  ] Reached target Graphical Interface.

10993 12:41:49.483548           Starting Update UTMP about System Runlevel Changes...

10994 12:41:49.529664  [  OK  ] Finished Update UTMP about System Runlevel Changes.

10995 12:41:49.632191  

10996 12:41:49.632350  

10997 12:41:49.635313  Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0

10998 12:41:49.635398  

10999 12:41:49.638294  debian-bullseye-arm64 login: root (automatic login)

11000 12:41:49.638379  

11001 12:41:49.638445  

11002 12:41:49.925440  Linux debian-bullseye-arm64 6.1.75-cip14 #1 SMP PREEMPT Mon Feb  5 12:20:06 UTC 2024 aarch64

11003 12:41:49.925577  

11004 12:41:49.932110  The programs included with the Debian GNU/Linux system are free software;

11005 12:41:49.938453  the exact distribution terms for each program are described in the

11006 12:41:49.941892  individual files in /usr/share/doc/*/copyright.

11007 12:41:49.942016  

11008 12:41:49.948444  Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent

11009 12:41:49.951823  permitted by applicable law.

11010 12:41:50.013197  Matched prompt #10: / #
11012 12:41:50.013446  Setting prompt string to ['/ #']
11013 12:41:50.013543  end: 2.2.5.1 login-action (duration 00:00:28) [common]
11015 12:41:50.013736  end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11016 12:41:50.013827  start: 2.2.6 expect-shell-connection (timeout 00:03:35) [common]
11017 12:41:50.013900  Setting prompt string to ['/ #']
11018 12:41:50.014006  Forcing a shell prompt, looking for ['/ #']
11020 12:41:50.064226  / # 

11021 12:41:50.064339  expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11022 12:41:50.064416  Waiting using forced prompt support (timeout 00:02:30)
11023 12:41:50.069547  

11024 12:41:50.069823  end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11025 12:41:50.069922  start: 2.2.7 export-device-env (timeout 00:03:35) [common]
11027 12:41:50.170321  / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12703575/extract-nfsrootfs-nzirnmiu'

11028 12:41:50.175579  export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12703575/extract-nfsrootfs-nzirnmiu'

11030 12:41:50.276094  / # export NFS_SERVER_IP='192.168.201.1'

11031 12:41:50.281045  export NFS_SERVER_IP='192.168.201.1'

11032 12:41:50.281334  end: 2.2.7 export-device-env (duration 00:00:00) [common]
11033 12:41:50.281437  end: 2.2 depthcharge-retry (duration 00:01:25) [common]
11034 12:41:50.281526  end: 2 depthcharge-action (duration 00:01:25) [common]
11035 12:41:50.281621  start: 3 lava-test-retry (timeout 00:01:00) [common]
11036 12:41:50.281712  start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11037 12:41:50.281789  Using namespace: common
11039 12:41:50.382099  / # #

11040 12:41:50.382237  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11041 12:41:50.386796  #

11042 12:41:50.387068  Using /lava-12703575
11044 12:41:50.487377  / # export SHELL=/bin/sh

11045 12:41:50.492462  export SHELL=/bin/sh

11047 12:41:50.592953  / # . /lava-12703575/environment

11048 12:41:50.598301  . /lava-12703575/environment

11050 12:41:50.703898  / # /lava-12703575/bin/lava-test-runner /lava-12703575/0

11051 12:41:50.704026  Test shell timeout: 10s (minimum of the action and connection timeout)
11052 12:41:50.709128  /lava-12703575/bin/lava-test-runner /lava-12703575/0

11053 12:41:50.920874  + export TESTRUN_ID=0_dmesg

11054 12:41:50.924238  + cd /lava-12703575/0/tests/0_dmesg

11055 12:41:50.926989  + cat uuid

11056 12:41:50.938159  + UUID=12703575_<8>[   27.749664] <LAVA_SIGNAL_STARTRUN 0_dmesg 12703575_1.6.2.3.1>

11057 12:41:50.938249  1.6.2.3.1

11058 12:41:50.938318  + set +x

11059 12:41:50.938561  Received signal: <STARTRUN> 0_dmesg 12703575_1.6.2.3.1
11060 12:41:50.938631  Starting test lava.0_dmesg (12703575_1.6.2.3.1)
11061 12:41:50.938719  Skipping test definition patterns.
11062 12:41:50.944727  + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh

11063 12:41:51.021780  <8>[   27.833504] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>

11064 12:41:51.022065  Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11066 12:41:51.087681  <8>[   27.899345] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>

11067 12:41:51.087967  Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11069 12:41:51.151008  <8>[   27.962788] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>

11070 12:41:51.151294  Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11072 12:41:51.154255  + set +x

11073 12:41:51.157549  <8>[   27.972441] <LAVA_SIGNAL_ENDRUN 0_dmesg 12703575_1.6.2.3.1>

11074 12:41:51.157805  Received signal: <ENDRUN> 0_dmesg 12703575_1.6.2.3.1
11075 12:41:51.157896  Ending use of test pattern.
11076 12:41:51.158002  Ending test lava.0_dmesg (12703575_1.6.2.3.1), duration 0.22
11078 12:41:51.163216  <LAVA_TEST_RUNNER EXIT>

11079 12:41:51.163470  ok: lava_test_shell seems to have completed
11080 12:41:51.163575  alert: pass
crit: pass
emerg: pass

11081 12:41:51.163666  end: 3.1 lava-test-shell (duration 00:00:01) [common]
11082 12:41:51.163750  end: 3 lava-test-retry (duration 00:00:01) [common]
11083 12:41:51.163834  start: 4 lava-test-retry (timeout 00:01:00) [common]
11084 12:41:51.163917  start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11085 12:41:51.163983  Using namespace: common
11087 12:41:51.264309  / # #

11088 12:41:51.264441  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11089 12:41:51.264551  Using /lava-12703575
11091 12:41:51.364875  export SHELL=/bin/sh

11092 12:41:51.365034  #

11094 12:41:51.465553  / # export SHELL=/bin/sh. /lava-12703575/environment

11095 12:41:51.465718  

11097 12:41:51.566239  / # . /lava-12703575/environment/lava-12703575/bin/lava-test-runner /lava-12703575/1

11098 12:41:51.566368  Test shell timeout: 10s (minimum of the action and connection timeout)
11099 12:41:51.566483  

11100 12:41:51.571111  / # /lava-12703575/bin/lava-test-runner /lava-12703575/1

11101 12:41:51.678276  + export TESTRUN_ID=1_bootrr

11102 12:41:51.681420  + cd /lava-12703575/1/tests/1_bootrr

11103 12:41:51.684305  + cat uuid

11104 12:41:51.694789  + UUID=12703575_<8>[   28.506757] <LAVA_SIGNAL_STARTRUN 1_bootrr 12703575_1.6.2.3.5>

11105 12:41:51.694878  1.6.2.3.5

11106 12:41:51.694948  + set +x

11107 12:41:51.695186  Received signal: <STARTRUN> 1_bootrr 12703575_1.6.2.3.5
11108 12:41:51.695288  Starting test lava.1_bootrr (12703575_1.6.2.3.5)
11109 12:41:51.695376  Skipping test definition patterns.
11110 12:41:51.707890  + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-12703575/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin

11111 12:41:51.711525  + cd /opt/bootrr/libexec/bootrr

11112 12:41:51.711612  + sh helpers/bootrr-auto

11113 12:41:51.762947  /lava-12703575/1/../bin/lava-test-case

11114 12:41:51.784704  <8>[   28.596609] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>

11115 12:41:51.784980  Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11117 12:41:51.817927  /lava-12703575/1/../bin/lava-test-case

11118 12:41:51.838130  <8>[   28.649976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>

11119 12:41:51.838405  Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11121 12:41:51.856472  /lava-12703575/1/../bin/lava-test-case

11122 12:41:51.876081  <8>[   28.687963] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>

11123 12:41:51.876341  Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11125 12:41:51.923278  /lava-12703575/1/../bin/lava-test-case

11126 12:41:51.942403  <8>[   28.754085] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>

11127 12:41:51.942675  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11129 12:41:51.972343  /lava-12703575/1/../bin/lava-test-case

11130 12:41:51.989679  <8>[   28.801789] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>

11131 12:41:51.989997  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11133 12:41:52.022582  /lava-12703575/1/../bin/lava-test-case

11134 12:41:52.043030  <8>[   28.854591] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>

11135 12:41:52.043318  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11137 12:41:52.072003  /lava-12703575/1/../bin/lava-test-case

11138 12:41:52.095072  <8>[   28.907042] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>

11139 12:41:52.095352  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11141 12:41:52.124470  /lava-12703575/1/../bin/lava-test-case

11142 12:41:52.147252  <8>[   28.958925] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>

11143 12:41:52.147518  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11145 12:41:52.166561  /lava-12703575/1/../bin/lava-test-case

11146 12:41:52.188512  <8>[   29.000270] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>

11147 12:41:52.189317  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11149 12:41:52.226685  /lava-12703575/1/../bin/lava-test-case

11150 12:41:52.258001  <8>[   29.069613] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>

11151 12:41:52.258735  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11153 12:41:52.282713  /lava-12703575/1/../bin/lava-test-case

11154 12:41:52.309273  <8>[   29.120823] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>

11155 12:41:52.309998  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11157 12:41:52.353874  /lava-12703575/1/../bin/lava-test-case

11158 12:41:52.379370  <8>[   29.190897] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>

11159 12:41:52.380245  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11161 12:41:52.413258  /lava-12703575/1/../bin/lava-test-case

11162 12:41:52.440709  <8>[   29.252192] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>

11163 12:41:52.441536  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11165 12:41:52.475107  /lava-12703575/1/../bin/lava-test-case

11166 12:41:52.502164  <8>[   29.314012] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>

11167 12:41:52.503034  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11169 12:41:52.532447  /lava-12703575/1/../bin/lava-test-case

11170 12:41:52.554963  <8>[   29.366965] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>

11171 12:41:52.555247  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11173 12:41:52.577167  /lava-12703575/1/../bin/lava-test-case

11174 12:41:52.601322  <8>[   29.413067] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>

11175 12:41:52.601606  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11177 12:41:52.631218  /lava-12703575/1/../bin/lava-test-case

11178 12:41:52.656422  <8>[   29.468380] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>

11179 12:41:52.656717  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11181 12:41:52.680778  /lava-12703575/1/../bin/lava-test-case

11182 12:41:52.700789  <8>[   29.512996] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>

11183 12:41:52.701100  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11185 12:41:52.732697  /lava-12703575/1/../bin/lava-test-case

11186 12:41:52.755410  <8>[   29.567492] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>

11187 12:41:52.755751  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11189 12:41:52.774909  /lava-12703575/1/../bin/lava-test-case

11190 12:41:52.797784  <8>[   29.609898] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>

11191 12:41:52.798079  Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11193 12:41:52.831253  /lava-12703575/1/../bin/lava-test-case

11194 12:41:52.854774  <8>[   29.666709] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>

11195 12:41:52.855068  Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11197 12:41:52.873320  /lava-12703575/1/../bin/lava-test-case

11198 12:41:52.893651  <8>[   29.705890] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>

11199 12:41:52.893972  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11201 12:41:52.924658  /lava-12703575/1/../bin/lava-test-case

11202 12:41:52.949235  <8>[   29.761077] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>

11203 12:41:52.949529  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11205 12:41:52.968765  /lava-12703575/1/../bin/lava-test-case

11206 12:41:52.991642  <8>[   29.803352] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>

11207 12:41:52.992025  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11209 12:41:53.027995  /lava-12703575/1/../bin/lava-test-case

11210 12:41:53.052680  <8>[   29.864268] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>

11211 12:41:53.053530  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11213 12:41:53.087125  /lava-12703575/1/../bin/lava-test-case

11214 12:41:53.112936  <8>[   29.924617] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>

11215 12:41:53.113830  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11217 12:41:53.134088  /lava-12703575/1/../bin/lava-test-case

11218 12:41:53.154504  <8>[   29.966587] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>

11219 12:41:53.154784  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11221 12:41:53.180884  /lava-12703575/1/../bin/lava-test-case

11222 12:41:53.198809  <8>[   30.010703] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>

11223 12:41:53.199102  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11225 12:41:53.217828  /lava-12703575/1/../bin/lava-test-case

11226 12:41:53.242288  <8>[   30.054543] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>

11227 12:41:53.242558  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11229 12:41:53.269405  /lava-12703575/1/../bin/lava-test-case

11230 12:41:53.289870  <8>[   30.101944] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>

11231 12:41:53.290182  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11233 12:41:53.322107  /lava-12703575/1/../bin/lava-test-case

11234 12:41:53.343522  <8>[   30.155420] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>

11235 12:41:53.343790  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11237 12:41:53.380998  /lava-12703575/1/../bin/lava-test-case

11238 12:41:53.402197  <8>[   30.214176] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>

11239 12:41:53.402468  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11241 12:41:53.431218  /lava-12703575/1/../bin/lava-test-case

11242 12:41:53.456494  <8>[   30.268615] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>

11243 12:41:53.456773  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11245 12:41:53.474815  /lava-12703575/1/../bin/lava-test-case

11246 12:41:53.494439  <8>[   30.306660] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>

11247 12:41:53.494703  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11249 12:41:53.523435  /lava-12703575/1/../bin/lava-test-case

11250 12:41:53.547676  <8>[   30.359731] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>

11251 12:41:53.547940  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11253 12:41:53.574926  /lava-12703575/1/../bin/lava-test-case

11254 12:41:53.593708  <8>[   30.405699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>

11255 12:41:53.593964  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11257 12:41:53.620157  /lava-12703575/1/../bin/lava-test-case

11258 12:41:53.641026  <8>[   30.452984] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>

11259 12:41:53.641290  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11261 12:41:53.671632  /lava-12703575/1/../bin/lava-test-case

11262 12:41:53.693321  <8>[   30.505033] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>

11263 12:41:53.693594  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11265 12:41:53.716479  /lava-12703575/1/../bin/lava-test-case

11266 12:41:53.738049  <8>[   30.549742] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>

11267 12:41:53.738799  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11269 12:41:53.768344  /lava-12703575/1/../bin/lava-test-case

11270 12:41:53.789920  <8>[   30.602063] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>

11271 12:41:53.790230  Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11273 12:41:53.808806  /lava-12703575/1/../bin/lava-test-case

11274 12:41:53.830487  <8>[   30.642441] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>

11275 12:41:53.830744  Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11277 12:41:53.858919  /lava-12703575/1/../bin/lava-test-case

11278 12:41:53.882600  <8>[   30.694486] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>

11279 12:41:53.882870  Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11281 12:41:53.902834  /lava-12703575/1/../bin/lava-test-case

11282 12:41:53.922589  <8>[   30.734782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>

11283 12:41:53.922847  Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11285 12:41:53.950679  /lava-12703575/1/../bin/lava-test-case

11286 12:41:53.971425  <8>[   30.783430] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>

11287 12:41:53.971702  Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11289 12:41:53.989574  /lava-12703575/1/../bin/lava-test-case

11290 12:41:54.012431  <8>[   30.824414] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>

11291 12:41:54.012699  Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11293 12:41:54.050384  /lava-12703575/1/../bin/lava-test-case

11294 12:41:54.071808  <8>[   30.883749] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>

11295 12:41:54.072072  Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11297 12:41:54.089529  /lava-12703575/1/../bin/lava-test-case

11298 12:41:54.110385  <8>[   30.922292] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>

11299 12:41:54.110657  Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11301 12:41:54.140678  /lava-12703575/1/../bin/lava-test-case

11302 12:41:54.162523  <8>[   30.974597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>

11303 12:41:54.162791  Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11305 12:41:54.181336  /lava-12703575/1/../bin/lava-test-case

11306 12:41:54.202659  <8>[   31.014832] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>

11307 12:41:54.202952  Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11309 12:41:54.227967  /lava-12703575/1/../bin/lava-test-case

11310 12:41:54.247774  <8>[   31.060039] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>

11311 12:41:54.248060  Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11313 12:41:54.278162  /lava-12703575/1/../bin/lava-test-case

11314 12:41:54.298487  <8>[   31.110574] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>

11315 12:41:54.298750  Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11317 12:41:54.316955  /lava-12703575/1/../bin/lava-test-case

11318 12:41:54.338690  <8>[   31.150625] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>

11319 12:41:54.338967  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11321 12:41:54.376573  /lava-12703575/1/../bin/lava-test-case

11322 12:41:54.398581  <8>[   31.210511] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>

11323 12:41:54.398899  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11325 12:41:54.418004  /lava-12703575/1/../bin/lava-test-case

11326 12:41:54.437736  <8>[   31.250051] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>

11327 12:41:54.437992  Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11329 12:41:54.468272  /lava-12703575/1/../bin/lava-test-case

11330 12:41:54.490499  <8>[   31.302115] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>

11331 12:41:54.491309  Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11333 12:41:54.520954  /lava-12703575/1/../bin/lava-test-case

11334 12:41:54.541307  <8>[   31.353417] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>

11335 12:41:54.541613  Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11337 12:41:54.567452  /lava-12703575/1/../bin/lava-test-case

11338 12:41:54.591505  <8>[   31.403690] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>

11339 12:41:54.591778  Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11341 12:41:54.617514  /lava-12703575/1/../bin/lava-test-case

11342 12:41:54.638916  <8>[   31.450967] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>

11343 12:41:54.639190  Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11345 12:41:54.670820  /lava-12703575/1/../bin/lava-test-case

11346 12:41:54.691998  <8>[   31.504020] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>

11347 12:41:54.692268  Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11349 12:41:54.717457  /lava-12703575/1/../bin/lava-test-case

11350 12:41:54.738027  <8>[   31.550272] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>

11351 12:41:54.738290  Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11353 12:41:54.765252  /lava-12703575/1/../bin/lava-test-case

11354 12:41:54.784359  <8>[   31.596501] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>

11355 12:41:54.784630  Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11357 12:41:54.809732  /lava-12703575/1/../bin/lava-test-case

11358 12:41:54.829886  <8>[   31.641998] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>

11359 12:41:54.830188  Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11361 12:41:54.847252  /lava-12703575/1/../bin/lava-test-case

11362 12:41:54.866340  <8>[   31.678243] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>

11363 12:41:54.866622  Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11365 12:41:54.890878  /lava-12703575/1/../bin/lava-test-case

11366 12:41:54.911680  <8>[   31.723853] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>

11367 12:41:54.911944  Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11369 12:41:54.928151  /lava-12703575/1/../bin/lava-test-case

11370 12:41:54.949858  <8>[   31.761912] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>

11371 12:41:54.950169  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11373 12:41:54.979236  /lava-12703575/1/../bin/lava-test-case

11374 12:41:55.002174  <8>[   31.814306] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>

11375 12:41:55.002455  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11377 12:41:55.029971  /lava-12703575/1/../bin/lava-test-case

11378 12:41:55.050481  <8>[   31.862617] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>

11379 12:41:55.050747  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11381 12:41:55.076780  /lava-12703575/1/../bin/lava-test-case

11382 12:41:55.097178  <8>[   31.909302] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>

11383 12:41:55.097457  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11385 12:41:55.126976  /lava-12703575/1/../bin/lava-test-case

11386 12:41:55.147568  <8>[   31.959596] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>

11387 12:41:55.147856  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11389 12:41:55.175605  /lava-12703575/1/../bin/lava-test-case

11390 12:41:55.196336  <8>[   32.008663] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>

11391 12:41:55.196608  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11393 12:41:55.225501  /lava-12703575/1/../bin/lava-test-case

11394 12:41:55.249046  <8>[   32.061173] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>

11395 12:41:55.249324  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11397 12:41:55.278371  /lava-12703575/1/../bin/lava-test-case

11398 12:41:55.299389  <8>[   32.111604] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>

11399 12:41:55.299684  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11401 12:41:55.327355  /lava-12703575/1/../bin/lava-test-case

11402 12:41:55.351992  <8>[   32.164381] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>

11403 12:41:55.352257  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11405 12:41:55.386217  /lava-12703575/1/../bin/lava-test-case

11406 12:41:55.409198  <8>[   32.221454] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>

11407 12:41:55.409468  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11409 12:41:55.436303  /lava-12703575/1/../bin/lava-test-case

11410 12:41:55.456622  <8>[   32.268825] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>

11411 12:41:55.456890  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11413 12:41:55.484465  /lava-12703575/1/../bin/lava-test-case

11414 12:41:55.502646  <8>[   32.314638] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>

11415 12:41:55.502910  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11417 12:41:55.529380  /lava-12703575/1/../bin/lava-test-case

11418 12:41:55.553280  <8>[   32.365373] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>

11419 12:41:55.553553  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11421 12:41:55.579709  /lava-12703575/1/../bin/lava-test-case

11422 12:41:55.598564  <8>[   32.410724] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>

11423 12:41:55.598834  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11425 12:41:55.628060  /lava-12703575/1/../bin/lava-test-case

11426 12:41:55.650095  <8>[   32.462371] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>

11427 12:41:55.650363  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11429 12:41:55.677314  /lava-12703575/1/../bin/lava-test-case

11430 12:41:55.697865  <8>[   32.510011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>

11431 12:41:55.698197  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11433 12:41:55.733455  /lava-12703575/1/../bin/lava-test-case

11434 12:41:55.753854  <8>[   32.566298] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>

11435 12:41:55.754182  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11437 12:41:55.783157  /lava-12703575/1/../bin/lava-test-case

11438 12:41:55.800917  <8>[   32.613171] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>

11439 12:41:55.801185  Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11441 12:41:55.819210  /lava-12703575/1/../bin/lava-test-case

11442 12:41:55.839401  <8>[   32.651587] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>

11443 12:41:55.839670  Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11445 12:41:55.876000  /lava-12703575/1/../bin/lava-test-case

11446 12:41:55.897960  <8>[   32.710169] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>

11447 12:41:55.898240  Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11449 12:41:55.913926  /lava-12703575/1/../bin/lava-test-case

11450 12:41:55.937400  <8>[   32.749737] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>

11451 12:41:55.937665  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11453 12:41:55.965086  /lava-12703575/1/../bin/lava-test-case

11454 12:41:55.983716  <8>[   32.796029] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>

11455 12:41:55.983979  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11457 12:41:56.000899  /lava-12703575/1/../bin/lava-test-case

11458 12:41:56.024408  <8>[   32.836581] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>

11459 12:41:56.024665  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11461 12:41:56.061608  /lava-12703575/1/../bin/lava-test-case

11462 12:41:56.084218  <8>[   32.896078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>

11463 12:41:56.084584  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11465 12:41:56.100246  /lava-12703575/1/../bin/lava-test-case

11466 12:41:56.125191  <8>[   32.937353] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>

11467 12:41:56.125456  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11469 12:41:56.152631  /lava-12703575/1/../bin/lava-test-case

11470 12:41:56.176287  <8>[   32.988388] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>

11471 12:41:56.176584  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11473 12:41:56.193598  /lava-12703575/1/../bin/lava-test-case

11474 12:41:56.216295  <8>[   33.028804] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>

11475 12:41:56.216581  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11477 12:41:56.246294  /lava-12703575/1/../bin/lava-test-case

11478 12:41:56.268755  <8>[   33.081133] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>

11479 12:41:56.269053  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11481 12:41:56.285233  /lava-12703575/1/../bin/lava-test-case

11482 12:41:56.306646  <8>[   33.118633] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>

11483 12:41:56.306928  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11485 12:41:56.336389  /lava-12703575/1/../bin/lava-test-case

11486 12:41:56.357968  <8>[   33.170097] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>

11487 12:41:56.358649  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11489 12:41:56.399305  /lava-12703575/1/../bin/lava-test-case

11490 12:41:56.426747  <8>[   33.238787] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>

11491 12:41:56.427711  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11493 12:41:56.448064  /lava-12703575/1/../bin/lava-test-case

11494 12:41:56.473305  <8>[   33.285434] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>

11495 12:41:56.474295  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11497 12:41:56.505617  /lava-12703575/1/../bin/lava-test-case

11498 12:41:56.532984  <8>[   33.344881] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>

11499 12:41:56.533810  Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11501 12:41:56.555206  /lava-12703575/1/../bin/lava-test-case

11502 12:41:56.583609  <8>[   33.395448] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>

11503 12:41:56.584366  Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11505 12:41:56.612345  /lava-12703575/1/../bin/lava-test-case

11506 12:41:56.637881  <8>[   33.450031] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>

11507 12:41:56.638190  Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11509 12:41:56.655049  /lava-12703575/1/../bin/lava-test-case

11510 12:41:56.673839  <8>[   33.485878] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>

11511 12:41:56.674125  Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11513 12:41:57.713374  /lava-12703575/1/../bin/lava-test-case

11514 12:41:57.736434  <8>[   34.549151] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>

11515 12:41:57.736702  Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11517 12:41:57.756156  /lava-12703575/1/../bin/lava-test-case

11518 12:41:57.776681  <8>[   34.589163] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>

11519 12:41:57.776960  Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11521 12:41:58.811116  /lava-12703575/1/../bin/lava-test-case

11522 12:41:58.834090  <8>[   35.646937] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>

11523 12:41:58.834364  Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11525 12:41:58.853550  /lava-12703575/1/../bin/lava-test-case

11526 12:41:58.873524  <8>[   35.686173] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>

11527 12:41:58.873793  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11529 12:41:59.907186  /lava-12703575/1/../bin/lava-test-case

11530 12:41:59.929191  <8>[   36.741779] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>

11531 12:41:59.929470  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11533 12:41:59.947692  /lava-12703575/1/../bin/lava-test-case

11534 12:41:59.964519  <8>[   36.777200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>

11535 12:41:59.964776  Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11537 12:42:00.998881  /lava-12703575/1/../bin/lava-test-case

11538 12:42:01.019611  <8>[   37.832356] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>

11539 12:42:01.020623  Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11541 12:42:01.039623  /lava-12703575/1/../bin/lava-test-case

11542 12:42:01.063206  <8>[   37.875918] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>

11543 12:42:01.064068  Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11545 12:42:02.105100  /lava-12703575/1/../bin/lava-test-case

11546 12:42:02.130819  <8>[   38.943887] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>

11547 12:42:02.131088  Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11549 12:42:02.145960  /lava-12703575/1/../bin/lava-test-case

11550 12:42:02.168186  <8>[   38.981370] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>

11551 12:42:02.168445  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11553 12:42:03.208420  /lava-12703575/1/../bin/lava-test-case

11554 12:42:03.237790  <8>[   40.051044] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>

11555 12:42:03.238106  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11557 12:42:03.258359  /lava-12703575/1/../bin/lava-test-case

11558 12:42:03.282581  <8>[   40.095846] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>

11559 12:42:03.282842  Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11561 12:42:04.322325  /lava-12703575/1/../bin/lava-test-case

11562 12:42:04.345599  <8>[   41.158786] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>

11563 12:42:04.345916  Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11565 12:42:04.364108  /lava-12703575/1/../bin/lava-test-case

11566 12:42:04.385500  <8>[   41.198621] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>

11567 12:42:04.385794  Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11569 12:42:04.404379  /lava-12703575/1/../bin/lava-test-case

11570 12:42:04.424578  <8>[   41.238077] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>

11571 12:42:04.424873  Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11573 12:42:05.463066  /lava-12703575/1/../bin/lava-test-case

11574 12:42:05.489409  <8>[   42.302284] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>

11575 12:42:05.490257  Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11577 12:42:05.510462  /lava-12703575/1/../bin/lava-test-case

11578 12:42:05.536860  <8>[   42.349867] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>

11579 12:42:05.537671  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11581 12:42:05.573640  /lava-12703575/1/../bin/lava-test-case

11582 12:42:05.605388  <8>[   42.418280] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>

11583 12:42:05.606108  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11585 12:42:05.629696  /lava-12703575/1/../bin/lava-test-case

11586 12:42:05.656177  <8>[   42.469392] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>

11587 12:42:05.656440  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11589 12:42:05.684183  /lava-12703575/1/../bin/lava-test-case

11590 12:42:05.704173  <8>[   42.517651] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>

11591 12:42:05.704441  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11593 12:42:05.733065  /lava-12703575/1/../bin/lava-test-case

11594 12:42:05.755540  <8>[   42.568765] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>

11595 12:42:05.755815  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11597 12:42:05.793862  /lava-12703575/1/../bin/lava-test-case

11598 12:42:05.819466  <8>[   42.632661] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>

11599 12:42:05.820363  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11601 12:42:05.842210  /lava-12703575/1/../bin/lava-test-case

11602 12:42:05.870814  <8>[   42.683690] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>

11603 12:42:05.871566  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11605 12:42:05.903125  /lava-12703575/1/../bin/lava-test-case

11606 12:42:05.924191  <8>[   42.737543] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>

11607 12:42:05.924479  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11609 12:42:05.955476  /lava-12703575/1/../bin/lava-test-case

11610 12:42:05.979032  <8>[   42.792159] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>

11611 12:42:05.979300  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11613 12:42:05.997252  /lava-12703575/1/../bin/lava-test-case

11614 12:42:06.021266  <8>[   42.834702] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>

11615 12:42:06.021524  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11617 12:42:06.049519  /lava-12703575/1/../bin/lava-test-case

11618 12:42:06.069318  <8>[   42.882454] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>

11619 12:42:06.069583  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11621 12:42:06.096164  /lava-12703575/1/../bin/lava-test-case

11622 12:42:06.116664  <8>[   42.930015] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>

11623 12:42:06.116913  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11625 12:42:06.143698  /lava-12703575/1/../bin/lava-test-case

11626 12:42:06.165854  <8>[   42.979371] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>

11627 12:42:06.166132  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11629 12:42:06.186931  /lava-12703575/1/../bin/lava-test-case

11630 12:42:06.205879  <8>[   43.019429] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>

11631 12:42:06.206134  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11633 12:42:06.232714  /lava-12703575/1/../bin/lava-test-case

11634 12:42:06.255587  <8>[   43.069149] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>

11635 12:42:06.255846  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11637 12:42:06.272553  /lava-12703575/1/../bin/lava-test-case

11638 12:42:06.290153  <8>[   43.103782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>

11639 12:42:06.290407  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11641 12:42:06.319661  /lava-12703575/1/../bin/lava-test-case

11642 12:42:06.337299  <8>[   43.150867] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>

11643 12:42:06.337554  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11645 12:42:06.356297  /lava-12703575/1/../bin/lava-test-case

11646 12:42:06.373796  <8>[   43.187197] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>

11647 12:42:06.374078  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11649 12:42:06.411030  /lava-12703575/1/../bin/lava-test-case

11650 12:42:06.430901  <8>[   43.244205] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>

11651 12:42:06.431676  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11653 12:42:06.448559  /lava-12703575/1/../bin/lava-test-case

11654 12:42:06.468353  <8>[   43.281657] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>

11655 12:42:06.468619  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11657 12:42:07.507694  /lava-12703575/1/../bin/lava-test-case

11658 12:42:07.534741  <8>[   44.347732] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>

11659 12:42:07.535430  Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11661 12:42:08.572792  /lava-12703575/1/../bin/lava-test-case

11662 12:42:08.601461  <8>[   45.414747] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>

11663 12:42:08.602539  Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11665 12:42:08.620289  /lava-12703575/1/../bin/lava-test-case

11666 12:42:08.644520  <8>[   45.457689] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>

11667 12:42:08.645221  Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11669 12:42:08.674912  /lava-12703575/1/../bin/lava-test-case

11670 12:42:08.698430  <8>[   45.511948] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>

11671 12:42:08.699148  Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11673 12:42:08.719250  /lava-12703575/1/../bin/lava-test-case

11674 12:42:08.743461  <8>[   45.556895] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>

11675 12:42:08.744186  Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11677 12:42:08.777397  /lava-12703575/1/../bin/lava-test-case

11678 12:42:08.804598  <8>[   45.618221] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>

11679 12:42:08.805344  Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11681 12:42:08.825781  /lava-12703575/1/../bin/lava-test-case

11682 12:42:08.850247  <8>[   45.664246] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>

11683 12:42:08.850503  Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11685 12:42:08.885696  /lava-12703575/1/../bin/lava-test-case

11686 12:42:08.912680  <8>[   45.726221] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>

11687 12:42:08.912979  Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11689 12:42:08.931404  /lava-12703575/1/../bin/lava-test-case

11690 12:42:08.953767  <8>[   45.767635] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>

11691 12:42:08.954045  Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11693 12:42:08.985005  /lava-12703575/1/../bin/lava-test-case

11694 12:42:09.009456  <8>[   45.822735] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>

11695 12:42:09.010264  Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11697 12:42:09.031111  /lava-12703575/1/../bin/lava-test-case

11698 12:42:09.058199  <8>[   45.871371] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>

11699 12:42:09.059042  Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11701 12:42:09.092793  /lava-12703575/1/../bin/lava-test-case

11702 12:42:09.121423  <8>[   45.934823] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>

11703 12:42:09.122302  Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11705 12:42:09.143173  /lava-12703575/1/../bin/lava-test-case

11706 12:42:09.169302  <8>[   45.982839] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>

11707 12:42:09.169662  Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11709 12:42:09.205898  /lava-12703575/1/../bin/lava-test-case

11710 12:42:09.228348  <8>[   46.042113] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>

11711 12:42:09.228625  Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11713 12:42:09.247644  /lava-12703575/1/../bin/lava-test-case

11714 12:42:09.271313  <8>[   46.084804] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>

11715 12:42:09.271571  Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11717 12:42:09.301921  /lava-12703575/1/../bin/lava-test-case

11718 12:42:09.327961  <8>[   46.141373] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>

11719 12:42:09.328745  Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11721 12:42:09.338194  <6>[   46.158648] vpu: disabling

11722 12:42:09.341723  <6>[   46.161853] vproc2: disabling

11723 12:42:09.345129  <6>[   46.165306] vproc1: disabling

11724 12:42:09.348581  <6>[   46.168776] vaud18: disabling

11725 12:42:09.356336  <6>[   46.173656] vsram_others: disabling

11726 12:42:09.359881  <6>[   46.179128] va09: disabling

11727 12:42:09.363554  <6>[   46.182752] vsram_md: disabling

11728 12:42:09.366746  <6>[   46.186415] Vgpu: disabling

11729 12:42:09.375831  /lava-12703575/1/../bin/lava-test-case

11730 12:42:09.399794  <8>[   46.213704] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>

11731 12:42:09.400171  Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11733 12:42:09.432779  /lava-12703575/1/../bin/lava-test-case

11734 12:42:09.457784  <8>[   46.271427] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>

11735 12:42:09.458169  Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11737 12:42:09.480904  /lava-12703575/1/../bin/lava-test-case

11738 12:42:09.506635  <8>[   46.320174] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>

11739 12:42:09.506987  Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11741 12:42:09.548735  /lava-12703575/1/../bin/lava-test-case

11742 12:42:09.573892  <8>[   46.387378] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>

11743 12:42:09.574435  Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11745 12:42:09.594801  /lava-12703575/1/../bin/lava-test-case

11746 12:42:09.622520  <8>[   46.435636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>

11747 12:42:09.623405  Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11749 12:42:09.654976  /lava-12703575/1/../bin/lava-test-case

11750 12:42:09.680920  <8>[   46.494846] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>

11751 12:42:09.681329  Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11753 12:42:10.711809  /lava-12703575/1/../bin/lava-test-case

11754 12:42:10.741397  <8>[   47.554967] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>

11755 12:42:10.742370  Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11757 12:42:11.775084  /lava-12703575/1/../bin/lava-test-case

11758 12:42:11.803891  <8>[   48.617471] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>

11759 12:42:11.804680  Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11760 12:42:11.805221  Bad test result: blocked
11761 12:42:11.827652  /lava-12703575/1/../bin/lava-test-case

11762 12:42:11.852537  <8>[   48.666185] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>

11763 12:42:11.853456  Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11765 12:42:12.892628  /lava-12703575/1/../bin/lava-test-case

11766 12:42:12.917556  <8>[   49.731706] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>

11767 12:42:12.917829  Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11769 12:42:12.936584  /lava-12703575/1/../bin/lava-test-case

11770 12:42:12.960738  <8>[   49.775116] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>

11771 12:42:12.960997  Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11773 12:42:12.990607  /lava-12703575/1/../bin/lava-test-case

11774 12:42:13.014883  <8>[   49.829065] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>

11775 12:42:13.015250  Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11777 12:42:13.044826  /lava-12703575/1/../bin/lava-test-case

11778 12:42:13.070446  <8>[   49.884520] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>

11779 12:42:13.070713  Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11781 12:42:13.089522  /lava-12703575/1/../bin/lava-test-case

11782 12:42:13.111058  <8>[   49.925458] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>

11783 12:42:13.111322  Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11785 12:42:13.139999  /lava-12703575/1/../bin/lava-test-case

11786 12:42:13.162694  <8>[   49.977065] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>

11787 12:42:13.162956  Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11789 12:42:13.180238  /lava-12703575/1/../bin/lava-test-case

11790 12:42:13.202310  <8>[   50.016650] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>

11791 12:42:13.202567  Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11793 12:42:14.246014  /lava-12703575/1/../bin/lava-test-case

11794 12:42:14.273619  <8>[   51.087508] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>

11795 12:42:14.274303  Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11797 12:42:14.290515  /lava-12703575/1/../bin/lava-test-case

11798 12:42:14.313164  <8>[   51.127812] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>

11799 12:42:14.313437  Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11801 12:42:15.353630  /lava-12703575/1/../bin/lava-test-case

11802 12:42:15.380291  <8>[   52.194678] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>

11803 12:42:15.381007  Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11805 12:42:15.400414  /lava-12703575/1/../bin/lava-test-case

11806 12:42:15.425884  <8>[   52.240016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>

11807 12:42:15.426776  Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11809 12:42:16.467748  /lava-12703575/1/../bin/lava-test-case

11810 12:42:16.495971  <8>[   53.310431] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>

11811 12:42:16.496838  Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11813 12:42:16.518051  /lava-12703575/1/../bin/lava-test-case

11814 12:42:16.545657  <8>[   53.359748] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>

11815 12:42:16.546588  Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11817 12:42:17.589339  /lava-12703575/1/../bin/lava-test-case

11818 12:42:17.615581  <8>[   54.430025] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>

11819 12:42:17.616372  Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11821 12:42:17.635748  /lava-12703575/1/../bin/lava-test-case

11822 12:42:17.662180  <8>[   54.476902] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>

11823 12:42:17.662894  Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11825 12:42:17.692420  /lava-12703575/1/../bin/lava-test-case

11826 12:42:17.717624  <8>[   54.531921] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>

11827 12:42:17.718447  Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11829 12:42:17.751771  /lava-12703575/1/../bin/lava-test-case

11830 12:42:17.772603  <8>[   54.587297] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>

11831 12:42:17.772882  Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11833 12:42:17.788516  /lava-12703575/1/../bin/lava-test-case

11834 12:42:17.808002  <8>[   54.623025] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>

11835 12:42:17.808264  Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11837 12:42:17.835133  /lava-12703575/1/../bin/lava-test-case

11838 12:42:17.855455  <8>[   54.670418] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>

11839 12:42:17.855713  Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11841 12:42:17.873261  /lava-12703575/1/../bin/lava-test-case

11842 12:42:17.895261  <8>[   54.710069] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>

11843 12:42:17.895538  Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11845 12:42:17.931525  /lava-12703575/1/../bin/lava-test-case

11846 12:42:17.952339  <8>[   54.767214] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>

11847 12:42:17.952603  Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11849 12:42:17.971509  /lava-12703575/1/../bin/lava-test-case

11850 12:42:17.991945  <8>[   54.806542] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>

11851 12:42:17.992204  Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11853 12:42:18.018911  /lava-12703575/1/../bin/lava-test-case

11854 12:42:18.040669  <8>[   54.855523] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>

11855 12:42:18.040928  Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11857 12:42:18.046663  + set +x

11858 12:42:18.049973  Received signal: <ENDRUN> 1_bootrr 12703575_1.6.2.3.5
11859 12:42:18.050070  Ending use of test pattern.
11860 12:42:18.050134  Ending test lava.1_bootrr (12703575_1.6.2.3.5), duration 26.35
11862 12:42:18.053081  <8>[   54.868141] <LAVA_SIGNAL_ENDRUN 1_bootrr 12703575_1.6.2.3.5>

11863 12:42:18.057223  <LAVA_TEST_RUNNER EXIT>

11864 12:42:18.057475  ok: lava_test_shell seems to have completed
11865 12:42:18.058503  all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass

11866 12:42:18.058647  end: 4.1 lava-test-shell (duration 00:00:27) [common]
11867 12:42:18.058739  end: 4 lava-test-retry (duration 00:00:27) [common]
11868 12:42:18.058831  start: 5 finalize (timeout 00:07:42) [common]
11869 12:42:18.058921  start: 5.1 power-off (timeout 00:00:30) [common]
11870 12:42:18.059072  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11871 12:42:18.133259  >> Command sent successfully.

11872 12:42:18.135626  Returned 0 in 0 seconds
11873 12:42:18.236432  end: 5.1 power-off (duration 00:00:00) [common]
11875 12:42:18.238634  start: 5.2 read-feedback (timeout 00:07:42) [common]
11876 12:42:18.240145  Listened to connection for namespace 'common' for up to 1s
11877 12:42:19.240174  Finalising connection for namespace 'common'
11878 12:42:19.240353  Disconnecting from shell: Finalise
11879 12:42:19.240479  / # 
11880 12:42:19.340813  end: 5.2 read-feedback (duration 00:00:01) [common]
11881 12:42:19.340993  end: 5 finalize (duration 00:00:01) [common]
11882 12:42:19.341158  Cleaning after the job
11883 12:42:19.341297  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703575/tftp-deploy-50eelh8k/ramdisk
11884 12:42:19.343403  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703575/tftp-deploy-50eelh8k/kernel
11885 12:42:19.353130  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703575/tftp-deploy-50eelh8k/dtb
11886 12:42:19.353322  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703575/tftp-deploy-50eelh8k/nfsrootfs
11887 12:42:19.408342  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703575/tftp-deploy-50eelh8k/modules
11888 12:42:19.413932  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12703575
11889 12:42:19.724303  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12703575
11890 12:42:19.724487  Job finished correctly