Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 16
- Kernel Errors: 36
1 12:41:28.360327 lava-dispatcher, installed at version: 2024.01
2 12:41:28.360538 start: 0 validate
3 12:41:28.360681 Start time: 2024-02-05 12:41:28.360671+00:00 (UTC)
4 12:41:28.360848 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:41:28.360978 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 12:41:28.628183 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:41:28.628897 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:41:28.898488 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:41:28.899194 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:41:29.167406 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:41:29.168191 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:41:29.438681 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:41:29.439480 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.75-cip14-6-ga817aa655908%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:41:29.710808 validate duration: 1.35
16 12:41:29.711061 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:41:29.711154 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:41:29.711236 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:41:29.711360 Not decompressing ramdisk as can be used compressed.
20 12:41:29.711442 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 12:41:29.711503 saving as /var/lib/lava/dispatcher/tmp/12703551/tftp-deploy-oba5nm6w/ramdisk/initrd.cpio.gz
22 12:41:29.711566 total size: 4665395 (4 MB)
23 12:41:29.712621 progress 0 % (0 MB)
24 12:41:29.714030 progress 5 % (0 MB)
25 12:41:29.715490 progress 10 % (0 MB)
26 12:41:29.716716 progress 15 % (0 MB)
27 12:41:29.717964 progress 20 % (0 MB)
28 12:41:29.719244 progress 25 % (1 MB)
29 12:41:29.720487 progress 30 % (1 MB)
30 12:41:29.721714 progress 35 % (1 MB)
31 12:41:29.722977 progress 40 % (1 MB)
32 12:41:29.724362 progress 45 % (2 MB)
33 12:41:29.725578 progress 50 % (2 MB)
34 12:41:29.726856 progress 55 % (2 MB)
35 12:41:29.728085 progress 60 % (2 MB)
36 12:41:29.729322 progress 65 % (2 MB)
37 12:41:29.730587 progress 70 % (3 MB)
38 12:41:29.731809 progress 75 % (3 MB)
39 12:41:29.733024 progress 80 % (3 MB)
40 12:41:29.734411 progress 85 % (3 MB)
41 12:41:29.735680 progress 90 % (4 MB)
42 12:41:29.736899 progress 95 % (4 MB)
43 12:41:29.738136 progress 100 % (4 MB)
44 12:41:29.738290 4 MB downloaded in 0.03 s (166.49 MB/s)
45 12:41:29.738486 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:41:29.738726 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:41:29.738812 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:41:29.738895 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:41:29.739043 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:41:29.739146 saving as /var/lib/lava/dispatcher/tmp/12703551/tftp-deploy-oba5nm6w/kernel/Image
52 12:41:29.739212 total size: 51534336 (49 MB)
53 12:41:29.739275 No compression specified
54 12:41:29.740392 progress 0 % (0 MB)
55 12:41:29.753556 progress 5 % (2 MB)
56 12:41:29.766876 progress 10 % (4 MB)
57 12:41:29.780065 progress 15 % (7 MB)
58 12:41:29.793489 progress 20 % (9 MB)
59 12:41:29.806923 progress 25 % (12 MB)
60 12:41:29.820083 progress 30 % (14 MB)
61 12:41:29.833692 progress 35 % (17 MB)
62 12:41:29.847073 progress 40 % (19 MB)
63 12:41:29.860168 progress 45 % (22 MB)
64 12:41:29.873489 progress 50 % (24 MB)
65 12:41:29.886725 progress 55 % (27 MB)
66 12:41:29.900137 progress 60 % (29 MB)
67 12:41:29.913442 progress 65 % (31 MB)
68 12:41:29.926792 progress 70 % (34 MB)
69 12:41:29.940245 progress 75 % (36 MB)
70 12:41:29.953597 progress 80 % (39 MB)
71 12:41:29.966808 progress 85 % (41 MB)
72 12:41:29.980145 progress 90 % (44 MB)
73 12:41:29.993437 progress 95 % (46 MB)
74 12:41:30.006576 progress 100 % (49 MB)
75 12:41:30.006810 49 MB downloaded in 0.27 s (183.66 MB/s)
76 12:41:30.006961 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:41:30.007200 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:41:30.007290 start: 1.3 download-retry (timeout 00:10:00) [common]
80 12:41:30.007375 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 12:41:30.007512 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:41:30.007589 saving as /var/lib/lava/dispatcher/tmp/12703551/tftp-deploy-oba5nm6w/dtb/mt8192-asurada-spherion-r0.dtb
83 12:41:30.007649 total size: 47278 (0 MB)
84 12:41:30.007709 No compression specified
85 12:41:30.008838 progress 69 % (0 MB)
86 12:41:30.009112 progress 100 % (0 MB)
87 12:41:30.009267 0 MB downloaded in 0.00 s (27.91 MB/s)
88 12:41:30.009385 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:41:30.009602 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:41:30.009686 start: 1.4 download-retry (timeout 00:10:00) [common]
92 12:41:30.009766 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 12:41:30.009879 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 12:41:30.009949 saving as /var/lib/lava/dispatcher/tmp/12703551/tftp-deploy-oba5nm6w/nfsrootfs/full.rootfs.tar
95 12:41:30.010008 total size: 200813988 (191 MB)
96 12:41:30.010068 Using unxz to decompress xz
97 12:41:30.014059 progress 0 % (0 MB)
98 12:41:30.559864 progress 5 % (9 MB)
99 12:41:31.072622 progress 10 % (19 MB)
100 12:41:31.669176 progress 15 % (28 MB)
101 12:41:32.051238 progress 20 % (38 MB)
102 12:41:32.393275 progress 25 % (47 MB)
103 12:41:33.006265 progress 30 % (57 MB)
104 12:41:33.564299 progress 35 % (67 MB)
105 12:41:34.159711 progress 40 % (76 MB)
106 12:41:34.745465 progress 45 % (86 MB)
107 12:41:35.330031 progress 50 % (95 MB)
108 12:41:35.960859 progress 55 % (105 MB)
109 12:41:36.624399 progress 60 % (114 MB)
110 12:41:36.750720 progress 65 % (124 MB)
111 12:41:36.891561 progress 70 % (134 MB)
112 12:41:36.987848 progress 75 % (143 MB)
113 12:41:37.058579 progress 80 % (153 MB)
114 12:41:37.126622 progress 85 % (162 MB)
115 12:41:37.227197 progress 90 % (172 MB)
116 12:41:37.507104 progress 95 % (181 MB)
117 12:41:38.085590 progress 100 % (191 MB)
118 12:41:38.090814 191 MB downloaded in 8.08 s (23.70 MB/s)
119 12:41:38.091089 end: 1.4.1 http-download (duration 00:00:08) [common]
121 12:41:38.091383 end: 1.4 download-retry (duration 00:00:08) [common]
122 12:41:38.091490 start: 1.5 download-retry (timeout 00:09:52) [common]
123 12:41:38.091595 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 12:41:38.091765 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:41:38.091841 saving as /var/lib/lava/dispatcher/tmp/12703551/tftp-deploy-oba5nm6w/modules/modules.tar
126 12:41:38.091923 total size: 8639964 (8 MB)
127 12:41:38.092026 Using unxz to decompress xz
128 12:41:38.096638 progress 0 % (0 MB)
129 12:41:38.117724 progress 5 % (0 MB)
130 12:41:38.141190 progress 10 % (0 MB)
131 12:41:38.164774 progress 15 % (1 MB)
132 12:41:38.188097 progress 20 % (1 MB)
133 12:41:38.212080 progress 25 % (2 MB)
134 12:41:38.239717 progress 30 % (2 MB)
135 12:41:38.264018 progress 35 % (2 MB)
136 12:41:38.287318 progress 40 % (3 MB)
137 12:41:38.311707 progress 45 % (3 MB)
138 12:41:38.336871 progress 50 % (4 MB)
139 12:41:38.363037 progress 55 % (4 MB)
140 12:41:38.387773 progress 60 % (4 MB)
141 12:41:38.413560 progress 65 % (5 MB)
142 12:41:38.438588 progress 70 % (5 MB)
143 12:41:38.462049 progress 75 % (6 MB)
144 12:41:38.488758 progress 80 % (6 MB)
145 12:41:38.516493 progress 85 % (7 MB)
146 12:41:38.541285 progress 90 % (7 MB)
147 12:41:38.570966 progress 95 % (7 MB)
148 12:41:38.598661 progress 100 % (8 MB)
149 12:41:38.604526 8 MB downloaded in 0.51 s (16.07 MB/s)
150 12:41:38.604777 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:41:38.605042 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:41:38.605135 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 12:41:38.605234 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 12:41:42.071808 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12703551/extract-nfsrootfs-tshsvmla
156 12:41:42.072017 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 12:41:42.072122 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 12:41:42.072294 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4
159 12:41:42.072427 makedir: /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/bin
160 12:41:42.072529 makedir: /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/tests
161 12:41:42.072628 makedir: /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/results
162 12:41:42.072728 Creating /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/bin/lava-add-keys
163 12:41:42.072876 Creating /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/bin/lava-add-sources
164 12:41:42.073008 Creating /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/bin/lava-background-process-start
165 12:41:42.073137 Creating /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/bin/lava-background-process-stop
166 12:41:42.073265 Creating /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/bin/lava-common-functions
167 12:41:42.073392 Creating /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/bin/lava-echo-ipv4
168 12:41:42.073519 Creating /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/bin/lava-install-packages
169 12:41:42.073647 Creating /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/bin/lava-installed-packages
170 12:41:42.073774 Creating /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/bin/lava-os-build
171 12:41:42.073901 Creating /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/bin/lava-probe-channel
172 12:41:42.074026 Creating /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/bin/lava-probe-ip
173 12:41:42.074152 Creating /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/bin/lava-target-ip
174 12:41:42.074278 Creating /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/bin/lava-target-mac
175 12:41:42.074407 Creating /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/bin/lava-target-storage
176 12:41:42.074575 Creating /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/bin/lava-test-case
177 12:41:42.074703 Creating /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/bin/lava-test-event
178 12:41:42.074828 Creating /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/bin/lava-test-feedback
179 12:41:42.074954 Creating /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/bin/lava-test-raise
180 12:41:42.075080 Creating /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/bin/lava-test-reference
181 12:41:42.075205 Creating /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/bin/lava-test-runner
182 12:41:42.075331 Creating /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/bin/lava-test-set
183 12:41:42.075455 Creating /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/bin/lava-test-shell
184 12:41:42.075583 Updating /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/bin/lava-add-keys (debian)
185 12:41:42.075738 Updating /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/bin/lava-add-sources (debian)
186 12:41:42.075882 Updating /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/bin/lava-install-packages (debian)
187 12:41:42.076023 Updating /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/bin/lava-installed-packages (debian)
188 12:41:42.076163 Updating /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/bin/lava-os-build (debian)
189 12:41:42.076286 Creating /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/environment
190 12:41:42.076381 LAVA metadata
191 12:41:42.076450 - LAVA_JOB_ID=12703551
192 12:41:42.076514 - LAVA_DISPATCHER_IP=192.168.201.1
193 12:41:42.076613 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 12:41:42.076680 skipped lava-vland-overlay
195 12:41:42.076754 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 12:41:42.076832 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 12:41:42.076893 skipped lava-multinode-overlay
198 12:41:42.076965 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 12:41:42.077044 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 12:41:42.077116 Loading test definitions
201 12:41:42.077202 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 12:41:42.077272 Using /lava-12703551 at stage 0
203 12:41:42.077553 uuid=12703551_1.6.2.3.1 testdef=None
204 12:41:42.077643 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 12:41:42.077754 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 12:41:42.078253 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 12:41:42.078638 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 12:41:42.079213 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 12:41:42.079444 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 12:41:42.079986 runner path: /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/0/tests/0_timesync-off test_uuid 12703551_1.6.2.3.1
213 12:41:42.080147 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 12:41:42.080373 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 12:41:42.080446 Using /lava-12703551 at stage 0
217 12:41:42.080542 Fetching tests from https://github.com/kernelci/test-definitions.git
218 12:41:42.080629 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/0/tests/1_kselftest-dt'
219 12:41:47.825898 Running '/usr/bin/git checkout kernelci.org
220 12:41:47.973639 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 12:41:47.974384 uuid=12703551_1.6.2.3.5 testdef=None
222 12:41:47.974600 end: 1.6.2.3.5 git-repo-action (duration 00:00:06) [common]
224 12:41:47.974865 start: 1.6.2.3.6 test-overlay (timeout 00:09:42) [common]
225 12:41:47.975618 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 12:41:47.975852 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:42) [common]
228 12:41:47.976861 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 12:41:47.977107 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:42) [common]
231 12:41:47.978116 runner path: /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/0/tests/1_kselftest-dt test_uuid 12703551_1.6.2.3.5
232 12:41:47.978206 BOARD='mt8192-asurada-spherion-r0'
233 12:41:47.978291 BRANCH='cip-gitlab'
234 12:41:47.978379 SKIPFILE='/dev/null'
235 12:41:47.978493 SKIP_INSTALL='True'
236 12:41:47.978552 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 12:41:47.978613 TST_CASENAME=''
238 12:41:47.978677 TST_CMDFILES='dt'
239 12:41:47.978823 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 12:41:47.979044 Creating lava-test-runner.conf files
242 12:41:47.979109 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12703551/lava-overlay-6_fladp4/lava-12703551/0 for stage 0
243 12:41:47.979210 - 0_timesync-off
244 12:41:47.979308 - 1_kselftest-dt
245 12:41:47.979440 end: 1.6.2.3 test-definition (duration 00:00:06) [common]
246 12:41:47.979561 start: 1.6.2.4 compress-overlay (timeout 00:09:42) [common]
247 12:41:55.500999 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 12:41:55.501165 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:34) [common]
249 12:41:55.501255 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 12:41:55.501357 end: 1.6.2 lava-overlay (duration 00:00:13) [common]
251 12:41:55.501446 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
252 12:41:55.622674 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 12:41:55.623058 start: 1.6.4 extract-modules (timeout 00:09:34) [common]
254 12:41:55.623173 extracting modules file /var/lib/lava/dispatcher/tmp/12703551/tftp-deploy-oba5nm6w/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12703551/extract-nfsrootfs-tshsvmla
255 12:41:55.845376 extracting modules file /var/lib/lava/dispatcher/tmp/12703551/tftp-deploy-oba5nm6w/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12703551/extract-overlay-ramdisk-rlw71qy0/ramdisk
256 12:41:56.071805 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 12:41:56.071972 start: 1.6.5 apply-overlay-tftp (timeout 00:09:34) [common]
258 12:41:56.072057 [common] Applying overlay to NFS
259 12:41:56.072128 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12703551/compress-overlay-0972vwbm/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12703551/extract-nfsrootfs-tshsvmla
260 12:41:57.002796 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 12:41:57.002970 start: 1.6.6 configure-preseed-file (timeout 00:09:33) [common]
262 12:41:57.003070 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 12:41:57.003164 start: 1.6.7 compress-ramdisk (timeout 00:09:33) [common]
264 12:41:57.003250 Building ramdisk /var/lib/lava/dispatcher/tmp/12703551/extract-overlay-ramdisk-rlw71qy0/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12703551/extract-overlay-ramdisk-rlw71qy0/ramdisk
265 12:41:57.338579 >> 119430 blocks
266 12:41:59.250994 rename /var/lib/lava/dispatcher/tmp/12703551/extract-overlay-ramdisk-rlw71qy0/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12703551/tftp-deploy-oba5nm6w/ramdisk/ramdisk.cpio.gz
267 12:41:59.251568 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 12:41:59.251746 start: 1.6.8 prepare-kernel (timeout 00:09:30) [common]
269 12:41:59.251890 start: 1.6.8.1 prepare-fit (timeout 00:09:30) [common]
270 12:41:59.252057 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12703551/tftp-deploy-oba5nm6w/kernel/Image'
271 12:42:12.759326 Returned 0 in 13 seconds
272 12:42:12.859979 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12703551/tftp-deploy-oba5nm6w/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12703551/tftp-deploy-oba5nm6w/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12703551/tftp-deploy-oba5nm6w/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12703551/tftp-deploy-oba5nm6w/kernel/image.itb
273 12:42:13.212168 output: FIT description: Kernel Image image with one or more FDT blobs
274 12:42:13.212551 output: Created: Mon Feb 5 12:42:13 2024
275 12:42:13.212624 output: Image 0 (kernel-1)
276 12:42:13.212691 output: Description:
277 12:42:13.212756 output: Created: Mon Feb 5 12:42:13 2024
278 12:42:13.212820 output: Type: Kernel Image
279 12:42:13.212882 output: Compression: lzma compressed
280 12:42:13.212942 output: Data Size: 12052857 Bytes = 11770.37 KiB = 11.49 MiB
281 12:42:13.213003 output: Architecture: AArch64
282 12:42:13.213078 output: OS: Linux
283 12:42:13.213147 output: Load Address: 0x00000000
284 12:42:13.213204 output: Entry Point: 0x00000000
285 12:42:13.213259 output: Hash algo: crc32
286 12:42:13.213311 output: Hash value: 8a14336a
287 12:42:13.213365 output: Image 1 (fdt-1)
288 12:42:13.213417 output: Description: mt8192-asurada-spherion-r0
289 12:42:13.213469 output: Created: Mon Feb 5 12:42:13 2024
290 12:42:13.213521 output: Type: Flat Device Tree
291 12:42:13.213573 output: Compression: uncompressed
292 12:42:13.213625 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 12:42:13.213678 output: Architecture: AArch64
294 12:42:13.213729 output: Hash algo: crc32
295 12:42:13.213781 output: Hash value: cc4352de
296 12:42:13.213833 output: Image 2 (ramdisk-1)
297 12:42:13.213884 output: Description: unavailable
298 12:42:13.213936 output: Created: Mon Feb 5 12:42:13 2024
299 12:42:13.213988 output: Type: RAMDisk Image
300 12:42:13.214039 output: Compression: Unknown Compression
301 12:42:13.214090 output: Data Size: 17803101 Bytes = 17385.84 KiB = 16.98 MiB
302 12:42:13.214142 output: Architecture: AArch64
303 12:42:13.214193 output: OS: Linux
304 12:42:13.214245 output: Load Address: unavailable
305 12:42:13.214296 output: Entry Point: unavailable
306 12:42:13.214347 output: Hash algo: crc32
307 12:42:13.214408 output: Hash value: d671d611
308 12:42:13.214496 output: Default Configuration: 'conf-1'
309 12:42:13.214547 output: Configuration 0 (conf-1)
310 12:42:13.214599 output: Description: mt8192-asurada-spherion-r0
311 12:42:13.214650 output: Kernel: kernel-1
312 12:42:13.214702 output: Init Ramdisk: ramdisk-1
313 12:42:13.214753 output: FDT: fdt-1
314 12:42:13.214804 output: Loadables: kernel-1
315 12:42:13.214856 output:
316 12:42:13.215066 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 12:42:13.215166 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 12:42:13.215267 end: 1.6 prepare-tftp-overlay (duration 00:00:35) [common]
319 12:42:13.215360 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:16) [common]
320 12:42:13.215443 No LXC device requested
321 12:42:13.215525 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 12:42:13.215609 start: 1.8 deploy-device-env (timeout 00:09:16) [common]
323 12:42:13.215688 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 12:42:13.215754 Checking files for TFTP limit of 4294967296 bytes.
325 12:42:13.216263 end: 1 tftp-deploy (duration 00:00:44) [common]
326 12:42:13.216374 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 12:42:13.216469 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 12:42:13.216595 substitutions:
329 12:42:13.216662 - {DTB}: 12703551/tftp-deploy-oba5nm6w/dtb/mt8192-asurada-spherion-r0.dtb
330 12:42:13.216727 - {INITRD}: 12703551/tftp-deploy-oba5nm6w/ramdisk/ramdisk.cpio.gz
331 12:42:13.216786 - {KERNEL}: 12703551/tftp-deploy-oba5nm6w/kernel/Image
332 12:42:13.216843 - {LAVA_MAC}: None
333 12:42:13.216898 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12703551/extract-nfsrootfs-tshsvmla
334 12:42:13.216953 - {NFS_SERVER_IP}: 192.168.201.1
335 12:42:13.217007 - {PRESEED_CONFIG}: None
336 12:42:13.217060 - {PRESEED_LOCAL}: None
337 12:42:13.217113 - {RAMDISK}: 12703551/tftp-deploy-oba5nm6w/ramdisk/ramdisk.cpio.gz
338 12:42:13.217165 - {ROOT_PART}: None
339 12:42:13.217217 - {ROOT}: None
340 12:42:13.217270 - {SERVER_IP}: 192.168.201.1
341 12:42:13.217321 - {TEE}: None
342 12:42:13.217373 Parsed boot commands:
343 12:42:13.217426 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 12:42:13.217608 Parsed boot commands: tftpboot 192.168.201.1 12703551/tftp-deploy-oba5nm6w/kernel/image.itb 12703551/tftp-deploy-oba5nm6w/kernel/cmdline
345 12:42:13.217696 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 12:42:13.217782 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 12:42:13.217906 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 12:42:13.217992 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 12:42:13.218069 Not connected, no need to disconnect.
350 12:42:13.218144 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 12:42:13.218226 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 12:42:13.218296 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
353 12:42:13.222333 Setting prompt string to ['lava-test: # ']
354 12:42:13.222767 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 12:42:13.222873 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 12:42:13.222974 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 12:42:13.223068 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 12:42:13.223270 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
359 12:42:18.368395 >> Command sent successfully.
360 12:42:18.379646 Returned 0 in 5 seconds
361 12:42:18.480886 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 12:42:18.482285 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 12:42:18.482829 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 12:42:18.483300 Setting prompt string to 'Starting depthcharge on Spherion...'
366 12:42:18.483642 Changing prompt to 'Starting depthcharge on Spherion...'
367 12:42:18.483986 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 12:42:18.485218 [Enter `^Ec?' for help]
369 12:42:18.646711
370 12:42:18.647315
371 12:42:18.647675 F0: 102B 0000
372 12:42:18.648027
373 12:42:18.648533 F3: 1001 0000 [0200]
374 12:42:18.650548
375 12:42:18.650978 F3: 1001 0000
376 12:42:18.651335
377 12:42:18.651669 F7: 102D 0000
378 12:42:18.651982
379 12:42:18.653321 F1: 0000 0000
380 12:42:18.653750
381 12:42:18.654092 V0: 0000 0000 [0001]
382 12:42:18.654474
383 12:42:18.656728 00: 0007 8000
384 12:42:18.657213
385 12:42:18.657558 01: 0000 0000
386 12:42:18.657884
387 12:42:18.660549 BP: 0C00 0209 [0000]
388 12:42:18.660980
389 12:42:18.661334 G0: 1182 0000
390 12:42:18.661688
391 12:42:18.663714 EC: 0000 0021 [4000]
392 12:42:18.664142
393 12:42:18.664496 S7: 0000 0000 [0000]
394 12:42:18.665049
395 12:42:18.668422 CC: 0000 0000 [0001]
396 12:42:18.668851
397 12:42:18.669188 T0: 0000 0040 [010F]
398 12:42:18.669510
399 12:42:18.669990 Jump to BL
400 12:42:18.670318
401 12:42:18.694133
402 12:42:18.694728
403 12:42:18.695078
404 12:42:18.701358 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 12:42:18.705540 ARM64: Exception handlers installed.
406 12:42:18.709648 ARM64: Testing exception
407 12:42:18.712394 ARM64: Done test exception
408 12:42:18.718947 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 12:42:18.729075 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 12:42:18.735817 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 12:42:18.746320 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 12:42:18.752622 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 12:42:18.759186 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 12:42:18.770917 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 12:42:18.777876 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 12:42:18.796805 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 12:42:18.800374 WDT: Last reset was cold boot
418 12:42:18.803795 SPI1(PAD0) initialized at 2873684 Hz
419 12:42:18.807276 SPI5(PAD0) initialized at 992727 Hz
420 12:42:18.810296 VBOOT: Loading verstage.
421 12:42:18.817138 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:42:18.820377 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 12:42:18.823450 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 12:42:18.827096 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 12:42:18.834437 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 12:42:18.841195 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 12:42:18.851690 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 12:42:18.852232
429 12:42:18.852598
430 12:42:18.861916 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 12:42:18.865289 ARM64: Exception handlers installed.
432 12:42:18.868422 ARM64: Testing exception
433 12:42:18.868900 ARM64: Done test exception
434 12:42:18.875590 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 12:42:18.878930 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 12:42:18.893626 Probing TPM: . done!
437 12:42:18.894124 TPM ready after 0 ms
438 12:42:18.901498 Connected to device vid:did:rid of 1ae0:0028:00
439 12:42:18.908411 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 12:42:18.964798 Initialized TPM device CR50 revision 0
441 12:42:18.976337 tlcl_send_startup: Startup return code is 0
442 12:42:18.976776 TPM: setup succeeded
443 12:42:18.988262 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 12:42:18.997388 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 12:42:19.007637 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 12:42:19.018678 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 12:42:19.021740 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 12:42:19.030689 in-header: 03 07 00 00 08 00 00 00
449 12:42:19.034849 in-data: aa e4 47 04 13 02 00 00
450 12:42:19.038747 Chrome EC: UHEPI supported
451 12:42:19.042067 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 12:42:19.046514 in-header: 03 ad 00 00 08 00 00 00
453 12:42:19.050038 in-data: 00 20 20 08 00 00 00 00
454 12:42:19.050629 Phase 1
455 12:42:19.057419 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 12:42:19.061152 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 12:42:19.068597 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 12:42:19.069049 Recovery requested (1009000e)
459 12:42:19.078929 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 12:42:19.084734 tlcl_extend: response is 0
461 12:42:19.093915 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 12:42:19.099581 tlcl_extend: response is 0
463 12:42:19.106212 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 12:42:19.126439 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 12:42:19.133476 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 12:42:19.133911
467 12:42:19.134274
468 12:42:19.144315 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 12:42:19.147919 ARM64: Exception handlers installed.
470 12:42:19.148439 ARM64: Testing exception
471 12:42:19.150609 ARM64: Done test exception
472 12:42:19.171700 pmic_efuse_setting: Set efuses in 11 msecs
473 12:42:19.175373 pmwrap_interface_init: Select PMIF_VLD_RDY
474 12:42:19.182100 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 12:42:19.185439 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 12:42:19.192698 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 12:42:19.195981 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 12:42:19.200064 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 12:42:19.203668 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 12:42:19.211152 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 12:42:19.215446 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 12:42:19.218108 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 12:42:19.226012 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 12:42:19.229540 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 12:42:19.233259 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 12:42:19.237510 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 12:42:19.245188 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 12:42:19.248902 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 12:42:19.255684 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 12:42:19.259120 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 12:42:19.267277 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 12:42:19.271297 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 12:42:19.278496 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 12:42:19.282984 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 12:42:19.289284 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 12:42:19.293543 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 12:42:19.300555 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 12:42:19.304354 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 12:42:19.311858 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 12:42:19.315238 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 12:42:19.319495 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 12:42:19.326486 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 12:42:19.330529 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 12:42:19.338451 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 12:42:19.341007 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 12:42:19.345183 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 12:42:19.352289 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 12:42:19.355919 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 12:42:19.359909 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 12:42:19.366896 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 12:42:19.370978 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 12:42:19.374318 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 12:42:19.378514 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 12:42:19.385476 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 12:42:19.388739 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 12:42:19.393307 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 12:42:19.397114 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 12:42:19.400172 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 12:42:19.407521 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 12:42:19.412077 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 12:42:19.415350 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 12:42:19.418751 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 12:42:19.422957 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 12:42:19.426480 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 12:42:19.434453 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 12:42:19.441754 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 12:42:19.449664 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 12:42:19.456184 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 12:42:19.463531 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 12:42:19.467399 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 12:42:19.475000 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 12:42:19.478465 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 12:42:19.485691 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0xc
534 12:42:19.489571 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 12:42:19.496984 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 12:42:19.500658 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 12:42:19.509784 [RTC]rtc_get_frequency_meter,154: input=15, output=790
538 12:42:19.518656 [RTC]rtc_get_frequency_meter,154: input=23, output=978
539 12:42:19.528189 [RTC]rtc_get_frequency_meter,154: input=19, output=883
540 12:42:19.537975 [RTC]rtc_get_frequency_meter,154: input=17, output=837
541 12:42:19.547145 [RTC]rtc_get_frequency_meter,154: input=16, output=813
542 12:42:19.556834 [RTC]rtc_get_frequency_meter,154: input=15, output=789
543 12:42:19.566814 [RTC]rtc_get_frequency_meter,154: input=16, output=814
544 12:42:19.570129 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
545 12:42:19.574501 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
546 12:42:19.577677 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 12:42:19.585652 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 12:42:19.589128 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 12:42:19.593148 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 12:42:19.596847 ADC[4]: Raw value=901697 ID=7
551 12:42:19.597415 ADC[3]: Raw value=213336 ID=1
552 12:42:19.599872 RAM Code: 0x71
553 12:42:19.604259 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 12:42:19.607492 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 12:42:19.619266 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 12:42:19.623012 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 12:42:19.625730 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 12:42:19.630010 in-header: 03 07 00 00 08 00 00 00
559 12:42:19.633987 in-data: aa e4 47 04 13 02 00 00
560 12:42:19.637340 Chrome EC: UHEPI supported
561 12:42:19.645359 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 12:42:19.645787 in-header: 03 ed 00 00 08 00 00 00
563 12:42:19.649172 in-data: 80 20 60 08 00 00 00 00
564 12:42:19.653029 MRC: failed to locate region type 0.
565 12:42:19.660166 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 12:42:19.663848 DRAM-K: Running full calibration
567 12:42:19.668123 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 12:42:19.671575 header.status = 0x0
569 12:42:19.674943 header.version = 0x6 (expected: 0x6)
570 12:42:19.678232 header.size = 0xd00 (expected: 0xd00)
571 12:42:19.678805 header.flags = 0x0
572 12:42:19.685408 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 12:42:19.703796 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 12:42:19.711896 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 12:42:19.712326 dram_init: ddr_geometry: 2
576 12:42:19.714908 [EMI] MDL number = 2
577 12:42:19.718592 [EMI] Get MDL freq = 0
578 12:42:19.719134 dram_init: ddr_type: 0
579 12:42:19.722029 is_discrete_lpddr4: 1
580 12:42:19.726325 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 12:42:19.726875
582 12:42:19.727213
583 12:42:19.729005 [Bian_co] ETT version 0.0.0.1
584 12:42:19.732888 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 12:42:19.733310
586 12:42:19.736307 dramc_set_vcore_voltage set vcore to 650000
587 12:42:19.736727 Read voltage for 800, 4
588 12:42:19.739985 Vio18 = 0
589 12:42:19.740545 Vcore = 650000
590 12:42:19.740889 Vdram = 0
591 12:42:19.743810 Vddq = 0
592 12:42:19.744233 Vmddr = 0
593 12:42:19.744568 dram_init: config_dvfs: 1
594 12:42:19.751430 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 12:42:19.755667 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 12:42:19.758887 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
597 12:42:19.763227 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
598 12:42:19.765742 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
599 12:42:19.772575 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
600 12:42:19.773001 MEM_TYPE=3, freq_sel=18
601 12:42:19.776176 sv_algorithm_assistance_LP4_1600
602 12:42:19.779795 ============ PULL DRAM RESETB DOWN ============
603 12:42:19.786064 ========== PULL DRAM RESETB DOWN end =========
604 12:42:19.789246 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 12:42:19.792788 ===================================
606 12:42:19.796282 LPDDR4 DRAM CONFIGURATION
607 12:42:19.798806 ===================================
608 12:42:19.799299 EX_ROW_EN[0] = 0x0
609 12:42:19.803048 EX_ROW_EN[1] = 0x0
610 12:42:19.803643 LP4Y_EN = 0x0
611 12:42:19.806204 WORK_FSP = 0x0
612 12:42:19.806860 WL = 0x2
613 12:42:19.808985 RL = 0x2
614 12:42:19.813199 BL = 0x2
615 12:42:19.813796 RPST = 0x0
616 12:42:19.815606 RD_PRE = 0x0
617 12:42:19.816081 WR_PRE = 0x1
618 12:42:19.819621 WR_PST = 0x0
619 12:42:19.820206 DBI_WR = 0x0
620 12:42:19.823114 DBI_RD = 0x0
621 12:42:19.823590 OTF = 0x1
622 12:42:19.826046 ===================================
623 12:42:19.829365 ===================================
624 12:42:19.829844 ANA top config
625 12:42:19.832666 ===================================
626 12:42:19.836083 DLL_ASYNC_EN = 0
627 12:42:19.839472 ALL_SLAVE_EN = 1
628 12:42:19.843241 NEW_RANK_MODE = 1
629 12:42:19.846043 DLL_IDLE_MODE = 1
630 12:42:19.846762 LP45_APHY_COMB_EN = 1
631 12:42:19.849721 TX_ODT_DIS = 1
632 12:42:19.852723 NEW_8X_MODE = 1
633 12:42:19.856431 ===================================
634 12:42:19.859216 ===================================
635 12:42:19.862882 data_rate = 1600
636 12:42:19.865869 CKR = 1
637 12:42:19.866334 DQ_P2S_RATIO = 8
638 12:42:19.869401 ===================================
639 12:42:19.873134 CA_P2S_RATIO = 8
640 12:42:19.876114 DQ_CA_OPEN = 0
641 12:42:19.880846 DQ_SEMI_OPEN = 0
642 12:42:19.882930 CA_SEMI_OPEN = 0
643 12:42:19.883377 CA_FULL_RATE = 0
644 12:42:19.886296 DQ_CKDIV4_EN = 1
645 12:42:19.889852 CA_CKDIV4_EN = 1
646 12:42:19.892785 CA_PREDIV_EN = 0
647 12:42:19.896464 PH8_DLY = 0
648 12:42:19.899935 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 12:42:19.900512 DQ_AAMCK_DIV = 4
650 12:42:19.903769 CA_AAMCK_DIV = 4
651 12:42:19.906981 CA_ADMCK_DIV = 4
652 12:42:19.909858 DQ_TRACK_CA_EN = 0
653 12:42:19.913459 CA_PICK = 800
654 12:42:19.916325 CA_MCKIO = 800
655 12:42:19.916774 MCKIO_SEMI = 0
656 12:42:19.920417 PLL_FREQ = 3068
657 12:42:19.924127 DQ_UI_PI_RATIO = 32
658 12:42:19.927853 CA_UI_PI_RATIO = 0
659 12:42:19.931554 ===================================
660 12:42:19.932003 ===================================
661 12:42:19.935138 memory_type:LPDDR4
662 12:42:19.938921 GP_NUM : 10
663 12:42:19.939453 SRAM_EN : 1
664 12:42:19.942584 MD32_EN : 0
665 12:42:19.946484 ===================================
666 12:42:19.946933 [ANA_INIT] >>>>>>>>>>>>>>
667 12:42:19.950375 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 12:42:19.953723 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 12:42:19.957737 ===================================
670 12:42:19.960359 data_rate = 1600,PCW = 0X7600
671 12:42:19.964115 ===================================
672 12:42:19.967381 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 12:42:19.970804 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 12:42:19.977839 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 12:42:19.980908 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 12:42:19.983865 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 12:42:19.987695 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 12:42:19.991384 [ANA_INIT] flow start
679 12:42:19.994215 [ANA_INIT] PLL >>>>>>>>
680 12:42:19.994702 [ANA_INIT] PLL <<<<<<<<
681 12:42:19.997625 [ANA_INIT] MIDPI >>>>>>>>
682 12:42:20.001038 [ANA_INIT] MIDPI <<<<<<<<
683 12:42:20.001594 [ANA_INIT] DLL >>>>>>>>
684 12:42:20.004663 [ANA_INIT] flow end
685 12:42:20.007622 ============ LP4 DIFF to SE enter ============
686 12:42:20.011725 ============ LP4 DIFF to SE exit ============
687 12:42:20.015000 [ANA_INIT] <<<<<<<<<<<<<
688 12:42:20.018066 [Flow] Enable top DCM control >>>>>
689 12:42:20.020997 [Flow] Enable top DCM control <<<<<
690 12:42:20.024516 Enable DLL master slave shuffle
691 12:42:20.031315 ==============================================================
692 12:42:20.031861 Gating Mode config
693 12:42:20.038547 ==============================================================
694 12:42:20.039101 Config description:
695 12:42:20.048378 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 12:42:20.054523 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 12:42:20.061475 SELPH_MODE 0: By rank 1: By Phase
698 12:42:20.064673 ==============================================================
699 12:42:20.068409 GAT_TRACK_EN = 1
700 12:42:20.071770 RX_GATING_MODE = 2
701 12:42:20.075142 RX_GATING_TRACK_MODE = 2
702 12:42:20.078592 SELPH_MODE = 1
703 12:42:20.082321 PICG_EARLY_EN = 1
704 12:42:20.085152 VALID_LAT_VALUE = 1
705 12:42:20.088825 ==============================================================
706 12:42:20.091886 Enter into Gating configuration >>>>
707 12:42:20.095056 Exit from Gating configuration <<<<
708 12:42:20.098551 Enter into DVFS_PRE_config >>>>>
709 12:42:20.108296 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 12:42:20.112001 Exit from DVFS_PRE_config <<<<<
711 12:42:20.115111 Enter into PICG configuration >>>>
712 12:42:20.118553 Exit from PICG configuration <<<<
713 12:42:20.122037 [RX_INPUT] configuration >>>>>
714 12:42:20.125620 [RX_INPUT] configuration <<<<<
715 12:42:20.132149 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 12:42:20.135711 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 12:42:20.143360 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 12:42:20.149475 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 12:42:20.152513 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 12:42:20.159375 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 12:42:20.163168 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 12:42:20.170117 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 12:42:20.172688 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 12:42:20.176339 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 12:42:20.179359 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 12:42:20.186253 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 12:42:20.189867 ===================================
728 12:42:20.190494 LPDDR4 DRAM CONFIGURATION
729 12:42:20.193485 ===================================
730 12:42:20.196354 EX_ROW_EN[0] = 0x0
731 12:42:20.200124 EX_ROW_EN[1] = 0x0
732 12:42:20.200693 LP4Y_EN = 0x0
733 12:42:20.202993 WORK_FSP = 0x0
734 12:42:20.203564 WL = 0x2
735 12:42:20.206195 RL = 0x2
736 12:42:20.206739 BL = 0x2
737 12:42:20.209391 RPST = 0x0
738 12:42:20.209864 RD_PRE = 0x0
739 12:42:20.213092 WR_PRE = 0x1
740 12:42:20.213562 WR_PST = 0x0
741 12:42:20.216299 DBI_WR = 0x0
742 12:42:20.216873 DBI_RD = 0x0
743 12:42:20.219969 OTF = 0x1
744 12:42:20.223319 ===================================
745 12:42:20.226161 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 12:42:20.229648 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 12:42:20.233412 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 12:42:20.236427 ===================================
749 12:42:20.239866 LPDDR4 DRAM CONFIGURATION
750 12:42:20.243543 ===================================
751 12:42:20.246567 EX_ROW_EN[0] = 0x10
752 12:42:20.247017 EX_ROW_EN[1] = 0x0
753 12:42:20.250536 LP4Y_EN = 0x0
754 12:42:20.251066 WORK_FSP = 0x0
755 12:42:20.253267 WL = 0x2
756 12:42:20.253692 RL = 0x2
757 12:42:20.257078 BL = 0x2
758 12:42:20.257643 RPST = 0x0
759 12:42:20.259948 RD_PRE = 0x0
760 12:42:20.260378 WR_PRE = 0x1
761 12:42:20.263616 WR_PST = 0x0
762 12:42:20.264044 DBI_WR = 0x0
763 12:42:20.266485 DBI_RD = 0x0
764 12:42:20.266917 OTF = 0x1
765 12:42:20.269853 ===================================
766 12:42:20.276729 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 12:42:20.281658 nWR fixed to 40
768 12:42:20.284799 [ModeRegInit_LP4] CH0 RK0
769 12:42:20.285369 [ModeRegInit_LP4] CH0 RK1
770 12:42:20.288220 [ModeRegInit_LP4] CH1 RK0
771 12:42:20.291436 [ModeRegInit_LP4] CH1 RK1
772 12:42:20.291865 match AC timing 13
773 12:42:20.298177 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 12:42:20.301771 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 12:42:20.305289 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 12:42:20.311814 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 12:42:20.315008 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 12:42:20.315433 [EMI DOE] emi_dcm 0
779 12:42:20.321824 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 12:42:20.322249 ==
781 12:42:20.325162 Dram Type= 6, Freq= 0, CH_0, rank 0
782 12:42:20.329123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 12:42:20.329687 ==
784 12:42:20.335138 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 12:42:20.338728 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 12:42:20.349131 [CA 0] Center 37 (7~68) winsize 62
787 12:42:20.352818 [CA 1] Center 37 (6~68) winsize 63
788 12:42:20.355986 [CA 2] Center 35 (5~66) winsize 62
789 12:42:20.359062 [CA 3] Center 34 (4~65) winsize 62
790 12:42:20.362624 [CA 4] Center 34 (3~65) winsize 63
791 12:42:20.366477 [CA 5] Center 33 (3~64) winsize 62
792 12:42:20.367056
793 12:42:20.369198 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 12:42:20.369658
795 12:42:20.372351 [CATrainingPosCal] consider 1 rank data
796 12:42:20.375720 u2DelayCellTimex100 = 270/100 ps
797 12:42:20.379171 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 12:42:20.382781 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 12:42:20.389862 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
800 12:42:20.392846 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 12:42:20.396326 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
802 12:42:20.399648 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 12:42:20.400416
804 12:42:20.402603 CA PerBit enable=1, Macro0, CA PI delay=33
805 12:42:20.403075
806 12:42:20.406320 [CBTSetCACLKResult] CA Dly = 33
807 12:42:20.406942 CS Dly: 5 (0~36)
808 12:42:20.407323 ==
809 12:42:20.409691 Dram Type= 6, Freq= 0, CH_0, rank 1
810 12:42:20.416048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 12:42:20.416626 ==
812 12:42:20.419483 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 12:42:20.426675 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 12:42:20.435624 [CA 0] Center 37 (6~68) winsize 63
815 12:42:20.439163 [CA 1] Center 37 (6~68) winsize 63
816 12:42:20.442594 [CA 2] Center 35 (4~66) winsize 63
817 12:42:20.445669 [CA 3] Center 35 (4~66) winsize 63
818 12:42:20.449362 [CA 4] Center 34 (4~65) winsize 62
819 12:42:20.452193 [CA 5] Center 34 (4~64) winsize 61
820 12:42:20.452675
821 12:42:20.455589 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 12:42:20.456157
823 12:42:20.459239 [CATrainingPosCal] consider 2 rank data
824 12:42:20.462138 u2DelayCellTimex100 = 270/100 ps
825 12:42:20.465971 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
826 12:42:20.469336 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
827 12:42:20.472128 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
828 12:42:20.478951 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
829 12:42:20.482539 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
830 12:42:20.485782 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
831 12:42:20.486362
832 12:42:20.489233 CA PerBit enable=1, Macro0, CA PI delay=34
833 12:42:20.489804
834 12:42:20.492972 [CBTSetCACLKResult] CA Dly = 34
835 12:42:20.493540 CS Dly: 5 (0~37)
836 12:42:20.493939
837 12:42:20.496032 ----->DramcWriteLeveling(PI) begin...
838 12:42:20.496513 ==
839 12:42:20.499378 Dram Type= 6, Freq= 0, CH_0, rank 0
840 12:42:20.506879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 12:42:20.507363 ==
842 12:42:20.507739 Write leveling (Byte 0): 29 => 29
843 12:42:20.510249 Write leveling (Byte 1): 29 => 29
844 12:42:20.514246 DramcWriteLeveling(PI) end<-----
845 12:42:20.514715
846 12:42:20.515057 ==
847 12:42:20.518054 Dram Type= 6, Freq= 0, CH_0, rank 0
848 12:42:20.520979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 12:42:20.521406 ==
850 12:42:20.524652 [Gating] SW mode calibration
851 12:42:20.531875 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 12:42:20.535780 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 12:42:20.542525 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 12:42:20.548760 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 12:42:20.549193 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
856 12:42:20.556043 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 12:42:20.558756 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 12:42:20.562640 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:42:20.568990 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:42:20.572359 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:42:20.575588 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 12:42:20.579196 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 12:42:20.586500 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 12:42:20.589449 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 12:42:20.593067 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 12:42:20.599212 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 12:42:20.602609 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 12:42:20.605999 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 12:42:20.612374 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 12:42:20.615781 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 12:42:20.620033 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
872 12:42:20.626241 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
873 12:42:20.629645 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 12:42:20.632559 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 12:42:20.635863 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 12:42:20.643337 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 12:42:20.646102 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 12:42:20.649976 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 12:42:20.656924 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 12:42:20.659996 0 9 12 | B1->B0 | 2424 3030 | 0 1 | (0 0) (1 1)
881 12:42:20.663095 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 12:42:20.669830 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 12:42:20.673390 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 12:42:20.676494 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 12:42:20.683348 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 12:42:20.687025 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
887 12:42:20.689856 0 10 8 | B1->B0 | 3434 3030 | 0 1 | (0 0) (1 0)
888 12:42:20.696269 0 10 12 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
889 12:42:20.700163 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 12:42:20.703383 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 12:42:20.707132 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 12:42:20.713096 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 12:42:20.717115 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 12:42:20.719969 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
895 12:42:20.726768 0 11 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
896 12:42:20.730224 0 11 12 | B1->B0 | 3737 4343 | 0 0 | (0 0) (1 1)
897 12:42:20.733661 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 12:42:20.740288 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 12:42:20.744005 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 12:42:20.747025 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 12:42:20.754023 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 12:42:20.757586 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 12:42:20.760455 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
904 12:42:20.764002 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
905 12:42:20.770926 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 12:42:20.773480 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 12:42:20.777294 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 12:42:20.784120 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 12:42:20.787299 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 12:42:20.791127 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 12:42:20.797122 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 12:42:20.800631 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 12:42:20.804560 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 12:42:20.810937 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 12:42:20.814352 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 12:42:20.817396 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 12:42:20.820847 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 12:42:20.827644 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 12:42:20.830900 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
920 12:42:20.834176 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 12:42:20.837297 Total UI for P1: 0, mck2ui 16
922 12:42:20.840421 best dqsien dly found for B0: ( 0, 14, 8)
923 12:42:20.843864 Total UI for P1: 0, mck2ui 16
924 12:42:20.847451 best dqsien dly found for B1: ( 0, 14, 8)
925 12:42:20.851179 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
926 12:42:20.854816 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 12:42:20.855339
928 12:42:20.857738 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
929 12:42:20.864316 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 12:42:20.864736 [Gating] SW calibration Done
931 12:42:20.865070 ==
932 12:42:20.867996 Dram Type= 6, Freq= 0, CH_0, rank 0
933 12:42:20.874508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 12:42:20.874955 ==
935 12:42:20.875361 RX Vref Scan: 0
936 12:42:20.875697
937 12:42:20.877719 RX Vref 0 -> 0, step: 1
938 12:42:20.878138
939 12:42:20.880901 RX Delay -130 -> 252, step: 16
940 12:42:20.884197 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 12:42:20.887556 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
942 12:42:20.891418 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 12:42:20.897575 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 12:42:20.902090 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 12:42:20.904776 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 12:42:20.908063 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 12:42:20.911132 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
948 12:42:20.914542 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 12:42:20.920986 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
950 12:42:20.924491 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
951 12:42:20.927752 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 12:42:20.931309 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 12:42:20.935269 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 12:42:20.941950 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
955 12:42:20.945343 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
956 12:42:20.945766 ==
957 12:42:20.947998 Dram Type= 6, Freq= 0, CH_0, rank 0
958 12:42:20.951651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 12:42:20.952075 ==
960 12:42:20.955438 DQS Delay:
961 12:42:20.955860 DQS0 = 0, DQS1 = 0
962 12:42:20.956194 DQM Delay:
963 12:42:20.958275 DQM0 = 87, DQM1 = 80
964 12:42:20.958723 DQ Delay:
965 12:42:20.961342 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
966 12:42:20.965129 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
967 12:42:20.968186 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
968 12:42:20.971831 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
969 12:42:20.972255
970 12:42:20.972587
971 12:42:20.972895 ==
972 12:42:20.975073 Dram Type= 6, Freq= 0, CH_0, rank 0
973 12:42:20.981501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 12:42:20.981929 ==
975 12:42:20.982269
976 12:42:20.982621
977 12:42:20.982925 TX Vref Scan disable
978 12:42:20.984774 == TX Byte 0 ==
979 12:42:20.988546 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
980 12:42:20.991780 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
981 12:42:20.995563 == TX Byte 1 ==
982 12:42:20.998084 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
983 12:42:21.001492 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
984 12:42:21.004857 ==
985 12:42:21.008481 Dram Type= 6, Freq= 0, CH_0, rank 0
986 12:42:21.011941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 12:42:21.012366 ==
988 12:42:21.024347 TX Vref=22, minBit 0, minWin=27, winSum=441
989 12:42:21.027263 TX Vref=24, minBit 3, minWin=27, winSum=443
990 12:42:21.030433 TX Vref=26, minBit 7, minWin=27, winSum=446
991 12:42:21.034488 TX Vref=28, minBit 13, minWin=27, winSum=451
992 12:42:21.037365 TX Vref=30, minBit 2, minWin=28, winSum=453
993 12:42:21.041032 TX Vref=32, minBit 3, minWin=27, winSum=452
994 12:42:21.047484 [TxChooseVref] Worse bit 2, Min win 28, Win sum 453, Final Vref 30
995 12:42:21.047912
996 12:42:21.050900 Final TX Range 1 Vref 30
997 12:42:21.051324
998 12:42:21.051660 ==
999 12:42:21.054479 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 12:42:21.058235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 12:42:21.058710 ==
1002 12:42:21.059049
1003 12:42:21.059359
1004 12:42:21.060881 TX Vref Scan disable
1005 12:42:21.064147 == TX Byte 0 ==
1006 12:42:21.068967 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1007 12:42:21.071193 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1008 12:42:21.074288 == TX Byte 1 ==
1009 12:42:21.078062 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1010 12:42:21.081166 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1011 12:42:21.081626
1012 12:42:21.084693 [DATLAT]
1013 12:42:21.085114 Freq=800, CH0 RK0
1014 12:42:21.085464
1015 12:42:21.087529 DATLAT Default: 0xa
1016 12:42:21.088241 0, 0xFFFF, sum = 0
1017 12:42:21.090822 1, 0xFFFF, sum = 0
1018 12:42:21.091425 2, 0xFFFF, sum = 0
1019 12:42:21.094773 3, 0xFFFF, sum = 0
1020 12:42:21.095220 4, 0xFFFF, sum = 0
1021 12:42:21.097621 5, 0xFFFF, sum = 0
1022 12:42:21.098258 6, 0xFFFF, sum = 0
1023 12:42:21.100815 7, 0xFFFF, sum = 0
1024 12:42:21.101404 8, 0xFFFF, sum = 0
1025 12:42:21.104129 9, 0x0, sum = 1
1026 12:42:21.104573 10, 0x0, sum = 2
1027 12:42:21.107644 11, 0x0, sum = 3
1028 12:42:21.108062 12, 0x0, sum = 4
1029 12:42:21.111070 best_step = 10
1030 12:42:21.111678
1031 12:42:21.112235 ==
1032 12:42:21.114366 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 12:42:21.117938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 12:42:21.118646 ==
1035 12:42:21.121301 RX Vref Scan: 1
1036 12:42:21.121747
1037 12:42:21.122141 Set Vref Range= 32 -> 127
1038 12:42:21.122648
1039 12:42:21.124557 RX Vref 32 -> 127, step: 1
1040 12:42:21.124989
1041 12:42:21.127811 RX Delay -95 -> 252, step: 8
1042 12:42:21.128245
1043 12:42:21.131200 Set Vref, RX VrefLevel [Byte0]: 32
1044 12:42:21.134763 [Byte1]: 32
1045 12:42:21.135202
1046 12:42:21.138523 Set Vref, RX VrefLevel [Byte0]: 33
1047 12:42:21.141612 [Byte1]: 33
1048 12:42:21.142037
1049 12:42:21.145344 Set Vref, RX VrefLevel [Byte0]: 34
1050 12:42:21.148955 [Byte1]: 34
1051 12:42:21.149531
1052 12:42:21.152335 Set Vref, RX VrefLevel [Byte0]: 35
1053 12:42:21.155740 [Byte1]: 35
1054 12:42:21.160245
1055 12:42:21.160759 Set Vref, RX VrefLevel [Byte0]: 36
1056 12:42:21.162474 [Byte1]: 36
1057 12:42:21.167353
1058 12:42:21.167917 Set Vref, RX VrefLevel [Byte0]: 37
1059 12:42:21.171110 [Byte1]: 37
1060 12:42:21.175325
1061 12:42:21.175736 Set Vref, RX VrefLevel [Byte0]: 38
1062 12:42:21.178510 [Byte1]: 38
1063 12:42:21.182790
1064 12:42:21.183201 Set Vref, RX VrefLevel [Byte0]: 39
1065 12:42:21.185799 [Byte1]: 39
1066 12:42:21.189861
1067 12:42:21.193039 Set Vref, RX VrefLevel [Byte0]: 40
1068 12:42:21.193461 [Byte1]: 40
1069 12:42:21.197950
1070 12:42:21.198656 Set Vref, RX VrefLevel [Byte0]: 41
1071 12:42:21.201679 [Byte1]: 41
1072 12:42:21.205896
1073 12:42:21.206328 Set Vref, RX VrefLevel [Byte0]: 42
1074 12:42:21.208512 [Byte1]: 42
1075 12:42:21.212550
1076 12:42:21.212960 Set Vref, RX VrefLevel [Byte0]: 43
1077 12:42:21.216471 [Byte1]: 43
1078 12:42:21.220060
1079 12:42:21.220473 Set Vref, RX VrefLevel [Byte0]: 44
1080 12:42:21.223882 [Byte1]: 44
1081 12:42:21.227994
1082 12:42:21.228416 Set Vref, RX VrefLevel [Byte0]: 45
1083 12:42:21.231248 [Byte1]: 45
1084 12:42:21.235631
1085 12:42:21.236040 Set Vref, RX VrefLevel [Byte0]: 46
1086 12:42:21.239117 [Byte1]: 46
1087 12:42:21.243523
1088 12:42:21.243933 Set Vref, RX VrefLevel [Byte0]: 47
1089 12:42:21.246937 [Byte1]: 47
1090 12:42:21.250655
1091 12:42:21.251065 Set Vref, RX VrefLevel [Byte0]: 48
1092 12:42:21.253994 [Byte1]: 48
1093 12:42:21.258540
1094 12:42:21.259019 Set Vref, RX VrefLevel [Byte0]: 49
1095 12:42:21.261692 [Byte1]: 49
1096 12:42:21.265999
1097 12:42:21.266633 Set Vref, RX VrefLevel [Byte0]: 50
1098 12:42:21.269118 [Byte1]: 50
1099 12:42:21.273510
1100 12:42:21.273928 Set Vref, RX VrefLevel [Byte0]: 51
1101 12:42:21.276788 [Byte1]: 51
1102 12:42:21.281665
1103 12:42:21.282073 Set Vref, RX VrefLevel [Byte0]: 52
1104 12:42:21.284834 [Byte1]: 52
1105 12:42:21.288754
1106 12:42:21.292053 Set Vref, RX VrefLevel [Byte0]: 53
1107 12:42:21.292467 [Byte1]: 53
1108 12:42:21.296402
1109 12:42:21.296888 Set Vref, RX VrefLevel [Byte0]: 54
1110 12:42:21.299685 [Byte1]: 54
1111 12:42:21.303995
1112 12:42:21.304403 Set Vref, RX VrefLevel [Byte0]: 55
1113 12:42:21.307082 [Byte1]: 55
1114 12:42:21.311661
1115 12:42:21.312089 Set Vref, RX VrefLevel [Byte0]: 56
1116 12:42:21.315155 [Byte1]: 56
1117 12:42:21.318775
1118 12:42:21.319184 Set Vref, RX VrefLevel [Byte0]: 57
1119 12:42:21.322208 [Byte1]: 57
1120 12:42:21.326874
1121 12:42:21.327301 Set Vref, RX VrefLevel [Byte0]: 58
1122 12:42:21.330248 [Byte1]: 58
1123 12:42:21.333995
1124 12:42:21.334467 Set Vref, RX VrefLevel [Byte0]: 59
1125 12:42:21.337190 [Byte1]: 59
1126 12:42:21.342062
1127 12:42:21.342534 Set Vref, RX VrefLevel [Byte0]: 60
1128 12:42:21.345313 [Byte1]: 60
1129 12:42:21.349265
1130 12:42:21.349672 Set Vref, RX VrefLevel [Byte0]: 61
1131 12:42:21.353306 [Byte1]: 61
1132 12:42:21.356952
1133 12:42:21.357373 Set Vref, RX VrefLevel [Byte0]: 62
1134 12:42:21.360018 [Byte1]: 62
1135 12:42:21.364860
1136 12:42:21.365270 Set Vref, RX VrefLevel [Byte0]: 63
1137 12:42:21.368286 [Byte1]: 63
1138 12:42:21.372131
1139 12:42:21.372578 Set Vref, RX VrefLevel [Byte0]: 64
1140 12:42:21.375956 [Byte1]: 64
1141 12:42:21.379914
1142 12:42:21.380351 Set Vref, RX VrefLevel [Byte0]: 65
1143 12:42:21.382979 [Byte1]: 65
1144 12:42:21.386975
1145 12:42:21.387430 Set Vref, RX VrefLevel [Byte0]: 66
1146 12:42:21.390668 [Byte1]: 66
1147 12:42:21.394756
1148 12:42:21.395150 Set Vref, RX VrefLevel [Byte0]: 67
1149 12:42:21.397993 [Byte1]: 67
1150 12:42:21.402468
1151 12:42:21.402871 Set Vref, RX VrefLevel [Byte0]: 68
1152 12:42:21.405746 [Byte1]: 68
1153 12:42:21.409763
1154 12:42:21.410168 Set Vref, RX VrefLevel [Byte0]: 69
1155 12:42:21.413905 [Byte1]: 69
1156 12:42:21.418125
1157 12:42:21.418591 Set Vref, RX VrefLevel [Byte0]: 70
1158 12:42:21.421313 [Byte1]: 70
1159 12:42:21.425335
1160 12:42:21.425814 Set Vref, RX VrefLevel [Byte0]: 71
1161 12:42:21.428638 [Byte1]: 71
1162 12:42:21.433088
1163 12:42:21.433518 Set Vref, RX VrefLevel [Byte0]: 72
1164 12:42:21.436089 [Byte1]: 72
1165 12:42:21.440774
1166 12:42:21.441207 Set Vref, RX VrefLevel [Byte0]: 73
1167 12:42:21.443805 [Byte1]: 73
1168 12:42:21.448586
1169 12:42:21.449049 Set Vref, RX VrefLevel [Byte0]: 74
1170 12:42:21.451666 [Byte1]: 74
1171 12:42:21.456241
1172 12:42:21.456653 Set Vref, RX VrefLevel [Byte0]: 75
1173 12:42:21.459093 [Byte1]: 75
1174 12:42:21.463386
1175 12:42:21.463849 Set Vref, RX VrefLevel [Byte0]: 76
1176 12:42:21.466938 [Byte1]: 76
1177 12:42:21.470753
1178 12:42:21.470832 Set Vref, RX VrefLevel [Byte0]: 77
1179 12:42:21.473858 [Byte1]: 77
1180 12:42:21.478121
1181 12:42:21.478205 Set Vref, RX VrefLevel [Byte0]: 78
1182 12:42:21.481478 [Byte1]: 78
1183 12:42:21.485609
1184 12:42:21.485689 Final RX Vref Byte 0 = 61 to rank0
1185 12:42:21.488944 Final RX Vref Byte 1 = 58 to rank0
1186 12:42:21.492704 Final RX Vref Byte 0 = 61 to rank1
1187 12:42:21.496155 Final RX Vref Byte 1 = 58 to rank1==
1188 12:42:21.499446 Dram Type= 6, Freq= 0, CH_0, rank 0
1189 12:42:21.502803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1190 12:42:21.505965 ==
1191 12:42:21.506045 DQS Delay:
1192 12:42:21.506107 DQS0 = 0, DQS1 = 0
1193 12:42:21.509231 DQM Delay:
1194 12:42:21.509311 DQM0 = 88, DQM1 = 80
1195 12:42:21.512938 DQ Delay:
1196 12:42:21.513018 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1197 12:42:21.516178 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1198 12:42:21.519232 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =76
1199 12:42:21.522947 DQ12 =88, DQ13 =80, DQ14 =92, DQ15 =88
1200 12:42:21.523028
1201 12:42:21.523091
1202 12:42:21.533197 [DQSOSCAuto] RK0, (LSB)MR18= 0x250d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
1203 12:42:21.536485 CH0 RK0: MR19=606, MR18=250D
1204 12:42:21.539564 CH0_RK0: MR19=0x606, MR18=0x250D, DQSOSC=400, MR23=63, INC=92, DEC=61
1205 12:42:21.542563
1206 12:42:21.546252 ----->DramcWriteLeveling(PI) begin...
1207 12:42:21.546334 ==
1208 12:42:21.549327 Dram Type= 6, Freq= 0, CH_0, rank 1
1209 12:42:21.552849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1210 12:42:21.552930 ==
1211 12:42:21.556188 Write leveling (Byte 0): 31 => 31
1212 12:42:21.560385 Write leveling (Byte 1): 28 => 28
1213 12:42:21.563786 DramcWriteLeveling(PI) end<-----
1214 12:42:21.563887
1215 12:42:21.563984 ==
1216 12:42:21.566410 Dram Type= 6, Freq= 0, CH_0, rank 1
1217 12:42:21.569400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1218 12:42:21.569501 ==
1219 12:42:21.573227 [Gating] SW mode calibration
1220 12:42:21.615475 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1221 12:42:21.616280 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1222 12:42:21.616756 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1223 12:42:21.617234 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1224 12:42:21.617569 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1225 12:42:21.617924 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1226 12:42:21.618432 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 12:42:21.618792 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 12:42:21.619183 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 12:42:21.622104 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 12:42:21.625165 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 12:42:21.628654 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 12:42:21.632556 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 12:42:21.638511 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 12:42:21.642495 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 12:42:21.645705 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 12:42:21.651951 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 12:42:21.655615 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 12:42:21.658502 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 12:42:21.665293 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1240 12:42:21.668949 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1241 12:42:21.672486 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 12:42:21.678662 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 12:42:21.682739 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 12:42:21.685546 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 12:42:21.688626 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 12:42:21.695810 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 12:42:21.698812 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 12:42:21.702241 0 9 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
1249 12:42:21.709150 0 9 12 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
1250 12:42:21.712388 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 12:42:21.715621 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 12:42:21.722308 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 12:42:21.725976 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 12:42:21.728892 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1255 12:42:21.735550 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
1256 12:42:21.739741 0 10 8 | B1->B0 | 3030 2727 | 0 1 | (0 1) (1 0)
1257 12:42:21.742384 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1258 12:42:21.748670 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 12:42:21.752510 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 12:42:21.756295 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 12:42:21.759980 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 12:42:21.763546 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 12:42:21.770588 0 11 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
1264 12:42:21.774303 0 11 8 | B1->B0 | 2828 3d3d | 0 0 | (0 0) (0 0)
1265 12:42:21.777845 0 11 12 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1266 12:42:21.781690 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 12:42:21.788589 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 12:42:21.791141 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 12:42:21.795090 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 12:42:21.801604 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 12:42:21.804874 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1272 12:42:21.808252 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1273 12:42:21.812204 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1274 12:42:21.818644 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 12:42:21.821468 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 12:42:21.825278 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 12:42:21.832248 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 12:42:21.835498 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 12:42:21.838484 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 12:42:21.845238 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 12:42:21.848366 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 12:42:21.852135 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 12:42:21.858574 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 12:42:21.861859 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 12:42:21.865520 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 12:42:21.868445 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1287 12:42:21.875526 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1288 12:42:21.878661 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1289 12:42:21.882170 Total UI for P1: 0, mck2ui 16
1290 12:42:21.885536 best dqsien dly found for B0: ( 0, 14, 2)
1291 12:42:21.888575 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1292 12:42:21.892141 Total UI for P1: 0, mck2ui 16
1293 12:42:21.895881 best dqsien dly found for B1: ( 0, 14, 10)
1294 12:42:21.898672 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1295 12:42:21.902073 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1296 12:42:21.902153
1297 12:42:21.908652 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1298 12:42:21.912226 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1299 12:42:21.912307 [Gating] SW calibration Done
1300 12:42:21.915500 ==
1301 12:42:21.915581 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 12:42:21.922060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 12:42:21.922167 ==
1304 12:42:21.922259 RX Vref Scan: 0
1305 12:42:21.922346
1306 12:42:21.925528 RX Vref 0 -> 0, step: 1
1307 12:42:21.925608
1308 12:42:21.929114 RX Delay -130 -> 252, step: 16
1309 12:42:21.932152 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1310 12:42:21.936362 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1311 12:42:21.939450 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1312 12:42:21.945386 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1313 12:42:21.949073 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1314 12:42:21.952287 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1315 12:42:21.955813 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1316 12:42:21.959255 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1317 12:42:21.966056 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1318 12:42:21.968862 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1319 12:42:21.972173 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1320 12:42:21.976077 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1321 12:42:21.979128 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1322 12:42:21.985682 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1323 12:42:21.989030 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1324 12:42:21.992808 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1325 12:42:21.992889 ==
1326 12:42:21.995666 Dram Type= 6, Freq= 0, CH_0, rank 1
1327 12:42:21.999045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1328 12:42:21.999126 ==
1329 12:42:22.002551 DQS Delay:
1330 12:42:22.002630 DQS0 = 0, DQS1 = 0
1331 12:42:22.005847 DQM Delay:
1332 12:42:22.005927 DQM0 = 86, DQM1 = 75
1333 12:42:22.005990 DQ Delay:
1334 12:42:22.009142 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1335 12:42:22.012516 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
1336 12:42:22.015794 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1337 12:42:22.019109 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1338 12:42:22.019189
1339 12:42:22.019252
1340 12:42:22.019311 ==
1341 12:42:22.022331 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 12:42:22.029905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 12:42:22.029986 ==
1344 12:42:22.030050
1345 12:42:22.030108
1346 12:42:22.030164 TX Vref Scan disable
1347 12:42:22.033359 == TX Byte 0 ==
1348 12:42:22.036259 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1349 12:42:22.040217 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1350 12:42:22.043640 == TX Byte 1 ==
1351 12:42:22.046388 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1352 12:42:22.049829 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1353 12:42:22.053250 ==
1354 12:42:22.056492 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 12:42:22.060357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 12:42:22.060438 ==
1357 12:42:22.072850 TX Vref=22, minBit 3, minWin=27, winSum=445
1358 12:42:22.075745 TX Vref=24, minBit 12, minWin=27, winSum=450
1359 12:42:22.079260 TX Vref=26, minBit 3, minWin=27, winSum=450
1360 12:42:22.082218 TX Vref=28, minBit 8, minWin=27, winSum=453
1361 12:42:22.086099 TX Vref=30, minBit 5, minWin=28, winSum=459
1362 12:42:22.093231 TX Vref=32, minBit 13, minWin=27, winSum=456
1363 12:42:22.096209 [TxChooseVref] Worse bit 5, Min win 28, Win sum 459, Final Vref 30
1364 12:42:22.096283
1365 12:42:22.099607 Final TX Range 1 Vref 30
1366 12:42:22.099675
1367 12:42:22.099735 ==
1368 12:42:22.102552 Dram Type= 6, Freq= 0, CH_0, rank 1
1369 12:42:22.105915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1370 12:42:22.105989 ==
1371 12:42:22.106050
1372 12:42:22.109116
1373 12:42:22.109187 TX Vref Scan disable
1374 12:42:22.112736 == TX Byte 0 ==
1375 12:42:22.116002 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1376 12:42:22.122459 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1377 12:42:22.122536 == TX Byte 1 ==
1378 12:42:22.126525 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1379 12:42:22.129848 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1380 12:42:22.132959
1381 12:42:22.133038 [DATLAT]
1382 12:42:22.133100 Freq=800, CH0 RK1
1383 12:42:22.133159
1384 12:42:22.136178 DATLAT Default: 0xa
1385 12:42:22.136258 0, 0xFFFF, sum = 0
1386 12:42:22.139600 1, 0xFFFF, sum = 0
1387 12:42:22.139694 2, 0xFFFF, sum = 0
1388 12:42:22.142630 3, 0xFFFF, sum = 0
1389 12:42:22.142711 4, 0xFFFF, sum = 0
1390 12:42:22.146630 5, 0xFFFF, sum = 0
1391 12:42:22.146711 6, 0xFFFF, sum = 0
1392 12:42:22.149989 7, 0xFFFF, sum = 0
1393 12:42:22.150096 8, 0xFFFF, sum = 0
1394 12:42:22.153150 9, 0x0, sum = 1
1395 12:42:22.153230 10, 0x0, sum = 2
1396 12:42:22.156175 11, 0x0, sum = 3
1397 12:42:22.156255 12, 0x0, sum = 4
1398 12:42:22.159731 best_step = 10
1399 12:42:22.159810
1400 12:42:22.159872 ==
1401 12:42:22.162861 Dram Type= 6, Freq= 0, CH_0, rank 1
1402 12:42:22.166553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1403 12:42:22.166647 ==
1404 12:42:22.169818 RX Vref Scan: 0
1405 12:42:22.169897
1406 12:42:22.169959 RX Vref 0 -> 0, step: 1
1407 12:42:22.170017
1408 12:42:22.173594 RX Delay -111 -> 252, step: 8
1409 12:42:22.179942 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1410 12:42:22.183449 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1411 12:42:22.187080 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1412 12:42:22.190317 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1413 12:42:22.193411 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1414 12:42:22.196639 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1415 12:42:22.203712 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1416 12:42:22.206584 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1417 12:42:22.210008 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1418 12:42:22.213554 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1419 12:42:22.216994 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1420 12:42:22.223568 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1421 12:42:22.226910 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1422 12:42:22.230391 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1423 12:42:22.233576 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1424 12:42:22.237001 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1425 12:42:22.240154 ==
1426 12:42:22.240243 Dram Type= 6, Freq= 0, CH_0, rank 1
1427 12:42:22.247456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1428 12:42:22.247538 ==
1429 12:42:22.247610 DQS Delay:
1430 12:42:22.250281 DQS0 = 0, DQS1 = 0
1431 12:42:22.250353 DQM Delay:
1432 12:42:22.253769 DQM0 = 87, DQM1 = 78
1433 12:42:22.253846 DQ Delay:
1434 12:42:22.256968 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1435 12:42:22.260219 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1436 12:42:22.263798 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1437 12:42:22.267215 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1438 12:42:22.267313
1439 12:42:22.267388
1440 12:42:22.273783 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f19, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1441 12:42:22.277347 CH0 RK1: MR19=606, MR18=2F19
1442 12:42:22.283717 CH0_RK1: MR19=0x606, MR18=0x2F19, DQSOSC=397, MR23=63, INC=93, DEC=62
1443 12:42:22.287583 [RxdqsGatingPostProcess] freq 800
1444 12:42:22.290273 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1445 12:42:22.293677 Pre-setting of DQS Precalculation
1446 12:42:22.300469 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1447 12:42:22.300553 ==
1448 12:42:22.304522 Dram Type= 6, Freq= 0, CH_1, rank 0
1449 12:42:22.307327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1450 12:42:22.307406 ==
1451 12:42:22.313769 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1452 12:42:22.317523 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1453 12:42:22.328192 [CA 0] Center 36 (6~67) winsize 62
1454 12:42:22.331475 [CA 1] Center 36 (6~67) winsize 62
1455 12:42:22.334657 [CA 2] Center 34 (4~65) winsize 62
1456 12:42:22.337675 [CA 3] Center 33 (3~64) winsize 62
1457 12:42:22.341040 [CA 4] Center 34 (3~65) winsize 63
1458 12:42:22.344258 [CA 5] Center 33 (3~64) winsize 62
1459 12:42:22.344332
1460 12:42:22.347813 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1461 12:42:22.347887
1462 12:42:22.351259 [CATrainingPosCal] consider 1 rank data
1463 12:42:22.354464 u2DelayCellTimex100 = 270/100 ps
1464 12:42:22.358033 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1465 12:42:22.361026 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1466 12:42:22.364433 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1467 12:42:22.371362 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1468 12:42:22.374503 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1469 12:42:22.378307 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1470 12:42:22.378385
1471 12:42:22.381340 CA PerBit enable=1, Macro0, CA PI delay=33
1472 12:42:22.381416
1473 12:42:22.384888 [CBTSetCACLKResult] CA Dly = 33
1474 12:42:22.384960 CS Dly: 4 (0~35)
1475 12:42:22.385021 ==
1476 12:42:22.388100 Dram Type= 6, Freq= 0, CH_1, rank 1
1477 12:42:22.394780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1478 12:42:22.394856 ==
1479 12:42:22.399171 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1480 12:42:22.404720 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1481 12:42:22.413801 [CA 0] Center 36 (5~67) winsize 63
1482 12:42:22.417237 [CA 1] Center 36 (6~67) winsize 62
1483 12:42:22.420537 [CA 2] Center 33 (3~64) winsize 62
1484 12:42:22.425070 [CA 3] Center 33 (3~64) winsize 62
1485 12:42:22.429010 [CA 4] Center 34 (3~65) winsize 63
1486 12:42:22.432392 [CA 5] Center 33 (3~64) winsize 62
1487 12:42:22.432470
1488 12:42:22.436720 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1489 12:42:22.436803
1490 12:42:22.439659 [CATrainingPosCal] consider 2 rank data
1491 12:42:22.439739 u2DelayCellTimex100 = 270/100 ps
1492 12:42:22.443370 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1493 12:42:22.447602 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1494 12:42:22.451601 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1495 12:42:22.455000 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1496 12:42:22.457959 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
1497 12:42:22.461848 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1498 12:42:22.461933
1499 12:42:22.468311 CA PerBit enable=1, Macro0, CA PI delay=33
1500 12:42:22.468394
1501 12:42:22.468458 [CBTSetCACLKResult] CA Dly = 33
1502 12:42:22.471616 CS Dly: 5 (0~37)
1503 12:42:22.471712
1504 12:42:22.475928 ----->DramcWriteLeveling(PI) begin...
1505 12:42:22.475999 ==
1506 12:42:22.478418 Dram Type= 6, Freq= 0, CH_1, rank 0
1507 12:42:22.482166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1508 12:42:22.482271 ==
1509 12:42:22.485146 Write leveling (Byte 0): 29 => 29
1510 12:42:22.489019 Write leveling (Byte 1): 29 => 29
1511 12:42:22.491956 DramcWriteLeveling(PI) end<-----
1512 12:42:22.492036
1513 12:42:22.492102 ==
1514 12:42:22.495526 Dram Type= 6, Freq= 0, CH_1, rank 0
1515 12:42:22.498832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1516 12:42:22.501942 ==
1517 12:42:22.502021 [Gating] SW mode calibration
1518 12:42:22.508701 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1519 12:42:22.515191 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1520 12:42:22.518917 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1521 12:42:22.525396 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1522 12:42:22.529087 0 6 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1523 12:42:22.532573 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 12:42:22.535166 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 12:42:22.542106 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 12:42:22.545882 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 12:42:22.548859 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 12:42:22.555690 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 12:42:22.558726 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 12:42:22.562530 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 12:42:22.569139 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 12:42:22.572585 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1533 12:42:22.575895 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1534 12:42:22.582826 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 12:42:22.585881 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1536 12:42:22.589323 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 12:42:22.596041 0 8 4 | B1->B0 | 2424 2323 | 0 0 | (0 1) (0 1)
1538 12:42:22.599196 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1539 12:42:22.602809 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 12:42:22.606736 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 12:42:22.612267 0 8 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1542 12:42:22.615829 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 12:42:22.619126 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 12:42:22.626035 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 12:42:22.628988 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 12:42:22.632297 0 9 8 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
1547 12:42:22.639420 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1548 12:42:22.642614 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1549 12:42:22.646112 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1550 12:42:22.652715 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1551 12:42:22.656532 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 12:42:22.659573 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1553 12:42:22.665946 0 10 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1554 12:42:22.669546 0 10 8 | B1->B0 | 2c2c 2c2c | 0 0 | (0 0) (0 0)
1555 12:42:22.672969 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 12:42:22.675938 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 12:42:22.682886 0 10 20 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1558 12:42:22.686411 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 12:42:22.689821 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 12:42:22.695915 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1561 12:42:22.699378 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1562 12:42:22.703120 0 11 8 | B1->B0 | 3737 3939 | 1 0 | (0 0) (0 0)
1563 12:42:22.709305 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 12:42:22.712832 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 12:42:22.715927 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 12:42:22.723056 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 12:42:22.726106 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 12:42:22.729497 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 12:42:22.736727 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1570 12:42:22.739868 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 12:42:22.743004 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 12:42:22.749980 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 12:42:22.753439 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 12:42:22.757030 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 12:42:22.760802 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 12:42:22.766584 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 12:42:22.770119 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 12:42:22.773715 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 12:42:22.780110 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 12:42:22.783345 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 12:42:22.786953 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 12:42:22.793346 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 12:42:22.796780 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 12:42:22.799983 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 12:42:22.803466 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1586 12:42:22.810081 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1587 12:42:22.813330 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1588 12:42:22.816645 Total UI for P1: 0, mck2ui 16
1589 12:42:22.820311 best dqsien dly found for B0: ( 0, 14, 6)
1590 12:42:22.823820 Total UI for P1: 0, mck2ui 16
1591 12:42:22.826682 best dqsien dly found for B1: ( 0, 14, 6)
1592 12:42:22.830428 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1593 12:42:22.833486 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1594 12:42:22.833565
1595 12:42:22.837116 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1596 12:42:22.840405 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1597 12:42:22.843520 [Gating] SW calibration Done
1598 12:42:22.843599 ==
1599 12:42:22.846799 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 12:42:22.851082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 12:42:22.851162 ==
1602 12:42:22.854123 RX Vref Scan: 0
1603 12:42:22.854228
1604 12:42:22.857274 RX Vref 0 -> 0, step: 1
1605 12:42:22.857359
1606 12:42:22.860487 RX Delay -130 -> 252, step: 16
1607 12:42:22.863686 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1608 12:42:22.867330 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1609 12:42:22.870366 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1610 12:42:22.873927 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1611 12:42:22.877511 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1612 12:42:22.883824 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1613 12:42:22.887251 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1614 12:42:22.891361 iDelay=222, Bit 7, Center 69 (-50 ~ 189) 240
1615 12:42:22.894577 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1616 12:42:22.897349 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1617 12:42:22.904184 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1618 12:42:22.907410 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1619 12:42:22.911172 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1620 12:42:22.914355 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1621 12:42:22.917382 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1622 12:42:22.924280 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1623 12:42:22.924361 ==
1624 12:42:22.927510 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 12:42:22.930614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 12:42:22.930722 ==
1627 12:42:22.930814 DQS Delay:
1628 12:42:22.934416 DQS0 = 0, DQS1 = 0
1629 12:42:22.934536 DQM Delay:
1630 12:42:22.937663 DQM0 = 82, DQM1 = 74
1631 12:42:22.937784 DQ Delay:
1632 12:42:22.940601 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1633 12:42:22.944238 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =69
1634 12:42:22.947828 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1635 12:42:22.950850 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1636 12:42:22.950955
1637 12:42:22.951058
1638 12:42:22.951154 ==
1639 12:42:22.955069 Dram Type= 6, Freq= 0, CH_1, rank 0
1640 12:42:22.958061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1641 12:42:22.958142 ==
1642 12:42:22.958271
1643 12:42:22.958357
1644 12:42:22.961004 TX Vref Scan disable
1645 12:42:22.964698 == TX Byte 0 ==
1646 12:42:22.967948 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1647 12:42:22.971416 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1648 12:42:22.974495 == TX Byte 1 ==
1649 12:42:22.978219 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1650 12:42:22.981383 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1651 12:42:22.981479 ==
1652 12:42:22.985103 Dram Type= 6, Freq= 0, CH_1, rank 0
1653 12:42:22.987898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1654 12:42:22.991454 ==
1655 12:42:23.002574 TX Vref=22, minBit 11, minWin=26, winSum=437
1656 12:42:23.006677 TX Vref=24, minBit 8, minWin=26, winSum=438
1657 12:42:23.010533 TX Vref=26, minBit 0, minWin=27, winSum=443
1658 12:42:23.013291 TX Vref=28, minBit 10, minWin=27, winSum=452
1659 12:42:23.016537 TX Vref=30, minBit 10, minWin=27, winSum=452
1660 12:42:23.019819 TX Vref=32, minBit 0, minWin=28, winSum=453
1661 12:42:23.026701 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 32
1662 12:42:23.026801
1663 12:42:23.029743 Final TX Range 1 Vref 32
1664 12:42:23.029811
1665 12:42:23.029871 ==
1666 12:42:23.033143 Dram Type= 6, Freq= 0, CH_1, rank 0
1667 12:42:23.036707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1668 12:42:23.036783 ==
1669 12:42:23.036843
1670 12:42:23.036899
1671 12:42:23.040382 TX Vref Scan disable
1672 12:42:23.044091 == TX Byte 0 ==
1673 12:42:23.046746 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1674 12:42:23.049900 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1675 12:42:23.053366 == TX Byte 1 ==
1676 12:42:23.057058 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1677 12:42:23.060179 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1678 12:42:23.060283
1679 12:42:23.063189 [DATLAT]
1680 12:42:23.063288 Freq=800, CH1 RK0
1681 12:42:23.063377
1682 12:42:23.066860 DATLAT Default: 0xa
1683 12:42:23.066959 0, 0xFFFF, sum = 0
1684 12:42:23.070127 1, 0xFFFF, sum = 0
1685 12:42:23.070226 2, 0xFFFF, sum = 0
1686 12:42:23.073308 3, 0xFFFF, sum = 0
1687 12:42:23.073408 4, 0xFFFF, sum = 0
1688 12:42:23.076772 5, 0xFFFF, sum = 0
1689 12:42:23.076883 6, 0xFFFF, sum = 0
1690 12:42:23.080400 7, 0xFFFF, sum = 0
1691 12:42:23.080507 8, 0xFFFF, sum = 0
1692 12:42:23.083473 9, 0x0, sum = 1
1693 12:42:23.083556 10, 0x0, sum = 2
1694 12:42:23.086867 11, 0x0, sum = 3
1695 12:42:23.087009 12, 0x0, sum = 4
1696 12:42:23.087136 best_step = 10
1697 12:42:23.087257
1698 12:42:23.090562 ==
1699 12:42:23.093658 Dram Type= 6, Freq= 0, CH_1, rank 0
1700 12:42:23.097121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1701 12:42:23.097222 ==
1702 12:42:23.097312 RX Vref Scan: 1
1703 12:42:23.097398
1704 12:42:23.100648 Set Vref Range= 32 -> 127
1705 12:42:23.100746
1706 12:42:23.103744 RX Vref 32 -> 127, step: 1
1707 12:42:23.103871
1708 12:42:23.107325 RX Delay -111 -> 252, step: 8
1709 12:42:23.107452
1710 12:42:23.110292 Set Vref, RX VrefLevel [Byte0]: 32
1711 12:42:23.114013 [Byte1]: 32
1712 12:42:23.114117
1713 12:42:23.117289 Set Vref, RX VrefLevel [Byte0]: 33
1714 12:42:23.120245 [Byte1]: 33
1715 12:42:23.120367
1716 12:42:23.123420 Set Vref, RX VrefLevel [Byte0]: 34
1717 12:42:23.126990 [Byte1]: 34
1718 12:42:23.130730
1719 12:42:23.130832 Set Vref, RX VrefLevel [Byte0]: 35
1720 12:42:23.134090 [Byte1]: 35
1721 12:42:23.138735
1722 12:42:23.138848 Set Vref, RX VrefLevel [Byte0]: 36
1723 12:42:23.142316 [Byte1]: 36
1724 12:42:23.145971
1725 12:42:23.146070 Set Vref, RX VrefLevel [Byte0]: 37
1726 12:42:23.149153 [Byte1]: 37
1727 12:42:23.153510
1728 12:42:23.153599 Set Vref, RX VrefLevel [Byte0]: 38
1729 12:42:23.156991 [Byte1]: 38
1730 12:42:23.161436
1731 12:42:23.161597 Set Vref, RX VrefLevel [Byte0]: 39
1732 12:42:23.165092 [Byte1]: 39
1733 12:42:23.168691
1734 12:42:23.168825 Set Vref, RX VrefLevel [Byte0]: 40
1735 12:42:23.175746 [Byte1]: 40
1736 12:42:23.175886
1737 12:42:23.179243 Set Vref, RX VrefLevel [Byte0]: 41
1738 12:42:23.182026 [Byte1]: 41
1739 12:42:23.182125
1740 12:42:23.185514 Set Vref, RX VrefLevel [Byte0]: 42
1741 12:42:23.188772 [Byte1]: 42
1742 12:42:23.188905
1743 12:42:23.192045 Set Vref, RX VrefLevel [Byte0]: 43
1744 12:42:23.195708 [Byte1]: 43
1745 12:42:23.199548
1746 12:42:23.199694 Set Vref, RX VrefLevel [Byte0]: 44
1747 12:42:23.202764 [Byte1]: 44
1748 12:42:23.207079
1749 12:42:23.207168 Set Vref, RX VrefLevel [Byte0]: 45
1750 12:42:23.210213 [Byte1]: 45
1751 12:42:23.214760
1752 12:42:23.214842 Set Vref, RX VrefLevel [Byte0]: 46
1753 12:42:23.217766 [Byte1]: 46
1754 12:42:23.222191
1755 12:42:23.222287 Set Vref, RX VrefLevel [Byte0]: 47
1756 12:42:23.225542 [Byte1]: 47
1757 12:42:23.230499
1758 12:42:23.230582 Set Vref, RX VrefLevel [Byte0]: 48
1759 12:42:23.233666 [Byte1]: 48
1760 12:42:23.238176
1761 12:42:23.238258 Set Vref, RX VrefLevel [Byte0]: 49
1762 12:42:23.241488 [Byte1]: 49
1763 12:42:23.245415
1764 12:42:23.245514 Set Vref, RX VrefLevel [Byte0]: 50
1765 12:42:23.248605 [Byte1]: 50
1766 12:42:23.253197
1767 12:42:23.253280 Set Vref, RX VrefLevel [Byte0]: 51
1768 12:42:23.256048 [Byte1]: 51
1769 12:42:23.260665
1770 12:42:23.260743 Set Vref, RX VrefLevel [Byte0]: 52
1771 12:42:23.264031 [Byte1]: 52
1772 12:42:23.268212
1773 12:42:23.268287 Set Vref, RX VrefLevel [Byte0]: 53
1774 12:42:23.271691 [Byte1]: 53
1775 12:42:23.275623
1776 12:42:23.275706 Set Vref, RX VrefLevel [Byte0]: 54
1777 12:42:23.279231 [Byte1]: 54
1778 12:42:23.283899
1779 12:42:23.283982 Set Vref, RX VrefLevel [Byte0]: 55
1780 12:42:23.286782 [Byte1]: 55
1781 12:42:23.291288
1782 12:42:23.291370 Set Vref, RX VrefLevel [Byte0]: 56
1783 12:42:23.294693 [Byte1]: 56
1784 12:42:23.299179
1785 12:42:23.299265 Set Vref, RX VrefLevel [Byte0]: 57
1786 12:42:23.302505 [Byte1]: 57
1787 12:42:23.306773
1788 12:42:23.306855 Set Vref, RX VrefLevel [Byte0]: 58
1789 12:42:23.309856 [Byte1]: 58
1790 12:42:23.314316
1791 12:42:23.314429 Set Vref, RX VrefLevel [Byte0]: 59
1792 12:42:23.318306 [Byte1]: 59
1793 12:42:23.321635
1794 12:42:23.321744 Set Vref, RX VrefLevel [Byte0]: 60
1795 12:42:23.325387 [Byte1]: 60
1796 12:42:23.329141
1797 12:42:23.329246 Set Vref, RX VrefLevel [Byte0]: 61
1798 12:42:23.333042 [Byte1]: 61
1799 12:42:23.337001
1800 12:42:23.337107 Set Vref, RX VrefLevel [Byte0]: 62
1801 12:42:23.340555 [Byte1]: 62
1802 12:42:23.344932
1803 12:42:23.345006 Set Vref, RX VrefLevel [Byte0]: 63
1804 12:42:23.348237 [Byte1]: 63
1805 12:42:23.352763
1806 12:42:23.352836 Set Vref, RX VrefLevel [Byte0]: 64
1807 12:42:23.356358 [Byte1]: 64
1808 12:42:23.360167
1809 12:42:23.360264 Set Vref, RX VrefLevel [Byte0]: 65
1810 12:42:23.363653 [Byte1]: 65
1811 12:42:23.367598
1812 12:42:23.367695 Set Vref, RX VrefLevel [Byte0]: 66
1813 12:42:23.371431 [Byte1]: 66
1814 12:42:23.375248
1815 12:42:23.375353 Set Vref, RX VrefLevel [Byte0]: 67
1816 12:42:23.378680 [Byte1]: 67
1817 12:42:23.382788
1818 12:42:23.382858 Set Vref, RX VrefLevel [Byte0]: 68
1819 12:42:23.386517 [Byte1]: 68
1820 12:42:23.390497
1821 12:42:23.390571 Set Vref, RX VrefLevel [Byte0]: 69
1822 12:42:23.393722 [Byte1]: 69
1823 12:42:23.398313
1824 12:42:23.398423 Set Vref, RX VrefLevel [Byte0]: 70
1825 12:42:23.401571 [Byte1]: 70
1826 12:42:23.406143
1827 12:42:23.406250 Set Vref, RX VrefLevel [Byte0]: 71
1828 12:42:23.409200 [Byte1]: 71
1829 12:42:23.413631
1830 12:42:23.413737 Set Vref, RX VrefLevel [Byte0]: 72
1831 12:42:23.417560 [Byte1]: 72
1832 12:42:23.421499
1833 12:42:23.421602 Set Vref, RX VrefLevel [Byte0]: 73
1834 12:42:23.424354 [Byte1]: 73
1835 12:42:23.428998
1836 12:42:23.429070 Set Vref, RX VrefLevel [Byte0]: 74
1837 12:42:23.432302 [Byte1]: 74
1838 12:42:23.436053
1839 12:42:23.440175 Set Vref, RX VrefLevel [Byte0]: 75
1840 12:42:23.443788 [Byte1]: 75
1841 12:42:23.443890
1842 12:42:23.446216 Set Vref, RX VrefLevel [Byte0]: 76
1843 12:42:23.449758 [Byte1]: 76
1844 12:42:23.449862
1845 12:42:23.453219 Set Vref, RX VrefLevel [Byte0]: 77
1846 12:42:23.456536 [Byte1]: 77
1847 12:42:23.456643
1848 12:42:23.460318 Final RX Vref Byte 0 = 64 to rank0
1849 12:42:23.463556 Final RX Vref Byte 1 = 56 to rank0
1850 12:42:23.466345 Final RX Vref Byte 0 = 64 to rank1
1851 12:42:23.469920 Final RX Vref Byte 1 = 56 to rank1==
1852 12:42:23.473346 Dram Type= 6, Freq= 0, CH_1, rank 0
1853 12:42:23.476378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1854 12:42:23.479799 ==
1855 12:42:23.479872 DQS Delay:
1856 12:42:23.479934 DQS0 = 0, DQS1 = 0
1857 12:42:23.483421 DQM Delay:
1858 12:42:23.483491 DQM0 = 82, DQM1 = 73
1859 12:42:23.483551 DQ Delay:
1860 12:42:23.486578 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =84
1861 12:42:23.490263 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1862 12:42:23.493457 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1863 12:42:23.496723 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =76
1864 12:42:23.496803
1865 12:42:23.496867
1866 12:42:23.506859 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b00, (MSB)MR19= 0x606, tDQSOscB0 = 410 ps tDQSOscB1 = 398 ps
1867 12:42:23.510627 CH1 RK0: MR19=606, MR18=2B00
1868 12:42:23.513427 CH1_RK0: MR19=0x606, MR18=0x2B00, DQSOSC=398, MR23=63, INC=93, DEC=62
1869 12:42:23.516764
1870 12:42:23.520238 ----->DramcWriteLeveling(PI) begin...
1871 12:42:23.520321 ==
1872 12:42:23.523459 Dram Type= 6, Freq= 0, CH_1, rank 1
1873 12:42:23.526882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1874 12:42:23.526964 ==
1875 12:42:23.529966 Write leveling (Byte 0): 30 => 30
1876 12:42:23.533651 Write leveling (Byte 1): 30 => 30
1877 12:42:23.537242 DramcWriteLeveling(PI) end<-----
1878 12:42:23.537323
1879 12:42:23.537385 ==
1880 12:42:23.540339 Dram Type= 6, Freq= 0, CH_1, rank 1
1881 12:42:23.543751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1882 12:42:23.543839 ==
1883 12:42:23.546983 [Gating] SW mode calibration
1884 12:42:23.554132 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1885 12:42:23.556981 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1886 12:42:23.563453 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1887 12:42:23.566664 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1888 12:42:23.570893 0 6 8 | B1->B0 | 2323 2323 | 1 0 | (1 0) (0 0)
1889 12:42:23.576651 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 12:42:23.580521 0 6 16 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1891 12:42:23.583663 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 12:42:23.590750 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 12:42:23.594042 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 12:42:23.597522 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 12:42:23.603764 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 12:42:23.607238 0 7 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1897 12:42:23.610895 0 7 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1898 12:42:23.617346 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1899 12:42:23.620681 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1900 12:42:23.624148 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 12:42:23.627252 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 12:42:23.633943 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1903 12:42:23.636877 0 8 4 | B1->B0 | 2423 2323 | 1 0 | (1 1) (0 0)
1904 12:42:23.640390 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 12:42:23.646868 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 12:42:23.650416 0 8 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1907 12:42:23.653899 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 12:42:23.660710 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 12:42:23.663730 0 8 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1910 12:42:23.667161 0 9 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1911 12:42:23.674304 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 12:42:23.677804 0 9 8 | B1->B0 | 3030 3434 | 1 0 | (1 1) (0 0)
1913 12:42:23.680631 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 12:42:23.687406 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1915 12:42:23.690860 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1916 12:42:23.693958 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1917 12:42:23.700861 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1918 12:42:23.704086 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1919 12:42:23.707682 0 10 4 | B1->B0 | 3232 2c2c | 0 0 | (0 1) (0 1)
1920 12:42:23.710888 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1921 12:42:23.717310 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 12:42:23.720809 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 12:42:23.724064 0 10 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1924 12:42:23.730578 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 12:42:23.734365 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1926 12:42:23.738333 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1927 12:42:23.744282 0 11 4 | B1->B0 | 2b2b 3939 | 1 0 | (1 1) (0 0)
1928 12:42:23.747671 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1929 12:42:23.751286 0 11 12 | B1->B0 | 4645 4646 | 1 0 | (0 0) (0 0)
1930 12:42:23.757823 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 12:42:23.761622 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 12:42:23.765058 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 12:42:23.770878 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1934 12:42:23.774114 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1935 12:42:23.777514 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1936 12:42:23.781138 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 12:42:23.787564 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 12:42:23.791320 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 12:42:23.795038 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 12:42:23.800911 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 12:42:23.804265 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 12:42:23.808305 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 12:42:23.814134 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 12:42:23.817753 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 12:42:23.821481 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 12:42:23.827630 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 12:42:23.831020 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 12:42:23.834311 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 12:42:23.841472 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 12:42:23.844417 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 12:42:23.847676 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1952 12:42:23.854967 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1953 12:42:23.855068 Total UI for P1: 0, mck2ui 16
1954 12:42:23.857522 best dqsien dly found for B0: ( 0, 14, 4)
1955 12:42:23.861086 Total UI for P1: 0, mck2ui 16
1956 12:42:23.864459 best dqsien dly found for B1: ( 0, 14, 6)
1957 12:42:23.867901 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1958 12:42:23.871464 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1959 12:42:23.871536
1960 12:42:23.878227 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1961 12:42:23.881707 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1962 12:42:23.881797 [Gating] SW calibration Done
1963 12:42:23.885174 ==
1964 12:42:23.885275 Dram Type= 6, Freq= 0, CH_1, rank 1
1965 12:42:23.891928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1966 12:42:23.892038 ==
1967 12:42:23.892163 RX Vref Scan: 0
1968 12:42:23.892249
1969 12:42:23.895347 RX Vref 0 -> 0, step: 1
1970 12:42:23.895415
1971 12:42:23.898552 RX Delay -130 -> 252, step: 16
1972 12:42:23.901711 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1973 12:42:23.904875 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1974 12:42:23.908796 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1975 12:42:23.915014 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1976 12:42:23.918610 iDelay=206, Bit 4, Center 77 (-34 ~ 189) 224
1977 12:42:23.921907 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1978 12:42:23.925486 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1979 12:42:23.928420 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1980 12:42:23.935501 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1981 12:42:23.938530 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1982 12:42:23.941913 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1983 12:42:23.945305 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1984 12:42:23.948146 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1985 12:42:23.955243 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1986 12:42:23.958859 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1987 12:42:23.962142 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1988 12:42:23.962244 ==
1989 12:42:23.965127 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 12:42:23.968529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 12:42:23.968654 ==
1992 12:42:23.972333 DQS Delay:
1993 12:42:23.972450 DQS0 = 0, DQS1 = 0
1994 12:42:23.975458 DQM Delay:
1995 12:42:23.975528 DQM0 = 78, DQM1 = 78
1996 12:42:23.975589 DQ Delay:
1997 12:42:23.978307 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1998 12:42:23.981757 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =69
1999 12:42:23.985223 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
2000 12:42:23.988304 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2001 12:42:23.988405
2002 12:42:23.988481
2003 12:42:23.988580 ==
2004 12:42:23.992215 Dram Type= 6, Freq= 0, CH_1, rank 1
2005 12:42:23.998376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2006 12:42:23.998493 ==
2007 12:42:23.998555
2008 12:42:23.998613
2009 12:42:23.998668 TX Vref Scan disable
2010 12:42:24.001935 == TX Byte 0 ==
2011 12:42:24.006011 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2012 12:42:24.008898 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2013 12:42:24.012360 == TX Byte 1 ==
2014 12:42:24.015853 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2015 12:42:24.019227 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2016 12:42:24.022212 ==
2017 12:42:24.025243 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 12:42:24.028870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 12:42:24.028979 ==
2020 12:42:24.040844 TX Vref=22, minBit 1, minWin=27, winSum=442
2021 12:42:24.044810 TX Vref=24, minBit 0, minWin=27, winSum=446
2022 12:42:24.047872 TX Vref=26, minBit 15, minWin=27, winSum=451
2023 12:42:24.051963 TX Vref=28, minBit 15, minWin=27, winSum=452
2024 12:42:24.054468 TX Vref=30, minBit 1, minWin=28, winSum=455
2025 12:42:24.057822 TX Vref=32, minBit 3, minWin=28, winSum=455
2026 12:42:24.064956 [TxChooseVref] Worse bit 1, Min win 28, Win sum 455, Final Vref 30
2027 12:42:24.065058
2028 12:42:24.067828 Final TX Range 1 Vref 30
2029 12:42:24.067911
2030 12:42:24.067979 ==
2031 12:42:24.071507 Dram Type= 6, Freq= 0, CH_1, rank 1
2032 12:42:24.074863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2033 12:42:24.074969 ==
2034 12:42:24.075060
2035 12:42:24.075146
2036 12:42:24.077971 TX Vref Scan disable
2037 12:42:24.081783 == TX Byte 0 ==
2038 12:42:24.084667 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2039 12:42:24.088307 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2040 12:42:24.091426 == TX Byte 1 ==
2041 12:42:24.094832 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2042 12:42:24.098469 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2043 12:42:24.098564
2044 12:42:24.101314 [DATLAT]
2045 12:42:24.101389 Freq=800, CH1 RK1
2046 12:42:24.101450
2047 12:42:24.105781 DATLAT Default: 0xa
2048 12:42:24.105853 0, 0xFFFF, sum = 0
2049 12:42:24.108872 1, 0xFFFF, sum = 0
2050 12:42:24.108976 2, 0xFFFF, sum = 0
2051 12:42:24.111771 3, 0xFFFF, sum = 0
2052 12:42:24.111870 4, 0xFFFF, sum = 0
2053 12:42:24.114788 5, 0xFFFF, sum = 0
2054 12:42:24.114890 6, 0xFFFF, sum = 0
2055 12:42:24.118656 7, 0xFFFF, sum = 0
2056 12:42:24.118755 8, 0xFFFF, sum = 0
2057 12:42:24.121380 9, 0x0, sum = 1
2058 12:42:24.121484 10, 0x0, sum = 2
2059 12:42:24.124999 11, 0x0, sum = 3
2060 12:42:24.125112 12, 0x0, sum = 4
2061 12:42:24.128159 best_step = 10
2062 12:42:24.128257
2063 12:42:24.128349 ==
2064 12:42:24.132078 Dram Type= 6, Freq= 0, CH_1, rank 1
2065 12:42:24.135736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2066 12:42:24.135861 ==
2067 12:42:24.135961 RX Vref Scan: 0
2068 12:42:24.138331
2069 12:42:24.138456 RX Vref 0 -> 0, step: 1
2070 12:42:24.138550
2071 12:42:24.141864 RX Delay -95 -> 252, step: 8
2072 12:42:24.145173 iDelay=201, Bit 0, Center 84 (-31 ~ 200) 232
2073 12:42:24.152060 iDelay=201, Bit 1, Center 76 (-39 ~ 192) 232
2074 12:42:24.155135 iDelay=201, Bit 2, Center 68 (-47 ~ 184) 232
2075 12:42:24.158261 iDelay=201, Bit 3, Center 80 (-31 ~ 192) 224
2076 12:42:24.161892 iDelay=201, Bit 4, Center 80 (-31 ~ 192) 224
2077 12:42:24.165583 iDelay=201, Bit 5, Center 88 (-23 ~ 200) 224
2078 12:42:24.172185 iDelay=201, Bit 6, Center 88 (-23 ~ 200) 224
2079 12:42:24.175246 iDelay=201, Bit 7, Center 80 (-31 ~ 192) 224
2080 12:42:24.178591 iDelay=201, Bit 8, Center 64 (-55 ~ 184) 240
2081 12:42:24.181908 iDelay=201, Bit 9, Center 64 (-47 ~ 176) 224
2082 12:42:24.185113 iDelay=201, Bit 10, Center 72 (-47 ~ 192) 240
2083 12:42:24.189153 iDelay=201, Bit 11, Center 68 (-47 ~ 184) 232
2084 12:42:24.195523 iDelay=201, Bit 12, Center 80 (-31 ~ 192) 224
2085 12:42:24.199408 iDelay=201, Bit 13, Center 84 (-31 ~ 200) 232
2086 12:42:24.202110 iDelay=201, Bit 14, Center 80 (-39 ~ 200) 240
2087 12:42:24.205634 iDelay=201, Bit 15, Center 84 (-31 ~ 200) 232
2088 12:42:24.205716 ==
2089 12:42:24.208806 Dram Type= 6, Freq= 0, CH_1, rank 1
2090 12:42:24.215963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2091 12:42:24.216045 ==
2092 12:42:24.216111 DQS Delay:
2093 12:42:24.219327 DQS0 = 0, DQS1 = 0
2094 12:42:24.219406 DQM Delay:
2095 12:42:24.219469 DQM0 = 80, DQM1 = 74
2096 12:42:24.222870 DQ Delay:
2097 12:42:24.226269 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =80
2098 12:42:24.228685 DQ4 =80, DQ5 =88, DQ6 =88, DQ7 =80
2099 12:42:24.232193 DQ8 =64, DQ9 =64, DQ10 =72, DQ11 =68
2100 12:42:24.235446 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =84
2101 12:42:24.235551
2102 12:42:24.235641
2103 12:42:24.242610 [DQSOSCAuto] RK1, (LSB)MR18= 0x222d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2104 12:42:24.245374 CH1 RK1: MR19=606, MR18=222D
2105 12:42:24.252513 CH1_RK1: MR19=0x606, MR18=0x222D, DQSOSC=398, MR23=63, INC=93, DEC=62
2106 12:42:24.255318 [RxdqsGatingPostProcess] freq 800
2107 12:42:24.259203 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2108 12:42:24.262874 Pre-setting of DQS Precalculation
2109 12:42:24.269185 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2110 12:42:24.275715 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2111 12:42:24.282527 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2112 12:42:24.282607
2113 12:42:24.282670
2114 12:42:24.285828 [Calibration Summary] 1600 Mbps
2115 12:42:24.285933 CH 0, Rank 0
2116 12:42:24.289504 SW Impedance : PASS
2117 12:42:24.293098 DUTY Scan : NO K
2118 12:42:24.293177 ZQ Calibration : PASS
2119 12:42:24.295880 Jitter Meter : NO K
2120 12:42:24.295985 CBT Training : PASS
2121 12:42:24.299243 Write leveling : PASS
2122 12:42:24.302610 RX DQS gating : PASS
2123 12:42:24.302719 RX DQ/DQS(RDDQC) : PASS
2124 12:42:24.306040 TX DQ/DQS : PASS
2125 12:42:24.309792 RX DATLAT : PASS
2126 12:42:24.309872 RX DQ/DQS(Engine): PASS
2127 12:42:24.312335 TX OE : NO K
2128 12:42:24.312441 All Pass.
2129 12:42:24.312564
2130 12:42:24.316171 CH 0, Rank 1
2131 12:42:24.316303 SW Impedance : PASS
2132 12:42:24.319526 DUTY Scan : NO K
2133 12:42:24.323097 ZQ Calibration : PASS
2134 12:42:24.323176 Jitter Meter : NO K
2135 12:42:24.326132 CBT Training : PASS
2136 12:42:24.329478 Write leveling : PASS
2137 12:42:24.329583 RX DQS gating : PASS
2138 12:42:24.333148 RX DQ/DQS(RDDQC) : PASS
2139 12:42:24.333256 TX DQ/DQS : PASS
2140 12:42:24.335932 RX DATLAT : PASS
2141 12:42:24.339101 RX DQ/DQS(Engine): PASS
2142 12:42:24.339195 TX OE : NO K
2143 12:42:24.342687 All Pass.
2144 12:42:24.342798
2145 12:42:24.342916 CH 1, Rank 0
2146 12:42:24.345933 SW Impedance : PASS
2147 12:42:24.346028 DUTY Scan : NO K
2148 12:42:24.349378 ZQ Calibration : PASS
2149 12:42:24.352627 Jitter Meter : NO K
2150 12:42:24.352707 CBT Training : PASS
2151 12:42:24.356299 Write leveling : PASS
2152 12:42:24.359264 RX DQS gating : PASS
2153 12:42:24.359362 RX DQ/DQS(RDDQC) : PASS
2154 12:42:24.362582 TX DQ/DQS : PASS
2155 12:42:24.365924 RX DATLAT : PASS
2156 12:42:24.366034 RX DQ/DQS(Engine): PASS
2157 12:42:24.369238 TX OE : NO K
2158 12:42:24.369318 All Pass.
2159 12:42:24.369381
2160 12:42:24.372977 CH 1, Rank 1
2161 12:42:24.373063 SW Impedance : PASS
2162 12:42:24.376180 DUTY Scan : NO K
2163 12:42:24.376336 ZQ Calibration : PASS
2164 12:42:24.379531 Jitter Meter : NO K
2165 12:42:24.382616 CBT Training : PASS
2166 12:42:24.382690 Write leveling : PASS
2167 12:42:24.386804 RX DQS gating : PASS
2168 12:42:24.389779 RX DQ/DQS(RDDQC) : PASS
2169 12:42:24.389858 TX DQ/DQS : PASS
2170 12:42:24.392795 RX DATLAT : PASS
2171 12:42:24.396422 RX DQ/DQS(Engine): PASS
2172 12:42:24.396548 TX OE : NO K
2173 12:42:24.396668 All Pass.
2174 12:42:24.399867
2175 12:42:24.399946 DramC Write-DBI off
2176 12:42:24.403176 PER_BANK_REFRESH: Hybrid Mode
2177 12:42:24.403256 TX_TRACKING: ON
2178 12:42:24.407227 [GetDramInforAfterCalByMRR] Vendor 6.
2179 12:42:24.409934 [GetDramInforAfterCalByMRR] Revision 606.
2180 12:42:24.416550 [GetDramInforAfterCalByMRR] Revision 2 0.
2181 12:42:24.416630 MR0 0x3b3b
2182 12:42:24.416697 MR8 0x5151
2183 12:42:24.420154 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2184 12:42:24.420234
2185 12:42:24.423458 MR0 0x3b3b
2186 12:42:24.423537 MR8 0x5151
2187 12:42:24.426324 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2188 12:42:24.426466
2189 12:42:24.436795 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2190 12:42:24.439862 [FAST_K] Save calibration result to emmc
2191 12:42:24.443506 [FAST_K] Save calibration result to emmc
2192 12:42:24.447023 dram_init: config_dvfs: 1
2193 12:42:24.450920 dramc_set_vcore_voltage set vcore to 662500
2194 12:42:24.451026 Read voltage for 1200, 2
2195 12:42:24.453674 Vio18 = 0
2196 12:42:24.453758 Vcore = 662500
2197 12:42:24.453852 Vdram = 0
2198 12:42:24.457273 Vddq = 0
2199 12:42:24.457353 Vmddr = 0
2200 12:42:24.460357 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2201 12:42:24.467082 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2202 12:42:24.470607 MEM_TYPE=3, freq_sel=15
2203 12:42:24.470694 sv_algorithm_assistance_LP4_1600
2204 12:42:24.476892 ============ PULL DRAM RESETB DOWN ============
2205 12:42:24.480227 ========== PULL DRAM RESETB DOWN end =========
2206 12:42:24.484441 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2207 12:42:24.487342 ===================================
2208 12:42:24.490825 LPDDR4 DRAM CONFIGURATION
2209 12:42:24.493711 ===================================
2210 12:42:24.497302 EX_ROW_EN[0] = 0x0
2211 12:42:24.497381 EX_ROW_EN[1] = 0x0
2212 12:42:24.500699 LP4Y_EN = 0x0
2213 12:42:24.500778 WORK_FSP = 0x0
2214 12:42:24.503807 WL = 0x4
2215 12:42:24.503892 RL = 0x4
2216 12:42:24.507151 BL = 0x2
2217 12:42:24.507231 RPST = 0x0
2218 12:42:24.510662 RD_PRE = 0x0
2219 12:42:24.510740 WR_PRE = 0x1
2220 12:42:24.514174 WR_PST = 0x0
2221 12:42:24.514253 DBI_WR = 0x0
2222 12:42:24.517368 DBI_RD = 0x0
2223 12:42:24.517447 OTF = 0x1
2224 12:42:24.520867 ===================================
2225 12:42:24.524712 ===================================
2226 12:42:24.527835 ANA top config
2227 12:42:24.531493 ===================================
2228 12:42:24.531577 DLL_ASYNC_EN = 0
2229 12:42:24.534132 ALL_SLAVE_EN = 0
2230 12:42:24.537669 NEW_RANK_MODE = 1
2231 12:42:24.540859 DLL_IDLE_MODE = 1
2232 12:42:24.540940 LP45_APHY_COMB_EN = 1
2233 12:42:24.544349 TX_ODT_DIS = 1
2234 12:42:24.547721 NEW_8X_MODE = 1
2235 12:42:24.550830 ===================================
2236 12:42:24.554321 ===================================
2237 12:42:24.557422 data_rate = 2400
2238 12:42:24.561068 CKR = 1
2239 12:42:24.564314 DQ_P2S_RATIO = 8
2240 12:42:24.567582 ===================================
2241 12:42:24.567661 CA_P2S_RATIO = 8
2242 12:42:24.571029 DQ_CA_OPEN = 0
2243 12:42:24.574527 DQ_SEMI_OPEN = 0
2244 12:42:24.578111 CA_SEMI_OPEN = 0
2245 12:42:24.581238 CA_FULL_RATE = 0
2246 12:42:24.581318 DQ_CKDIV4_EN = 0
2247 12:42:24.584414 CA_CKDIV4_EN = 0
2248 12:42:24.587963 CA_PREDIV_EN = 0
2249 12:42:24.591089 PH8_DLY = 17
2250 12:42:24.594571 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2251 12:42:24.597655 DQ_AAMCK_DIV = 4
2252 12:42:24.597734 CA_AAMCK_DIV = 4
2253 12:42:24.601290 CA_ADMCK_DIV = 4
2254 12:42:24.604629 DQ_TRACK_CA_EN = 0
2255 12:42:24.607861 CA_PICK = 1200
2256 12:42:24.611322 CA_MCKIO = 1200
2257 12:42:24.614813 MCKIO_SEMI = 0
2258 12:42:24.618199 PLL_FREQ = 2366
2259 12:42:24.618282 DQ_UI_PI_RATIO = 32
2260 12:42:24.621346 CA_UI_PI_RATIO = 0
2261 12:42:24.624705 ===================================
2262 12:42:24.628195 ===================================
2263 12:42:24.631606 memory_type:LPDDR4
2264 12:42:24.635306 GP_NUM : 10
2265 12:42:24.635388 SRAM_EN : 1
2266 12:42:24.637932 MD32_EN : 0
2267 12:42:24.641924 ===================================
2268 12:42:24.642007 [ANA_INIT] >>>>>>>>>>>>>>
2269 12:42:24.644949 <<<<<< [CONFIGURE PHASE]: ANA_TX
2270 12:42:24.648345 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2271 12:42:24.652014 ===================================
2272 12:42:24.655104 data_rate = 2400,PCW = 0X5b00
2273 12:42:24.658354 ===================================
2274 12:42:24.661797 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2275 12:42:24.668316 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2276 12:42:24.671577 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2277 12:42:24.678283 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2278 12:42:24.681920 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2279 12:42:24.685463 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2280 12:42:24.685544 [ANA_INIT] flow start
2281 12:42:24.688171 [ANA_INIT] PLL >>>>>>>>
2282 12:42:24.691773 [ANA_INIT] PLL <<<<<<<<
2283 12:42:24.694978 [ANA_INIT] MIDPI >>>>>>>>
2284 12:42:24.695068 [ANA_INIT] MIDPI <<<<<<<<
2285 12:42:24.698367 [ANA_INIT] DLL >>>>>>>>
2286 12:42:24.701627 [ANA_INIT] DLL <<<<<<<<
2287 12:42:24.701707 [ANA_INIT] flow end
2288 12:42:24.705100 ============ LP4 DIFF to SE enter ============
2289 12:42:24.712486 ============ LP4 DIFF to SE exit ============
2290 12:42:24.712594 [ANA_INIT] <<<<<<<<<<<<<
2291 12:42:24.715595 [Flow] Enable top DCM control >>>>>
2292 12:42:24.718716 [Flow] Enable top DCM control <<<<<
2293 12:42:24.722066 Enable DLL master slave shuffle
2294 12:42:24.728741 ==============================================================
2295 12:42:24.728821 Gating Mode config
2296 12:42:24.735604 ==============================================================
2297 12:42:24.738813 Config description:
2298 12:42:24.745455 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2299 12:42:24.752227 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2300 12:42:24.759110 SELPH_MODE 0: By rank 1: By Phase
2301 12:42:24.762670 ==============================================================
2302 12:42:24.765644 GAT_TRACK_EN = 1
2303 12:42:24.768862 RX_GATING_MODE = 2
2304 12:42:24.772288 RX_GATING_TRACK_MODE = 2
2305 12:42:24.775935 SELPH_MODE = 1
2306 12:42:24.779940 PICG_EARLY_EN = 1
2307 12:42:24.782316 VALID_LAT_VALUE = 1
2308 12:42:24.785620 ==============================================================
2309 12:42:24.789308 Enter into Gating configuration >>>>
2310 12:42:24.792641 Exit from Gating configuration <<<<
2311 12:42:24.795932 Enter into DVFS_PRE_config >>>>>
2312 12:42:24.809518 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2313 12:42:24.812644 Exit from DVFS_PRE_config <<<<<
2314 12:42:24.815852 Enter into PICG configuration >>>>
2315 12:42:24.815941 Exit from PICG configuration <<<<
2316 12:42:24.819336 [RX_INPUT] configuration >>>>>
2317 12:42:24.822704 [RX_INPUT] configuration <<<<<
2318 12:42:24.829691 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2319 12:42:24.832536 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2320 12:42:24.839828 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2321 12:42:24.846548 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2322 12:42:24.853289 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2323 12:42:24.859553 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2324 12:42:24.863024 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2325 12:42:24.866388 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2326 12:42:24.869726 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2327 12:42:24.876391 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2328 12:42:24.879886 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2329 12:42:24.883256 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2330 12:42:24.886539 ===================================
2331 12:42:24.890074 LPDDR4 DRAM CONFIGURATION
2332 12:42:24.893059 ===================================
2333 12:42:24.893136 EX_ROW_EN[0] = 0x0
2334 12:42:24.896457 EX_ROW_EN[1] = 0x0
2335 12:42:24.896526 LP4Y_EN = 0x0
2336 12:42:24.899480 WORK_FSP = 0x0
2337 12:42:24.899578 WL = 0x4
2338 12:42:24.903097 RL = 0x4
2339 12:42:24.906359 BL = 0x2
2340 12:42:24.906471 RPST = 0x0
2341 12:42:24.909437 RD_PRE = 0x0
2342 12:42:24.909509 WR_PRE = 0x1
2343 12:42:24.913004 WR_PST = 0x0
2344 12:42:24.913100 DBI_WR = 0x0
2345 12:42:24.916586 DBI_RD = 0x0
2346 12:42:24.916685 OTF = 0x1
2347 12:42:24.920199 ===================================
2348 12:42:24.923463 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2349 12:42:24.929593 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2350 12:42:24.933067 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2351 12:42:24.936758 ===================================
2352 12:42:24.939644 LPDDR4 DRAM CONFIGURATION
2353 12:42:24.943064 ===================================
2354 12:42:24.943139 EX_ROW_EN[0] = 0x10
2355 12:42:24.946889 EX_ROW_EN[1] = 0x0
2356 12:42:24.946959 LP4Y_EN = 0x0
2357 12:42:24.950072 WORK_FSP = 0x0
2358 12:42:24.950170 WL = 0x4
2359 12:42:24.953551 RL = 0x4
2360 12:42:24.953642 BL = 0x2
2361 12:42:24.956844 RPST = 0x0
2362 12:42:24.956938 RD_PRE = 0x0
2363 12:42:24.959718 WR_PRE = 0x1
2364 12:42:24.959784 WR_PST = 0x0
2365 12:42:24.963371 DBI_WR = 0x0
2366 12:42:24.963441 DBI_RD = 0x0
2367 12:42:24.966833 OTF = 0x1
2368 12:42:24.969922 ===================================
2369 12:42:24.976845 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2370 12:42:24.976945 ==
2371 12:42:24.979905 Dram Type= 6, Freq= 0, CH_0, rank 0
2372 12:42:24.983851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2373 12:42:24.983922 ==
2374 12:42:24.986844 [Duty_Offset_Calibration]
2375 12:42:24.986912 B0:2 B1:-1 CA:1
2376 12:42:24.986971
2377 12:42:24.990340 [DutyScan_Calibration_Flow] k_type=0
2378 12:42:25.000007
2379 12:42:25.000087 ==CLK 0==
2380 12:42:25.003247 Final CLK duty delay cell = -4
2381 12:42:25.006650 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2382 12:42:25.009749 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2383 12:42:25.013440 [-4] AVG Duty = 4953%(X100)
2384 12:42:25.013537
2385 12:42:25.016662 CH0 CLK Duty spec in!! Max-Min= 156%
2386 12:42:25.020022 [DutyScan_Calibration_Flow] ====Done====
2387 12:42:25.020094
2388 12:42:25.022942 [DutyScan_Calibration_Flow] k_type=1
2389 12:42:25.038058
2390 12:42:25.038160 ==DQS 0 ==
2391 12:42:25.040760 Final DQS duty delay cell = -4
2392 12:42:25.044668 [-4] MAX Duty = 5000%(X100), DQS PI = 48
2393 12:42:25.048194 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2394 12:42:25.051500 [-4] AVG Duty = 4938%(X100)
2395 12:42:25.051575
2396 12:42:25.051635 ==DQS 1 ==
2397 12:42:25.054716 Final DQS duty delay cell = -4
2398 12:42:25.058132 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2399 12:42:25.061142 [-4] MIN Duty = 5000%(X100), DQS PI = 44
2400 12:42:25.064642 [-4] AVG Duty = 5062%(X100)
2401 12:42:25.064734
2402 12:42:25.067826 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2403 12:42:25.067924
2404 12:42:25.071081 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2405 12:42:25.074302 [DutyScan_Calibration_Flow] ====Done====
2406 12:42:25.074421
2407 12:42:25.077728 [DutyScan_Calibration_Flow] k_type=3
2408 12:42:25.094620
2409 12:42:25.094699 ==DQM 0 ==
2410 12:42:25.098347 Final DQM duty delay cell = 0
2411 12:42:25.101428 [0] MAX Duty = 5031%(X100), DQS PI = 54
2412 12:42:25.104782 [0] MIN Duty = 4907%(X100), DQS PI = 2
2413 12:42:25.104878 [0] AVG Duty = 4969%(X100)
2414 12:42:25.107905
2415 12:42:25.107999 ==DQM 1 ==
2416 12:42:25.111721 Final DQM duty delay cell = 0
2417 12:42:25.114668 [0] MAX Duty = 5156%(X100), DQS PI = 62
2418 12:42:25.118043 [0] MIN Duty = 5000%(X100), DQS PI = 8
2419 12:42:25.118148 [0] AVG Duty = 5078%(X100)
2420 12:42:25.118241
2421 12:42:25.125290 CH0 DQM 0 Duty spec in!! Max-Min= 124%
2422 12:42:25.125393
2423 12:42:25.128036 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2424 12:42:25.131496 [DutyScan_Calibration_Flow] ====Done====
2425 12:42:25.131570
2426 12:42:25.135203 [DutyScan_Calibration_Flow] k_type=2
2427 12:42:25.150376
2428 12:42:25.150485 ==DQ 0 ==
2429 12:42:25.154049 Final DQ duty delay cell = -4
2430 12:42:25.156993 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2431 12:42:25.160780 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2432 12:42:25.164161 [-4] AVG Duty = 4984%(X100)
2433 12:42:25.164232
2434 12:42:25.164292 ==DQ 1 ==
2435 12:42:25.167385 Final DQ duty delay cell = 0
2436 12:42:25.170611 [0] MAX Duty = 5031%(X100), DQS PI = 18
2437 12:42:25.174651 [0] MIN Duty = 4907%(X100), DQS PI = 46
2438 12:42:25.174765 [0] AVG Duty = 4969%(X100)
2439 12:42:25.174857
2440 12:42:25.177412 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2441 12:42:25.180858
2442 12:42:25.184495 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2443 12:42:25.187451 [DutyScan_Calibration_Flow] ====Done====
2444 12:42:25.187532 ==
2445 12:42:25.191021 Dram Type= 6, Freq= 0, CH_1, rank 0
2446 12:42:25.194463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2447 12:42:25.194545 ==
2448 12:42:25.197852 [Duty_Offset_Calibration]
2449 12:42:25.197966 B0:1 B1:1 CA:2
2450 12:42:25.198045
2451 12:42:25.201099 [DutyScan_Calibration_Flow] k_type=0
2452 12:42:25.210825
2453 12:42:25.210906 ==CLK 0==
2454 12:42:25.214256 Final CLK duty delay cell = 0
2455 12:42:25.217681 [0] MAX Duty = 5156%(X100), DQS PI = 24
2456 12:42:25.220974 [0] MIN Duty = 4969%(X100), DQS PI = 40
2457 12:42:25.221056 [0] AVG Duty = 5062%(X100)
2458 12:42:25.224359
2459 12:42:25.224440 CH1 CLK Duty spec in!! Max-Min= 187%
2460 12:42:25.231401 [DutyScan_Calibration_Flow] ====Done====
2461 12:42:25.231483
2462 12:42:25.233933 [DutyScan_Calibration_Flow] k_type=1
2463 12:42:25.249966
2464 12:42:25.250064 ==DQS 0 ==
2465 12:42:25.253411 Final DQS duty delay cell = 0
2466 12:42:25.256495 [0] MAX Duty = 5031%(X100), DQS PI = 18
2467 12:42:25.260078 [0] MIN Duty = 4844%(X100), DQS PI = 48
2468 12:42:25.263382 [0] AVG Duty = 4937%(X100)
2469 12:42:25.263463
2470 12:42:25.263526 ==DQS 1 ==
2471 12:42:25.266933 Final DQS duty delay cell = 0
2472 12:42:25.270333 [0] MAX Duty = 5062%(X100), DQS PI = 36
2473 12:42:25.273715 [0] MIN Duty = 4907%(X100), DQS PI = 0
2474 12:42:25.273833 [0] AVG Duty = 4984%(X100)
2475 12:42:25.273924
2476 12:42:25.280422 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2477 12:42:25.280502
2478 12:42:25.283483 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2479 12:42:25.287756 [DutyScan_Calibration_Flow] ====Done====
2480 12:42:25.287836
2481 12:42:25.289994 [DutyScan_Calibration_Flow] k_type=3
2482 12:42:25.307008
2483 12:42:25.307088 ==DQM 0 ==
2484 12:42:25.309987 Final DQM duty delay cell = 0
2485 12:42:25.313612 [0] MAX Duty = 5093%(X100), DQS PI = 18
2486 12:42:25.316879 [0] MIN Duty = 4907%(X100), DQS PI = 48
2487 12:42:25.316959 [0] AVG Duty = 5000%(X100)
2488 12:42:25.320112
2489 12:42:25.320192 ==DQM 1 ==
2490 12:42:25.322975 Final DQM duty delay cell = 0
2491 12:42:25.326668 [0] MAX Duty = 5156%(X100), DQS PI = 62
2492 12:42:25.330020 [0] MIN Duty = 4938%(X100), DQS PI = 22
2493 12:42:25.333297 [0] AVG Duty = 5047%(X100)
2494 12:42:25.333377
2495 12:42:25.336477 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2496 12:42:25.336559
2497 12:42:25.340166 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2498 12:42:25.343819 [DutyScan_Calibration_Flow] ====Done====
2499 12:42:25.343901
2500 12:42:25.346306 [DutyScan_Calibration_Flow] k_type=2
2501 12:42:25.363264
2502 12:42:25.363345 ==DQ 0 ==
2503 12:42:25.366560 Final DQ duty delay cell = 0
2504 12:42:25.370019 [0] MAX Duty = 5124%(X100), DQS PI = 18
2505 12:42:25.373462 [0] MIN Duty = 4938%(X100), DQS PI = 50
2506 12:42:25.373543 [0] AVG Duty = 5031%(X100)
2507 12:42:25.373607
2508 12:42:25.376984 ==DQ 1 ==
2509 12:42:25.380261 Final DQ duty delay cell = 0
2510 12:42:25.383207 [0] MAX Duty = 5093%(X100), DQS PI = 12
2511 12:42:25.386663 [0] MIN Duty = 5000%(X100), DQS PI = 50
2512 12:42:25.386744 [0] AVG Duty = 5046%(X100)
2513 12:42:25.386807
2514 12:42:25.390147 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2515 12:42:25.390228
2516 12:42:25.393504 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2517 12:42:25.396672 [DutyScan_Calibration_Flow] ====Done====
2518 12:42:25.402190 nWR fixed to 30
2519 12:42:25.405413 [ModeRegInit_LP4] CH0 RK0
2520 12:42:25.405494 [ModeRegInit_LP4] CH0 RK1
2521 12:42:25.408857 [ModeRegInit_LP4] CH1 RK0
2522 12:42:25.412228 [ModeRegInit_LP4] CH1 RK1
2523 12:42:25.412310 match AC timing 7
2524 12:42:25.419201 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2525 12:42:25.422339 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2526 12:42:25.425396 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2527 12:42:25.431897 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2528 12:42:25.435787 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2529 12:42:25.435902 ==
2530 12:42:25.439046 Dram Type= 6, Freq= 0, CH_0, rank 0
2531 12:42:25.442784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2532 12:42:25.442865 ==
2533 12:42:25.449133 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2534 12:42:25.455849 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2535 12:42:25.462824 [CA 0] Center 40 (10~71) winsize 62
2536 12:42:25.466441 [CA 1] Center 39 (9~70) winsize 62
2537 12:42:25.469413 [CA 2] Center 36 (6~67) winsize 62
2538 12:42:25.473136 [CA 3] Center 35 (5~66) winsize 62
2539 12:42:25.476303 [CA 4] Center 35 (5~65) winsize 61
2540 12:42:25.480142 [CA 5] Center 34 (4~65) winsize 62
2541 12:42:25.480223
2542 12:42:25.483375 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2543 12:42:25.483456
2544 12:42:25.486260 [CATrainingPosCal] consider 1 rank data
2545 12:42:25.489809 u2DelayCellTimex100 = 270/100 ps
2546 12:42:25.493495 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2547 12:42:25.496408 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2548 12:42:25.503276 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2549 12:42:25.507017 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2550 12:42:25.509985 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2551 12:42:25.513325 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
2552 12:42:25.513406
2553 12:42:25.516491 CA PerBit enable=1, Macro0, CA PI delay=34
2554 12:42:25.516572
2555 12:42:25.520081 [CBTSetCACLKResult] CA Dly = 34
2556 12:42:25.520162 CS Dly: 7 (0~38)
2557 12:42:25.520226 ==
2558 12:42:25.523605 Dram Type= 6, Freq= 0, CH_0, rank 1
2559 12:42:25.530221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2560 12:42:25.530303 ==
2561 12:42:25.533433 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2562 12:42:25.540057 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2563 12:42:25.548920 [CA 0] Center 39 (9~70) winsize 62
2564 12:42:25.552184 [CA 1] Center 40 (10~70) winsize 61
2565 12:42:25.556345 [CA 2] Center 36 (6~67) winsize 62
2566 12:42:25.558777 [CA 3] Center 35 (5~66) winsize 62
2567 12:42:25.562792 [CA 4] Center 34 (4~65) winsize 62
2568 12:42:25.566386 [CA 5] Center 34 (4~64) winsize 61
2569 12:42:25.566530
2570 12:42:25.568679 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2571 12:42:25.568759
2572 12:42:25.572530 [CATrainingPosCal] consider 2 rank data
2573 12:42:25.575619 u2DelayCellTimex100 = 270/100 ps
2574 12:42:25.579122 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2575 12:42:25.585553 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2576 12:42:25.588924 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2577 12:42:25.592534 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2578 12:42:25.595783 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2579 12:42:25.598957 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2580 12:42:25.599038
2581 12:42:25.602846 CA PerBit enable=1, Macro0, CA PI delay=34
2582 12:42:25.602927
2583 12:42:25.605736 [CBTSetCACLKResult] CA Dly = 34
2584 12:42:25.605817 CS Dly: 8 (0~41)
2585 12:42:25.605880
2586 12:42:25.609007 ----->DramcWriteLeveling(PI) begin...
2587 12:42:25.613201 ==
2588 12:42:25.613281 Dram Type= 6, Freq= 0, CH_0, rank 0
2589 12:42:25.619274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2590 12:42:25.619356 ==
2591 12:42:25.622612 Write leveling (Byte 0): 30 => 30
2592 12:42:25.625876 Write leveling (Byte 1): 30 => 30
2593 12:42:25.625989 DramcWriteLeveling(PI) end<-----
2594 12:42:25.629441
2595 12:42:25.629521 ==
2596 12:42:25.632989 Dram Type= 6, Freq= 0, CH_0, rank 0
2597 12:42:25.636070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2598 12:42:25.636152 ==
2599 12:42:25.639252 [Gating] SW mode calibration
2600 12:42:25.645936 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2601 12:42:25.649324 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2602 12:42:25.656499 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 12:42:25.659427 0 15 4 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
2604 12:42:25.662766 0 15 8 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2605 12:42:25.669994 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2606 12:42:25.673052 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2607 12:42:25.676360 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2608 12:42:25.683234 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2609 12:42:25.685958 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2610 12:42:25.689302 1 0 0 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2611 12:42:25.693167 1 0 4 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (1 0)
2612 12:42:25.700245 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2613 12:42:25.703147 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2614 12:42:25.707004 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2615 12:42:25.713602 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2616 12:42:25.716970 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2617 12:42:25.720421 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2618 12:42:25.727010 1 1 0 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
2619 12:42:25.730582 1 1 4 | B1->B0 | 3a3a 4444 | 1 0 | (0 0) (0 0)
2620 12:42:25.733739 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 12:42:25.737088 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2622 12:42:25.743987 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 12:42:25.747457 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2624 12:42:25.750651 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2625 12:42:25.756929 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2626 12:42:25.760862 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2627 12:42:25.763830 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2628 12:42:25.770737 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 12:42:25.773761 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 12:42:25.777128 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 12:42:25.783960 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 12:42:25.786902 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 12:42:25.790501 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 12:42:25.797430 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 12:42:25.800038 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 12:42:25.803319 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 12:42:25.810789 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 12:42:25.814063 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 12:42:25.817400 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 12:42:25.820868 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 12:42:25.826973 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 12:42:25.830333 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2643 12:42:25.834520 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2644 12:42:25.837381 Total UI for P1: 0, mck2ui 16
2645 12:42:25.840796 best dqsien dly found for B0: ( 1, 4, 0)
2646 12:42:25.844116 Total UI for P1: 0, mck2ui 16
2647 12:42:25.847149 best dqsien dly found for B1: ( 1, 4, 0)
2648 12:42:25.850332 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2649 12:42:25.854050 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2650 12:42:25.854131
2651 12:42:25.857276 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2652 12:42:25.863712 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2653 12:42:25.863794 [Gating] SW calibration Done
2654 12:42:25.863858 ==
2655 12:42:25.867221 Dram Type= 6, Freq= 0, CH_0, rank 0
2656 12:42:25.874252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2657 12:42:25.874358 ==
2658 12:42:25.874479 RX Vref Scan: 0
2659 12:42:25.874553
2660 12:42:25.877725 RX Vref 0 -> 0, step: 1
2661 12:42:25.877806
2662 12:42:25.880674 RX Delay -40 -> 252, step: 8
2663 12:42:25.884126 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2664 12:42:25.887521 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2665 12:42:25.891205 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2666 12:42:25.894561 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2667 12:42:25.901088 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2668 12:42:25.904386 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2669 12:42:25.907463 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2670 12:42:25.911492 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2671 12:42:25.914499 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2672 12:42:25.921493 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2673 12:42:25.924687 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2674 12:42:25.928113 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2675 12:42:25.931119 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2676 12:42:25.934415 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2677 12:42:25.941116 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2678 12:42:25.944479 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2679 12:42:25.944561 ==
2680 12:42:25.948148 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 12:42:25.951307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 12:42:25.951388 ==
2683 12:42:25.951452 DQS Delay:
2684 12:42:25.954521 DQS0 = 0, DQS1 = 0
2685 12:42:25.954601 DQM Delay:
2686 12:42:25.957835 DQM0 = 116, DQM1 = 107
2687 12:42:25.957915 DQ Delay:
2688 12:42:25.961235 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2689 12:42:25.964701 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2690 12:42:25.967939 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2691 12:42:25.971379 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2692 12:42:25.971460
2693 12:42:25.974626
2694 12:42:25.974707 ==
2695 12:42:25.977805 Dram Type= 6, Freq= 0, CH_0, rank 0
2696 12:42:25.981380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2697 12:42:25.981462 ==
2698 12:42:25.981525
2699 12:42:25.981584
2700 12:42:25.984732 TX Vref Scan disable
2701 12:42:25.984813 == TX Byte 0 ==
2702 12:42:25.988101 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2703 12:42:25.994455 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2704 12:42:25.994536 == TX Byte 1 ==
2705 12:42:25.998961 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2706 12:42:26.004945 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2707 12:42:26.005026 ==
2708 12:42:26.008358 Dram Type= 6, Freq= 0, CH_0, rank 0
2709 12:42:26.011897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2710 12:42:26.011979 ==
2711 12:42:26.023787 TX Vref=22, minBit 1, minWin=24, winSum=416
2712 12:42:26.026713 TX Vref=24, minBit 5, minWin=25, winSum=421
2713 12:42:26.029917 TX Vref=26, minBit 5, minWin=25, winSum=424
2714 12:42:26.033535 TX Vref=28, minBit 0, minWin=26, winSum=426
2715 12:42:26.037150 TX Vref=30, minBit 0, minWin=26, winSum=432
2716 12:42:26.039840 TX Vref=32, minBit 0, minWin=26, winSum=427
2717 12:42:26.047145 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 30
2718 12:42:26.047227
2719 12:42:26.050116 Final TX Range 1 Vref 30
2720 12:42:26.050198
2721 12:42:26.050262 ==
2722 12:42:26.053859 Dram Type= 6, Freq= 0, CH_0, rank 0
2723 12:42:26.056744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2724 12:42:26.056826 ==
2725 12:42:26.056890
2726 12:42:26.056949
2727 12:42:26.060073 TX Vref Scan disable
2728 12:42:26.064004 == TX Byte 0 ==
2729 12:42:26.066736 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2730 12:42:26.070602 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2731 12:42:26.073618 == TX Byte 1 ==
2732 12:42:26.077095 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2733 12:42:26.080707 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2734 12:42:26.080788
2735 12:42:26.083931 [DATLAT]
2736 12:42:26.084012 Freq=1200, CH0 RK0
2737 12:42:26.084077
2738 12:42:26.086795 DATLAT Default: 0xd
2739 12:42:26.086877 0, 0xFFFF, sum = 0
2740 12:42:26.090385 1, 0xFFFF, sum = 0
2741 12:42:26.090507 2, 0xFFFF, sum = 0
2742 12:42:26.093771 3, 0xFFFF, sum = 0
2743 12:42:26.093879 4, 0xFFFF, sum = 0
2744 12:42:26.096950 5, 0xFFFF, sum = 0
2745 12:42:26.097033 6, 0xFFFF, sum = 0
2746 12:42:26.100879 7, 0xFFFF, sum = 0
2747 12:42:26.100961 8, 0xFFFF, sum = 0
2748 12:42:26.104047 9, 0xFFFF, sum = 0
2749 12:42:26.104130 10, 0xFFFF, sum = 0
2750 12:42:26.106988 11, 0xFFFF, sum = 0
2751 12:42:26.107058 12, 0x0, sum = 1
2752 12:42:26.110873 13, 0x0, sum = 2
2753 12:42:26.110944 14, 0x0, sum = 3
2754 12:42:26.114094 15, 0x0, sum = 4
2755 12:42:26.114160 best_step = 13
2756 12:42:26.114225
2757 12:42:26.114282 ==
2758 12:42:26.117525 Dram Type= 6, Freq= 0, CH_0, rank 0
2759 12:42:26.120910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2760 12:42:26.124203 ==
2761 12:42:26.124307 RX Vref Scan: 1
2762 12:42:26.124397
2763 12:42:26.127602 Set Vref Range= 32 -> 127
2764 12:42:26.127675
2765 12:42:26.130777 RX Vref 32 -> 127, step: 1
2766 12:42:26.130847
2767 12:42:26.130907 RX Delay -21 -> 252, step: 4
2768 12:42:26.130969
2769 12:42:26.134121 Set Vref, RX VrefLevel [Byte0]: 32
2770 12:42:26.137303 [Byte1]: 32
2771 12:42:26.141339
2772 12:42:26.141436 Set Vref, RX VrefLevel [Byte0]: 33
2773 12:42:26.144775 [Byte1]: 33
2774 12:42:26.149609
2775 12:42:26.149689 Set Vref, RX VrefLevel [Byte0]: 34
2776 12:42:26.152581 [Byte1]: 34
2777 12:42:26.157202
2778 12:42:26.157311 Set Vref, RX VrefLevel [Byte0]: 35
2779 12:42:26.161158 [Byte1]: 35
2780 12:42:26.165311
2781 12:42:26.165418 Set Vref, RX VrefLevel [Byte0]: 36
2782 12:42:26.169106 [Byte1]: 36
2783 12:42:26.173669
2784 12:42:26.173776 Set Vref, RX VrefLevel [Byte0]: 37
2785 12:42:26.176307 [Byte1]: 37
2786 12:42:26.181554
2787 12:42:26.181650 Set Vref, RX VrefLevel [Byte0]: 38
2788 12:42:26.184694 [Byte1]: 38
2789 12:42:26.189678
2790 12:42:26.189815 Set Vref, RX VrefLevel [Byte0]: 39
2791 12:42:26.191954 [Byte1]: 39
2792 12:42:26.197072
2793 12:42:26.197193 Set Vref, RX VrefLevel [Byte0]: 40
2794 12:42:26.200370 [Byte1]: 40
2795 12:42:26.204776
2796 12:42:26.204851 Set Vref, RX VrefLevel [Byte0]: 41
2797 12:42:26.208154 [Byte1]: 41
2798 12:42:26.212577
2799 12:42:26.212647 Set Vref, RX VrefLevel [Byte0]: 42
2800 12:42:26.216239 [Byte1]: 42
2801 12:42:26.220365
2802 12:42:26.220442 Set Vref, RX VrefLevel [Byte0]: 43
2803 12:42:26.224160 [Byte1]: 43
2804 12:42:26.228536
2805 12:42:26.228642 Set Vref, RX VrefLevel [Byte0]: 44
2806 12:42:26.231579 [Byte1]: 44
2807 12:42:26.236253
2808 12:42:26.236356 Set Vref, RX VrefLevel [Byte0]: 45
2809 12:42:26.240041 [Byte1]: 45
2810 12:42:26.244583
2811 12:42:26.244689 Set Vref, RX VrefLevel [Byte0]: 46
2812 12:42:26.247887 [Byte1]: 46
2813 12:42:26.252433
2814 12:42:26.252533 Set Vref, RX VrefLevel [Byte0]: 47
2815 12:42:26.255846 [Byte1]: 47
2816 12:42:26.259906
2817 12:42:26.260007 Set Vref, RX VrefLevel [Byte0]: 48
2818 12:42:26.263554 [Byte1]: 48
2819 12:42:26.268075
2820 12:42:26.268173 Set Vref, RX VrefLevel [Byte0]: 49
2821 12:42:26.271767 [Byte1]: 49
2822 12:42:26.275925
2823 12:42:26.276009 Set Vref, RX VrefLevel [Byte0]: 50
2824 12:42:26.279548 [Byte1]: 50
2825 12:42:26.284588
2826 12:42:26.284670 Set Vref, RX VrefLevel [Byte0]: 51
2827 12:42:26.287883 [Byte1]: 51
2828 12:42:26.291700
2829 12:42:26.291783 Set Vref, RX VrefLevel [Byte0]: 52
2830 12:42:26.295229 [Byte1]: 52
2831 12:42:26.299889
2832 12:42:26.299972 Set Vref, RX VrefLevel [Byte0]: 53
2833 12:42:26.303005 [Byte1]: 53
2834 12:42:26.308003
2835 12:42:26.308118 Set Vref, RX VrefLevel [Byte0]: 54
2836 12:42:26.311014 [Byte1]: 54
2837 12:42:26.316184
2838 12:42:26.316288 Set Vref, RX VrefLevel [Byte0]: 55
2839 12:42:26.318973 [Byte1]: 55
2840 12:42:26.323589
2841 12:42:26.323731 Set Vref, RX VrefLevel [Byte0]: 56
2842 12:42:26.327370 [Byte1]: 56
2843 12:42:26.331847
2844 12:42:26.331923 Set Vref, RX VrefLevel [Byte0]: 57
2845 12:42:26.334953 [Byte1]: 57
2846 12:42:26.340235
2847 12:42:26.340315 Set Vref, RX VrefLevel [Byte0]: 58
2848 12:42:26.342997 [Byte1]: 58
2849 12:42:26.347626
2850 12:42:26.347707 Set Vref, RX VrefLevel [Byte0]: 59
2851 12:42:26.351180 [Byte1]: 59
2852 12:42:26.355359
2853 12:42:26.355440 Set Vref, RX VrefLevel [Byte0]: 60
2854 12:42:26.358723 [Byte1]: 60
2855 12:42:26.363829
2856 12:42:26.363910 Set Vref, RX VrefLevel [Byte0]: 61
2857 12:42:26.366847 [Byte1]: 61
2858 12:42:26.371615
2859 12:42:26.371696 Set Vref, RX VrefLevel [Byte0]: 62
2860 12:42:26.374687 [Byte1]: 62
2861 12:42:26.379363
2862 12:42:26.379444 Set Vref, RX VrefLevel [Byte0]: 63
2863 12:42:26.385814 [Byte1]: 63
2864 12:42:26.385896
2865 12:42:26.389215 Set Vref, RX VrefLevel [Byte0]: 64
2866 12:42:26.392305 [Byte1]: 64
2867 12:42:26.392387
2868 12:42:26.395969 Set Vref, RX VrefLevel [Byte0]: 65
2869 12:42:26.399324 [Byte1]: 65
2870 12:42:26.403017
2871 12:42:26.403098 Set Vref, RX VrefLevel [Byte0]: 66
2872 12:42:26.406083 [Byte1]: 66
2873 12:42:26.411029
2874 12:42:26.411115 Set Vref, RX VrefLevel [Byte0]: 67
2875 12:42:26.414829 [Byte1]: 67
2876 12:42:26.419256
2877 12:42:26.419338 Set Vref, RX VrefLevel [Byte0]: 68
2878 12:42:26.422581 [Byte1]: 68
2879 12:42:26.426932
2880 12:42:26.427013 Set Vref, RX VrefLevel [Byte0]: 69
2881 12:42:26.429760 [Byte1]: 69
2882 12:42:26.434961
2883 12:42:26.435037 Final RX Vref Byte 0 = 54 to rank0
2884 12:42:26.438544 Final RX Vref Byte 1 = 50 to rank0
2885 12:42:26.441625 Final RX Vref Byte 0 = 54 to rank1
2886 12:42:26.445145 Final RX Vref Byte 1 = 50 to rank1==
2887 12:42:26.448050 Dram Type= 6, Freq= 0, CH_0, rank 0
2888 12:42:26.454983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2889 12:42:26.455058 ==
2890 12:42:26.455121 DQS Delay:
2891 12:42:26.455180 DQS0 = 0, DQS1 = 0
2892 12:42:26.457899 DQM Delay:
2893 12:42:26.457995 DQM0 = 115, DQM1 = 104
2894 12:42:26.461624 DQ Delay:
2895 12:42:26.464787 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =114
2896 12:42:26.467847 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2897 12:42:26.471322 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2898 12:42:26.475035 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =112
2899 12:42:26.475112
2900 12:42:26.475174
2901 12:42:26.481329 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbea, (MSB)MR19= 0x303, tDQSOscB0 = 419 ps tDQSOscB1 = 412 ps
2902 12:42:26.484586 CH0 RK0: MR19=303, MR18=FBEA
2903 12:42:26.492038 CH0_RK0: MR19=0x303, MR18=0xFBEA, DQSOSC=412, MR23=63, INC=38, DEC=25
2904 12:42:26.492115
2905 12:42:26.494601 ----->DramcWriteLeveling(PI) begin...
2906 12:42:26.494673 ==
2907 12:42:26.497904 Dram Type= 6, Freq= 0, CH_0, rank 1
2908 12:42:26.501146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2909 12:42:26.501223 ==
2910 12:42:26.504534 Write leveling (Byte 0): 34 => 34
2911 12:42:26.508080 Write leveling (Byte 1): 28 => 28
2912 12:42:26.511825 DramcWriteLeveling(PI) end<-----
2913 12:42:26.511899
2914 12:42:26.511960 ==
2915 12:42:26.514359 Dram Type= 6, Freq= 0, CH_0, rank 1
2916 12:42:26.520926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2917 12:42:26.521027 ==
2918 12:42:26.521117 [Gating] SW mode calibration
2919 12:42:26.531489 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2920 12:42:26.534617 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2921 12:42:26.538176 0 15 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2922 12:42:26.545075 0 15 4 | B1->B0 | 2929 3434 | 1 0 | (0 0) (0 0)
2923 12:42:26.548651 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2924 12:42:26.551545 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2925 12:42:26.558571 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2926 12:42:26.561392 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2927 12:42:26.564578 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2928 12:42:26.571299 0 15 28 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (1 0)
2929 12:42:26.574679 1 0 0 | B1->B0 | 2e2e 2828 | 0 0 | (0 0) (0 0)
2930 12:42:26.578564 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2931 12:42:26.585078 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2932 12:42:26.587960 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 12:42:26.591385 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2934 12:42:26.594879 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2935 12:42:26.601456 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2936 12:42:26.605168 1 0 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
2937 12:42:26.608450 1 1 0 | B1->B0 | 3636 4343 | 1 0 | (0 0) (0 0)
2938 12:42:26.614711 1 1 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2939 12:42:26.618080 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 12:42:26.621814 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 12:42:26.627997 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 12:42:26.632102 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 12:42:26.635872 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 12:42:26.641803 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2945 12:42:26.645129 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2946 12:42:26.648384 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 12:42:26.654985 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 12:42:26.658307 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 12:42:26.661927 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 12:42:26.665170 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 12:42:26.672336 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 12:42:26.675172 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 12:42:26.678977 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 12:42:26.685667 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 12:42:26.688611 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 12:42:26.691905 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 12:42:26.698841 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 12:42:26.702112 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 12:42:26.705507 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2960 12:42:26.712097 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2961 12:42:26.715531 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2962 12:42:26.718727 Total UI for P1: 0, mck2ui 16
2963 12:42:26.721830 best dqsien dly found for B0: ( 1, 3, 26)
2964 12:42:26.725833 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2965 12:42:26.729117 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2966 12:42:26.732359 Total UI for P1: 0, mck2ui 16
2967 12:42:26.736080 best dqsien dly found for B1: ( 1, 4, 2)
2968 12:42:26.739067 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2969 12:42:26.742295 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2970 12:42:26.745544
2971 12:42:26.749051 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2972 12:42:26.752466 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2973 12:42:26.755449 [Gating] SW calibration Done
2974 12:42:26.755550 ==
2975 12:42:26.759620 Dram Type= 6, Freq= 0, CH_0, rank 1
2976 12:42:26.762674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2977 12:42:26.762745 ==
2978 12:42:26.762815 RX Vref Scan: 0
2979 12:42:26.762881
2980 12:42:26.766346 RX Vref 0 -> 0, step: 1
2981 12:42:26.766487
2982 12:42:26.769259 RX Delay -40 -> 252, step: 8
2983 12:42:26.772818 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2984 12:42:26.775991 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2985 12:42:26.779234 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2986 12:42:26.786068 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2987 12:42:26.789537 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2988 12:42:26.792505 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2989 12:42:26.796094 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2990 12:42:26.799597 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2991 12:42:26.806002 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2992 12:42:26.809378 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2993 12:42:26.812843 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2994 12:42:26.816178 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2995 12:42:26.819558 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2996 12:42:26.826459 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2997 12:42:26.829213 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2998 12:42:26.832787 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2999 12:42:26.832893 ==
3000 12:42:26.836045 Dram Type= 6, Freq= 0, CH_0, rank 1
3001 12:42:26.840125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3002 12:42:26.840238 ==
3003 12:42:26.842738 DQS Delay:
3004 12:42:26.842875 DQS0 = 0, DQS1 = 0
3005 12:42:26.842982 DQM Delay:
3006 12:42:26.846351 DQM0 = 116, DQM1 = 106
3007 12:42:26.846479 DQ Delay:
3008 12:42:26.849429 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =115
3009 12:42:26.852621 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
3010 12:42:26.856198 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
3011 12:42:26.862610 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
3012 12:42:26.862711
3013 12:42:26.862791
3014 12:42:26.862884 ==
3015 12:42:26.866393 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 12:42:26.869514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 12:42:26.869651 ==
3018 12:42:26.869767
3019 12:42:26.869844
3020 12:42:26.872861 TX Vref Scan disable
3021 12:42:26.872959 == TX Byte 0 ==
3022 12:42:26.879688 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3023 12:42:26.883059 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3024 12:42:26.883158 == TX Byte 1 ==
3025 12:42:26.889628 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3026 12:42:26.893087 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3027 12:42:26.893187 ==
3028 12:42:26.896191 Dram Type= 6, Freq= 0, CH_0, rank 1
3029 12:42:26.900200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3030 12:42:26.900333 ==
3031 12:42:26.912380 TX Vref=22, minBit 1, minWin=25, winSum=420
3032 12:42:26.916046 TX Vref=24, minBit 3, minWin=25, winSum=430
3033 12:42:26.919078 TX Vref=26, minBit 3, minWin=25, winSum=427
3034 12:42:26.923109 TX Vref=28, minBit 4, minWin=26, winSum=432
3035 12:42:26.926060 TX Vref=30, minBit 12, minWin=26, winSum=437
3036 12:42:26.932750 TX Vref=32, minBit 13, minWin=26, winSum=437
3037 12:42:26.936345 [TxChooseVref] Worse bit 12, Min win 26, Win sum 437, Final Vref 30
3038 12:42:26.936444
3039 12:42:26.939447 Final TX Range 1 Vref 30
3040 12:42:26.939544
3041 12:42:26.939632 ==
3042 12:42:26.943182 Dram Type= 6, Freq= 0, CH_0, rank 1
3043 12:42:26.946541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3044 12:42:26.946616 ==
3045 12:42:26.946678
3046 12:42:26.946743
3047 12:42:26.949551 TX Vref Scan disable
3048 12:42:26.952699 == TX Byte 0 ==
3049 12:42:26.956701 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3050 12:42:26.959973 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3051 12:42:26.963857 == TX Byte 1 ==
3052 12:42:26.966335 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3053 12:42:26.970194 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3054 12:42:26.970298
3055 12:42:26.973479 [DATLAT]
3056 12:42:26.973553 Freq=1200, CH0 RK1
3057 12:42:26.973646
3058 12:42:26.976303 DATLAT Default: 0xd
3059 12:42:26.976374 0, 0xFFFF, sum = 0
3060 12:42:26.980190 1, 0xFFFF, sum = 0
3061 12:42:26.980296 2, 0xFFFF, sum = 0
3062 12:42:26.982969 3, 0xFFFF, sum = 0
3063 12:42:26.983048 4, 0xFFFF, sum = 0
3064 12:42:26.986357 5, 0xFFFF, sum = 0
3065 12:42:26.986470 6, 0xFFFF, sum = 0
3066 12:42:26.989694 7, 0xFFFF, sum = 0
3067 12:42:26.989765 8, 0xFFFF, sum = 0
3068 12:42:26.993235 9, 0xFFFF, sum = 0
3069 12:42:26.993307 10, 0xFFFF, sum = 0
3070 12:42:26.996949 11, 0xFFFF, sum = 0
3071 12:42:26.997027 12, 0x0, sum = 1
3072 12:42:27.000141 13, 0x0, sum = 2
3073 12:42:27.000213 14, 0x0, sum = 3
3074 12:42:27.003952 15, 0x0, sum = 4
3075 12:42:27.004060 best_step = 13
3076 12:42:27.004141
3077 12:42:27.004202 ==
3078 12:42:27.006609 Dram Type= 6, Freq= 0, CH_0, rank 1
3079 12:42:27.013607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3080 12:42:27.013689 ==
3081 12:42:27.013753 RX Vref Scan: 0
3082 12:42:27.013814
3083 12:42:27.017187 RX Vref 0 -> 0, step: 1
3084 12:42:27.017268
3085 12:42:27.020139 RX Delay -21 -> 252, step: 4
3086 12:42:27.023231 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3087 12:42:27.026790 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3088 12:42:27.030264 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3089 12:42:27.037193 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3090 12:42:27.040326 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3091 12:42:27.043393 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3092 12:42:27.047114 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3093 12:42:27.050081 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3094 12:42:27.057543 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3095 12:42:27.060399 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3096 12:42:27.063509 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3097 12:42:27.067216 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3098 12:42:27.071057 iDelay=195, Bit 12, Center 112 (43 ~ 182) 140
3099 12:42:27.074248 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3100 12:42:27.080146 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3101 12:42:27.083991 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3102 12:42:27.084065 ==
3103 12:42:27.086868 Dram Type= 6, Freq= 0, CH_0, rank 1
3104 12:42:27.090301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3105 12:42:27.090445 ==
3106 12:42:27.093845 DQS Delay:
3107 12:42:27.093922 DQS0 = 0, DQS1 = 0
3108 12:42:27.097480 DQM Delay:
3109 12:42:27.097562 DQM0 = 114, DQM1 = 104
3110 12:42:27.097625 DQ Delay:
3111 12:42:27.100388 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3112 12:42:27.104572 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3113 12:42:27.107282 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3114 12:42:27.114191 DQ12 =112, DQ13 =110, DQ14 =116, DQ15 =112
3115 12:42:27.114295
3116 12:42:27.114386
3117 12:42:27.120576 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f3, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps
3118 12:42:27.123986 CH0 RK1: MR19=403, MR18=1F3
3119 12:42:27.130560 CH0_RK1: MR19=0x403, MR18=0x1F3, DQSOSC=409, MR23=63, INC=39, DEC=26
3120 12:42:27.130652 [RxdqsGatingPostProcess] freq 1200
3121 12:42:27.137826 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3122 12:42:27.140931 best DQS0 dly(2T, 0.5T) = (0, 12)
3123 12:42:27.144011 best DQS1 dly(2T, 0.5T) = (0, 12)
3124 12:42:27.147764 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3125 12:42:27.151073 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3126 12:42:27.154170 best DQS0 dly(2T, 0.5T) = (0, 11)
3127 12:42:27.157785 best DQS1 dly(2T, 0.5T) = (0, 12)
3128 12:42:27.161000 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3129 12:42:27.164571 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3130 12:42:27.164667 Pre-setting of DQS Precalculation
3131 12:42:27.171115 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3132 12:42:27.171216 ==
3133 12:42:27.174697 Dram Type= 6, Freq= 0, CH_1, rank 0
3134 12:42:27.177427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3135 12:42:27.177526 ==
3136 12:42:27.184977 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3137 12:42:27.190914 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3138 12:42:27.198857 [CA 0] Center 38 (8~68) winsize 61
3139 12:42:27.201896 [CA 1] Center 38 (8~68) winsize 61
3140 12:42:27.204869 [CA 2] Center 35 (5~65) winsize 61
3141 12:42:27.208339 [CA 3] Center 34 (4~65) winsize 62
3142 12:42:27.211562 [CA 4] Center 34 (4~65) winsize 62
3143 12:42:27.215103 [CA 5] Center 34 (4~64) winsize 61
3144 12:42:27.215181
3145 12:42:27.218618 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3146 12:42:27.218692
3147 12:42:27.221764 [CATrainingPosCal] consider 1 rank data
3148 12:42:27.225207 u2DelayCellTimex100 = 270/100 ps
3149 12:42:27.228872 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3150 12:42:27.231625 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3151 12:42:27.238362 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3152 12:42:27.241964 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3153 12:42:27.245117 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3154 12:42:27.248846 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3155 12:42:27.248928
3156 12:42:27.252046 CA PerBit enable=1, Macro0, CA PI delay=34
3157 12:42:27.252127
3158 12:42:27.255275 [CBTSetCACLKResult] CA Dly = 34
3159 12:42:27.255357 CS Dly: 6 (0~37)
3160 12:42:27.255420 ==
3161 12:42:27.258672 Dram Type= 6, Freq= 0, CH_1, rank 1
3162 12:42:27.265181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3163 12:42:27.265264 ==
3164 12:42:27.268238 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3165 12:42:27.275128 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3166 12:42:27.284336 [CA 0] Center 38 (8~68) winsize 61
3167 12:42:27.287306 [CA 1] Center 38 (8~68) winsize 61
3168 12:42:27.290409 [CA 2] Center 34 (4~65) winsize 62
3169 12:42:27.294563 [CA 3] Center 34 (4~65) winsize 62
3170 12:42:27.297540 [CA 4] Center 34 (4~65) winsize 62
3171 12:42:27.300750 [CA 5] Center 33 (3~63) winsize 61
3172 12:42:27.300831
3173 12:42:27.304292 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3174 12:42:27.304376
3175 12:42:27.307245 [CATrainingPosCal] consider 2 rank data
3176 12:42:27.310861 u2DelayCellTimex100 = 270/100 ps
3177 12:42:27.314572 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3178 12:42:27.317603 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3179 12:42:27.320900 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3180 12:42:27.327981 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3181 12:42:27.331893 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3182 12:42:27.334205 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3183 12:42:27.334286
3184 12:42:27.337391 CA PerBit enable=1, Macro0, CA PI delay=33
3185 12:42:27.337472
3186 12:42:27.340710 [CBTSetCACLKResult] CA Dly = 33
3187 12:42:27.340791 CS Dly: 7 (0~40)
3188 12:42:27.340855
3189 12:42:27.343940 ----->DramcWriteLeveling(PI) begin...
3190 12:42:27.344037 ==
3191 12:42:27.347976 Dram Type= 6, Freq= 0, CH_1, rank 0
3192 12:42:27.354221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3193 12:42:27.354335 ==
3194 12:42:27.357474 Write leveling (Byte 0): 25 => 25
3195 12:42:27.360704 Write leveling (Byte 1): 30 => 30
3196 12:42:27.360808 DramcWriteLeveling(PI) end<-----
3197 12:42:27.360899
3198 12:42:27.364294 ==
3199 12:42:27.368047 Dram Type= 6, Freq= 0, CH_1, rank 0
3200 12:42:27.371343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3201 12:42:27.371438 ==
3202 12:42:27.374120 [Gating] SW mode calibration
3203 12:42:27.381225 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3204 12:42:27.384083 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3205 12:42:27.391213 0 15 0 | B1->B0 | 2626 2424 | 1 0 | (1 1) (0 0)
3206 12:42:27.394540 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3207 12:42:27.397906 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3208 12:42:27.404307 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3209 12:42:27.407920 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3210 12:42:27.411812 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3211 12:42:27.414587 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3212 12:42:27.421468 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3213 12:42:27.424713 1 0 0 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
3214 12:42:27.428442 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 12:42:27.434570 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3216 12:42:27.438066 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 12:42:27.441418 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3218 12:42:27.448306 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3219 12:42:27.451752 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3220 12:42:27.454671 1 0 28 | B1->B0 | 2c2c 2727 | 0 1 | (0 0) (0 0)
3221 12:42:27.461778 1 1 0 | B1->B0 | 4343 3939 | 0 0 | (0 0) (0 0)
3222 12:42:27.465482 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 12:42:27.468516 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 12:42:27.471510 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 12:42:27.478779 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 12:42:27.481972 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 12:42:27.485450 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 12:42:27.491994 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3229 12:42:27.495350 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3230 12:42:27.499436 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 12:42:27.505206 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 12:42:27.508369 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 12:42:27.511699 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 12:42:27.518691 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 12:42:27.522555 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 12:42:27.525102 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 12:42:27.531969 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 12:42:27.535426 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 12:42:27.538534 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 12:42:27.542375 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 12:42:27.548619 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 12:42:27.552036 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 12:42:27.555490 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 12:42:27.562516 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3245 12:42:27.565447 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3246 12:42:27.569060 Total UI for P1: 0, mck2ui 16
3247 12:42:27.572465 best dqsien dly found for B0: ( 1, 3, 28)
3248 12:42:27.576057 Total UI for P1: 0, mck2ui 16
3249 12:42:27.578841 best dqsien dly found for B1: ( 1, 3, 30)
3250 12:42:27.582602 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3251 12:42:27.585802 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3252 12:42:27.585911
3253 12:42:27.589007 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3254 12:42:27.591997 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3255 12:42:27.595692 [Gating] SW calibration Done
3256 12:42:27.595780 ==
3257 12:42:27.599186 Dram Type= 6, Freq= 0, CH_1, rank 0
3258 12:42:27.602339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3259 12:42:27.602471 ==
3260 12:42:27.606143 RX Vref Scan: 0
3261 12:42:27.606246
3262 12:42:27.608865 RX Vref 0 -> 0, step: 1
3263 12:42:27.608967
3264 12:42:27.609070 RX Delay -40 -> 252, step: 8
3265 12:42:27.616163 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3266 12:42:27.618818 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3267 12:42:27.622131 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3268 12:42:27.625728 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3269 12:42:27.629150 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3270 12:42:27.635840 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3271 12:42:27.639185 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3272 12:42:27.642855 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3273 12:42:27.645973 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3274 12:42:27.649646 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3275 12:42:27.652547 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3276 12:42:27.659548 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3277 12:42:27.663468 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3278 12:42:27.666142 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3279 12:42:27.669505 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3280 12:42:27.672810 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3281 12:42:27.675902 ==
3282 12:42:27.679248 Dram Type= 6, Freq= 0, CH_1, rank 0
3283 12:42:27.682746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3284 12:42:27.682847 ==
3285 12:42:27.682912 DQS Delay:
3286 12:42:27.686123 DQS0 = 0, DQS1 = 0
3287 12:42:27.686219 DQM Delay:
3288 12:42:27.689753 DQM0 = 116, DQM1 = 108
3289 12:42:27.689849 DQ Delay:
3290 12:42:27.692968 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3291 12:42:27.696259 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =115
3292 12:42:27.699483 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3293 12:42:27.703098 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3294 12:42:27.703175
3295 12:42:27.703238
3296 12:42:27.703296 ==
3297 12:42:27.706705 Dram Type= 6, Freq= 0, CH_1, rank 0
3298 12:42:27.713138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3299 12:42:27.713240 ==
3300 12:42:27.713331
3301 12:42:27.713420
3302 12:42:27.713505 TX Vref Scan disable
3303 12:42:27.716210 == TX Byte 0 ==
3304 12:42:27.719965 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3305 12:42:27.723326 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3306 12:42:27.726331 == TX Byte 1 ==
3307 12:42:27.729546 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3308 12:42:27.733548 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3309 12:42:27.736329 ==
3310 12:42:27.739984 Dram Type= 6, Freq= 0, CH_1, rank 0
3311 12:42:27.743204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3312 12:42:27.743304 ==
3313 12:42:27.754213 TX Vref=22, minBit 0, minWin=25, winSum=409
3314 12:42:27.757527 TX Vref=24, minBit 1, minWin=25, winSum=416
3315 12:42:27.761247 TX Vref=26, minBit 1, minWin=25, winSum=416
3316 12:42:27.764171 TX Vref=28, minBit 0, minWin=26, winSum=424
3317 12:42:27.767716 TX Vref=30, minBit 13, minWin=25, winSum=427
3318 12:42:27.774747 TX Vref=32, minBit 13, minWin=25, winSum=421
3319 12:42:27.778099 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 28
3320 12:42:27.778201
3321 12:42:27.781058 Final TX Range 1 Vref 28
3322 12:42:27.781158
3323 12:42:27.781253 ==
3324 12:42:27.784069 Dram Type= 6, Freq= 0, CH_1, rank 0
3325 12:42:27.787434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3326 12:42:27.787506 ==
3327 12:42:27.787567
3328 12:42:27.791010
3329 12:42:27.791080 TX Vref Scan disable
3330 12:42:27.794639 == TX Byte 0 ==
3331 12:42:27.798019 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3332 12:42:27.801354 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3333 12:42:27.804574 == TX Byte 1 ==
3334 12:42:27.807884 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3335 12:42:27.811806 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3336 12:42:27.811923
3337 12:42:27.814228 [DATLAT]
3338 12:42:27.814325 Freq=1200, CH1 RK0
3339 12:42:27.814436
3340 12:42:27.817792 DATLAT Default: 0xd
3341 12:42:27.817887 0, 0xFFFF, sum = 0
3342 12:42:27.821215 1, 0xFFFF, sum = 0
3343 12:42:27.821316 2, 0xFFFF, sum = 0
3344 12:42:27.824658 3, 0xFFFF, sum = 0
3345 12:42:27.824759 4, 0xFFFF, sum = 0
3346 12:42:27.828319 5, 0xFFFF, sum = 0
3347 12:42:27.828396 6, 0xFFFF, sum = 0
3348 12:42:27.831746 7, 0xFFFF, sum = 0
3349 12:42:27.831859 8, 0xFFFF, sum = 0
3350 12:42:27.835047 9, 0xFFFF, sum = 0
3351 12:42:27.835117 10, 0xFFFF, sum = 0
3352 12:42:27.837971 11, 0xFFFF, sum = 0
3353 12:42:27.838052 12, 0x0, sum = 1
3354 12:42:27.841450 13, 0x0, sum = 2
3355 12:42:27.841522 14, 0x0, sum = 3
3356 12:42:27.844956 15, 0x0, sum = 4
3357 12:42:27.845056 best_step = 13
3358 12:42:27.845148
3359 12:42:27.845234 ==
3360 12:42:27.847925 Dram Type= 6, Freq= 0, CH_1, rank 0
3361 12:42:27.854613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3362 12:42:27.854696 ==
3363 12:42:27.854758 RX Vref Scan: 1
3364 12:42:27.854816
3365 12:42:27.858172 Set Vref Range= 32 -> 127
3366 12:42:27.858268
3367 12:42:27.861325 RX Vref 32 -> 127, step: 1
3368 12:42:27.861420
3369 12:42:27.864620 RX Delay -21 -> 252, step: 4
3370 12:42:27.864710
3371 12:42:27.864770 Set Vref, RX VrefLevel [Byte0]: 32
3372 12:42:27.867998 [Byte1]: 32
3373 12:42:27.872932
3374 12:42:27.873029 Set Vref, RX VrefLevel [Byte0]: 33
3375 12:42:27.876101 [Byte1]: 33
3376 12:42:27.880477
3377 12:42:27.880554 Set Vref, RX VrefLevel [Byte0]: 34
3378 12:42:27.884083 [Byte1]: 34
3379 12:42:27.888610
3380 12:42:27.888681 Set Vref, RX VrefLevel [Byte0]: 35
3381 12:42:27.891595 [Byte1]: 35
3382 12:42:27.896408
3383 12:42:27.896526 Set Vref, RX VrefLevel [Byte0]: 36
3384 12:42:27.899539 [Byte1]: 36
3385 12:42:27.904446
3386 12:42:27.904546 Set Vref, RX VrefLevel [Byte0]: 37
3387 12:42:27.907540 [Byte1]: 37
3388 12:42:27.912738
3389 12:42:27.912864 Set Vref, RX VrefLevel [Byte0]: 38
3390 12:42:27.915595 [Byte1]: 38
3391 12:42:27.920051
3392 12:42:27.920147 Set Vref, RX VrefLevel [Byte0]: 39
3393 12:42:27.923294 [Byte1]: 39
3394 12:42:27.928960
3395 12:42:27.929063 Set Vref, RX VrefLevel [Byte0]: 40
3396 12:42:27.931262 [Byte1]: 40
3397 12:42:27.936444
3398 12:42:27.936546 Set Vref, RX VrefLevel [Byte0]: 41
3399 12:42:27.939203 [Byte1]: 41
3400 12:42:27.944118
3401 12:42:27.944225 Set Vref, RX VrefLevel [Byte0]: 42
3402 12:42:27.947133 [Byte1]: 42
3403 12:42:27.952247
3404 12:42:27.952347 Set Vref, RX VrefLevel [Byte0]: 43
3405 12:42:27.955239 [Byte1]: 43
3406 12:42:27.959949
3407 12:42:27.960065 Set Vref, RX VrefLevel [Byte0]: 44
3408 12:42:27.963167 [Byte1]: 44
3409 12:42:27.967892
3410 12:42:27.967994 Set Vref, RX VrefLevel [Byte0]: 45
3411 12:42:27.974306 [Byte1]: 45
3412 12:42:27.974430
3413 12:42:27.977561 Set Vref, RX VrefLevel [Byte0]: 46
3414 12:42:27.981148 [Byte1]: 46
3415 12:42:27.981288
3416 12:42:27.985407 Set Vref, RX VrefLevel [Byte0]: 47
3417 12:42:27.987648 [Byte1]: 47
3418 12:42:27.992107
3419 12:42:27.992203 Set Vref, RX VrefLevel [Byte0]: 48
3420 12:42:27.994656 [Byte1]: 48
3421 12:42:27.999202
3422 12:42:27.999277 Set Vref, RX VrefLevel [Byte0]: 49
3423 12:42:28.003682 [Byte1]: 49
3424 12:42:28.007391
3425 12:42:28.007484 Set Vref, RX VrefLevel [Byte0]: 50
3426 12:42:28.010854 [Byte1]: 50
3427 12:42:28.015460
3428 12:42:28.015532 Set Vref, RX VrefLevel [Byte0]: 51
3429 12:42:28.018780 [Byte1]: 51
3430 12:42:28.023133
3431 12:42:28.023217 Set Vref, RX VrefLevel [Byte0]: 52
3432 12:42:28.026418 [Byte1]: 52
3433 12:42:28.031271
3434 12:42:28.031345 Set Vref, RX VrefLevel [Byte0]: 53
3435 12:42:28.034401 [Byte1]: 53
3436 12:42:28.038863
3437 12:42:28.038956 Set Vref, RX VrefLevel [Byte0]: 54
3438 12:42:28.042895 [Byte1]: 54
3439 12:42:28.047009
3440 12:42:28.047086 Set Vref, RX VrefLevel [Byte0]: 55
3441 12:42:28.050005 [Byte1]: 55
3442 12:42:28.054691
3443 12:42:28.054792 Set Vref, RX VrefLevel [Byte0]: 56
3444 12:42:28.058559 [Byte1]: 56
3445 12:42:28.063136
3446 12:42:28.063211 Set Vref, RX VrefLevel [Byte0]: 57
3447 12:42:28.065869 [Byte1]: 57
3448 12:42:28.071022
3449 12:42:28.071122 Set Vref, RX VrefLevel [Byte0]: 58
3450 12:42:28.074682 [Byte1]: 58
3451 12:42:28.078547
3452 12:42:28.078617 Set Vref, RX VrefLevel [Byte0]: 59
3453 12:42:28.081682 [Byte1]: 59
3454 12:42:28.086676
3455 12:42:28.086751 Set Vref, RX VrefLevel [Byte0]: 60
3456 12:42:28.090042 [Byte1]: 60
3457 12:42:28.094234
3458 12:42:28.094333 Set Vref, RX VrefLevel [Byte0]: 61
3459 12:42:28.097765 [Byte1]: 61
3460 12:42:28.102447
3461 12:42:28.102559 Set Vref, RX VrefLevel [Byte0]: 62
3462 12:42:28.105745 [Byte1]: 62
3463 12:42:28.110174
3464 12:42:28.110242 Set Vref, RX VrefLevel [Byte0]: 63
3465 12:42:28.113891 [Byte1]: 63
3466 12:42:28.118319
3467 12:42:28.118436 Set Vref, RX VrefLevel [Byte0]: 64
3468 12:42:28.121403 [Byte1]: 64
3469 12:42:28.126049
3470 12:42:28.126118 Set Vref, RX VrefLevel [Byte0]: 65
3471 12:42:28.129977 [Byte1]: 65
3472 12:42:28.134155
3473 12:42:28.134225 Set Vref, RX VrefLevel [Byte0]: 66
3474 12:42:28.137405 [Byte1]: 66
3475 12:42:28.141820
3476 12:42:28.141893 Set Vref, RX VrefLevel [Byte0]: 67
3477 12:42:28.145017 [Byte1]: 67
3478 12:42:28.150158
3479 12:42:28.150261 Set Vref, RX VrefLevel [Byte0]: 68
3480 12:42:28.153193 [Byte1]: 68
3481 12:42:28.157753
3482 12:42:28.157855 Set Vref, RX VrefLevel [Byte0]: 69
3483 12:42:28.161436 [Byte1]: 69
3484 12:42:28.165979
3485 12:42:28.166078 Set Vref, RX VrefLevel [Byte0]: 70
3486 12:42:28.168873 [Byte1]: 70
3487 12:42:28.173619
3488 12:42:28.173693 Set Vref, RX VrefLevel [Byte0]: 71
3489 12:42:28.177253 [Byte1]: 71
3490 12:42:28.181602
3491 12:42:28.181705 Final RX Vref Byte 0 = 57 to rank0
3492 12:42:28.185044 Final RX Vref Byte 1 = 49 to rank0
3493 12:42:28.188725 Final RX Vref Byte 0 = 57 to rank1
3494 12:42:28.191438 Final RX Vref Byte 1 = 49 to rank1==
3495 12:42:28.194910 Dram Type= 6, Freq= 0, CH_1, rank 0
3496 12:42:28.198383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3497 12:42:28.202161 ==
3498 12:42:28.202237 DQS Delay:
3499 12:42:28.202300 DQS0 = 0, DQS1 = 0
3500 12:42:28.205682 DQM Delay:
3501 12:42:28.205756 DQM0 = 116, DQM1 = 108
3502 12:42:28.208504 DQ Delay:
3503 12:42:28.212385 DQ0 =116, DQ1 =110, DQ2 =106, DQ3 =114
3504 12:42:28.215544 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =114
3505 12:42:28.218550 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =104
3506 12:42:28.222195 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =114
3507 12:42:28.222307
3508 12:42:28.222429
3509 12:42:28.228428 [DQSOSCAuto] RK0, (LSB)MR18= 0xfee3, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
3510 12:42:28.231877 CH1 RK0: MR19=303, MR18=FEE3
3511 12:42:28.238264 CH1_RK0: MR19=0x303, MR18=0xFEE3, DQSOSC=410, MR23=63, INC=39, DEC=26
3512 12:42:28.238365
3513 12:42:28.242072 ----->DramcWriteLeveling(PI) begin...
3514 12:42:28.242172 ==
3515 12:42:28.245031 Dram Type= 6, Freq= 0, CH_1, rank 1
3516 12:42:28.248600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3517 12:42:28.248694 ==
3518 12:42:28.251841 Write leveling (Byte 0): 26 => 26
3519 12:42:28.255992 Write leveling (Byte 1): 27 => 27
3520 12:42:28.258681 DramcWriteLeveling(PI) end<-----
3521 12:42:28.258777
3522 12:42:28.258864 ==
3523 12:42:28.262508 Dram Type= 6, Freq= 0, CH_1, rank 1
3524 12:42:28.265368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3525 12:42:28.268551 ==
3526 12:42:28.268647 [Gating] SW mode calibration
3527 12:42:28.276068 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3528 12:42:28.282004 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3529 12:42:28.285350 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3530 12:42:28.292243 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3531 12:42:28.295877 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3532 12:42:28.298756 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3533 12:42:28.305338 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3534 12:42:28.309024 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3535 12:42:28.312513 0 15 24 | B1->B0 | 3333 2727 | 1 1 | (1 1) (1 0)
3536 12:42:28.316076 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3537 12:42:28.322375 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3538 12:42:28.325993 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3539 12:42:28.328828 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3540 12:42:28.335622 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3541 12:42:28.338774 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3542 12:42:28.342224 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3543 12:42:28.348623 1 0 24 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
3544 12:42:28.352167 1 0 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
3545 12:42:28.355421 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3546 12:42:28.362084 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3547 12:42:28.365226 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3548 12:42:28.368883 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3549 12:42:28.376051 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3550 12:42:28.378914 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3551 12:42:28.382296 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3552 12:42:28.388956 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3553 12:42:28.392699 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 12:42:28.395433 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 12:42:28.402247 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 12:42:28.405788 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 12:42:28.408578 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 12:42:28.415761 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 12:42:28.418844 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 12:42:28.422561 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3561 12:42:28.425821 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3562 12:42:28.432653 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 12:42:28.435373 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 12:42:28.439139 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3565 12:42:28.445719 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3566 12:42:28.448603 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3567 12:42:28.451982 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3568 12:42:28.458790 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3569 12:42:28.462085 Total UI for P1: 0, mck2ui 16
3570 12:42:28.465504 best dqsien dly found for B0: ( 1, 3, 24)
3571 12:42:28.469204 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3572 12:42:28.471725 Total UI for P1: 0, mck2ui 16
3573 12:42:28.475277 best dqsien dly found for B1: ( 1, 3, 28)
3574 12:42:28.478383 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3575 12:42:28.481976 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3576 12:42:28.482077
3577 12:42:28.485768 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3578 12:42:28.489083 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3579 12:42:28.492272 [Gating] SW calibration Done
3580 12:42:28.492373 ==
3581 12:42:28.495183 Dram Type= 6, Freq= 0, CH_1, rank 1
3582 12:42:28.498636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3583 12:42:28.502472 ==
3584 12:42:28.502552 RX Vref Scan: 0
3585 12:42:28.502615
3586 12:42:28.505209 RX Vref 0 -> 0, step: 1
3587 12:42:28.505307
3588 12:42:28.508617 RX Delay -40 -> 252, step: 8
3589 12:42:28.512284 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3590 12:42:28.514846 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3591 12:42:28.518119 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3592 12:42:28.521945 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3593 12:42:28.528804 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3594 12:42:28.532193 iDelay=200, Bit 5, Center 123 (56 ~ 191) 136
3595 12:42:28.535665 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3596 12:42:28.538324 iDelay=200, Bit 7, Center 111 (48 ~ 175) 128
3597 12:42:28.541789 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3598 12:42:28.545575 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3599 12:42:28.551900 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3600 12:42:28.555121 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3601 12:42:28.558632 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3602 12:42:28.562068 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3603 12:42:28.565311 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3604 12:42:28.572192 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3605 12:42:28.572293 ==
3606 12:42:28.575074 Dram Type= 6, Freq= 0, CH_1, rank 1
3607 12:42:28.578512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3608 12:42:28.578584 ==
3609 12:42:28.578644 DQS Delay:
3610 12:42:28.581834 DQS0 = 0, DQS1 = 0
3611 12:42:28.581926 DQM Delay:
3612 12:42:28.585052 DQM0 = 114, DQM1 = 107
3613 12:42:28.585147 DQ Delay:
3614 12:42:28.588947 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =115
3615 12:42:28.592086 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3616 12:42:28.595932 DQ8 =95, DQ9 =99, DQ10 =107, DQ11 =99
3617 12:42:28.599216 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =115
3618 12:42:28.599315
3619 12:42:28.599406
3620 12:42:28.602566 ==
3621 12:42:28.602634 Dram Type= 6, Freq= 0, CH_1, rank 1
3622 12:42:28.608605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3623 12:42:28.608706 ==
3624 12:42:28.608796
3625 12:42:28.608882
3626 12:42:28.612411 TX Vref Scan disable
3627 12:42:28.612505 == TX Byte 0 ==
3628 12:42:28.615478 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3629 12:42:28.622578 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3630 12:42:28.622684 == TX Byte 1 ==
3631 12:42:28.625100 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3632 12:42:28.631976 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3633 12:42:28.632074 ==
3634 12:42:28.635100 Dram Type= 6, Freq= 0, CH_1, rank 1
3635 12:42:28.638463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3636 12:42:28.638536 ==
3637 12:42:28.650637 TX Vref=22, minBit 1, minWin=25, winSum=417
3638 12:42:28.653493 TX Vref=24, minBit 0, minWin=25, winSum=422
3639 12:42:28.657137 TX Vref=26, minBit 0, minWin=25, winSum=425
3640 12:42:28.660094 TX Vref=28, minBit 1, minWin=26, winSum=426
3641 12:42:28.663338 TX Vref=30, minBit 3, minWin=26, winSum=428
3642 12:42:28.670313 TX Vref=32, minBit 2, minWin=26, winSum=426
3643 12:42:28.673431 [TxChooseVref] Worse bit 3, Min win 26, Win sum 428, Final Vref 30
3644 12:42:28.673529
3645 12:42:28.677005 Final TX Range 1 Vref 30
3646 12:42:28.677099
3647 12:42:28.677186 ==
3648 12:42:28.680640 Dram Type= 6, Freq= 0, CH_1, rank 1
3649 12:42:28.683936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3650 12:42:28.684006 ==
3651 12:42:28.684065
3652 12:42:28.686735
3653 12:42:28.686806 TX Vref Scan disable
3654 12:42:28.690549 == TX Byte 0 ==
3655 12:42:28.693320 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3656 12:42:28.697008 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3657 12:42:28.700644 == TX Byte 1 ==
3658 12:42:28.703470 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3659 12:42:28.707899 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3660 12:42:28.707995
3661 12:42:28.710178 [DATLAT]
3662 12:42:28.710271 Freq=1200, CH1 RK1
3663 12:42:28.710356
3664 12:42:28.713936 DATLAT Default: 0xd
3665 12:42:28.714027 0, 0xFFFF, sum = 0
3666 12:42:28.716794 1, 0xFFFF, sum = 0
3667 12:42:28.716867 2, 0xFFFF, sum = 0
3668 12:42:28.720665 3, 0xFFFF, sum = 0
3669 12:42:28.720740 4, 0xFFFF, sum = 0
3670 12:42:28.723556 5, 0xFFFF, sum = 0
3671 12:42:28.723655 6, 0xFFFF, sum = 0
3672 12:42:28.727065 7, 0xFFFF, sum = 0
3673 12:42:28.727138 8, 0xFFFF, sum = 0
3674 12:42:28.730883 9, 0xFFFF, sum = 0
3675 12:42:28.733913 10, 0xFFFF, sum = 0
3676 12:42:28.734029 11, 0xFFFF, sum = 0
3677 12:42:28.737049 12, 0x0, sum = 1
3678 12:42:28.737152 13, 0x0, sum = 2
3679 12:42:28.737242 14, 0x0, sum = 3
3680 12:42:28.740148 15, 0x0, sum = 4
3681 12:42:28.740242 best_step = 13
3682 12:42:28.740329
3683 12:42:28.743414 ==
3684 12:42:28.743509 Dram Type= 6, Freq= 0, CH_1, rank 1
3685 12:42:28.750936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3686 12:42:28.751008 ==
3687 12:42:28.751073 RX Vref Scan: 0
3688 12:42:28.751145
3689 12:42:28.753383 RX Vref 0 -> 0, step: 1
3690 12:42:28.753473
3691 12:42:28.756814 RX Delay -21 -> 252, step: 4
3692 12:42:28.760691 iDelay=191, Bit 0, Center 114 (47 ~ 182) 136
3693 12:42:28.763927 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3694 12:42:28.770260 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3695 12:42:28.773506 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3696 12:42:28.776922 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3697 12:42:28.780157 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3698 12:42:28.783361 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3699 12:42:28.790453 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3700 12:42:28.793752 iDelay=191, Bit 8, Center 98 (35 ~ 162) 128
3701 12:42:28.797096 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3702 12:42:28.800357 iDelay=191, Bit 10, Center 108 (43 ~ 174) 132
3703 12:42:28.803586 iDelay=191, Bit 11, Center 100 (35 ~ 166) 132
3704 12:42:28.811148 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3705 12:42:28.814365 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3706 12:42:28.817574 iDelay=191, Bit 14, Center 116 (55 ~ 178) 124
3707 12:42:28.820523 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3708 12:42:28.820623 ==
3709 12:42:28.823675 Dram Type= 6, Freq= 0, CH_1, rank 1
3710 12:42:28.827114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3711 12:42:28.830492 ==
3712 12:42:28.830598 DQS Delay:
3713 12:42:28.830692 DQS0 = 0, DQS1 = 0
3714 12:42:28.833870 DQM Delay:
3715 12:42:28.833965 DQM0 = 113, DQM1 = 108
3716 12:42:28.836797 DQ Delay:
3717 12:42:28.840162 DQ0 =114, DQ1 =110, DQ2 =104, DQ3 =112
3718 12:42:28.843899 DQ4 =114, DQ5 =122, DQ6 =122, DQ7 =110
3719 12:42:28.846740 DQ8 =98, DQ9 =98, DQ10 =108, DQ11 =100
3720 12:42:28.850208 DQ12 =114, DQ13 =118, DQ14 =116, DQ15 =116
3721 12:42:28.850300
3722 12:42:28.850389
3723 12:42:28.856987 [DQSOSCAuto] RK1, (LSB)MR18= 0xf4fc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 415 ps
3724 12:42:28.860684 CH1 RK1: MR19=303, MR18=F4FC
3725 12:42:28.867049 CH1_RK1: MR19=0x303, MR18=0xF4FC, DQSOSC=411, MR23=63, INC=38, DEC=25
3726 12:42:28.871136 [RxdqsGatingPostProcess] freq 1200
3727 12:42:28.877517 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3728 12:42:28.880165 best DQS0 dly(2T, 0.5T) = (0, 11)
3729 12:42:28.880232 best DQS1 dly(2T, 0.5T) = (0, 11)
3730 12:42:28.883941 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3731 12:42:28.887259 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3732 12:42:28.890275 best DQS0 dly(2T, 0.5T) = (0, 11)
3733 12:42:28.893744 best DQS1 dly(2T, 0.5T) = (0, 11)
3734 12:42:28.896993 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3735 12:42:28.900134 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3736 12:42:28.903557 Pre-setting of DQS Precalculation
3737 12:42:28.910552 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3738 12:42:28.917142 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3739 12:42:28.923446 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3740 12:42:28.923522
3741 12:42:28.923587
3742 12:42:28.926992 [Calibration Summary] 2400 Mbps
3743 12:42:28.927091 CH 0, Rank 0
3744 12:42:28.930840 SW Impedance : PASS
3745 12:42:28.933837 DUTY Scan : NO K
3746 12:42:28.933942 ZQ Calibration : PASS
3747 12:42:28.936965 Jitter Meter : NO K
3748 12:42:28.937069 CBT Training : PASS
3749 12:42:28.940965 Write leveling : PASS
3750 12:42:28.943924 RX DQS gating : PASS
3751 12:42:28.944002 RX DQ/DQS(RDDQC) : PASS
3752 12:42:28.947346 TX DQ/DQS : PASS
3753 12:42:28.950541 RX DATLAT : PASS
3754 12:42:28.950646 RX DQ/DQS(Engine): PASS
3755 12:42:28.953697 TX OE : NO K
3756 12:42:28.953799 All Pass.
3757 12:42:28.953892
3758 12:42:28.957208 CH 0, Rank 1
3759 12:42:28.957286 SW Impedance : PASS
3760 12:42:28.960563 DUTY Scan : NO K
3761 12:42:28.964289 ZQ Calibration : PASS
3762 12:42:28.964393 Jitter Meter : NO K
3763 12:42:28.966784 CBT Training : PASS
3764 12:42:28.970692 Write leveling : PASS
3765 12:42:28.970791 RX DQS gating : PASS
3766 12:42:28.973521 RX DQ/DQS(RDDQC) : PASS
3767 12:42:28.977315 TX DQ/DQS : PASS
3768 12:42:28.977390 RX DATLAT : PASS
3769 12:42:28.980351 RX DQ/DQS(Engine): PASS
3770 12:42:28.980454 TX OE : NO K
3771 12:42:28.983641 All Pass.
3772 12:42:28.983725
3773 12:42:28.983828 CH 1, Rank 0
3774 12:42:28.987026 SW Impedance : PASS
3775 12:42:28.987104 DUTY Scan : NO K
3776 12:42:28.990449 ZQ Calibration : PASS
3777 12:42:28.994211 Jitter Meter : NO K
3778 12:42:28.994308 CBT Training : PASS
3779 12:42:28.996994 Write leveling : PASS
3780 12:42:29.000160 RX DQS gating : PASS
3781 12:42:29.000239 RX DQ/DQS(RDDQC) : PASS
3782 12:42:29.003638 TX DQ/DQS : PASS
3783 12:42:29.006875 RX DATLAT : PASS
3784 12:42:29.006971 RX DQ/DQS(Engine): PASS
3785 12:42:29.010332 TX OE : NO K
3786 12:42:29.010432 All Pass.
3787 12:42:29.010503
3788 12:42:29.013511 CH 1, Rank 1
3789 12:42:29.013612 SW Impedance : PASS
3790 12:42:29.017110 DUTY Scan : NO K
3791 12:42:29.020307 ZQ Calibration : PASS
3792 12:42:29.020380 Jitter Meter : NO K
3793 12:42:29.023823 CBT Training : PASS
3794 12:42:29.026901 Write leveling : PASS
3795 12:42:29.027006 RX DQS gating : PASS
3796 12:42:29.030296 RX DQ/DQS(RDDQC) : PASS
3797 12:42:29.030424 TX DQ/DQS : PASS
3798 12:42:29.033723 RX DATLAT : PASS
3799 12:42:29.037148 RX DQ/DQS(Engine): PASS
3800 12:42:29.037246 TX OE : NO K
3801 12:42:29.040567 All Pass.
3802 12:42:29.040663
3803 12:42:29.040751 DramC Write-DBI off
3804 12:42:29.043588 PER_BANK_REFRESH: Hybrid Mode
3805 12:42:29.047263 TX_TRACKING: ON
3806 12:42:29.053883 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3807 12:42:29.056671 [FAST_K] Save calibration result to emmc
3808 12:42:29.060307 dramc_set_vcore_voltage set vcore to 650000
3809 12:42:29.063626 Read voltage for 600, 5
3810 12:42:29.063697 Vio18 = 0
3811 12:42:29.066855 Vcore = 650000
3812 12:42:29.066934 Vdram = 0
3813 12:42:29.066996 Vddq = 0
3814 12:42:29.070342 Vmddr = 0
3815 12:42:29.073931 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3816 12:42:29.080248 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3817 12:42:29.080348 MEM_TYPE=3, freq_sel=19
3818 12:42:29.083399 sv_algorithm_assistance_LP4_1600
3819 12:42:29.090294 ============ PULL DRAM RESETB DOWN ============
3820 12:42:29.093401 ========== PULL DRAM RESETB DOWN end =========
3821 12:42:29.096920 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3822 12:42:29.100458 ===================================
3823 12:42:29.103266 LPDDR4 DRAM CONFIGURATION
3824 12:42:29.106995 ===================================
3825 12:42:29.107068 EX_ROW_EN[0] = 0x0
3826 12:42:29.109916 EX_ROW_EN[1] = 0x0
3827 12:42:29.113456 LP4Y_EN = 0x0
3828 12:42:29.113561 WORK_FSP = 0x0
3829 12:42:29.117185 WL = 0x2
3830 12:42:29.117283 RL = 0x2
3831 12:42:29.120450 BL = 0x2
3832 12:42:29.120548 RPST = 0x0
3833 12:42:29.123742 RD_PRE = 0x0
3834 12:42:29.123847 WR_PRE = 0x1
3835 12:42:29.126857 WR_PST = 0x0
3836 12:42:29.126929 DBI_WR = 0x0
3837 12:42:29.130101 DBI_RD = 0x0
3838 12:42:29.130201 OTF = 0x1
3839 12:42:29.133539 ===================================
3840 12:42:29.137393 ===================================
3841 12:42:29.140334 ANA top config
3842 12:42:29.143736 ===================================
3843 12:42:29.143837 DLL_ASYNC_EN = 0
3844 12:42:29.147174 ALL_SLAVE_EN = 1
3845 12:42:29.150149 NEW_RANK_MODE = 1
3846 12:42:29.153612 DLL_IDLE_MODE = 1
3847 12:42:29.153707 LP45_APHY_COMB_EN = 1
3848 12:42:29.156802 TX_ODT_DIS = 1
3849 12:42:29.160051 NEW_8X_MODE = 1
3850 12:42:29.163410 ===================================
3851 12:42:29.167012 ===================================
3852 12:42:29.170320 data_rate = 1200
3853 12:42:29.174098 CKR = 1
3854 12:42:29.177004 DQ_P2S_RATIO = 8
3855 12:42:29.177102 ===================================
3856 12:42:29.180013 CA_P2S_RATIO = 8
3857 12:42:29.183299 DQ_CA_OPEN = 0
3858 12:42:29.187367 DQ_SEMI_OPEN = 0
3859 12:42:29.190109 CA_SEMI_OPEN = 0
3860 12:42:29.194209 CA_FULL_RATE = 0
3861 12:42:29.194299 DQ_CKDIV4_EN = 1
3862 12:42:29.196775 CA_CKDIV4_EN = 1
3863 12:42:29.200181 CA_PREDIV_EN = 0
3864 12:42:29.204088 PH8_DLY = 0
3865 12:42:29.206893 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3866 12:42:29.209989 DQ_AAMCK_DIV = 4
3867 12:42:29.210072 CA_AAMCK_DIV = 4
3868 12:42:29.213396 CA_ADMCK_DIV = 4
3869 12:42:29.216992 DQ_TRACK_CA_EN = 0
3870 12:42:29.220243 CA_PICK = 600
3871 12:42:29.223897 CA_MCKIO = 600
3872 12:42:29.227194 MCKIO_SEMI = 0
3873 12:42:29.231045 PLL_FREQ = 2288
3874 12:42:29.231150 DQ_UI_PI_RATIO = 32
3875 12:42:29.233745 CA_UI_PI_RATIO = 0
3876 12:42:29.237208 ===================================
3877 12:42:29.240648 ===================================
3878 12:42:29.243620 memory_type:LPDDR4
3879 12:42:29.247258 GP_NUM : 10
3880 12:42:29.247329 SRAM_EN : 1
3881 12:42:29.250546 MD32_EN : 0
3882 12:42:29.253672 ===================================
3883 12:42:29.253775 [ANA_INIT] >>>>>>>>>>>>>>
3884 12:42:29.257500 <<<<<< [CONFIGURE PHASE]: ANA_TX
3885 12:42:29.260413 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3886 12:42:29.263781 ===================================
3887 12:42:29.267834 data_rate = 1200,PCW = 0X5800
3888 12:42:29.270811 ===================================
3889 12:42:29.273776 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3890 12:42:29.280691 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3891 12:42:29.284139 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3892 12:42:29.291568 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3893 12:42:29.294388 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3894 12:42:29.297634 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3895 12:42:29.297706 [ANA_INIT] flow start
3896 12:42:29.300775 [ANA_INIT] PLL >>>>>>>>
3897 12:42:29.304316 [ANA_INIT] PLL <<<<<<<<
3898 12:42:29.307982 [ANA_INIT] MIDPI >>>>>>>>
3899 12:42:29.308078 [ANA_INIT] MIDPI <<<<<<<<
3900 12:42:29.310504 [ANA_INIT] DLL >>>>>>>>
3901 12:42:29.310573 [ANA_INIT] flow end
3902 12:42:29.317957 ============ LP4 DIFF to SE enter ============
3903 12:42:29.321005 ============ LP4 DIFF to SE exit ============
3904 12:42:29.324000 [ANA_INIT] <<<<<<<<<<<<<
3905 12:42:29.327421 [Flow] Enable top DCM control >>>>>
3906 12:42:29.331153 [Flow] Enable top DCM control <<<<<
3907 12:42:29.331248 Enable DLL master slave shuffle
3908 12:42:29.337527 ==============================================================
3909 12:42:29.340636 Gating Mode config
3910 12:42:29.343935 ==============================================================
3911 12:42:29.347595 Config description:
3912 12:42:29.357341 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3913 12:42:29.363963 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3914 12:42:29.367958 SELPH_MODE 0: By rank 1: By Phase
3915 12:42:29.374013 ==============================================================
3916 12:42:29.377871 GAT_TRACK_EN = 1
3917 12:42:29.381172 RX_GATING_MODE = 2
3918 12:42:29.384121 RX_GATING_TRACK_MODE = 2
3919 12:42:29.384233 SELPH_MODE = 1
3920 12:42:29.387583 PICG_EARLY_EN = 1
3921 12:42:29.391183 VALID_LAT_VALUE = 1
3922 12:42:29.397441 ==============================================================
3923 12:42:29.400906 Enter into Gating configuration >>>>
3924 12:42:29.404331 Exit from Gating configuration <<<<
3925 12:42:29.407887 Enter into DVFS_PRE_config >>>>>
3926 12:42:29.417694 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3927 12:42:29.420925 Exit from DVFS_PRE_config <<<<<
3928 12:42:29.424571 Enter into PICG configuration >>>>
3929 12:42:29.427684 Exit from PICG configuration <<<<
3930 12:42:29.430708 [RX_INPUT] configuration >>>>>
3931 12:42:29.434574 [RX_INPUT] configuration <<<<<
3932 12:42:29.437254 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3933 12:42:29.444133 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3934 12:42:29.450449 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3935 12:42:29.457885 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3936 12:42:29.460984 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3937 12:42:29.467750 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3938 12:42:29.470887 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3939 12:42:29.477345 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3940 12:42:29.480946 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3941 12:42:29.484458 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3942 12:42:29.487440 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3943 12:42:29.494672 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3944 12:42:29.497562 ===================================
3945 12:42:29.497660 LPDDR4 DRAM CONFIGURATION
3946 12:42:29.501303 ===================================
3947 12:42:29.504016 EX_ROW_EN[0] = 0x0
3948 12:42:29.507588 EX_ROW_EN[1] = 0x0
3949 12:42:29.507658 LP4Y_EN = 0x0
3950 12:42:29.511420 WORK_FSP = 0x0
3951 12:42:29.511492 WL = 0x2
3952 12:42:29.514092 RL = 0x2
3953 12:42:29.514194 BL = 0x2
3954 12:42:29.517364 RPST = 0x0
3955 12:42:29.517460 RD_PRE = 0x0
3956 12:42:29.521270 WR_PRE = 0x1
3957 12:42:29.521341 WR_PST = 0x0
3958 12:42:29.524411 DBI_WR = 0x0
3959 12:42:29.524498 DBI_RD = 0x0
3960 12:42:29.527484 OTF = 0x1
3961 12:42:29.531253 ===================================
3962 12:42:29.534232 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3963 12:42:29.537400 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3964 12:42:29.544154 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3965 12:42:29.547833 ===================================
3966 12:42:29.547931 LPDDR4 DRAM CONFIGURATION
3967 12:42:29.551542 ===================================
3968 12:42:29.554518 EX_ROW_EN[0] = 0x10
3969 12:42:29.554589 EX_ROW_EN[1] = 0x0
3970 12:42:29.557746 LP4Y_EN = 0x0
3971 12:42:29.557815 WORK_FSP = 0x0
3972 12:42:29.561383 WL = 0x2
3973 12:42:29.561478 RL = 0x2
3974 12:42:29.564383 BL = 0x2
3975 12:42:29.564478 RPST = 0x0
3976 12:42:29.567737 RD_PRE = 0x0
3977 12:42:29.570957 WR_PRE = 0x1
3978 12:42:29.571062 WR_PST = 0x0
3979 12:42:29.574628 DBI_WR = 0x0
3980 12:42:29.574725 DBI_RD = 0x0
3981 12:42:29.577937 OTF = 0x1
3982 12:42:29.581354 ===================================
3983 12:42:29.585097 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3984 12:42:29.589927 nWR fixed to 30
3985 12:42:29.592981 [ModeRegInit_LP4] CH0 RK0
3986 12:42:29.593066 [ModeRegInit_LP4] CH0 RK1
3987 12:42:29.596375 [ModeRegInit_LP4] CH1 RK0
3988 12:42:29.599580 [ModeRegInit_LP4] CH1 RK1
3989 12:42:29.599661 match AC timing 17
3990 12:42:29.606549 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3991 12:42:29.609830 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3992 12:42:29.613045 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3993 12:42:29.619565 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3994 12:42:29.622796 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3995 12:42:29.622896 ==
3996 12:42:29.626393 Dram Type= 6, Freq= 0, CH_0, rank 0
3997 12:42:29.629543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3998 12:42:29.629624 ==
3999 12:42:29.636775 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4000 12:42:29.642781 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4001 12:42:29.646354 [CA 0] Center 36 (6~66) winsize 61
4002 12:42:29.649769 [CA 1] Center 36 (6~66) winsize 61
4003 12:42:29.652994 [CA 2] Center 34 (4~65) winsize 62
4004 12:42:29.656255 [CA 3] Center 34 (4~65) winsize 62
4005 12:42:29.659493 [CA 4] Center 34 (4~64) winsize 61
4006 12:42:29.663544 [CA 5] Center 33 (3~64) winsize 62
4007 12:42:29.663646
4008 12:42:29.666905 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4009 12:42:29.666978
4010 12:42:29.669491 [CATrainingPosCal] consider 1 rank data
4011 12:42:29.672889 u2DelayCellTimex100 = 270/100 ps
4012 12:42:29.676736 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4013 12:42:29.679842 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4014 12:42:29.682984 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4015 12:42:29.686645 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4016 12:42:29.690066 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4017 12:42:29.693509 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4018 12:42:29.693581
4019 12:42:29.699958 CA PerBit enable=1, Macro0, CA PI delay=33
4020 12:42:29.700031
4021 12:42:29.700094 [CBTSetCACLKResult] CA Dly = 33
4022 12:42:29.703234 CS Dly: 5 (0~36)
4023 12:42:29.703313 ==
4024 12:42:29.706765 Dram Type= 6, Freq= 0, CH_0, rank 1
4025 12:42:29.710135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4026 12:42:29.710206 ==
4027 12:42:29.716281 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4028 12:42:29.723453 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4029 12:42:29.726522 [CA 0] Center 36 (6~66) winsize 61
4030 12:42:29.729628 [CA 1] Center 36 (6~66) winsize 61
4031 12:42:29.733355 [CA 2] Center 34 (4~65) winsize 62
4032 12:42:29.736285 [CA 3] Center 34 (4~65) winsize 62
4033 12:42:29.740538 [CA 4] Center 33 (3~64) winsize 62
4034 12:42:29.743174 [CA 5] Center 33 (3~64) winsize 62
4035 12:42:29.743251
4036 12:42:29.746251 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4037 12:42:29.746346
4038 12:42:29.750466 [CATrainingPosCal] consider 2 rank data
4039 12:42:29.753259 u2DelayCellTimex100 = 270/100 ps
4040 12:42:29.756538 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4041 12:42:29.759539 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4042 12:42:29.762856 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4043 12:42:29.767188 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4044 12:42:29.769789 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4045 12:42:29.773393 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4046 12:42:29.773492
4047 12:42:29.780263 CA PerBit enable=1, Macro0, CA PI delay=33
4048 12:42:29.780364
4049 12:42:29.780456 [CBTSetCACLKResult] CA Dly = 33
4050 12:42:29.783028 CS Dly: 4 (0~35)
4051 12:42:29.783126
4052 12:42:29.786388 ----->DramcWriteLeveling(PI) begin...
4053 12:42:29.786484 ==
4054 12:42:29.789513 Dram Type= 6, Freq= 0, CH_0, rank 0
4055 12:42:29.792966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4056 12:42:29.793049 ==
4057 12:42:29.796315 Write leveling (Byte 0): 32 => 32
4058 12:42:29.799718 Write leveling (Byte 1): 30 => 30
4059 12:42:29.803117 DramcWriteLeveling(PI) end<-----
4060 12:42:29.803220
4061 12:42:29.803310 ==
4062 12:42:29.806108 Dram Type= 6, Freq= 0, CH_0, rank 0
4063 12:42:29.813105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4064 12:42:29.813218 ==
4065 12:42:29.813370 [Gating] SW mode calibration
4066 12:42:29.823181 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4067 12:42:29.826003 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4068 12:42:29.829582 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4069 12:42:29.836271 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4070 12:42:29.839581 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4071 12:42:29.842970 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4072 12:42:29.849372 0 9 16 | B1->B0 | 3030 2a2a | 0 0 | (1 0) (0 0)
4073 12:42:29.852995 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4074 12:42:29.855877 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4075 12:42:29.862646 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4076 12:42:29.866094 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4077 12:42:29.869132 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4078 12:42:29.875763 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4079 12:42:29.880067 0 10 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4080 12:42:29.882873 0 10 16 | B1->B0 | 2f2f 3b3b | 0 1 | (0 0) (0 0)
4081 12:42:29.889362 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4082 12:42:29.893660 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4083 12:42:29.895995 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4084 12:42:29.899319 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4085 12:42:29.906325 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4086 12:42:29.909602 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4087 12:42:29.913409 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4088 12:42:29.919394 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4089 12:42:29.923181 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 12:42:29.926069 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 12:42:29.933451 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 12:42:29.936103 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 12:42:29.939488 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 12:42:29.946268 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 12:42:29.949480 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 12:42:29.952672 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4097 12:42:29.959464 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 12:42:29.962704 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 12:42:29.966174 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 12:42:29.972772 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4101 12:42:29.976057 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4102 12:42:29.979995 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4103 12:42:29.983147 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4104 12:42:29.989394 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4105 12:42:29.992828 Total UI for P1: 0, mck2ui 16
4106 12:42:29.996374 best dqsien dly found for B0: ( 0, 13, 12)
4107 12:42:29.999566 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4108 12:42:30.002910 Total UI for P1: 0, mck2ui 16
4109 12:42:30.006466 best dqsien dly found for B1: ( 0, 13, 14)
4110 12:42:30.009805 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4111 12:42:30.013269 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4112 12:42:30.013371
4113 12:42:30.016369 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4114 12:42:30.020049 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4115 12:42:30.023323 [Gating] SW calibration Done
4116 12:42:30.023428 ==
4117 12:42:30.026063 Dram Type= 6, Freq= 0, CH_0, rank 0
4118 12:42:30.032923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4119 12:42:30.033028 ==
4120 12:42:30.033119 RX Vref Scan: 0
4121 12:42:30.033209
4122 12:42:30.036160 RX Vref 0 -> 0, step: 1
4123 12:42:30.036264
4124 12:42:30.039913 RX Delay -230 -> 252, step: 16
4125 12:42:30.043079 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4126 12:42:30.046339 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4127 12:42:30.049634 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4128 12:42:30.056280 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4129 12:42:30.059532 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4130 12:42:30.062898 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4131 12:42:30.066304 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4132 12:42:30.069587 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4133 12:42:30.076175 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4134 12:42:30.079666 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4135 12:42:30.083201 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4136 12:42:30.086663 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4137 12:42:30.092920 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4138 12:42:30.096623 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4139 12:42:30.099661 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4140 12:42:30.103371 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4141 12:42:30.103498 ==
4142 12:42:30.106141 Dram Type= 6, Freq= 0, CH_0, rank 0
4143 12:42:30.113166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4144 12:42:30.113270 ==
4145 12:42:30.113362 DQS Delay:
4146 12:42:30.116446 DQS0 = 0, DQS1 = 0
4147 12:42:30.116558 DQM Delay:
4148 12:42:30.116664 DQM0 = 42, DQM1 = 35
4149 12:42:30.120066 DQ Delay:
4150 12:42:30.123537 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4151 12:42:30.123636 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4152 12:42:30.126720 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =25
4153 12:42:30.133715 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4154 12:42:30.133795
4155 12:42:30.133858
4156 12:42:30.133976 ==
4157 12:42:30.137011 Dram Type= 6, Freq= 0, CH_0, rank 0
4158 12:42:30.139805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4159 12:42:30.139905 ==
4160 12:42:30.139994
4161 12:42:30.140081
4162 12:42:30.143082 TX Vref Scan disable
4163 12:42:30.143181 == TX Byte 0 ==
4164 12:42:30.149972 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4165 12:42:30.153254 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4166 12:42:30.153360 == TX Byte 1 ==
4167 12:42:30.159977 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4168 12:42:30.163121 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4169 12:42:30.163226 ==
4170 12:42:30.166531 Dram Type= 6, Freq= 0, CH_0, rank 0
4171 12:42:30.169792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4172 12:42:30.169909 ==
4173 12:42:30.170012
4174 12:42:30.170097
4175 12:42:30.173287 TX Vref Scan disable
4176 12:42:30.176414 == TX Byte 0 ==
4177 12:42:30.179784 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4178 12:42:30.183092 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4179 12:42:30.186898 == TX Byte 1 ==
4180 12:42:30.189936 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4181 12:42:30.193181 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4182 12:42:30.193280
4183 12:42:30.196540 [DATLAT]
4184 12:42:30.196635 Freq=600, CH0 RK0
4185 12:42:30.196722
4186 12:42:30.199761 DATLAT Default: 0x9
4187 12:42:30.199831 0, 0xFFFF, sum = 0
4188 12:42:30.203115 1, 0xFFFF, sum = 0
4189 12:42:30.203191 2, 0xFFFF, sum = 0
4190 12:42:30.206677 3, 0xFFFF, sum = 0
4191 12:42:30.206752 4, 0xFFFF, sum = 0
4192 12:42:30.210228 5, 0xFFFF, sum = 0
4193 12:42:30.210324 6, 0xFFFF, sum = 0
4194 12:42:30.213476 7, 0xFFFF, sum = 0
4195 12:42:30.213553 8, 0x0, sum = 1
4196 12:42:30.216527 9, 0x0, sum = 2
4197 12:42:30.216629 10, 0x0, sum = 3
4198 12:42:30.219596 11, 0x0, sum = 4
4199 12:42:30.219698 best_step = 9
4200 12:42:30.219790
4201 12:42:30.219875 ==
4202 12:42:30.223314 Dram Type= 6, Freq= 0, CH_0, rank 0
4203 12:42:30.229912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4204 12:42:30.230017 ==
4205 12:42:30.230126 RX Vref Scan: 1
4206 12:42:30.230218
4207 12:42:30.232842 RX Vref 0 -> 0, step: 1
4208 12:42:30.232944
4209 12:42:30.236374 RX Delay -195 -> 252, step: 8
4210 12:42:30.236459
4211 12:42:30.240172 Set Vref, RX VrefLevel [Byte0]: 54
4212 12:42:30.242851 [Byte1]: 50
4213 12:42:30.242949
4214 12:42:30.246760 Final RX Vref Byte 0 = 54 to rank0
4215 12:42:30.249827 Final RX Vref Byte 1 = 50 to rank0
4216 12:42:30.253001 Final RX Vref Byte 0 = 54 to rank1
4217 12:42:30.256254 Final RX Vref Byte 1 = 50 to rank1==
4218 12:42:30.259350 Dram Type= 6, Freq= 0, CH_0, rank 0
4219 12:42:30.262772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4220 12:42:30.262848 ==
4221 12:42:30.266402 DQS Delay:
4222 12:42:30.266488 DQS0 = 0, DQS1 = 0
4223 12:42:30.266551 DQM Delay:
4224 12:42:30.269986 DQM0 = 43, DQM1 = 33
4225 12:42:30.270053 DQ Delay:
4226 12:42:30.272686 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4227 12:42:30.276224 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4228 12:42:30.279371 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4229 12:42:30.283191 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4230 12:42:30.283265
4231 12:42:30.283325
4232 12:42:30.292890 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e1d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
4233 12:42:30.292971 CH0 RK0: MR19=808, MR18=3E1D
4234 12:42:30.299417 CH0_RK0: MR19=0x808, MR18=0x3E1D, DQSOSC=398, MR23=63, INC=165, DEC=110
4235 12:42:30.299493
4236 12:42:30.303234 ----->DramcWriteLeveling(PI) begin...
4237 12:42:30.305959 ==
4238 12:42:30.309423 Dram Type= 6, Freq= 0, CH_0, rank 1
4239 12:42:30.312610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4240 12:42:30.312710 ==
4241 12:42:30.316137 Write leveling (Byte 0): 32 => 32
4242 12:42:30.319657 Write leveling (Byte 1): 32 => 32
4243 12:42:30.322838 DramcWriteLeveling(PI) end<-----
4244 12:42:30.322935
4245 12:42:30.323028 ==
4246 12:42:30.325966 Dram Type= 6, Freq= 0, CH_0, rank 1
4247 12:42:30.329209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4248 12:42:30.329319 ==
4249 12:42:30.332617 [Gating] SW mode calibration
4250 12:42:30.339319 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4251 12:42:30.343481 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4252 12:42:30.349108 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4253 12:42:30.352961 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4254 12:42:30.356159 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4255 12:42:30.362683 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
4256 12:42:30.366068 0 9 16 | B1->B0 | 3030 2323 | 1 0 | (0 0) (0 0)
4257 12:42:30.369260 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4258 12:42:30.375842 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4259 12:42:30.379417 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4260 12:42:30.382552 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4261 12:42:30.389399 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4262 12:42:30.392557 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4263 12:42:30.396261 0 10 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (1 1)
4264 12:42:30.402425 0 10 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
4265 12:42:30.406087 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4266 12:42:30.409662 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4267 12:42:30.416145 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4268 12:42:30.419555 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4269 12:42:30.422654 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4270 12:42:30.429208 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4271 12:42:30.432578 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4272 12:42:30.435592 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4273 12:42:30.442607 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 12:42:30.445972 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 12:42:30.449449 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 12:42:30.455635 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 12:42:30.459029 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 12:42:30.462453 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 12:42:30.466315 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 12:42:30.472209 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 12:42:30.475675 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 12:42:30.479288 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 12:42:30.485923 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 12:42:30.489476 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 12:42:30.492858 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 12:42:30.499046 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 12:42:30.502978 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 12:42:30.506508 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4289 12:42:30.509633 Total UI for P1: 0, mck2ui 16
4290 12:42:30.512706 best dqsien dly found for B0: ( 0, 13, 14)
4291 12:42:30.515773 Total UI for P1: 0, mck2ui 16
4292 12:42:30.519125 best dqsien dly found for B1: ( 0, 13, 14)
4293 12:42:30.522714 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4294 12:42:30.526115 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4295 12:42:30.526190
4296 12:42:30.532824 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4297 12:42:30.536206 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4298 12:42:30.536318 [Gating] SW calibration Done
4299 12:42:30.539185 ==
4300 12:42:30.542640 Dram Type= 6, Freq= 0, CH_0, rank 1
4301 12:42:30.545809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4302 12:42:30.545907 ==
4303 12:42:30.545997 RX Vref Scan: 0
4304 12:42:30.546083
4305 12:42:30.549000 RX Vref 0 -> 0, step: 1
4306 12:42:30.549095
4307 12:42:30.552305 RX Delay -230 -> 252, step: 16
4308 12:42:30.556297 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4309 12:42:30.559515 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4310 12:42:30.565712 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4311 12:42:30.569051 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4312 12:42:30.572620 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4313 12:42:30.575636 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4314 12:42:30.579099 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4315 12:42:30.586242 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4316 12:42:30.589561 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4317 12:42:30.592977 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4318 12:42:30.596136 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4319 12:42:30.602343 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4320 12:42:30.605505 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4321 12:42:30.609026 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4322 12:42:30.612633 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4323 12:42:30.619512 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4324 12:42:30.619612 ==
4325 12:42:30.622431 Dram Type= 6, Freq= 0, CH_0, rank 1
4326 12:42:30.625808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4327 12:42:30.625908 ==
4328 12:42:30.625997 DQS Delay:
4329 12:42:30.629341 DQS0 = 0, DQS1 = 0
4330 12:42:30.629439 DQM Delay:
4331 12:42:30.632582 DQM0 = 40, DQM1 = 33
4332 12:42:30.632683 DQ Delay:
4333 12:42:30.636222 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4334 12:42:30.639021 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4335 12:42:30.642528 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4336 12:42:30.645664 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4337 12:42:30.645762
4338 12:42:30.645860
4339 12:42:30.645946 ==
4340 12:42:30.649196 Dram Type= 6, Freq= 0, CH_0, rank 1
4341 12:42:30.652794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 12:42:30.652897 ==
4343 12:42:30.652989
4344 12:42:30.653074
4345 12:42:30.655988 TX Vref Scan disable
4346 12:42:30.659008 == TX Byte 0 ==
4347 12:42:30.662761 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4348 12:42:30.666260 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4349 12:42:30.669201 == TX Byte 1 ==
4350 12:42:30.672623 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4351 12:42:30.676159 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4352 12:42:30.676264 ==
4353 12:42:30.679165 Dram Type= 6, Freq= 0, CH_0, rank 1
4354 12:42:30.686348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4355 12:42:30.686496 ==
4356 12:42:30.686586
4357 12:42:30.686682
4358 12:42:30.686767 TX Vref Scan disable
4359 12:42:30.690217 == TX Byte 0 ==
4360 12:42:30.693073 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4361 12:42:30.699520 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4362 12:42:30.699598 == TX Byte 1 ==
4363 12:42:30.703015 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4364 12:42:30.709548 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4365 12:42:30.709662
4366 12:42:30.709764 [DATLAT]
4367 12:42:30.709875 Freq=600, CH0 RK1
4368 12:42:30.709960
4369 12:42:30.713068 DATLAT Default: 0x9
4370 12:42:30.713164 0, 0xFFFF, sum = 0
4371 12:42:30.716642 1, 0xFFFF, sum = 0
4372 12:42:30.716716 2, 0xFFFF, sum = 0
4373 12:42:30.719902 3, 0xFFFF, sum = 0
4374 12:42:30.720006 4, 0xFFFF, sum = 0
4375 12:42:30.723082 5, 0xFFFF, sum = 0
4376 12:42:30.723195 6, 0xFFFF, sum = 0
4377 12:42:30.726767 7, 0xFFFF, sum = 0
4378 12:42:30.726836 8, 0x0, sum = 1
4379 12:42:30.730465 9, 0x0, sum = 2
4380 12:42:30.730561 10, 0x0, sum = 3
4381 12:42:30.733396 11, 0x0, sum = 4
4382 12:42:30.733495 best_step = 9
4383 12:42:30.733570
4384 12:42:30.733628 ==
4385 12:42:30.737334 Dram Type= 6, Freq= 0, CH_0, rank 1
4386 12:42:30.743123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4387 12:42:30.743220 ==
4388 12:42:30.743318 RX Vref Scan: 0
4389 12:42:30.743404
4390 12:42:30.746724 RX Vref 0 -> 0, step: 1
4391 12:42:30.746818
4392 12:42:30.750034 RX Delay -195 -> 252, step: 8
4393 12:42:30.753378 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4394 12:42:30.760186 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4395 12:42:30.763014 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4396 12:42:30.766348 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4397 12:42:30.769584 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4398 12:42:30.773395 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4399 12:42:30.779743 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4400 12:42:30.783185 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4401 12:42:30.786770 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4402 12:42:30.789949 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4403 12:42:30.793200 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4404 12:42:30.800305 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4405 12:42:30.803282 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4406 12:42:30.806775 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4407 12:42:30.809824 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4408 12:42:30.816312 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4409 12:42:30.816387 ==
4410 12:42:30.819859 Dram Type= 6, Freq= 0, CH_0, rank 1
4411 12:42:30.823471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 12:42:30.823547 ==
4413 12:42:30.823633 DQS Delay:
4414 12:42:30.826991 DQS0 = 0, DQS1 = 0
4415 12:42:30.827062 DQM Delay:
4416 12:42:30.830213 DQM0 = 39, DQM1 = 33
4417 12:42:30.830308 DQ Delay:
4418 12:42:30.833588 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4419 12:42:30.836984 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =44
4420 12:42:30.839784 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =20
4421 12:42:30.843206 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44
4422 12:42:30.843300
4423 12:42:30.843385
4424 12:42:30.849773 [DQSOSCAuto] RK1, (LSB)MR18= 0x4527, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4425 12:42:30.853623 CH0 RK1: MR19=808, MR18=4527
4426 12:42:30.860312 CH0_RK1: MR19=0x808, MR18=0x4527, DQSOSC=396, MR23=63, INC=167, DEC=111
4427 12:42:30.863196 [RxdqsGatingPostProcess] freq 600
4428 12:42:30.869810 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4429 12:42:30.873126 Pre-setting of DQS Precalculation
4430 12:42:30.876530 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4431 12:42:30.876630 ==
4432 12:42:30.880956 Dram Type= 6, Freq= 0, CH_1, rank 0
4433 12:42:30.883508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4434 12:42:30.883596 ==
4435 12:42:30.890319 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4436 12:42:30.896935 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4437 12:42:30.900331 [CA 0] Center 35 (5~65) winsize 61
4438 12:42:30.903572 [CA 1] Center 35 (5~65) winsize 61
4439 12:42:30.907142 [CA 2] Center 34 (4~65) winsize 62
4440 12:42:30.909889 [CA 3] Center 33 (3~64) winsize 62
4441 12:42:30.913352 [CA 4] Center 34 (3~65) winsize 63
4442 12:42:30.916763 [CA 5] Center 33 (3~64) winsize 62
4443 12:42:30.916859
4444 12:42:30.920389 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4445 12:42:30.920484
4446 12:42:30.923282 [CATrainingPosCal] consider 1 rank data
4447 12:42:30.926519 u2DelayCellTimex100 = 270/100 ps
4448 12:42:30.930215 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4449 12:42:30.933533 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4450 12:42:30.936444 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4451 12:42:30.940026 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4452 12:42:30.943408 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4453 12:42:30.946596 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4454 12:42:30.946695
4455 12:42:30.953601 CA PerBit enable=1, Macro0, CA PI delay=33
4456 12:42:30.953717
4457 12:42:30.956429 [CBTSetCACLKResult] CA Dly = 33
4458 12:42:30.956525 CS Dly: 4 (0~35)
4459 12:42:30.956614 ==
4460 12:42:30.960325 Dram Type= 6, Freq= 0, CH_1, rank 1
4461 12:42:30.963392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4462 12:42:30.963489 ==
4463 12:42:30.969995 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4464 12:42:30.976664 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4465 12:42:30.980095 [CA 0] Center 35 (5~66) winsize 62
4466 12:42:30.983152 [CA 1] Center 36 (6~66) winsize 61
4467 12:42:30.986628 [CA 2] Center 34 (4~65) winsize 62
4468 12:42:30.990008 [CA 3] Center 34 (3~65) winsize 63
4469 12:42:30.993122 [CA 4] Center 34 (3~65) winsize 63
4470 12:42:30.996892 [CA 5] Center 33 (3~64) winsize 62
4471 12:42:30.996962
4472 12:42:30.999779 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4473 12:42:30.999865
4474 12:42:31.003553 [CATrainingPosCal] consider 2 rank data
4475 12:42:31.006331 u2DelayCellTimex100 = 270/100 ps
4476 12:42:31.009783 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4477 12:42:31.012884 CA1 delay=35 (6~65),Diff = 2 PI (19 cell)
4478 12:42:31.016164 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4479 12:42:31.019873 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4480 12:42:31.023445 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4481 12:42:31.030115 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4482 12:42:31.030216
4483 12:42:31.033497 CA PerBit enable=1, Macro0, CA PI delay=33
4484 12:42:31.033594
4485 12:42:31.036292 [CBTSetCACLKResult] CA Dly = 33
4486 12:42:31.036385 CS Dly: 4 (0~36)
4487 12:42:31.036472
4488 12:42:31.040165 ----->DramcWriteLeveling(PI) begin...
4489 12:42:31.040259 ==
4490 12:42:31.042707 Dram Type= 6, Freq= 0, CH_1, rank 0
4491 12:42:31.049644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 12:42:31.049720 ==
4493 12:42:31.053044 Write leveling (Byte 0): 29 => 29
4494 12:42:31.053155 Write leveling (Byte 1): 31 => 31
4495 12:42:31.056547 DramcWriteLeveling(PI) end<-----
4496 12:42:31.056620
4497 12:42:31.056682 ==
4498 12:42:31.059532 Dram Type= 6, Freq= 0, CH_1, rank 0
4499 12:42:31.066220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4500 12:42:31.066293 ==
4501 12:42:31.069523 [Gating] SW mode calibration
4502 12:42:31.076185 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4503 12:42:31.079726 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4504 12:42:31.086238 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4505 12:42:31.089884 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4506 12:42:31.093148 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4507 12:42:31.096198 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4508 12:42:31.103258 0 9 16 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
4509 12:42:31.106274 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4510 12:42:31.109359 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4511 12:42:31.116212 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4512 12:42:31.119532 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4513 12:42:31.123335 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4514 12:42:31.129340 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4515 12:42:31.132553 0 10 12 | B1->B0 | 2525 2a2a | 0 0 | (0 0) (1 1)
4516 12:42:31.136022 0 10 16 | B1->B0 | 3b3b 4040 | 0 0 | (0 0) (0 0)
4517 12:42:31.142622 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4518 12:42:31.146118 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4519 12:42:31.149374 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4520 12:42:31.156122 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4521 12:42:31.159614 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4522 12:42:31.163281 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4523 12:42:31.169685 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4524 12:42:31.172891 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 12:42:31.176138 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 12:42:31.182770 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 12:42:31.186109 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 12:42:31.189558 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 12:42:31.192805 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 12:42:31.200237 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 12:42:31.203011 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4532 12:42:31.206079 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4533 12:42:31.212743 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 12:42:31.216516 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 12:42:31.219639 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 12:42:31.226321 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 12:42:31.230584 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4538 12:42:31.232936 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4539 12:42:31.239829 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4540 12:42:31.243220 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4541 12:42:31.246198 Total UI for P1: 0, mck2ui 16
4542 12:42:31.249863 best dqsien dly found for B0: ( 0, 13, 14)
4543 12:42:31.253282 Total UI for P1: 0, mck2ui 16
4544 12:42:31.256195 best dqsien dly found for B1: ( 0, 13, 14)
4545 12:42:31.259845 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4546 12:42:31.263798 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4547 12:42:31.263929
4548 12:42:31.266531 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4549 12:42:31.270009 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4550 12:42:31.272969 [Gating] SW calibration Done
4551 12:42:31.273112 ==
4552 12:42:31.276015 Dram Type= 6, Freq= 0, CH_1, rank 0
4553 12:42:31.279499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4554 12:42:31.282849 ==
4555 12:42:31.282940 RX Vref Scan: 0
4556 12:42:31.283029
4557 12:42:31.286747 RX Vref 0 -> 0, step: 1
4558 12:42:31.286845
4559 12:42:31.289974 RX Delay -230 -> 252, step: 16
4560 12:42:31.293625 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4561 12:42:31.296065 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4562 12:42:31.299697 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4563 12:42:31.303454 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4564 12:42:31.309647 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4565 12:42:31.313066 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4566 12:42:31.316478 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4567 12:42:31.319440 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4568 12:42:31.326224 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4569 12:42:31.330334 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4570 12:42:31.332883 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4571 12:42:31.336126 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4572 12:42:31.339682 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4573 12:42:31.346275 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4574 12:42:31.349735 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4575 12:42:31.352722 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4576 12:42:31.352828 ==
4577 12:42:31.356523 Dram Type= 6, Freq= 0, CH_1, rank 0
4578 12:42:31.359448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 12:42:31.363033 ==
4580 12:42:31.363134 DQS Delay:
4581 12:42:31.363225 DQS0 = 0, DQS1 = 0
4582 12:42:31.366569 DQM Delay:
4583 12:42:31.366644 DQM0 = 46, DQM1 = 37
4584 12:42:31.370021 DQ Delay:
4585 12:42:31.370118 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4586 12:42:31.373491 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =41
4587 12:42:31.376510 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4588 12:42:31.379524 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =41
4589 12:42:31.379598
4590 12:42:31.383359
4591 12:42:31.383429 ==
4592 12:42:31.386565 Dram Type= 6, Freq= 0, CH_1, rank 0
4593 12:42:31.389915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4594 12:42:31.389987 ==
4595 12:42:31.390047
4596 12:42:31.390104
4597 12:42:31.393044 TX Vref Scan disable
4598 12:42:31.393122 == TX Byte 0 ==
4599 12:42:31.399599 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4600 12:42:31.403262 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4601 12:42:31.403339 == TX Byte 1 ==
4602 12:42:31.409715 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4603 12:42:31.413390 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4604 12:42:31.413462 ==
4605 12:42:31.416209 Dram Type= 6, Freq= 0, CH_1, rank 0
4606 12:42:31.419575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4607 12:42:31.419644 ==
4608 12:42:31.419703
4609 12:42:31.419763
4610 12:42:31.423060 TX Vref Scan disable
4611 12:42:31.426452 == TX Byte 0 ==
4612 12:42:31.430025 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4613 12:42:31.433298 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4614 12:42:31.436509 == TX Byte 1 ==
4615 12:42:31.439530 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4616 12:42:31.443432 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4617 12:42:31.443505
4618 12:42:31.446787 [DATLAT]
4619 12:42:31.446862 Freq=600, CH1 RK0
4620 12:42:31.446924
4621 12:42:31.449709 DATLAT Default: 0x9
4622 12:42:31.449781 0, 0xFFFF, sum = 0
4623 12:42:31.452870 1, 0xFFFF, sum = 0
4624 12:42:31.452944 2, 0xFFFF, sum = 0
4625 12:42:31.456417 3, 0xFFFF, sum = 0
4626 12:42:31.456494 4, 0xFFFF, sum = 0
4627 12:42:31.460253 5, 0xFFFF, sum = 0
4628 12:42:31.460325 6, 0xFFFF, sum = 0
4629 12:42:31.463724 7, 0xFFFF, sum = 0
4630 12:42:31.463795 8, 0x0, sum = 1
4631 12:42:31.467050 9, 0x0, sum = 2
4632 12:42:31.467121 10, 0x0, sum = 3
4633 12:42:31.469820 11, 0x0, sum = 4
4634 12:42:31.469899 best_step = 9
4635 12:42:31.469961
4636 12:42:31.470018 ==
4637 12:42:31.473518 Dram Type= 6, Freq= 0, CH_1, rank 0
4638 12:42:31.476724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4639 12:42:31.476792 ==
4640 12:42:31.480446 RX Vref Scan: 1
4641 12:42:31.480529
4642 12:42:31.483646 RX Vref 0 -> 0, step: 1
4643 12:42:31.483748
4644 12:42:31.483839 RX Delay -195 -> 252, step: 8
4645 12:42:31.483925
4646 12:42:31.487090 Set Vref, RX VrefLevel [Byte0]: 57
4647 12:42:31.489962 [Byte1]: 49
4648 12:42:31.494696
4649 12:42:31.494769 Final RX Vref Byte 0 = 57 to rank0
4650 12:42:31.498289 Final RX Vref Byte 1 = 49 to rank0
4651 12:42:31.501221 Final RX Vref Byte 0 = 57 to rank1
4652 12:42:31.504624 Final RX Vref Byte 1 = 49 to rank1==
4653 12:42:31.508089 Dram Type= 6, Freq= 0, CH_1, rank 0
4654 12:42:31.514856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4655 12:42:31.514934 ==
4656 12:42:31.514996 DQS Delay:
4657 12:42:31.515054 DQS0 = 0, DQS1 = 0
4658 12:42:31.518000 DQM Delay:
4659 12:42:31.518074 DQM0 = 41, DQM1 = 33
4660 12:42:31.521006 DQ Delay:
4661 12:42:31.524643 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4662 12:42:31.524727 DQ4 =44, DQ5 =48, DQ6 =52, DQ7 =36
4663 12:42:31.528045 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =28
4664 12:42:31.531128 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4665 12:42:31.534626
4666 12:42:31.534701
4667 12:42:31.541157 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e04, (MSB)MR19= 0x808, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
4668 12:42:31.544959 CH1 RK0: MR19=808, MR18=3E04
4669 12:42:31.551500 CH1_RK0: MR19=0x808, MR18=0x3E04, DQSOSC=398, MR23=63, INC=165, DEC=110
4670 12:42:31.551582
4671 12:42:31.554782 ----->DramcWriteLeveling(PI) begin...
4672 12:42:31.554886 ==
4673 12:42:31.558043 Dram Type= 6, Freq= 0, CH_1, rank 1
4674 12:42:31.561497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 12:42:31.561595 ==
4676 12:42:31.564566 Write leveling (Byte 0): 29 => 29
4677 12:42:31.567680 Write leveling (Byte 1): 30 => 30
4678 12:42:31.571210 DramcWriteLeveling(PI) end<-----
4679 12:42:31.571284
4680 12:42:31.571344 ==
4681 12:42:31.574954 Dram Type= 6, Freq= 0, CH_1, rank 1
4682 12:42:31.577758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4683 12:42:31.577857 ==
4684 12:42:31.581014 [Gating] SW mode calibration
4685 12:42:31.588183 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4686 12:42:31.594957 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4687 12:42:31.597892 0 9 0 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
4688 12:42:31.600936 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4689 12:42:31.608118 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4690 12:42:31.611485 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (1 1) (1 1)
4691 12:42:31.614972 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4692 12:42:31.621424 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4693 12:42:31.625049 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4694 12:42:31.627990 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4695 12:42:31.634645 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4696 12:42:31.638172 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4697 12:42:31.641257 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4698 12:42:31.648278 0 10 12 | B1->B0 | 2e2e 3b3b | 0 0 | (0 0) (1 1)
4699 12:42:31.651531 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4700 12:42:31.654914 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4701 12:42:31.661267 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4702 12:42:31.664742 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4703 12:42:31.668152 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4704 12:42:31.671387 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4705 12:42:31.678325 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4706 12:42:31.681633 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4707 12:42:31.684706 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 12:42:31.691419 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 12:42:31.694960 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 12:42:31.697907 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 12:42:31.704764 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 12:42:31.708456 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 12:42:31.711572 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 12:42:31.718021 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 12:42:31.721833 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 12:42:31.725114 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 12:42:31.732066 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 12:42:31.735347 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 12:42:31.738113 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4720 12:42:31.741875 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4721 12:42:31.748824 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4722 12:42:31.752016 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4723 12:42:31.755916 Total UI for P1: 0, mck2ui 16
4724 12:42:31.758560 best dqsien dly found for B0: ( 0, 13, 8)
4725 12:42:31.761855 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4726 12:42:31.765292 Total UI for P1: 0, mck2ui 16
4727 12:42:31.768064 best dqsien dly found for B1: ( 0, 13, 12)
4728 12:42:31.771619 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4729 12:42:31.775285 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4730 12:42:31.775360
4731 12:42:31.781998 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4732 12:42:31.786020 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4733 12:42:31.788363 [Gating] SW calibration Done
4734 12:42:31.788438 ==
4735 12:42:31.792140 Dram Type= 6, Freq= 0, CH_1, rank 1
4736 12:42:31.795004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4737 12:42:31.795074 ==
4738 12:42:31.795134 RX Vref Scan: 0
4739 12:42:31.795194
4740 12:42:31.798489 RX Vref 0 -> 0, step: 1
4741 12:42:31.798560
4742 12:42:31.801436 RX Delay -230 -> 252, step: 16
4743 12:42:31.805015 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4744 12:42:31.808277 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4745 12:42:31.815373 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4746 12:42:31.817977 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4747 12:42:31.821809 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4748 12:42:31.824881 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4749 12:42:31.831947 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4750 12:42:31.835087 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4751 12:42:31.838024 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4752 12:42:31.841427 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4753 12:42:31.845207 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4754 12:42:31.852021 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4755 12:42:31.855000 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4756 12:42:31.858636 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4757 12:42:31.861463 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4758 12:42:31.868603 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4759 12:42:31.868709 ==
4760 12:42:31.872103 Dram Type= 6, Freq= 0, CH_1, rank 1
4761 12:42:31.875500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4762 12:42:31.875575 ==
4763 12:42:31.875636 DQS Delay:
4764 12:42:31.879041 DQS0 = 0, DQS1 = 0
4765 12:42:31.879113 DQM Delay:
4766 12:42:31.881679 DQM0 = 40, DQM1 = 34
4767 12:42:31.881788 DQ Delay:
4768 12:42:31.884970 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4769 12:42:31.888250 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4770 12:42:31.891585 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4771 12:42:31.895327 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4772 12:42:31.895429
4773 12:42:31.895528
4774 12:42:31.895617 ==
4775 12:42:31.898377 Dram Type= 6, Freq= 0, CH_1, rank 1
4776 12:42:31.901488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4777 12:42:31.901594 ==
4778 12:42:31.901684
4779 12:42:31.901770
4780 12:42:31.905597 TX Vref Scan disable
4781 12:42:31.908262 == TX Byte 0 ==
4782 12:42:31.911640 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4783 12:42:31.915193 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4784 12:42:31.918187 == TX Byte 1 ==
4785 12:42:31.921987 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4786 12:42:31.925080 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4787 12:42:31.925183 ==
4788 12:42:31.928475 Dram Type= 6, Freq= 0, CH_1, rank 1
4789 12:42:31.935013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4790 12:42:31.935093 ==
4791 12:42:31.935168
4792 12:42:31.935255
4793 12:42:31.935344 TX Vref Scan disable
4794 12:42:31.939000 == TX Byte 0 ==
4795 12:42:31.943133 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4796 12:42:31.945769 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4797 12:42:31.948892 == TX Byte 1 ==
4798 12:42:31.952792 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4799 12:42:31.955721 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4800 12:42:31.959250
4801 12:42:31.959349 [DATLAT]
4802 12:42:31.959439 Freq=600, CH1 RK1
4803 12:42:31.959529
4804 12:42:31.963437 DATLAT Default: 0x9
4805 12:42:31.963534 0, 0xFFFF, sum = 0
4806 12:42:31.966036 1, 0xFFFF, sum = 0
4807 12:42:31.966137 2, 0xFFFF, sum = 0
4808 12:42:31.969762 3, 0xFFFF, sum = 0
4809 12:42:31.969864 4, 0xFFFF, sum = 0
4810 12:42:31.972719 5, 0xFFFF, sum = 0
4811 12:42:31.975524 6, 0xFFFF, sum = 0
4812 12:42:31.975601 7, 0xFFFF, sum = 0
4813 12:42:31.975665 8, 0x0, sum = 1
4814 12:42:31.979014 9, 0x0, sum = 2
4815 12:42:31.979124 10, 0x0, sum = 3
4816 12:42:31.982738 11, 0x0, sum = 4
4817 12:42:31.982853 best_step = 9
4818 12:42:31.982945
4819 12:42:31.983041 ==
4820 12:42:31.985760 Dram Type= 6, Freq= 0, CH_1, rank 1
4821 12:42:31.992862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4822 12:42:31.992940 ==
4823 12:42:31.993006 RX Vref Scan: 0
4824 12:42:31.993069
4825 12:42:31.995773 RX Vref 0 -> 0, step: 1
4826 12:42:31.995845
4827 12:42:31.999278 RX Delay -195 -> 252, step: 8
4828 12:42:32.002626 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4829 12:42:32.009157 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4830 12:42:32.012952 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4831 12:42:32.015713 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4832 12:42:32.019368 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4833 12:42:32.022233 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4834 12:42:32.028888 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4835 12:42:32.032507 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4836 12:42:32.035683 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4837 12:42:32.039823 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4838 12:42:32.042490 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4839 12:42:32.049041 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4840 12:42:32.052355 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4841 12:42:32.055736 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4842 12:42:32.059171 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4843 12:42:32.066072 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4844 12:42:32.066174 ==
4845 12:42:32.068981 Dram Type= 6, Freq= 0, CH_1, rank 1
4846 12:42:32.072837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4847 12:42:32.072935 ==
4848 12:42:32.073025 DQS Delay:
4849 12:42:32.076296 DQS0 = 0, DQS1 = 0
4850 12:42:32.076401 DQM Delay:
4851 12:42:32.079837 DQM0 = 38, DQM1 = 32
4852 12:42:32.079935 DQ Delay:
4853 12:42:32.082454 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =36
4854 12:42:32.085574 DQ4 =40, DQ5 =52, DQ6 =48, DQ7 =36
4855 12:42:32.089299 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =24
4856 12:42:32.092156 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4857 12:42:32.092261
4858 12:42:32.092353
4859 12:42:32.102528 [DQSOSCAuto] RK1, (LSB)MR18= 0x3543, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 399 ps
4860 12:42:32.102604 CH1 RK1: MR19=808, MR18=3543
4861 12:42:32.109011 CH1_RK1: MR19=0x808, MR18=0x3543, DQSOSC=397, MR23=63, INC=166, DEC=110
4862 12:42:32.112485 [RxdqsGatingPostProcess] freq 600
4863 12:42:32.119149 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4864 12:42:32.122488 Pre-setting of DQS Precalculation
4865 12:42:32.126214 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4866 12:42:32.132565 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4867 12:42:32.139436 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4868 12:42:32.139543
4869 12:42:32.139633
4870 12:42:32.142759 [Calibration Summary] 1200 Mbps
4871 12:42:32.145603 CH 0, Rank 0
4872 12:42:32.145675 SW Impedance : PASS
4873 12:42:32.149437 DUTY Scan : NO K
4874 12:42:32.152445 ZQ Calibration : PASS
4875 12:42:32.152549 Jitter Meter : NO K
4876 12:42:32.155562 CBT Training : PASS
4877 12:42:32.158979 Write leveling : PASS
4878 12:42:32.159050 RX DQS gating : PASS
4879 12:42:32.162555 RX DQ/DQS(RDDQC) : PASS
4880 12:42:32.165653 TX DQ/DQS : PASS
4881 12:42:32.165753 RX DATLAT : PASS
4882 12:42:32.169773 RX DQ/DQS(Engine): PASS
4883 12:42:32.169869 TX OE : NO K
4884 12:42:32.172710 All Pass.
4885 12:42:32.172804
4886 12:42:32.172899 CH 0, Rank 1
4887 12:42:32.175838 SW Impedance : PASS
4888 12:42:32.175945 DUTY Scan : NO K
4889 12:42:32.179959 ZQ Calibration : PASS
4890 12:42:32.182319 Jitter Meter : NO K
4891 12:42:32.182452 CBT Training : PASS
4892 12:42:32.185890 Write leveling : PASS
4893 12:42:32.189495 RX DQS gating : PASS
4894 12:42:32.189569 RX DQ/DQS(RDDQC) : PASS
4895 12:42:32.192321 TX DQ/DQS : PASS
4896 12:42:32.196180 RX DATLAT : PASS
4897 12:42:32.196252 RX DQ/DQS(Engine): PASS
4898 12:42:32.199581 TX OE : NO K
4899 12:42:32.199653 All Pass.
4900 12:42:32.199715
4901 12:42:32.202651 CH 1, Rank 0
4902 12:42:32.202719 SW Impedance : PASS
4903 12:42:32.205786 DUTY Scan : NO K
4904 12:42:32.209067 ZQ Calibration : PASS
4905 12:42:32.209164 Jitter Meter : NO K
4906 12:42:32.212501 CBT Training : PASS
4907 12:42:32.212596 Write leveling : PASS
4908 12:42:32.215741 RX DQS gating : PASS
4909 12:42:32.219529 RX DQ/DQS(RDDQC) : PASS
4910 12:42:32.219613 TX DQ/DQS : PASS
4911 12:42:32.222722 RX DATLAT : PASS
4912 12:42:32.226082 RX DQ/DQS(Engine): PASS
4913 12:42:32.226183 TX OE : NO K
4914 12:42:32.229536 All Pass.
4915 12:42:32.229623
4916 12:42:32.229711 CH 1, Rank 1
4917 12:42:32.232502 SW Impedance : PASS
4918 12:42:32.232601 DUTY Scan : NO K
4919 12:42:32.235819 ZQ Calibration : PASS
4920 12:42:32.239433 Jitter Meter : NO K
4921 12:42:32.239533 CBT Training : PASS
4922 12:42:32.242696 Write leveling : PASS
4923 12:42:32.245871 RX DQS gating : PASS
4924 12:42:32.245984 RX DQ/DQS(RDDQC) : PASS
4925 12:42:32.248988 TX DQ/DQS : PASS
4926 12:42:32.249084 RX DATLAT : PASS
4927 12:42:32.252523 RX DQ/DQS(Engine): PASS
4928 12:42:32.255917 TX OE : NO K
4929 12:42:32.256030 All Pass.
4930 12:42:32.256121
4931 12:42:32.259203 DramC Write-DBI off
4932 12:42:32.259298 PER_BANK_REFRESH: Hybrid Mode
4933 12:42:32.262595 TX_TRACKING: ON
4934 12:42:32.272558 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4935 12:42:32.275872 [FAST_K] Save calibration result to emmc
4936 12:42:32.279112 dramc_set_vcore_voltage set vcore to 662500
4937 12:42:32.279215 Read voltage for 933, 3
4938 12:42:32.282692 Vio18 = 0
4939 12:42:32.282761 Vcore = 662500
4940 12:42:32.282821 Vdram = 0
4941 12:42:32.286091 Vddq = 0
4942 12:42:32.286192 Vmddr = 0
4943 12:42:32.289125 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4944 12:42:32.295778 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4945 12:42:32.299445 MEM_TYPE=3, freq_sel=17
4946 12:42:32.302600 sv_algorithm_assistance_LP4_1600
4947 12:42:32.306170 ============ PULL DRAM RESETB DOWN ============
4948 12:42:32.308995 ========== PULL DRAM RESETB DOWN end =========
4949 12:42:32.316032 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4950 12:42:32.319120 ===================================
4951 12:42:32.319228 LPDDR4 DRAM CONFIGURATION
4952 12:42:32.323096 ===================================
4953 12:42:32.326250 EX_ROW_EN[0] = 0x0
4954 12:42:32.326355 EX_ROW_EN[1] = 0x0
4955 12:42:32.329133 LP4Y_EN = 0x0
4956 12:42:32.329230 WORK_FSP = 0x0
4957 12:42:32.332618 WL = 0x3
4958 12:42:32.332719 RL = 0x3
4959 12:42:32.335992 BL = 0x2
4960 12:42:32.336112 RPST = 0x0
4961 12:42:32.339791 RD_PRE = 0x0
4962 12:42:32.339896 WR_PRE = 0x1
4963 12:42:32.342623 WR_PST = 0x0
4964 12:42:32.346038 DBI_WR = 0x0
4965 12:42:32.346140 DBI_RD = 0x0
4966 12:42:32.349014 OTF = 0x1
4967 12:42:32.352287 ===================================
4968 12:42:32.356446 ===================================
4969 12:42:32.356599 ANA top config
4970 12:42:32.359451 ===================================
4971 12:42:32.362486 DLL_ASYNC_EN = 0
4972 12:42:32.362560 ALL_SLAVE_EN = 1
4973 12:42:32.365870 NEW_RANK_MODE = 1
4974 12:42:32.369414 DLL_IDLE_MODE = 1
4975 12:42:32.372797 LP45_APHY_COMB_EN = 1
4976 12:42:32.376485 TX_ODT_DIS = 1
4977 12:42:32.376590 NEW_8X_MODE = 1
4978 12:42:32.379124 ===================================
4979 12:42:32.382953 ===================================
4980 12:42:32.386015 data_rate = 1866
4981 12:42:32.389286 CKR = 1
4982 12:42:32.392483 DQ_P2S_RATIO = 8
4983 12:42:32.396142 ===================================
4984 12:42:32.399159 CA_P2S_RATIO = 8
4985 12:42:32.402511 DQ_CA_OPEN = 0
4986 12:42:32.402582 DQ_SEMI_OPEN = 0
4987 12:42:32.405980 CA_SEMI_OPEN = 0
4988 12:42:32.409009 CA_FULL_RATE = 0
4989 12:42:32.412588 DQ_CKDIV4_EN = 1
4990 12:42:32.416096 CA_CKDIV4_EN = 1
4991 12:42:32.418944 CA_PREDIV_EN = 0
4992 12:42:32.419013 PH8_DLY = 0
4993 12:42:32.422557 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4994 12:42:32.425930 DQ_AAMCK_DIV = 4
4995 12:42:32.429143 CA_AAMCK_DIV = 4
4996 12:42:32.432487 CA_ADMCK_DIV = 4
4997 12:42:32.432583 DQ_TRACK_CA_EN = 0
4998 12:42:32.435921 CA_PICK = 933
4999 12:42:32.439096 CA_MCKIO = 933
5000 12:42:32.442044 MCKIO_SEMI = 0
5001 12:42:32.445641 PLL_FREQ = 3732
5002 12:42:32.448916 DQ_UI_PI_RATIO = 32
5003 12:42:32.452028 CA_UI_PI_RATIO = 0
5004 12:42:32.455884 ===================================
5005 12:42:32.458666 ===================================
5006 12:42:32.458770 memory_type:LPDDR4
5007 12:42:32.462900 GP_NUM : 10
5008 12:42:32.465550 SRAM_EN : 1
5009 12:42:32.465646 MD32_EN : 0
5010 12:42:32.469067 ===================================
5011 12:42:32.472146 [ANA_INIT] >>>>>>>>>>>>>>
5012 12:42:32.475683 <<<<<< [CONFIGURE PHASE]: ANA_TX
5013 12:42:32.478542 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5014 12:42:32.481977 ===================================
5015 12:42:32.485849 data_rate = 1866,PCW = 0X8f00
5016 12:42:32.489005 ===================================
5017 12:42:32.492535 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5018 12:42:32.495063 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5019 12:42:32.502279 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5020 12:42:32.505700 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5021 12:42:32.508300 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5022 12:42:32.515074 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5023 12:42:32.515165 [ANA_INIT] flow start
5024 12:42:32.518450 [ANA_INIT] PLL >>>>>>>>
5025 12:42:32.518542 [ANA_INIT] PLL <<<<<<<<
5026 12:42:32.521657 [ANA_INIT] MIDPI >>>>>>>>
5027 12:42:32.524977 [ANA_INIT] MIDPI <<<<<<<<
5028 12:42:32.528456 [ANA_INIT] DLL >>>>>>>>
5029 12:42:32.528546 [ANA_INIT] flow end
5030 12:42:32.531812 ============ LP4 DIFF to SE enter ============
5031 12:42:32.538517 ============ LP4 DIFF to SE exit ============
5032 12:42:32.538597 [ANA_INIT] <<<<<<<<<<<<<
5033 12:42:32.541989 [Flow] Enable top DCM control >>>>>
5034 12:42:32.544963 [Flow] Enable top DCM control <<<<<
5035 12:42:32.548576 Enable DLL master slave shuffle
5036 12:42:32.555496 ==============================================================
5037 12:42:32.555605 Gating Mode config
5038 12:42:32.561512 ==============================================================
5039 12:42:32.565612 Config description:
5040 12:42:32.575543 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5041 12:42:32.578595 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5042 12:42:32.585056 SELPH_MODE 0: By rank 1: By Phase
5043 12:42:32.592244 ==============================================================
5044 12:42:32.595027 GAT_TRACK_EN = 1
5045 12:42:32.595134 RX_GATING_MODE = 2
5046 12:42:32.598519 RX_GATING_TRACK_MODE = 2
5047 12:42:32.601997 SELPH_MODE = 1
5048 12:42:32.604793 PICG_EARLY_EN = 1
5049 12:42:32.608332 VALID_LAT_VALUE = 1
5050 12:42:32.615642 ==============================================================
5051 12:42:32.618304 Enter into Gating configuration >>>>
5052 12:42:32.622132 Exit from Gating configuration <<<<
5053 12:42:32.625049 Enter into DVFS_PRE_config >>>>>
5054 12:42:32.635695 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5055 12:42:32.638743 Exit from DVFS_PRE_config <<<<<
5056 12:42:32.641763 Enter into PICG configuration >>>>
5057 12:42:32.645083 Exit from PICG configuration <<<<
5058 12:42:32.648352 [RX_INPUT] configuration >>>>>
5059 12:42:32.648461 [RX_INPUT] configuration <<<<<
5060 12:42:32.655170 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5061 12:42:32.661635 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5062 12:42:32.665192 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5063 12:42:32.672466 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5064 12:42:32.678554 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5065 12:42:32.684795 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5066 12:42:32.688385 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5067 12:42:32.691637 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5068 12:42:32.699504 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5069 12:42:32.701734 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5070 12:42:32.706437 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5071 12:42:32.711393 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5072 12:42:32.715117 ===================================
5073 12:42:32.715193 LPDDR4 DRAM CONFIGURATION
5074 12:42:32.718270 ===================================
5075 12:42:32.721576 EX_ROW_EN[0] = 0x0
5076 12:42:32.721675 EX_ROW_EN[1] = 0x0
5077 12:42:32.725061 LP4Y_EN = 0x0
5078 12:42:32.725162 WORK_FSP = 0x0
5079 12:42:32.728461 WL = 0x3
5080 12:42:32.731572 RL = 0x3
5081 12:42:32.731678 BL = 0x2
5082 12:42:32.735030 RPST = 0x0
5083 12:42:32.735113 RD_PRE = 0x0
5084 12:42:32.738336 WR_PRE = 0x1
5085 12:42:32.738463 WR_PST = 0x0
5086 12:42:32.741676 DBI_WR = 0x0
5087 12:42:32.741779 DBI_RD = 0x0
5088 12:42:32.745141 OTF = 0x1
5089 12:42:32.748101 ===================================
5090 12:42:32.751734 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5091 12:42:32.754734 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5092 12:42:32.758148 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5093 12:42:32.761885 ===================================
5094 12:42:32.765195 LPDDR4 DRAM CONFIGURATION
5095 12:42:32.768217 ===================================
5096 12:42:32.771767 EX_ROW_EN[0] = 0x10
5097 12:42:32.771867 EX_ROW_EN[1] = 0x0
5098 12:42:32.775316 LP4Y_EN = 0x0
5099 12:42:32.775424 WORK_FSP = 0x0
5100 12:42:32.778840 WL = 0x3
5101 12:42:32.778917 RL = 0x3
5102 12:42:32.782102 BL = 0x2
5103 12:42:32.782196 RPST = 0x0
5104 12:42:32.785183 RD_PRE = 0x0
5105 12:42:32.785283 WR_PRE = 0x1
5106 12:42:32.788655 WR_PST = 0x0
5107 12:42:32.788727 DBI_WR = 0x0
5108 12:42:32.792049 DBI_RD = 0x0
5109 12:42:32.792147 OTF = 0x1
5110 12:42:32.795252 ===================================
5111 12:42:32.801933 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5112 12:42:32.806726 nWR fixed to 30
5113 12:42:32.810942 [ModeRegInit_LP4] CH0 RK0
5114 12:42:32.811015 [ModeRegInit_LP4] CH0 RK1
5115 12:42:32.813440 [ModeRegInit_LP4] CH1 RK0
5116 12:42:32.816365 [ModeRegInit_LP4] CH1 RK1
5117 12:42:32.816471 match AC timing 9
5118 12:42:32.823146 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5119 12:42:32.826899 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5120 12:42:32.829790 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5121 12:42:32.836233 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5122 12:42:32.839433 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5123 12:42:32.839521 ==
5124 12:42:32.842908 Dram Type= 6, Freq= 0, CH_0, rank 0
5125 12:42:32.846115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5126 12:42:32.846219 ==
5127 12:42:32.852775 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5128 12:42:32.859761 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5129 12:42:32.862526 [CA 0] Center 38 (8~69) winsize 62
5130 12:42:32.866150 [CA 1] Center 38 (7~69) winsize 63
5131 12:42:32.869486 [CA 2] Center 35 (5~66) winsize 62
5132 12:42:32.873165 [CA 3] Center 35 (5~65) winsize 61
5133 12:42:32.875938 [CA 4] Center 34 (4~64) winsize 61
5134 12:42:32.879071 [CA 5] Center 34 (4~64) winsize 61
5135 12:42:32.879153
5136 12:42:32.882615 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5137 12:42:32.882701
5138 12:42:32.885998 [CATrainingPosCal] consider 1 rank data
5139 12:42:32.889543 u2DelayCellTimex100 = 270/100 ps
5140 12:42:32.892629 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5141 12:42:32.895910 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5142 12:42:32.899463 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5143 12:42:32.902980 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5144 12:42:32.906023 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5145 12:42:32.912431 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5146 12:42:32.912513
5147 12:42:32.916130 CA PerBit enable=1, Macro0, CA PI delay=34
5148 12:42:32.916210
5149 12:42:32.919965 [CBTSetCACLKResult] CA Dly = 34
5150 12:42:32.920045 CS Dly: 6 (0~37)
5151 12:42:32.920143 ==
5152 12:42:32.922345 Dram Type= 6, Freq= 0, CH_0, rank 1
5153 12:42:32.926068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5154 12:42:32.926196 ==
5155 12:42:32.932762 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5156 12:42:32.939177 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5157 12:42:32.943230 [CA 0] Center 38 (7~69) winsize 63
5158 12:42:32.946074 [CA 1] Center 38 (7~69) winsize 63
5159 12:42:32.949257 [CA 2] Center 35 (5~66) winsize 62
5160 12:42:32.952491 [CA 3] Center 35 (4~66) winsize 63
5161 12:42:32.956294 [CA 4] Center 34 (4~65) winsize 62
5162 12:42:32.959182 [CA 5] Center 33 (3~64) winsize 62
5163 12:42:32.959254
5164 12:42:32.962472 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5165 12:42:32.962545
5166 12:42:32.965419 [CATrainingPosCal] consider 2 rank data
5167 12:42:32.969406 u2DelayCellTimex100 = 270/100 ps
5168 12:42:32.972993 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5169 12:42:32.975961 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5170 12:42:32.978945 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5171 12:42:32.982716 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5172 12:42:32.985827 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5173 12:42:32.992213 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5174 12:42:32.992291
5175 12:42:32.996298 CA PerBit enable=1, Macro0, CA PI delay=34
5176 12:42:32.996376
5177 12:42:32.999311 [CBTSetCACLKResult] CA Dly = 34
5178 12:42:32.999383 CS Dly: 7 (0~39)
5179 12:42:32.999443
5180 12:42:33.002990 ----->DramcWriteLeveling(PI) begin...
5181 12:42:33.003061 ==
5182 12:42:33.005906 Dram Type= 6, Freq= 0, CH_0, rank 0
5183 12:42:33.009547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5184 12:42:33.012963 ==
5185 12:42:33.013067 Write leveling (Byte 0): 30 => 30
5186 12:42:33.015616 Write leveling (Byte 1): 29 => 29
5187 12:42:33.018913 DramcWriteLeveling(PI) end<-----
5188 12:42:33.018983
5189 12:42:33.019043 ==
5190 12:42:33.022472 Dram Type= 6, Freq= 0, CH_0, rank 0
5191 12:42:33.029185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5192 12:42:33.029325 ==
5193 12:42:33.029415 [Gating] SW mode calibration
5194 12:42:33.039246 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5195 12:42:33.042727 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5196 12:42:33.045869 0 14 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5197 12:42:33.052836 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5198 12:42:33.056444 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5199 12:42:33.059103 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5200 12:42:33.066275 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5201 12:42:33.069135 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5202 12:42:33.072506 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5203 12:42:33.079216 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
5204 12:42:33.082780 0 15 0 | B1->B0 | 3232 2f2f | 0 0 | (0 1) (0 1)
5205 12:42:33.086615 0 15 4 | B1->B0 | 2929 2323 | 0 0 | (0 0) (1 0)
5206 12:42:33.092426 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5207 12:42:33.096041 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5208 12:42:33.099284 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5209 12:42:33.105979 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5210 12:42:33.109047 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5211 12:42:33.112841 0 15 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5212 12:42:33.119087 1 0 0 | B1->B0 | 3030 3f3f | 0 0 | (0 0) (0 0)
5213 12:42:33.122539 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5214 12:42:33.125952 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5215 12:42:33.132328 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5216 12:42:33.136293 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5217 12:42:33.140084 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5218 12:42:33.142992 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5219 12:42:33.149873 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5220 12:42:33.152652 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5221 12:42:33.156261 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5222 12:42:33.162658 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 12:42:33.166498 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 12:42:33.169292 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 12:42:33.175988 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 12:42:33.180075 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 12:42:33.182710 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5228 12:42:33.189713 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5229 12:42:33.192915 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5230 12:42:33.196260 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 12:42:33.202693 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 12:42:33.206175 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 12:42:33.209716 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 12:42:33.216647 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5235 12:42:33.219655 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5236 12:42:33.222575 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5237 12:42:33.225995 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5238 12:42:33.229576 Total UI for P1: 0, mck2ui 16
5239 12:42:33.233084 best dqsien dly found for B0: ( 1, 3, 0)
5240 12:42:33.239687 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5241 12:42:33.243084 Total UI for P1: 0, mck2ui 16
5242 12:42:33.246102 best dqsien dly found for B1: ( 1, 3, 2)
5243 12:42:33.249762 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5244 12:42:33.253158 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5245 12:42:33.253230
5246 12:42:33.255974 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5247 12:42:33.259327 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5248 12:42:33.262973 [Gating] SW calibration Done
5249 12:42:33.263079 ==
5250 12:42:33.266258 Dram Type= 6, Freq= 0, CH_0, rank 0
5251 12:42:33.269988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5252 12:42:33.270068 ==
5253 12:42:33.273647 RX Vref Scan: 0
5254 12:42:33.273752
5255 12:42:33.273870 RX Vref 0 -> 0, step: 1
5256 12:42:33.273964
5257 12:42:33.276343 RX Delay -80 -> 252, step: 8
5258 12:42:33.279818 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5259 12:42:33.282831 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5260 12:42:33.289905 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5261 12:42:33.293275 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5262 12:42:33.296438 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5263 12:42:33.299518 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5264 12:42:33.303256 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5265 12:42:33.306304 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5266 12:42:33.313013 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5267 12:42:33.316712 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5268 12:42:33.319495 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5269 12:42:33.322958 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5270 12:42:33.326174 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5271 12:42:33.329535 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5272 12:42:33.336295 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5273 12:42:33.339808 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5274 12:42:33.339885 ==
5275 12:42:33.343195 Dram Type= 6, Freq= 0, CH_0, rank 0
5276 12:42:33.346549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 12:42:33.346624 ==
5278 12:42:33.346685 DQS Delay:
5279 12:42:33.349601 DQS0 = 0, DQS1 = 0
5280 12:42:33.349696 DQM Delay:
5281 12:42:33.353053 DQM0 = 98, DQM1 = 88
5282 12:42:33.353126 DQ Delay:
5283 12:42:33.356307 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =91
5284 12:42:33.359605 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5285 12:42:33.363157 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =83
5286 12:42:33.366457 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5287 12:42:33.366531
5288 12:42:33.366591
5289 12:42:33.366648 ==
5290 12:42:33.369756 Dram Type= 6, Freq= 0, CH_0, rank 0
5291 12:42:33.376260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 12:42:33.376361 ==
5293 12:42:33.376453
5294 12:42:33.376539
5295 12:42:33.376623 TX Vref Scan disable
5296 12:42:33.380052 == TX Byte 0 ==
5297 12:42:33.383274 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5298 12:42:33.386341 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5299 12:42:33.389834 == TX Byte 1 ==
5300 12:42:33.393035 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5301 12:42:33.399732 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5302 12:42:33.399809 ==
5303 12:42:33.403074 Dram Type= 6, Freq= 0, CH_0, rank 0
5304 12:42:33.406375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5305 12:42:33.406476 ==
5306 12:42:33.406539
5307 12:42:33.406601
5308 12:42:33.409934 TX Vref Scan disable
5309 12:42:33.410034 == TX Byte 0 ==
5310 12:42:33.416565 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5311 12:42:33.419446 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5312 12:42:33.419627 == TX Byte 1 ==
5313 12:42:33.426303 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5314 12:42:33.429395 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5315 12:42:33.429495
5316 12:42:33.429571 [DATLAT]
5317 12:42:33.433153 Freq=933, CH0 RK0
5318 12:42:33.433252
5319 12:42:33.433343 DATLAT Default: 0xd
5320 12:42:33.436459 0, 0xFFFF, sum = 0
5321 12:42:33.436577 1, 0xFFFF, sum = 0
5322 12:42:33.439746 2, 0xFFFF, sum = 0
5323 12:42:33.439849 3, 0xFFFF, sum = 0
5324 12:42:33.443092 4, 0xFFFF, sum = 0
5325 12:42:33.443203 5, 0xFFFF, sum = 0
5326 12:42:33.446349 6, 0xFFFF, sum = 0
5327 12:42:33.446463 7, 0xFFFF, sum = 0
5328 12:42:33.449597 8, 0xFFFF, sum = 0
5329 12:42:33.452783 9, 0xFFFF, sum = 0
5330 12:42:33.452886 10, 0x0, sum = 1
5331 12:42:33.452979 11, 0x0, sum = 2
5332 12:42:33.456515 12, 0x0, sum = 3
5333 12:42:33.456619 13, 0x0, sum = 4
5334 12:42:33.459571 best_step = 11
5335 12:42:33.459670
5336 12:42:33.459761 ==
5337 12:42:33.462901 Dram Type= 6, Freq= 0, CH_0, rank 0
5338 12:42:33.466372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5339 12:42:33.466515 ==
5340 12:42:33.469354 RX Vref Scan: 1
5341 12:42:33.469452
5342 12:42:33.469540 RX Vref 0 -> 0, step: 1
5343 12:42:33.469636
5344 12:42:33.472818 RX Delay -61 -> 252, step: 4
5345 12:42:33.472918
5346 12:42:33.476660 Set Vref, RX VrefLevel [Byte0]: 54
5347 12:42:33.479515 [Byte1]: 50
5348 12:42:33.483836
5349 12:42:33.483909 Final RX Vref Byte 0 = 54 to rank0
5350 12:42:33.487042 Final RX Vref Byte 1 = 50 to rank0
5351 12:42:33.490902 Final RX Vref Byte 0 = 54 to rank1
5352 12:42:33.494043 Final RX Vref Byte 1 = 50 to rank1==
5353 12:42:33.496894 Dram Type= 6, Freq= 0, CH_0, rank 0
5354 12:42:33.503546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5355 12:42:33.503628 ==
5356 12:42:33.503691 DQS Delay:
5357 12:42:33.503749 DQS0 = 0, DQS1 = 0
5358 12:42:33.507154 DQM Delay:
5359 12:42:33.507221 DQM0 = 97, DQM1 = 88
5360 12:42:33.510371 DQ Delay:
5361 12:42:33.513485 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =94
5362 12:42:33.516961 DQ4 =98, DQ5 =86, DQ6 =106, DQ7 =104
5363 12:42:33.520481 DQ8 =78, DQ9 =76, DQ10 =86, DQ11 =80
5364 12:42:33.523282 DQ12 =96, DQ13 =90, DQ14 =100, DQ15 =100
5365 12:42:33.523382
5366 12:42:33.523470
5367 12:42:33.530539 [DQSOSCAuto] RK0, (LSB)MR18= 0xffa, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 417 ps
5368 12:42:33.533649 CH0 RK0: MR19=504, MR18=FFA
5369 12:42:33.540368 CH0_RK0: MR19=0x504, MR18=0xFFA, DQSOSC=417, MR23=63, INC=62, DEC=41
5370 12:42:33.540452
5371 12:42:33.543884 ----->DramcWriteLeveling(PI) begin...
5372 12:42:33.543986 ==
5373 12:42:33.546906 Dram Type= 6, Freq= 0, CH_0, rank 1
5374 12:42:33.550420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5375 12:42:33.550507 ==
5376 12:42:33.553294 Write leveling (Byte 0): 32 => 32
5377 12:42:33.556873 Write leveling (Byte 1): 31 => 31
5378 12:42:33.560355 DramcWriteLeveling(PI) end<-----
5379 12:42:33.560463
5380 12:42:33.560552 ==
5381 12:42:33.563269 Dram Type= 6, Freq= 0, CH_0, rank 1
5382 12:42:33.566634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5383 12:42:33.566731 ==
5384 12:42:33.570300 [Gating] SW mode calibration
5385 12:42:33.576983 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5386 12:42:33.583864 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5387 12:42:33.587053 0 14 0 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
5388 12:42:33.590380 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5389 12:42:33.596566 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5390 12:42:33.600276 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5391 12:42:33.603784 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5392 12:42:33.610190 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5393 12:42:33.613230 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5394 12:42:33.616808 0 14 28 | B1->B0 | 3232 2d2d | 1 0 | (0 0) (0 0)
5395 12:42:33.623638 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 0) (1 0)
5396 12:42:33.626990 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5397 12:42:33.630629 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5398 12:42:33.636770 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5399 12:42:33.640397 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5400 12:42:33.643602 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5401 12:42:33.650659 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5402 12:42:33.654295 0 15 28 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
5403 12:42:33.657535 1 0 0 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
5404 12:42:33.660888 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5405 12:42:33.667142 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5406 12:42:33.671233 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5407 12:42:33.673841 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5408 12:42:33.680503 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5409 12:42:33.684522 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5410 12:42:33.687375 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5411 12:42:33.693842 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5412 12:42:33.697486 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 12:42:33.700779 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 12:42:33.707322 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 12:42:33.710878 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 12:42:33.714014 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 12:42:33.720477 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 12:42:33.723740 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 12:42:33.727084 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 12:42:33.730334 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 12:42:33.737389 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 12:42:33.740356 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 12:42:33.743646 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 12:42:33.750372 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 12:42:33.753902 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 12:42:33.757499 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5427 12:42:33.764443 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5428 12:42:33.767456 Total UI for P1: 0, mck2ui 16
5429 12:42:33.770178 best dqsien dly found for B0: ( 1, 2, 28)
5430 12:42:33.774194 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5431 12:42:33.777226 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5432 12:42:33.780561 Total UI for P1: 0, mck2ui 16
5433 12:42:33.783672 best dqsien dly found for B1: ( 1, 3, 2)
5434 12:42:33.787638 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5435 12:42:33.790813 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5436 12:42:33.790916
5437 12:42:33.797539 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5438 12:42:33.800582 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5439 12:42:33.800660 [Gating] SW calibration Done
5440 12:42:33.803934 ==
5441 12:42:33.804038 Dram Type= 6, Freq= 0, CH_0, rank 1
5442 12:42:33.811097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5443 12:42:33.811207 ==
5444 12:42:33.811291 RX Vref Scan: 0
5445 12:42:33.811379
5446 12:42:33.813626 RX Vref 0 -> 0, step: 1
5447 12:42:33.813732
5448 12:42:33.817472 RX Delay -80 -> 252, step: 8
5449 12:42:33.820668 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5450 12:42:33.824235 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5451 12:42:33.827501 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5452 12:42:33.831237 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5453 12:42:33.837280 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5454 12:42:33.840516 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5455 12:42:33.844070 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5456 12:42:33.846957 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5457 12:42:33.850707 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5458 12:42:33.853952 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5459 12:42:33.860736 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5460 12:42:33.863826 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5461 12:42:33.866980 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5462 12:42:33.870472 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5463 12:42:33.873640 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5464 12:42:33.877353 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5465 12:42:33.880947 ==
5466 12:42:33.881059 Dram Type= 6, Freq= 0, CH_0, rank 1
5467 12:42:33.887300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5468 12:42:33.887411 ==
5469 12:42:33.887503 DQS Delay:
5470 12:42:33.890714 DQS0 = 0, DQS1 = 0
5471 12:42:33.890814 DQM Delay:
5472 12:42:33.894780 DQM0 = 97, DQM1 = 86
5473 12:42:33.894850 DQ Delay:
5474 12:42:33.897813 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5475 12:42:33.900985 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =103
5476 12:42:33.904087 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =75
5477 12:42:33.907445 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =95
5478 12:42:33.907515
5479 12:42:33.907576
5480 12:42:33.907638 ==
5481 12:42:33.910512 Dram Type= 6, Freq= 0, CH_0, rank 1
5482 12:42:33.914185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5483 12:42:33.914287 ==
5484 12:42:33.914384
5485 12:42:33.914486
5486 12:42:33.917709 TX Vref Scan disable
5487 12:42:33.920638 == TX Byte 0 ==
5488 12:42:33.924456 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5489 12:42:33.927179 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5490 12:42:33.931496 == TX Byte 1 ==
5491 12:42:33.934285 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5492 12:42:33.937697 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5493 12:42:33.937805 ==
5494 12:42:33.940569 Dram Type= 6, Freq= 0, CH_0, rank 1
5495 12:42:33.944180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5496 12:42:33.947248 ==
5497 12:42:33.947352
5498 12:42:33.947440
5499 12:42:33.947528 TX Vref Scan disable
5500 12:42:33.950771 == TX Byte 0 ==
5501 12:42:33.954517 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5502 12:42:33.957736 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5503 12:42:33.960646 == TX Byte 1 ==
5504 12:42:33.964127 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5505 12:42:33.967235 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5506 12:42:33.970881
5507 12:42:33.971011 [DATLAT]
5508 12:42:33.971101 Freq=933, CH0 RK1
5509 12:42:33.971187
5510 12:42:33.974143 DATLAT Default: 0xb
5511 12:42:33.974238 0, 0xFFFF, sum = 0
5512 12:42:33.977409 1, 0xFFFF, sum = 0
5513 12:42:33.977510 2, 0xFFFF, sum = 0
5514 12:42:33.980606 3, 0xFFFF, sum = 0
5515 12:42:33.980706 4, 0xFFFF, sum = 0
5516 12:42:33.983890 5, 0xFFFF, sum = 0
5517 12:42:33.987307 6, 0xFFFF, sum = 0
5518 12:42:33.987404 7, 0xFFFF, sum = 0
5519 12:42:33.991099 8, 0xFFFF, sum = 0
5520 12:42:33.991196 9, 0xFFFF, sum = 0
5521 12:42:33.994557 10, 0x0, sum = 1
5522 12:42:33.994654 11, 0x0, sum = 2
5523 12:42:33.994744 12, 0x0, sum = 3
5524 12:42:33.997163 13, 0x0, sum = 4
5525 12:42:33.997231 best_step = 11
5526 12:42:33.997292
5527 12:42:33.997350 ==
5528 12:42:34.001197 Dram Type= 6, Freq= 0, CH_0, rank 1
5529 12:42:34.007279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5530 12:42:34.007377 ==
5531 12:42:34.007466 RX Vref Scan: 0
5532 12:42:34.007554
5533 12:42:34.010879 RX Vref 0 -> 0, step: 1
5534 12:42:34.010968
5535 12:42:34.014063 RX Delay -61 -> 252, step: 4
5536 12:42:34.017445 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5537 12:42:34.021407 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5538 12:42:34.027334 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5539 12:42:34.030703 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5540 12:42:34.033998 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5541 12:42:34.037962 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5542 12:42:34.040526 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5543 12:42:34.044181 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5544 12:42:34.050520 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5545 12:42:34.053861 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5546 12:42:34.056980 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5547 12:42:34.060566 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5548 12:42:34.063816 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5549 12:42:34.070606 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5550 12:42:34.074269 iDelay=199, Bit 14, Center 96 (11 ~ 182) 172
5551 12:42:34.077959 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5552 12:42:34.078061 ==
5553 12:42:34.080763 Dram Type= 6, Freq= 0, CH_0, rank 1
5554 12:42:34.084265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5555 12:42:34.084370 ==
5556 12:42:34.087720 DQS Delay:
5557 12:42:34.087795 DQS0 = 0, DQS1 = 0
5558 12:42:34.087855 DQM Delay:
5559 12:42:34.090552 DQM0 = 95, DQM1 = 87
5560 12:42:34.090651 DQ Delay:
5561 12:42:34.094007 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5562 12:42:34.097225 DQ4 =94, DQ5 =84, DQ6 =106, DQ7 =102
5563 12:42:34.100699 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =78
5564 12:42:34.104321 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =96
5565 12:42:34.104419
5566 12:42:34.104506
5567 12:42:34.113763 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a09, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5568 12:42:34.117143 CH0 RK1: MR19=505, MR18=1A09
5569 12:42:34.120459 CH0_RK1: MR19=0x505, MR18=0x1A09, DQSOSC=413, MR23=63, INC=63, DEC=42
5570 12:42:34.124111 [RxdqsGatingPostProcess] freq 933
5571 12:42:34.130872 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5572 12:42:34.134131 best DQS0 dly(2T, 0.5T) = (0, 11)
5573 12:42:34.137550 best DQS1 dly(2T, 0.5T) = (0, 11)
5574 12:42:34.140556 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5575 12:42:34.144230 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5576 12:42:34.147235 best DQS0 dly(2T, 0.5T) = (0, 10)
5577 12:42:34.147331 best DQS1 dly(2T, 0.5T) = (0, 11)
5578 12:42:34.150810 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5579 12:42:34.154509 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5580 12:42:34.158041 Pre-setting of DQS Precalculation
5581 12:42:34.164111 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5582 12:42:34.164213 ==
5583 12:42:34.167293 Dram Type= 6, Freq= 0, CH_1, rank 0
5584 12:42:34.170856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5585 12:42:34.170960 ==
5586 12:42:34.177345 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5587 12:42:34.184355 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5588 12:42:34.187266 [CA 0] Center 37 (7~67) winsize 61
5589 12:42:34.190973 [CA 1] Center 36 (6~67) winsize 62
5590 12:42:34.194326 [CA 2] Center 34 (4~64) winsize 61
5591 12:42:34.197278 [CA 3] Center 33 (3~64) winsize 62
5592 12:42:34.200740 [CA 4] Center 33 (3~64) winsize 62
5593 12:42:34.200848 [CA 5] Center 33 (3~64) winsize 62
5594 12:42:34.203940
5595 12:42:34.207392 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5596 12:42:34.207489
5597 12:42:34.210810 [CATrainingPosCal] consider 1 rank data
5598 12:42:34.214308 u2DelayCellTimex100 = 270/100 ps
5599 12:42:34.218000 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5600 12:42:34.221051 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5601 12:42:34.224087 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5602 12:42:34.227648 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5603 12:42:34.230894 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5604 12:42:34.234318 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5605 12:42:34.234436
5606 12:42:34.237478 CA PerBit enable=1, Macro0, CA PI delay=33
5607 12:42:34.237552
5608 12:42:34.240672 [CBTSetCACLKResult] CA Dly = 33
5609 12:42:34.244362 CS Dly: 4 (0~35)
5610 12:42:34.244469 ==
5611 12:42:34.247465 Dram Type= 6, Freq= 0, CH_1, rank 1
5612 12:42:34.251362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5613 12:42:34.251461 ==
5614 12:42:34.257598 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5615 12:42:34.263876 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5616 12:42:34.267671 [CA 0] Center 36 (6~67) winsize 62
5617 12:42:34.270729 [CA 1] Center 36 (6~67) winsize 62
5618 12:42:34.274286 [CA 2] Center 34 (4~64) winsize 61
5619 12:42:34.277499 [CA 3] Center 34 (4~64) winsize 61
5620 12:42:34.280926 [CA 4] Center 34 (4~64) winsize 61
5621 12:42:34.281027 [CA 5] Center 33 (3~63) winsize 61
5622 12:42:34.284384
5623 12:42:34.287745 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5624 12:42:34.287822
5625 12:42:34.290576 [CATrainingPosCal] consider 2 rank data
5626 12:42:34.293964 u2DelayCellTimex100 = 270/100 ps
5627 12:42:34.297504 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5628 12:42:34.300611 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5629 12:42:34.304119 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5630 12:42:34.307359 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5631 12:42:34.310743 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5632 12:42:34.314161 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5633 12:42:34.314263
5634 12:42:34.317492 CA PerBit enable=1, Macro0, CA PI delay=33
5635 12:42:34.317579
5636 12:42:34.320469 [CBTSetCACLKResult] CA Dly = 33
5637 12:42:34.324184 CS Dly: 5 (0~38)
5638 12:42:34.324284
5639 12:42:34.327040 ----->DramcWriteLeveling(PI) begin...
5640 12:42:34.327138 ==
5641 12:42:34.330316 Dram Type= 6, Freq= 0, CH_1, rank 0
5642 12:42:34.333946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5643 12:42:34.334055 ==
5644 12:42:34.336974 Write leveling (Byte 0): 27 => 27
5645 12:42:34.340385 Write leveling (Byte 1): 27 => 27
5646 12:42:34.345038 DramcWriteLeveling(PI) end<-----
5647 12:42:34.345139
5648 12:42:34.345232 ==
5649 12:42:34.347937 Dram Type= 6, Freq= 0, CH_1, rank 0
5650 12:42:34.350837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5651 12:42:34.350933 ==
5652 12:42:34.354092 [Gating] SW mode calibration
5653 12:42:34.360578 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5654 12:42:34.367145 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5655 12:42:34.370970 0 14 0 | B1->B0 | 2d2d 3131 | 0 1 | (0 0) (1 1)
5656 12:42:34.377773 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5657 12:42:34.380407 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5658 12:42:34.383743 0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5659 12:42:34.391097 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5660 12:42:34.393843 0 14 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5661 12:42:34.397316 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5662 12:42:34.400343 0 14 28 | B1->B0 | 3030 3030 | 1 1 | (1 0) (1 0)
5663 12:42:34.406919 0 15 0 | B1->B0 | 2929 2626 | 0 0 | (0 0) (0 0)
5664 12:42:34.410268 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5665 12:42:34.414163 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5666 12:42:34.420691 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5667 12:42:34.424035 0 15 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5668 12:42:34.427352 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5669 12:42:34.434007 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5670 12:42:34.437594 0 15 28 | B1->B0 | 2e2e 2525 | 1 1 | (0 0) (0 0)
5671 12:42:34.440606 1 0 0 | B1->B0 | 4343 4343 | 1 0 | (0 0) (0 0)
5672 12:42:34.447002 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5673 12:42:34.450726 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5674 12:42:34.454465 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5675 12:42:34.460690 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5676 12:42:34.463882 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5677 12:42:34.467699 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5678 12:42:34.474188 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5679 12:42:34.477052 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5680 12:42:34.480698 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 12:42:34.484339 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 12:42:34.490544 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 12:42:34.494708 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 12:42:34.497847 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5685 12:42:34.504236 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5686 12:42:34.507423 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 12:42:34.510919 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 12:42:34.517384 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 12:42:34.520574 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 12:42:34.523929 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 12:42:34.530581 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5692 12:42:34.533956 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5693 12:42:34.537170 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5694 12:42:34.543908 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5695 12:42:34.544014 Total UI for P1: 0, mck2ui 16
5696 12:42:34.550362 best dqsien dly found for B0: ( 1, 2, 26)
5697 12:42:34.553849 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5698 12:42:34.557503 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5699 12:42:34.560507 Total UI for P1: 0, mck2ui 16
5700 12:42:34.564005 best dqsien dly found for B1: ( 1, 2, 28)
5701 12:42:34.567296 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5702 12:42:34.570639 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5703 12:42:34.570723
5704 12:42:34.573816 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5705 12:42:34.580641 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5706 12:42:34.580751 [Gating] SW calibration Done
5707 12:42:34.580855 ==
5708 12:42:34.584129 Dram Type= 6, Freq= 0, CH_1, rank 0
5709 12:42:34.590659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5710 12:42:34.590748 ==
5711 12:42:34.590827 RX Vref Scan: 0
5712 12:42:34.590923
5713 12:42:34.594100 RX Vref 0 -> 0, step: 1
5714 12:42:34.594179
5715 12:42:34.597684 RX Delay -80 -> 252, step: 8
5716 12:42:34.600485 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5717 12:42:34.603732 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5718 12:42:34.607558 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5719 12:42:34.610567 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5720 12:42:34.617004 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5721 12:42:34.620411 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5722 12:42:34.624192 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5723 12:42:34.627339 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5724 12:42:34.631256 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5725 12:42:34.634147 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5726 12:42:34.640492 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5727 12:42:34.643969 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5728 12:42:34.647383 iDelay=200, Bit 12, Center 99 (0 ~ 199) 200
5729 12:42:34.650592 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5730 12:42:34.654325 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5731 12:42:34.660875 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5732 12:42:34.660977 ==
5733 12:42:34.663949 Dram Type= 6, Freq= 0, CH_1, rank 0
5734 12:42:34.667310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 12:42:34.667384 ==
5736 12:42:34.667446 DQS Delay:
5737 12:42:34.670777 DQS0 = 0, DQS1 = 0
5738 12:42:34.670859 DQM Delay:
5739 12:42:34.673771 DQM0 = 95, DQM1 = 89
5740 12:42:34.673847 DQ Delay:
5741 12:42:34.677033 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =95
5742 12:42:34.680280 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5743 12:42:34.683854 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5744 12:42:34.687031 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =95
5745 12:42:34.687113
5746 12:42:34.687176
5747 12:42:34.687235 ==
5748 12:42:34.690605 Dram Type= 6, Freq= 0, CH_1, rank 0
5749 12:42:34.694261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 12:42:34.694343 ==
5751 12:42:34.694413
5752 12:42:34.694473
5753 12:42:34.696989 TX Vref Scan disable
5754 12:42:34.700678 == TX Byte 0 ==
5755 12:42:34.703558 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5756 12:42:34.707035 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5757 12:42:34.710875 == TX Byte 1 ==
5758 12:42:34.713841 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5759 12:42:34.717048 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5760 12:42:34.717122 ==
5761 12:42:34.720623 Dram Type= 6, Freq= 0, CH_1, rank 0
5762 12:42:34.724383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5763 12:42:34.726993 ==
5764 12:42:34.727077
5765 12:42:34.727156
5766 12:42:34.727260 TX Vref Scan disable
5767 12:42:34.731004 == TX Byte 0 ==
5768 12:42:34.734175 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5769 12:42:34.741088 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5770 12:42:34.741171 == TX Byte 1 ==
5771 12:42:34.744280 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5772 12:42:34.747746 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5773 12:42:34.751227
5774 12:42:34.751308 [DATLAT]
5775 12:42:34.751372 Freq=933, CH1 RK0
5776 12:42:34.751431
5777 12:42:34.754170 DATLAT Default: 0xd
5778 12:42:34.754250 0, 0xFFFF, sum = 0
5779 12:42:34.757884 1, 0xFFFF, sum = 0
5780 12:42:34.757967 2, 0xFFFF, sum = 0
5781 12:42:34.760878 3, 0xFFFF, sum = 0
5782 12:42:34.760961 4, 0xFFFF, sum = 0
5783 12:42:34.764055 5, 0xFFFF, sum = 0
5784 12:42:34.764139 6, 0xFFFF, sum = 0
5785 12:42:34.768054 7, 0xFFFF, sum = 0
5786 12:42:34.771037 8, 0xFFFF, sum = 0
5787 12:42:34.771134 9, 0xFFFF, sum = 0
5788 12:42:34.774028 10, 0x0, sum = 1
5789 12:42:34.774111 11, 0x0, sum = 2
5790 12:42:34.774175 12, 0x0, sum = 3
5791 12:42:34.777713 13, 0x0, sum = 4
5792 12:42:34.777841 best_step = 11
5793 12:42:34.777912
5794 12:42:34.777972 ==
5795 12:42:34.780700 Dram Type= 6, Freq= 0, CH_1, rank 0
5796 12:42:34.787729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5797 12:42:34.787826 ==
5798 12:42:34.787890 RX Vref Scan: 1
5799 12:42:34.787949
5800 12:42:34.791030 RX Vref 0 -> 0, step: 1
5801 12:42:34.791111
5802 12:42:34.794348 RX Delay -61 -> 252, step: 4
5803 12:42:34.794465
5804 12:42:34.797375 Set Vref, RX VrefLevel [Byte0]: 57
5805 12:42:34.801181 [Byte1]: 49
5806 12:42:34.801257
5807 12:42:34.804053 Final RX Vref Byte 0 = 57 to rank0
5808 12:42:34.807535 Final RX Vref Byte 1 = 49 to rank0
5809 12:42:34.811330 Final RX Vref Byte 0 = 57 to rank1
5810 12:42:34.814520 Final RX Vref Byte 1 = 49 to rank1==
5811 12:42:34.817625 Dram Type= 6, Freq= 0, CH_1, rank 0
5812 12:42:34.821159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5813 12:42:34.821256 ==
5814 12:42:34.824508 DQS Delay:
5815 12:42:34.824617 DQS0 = 0, DQS1 = 0
5816 12:42:34.827581 DQM Delay:
5817 12:42:34.827660 DQM0 = 98, DQM1 = 90
5818 12:42:34.827723 DQ Delay:
5819 12:42:34.831318 DQ0 =100, DQ1 =92, DQ2 =88, DQ3 =96
5820 12:42:34.834355 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =96
5821 12:42:34.837321 DQ8 =82, DQ9 =80, DQ10 =90, DQ11 =84
5822 12:42:34.841322 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =94
5823 12:42:34.841402
5824 12:42:34.841464
5825 12:42:34.850660 [DQSOSCAuto] RK0, (LSB)MR18= 0x11ee, (MSB)MR19= 0x504, tDQSOscB0 = 428 ps tDQSOscB1 = 416 ps
5826 12:42:34.854000 CH1 RK0: MR19=504, MR18=11EE
5827 12:42:34.860833 CH1_RK0: MR19=0x504, MR18=0x11EE, DQSOSC=416, MR23=63, INC=62, DEC=41
5828 12:42:34.860914
5829 12:42:34.864075 ----->DramcWriteLeveling(PI) begin...
5830 12:42:34.864208 ==
5831 12:42:34.867852 Dram Type= 6, Freq= 0, CH_1, rank 1
5832 12:42:34.870881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5833 12:42:34.870962 ==
5834 12:42:34.873948 Write leveling (Byte 0): 26 => 26
5835 12:42:34.877332 Write leveling (Byte 1): 27 => 27
5836 12:42:34.880596 DramcWriteLeveling(PI) end<-----
5837 12:42:34.880681
5838 12:42:34.880743 ==
5839 12:42:34.883927 Dram Type= 6, Freq= 0, CH_1, rank 1
5840 12:42:34.887243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5841 12:42:34.887324 ==
5842 12:42:34.890677 [Gating] SW mode calibration
5843 12:42:34.897208 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5844 12:42:34.903936 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5845 12:42:34.907351 0 14 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5846 12:42:34.910666 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5847 12:42:34.917223 0 14 8 | B1->B0 | 3534 3434 | 1 1 | (1 1) (1 1)
5848 12:42:34.920484 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5849 12:42:34.924358 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5850 12:42:34.930728 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5851 12:42:34.934197 0 14 24 | B1->B0 | 3232 3030 | 0 0 | (0 0) (0 1)
5852 12:42:34.937101 0 14 28 | B1->B0 | 2a29 2323 | 1 0 | (0 0) (0 0)
5853 12:42:34.944300 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5854 12:42:34.947002 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5855 12:42:34.950681 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5856 12:42:34.957787 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5857 12:42:34.960061 0 15 16 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
5858 12:42:34.963559 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5859 12:42:34.967092 0 15 24 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
5860 12:42:34.973581 0 15 28 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (0 0)
5861 12:42:34.977060 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5862 12:42:34.980436 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5863 12:42:34.986816 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5864 12:42:34.990793 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5865 12:42:34.993980 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5866 12:42:35.000374 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5867 12:42:35.003386 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5868 12:42:35.006762 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5869 12:42:35.013617 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 12:42:35.016679 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 12:42:35.020057 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 12:42:35.026791 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5873 12:42:35.030378 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 12:42:35.033563 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5875 12:42:35.040226 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5876 12:42:35.043959 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 12:42:35.046832 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 12:42:35.054065 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 12:42:35.057235 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 12:42:35.060123 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5881 12:42:35.063513 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5882 12:42:35.070264 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5883 12:42:35.073588 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5884 12:42:35.076795 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5885 12:42:35.080799 Total UI for P1: 0, mck2ui 16
5886 12:42:35.083660 best dqsien dly found for B0: ( 1, 2, 24)
5887 12:42:35.087351 Total UI for P1: 0, mck2ui 16
5888 12:42:35.090622 best dqsien dly found for B1: ( 1, 2, 26)
5889 12:42:35.094344 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5890 12:42:35.096974 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5891 12:42:35.097054
5892 12:42:35.103596 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5893 12:42:35.106960 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5894 12:42:35.110191 [Gating] SW calibration Done
5895 12:42:35.110271 ==
5896 12:42:35.113634 Dram Type= 6, Freq= 0, CH_1, rank 1
5897 12:42:35.117130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5898 12:42:35.117210 ==
5899 12:42:35.117274 RX Vref Scan: 0
5900 12:42:35.117332
5901 12:42:35.120540 RX Vref 0 -> 0, step: 1
5902 12:42:35.120620
5903 12:42:35.124030 RX Delay -80 -> 252, step: 8
5904 12:42:35.127088 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5905 12:42:35.130748 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5906 12:42:35.133640 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5907 12:42:35.140324 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5908 12:42:35.143626 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5909 12:42:35.146974 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5910 12:42:35.150774 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5911 12:42:35.153805 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5912 12:42:35.157044 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5913 12:42:35.163902 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5914 12:42:35.167037 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5915 12:42:35.170275 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5916 12:42:35.174238 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5917 12:42:35.177332 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5918 12:42:35.180413 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5919 12:42:35.187691 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5920 12:42:35.187772 ==
5921 12:42:35.191176 Dram Type= 6, Freq= 0, CH_1, rank 1
5922 12:42:35.193913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5923 12:42:35.193993 ==
5924 12:42:35.194056 DQS Delay:
5925 12:42:35.197398 DQS0 = 0, DQS1 = 0
5926 12:42:35.197478 DQM Delay:
5927 12:42:35.200387 DQM0 = 94, DQM1 = 88
5928 12:42:35.200467 DQ Delay:
5929 12:42:35.203867 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5930 12:42:35.207786 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5931 12:42:35.210678 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5932 12:42:35.213858 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5933 12:42:35.213938
5934 12:42:35.214001
5935 12:42:35.214060 ==
5936 12:42:35.217131 Dram Type= 6, Freq= 0, CH_1, rank 1
5937 12:42:35.220584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5938 12:42:35.220665 ==
5939 12:42:35.220728
5940 12:42:35.223938
5941 12:42:35.224018 TX Vref Scan disable
5942 12:42:35.227815 == TX Byte 0 ==
5943 12:42:35.231081 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5944 12:42:35.233589 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5945 12:42:35.237486 == TX Byte 1 ==
5946 12:42:35.240275 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5947 12:42:35.243698 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5948 12:42:35.243779 ==
5949 12:42:35.247179 Dram Type= 6, Freq= 0, CH_1, rank 1
5950 12:42:35.253502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5951 12:42:35.253582 ==
5952 12:42:35.253646
5953 12:42:35.253704
5954 12:42:35.253760 TX Vref Scan disable
5955 12:42:35.258035 == TX Byte 0 ==
5956 12:42:35.260983 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5957 12:42:35.264429 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5958 12:42:35.267640 == TX Byte 1 ==
5959 12:42:35.271300 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5960 12:42:35.277727 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5961 12:42:35.277808
5962 12:42:35.277871 [DATLAT]
5963 12:42:35.277930 Freq=933, CH1 RK1
5964 12:42:35.277987
5965 12:42:35.281140 DATLAT Default: 0xb
5966 12:42:35.281220 0, 0xFFFF, sum = 0
5967 12:42:35.284432 1, 0xFFFF, sum = 0
5968 12:42:35.284514 2, 0xFFFF, sum = 0
5969 12:42:35.287475 3, 0xFFFF, sum = 0
5970 12:42:35.291469 4, 0xFFFF, sum = 0
5971 12:42:35.291551 5, 0xFFFF, sum = 0
5972 12:42:35.294532 6, 0xFFFF, sum = 0
5973 12:42:35.294614 7, 0xFFFF, sum = 0
5974 12:42:35.297510 8, 0xFFFF, sum = 0
5975 12:42:35.297591 9, 0xFFFF, sum = 0
5976 12:42:35.300813 10, 0x0, sum = 1
5977 12:42:35.300894 11, 0x0, sum = 2
5978 12:42:35.304032 12, 0x0, sum = 3
5979 12:42:35.304118 13, 0x0, sum = 4
5980 12:42:35.304183 best_step = 11
5981 12:42:35.304241
5982 12:42:35.307548 ==
5983 12:42:35.310665 Dram Type= 6, Freq= 0, CH_1, rank 1
5984 12:42:35.314887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5985 12:42:35.314968 ==
5986 12:42:35.315032 RX Vref Scan: 0
5987 12:42:35.315090
5988 12:42:35.317662 RX Vref 0 -> 0, step: 1
5989 12:42:35.317742
5990 12:42:35.320736 RX Delay -61 -> 252, step: 4
5991 12:42:35.324151 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5992 12:42:35.330805 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5993 12:42:35.334606 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5994 12:42:35.337811 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5995 12:42:35.340802 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5996 12:42:35.344421 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5997 12:42:35.347186 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5998 12:42:35.354135 iDelay=199, Bit 7, Center 92 (3 ~ 182) 180
5999 12:42:35.357340 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
6000 12:42:35.360867 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
6001 12:42:35.363911 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
6002 12:42:35.367620 iDelay=199, Bit 11, Center 84 (-5 ~ 174) 180
6003 12:42:35.371496 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
6004 12:42:35.377628 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
6005 12:42:35.380741 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
6006 12:42:35.384173 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
6007 12:42:35.384253 ==
6008 12:42:35.387793 Dram Type= 6, Freq= 0, CH_1, rank 1
6009 12:42:35.390928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6010 12:42:35.391009 ==
6011 12:42:35.393703 DQS Delay:
6012 12:42:35.393783 DQS0 = 0, DQS1 = 0
6013 12:42:35.397272 DQM Delay:
6014 12:42:35.397351 DQM0 = 96, DQM1 = 90
6015 12:42:35.397415 DQ Delay:
6016 12:42:35.400787 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =94
6017 12:42:35.404039 DQ4 =98, DQ5 =106, DQ6 =104, DQ7 =92
6018 12:42:35.407177 DQ8 =78, DQ9 =78, DQ10 =90, DQ11 =84
6019 12:42:35.411097 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =98
6020 12:42:35.411177
6021 12:42:35.411240
6022 12:42:35.420813 [DQSOSCAuto] RK1, (LSB)MR18= 0x101a, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
6023 12:42:35.423809 CH1 RK1: MR19=505, MR18=101A
6024 12:42:35.427156 CH1_RK1: MR19=0x505, MR18=0x101A, DQSOSC=413, MR23=63, INC=63, DEC=42
6025 12:42:35.430647 [RxdqsGatingPostProcess] freq 933
6026 12:42:35.437550 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6027 12:42:35.440740 best DQS0 dly(2T, 0.5T) = (0, 10)
6028 12:42:35.444162 best DQS1 dly(2T, 0.5T) = (0, 10)
6029 12:42:35.447703 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6030 12:42:35.450765 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6031 12:42:35.453666 best DQS0 dly(2T, 0.5T) = (0, 10)
6032 12:42:35.457125 best DQS1 dly(2T, 0.5T) = (0, 10)
6033 12:42:35.460426 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6034 12:42:35.464456 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6035 12:42:35.466972 Pre-setting of DQS Precalculation
6036 12:42:35.470667 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6037 12:42:35.477141 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6038 12:42:35.484373 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6039 12:42:35.484455
6040 12:42:35.484518
6041 12:42:35.487313 [Calibration Summary] 1866 Mbps
6042 12:42:35.490840 CH 0, Rank 0
6043 12:42:35.490921 SW Impedance : PASS
6044 12:42:35.494095 DUTY Scan : NO K
6045 12:42:35.497659 ZQ Calibration : PASS
6046 12:42:35.497739 Jitter Meter : NO K
6047 12:42:35.501056 CBT Training : PASS
6048 12:42:35.504184 Write leveling : PASS
6049 12:42:35.504264 RX DQS gating : PASS
6050 12:42:35.507801 RX DQ/DQS(RDDQC) : PASS
6051 12:42:35.507880 TX DQ/DQS : PASS
6052 12:42:35.510668 RX DATLAT : PASS
6053 12:42:35.513851 RX DQ/DQS(Engine): PASS
6054 12:42:35.513931 TX OE : NO K
6055 12:42:35.517633 All Pass.
6056 12:42:35.517713
6057 12:42:35.517776 CH 0, Rank 1
6058 12:42:35.520818 SW Impedance : PASS
6059 12:42:35.520898 DUTY Scan : NO K
6060 12:42:35.524540 ZQ Calibration : PASS
6061 12:42:35.528230 Jitter Meter : NO K
6062 12:42:35.528310 CBT Training : PASS
6063 12:42:35.530596 Write leveling : PASS
6064 12:42:35.534306 RX DQS gating : PASS
6065 12:42:35.534388 RX DQ/DQS(RDDQC) : PASS
6066 12:42:35.537525 TX DQ/DQS : PASS
6067 12:42:35.541276 RX DATLAT : PASS
6068 12:42:35.541356 RX DQ/DQS(Engine): PASS
6069 12:42:35.544567 TX OE : NO K
6070 12:42:35.544648 All Pass.
6071 12:42:35.544711
6072 12:42:35.548085 CH 1, Rank 0
6073 12:42:35.548165 SW Impedance : PASS
6074 12:42:35.550344 DUTY Scan : NO K
6075 12:42:35.550447 ZQ Calibration : PASS
6076 12:42:35.554268 Jitter Meter : NO K
6077 12:42:35.557507 CBT Training : PASS
6078 12:42:35.557587 Write leveling : PASS
6079 12:42:35.560841 RX DQS gating : PASS
6080 12:42:35.564527 RX DQ/DQS(RDDQC) : PASS
6081 12:42:35.564607 TX DQ/DQS : PASS
6082 12:42:35.567522 RX DATLAT : PASS
6083 12:42:35.570610 RX DQ/DQS(Engine): PASS
6084 12:42:35.570690 TX OE : NO K
6085 12:42:35.573854 All Pass.
6086 12:42:35.573933
6087 12:42:35.573996 CH 1, Rank 1
6088 12:42:35.577505 SW Impedance : PASS
6089 12:42:35.577585 DUTY Scan : NO K
6090 12:42:35.580515 ZQ Calibration : PASS
6091 12:42:35.584005 Jitter Meter : NO K
6092 12:42:35.584086 CBT Training : PASS
6093 12:42:35.587658 Write leveling : PASS
6094 12:42:35.591279 RX DQS gating : PASS
6095 12:42:35.591359 RX DQ/DQS(RDDQC) : PASS
6096 12:42:35.593996 TX DQ/DQS : PASS
6097 12:42:35.594077 RX DATLAT : PASS
6098 12:42:35.597507 RX DQ/DQS(Engine): PASS
6099 12:42:35.600856 TX OE : NO K
6100 12:42:35.600937 All Pass.
6101 12:42:35.601001
6102 12:42:35.604735 DramC Write-DBI off
6103 12:42:35.604817 PER_BANK_REFRESH: Hybrid Mode
6104 12:42:35.608012 TX_TRACKING: ON
6105 12:42:35.617622 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6106 12:42:35.620941 [FAST_K] Save calibration result to emmc
6107 12:42:35.624407 dramc_set_vcore_voltage set vcore to 650000
6108 12:42:35.624483 Read voltage for 400, 6
6109 12:42:35.627445 Vio18 = 0
6110 12:42:35.627544 Vcore = 650000
6111 12:42:35.627648 Vdram = 0
6112 12:42:35.630838 Vddq = 0
6113 12:42:35.630904 Vmddr = 0
6114 12:42:35.634448 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6115 12:42:35.640753 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6116 12:42:35.644352 MEM_TYPE=3, freq_sel=20
6117 12:42:35.647292 sv_algorithm_assistance_LP4_800
6118 12:42:35.650765 ============ PULL DRAM RESETB DOWN ============
6119 12:42:35.653979 ========== PULL DRAM RESETB DOWN end =========
6120 12:42:35.660729 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6121 12:42:35.660842 ===================================
6122 12:42:35.664483 LPDDR4 DRAM CONFIGURATION
6123 12:42:35.667663 ===================================
6124 12:42:35.670745 EX_ROW_EN[0] = 0x0
6125 12:42:35.670826 EX_ROW_EN[1] = 0x0
6126 12:42:35.673998 LP4Y_EN = 0x0
6127 12:42:35.674079 WORK_FSP = 0x0
6128 12:42:35.677477 WL = 0x2
6129 12:42:35.677558 RL = 0x2
6130 12:42:35.680527 BL = 0x2
6131 12:42:35.680607 RPST = 0x0
6132 12:42:35.683906 RD_PRE = 0x0
6133 12:42:35.687120 WR_PRE = 0x1
6134 12:42:35.687200 WR_PST = 0x0
6135 12:42:35.691257 DBI_WR = 0x0
6136 12:42:35.691337 DBI_RD = 0x0
6137 12:42:35.694313 OTF = 0x1
6138 12:42:35.697180 ===================================
6139 12:42:35.700983 ===================================
6140 12:42:35.701064 ANA top config
6141 12:42:35.704234 ===================================
6142 12:42:35.707241 DLL_ASYNC_EN = 0
6143 12:42:35.707322 ALL_SLAVE_EN = 1
6144 12:42:35.710370 NEW_RANK_MODE = 1
6145 12:42:35.713861 DLL_IDLE_MODE = 1
6146 12:42:35.717762 LP45_APHY_COMB_EN = 1
6147 12:42:35.721326 TX_ODT_DIS = 1
6148 12:42:35.721407 NEW_8X_MODE = 1
6149 12:42:35.723626 ===================================
6150 12:42:35.727171 ===================================
6151 12:42:35.730377 data_rate = 800
6152 12:42:35.733941 CKR = 1
6153 12:42:35.737650 DQ_P2S_RATIO = 4
6154 12:42:35.740326 ===================================
6155 12:42:35.743826 CA_P2S_RATIO = 4
6156 12:42:35.743907 DQ_CA_OPEN = 0
6157 12:42:35.748114 DQ_SEMI_OPEN = 1
6158 12:42:35.750811 CA_SEMI_OPEN = 1
6159 12:42:35.754429 CA_FULL_RATE = 0
6160 12:42:35.757914 DQ_CKDIV4_EN = 0
6161 12:42:35.761536 CA_CKDIV4_EN = 1
6162 12:42:35.761651 CA_PREDIV_EN = 0
6163 12:42:35.764221 PH8_DLY = 0
6164 12:42:35.767704 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6165 12:42:35.770775 DQ_AAMCK_DIV = 0
6166 12:42:35.774587 CA_AAMCK_DIV = 0
6167 12:42:35.777448 CA_ADMCK_DIV = 4
6168 12:42:35.777520 DQ_TRACK_CA_EN = 0
6169 12:42:35.780598 CA_PICK = 800
6170 12:42:35.784042 CA_MCKIO = 400
6171 12:42:35.787423 MCKIO_SEMI = 400
6172 12:42:35.791057 PLL_FREQ = 3016
6173 12:42:35.793973 DQ_UI_PI_RATIO = 32
6174 12:42:35.797425 CA_UI_PI_RATIO = 32
6175 12:42:35.800781 ===================================
6176 12:42:35.803959 ===================================
6177 12:42:35.804029 memory_type:LPDDR4
6178 12:42:35.807418 GP_NUM : 10
6179 12:42:35.810643 SRAM_EN : 1
6180 12:42:35.810718 MD32_EN : 0
6181 12:42:35.813659 ===================================
6182 12:42:35.817322 [ANA_INIT] >>>>>>>>>>>>>>
6183 12:42:35.820418 <<<<<< [CONFIGURE PHASE]: ANA_TX
6184 12:42:35.824672 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6185 12:42:35.827664 ===================================
6186 12:42:35.831046 data_rate = 800,PCW = 0X7400
6187 12:42:35.834455 ===================================
6188 12:42:35.837527 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6189 12:42:35.840725 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6190 12:42:35.854121 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6191 12:42:35.857397 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6192 12:42:35.860689 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6193 12:42:35.864611 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6194 12:42:35.867586 [ANA_INIT] flow start
6195 12:42:35.867660 [ANA_INIT] PLL >>>>>>>>
6196 12:42:35.870553 [ANA_INIT] PLL <<<<<<<<
6197 12:42:35.874066 [ANA_INIT] MIDPI >>>>>>>>
6198 12:42:35.874144 [ANA_INIT] MIDPI <<<<<<<<
6199 12:42:35.877604 [ANA_INIT] DLL >>>>>>>>
6200 12:42:35.881005 [ANA_INIT] flow end
6201 12:42:35.883874 ============ LP4 DIFF to SE enter ============
6202 12:42:35.887569 ============ LP4 DIFF to SE exit ============
6203 12:42:35.890855 [ANA_INIT] <<<<<<<<<<<<<
6204 12:42:35.894374 [Flow] Enable top DCM control >>>>>
6205 12:42:35.897636 [Flow] Enable top DCM control <<<<<
6206 12:42:35.900930 Enable DLL master slave shuffle
6207 12:42:35.904342 ==============================================================
6208 12:42:35.907397 Gating Mode config
6209 12:42:35.914290 ==============================================================
6210 12:42:35.914373 Config description:
6211 12:42:35.924917 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6212 12:42:35.931282 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6213 12:42:35.934647 SELPH_MODE 0: By rank 1: By Phase
6214 12:42:35.940997 ==============================================================
6215 12:42:35.944373 GAT_TRACK_EN = 0
6216 12:42:35.947549 RX_GATING_MODE = 2
6217 12:42:35.951102 RX_GATING_TRACK_MODE = 2
6218 12:42:35.954167 SELPH_MODE = 1
6219 12:42:35.957199 PICG_EARLY_EN = 1
6220 12:42:35.960644 VALID_LAT_VALUE = 1
6221 12:42:35.964015 ==============================================================
6222 12:42:35.967765 Enter into Gating configuration >>>>
6223 12:42:35.970824 Exit from Gating configuration <<<<
6224 12:42:35.974524 Enter into DVFS_PRE_config >>>>>
6225 12:42:35.987080 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6226 12:42:35.987162 Exit from DVFS_PRE_config <<<<<
6227 12:42:35.990857 Enter into PICG configuration >>>>
6228 12:42:35.994647 Exit from PICG configuration <<<<
6229 12:42:35.997481 [RX_INPUT] configuration >>>>>
6230 12:42:36.000786 [RX_INPUT] configuration <<<<<
6231 12:42:36.007153 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6232 12:42:36.010646 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6233 12:42:36.017525 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6234 12:42:36.024016 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6235 12:42:36.030592 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6236 12:42:36.037620 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6237 12:42:36.040685 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6238 12:42:36.043980 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6239 12:42:36.047867 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6240 12:42:36.054199 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6241 12:42:36.057272 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6242 12:42:36.060442 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6243 12:42:36.063841 ===================================
6244 12:42:36.067098 LPDDR4 DRAM CONFIGURATION
6245 12:42:36.070722 ===================================
6246 12:42:36.070802 EX_ROW_EN[0] = 0x0
6247 12:42:36.073757 EX_ROW_EN[1] = 0x0
6248 12:42:36.073828 LP4Y_EN = 0x0
6249 12:42:36.077481 WORK_FSP = 0x0
6250 12:42:36.077551 WL = 0x2
6251 12:42:36.080488 RL = 0x2
6252 12:42:36.083855 BL = 0x2
6253 12:42:36.083929 RPST = 0x0
6254 12:42:36.087180 RD_PRE = 0x0
6255 12:42:36.087254 WR_PRE = 0x1
6256 12:42:36.090497 WR_PST = 0x0
6257 12:42:36.090568 DBI_WR = 0x0
6258 12:42:36.094206 DBI_RD = 0x0
6259 12:42:36.094280 OTF = 0x1
6260 12:42:36.097163 ===================================
6261 12:42:36.100692 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6262 12:42:36.107011 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6263 12:42:36.110529 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6264 12:42:36.114269 ===================================
6265 12:42:36.116990 LPDDR4 DRAM CONFIGURATION
6266 12:42:36.120535 ===================================
6267 12:42:36.120607 EX_ROW_EN[0] = 0x10
6268 12:42:36.124183 EX_ROW_EN[1] = 0x0
6269 12:42:36.124258 LP4Y_EN = 0x0
6270 12:42:36.127525 WORK_FSP = 0x0
6271 12:42:36.127595 WL = 0x2
6272 12:42:36.130935 RL = 0x2
6273 12:42:36.131006 BL = 0x2
6274 12:42:36.133762 RPST = 0x0
6275 12:42:36.133831 RD_PRE = 0x0
6276 12:42:36.137133 WR_PRE = 0x1
6277 12:42:36.137204 WR_PST = 0x0
6278 12:42:36.140898 DBI_WR = 0x0
6279 12:42:36.143721 DBI_RD = 0x0
6280 12:42:36.143795 OTF = 0x1
6281 12:42:36.147429 ===================================
6282 12:42:36.154477 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6283 12:42:36.157550 nWR fixed to 30
6284 12:42:36.160464 [ModeRegInit_LP4] CH0 RK0
6285 12:42:36.160539 [ModeRegInit_LP4] CH0 RK1
6286 12:42:36.163813 [ModeRegInit_LP4] CH1 RK0
6287 12:42:36.167412 [ModeRegInit_LP4] CH1 RK1
6288 12:42:36.167536 match AC timing 19
6289 12:42:36.174269 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6290 12:42:36.177487 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6291 12:42:36.180958 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6292 12:42:36.187188 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6293 12:42:36.190593 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6294 12:42:36.190670 ==
6295 12:42:36.193830 Dram Type= 6, Freq= 0, CH_0, rank 0
6296 12:42:36.197540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6297 12:42:36.197615 ==
6298 12:42:36.204345 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6299 12:42:36.211085 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6300 12:42:36.213972 [CA 0] Center 36 (8~64) winsize 57
6301 12:42:36.217468 [CA 1] Center 36 (8~64) winsize 57
6302 12:42:36.217547 [CA 2] Center 36 (8~64) winsize 57
6303 12:42:36.220822 [CA 3] Center 36 (8~64) winsize 57
6304 12:42:36.224024 [CA 4] Center 36 (8~64) winsize 57
6305 12:42:36.227632 [CA 5] Center 36 (8~64) winsize 57
6306 12:42:36.227712
6307 12:42:36.230542 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6308 12:42:36.230636
6309 12:42:36.237772 [CATrainingPosCal] consider 1 rank data
6310 12:42:36.237891 u2DelayCellTimex100 = 270/100 ps
6311 12:42:36.240928 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 12:42:36.247636 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 12:42:36.251057 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 12:42:36.254568 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 12:42:36.257843 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 12:42:36.260966 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 12:42:36.261046
6318 12:42:36.264158 CA PerBit enable=1, Macro0, CA PI delay=36
6319 12:42:36.264264
6320 12:42:36.267514 [CBTSetCACLKResult] CA Dly = 36
6321 12:42:36.267601 CS Dly: 1 (0~32)
6322 12:42:36.271076 ==
6323 12:42:36.274031 Dram Type= 6, Freq= 0, CH_0, rank 1
6324 12:42:36.277961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6325 12:42:36.278041 ==
6326 12:42:36.280796 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6327 12:42:36.287530 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6328 12:42:36.291118 [CA 0] Center 36 (8~64) winsize 57
6329 12:42:36.294295 [CA 1] Center 36 (8~64) winsize 57
6330 12:42:36.298217 [CA 2] Center 36 (8~64) winsize 57
6331 12:42:36.300924 [CA 3] Center 36 (8~64) winsize 57
6332 12:42:36.304466 [CA 4] Center 36 (8~64) winsize 57
6333 12:42:36.308075 [CA 5] Center 36 (8~64) winsize 57
6334 12:42:36.308155
6335 12:42:36.311098 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6336 12:42:36.311178
6337 12:42:36.314727 [CATrainingPosCal] consider 2 rank data
6338 12:42:36.317750 u2DelayCellTimex100 = 270/100 ps
6339 12:42:36.320698 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6340 12:42:36.324130 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6341 12:42:36.327466 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6342 12:42:36.330649 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6343 12:42:36.334166 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6344 12:42:36.337817 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6345 12:42:36.341326
6346 12:42:36.344378 CA PerBit enable=1, Macro0, CA PI delay=36
6347 12:42:36.344459
6348 12:42:36.347931 [CBTSetCACLKResult] CA Dly = 36
6349 12:42:36.348010 CS Dly: 1 (0~32)
6350 12:42:36.348072
6351 12:42:36.351611 ----->DramcWriteLeveling(PI) begin...
6352 12:42:36.351693 ==
6353 12:42:36.354251 Dram Type= 6, Freq= 0, CH_0, rank 0
6354 12:42:36.357739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6355 12:42:36.361153 ==
6356 12:42:36.361259 Write leveling (Byte 0): 40 => 8
6357 12:42:36.364199 Write leveling (Byte 1): 32 => 0
6358 12:42:36.367727 DramcWriteLeveling(PI) end<-----
6359 12:42:36.367831
6360 12:42:36.367920 ==
6361 12:42:36.371094 Dram Type= 6, Freq= 0, CH_0, rank 0
6362 12:42:36.377508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6363 12:42:36.377626 ==
6364 12:42:36.377704 [Gating] SW mode calibration
6365 12:42:36.387899 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6366 12:42:36.390531 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6367 12:42:36.394268 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6368 12:42:36.400697 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6369 12:42:36.404202 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6370 12:42:36.407249 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6371 12:42:36.413909 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6372 12:42:36.417089 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6373 12:42:36.420643 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6374 12:42:36.427423 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6375 12:42:36.431142 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6376 12:42:36.434266 Total UI for P1: 0, mck2ui 16
6377 12:42:36.437211 best dqsien dly found for B0: ( 0, 14, 24)
6378 12:42:36.440921 Total UI for P1: 0, mck2ui 16
6379 12:42:36.444237 best dqsien dly found for B1: ( 0, 14, 24)
6380 12:42:36.447719 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6381 12:42:36.451049 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6382 12:42:36.451129
6383 12:42:36.454252 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6384 12:42:36.457766 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6385 12:42:36.461533 [Gating] SW calibration Done
6386 12:42:36.461612 ==
6387 12:42:36.464007 Dram Type= 6, Freq= 0, CH_0, rank 0
6388 12:42:36.467631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6389 12:42:36.467711 ==
6390 12:42:36.471074 RX Vref Scan: 0
6391 12:42:36.471152
6392 12:42:36.474547 RX Vref 0 -> 0, step: 1
6393 12:42:36.474625
6394 12:42:36.477504 RX Delay -410 -> 252, step: 16
6395 12:42:36.480896 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6396 12:42:36.483927 iDelay=230, Bit 1, Center -19 (-266 ~ 229) 496
6397 12:42:36.487381 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6398 12:42:36.494110 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6399 12:42:36.497597 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6400 12:42:36.501112 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6401 12:42:36.504212 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6402 12:42:36.510602 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6403 12:42:36.514196 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6404 12:42:36.517414 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6405 12:42:36.520772 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6406 12:42:36.527432 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6407 12:42:36.531297 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6408 12:42:36.534417 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6409 12:42:36.537733 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6410 12:42:36.545092 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6411 12:42:36.545166 ==
6412 12:42:36.547763 Dram Type= 6, Freq= 0, CH_0, rank 0
6413 12:42:36.550897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6414 12:42:36.550966 ==
6415 12:42:36.551024 DQS Delay:
6416 12:42:36.554244 DQS0 = 35, DQS1 = 51
6417 12:42:36.554318 DQM Delay:
6418 12:42:36.557757 DQM0 = 9, DQM1 = 10
6419 12:42:36.557826 DQ Delay:
6420 12:42:36.561041 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =0
6421 12:42:36.564194 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6422 12:42:36.568037 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6423 12:42:36.571390 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6424 12:42:36.571501
6425 12:42:36.571587
6426 12:42:36.571674 ==
6427 12:42:36.574486 Dram Type= 6, Freq= 0, CH_0, rank 0
6428 12:42:36.577792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6429 12:42:36.577861 ==
6430 12:42:36.577920
6431 12:42:36.577979
6432 12:42:36.580670 TX Vref Scan disable
6433 12:42:36.580740 == TX Byte 0 ==
6434 12:42:36.587485 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6435 12:42:36.590788 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6436 12:42:36.590890 == TX Byte 1 ==
6437 12:42:36.598077 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6438 12:42:36.601150 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6439 12:42:36.601226 ==
6440 12:42:36.604847 Dram Type= 6, Freq= 0, CH_0, rank 0
6441 12:42:36.607630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6442 12:42:36.607700 ==
6443 12:42:36.607763
6444 12:42:36.607853
6445 12:42:36.610994 TX Vref Scan disable
6446 12:42:36.611086 == TX Byte 0 ==
6447 12:42:36.618287 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6448 12:42:36.621676 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6449 12:42:36.621749 == TX Byte 1 ==
6450 12:42:36.628476 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6451 12:42:36.631158 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6452 12:42:36.631237
6453 12:42:36.631299 [DATLAT]
6454 12:42:36.634944 Freq=400, CH0 RK0
6455 12:42:36.635015
6456 12:42:36.635074 DATLAT Default: 0xf
6457 12:42:36.638358 0, 0xFFFF, sum = 0
6458 12:42:36.638480 1, 0xFFFF, sum = 0
6459 12:42:36.641210 2, 0xFFFF, sum = 0
6460 12:42:36.641275 3, 0xFFFF, sum = 0
6461 12:42:36.644992 4, 0xFFFF, sum = 0
6462 12:42:36.645069 5, 0xFFFF, sum = 0
6463 12:42:36.647674 6, 0xFFFF, sum = 0
6464 12:42:36.647748 7, 0xFFFF, sum = 0
6465 12:42:36.651473 8, 0xFFFF, sum = 0
6466 12:42:36.651545 9, 0xFFFF, sum = 0
6467 12:42:36.654709 10, 0xFFFF, sum = 0
6468 12:42:36.657605 11, 0xFFFF, sum = 0
6469 12:42:36.657700 12, 0xFFFF, sum = 0
6470 12:42:36.661379 13, 0x0, sum = 1
6471 12:42:36.661448 14, 0x0, sum = 2
6472 12:42:36.664228 15, 0x0, sum = 3
6473 12:42:36.664301 16, 0x0, sum = 4
6474 12:42:36.664361 best_step = 14
6475 12:42:36.664417
6476 12:42:36.668194 ==
6477 12:42:36.670869 Dram Type= 6, Freq= 0, CH_0, rank 0
6478 12:42:36.674808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 12:42:36.674878 ==
6480 12:42:36.674938 RX Vref Scan: 1
6481 12:42:36.674994
6482 12:42:36.677934 RX Vref 0 -> 0, step: 1
6483 12:42:36.678013
6484 12:42:36.681371 RX Delay -343 -> 252, step: 8
6485 12:42:36.681488
6486 12:42:36.684151 Set Vref, RX VrefLevel [Byte0]: 54
6487 12:42:36.687839 [Byte1]: 50
6488 12:42:36.691272
6489 12:42:36.691346 Final RX Vref Byte 0 = 54 to rank0
6490 12:42:36.694923 Final RX Vref Byte 1 = 50 to rank0
6491 12:42:36.697971 Final RX Vref Byte 0 = 54 to rank1
6492 12:42:36.701764 Final RX Vref Byte 1 = 50 to rank1==
6493 12:42:36.704291 Dram Type= 6, Freq= 0, CH_0, rank 0
6494 12:42:36.711564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 12:42:36.711649 ==
6496 12:42:36.711712 DQS Delay:
6497 12:42:36.711771 DQS0 = 44, DQS1 = 60
6498 12:42:36.714713 DQM Delay:
6499 12:42:36.714792 DQM0 = 12, DQM1 = 15
6500 12:42:36.718073 DQ Delay:
6501 12:42:36.721403 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =12
6502 12:42:36.721483 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6503 12:42:36.724501 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6504 12:42:36.728269 DQ12 =24, DQ13 =20, DQ14 =28, DQ15 =28
6505 12:42:36.728380
6506 12:42:36.731278
6507 12:42:36.737917 [DQSOSCAuto] RK0, (LSB)MR18= 0x8554, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 393 ps
6508 12:42:36.740952 CH0 RK0: MR19=C0C, MR18=8554
6509 12:42:36.747694 CH0_RK0: MR19=0xC0C, MR18=0x8554, DQSOSC=393, MR23=63, INC=382, DEC=254
6510 12:42:36.747777 ==
6511 12:42:36.750955 Dram Type= 6, Freq= 0, CH_0, rank 1
6512 12:42:36.755128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6513 12:42:36.755210 ==
6514 12:42:36.757668 [Gating] SW mode calibration
6515 12:42:36.764501 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6516 12:42:36.771137 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6517 12:42:36.774276 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6518 12:42:36.778121 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6519 12:42:36.781454 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6520 12:42:36.787964 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6521 12:42:36.791488 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6522 12:42:36.794523 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6523 12:42:36.801656 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6524 12:42:36.804813 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6525 12:42:36.807864 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6526 12:42:36.811367 Total UI for P1: 0, mck2ui 16
6527 12:42:36.814360 best dqsien dly found for B0: ( 0, 14, 24)
6528 12:42:36.817731 Total UI for P1: 0, mck2ui 16
6529 12:42:36.821973 best dqsien dly found for B1: ( 0, 14, 24)
6530 12:42:36.824556 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6531 12:42:36.827683 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6532 12:42:36.827763
6533 12:42:36.834642 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6534 12:42:36.838059 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6535 12:42:36.841006 [Gating] SW calibration Done
6536 12:42:36.841087 ==
6537 12:42:36.844242 Dram Type= 6, Freq= 0, CH_0, rank 1
6538 12:42:36.847938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6539 12:42:36.848023 ==
6540 12:42:36.848085 RX Vref Scan: 0
6541 12:42:36.848151
6542 12:42:36.851209 RX Vref 0 -> 0, step: 1
6543 12:42:36.851289
6544 12:42:36.854993 RX Delay -410 -> 252, step: 16
6545 12:42:36.857585 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6546 12:42:36.864436 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6547 12:42:36.867484 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6548 12:42:36.871366 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6549 12:42:36.874331 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6550 12:42:36.877710 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6551 12:42:36.884694 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6552 12:42:36.888022 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6553 12:42:36.891046 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6554 12:42:36.894599 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6555 12:42:36.901168 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6556 12:42:36.904764 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6557 12:42:36.907709 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6558 12:42:36.911518 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6559 12:42:36.918124 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6560 12:42:36.921563 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6561 12:42:36.921641 ==
6562 12:42:36.924535 Dram Type= 6, Freq= 0, CH_0, rank 1
6563 12:42:36.927794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6564 12:42:36.927870 ==
6565 12:42:36.931226 DQS Delay:
6566 12:42:36.931304 DQS0 = 43, DQS1 = 51
6567 12:42:36.934599 DQM Delay:
6568 12:42:36.934674 DQM0 = 11, DQM1 = 10
6569 12:42:36.934759 DQ Delay:
6570 12:42:36.937629 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6571 12:42:36.941055 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6572 12:42:36.944445 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6573 12:42:36.947934 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6574 12:42:36.948008
6575 12:42:36.948075
6576 12:42:36.948135 ==
6577 12:42:36.951029 Dram Type= 6, Freq= 0, CH_0, rank 1
6578 12:42:36.958103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6579 12:42:36.958177 ==
6580 12:42:36.958237
6581 12:42:36.958361
6582 12:42:36.958441 TX Vref Scan disable
6583 12:42:36.961092 == TX Byte 0 ==
6584 12:42:36.965265 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6585 12:42:36.968112 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6586 12:42:36.970945 == TX Byte 1 ==
6587 12:42:36.974604 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6588 12:42:36.977780 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6589 12:42:36.977861 ==
6590 12:42:36.981533 Dram Type= 6, Freq= 0, CH_0, rank 1
6591 12:42:36.988071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6592 12:42:36.988150 ==
6593 12:42:36.988211
6594 12:42:36.988275
6595 12:42:36.988335 TX Vref Scan disable
6596 12:42:36.991479 == TX Byte 0 ==
6597 12:42:36.994532 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6598 12:42:36.998388 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6599 12:42:37.001095 == TX Byte 1 ==
6600 12:42:37.004200 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6601 12:42:37.007984 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6602 12:42:37.008057
6603 12:42:37.011197 [DATLAT]
6604 12:42:37.011271 Freq=400, CH0 RK1
6605 12:42:37.011334
6606 12:42:37.014215 DATLAT Default: 0xe
6607 12:42:37.014295 0, 0xFFFF, sum = 0
6608 12:42:37.018211 1, 0xFFFF, sum = 0
6609 12:42:37.018287 2, 0xFFFF, sum = 0
6610 12:42:37.020963 3, 0xFFFF, sum = 0
6611 12:42:37.021037 4, 0xFFFF, sum = 0
6612 12:42:37.024484 5, 0xFFFF, sum = 0
6613 12:42:37.024554 6, 0xFFFF, sum = 0
6614 12:42:37.028097 7, 0xFFFF, sum = 0
6615 12:42:37.028171 8, 0xFFFF, sum = 0
6616 12:42:37.031135 9, 0xFFFF, sum = 0
6617 12:42:37.031215 10, 0xFFFF, sum = 0
6618 12:42:37.034660 11, 0xFFFF, sum = 0
6619 12:42:37.034738 12, 0xFFFF, sum = 0
6620 12:42:37.037807 13, 0x0, sum = 1
6621 12:42:37.037885 14, 0x0, sum = 2
6622 12:42:37.041587 15, 0x0, sum = 3
6623 12:42:37.041662 16, 0x0, sum = 4
6624 12:42:37.044291 best_step = 14
6625 12:42:37.044363
6626 12:42:37.044458 ==
6627 12:42:37.047921 Dram Type= 6, Freq= 0, CH_0, rank 1
6628 12:42:37.052114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6629 12:42:37.052192 ==
6630 12:42:37.054870 RX Vref Scan: 0
6631 12:42:37.054955
6632 12:42:37.055018 RX Vref 0 -> 0, step: 1
6633 12:42:37.055078
6634 12:42:37.057846 RX Delay -343 -> 252, step: 8
6635 12:42:37.066012 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6636 12:42:37.069097 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6637 12:42:37.072049 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6638 12:42:37.075403 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6639 12:42:37.081976 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6640 12:42:37.085270 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6641 12:42:37.089023 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6642 12:42:37.092611 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6643 12:42:37.098754 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6644 12:42:37.102226 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6645 12:42:37.105458 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6646 12:42:37.109156 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6647 12:42:37.115938 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6648 12:42:37.118908 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6649 12:42:37.122660 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6650 12:42:37.125929 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6651 12:42:37.128719 ==
6652 12:42:37.132354 Dram Type= 6, Freq= 0, CH_0, rank 1
6653 12:42:37.135663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6654 12:42:37.135739 ==
6655 12:42:37.135824 DQS Delay:
6656 12:42:37.139309 DQS0 = 48, DQS1 = 60
6657 12:42:37.139389 DQM Delay:
6658 12:42:37.142302 DQM0 = 13, DQM1 = 13
6659 12:42:37.142409 DQ Delay:
6660 12:42:37.145442 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6661 12:42:37.149303 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6662 12:42:37.152257 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6663 12:42:37.156055 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6664 12:42:37.156126
6665 12:42:37.156204
6666 12:42:37.162097 [DQSOSCAuto] RK1, (LSB)MR18= 0x8e61, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 392 ps
6667 12:42:37.165498 CH0 RK1: MR19=C0C, MR18=8E61
6668 12:42:37.172804 CH0_RK1: MR19=0xC0C, MR18=0x8E61, DQSOSC=392, MR23=63, INC=384, DEC=256
6669 12:42:37.175441 [RxdqsGatingPostProcess] freq 400
6670 12:42:37.179106 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6671 12:42:37.182287 best DQS0 dly(2T, 0.5T) = (0, 10)
6672 12:42:37.185695 best DQS1 dly(2T, 0.5T) = (0, 10)
6673 12:42:37.188815 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6674 12:42:37.192467 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6675 12:42:37.195545 best DQS0 dly(2T, 0.5T) = (0, 10)
6676 12:42:37.199030 best DQS1 dly(2T, 0.5T) = (0, 10)
6677 12:42:37.202427 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6678 12:42:37.205834 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6679 12:42:37.208982 Pre-setting of DQS Precalculation
6680 12:42:37.212127 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6681 12:42:37.212217 ==
6682 12:42:37.215541 Dram Type= 6, Freq= 0, CH_1, rank 0
6683 12:42:37.222498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6684 12:42:37.222595 ==
6685 12:42:37.225325 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6686 12:42:37.231963 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6687 12:42:37.235645 [CA 0] Center 36 (8~64) winsize 57
6688 12:42:37.238974 [CA 1] Center 36 (8~64) winsize 57
6689 12:42:37.242358 [CA 2] Center 36 (8~64) winsize 57
6690 12:42:37.245872 [CA 3] Center 36 (8~64) winsize 57
6691 12:42:37.248779 [CA 4] Center 36 (8~64) winsize 57
6692 12:42:37.252494 [CA 5] Center 36 (8~64) winsize 57
6693 12:42:37.252596
6694 12:42:37.255562 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6695 12:42:37.255659
6696 12:42:37.259566 [CATrainingPosCal] consider 1 rank data
6697 12:42:37.262090 u2DelayCellTimex100 = 270/100 ps
6698 12:42:37.265500 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 12:42:37.269498 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 12:42:37.272329 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 12:42:37.275884 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 12:42:37.279071 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 12:42:37.282279 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 12:42:37.282377
6705 12:42:37.288750 CA PerBit enable=1, Macro0, CA PI delay=36
6706 12:42:37.288833
6707 12:42:37.292257 [CBTSetCACLKResult] CA Dly = 36
6708 12:42:37.292332 CS Dly: 1 (0~32)
6709 12:42:37.292421 ==
6710 12:42:37.295722 Dram Type= 6, Freq= 0, CH_1, rank 1
6711 12:42:37.299183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6712 12:42:37.299261 ==
6713 12:42:37.305428 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6714 12:42:37.312244 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6715 12:42:37.315903 [CA 0] Center 36 (8~64) winsize 57
6716 12:42:37.318834 [CA 1] Center 36 (8~64) winsize 57
6717 12:42:37.322553 [CA 2] Center 36 (8~64) winsize 57
6718 12:42:37.325766 [CA 3] Center 36 (8~64) winsize 57
6719 12:42:37.325847 [CA 4] Center 36 (8~64) winsize 57
6720 12:42:37.329013 [CA 5] Center 36 (8~64) winsize 57
6721 12:42:37.329093
6722 12:42:37.335968 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6723 12:42:37.336097
6724 12:42:37.339167 [CATrainingPosCal] consider 2 rank data
6725 12:42:37.342517 u2DelayCellTimex100 = 270/100 ps
6726 12:42:37.345511 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6727 12:42:37.348982 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6728 12:42:37.352487 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6729 12:42:37.355815 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6730 12:42:37.359079 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6731 12:42:37.362297 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6732 12:42:37.362368
6733 12:42:37.365505 CA PerBit enable=1, Macro0, CA PI delay=36
6734 12:42:37.365586
6735 12:42:37.368897 [CBTSetCACLKResult] CA Dly = 36
6736 12:42:37.372514 CS Dly: 1 (0~32)
6737 12:42:37.372600
6738 12:42:37.375694 ----->DramcWriteLeveling(PI) begin...
6739 12:42:37.375772 ==
6740 12:42:37.378900 Dram Type= 6, Freq= 0, CH_1, rank 0
6741 12:42:37.382301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6742 12:42:37.382378 ==
6743 12:42:37.385234 Write leveling (Byte 0): 40 => 8
6744 12:42:37.388940 Write leveling (Byte 1): 40 => 8
6745 12:42:37.392200 DramcWriteLeveling(PI) end<-----
6746 12:42:37.392283
6747 12:42:37.392362 ==
6748 12:42:37.396113 Dram Type= 6, Freq= 0, CH_1, rank 0
6749 12:42:37.398945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6750 12:42:37.399049 ==
6751 12:42:37.402067 [Gating] SW mode calibration
6752 12:42:37.409211 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6753 12:42:37.415324 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6754 12:42:37.418849 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6755 12:42:37.422097 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6756 12:42:37.429348 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6757 12:42:37.432195 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6758 12:42:37.435635 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6759 12:42:37.442304 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6760 12:42:37.445152 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6761 12:42:37.448773 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6762 12:42:37.455733 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6763 12:42:37.455815 Total UI for P1: 0, mck2ui 16
6764 12:42:37.461889 best dqsien dly found for B0: ( 0, 14, 24)
6765 12:42:37.461970 Total UI for P1: 0, mck2ui 16
6766 12:42:37.465344 best dqsien dly found for B1: ( 0, 14, 24)
6767 12:42:37.471881 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6768 12:42:37.475673 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6769 12:42:37.475754
6770 12:42:37.478404 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6771 12:42:37.482047 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6772 12:42:37.485157 [Gating] SW calibration Done
6773 12:42:37.485238 ==
6774 12:42:37.488700 Dram Type= 6, Freq= 0, CH_1, rank 0
6775 12:42:37.492054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6776 12:42:37.492136 ==
6777 12:42:37.495228 RX Vref Scan: 0
6778 12:42:37.495309
6779 12:42:37.495372 RX Vref 0 -> 0, step: 1
6780 12:42:37.495473
6781 12:42:37.498513 RX Delay -410 -> 252, step: 16
6782 12:42:37.504984 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6783 12:42:37.508219 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6784 12:42:37.511514 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6785 12:42:37.514946 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6786 12:42:37.521794 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6787 12:42:37.525534 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6788 12:42:37.529076 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6789 12:42:37.531567 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6790 12:42:37.538182 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6791 12:42:37.541828 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6792 12:42:37.545357 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6793 12:42:37.548701 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6794 12:42:37.554924 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6795 12:42:37.558385 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6796 12:42:37.561898 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6797 12:42:37.565746 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6798 12:42:37.565828 ==
6799 12:42:37.568219 Dram Type= 6, Freq= 0, CH_1, rank 0
6800 12:42:37.575063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6801 12:42:37.575153 ==
6802 12:42:37.575237 DQS Delay:
6803 12:42:37.579092 DQS0 = 51, DQS1 = 59
6804 12:42:37.579168 DQM Delay:
6805 12:42:37.579256 DQM0 = 19, DQM1 = 17
6806 12:42:37.581955 DQ Delay:
6807 12:42:37.585239 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6808 12:42:37.588613 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6809 12:42:37.592046 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6810 12:42:37.595331 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =24
6811 12:42:37.595421
6812 12:42:37.595507
6813 12:42:37.595584 ==
6814 12:42:37.598191 Dram Type= 6, Freq= 0, CH_1, rank 0
6815 12:42:37.602131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6816 12:42:37.602210 ==
6817 12:42:37.602315
6818 12:42:37.602438
6819 12:42:37.605424 TX Vref Scan disable
6820 12:42:37.605505 == TX Byte 0 ==
6821 12:42:37.608701 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6822 12:42:37.615655 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6823 12:42:37.615732 == TX Byte 1 ==
6824 12:42:37.618616 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6825 12:42:37.625047 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6826 12:42:37.625128 ==
6827 12:42:37.628478 Dram Type= 6, Freq= 0, CH_1, rank 0
6828 12:42:37.631768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6829 12:42:37.631848 ==
6830 12:42:37.631929
6831 12:42:37.632004
6832 12:42:37.635333 TX Vref Scan disable
6833 12:42:37.635408 == TX Byte 0 ==
6834 12:42:37.638316 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6835 12:42:37.645398 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6836 12:42:37.645479 == TX Byte 1 ==
6837 12:42:37.649061 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6838 12:42:37.655210 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6839 12:42:37.655293
6840 12:42:37.655357 [DATLAT]
6841 12:42:37.655416 Freq=400, CH1 RK0
6842 12:42:37.658662
6843 12:42:37.658743 DATLAT Default: 0xf
6844 12:42:37.661916 0, 0xFFFF, sum = 0
6845 12:42:37.661999 1, 0xFFFF, sum = 0
6846 12:42:37.665340 2, 0xFFFF, sum = 0
6847 12:42:37.665422 3, 0xFFFF, sum = 0
6848 12:42:37.668770 4, 0xFFFF, sum = 0
6849 12:42:37.668852 5, 0xFFFF, sum = 0
6850 12:42:37.672272 6, 0xFFFF, sum = 0
6851 12:42:37.672354 7, 0xFFFF, sum = 0
6852 12:42:37.675411 8, 0xFFFF, sum = 0
6853 12:42:37.675493 9, 0xFFFF, sum = 0
6854 12:42:37.678536 10, 0xFFFF, sum = 0
6855 12:42:37.678618 11, 0xFFFF, sum = 0
6856 12:42:37.681721 12, 0xFFFF, sum = 0
6857 12:42:37.681802 13, 0x0, sum = 1
6858 12:42:37.685442 14, 0x0, sum = 2
6859 12:42:37.685524 15, 0x0, sum = 3
6860 12:42:37.688558 16, 0x0, sum = 4
6861 12:42:37.688641 best_step = 14
6862 12:42:37.688705
6863 12:42:37.688763 ==
6864 12:42:37.692311 Dram Type= 6, Freq= 0, CH_1, rank 0
6865 12:42:37.695486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 12:42:37.698548 ==
6867 12:42:37.698629 RX Vref Scan: 1
6868 12:42:37.698693
6869 12:42:37.702237 RX Vref 0 -> 0, step: 1
6870 12:42:37.702318
6871 12:42:37.705136 RX Delay -359 -> 252, step: 8
6872 12:42:37.705217
6873 12:42:37.708714 Set Vref, RX VrefLevel [Byte0]: 57
6874 12:42:37.711940 [Byte1]: 49
6875 12:42:37.712021
6876 12:42:37.715831 Final RX Vref Byte 0 = 57 to rank0
6877 12:42:37.719357 Final RX Vref Byte 1 = 49 to rank0
6878 12:42:37.722083 Final RX Vref Byte 0 = 57 to rank1
6879 12:42:37.725724 Final RX Vref Byte 1 = 49 to rank1==
6880 12:42:37.728482 Dram Type= 6, Freq= 0, CH_1, rank 0
6881 12:42:37.732077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 12:42:37.732159 ==
6883 12:42:37.735059 DQS Delay:
6884 12:42:37.735140 DQS0 = 48, DQS1 = 60
6885 12:42:37.739221 DQM Delay:
6886 12:42:37.739301 DQM0 = 12, DQM1 = 12
6887 12:42:37.739365 DQ Delay:
6888 12:42:37.741843 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6889 12:42:37.745358 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
6890 12:42:37.749314 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6891 12:42:37.751877 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6892 12:42:37.751958
6893 12:42:37.752021
6894 12:42:37.762315 [DQSOSCAuto] RK0, (LSB)MR18= 0x8c34, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6895 12:42:37.762431 CH1 RK0: MR19=C0C, MR18=8C34
6896 12:42:37.768616 CH1_RK0: MR19=0xC0C, MR18=0x8C34, DQSOSC=392, MR23=63, INC=384, DEC=256
6897 12:42:37.768705 ==
6898 12:42:37.772286 Dram Type= 6, Freq= 0, CH_1, rank 1
6899 12:42:37.778637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6900 12:42:37.778725 ==
6901 12:42:37.782309 [Gating] SW mode calibration
6902 12:42:37.788885 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6903 12:42:37.792045 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6904 12:42:37.798334 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6905 12:42:37.802237 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6906 12:42:37.805389 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6907 12:42:37.808564 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6908 12:42:37.815139 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6909 12:42:37.818927 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6910 12:42:37.821993 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6911 12:42:37.828937 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6912 12:42:37.831721 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6913 12:42:37.835244 Total UI for P1: 0, mck2ui 16
6914 12:42:37.838579 best dqsien dly found for B0: ( 0, 14, 24)
6915 12:42:37.842081 Total UI for P1: 0, mck2ui 16
6916 12:42:37.845148 best dqsien dly found for B1: ( 0, 14, 24)
6917 12:42:37.848623 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6918 12:42:37.851903 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6919 12:42:37.851986
6920 12:42:37.855523 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6921 12:42:37.858380 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6922 12:42:37.861893 [Gating] SW calibration Done
6923 12:42:37.861972 ==
6924 12:42:37.865474 Dram Type= 6, Freq= 0, CH_1, rank 1
6925 12:42:37.873033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6926 12:42:37.873116 ==
6927 12:42:37.873178 RX Vref Scan: 0
6928 12:42:37.873237
6929 12:42:37.875419 RX Vref 0 -> 0, step: 1
6930 12:42:37.875491
6931 12:42:37.878708 RX Delay -410 -> 252, step: 16
6932 12:42:37.882166 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6933 12:42:37.885430 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6934 12:42:37.888673 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6935 12:42:37.895662 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6936 12:42:37.898481 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6937 12:42:37.902037 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6938 12:42:37.905121 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6939 12:42:37.912167 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6940 12:42:37.915312 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6941 12:42:37.918731 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6942 12:42:37.921953 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6943 12:42:37.928374 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6944 12:42:37.932272 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6945 12:42:37.935367 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6946 12:42:37.938426 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6947 12:42:37.945713 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6948 12:42:37.945796 ==
6949 12:42:37.948835 Dram Type= 6, Freq= 0, CH_1, rank 1
6950 12:42:37.952032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6951 12:42:37.952112 ==
6952 12:42:37.952175 DQS Delay:
6953 12:42:37.955090 DQS0 = 43, DQS1 = 59
6954 12:42:37.955162 DQM Delay:
6955 12:42:37.958696 DQM0 = 10, DQM1 = 17
6956 12:42:37.958769 DQ Delay:
6957 12:42:37.962141 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6958 12:42:37.965650 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6959 12:42:37.968974 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6960 12:42:37.972594 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6961 12:42:37.972696
6962 12:42:37.972783
6963 12:42:37.972871 ==
6964 12:42:37.975647 Dram Type= 6, Freq= 0, CH_1, rank 1
6965 12:42:37.978717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6966 12:42:37.978794 ==
6967 12:42:37.978859
6968 12:42:37.978917
6969 12:42:37.982694 TX Vref Scan disable
6970 12:42:37.982771 == TX Byte 0 ==
6971 12:42:37.988624 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6972 12:42:37.992259 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6973 12:42:37.992358 == TX Byte 1 ==
6974 12:42:37.998884 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6975 12:42:38.002347 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6976 12:42:38.002432 ==
6977 12:42:38.005588 Dram Type= 6, Freq= 0, CH_1, rank 1
6978 12:42:38.009147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6979 12:42:38.009222 ==
6980 12:42:38.009283
6981 12:42:38.009345
6982 12:42:38.012143 TX Vref Scan disable
6983 12:42:38.012215 == TX Byte 0 ==
6984 12:42:38.018943 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6985 12:42:38.022206 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6986 12:42:38.022279 == TX Byte 1 ==
6987 12:42:38.028668 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6988 12:42:38.032102 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6989 12:42:38.032207
6990 12:42:38.032300 [DATLAT]
6991 12:42:38.035258 Freq=400, CH1 RK1
6992 12:42:38.035330
6993 12:42:38.035392 DATLAT Default: 0xe
6994 12:42:38.038554 0, 0xFFFF, sum = 0
6995 12:42:38.038644 1, 0xFFFF, sum = 0
6996 12:42:38.042283 2, 0xFFFF, sum = 0
6997 12:42:38.042354 3, 0xFFFF, sum = 0
6998 12:42:38.045432 4, 0xFFFF, sum = 0
6999 12:42:38.045533 5, 0xFFFF, sum = 0
7000 12:42:38.048805 6, 0xFFFF, sum = 0
7001 12:42:38.048894 7, 0xFFFF, sum = 0
7002 12:42:38.052159 8, 0xFFFF, sum = 0
7003 12:42:38.052250 9, 0xFFFF, sum = 0
7004 12:42:38.055704 10, 0xFFFF, sum = 0
7005 12:42:38.058924 11, 0xFFFF, sum = 0
7006 12:42:38.059005 12, 0xFFFF, sum = 0
7007 12:42:38.062249 13, 0x0, sum = 1
7008 12:42:38.062324 14, 0x0, sum = 2
7009 12:42:38.062385 15, 0x0, sum = 3
7010 12:42:38.066095 16, 0x0, sum = 4
7011 12:42:38.066168 best_step = 14
7012 12:42:38.066230
7013 12:42:38.066287 ==
7014 12:42:38.068720 Dram Type= 6, Freq= 0, CH_1, rank 1
7015 12:42:38.075406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7016 12:42:38.075478 ==
7017 12:42:38.075542 RX Vref Scan: 0
7018 12:42:38.075599
7019 12:42:38.078977 RX Vref 0 -> 0, step: 1
7020 12:42:38.079047
7021 12:42:38.082409 RX Delay -359 -> 252, step: 8
7022 12:42:38.089479 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
7023 12:42:38.092140 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
7024 12:42:38.096315 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
7025 12:42:38.099068 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
7026 12:42:38.105474 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
7027 12:42:38.108613 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
7028 12:42:38.112242 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
7029 12:42:38.115205 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
7030 12:42:38.122520 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
7031 12:42:38.125466 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
7032 12:42:38.128659 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
7033 12:42:38.132685 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
7034 12:42:38.138491 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
7035 12:42:38.142391 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7036 12:42:38.145183 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7037 12:42:38.151893 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
7038 12:42:38.151971 ==
7039 12:42:38.155396 Dram Type= 6, Freq= 0, CH_1, rank 1
7040 12:42:38.159122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7041 12:42:38.159198 ==
7042 12:42:38.159259 DQS Delay:
7043 12:42:38.162100 DQS0 = 48, DQS1 = 60
7044 12:42:38.162169 DQM Delay:
7045 12:42:38.165614 DQM0 = 9, DQM1 = 13
7046 12:42:38.165693 DQ Delay:
7047 12:42:38.168599 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
7048 12:42:38.171953 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
7049 12:42:38.175569 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
7050 12:42:38.178853 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
7051 12:42:38.178931
7052 12:42:38.179012
7053 12:42:38.185677 [DQSOSCAuto] RK1, (LSB)MR18= 0x748a, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 395 ps
7054 12:42:38.188798 CH1 RK1: MR19=C0C, MR18=748A
7055 12:42:38.195499 CH1_RK1: MR19=0xC0C, MR18=0x748A, DQSOSC=392, MR23=63, INC=384, DEC=256
7056 12:42:38.199462 [RxdqsGatingPostProcess] freq 400
7057 12:42:38.202604 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7058 12:42:38.205439 best DQS0 dly(2T, 0.5T) = (0, 10)
7059 12:42:38.208955 best DQS1 dly(2T, 0.5T) = (0, 10)
7060 12:42:38.212305 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7061 12:42:38.215901 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7062 12:42:38.219347 best DQS0 dly(2T, 0.5T) = (0, 10)
7063 12:42:38.222454 best DQS1 dly(2T, 0.5T) = (0, 10)
7064 12:42:38.225518 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7065 12:42:38.229196 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7066 12:42:38.232476 Pre-setting of DQS Precalculation
7067 12:42:38.235990 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7068 12:42:38.241841 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7069 12:42:38.252039 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7070 12:42:38.252114
7071 12:42:38.252175
7072 12:42:38.255338 [Calibration Summary] 800 Mbps
7073 12:42:38.255410 CH 0, Rank 0
7074 12:42:38.258524 SW Impedance : PASS
7075 12:42:38.258590 DUTY Scan : NO K
7076 12:42:38.262194 ZQ Calibration : PASS
7077 12:42:38.265357 Jitter Meter : NO K
7078 12:42:38.265435 CBT Training : PASS
7079 12:42:38.268861 Write leveling : PASS
7080 12:42:38.268934 RX DQS gating : PASS
7081 12:42:38.272085 RX DQ/DQS(RDDQC) : PASS
7082 12:42:38.275290 TX DQ/DQS : PASS
7083 12:42:38.275364 RX DATLAT : PASS
7084 12:42:38.278913 RX DQ/DQS(Engine): PASS
7085 12:42:38.282260 TX OE : NO K
7086 12:42:38.282333 All Pass.
7087 12:42:38.282426
7088 12:42:38.282500 CH 0, Rank 1
7089 12:42:38.285369 SW Impedance : PASS
7090 12:42:38.289008 DUTY Scan : NO K
7091 12:42:38.289076 ZQ Calibration : PASS
7092 12:42:38.292558 Jitter Meter : NO K
7093 12:42:38.295735 CBT Training : PASS
7094 12:42:38.295807 Write leveling : NO K
7095 12:42:38.298782 RX DQS gating : PASS
7096 12:42:38.302384 RX DQ/DQS(RDDQC) : PASS
7097 12:42:38.302492 TX DQ/DQS : PASS
7098 12:42:38.305386 RX DATLAT : PASS
7099 12:42:38.305451 RX DQ/DQS(Engine): PASS
7100 12:42:38.308673 TX OE : NO K
7101 12:42:38.308738 All Pass.
7102 12:42:38.308795
7103 12:42:38.311897 CH 1, Rank 0
7104 12:42:38.311977 SW Impedance : PASS
7105 12:42:38.315681 DUTY Scan : NO K
7106 12:42:38.319035 ZQ Calibration : PASS
7107 12:42:38.319105 Jitter Meter : NO K
7108 12:42:38.322132 CBT Training : PASS
7109 12:42:38.325646 Write leveling : PASS
7110 12:42:38.325722 RX DQS gating : PASS
7111 12:42:38.328938 RX DQ/DQS(RDDQC) : PASS
7112 12:42:38.331943 TX DQ/DQS : PASS
7113 12:42:38.332017 RX DATLAT : PASS
7114 12:42:38.335282 RX DQ/DQS(Engine): PASS
7115 12:42:38.339164 TX OE : NO K
7116 12:42:38.339235 All Pass.
7117 12:42:38.339295
7118 12:42:38.339356 CH 1, Rank 1
7119 12:42:38.342796 SW Impedance : PASS
7120 12:42:38.345389 DUTY Scan : NO K
7121 12:42:38.345457 ZQ Calibration : PASS
7122 12:42:38.349824 Jitter Meter : NO K
7123 12:42:38.352380 CBT Training : PASS
7124 12:42:38.352454 Write leveling : NO K
7125 12:42:38.355367 RX DQS gating : PASS
7126 12:42:38.355438 RX DQ/DQS(RDDQC) : PASS
7127 12:42:38.359260 TX DQ/DQS : PASS
7128 12:42:38.362214 RX DATLAT : PASS
7129 12:42:38.362283 RX DQ/DQS(Engine): PASS
7130 12:42:38.365538 TX OE : NO K
7131 12:42:38.365609 All Pass.
7132 12:42:38.365668
7133 12:42:38.368620 DramC Write-DBI off
7134 12:42:38.372072 PER_BANK_REFRESH: Hybrid Mode
7135 12:42:38.372144 TX_TRACKING: ON
7136 12:42:38.382801 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7137 12:42:38.385681 [FAST_K] Save calibration result to emmc
7138 12:42:38.388799 dramc_set_vcore_voltage set vcore to 725000
7139 12:42:38.392001 Read voltage for 1600, 0
7140 12:42:38.392076 Vio18 = 0
7141 12:42:38.392137 Vcore = 725000
7142 12:42:38.395786 Vdram = 0
7143 12:42:38.395857 Vddq = 0
7144 12:42:38.395917 Vmddr = 0
7145 12:42:38.402163 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7146 12:42:38.405605 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7147 12:42:38.408915 MEM_TYPE=3, freq_sel=13
7148 12:42:38.412755 sv_algorithm_assistance_LP4_3733
7149 12:42:38.415734 ============ PULL DRAM RESETB DOWN ============
7150 12:42:38.418883 ========== PULL DRAM RESETB DOWN end =========
7151 12:42:38.426507 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7152 12:42:38.429216 ===================================
7153 12:42:38.429289 LPDDR4 DRAM CONFIGURATION
7154 12:42:38.432393 ===================================
7155 12:42:38.435953 EX_ROW_EN[0] = 0x0
7156 12:42:38.439166 EX_ROW_EN[1] = 0x0
7157 12:42:38.439238 LP4Y_EN = 0x0
7158 12:42:38.442333 WORK_FSP = 0x1
7159 12:42:38.442469 WL = 0x5
7160 12:42:38.446143 RL = 0x5
7161 12:42:38.446218 BL = 0x2
7162 12:42:38.448949 RPST = 0x0
7163 12:42:38.449019 RD_PRE = 0x0
7164 12:42:38.452363 WR_PRE = 0x1
7165 12:42:38.452436 WR_PST = 0x1
7166 12:42:38.455941 DBI_WR = 0x0
7167 12:42:38.456017 DBI_RD = 0x0
7168 12:42:38.459050 OTF = 0x1
7169 12:42:38.462565 ===================================
7170 12:42:38.465776 ===================================
7171 12:42:38.465851 ANA top config
7172 12:42:38.469330 ===================================
7173 12:42:38.472983 DLL_ASYNC_EN = 0
7174 12:42:38.475800 ALL_SLAVE_EN = 0
7175 12:42:38.479262 NEW_RANK_MODE = 1
7176 12:42:38.479339 DLL_IDLE_MODE = 1
7177 12:42:38.482267 LP45_APHY_COMB_EN = 1
7178 12:42:38.485799 TX_ODT_DIS = 0
7179 12:42:38.489535 NEW_8X_MODE = 1
7180 12:42:38.492194 ===================================
7181 12:42:38.495788 ===================================
7182 12:42:38.499324 data_rate = 3200
7183 12:42:38.499405 CKR = 1
7184 12:42:38.502601 DQ_P2S_RATIO = 8
7185 12:42:38.505475 ===================================
7186 12:42:38.509102 CA_P2S_RATIO = 8
7187 12:42:38.512663 DQ_CA_OPEN = 0
7188 12:42:38.515502 DQ_SEMI_OPEN = 0
7189 12:42:38.515571 CA_SEMI_OPEN = 0
7190 12:42:38.519263 CA_FULL_RATE = 0
7191 12:42:38.522312 DQ_CKDIV4_EN = 0
7192 12:42:38.525818 CA_CKDIV4_EN = 0
7193 12:42:38.529394 CA_PREDIV_EN = 0
7194 12:42:38.532572 PH8_DLY = 12
7195 12:42:38.532646 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7196 12:42:38.535481 DQ_AAMCK_DIV = 4
7197 12:42:38.539156 CA_AAMCK_DIV = 4
7198 12:42:38.542195 CA_ADMCK_DIV = 4
7199 12:42:38.545501 DQ_TRACK_CA_EN = 0
7200 12:42:38.548776 CA_PICK = 1600
7201 12:42:38.552523 CA_MCKIO = 1600
7202 12:42:38.552600 MCKIO_SEMI = 0
7203 12:42:38.556008 PLL_FREQ = 3068
7204 12:42:38.559616 DQ_UI_PI_RATIO = 32
7205 12:42:38.562333 CA_UI_PI_RATIO = 0
7206 12:42:38.565884 ===================================
7207 12:42:38.569192 ===================================
7208 12:42:38.572288 memory_type:LPDDR4
7209 12:42:38.572368 GP_NUM : 10
7210 12:42:38.576217 SRAM_EN : 1
7211 12:42:38.576296 MD32_EN : 0
7212 12:42:38.578993 ===================================
7213 12:42:38.582689 [ANA_INIT] >>>>>>>>>>>>>>
7214 12:42:38.585660 <<<<<< [CONFIGURE PHASE]: ANA_TX
7215 12:42:38.589130 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7216 12:42:38.592293 ===================================
7217 12:42:38.595919 data_rate = 3200,PCW = 0X7600
7218 12:42:38.598977 ===================================
7219 12:42:38.602808 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7220 12:42:38.609002 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7221 12:42:38.612739 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7222 12:42:38.619156 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7223 12:42:38.622628 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7224 12:42:38.625904 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7225 12:42:38.626009 [ANA_INIT] flow start
7226 12:42:38.629137 [ANA_INIT] PLL >>>>>>>>
7227 12:42:38.632282 [ANA_INIT] PLL <<<<<<<<
7228 12:42:38.632393 [ANA_INIT] MIDPI >>>>>>>>
7229 12:42:38.635975 [ANA_INIT] MIDPI <<<<<<<<
7230 12:42:38.639135 [ANA_INIT] DLL >>>>>>>>
7231 12:42:38.639214 [ANA_INIT] DLL <<<<<<<<
7232 12:42:38.642269 [ANA_INIT] flow end
7233 12:42:38.645994 ============ LP4 DIFF to SE enter ============
7234 12:42:38.649103 ============ LP4 DIFF to SE exit ============
7235 12:42:38.652481 [ANA_INIT] <<<<<<<<<<<<<
7236 12:42:38.655771 [Flow] Enable top DCM control >>>>>
7237 12:42:38.658926 [Flow] Enable top DCM control <<<<<
7238 12:42:38.662355 Enable DLL master slave shuffle
7239 12:42:38.668975 ==============================================================
7240 12:42:38.669096 Gating Mode config
7241 12:42:38.675930 ==============================================================
7242 12:42:38.676010 Config description:
7243 12:42:38.685681 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7244 12:42:38.692661 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7245 12:42:38.699410 SELPH_MODE 0: By rank 1: By Phase
7246 12:42:38.702707 ==============================================================
7247 12:42:38.705972 GAT_TRACK_EN = 1
7248 12:42:38.709412 RX_GATING_MODE = 2
7249 12:42:38.712939 RX_GATING_TRACK_MODE = 2
7250 12:42:38.716249 SELPH_MODE = 1
7251 12:42:38.719041 PICG_EARLY_EN = 1
7252 12:42:38.722359 VALID_LAT_VALUE = 1
7253 12:42:38.726033 ==============================================================
7254 12:42:38.729249 Enter into Gating configuration >>>>
7255 12:42:38.732773 Exit from Gating configuration <<<<
7256 12:42:38.736111 Enter into DVFS_PRE_config >>>>>
7257 12:42:38.749146 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7258 12:42:38.752979 Exit from DVFS_PRE_config <<<<<
7259 12:42:38.756256 Enter into PICG configuration >>>>
7260 12:42:38.759211 Exit from PICG configuration <<<<
7261 12:42:38.759290 [RX_INPUT] configuration >>>>>
7262 12:42:38.762788 [RX_INPUT] configuration <<<<<
7263 12:42:38.769022 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7264 12:42:38.772567 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7265 12:42:38.779155 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7266 12:42:38.785508 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7267 12:42:38.792148 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7268 12:42:38.799557 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7269 12:42:38.802846 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7270 12:42:38.806091 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7271 12:42:38.808903 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7272 12:42:38.815706 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7273 12:42:38.819072 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7274 12:42:38.822611 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7275 12:42:38.825956 ===================================
7276 12:42:38.829097 LPDDR4 DRAM CONFIGURATION
7277 12:42:38.832443 ===================================
7278 12:42:38.835684 EX_ROW_EN[0] = 0x0
7279 12:42:38.835757 EX_ROW_EN[1] = 0x0
7280 12:42:38.839359 LP4Y_EN = 0x0
7281 12:42:38.839433 WORK_FSP = 0x1
7282 12:42:38.842293 WL = 0x5
7283 12:42:38.842364 RL = 0x5
7284 12:42:38.845803 BL = 0x2
7285 12:42:38.845879 RPST = 0x0
7286 12:42:38.849219 RD_PRE = 0x0
7287 12:42:38.849293 WR_PRE = 0x1
7288 12:42:38.852579 WR_PST = 0x1
7289 12:42:38.852681 DBI_WR = 0x0
7290 12:42:38.855770 DBI_RD = 0x0
7291 12:42:38.855882 OTF = 0x1
7292 12:42:38.859707 ===================================
7293 12:42:38.862377 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7294 12:42:38.868806 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7295 12:42:38.872995 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7296 12:42:38.876134 ===================================
7297 12:42:38.879177 LPDDR4 DRAM CONFIGURATION
7298 12:42:38.882474 ===================================
7299 12:42:38.882549 EX_ROW_EN[0] = 0x10
7300 12:42:38.885796 EX_ROW_EN[1] = 0x0
7301 12:42:38.889033 LP4Y_EN = 0x0
7302 12:42:38.889116 WORK_FSP = 0x1
7303 12:42:38.892802 WL = 0x5
7304 12:42:38.892914 RL = 0x5
7305 12:42:38.895918 BL = 0x2
7306 12:42:38.896011 RPST = 0x0
7307 12:42:38.899062 RD_PRE = 0x0
7308 12:42:38.899198 WR_PRE = 0x1
7309 12:42:38.902297 WR_PST = 0x1
7310 12:42:38.902430 DBI_WR = 0x0
7311 12:42:38.905752 DBI_RD = 0x0
7312 12:42:38.905832 OTF = 0x1
7313 12:42:38.909215 ===================================
7314 12:42:38.915721 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7315 12:42:38.915802 ==
7316 12:42:38.919033 Dram Type= 6, Freq= 0, CH_0, rank 0
7317 12:42:38.922500 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7318 12:42:38.922593 ==
7319 12:42:38.925682 [Duty_Offset_Calibration]
7320 12:42:38.929304 B0:2 B1:-1 CA:1
7321 12:42:38.929388
7322 12:42:38.932219 [DutyScan_Calibration_Flow] k_type=0
7323 12:42:38.940087
7324 12:42:38.940170 ==CLK 0==
7325 12:42:38.943637 Final CLK duty delay cell = -4
7326 12:42:38.947102 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7327 12:42:38.950156 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7328 12:42:38.953436 [-4] AVG Duty = 4937%(X100)
7329 12:42:38.953516
7330 12:42:38.956730 CH0 CLK Duty spec in!! Max-Min= 187%
7331 12:42:38.960737 [DutyScan_Calibration_Flow] ====Done====
7332 12:42:38.960816
7333 12:42:38.963510 [DutyScan_Calibration_Flow] k_type=1
7334 12:42:38.979907
7335 12:42:38.979988 ==DQS 0 ==
7336 12:42:38.982887 Final DQS duty delay cell = 0
7337 12:42:38.986231 [0] MAX Duty = 5125%(X100), DQS PI = 46
7338 12:42:38.989673 [0] MIN Duty = 5000%(X100), DQS PI = 16
7339 12:42:38.992917 [0] AVG Duty = 5062%(X100)
7340 12:42:38.992989
7341 12:42:38.993055 ==DQS 1 ==
7342 12:42:38.996201 Final DQS duty delay cell = -4
7343 12:42:38.999629 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7344 12:42:39.003214 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7345 12:42:39.006196 [-4] AVG Duty = 5046%(X100)
7346 12:42:39.006267
7347 12:42:39.009632 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7348 12:42:39.009702
7349 12:42:39.012955 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7350 12:42:39.016628 [DutyScan_Calibration_Flow] ====Done====
7351 12:42:39.016697
7352 12:42:39.019753 [DutyScan_Calibration_Flow] k_type=3
7353 12:42:39.037468
7354 12:42:39.037545 ==DQM 0 ==
7355 12:42:39.040929 Final DQM duty delay cell = 0
7356 12:42:39.043853 [0] MAX Duty = 5000%(X100), DQS PI = 18
7357 12:42:39.047154 [0] MIN Duty = 4875%(X100), DQS PI = 6
7358 12:42:39.047227 [0] AVG Duty = 4937%(X100)
7359 12:42:39.050024
7360 12:42:39.050094 ==DQM 1 ==
7361 12:42:39.053668 Final DQM duty delay cell = 0
7362 12:42:39.056917 [0] MAX Duty = 5218%(X100), DQS PI = 58
7363 12:42:39.060283 [0] MIN Duty = 4969%(X100), DQS PI = 18
7364 12:42:39.060356 [0] AVG Duty = 5093%(X100)
7365 12:42:39.063814
7366 12:42:39.067239 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7367 12:42:39.067347
7368 12:42:39.070474 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7369 12:42:39.073805 [DutyScan_Calibration_Flow] ====Done====
7370 12:42:39.073898
7371 12:42:39.076768 [DutyScan_Calibration_Flow] k_type=2
7372 12:42:39.093154
7373 12:42:39.093266 ==DQ 0 ==
7374 12:42:39.096607 Final DQ duty delay cell = -4
7375 12:42:39.099786 [-4] MAX Duty = 5062%(X100), DQS PI = 56
7376 12:42:39.103561 [-4] MIN Duty = 4844%(X100), DQS PI = 14
7377 12:42:39.106947 [-4] AVG Duty = 4953%(X100)
7378 12:42:39.107019
7379 12:42:39.107098 ==DQ 1 ==
7380 12:42:39.110290 Final DQ duty delay cell = 0
7381 12:42:39.113157 [0] MAX Duty = 5031%(X100), DQS PI = 30
7382 12:42:39.116553 [0] MIN Duty = 4907%(X100), DQS PI = 18
7383 12:42:39.120090 [0] AVG Duty = 4969%(X100)
7384 12:42:39.120161
7385 12:42:39.123543 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7386 12:42:39.123629
7387 12:42:39.126542 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7388 12:42:39.130317 [DutyScan_Calibration_Flow] ====Done====
7389 12:42:39.130456 ==
7390 12:42:39.133720 Dram Type= 6, Freq= 0, CH_1, rank 0
7391 12:42:39.136833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7392 12:42:39.137004 ==
7393 12:42:39.140289 [Duty_Offset_Calibration]
7394 12:42:39.140357 B0:1 B1:1 CA:2
7395 12:42:39.140416
7396 12:42:39.143661 [DutyScan_Calibration_Flow] k_type=0
7397 12:42:39.153944
7398 12:42:39.154051 ==CLK 0==
7399 12:42:39.157013 Final CLK duty delay cell = 0
7400 12:42:39.161006 [0] MAX Duty = 5218%(X100), DQS PI = 24
7401 12:42:39.164039 [0] MIN Duty = 4969%(X100), DQS PI = 48
7402 12:42:39.164113 [0] AVG Duty = 5093%(X100)
7403 12:42:39.167155
7404 12:42:39.170439 CH1 CLK Duty spec in!! Max-Min= 249%
7405 12:42:39.174305 [DutyScan_Calibration_Flow] ====Done====
7406 12:42:39.174423
7407 12:42:39.177195 [DutyScan_Calibration_Flow] k_type=1
7408 12:42:39.193891
7409 12:42:39.193999 ==DQS 0 ==
7410 12:42:39.197402 Final DQS duty delay cell = 0
7411 12:42:39.200353 [0] MAX Duty = 5031%(X100), DQS PI = 20
7412 12:42:39.203515 [0] MIN Duty = 4813%(X100), DQS PI = 52
7413 12:42:39.206909 [0] AVG Duty = 4922%(X100)
7414 12:42:39.206992
7415 12:42:39.207055 ==DQS 1 ==
7416 12:42:39.210175 Final DQS duty delay cell = 0
7417 12:42:39.213875 [0] MAX Duty = 5062%(X100), DQS PI = 34
7418 12:42:39.217357 [0] MIN Duty = 4938%(X100), DQS PI = 14
7419 12:42:39.220444 [0] AVG Duty = 5000%(X100)
7420 12:42:39.220549
7421 12:42:39.223315 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7422 12:42:39.223385
7423 12:42:39.226849 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7424 12:42:39.230197 [DutyScan_Calibration_Flow] ====Done====
7425 12:42:39.230298
7426 12:42:39.233448 [DutyScan_Calibration_Flow] k_type=3
7427 12:42:39.250911
7428 12:42:39.251054 ==DQM 0 ==
7429 12:42:39.254106 Final DQM duty delay cell = 0
7430 12:42:39.257925 [0] MAX Duty = 5187%(X100), DQS PI = 20
7431 12:42:39.260765 [0] MIN Duty = 4844%(X100), DQS PI = 50
7432 12:42:39.263931 [0] AVG Duty = 5015%(X100)
7433 12:42:39.264020
7434 12:42:39.264083 ==DQM 1 ==
7435 12:42:39.267759 Final DQM duty delay cell = 0
7436 12:42:39.270842 [0] MAX Duty = 5125%(X100), DQS PI = 8
7437 12:42:39.274215 [0] MIN Duty = 4875%(X100), DQS PI = 20
7438 12:42:39.274310 [0] AVG Duty = 5000%(X100)
7439 12:42:39.277472
7440 12:42:39.281078 CH1 DQM 0 Duty spec in!! Max-Min= 343%
7441 12:42:39.281177
7442 12:42:39.283770 CH1 DQM 1 Duty spec in!! Max-Min= 250%
7443 12:42:39.287643 [DutyScan_Calibration_Flow] ====Done====
7444 12:42:39.287732
7445 12:42:39.290311 [DutyScan_Calibration_Flow] k_type=2
7446 12:42:39.307309
7447 12:42:39.307385 ==DQ 0 ==
7448 12:42:39.310825 Final DQ duty delay cell = 0
7449 12:42:39.314427 [0] MAX Duty = 5125%(X100), DQS PI = 22
7450 12:42:39.317803 [0] MIN Duty = 4938%(X100), DQS PI = 50
7451 12:42:39.317910 [0] AVG Duty = 5031%(X100)
7452 12:42:39.317999
7453 12:42:39.321046 ==DQ 1 ==
7454 12:42:39.324103 Final DQ duty delay cell = 0
7455 12:42:39.327462 [0] MAX Duty = 5093%(X100), DQS PI = 6
7456 12:42:39.330966 [0] MIN Duty = 5031%(X100), DQS PI = 0
7457 12:42:39.331067 [0] AVG Duty = 5062%(X100)
7458 12:42:39.331168
7459 12:42:39.334194 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7460 12:42:39.334284
7461 12:42:39.337768 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7462 12:42:39.340691 [DutyScan_Calibration_Flow] ====Done====
7463 12:42:39.347008 nWR fixed to 30
7464 12:42:39.349512 [ModeRegInit_LP4] CH0 RK0
7465 12:42:39.349593 [ModeRegInit_LP4] CH0 RK1
7466 12:42:39.353418 [ModeRegInit_LP4] CH1 RK0
7467 12:42:39.356325 [ModeRegInit_LP4] CH1 RK1
7468 12:42:39.356402 match AC timing 5
7469 12:42:39.363484 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7470 12:42:39.366025 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7471 12:42:39.369598 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7472 12:42:39.376132 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7473 12:42:39.379912 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7474 12:42:39.379988 [MiockJmeterHQA]
7475 12:42:39.380050
7476 12:42:39.382926 [DramcMiockJmeter] u1RxGatingPI = 0
7477 12:42:39.386431 0 : 4252, 4027
7478 12:42:39.386528 4 : 4252, 4027
7479 12:42:39.390078 8 : 4363, 4137
7480 12:42:39.390152 12 : 4252, 4027
7481 12:42:39.392930 16 : 4363, 4137
7482 12:42:39.393003 20 : 4255, 4029
7483 12:42:39.393063 24 : 4363, 4138
7484 12:42:39.396686 28 : 4252, 4027
7485 12:42:39.396764 32 : 4252, 4027
7486 12:42:39.399872 36 : 4253, 4026
7487 12:42:39.399945 40 : 4254, 4029
7488 12:42:39.403526 44 : 4363, 4137
7489 12:42:39.403606 48 : 4250, 4027
7490 12:42:39.403670 52 : 4363, 4137
7491 12:42:39.406528 56 : 4250, 4026
7492 12:42:39.406605 60 : 4249, 4027
7493 12:42:39.409476 64 : 4250, 4026
7494 12:42:39.409553 68 : 4361, 4137
7495 12:42:39.413032 72 : 4250, 4027
7496 12:42:39.413100 76 : 4361, 4137
7497 12:42:39.416951 80 : 4250, 4027
7498 12:42:39.417041 84 : 4250, 4026
7499 12:42:39.417170 88 : 4250, 4026
7500 12:42:39.419811 92 : 4252, 4029
7501 12:42:39.419901 96 : 4361, 3611
7502 12:42:39.423749 100 : 4250, 0
7503 12:42:39.423817 104 : 4361, 0
7504 12:42:39.423885 108 : 4362, 0
7505 12:42:39.426604 112 : 4250, 0
7506 12:42:39.426670 116 : 4360, 0
7507 12:42:39.430211 120 : 4250, 0
7508 12:42:39.430280 124 : 4249, 0
7509 12:42:39.430339 128 : 4252, 0
7510 12:42:39.433333 132 : 4250, 0
7511 12:42:39.433402 136 : 4252, 0
7512 12:42:39.436752 140 : 4361, 0
7513 12:42:39.436824 144 : 4249, 0
7514 12:42:39.436882 148 : 4250, 0
7515 12:42:39.439978 152 : 4250, 0
7516 12:42:39.440053 156 : 4249, 0
7517 12:42:39.440114 160 : 4363, 0
7518 12:42:39.443260 164 : 4250, 0
7519 12:42:39.443354 168 : 4250, 0
7520 12:42:39.447142 172 : 4250, 0
7521 12:42:39.447219 176 : 4363, 0
7522 12:42:39.447282 180 : 4250, 0
7523 12:42:39.449794 184 : 4250, 0
7524 12:42:39.449879 188 : 4252, 0
7525 12:42:39.452986 192 : 4250, 0
7526 12:42:39.453057 196 : 4250, 0
7527 12:42:39.453120 200 : 4252, 0
7528 12:42:39.456521 204 : 4250, 0
7529 12:42:39.456593 208 : 4361, 0
7530 12:42:39.459903 212 : 4361, 127
7531 12:42:39.459974 216 : 4250, 3735
7532 12:42:39.460037 220 : 4361, 4137
7533 12:42:39.463565 224 : 4250, 4027
7534 12:42:39.463639 228 : 4250, 4027
7535 12:42:39.466855 232 : 4361, 4137
7536 12:42:39.466939 236 : 4361, 4137
7537 12:42:39.469779 240 : 4250, 4027
7538 12:42:39.469853 244 : 4363, 4140
7539 12:42:39.473036 248 : 4361, 4137
7540 12:42:39.473106 252 : 4250, 4026
7541 12:42:39.476524 256 : 4250, 4027
7542 12:42:39.476598 260 : 4252, 4029
7543 12:42:39.480224 264 : 4250, 4027
7544 12:42:39.480301 268 : 4250, 4026
7545 12:42:39.482995 272 : 4250, 4027
7546 12:42:39.483064 276 : 4252, 4030
7547 12:42:39.483123 280 : 4250, 4027
7548 12:42:39.486368 284 : 4360, 4137
7549 12:42:39.486474 288 : 4361, 4137
7550 12:42:39.489896 292 : 4250, 4027
7551 12:42:39.489965 296 : 4363, 4140
7552 12:42:39.493620 300 : 4250, 4027
7553 12:42:39.493696 304 : 4250, 4026
7554 12:42:39.496385 308 : 4250, 4027
7555 12:42:39.496454 312 : 4252, 4030
7556 12:42:39.500188 316 : 4250, 4027
7557 12:42:39.500270 320 : 4250, 4026
7558 12:42:39.503362 324 : 4250, 4027
7559 12:42:39.503438 328 : 4252, 4030
7560 12:42:39.503498 332 : 4250, 3031
7561 12:42:39.506829 336 : 4360, 172
7562 12:42:39.506909
7563 12:42:39.509970 MIOCK jitter meter ch=0
7564 12:42:39.510047
7565 12:42:39.513132 1T = (336-100) = 236 dly cells
7566 12:42:39.516410 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7567 12:42:39.516487 ==
7568 12:42:39.520178 Dram Type= 6, Freq= 0, CH_0, rank 0
7569 12:42:39.523524 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7570 12:42:39.526854 ==
7571 12:42:39.530520 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7572 12:42:39.533352 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7573 12:42:39.540471 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7574 12:42:39.546295 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7575 12:42:39.554337 [CA 0] Center 44 (14~75) winsize 62
7576 12:42:39.557748 [CA 1] Center 44 (14~75) winsize 62
7577 12:42:39.560602 [CA 2] Center 40 (11~69) winsize 59
7578 12:42:39.564064 [CA 3] Center 39 (10~69) winsize 60
7579 12:42:39.567489 [CA 4] Center 38 (8~68) winsize 61
7580 12:42:39.570702 [CA 5] Center 37 (7~67) winsize 61
7581 12:42:39.570814
7582 12:42:39.573891 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7583 12:42:39.573987
7584 12:42:39.577131 [CATrainingPosCal] consider 1 rank data
7585 12:42:39.580543 u2DelayCellTimex100 = 275/100 ps
7586 12:42:39.587232 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7587 12:42:39.590505 CA1 delay=44 (14~75),Diff = 7 PI (24 cell)
7588 12:42:39.593687 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7589 12:42:39.597170 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7590 12:42:39.600886 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7591 12:42:39.603728 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7592 12:42:39.603805
7593 12:42:39.607640 CA PerBit enable=1, Macro0, CA PI delay=37
7594 12:42:39.607717
7595 12:42:39.610520 [CBTSetCACLKResult] CA Dly = 37
7596 12:42:39.614261 CS Dly: 10 (0~41)
7597 12:42:39.617343 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7598 12:42:39.620621 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7599 12:42:39.620695 ==
7600 12:42:39.624633 Dram Type= 6, Freq= 0, CH_0, rank 1
7601 12:42:39.627414 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7602 12:42:39.630618 ==
7603 12:42:39.633854 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7604 12:42:39.637778 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7605 12:42:39.644126 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7606 12:42:39.647542 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7607 12:42:39.657823 [CA 0] Center 43 (13~74) winsize 62
7608 12:42:39.661383 [CA 1] Center 43 (13~74) winsize 62
7609 12:42:39.664584 [CA 2] Center 39 (10~69) winsize 60
7610 12:42:39.667763 [CA 3] Center 38 (9~68) winsize 60
7611 12:42:39.671393 [CA 4] Center 37 (7~67) winsize 61
7612 12:42:39.674452 [CA 5] Center 37 (7~67) winsize 61
7613 12:42:39.674524
7614 12:42:39.677832 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7615 12:42:39.677907
7616 12:42:39.681341 [CATrainingPosCal] consider 2 rank data
7617 12:42:39.684686 u2DelayCellTimex100 = 275/100 ps
7618 12:42:39.687899 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7619 12:42:39.694401 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7620 12:42:39.698205 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7621 12:42:39.701156 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7622 12:42:39.705127 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7623 12:42:39.707599 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7624 12:42:39.707672
7625 12:42:39.711547 CA PerBit enable=1, Macro0, CA PI delay=37
7626 12:42:39.711622
7627 12:42:39.714759 [CBTSetCACLKResult] CA Dly = 37
7628 12:42:39.717938 CS Dly: 11 (0~44)
7629 12:42:39.721714 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7630 12:42:39.724160 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7631 12:42:39.724236
7632 12:42:39.728088 ----->DramcWriteLeveling(PI) begin...
7633 12:42:39.728170 ==
7634 12:42:39.732313 Dram Type= 6, Freq= 0, CH_0, rank 0
7635 12:42:39.734649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7636 12:42:39.738003 ==
7637 12:42:39.741259 Write leveling (Byte 0): 34 => 34
7638 12:42:39.741331 Write leveling (Byte 1): 27 => 27
7639 12:42:39.744401 DramcWriteLeveling(PI) end<-----
7640 12:42:39.744508
7641 12:42:39.744583 ==
7642 12:42:39.748058 Dram Type= 6, Freq= 0, CH_0, rank 0
7643 12:42:39.754241 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7644 12:42:39.754320 ==
7645 12:42:39.757767 [Gating] SW mode calibration
7646 12:42:39.764602 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7647 12:42:39.767855 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7648 12:42:39.774195 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7649 12:42:39.777577 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7650 12:42:39.781817 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7651 12:42:39.787605 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7652 12:42:39.791210 1 4 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7653 12:42:39.794910 1 4 20 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
7654 12:42:39.797927 1 4 24 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
7655 12:42:39.804476 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7656 12:42:39.807917 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7657 12:42:39.811054 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7658 12:42:39.818298 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7659 12:42:39.821317 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7660 12:42:39.824455 1 5 16 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (1 0)
7661 12:42:39.831619 1 5 20 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
7662 12:42:39.834533 1 5 24 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
7663 12:42:39.838081 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7664 12:42:39.844622 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7665 12:42:39.847754 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7666 12:42:39.851639 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7667 12:42:39.857959 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7668 12:42:39.861459 1 6 16 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7669 12:42:39.864578 1 6 20 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7670 12:42:39.867964 1 6 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7671 12:42:39.874494 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7672 12:42:39.878336 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7673 12:42:39.881527 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7674 12:42:39.888148 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7675 12:42:39.891551 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7676 12:42:39.894598 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7677 12:42:39.901139 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7678 12:42:39.904516 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7679 12:42:39.908265 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 12:42:39.914527 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 12:42:39.917702 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7682 12:42:39.921198 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7683 12:42:39.927944 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7684 12:42:39.931486 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7685 12:42:39.934708 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7686 12:42:39.941368 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 12:42:39.944766 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 12:42:39.948743 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 12:42:39.954641 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7690 12:42:39.958688 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 12:42:39.961273 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7692 12:42:39.964906 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7693 12:42:39.971357 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7694 12:42:39.975150 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7695 12:42:39.978271 Total UI for P1: 0, mck2ui 16
7696 12:42:39.981184 best dqsien dly found for B0: ( 1, 9, 16)
7697 12:42:39.984550 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7698 12:42:39.988129 Total UI for P1: 0, mck2ui 16
7699 12:42:39.991689 best dqsien dly found for B1: ( 1, 9, 22)
7700 12:42:39.994320 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7701 12:42:39.998198 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7702 12:42:39.998272
7703 12:42:40.004418 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7704 12:42:40.008049 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7705 12:42:40.011020 [Gating] SW calibration Done
7706 12:42:40.011096 ==
7707 12:42:40.014697 Dram Type= 6, Freq= 0, CH_0, rank 0
7708 12:42:40.017953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7709 12:42:40.018033 ==
7710 12:42:40.018094 RX Vref Scan: 0
7711 12:42:40.021184
7712 12:42:40.021256 RX Vref 0 -> 0, step: 1
7713 12:42:40.021319
7714 12:42:40.024774 RX Delay 0 -> 252, step: 8
7715 12:42:40.028078 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7716 12:42:40.031417 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7717 12:42:40.037892 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7718 12:42:40.041167 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7719 12:42:40.044708 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7720 12:42:40.048064 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7721 12:42:40.051412 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7722 12:42:40.058168 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7723 12:42:40.061563 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7724 12:42:40.064716 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7725 12:42:40.067991 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7726 12:42:40.071052 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7727 12:42:40.077763 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7728 12:42:40.081215 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7729 12:42:40.084855 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7730 12:42:40.088157 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7731 12:42:40.088237 ==
7732 12:42:40.091028 Dram Type= 6, Freq= 0, CH_0, rank 0
7733 12:42:40.094306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7734 12:42:40.098186 ==
7735 12:42:40.098286 DQS Delay:
7736 12:42:40.098404 DQS0 = 0, DQS1 = 0
7737 12:42:40.101480 DQM Delay:
7738 12:42:40.101576 DQM0 = 132, DQM1 = 123
7739 12:42:40.104466 DQ Delay:
7740 12:42:40.108720 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7741 12:42:40.111531 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7742 12:42:40.114821 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115
7743 12:42:40.118074 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7744 12:42:40.118175
7745 12:42:40.118270
7746 12:42:40.118360 ==
7747 12:42:40.121343 Dram Type= 6, Freq= 0, CH_0, rank 0
7748 12:42:40.124946 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7749 12:42:40.125016 ==
7750 12:42:40.125091
7751 12:42:40.125152
7752 12:42:40.127797 TX Vref Scan disable
7753 12:42:40.131386 == TX Byte 0 ==
7754 12:42:40.135094 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7755 12:42:40.138360 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7756 12:42:40.141273 == TX Byte 1 ==
7757 12:42:40.144501 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7758 12:42:40.148092 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7759 12:42:40.148193 ==
7760 12:42:40.151653 Dram Type= 6, Freq= 0, CH_0, rank 0
7761 12:42:40.158038 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7762 12:42:40.158145 ==
7763 12:42:40.171199
7764 12:42:40.174656 TX Vref early break, caculate TX vref
7765 12:42:40.177969 TX Vref=16, minBit 4, minWin=21, winSum=354
7766 12:42:40.181159 TX Vref=18, minBit 1, minWin=22, winSum=368
7767 12:42:40.184248 TX Vref=20, minBit 7, minWin=22, winSum=378
7768 12:42:40.187764 TX Vref=22, minBit 4, minWin=23, winSum=390
7769 12:42:40.191191 TX Vref=24, minBit 4, minWin=23, winSum=399
7770 12:42:40.197531 TX Vref=26, minBit 4, minWin=24, winSum=408
7771 12:42:40.201173 TX Vref=28, minBit 4, minWin=24, winSum=415
7772 12:42:40.204181 TX Vref=30, minBit 3, minWin=25, winSum=418
7773 12:42:40.208242 TX Vref=32, minBit 4, minWin=24, winSum=410
7774 12:42:40.211282 TX Vref=34, minBit 2, minWin=24, winSum=401
7775 12:42:40.214920 TX Vref=36, minBit 9, minWin=22, winSum=386
7776 12:42:40.221137 [TxChooseVref] Worse bit 3, Min win 25, Win sum 418, Final Vref 30
7777 12:42:40.221247
7778 12:42:40.224337 Final TX Range 0 Vref 30
7779 12:42:40.224408
7780 12:42:40.224474 ==
7781 12:42:40.227716 Dram Type= 6, Freq= 0, CH_0, rank 0
7782 12:42:40.231004 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7783 12:42:40.231088 ==
7784 12:42:40.231152
7785 12:42:40.231213
7786 12:42:40.234367 TX Vref Scan disable
7787 12:42:40.240875 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7788 12:42:40.240951 == TX Byte 0 ==
7789 12:42:40.244617 u2DelayCellOfst[0]=14 cells (4 PI)
7790 12:42:40.248004 u2DelayCellOfst[1]=17 cells (5 PI)
7791 12:42:40.251172 u2DelayCellOfst[2]=10 cells (3 PI)
7792 12:42:40.254334 u2DelayCellOfst[3]=10 cells (3 PI)
7793 12:42:40.258546 u2DelayCellOfst[4]=10 cells (3 PI)
7794 12:42:40.261634 u2DelayCellOfst[5]=0 cells (0 PI)
7795 12:42:40.264457 u2DelayCellOfst[6]=17 cells (5 PI)
7796 12:42:40.268244 u2DelayCellOfst[7]=17 cells (5 PI)
7797 12:42:40.271112 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7798 12:42:40.274804 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7799 12:42:40.278166 == TX Byte 1 ==
7800 12:42:40.281051 u2DelayCellOfst[8]=0 cells (0 PI)
7801 12:42:40.281122 u2DelayCellOfst[9]=0 cells (0 PI)
7802 12:42:40.285016 u2DelayCellOfst[10]=7 cells (2 PI)
7803 12:42:40.287774 u2DelayCellOfst[11]=0 cells (0 PI)
7804 12:42:40.291520 u2DelayCellOfst[12]=10 cells (3 PI)
7805 12:42:40.294384 u2DelayCellOfst[13]=10 cells (3 PI)
7806 12:42:40.298292 u2DelayCellOfst[14]=14 cells (4 PI)
7807 12:42:40.301813 u2DelayCellOfst[15]=14 cells (4 PI)
7808 12:42:40.304947 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7809 12:42:40.311314 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7810 12:42:40.311391 DramC Write-DBI on
7811 12:42:40.311457 ==
7812 12:42:40.314612 Dram Type= 6, Freq= 0, CH_0, rank 0
7813 12:42:40.318035 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7814 12:42:40.321449 ==
7815 12:42:40.321530
7816 12:42:40.321591
7817 12:42:40.321648 TX Vref Scan disable
7818 12:42:40.325025 == TX Byte 0 ==
7819 12:42:40.328791 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7820 12:42:40.331569 == TX Byte 1 ==
7821 12:42:40.334761 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7822 12:42:40.338377 DramC Write-DBI off
7823 12:42:40.338479
7824 12:42:40.338540 [DATLAT]
7825 12:42:40.338598 Freq=1600, CH0 RK0
7826 12:42:40.338662
7827 12:42:40.341300 DATLAT Default: 0xf
7828 12:42:40.341367 0, 0xFFFF, sum = 0
7829 12:42:40.344827 1, 0xFFFF, sum = 0
7830 12:42:40.344906 2, 0xFFFF, sum = 0
7831 12:42:40.348102 3, 0xFFFF, sum = 0
7832 12:42:40.351214 4, 0xFFFF, sum = 0
7833 12:42:40.351285 5, 0xFFFF, sum = 0
7834 12:42:40.354773 6, 0xFFFF, sum = 0
7835 12:42:40.354846 7, 0xFFFF, sum = 0
7836 12:42:40.358250 8, 0xFFFF, sum = 0
7837 12:42:40.358320 9, 0xFFFF, sum = 0
7838 12:42:40.361259 10, 0xFFFF, sum = 0
7839 12:42:40.361329 11, 0xFFFF, sum = 0
7840 12:42:40.364355 12, 0xFFFF, sum = 0
7841 12:42:40.364433 13, 0xFFFF, sum = 0
7842 12:42:40.367856 14, 0x0, sum = 1
7843 12:42:40.367927 15, 0x0, sum = 2
7844 12:42:40.371314 16, 0x0, sum = 3
7845 12:42:40.371386 17, 0x0, sum = 4
7846 12:42:40.374648 best_step = 15
7847 12:42:40.374720
7848 12:42:40.374781 ==
7849 12:42:40.378097 Dram Type= 6, Freq= 0, CH_0, rank 0
7850 12:42:40.381122 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7851 12:42:40.381193 ==
7852 12:42:40.384410 RX Vref Scan: 1
7853 12:42:40.384487
7854 12:42:40.384552 Set Vref Range= 24 -> 127
7855 12:42:40.384623
7856 12:42:40.387771 RX Vref 24 -> 127, step: 1
7857 12:42:40.387843
7858 12:42:40.390948 RX Delay 11 -> 252, step: 4
7859 12:42:40.391020
7860 12:42:40.394619 Set Vref, RX VrefLevel [Byte0]: 24
7861 12:42:40.397688 [Byte1]: 24
7862 12:42:40.397764
7863 12:42:40.401044 Set Vref, RX VrefLevel [Byte0]: 25
7864 12:42:40.404232 [Byte1]: 25
7865 12:42:40.404382
7866 12:42:40.407711 Set Vref, RX VrefLevel [Byte0]: 26
7867 12:42:40.411434 [Byte1]: 26
7868 12:42:40.415315
7869 12:42:40.415389 Set Vref, RX VrefLevel [Byte0]: 27
7870 12:42:40.418599 [Byte1]: 27
7871 12:42:40.422714
7872 12:42:40.422786 Set Vref, RX VrefLevel [Byte0]: 28
7873 12:42:40.426515 [Byte1]: 28
7874 12:42:40.430261
7875 12:42:40.430334 Set Vref, RX VrefLevel [Byte0]: 29
7876 12:42:40.433952 [Byte1]: 29
7877 12:42:40.437774
7878 12:42:40.437849 Set Vref, RX VrefLevel [Byte0]: 30
7879 12:42:40.441053 [Byte1]: 30
7880 12:42:40.445597
7881 12:42:40.445701 Set Vref, RX VrefLevel [Byte0]: 31
7882 12:42:40.449438 [Byte1]: 31
7883 12:42:40.453396
7884 12:42:40.453503 Set Vref, RX VrefLevel [Byte0]: 32
7885 12:42:40.456427 [Byte1]: 32
7886 12:42:40.460927
7887 12:42:40.461009 Set Vref, RX VrefLevel [Byte0]: 33
7888 12:42:40.463920 [Byte1]: 33
7889 12:42:40.468215
7890 12:42:40.468339 Set Vref, RX VrefLevel [Byte0]: 34
7891 12:42:40.472261 [Byte1]: 34
7892 12:42:40.475945
7893 12:42:40.476025 Set Vref, RX VrefLevel [Byte0]: 35
7894 12:42:40.479656 [Byte1]: 35
7895 12:42:40.484273
7896 12:42:40.484407 Set Vref, RX VrefLevel [Byte0]: 36
7897 12:42:40.487025 [Byte1]: 36
7898 12:42:40.491192
7899 12:42:40.491285 Set Vref, RX VrefLevel [Byte0]: 37
7900 12:42:40.494836 [Byte1]: 37
7901 12:42:40.499137
7902 12:42:40.499217 Set Vref, RX VrefLevel [Byte0]: 38
7903 12:42:40.502211 [Byte1]: 38
7904 12:42:40.506975
7905 12:42:40.507058 Set Vref, RX VrefLevel [Byte0]: 39
7906 12:42:40.509833 [Byte1]: 39
7907 12:42:40.514060
7908 12:42:40.514141 Set Vref, RX VrefLevel [Byte0]: 40
7909 12:42:40.517904 [Byte1]: 40
7910 12:42:40.521782
7911 12:42:40.521863 Set Vref, RX VrefLevel [Byte0]: 41
7912 12:42:40.524741 [Byte1]: 41
7913 12:42:40.529729
7914 12:42:40.529809 Set Vref, RX VrefLevel [Byte0]: 42
7915 12:42:40.532702 [Byte1]: 42
7916 12:42:40.536854
7917 12:42:40.536936 Set Vref, RX VrefLevel [Byte0]: 43
7918 12:42:40.540284 [Byte1]: 43
7919 12:42:40.544713
7920 12:42:40.544798 Set Vref, RX VrefLevel [Byte0]: 44
7921 12:42:40.548097 [Byte1]: 44
7922 12:42:40.552598
7923 12:42:40.552694 Set Vref, RX VrefLevel [Byte0]: 45
7924 12:42:40.555556 [Byte1]: 45
7925 12:42:40.559634
7926 12:42:40.559715 Set Vref, RX VrefLevel [Byte0]: 46
7927 12:42:40.563366 [Byte1]: 46
7928 12:42:40.567360
7929 12:42:40.567440 Set Vref, RX VrefLevel [Byte0]: 47
7930 12:42:40.570940 [Byte1]: 47
7931 12:42:40.575435
7932 12:42:40.575515 Set Vref, RX VrefLevel [Byte0]: 48
7933 12:42:40.578262 [Byte1]: 48
7934 12:42:40.582786
7935 12:42:40.582867 Set Vref, RX VrefLevel [Byte0]: 49
7936 12:42:40.585875 [Byte1]: 49
7937 12:42:40.590586
7938 12:42:40.590667 Set Vref, RX VrefLevel [Byte0]: 50
7939 12:42:40.595148 [Byte1]: 50
7940 12:42:40.598287
7941 12:42:40.598407 Set Vref, RX VrefLevel [Byte0]: 51
7942 12:42:40.601027 [Byte1]: 51
7943 12:42:40.605831
7944 12:42:40.605908 Set Vref, RX VrefLevel [Byte0]: 52
7945 12:42:40.608852 [Byte1]: 52
7946 12:42:40.613114
7947 12:42:40.613189 Set Vref, RX VrefLevel [Byte0]: 53
7948 12:42:40.616383 [Byte1]: 53
7949 12:42:40.620652
7950 12:42:40.620730 Set Vref, RX VrefLevel [Byte0]: 54
7951 12:42:40.624167 [Byte1]: 54
7952 12:42:40.628115
7953 12:42:40.628191 Set Vref, RX VrefLevel [Byte0]: 55
7954 12:42:40.631396 [Byte1]: 55
7955 12:42:40.636074
7956 12:42:40.636156 Set Vref, RX VrefLevel [Byte0]: 56
7957 12:42:40.639352 [Byte1]: 56
7958 12:42:40.643867
7959 12:42:40.643943 Set Vref, RX VrefLevel [Byte0]: 57
7960 12:42:40.646911 [Byte1]: 57
7961 12:42:40.651369
7962 12:42:40.651442 Set Vref, RX VrefLevel [Byte0]: 58
7963 12:42:40.654756 [Byte1]: 58
7964 12:42:40.659046
7965 12:42:40.659119 Set Vref, RX VrefLevel [Byte0]: 59
7966 12:42:40.662374 [Byte1]: 59
7967 12:42:40.666262
7968 12:42:40.666333 Set Vref, RX VrefLevel [Byte0]: 60
7969 12:42:40.669519 [Byte1]: 60
7970 12:42:40.674236
7971 12:42:40.674307 Set Vref, RX VrefLevel [Byte0]: 61
7972 12:42:40.677793 [Byte1]: 61
7973 12:42:40.681672
7974 12:42:40.681749 Set Vref, RX VrefLevel [Byte0]: 62
7975 12:42:40.685476 [Byte1]: 62
7976 12:42:40.689024
7977 12:42:40.689095 Set Vref, RX VrefLevel [Byte0]: 63
7978 12:42:40.692535 [Byte1]: 63
7979 12:42:40.696656
7980 12:42:40.696733 Set Vref, RX VrefLevel [Byte0]: 64
7981 12:42:40.700186 [Byte1]: 64
7982 12:42:40.704470
7983 12:42:40.704553 Set Vref, RX VrefLevel [Byte0]: 65
7984 12:42:40.707861 [Byte1]: 65
7985 12:42:40.712069
7986 12:42:40.712145 Set Vref, RX VrefLevel [Byte0]: 66
7987 12:42:40.715509 [Byte1]: 66
7988 12:42:40.719480
7989 12:42:40.719560 Set Vref, RX VrefLevel [Byte0]: 67
7990 12:42:40.723198 [Byte1]: 67
7991 12:42:40.727114
7992 12:42:40.727187 Set Vref, RX VrefLevel [Byte0]: 68
7993 12:42:40.730643 [Byte1]: 68
7994 12:42:40.735003
7995 12:42:40.735082 Set Vref, RX VrefLevel [Byte0]: 69
7996 12:42:40.738322 [Byte1]: 69
7997 12:42:40.742373
7998 12:42:40.742493 Set Vref, RX VrefLevel [Byte0]: 70
7999 12:42:40.745611 [Byte1]: 70
8000 12:42:40.749763
8001 12:42:40.749841 Set Vref, RX VrefLevel [Byte0]: 71
8002 12:42:40.753466 [Byte1]: 71
8003 12:42:40.758005
8004 12:42:40.758112 Set Vref, RX VrefLevel [Byte0]: 72
8005 12:42:40.761009 [Byte1]: 72
8006 12:42:40.765515
8007 12:42:40.765606 Set Vref, RX VrefLevel [Byte0]: 73
8008 12:42:40.768714 [Byte1]: 73
8009 12:42:40.773066
8010 12:42:40.773161 Set Vref, RX VrefLevel [Byte0]: 74
8011 12:42:40.776102 [Byte1]: 74
8012 12:42:40.780634
8013 12:42:40.780714 Set Vref, RX VrefLevel [Byte0]: 75
8014 12:42:40.783930 [Byte1]: 75
8015 12:42:40.788405
8016 12:42:40.788481 Set Vref, RX VrefLevel [Byte0]: 76
8017 12:42:40.791247 [Byte1]: 76
8018 12:42:40.795735
8019 12:42:40.795839 Set Vref, RX VrefLevel [Byte0]: 77
8020 12:42:40.799441 [Byte1]: 77
8021 12:42:40.803561
8022 12:42:40.803635 Set Vref, RX VrefLevel [Byte0]: 78
8023 12:42:40.807285 [Byte1]: 78
8024 12:42:40.810915
8025 12:42:40.810988 Final RX Vref Byte 0 = 62 to rank0
8026 12:42:40.814720 Final RX Vref Byte 1 = 59 to rank0
8027 12:42:40.817853 Final RX Vref Byte 0 = 62 to rank1
8028 12:42:40.820809 Final RX Vref Byte 1 = 59 to rank1==
8029 12:42:40.824076 Dram Type= 6, Freq= 0, CH_0, rank 0
8030 12:42:40.831538 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8031 12:42:40.831622 ==
8032 12:42:40.831685 DQS Delay:
8033 12:42:40.831744 DQS0 = 0, DQS1 = 0
8034 12:42:40.834679 DQM Delay:
8035 12:42:40.834772 DQM0 = 129, DQM1 = 121
8036 12:42:40.837903 DQ Delay:
8037 12:42:40.840898 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =124
8038 12:42:40.844519 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
8039 12:42:40.848776 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
8040 12:42:40.850818 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
8041 12:42:40.850900
8042 12:42:40.850963
8043 12:42:40.851023
8044 12:42:40.854209 [DramC_TX_OE_Calibration] TA2
8045 12:42:40.857542 Original DQ_B0 (3 6) =30, OEN = 27
8046 12:42:40.861296 Original DQ_B1 (3 6) =30, OEN = 27
8047 12:42:40.864042 24, 0x0, End_B0=24 End_B1=24
8048 12:42:40.864124 25, 0x0, End_B0=25 End_B1=25
8049 12:42:40.867724 26, 0x0, End_B0=26 End_B1=26
8050 12:42:40.870881 27, 0x0, End_B0=27 End_B1=27
8051 12:42:40.874600 28, 0x0, End_B0=28 End_B1=28
8052 12:42:40.874752 29, 0x0, End_B0=29 End_B1=29
8053 12:42:40.877555 30, 0x0, End_B0=30 End_B1=30
8054 12:42:40.880959 31, 0x4141, End_B0=30 End_B1=30
8055 12:42:40.884119 Byte0 end_step=30 best_step=27
8056 12:42:40.887639 Byte1 end_step=30 best_step=27
8057 12:42:40.890757 Byte0 TX OE(2T, 0.5T) = (3, 3)
8058 12:42:40.890829 Byte1 TX OE(2T, 0.5T) = (3, 3)
8059 12:42:40.890891
8060 12:42:40.894123
8061 12:42:40.901041 [DQSOSCAuto] RK0, (LSB)MR18= 0x1105, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 401 ps
8062 12:42:40.904224 CH0 RK0: MR19=303, MR18=1105
8063 12:42:40.910743 CH0_RK0: MR19=0x303, MR18=0x1105, DQSOSC=401, MR23=63, INC=22, DEC=15
8064 12:42:40.910876
8065 12:42:40.914737 ----->DramcWriteLeveling(PI) begin...
8066 12:42:40.914830 ==
8067 12:42:40.917442 Dram Type= 6, Freq= 0, CH_0, rank 1
8068 12:42:40.920900 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8069 12:42:40.920978 ==
8070 12:42:40.924525 Write leveling (Byte 0): 35 => 35
8071 12:42:40.928399 Write leveling (Byte 1): 28 => 28
8072 12:42:40.931040 DramcWriteLeveling(PI) end<-----
8073 12:42:40.931115
8074 12:42:40.931185 ==
8075 12:42:40.934507 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 12:42:40.937661 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 12:42:40.937732 ==
8078 12:42:40.940892 [Gating] SW mode calibration
8079 12:42:40.947632 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8080 12:42:40.953953 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8081 12:42:40.957864 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 12:42:40.960955 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8083 12:42:40.967695 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8084 12:42:40.971110 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8085 12:42:40.974391 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8086 12:42:40.981091 1 4 20 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
8087 12:42:40.984645 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
8088 12:42:40.987731 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8089 12:42:40.994577 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8090 12:42:40.997294 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8091 12:42:41.001106 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8092 12:42:41.003935 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
8093 12:42:41.010962 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8094 12:42:41.013973 1 5 20 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
8095 12:42:41.017663 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8096 12:42:41.024395 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8097 12:42:41.027666 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8098 12:42:41.030601 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8099 12:42:41.037584 1 6 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1)
8100 12:42:41.040985 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8101 12:42:41.044184 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8102 12:42:41.051041 1 6 20 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
8103 12:42:41.054362 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8104 12:42:41.057673 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8105 12:42:41.064780 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8106 12:42:41.067743 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8107 12:42:41.071328 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8108 12:42:41.077521 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8109 12:42:41.080544 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8110 12:42:41.084881 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8111 12:42:41.090650 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8112 12:42:41.094179 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 12:42:41.098093 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8114 12:42:41.101162 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8115 12:42:41.107481 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 12:42:41.110924 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8117 12:42:41.114722 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8118 12:42:41.121076 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8119 12:42:41.124365 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8120 12:42:41.127748 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8121 12:42:41.134378 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8122 12:42:41.137732 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8123 12:42:41.141020 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8124 12:42:41.148494 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8125 12:42:41.150915 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8126 12:42:41.154422 Total UI for P1: 0, mck2ui 16
8127 12:42:41.157692 best dqsien dly found for B0: ( 1, 9, 10)
8128 12:42:41.161091 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8129 12:42:41.167639 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8130 12:42:41.167723 Total UI for P1: 0, mck2ui 16
8131 12:42:41.171006 best dqsien dly found for B1: ( 1, 9, 20)
8132 12:42:41.177464 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8133 12:42:41.181237 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8134 12:42:41.181320
8135 12:42:41.184228 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8136 12:42:41.187521 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8137 12:42:41.190749 [Gating] SW calibration Done
8138 12:42:41.190832 ==
8139 12:42:41.194322 Dram Type= 6, Freq= 0, CH_0, rank 1
8140 12:42:41.197512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8141 12:42:41.197596 ==
8142 12:42:41.201212 RX Vref Scan: 0
8143 12:42:41.201294
8144 12:42:41.201359 RX Vref 0 -> 0, step: 1
8145 12:42:41.201421
8146 12:42:41.204104 RX Delay 0 -> 252, step: 8
8147 12:42:41.207761 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8148 12:42:41.211135 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8149 12:42:41.217962 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8150 12:42:41.221098 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8151 12:42:41.225055 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8152 12:42:41.227959 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8153 12:42:41.231331 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8154 12:42:41.238164 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8155 12:42:41.241136 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8156 12:42:41.244748 iDelay=200, Bit 9, Center 111 (48 ~ 175) 128
8157 12:42:41.248167 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8158 12:42:41.251194 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8159 12:42:41.257663 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8160 12:42:41.261213 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8161 12:42:41.264410 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8162 12:42:41.268390 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8163 12:42:41.268471 ==
8164 12:42:41.271475 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 12:42:41.277599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 12:42:41.277683 ==
8167 12:42:41.277747 DQS Delay:
8168 12:42:41.281474 DQS0 = 0, DQS1 = 0
8169 12:42:41.281559 DQM Delay:
8170 12:42:41.281622 DQM0 = 130, DQM1 = 124
8171 12:42:41.284100 DQ Delay:
8172 12:42:41.287668 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
8173 12:42:41.291602 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8174 12:42:41.294353 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
8175 12:42:41.298218 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8176 12:42:41.298330
8177 12:42:41.298449
8178 12:42:41.298510 ==
8179 12:42:41.301290 Dram Type= 6, Freq= 0, CH_0, rank 1
8180 12:42:41.304115 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8181 12:42:41.308080 ==
8182 12:42:41.308161
8183 12:42:41.308223
8184 12:42:41.308282 TX Vref Scan disable
8185 12:42:41.311374 == TX Byte 0 ==
8186 12:42:41.314774 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8187 12:42:41.317329 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8188 12:42:41.321225 == TX Byte 1 ==
8189 12:42:41.324341 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8190 12:42:41.327641 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8191 12:42:41.327722 ==
8192 12:42:41.331147 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 12:42:41.337511 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 12:42:41.337592 ==
8195 12:42:41.351252
8196 12:42:41.355325 TX Vref early break, caculate TX vref
8197 12:42:41.357944 TX Vref=16, minBit 4, minWin=22, winSum=376
8198 12:42:41.361408 TX Vref=18, minBit 1, minWin=23, winSum=385
8199 12:42:41.364551 TX Vref=20, minBit 0, minWin=24, winSum=397
8200 12:42:41.367871 TX Vref=22, minBit 3, minWin=24, winSum=399
8201 12:42:41.372070 TX Vref=24, minBit 4, minWin=24, winSum=411
8202 12:42:41.377845 TX Vref=26, minBit 2, minWin=25, winSum=419
8203 12:42:41.381527 TX Vref=28, minBit 2, minWin=25, winSum=421
8204 12:42:41.384827 TX Vref=30, minBit 0, minWin=25, winSum=418
8205 12:42:41.388361 TX Vref=32, minBit 0, minWin=25, winSum=416
8206 12:42:41.391801 TX Vref=34, minBit 0, minWin=24, winSum=408
8207 12:42:41.394439 TX Vref=36, minBit 4, minWin=23, winSum=397
8208 12:42:41.402028 [TxChooseVref] Worse bit 2, Min win 25, Win sum 421, Final Vref 28
8209 12:42:41.402110
8210 12:42:41.405283 Final TX Range 0 Vref 28
8211 12:42:41.405365
8212 12:42:41.405429 ==
8213 12:42:41.407843 Dram Type= 6, Freq= 0, CH_0, rank 1
8214 12:42:41.411170 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8215 12:42:41.411252 ==
8216 12:42:41.411316
8217 12:42:41.411374
8218 12:42:41.414430 TX Vref Scan disable
8219 12:42:41.421303 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8220 12:42:41.421384 == TX Byte 0 ==
8221 12:42:41.424422 u2DelayCellOfst[0]=14 cells (4 PI)
8222 12:42:41.427972 u2DelayCellOfst[1]=17 cells (5 PI)
8223 12:42:41.431697 u2DelayCellOfst[2]=10 cells (3 PI)
8224 12:42:41.434740 u2DelayCellOfst[3]=10 cells (3 PI)
8225 12:42:41.438119 u2DelayCellOfst[4]=10 cells (3 PI)
8226 12:42:41.441521 u2DelayCellOfst[5]=0 cells (0 PI)
8227 12:42:41.444882 u2DelayCellOfst[6]=17 cells (5 PI)
8228 12:42:41.448163 u2DelayCellOfst[7]=17 cells (5 PI)
8229 12:42:41.451662 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8230 12:42:41.454751 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8231 12:42:41.458060 == TX Byte 1 ==
8232 12:42:41.458141 u2DelayCellOfst[8]=0 cells (0 PI)
8233 12:42:41.461941 u2DelayCellOfst[9]=0 cells (0 PI)
8234 12:42:41.465186 u2DelayCellOfst[10]=10 cells (3 PI)
8235 12:42:41.467989 u2DelayCellOfst[11]=0 cells (0 PI)
8236 12:42:41.471896 u2DelayCellOfst[12]=14 cells (4 PI)
8237 12:42:41.474782 u2DelayCellOfst[13]=10 cells (3 PI)
8238 12:42:41.478263 u2DelayCellOfst[14]=17 cells (5 PI)
8239 12:42:41.481303 u2DelayCellOfst[15]=10 cells (3 PI)
8240 12:42:41.484600 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8241 12:42:41.491142 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8242 12:42:41.491223 DramC Write-DBI on
8243 12:42:41.491292 ==
8244 12:42:41.494596 Dram Type= 6, Freq= 0, CH_0, rank 1
8245 12:42:41.501492 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8246 12:42:41.501573 ==
8247 12:42:41.501637
8248 12:42:41.501695
8249 12:42:41.501752 TX Vref Scan disable
8250 12:42:41.504939 == TX Byte 0 ==
8251 12:42:41.508281 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8252 12:42:41.511643 == TX Byte 1 ==
8253 12:42:41.514951 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8254 12:42:41.518355 DramC Write-DBI off
8255 12:42:41.518445
8256 12:42:41.518509 [DATLAT]
8257 12:42:41.518580 Freq=1600, CH0 RK1
8258 12:42:41.518644
8259 12:42:41.521649 DATLAT Default: 0xf
8260 12:42:41.521729 0, 0xFFFF, sum = 0
8261 12:42:41.524911 1, 0xFFFF, sum = 0
8262 12:42:41.524993 2, 0xFFFF, sum = 0
8263 12:42:41.528219 3, 0xFFFF, sum = 0
8264 12:42:41.528301 4, 0xFFFF, sum = 0
8265 12:42:41.531737 5, 0xFFFF, sum = 0
8266 12:42:41.535580 6, 0xFFFF, sum = 0
8267 12:42:41.535661 7, 0xFFFF, sum = 0
8268 12:42:41.538357 8, 0xFFFF, sum = 0
8269 12:42:41.538481 9, 0xFFFF, sum = 0
8270 12:42:41.541618 10, 0xFFFF, sum = 0
8271 12:42:41.541748 11, 0xFFFF, sum = 0
8272 12:42:41.545146 12, 0xFFFF, sum = 0
8273 12:42:41.545228 13, 0xFFFF, sum = 0
8274 12:42:41.548518 14, 0x0, sum = 1
8275 12:42:41.548600 15, 0x0, sum = 2
8276 12:42:41.552097 16, 0x0, sum = 3
8277 12:42:41.552178 17, 0x0, sum = 4
8278 12:42:41.554868 best_step = 15
8279 12:42:41.554948
8280 12:42:41.555012 ==
8281 12:42:41.558894 Dram Type= 6, Freq= 0, CH_0, rank 1
8282 12:42:41.561981 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8283 12:42:41.562062 ==
8284 12:42:41.562125 RX Vref Scan: 0
8285 12:42:41.562185
8286 12:42:41.565524 RX Vref 0 -> 0, step: 1
8287 12:42:41.565605
8288 12:42:41.568617 RX Delay 3 -> 252, step: 4
8289 12:42:41.571836 iDelay=195, Bit 0, Center 128 (71 ~ 186) 116
8290 12:42:41.578801 iDelay=195, Bit 1, Center 130 (75 ~ 186) 112
8291 12:42:41.581952 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8292 12:42:41.585641 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8293 12:42:41.588843 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8294 12:42:41.591711 iDelay=195, Bit 5, Center 116 (63 ~ 170) 108
8295 12:42:41.595114 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8296 12:42:41.602014 iDelay=195, Bit 7, Center 136 (83 ~ 190) 108
8297 12:42:41.604908 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8298 12:42:41.608610 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8299 12:42:41.612029 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8300 12:42:41.615179 iDelay=195, Bit 11, Center 114 (63 ~ 166) 104
8301 12:42:41.622101 iDelay=195, Bit 12, Center 126 (75 ~ 178) 104
8302 12:42:41.625726 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
8303 12:42:41.628623 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8304 12:42:41.631642 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8305 12:42:41.631722 ==
8306 12:42:41.635513 Dram Type= 6, Freq= 0, CH_0, rank 1
8307 12:42:41.641988 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8308 12:42:41.642070 ==
8309 12:42:41.642133 DQS Delay:
8310 12:42:41.645120 DQS0 = 0, DQS1 = 0
8311 12:42:41.645200 DQM Delay:
8312 12:42:41.645264 DQM0 = 128, DQM1 = 122
8313 12:42:41.648651 DQ Delay:
8314 12:42:41.652260 DQ0 =128, DQ1 =130, DQ2 =124, DQ3 =126
8315 12:42:41.654966 DQ4 =128, DQ5 =116, DQ6 =138, DQ7 =136
8316 12:42:41.658827 DQ8 =114, DQ9 =110, DQ10 =122, DQ11 =114
8317 12:42:41.663016 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8318 12:42:41.663097
8319 12:42:41.663160
8320 12:42:41.663218
8321 12:42:41.665494 [DramC_TX_OE_Calibration] TA2
8322 12:42:41.668748 Original DQ_B0 (3 6) =30, OEN = 27
8323 12:42:41.672078 Original DQ_B1 (3 6) =30, OEN = 27
8324 12:42:41.674998 24, 0x0, End_B0=24 End_B1=24
8325 12:42:41.675079 25, 0x0, End_B0=25 End_B1=25
8326 12:42:41.678693 26, 0x0, End_B0=26 End_B1=26
8327 12:42:41.682078 27, 0x0, End_B0=27 End_B1=27
8328 12:42:41.684875 28, 0x0, End_B0=28 End_B1=28
8329 12:42:41.688191 29, 0x0, End_B0=29 End_B1=29
8330 12:42:41.688275 30, 0x0, End_B0=30 End_B1=30
8331 12:42:41.692067 31, 0x4141, End_B0=30 End_B1=30
8332 12:42:41.694923 Byte0 end_step=30 best_step=27
8333 12:42:41.698303 Byte1 end_step=30 best_step=27
8334 12:42:41.701579 Byte0 TX OE(2T, 0.5T) = (3, 3)
8335 12:42:41.704889 Byte1 TX OE(2T, 0.5T) = (3, 3)
8336 12:42:41.704970
8337 12:42:41.705033
8338 12:42:41.711746 [DQSOSCAuto] RK1, (LSB)MR18= 0x1609, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 398 ps
8339 12:42:41.715329 CH0 RK1: MR19=303, MR18=1609
8340 12:42:41.721693 CH0_RK1: MR19=0x303, MR18=0x1609, DQSOSC=398, MR23=63, INC=23, DEC=15
8341 12:42:41.724998 [RxdqsGatingPostProcess] freq 1600
8342 12:42:41.728426 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8343 12:42:41.731730 best DQS0 dly(2T, 0.5T) = (1, 1)
8344 12:42:41.734817 best DQS1 dly(2T, 0.5T) = (1, 1)
8345 12:42:41.738567 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8346 12:42:41.741732 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8347 12:42:41.745193 best DQS0 dly(2T, 0.5T) = (1, 1)
8348 12:42:41.748495 best DQS1 dly(2T, 0.5T) = (1, 1)
8349 12:42:41.751746 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8350 12:42:41.755343 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8351 12:42:41.755424 Pre-setting of DQS Precalculation
8352 12:42:41.761810 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8353 12:42:41.761891 ==
8354 12:42:41.765344 Dram Type= 6, Freq= 0, CH_1, rank 0
8355 12:42:41.769494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8356 12:42:41.769576 ==
8357 12:42:41.775073 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8358 12:42:41.778577 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8359 12:42:41.781743 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8360 12:42:41.788678 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8361 12:42:41.798354 [CA 0] Center 42 (14~71) winsize 58
8362 12:42:41.801479 [CA 1] Center 42 (13~71) winsize 59
8363 12:42:41.804646 [CA 2] Center 37 (8~66) winsize 59
8364 12:42:41.808333 [CA 3] Center 36 (7~65) winsize 59
8365 12:42:41.811515 [CA 4] Center 37 (8~67) winsize 60
8366 12:42:41.814801 [CA 5] Center 36 (6~66) winsize 61
8367 12:42:41.814881
8368 12:42:41.818009 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8369 12:42:41.818089
8370 12:42:41.821916 [CATrainingPosCal] consider 1 rank data
8371 12:42:41.824755 u2DelayCellTimex100 = 275/100 ps
8372 12:42:41.828241 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8373 12:42:41.834884 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8374 12:42:41.838578 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8375 12:42:41.841257 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8376 12:42:41.844782 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8377 12:42:41.848056 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8378 12:42:41.848137
8379 12:42:41.851408 CA PerBit enable=1, Macro0, CA PI delay=36
8380 12:42:41.851488
8381 12:42:41.855015 [CBTSetCACLKResult] CA Dly = 36
8382 12:42:41.855095 CS Dly: 9 (0~40)
8383 12:42:41.861664 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8384 12:42:41.864848 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8385 12:42:41.864932 ==
8386 12:42:41.868093 Dram Type= 6, Freq= 0, CH_1, rank 1
8387 12:42:41.871576 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8388 12:42:41.871657 ==
8389 12:42:41.877976 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8390 12:42:41.881707 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8391 12:42:41.888353 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8392 12:42:41.891136 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8393 12:42:41.901390 [CA 0] Center 43 (14~72) winsize 59
8394 12:42:41.904669 [CA 1] Center 43 (14~72) winsize 59
8395 12:42:41.908151 [CA 2] Center 38 (10~67) winsize 58
8396 12:42:41.911115 [CA 3] Center 37 (8~66) winsize 59
8397 12:42:41.914836 [CA 4] Center 38 (9~67) winsize 59
8398 12:42:41.917611 [CA 5] Center 37 (8~66) winsize 59
8399 12:42:41.917691
8400 12:42:41.921138 [CmdBusTrainingLP45] Vref(ca) range 0: 28
8401 12:42:41.921218
8402 12:42:41.924710 [CATrainingPosCal] consider 2 rank data
8403 12:42:41.928269 u2DelayCellTimex100 = 275/100 ps
8404 12:42:41.931605 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8405 12:42:41.938030 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8406 12:42:41.940936 CA2 delay=38 (10~66),Diff = 2 PI (7 cell)
8407 12:42:41.944396 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8408 12:42:41.947830 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8409 12:42:41.951154 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8410 12:42:41.951236
8411 12:42:41.954725 CA PerBit enable=1, Macro0, CA PI delay=36
8412 12:42:41.954806
8413 12:42:41.957526 [CBTSetCACLKResult] CA Dly = 36
8414 12:42:41.961406 CS Dly: 10 (0~43)
8415 12:42:41.964503 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8416 12:42:41.967846 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8417 12:42:41.967927
8418 12:42:41.970901 ----->DramcWriteLeveling(PI) begin...
8419 12:42:41.970988 ==
8420 12:42:41.974328 Dram Type= 6, Freq= 0, CH_1, rank 0
8421 12:42:41.977776 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8422 12:42:41.980867 ==
8423 12:42:41.980948 Write leveling (Byte 0): 26 => 26
8424 12:42:41.984959 Write leveling (Byte 1): 27 => 27
8425 12:42:41.988189 DramcWriteLeveling(PI) end<-----
8426 12:42:41.988295
8427 12:42:41.988361 ==
8428 12:42:41.991225 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 12:42:41.997753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 12:42:41.997841 ==
8431 12:42:42.001109 [Gating] SW mode calibration
8432 12:42:42.007657 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8433 12:42:42.010861 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8434 12:42:42.018228 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8435 12:42:42.020799 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8436 12:42:42.025213 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8437 12:42:42.027784 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8438 12:42:42.034322 1 4 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
8439 12:42:42.037477 1 4 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8440 12:42:42.041009 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8441 12:42:42.047499 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8442 12:42:42.051231 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8443 12:42:42.054423 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8444 12:42:42.060896 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8445 12:42:42.064681 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8446 12:42:42.067823 1 5 16 | B1->B0 | 2727 2e2e | 0 0 | (1 0) (0 1)
8447 12:42:42.074735 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8448 12:42:42.077510 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8449 12:42:42.081018 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8450 12:42:42.088159 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8451 12:42:42.091211 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8452 12:42:42.094814 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8453 12:42:42.101267 1 6 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8454 12:42:42.104697 1 6 16 | B1->B0 | 3939 2e2e | 0 0 | (0 0) (1 1)
8455 12:42:42.107430 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8456 12:42:42.111330 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8457 12:42:42.117616 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8458 12:42:42.121146 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8459 12:42:42.124932 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8460 12:42:42.131106 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8461 12:42:42.134418 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8462 12:42:42.138358 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8463 12:42:42.144687 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8464 12:42:42.148197 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8465 12:42:42.151185 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 12:42:42.158038 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8467 12:42:42.161120 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8468 12:42:42.164773 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8469 12:42:42.171467 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8470 12:42:42.174839 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8471 12:42:42.177993 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8472 12:42:42.185022 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8473 12:42:42.188020 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8474 12:42:42.191177 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8475 12:42:42.195086 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8476 12:42:42.202080 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8477 12:42:42.205405 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8478 12:42:42.208155 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8479 12:42:42.214909 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8480 12:42:42.214990 Total UI for P1: 0, mck2ui 16
8481 12:42:42.222331 best dqsien dly found for B0: ( 1, 9, 16)
8482 12:42:42.222456 Total UI for P1: 0, mck2ui 16
8483 12:42:42.228427 best dqsien dly found for B1: ( 1, 9, 16)
8484 12:42:42.231999 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8485 12:42:42.234967 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8486 12:42:42.235048
8487 12:42:42.238261 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8488 12:42:42.241739 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8489 12:42:42.245352 [Gating] SW calibration Done
8490 12:42:42.245432 ==
8491 12:42:42.248156 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 12:42:42.251345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 12:42:42.251427 ==
8494 12:42:42.254939 RX Vref Scan: 0
8495 12:42:42.255019
8496 12:42:42.255083 RX Vref 0 -> 0, step: 1
8497 12:42:42.255144
8498 12:42:42.258420 RX Delay 0 -> 252, step: 8
8499 12:42:42.261700 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8500 12:42:42.268146 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8501 12:42:42.271351 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8502 12:42:42.274981 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8503 12:42:42.278191 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8504 12:42:42.281370 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8505 12:42:42.284791 iDelay=208, Bit 6, Center 143 (96 ~ 191) 96
8506 12:42:42.291630 iDelay=208, Bit 7, Center 131 (80 ~ 183) 104
8507 12:42:42.294825 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8508 12:42:42.297982 iDelay=208, Bit 9, Center 115 (64 ~ 167) 104
8509 12:42:42.301407 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8510 12:42:42.307827 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8511 12:42:42.311271 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8512 12:42:42.314869 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8513 12:42:42.318105 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8514 12:42:42.321331 iDelay=208, Bit 15, Center 131 (80 ~ 183) 104
8515 12:42:42.321412 ==
8516 12:42:42.324960 Dram Type= 6, Freq= 0, CH_1, rank 0
8517 12:42:42.331583 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8518 12:42:42.331664 ==
8519 12:42:42.331728 DQS Delay:
8520 12:42:42.335015 DQS0 = 0, DQS1 = 0
8521 12:42:42.335095 DQM Delay:
8522 12:42:42.338220 DQM0 = 135, DQM1 = 127
8523 12:42:42.338300 DQ Delay:
8524 12:42:42.341243 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8525 12:42:42.344692 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =131
8526 12:42:42.348126 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8527 12:42:42.351286 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =131
8528 12:42:42.351367
8529 12:42:42.351430
8530 12:42:42.351488 ==
8531 12:42:42.354670 Dram Type= 6, Freq= 0, CH_1, rank 0
8532 12:42:42.361617 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8533 12:42:42.361699 ==
8534 12:42:42.361763
8535 12:42:42.361821
8536 12:42:42.361878 TX Vref Scan disable
8537 12:42:42.364670 == TX Byte 0 ==
8538 12:42:42.367663 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8539 12:42:42.371072 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8540 12:42:42.374745 == TX Byte 1 ==
8541 12:42:42.377949 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8542 12:42:42.381448 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8543 12:42:42.385101 ==
8544 12:42:42.388490 Dram Type= 6, Freq= 0, CH_1, rank 0
8545 12:42:42.391665 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8546 12:42:42.391746 ==
8547 12:42:42.403401
8548 12:42:42.406643 TX Vref early break, caculate TX vref
8549 12:42:42.410077 TX Vref=16, minBit 8, minWin=20, winSum=361
8550 12:42:42.413702 TX Vref=18, minBit 5, minWin=22, winSum=375
8551 12:42:42.416860 TX Vref=20, minBit 8, minWin=22, winSum=382
8552 12:42:42.420259 TX Vref=22, minBit 5, minWin=23, winSum=394
8553 12:42:42.423701 TX Vref=24, minBit 8, minWin=23, winSum=401
8554 12:42:42.430279 TX Vref=26, minBit 8, minWin=24, winSum=411
8555 12:42:42.433346 TX Vref=28, minBit 8, minWin=25, winSum=421
8556 12:42:42.436816 TX Vref=30, minBit 11, minWin=25, winSum=418
8557 12:42:42.440312 TX Vref=32, minBit 3, minWin=24, winSum=408
8558 12:42:42.443803 TX Vref=34, minBit 9, minWin=23, winSum=398
8559 12:42:42.450138 [TxChooseVref] Worse bit 8, Min win 25, Win sum 421, Final Vref 28
8560 12:42:42.450245
8561 12:42:42.453910 Final TX Range 0 Vref 28
8562 12:42:42.453991
8563 12:42:42.454053 ==
8564 12:42:42.456839 Dram Type= 6, Freq= 0, CH_1, rank 0
8565 12:42:42.459971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8566 12:42:42.460052 ==
8567 12:42:42.460116
8568 12:42:42.460175
8569 12:42:42.463886 TX Vref Scan disable
8570 12:42:42.466754 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8571 12:42:42.470205 == TX Byte 0 ==
8572 12:42:42.473580 u2DelayCellOfst[0]=17 cells (5 PI)
8573 12:42:42.477810 u2DelayCellOfst[1]=14 cells (4 PI)
8574 12:42:42.480315 u2DelayCellOfst[2]=0 cells (0 PI)
8575 12:42:42.483470 u2DelayCellOfst[3]=10 cells (3 PI)
8576 12:42:42.486965 u2DelayCellOfst[4]=14 cells (4 PI)
8577 12:42:42.490614 u2DelayCellOfst[5]=24 cells (7 PI)
8578 12:42:42.490694 u2DelayCellOfst[6]=21 cells (6 PI)
8579 12:42:42.493288 u2DelayCellOfst[7]=10 cells (3 PI)
8580 12:42:42.500147 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8581 12:42:42.503443 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8582 12:42:42.503524 == TX Byte 1 ==
8583 12:42:42.507273 u2DelayCellOfst[8]=0 cells (0 PI)
8584 12:42:42.510556 u2DelayCellOfst[9]=10 cells (3 PI)
8585 12:42:42.513704 u2DelayCellOfst[10]=14 cells (4 PI)
8586 12:42:42.517019 u2DelayCellOfst[11]=10 cells (3 PI)
8587 12:42:42.520267 u2DelayCellOfst[12]=17 cells (5 PI)
8588 12:42:42.523679 u2DelayCellOfst[13]=21 cells (6 PI)
8589 12:42:42.527281 u2DelayCellOfst[14]=21 cells (6 PI)
8590 12:42:42.530254 u2DelayCellOfst[15]=21 cells (6 PI)
8591 12:42:42.533631 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8592 12:42:42.540049 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8593 12:42:42.540130 DramC Write-DBI on
8594 12:42:42.540194 ==
8595 12:42:42.543382 Dram Type= 6, Freq= 0, CH_1, rank 0
8596 12:42:42.546703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8597 12:42:42.546787 ==
8598 12:42:42.546850
8599 12:42:42.550154
8600 12:42:42.550233 TX Vref Scan disable
8601 12:42:42.553502 == TX Byte 0 ==
8602 12:42:42.557231 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8603 12:42:42.560005 == TX Byte 1 ==
8604 12:42:42.563396 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8605 12:42:42.563477 DramC Write-DBI off
8606 12:42:42.563540
8607 12:42:42.567188 [DATLAT]
8608 12:42:42.567268 Freq=1600, CH1 RK0
8609 12:42:42.567332
8610 12:42:42.570145 DATLAT Default: 0xf
8611 12:42:42.570225 0, 0xFFFF, sum = 0
8612 12:42:42.573770 1, 0xFFFF, sum = 0
8613 12:42:42.573852 2, 0xFFFF, sum = 0
8614 12:42:42.576919 3, 0xFFFF, sum = 0
8615 12:42:42.577001 4, 0xFFFF, sum = 0
8616 12:42:42.580287 5, 0xFFFF, sum = 0
8617 12:42:42.580369 6, 0xFFFF, sum = 0
8618 12:42:42.583612 7, 0xFFFF, sum = 0
8619 12:42:42.583694 8, 0xFFFF, sum = 0
8620 12:42:42.586836 9, 0xFFFF, sum = 0
8621 12:42:42.586918 10, 0xFFFF, sum = 0
8622 12:42:42.589976 11, 0xFFFF, sum = 0
8623 12:42:42.593557 12, 0xFFFF, sum = 0
8624 12:42:42.593642 13, 0xFFFF, sum = 0
8625 12:42:42.597216 14, 0x0, sum = 1
8626 12:42:42.597298 15, 0x0, sum = 2
8627 12:42:42.599933 16, 0x0, sum = 3
8628 12:42:42.600014 17, 0x0, sum = 4
8629 12:42:42.600079 best_step = 15
8630 12:42:42.600138
8631 12:42:42.603756 ==
8632 12:42:42.606944 Dram Type= 6, Freq= 0, CH_1, rank 0
8633 12:42:42.610030 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8634 12:42:42.610110 ==
8635 12:42:42.610174 RX Vref Scan: 1
8636 12:42:42.610234
8637 12:42:42.613276 Set Vref Range= 24 -> 127
8638 12:42:42.613356
8639 12:42:42.616697 RX Vref 24 -> 127, step: 1
8640 12:42:42.616778
8641 12:42:42.621098 RX Delay 11 -> 252, step: 4
8642 12:42:42.621178
8643 12:42:42.623506 Set Vref, RX VrefLevel [Byte0]: 24
8644 12:42:42.627313 [Byte1]: 24
8645 12:42:42.627393
8646 12:42:42.630483 Set Vref, RX VrefLevel [Byte0]: 25
8647 12:42:42.634034 [Byte1]: 25
8648 12:42:42.634114
8649 12:42:42.637206 Set Vref, RX VrefLevel [Byte0]: 26
8650 12:42:42.640275 [Byte1]: 26
8651 12:42:42.640355
8652 12:42:42.643749 Set Vref, RX VrefLevel [Byte0]: 27
8653 12:42:42.647336 [Byte1]: 27
8654 12:42:42.650977
8655 12:42:42.651058 Set Vref, RX VrefLevel [Byte0]: 28
8656 12:42:42.654293 [Byte1]: 28
8657 12:42:42.659066
8658 12:42:42.659145 Set Vref, RX VrefLevel [Byte0]: 29
8659 12:42:42.662214 [Byte1]: 29
8660 12:42:42.666087
8661 12:42:42.666166 Set Vref, RX VrefLevel [Byte0]: 30
8662 12:42:42.669579 [Byte1]: 30
8663 12:42:42.673936
8664 12:42:42.674016 Set Vref, RX VrefLevel [Byte0]: 31
8665 12:42:42.677305 [Byte1]: 31
8666 12:42:42.681717
8667 12:42:42.681797 Set Vref, RX VrefLevel [Byte0]: 32
8668 12:42:42.684597 [Byte1]: 32
8669 12:42:42.688806
8670 12:42:42.688886 Set Vref, RX VrefLevel [Byte0]: 33
8671 12:42:42.692947 [Byte1]: 33
8672 12:42:42.696738
8673 12:42:42.696818 Set Vref, RX VrefLevel [Byte0]: 34
8674 12:42:42.700344 [Byte1]: 34
8675 12:42:42.704314
8676 12:42:42.704394 Set Vref, RX VrefLevel [Byte0]: 35
8677 12:42:42.708042 [Byte1]: 35
8678 12:42:42.711890
8679 12:42:42.711970 Set Vref, RX VrefLevel [Byte0]: 36
8680 12:42:42.715385 [Byte1]: 36
8681 12:42:42.720017
8682 12:42:42.720097 Set Vref, RX VrefLevel [Byte0]: 37
8683 12:42:42.722860 [Byte1]: 37
8684 12:42:42.727409
8685 12:42:42.727489 Set Vref, RX VrefLevel [Byte0]: 38
8686 12:42:42.730960 [Byte1]: 38
8687 12:42:42.735120
8688 12:42:42.735200 Set Vref, RX VrefLevel [Byte0]: 39
8689 12:42:42.738186 [Byte1]: 39
8690 12:42:42.742760
8691 12:42:42.742840 Set Vref, RX VrefLevel [Byte0]: 40
8692 12:42:42.746176 [Byte1]: 40
8693 12:42:42.750337
8694 12:42:42.750475 Set Vref, RX VrefLevel [Byte0]: 41
8695 12:42:42.753551 [Byte1]: 41
8696 12:42:42.757912
8697 12:42:42.757996 Set Vref, RX VrefLevel [Byte0]: 42
8698 12:42:42.761391 [Byte1]: 42
8699 12:42:42.765041
8700 12:42:42.765122 Set Vref, RX VrefLevel [Byte0]: 43
8701 12:42:42.768471 [Byte1]: 43
8702 12:42:42.773018
8703 12:42:42.773098 Set Vref, RX VrefLevel [Byte0]: 44
8704 12:42:42.776320 [Byte1]: 44
8705 12:42:42.780624
8706 12:42:42.780704 Set Vref, RX VrefLevel [Byte0]: 45
8707 12:42:42.784329 [Byte1]: 45
8708 12:42:42.788064
8709 12:42:42.788143 Set Vref, RX VrefLevel [Byte0]: 46
8710 12:42:42.791310 [Byte1]: 46
8711 12:42:42.795630
8712 12:42:42.795710 Set Vref, RX VrefLevel [Byte0]: 47
8713 12:42:42.799099 [Byte1]: 47
8714 12:42:42.803148
8715 12:42:42.803228 Set Vref, RX VrefLevel [Byte0]: 48
8716 12:42:42.806557 [Byte1]: 48
8717 12:42:42.811203
8718 12:42:42.811283 Set Vref, RX VrefLevel [Byte0]: 49
8719 12:42:42.814309 [Byte1]: 49
8720 12:42:42.818494
8721 12:42:42.818574 Set Vref, RX VrefLevel [Byte0]: 50
8722 12:42:42.822250 [Byte1]: 50
8723 12:42:42.826337
8724 12:42:42.826451 Set Vref, RX VrefLevel [Byte0]: 51
8725 12:42:42.829746 [Byte1]: 51
8726 12:42:42.833700
8727 12:42:42.833780 Set Vref, RX VrefLevel [Byte0]: 52
8728 12:42:42.837541 [Byte1]: 52
8729 12:42:42.841195
8730 12:42:42.841275 Set Vref, RX VrefLevel [Byte0]: 53
8731 12:42:42.844706 [Byte1]: 53
8732 12:42:42.848810
8733 12:42:42.848890 Set Vref, RX VrefLevel [Byte0]: 54
8734 12:42:42.852725 [Byte1]: 54
8735 12:42:42.856549
8736 12:42:42.856629 Set Vref, RX VrefLevel [Byte0]: 55
8737 12:42:42.860038 [Byte1]: 55
8738 12:42:42.864120
8739 12:42:42.864201 Set Vref, RX VrefLevel [Byte0]: 56
8740 12:42:42.867382 [Byte1]: 56
8741 12:42:42.871842
8742 12:42:42.871922 Set Vref, RX VrefLevel [Byte0]: 57
8743 12:42:42.875087 [Byte1]: 57
8744 12:42:42.879896
8745 12:42:42.879976 Set Vref, RX VrefLevel [Byte0]: 58
8746 12:42:42.883460 [Byte1]: 58
8747 12:42:42.887237
8748 12:42:42.887336 Set Vref, RX VrefLevel [Byte0]: 59
8749 12:42:42.890274 [Byte1]: 59
8750 12:42:42.894381
8751 12:42:42.894497 Set Vref, RX VrefLevel [Byte0]: 60
8752 12:42:42.897804 [Byte1]: 60
8753 12:42:42.901975
8754 12:42:42.902056 Set Vref, RX VrefLevel [Byte0]: 61
8755 12:42:42.905945 [Byte1]: 61
8756 12:42:42.910031
8757 12:42:42.910110 Set Vref, RX VrefLevel [Byte0]: 62
8758 12:42:42.913295 [Byte1]: 62
8759 12:42:42.917491
8760 12:42:42.917574 Set Vref, RX VrefLevel [Byte0]: 63
8761 12:42:42.920798 [Byte1]: 63
8762 12:42:42.925719
8763 12:42:42.925799 Set Vref, RX VrefLevel [Byte0]: 64
8764 12:42:42.928226 [Byte1]: 64
8765 12:42:42.932971
8766 12:42:42.933051 Set Vref, RX VrefLevel [Byte0]: 65
8767 12:42:42.935768 [Byte1]: 65
8768 12:42:42.940559
8769 12:42:42.940639 Set Vref, RX VrefLevel [Byte0]: 66
8770 12:42:42.943561 [Byte1]: 66
8771 12:42:42.947763
8772 12:42:42.947843 Set Vref, RX VrefLevel [Byte0]: 67
8773 12:42:42.951450 [Byte1]: 67
8774 12:42:42.955949
8775 12:42:42.956029 Set Vref, RX VrefLevel [Byte0]: 68
8776 12:42:42.958970 [Byte1]: 68
8777 12:42:42.963239
8778 12:42:42.963319 Set Vref, RX VrefLevel [Byte0]: 69
8779 12:42:42.966838 [Byte1]: 69
8780 12:42:42.970849
8781 12:42:42.970929 Set Vref, RX VrefLevel [Byte0]: 70
8782 12:42:42.974371 [Byte1]: 70
8783 12:42:42.978323
8784 12:42:42.978463 Set Vref, RX VrefLevel [Byte0]: 71
8785 12:42:42.981432 [Byte1]: 71
8786 12:42:42.985973
8787 12:42:42.986054 Set Vref, RX VrefLevel [Byte0]: 72
8788 12:42:42.989430 [Byte1]: 72
8789 12:42:42.993652
8790 12:42:42.993732 Set Vref, RX VrefLevel [Byte0]: 73
8791 12:42:42.996668 [Byte1]: 73
8792 12:42:43.001647
8793 12:42:43.001726 Set Vref, RX VrefLevel [Byte0]: 74
8794 12:42:43.004457 [Byte1]: 74
8795 12:42:43.008611
8796 12:42:43.008691 Set Vref, RX VrefLevel [Byte0]: 75
8797 12:42:43.011944 [Byte1]: 75
8798 12:42:43.016529
8799 12:42:43.016609 Set Vref, RX VrefLevel [Byte0]: 76
8800 12:42:43.020031 [Byte1]: 76
8801 12:42:43.024028
8802 12:42:43.024108 Set Vref, RX VrefLevel [Byte0]: 77
8803 12:42:43.027607 [Byte1]: 77
8804 12:42:43.031935
8805 12:42:43.032014 Set Vref, RX VrefLevel [Byte0]: 78
8806 12:42:43.035919 [Byte1]: 78
8807 12:42:43.039557
8808 12:42:43.039638 Final RX Vref Byte 0 = 61 to rank0
8809 12:42:43.042409 Final RX Vref Byte 1 = 54 to rank0
8810 12:42:43.046019 Final RX Vref Byte 0 = 61 to rank1
8811 12:42:43.049511 Final RX Vref Byte 1 = 54 to rank1==
8812 12:42:43.053278 Dram Type= 6, Freq= 0, CH_1, rank 0
8813 12:42:43.059232 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8814 12:42:43.059315 ==
8815 12:42:43.059379 DQS Delay:
8816 12:42:43.059438 DQS0 = 0, DQS1 = 0
8817 12:42:43.062329 DQM Delay:
8818 12:42:43.062465 DQM0 = 131, DQM1 = 124
8819 12:42:43.066330 DQ Delay:
8820 12:42:43.069830 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =128
8821 12:42:43.072987 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8822 12:42:43.076496 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
8823 12:42:43.079168 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8824 12:42:43.079249
8825 12:42:43.079337
8826 12:42:43.079401
8827 12:42:43.082934 [DramC_TX_OE_Calibration] TA2
8828 12:42:43.085955 Original DQ_B0 (3 6) =30, OEN = 27
8829 12:42:43.089220 Original DQ_B1 (3 6) =30, OEN = 27
8830 12:42:43.092756 24, 0x0, End_B0=24 End_B1=24
8831 12:42:43.092838 25, 0x0, End_B0=25 End_B1=25
8832 12:42:43.095988 26, 0x0, End_B0=26 End_B1=26
8833 12:42:43.099355 27, 0x0, End_B0=27 End_B1=27
8834 12:42:43.102370 28, 0x0, End_B0=28 End_B1=28
8835 12:42:43.102495 29, 0x0, End_B0=29 End_B1=29
8836 12:42:43.106016 30, 0x0, End_B0=30 End_B1=30
8837 12:42:43.109145 31, 0x4141, End_B0=30 End_B1=30
8838 12:42:43.113105 Byte0 end_step=30 best_step=27
8839 12:42:43.115914 Byte1 end_step=30 best_step=27
8840 12:42:43.119442 Byte0 TX OE(2T, 0.5T) = (3, 3)
8841 12:42:43.119522 Byte1 TX OE(2T, 0.5T) = (3, 3)
8842 12:42:43.119586
8843 12:42:43.122382
8844 12:42:43.129352 [DQSOSCAuto] RK0, (LSB)MR18= 0x14ff, (MSB)MR19= 0x302, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
8845 12:42:43.132691 CH1 RK0: MR19=302, MR18=14FF
8846 12:42:43.139375 CH1_RK0: MR19=0x302, MR18=0x14FF, DQSOSC=399, MR23=63, INC=23, DEC=15
8847 12:42:43.139456
8848 12:42:43.142450 ----->DramcWriteLeveling(PI) begin...
8849 12:42:43.142532 ==
8850 12:42:43.146255 Dram Type= 6, Freq= 0, CH_1, rank 1
8851 12:42:43.149223 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8852 12:42:43.149305 ==
8853 12:42:43.152822 Write leveling (Byte 0): 25 => 25
8854 12:42:43.155792 Write leveling (Byte 1): 26 => 26
8855 12:42:43.159155 DramcWriteLeveling(PI) end<-----
8856 12:42:43.159236
8857 12:42:43.159300 ==
8858 12:42:43.162739 Dram Type= 6, Freq= 0, CH_1, rank 1
8859 12:42:43.166278 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8860 12:42:43.166384 ==
8861 12:42:43.169230 [Gating] SW mode calibration
8862 12:42:43.176068 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8863 12:42:43.182832 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8864 12:42:43.186295 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8865 12:42:43.189123 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8866 12:42:43.195939 1 4 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8867 12:42:43.199394 1 4 12 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
8868 12:42:43.203185 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8869 12:42:43.209474 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8870 12:42:43.212586 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8871 12:42:43.215641 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8872 12:42:43.222908 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8873 12:42:43.225676 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8874 12:42:43.229396 1 5 8 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
8875 12:42:43.232636 1 5 12 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
8876 12:42:43.238884 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8877 12:42:43.242675 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8878 12:42:43.246210 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8879 12:42:43.252431 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8880 12:42:43.255948 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8881 12:42:43.259770 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8882 12:42:43.266240 1 6 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8883 12:42:43.268970 1 6 12 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
8884 12:42:43.272440 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8885 12:42:43.279601 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8886 12:42:43.282507 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8887 12:42:43.286197 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8888 12:42:43.292366 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8889 12:42:43.296205 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8890 12:42:43.299005 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8891 12:42:43.305886 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8892 12:42:43.309458 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8893 12:42:43.312539 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8894 12:42:43.319121 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8895 12:42:43.322556 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8896 12:42:43.325586 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8897 12:42:43.329373 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8898 12:42:43.336287 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8899 12:42:43.339492 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8900 12:42:43.342313 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8901 12:42:43.349258 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8902 12:42:43.352505 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8903 12:42:43.355991 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8904 12:42:43.362610 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8905 12:42:43.365929 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8906 12:42:43.369326 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8907 12:42:43.376001 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8908 12:42:43.376082 Total UI for P1: 0, mck2ui 16
8909 12:42:43.382472 best dqsien dly found for B0: ( 1, 9, 8)
8910 12:42:43.385948 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8911 12:42:43.389150 Total UI for P1: 0, mck2ui 16
8912 12:42:43.392593 best dqsien dly found for B1: ( 1, 9, 12)
8913 12:42:43.395762 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8914 12:42:43.399187 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8915 12:42:43.399268
8916 12:42:43.402851 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8917 12:42:43.406059 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8918 12:42:43.409096 [Gating] SW calibration Done
8919 12:42:43.409176 ==
8920 12:42:43.413129 Dram Type= 6, Freq= 0, CH_1, rank 1
8921 12:42:43.415892 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8922 12:42:43.415974 ==
8923 12:42:43.419425 RX Vref Scan: 0
8924 12:42:43.419505
8925 12:42:43.422989 RX Vref 0 -> 0, step: 1
8926 12:42:43.423069
8927 12:42:43.423132 RX Delay 0 -> 252, step: 8
8928 12:42:43.429807 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8929 12:42:43.432520 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8930 12:42:43.436034 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8931 12:42:43.439499 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8932 12:42:43.442776 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8933 12:42:43.449610 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8934 12:42:43.452527 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8935 12:42:43.456084 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8936 12:42:43.459292 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8937 12:42:43.462443 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8938 12:42:43.469279 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8939 12:42:43.473175 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8940 12:42:43.476040 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8941 12:42:43.479102 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8942 12:42:43.482668 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8943 12:42:43.489078 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8944 12:42:43.489164 ==
8945 12:42:43.492364 Dram Type= 6, Freq= 0, CH_1, rank 1
8946 12:42:43.496226 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8947 12:42:43.496311 ==
8948 12:42:43.496374 DQS Delay:
8949 12:42:43.499296 DQS0 = 0, DQS1 = 0
8950 12:42:43.499389 DQM Delay:
8951 12:42:43.502804 DQM0 = 133, DQM1 = 127
8952 12:42:43.502885 DQ Delay:
8953 12:42:43.506204 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =135
8954 12:42:43.509524 DQ4 =135, DQ5 =147, DQ6 =139, DQ7 =127
8955 12:42:43.512496 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8956 12:42:43.516444 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8957 12:42:43.516550
8958 12:42:43.516645
8959 12:42:43.518951 ==
8960 12:42:43.522354 Dram Type= 6, Freq= 0, CH_1, rank 1
8961 12:42:43.526383 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8962 12:42:43.526502 ==
8963 12:42:43.526566
8964 12:42:43.526625
8965 12:42:43.529226 TX Vref Scan disable
8966 12:42:43.529333 == TX Byte 0 ==
8967 12:42:43.532417 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8968 12:42:43.538964 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8969 12:42:43.539061 == TX Byte 1 ==
8970 12:42:43.542651 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8971 12:42:43.549194 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8972 12:42:43.549275 ==
8973 12:42:43.553296 Dram Type= 6, Freq= 0, CH_1, rank 1
8974 12:42:43.555515 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8975 12:42:43.555596 ==
8976 12:42:43.568745
8977 12:42:43.571634 TX Vref early break, caculate TX vref
8978 12:42:43.574919 TX Vref=16, minBit 5, minWin=23, winSum=381
8979 12:42:43.579023 TX Vref=18, minBit 8, minWin=23, winSum=393
8980 12:42:43.581729 TX Vref=20, minBit 5, minWin=24, winSum=400
8981 12:42:43.585002 TX Vref=22, minBit 11, minWin=24, winSum=411
8982 12:42:43.588812 TX Vref=24, minBit 9, minWin=24, winSum=417
8983 12:42:43.594966 TX Vref=26, minBit 6, minWin=25, winSum=424
8984 12:42:43.598406 TX Vref=28, minBit 1, minWin=26, winSum=429
8985 12:42:43.601771 TX Vref=30, minBit 5, minWin=25, winSum=423
8986 12:42:43.605020 TX Vref=32, minBit 0, minWin=25, winSum=417
8987 12:42:43.608256 TX Vref=34, minBit 0, minWin=24, winSum=406
8988 12:42:43.615228 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 28
8989 12:42:43.615310
8990 12:42:43.618194 Final TX Range 0 Vref 28
8991 12:42:43.618300
8992 12:42:43.618391 ==
8993 12:42:43.621844 Dram Type= 6, Freq= 0, CH_1, rank 1
8994 12:42:43.624842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8995 12:42:43.624923 ==
8996 12:42:43.624986
8997 12:42:43.625044
8998 12:42:43.628377 TX Vref Scan disable
8999 12:42:43.635266 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
9000 12:42:43.635413 == TX Byte 0 ==
9001 12:42:43.638178 u2DelayCellOfst[0]=17 cells (5 PI)
9002 12:42:43.641815 u2DelayCellOfst[1]=10 cells (3 PI)
9003 12:42:43.644938 u2DelayCellOfst[2]=0 cells (0 PI)
9004 12:42:43.648021 u2DelayCellOfst[3]=7 cells (2 PI)
9005 12:42:43.652016 u2DelayCellOfst[4]=10 cells (3 PI)
9006 12:42:43.654669 u2DelayCellOfst[5]=17 cells (5 PI)
9007 12:42:43.658060 u2DelayCellOfst[6]=17 cells (5 PI)
9008 12:42:43.658188 u2DelayCellOfst[7]=7 cells (2 PI)
9009 12:42:43.665151 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9010 12:42:43.668198 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9011 12:42:43.668368 == TX Byte 1 ==
9012 12:42:43.671239 u2DelayCellOfst[8]=0 cells (0 PI)
9013 12:42:43.674651 u2DelayCellOfst[9]=3 cells (1 PI)
9014 12:42:43.678146 u2DelayCellOfst[10]=10 cells (3 PI)
9015 12:42:43.681574 u2DelayCellOfst[11]=3 cells (1 PI)
9016 12:42:43.684864 u2DelayCellOfst[12]=14 cells (4 PI)
9017 12:42:43.688295 u2DelayCellOfst[13]=14 cells (4 PI)
9018 12:42:43.691440 u2DelayCellOfst[14]=17 cells (5 PI)
9019 12:42:43.695364 u2DelayCellOfst[15]=14 cells (4 PI)
9020 12:42:43.697899 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9021 12:42:43.704696 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9022 12:42:43.704799 DramC Write-DBI on
9023 12:42:43.704865 ==
9024 12:42:43.707928 Dram Type= 6, Freq= 0, CH_1, rank 1
9025 12:42:43.711959 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9026 12:42:43.712040 ==
9027 12:42:43.714604
9028 12:42:43.714684
9029 12:42:43.714747 TX Vref Scan disable
9030 12:42:43.717704 == TX Byte 0 ==
9031 12:42:43.721407 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9032 12:42:43.724557 == TX Byte 1 ==
9033 12:42:43.728287 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9034 12:42:43.728369 DramC Write-DBI off
9035 12:42:43.731672
9036 12:42:43.731754 [DATLAT]
9037 12:42:43.731819 Freq=1600, CH1 RK1
9038 12:42:43.731880
9039 12:42:43.734675 DATLAT Default: 0xf
9040 12:42:43.734757 0, 0xFFFF, sum = 0
9041 12:42:43.737882 1, 0xFFFF, sum = 0
9042 12:42:43.737965 2, 0xFFFF, sum = 0
9043 12:42:43.741623 3, 0xFFFF, sum = 0
9044 12:42:43.741706 4, 0xFFFF, sum = 0
9045 12:42:43.744513 5, 0xFFFF, sum = 0
9046 12:42:43.748638 6, 0xFFFF, sum = 0
9047 12:42:43.748722 7, 0xFFFF, sum = 0
9048 12:42:43.751204 8, 0xFFFF, sum = 0
9049 12:42:43.751287 9, 0xFFFF, sum = 0
9050 12:42:43.754414 10, 0xFFFF, sum = 0
9051 12:42:43.754494 11, 0xFFFF, sum = 0
9052 12:42:43.758884 12, 0xFFFF, sum = 0
9053 12:42:43.758967 13, 0xFFFF, sum = 0
9054 12:42:43.761190 14, 0x0, sum = 1
9055 12:42:43.761273 15, 0x0, sum = 2
9056 12:42:43.764877 16, 0x0, sum = 3
9057 12:42:43.764987 17, 0x0, sum = 4
9058 12:42:43.765082 best_step = 15
9059 12:42:43.768437
9060 12:42:43.768520 ==
9061 12:42:43.771604 Dram Type= 6, Freq= 0, CH_1, rank 1
9062 12:42:43.774692 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9063 12:42:43.774775 ==
9064 12:42:43.774840 RX Vref Scan: 0
9065 12:42:43.774901
9066 12:42:43.778321 RX Vref 0 -> 0, step: 1
9067 12:42:43.778439
9068 12:42:43.781821 RX Delay 11 -> 252, step: 4
9069 12:42:43.784899 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
9070 12:42:43.788292 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
9071 12:42:43.794541 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
9072 12:42:43.797978 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
9073 12:42:43.801367 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
9074 12:42:43.804999 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
9075 12:42:43.808823 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
9076 12:42:43.814760 iDelay=191, Bit 7, Center 126 (75 ~ 178) 104
9077 12:42:43.818430 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
9078 12:42:43.821816 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
9079 12:42:43.825008 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
9080 12:42:43.828752 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
9081 12:42:43.834667 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
9082 12:42:43.838637 iDelay=191, Bit 13, Center 136 (83 ~ 190) 108
9083 12:42:43.841820 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
9084 12:42:43.844997 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
9085 12:42:43.845098 ==
9086 12:42:43.848343 Dram Type= 6, Freq= 0, CH_1, rank 1
9087 12:42:43.851429 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9088 12:42:43.855015 ==
9089 12:42:43.855093 DQS Delay:
9090 12:42:43.855156 DQS0 = 0, DQS1 = 0
9091 12:42:43.858301 DQM Delay:
9092 12:42:43.858374 DQM0 = 129, DQM1 = 126
9093 12:42:43.861658 DQ Delay:
9094 12:42:43.864998 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =126
9095 12:42:43.868063 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =126
9096 12:42:43.871433 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9097 12:42:43.875227 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =134
9098 12:42:43.875301
9099 12:42:43.875362
9100 12:42:43.875420
9101 12:42:43.878135 [DramC_TX_OE_Calibration] TA2
9102 12:42:43.881797 Original DQ_B0 (3 6) =30, OEN = 27
9103 12:42:43.885558 Original DQ_B1 (3 6) =30, OEN = 27
9104 12:42:43.888419 24, 0x0, End_B0=24 End_B1=24
9105 12:42:43.888497 25, 0x0, End_B0=25 End_B1=25
9106 12:42:43.891509 26, 0x0, End_B0=26 End_B1=26
9107 12:42:43.895215 27, 0x0, End_B0=27 End_B1=27
9108 12:42:43.898159 28, 0x0, End_B0=28 End_B1=28
9109 12:42:43.898234 29, 0x0, End_B0=29 End_B1=29
9110 12:42:43.901425 30, 0x0, End_B0=30 End_B1=30
9111 12:42:43.905365 31, 0x4141, End_B0=30 End_B1=30
9112 12:42:43.907910 Byte0 end_step=30 best_step=27
9113 12:42:43.911435 Byte1 end_step=30 best_step=27
9114 12:42:43.915144 Byte0 TX OE(2T, 0.5T) = (3, 3)
9115 12:42:43.915218 Byte1 TX OE(2T, 0.5T) = (3, 3)
9116 12:42:43.915280
9117 12:42:43.915339
9118 12:42:43.925409 [DQSOSCAuto] RK1, (LSB)MR18= 0x1117, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
9119 12:42:43.928750 CH1 RK1: MR19=303, MR18=1117
9120 12:42:43.931959 CH1_RK1: MR19=0x303, MR18=0x1117, DQSOSC=398, MR23=63, INC=23, DEC=15
9121 12:42:43.935059 [RxdqsGatingPostProcess] freq 1600
9122 12:42:43.942036 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9123 12:42:43.944963 best DQS0 dly(2T, 0.5T) = (1, 1)
9124 12:42:43.948255 best DQS1 dly(2T, 0.5T) = (1, 1)
9125 12:42:43.951463 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9126 12:42:43.955335 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9127 12:42:43.958076 best DQS0 dly(2T, 0.5T) = (1, 1)
9128 12:42:43.961670 best DQS1 dly(2T, 0.5T) = (1, 1)
9129 12:42:43.964965 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9130 12:42:43.965046 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9131 12:42:43.968452 Pre-setting of DQS Precalculation
9132 12:42:43.975242 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9133 12:42:43.981895 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9134 12:42:43.989113 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9135 12:42:43.989206
9136 12:42:43.989269
9137 12:42:43.991713 [Calibration Summary] 3200 Mbps
9138 12:42:43.991783 CH 0, Rank 0
9139 12:42:43.995166 SW Impedance : PASS
9140 12:42:43.998408 DUTY Scan : NO K
9141 12:42:43.998490 ZQ Calibration : PASS
9142 12:42:44.002346 Jitter Meter : NO K
9143 12:42:44.004798 CBT Training : PASS
9144 12:42:44.004888 Write leveling : PASS
9145 12:42:44.008356 RX DQS gating : PASS
9146 12:42:44.011939 RX DQ/DQS(RDDQC) : PASS
9147 12:42:44.012036 TX DQ/DQS : PASS
9148 12:42:44.015069 RX DATLAT : PASS
9149 12:42:44.018738 RX DQ/DQS(Engine): PASS
9150 12:42:44.018818 TX OE : PASS
9151 12:42:44.018899 All Pass.
9152 12:42:44.021951
9153 12:42:44.022064 CH 0, Rank 1
9154 12:42:44.024981 SW Impedance : PASS
9155 12:42:44.025175 DUTY Scan : NO K
9156 12:42:44.028492 ZQ Calibration : PASS
9157 12:42:44.028598 Jitter Meter : NO K
9158 12:42:44.031802 CBT Training : PASS
9159 12:42:44.035215 Write leveling : PASS
9160 12:42:44.035296 RX DQS gating : PASS
9161 12:42:44.038552 RX DQ/DQS(RDDQC) : PASS
9162 12:42:44.041919 TX DQ/DQS : PASS
9163 12:42:44.042024 RX DATLAT : PASS
9164 12:42:44.045326 RX DQ/DQS(Engine): PASS
9165 12:42:44.048395 TX OE : PASS
9166 12:42:44.048485 All Pass.
9167 12:42:44.048546
9168 12:42:44.048604 CH 1, Rank 0
9169 12:42:44.051717 SW Impedance : PASS
9170 12:42:44.055309 DUTY Scan : NO K
9171 12:42:44.055411 ZQ Calibration : PASS
9172 12:42:44.058666 Jitter Meter : NO K
9173 12:42:44.061897 CBT Training : PASS
9174 12:42:44.061972 Write leveling : PASS
9175 12:42:44.064865 RX DQS gating : PASS
9176 12:42:44.068623 RX DQ/DQS(RDDQC) : PASS
9177 12:42:44.068700 TX DQ/DQS : PASS
9178 12:42:44.071923 RX DATLAT : PASS
9179 12:42:44.072000 RX DQ/DQS(Engine): PASS
9180 12:42:44.075445 TX OE : PASS
9181 12:42:44.075528 All Pass.
9182 12:42:44.075590
9183 12:42:44.078404 CH 1, Rank 1
9184 12:42:44.078494 SW Impedance : PASS
9185 12:42:44.081857 DUTY Scan : NO K
9186 12:42:44.084789 ZQ Calibration : PASS
9187 12:42:44.084884 Jitter Meter : NO K
9188 12:42:44.088542 CBT Training : PASS
9189 12:42:44.091594 Write leveling : PASS
9190 12:42:44.091673 RX DQS gating : PASS
9191 12:42:44.095041 RX DQ/DQS(RDDQC) : PASS
9192 12:42:44.098213 TX DQ/DQS : PASS
9193 12:42:44.098287 RX DATLAT : PASS
9194 12:42:44.101478 RX DQ/DQS(Engine): PASS
9195 12:42:44.104734 TX OE : PASS
9196 12:42:44.104815 All Pass.
9197 12:42:44.104901
9198 12:42:44.108040 DramC Write-DBI on
9199 12:42:44.108116 PER_BANK_REFRESH: Hybrid Mode
9200 12:42:44.111508 TX_TRACKING: ON
9201 12:42:44.121310 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9202 12:42:44.127849 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9203 12:42:44.134779 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9204 12:42:44.138080 [FAST_K] Save calibration result to emmc
9205 12:42:44.141190 sync common calibartion params.
9206 12:42:44.145374 sync cbt_mode0:1, 1:1
9207 12:42:44.145482 dram_init: ddr_geometry: 2
9208 12:42:44.147955 dram_init: ddr_geometry: 2
9209 12:42:44.151471 dram_init: ddr_geometry: 2
9210 12:42:44.151552 0:dram_rank_size:100000000
9211 12:42:44.154535 1:dram_rank_size:100000000
9212 12:42:44.161427 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9213 12:42:44.164837 DFS_SHUFFLE_HW_MODE: ON
9214 12:42:44.168024 dramc_set_vcore_voltage set vcore to 725000
9215 12:42:44.168105 Read voltage for 1600, 0
9216 12:42:44.171670 Vio18 = 0
9217 12:42:44.171751 Vcore = 725000
9218 12:42:44.171832 Vdram = 0
9219 12:42:44.174826 Vddq = 0
9220 12:42:44.174920 Vmddr = 0
9221 12:42:44.177984 switch to 3200 Mbps bootup
9222 12:42:44.178067 [DramcRunTimeConfig]
9223 12:42:44.178132 PHYPLL
9224 12:42:44.181416 DPM_CONTROL_AFTERK: ON
9225 12:42:44.184853 PER_BANK_REFRESH: ON
9226 12:42:44.184934 REFRESH_OVERHEAD_REDUCTION: ON
9227 12:42:44.188149 CMD_PICG_NEW_MODE: OFF
9228 12:42:44.191337 XRTWTW_NEW_MODE: ON
9229 12:42:44.191423 XRTRTR_NEW_MODE: ON
9230 12:42:44.194954 TX_TRACKING: ON
9231 12:42:44.195066 RDSEL_TRACKING: OFF
9232 12:42:44.197985 DQS Precalculation for DVFS: ON
9233 12:42:44.198070 RX_TRACKING: OFF
9234 12:42:44.201339 HW_GATING DBG: ON
9235 12:42:44.201445 ZQCS_ENABLE_LP4: ON
9236 12:42:44.204847 RX_PICG_NEW_MODE: ON
9237 12:42:44.208370 TX_PICG_NEW_MODE: ON
9238 12:42:44.208444 ENABLE_RX_DCM_DPHY: ON
9239 12:42:44.211523 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9240 12:42:44.214651 DUMMY_READ_FOR_TRACKING: OFF
9241 12:42:44.218297 !!! SPM_CONTROL_AFTERK: OFF
9242 12:42:44.218382 !!! SPM could not control APHY
9243 12:42:44.221239 IMPEDANCE_TRACKING: ON
9244 12:42:44.224485 TEMP_SENSOR: ON
9245 12:42:44.224560 HW_SAVE_FOR_SR: OFF
9246 12:42:44.227909 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9247 12:42:44.231896 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9248 12:42:44.234844 Read ODT Tracking: ON
9249 12:42:44.234922 Refresh Rate DeBounce: ON
9250 12:42:44.238005 DFS_NO_QUEUE_FLUSH: ON
9251 12:42:44.241828 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9252 12:42:44.244608 ENABLE_DFS_RUNTIME_MRW: OFF
9253 12:42:44.244694 DDR_RESERVE_NEW_MODE: ON
9254 12:42:44.248025 MR_CBT_SWITCH_FREQ: ON
9255 12:42:44.251185 =========================
9256 12:42:44.269303 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9257 12:42:44.272669 dram_init: ddr_geometry: 2
9258 12:42:44.291132 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9259 12:42:44.294286 dram_init: dram init end (result: 0)
9260 12:42:44.301294 DRAM-K: Full calibration passed in 24626 msecs
9261 12:42:44.304150 MRC: failed to locate region type 0.
9262 12:42:44.304243 DRAM rank0 size:0x100000000,
9263 12:42:44.308010 DRAM rank1 size=0x100000000
9264 12:42:44.317458 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9265 12:42:44.324544 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9266 12:42:44.331126 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9267 12:42:44.337324 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9268 12:42:44.341325 DRAM rank0 size:0x100000000,
9269 12:42:44.344065 DRAM rank1 size=0x100000000
9270 12:42:44.344172 CBMEM:
9271 12:42:44.347800 IMD: root @ 0xfffff000 254 entries.
9272 12:42:44.350695 IMD: root @ 0xffffec00 62 entries.
9273 12:42:44.354640 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9274 12:42:44.357457 WARNING: RO_VPD is uninitialized or empty.
9275 12:42:44.363982 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9276 12:42:44.370564 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9277 12:42:44.383480 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9278 12:42:44.394829 BS: romstage times (exec / console): total (unknown) / 24121 ms
9279 12:42:44.394913
9280 12:42:44.394982
9281 12:42:44.405252 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9282 12:42:44.408153 ARM64: Exception handlers installed.
9283 12:42:44.412069 ARM64: Testing exception
9284 12:42:44.415234 ARM64: Done test exception
9285 12:42:44.415309 Enumerating buses...
9286 12:42:44.418614 Show all devs... Before device enumeration.
9287 12:42:44.422160 Root Device: enabled 1
9288 12:42:44.425336 CPU_CLUSTER: 0: enabled 1
9289 12:42:44.425450 CPU: 00: enabled 1
9290 12:42:44.428565 Compare with tree...
9291 12:42:44.428670 Root Device: enabled 1
9292 12:42:44.432358 CPU_CLUSTER: 0: enabled 1
9293 12:42:44.434752 CPU: 00: enabled 1
9294 12:42:44.434831 Root Device scanning...
9295 12:42:44.438207 scan_static_bus for Root Device
9296 12:42:44.441599 CPU_CLUSTER: 0 enabled
9297 12:42:44.445182 scan_static_bus for Root Device done
9298 12:42:44.447989 scan_bus: bus Root Device finished in 8 msecs
9299 12:42:44.448106 done
9300 12:42:44.454867 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9301 12:42:44.458274 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9302 12:42:44.464829 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9303 12:42:44.468259 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9304 12:42:44.471562 Allocating resources...
9305 12:42:44.474477 Reading resources...
9306 12:42:44.478365 Root Device read_resources bus 0 link: 0
9307 12:42:44.478451 DRAM rank0 size:0x100000000,
9308 12:42:44.481719 DRAM rank1 size=0x100000000
9309 12:42:44.484880 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9310 12:42:44.488024 CPU: 00 missing read_resources
9311 12:42:44.491397 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9312 12:42:44.497951 Root Device read_resources bus 0 link: 0 done
9313 12:42:44.498027 Done reading resources.
9314 12:42:44.504788 Show resources in subtree (Root Device)...After reading.
9315 12:42:44.508694 Root Device child on link 0 CPU_CLUSTER: 0
9316 12:42:44.511745 CPU_CLUSTER: 0 child on link 0 CPU: 00
9317 12:42:44.521399 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9318 12:42:44.521496 CPU: 00
9319 12:42:44.524604 Root Device assign_resources, bus 0 link: 0
9320 12:42:44.528115 CPU_CLUSTER: 0 missing set_resources
9321 12:42:44.531089 Root Device assign_resources, bus 0 link: 0 done
9322 12:42:44.534613 Done setting resources.
9323 12:42:44.541580 Show resources in subtree (Root Device)...After assigning values.
9324 12:42:44.544480 Root Device child on link 0 CPU_CLUSTER: 0
9325 12:42:44.548262 CPU_CLUSTER: 0 child on link 0 CPU: 00
9326 12:42:44.557952 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9327 12:42:44.558035 CPU: 00
9328 12:42:44.560891 Done allocating resources.
9329 12:42:44.564817 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9330 12:42:44.567777 Enabling resources...
9331 12:42:44.567851 done.
9332 12:42:44.574735 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9333 12:42:44.574815 Initializing devices...
9334 12:42:44.578166 Root Device init
9335 12:42:44.578240 init hardware done!
9336 12:42:44.581216 0x00000018: ctrlr->caps
9337 12:42:44.584663 52.000 MHz: ctrlr->f_max
9338 12:42:44.584771 0.400 MHz: ctrlr->f_min
9339 12:42:44.588313 0x40ff8080: ctrlr->voltages
9340 12:42:44.588420 sclk: 390625
9341 12:42:44.590912 Bus Width = 1
9342 12:42:44.591022 sclk: 390625
9343 12:42:44.591114 Bus Width = 1
9344 12:42:44.594551 Early init status = 3
9345 12:42:44.601149 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9346 12:42:44.604762 in-header: 03 fc 00 00 01 00 00 00
9347 12:42:44.608051 in-data: 00
9348 12:42:44.611189 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9349 12:42:44.616497 in-header: 03 fd 00 00 00 00 00 00
9350 12:42:44.619213 in-data:
9351 12:42:44.622451 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9352 12:42:44.626884 in-header: 03 fc 00 00 01 00 00 00
9353 12:42:44.630228 in-data: 00
9354 12:42:44.633238 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9355 12:42:44.638999 in-header: 03 fd 00 00 00 00 00 00
9356 12:42:44.642378 in-data:
9357 12:42:44.645540 [SSUSB] Setting up USB HOST controller...
9358 12:42:44.649275 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9359 12:42:44.652794 [SSUSB] phy power-on done.
9360 12:42:44.655981 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9361 12:42:44.662461 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9362 12:42:44.665391 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9363 12:42:44.672259 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9364 12:42:44.678880 read SPI 0x50eb0 0x2ad3: 1173 us, 9346 KB/s, 74.768 Mbps
9365 12:42:44.685524 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9366 12:42:44.692363 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9367 12:42:44.699544 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9368 12:42:44.702816 SPM: binary array size = 0x9dc
9369 12:42:44.705585 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9370 12:42:44.712313 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9371 12:42:44.718840 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9372 12:42:44.722335 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9373 12:42:44.725518 configure_display: Starting display init
9374 12:42:44.762560 anx7625_power_on_init: Init interface.
9375 12:42:44.765690 anx7625_disable_pd_protocol: Disabled PD feature.
9376 12:42:44.769685 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9377 12:42:44.796600 anx7625_start_dp_work: Secure OCM version=00
9378 12:42:44.800207 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9379 12:42:44.814844 sp_tx_get_edid_block: EDID Block = 1
9380 12:42:44.917598 Extracted contents:
9381 12:42:44.921181 header: 00 ff ff ff ff ff ff 00
9382 12:42:44.924305 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9383 12:42:44.927291 version: 01 04
9384 12:42:44.930775 basic params: 95 1f 11 78 0a
9385 12:42:44.933957 chroma info: 76 90 94 55 54 90 27 21 50 54
9386 12:42:44.937422 established: 00 00 00
9387 12:42:44.941020 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9388 12:42:44.947637 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9389 12:42:44.954189 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9390 12:42:44.961091 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9391 12:42:44.967288 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9392 12:42:44.971551 extensions: 00
9393 12:42:44.971628 checksum: fb
9394 12:42:44.971690
9395 12:42:44.974092 Manufacturer: IVO Model 57d Serial Number 0
9396 12:42:44.977303 Made week 0 of 2020
9397 12:42:44.977375 EDID version: 1.4
9398 12:42:44.980372 Digital display
9399 12:42:44.983866 6 bits per primary color channel
9400 12:42:44.983939 DisplayPort interface
9401 12:42:44.987337 Maximum image size: 31 cm x 17 cm
9402 12:42:44.991029 Gamma: 220%
9403 12:42:44.991099 Check DPMS levels
9404 12:42:44.994049 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9405 12:42:44.997522 First detailed timing is preferred timing
9406 12:42:45.000591 Established timings supported:
9407 12:42:45.004183 Standard timings supported:
9408 12:42:45.004254 Detailed timings
9409 12:42:45.010548 Hex of detail: 383680a07038204018303c0035ae10000019
9410 12:42:45.013968 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9411 12:42:45.018037 0780 0798 07c8 0820 hborder 0
9412 12:42:45.024323 0438 043b 0447 0458 vborder 0
9413 12:42:45.024398 -hsync -vsync
9414 12:42:45.027339 Did detailed timing
9415 12:42:45.030728 Hex of detail: 000000000000000000000000000000000000
9416 12:42:45.034118 Manufacturer-specified data, tag 0
9417 12:42:45.040885 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9418 12:42:45.040960 ASCII string: InfoVision
9419 12:42:45.047444 Hex of detail: 000000fe00523134304e574635205248200a
9420 12:42:45.047520 ASCII string: R140NWF5 RH
9421 12:42:45.050317 Checksum
9422 12:42:45.050389 Checksum: 0xfb (valid)
9423 12:42:45.057714 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9424 12:42:45.057797 DSI data_rate: 832800000 bps
9425 12:42:45.065801 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9426 12:42:45.068647 anx7625_parse_edid: pixelclock(138800).
9427 12:42:45.071978 hactive(1920), hsync(48), hfp(24), hbp(88)
9428 12:42:45.075125 vactive(1080), vsync(12), vfp(3), vbp(17)
9429 12:42:45.078342 anx7625_dsi_config: config dsi.
9430 12:42:45.085050 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9431 12:42:45.099668 anx7625_dsi_config: success to config DSI
9432 12:42:45.102431 anx7625_dp_start: MIPI phy setup OK.
9433 12:42:45.106152 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9434 12:42:45.109735 mtk_ddp_mode_set invalid vrefresh 60
9435 12:42:45.112738 main_disp_path_setup
9436 12:42:45.112847 ovl_layer_smi_id_en
9437 12:42:45.116507 ovl_layer_smi_id_en
9438 12:42:45.116585 ccorr_config
9439 12:42:45.116648 aal_config
9440 12:42:45.119462 gamma_config
9441 12:42:45.119566 postmask_config
9442 12:42:45.123053 dither_config
9443 12:42:45.126589 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9444 12:42:45.134275 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9445 12:42:45.136669 Root Device init finished in 555 msecs
9446 12:42:45.136778 CPU_CLUSTER: 0 init
9447 12:42:45.146351 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9448 12:42:45.149907 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9449 12:42:45.153029 APU_MBOX 0x190000b0 = 0x10001
9450 12:42:45.157085 APU_MBOX 0x190001b0 = 0x10001
9451 12:42:45.159671 APU_MBOX 0x190005b0 = 0x10001
9452 12:42:45.162951 APU_MBOX 0x190006b0 = 0x10001
9453 12:42:45.165817 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9454 12:42:45.178543 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9455 12:42:45.190982 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9456 12:42:45.197812 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9457 12:42:45.208948 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9458 12:42:45.218008 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9459 12:42:45.221655 CPU_CLUSTER: 0 init finished in 81 msecs
9460 12:42:45.225140 Devices initialized
9461 12:42:45.228389 Show all devs... After init.
9462 12:42:45.228469 Root Device: enabled 1
9463 12:42:45.231438 CPU_CLUSTER: 0: enabled 1
9464 12:42:45.235028 CPU: 00: enabled 1
9465 12:42:45.238314 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9466 12:42:45.242720 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9467 12:42:45.245960 ELOG: NV offset 0x57f000 size 0x1000
9468 12:42:45.251993 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9469 12:42:45.258335 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9470 12:42:45.261781 ELOG: Event(17) added with size 13 at 2024-02-05 12:43:07 UTC
9471 12:42:45.265200 out: cmd=0x121: 03 db 21 01 00 00 00 00
9472 12:42:45.269723 in-header: 03 a0 00 00 2c 00 00 00
9473 12:42:45.282593 in-data: bf 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9474 12:42:45.289834 ELOG: Event(A1) added with size 10 at 2024-02-05 12:43:07 UTC
9475 12:42:45.296233 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9476 12:42:45.303470 ELOG: Event(A0) added with size 9 at 2024-02-05 12:43:07 UTC
9477 12:42:45.305846 elog_add_boot_reason: Logged dev mode boot
9478 12:42:45.309403 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9479 12:42:45.312687 Finalize devices...
9480 12:42:45.312758 Devices finalized
9481 12:42:45.319685 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9482 12:42:45.323116 Writing coreboot table at 0xffe64000
9483 12:42:45.326548 0. 000000000010a000-0000000000113fff: RAMSTAGE
9484 12:42:45.329123 1. 0000000040000000-00000000400fffff: RAM
9485 12:42:45.333201 2. 0000000040100000-000000004032afff: RAMSTAGE
9486 12:42:45.339550 3. 000000004032b000-00000000545fffff: RAM
9487 12:42:45.342689 4. 0000000054600000-000000005465ffff: BL31
9488 12:42:45.346119 5. 0000000054660000-00000000ffe63fff: RAM
9489 12:42:45.349607 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9490 12:42:45.356274 7. 0000000100000000-000000023fffffff: RAM
9491 12:42:45.356388 Passing 5 GPIOs to payload:
9492 12:42:45.362721 NAME | PORT | POLARITY | VALUE
9493 12:42:45.366351 EC in RW | 0x000000aa | low | undefined
9494 12:42:45.372953 EC interrupt | 0x00000005 | low | undefined
9495 12:42:45.375955 TPM interrupt | 0x000000ab | high | undefined
9496 12:42:45.379830 SD card detect | 0x00000011 | high | undefined
9497 12:42:45.386376 speaker enable | 0x00000093 | high | undefined
9498 12:42:45.390167 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9499 12:42:45.393497 in-header: 03 f9 00 00 02 00 00 00
9500 12:42:45.393608 in-data: 02 00
9501 12:42:45.396673 ADC[4]: Raw value=900590 ID=7
9502 12:42:45.399538 ADC[3]: Raw value=213336 ID=1
9503 12:42:45.399615 RAM Code: 0x71
9504 12:42:45.402779 ADC[6]: Raw value=74926 ID=0
9505 12:42:45.406482 ADC[5]: Raw value=212229 ID=1
9506 12:42:45.406559 SKU Code: 0x1
9507 12:42:45.412895 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 51b0
9508 12:42:45.416406 coreboot table: 964 bytes.
9509 12:42:45.420396 IMD ROOT 0. 0xfffff000 0x00001000
9510 12:42:45.423030 IMD SMALL 1. 0xffffe000 0x00001000
9511 12:42:45.426554 RO MCACHE 2. 0xffffc000 0x00001104
9512 12:42:45.429332 CONSOLE 3. 0xfff7c000 0x00080000
9513 12:42:45.432922 FMAP 4. 0xfff7b000 0x00000452
9514 12:42:45.435930 TIME STAMP 5. 0xfff7a000 0x00000910
9515 12:42:45.439162 VBOOT WORK 6. 0xfff66000 0x00014000
9516 12:42:45.442927 RAMOOPS 7. 0xffe66000 0x00100000
9517 12:42:45.446249 COREBOOT 8. 0xffe64000 0x00002000
9518 12:42:45.446321 IMD small region:
9519 12:42:45.449775 IMD ROOT 0. 0xffffec00 0x00000400
9520 12:42:45.453525 VPD 1. 0xffffeb80 0x0000006c
9521 12:42:45.456148 MMC STATUS 2. 0xffffeb60 0x00000004
9522 12:42:45.463154 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9523 12:42:45.463265 Probing TPM: done!
9524 12:42:45.469457 Connected to device vid:did:rid of 1ae0:0028:00
9525 12:42:45.476562 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9526 12:42:45.479432 Initialized TPM device CR50 revision 0
9527 12:42:45.483600 Checking cr50 for pending updates
9528 12:42:45.488983 Reading cr50 TPM mode
9529 12:42:45.497744 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9530 12:42:45.504872 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9531 12:42:45.545076 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9532 12:42:45.548463 Checking segment from ROM address 0x40100000
9533 12:42:45.551176 Checking segment from ROM address 0x4010001c
9534 12:42:45.557611 Loading segment from ROM address 0x40100000
9535 12:42:45.557720 code (compression=0)
9536 12:42:45.564638 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9537 12:42:45.574552 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9538 12:42:45.574671 it's not compressed!
9539 12:42:45.581354 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9540 12:42:45.584321 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9541 12:42:45.604911 Loading segment from ROM address 0x4010001c
9542 12:42:45.605023 Entry Point 0x80000000
9543 12:42:45.608092 Loaded segments
9544 12:42:45.611412 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9545 12:42:45.618489 Jumping to boot code at 0x80000000(0xffe64000)
9546 12:42:45.624958 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9547 12:42:45.632055 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9548 12:42:45.639846 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9549 12:42:45.642846 Checking segment from ROM address 0x40100000
9550 12:42:45.646250 Checking segment from ROM address 0x4010001c
9551 12:42:45.652415 Loading segment from ROM address 0x40100000
9552 12:42:45.652498 code (compression=1)
9553 12:42:45.659974 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9554 12:42:45.669436 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9555 12:42:45.669514 using LZMA
9556 12:42:45.677785 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9557 12:42:45.684376 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9558 12:42:45.688019 Loading segment from ROM address 0x4010001c
9559 12:42:45.688094 Entry Point 0x54601000
9560 12:42:45.691691 Loaded segments
9561 12:42:45.694773 NOTICE: MT8192 bl31_setup
9562 12:42:45.701306 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9563 12:42:45.704663 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9564 12:42:45.708339 WARNING: region 0:
9565 12:42:45.711154 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9566 12:42:45.711235 WARNING: region 1:
9567 12:42:45.718143 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9568 12:42:45.721542 WARNING: region 2:
9569 12:42:45.724587 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9570 12:42:45.728342 WARNING: region 3:
9571 12:42:45.731487 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9572 12:42:45.734755 WARNING: region 4:
9573 12:42:45.738691 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9574 12:42:45.741876 WARNING: region 5:
9575 12:42:45.744870 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9576 12:42:45.748484 WARNING: region 6:
9577 12:42:45.752043 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9578 12:42:45.752124 WARNING: region 7:
9579 12:42:45.758044 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9580 12:42:45.764741 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9581 12:42:45.768359 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9582 12:42:45.771695 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9583 12:42:45.777943 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9584 12:42:45.781385 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9585 12:42:45.785070 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9586 12:42:45.791468 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9587 12:42:45.795019 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9588 12:42:45.798509 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9589 12:42:45.804892 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9590 12:42:45.809210 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9591 12:42:45.811823 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9592 12:42:45.818346 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9593 12:42:45.821599 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9594 12:42:45.828351 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9595 12:42:45.831832 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9596 12:42:45.835552 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9597 12:42:45.842200 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9598 12:42:45.845008 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9599 12:42:45.848486 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9600 12:42:45.855516 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9601 12:42:45.858767 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9602 12:42:45.865434 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9603 12:42:45.869096 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9604 12:42:45.871801 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9605 12:42:45.878781 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9606 12:42:45.882281 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9607 12:42:45.888897 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9608 12:42:45.892058 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9609 12:42:45.895350 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9610 12:42:45.902081 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9611 12:42:45.905167 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9612 12:42:45.908750 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9613 12:42:45.915545 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9614 12:42:45.919286 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9615 12:42:45.922042 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9616 12:42:45.925861 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9617 12:42:45.928684 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9618 12:42:45.935447 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9619 12:42:45.938607 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9620 12:42:45.942332 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9621 12:42:45.945286 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9622 12:42:45.952270 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9623 12:42:45.955857 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9624 12:42:45.959205 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9625 12:42:45.962392 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9626 12:42:45.968899 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9627 12:42:45.972427 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9628 12:42:45.975616 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9629 12:42:45.982393 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9630 12:42:45.985585 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9631 12:42:45.992320 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9632 12:42:45.995844 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9633 12:42:45.999149 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9634 12:42:46.006008 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9635 12:42:46.009334 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9636 12:42:46.015978 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9637 12:42:46.019238 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9638 12:42:46.026222 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9639 12:42:46.030612 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9640 12:42:46.032551 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9641 12:42:46.039633 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9642 12:42:46.042985 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9643 12:42:46.049380 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9644 12:42:46.053711 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9645 12:42:46.059529 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9646 12:42:46.062698 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9647 12:42:46.066621 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9648 12:42:46.073275 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9649 12:42:46.076326 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9650 12:42:46.083084 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9651 12:42:46.086556 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9652 12:42:46.089342 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9653 12:42:46.096106 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9654 12:42:46.099398 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9655 12:42:46.106824 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9656 12:42:46.109853 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9657 12:42:46.116209 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9658 12:42:46.119830 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9659 12:42:46.126881 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9660 12:42:46.130043 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9661 12:42:46.133109 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9662 12:42:46.139900 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9663 12:42:46.143331 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9664 12:42:46.150073 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9665 12:42:46.154650 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9666 12:42:46.156432 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9667 12:42:46.163371 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9668 12:42:46.166870 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9669 12:42:46.173441 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9670 12:42:46.176933 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9671 12:42:46.183656 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9672 12:42:46.186829 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9673 12:42:46.190126 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9674 12:42:46.196822 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9675 12:42:46.200212 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9676 12:42:46.207041 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9677 12:42:46.210128 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9678 12:42:46.213856 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9679 12:42:46.216920 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9680 12:42:46.220265 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9681 12:42:46.228199 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9682 12:42:46.230487 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9683 12:42:46.236799 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9684 12:42:46.240515 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9685 12:42:46.243705 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9686 12:42:46.250716 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9687 12:42:46.253913 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9688 12:42:46.260888 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9689 12:42:46.263736 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9690 12:42:46.267657 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9691 12:42:46.274372 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9692 12:42:46.277032 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9693 12:42:46.284146 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9694 12:42:46.287261 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9695 12:42:46.291155 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9696 12:42:46.297922 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9697 12:42:46.301031 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9698 12:42:46.303833 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9699 12:42:46.307334 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9700 12:42:46.314052 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9701 12:42:46.317567 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9702 12:42:46.320936 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9703 12:42:46.324032 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9704 12:42:46.330703 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9705 12:42:46.334091 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9706 12:42:46.340980 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9707 12:42:46.343975 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9708 12:42:46.347370 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9709 12:42:46.353881 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9710 12:42:46.357688 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9711 12:42:46.360731 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9712 12:42:46.367418 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9713 12:42:46.370635 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9714 12:42:46.377253 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9715 12:42:46.380584 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9716 12:42:46.383798 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9717 12:42:46.391017 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9718 12:42:46.393819 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9719 12:42:46.401395 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9720 12:42:46.404709 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9721 12:42:46.407276 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9722 12:42:46.414368 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9723 12:42:46.417440 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9724 12:42:46.421138 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9725 12:42:46.427252 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9726 12:42:46.430752 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9727 12:42:46.437732 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9728 12:42:46.441086 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9729 12:42:46.444503 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9730 12:42:46.451226 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9731 12:42:46.455047 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9732 12:42:46.458170 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9733 12:42:46.464371 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9734 12:42:46.467921 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9735 12:42:46.474684 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9736 12:42:46.477763 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9737 12:42:46.481096 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9738 12:42:46.487896 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9739 12:42:46.491487 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9740 12:42:46.498458 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9741 12:42:46.501225 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9742 12:42:46.504633 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9743 12:42:46.511059 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9744 12:42:46.514497 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9745 12:42:46.518076 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9746 12:42:46.524932 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9747 12:42:46.527732 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9748 12:42:46.534325 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9749 12:42:46.538122 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9750 12:42:46.541201 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9751 12:42:46.547537 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9752 12:42:46.551189 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9753 12:42:46.558098 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9754 12:42:46.561402 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9755 12:42:46.565001 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9756 12:42:46.571424 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9757 12:42:46.574927 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9758 12:42:46.581159 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9759 12:42:46.584473 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9760 12:42:46.587934 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9761 12:42:46.594457 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9762 12:42:46.598054 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9763 12:42:46.600933 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9764 12:42:46.607749 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9765 12:42:46.610843 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9766 12:42:46.617568 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9767 12:42:46.621104 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9768 12:42:46.624810 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9769 12:42:46.631005 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9770 12:42:46.634154 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9771 12:42:46.640796 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9772 12:42:46.645142 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9773 12:42:46.647623 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9774 12:42:46.654552 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9775 12:42:46.657691 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9776 12:42:46.664518 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9777 12:42:46.667396 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9778 12:42:46.675326 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9779 12:42:46.677290 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9780 12:42:46.681219 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9781 12:42:46.687866 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9782 12:42:46.690984 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9783 12:42:46.697638 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9784 12:42:46.701434 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9785 12:42:46.704485 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9786 12:42:46.711559 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9787 12:42:46.714047 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9788 12:42:46.720962 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9789 12:42:46.724354 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9790 12:42:46.728563 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9791 12:42:46.734711 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9792 12:42:46.737545 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9793 12:42:46.744324 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9794 12:42:46.747569 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9795 12:42:46.751287 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9796 12:42:46.757788 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9797 12:42:46.761268 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9798 12:42:46.767746 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9799 12:42:46.771097 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9800 12:42:46.777936 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9801 12:42:46.781072 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9802 12:42:46.784666 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9803 12:42:46.790927 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9804 12:42:46.794597 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9805 12:42:46.801265 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9806 12:42:46.804195 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9807 12:42:46.810577 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9808 12:42:46.814281 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9809 12:42:46.817886 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9810 12:42:46.820977 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9811 12:42:46.824171 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9812 12:42:46.830893 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9813 12:42:46.834361 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9814 12:42:46.837921 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9815 12:42:46.844960 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9816 12:42:46.847928 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9817 12:42:46.854191 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9818 12:42:46.857706 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9819 12:42:46.861086 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9820 12:42:46.864164 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9821 12:42:46.871235 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9822 12:42:46.874873 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9823 12:42:46.877435 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9824 12:42:46.884385 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9825 12:42:46.887828 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9826 12:42:46.894117 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9827 12:42:46.898065 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9828 12:42:46.901011 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9829 12:42:46.908021 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9830 12:42:46.911071 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9831 12:42:46.914908 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9832 12:42:46.920997 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9833 12:42:46.924337 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9834 12:42:46.930917 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9835 12:42:46.934240 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9836 12:42:46.937920 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9837 12:42:46.944328 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9838 12:42:46.947343 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9839 12:42:46.950951 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9840 12:42:46.957648 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9841 12:42:46.961169 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9842 12:42:46.964117 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9843 12:42:46.970732 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9844 12:42:46.974066 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9845 12:42:46.980820 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9846 12:42:46.984491 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9847 12:42:46.987438 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9848 12:42:46.991187 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9849 12:42:46.997402 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9850 12:42:47.001275 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9851 12:42:47.004119 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9852 12:42:47.007951 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9853 12:42:47.010949 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9854 12:42:47.017639 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9855 12:42:47.020869 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9856 12:42:47.024679 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9857 12:42:47.030793 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9858 12:42:47.034306 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9859 12:42:47.037978 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9860 12:42:47.041016 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9861 12:42:47.047630 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9862 12:42:47.051026 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9863 12:42:47.054353 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9864 12:42:47.060816 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9865 12:42:47.064346 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9866 12:42:47.071104 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9867 12:42:47.074259 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9868 12:42:47.081040 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9869 12:42:47.084402 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9870 12:42:47.087939 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9871 12:42:47.094159 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9872 12:42:47.097683 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9873 12:42:47.104580 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9874 12:42:47.107557 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9875 12:42:47.110972 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9876 12:42:47.117459 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9877 12:42:47.121451 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9878 12:42:47.124570 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9879 12:42:47.131588 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9880 12:42:47.134136 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9881 12:42:47.141137 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9882 12:42:47.144871 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9883 12:42:47.151249 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9884 12:42:47.154653 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9885 12:42:47.158694 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9886 12:42:47.165117 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9887 12:42:47.167984 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9888 12:42:47.174661 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9889 12:42:47.178075 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9890 12:42:47.181056 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9891 12:42:47.188214 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9892 12:42:47.191287 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9893 12:42:47.194638 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9894 12:42:47.201019 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9895 12:42:47.204515 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9896 12:42:47.211154 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9897 12:42:47.214583 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9898 12:42:47.221066 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9899 12:42:47.224454 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9900 12:42:47.227872 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9901 12:42:47.234632 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9902 12:42:47.237716 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9903 12:42:47.244189 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9904 12:42:47.248690 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9905 12:42:47.250989 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9906 12:42:47.257984 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9907 12:42:47.261397 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9908 12:42:47.267860 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9909 12:42:47.271027 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9910 12:42:47.274572 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9911 12:42:47.280955 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9912 12:42:47.284681 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9913 12:42:47.291394 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9914 12:42:47.294388 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9915 12:42:47.297690 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9916 12:42:47.304817 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9917 12:42:47.308127 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9918 12:42:47.314816 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9919 12:42:47.317764 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9920 12:42:47.321192 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9921 12:42:47.328108 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9922 12:42:47.331139 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9923 12:42:47.337977 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9924 12:42:47.341922 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9925 12:42:47.344924 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9926 12:42:47.351352 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9927 12:42:47.354867 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9928 12:42:47.361547 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9929 12:42:47.365016 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9930 12:42:47.368220 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9931 12:42:47.374566 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9932 12:42:47.378246 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9933 12:42:47.385271 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9934 12:42:47.388391 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9935 12:42:47.391139 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9936 12:42:47.398378 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9937 12:42:47.401038 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9938 12:42:47.407761 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9939 12:42:47.411247 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9940 12:42:47.417736 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9941 12:42:47.421378 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9942 12:42:47.424771 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9943 12:42:47.430965 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9944 12:42:47.434337 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9945 12:42:47.440840 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9946 12:42:47.444331 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9947 12:42:47.451214 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9948 12:42:47.454347 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9949 12:42:47.458005 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9950 12:42:47.464452 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9951 12:42:47.467546 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9952 12:42:47.474517 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9953 12:42:47.477876 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9954 12:42:47.484636 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9955 12:42:47.487618 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9956 12:42:47.494488 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9957 12:42:47.498362 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9958 12:42:47.501120 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9959 12:42:47.508141 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9960 12:42:47.511487 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9961 12:42:47.518050 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9962 12:42:47.521340 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9963 12:42:47.527849 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9964 12:42:47.531061 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9965 12:42:47.534363 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9966 12:42:47.541383 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9967 12:42:47.544330 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9968 12:42:47.550894 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9969 12:42:47.555119 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9970 12:42:47.558024 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9971 12:42:47.564859 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9972 12:42:47.568128 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9973 12:42:47.574647 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9974 12:42:47.577648 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9975 12:42:47.584829 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9976 12:42:47.587948 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9977 12:42:47.591000 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9978 12:42:47.598258 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9979 12:42:47.601193 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9980 12:42:47.607944 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9981 12:42:47.611148 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9982 12:42:47.614843 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9983 12:42:47.621232 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9984 12:42:47.624993 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9985 12:42:47.631527 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9986 12:42:47.634704 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9987 12:42:47.641628 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9988 12:42:47.644432 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9989 12:42:47.651045 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9990 12:42:47.654316 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9991 12:42:47.661276 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9992 12:42:47.664781 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9993 12:42:47.671205 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9994 12:42:47.674680 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9995 12:42:47.677983 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9996 12:42:47.684804 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9997 12:42:47.687727 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9998 12:42:47.694579 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9999 12:42:47.697676 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10000 12:42:47.704200 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10001 12:42:47.707990 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10002 12:42:47.714380 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10003 12:42:47.718746 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10004 12:42:47.724273 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10005 12:42:47.727752 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10006 12:42:47.734310 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10007 12:42:47.737655 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10008 12:42:47.744514 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10009 12:42:47.747747 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10010 12:42:47.753908 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10011 12:42:47.757369 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10012 12:42:47.765055 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10013 12:42:47.768103 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10014 12:42:47.774006 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10015 12:42:47.774078 INFO: [APUAPC] vio 0
10016 12:42:47.781097 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10017 12:42:47.784654 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10018 12:42:47.787662 INFO: [APUAPC] D0_APC_0: 0x400510
10019 12:42:47.791515 INFO: [APUAPC] D0_APC_1: 0x0
10020 12:42:47.794154 INFO: [APUAPC] D0_APC_2: 0x1540
10021 12:42:47.797553 INFO: [APUAPC] D0_APC_3: 0x0
10022 12:42:47.801240 INFO: [APUAPC] D1_APC_0: 0xffffffff
10023 12:42:47.804590 INFO: [APUAPC] D1_APC_1: 0xffffffff
10024 12:42:47.808003 INFO: [APUAPC] D1_APC_2: 0x3fffff
10025 12:42:47.810859 INFO: [APUAPC] D1_APC_3: 0x0
10026 12:42:47.814537 INFO: [APUAPC] D2_APC_0: 0xffffffff
10027 12:42:47.817896 INFO: [APUAPC] D2_APC_1: 0xffffffff
10028 12:42:47.820931 INFO: [APUAPC] D2_APC_2: 0x3fffff
10029 12:42:47.824520 INFO: [APUAPC] D2_APC_3: 0x0
10030 12:42:47.827894 INFO: [APUAPC] D3_APC_0: 0xffffffff
10031 12:42:47.831095 INFO: [APUAPC] D3_APC_1: 0xffffffff
10032 12:42:47.834633 INFO: [APUAPC] D3_APC_2: 0x3fffff
10033 12:42:47.837411 INFO: [APUAPC] D3_APC_3: 0x0
10034 12:42:47.840688 INFO: [APUAPC] D4_APC_0: 0xffffffff
10035 12:42:47.844454 INFO: [APUAPC] D4_APC_1: 0xffffffff
10036 12:42:47.847852 INFO: [APUAPC] D4_APC_2: 0x3fffff
10037 12:42:47.847932 INFO: [APUAPC] D4_APC_3: 0x0
10038 12:42:47.851017 INFO: [APUAPC] D5_APC_0: 0xffffffff
10039 12:42:47.854105 INFO: [APUAPC] D5_APC_1: 0xffffffff
10040 12:42:47.857387 INFO: [APUAPC] D5_APC_2: 0x3fffff
10041 12:42:47.861031 INFO: [APUAPC] D5_APC_3: 0x0
10042 12:42:47.864355 INFO: [APUAPC] D6_APC_0: 0xffffffff
10043 12:42:47.867977 INFO: [APUAPC] D6_APC_1: 0xffffffff
10044 12:42:47.870953 INFO: [APUAPC] D6_APC_2: 0x3fffff
10045 12:42:47.874597 INFO: [APUAPC] D6_APC_3: 0x0
10046 12:42:47.877958 INFO: [APUAPC] D7_APC_0: 0xffffffff
10047 12:42:47.880781 INFO: [APUAPC] D7_APC_1: 0xffffffff
10048 12:42:47.884630 INFO: [APUAPC] D7_APC_2: 0x3fffff
10049 12:42:47.887466 INFO: [APUAPC] D7_APC_3: 0x0
10050 12:42:47.890921 INFO: [APUAPC] D8_APC_0: 0xffffffff
10051 12:42:47.894129 INFO: [APUAPC] D8_APC_1: 0xffffffff
10052 12:42:47.897876 INFO: [APUAPC] D8_APC_2: 0x3fffff
10053 12:42:47.900998 INFO: [APUAPC] D8_APC_3: 0x0
10054 12:42:47.904444 INFO: [APUAPC] D9_APC_0: 0xffffffff
10055 12:42:47.907509 INFO: [APUAPC] D9_APC_1: 0xffffffff
10056 12:42:47.911026 INFO: [APUAPC] D9_APC_2: 0x3fffff
10057 12:42:47.915072 INFO: [APUAPC] D9_APC_3: 0x0
10058 12:42:47.917891 INFO: [APUAPC] D10_APC_0: 0xffffffff
10059 12:42:47.921465 INFO: [APUAPC] D10_APC_1: 0xffffffff
10060 12:42:47.924761 INFO: [APUAPC] D10_APC_2: 0x3fffff
10061 12:42:47.927862 INFO: [APUAPC] D10_APC_3: 0x0
10062 12:42:47.931790 INFO: [APUAPC] D11_APC_0: 0xffffffff
10063 12:42:47.934218 INFO: [APUAPC] D11_APC_1: 0xffffffff
10064 12:42:47.937799 INFO: [APUAPC] D11_APC_2: 0x3fffff
10065 12:42:47.940856 INFO: [APUAPC] D11_APC_3: 0x0
10066 12:42:47.944508 INFO: [APUAPC] D12_APC_0: 0xffffffff
10067 12:42:47.947544 INFO: [APUAPC] D12_APC_1: 0xffffffff
10068 12:42:47.950801 INFO: [APUAPC] D12_APC_2: 0x3fffff
10069 12:42:47.954428 INFO: [APUAPC] D12_APC_3: 0x0
10070 12:42:47.957829 INFO: [APUAPC] D13_APC_0: 0xffffffff
10071 12:42:47.960957 INFO: [APUAPC] D13_APC_1: 0xffffffff
10072 12:42:47.964526 INFO: [APUAPC] D13_APC_2: 0x3fffff
10073 12:42:47.968086 INFO: [APUAPC] D13_APC_3: 0x0
10074 12:42:47.971437 INFO: [APUAPC] D14_APC_0: 0xffffffff
10075 12:42:47.974363 INFO: [APUAPC] D14_APC_1: 0xffffffff
10076 12:42:47.978124 INFO: [APUAPC] D14_APC_2: 0x3fffff
10077 12:42:47.980796 INFO: [APUAPC] D14_APC_3: 0x0
10078 12:42:47.984647 INFO: [APUAPC] D15_APC_0: 0xffffffff
10079 12:42:47.987557 INFO: [APUAPC] D15_APC_1: 0xffffffff
10080 12:42:47.991215 INFO: [APUAPC] D15_APC_2: 0x3fffff
10081 12:42:47.994161 INFO: [APUAPC] D15_APC_3: 0x0
10082 12:42:47.997572 INFO: [APUAPC] APC_CON: 0x4
10083 12:42:48.001117 INFO: [NOCDAPC] D0_APC_0: 0x0
10084 12:42:48.004490 INFO: [NOCDAPC] D0_APC_1: 0x0
10085 12:42:48.004587 INFO: [NOCDAPC] D1_APC_0: 0x0
10086 12:42:48.008131 INFO: [NOCDAPC] D1_APC_1: 0xfff
10087 12:42:48.010731 INFO: [NOCDAPC] D2_APC_0: 0x0
10088 12:42:48.014532 INFO: [NOCDAPC] D2_APC_1: 0xfff
10089 12:42:48.017452 INFO: [NOCDAPC] D3_APC_0: 0x0
10090 12:42:48.021295 INFO: [NOCDAPC] D3_APC_1: 0xfff
10091 12:42:48.024474 INFO: [NOCDAPC] D4_APC_0: 0x0
10092 12:42:48.027347 INFO: [NOCDAPC] D4_APC_1: 0xfff
10093 12:42:48.031170 INFO: [NOCDAPC] D5_APC_0: 0x0
10094 12:42:48.034671 INFO: [NOCDAPC] D5_APC_1: 0xfff
10095 12:42:48.034752 INFO: [NOCDAPC] D6_APC_0: 0x0
10096 12:42:48.037820 INFO: [NOCDAPC] D6_APC_1: 0xfff
10097 12:42:48.041165 INFO: [NOCDAPC] D7_APC_0: 0x0
10098 12:42:48.044523 INFO: [NOCDAPC] D7_APC_1: 0xfff
10099 12:42:48.048012 INFO: [NOCDAPC] D8_APC_0: 0x0
10100 12:42:48.051562 INFO: [NOCDAPC] D8_APC_1: 0xfff
10101 12:42:48.055129 INFO: [NOCDAPC] D9_APC_0: 0x0
10102 12:42:48.057547 INFO: [NOCDAPC] D9_APC_1: 0xfff
10103 12:42:48.061256 INFO: [NOCDAPC] D10_APC_0: 0x0
10104 12:42:48.064188 INFO: [NOCDAPC] D10_APC_1: 0xfff
10105 12:42:48.067868 INFO: [NOCDAPC] D11_APC_0: 0x0
10106 12:42:48.071254 INFO: [NOCDAPC] D11_APC_1: 0xfff
10107 12:42:48.071333 INFO: [NOCDAPC] D12_APC_0: 0x0
10108 12:42:48.074319 INFO: [NOCDAPC] D12_APC_1: 0xfff
10109 12:42:48.078142 INFO: [NOCDAPC] D13_APC_0: 0x0
10110 12:42:48.081089 INFO: [NOCDAPC] D13_APC_1: 0xfff
10111 12:42:48.084508 INFO: [NOCDAPC] D14_APC_0: 0x0
10112 12:42:48.087891 INFO: [NOCDAPC] D14_APC_1: 0xfff
10113 12:42:48.091445 INFO: [NOCDAPC] D15_APC_0: 0x0
10114 12:42:48.094329 INFO: [NOCDAPC] D15_APC_1: 0xfff
10115 12:42:48.098302 INFO: [NOCDAPC] APC_CON: 0x4
10116 12:42:48.101290 INFO: [APUAPC] set_apusys_apc done
10117 12:42:48.104257 INFO: [DEVAPC] devapc_init done
10118 12:42:48.108693 INFO: GICv3 without legacy support detected.
10119 12:42:48.111290 INFO: ARM GICv3 driver initialized in EL3
10120 12:42:48.114791 INFO: Maximum SPI INTID supported: 639
10121 12:42:48.117886 INFO: BL31: Initializing runtime services
10122 12:42:48.124978 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10123 12:42:48.127728 INFO: SPM: enable CPC mode
10124 12:42:48.134822 INFO: mcdi ready for mcusys-off-idle and system suspend
10125 12:42:48.138132 INFO: BL31: Preparing for EL3 exit to normal world
10126 12:42:48.141065 INFO: Entry point address = 0x80000000
10127 12:42:48.144351 INFO: SPSR = 0x8
10128 12:42:48.149375
10129 12:42:48.149454
10130 12:42:48.149516
10131 12:42:48.152713 Starting depthcharge on Spherion...
10132 12:42:48.152793
10133 12:42:48.152869 Wipe memory regions:
10134 12:42:48.152956
10135 12:42:48.153789 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10136 12:42:48.153916 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10137 12:42:48.154017 Setting prompt string to ['asurada:']
10138 12:42:48.154099 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10139 12:42:48.155785 [0x00000040000000, 0x00000054600000)
10140 12:42:48.277999
10141 12:42:48.278136 [0x00000054660000, 0x00000080000000)
10142 12:42:48.539002
10143 12:42:48.539124 [0x000000821a7280, 0x000000ffe64000)
10144 12:42:49.283227
10145 12:42:49.283376 [0x00000100000000, 0x00000240000000)
10146 12:42:51.173491
10147 12:42:51.176451 Initializing XHCI USB controller at 0x11200000.
10148 12:42:52.214544
10149 12:42:52.218121 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10150 12:42:52.218808
10151 12:42:52.219195
10152 12:42:52.219526
10153 12:42:52.220373 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10155 12:42:52.321514 asurada: tftpboot 192.168.201.1 12703551/tftp-deploy-oba5nm6w/kernel/image.itb 12703551/tftp-deploy-oba5nm6w/kernel/cmdline
10156 12:42:52.322134 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10157 12:42:52.322779 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10158 12:42:52.327004 tftpboot 192.168.201.1 12703551/tftp-deploy-oba5nm6w/kernel/image.itbtp-deploy-oba5nm6w/kernel/cmdline
10159 12:42:52.327467
10160 12:42:52.327825 Waiting for link
10161 12:42:52.487577
10162 12:42:52.488077 R8152: Initializing
10163 12:42:52.488521
10164 12:42:52.490892 Version 6 (ocp_data = 5c30)
10165 12:42:52.491584
10166 12:42:52.494388 R8152: Done initializing
10167 12:42:52.494927
10168 12:42:52.495293 Adding net device
10169 12:42:54.456021
10170 12:42:54.456563 done.
10171 12:42:54.456963
10172 12:42:54.457305 MAC: 00:24:32:30:78:52
10173 12:42:54.457628
10174 12:42:54.459584 Sending DHCP discover... done.
10175 12:42:54.460182
10176 12:42:54.462600 Waiting for reply... done.
10177 12:42:54.463053
10178 12:42:54.465670 Sending DHCP request... done.
10179 12:42:54.466125
10180 12:42:54.471113 Waiting for reply... done.
10181 12:42:54.471570
10182 12:42:54.471933 My ip is 192.168.201.14
10183 12:42:54.472274
10184 12:42:54.474905 The DHCP server ip is 192.168.201.1
10185 12:42:54.475361
10186 12:42:54.480994 TFTP server IP predefined by user: 192.168.201.1
10187 12:42:54.481538
10188 12:42:54.487307 Bootfile predefined by user: 12703551/tftp-deploy-oba5nm6w/kernel/image.itb
10189 12:42:54.487761
10190 12:42:54.488116 Sending tftp read request... done.
10191 12:42:54.490942
10192 12:42:54.497601 Waiting for the transfer...
10193 12:42:54.498149
10194 12:42:55.175957 00000000 ################################################################
10195 12:42:55.176107
10196 12:42:55.763887 00080000 ################################################################
10197 12:42:55.764018
10198 12:42:56.341567 00100000 ################################################################
10199 12:42:56.341704
10200 12:42:56.987394 00180000 ################################################################
10201 12:42:56.987947
10202 12:42:57.678438 00200000 ################################################################
10203 12:42:57.678937
10204 12:42:58.358019 00280000 ################################################################
10205 12:42:58.358553
10206 12:42:59.044607 00300000 ################################################################
10207 12:42:59.045123
10208 12:42:59.725111 00380000 ################################################################
10209 12:42:59.725641
10210 12:43:00.402010 00400000 ################################################################
10211 12:43:00.402566
10212 12:43:00.968428 00480000 ################################################################
10213 12:43:00.968565
10214 12:43:01.574567 00500000 ################################################################
10215 12:43:01.574715
10216 12:43:02.224739 00580000 ################################################################
10217 12:43:02.225267
10218 12:43:02.883430 00600000 ################################################################
10219 12:43:02.883588
10220 12:43:03.488600 00680000 ################################################################
10221 12:43:03.488751
10222 12:43:04.032081 00700000 ################################################################
10223 12:43:04.032229
10224 12:43:04.605909 00780000 ################################################################
10225 12:43:04.606050
10226 12:43:05.219163 00800000 ################################################################
10227 12:43:05.219316
10228 12:43:05.823195 00880000 ################################################################
10229 12:43:05.823713
10230 12:43:06.492811 00900000 ################################################################
10231 12:43:06.493359
10232 12:43:07.080363 00980000 ################################################################
10233 12:43:07.080520
10234 12:43:07.624773 00a00000 ################################################################
10235 12:43:07.624932
10236 12:43:08.190035 00a80000 ################################################################
10237 12:43:08.190189
10238 12:43:08.761104 00b00000 ################################################################
10239 12:43:08.761252
10240 12:43:09.354469 00b80000 ################################################################
10241 12:43:09.354601
10242 12:43:09.941783 00c00000 ################################################################
10243 12:43:09.941949
10244 12:43:10.551260 00c80000 ################################################################
10245 12:43:10.551402
10246 12:43:11.194923 00d00000 ################################################################
10247 12:43:11.195420
10248 12:43:11.794233 00d80000 ################################################################
10249 12:43:11.794368
10250 12:43:12.413689 00e00000 ################################################################
10251 12:43:12.413829
10252 12:43:13.039046 00e80000 ################################################################
10253 12:43:13.039552
10254 12:43:13.650704 00f00000 ################################################################
10255 12:43:13.651255
10256 12:43:14.329111 00f80000 ################################################################
10257 12:43:14.329610
10258 12:43:14.987536 01000000 ################################################################
10259 12:43:14.988025
10260 12:43:15.589257 01080000 ################################################################
10261 12:43:15.589395
10262 12:43:16.164345 01100000 ################################################################
10263 12:43:16.164492
10264 12:43:16.745835 01180000 ################################################################
10265 12:43:16.745996
10266 12:43:17.321777 01200000 ################################################################
10267 12:43:17.321924
10268 12:43:17.882731 01280000 ################################################################
10269 12:43:17.882882
10270 12:43:18.501944 01300000 ################################################################
10271 12:43:18.502507
10272 12:43:19.161819 01380000 ################################################################
10273 12:43:19.162349
10274 12:43:19.796374 01400000 ################################################################
10275 12:43:19.796527
10276 12:43:20.388040 01480000 ################################################################
10277 12:43:20.388199
10278 12:43:20.979185 01500000 ################################################################
10279 12:43:20.979338
10280 12:43:21.546906 01580000 ################################################################
10281 12:43:21.547060
10282 12:43:22.120372 01600000 ################################################################
10283 12:43:22.120525
10284 12:43:22.712039 01680000 ################################################################
10285 12:43:22.712206
10286 12:43:23.287433 01700000 ################################################################
10287 12:43:23.287578
10288 12:43:23.952414 01780000 ################################################################
10289 12:43:23.952942
10290 12:43:24.634980 01800000 ################################################################
10291 12:43:24.635499
10292 12:43:25.322102 01880000 ################################################################
10293 12:43:25.322680
10294 12:43:26.005590 01900000 ################################################################
10295 12:43:26.006103
10296 12:43:26.693532 01980000 ################################################################
10297 12:43:26.694050
10298 12:43:27.385667 01a00000 ################################################################
10299 12:43:27.386174
10300 12:43:28.081264 01a80000 ################################################################
10301 12:43:28.081772
10302 12:43:28.770765 01b00000 ################################################################
10303 12:43:28.771308
10304 12:43:29.462042 01b80000 ################################################################
10305 12:43:29.462763
10306 12:43:30.136520 01c00000 ################################################################
10307 12:43:30.137039
10308 12:43:30.164369 01c80000 ### done.
10309 12:43:30.164771
10310 12:43:30.167658 The bootfile was 29905274 bytes long.
10311 12:43:30.168079
10312 12:43:30.171311 Sending tftp read request... done.
10313 12:43:30.171728
10314 12:43:30.174656 Waiting for the transfer...
10315 12:43:30.175094
10316 12:43:30.175423 00000000 # done.
10317 12:43:30.175739
10318 12:43:30.181795 Command line loaded dynamically from TFTP file: 12703551/tftp-deploy-oba5nm6w/kernel/cmdline
10319 12:43:30.182316
10320 12:43:30.205039 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12703551/extract-nfsrootfs-tshsvmla,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10321 12:43:30.205603
10322 12:43:30.205935 Loading FIT.
10323 12:43:30.206237
10324 12:43:30.208088 Image ramdisk-1 has 17803101 bytes.
10325 12:43:30.208499
10326 12:43:30.211113 Image fdt-1 has 47278 bytes.
10327 12:43:30.211605
10328 12:43:30.214519 Image kernel-1 has 12052857 bytes.
10329 12:43:30.214958
10330 12:43:30.224608 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10331 12:43:30.225155
10332 12:43:30.241411 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10333 12:43:30.241937
10334 12:43:30.244636 Choosing best match conf-1 for compat google,spherion-rev2.
10335 12:43:30.248203
10336 12:43:30.252060 Connected to device vid:did:rid of 1ae0:0028:00
10337 12:43:30.262563
10338 12:43:30.266506 tpm_get_response: command 0x17b, return code 0x0
10339 12:43:30.267027
10340 12:43:30.268813 ec_init: CrosEC protocol v3 supported (256, 248)
10341 12:43:30.273169
10342 12:43:30.276612 tpm_cleanup: add release locality here.
10343 12:43:30.277029
10344 12:43:30.277360 Shutting down all USB controllers.
10345 12:43:30.277702
10346 12:43:30.280450 Removing current net device
10347 12:43:30.280966
10348 12:43:30.286495 Exiting depthcharge with code 4 at timestamp: 71588819
10349 12:43:30.287008
10350 12:43:30.291134 LZMA decompressing kernel-1 to 0x821a6718
10351 12:43:30.291651
10352 12:43:30.293632 LZMA decompressing kernel-1 to 0x40000000
10353 12:43:31.793117
10354 12:43:31.793674 jumping to kernel
10355 12:43:31.795427 end: 2.2.4 bootloader-commands (duration 00:00:44) [common]
10356 12:43:31.795960 start: 2.2.5 auto-login-action (timeout 00:03:41) [common]
10357 12:43:31.796375 Setting prompt string to ['Linux version [0-9]']
10358 12:43:31.796842 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10359 12:43:31.797232 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10360 12:43:31.875790
10361 12:43:31.879713 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10362 12:43:31.882880 start: 2.2.5.1 login-action (timeout 00:03:41) [common]
10363 12:43:31.883452 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10364 12:43:31.883846 Setting prompt string to []
10365 12:43:31.884263 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10366 12:43:31.884732 Using line separator: #'\n'#
10367 12:43:31.885086 No login prompt set.
10368 12:43:31.885417 Parsing kernel messages
10369 12:43:31.885725 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10370 12:43:31.886293 [login-action] Waiting for messages, (timeout 00:03:41)
10371 12:43:31.886703 Waiting using forced prompt support (timeout 00:01:51)
10372 12:43:31.902292 [ 0.000000] Linux version 6.1.75-cip14 (KernelCI@build-j98433-arm64-gcc-10-defconfig-arm64-chromebook-89n64) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Feb 5 12:20:06 UTC 2024
10373 12:43:31.906195 [ 0.000000] random: crng init done
10374 12:43:31.912451 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10375 12:43:31.913005 [ 0.000000] efi: UEFI not found.
10376 12:43:31.922994 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10377 12:43:31.929002 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10378 12:43:31.939012 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10379 12:43:31.948965 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10380 12:43:31.955638 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10381 12:43:31.958427 [ 0.000000] printk: bootconsole [mtk8250] enabled
10382 12:43:31.967871 [ 0.000000] NUMA: No NUMA configuration found
10383 12:43:31.974564 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10384 12:43:31.980936 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10385 12:43:31.981496 [ 0.000000] Zone ranges:
10386 12:43:31.987416 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10387 12:43:31.990427 [ 0.000000] DMA32 empty
10388 12:43:31.997322 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10389 12:43:32.000596 [ 0.000000] Movable zone start for each node
10390 12:43:32.003887 [ 0.000000] Early memory node ranges
10391 12:43:32.010797 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10392 12:43:32.017174 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10393 12:43:32.023794 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10394 12:43:32.030736 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10395 12:43:32.037653 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10396 12:43:32.044410 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10397 12:43:32.100124 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10398 12:43:32.106954 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10399 12:43:32.113657 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10400 12:43:32.116725 [ 0.000000] psci: probing for conduit method from DT.
10401 12:43:32.123281 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10402 12:43:32.126130 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10403 12:43:32.133322 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10404 12:43:32.136171 [ 0.000000] psci: SMC Calling Convention v1.2
10405 12:43:32.143044 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10406 12:43:32.146515 [ 0.000000] Detected VIPT I-cache on CPU0
10407 12:43:32.153539 [ 0.000000] CPU features: detected: GIC system register CPU interface
10408 12:43:32.160353 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10409 12:43:32.166796 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10410 12:43:32.172783 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10411 12:43:32.180377 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10412 12:43:32.186697 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10413 12:43:32.193463 [ 0.000000] alternatives: applying boot alternatives
10414 12:43:32.196875 [ 0.000000] Fallback order for Node 0: 0
10415 12:43:32.203362 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10416 12:43:32.206065 [ 0.000000] Policy zone: Normal
10417 12:43:32.229511 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12703551/extract-nfsrootfs-tshsvmla,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10418 12:43:32.239644 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10419 12:43:32.252969 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10420 12:43:32.263516 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10421 12:43:32.269378 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10422 12:43:32.272529 <6>[ 0.000000] software IO TLB: area num 8.
10423 12:43:32.329577 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10424 12:43:32.478310 <6>[ 0.000000] Memory: 7949868K/8385536K available (17984K kernel code, 4118K rwdata, 19612K rodata, 8448K init, 616K bss, 402900K reserved, 32768K cma-reserved)
10425 12:43:32.485035 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10426 12:43:32.491564 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10427 12:43:32.494972 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10428 12:43:32.501862 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10429 12:43:32.508449 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10430 12:43:32.511139 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10431 12:43:32.521829 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10432 12:43:32.528709 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10433 12:43:32.531373 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10434 12:43:32.539433 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10435 12:43:32.542897 <6>[ 0.000000] GICv3: 608 SPIs implemented
10436 12:43:32.548795 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10437 12:43:32.552228 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10438 12:43:32.556266 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10439 12:43:32.565679 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10440 12:43:32.575420 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10441 12:43:32.589191 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10442 12:43:32.595565 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10443 12:43:32.604605 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10444 12:43:32.618011 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10445 12:43:32.624632 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10446 12:43:32.631241 <6>[ 0.009233] Console: colour dummy device 80x25
10447 12:43:32.641604 <6>[ 0.013961] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10448 12:43:32.644310 <6>[ 0.024403] pid_max: default: 32768 minimum: 301
10449 12:43:32.651780 <6>[ 0.029273] LSM: Security Framework initializing
10450 12:43:32.658510 <6>[ 0.034242] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10451 12:43:32.668538 <6>[ 0.042102] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10452 12:43:32.674456 <6>[ 0.051527] cblist_init_generic: Setting adjustable number of callback queues.
10453 12:43:32.681065 <6>[ 0.058971] cblist_init_generic: Setting shift to 3 and lim to 1.
10454 12:43:32.690746 <6>[ 0.065349] cblist_init_generic: Setting adjustable number of callback queues.
10455 12:43:32.698158 <6>[ 0.072822] cblist_init_generic: Setting shift to 3 and lim to 1.
10456 12:43:32.701855 <6>[ 0.079263] rcu: Hierarchical SRCU implementation.
10457 12:43:32.707972 <6>[ 0.084279] rcu: Max phase no-delay instances is 1000.
10458 12:43:32.714864 <6>[ 0.091305] EFI services will not be available.
10459 12:43:32.717679 <6>[ 0.096294] smp: Bringing up secondary CPUs ...
10460 12:43:32.725587 <6>[ 0.101377] Detected VIPT I-cache on CPU1
10461 12:43:32.732324 <6>[ 0.101445] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10462 12:43:32.739382 <6>[ 0.101476] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10463 12:43:32.742173 <6>[ 0.101822] Detected VIPT I-cache on CPU2
10464 12:43:32.749052 <6>[ 0.101873] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10465 12:43:32.755581 <6>[ 0.101891] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10466 12:43:32.762311 <6>[ 0.102149] Detected VIPT I-cache on CPU3
10467 12:43:32.769107 <6>[ 0.102196] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10468 12:43:32.775661 <6>[ 0.102210] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10469 12:43:32.778880 <6>[ 0.102514] CPU features: detected: Spectre-v4
10470 12:43:32.786009 <6>[ 0.102519] CPU features: detected: Spectre-BHB
10471 12:43:32.788932 <6>[ 0.102524] Detected PIPT I-cache on CPU4
10472 12:43:32.796337 <6>[ 0.102582] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10473 12:43:32.802121 <6>[ 0.102599] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10474 12:43:32.805625 <6>[ 0.102893] Detected PIPT I-cache on CPU5
10475 12:43:32.815682 <6>[ 0.102955] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10476 12:43:32.822335 <6>[ 0.102972] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10477 12:43:32.826455 <6>[ 0.103258] Detected PIPT I-cache on CPU6
10478 12:43:32.831948 <6>[ 0.103322] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10479 12:43:32.839333 <6>[ 0.103339] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10480 12:43:32.842199 <6>[ 0.103638] Detected PIPT I-cache on CPU7
10481 12:43:32.852259 <6>[ 0.103702] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10482 12:43:32.858731 <6>[ 0.103719] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10483 12:43:32.862781 <6>[ 0.103767] smp: Brought up 1 node, 8 CPUs
10484 12:43:32.865397 <6>[ 0.245160] SMP: Total of 8 processors activated.
10485 12:43:32.872231 <6>[ 0.250112] CPU features: detected: 32-bit EL0 Support
10486 12:43:32.882160 <6>[ 0.255507] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10487 12:43:32.889652 <6>[ 0.264307] CPU features: detected: Common not Private translations
10488 12:43:32.892619 <6>[ 0.270822] CPU features: detected: CRC32 instructions
10489 12:43:32.899100 <6>[ 0.276173] CPU features: detected: RCpc load-acquire (LDAPR)
10490 12:43:32.905608 <6>[ 0.282133] CPU features: detected: LSE atomic instructions
10491 12:43:32.912371 <6>[ 0.287950] CPU features: detected: Privileged Access Never
10492 12:43:32.915131 <6>[ 0.293730] CPU features: detected: RAS Extension Support
10493 12:43:32.922389 <6>[ 0.299338] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10494 12:43:32.928518 <6>[ 0.306556] CPU: All CPU(s) started at EL2
10495 12:43:32.931771 <6>[ 0.310873] alternatives: applying system-wide alternatives
10496 12:43:32.943083 <6>[ 0.321548] devtmpfs: initialized
10497 12:43:32.959861 <6>[ 0.330753] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10498 12:43:32.965894 <6>[ 0.340717] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10499 12:43:32.972332 <6>[ 0.348899] pinctrl core: initialized pinctrl subsystem
10500 12:43:32.976004 <6>[ 0.355537] DMI not present or invalid.
10501 12:43:32.983048 <6>[ 0.359945] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10502 12:43:32.993692 <6>[ 0.366810] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10503 12:43:32.999011 <6>[ 0.374399] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10504 12:43:33.009346 <6>[ 0.382622] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10505 12:43:33.012370 <6>[ 0.390864] audit: initializing netlink subsys (disabled)
10506 12:43:33.022513 <5>[ 0.396557] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10507 12:43:33.029302 <6>[ 0.397256] thermal_sys: Registered thermal governor 'step_wise'
10508 12:43:33.035689 <6>[ 0.404524] thermal_sys: Registered thermal governor 'power_allocator'
10509 12:43:33.038974 <6>[ 0.410780] cpuidle: using governor menu
10510 12:43:33.042787 <6>[ 0.421742] NET: Registered PF_QIPCRTR protocol family
10511 12:43:33.052664 <6>[ 0.427226] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10512 12:43:33.055891 <6>[ 0.434330] ASID allocator initialised with 32768 entries
10513 12:43:33.062915 <6>[ 0.440892] Serial: AMBA PL011 UART driver
10514 12:43:33.071685 <4>[ 0.449655] Trying to register duplicate clock ID: 134
10515 12:43:33.126139 <6>[ 0.507317] KASLR enabled
10516 12:43:33.140697 <6>[ 0.515052] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10517 12:43:33.147478 <6>[ 0.522067] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10518 12:43:33.154071 <6>[ 0.528557] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10519 12:43:33.160708 <6>[ 0.535563] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10520 12:43:33.166943 <6>[ 0.542052] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10521 12:43:33.174268 <6>[ 0.549058] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10522 12:43:33.180260 <6>[ 0.555546] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10523 12:43:33.186844 <6>[ 0.562550] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10524 12:43:33.189957 <6>[ 0.570005] ACPI: Interpreter disabled.
10525 12:43:33.198695 <6>[ 0.576432] iommu: Default domain type: Translated
10526 12:43:33.205369 <6>[ 0.581543] iommu: DMA domain TLB invalidation policy: strict mode
10527 12:43:33.208310 <5>[ 0.588203] SCSI subsystem initialized
10528 12:43:33.214862 <6>[ 0.592372] usbcore: registered new interface driver usbfs
10529 12:43:33.221576 <6>[ 0.598104] usbcore: registered new interface driver hub
10530 12:43:33.225077 <6>[ 0.603656] usbcore: registered new device driver usb
10531 12:43:33.231798 <6>[ 0.609755] pps_core: LinuxPPS API ver. 1 registered
10532 12:43:33.241801 <6>[ 0.614947] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10533 12:43:33.245782 <6>[ 0.624297] PTP clock support registered
10534 12:43:33.248303 <6>[ 0.628539] EDAC MC: Ver: 3.0.0
10535 12:43:33.255587 <6>[ 0.633688] FPGA manager framework
10536 12:43:33.262486 <6>[ 0.637368] Advanced Linux Sound Architecture Driver Initialized.
10537 12:43:33.265686 <6>[ 0.644146] vgaarb: loaded
10538 12:43:33.272086 <6>[ 0.647315] clocksource: Switched to clocksource arch_sys_counter
10539 12:43:33.275646 <5>[ 0.653758] VFS: Disk quotas dquot_6.6.0
10540 12:43:33.282525 <6>[ 0.657944] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10541 12:43:33.285832 <6>[ 0.665134] pnp: PnP ACPI: disabled
10542 12:43:33.293837 <6>[ 0.671789] NET: Registered PF_INET protocol family
10543 12:43:33.304128 <6>[ 0.677386] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10544 12:43:33.314994 <6>[ 0.689698] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10545 12:43:33.325553 <6>[ 0.698513] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10546 12:43:33.331656 <6>[ 0.706485] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10547 12:43:33.338534 <6>[ 0.715184] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10548 12:43:33.349811 <6>[ 0.724939] TCP: Hash tables configured (established 65536 bind 65536)
10549 12:43:33.357429 <6>[ 0.731805] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10550 12:43:33.364001 <6>[ 0.739005] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10551 12:43:33.370031 <6>[ 0.746707] NET: Registered PF_UNIX/PF_LOCAL protocol family
10552 12:43:33.376621 <6>[ 0.752860] RPC: Registered named UNIX socket transport module.
10553 12:43:33.379943 <6>[ 0.759014] RPC: Registered udp transport module.
10554 12:43:33.387433 <6>[ 0.763947] RPC: Registered tcp transport module.
10555 12:43:33.393563 <6>[ 0.768878] RPC: Registered tcp NFSv4.1 backchannel transport module.
10556 12:43:33.396545 <6>[ 0.775542] PCI: CLS 0 bytes, default 64
10557 12:43:33.399887 <6>[ 0.779879] Unpacking initramfs...
10558 12:43:33.425206 <6>[ 0.799430] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10559 12:43:33.435364 <6>[ 0.808072] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10560 12:43:33.438471 <6>[ 0.816911] kvm [1]: IPA Size Limit: 40 bits
10561 12:43:33.444651 <6>[ 0.821435] kvm [1]: GICv3: no GICV resource entry
10562 12:43:33.447867 <6>[ 0.826456] kvm [1]: disabling GICv2 emulation
10563 12:43:33.454871 <6>[ 0.831145] kvm [1]: GIC system register CPU interface enabled
10564 12:43:33.458075 <6>[ 0.837305] kvm [1]: vgic interrupt IRQ18
10565 12:43:33.464660 <6>[ 0.841664] kvm [1]: VHE mode initialized successfully
10566 12:43:33.471442 <5>[ 0.848192] Initialise system trusted keyrings
10567 12:43:33.477931 <6>[ 0.853091] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10568 12:43:33.485527 <6>[ 0.863168] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10569 12:43:33.491922 <5>[ 0.869547] NFS: Registering the id_resolver key type
10570 12:43:33.494806 <5>[ 0.874845] Key type id_resolver registered
10571 12:43:33.502503 <5>[ 0.879257] Key type id_legacy registered
10572 12:43:33.508578 <6>[ 0.883535] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10573 12:43:33.515180 <6>[ 0.890457] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10574 12:43:33.521949 <6>[ 0.898171] 9p: Installing v9fs 9p2000 file system support
10575 12:43:33.557802 <5>[ 0.935358] Key type asymmetric registered
10576 12:43:33.560591 <5>[ 0.939688] Asymmetric key parser 'x509' registered
10577 12:43:33.570976 <6>[ 0.944830] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10578 12:43:33.574441 <6>[ 0.952449] io scheduler mq-deadline registered
10579 12:43:33.576997 <6>[ 0.957229] io scheduler kyber registered
10580 12:43:33.596723 <6>[ 0.974312] EINJ: ACPI disabled.
10581 12:43:33.628640 <4>[ 0.999746] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10582 12:43:33.638445 <4>[ 1.010369] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10583 12:43:33.653650 <6>[ 1.031180] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10584 12:43:33.662031 <6>[ 1.039155] printk: console [ttyS0] disabled
10585 12:43:33.689011 <6>[ 1.063784] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10586 12:43:33.695606 <6>[ 1.073270] printk: console [ttyS0] enabled
10587 12:43:33.699238 <6>[ 1.073270] printk: console [ttyS0] enabled
10588 12:43:33.705623 <6>[ 1.082175] printk: bootconsole [mtk8250] disabled
10589 12:43:33.709012 <6>[ 1.082175] printk: bootconsole [mtk8250] disabled
10590 12:43:33.715441 <6>[ 1.093563] SuperH (H)SCI(F) driver initialized
10591 12:43:33.718884 <6>[ 1.098842] msm_serial: driver initialized
10592 12:43:33.733046 <6>[ 1.107833] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10593 12:43:33.743060 <6>[ 1.116380] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10594 12:43:33.750104 <6>[ 1.124921] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10595 12:43:33.759810 <6>[ 1.133551] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10596 12:43:33.766198 <6>[ 1.142258] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10597 12:43:33.776455 <6>[ 1.150970] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10598 12:43:33.785775 <6>[ 1.159510] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10599 12:43:33.793079 <6>[ 1.168320] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10600 12:43:33.802937 <6>[ 1.176865] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10601 12:43:33.814864 <6>[ 1.192497] loop: module loaded
10602 12:43:33.821064 <6>[ 1.198492] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10603 12:43:33.843866 <4>[ 1.222031] mtk-pmic-keys: Failed to locate of_node [id: -1]
10604 12:43:33.850502 <6>[ 1.229115] megasas: 07.719.03.00-rc1
10605 12:43:33.860703 <6>[ 1.238958] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10606 12:43:33.872625 <6>[ 1.250683] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10607 12:43:33.889467 <6>[ 1.267221] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10608 12:43:33.945670 <6>[ 1.317032] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10609 12:43:34.149019 <6>[ 1.527089] Freeing initrd memory: 17380K
10610 12:43:34.160267 <6>[ 1.537575] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10611 12:43:34.170601 <6>[ 1.548607] tun: Universal TUN/TAP device driver, 1.6
10612 12:43:34.174203 <6>[ 1.554682] thunder_xcv, ver 1.0
10613 12:43:34.176970 <6>[ 1.558185] thunder_bgx, ver 1.0
10614 12:43:34.180893 <6>[ 1.561680] nicpf, ver 1.0
10615 12:43:34.191099 <6>[ 1.565713] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10616 12:43:34.194442 <6>[ 1.573189] hns3: Copyright (c) 2017 Huawei Corporation.
10617 12:43:34.197740 <6>[ 1.578775] hclge is initializing
10618 12:43:34.204167 <6>[ 1.582356] e1000: Intel(R) PRO/1000 Network Driver
10619 12:43:34.211126 <6>[ 1.587485] e1000: Copyright (c) 1999-2006 Intel Corporation.
10620 12:43:34.214250 <6>[ 1.593500] e1000e: Intel(R) PRO/1000 Network Driver
10621 12:43:34.220888 <6>[ 1.598716] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10622 12:43:34.227828 <6>[ 1.604904] igb: Intel(R) Gigabit Ethernet Network Driver
10623 12:43:34.234450 <6>[ 1.610553] igb: Copyright (c) 2007-2014 Intel Corporation.
10624 12:43:34.241699 <6>[ 1.616390] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10625 12:43:34.244321 <6>[ 1.622908] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10626 12:43:34.251021 <6>[ 1.629376] sky2: driver version 1.30
10627 12:43:34.258570 <6>[ 1.634354] VFIO - User Level meta-driver version: 0.3
10628 12:43:34.264784 <6>[ 1.642564] usbcore: registered new interface driver usb-storage
10629 12:43:34.270968 <6>[ 1.649016] usbcore: registered new device driver onboard-usb-hub
10630 12:43:34.279869 <6>[ 1.658185] mt6397-rtc mt6359-rtc: registered as rtc0
10631 12:43:34.289926 <6>[ 1.663653] mt6397-rtc mt6359-rtc: setting system clock to 2024-02-05T12:43:56 UTC (1707137036)
10632 12:43:34.293249 <6>[ 1.673212] i2c_dev: i2c /dev entries driver
10633 12:43:34.310345 <6>[ 1.684963] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10634 12:43:34.330039 <6>[ 1.707949] cpu cpu0: EM: created perf domain
10635 12:43:34.333633 <6>[ 1.712892] cpu cpu4: EM: created perf domain
10636 12:43:34.340185 <6>[ 1.718520] sdhci: Secure Digital Host Controller Interface driver
10637 12:43:34.347111 <6>[ 1.724953] sdhci: Copyright(c) Pierre Ossman
10638 12:43:34.354285 <6>[ 1.729911] Synopsys Designware Multimedia Card Interface Driver
10639 12:43:34.360179 <6>[ 1.736549] sdhci-pltfm: SDHCI platform and OF driver helper
10640 12:43:34.363595 <6>[ 1.736666] mmc0: CQHCI version 5.10
10641 12:43:34.370335 <6>[ 1.746498] ledtrig-cpu: registered to indicate activity on CPUs
10642 12:43:34.376930 <6>[ 1.753493] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10643 12:43:34.383755 <6>[ 1.760547] usbcore: registered new interface driver usbhid
10644 12:43:34.387393 <6>[ 1.766369] usbhid: USB HID core driver
10645 12:43:34.393677 <6>[ 1.770561] spi_master spi0: will run message pump with realtime priority
10646 12:43:34.437225 <6>[ 1.808477] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10647 12:43:34.456699 <6>[ 1.824445] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10648 12:43:34.460183 <6>[ 1.838055] mmc0: Command Queue Engine enabled
10649 12:43:34.467017 <6>[ 1.842826] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10650 12:43:34.473534 <6>[ 1.849766] cros-ec-spi spi0.0: Chrome EC device registered
10651 12:43:34.477118 <6>[ 1.850090] mmcblk0: mmc0:0001 DA4128 116 GiB
10652 12:43:34.487520 <6>[ 1.865091] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10653 12:43:34.495369 <6>[ 1.872683] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10654 12:43:34.501918 <6>[ 1.878651] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10655 12:43:34.507874 <6>[ 1.884681] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10656 12:43:34.517859 <6>[ 1.890399] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10657 12:43:34.524708 <6>[ 1.902087] NET: Registered PF_PACKET protocol family
10658 12:43:34.528007 <6>[ 1.907491] 9pnet: Installing 9P2000 support
10659 12:43:34.535160 <5>[ 1.912057] Key type dns_resolver registered
10660 12:43:34.538319 <6>[ 1.917033] registered taskstats version 1
10661 12:43:34.544307 <5>[ 1.921423] Loading compiled-in X.509 certificates
10662 12:43:34.573878 <4>[ 1.945148] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10663 12:43:34.583694 <4>[ 1.955967] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10664 12:43:34.590429 <3>[ 1.966515] debugfs: File 'uA_load' in directory '/' already present!
10665 12:43:34.597163 <3>[ 1.973220] debugfs: File 'min_uV' in directory '/' already present!
10666 12:43:34.603599 <3>[ 1.979831] debugfs: File 'max_uV' in directory '/' already present!
10667 12:43:34.610839 <3>[ 1.986443] debugfs: File 'constraint_flags' in directory '/' already present!
10668 12:43:34.621677 <3>[ 1.996296] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10669 12:43:34.631256 <6>[ 2.009604] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10670 12:43:34.638695 <6>[ 2.016553] xhci-mtk 11200000.usb: xHCI Host Controller
10671 12:43:34.644978 <6>[ 2.022076] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10672 12:43:34.654864 <6>[ 2.029906] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10673 12:43:34.662445 <6>[ 2.039325] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10674 12:43:34.669077 <6>[ 2.045387] xhci-mtk 11200000.usb: xHCI Host Controller
10675 12:43:34.675831 <6>[ 2.050865] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10676 12:43:34.682330 <6>[ 2.058511] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10677 12:43:34.685969 <6>[ 2.066151] hub 1-0:1.0: USB hub found
10678 12:43:34.692727 <6>[ 2.070162] hub 1-0:1.0: 1 port detected
10679 12:43:34.699036 <6>[ 2.074439] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10680 12:43:34.702534 <6>[ 2.082975] hub 2-0:1.0: USB hub found
10681 12:43:34.709759 <6>[ 2.086979] hub 2-0:1.0: 1 port detected
10682 12:43:34.716791 <6>[ 2.094829] mtk-msdc 11f70000.mmc: Got CD GPIO
10683 12:43:34.727558 <6>[ 2.102298] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10684 12:43:34.733960 <6>[ 2.110339] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10685 12:43:34.744385 <4>[ 2.118254] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10686 12:43:34.753875 <6>[ 2.127776] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10687 12:43:34.760886 <6>[ 2.135858] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10688 12:43:34.767943 <6>[ 2.143873] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10689 12:43:34.777620 <6>[ 2.151786] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10690 12:43:34.784707 <6>[ 2.159603] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10691 12:43:34.795132 <6>[ 2.167421] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10692 12:43:34.804491 <6>[ 2.177795] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10693 12:43:34.811381 <6>[ 2.186149] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10694 12:43:34.820951 <6>[ 2.194488] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10695 12:43:34.827775 <6>[ 2.202827] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10696 12:43:34.837566 <6>[ 2.211166] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10697 12:43:34.844635 <6>[ 2.219509] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10698 12:43:34.854325 <6>[ 2.227847] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10699 12:43:34.861212 <6>[ 2.236186] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10700 12:43:34.871397 <6>[ 2.244524] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10701 12:43:34.877948 <6>[ 2.252867] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10702 12:43:34.888954 <6>[ 2.261208] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10703 12:43:34.894787 <6>[ 2.269546] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10704 12:43:34.901485 <6>[ 2.277906] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10705 12:43:34.911341 <6>[ 2.286249] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10706 12:43:34.917676 <6>[ 2.294588] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10707 12:43:34.924853 <6>[ 2.303370] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10708 12:43:34.932142 <6>[ 2.310530] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10709 12:43:34.939077 <6>[ 2.317333] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10710 12:43:34.945599 <6>[ 2.324093] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10711 12:43:34.955903 <6>[ 2.331027] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10712 12:43:34.962369 <6>[ 2.337879] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10713 12:43:34.972424 <6>[ 2.347009] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10714 12:43:34.982876 <6>[ 2.356129] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10715 12:43:34.992244 <6>[ 2.365424] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10716 12:43:35.002452 <6>[ 2.374892] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10717 12:43:35.008702 <6>[ 2.384359] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10718 12:43:35.018582 <6>[ 2.393479] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10719 12:43:35.028447 <6>[ 2.402945] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10720 12:43:35.039100 <6>[ 2.412063] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10721 12:43:35.049027 <6>[ 2.421357] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10722 12:43:35.059144 <6>[ 2.431518] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10723 12:43:35.068765 <6>[ 2.443519] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10724 12:43:35.075366 <6>[ 2.453264] Trying to probe devices needed for running init ...
10725 12:43:35.096830 <6>[ 2.471597] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10726 12:43:35.125022 <6>[ 2.503140] hub 2-1:1.0: USB hub found
10727 12:43:35.128605 <6>[ 2.507630] hub 2-1:1.0: 3 ports detected
10728 12:43:35.137098 <6>[ 2.514947] hub 2-1:1.0: USB hub found
10729 12:43:35.139853 <6>[ 2.519272] hub 2-1:1.0: 3 ports detected
10730 12:43:35.248694 <6>[ 2.623587] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10731 12:43:35.403397 <6>[ 2.781495] hub 1-1:1.0: USB hub found
10732 12:43:35.406368 <6>[ 2.786034] hub 1-1:1.0: 4 ports detected
10733 12:43:35.416261 <6>[ 2.794151] hub 1-1:1.0: USB hub found
10734 12:43:35.419345 <6>[ 2.798669] hub 1-1:1.0: 4 ports detected
10735 12:43:35.488453 <6>[ 2.863743] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10736 12:43:35.740434 <6>[ 3.115619] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10737 12:43:35.873179 <6>[ 3.251452] hub 1-1.4:1.0: USB hub found
10738 12:43:35.876888 <6>[ 3.256123] hub 1-1.4:1.0: 2 ports detected
10739 12:43:35.886581 <6>[ 3.264685] hub 1-1.4:1.0: USB hub found
10740 12:43:35.889170 <6>[ 3.269286] hub 1-1.4:1.0: 2 ports detected
10741 12:43:36.188431 <6>[ 3.563621] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10742 12:43:36.380323 <6>[ 3.755621] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10743 12:43:47.353675 <6>[ 14.736504] ALSA device list:
10744 12:43:47.360162 <6>[ 14.739791] No soundcards found.
10745 12:43:47.367990 <6>[ 14.747636] Freeing unused kernel memory: 8448K
10746 12:43:47.371325 <6>[ 14.752584] Run /init as init process
10747 12:43:47.382302 Loading, please wait...
10748 12:43:47.403751 Starting version 247.3-7+deb11u2
10749 12:43:47.618464 <6>[ 14.995198] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10750 12:43:47.630375 <6>[ 15.006885] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10751 12:43:47.637347 <6>[ 15.014665] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10752 12:43:47.647621 <6>[ 15.023384] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10753 12:43:47.653937 <4>[ 15.025709] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10754 12:43:47.663674 <6>[ 15.027816] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10755 12:43:47.667418 <6>[ 15.040273] mc: Linux media interface: v0.10
10756 12:43:47.674293 <6>[ 15.040294] remoteproc remoteproc0: scp is available
10757 12:43:47.677132 <6>[ 15.040538] remoteproc remoteproc0: powering up scp
10758 12:43:47.686947 <6>[ 15.040544] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10759 12:43:47.689981 <6>[ 15.040580] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10760 12:43:47.699958 <4>[ 15.052758] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10761 12:43:47.707397 <3>[ 15.059500] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10762 12:43:47.714021 <6>[ 15.064030] usbcore: registered new device driver r8152-cfgselector
10763 12:43:47.721272 <3>[ 15.070491] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10764 12:43:47.730438 <3>[ 15.070494] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10765 12:43:47.737215 <3>[ 15.070590] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10766 12:43:47.747909 <4>[ 15.084027] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10767 12:43:47.751109 <4>[ 15.084027] Fallback method does not support PEC.
10768 12:43:47.760639 <3>[ 15.091806] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10769 12:43:47.767066 <3>[ 15.114673] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10770 12:43:47.777155 <3>[ 15.122386] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10771 12:43:47.784200 <3>[ 15.122391] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10772 12:43:47.790937 <3>[ 15.122394] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10773 12:43:47.801664 <3>[ 15.122435] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10774 12:43:47.811262 <6>[ 15.135970] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10775 12:43:47.821627 <6>[ 15.136488] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10776 12:43:47.827668 <3>[ 15.144135] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10777 12:43:47.834496 <3>[ 15.144139] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10778 12:43:47.844387 <3>[ 15.144141] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10779 12:43:47.850806 <3>[ 15.144173] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10780 12:43:47.857874 <6>[ 15.152727] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10781 12:43:47.864244 <6>[ 15.152733] pci_bus 0000:00: root bus resource [bus 00-ff]
10782 12:43:47.870993 <6>[ 15.152737] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10783 12:43:47.880950 <6>[ 15.152739] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10784 12:43:47.887694 <6>[ 15.152765] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10785 12:43:47.894498 <6>[ 15.152778] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10786 12:43:47.901148 <6>[ 15.152850] pci 0000:00:00.0: supports D1 D2
10787 12:43:47.907496 <6>[ 15.152852] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10788 12:43:47.913788 <6>[ 15.153928] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10789 12:43:47.923712 <3>[ 15.160990] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10790 12:43:47.930658 <3>[ 15.160993] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10791 12:43:47.940457 <3>[ 15.160996] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10792 12:43:47.947122 <3>[ 15.160999] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10793 12:43:47.957652 <3>[ 15.161016] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10794 12:43:47.963506 <6>[ 15.161362] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10795 12:43:47.973806 <6>[ 15.162526] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10796 12:43:47.980451 <6>[ 15.162536] remoteproc remoteproc0: remote processor scp is now up
10797 12:43:47.986800 <6>[ 15.162538] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10798 12:43:47.993389 <6>[ 15.169176] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10799 12:43:48.000224 <3>[ 15.173284] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10800 12:43:48.010526 <6>[ 15.174250] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10801 12:43:48.017385 <6>[ 15.186594] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10802 12:43:48.026453 <4>[ 15.186781] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10803 12:43:48.037035 <4>[ 15.186790] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10804 12:43:48.043405 <6>[ 15.195478] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10805 12:43:48.050020 <6>[ 15.195761] videodev: Linux video capture interface: v2.00
10806 12:43:48.056952 <6>[ 15.210764] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10807 12:43:48.063868 <6>[ 15.212581] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10808 12:43:48.066904 <6>[ 15.229259] Bluetooth: Core ver 2.22
10809 12:43:48.076516 <6>[ 15.236827] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10810 12:43:48.080400 <6>[ 15.239412] r8152 2-1.3:1.0 eth0: v1.12.13
10811 12:43:48.087389 <6>[ 15.239494] usbcore: registered new interface driver r8152
10812 12:43:48.090848 <6>[ 15.243773] NET: Registered PF_BLUETOOTH protocol family
10813 12:43:48.096404 <6>[ 15.249523] pci 0000:01:00.0: supports D1 D2
10814 12:43:48.103438 <6>[ 15.250907] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10815 12:43:48.116173 <6>[ 15.252141] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10816 12:43:48.123407 <6>[ 15.252285] usbcore: registered new interface driver uvcvideo
10817 12:43:48.129161 <6>[ 15.256543] Bluetooth: HCI device and connection manager initialized
10818 12:43:48.132643 <6>[ 15.256963] usbcore: registered new interface driver cdc_ether
10819 12:43:48.139587 <6>[ 15.266446] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10820 12:43:48.146505 <6>[ 15.266659] usbcore: registered new interface driver r8153_ecm
10821 12:43:48.153085 <6>[ 15.272713] Bluetooth: HCI socket layer initialized
10822 12:43:48.159889 <6>[ 15.273343] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10823 12:43:48.166207 <6>[ 15.280426] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10824 12:43:48.169130 <6>[ 15.284748] Bluetooth: L2CAP socket layer initialized
10825 12:43:48.175497 <6>[ 15.295496] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10826 12:43:48.182496 <6>[ 15.299856] Bluetooth: SCO socket layer initialized
10827 12:43:48.189299 <6>[ 15.307953] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10828 12:43:48.195954 <6>[ 15.377286] usbcore: registered new interface driver btusb
10829 12:43:48.205460 <4>[ 15.378160] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10830 12:43:48.213539 <3>[ 15.378166] Bluetooth: hci0: Failed to load firmware file (-2)
10831 12:43:48.218737 <3>[ 15.378168] Bluetooth: hci0: Failed to set up firmware (-2)
10832 12:43:48.228947 <4>[ 15.378170] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10833 12:43:48.235543 <6>[ 15.385572] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10834 12:43:48.245651 <6>[ 15.385582] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10835 12:43:48.251904 <6>[ 15.629240] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10836 12:43:48.262434 <6>[ 15.637243] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10837 12:43:48.265116 <6>[ 15.645245] pci 0000:00:00.0: PCI bridge to [bus 01]
10838 12:43:48.275324 <6>[ 15.650460] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10839 12:43:48.281288 <6>[ 15.658594] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10840 12:43:48.288184 <6>[ 15.665432] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10841 12:43:48.291666 <6>[ 15.672063] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10842 12:43:48.309241 <5>[ 15.685915] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10843 12:43:48.327808 <5>[ 15.703592] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10844 12:43:48.333961 <5>[ 15.710982] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10845 12:43:48.344355 <4>[ 15.719492] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10846 12:43:48.347230 <6>[ 15.728375] cfg80211: failed to load regulatory.db
10847 12:43:48.397309 <6>[ 15.774123] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10848 12:43:48.404064 <6>[ 15.781620] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10849 12:43:48.428290 <6>[ 15.808257] mt7921e 0000:01:00.0: ASIC revision: 79610010
10850 12:43:48.530158 <6>[ 15.906590] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10851 12:43:48.533082 <6>[ 15.906590]
10852 12:43:48.545550 Begin: Loading essential drivers ... done.
10853 12:43:48.549789 Begin: Running /scripts/init-premount ... done.
10854 12:43:48.555134 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10855 12:43:48.565466 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10856 12:43:48.569034 Device /sys/class/net/enx002432307852 found
10857 12:43:48.569585 done.
10858 12:43:48.619514 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10859 12:43:48.799063 <6>[ 16.175579] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10860 12:43:49.472937 <6>[ 16.853221] r8152 2-1.3:1.0 enx002432307852: carrier on
10861 12:43:49.647542 <6>[ 17.027501] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10862 12:43:49.783444 IP-Config: no response after 2 secs - giving up
10863 12:43:49.823175 IP-Config: wlp1s0 hardware address d8:f3:bc:78:28:3d mtu 1500 DHCP
10864 12:43:50.550836 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10865 12:43:50.556939 IP-Config: enx002432307852 complete (dhcp from 192.168.201.1):
10866 12:43:50.564494 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10867 12:43:50.570635 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10868 12:43:50.577112 host : mt8192-asurada-spherion-r0-cbg-3
10869 12:43:50.583600 domain : lava-rack
10870 12:43:50.587131 rootserver: 192.168.201.1 rootpath:
10871 12:43:50.587586 filename :
10872 12:43:50.727187 done.
10873 12:43:50.735710 Begin: Running /scripts/nfs-bottom ... done.
10874 12:43:50.759436 Begin: Running /scripts/init-bottom ... done.
10875 12:43:52.037473 <6>[ 19.418199] NET: Registered PF_INET6 protocol family
10876 12:43:52.044824 <6>[ 19.425585] Segment Routing with IPv6
10877 12:43:52.048298 <6>[ 19.429558] In-situ OAM (IOAM) with IPv6
10878 12:43:52.214284 <30>[ 19.574350] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10879 12:43:52.217325 <30>[ 19.598727] systemd[1]: Detected architecture arm64.
10880 12:43:52.241581
10881 12:43:52.244945 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10882 12:43:52.245355
10883 12:43:52.262379 <30>[ 19.642638] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10884 12:43:53.216659 <30>[ 20.593824] systemd[1]: Queued start job for default target Graphical Interface.
10885 12:43:53.249686 <30>[ 20.630123] systemd[1]: Created slice system-getty.slice.
10886 12:43:53.256226 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10887 12:43:53.272824 <30>[ 20.653092] systemd[1]: Created slice system-modprobe.slice.
10888 12:43:53.279122 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10889 12:43:53.297998 <30>[ 20.677658] systemd[1]: Created slice system-serial\x2dgetty.slice.
10890 12:43:53.307719 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10891 12:43:53.320994 <30>[ 20.700704] systemd[1]: Created slice User and Session Slice.
10892 12:43:53.326598 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10893 12:43:53.347530 <30>[ 20.724460] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10894 12:43:53.357124 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10895 12:43:53.375360 <30>[ 20.752376] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10896 12:43:53.381766 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10897 12:43:53.405861 <30>[ 20.779772] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10898 12:43:53.413117 <30>[ 20.791928] systemd[1]: Reached target Local Encrypted Volumes.
10899 12:43:53.419847 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10900 12:43:53.436236 <30>[ 20.816149] systemd[1]: Reached target Paths.
10901 12:43:53.439650 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10902 12:43:53.455239 <30>[ 20.835588] systemd[1]: Reached target Remote File Systems.
10903 12:43:53.461548 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10904 12:43:53.479814 <30>[ 20.859968] systemd[1]: Reached target Slices.
10905 12:43:53.486312 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10906 12:43:53.499625 <30>[ 20.879600] systemd[1]: Reached target Swap.
10907 12:43:53.502593 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10908 12:43:53.522975 <30>[ 20.900088] systemd[1]: Listening on initctl Compatibility Named Pipe.
10909 12:43:53.530243 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10910 12:43:53.536630 <30>[ 20.916345] systemd[1]: Listening on Journal Audit Socket.
10911 12:43:53.542558 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10912 12:43:53.560914 <30>[ 20.941176] systemd[1]: Listening on Journal Socket (/dev/log).
10913 12:43:53.567569 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10914 12:43:53.584003 <30>[ 20.964154] systemd[1]: Listening on Journal Socket.
10915 12:43:53.590479 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10916 12:43:53.608280 <30>[ 20.985361] systemd[1]: Listening on Network Service Netlink Socket.
10917 12:43:53.614926 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10918 12:43:53.631673 <30>[ 21.010894] systemd[1]: Listening on udev Control Socket.
10919 12:43:53.636896 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10920 12:43:53.651202 <30>[ 21.032036] systemd[1]: Listening on udev Kernel Socket.
10921 12:43:53.657762 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10922 12:43:53.711088 <30>[ 21.091771] systemd[1]: Mounting Huge Pages File System...
10923 12:43:53.717947 Mounting [0;1;39mHuge Pages File System[0m...
10924 12:43:53.735259 <30>[ 21.115751] systemd[1]: Mounting POSIX Message Queue File System...
10925 12:43:53.741912 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10926 12:43:53.787117 <30>[ 21.167821] systemd[1]: Mounting Kernel Debug File System...
10927 12:43:53.793773 Mounting [0;1;39mKernel Debug File System[0m...
10928 12:43:53.810927 <30>[ 21.188221] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10929 12:43:53.828036 <30>[ 21.205216] systemd[1]: Starting Create list of static device nodes for the current kernel...
10930 12:43:53.837770 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10931 12:43:53.855956 <30>[ 21.236046] systemd[1]: Starting Load Kernel Module configfs...
10932 12:43:53.862214 Starting [0;1;39mLoad Kernel Module configfs[0m...
10933 12:43:53.879048 <30>[ 21.259139] systemd[1]: Starting Load Kernel Module drm...
10934 12:43:53.884921 Starting [0;1;39mLoad Kernel Module drm[0m...
10935 12:43:53.902955 <30>[ 21.283250] systemd[1]: Starting Load Kernel Module fuse...
10936 12:43:53.909180 Starting [0;1;39mLoad Kernel Module fuse[0m...
10937 12:43:53.932569 <30>[ 21.309161] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10938 12:43:53.947893 <30>[ 21.328285] systemd[1]: Starting Journal Service...
10939 12:43:53.954314 Starting [0;1;39mJournal Service[0m...
10940 12:43:53.964256 <6>[ 21.345245] fuse: init (API version 7.37)
10941 12:43:54.007869 <30>[ 21.388171] systemd[1]: Starting Load Kernel Modules...
10942 12:43:54.014307 Starting [0;1;39mLoad Kernel Modules[0m...
10943 12:43:54.035779 <30>[ 21.412733] systemd[1]: Starting Remount Root and Kernel File Systems...
10944 12:43:54.042579 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10945 12:43:54.060237 <30>[ 21.440959] systemd[1]: Starting Coldplug All udev Devices...
10946 12:43:54.066786 Starting [0;1;39mColdplug All udev Devices[0m...
10947 12:43:54.095963 <3>[ 21.473475] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 12:43:54.103001 <30>[ 21.474243] systemd[1]: Mounted Huge Pages File System.
10949 12:43:54.109126 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10950 12:43:54.124271 <30>[ 21.504045] systemd[1]: Mounted POSIX Message Queue File System.
10951 12:43:54.137301 [[0;32m OK [0m] Mounted [0;<3>[ 21.512350] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 12:43:54.140595 1;39mPOSIX Message Queue File System[0m.
10953 12:43:54.155580 <30>[ 21.536291] systemd[1]: Mounted Kernel Debug File System.
10954 12:43:54.162467 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10955 12:43:54.178730 <3>[ 21.555622] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 12:43:54.188782 <30>[ 21.565548] systemd[1]: Finished Create list of static device nodes for the current kernel.
10957 12:43:54.195733 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10958 12:43:54.207606 <3>[ 21.584666] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 12:43:54.214454 <30>[ 21.594547] systemd[1]: modprobe@configfs.service: Succeeded.
10960 12:43:54.221279 <30>[ 21.601422] systemd[1]: Finished Load Kernel Module configfs.
10961 12:43:54.228539 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10962 12:43:54.238813 <3>[ 21.614525] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10963 12:43:54.244937 <30>[ 21.624269] systemd[1]: modprobe@drm.service: Succeeded.
10964 12:43:54.251435 <30>[ 21.630458] systemd[1]: Finished Load Kernel Module drm.
10965 12:43:54.255000 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10966 12:43:54.270266 <3>[ 21.647460] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10967 12:43:54.277239 <30>[ 21.657712] systemd[1]: modprobe@fuse.service: Succeeded.
10968 12:43:54.284928 <30>[ 21.665031] systemd[1]: Finished Load Kernel Module fuse.
10969 12:43:54.291238 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10970 12:43:54.301546 <3>[ 21.678842] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10971 12:43:54.309285 <30>[ 21.689372] systemd[1]: Finished Load Kernel Modules.
10972 12:43:54.315352 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10973 12:43:54.332219 <3>[ 21.709344] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10974 12:43:54.338840 <30>[ 21.709372] systemd[1]: Finished Remount Root and Kernel File Systems.
10975 12:43:54.345788 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10976 12:43:54.361822 <3>[ 21.739241] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10977 12:43:54.389551 <30>[ 21.770036] systemd[1]: Mounting FUSE Control File System...
10978 12:43:54.399336 <3>[ 21.770936] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10979 12:43:54.405628 Mounting [0;1;39mFUSE Control File System[0m...
10980 12:43:54.424222 <30>[ 21.804211] systemd[1]: Mounting Kernel Configuration File System...
10981 12:43:54.431367 Mounting [0;1;39mKernel Configuration File System[0m...
10982 12:43:54.457561 <30>[ 21.834032] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10983 12:43:54.467139 <30>[ 21.843153] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10984 12:43:54.475741 <30>[ 21.855995] systemd[1]: Starting Load/Save Random Seed...
10985 12:43:54.481892 Starting [0;1;39mLoad/Save Random Seed[0m...
10986 12:43:54.499104 <30>[ 21.879564] systemd[1]: Starting Apply Kernel Variables...
10987 12:43:54.505723 Starting [0;1;39mApply Kernel Variables[0m...
10988 12:43:54.524302 <30>[ 21.905159] systemd[1]: Starting Create System Users...
10989 12:43:54.545402 Starting [0;1;39mCreat<4>[ 21.913707] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10990 12:43:54.551655 e System Users[<3>[ 21.929669] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10991 12:43:54.554632 0m...
10992 12:43:54.565302 <30>[ 21.946043] systemd[1]: Started Journal Service.
10993 12:43:54.569022 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10994 12:43:54.598432 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10995 12:43:54.614528 See 'systemctl status systemd-udev-trigger.service' for details.
10996 12:43:54.631137 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10997 12:43:54.646469 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10998 12:43:54.663972 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10999 12:43:54.685375 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11000 12:43:54.705387 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11001 12:43:54.747624 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11002 12:43:54.765392 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11003 12:43:54.812109 <46>[ 22.189193] systemd-journald[298]: Received client request to flush runtime journal.
11004 12:43:55.136540 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11005 12:43:55.151902 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11006 12:43:55.167347 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11007 12:43:55.211136 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11008 12:43:56.220972 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11009 12:43:56.271592 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11010 12:43:56.350078 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11011 12:43:56.424713 Starting [0;1;39mNetwork Service[0m...
11012 12:43:56.733835 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11013 12:43:56.752598 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11014 12:43:56.798581 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11015 12:43:57.145804 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11016 12:43:57.162152 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11017 12:43:57.179594 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11018 12:43:57.220358 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11019 12:43:57.234983 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
11020 12:43:57.255484 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11021 12:43:57.279507 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11022 12:43:57.339970 Starting [0;1;39mNetwork Name Resolution[0m...
11023 12:43:57.372716 Starting [0;1;39mNetwork Time Synchronization[0m...
11024 12:43:57.390699 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11025 12:43:57.439035 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11026 12:43:57.587101 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11027 12:43:57.603465 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11028 12:43:57.622701 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11029 12:43:57.635004 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11030 12:43:57.651178 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11031 12:43:57.697220 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11032 12:43:57.771858 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11033 12:43:57.829772 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11034 12:43:57.862518 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11035 12:43:57.879572 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11036 12:43:57.906130 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11037 12:43:57.919196 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11038 12:43:57.934837 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11039 12:43:57.999482 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11040 12:43:58.671174 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11041 12:43:59.059634 Starting [0;1;39mUser Login Management[0m...
11042 12:43:59.145659 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11043 12:43:59.164055 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11044 12:43:59.185895 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11045 12:43:59.232238 Starting [0;1;39mPermit User Sessions[0m...
11046 12:43:59.395429 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11047 12:43:59.435592 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11048 12:43:59.460263 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11049 12:43:59.479151 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11050 12:43:59.501913 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11051 12:43:59.517458 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11052 12:43:59.537411 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11053 12:43:59.557630 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11054 12:43:59.607544 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11055 12:43:59.679259 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11056 12:43:59.750218
11057 12:43:59.750750
11058 12:43:59.752517 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11059 12:43:59.752958
11060 12:43:59.755908 debian-bullseye-arm64 login: root (automatic login)
11061 12:43:59.756458
11062 12:43:59.756927
11063 12:44:00.177978 Linux debian-bullseye-arm64 6.1.75-cip14 #1 SMP PREEMPT Mon Feb 5 12:20:06 UTC 2024 aarch64
11064 12:44:00.178514
11065 12:44:00.184861 The programs included with the Debian GNU/Linux system are free software;
11066 12:44:00.191526 the exact distribution terms for each program are described in the
11067 12:44:00.195515 individual files in /usr/share/doc/*/copyright.
11068 12:44:00.196008
11069 12:44:00.201131 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11070 12:44:00.204292 permitted by applicable law.
11071 12:44:01.382111 Matched prompt #10: / #
11073 12:44:01.383469 Setting prompt string to ['/ #']
11074 12:44:01.384048 end: 2.2.5.1 login-action (duration 00:00:30) [common]
11076 12:44:01.385574 end: 2.2.5 auto-login-action (duration 00:00:30) [common]
11077 12:44:01.386227 start: 2.2.6 expect-shell-connection (timeout 00:03:12) [common]
11078 12:44:01.386944 Setting prompt string to ['/ #']
11079 12:44:01.387461 Forcing a shell prompt, looking for ['/ #']
11081 12:44:01.438552 / #
11082 12:44:01.439244 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11083 12:44:01.439661 Waiting using forced prompt support (timeout 00:02:30)
11084 12:44:01.445405
11085 12:44:01.446334 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11086 12:44:01.446898 start: 2.2.7 export-device-env (timeout 00:03:12) [common]
11088 12:44:01.548168 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12703551/extract-nfsrootfs-tshsvmla'
11089 12:44:01.555360 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12703551/extract-nfsrootfs-tshsvmla'
11091 12:44:01.657180 / # export NFS_SERVER_IP='192.168.201.1'
11092 12:44:01.663287 export NFS_SERVER_IP='192.168.201.1'
11093 12:44:01.663748 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11094 12:44:01.663943 end: 2.2 depthcharge-retry (duration 00:01:48) [common]
11095 12:44:01.664116 end: 2 depthcharge-action (duration 00:01:48) [common]
11096 12:44:01.664277 start: 3 lava-test-retry (timeout 00:07:28) [common]
11097 12:44:01.664430 start: 3.1 lava-test-shell (timeout 00:07:28) [common]
11098 12:44:01.664565 Using namespace: common
11100 12:44:01.765384 / # #
11101 12:44:01.766045 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11102 12:44:01.772528 #
11103 12:44:01.773392 Using /lava-12703551
11105 12:44:01.874620 / # export SHELL=/bin/bash
11106 12:44:01.881324 export SHELL=/bin/bash
11108 12:44:01.983244 / # . /lava-12703551/environment
11109 12:44:01.989437 . /lava-12703551/environment
11111 12:44:02.099159 / # /lava-12703551/bin/lava-test-runner /lava-12703551/0
11112 12:44:02.099781 Test shell timeout: 10s (minimum of the action and connection timeout)
11113 12:44:02.106293 /lava-12703551/bin/lava-test-runner /lava-12703551/0
11114 12:44:02.484852 + export TESTRUN_ID=0_timesync-off
11115 12:44:02.488542 + TESTRUN_ID=0_timesync-off
11116 12:44:02.491234 + cd /lava-12703551/0/tests/0_timesync-off
11117 12:44:02.494725 ++ cat uuid
11118 12:44:02.502988 + UUID=12703551_1.6.2.3.1
11119 12:44:02.503574 + set +x
11120 12:44:02.509572 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12703551_1.6.2.3.1>
11121 12:44:02.510277 Received signal: <STARTRUN> 0_timesync-off 12703551_1.6.2.3.1
11122 12:44:02.510715 Starting test lava.0_timesync-off (12703551_1.6.2.3.1)
11123 12:44:02.511133 Skipping test definition patterns.
11124 12:44:02.513250 + systemctl stop systemd-timesyncd
11125 12:44:02.581943 + set +x
11126 12:44:02.585065 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12703551_1.6.2.3.1>
11127 12:44:02.585751 Received signal: <ENDRUN> 0_timesync-off 12703551_1.6.2.3.1
11128 12:44:02.586167 Ending use of test pattern.
11129 12:44:02.586533 Ending test lava.0_timesync-off (12703551_1.6.2.3.1), duration 0.08
11131 12:44:02.698278 + export TESTRUN_ID=1_kselftest-dt
11132 12:44:02.701006 + TESTRUN_ID=1_kselftest-dt
11133 12:44:02.703905 + cd /lava-12703551/0/tests/1_kselftest-dt
11134 12:44:02.707030 ++ cat uuid
11135 12:44:02.716047 + UUID=12703551_1.6.2.3.5
11136 12:44:02.716470 + set +x
11137 12:44:02.723299 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 12703551_1.6.2.3.5>
11138 12:44:02.723982 Received signal: <STARTRUN> 1_kselftest-dt 12703551_1.6.2.3.5
11139 12:44:02.724337 Starting test lava.1_kselftest-dt (12703551_1.6.2.3.5)
11140 12:44:02.724744 Skipping test definition patterns.
11141 12:44:02.726949 + cd ./automated/linux/kselftest/
11142 12:44:02.753098 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11143 12:44:02.815896 INFO: install_deps skipped
11144 12:44:02.962589 --2024-02-05 12:44:02-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.75-cip14-6-ga817aa655908/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11145 12:44:02.991124 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11146 12:44:03.124096 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11147 12:44:03.256735 HTTP request sent, awaiting response... 200 OK
11148 12:44:03.259699 Length: 2966020 (2.8M) [application/octet-stream]
11149 12:44:03.262893 Saving to: 'kselftest.tar.xz'
11150 12:44:03.263468
11151 12:44:03.263829
11152 12:44:03.520818 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11153 12:44:03.788642 kselftest.tar.xz 1%[ ] 47.81K 182KB/s
11154 12:44:04.133890 kselftest.tar.xz 7%[> ] 217.50K 410KB/s
11155 12:44:04.450516 kselftest.tar.xz 28%[====> ] 821.30K 938KB/s
11156 12:44:04.793948 kselftest.tar.xz 49%[========> ] 1.40M 1.18MB/s
11157 12:44:04.996395 kselftest.tar.xz 98%[==================> ] 2.78M 1.81MB/s
11158 12:44:05.003285 kselftest.tar.xz 98%[==================> ] 2.80M 1.61MB/s
11159 12:44:05.010500 kselftest.tar.xz 100%[===================>] 2.83M 1.63MB/s in 1.7s
11160 12:44:05.010963
11161 12:44:05.262351 2024-02-05 12:44:05 (1.63 MB/s) - 'kselftest.tar.xz' saved [2966020/2966020]
11162 12:44:05.262538
11163 12:44:12.665982 skiplist:
11164 12:44:12.668935 ========================================
11165 12:44:12.672158 ========================================
11166 12:44:12.752920 ============== Tests to run ===============
11167 12:44:12.759950 ===========End Tests to run ===============
11168 12:44:12.764672 shardfile-dt fail
11169 12:44:12.794310 ./kselftest.sh: 131: cannot open /lava-12703551/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
11170 12:44:12.797132 + ../../utils/send-to-lava.sh ./output/result.txt
11171 12:44:12.903645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
11172 12:44:12.904185 + set +x
11173 12:44:12.904813 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
11175 12:44:12.910239 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 12703551_1.6.2.3.5>
11176 12:44:12.910793 <LAVA_TEST_RUNNER EXIT>
11177 12:44:12.911388 Received signal: <ENDRUN> 1_kselftest-dt 12703551_1.6.2.3.5
11178 12:44:12.911751 Ending use of test pattern.
11179 12:44:12.912054 Ending test lava.1_kselftest-dt (12703551_1.6.2.3.5), duration 10.19
11181 12:44:12.913156 ok: lava_test_shell seems to have completed
11182 12:44:12.913600 shardfile-dt: fail
11183 12:44:12.914086 end: 3.1 lava-test-shell (duration 00:00:11) [common]
11184 12:44:12.914647 end: 3 lava-test-retry (duration 00:00:11) [common]
11185 12:44:12.915194 start: 4 finalize (timeout 00:07:17) [common]
11186 12:44:12.915725 start: 4.1 power-off (timeout 00:00:30) [common]
11187 12:44:12.916588 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11188 12:44:13.036813 >> Command sent successfully.
11189 12:44:13.040739 Returned 0 in 0 seconds
11190 12:44:13.141765 end: 4.1 power-off (duration 00:00:00) [common]
11192 12:44:13.143430 start: 4.2 read-feedback (timeout 00:07:17) [common]
11193 12:44:13.144807 Listened to connection for namespace 'common' for up to 1s
11194 12:44:13.145681 Listened to connection for namespace 'common' for up to 1s
11195 12:44:14.145348 Finalising connection for namespace 'common'
11196 12:44:14.146092 Disconnecting from shell: Finalise
11197 12:44:14.146536 / #
11198 12:44:14.247584 end: 4.2 read-feedback (duration 00:00:01) [common]
11199 12:44:14.248362 end: 4 finalize (duration 00:00:01) [common]
11200 12:44:14.248984 Cleaning after the job
11201 12:44:14.249509 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703551/tftp-deploy-oba5nm6w/ramdisk
11202 12:44:14.263816 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703551/tftp-deploy-oba5nm6w/kernel
11203 12:44:14.297729 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703551/tftp-deploy-oba5nm6w/dtb
11204 12:44:14.298002 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703551/tftp-deploy-oba5nm6w/nfsrootfs
11205 12:44:14.390694 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12703551/tftp-deploy-oba5nm6w/modules
11206 12:44:14.397803 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12703551
11207 12:44:15.031900 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12703551
11208 12:44:15.032085 Job finished correctly